From 509efaf3d1819cf2bed1be1396aa24e56c9db303 Mon Sep 17 00:00:00 2001 From: Sathya Prakash M R Date: Sat, 5 Jul 2014 17:44:57 -0600 Subject: ARM: AM43xx: hwmod: add DSS hwmod data Add DSS hwmod data for AM43xx. Signed-off-by: Sathya Prakash M R [tomi.valkeinen@ti.com: added missing dispc flags] Signed-off-by: Tomi Valkeinen Acked-by: Rajendra Nayak Acked-by: Tony Lindgren Tested-by: Felipe Balbi # on linux-next 5f295cdf5c5d [paul@pwsan.com: fixed build break on AM43xx-only config] Signed-off-by: Paul Walmsley diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index 8421f38..75c73f2 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -200,6 +200,7 @@ obj-$(CONFIG_SOC_OMAP2420) += opp2420_data.o obj-$(CONFIG_SOC_OMAP2430) += opp2430_data.o # hwmod data +obj-y += omap_hwmod_common_ipblock_data.o obj-$(CONFIG_SOC_OMAP2420) += omap_hwmod_2xxx_ipblock_data.o obj-$(CONFIG_SOC_OMAP2420) += omap_hwmod_2xxx_3xxx_ipblock_data.o obj-$(CONFIG_SOC_OMAP2420) += omap_hwmod_2xxx_interconnect_data.o diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c index 5da7a42..c6c6384 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c @@ -37,46 +37,6 @@ struct omap_hwmod_class omap2_uart_class = { }; /* - * 'dss' class - * display sub-system - */ - -static struct omap_hwmod_class_sysconfig omap2_dss_sysc = { - .rev_offs = 0x0000, - .sysc_offs = 0x0010, - .syss_offs = 0x0014, - .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | - SYSS_HAS_RESET_STATUS), - .sysc_fields = &omap_hwmod_sysc_type1, -}; - -struct omap_hwmod_class omap2_dss_hwmod_class = { - .name = "dss", - .sysc = &omap2_dss_sysc, - .reset = omap_dss_reset, -}; - -/* - * 'rfbi' class - * remote frame buffer interface - */ - -static struct omap_hwmod_class_sysconfig omap2_rfbi_sysc = { - .rev_offs = 0x0000, - .sysc_offs = 0x0010, - .syss_offs = 0x0014, - .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | - SYSC_HAS_AUTOIDLE), - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), - .sysc_fields = &omap_hwmod_sysc_type1, -}; - -struct omap_hwmod_class omap2_rfbi_hwmod_class = { - .name = "rfbi", - .sysc = &omap2_rfbi_sysc, -}; - -/* * 'venc' class * video encoder */ diff --git a/arch/arm/mach-omap2/omap_hwmod_43xx_data.c b/arch/arm/mach-omap2/omap_hwmod_43xx_data.c index 5c2cc80..fea01aa 100644 --- a/arch/arm/mach-omap2/omap_hwmod_43xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_43xx_data.c @@ -19,6 +19,8 @@ #include "omap_hwmod.h" #include "omap_hwmod_33xx_43xx_common_data.h" #include "prcm43xx.h" +#include "omap_hwmod_common_data.h" + /* IP blocks */ static struct omap_hwmod am43xx_l4_hs_hwmod = { @@ -415,6 +417,72 @@ static struct omap_hwmod am43xx_qspi_hwmod = { }, }; +/* dss */ + +static struct omap_hwmod am43xx_dss_core_hwmod = { + .name = "dss_core", + .class = &omap2_dss_hwmod_class, + .clkdm_name = "dss_clkdm", + .main_clk = "disp_clk", + .prcm = { + .omap4 = { + .clkctrl_offs = AM43XX_CM_PER_DSS_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* dispc */ + +struct omap_dss_dispc_dev_attr am43xx_dss_dispc_dev_attr = { + .manager_count = 1, + .has_framedonetv_irq = 0 +}; + +static struct omap_hwmod_class_sysconfig am43xx_dispc_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .syss_offs = 0x0014, + .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET | + SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | + SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_MIDLEMODE), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | + MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class am43xx_dispc_hwmod_class = { + .name = "dispc", + .sysc = &am43xx_dispc_sysc, +}; + +static struct omap_hwmod am43xx_dss_dispc_hwmod = { + .name = "dss_dispc", + .class = &am43xx_dispc_hwmod_class, + .clkdm_name = "dss_clkdm", + .main_clk = "disp_clk", + .prcm = { + .omap4 = { + .clkctrl_offs = AM43XX_CM_PER_DSS_CLKCTRL_OFFSET, + }, + }, + .dev_attr = &am43xx_dss_dispc_dev_attr, +}; + +/* rfbi */ + +static struct omap_hwmod am43xx_dss_rfbi_hwmod = { + .name = "dss_rfbi", + .class = &omap2_rfbi_hwmod_class, + .clkdm_name = "dss_clkdm", + .main_clk = "disp_clk", + .prcm = { + .omap4 = { + .clkctrl_offs = AM43XX_CM_PER_DSS_CLKCTRL_OFFSET, + }, + }, +}; + /* Interfaces */ static struct omap_hwmod_ocp_if am43xx_l3_main__l4_hs = { .master = &am33xx_l3_main_hwmod, @@ -654,6 +722,34 @@ static struct omap_hwmod_ocp_if am43xx_l3_s__qspi = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; +static struct omap_hwmod_ocp_if am43xx_dss__l3_main = { + .master = &am43xx_dss_core_hwmod, + .slave = &am33xx_l3_main_hwmod, + .clk = "l3_gclk", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_ocp_if am43xx_l4_ls__dss = { + .master = &am33xx_l4_ls_hwmod, + .slave = &am43xx_dss_core_hwmod, + .clk = "l4ls_gclk", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_ocp_if am43xx_l4_ls__dss_dispc = { + .master = &am33xx_l4_ls_hwmod, + .slave = &am43xx_dss_dispc_hwmod, + .clk = "l4ls_gclk", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_ocp_if am43xx_l4_ls__dss_rfbi = { + .master = &am33xx_l4_ls_hwmod, + .slave = &am43xx_dss_rfbi_hwmod, + .clk = "l4ls_gclk", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + static struct omap_hwmod_ocp_if *am43xx_hwmod_ocp_ifs[] __initdata = { &am33xx_l4_wkup__synctimer, &am43xx_l4_ls__timer8, @@ -748,6 +844,10 @@ static struct omap_hwmod_ocp_if *am43xx_hwmod_ocp_ifs[] __initdata = { &am43xx_l4_ls__ocp2scp1, &am43xx_l3_s__usbotgss0, &am43xx_l3_s__usbotgss1, + &am43xx_dss__l3_main, + &am43xx_l4_ls__dss, + &am43xx_l4_ls__dss_dispc, + &am43xx_l4_ls__dss_rfbi, NULL, }; diff --git a/arch/arm/mach-omap2/omap_hwmod_common_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_common_ipblock_data.c new file mode 100644 index 0000000..f21664d --- /dev/null +++ b/arch/arm/mach-omap2/omap_hwmod_common_ipblock_data.c @@ -0,0 +1,55 @@ +/* + * omap_hwmod_common_ipblock_data.c - common IP block data for OMAP2+ + * + * Copyright (C) 2011 Nokia Corporation + * Copyright (C) 2012 Texas Instruments, Inc. + * Paul Walmsley + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "omap_hwmod.h" +#include "omap_hwmod_common_data.h" + +/* + * 'dss' class + * display sub-system + */ + +static struct omap_hwmod_class_sysconfig omap2_dss_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .syss_offs = 0x0014, + .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | + SYSS_HAS_RESET_STATUS), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +struct omap_hwmod_class omap2_dss_hwmod_class = { + .name = "dss", + .sysc = &omap2_dss_sysc, + .reset = omap_dss_reset, +}; + +/* + * 'rfbi' class + * remote frame buffer interface + */ + +static struct omap_hwmod_class_sysconfig omap2_rfbi_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .syss_offs = 0x0014, + .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | + SYSC_HAS_AUTOIDLE), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +struct omap_hwmod_class omap2_rfbi_hwmod_class = { + .name = "rfbi", + .sysc = &omap2_rfbi_sysc, +}; + diff --git a/arch/arm/mach-omap2/prcm43xx.h b/arch/arm/mach-omap2/prcm43xx.h index 7785be9..ad7b3e9 100644 --- a/arch/arm/mach-omap2/prcm43xx.h +++ b/arch/arm/mach-omap2/prcm43xx.h @@ -142,5 +142,6 @@ #define AM43XX_CM_PER_USBPHYOCP2SCP0_CLKCTRL_OFFSET 0x05B8 #define AM43XX_CM_PER_USB_OTG_SS1_CLKCTRL_OFFSET 0x0268 #define AM43XX_CM_PER_USBPHYOCP2SCP1_CLKCTRL_OFFSET 0x05C0 +#define AM43XX_CM_PER_DSS_CLKCTRL_OFFSET 0x0a20 #endif -- cgit v0.10.2 From 41ffada18f77b3309603dfff6a719b5b8425de3b Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Fri, 11 Jul 2014 16:44:34 -0500 Subject: ARM: dts: OMAP2+: Add mailbox fifo and user information The number of mailbox fifos and users (IP interrupts) are added to the Mailbox DT nodes on OMAP2420, OMAP2430, OMAP3, and OMAP5 family of SoCs through the DT properties "ti,mbox-num-fifos" and "ti,mbox-num-users" properties. This data represents the same data that used to be represented in hwmod attribute data through the .num_fifos and .num_users fields previously. Signed-off-by: Suman Anna Acked-by: Pavel Machek Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/omap2420.dtsi b/arch/arm/boot/dts/omap2420.dtsi index e83b046..6d21994 100644 --- a/arch/arm/boot/dts/omap2420.dtsi +++ b/arch/arm/boot/dts/omap2420.dtsi @@ -157,6 +157,8 @@ interrupts = <26>, <34>; interrupt-names = "dsp", "iva"; ti,hwmods = "mailbox"; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <6>; }; timer1: timer@48028000 { diff --git a/arch/arm/boot/dts/omap2430.dtsi b/arch/arm/boot/dts/omap2430.dtsi index c4e8013..aa6a354 100644 --- a/arch/arm/boot/dts/omap2430.dtsi +++ b/arch/arm/boot/dts/omap2430.dtsi @@ -247,6 +247,8 @@ reg = <0x48094000 0x200>; interrupts = <26>; ti,hwmods = "mailbox"; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <6>; }; timer1: timer@49018000 { diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi index b2891a9..575a49b 100644 --- a/arch/arm/boot/dts/omap3.dtsi +++ b/arch/arm/boot/dts/omap3.dtsi @@ -332,6 +332,8 @@ ti,hwmods = "mailbox"; reg = <0x48094000 0x200>; interrupts = <26>; + ti,mbox-num-users = <2>; + ti,mbox-num-fifos = <2>; }; mcspi1: spi@48098000 { diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi index 3bfda16..0e8336e 100644 --- a/arch/arm/boot/dts/omap5.dtsi +++ b/arch/arm/boot/dts/omap5.dtsi @@ -641,6 +641,8 @@ reg = <0x4a0f4000 0x200>; interrupts = ; ti,hwmods = "mailbox"; + ti,mbox-num-users = <3>; + ti,mbox-num-fifos = <8>; }; timer1: timer@4ae18000 { -- cgit v0.10.2 From 8ebc30dd504c41c6c01eca42486ea6d64fd75f06 Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Fri, 11 Jul 2014 16:44:35 -0500 Subject: ARM: dts: OMAP4: Add mailbox node The mailbox DT node data has been added for OMAP44xx devices. Signed-off-by: Suman Anna Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi index 7e26d22..69408b5 100644 --- a/arch/arm/boot/dts/omap4.dtsi +++ b/arch/arm/boot/dts/omap4.dtsi @@ -649,6 +649,15 @@ }; }; + mailbox: mailbox@4a0f4000 { + compatible = "ti,omap4-mailbox"; + reg = <0x4a0f4000 0x200>; + interrupts = ; + ti,hwmods = "mailbox"; + ti,mbox-num-users = <3>; + ti,mbox-num-fifos = <8>; + }; + timer1: timer@4a318000 { compatible = "ti,omap3430-timer"; reg = <0x4a318000 0x80>; -- cgit v0.10.2 From 402423019a098fee735143d90dc487efc25d4b85 Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Fri, 11 Jul 2014 16:44:36 -0500 Subject: ARM: dts: AM33xx: Add mailbox node The mailbox DT node data has been added for AM33xx device. The mailbox IP in AM33xx is similar to the version found in OMAP4+ devices. Signed-off-by: Suman Anna Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi index 4a4e02d..3a0a161 100644 --- a/arch/arm/boot/dts/am33xx.dtsi +++ b/arch/arm/boot/dts/am33xx.dtsi @@ -347,6 +347,15 @@ status = "disabled"; }; + mailbox: mailbox@480C8000 { + compatible = "ti,omap4-mailbox"; + reg = <0x480C8000 0x200>; + interrupts = <77>; + ti,hwmods = "mailbox"; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <8>; + }; + timer1: timer@44e31000 { compatible = "ti,am335x-timer-1ms"; reg = <0x44e31000 0x400>; -- cgit v0.10.2 From 44e6ab1b619853f05bf7250e55a6d82864e340d7 Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Fri, 11 Jul 2014 16:44:37 -0500 Subject: ARM: dts: AM4372: Correct mailbox node data The mailbox DT node for AM4372 is enabled and is corrected to remove some properties that have crept in by mistake. Fixes: 9e3269b (ARM: dts: AM4372: Add L2, EDMA, mailbox, MMC and SHAM nodes) Cc: Lokesh Vutla Signed-off-by: Suman Anna Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi index 49fa596..c9aee0e 100644 --- a/arch/arm/boot/dts/am4372.dtsi +++ b/arch/arm/boot/dts/am4372.dtsi @@ -168,9 +168,6 @@ ti,hwmods = "mailbox"; ti,mbox-num-users = <4>; ti,mbox-num-fifos = <8>; - ti,mbox-names = "wkup_m3"; - ti,mbox-data = <0 0 0 0>; - status = "disabled"; }; timer1: timer@44e31000 { -- cgit v0.10.2 From 38baefb33f418991072d64b0c8d619def3c362d3 Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Fri, 11 Jul 2014 16:44:38 -0500 Subject: ARM: dts: DRA7: Add mailbox nodes DRA7xx has 13 system mailboxes, and is present on both the DRA72x and DRA74x family of SoCs. Add the DT nodes for all these 13 mailboxes. Except for mailbox 1, all other mailboxes do not have interrupts mapped into the MPU GIC by default. All the mailboxes have been disabled and the interrupts property information is left out intentionally for now, because of the dependencies against the crossbar driver. These mailboxes can be enabled when a usecase arises and the crossbar driver dependencies are met. NOTE: The mailbox 1 has different number of mailbox fifos and IP interrupts compared to the remaining 12 mailboxes. Signed-off-by: Suman Anna Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index c29945e..99c40d4 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -338,6 +338,123 @@ status = "disabled"; }; + mailbox1: mailbox@4a0f4000 { + compatible = "ti,omap4-mailbox"; + reg = <0x4a0f4000 0x200>; + ti,hwmods = "mailbox1"; + ti,mbox-num-users = <3>; + ti,mbox-num-fifos = <8>; + status = "disabled"; + }; + + mailbox2: mailbox@4883a000 { + compatible = "ti,omap4-mailbox"; + reg = <0x4883a000 0x200>; + ti,hwmods = "mailbox2"; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <12>; + status = "disabled"; + }; + + mailbox3: mailbox@4883c000 { + compatible = "ti,omap4-mailbox"; + reg = <0x4883c000 0x200>; + ti,hwmods = "mailbox3"; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <12>; + status = "disabled"; + }; + + mailbox4: mailbox@4883e000 { + compatible = "ti,omap4-mailbox"; + reg = <0x4883e000 0x200>; + ti,hwmods = "mailbox4"; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <12>; + status = "disabled"; + }; + + mailbox5: mailbox@48840000 { + compatible = "ti,omap4-mailbox"; + reg = <0x48840000 0x200>; + ti,hwmods = "mailbox5"; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <12>; + status = "disabled"; + }; + + mailbox6: mailbox@48842000 { + compatible = "ti,omap4-mailbox"; + reg = <0x48842000 0x200>; + ti,hwmods = "mailbox6"; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <12>; + status = "disabled"; + }; + + mailbox7: mailbox@48844000 { + compatible = "ti,omap4-mailbox"; + reg = <0x48844000 0x200>; + ti,hwmods = "mailbox7"; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <12>; + status = "disabled"; + }; + + mailbox8: mailbox@48846000 { + compatible = "ti,omap4-mailbox"; + reg = <0x48846000 0x200>; + ti,hwmods = "mailbox8"; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <12>; + status = "disabled"; + }; + + mailbox9: mailbox@4885e000 { + compatible = "ti,omap4-mailbox"; + reg = <0x4885e000 0x200>; + ti,hwmods = "mailbox9"; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <12>; + status = "disabled"; + }; + + mailbox10: mailbox@48860000 { + compatible = "ti,omap4-mailbox"; + reg = <0x48860000 0x200>; + ti,hwmods = "mailbox10"; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <12>; + status = "disabled"; + }; + + mailbox11: mailbox@48862000 { + compatible = "ti,omap4-mailbox"; + reg = <0x48862000 0x200>; + ti,hwmods = "mailbox11"; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <12>; + status = "disabled"; + }; + + mailbox12: mailbox@48864000 { + compatible = "ti,omap4-mailbox"; + reg = <0x48864000 0x200>; + ti,hwmods = "mailbox12"; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <12>; + status = "disabled"; + }; + + mailbox13: mailbox@48802000 { + compatible = "ti,omap4-mailbox"; + reg = <0x48802000 0x200>; + ti,hwmods = "mailbox13"; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <12>; + status = "disabled"; + }; + timer1: timer@4ae18000 { compatible = "ti,omap5430-timer"; reg = <0x4ae18000 0x80>; -- cgit v0.10.2 From 067395d49c5149b7b50fa93e9cb691a184b24927 Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Fri, 11 Jul 2014 16:44:39 -0500 Subject: ARM: DRA7: hwmod_data: Add mailbox hwmod data Add the hwmod data for the 13 instances of the system mailbox IP in DRA7 SoC. The patch is needed for performing a soft-reset while configuring the respective mailbox instance, otherwise is a non-essential change for functionality. The modules are smart idled on reset, and the IP module mode is hardware controlled. Cc: Rajendra Nayak Cc: Paul Walmsley Signed-off-by: Suman Anna Signed-off-by: Tony Lindgren diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c index 20b4398..e35f5b1 100644 --- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c @@ -939,6 +939,194 @@ static struct omap_hwmod dra7xx_i2c5_hwmod = { }; /* + * 'mailbox' class + * + */ + +static struct omap_hwmod_class_sysconfig dra7xx_mailbox_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE | + SYSC_HAS_SOFTRESET), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type2, +}; + +static struct omap_hwmod_class dra7xx_mailbox_hwmod_class = { + .name = "mailbox", + .sysc = &dra7xx_mailbox_sysc, +}; + +/* mailbox1 */ +static struct omap_hwmod dra7xx_mailbox1_hwmod = { + .name = "mailbox1", + .class = &dra7xx_mailbox_hwmod_class, + .clkdm_name = "l4cfg_clkdm", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX1_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L4CFG_MAILBOX1_CONTEXT_OFFSET, + }, + }, +}; + +/* mailbox2 */ +static struct omap_hwmod dra7xx_mailbox2_hwmod = { + .name = "mailbox2", + .class = &dra7xx_mailbox_hwmod_class, + .clkdm_name = "l4cfg_clkdm", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX2_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L4CFG_MAILBOX2_CONTEXT_OFFSET, + }, + }, +}; + +/* mailbox3 */ +static struct omap_hwmod dra7xx_mailbox3_hwmod = { + .name = "mailbox3", + .class = &dra7xx_mailbox_hwmod_class, + .clkdm_name = "l4cfg_clkdm", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX3_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L4CFG_MAILBOX3_CONTEXT_OFFSET, + }, + }, +}; + +/* mailbox4 */ +static struct omap_hwmod dra7xx_mailbox4_hwmod = { + .name = "mailbox4", + .class = &dra7xx_mailbox_hwmod_class, + .clkdm_name = "l4cfg_clkdm", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX4_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L4CFG_MAILBOX4_CONTEXT_OFFSET, + }, + }, +}; + +/* mailbox5 */ +static struct omap_hwmod dra7xx_mailbox5_hwmod = { + .name = "mailbox5", + .class = &dra7xx_mailbox_hwmod_class, + .clkdm_name = "l4cfg_clkdm", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX5_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L4CFG_MAILBOX5_CONTEXT_OFFSET, + }, + }, +}; + +/* mailbox6 */ +static struct omap_hwmod dra7xx_mailbox6_hwmod = { + .name = "mailbox6", + .class = &dra7xx_mailbox_hwmod_class, + .clkdm_name = "l4cfg_clkdm", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX6_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L4CFG_MAILBOX6_CONTEXT_OFFSET, + }, + }, +}; + +/* mailbox7 */ +static struct omap_hwmod dra7xx_mailbox7_hwmod = { + .name = "mailbox7", + .class = &dra7xx_mailbox_hwmod_class, + .clkdm_name = "l4cfg_clkdm", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX7_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L4CFG_MAILBOX7_CONTEXT_OFFSET, + }, + }, +}; + +/* mailbox8 */ +static struct omap_hwmod dra7xx_mailbox8_hwmod = { + .name = "mailbox8", + .class = &dra7xx_mailbox_hwmod_class, + .clkdm_name = "l4cfg_clkdm", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX8_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L4CFG_MAILBOX8_CONTEXT_OFFSET, + }, + }, +}; + +/* mailbox9 */ +static struct omap_hwmod dra7xx_mailbox9_hwmod = { + .name = "mailbox9", + .class = &dra7xx_mailbox_hwmod_class, + .clkdm_name = "l4cfg_clkdm", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX9_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L4CFG_MAILBOX9_CONTEXT_OFFSET, + }, + }, +}; + +/* mailbox10 */ +static struct omap_hwmod dra7xx_mailbox10_hwmod = { + .name = "mailbox10", + .class = &dra7xx_mailbox_hwmod_class, + .clkdm_name = "l4cfg_clkdm", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX10_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L4CFG_MAILBOX10_CONTEXT_OFFSET, + }, + }, +}; + +/* mailbox11 */ +static struct omap_hwmod dra7xx_mailbox11_hwmod = { + .name = "mailbox11", + .class = &dra7xx_mailbox_hwmod_class, + .clkdm_name = "l4cfg_clkdm", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX11_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L4CFG_MAILBOX11_CONTEXT_OFFSET, + }, + }, +}; + +/* mailbox12 */ +static struct omap_hwmod dra7xx_mailbox12_hwmod = { + .name = "mailbox12", + .class = &dra7xx_mailbox_hwmod_class, + .clkdm_name = "l4cfg_clkdm", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX12_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L4CFG_MAILBOX12_CONTEXT_OFFSET, + }, + }, +}; + +/* mailbox13 */ +static struct omap_hwmod dra7xx_mailbox13_hwmod = { + .name = "mailbox13", + .class = &dra7xx_mailbox_hwmod_class, + .clkdm_name = "l4cfg_clkdm", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX13_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L4CFG_MAILBOX13_CONTEXT_OFFSET, + }, + }, +}; + +/* * 'mcspi' class * */ @@ -2246,6 +2434,110 @@ static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c5 = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; +/* l4_cfg -> mailbox1 */ +static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mailbox1 = { + .master = &dra7xx_l4_cfg_hwmod, + .slave = &dra7xx_mailbox1_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per3 -> mailbox2 */ +static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox2 = { + .master = &dra7xx_l4_per3_hwmod, + .slave = &dra7xx_mailbox2_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per3 -> mailbox3 */ +static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox3 = { + .master = &dra7xx_l4_per3_hwmod, + .slave = &dra7xx_mailbox3_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per3 -> mailbox4 */ +static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox4 = { + .master = &dra7xx_l4_per3_hwmod, + .slave = &dra7xx_mailbox4_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per3 -> mailbox5 */ +static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox5 = { + .master = &dra7xx_l4_per3_hwmod, + .slave = &dra7xx_mailbox5_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per3 -> mailbox6 */ +static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox6 = { + .master = &dra7xx_l4_per3_hwmod, + .slave = &dra7xx_mailbox6_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per3 -> mailbox7 */ +static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox7 = { + .master = &dra7xx_l4_per3_hwmod, + .slave = &dra7xx_mailbox7_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per3 -> mailbox8 */ +static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox8 = { + .master = &dra7xx_l4_per3_hwmod, + .slave = &dra7xx_mailbox8_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per3 -> mailbox9 */ +static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox9 = { + .master = &dra7xx_l4_per3_hwmod, + .slave = &dra7xx_mailbox9_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per3 -> mailbox10 */ +static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox10 = { + .master = &dra7xx_l4_per3_hwmod, + .slave = &dra7xx_mailbox10_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per3 -> mailbox11 */ +static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox11 = { + .master = &dra7xx_l4_per3_hwmod, + .slave = &dra7xx_mailbox11_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per3 -> mailbox12 */ +static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox12 = { + .master = &dra7xx_l4_per3_hwmod, + .slave = &dra7xx_mailbox12_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per3 -> mailbox13 */ +static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox13 = { + .master = &dra7xx_l4_per3_hwmod, + .slave = &dra7xx_mailbox13_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + /* l4_per1 -> mcspi1 */ static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi1 = { .master = &dra7xx_l4_per1_hwmod, @@ -2662,6 +2954,19 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = { &dra7xx_l4_per1__i2c3, &dra7xx_l4_per1__i2c4, &dra7xx_l4_per1__i2c5, + &dra7xx_l4_cfg__mailbox1, + &dra7xx_l4_per3__mailbox2, + &dra7xx_l4_per3__mailbox3, + &dra7xx_l4_per3__mailbox4, + &dra7xx_l4_per3__mailbox5, + &dra7xx_l4_per3__mailbox6, + &dra7xx_l4_per3__mailbox7, + &dra7xx_l4_per3__mailbox8, + &dra7xx_l4_per3__mailbox9, + &dra7xx_l4_per3__mailbox10, + &dra7xx_l4_per3__mailbox11, + &dra7xx_l4_per3__mailbox12, + &dra7xx_l4_per3__mailbox13, &dra7xx_l4_per1__mcspi1, &dra7xx_l4_per1__mcspi2, &dra7xx_l4_per1__mcspi3, -- cgit v0.10.2 From dbd5f4603e221cbbd6f206fb45e4d8b81f011a6a Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Fri, 11 Jul 2014 16:44:40 -0500 Subject: ARM: OMAP2+: Avoid mailbox legacy device creation for DT-boot The legacy platform device for mailbox should not be created for a DT boot, so adjust the platform device initialization logic appropriately. Signed-off-by: Suman Anna Signed-off-by: Tony Lindgren diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c index 592ba0a..708eb7d 100644 --- a/arch/arm/mach-omap2/devices.c +++ b/arch/arm/mach-omap2/devices.c @@ -460,9 +460,9 @@ static int __init omap2_init_devices(void) omap_init_audio(); omap_init_camera(); omap_init_hdmi_audio(); - omap_init_mbox(); /* If dtb is there, the devices will be created dynamically */ if (!of_have_populated_dt()) { + omap_init_mbox(); omap_init_mcspi(); omap_init_sham(); omap_init_aes(); -- cgit v0.10.2 From 635b3801e0bb59ce7440588a63b4d54f320d0cbc Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Fri, 11 Jul 2014 16:44:41 -0500 Subject: ARM: OMAP2: hwmod_data: Remove legacy mailbox data and addrs OMAP2 devices are devicetree boot only, and the legacy mode of mailbox device creation should no longer be used, so remove the mailbox attribute data and the hwmod addr space used for creating mailboxes in legacy mode. Acked-by: Paul Walmsley Signed-off-by: Suman Anna Signed-off-by: Tony Lindgren diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c index 2f15979..65b1647 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c @@ -16,7 +16,6 @@ #include #include #include -#include #include #include "omap_hwmod.h" @@ -163,18 +162,6 @@ static struct omap_hwmod omap2420_dma_system_hwmod = { }; /* mailbox */ -static struct omap_mbox_dev_info omap2420_mailbox_info[] = { - { .name = "dsp", .tx_id = 0, .rx_id = 1, .irq_id = 0, .usr_id = 0 }, - { .name = "iva", .tx_id = 2, .rx_id = 3, .irq_id = 1, .usr_id = 3 }, -}; - -static struct omap_mbox_pdata omap2420_mailbox_attrs = { - .num_users = 4, - .num_fifos = 6, - .info_cnt = ARRAY_SIZE(omap2420_mailbox_info), - .info = omap2420_mailbox_info, -}; - static struct omap_hwmod omap2420_mailbox_hwmod = { .name = "mailbox", .class = &omap2xxx_mailbox_hwmod_class, @@ -188,7 +175,6 @@ static struct omap_hwmod omap2420_mailbox_hwmod = { .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT, }, }, - .dev_attr = &omap2420_mailbox_attrs, }; /* diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c index 6d1b609..c2555cb 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c @@ -17,7 +17,6 @@ #include #include #include -#include #include #include "omap_hwmod.h" @@ -161,17 +160,6 @@ static struct omap_hwmod omap2430_dma_system_hwmod = { }; /* mailbox */ -static struct omap_mbox_dev_info omap2430_mailbox_info[] = { - { .name = "dsp", .tx_id = 0, .rx_id = 1 }, -}; - -static struct omap_mbox_pdata omap2430_mailbox_attrs = { - .num_users = 4, - .num_fifos = 6, - .info_cnt = ARRAY_SIZE(omap2430_mailbox_info), - .info = omap2430_mailbox_info, -}; - static struct omap_hwmod omap2430_mailbox_hwmod = { .name = "mailbox", .class = &omap2xxx_mailbox_hwmod_class, @@ -185,7 +173,6 @@ static struct omap_hwmod omap2430_mailbox_hwmod = { .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT, }, }, - .dev_attr = &omap2430_mailbox_attrs, }; /* mcspi3 */ diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_interconnect_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_interconnect_data.c index 0413dab..c1e98d5 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_interconnect_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_interconnect_data.c @@ -152,15 +152,6 @@ struct omap_hwmod_addr_space omap2_dma_system_addrs[] = { { } }; -struct omap_hwmod_addr_space omap2_mailbox_addrs[] = { - { - .pa_start = 0x48094000, - .pa_end = 0x48094000 + SZ_512 - 1, - .flags = ADDR_TYPE_RT, - }, - { } -}; - struct omap_hwmod_addr_space omap2_mcbsp1_addrs[] = { { .name = "mpu", diff --git a/arch/arm/mach-omap2/omap_hwmod_common_data.h b/arch/arm/mach-omap2/omap_hwmod_common_data.h index 2c38c6b..11ed5a1 100644 --- a/arch/arm/mach-omap2/omap_hwmod_common_data.h +++ b/arch/arm/mach-omap2/omap_hwmod_common_data.h @@ -33,7 +33,6 @@ extern struct omap_hwmod_addr_space omap2_mcspi1_addr_space[]; extern struct omap_hwmod_addr_space omap2_mcspi2_addr_space[]; extern struct omap_hwmod_addr_space omap2430_mcspi3_addr_space[]; extern struct omap_hwmod_addr_space omap2_dma_system_addrs[]; -extern struct omap_hwmod_addr_space omap2_mailbox_addrs[]; extern struct omap_hwmod_addr_space omap2_mcbsp1_addrs[]; extern struct omap_hwmod_addr_space omap2_hdq1w_addr_space[]; -- cgit v0.10.2 From 6be5da73fca9599394effac7338c4bb5cf399c7e Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Fri, 11 Jul 2014 16:44:42 -0500 Subject: ARM: OMAP4: hwmod_data: Remove legacy mailbox addrs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The legacy-style definition of the hwmod addr space is no longer required after the addition of the OMAP4 mailbox DT node, so clean up this data. Cc: Paul Walmsley Cc: Benoît Cousson Signed-off-by: Suman Anna Signed-off-by: Tony Lindgren diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c index 41e54f7..5e61b8c 100644 --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c @@ -4142,21 +4142,11 @@ static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = { - { - .pa_start = 0x4a0f4000, - .pa_end = 0x4a0f41ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - /* l4_cfg -> mailbox */ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = { .master = &omap44xx_l4_cfg_hwmod, .slave = &omap44xx_mailbox_hwmod, .clk = "l4_div_ck", - .addr = omap44xx_mailbox_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; -- cgit v0.10.2 From cbf14f3ab9bd6295b345fc812f08ddd844fb183e Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Fri, 11 Jul 2014 16:44:43 -0500 Subject: ARM: AM33xx: hwmod_data: Remove legacy mailbox addrs The legacy-style definition of the hwmod addr space is no longer required as AM33xx/AM43xx are DT-boot only, and the minimal mailbox DT nodes have been added, so clean up this data. Acked-by: Paul Walmsley Signed-off-by: Suman Anna Signed-off-by: Tony Lindgren diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_interconnect_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_interconnect_data.c index e2db378..8f5989d 100644 --- a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_interconnect_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_interconnect_data.c @@ -317,21 +317,11 @@ struct omap_hwmod_ocp_if am33xx_l4_per__i2c3 = { .user = OCP_USER_MPU, }; -static struct omap_hwmod_addr_space am33xx_mailbox_addrs[] = { - { - .pa_start = 0x480C8000, - .pa_end = 0x480C8000 + (SZ_4K - 1), - .flags = ADDR_TYPE_RT - }, - { } -}; - /* l4 ls -> mailbox */ struct omap_hwmod_ocp_if am33xx_l4_per__mailbox = { .master = &am33xx_l4_ls_hwmod, .slave = &am33xx_mailbox_hwmod, .clk = "l4ls_gclk", - .addr = am33xx_mailbox_addrs, .user = OCP_USER_MPU, }; -- cgit v0.10.2 From 76be4a54157ab0059fb29d8d516db46d239812e2 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Thu, 12 Jun 2014 17:15:22 +0530 Subject: ARM: OMAP2+: DMA: remove requirement of irq for platform-dma driver we have currently 2 DMA drivers that try to co-exist. drivers/dma/omap-dma.c which registers it's own IRQ and is device tree aware and uses arch/arm/plat-omap/dma.c instance created by arch/arm/mach-omap2/dma.c to maintain channel usage (omap_request_dma). Currently both try to register interrupts and mach-omap2/plat-omap dma.c attempts to use the IRQ number registered by hwmod to register it's own interrupt handler. Now, there is no reasonable way of static allocating DMA irq in GIC SPI when we use crossbar. However, since the dma_chan structure is freed as a result of IRQ not being present due to devm allocation, maintaining information of channel by platform code fails at a later point in time when that region of memory is reused. So, if hwmod does not indicate an IRQ number, then, assume that dma-engine will take care of the interrupt handling. Signed-off-by: Nishanth Menon Signed-off-by: Tony Lindgren diff --git a/arch/arm/mach-omap2/dma.c b/arch/arm/mach-omap2/dma.c index a6d2cf1..e1a56d8 100644 --- a/arch/arm/mach-omap2/dma.c +++ b/arch/arm/mach-omap2/dma.c @@ -259,6 +259,9 @@ static int __init omap2_system_dma_init_dev(struct omap_hwmod *oh, void *unused) if (cpu_is_omap34xx() && (omap_type() != OMAP2_DEVICE_TYPE_GP)) d->dev_caps |= HS_CHANNELS_RESERVED; + if (platform_get_irq_byname(pdev, "0") < 0) + d->dev_caps |= DMA_ENGINE_HANDLE_IRQ; + /* Check the capabilities register for descriptor loading feature */ if (dma_read(CAPS_0, 0) & DMA_HAS_DESCRIPTOR_CAPS) dma_common_ch_end = CCDN; diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c index b5608b1..7aae0e5 100644 --- a/arch/arm/plat-omap/dma.c +++ b/arch/arm/plat-omap/dma.c @@ -2100,7 +2100,7 @@ static int omap_system_dma_probe(struct platform_device *pdev) omap_dma_set_global_params(DMA_DEFAULT_ARB_RATE, DMA_DEFAULT_FIFO_DEPTH, 0); - if (dma_omap2plus()) { + if (dma_omap2plus() && !(d->dev_caps & DMA_ENGINE_HANDLE_IRQ)) { strcpy(irq_name, "0"); dma_irq = platform_get_irq_byname(pdev, irq_name); if (dma_irq < 0) { @@ -2145,7 +2145,8 @@ static int omap_system_dma_remove(struct platform_device *pdev) char irq_name[4]; strcpy(irq_name, "0"); dma_irq = platform_get_irq_byname(pdev, irq_name); - remove_irq(dma_irq, &omap24xx_dma_irq); + if (dma_irq >= 0) + remove_irq(dma_irq, &omap24xx_dma_irq); } else { int irq_rel = 0; for ( ; irq_rel < dma_chan_count; irq_rel++) { diff --git a/include/linux/omap-dma.h b/include/linux/omap-dma.h index 88e6ea4..6f06f8b 100644 --- a/include/linux/omap-dma.h +++ b/include/linux/omap-dma.h @@ -130,6 +130,7 @@ #define IS_WORD_16 BIT(0xd) #define ENABLE_16XX_MODE BIT(0xe) #define HS_CHANNELS_RESERVED BIT(0xf) +#define DMA_ENGINE_HANDLE_IRQ BIT(0x10) /* Defines for DMA Capabilities */ #define DMA_HAS_TRANSPARENT_CAPS (0x1 << 18) -- cgit v0.10.2 From 2aa7f52b532f9dc2c216c2892bc77b2fc2c89bb7 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Thu, 12 Jun 2014 17:15:23 +0530 Subject: ARM: DRA7: hwmod: remove interrupts for DMA DMA interrupts are now available in of, and the definitions are duplicates in hwmod. This prevents us from dynamically allocating interrupt resources for dma from devicetree. Signed-off-by: Nishanth Menon Signed-off-by: Tony Lindgren diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c index 20b4398..31fd260 100644 --- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c @@ -343,19 +343,10 @@ static struct omap_dma_dev_attr dma_dev_attr = { }; /* dma_system */ -static struct omap_hwmod_irq_info dra7xx_dma_system_irqs[] = { - { .name = "0", .irq = 12 + DRA7XX_IRQ_GIC_START }, - { .name = "1", .irq = 13 + DRA7XX_IRQ_GIC_START }, - { .name = "2", .irq = 14 + DRA7XX_IRQ_GIC_START }, - { .name = "3", .irq = 15 + DRA7XX_IRQ_GIC_START }, - { .irq = -1 } -}; - static struct omap_hwmod dra7xx_dma_system_hwmod = { .name = "dma_system", .class = &dra7xx_dma_hwmod_class, .clkdm_name = "dma_clkdm", - .mpu_irqs = dra7xx_dma_system_irqs, .main_clk = "l3_iclk_div", .prcm = { .omap4 = { -- cgit v0.10.2 From df0d0f11ff00db0b880e632549619a1b86b190d2 Mon Sep 17 00:00:00 2001 From: Roger Quadros Date: Sat, 5 Jul 2014 17:44:58 -0600 Subject: ARM: DRA7: hwmod: Add OCP2SCP3 module This module is needed for the SATA and PCIe PHYs. Signed-off-by: Roger Quadros Reviewed-by: Rajendra Nayak Tested-by: Sekhar Nori Signed-off-by: Paul Walmsley diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c index 20b4398..c9daee4 100644 --- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c @@ -1215,6 +1215,21 @@ static struct omap_hwmod dra7xx_ocp2scp1_hwmod = { }, }; +/* ocp2scp3 */ +static struct omap_hwmod dra7xx_ocp2scp3_hwmod = { + .name = "ocp2scp3", + .class = &dra7xx_ocp2scp_hwmod_class, + .clkdm_name = "l3init_clkdm", + .main_clk = "l4_root_clk_div", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET, + .modulemode = MODULEMODE_HWCTRL, + }, + }, +}; + /* * 'qspi' class * @@ -2326,6 +2341,14 @@ static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp1 = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; +/* l4_cfg -> ocp2scp3 */ +static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp3 = { + .master = &dra7xx_l4_cfg_hwmod, + .slave = &dra7xx_ocp2scp3_hwmod, + .clk = "l4_root_clk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + static struct omap_hwmod_addr_space dra7xx_qspi_addrs[] = { { .pa_start = 0x4b300000, @@ -2672,6 +2695,7 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = { &dra7xx_l4_per1__mmc4, &dra7xx_l4_cfg__mpu, &dra7xx_l4_cfg__ocp2scp1, + &dra7xx_l4_cfg__ocp2scp3, &dra7xx_l3_main_1__qspi, &dra7xx_l4_cfg__sata, &dra7xx_l4_cfg__smartreflex_core, -- cgit v0.10.2 From 70c18ef7f1aed9f4eb9013412190081c9836d7ec Mon Sep 17 00:00:00 2001 From: Kishon Vijay Abraham I Date: Wed, 25 Jun 2014 23:32:45 +0530 Subject: arm: dra7xx: Add hwmod data for pcie1 phy and pcie2 phy Added hwmod data for pcie1 and pcie2 phy present in DRA7xx SOC. Also added the missing CLKCTRL OFFSET macro and CONTEXT OFFSET macro for pcie1 phy and pcie2 phy. Cc: Tony Lindgren Cc: Russell King Cc: Paul Walmsley Signed-off-by: Kishon Vijay Abraham I Tested-by: Kishon Vijay Abraham I Reviewed-by: Rajendra Nayak Signed-off-by: Paul Walmsley diff --git a/arch/arm/mach-omap2/cm2_7xx.h b/arch/arm/mach-omap2/cm2_7xx.h index 9ad7594..e966e3a 100644 --- a/arch/arm/mach-omap2/cm2_7xx.h +++ b/arch/arm/mach-omap2/cm2_7xx.h @@ -357,6 +357,10 @@ #define DRA7XX_CM_L3INIT_SATA_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0088) #define DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET 0x00a0 #define DRA7XX_CM_PCIE_STATICDEP_OFFSET 0x00a4 +#define DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL_OFFSET 0x00b0 +#define DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x00b0) +#define DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL_OFFSET 0x00b8 +#define DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x00b8) #define DRA7XX_CM_GMAC_CLKSTCTRL_OFFSET 0x00c0 #define DRA7XX_CM_GMAC_STATICDEP_OFFSET 0x00c4 #define DRA7XX_CM_GMAC_DYNAMICDEP_OFFSET 0x00c8 diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c index c9daee4..b21647d 100644 --- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c @@ -1231,6 +1231,45 @@ static struct omap_hwmod dra7xx_ocp2scp3_hwmod = { }; /* + * 'PCIE PHY' class + * + */ + +static struct omap_hwmod_class dra7xx_pcie_phy_hwmod_class = { + .name = "pcie-phy", +}; + +/* pcie1 phy */ +static struct omap_hwmod dra7xx_pcie1_phy_hwmod = { + .name = "pcie1-phy", + .class = &dra7xx_pcie_phy_hwmod_class, + .clkdm_name = "l3init_clkdm", + .main_clk = "l4_root_clk_div", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L3INIT_PCIESS1_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* pcie2 phy */ +static struct omap_hwmod dra7xx_pcie2_phy_hwmod = { + .name = "pcie2-phy", + .class = &dra7xx_pcie_phy_hwmod_class, + .clkdm_name = "l3init_clkdm", + .main_clk = "l4_root_clk_div", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L3INIT_PCIESS2_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* * 'qspi' class * */ @@ -2349,6 +2388,22 @@ static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp3 = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; +/* l4_cfg -> pcie1 phy */ +static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie1_phy = { + .master = &dra7xx_l4_cfg_hwmod, + .slave = &dra7xx_pcie1_phy_hwmod, + .clk = "l4_root_clk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_cfg -> pcie2 phy */ +static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie2_phy = { + .master = &dra7xx_l4_cfg_hwmod, + .slave = &dra7xx_pcie2_phy_hwmod, + .clk = "l4_root_clk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + static struct omap_hwmod_addr_space dra7xx_qspi_addrs[] = { { .pa_start = 0x4b300000, @@ -2696,6 +2751,8 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = { &dra7xx_l4_cfg__mpu, &dra7xx_l4_cfg__ocp2scp1, &dra7xx_l4_cfg__ocp2scp3, + &dra7xx_l4_cfg__pcie1_phy, + &dra7xx_l4_cfg__pcie2_phy, &dra7xx_l3_main_1__qspi, &dra7xx_l4_cfg__sata, &dra7xx_l4_cfg__smartreflex_core, diff --git a/arch/arm/mach-omap2/prm7xx.h b/arch/arm/mach-omap2/prm7xx.h index d92a840..4bb50fbf 100644 --- a/arch/arm/mach-omap2/prm7xx.h +++ b/arch/arm/mach-omap2/prm7xx.h @@ -374,6 +374,10 @@ #define DRA7XX_RM_L3INIT_IEEE1500_2_OCP_CONTEXT_OFFSET 0x007c #define DRA7XX_PM_L3INIT_SATA_WKDEP_OFFSET 0x0088 #define DRA7XX_RM_L3INIT_SATA_CONTEXT_OFFSET 0x008c +#define DRA7XX_PM_L3INIT_PCIESS1_WKDEP_OFFSET 0x00b0 +#define DRA7XX_RM_L3INIT_PCIESS1_CONTEXT_OFFSET 0x00b4 +#define DRA7XX_PM_L3INIT_PCIESS2_WKDEP_OFFSET 0x00b8 +#define DRA7XX_RM_L3INIT_PCIESS2_CONTEXT_OFFSET 0x00bc #define DRA7XX_RM_GMAC_GMAC_CONTEXT_OFFSET 0x00d4 #define DRA7XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET 0x00e4 #define DRA7XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET 0x00ec -- cgit v0.10.2 From 8dd3eb711ecfe639306ccbe47a12bb2f2f64f4e2 Mon Sep 17 00:00:00 2001 From: Kishon Vijay Abraham I Date: Wed, 9 Jul 2014 14:32:47 +0530 Subject: arm: dra7xx: Add hwmod data for pcie1 and pcie2 subsystems Added hwmod data for pcie1 and pcie2 subsystem present in DRA7xx SOC. Cc: Tony Lindgren Cc: Russell King Cc: Paul Walmsley Signed-off-by: Kishon Vijay Abraham I Tested-by: Kishon Vijay Abraham I Reviewed-by: Rajendra Nayak Signed-off-by: Paul Walmsley diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c index b21647d..559bbcbe 100644 --- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c @@ -1231,6 +1231,43 @@ static struct omap_hwmod dra7xx_ocp2scp3_hwmod = { }; /* + * 'PCIE' class + * + */ + +static struct omap_hwmod_class dra7xx_pcie_hwmod_class = { + .name = "pcie", +}; + +/* pcie1 */ +static struct omap_hwmod dra7xx_pcie1_hwmod = { + .name = "pcie1", + .class = &dra7xx_pcie_hwmod_class, + .clkdm_name = "pcie_clkdm", + .main_clk = "l4_root_clk_div", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* pcie2 */ +static struct omap_hwmod dra7xx_pcie2_hwmod = { + .name = "pcie2", + .class = &dra7xx_pcie_hwmod_class, + .clkdm_name = "pcie_clkdm", + .main_clk = "l4_root_clk_div", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* * 'PCIE PHY' class * */ @@ -2388,6 +2425,38 @@ static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp3 = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; +/* l3_main_1 -> pcie1 */ +static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pcie1 = { + .master = &dra7xx_l3_main_1_hwmod, + .slave = &dra7xx_pcie1_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_cfg -> pcie1 */ +static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie1 = { + .master = &dra7xx_l4_cfg_hwmod, + .slave = &dra7xx_pcie1_hwmod, + .clk = "l4_root_clk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l3_main_1 -> pcie2 */ +static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pcie2 = { + .master = &dra7xx_l3_main_1_hwmod, + .slave = &dra7xx_pcie2_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_cfg -> pcie2 */ +static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie2 = { + .master = &dra7xx_l4_cfg_hwmod, + .slave = &dra7xx_pcie2_hwmod, + .clk = "l4_root_clk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + /* l4_cfg -> pcie1 phy */ static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie1_phy = { .master = &dra7xx_l4_cfg_hwmod, @@ -2751,6 +2820,10 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = { &dra7xx_l4_cfg__mpu, &dra7xx_l4_cfg__ocp2scp1, &dra7xx_l4_cfg__ocp2scp3, + &dra7xx_l3_main_1__pcie1, + &dra7xx_l4_cfg__pcie1, + &dra7xx_l3_main_1__pcie2, + &dra7xx_l4_cfg__pcie2, &dra7xx_l4_cfg__pcie1_phy, &dra7xx_l4_cfg__pcie2_phy, &dra7xx_l3_main_1__qspi, -- cgit v0.10.2 From 077c42f75ee309330a11d9437b4166601e4f2cd3 Mon Sep 17 00:00:00 2001 From: Mugunthan V N Date: Tue, 8 Jul 2014 18:46:39 +0530 Subject: arm: dra7xx: Add hwmod data for MDIO and CPSW Adding hwmod data for CPSW and MDIO which is present in DRA7xx SoC Cc: Rajendra Nayak Cc: Tony Lindgren Cc: Russell King Cc: Paul Walmsley Signed-off-by: Mugunthan V N Tested-by: Sebastian Andrzej Siewior Acked-by: Tony Lindgren Signed-off-by: Paul Walmsley diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c index 559bbcbe..6cf7b6f 100644 --- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c @@ -273,6 +273,56 @@ static struct omap_hwmod dra7xx_ctrl_module_wkup_hwmod = { }; /* + * 'gmac' class + * cpsw/gmac sub system + */ +static struct omap_hwmod_class_sysconfig dra7xx_gmac_sysc = { + .rev_offs = 0x0, + .sysc_offs = 0x8, + .syss_offs = 0x4, + .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE | + SYSS_HAS_RESET_STATUS), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE | + MSTANDBY_NO), + .sysc_fields = &omap_hwmod_sysc_type3, +}; + +static struct omap_hwmod_class dra7xx_gmac_hwmod_class = { + .name = "gmac", + .sysc = &dra7xx_gmac_sysc, +}; + +static struct omap_hwmod dra7xx_gmac_hwmod = { + .name = "gmac", + .class = &dra7xx_gmac_hwmod_class, + .clkdm_name = "gmac_clkdm", + .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY), + .main_clk = "dpll_gmac_ck", + .mpu_rt_idx = 1, + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_GMAC_GMAC_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_GMAC_GMAC_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* + * 'mdio' class + */ +static struct omap_hwmod_class dra7xx_mdio_hwmod_class = { + .name = "davinci_mdio", +}; + +static struct omap_hwmod dra7xx_mdio_hwmod = { + .name = "davinci_mdio", + .class = &dra7xx_mdio_hwmod_class, + .clkdm_name = "gmac_clkdm", + .main_clk = "dpll_gmac_ck", +}; + +/* * 'dcan' class * */ @@ -2090,6 +2140,19 @@ static struct omap_hwmod_ocp_if dra7xx_l4_wkup__ctrl_module_wkup = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; +static struct omap_hwmod_ocp_if dra7xx_l4_per2__cpgmac0 = { + .master = &dra7xx_l4_per2_hwmod, + .slave = &dra7xx_gmac_hwmod, + .clk = "dpll_gmac_ck", + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_ocp_if dra7xx_gmac__mdio = { + .master = &dra7xx_gmac_hwmod, + .slave = &dra7xx_mdio_hwmod, + .user = OCP_USER_MPU, +}; + /* l4_wkup -> dcan1 */ static struct omap_hwmod_ocp_if dra7xx_l4_wkup__dcan1 = { .master = &dra7xx_l4_wkup_hwmod, @@ -2789,6 +2852,8 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = { &dra7xx_l4_wkup__ctrl_module_wkup, &dra7xx_l4_wkup__dcan1, &dra7xx_l4_per2__dcan2, + &dra7xx_l4_per2__cpgmac0, + &dra7xx_gmac__mdio, &dra7xx_l4_cfg__dma_system, &dra7xx_l3_main_1__dss, &dra7xx_l3_main_1__dispc, -- cgit v0.10.2 From c913c8a15a02e91c1f0302d68bebf66838a9689d Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Tue, 22 Jul 2014 13:15:57 -0600 Subject: ARM: DRA7: hwmod: Add data for RTC Add hwmod data for RTC Signed-off-by: Lokesh Vutla Signed-off-by: Sekhar Nori Reviewed-by: Rajendra Nayak [paul@pwsan.com: updated to apply] Signed-off-by: Paul Walmsley diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c index 6cf7b6f..83d19d3 100644 --- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c @@ -1390,6 +1390,38 @@ static struct omap_hwmod dra7xx_qspi_hwmod = { }; /* + * 'rtcss' class + * + */ +static struct omap_hwmod_class_sysconfig dra7xx_rtcss_sysc = { + .sysc_offs = 0x0078, + .sysc_flags = SYSC_HAS_SIDLEMODE, + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | + SIDLE_SMART_WKUP), + .sysc_fields = &omap_hwmod_sysc_type3, +}; + +static struct omap_hwmod_class dra7xx_rtcss_hwmod_class = { + .name = "rtcss", + .sysc = &dra7xx_rtcss_sysc, +}; + +/* rtcss */ +static struct omap_hwmod dra7xx_rtcss_hwmod = { + .name = "rtcss", + .class = &dra7xx_rtcss_hwmod_class, + .clkdm_name = "rtc_clkdm", + .main_clk = "sys_32k_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_RTC_RTCSS_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_RTC_RTCSS_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* * 'sata' class * */ @@ -2554,6 +2586,14 @@ static struct omap_hwmod_ocp_if dra7xx_l3_main_1__qspi = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; +/* l4_per3 -> rtcss */ +static struct omap_hwmod_ocp_if dra7xx_l4_per3__rtcss = { + .master = &dra7xx_l4_per3_hwmod, + .slave = &dra7xx_rtcss_hwmod, + .clk = "l4_root_clk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + static struct omap_hwmod_addr_space dra7xx_sata_addrs[] = { { .name = "sysc", @@ -2892,6 +2932,7 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = { &dra7xx_l4_cfg__pcie1_phy, &dra7xx_l4_cfg__pcie2_phy, &dra7xx_l3_main_1__qspi, + &dra7xx_l4_per3__rtcss, &dra7xx_l4_cfg__sata, &dra7xx_l4_cfg__smartreflex_core, &dra7xx_l4_cfg__smartreflex_mpu, -- cgit v0.10.2