From 9def7ccfe8d5b84d382cff83553dd6db72f61a23 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Wed, 4 Nov 2015 20:25:16 +0800 Subject: ARM: rockchip: add support smp for rk3036 The dual-core Cortex A7 rk3036 is a bit special in that it does not allow to control the actual powerdomain of the cpu cores, while the rest of the smp-bringup like reset control and entry address handling stays the same. Its bigger sibling, the quad-core rk3128 again allows powerdomain control. So allow that case by introducing a separate smp-enable-method, that simply disables powerdomain handling in the common code. Signed-off-by: Heiko Stuebner Tested-by: Xing Zheng Acked-by: Rob Herring diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt index 3a07a87..8fb0749 100644 --- a/Documentation/devicetree/bindings/arm/cpus.txt +++ b/Documentation/devicetree/bindings/arm/cpus.txt @@ -200,6 +200,7 @@ nodes to be present and contain the properties described below. "qcom,gcc-msm8660" "qcom,kpss-acc-v1" "qcom,kpss-acc-v2" + "rockchip,rk3036-smp" "rockchip,rk3066-smp" "ste,dbx500-smp" diff --git a/arch/arm/mach-rockchip/platsmp.c b/arch/arm/mach-rockchip/platsmp.c index 3e7a4b7..5c138f9 100644 --- a/arch/arm/mach-rockchip/platsmp.c +++ b/arch/arm/mach-rockchip/platsmp.c @@ -42,6 +42,7 @@ static int ncores; #define PMU_PWRDN_SCU 4 static struct regmap *pmu; +static int has_pmu = true; static int pmu_power_domain_is_on(int pd) { @@ -89,20 +90,23 @@ static int pmu_set_power_domain(int pd, bool on) if (!IS_ERR(rstc) && !on) reset_control_assert(rstc); - ret = regmap_update_bits(pmu, PMU_PWRDN_CON, BIT(pd), val); - if (ret < 0) { - pr_err("%s: could not update power domain\n", __func__); - return ret; - } - - ret = -1; - while (ret != on) { - ret = pmu_power_domain_is_on(pd); + if (has_pmu) { + ret = regmap_update_bits(pmu, PMU_PWRDN_CON, BIT(pd), val); if (ret < 0) { - pr_err("%s: could not read power domain state\n", + pr_err("%s: could not update power domain\n", __func__); return ret; } + + ret = -1; + while (ret != on) { + ret = pmu_power_domain_is_on(pd); + if (ret < 0) { + pr_err("%s: could not read power domain state\n", + __func__); + return ret; + } + } } if (!IS_ERR(rstc)) { @@ -122,7 +126,7 @@ static int rockchip_boot_secondary(unsigned int cpu, struct task_struct *idle) { int ret; - if (!sram_base_addr || !pmu) { + if (!sram_base_addr || (has_pmu && !pmu)) { pr_err("%s: sram or pmu missing for cpu boot\n", __func__); return -ENXIO; } @@ -275,7 +279,7 @@ static void __init rockchip_smp_prepare_cpus(unsigned int max_cpus) return; } - if (rockchip_smp_prepare_pmu()) + if (has_pmu && rockchip_smp_prepare_pmu()) return; if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) { @@ -318,6 +322,13 @@ static void __init rockchip_smp_prepare_cpus(unsigned int max_cpus) pmu_set_power_domain(0 + i, false); } +static void __init rk3036_smp_prepare_cpus(unsigned int max_cpus) +{ + has_pmu = false; + + rockchip_smp_prepare_cpus(max_cpus); +} + #ifdef CONFIG_HOTPLUG_CPU static int rockchip_cpu_kill(unsigned int cpu) { @@ -340,6 +351,15 @@ static void rockchip_cpu_die(unsigned int cpu) } #endif +static struct smp_operations rk3036_smp_ops __initdata = { + .smp_prepare_cpus = rk3036_smp_prepare_cpus, + .smp_boot_secondary = rockchip_boot_secondary, +#ifdef CONFIG_HOTPLUG_CPU + .cpu_kill = rockchip_cpu_kill, + .cpu_die = rockchip_cpu_die, +#endif +}; + static struct smp_operations rockchip_smp_ops __initdata = { .smp_prepare_cpus = rockchip_smp_prepare_cpus, .smp_boot_secondary = rockchip_boot_secondary, @@ -349,4 +369,5 @@ static struct smp_operations rockchip_smp_ops __initdata = { #endif }; +CPU_METHOD_OF_DECLARE(rk3036_smp, "rockchip,rk3036-smp", &rk3036_smp_ops); CPU_METHOD_OF_DECLARE(rk3066_smp, "rockchip,rk3066-smp", &rockchip_smp_ops); -- cgit v0.10.2 From 4fb1967242dbc90ac9aa2e5716bf22edfcc5aa9c Mon Sep 17 00:00:00 2001 From: Alim Akhtar Date: Tue, 20 Oct 2015 14:54:40 +0530 Subject: ARM: dts: Add syscon-{reboot, poweroff} nodes for exynos3250 This patch adds syscon-{reboot, poweroff} nodes to allow the generic syscon-{reboot, poweroff} driver to reset/poweroff exynos3250 SoC. Signed-off-by: Alim Akhtar Reviewed-by: Pankaj Dubey Reviewed-by: Javier Martinez Canillas Tested-by: Krzysztof Kozlowski Reviewed-by: Krzysztof Kozlowski Acked-by: Moritz Fischer Signed-off-by: Krzysztof Kozlowski diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi index 2f30d63..18e3def 100644 --- a/arch/arm/boot/dts/exynos3250.dtsi +++ b/arch/arm/boot/dts/exynos3250.dtsi @@ -152,6 +152,20 @@ interrupt-parent = <&gic>; }; + poweroff: syscon-poweroff { + compatible = "syscon-poweroff"; + regmap = <&pmu_system_controller>; + offset = <0x330C>; /* PS_HOLD_CONTROL */ + mask = <0x5200>; /* Reset value */ + }; + + reboot: syscon-reboot { + compatible = "syscon-reboot"; + regmap = <&pmu_system_controller>; + offset = <0x0400>; /* SWRESET */ + mask = <0x1>; + }; + mipi_phy: video-phy@10020710 { compatible = "samsung,s5pv210-mipi-video-phy"; #phy-cells = <1>; -- cgit v0.10.2 From 6d19e1a12a838d64eec3211caa63d07966de4b35 Mon Sep 17 00:00:00 2001 From: Alim Akhtar Date: Tue, 20 Oct 2015 14:54:41 +0530 Subject: ARM: dts: Add syscon-{reboot, poweroff} nodes for exynos4 This patch adds syscon-{reboot, poweroff} nodes to allow the generic syscon-{reboot, poweroff} driver to reset/poweroff exynos4 SoC. Signed-off-by: Alim Akhtar Reviewed-by: Pankaj Dubey Reviewed-by: Javier Martinez Canillas Tested-by: Krzysztof Kozlowski Tested-by: Tobias Jakobi Reviewed-by: Krzysztof Kozlowski Acked-by: Moritz Fischer Signed-off-by: Krzysztof Kozlowski diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi index 3184e10..07e10ee 100644 --- a/arch/arm/boot/dts/exynos4.dtsi +++ b/arch/arm/boot/dts/exynos4.dtsi @@ -158,6 +158,20 @@ interrupt-parent = <&gic>; }; + poweroff: syscon-poweroff { + compatible = "syscon-poweroff"; + regmap = <&pmu_system_controller>; + offset = <0x330C>; /* PS_HOLD_CONTROL */ + mask = <0x5200>; /* reset value */ + }; + + reboot: syscon-reboot { + compatible = "syscon-reboot"; + regmap = <&pmu_system_controller>; + offset = <0x0400>; /* SWRESET */ + mask = <0x1>; + }; + dsi_0: dsi@11C80000 { compatible = "samsung,exynos4210-mipi-dsi"; reg = <0x11C80000 0x10000>; -- cgit v0.10.2 From 4a5e82960b8ea8b6d7eac714f3b33f5b27cdacab Mon Sep 17 00:00:00 2001 From: Alim Akhtar Date: Tue, 20 Oct 2015 14:54:42 +0530 Subject: ARM: dts: Add syscon-{reboot, poweroff} nodes for exynos5 This patch adds syscon-{reboot, poweroff} nodes to allow the generic syscon-{reboot, poweroff} driver to reset/poweroff exynos5 SoCs. Signed-off-by: Alim Akhtar Reviewed-by: Pankaj Dubey Reviewed-by: Javier Martinez Canillas Tested-by: Javier Martinez Canillas Tested-by: Krzysztof Kozlowski Tested-by: Anand Moon Reviewed-by: Krzysztof Kozlowski Acked-by: Moritz Fischer Signed-off-by: Krzysztof Kozlowski diff --git a/arch/arm/boot/dts/exynos5.dtsi b/arch/arm/boot/dts/exynos5.dtsi index 110dbd4..e2439e8 100644 --- a/arch/arm/boot/dts/exynos5.dtsi +++ b/arch/arm/boot/dts/exynos5.dtsi @@ -88,6 +88,20 @@ status = "disabled"; }; + poweroff: syscon-poweroff { + compatible = "syscon-poweroff"; + regmap = <&pmu_system_controller>; + offset = <0x330C>; /* PS_HOLD_CONTROL */ + mask = <0x5200>; /* reset value */ + }; + + reboot: syscon-reboot { + compatible = "syscon-reboot"; + regmap = <&pmu_system_controller>; + offset = <0x0400>; /* SWRESET */ + mask = <0x1>; + }; + fimd: fimd@14400000 { compatible = "samsung,exynos5250-fimd"; interrupt-parent = <&combiner>; -- cgit v0.10.2 From 35135f4b95f03be7ebbf31221ce738f1ec0faa02 Mon Sep 17 00:00:00 2001 From: Alim Akhtar Date: Tue, 20 Oct 2015 14:54:43 +0530 Subject: ARM: dts: Add syscon-{reboot, poweroff} nodes for exynos5410 This patch adds syscon-{reboot, poweroff} nodes to allow the generic syscon-{reboot, poweroff} driver to reset/poweroff exynos5410 SoC. Signed-off-by: Alim Akhtar Reviewed-by: Pankaj Dubey Reviewed-by: Javier Martinez Canillas Tested-by: Krzysztof Kozlowski Reviewed-by: Krzysztof Kozlowski Acked-by: Moritz Fischer Signed-off-by: Krzysztof Kozlowski diff --git a/arch/arm/boot/dts/exynos5410.dtsi b/arch/arm/boot/dts/exynos5410.dtsi index 731eefd..fad0779 100644 --- a/arch/arm/boot/dts/exynos5410.dtsi +++ b/arch/arm/boot/dts/exynos5410.dtsi @@ -102,6 +102,20 @@ reg = <0x10040000 0x5000>; }; + poweroff: syscon-poweroff { + compatible = "syscon-poweroff"; + regmap = <&pmu_system_controller>; + offset = <0x330C>; /* PS_HOLD_CONTROL */ + mask = <0x5200>; /* reset value */ + }; + + reboot: syscon-reboot { + compatible = "syscon-reboot"; + regmap = <&pmu_system_controller>; + offset = <0x0400>; /* SWRESET */ + mask = <0x1>; + }; + mct: mct@101C0000 { compatible = "samsung,exynos4210-mct"; reg = <0x101C0000 0xB00>; -- cgit v0.10.2 From 23067d39761626a0bd814a092404a7d424ebf0c3 Mon Sep 17 00:00:00 2001 From: Alim Akhtar Date: Fri, 20 Nov 2015 10:47:09 +0530 Subject: ARM: EXYNOS: Switch to syscon reboot and poweroff Since we switch to use generic syscon regmap based reset/poweroff driver for exynos SoC, lets select it from ARCH_EXYNOS instead of enabling it from various defconfigs. This also select POWER_RESET as SYSCON-{reset, poweroff} drivers depends on it. Also because of the above changes we don't need special handling for reboot/poweroff in exynos pmu driver. This patch also removes the same from exynos pmu driver to keep git bisect working. Note: This will break reboot/poweroff on boards with older dtbs with a newer kernel. Signed-off-by: Alim Akhtar Reviewed-by: Javier Martinez Canillas Tested-by: Javier Martinez Canillas Tested-by: Krzysztof Kozlowski Acked-by: Moritz Fischer Signed-off-by: Krzysztof Kozlowski diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index 3a10f1a..d279edf 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig @@ -27,6 +27,9 @@ menuconfig ARCH_EXYNOS select SRAM select THERMAL select MFD_SYSCON + select POWER_RESET + select POWER_RESET_SYSCON + select POWER_RESET_SYSCON_POWEROFF help Support for SAMSUNG EXYNOS SoCs (EXYNOS4/5) diff --git a/arch/arm/mach-exynos/pmu.c b/arch/arm/mach-exynos/pmu.c index de68938..393c04a 100644 --- a/arch/arm/mach-exynos/pmu.c +++ b/arch/arm/mach-exynos/pmu.c @@ -14,9 +14,6 @@ #include #include #include -#include -#include - #include "exynos-pmu.h" #include "regs-pmu.h" @@ -681,23 +678,6 @@ static unsigned int const exynos5420_list_disable_pmu_reg[] = { EXYNOS5420_CMU_RESET_FSYS_SYS_PWR_REG, }; -static void exynos_power_off(void) -{ - unsigned int tmp; - - pr_info("Power down.\n"); - tmp = pmu_raw_readl(EXYNOS_PS_HOLD_CONTROL); - tmp ^= (1 << 8); - pmu_raw_writel(tmp, EXYNOS_PS_HOLD_CONTROL); - - /* Wait a little so we don't give a false warning below */ - mdelay(100); - - pr_err("Power down failed, please power off system manually.\n"); - while (1) - ; -} - static void exynos5420_powerdown_conf(enum sys_powerdown mode) { u32 this_cluster; @@ -875,14 +855,6 @@ static void exynos5420_pmu_init(void) pr_info("EXYNOS5420 PMU initialized\n"); } -static int pmu_restart_notify(struct notifier_block *this, - unsigned long code, void *unused) -{ - pmu_raw_writel(0x1, EXYNOS_SWRESET); - - return NOTIFY_DONE; -} - static const struct exynos_pmu_data exynos3250_pmu_data = { .pmu_config = exynos3250_pmu_config, .pmu_init = exynos3250_pmu_init, @@ -940,20 +912,11 @@ static const struct of_device_id exynos_pmu_of_device_ids[] = { { /*sentinel*/ }, }; -/* - * Exynos PMU restart notifier, handles restart functionality - */ -static struct notifier_block pmu_restart_handler = { - .notifier_call = pmu_restart_notify, - .priority = 128, -}; - static int exynos_pmu_probe(struct platform_device *pdev) { const struct of_device_id *match; struct device *dev = &pdev->dev; struct resource *res; - int ret; res = platform_get_resource(pdev, IORESOURCE_MEM, 0); pmu_base_addr = devm_ioremap_resource(dev, res); @@ -978,12 +941,6 @@ static int exynos_pmu_probe(struct platform_device *pdev) platform_set_drvdata(pdev, pmu_context); - ret = register_restart_handler(&pmu_restart_handler); - if (ret) - dev_warn(dev, "can't register restart handler err=%d\n", ret); - - pm_power_off = exynos_power_off; - dev_dbg(dev, "Exynos PMU Driver probe done\n"); return 0; } -- cgit v0.10.2 From f31c7c7a0e4cedeee3cac9dbcb0a202008b86b54 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 29 Oct 2015 10:38:05 +0900 Subject: ARM: EXYNOS: Constify local exynos_pmu_data structure The Exynos5420 instance of exynos_pmu_data structure is not modified and can be made const. Suggested-by: Pavel Fedin Signed-off-by: Krzysztof Kozlowski Reviewed-by: Pankaj Dubey diff --git a/arch/arm/mach-exynos/pmu.c b/arch/arm/mach-exynos/pmu.c index 393c04a..28b7a72 100644 --- a/arch/arm/mach-exynos/pmu.c +++ b/arch/arm/mach-exynos/pmu.c @@ -880,7 +880,7 @@ static const struct exynos_pmu_data exynos5250_pmu_data = { .powerdown_conf = exynos5_powerdown_conf, }; -static struct exynos_pmu_data exynos5420_pmu_data = { +static const struct exynos_pmu_data exynos5420_pmu_data = { .pmu_config = exynos5420_pmu_config, .pmu_init = exynos5420_pmu_init, .powerdown_conf = exynos5420_powerdown_conf, -- cgit v0.10.2 From 8438aef01d3560549b3a95d247b3a69311fa6f2d Mon Sep 17 00:00:00 2001 From: Pankaj Dubey Date: Fri, 13 Nov 2015 14:59:35 +0530 Subject: ARM: EXYNOS: Remove redundant code from regs-pmu.h Commit 6ec4f8d0d91f ("ARM: EXYNOS: add generic function to calculate cpu number") introduced exynos_pmu_cpunr to be used by multi-cluster SoCs e.g. Exynos5420, but it's no more used in the codebase and hence removing this part of code. Signed-off-by: Pankaj Dubey Reviewed-by: Krzysztof Kozlowski Tested-by: Krzysztof Kozlowski Signed-off-by: Krzysztof Kozlowski diff --git a/arch/arm/mach-exynos/pmu.c b/arch/arm/mach-exynos/pmu.c index 28b7a72..628ae09 100644 --- a/arch/arm/mach-exynos/pmu.c +++ b/arch/arm/mach-exynos/pmu.c @@ -15,6 +15,8 @@ #include #include +#include + #include "exynos-pmu.h" #include "regs-pmu.h" diff --git a/arch/arm/mach-exynos/regs-pmu.h b/arch/arm/mach-exynos/regs-pmu.h index fba9068..5e4f4c2 100644 --- a/arch/arm/mach-exynos/regs-pmu.h +++ b/arch/arm/mach-exynos/regs-pmu.h @@ -484,15 +484,6 @@ #define EXYNOS5420_SWRESET_KFC_SEL 0x3 -#include -#define MAX_CPUS_IN_CLUSTER 4 - -static inline unsigned int exynos_pmu_cpunr(unsigned int mpidr) -{ - return ((MPIDR_AFFINITY_LEVEL(mpidr, 1) * MAX_CPUS_IN_CLUSTER) - + MPIDR_AFFINITY_LEVEL(mpidr, 0)); -} - /* Only for EXYNOS5420 */ #define EXYNOS5420_ISP_ARM_OPTION 0x2488 #define EXYNOS5420_L2RSTDISABLE_VALUE BIT(3) -- cgit v0.10.2 From 937b12306ea79044c86f2e69b3061c7279245825 Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Thu, 15 Oct 2015 12:32:22 +0200 Subject: ARM: BCM5301X: remove workaround imprecise abort fault handler This is not needed anymore. Handling a potentially pending imprecise external abort left behind by the bootloader is now done in a slightly safer way inside the common ARM startup code. Signed-off-by: Lucas Stach Acked-by: Hauke Mehrtens Tested-by: Tyler Baker Signed-off-by: Florian Fainelli diff --git a/arch/arm/mach-bcm/bcm_5301x.c b/arch/arm/mach-bcm/bcm_5301x.c index 5478fe6..c8830a2 100644 --- a/arch/arm/mach-bcm/bcm_5301x.c +++ b/arch/arm/mach-bcm/bcm_5301x.c @@ -9,40 +9,6 @@ #include #include -#include -#include - - -static bool first_fault = true; - -static int bcm5301x_abort_handler(unsigned long addr, unsigned int fsr, - struct pt_regs *regs) -{ - if ((fsr == 0x1406 || fsr == 0x1c06) && first_fault) { - first_fault = false; - - /* - * These faults with codes 0x1406 (BCM4709) or 0x1c06 happens - * for no good reason, possibly left over from the CFE boot - * loader. - */ - pr_warn("External imprecise Data abort at addr=%#lx, fsr=%#x ignored.\n", - addr, fsr); - - /* Returning non-zero causes fault display and panic */ - return 0; - } - - /* Others should cause a fault */ - return 1; -} - -static void __init bcm5301x_init_early(void) -{ - /* Install our hook */ - hook_fault_code(16 + 6, bcm5301x_abort_handler, SIGBUS, BUS_OBJERR, - "imprecise external abort"); -} static const char *const bcm5301x_dt_compat[] __initconst = { "brcm,bcm4708", @@ -52,6 +18,5 @@ static const char *const bcm5301x_dt_compat[] __initconst = { DT_MACHINE_START(BCM5301X, "BCM5301X") .l2c_aux_val = 0, .l2c_aux_mask = ~0, - .init_early = bcm5301x_init_early, .dt_compat = bcm5301x_dt_compat, MACHINE_END -- cgit v0.10.2 From f4ce7effe2253a325f8ba182903cbdf0d8698593 Mon Sep 17 00:00:00 2001 From: Hauke Mehrtens Date: Sat, 21 Nov 2015 15:29:47 +0100 Subject: ARM: BCM5310X: activate erratas needed for SoC The BCM4708 I have, which is probably the first generation which got to the consumer market, is using a ARM Cortex-A9 rev r3p0 and a L2C-310 rev r3p2 L2 cache controller. There are 3 workarounds for known erratas in the Linux kernel which could be activated and will be in this patch. There are currently no workarounds which have to be activated for the L2C-310 rev r3p2 in Linux. Signed-off-by: Hauke Mehrtens Signed-off-by: Florian Fainelli diff --git a/arch/arm/mach-bcm/Kconfig b/arch/arm/mach-bcm/Kconfig index 8c53c55..c32628b 100644 --- a/arch/arm/mach-bcm/Kconfig +++ b/arch/arm/mach-bcm/Kconfig @@ -52,6 +52,10 @@ config ARCH_BCM_NSP config ARCH_BCM_5301X bool "Broadcom BCM470X / BCM5301X ARM SoC" if ARCH_MULTI_V7 select ARCH_BCM_IPROC + select ARM_ERRATA_754322 + select ARM_ERRATA_775420 + select ARM_ERRATA_764369 if SMP + help Support for Broadcom BCM470X and BCM5301X SoCs with ARM CPU cores. -- cgit v0.10.2 From 5d48417592583ec64ec62661dd7cf1bd342a48fc Mon Sep 17 00:00:00 2001 From: Nicolas Pitre Date: Sat, 21 Nov 2015 20:35:31 -0500 Subject: mach-imx/mach-imx6ul.c: proper constness with __initconst Both the pointer array and the pointed data have to be const when using __initconst to be correct. This also fixes LTO builds that otherwise fail with section mismatch errors. Signed-off-by: Nicolas Pitre Signed-off-by: Shawn Guo diff --git a/arch/arm/mach-imx/mach-imx6ul.c b/arch/arm/mach-imx/mach-imx6ul.c index acaf705..a38b16b 100644 --- a/arch/arm/mach-imx/mach-imx6ul.c +++ b/arch/arm/mach-imx/mach-imx6ul.c @@ -84,7 +84,7 @@ static void __init imx6ul_init_late(void) platform_device_register_simple("imx6q-cpufreq", -1, NULL, 0); } -static const char *imx6ul_dt_compat[] __initconst = { +static const char * const imx6ul_dt_compat[] __initconst = { "fsl,imx6ul", NULL, }; -- cgit v0.10.2 From 31a7448f4fa8a528040e3df593e9781f55218183 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Mon, 2 Nov 2015 12:14:14 +0100 Subject: ARM: OMAP: dmtimer: Add clock source from DT Add a function which sets the timer source from the clocks binding on dm_timer_prepare call. In case the clocks property is not valid, it falls back to the set_source() with 32_KHZ clock as default. Suggested-by: Tony Lindgren Signed-off-by: Neil Armstrong Signed-off-by: Tony Lindgren diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c index 8ca94d3..7c7f260 100644 --- a/arch/arm/plat-omap/dmtimer.c +++ b/arch/arm/plat-omap/dmtimer.c @@ -137,6 +137,31 @@ static int omap_dm_timer_reset(struct omap_dm_timer *timer) return 0; } +static int omap_dm_timer_of_set_source(struct omap_dm_timer *timer) +{ + int ret; + struct clk *parent; + + /* + * FIXME: OMAP1 devices do not use the clock framework for dmtimers so + * do not call clk_get() for these devices. + */ + if (!timer->fclk) + return -ENODEV; + + parent = clk_get(&timer->pdev->dev, NULL); + if (IS_ERR(parent)) + return -ENODEV; + + ret = clk_set_parent(timer->fclk, parent); + if (ret < 0) + pr_err("%s: failed to set parent\n", __func__); + + clk_put(parent); + + return ret; +} + static int omap_dm_timer_prepare(struct omap_dm_timer *timer) { int rc; @@ -166,7 +191,11 @@ static int omap_dm_timer_prepare(struct omap_dm_timer *timer) __omap_dm_timer_enable_posted(timer); omap_dm_timer_disable(timer); - return omap_dm_timer_set_source(timer, OMAP_TIMER_SRC_32_KHZ); + rc = omap_dm_timer_of_set_source(timer); + if (rc == -ENODEV) + return omap_dm_timer_set_source(timer, OMAP_TIMER_SRC_32_KHZ); + + return rc; } static inline u32 omap_dm_timer_reserved_systimer(int id) -- cgit v0.10.2 From 8c0cabd7970c0d50d53bf795b1a0f6f570b19437 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Thu, 22 Oct 2015 11:18:53 +0200 Subject: ARM: OMAP: add DT support for ti,dm816-timer Adds ti,dm816-timer to the dmtimer OF match table. Cc: Brian Hutchinson Signed-off-by: Neil Armstrong Signed-off-by: Tony Lindgren diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c index 7c7f260..1600612 100644 --- a/arch/arm/plat-omap/dmtimer.c +++ b/arch/arm/plat-omap/dmtimer.c @@ -972,6 +972,10 @@ static const struct of_device_id omap_timer_match[] = { .compatible = "ti,am335x-timer-1ms", .data = &omap3plus_pdata, }, + { + .compatible = "ti,dm816-timer", + .data = &omap3plus_pdata, + }, {}, }; MODULE_DEVICE_TABLE(of, omap_timer_match); -- cgit v0.10.2 From 1539569bc95c6b65016160af842f7fbb9085f8bb Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Thu, 22 Oct 2015 11:18:59 +0200 Subject: ARM: OMAP2+: Add hwmod spinbox support for dm816x Add dm81xx hwmod data entries for dm816x spinbox support. Cc: Brian Hutchinson Signed-off-by: Neil Armstrong Signed-off-by: Tony Lindgren diff --git a/arch/arm/mach-omap2/omap_hwmod_81xx_data.c b/arch/arm/mach-omap2/omap_hwmod_81xx_data.c index b1288f5..13dfdf6 100644 --- a/arch/arm/mach-omap2/omap_hwmod_81xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_81xx_data.c @@ -1033,6 +1033,40 @@ static struct omap_hwmod_ocp_if dm81xx_l4_ls__mailbox = { .user = OCP_USER_MPU, }; +static struct omap_hwmod_class_sysconfig dm81xx_spinbox_sysc = { + .rev_offs = 0x000, + .sysc_offs = 0x010, + .syss_offs = 0x014, + .sysc_flags = SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | + SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE, + .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART, + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class dm81xx_spinbox_hwmod_class = { + .name = "spinbox", + .sysc = &dm81xx_spinbox_sysc, +}; + +static struct omap_hwmod dm81xx_spinbox_hwmod = { + .name = "spinbox", + .clkdm_name = "alwon_l3s_clkdm", + .class = &dm81xx_spinbox_hwmod_class, + .main_clk = "sysclk6_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = DM81XX_CM_ALWON_SPINBOX_CLKCTRL, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +static struct omap_hwmod_ocp_if dm81xx_l4_ls__spinbox = { + .master = &dm81xx_l4_ls_hwmod, + .slave = &dm81xx_spinbox_hwmod, + .user = OCP_USER_MPU, +}; + static struct omap_hwmod_class dm81xx_tpcc_hwmod_class = { .name = "tpcc", }; @@ -1295,6 +1329,7 @@ static struct omap_hwmod_ocp_if *dm816x_hwmod_ocp_ifs[] __initdata = { &dm816x_l4_ls__timer7, &dm81xx_l4_ls__mcspi1, &dm81xx_l4_ls__mailbox, + &dm81xx_l4_ls__spinbox, &dm81xx_l4_hs__emac0, &dm81xx_emac0__mdio, &dm816x_l4_hs__emac1, -- cgit v0.10.2 From dd20b0d5c74bc2157a2444f5173dabdc6449aa4d Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Wed, 16 Sep 2015 18:48:19 -0500 Subject: ARM: OMAP2+: Remove legacy device instantiation of IOMMUs The legacy-style IOMMU device creation is maintained currently only for OMAP3 SoC, as all other SoCs are DT-boot only, and also to ensure functionality of the OMAP3 ISP driver, the only in-kernel client user on OMAP3 that supported both modes. Commit 78c66fbcec71 ("[media] v4l: omap3isp: Drop platform data support") removed the legacy device support from the OMAP3 ISP driver, so the legacy device instantiation of OMAP IOMMU devices is no longer needed, and is cleaned up. Signed-off-by: Suman Anna [tony@atomide.com: updated to remove also the Makefile entry] Signed-off-by: Tony Lindgren diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index ceefcee..0ba6a0e 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -223,8 +223,6 @@ obj-$(CONFIG_SOC_DRA7XX) += omap_hwmod_7xx_data.o # EMU peripherals obj-$(CONFIG_HW_PERF_EVENTS) += pmu.o -obj-$(CONFIG_OMAP_IOMMU) += omap-iommu.o - # OMAP2420 MSDI controller integration support ("MMC") obj-$(CONFIG_SOC_OMAP2420) += msdi.o diff --git a/arch/arm/mach-omap2/omap-iommu.c b/arch/arm/mach-omap2/omap-iommu.c deleted file mode 100644 index 8867eb4..0000000 --- a/arch/arm/mach-omap2/omap-iommu.c +++ /dev/null @@ -1,66 +0,0 @@ -/* - * omap iommu: omap device registration - * - * Copyright (C) 2008-2009 Nokia Corporation - * - * Written by Hiroshi DOYU - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include -#include -#include -#include - -#include -#include "soc.h" -#include "omap_hwmod.h" -#include "omap_device.h" - -static int __init omap_iommu_dev_init(struct omap_hwmod *oh, void *unused) -{ - struct platform_device *pdev; - struct iommu_platform_data *pdata; - struct omap_mmu_dev_attr *a = (struct omap_mmu_dev_attr *)oh->dev_attr; - static int i; - - pdata = kzalloc(sizeof(*pdata), GFP_KERNEL); - if (!pdata) - return -ENOMEM; - - pdata->name = oh->name; - pdata->nr_tlb_entries = a->nr_tlb_entries; - - if (oh->rst_lines_cnt == 1) { - pdata->reset_name = oh->rst_lines->name; - pdata->assert_reset = omap_device_assert_hardreset; - pdata->deassert_reset = omap_device_deassert_hardreset; - } - - pdev = omap_device_build("omap-iommu", i, oh, pdata, sizeof(*pdata)); - - kfree(pdata); - - if (IS_ERR(pdev)) { - pr_err("%s: device build err: %ld\n", __func__, PTR_ERR(pdev)); - return PTR_ERR(pdev); - } - - i++; - - return 0; -} - -static int __init omap_iommu_init(void) -{ - /* If dtb is there, the devices will be created dynamically */ - if (of_have_populated_dt()) - return -ENODEV; - - return omap_hwmod_for_each_by_class("mmu", omap_iommu_dev_init, NULL); -} -omap_subsys_initcall(omap_iommu_init); -/* must be ready before omap3isp is probed */ -- cgit v0.10.2 From 621062f49b4e72e6361b1792a510e5b056689800 Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Wed, 16 Sep 2015 18:48:20 -0500 Subject: ARM: OMAP3: hwmod data: Remove legacy IOMMU data The legacy-mode device creation logic for IOMMU devices has been cleaned up, so the device attribute data, irq information and address data are no longer required. Remove all of these data for the ISP & IVA IOMMU devices. Signed-off-by: Suman Anna [tony@atomide.com: updated to apply for the include] Signed-off-by: Tony Lindgren diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c index aff78d5..0a98532 100644 --- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c @@ -25,7 +25,6 @@ #include "l4_3xxx.h" #include #include -#include #include #include "soc.h" @@ -2957,80 +2956,40 @@ static struct omap_hwmod_class omap3xxx_mmu_hwmod_class = { }; /* mmu isp */ - -static struct omap_mmu_dev_attr mmu_isp_dev_attr = { - .nr_tlb_entries = 8, -}; - static struct omap_hwmod omap3xxx_mmu_isp_hwmod; -static struct omap_hwmod_irq_info omap3xxx_mmu_isp_irqs[] = { - { .irq = 24 + OMAP_INTC_START, }, - { .irq = -1 } -}; - -static struct omap_hwmod_addr_space omap3xxx_mmu_isp_addrs[] = { - { - .pa_start = 0x480bd400, - .pa_end = 0x480bd47f, - .flags = ADDR_TYPE_RT, - }, - { } -}; /* l4_core -> mmu isp */ static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmu_isp = { .master = &omap3xxx_l4_core_hwmod, .slave = &omap3xxx_mmu_isp_hwmod, - .addr = omap3xxx_mmu_isp_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; static struct omap_hwmod omap3xxx_mmu_isp_hwmod = { .name = "mmu_isp", .class = &omap3xxx_mmu_hwmod_class, - .mpu_irqs = omap3xxx_mmu_isp_irqs, .main_clk = "cam_ick", - .dev_attr = &mmu_isp_dev_attr, .flags = HWMOD_NO_IDLEST, }; /* mmu iva */ -static struct omap_mmu_dev_attr mmu_iva_dev_attr = { - .nr_tlb_entries = 32, -}; - static struct omap_hwmod omap3xxx_mmu_iva_hwmod; -static struct omap_hwmod_irq_info omap3xxx_mmu_iva_irqs[] = { - { .irq = 28 + OMAP_INTC_START, }, - { .irq = -1 } -}; static struct omap_hwmod_rst_info omap3xxx_mmu_iva_resets[] = { { .name = "mmu", .rst_shift = 1, .st_shift = 9 }, }; -static struct omap_hwmod_addr_space omap3xxx_mmu_iva_addrs[] = { - { - .pa_start = 0x5d000000, - .pa_end = 0x5d00007f, - .flags = ADDR_TYPE_RT, - }, - { } -}; - /* l3_main -> iva mmu */ static struct omap_hwmod_ocp_if omap3xxx_l3_main__mmu_iva = { .master = &omap3xxx_l3_main_hwmod, .slave = &omap3xxx_mmu_iva_hwmod, - .addr = omap3xxx_mmu_iva_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; static struct omap_hwmod omap3xxx_mmu_iva_hwmod = { .name = "mmu_iva", .class = &omap3xxx_mmu_hwmod_class, - .mpu_irqs = omap3xxx_mmu_iva_irqs, .clkdm_name = "iva2_clkdm", .rst_lines = omap3xxx_mmu_iva_resets, .rst_lines_cnt = ARRAY_SIZE(omap3xxx_mmu_iva_resets), @@ -3043,7 +3002,6 @@ static struct omap_hwmod omap3xxx_mmu_iva_hwmod = { .idlest_idle_bit = OMAP3430_ST_IVA2_SHIFT, }, }, - .dev_attr = &mmu_iva_dev_attr, .flags = HWMOD_NO_IDLEST, }; -- cgit v0.10.2 From 1ad0ea0c6575e355d42397f65e70d3b83eb9742e Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Wed, 16 Sep 2015 18:48:21 -0500 Subject: ARM: OMAP4: hwmod data: Remove legacy IOMMU attr and addrs OMAP4 has been DT-boot only for some time, and the legacy-mode device creation logic for IOMMU devices has also been cleaned up, so the dev_attr and address data is no longer required. So, remove these attribute data and hwmod addr space for the IPU & DSP IOMMU devices. Signed-off-by: Suman Anna Signed-off-by: Tony Lindgren diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c index a5e444b..01fb60b 100644 --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c @@ -30,7 +30,6 @@ #include #include -#include #include #include "omap_hwmod.h" @@ -2088,30 +2087,16 @@ static struct omap_hwmod_class omap44xx_mmu_hwmod_class = { /* mmu ipu */ -static struct omap_mmu_dev_attr mmu_ipu_dev_attr = { - .nr_tlb_entries = 32, -}; - static struct omap_hwmod omap44xx_mmu_ipu_hwmod; static struct omap_hwmod_rst_info omap44xx_mmu_ipu_resets[] = { { .name = "mmu_cache", .rst_shift = 2 }, }; -static struct omap_hwmod_addr_space omap44xx_mmu_ipu_addrs[] = { - { - .pa_start = 0x55082000, - .pa_end = 0x550820ff, - .flags = ADDR_TYPE_RT, - }, - { } -}; - /* l3_main_2 -> mmu_ipu */ static struct omap_hwmod_ocp_if omap44xx_l3_main_2__mmu_ipu = { .master = &omap44xx_l3_main_2_hwmod, .slave = &omap44xx_mmu_ipu_hwmod, .clk = "l3_div_ck", - .addr = omap44xx_mmu_ipu_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; @@ -2130,35 +2115,20 @@ static struct omap_hwmod omap44xx_mmu_ipu_hwmod = { .modulemode = MODULEMODE_HWCTRL, }, }, - .dev_attr = &mmu_ipu_dev_attr, }; /* mmu dsp */ -static struct omap_mmu_dev_attr mmu_dsp_dev_attr = { - .nr_tlb_entries = 32, -}; - static struct omap_hwmod omap44xx_mmu_dsp_hwmod; static struct omap_hwmod_rst_info omap44xx_mmu_dsp_resets[] = { { .name = "mmu_cache", .rst_shift = 1 }, }; -static struct omap_hwmod_addr_space omap44xx_mmu_dsp_addrs[] = { - { - .pa_start = 0x4a066000, - .pa_end = 0x4a0660ff, - .flags = ADDR_TYPE_RT, - }, - { } -}; - /* l4_cfg -> dsp */ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mmu_dsp = { .master = &omap44xx_l4_cfg_hwmod, .slave = &omap44xx_mmu_dsp_hwmod, .clk = "l4_div_ck", - .addr = omap44xx_mmu_dsp_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; @@ -2177,7 +2147,6 @@ static struct omap_hwmod omap44xx_mmu_dsp_hwmod = { .modulemode = MODULEMODE_HWCTRL, }, }, - .dev_attr = &mmu_dsp_dev_attr, }; /* -- cgit v0.10.2 From b6a89194182fe7a33d383463b8b9af6e117d8146 Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Wed, 16 Sep 2015 18:48:22 -0500 Subject: ARM: OMAP2+: Remove omap_mmu_dev_attr structure The structure omap_mmu_dev_attr was used in the hwmod data for supplying device-specific data through the .dev_attr field and used in constructing the platform data for legacy device creation. The legacy device creation of OMAP IOMMU devices has been cleaned up, and this structure is no longer needed, so remove it. Signed-off-by: Suman Anna Signed-off-by: Tony Lindgren diff --git a/include/linux/platform_data/iommu-omap.h b/include/linux/platform_data/iommu-omap.h index 54a0a95..0496d17 100644 --- a/include/linux/platform_data/iommu-omap.h +++ b/include/linux/platform_data/iommu-omap.h @@ -29,15 +29,6 @@ struct omap_iommu_arch_data { struct omap_iommu *iommu_dev; }; -/** - * struct omap_mmu_dev_attr - OMAP mmu device attributes for omap_hwmod - * @nr_tlb_entries: number of entries supported by the translation - * look-aside buffer (TLB). - */ -struct omap_mmu_dev_attr { - int nr_tlb_entries; -}; - struct iommu_platform_data { const char *name; const char *reset_name; -- cgit v0.10.2 From ea05d2eaf66543e1305a6eb0f1a46db1257731c4 Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Mon, 5 Oct 2015 18:28:21 -0500 Subject: ARM: OMAP: dmtimer: check for fixed timers during config The omap_dm_timer_set_source() function provides a means for client users to configure the mux parent for a GPTimer's functional clock. However, not all timers are configurable (Eg: Timer12 on DRA7 is fed by an internal 32k oscillator clock, and does not have configurable parent clocks). So, check for such cases and proceed with out throwing an error. Signed-off-by: Suman Anna Signed-off-by: Tony Lindgren diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c index 1600612..7a327bd 100644 --- a/arch/arm/plat-omap/dmtimer.c +++ b/arch/arm/plat-omap/dmtimer.c @@ -36,6 +36,7 @@ */ #include +#include #include #include #include @@ -533,6 +534,12 @@ int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source) if (IS_ERR(timer->fclk)) return -EINVAL; +#if defined(CONFIG_COMMON_CLK) + /* Check if the clock has configurable parents */ + if (clk_hw_get_num_parents(__clk_get_hw(timer->fclk)) < 2) + return 0; +#endif + switch (source) { case OMAP_TIMER_SRC_SYS_CLK: parent_name = "timer_sys_ck"; -- cgit v0.10.2 From ed5a4c6248a9e842d691dd3660b9f79be846693f Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Mon, 5 Oct 2015 18:28:22 -0500 Subject: ARM: OMAP2+: timer: Remove secure timer for DRA7xx HS devices Timer 12 on DRA7 SoCs is reserved for secure usage on high-secure (HS) devices. The timer cannot be used by the kernel on HS devices, but is available on regular general purpose (GP) devices. This is similar to the behavior on OMAP3 devices, so extend the logic used in commit ad24bde8f102 ("ARM: OMAP3: Dynamically disable secure timer nodes for secure devices") to remove the secure timer on DRA7xx SoCs at run-time based on the SoC device type. Signed-off-by: Suman Anna Signed-off-by: Tony Lindgren diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c index b18ebbe..6c19d1e 100644 --- a/arch/arm/mach-omap2/timer.c +++ b/arch/arm/mach-omap2/timer.c @@ -194,8 +194,8 @@ static struct device_node * __init omap_get_timer_dt(const struct of_device_id * /** * omap_dmtimer_init - initialisation function when device tree is used * - * For secure OMAP3 devices, timers with device type "timer-secure" cannot - * be used by the kernel as they are reserved. Therefore, to prevent the + * For secure OMAP3/DRA7xx devices, timers with device type "timer-secure" + * cannot be used by the kernel as they are reserved. Therefore, to prevent the * kernel registering these devices remove them dynamically from the device * tree on boot. */ @@ -203,7 +203,7 @@ static void __init omap_dmtimer_init(void) { struct device_node *np; - if (!cpu_is_omap34xx()) + if (!cpu_is_omap34xx() && !soc_is_dra7xx()) return; /* If we are a secure device, remove any secure timer nodes */ -- cgit v0.10.2 From c9fbaa4997c0e6ff2d454abc667a33142ffcff66 Mon Sep 17 00:00:00 2001 From: Franklin S Cooper Jr Date: Wed, 28 Oct 2015 16:02:17 -0500 Subject: ARM: omap4: hwmod: Remove elm address space from hwmod data ELM address information is provided by device tree. No longer need to include this information within hwmod. This patch has only been boot tested. Signed-off-by: Franklin S Cooper Jr Signed-off-by: Tony Lindgren diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c index 01fb60b..dad871a 100644 --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c @@ -3884,21 +3884,11 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = { .user = OCP_USER_MPU, }; -static struct omap_hwmod_addr_space omap44xx_elm_addrs[] = { - { - .pa_start = 0x48078000, - .pa_end = 0x48078fff, - .flags = ADDR_TYPE_RT - }, - { } -}; - /* l4_per -> elm */ static struct omap_hwmod_ocp_if omap44xx_l4_per__elm = { .master = &omap44xx_l4_per_hwmod, .slave = &omap44xx_elm_hwmod, .clk = "l4_div_ck", - .addr = omap44xx_elm_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; -- cgit v0.10.2 From 448f8bc69f3f74e2ecd143ef9c774851fc70d347 Mon Sep 17 00:00:00 2001 From: Aaro Koskinen Date: Mon, 23 Nov 2015 23:32:57 +0200 Subject: ARM: OMAP: RX-51: fix a typo in log writing Fix a typo when registering HW RNG. Signed-off-by: Aaro Koskinen Signed-off-by: Tony Lindgren diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c index 14edcd7..ff1520b 100644 --- a/arch/arm/mach-omap2/board-rx51-peripherals.c +++ b/arch/arm/mach-omap2/board-rx51-peripherals.c @@ -1257,7 +1257,7 @@ static struct platform_device omap3_rom_rng_device = { static void __init rx51_init_omap3_rom_rng(void) { if (omap_type() == OMAP2_DEVICE_TYPE_SEC) { - pr_info("RX-51: Registring OMAP3 HWRNG device\n"); + pr_info("RX-51: Registering OMAP3 HWRNG device\n"); platform_device_register(&omap3_rom_rng_device); } } diff --git a/arch/arm/mach-omap2/pdata-quirks.c b/arch/arm/mach-omap2/pdata-quirks.c index 1dfe346..35ea6c0 100644 --- a/arch/arm/mach-omap2/pdata-quirks.c +++ b/arch/arm/mach-omap2/pdata-quirks.c @@ -268,7 +268,7 @@ static void __init nokia_n900_legacy_init(void) pr_warn("Thumb binaries may crash randomly without this workaround\n"); } - pr_info("RX-51: Registring OMAP3 HWRNG device\n"); + pr_info("RX-51: Registering OMAP3 HWRNG device\n"); platform_device_register(&omap3_rom_rng_device); } -- cgit v0.10.2 From b03408500e60a5f8142a1ba73949e523c059c265 Mon Sep 17 00:00:00 2001 From: "J.D. Schroeder" Date: Thu, 22 Oct 2015 19:24:16 -0500 Subject: ARM: DRA7: hwmod: Enable DEBUG_LL for UART4 UART4 low level debug support. This helps in debugging with UART4 serial console output on DRA7 based platforms. Extending the following fix for UART4. commit 1c7e36bfc3e2 ("ARM: DRA7: hwmod: Fix boot crash with DEBUG_LL enabled on UART3") For using DEBUG_LL, enable CONFIG_DEBUG_OMAP4UART4 in menuconfig. On DRA7, UART4 hwmod doesn't have this flag enabled, failure observed when UART4 is used for low level debugging. Hence, Enable DEBUG_OMAP4UART4_FLAGS for UART4 hwmod. Signed-off-by: J.D. Schroeder Signed-off-by: Praneeth Bajjuri Signed-off-by: Tony Lindgren diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c index 51d1ecb..1b4c500 100644 --- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c @@ -2065,7 +2065,7 @@ static struct omap_hwmod dra7xx_uart4_hwmod = { .class = &dra7xx_uart_hwmod_class, .clkdm_name = "l4per_clkdm", .main_clk = "uart4_gfclk_mux", - .flags = HWMOD_SWSUP_SIDLE_ACT, + .flags = HWMOD_SWSUP_SIDLE_ACT | DEBUG_OMAP4UART4_FLAGS, .prcm = { .omap4 = { .clkctrl_offs = DRA7XX_CM_L4PER_UART4_CLKCTRL_OFFSET, -- cgit v0.10.2 From e3526f004a35e5f324b1c835bca056f4df05bff0 Mon Sep 17 00:00:00 2001 From: Bai Ping Date: Tue, 24 Nov 2015 18:25:16 +0800 Subject: ARM: imx: enable cpufreq device on i.mx7d Add a cpufreq-dt device on i.MX7D, using the generic cpufreq-dt for CPU frequency scaling. Signed-off-by: Bai Ping Acked-by: Lucas Stach Signed-off-by: Shawn Guo diff --git a/arch/arm/mach-imx/mach-imx7d.c b/arch/arm/mach-imx/mach-imx7d.c index b450f52..5a27f20 100644 --- a/arch/arm/mach-imx/mach-imx7d.c +++ b/arch/arm/mach-imx/mach-imx7d.c @@ -105,6 +105,11 @@ static void __init imx7d_init_irq(void) irqchip_init(); } +static void __init imx7d_init_late(void) +{ + platform_device_register_simple("cpufreq-dt", -1, NULL, 0); +} + static const char *const imx7d_dt_compat[] __initconst = { "fsl,imx7d", NULL, @@ -112,6 +117,7 @@ static const char *const imx7d_dt_compat[] __initconst = { DT_MACHINE_START(IMX7D, "Freescale i.MX7 Dual (Device Tree)") .init_irq = imx7d_init_irq, + .init_late = imx7d_init_late, .init_machine = imx7d_init_machine, .dt_compat = imx7d_dt_compat, MACHINE_END -- cgit v0.10.2 From aa9fff5dcc7721b78f9915c9ce614c1297d4182c Mon Sep 17 00:00:00 2001 From: Colin Ian King Date: Sat, 28 Nov 2015 16:27:34 +0000 Subject: ARM: mach-imx: iomux-imx31: fix spelling mistake in error message Minor issue, fix spelling mistake, nonexistant -> nonexistent Signed-off-by: Colin Ian King Signed-off-by: Shawn Guo diff --git a/arch/arm/mach-imx/iomux-imx31.c b/arch/arm/mach-imx/iomux-imx31.c index 6dd22ca..0b5ba4b 100644 --- a/arch/arm/mach-imx/iomux-imx31.c +++ b/arch/arm/mach-imx/iomux-imx31.c @@ -100,7 +100,7 @@ int mxc_iomux_alloc_pin(unsigned int pin, const char *label) unsigned pad = pin & IOMUX_PADNUM_MASK; if (pad >= (PIN_MAX + 1)) { - printk(KERN_ERR "mxc_iomux: Attempt to request nonexistant pin %u for \"%s\"\n", + printk(KERN_ERR "mxc_iomux: Attempt to request nonexistent pin %u for \"%s\"\n", pad, label ? label : "?"); return -EINVAL; } -- cgit v0.10.2 From 8dd5ea72b0c0dbcdb5d629247ac7ead49c6a9c58 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Thu, 3 Dec 2015 11:38:09 -0800 Subject: ARM: OMAP2+: Change core_initcall levels to postcore_initcall We want to be able to probe a few selected device drivers before hwmod code populates the clocks in omap_hwmod_setup_all(). This allows us to convert most of the clock drivers into regular device drivers. We only need a few minimal clock drivers early for the system timers to select between the 32KiHz clock and the high frequency oscillator. With these changes, initializing the clock drivers can be just done at core_initcall time with something like: np = of_find_node_by_name(NULL, "plls"); if (np) of_platform_populate(np, NULL, NULL, NULL); And then these clocks will be available for the interconnect code to use. Having most of the clock drivers being regular device drivers allows us to use the nice things like devm_* functions and dev_err and dev_dbg. As an extra bonus, this also allows us to develop the clock drivers for new SoCs as loadable modules initially for cases where we can boot up the system based on the bootloader configured clocks. To do this, let's change the core_initcalls to postcore_initcall under mach-omap2. Cc: Felipe Balbi Cc: Grygorii Strashko Cc: Paul Walmsley Cc: Tero Kristo Signed-off-by: Tony Lindgren diff --git a/arch/arm/mach-omap2/omap2-restart.c b/arch/arm/mach-omap2/omap2-restart.c index d937b2e..497269d 100644 --- a/arch/arm/mach-omap2/omap2-restart.c +++ b/arch/arm/mach-omap2/omap2-restart.c @@ -62,4 +62,4 @@ static int __init omap2xxx_common_look_up_clks_for_reset(void) return 0; } -omap_core_initcall(omap2xxx_common_look_up_clks_for_reset); +omap_postcore_initcall(omap2xxx_common_look_up_clks_for_reset); diff --git a/arch/arm/mach-omap2/omap_device.c b/arch/arm/mach-omap2/omap_device.c index 72ebc4c..3750ed1 100644 --- a/arch/arm/mach-omap2/omap_device.c +++ b/arch/arm/mach-omap2/omap_device.c @@ -869,7 +869,7 @@ static int __init omap_device_init(void) bus_register_notifier(&platform_bus_type, &platform_nb); return 0; } -omap_core_initcall(omap_device_init); +omap_postcore_initcall(omap_device_init); /** * omap_device_late_idle - idle devices without drivers diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c index cc8a987..49d5376 100644 --- a/arch/arm/mach-omap2/omap_hwmod.c +++ b/arch/arm/mach-omap2/omap_hwmod.c @@ -3307,7 +3307,7 @@ static int __init omap_hwmod_setup_all(void) return 0; } -omap_core_initcall(omap_hwmod_setup_all); +omap_postcore_initcall(omap_hwmod_setup_all); /** * omap_hwmod_enable - enable an omap_hwmod diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c index 5fb50fe..f164c6b 100644 --- a/arch/arm/mach-omap2/serial.c +++ b/arch/arm/mach-omap2/serial.c @@ -213,7 +213,7 @@ static int __init omap_serial_early_init(void) return 0; } -omap_core_initcall(omap_serial_early_init); +omap_postcore_initcall(omap_serial_early_init); /** * omap_serial_init_port() - initialize single serial port -- cgit v0.10.2 From 84320e1a635fcf90cff4185f029ce9e31bf1d4a7 Mon Sep 17 00:00:00 2001 From: Kapil Hali Date: Tue, 1 Dec 2015 11:24:06 -0500 Subject: ARM: BCM: Clean up SMP support for Broadcom Kona These changes cleans up SMP implementaion for Broadcom's Kona SoC which are required for handling SMP for iProc family of SoCs at a single place for BCM NSP and BCM Kona. Signed-off-by: Kapil Hali Acked-by: Rob Herring Signed-off-by: Florian Fainelli diff --git a/arch/arm/boot/dts/bcm11351.dtsi b/arch/arm/boot/dts/bcm11351.dtsi index 2ddaa51..3dc7a8c 100644 --- a/arch/arm/boot/dts/bcm11351.dtsi +++ b/arch/arm/boot/dts/bcm11351.dtsi @@ -31,7 +31,6 @@ #address-cells = <1>; #size-cells = <0>; enable-method = "brcm,bcm11351-cpu-method"; - secondary-boot-reg = <0x3500417c>; cpu0: cpu@0 { device_type = "cpu"; @@ -42,6 +41,7 @@ cpu1: cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a9"; + secondary-boot-reg = <0x3500417c>; reg = <1>; }; }; diff --git a/arch/arm/boot/dts/bcm21664.dtsi b/arch/arm/boot/dts/bcm21664.dtsi index 2016b72..3f525be 100644 --- a/arch/arm/boot/dts/bcm21664.dtsi +++ b/arch/arm/boot/dts/bcm21664.dtsi @@ -31,7 +31,6 @@ #address-cells = <1>; #size-cells = <0>; enable-method = "brcm,bcm11351-cpu-method"; - secondary-boot-reg = <0x35004178>; cpu0: cpu@0 { device_type = "cpu"; @@ -42,6 +41,7 @@ cpu1: cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a9"; + secondary-boot-reg = <0x35004178>; reg = <1>; }; }; diff --git a/arch/arm/mach-bcm/kona_smp.c b/arch/arm/mach-bcm/kona_smp.c index 66a0465..15af781 100644 --- a/arch/arm/mach-bcm/kona_smp.c +++ b/arch/arm/mach-bcm/kona_smp.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2014 Broadcom Corporation + * Copyright (C) 2014-2015 Broadcom Corporation * Copyright 2014 Linaro Limited * * This program is free software; you can redistribute it and/or @@ -30,9 +30,10 @@ /* Name of device node property defining secondary boot register location */ #define OF_SECONDARY_BOOT "secondary-boot-reg" +#define MPIDR_CPUID_BITMASK 0x3 /* I/O address of register used to coordinate secondary core startup */ -static u32 secondary_boot; +static u32 secondary_boot_addr; /* * Enable the Cortex A9 Snoop Control Unit @@ -78,44 +79,68 @@ static int __init scu_a9_enable(void) static void __init bcm_smp_prepare_cpus(unsigned int max_cpus) { static cpumask_t only_cpu_0 = { CPU_BITS_CPU0 }; - struct device_node *node; + struct device_node *cpus_node = NULL; + struct device_node *cpu_node = NULL; int ret; - BUG_ON(secondary_boot); /* We're called only once */ - /* * This function is only called via smp_ops->smp_prepare_cpu(). * That only happens if a "/cpus" device tree node exists * and has an "enable-method" property that selects the SMP * operations defined herein. */ - node = of_find_node_by_path("/cpus"); - BUG_ON(!node); - - /* - * Our secondary enable method requires a "secondary-boot-reg" - * property to specify a register address used to request the - * ROM code boot a secondary code. If we have any trouble - * getting this we fall back to uniprocessor mode. - */ - if (of_property_read_u32(node, OF_SECONDARY_BOOT, &secondary_boot)) { - pr_err("%s: missing/invalid " OF_SECONDARY_BOOT " property\n", - node->name); - ret = -ENOENT; /* Arrange to disable SMP */ - goto out; + cpus_node = of_find_node_by_path("/cpus"); + if (!cpus_node) + return; + + for_each_child_of_node(cpus_node, cpu_node) { + u32 cpuid; + + if (of_node_cmp(cpu_node->type, "cpu")) + continue; + + if (of_property_read_u32(cpu_node, "reg", &cpuid)) { + pr_debug("%s: missing reg property\n", + cpu_node->full_name); + ret = -ENOENT; + goto out; + } + + /* + * "secondary-boot-reg" property should be defined only + * for secondary cpu + */ + if ((cpuid & MPIDR_CPUID_BITMASK) == 1) { + /* + * Our secondary enable method requires a + * "secondary-boot-reg" property to specify a register + * address used to request the ROM code boot a secondary + * core. If we have any trouble getting this we fall + * back to uniprocessor mode. + */ + if (of_property_read_u32(cpu_node, + OF_SECONDARY_BOOT, + &secondary_boot_addr)) { + pr_warn("%s: no" OF_SECONDARY_BOOT "property\n", + cpu_node->name); + ret = -ENOENT; + goto out; + } + } } /* - * Enable the SCU on Cortex A9 based SoCs. If -ENOENT is + * Enable the SCU on Cortex A9 based SoCs. If -ENOENT is * returned, the SoC reported a uniprocessor configuration. * We bail on any other error. */ ret = scu_a9_enable(); out: - of_node_put(node); + of_node_put(cpu_node); + of_node_put(cpus_node); + if (ret) { /* Update the CPU present map to reflect uniprocessor mode */ - BUG_ON(ret != -ENOENT); pr_warn("disabling SMP\n"); init_cpu_present(&only_cpu_0); } @@ -139,7 +164,7 @@ out: * - Wait for the secondary boot register to be re-written, which * indicates the secondary core has started. */ -static int bcm_boot_secondary(unsigned int cpu, struct task_struct *idle) +static int kona_boot_secondary(unsigned int cpu, struct task_struct *idle) { void __iomem *boot_reg; phys_addr_t boot_func; @@ -154,15 +179,16 @@ static int bcm_boot_secondary(unsigned int cpu, struct task_struct *idle) return -EINVAL; } - if (!secondary_boot) { + if (!secondary_boot_addr) { pr_err("required secondary boot register not specified\n"); return -EINVAL; } - boot_reg = ioremap_nocache((phys_addr_t)secondary_boot, sizeof(u32)); + boot_reg = ioremap_nocache( + (phys_addr_t)secondary_boot_addr, sizeof(u32)); if (!boot_reg) { pr_err("unable to map boot register for cpu %u\n", cpu_id); - return -ENOSYS; + return -ENOMEM; } /* @@ -191,12 +217,12 @@ static int bcm_boot_secondary(unsigned int cpu, struct task_struct *idle) pr_err("timeout waiting for cpu %u to start\n", cpu_id); - return -ENOSYS; + return -ENXIO; } static struct smp_operations bcm_smp_ops __initdata = { .smp_prepare_cpus = bcm_smp_prepare_cpus, - .smp_boot_secondary = bcm_boot_secondary, + .smp_boot_secondary = kona_boot_secondary, }; CPU_METHOD_OF_DECLARE(bcm_smp_bcm281xx, "brcm,bcm11351-cpu-method", &bcm_smp_ops); -- cgit v0.10.2 From 97890821bb58dea522f823d8db396f9c17c6e356 Mon Sep 17 00:00:00 2001 From: Kapil Hali Date: Tue, 1 Dec 2015 11:24:08 -0500 Subject: ARM: BCM: Add SMP support for Broadcom NSP Add SMP support for Broadcom's Northstar Plus SoC cpu enable method. This changes also consolidates iProc family's - BCM NSP and BCM Kona, platform SMP handling in a common file. Northstar Plus SoC is based on ARM Cortex-A9 revision r3p0 which requires configuration for ARM Errata 764369 for SMP. This change adds the needed configuration option. Signed-off-by: Kapil Hali Signed-off-by: Florian Fainelli diff --git a/arch/arm/mach-bcm/Kconfig b/arch/arm/mach-bcm/Kconfig index c32628b..6e3e043 100644 --- a/arch/arm/mach-bcm/Kconfig +++ b/arch/arm/mach-bcm/Kconfig @@ -40,6 +40,8 @@ config ARCH_BCM_NSP select ARCH_BCM_IPROC select ARM_ERRATA_754322 select ARM_ERRATA_775420 + select ARM_ERRATA_764369 if SMP + select HAVE_SMP help Support for Broadcom Northstar Plus SoC. Broadcom Northstar Plus family of SoCs are used for switching control diff --git a/arch/arm/mach-bcm/Makefile b/arch/arm/mach-bcm/Makefile index 892261f..5193a25 100644 --- a/arch/arm/mach-bcm/Makefile +++ b/arch/arm/mach-bcm/Makefile @@ -14,7 +14,11 @@ obj-$(CONFIG_ARCH_BCM_CYGNUS) += bcm_cygnus.o # Northstar Plus -obj-$(CONFIG_ARCH_BCM_NSP) += bcm_nsp.o +obj-$(CONFIG_ARCH_BCM_NSP) += bcm_nsp.o + +ifeq ($(CONFIG_ARCH_BCM_NSP),y) +obj-$(CONFIG_SMP) += platsmp.o +endif # BCM281XX obj-$(CONFIG_ARCH_BCM_281XX) += board_bcm281xx.o @@ -23,7 +27,7 @@ obj-$(CONFIG_ARCH_BCM_281XX) += board_bcm281xx.o obj-$(CONFIG_ARCH_BCM_21664) += board_bcm21664.o # BCM281XX and BCM21664 SMP support -obj-$(CONFIG_ARCH_BCM_MOBILE_SMP) += kona_smp.o +obj-$(CONFIG_ARCH_BCM_MOBILE_SMP) += platsmp.o # BCM281XX and BCM21664 L2 cache control obj-$(CONFIG_ARCH_BCM_MOBILE_L2_CACHE) += kona_l2_cache.o diff --git a/arch/arm/mach-bcm/kona_smp.c b/arch/arm/mach-bcm/kona_smp.c deleted file mode 100644 index 15af781..0000000 --- a/arch/arm/mach-bcm/kona_smp.c +++ /dev/null @@ -1,228 +0,0 @@ -/* - * Copyright (C) 2014-2015 Broadcom Corporation - * Copyright 2014 Linaro Limited - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation version 2. - * - * This program is distributed "as is" WITHOUT ANY WARRANTY of any - * kind, whether express or implied; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include - -#include -#include -#include - -/* Size of mapped Cortex A9 SCU address space */ -#define CORTEX_A9_SCU_SIZE 0x58 - -#define SECONDARY_TIMEOUT_NS NSEC_PER_MSEC /* 1 msec (in nanoseconds) */ -#define BOOT_ADDR_CPUID_MASK 0x3 - -/* Name of device node property defining secondary boot register location */ -#define OF_SECONDARY_BOOT "secondary-boot-reg" -#define MPIDR_CPUID_BITMASK 0x3 - -/* I/O address of register used to coordinate secondary core startup */ -static u32 secondary_boot_addr; - -/* - * Enable the Cortex A9 Snoop Control Unit - * - * By the time this is called we already know there are multiple - * cores present. We assume we're running on a Cortex A9 processor, - * so any trouble getting the base address register or getting the - * SCU base is a problem. - * - * Return 0 if successful or an error code otherwise. - */ -static int __init scu_a9_enable(void) -{ - unsigned long config_base; - void __iomem *scu_base; - - if (!scu_a9_has_base()) { - pr_err("no configuration base address register!\n"); - return -ENXIO; - } - - /* Config base address register value is zero for uniprocessor */ - config_base = scu_a9_get_base(); - if (!config_base) { - pr_err("hardware reports only one core\n"); - return -ENOENT; - } - - scu_base = ioremap((phys_addr_t)config_base, CORTEX_A9_SCU_SIZE); - if (!scu_base) { - pr_err("failed to remap config base (%lu/%u) for SCU\n", - config_base, CORTEX_A9_SCU_SIZE); - return -ENOMEM; - } - - scu_enable(scu_base); - - iounmap(scu_base); /* That's the last we'll need of this */ - - return 0; -} - -static void __init bcm_smp_prepare_cpus(unsigned int max_cpus) -{ - static cpumask_t only_cpu_0 = { CPU_BITS_CPU0 }; - struct device_node *cpus_node = NULL; - struct device_node *cpu_node = NULL; - int ret; - - /* - * This function is only called via smp_ops->smp_prepare_cpu(). - * That only happens if a "/cpus" device tree node exists - * and has an "enable-method" property that selects the SMP - * operations defined herein. - */ - cpus_node = of_find_node_by_path("/cpus"); - if (!cpus_node) - return; - - for_each_child_of_node(cpus_node, cpu_node) { - u32 cpuid; - - if (of_node_cmp(cpu_node->type, "cpu")) - continue; - - if (of_property_read_u32(cpu_node, "reg", &cpuid)) { - pr_debug("%s: missing reg property\n", - cpu_node->full_name); - ret = -ENOENT; - goto out; - } - - /* - * "secondary-boot-reg" property should be defined only - * for secondary cpu - */ - if ((cpuid & MPIDR_CPUID_BITMASK) == 1) { - /* - * Our secondary enable method requires a - * "secondary-boot-reg" property to specify a register - * address used to request the ROM code boot a secondary - * core. If we have any trouble getting this we fall - * back to uniprocessor mode. - */ - if (of_property_read_u32(cpu_node, - OF_SECONDARY_BOOT, - &secondary_boot_addr)) { - pr_warn("%s: no" OF_SECONDARY_BOOT "property\n", - cpu_node->name); - ret = -ENOENT; - goto out; - } - } - } - - /* - * Enable the SCU on Cortex A9 based SoCs. If -ENOENT is - * returned, the SoC reported a uniprocessor configuration. - * We bail on any other error. - */ - ret = scu_a9_enable(); -out: - of_node_put(cpu_node); - of_node_put(cpus_node); - - if (ret) { - /* Update the CPU present map to reflect uniprocessor mode */ - pr_warn("disabling SMP\n"); - init_cpu_present(&only_cpu_0); - } -} - -/* - * The ROM code has the secondary cores looping, waiting for an event. - * When an event occurs each core examines the bottom two bits of the - * secondary boot register. When a core finds those bits contain its - * own core id, it performs initialization, including computing its boot - * address by clearing the boot register value's bottom two bits. The - * core signals that it is beginning its execution by writing its boot - * address back to the secondary boot register, and finally jumps to - * that address. - * - * So to start a core executing we need to: - * - Encode the (hardware) CPU id with the bottom bits of the secondary - * start address. - * - Write that value into the secondary boot register. - * - Generate an event to wake up the secondary CPU(s). - * - Wait for the secondary boot register to be re-written, which - * indicates the secondary core has started. - */ -static int kona_boot_secondary(unsigned int cpu, struct task_struct *idle) -{ - void __iomem *boot_reg; - phys_addr_t boot_func; - u64 start_clock; - u32 cpu_id; - u32 boot_val; - bool timeout = false; - - cpu_id = cpu_logical_map(cpu); - if (cpu_id & ~BOOT_ADDR_CPUID_MASK) { - pr_err("bad cpu id (%u > %u)\n", cpu_id, BOOT_ADDR_CPUID_MASK); - return -EINVAL; - } - - if (!secondary_boot_addr) { - pr_err("required secondary boot register not specified\n"); - return -EINVAL; - } - - boot_reg = ioremap_nocache( - (phys_addr_t)secondary_boot_addr, sizeof(u32)); - if (!boot_reg) { - pr_err("unable to map boot register for cpu %u\n", cpu_id); - return -ENOMEM; - } - - /* - * Secondary cores will start in secondary_startup(), - * defined in "arch/arm/kernel/head.S" - */ - boot_func = virt_to_phys(secondary_startup); - BUG_ON(boot_func & BOOT_ADDR_CPUID_MASK); - BUG_ON(boot_func > (phys_addr_t)U32_MAX); - - /* The core to start is encoded in the low bits */ - boot_val = (u32)boot_func | cpu_id; - writel_relaxed(boot_val, boot_reg); - - sev(); - - /* The low bits will be cleared once the core has started */ - start_clock = local_clock(); - while (!timeout && readl_relaxed(boot_reg) == boot_val) - timeout = local_clock() - start_clock > SECONDARY_TIMEOUT_NS; - - iounmap(boot_reg); - - if (!timeout) - return 0; - - pr_err("timeout waiting for cpu %u to start\n", cpu_id); - - return -ENXIO; -} - -static struct smp_operations bcm_smp_ops __initdata = { - .smp_prepare_cpus = bcm_smp_prepare_cpus, - .smp_boot_secondary = kona_boot_secondary, -}; -CPU_METHOD_OF_DECLARE(bcm_smp_bcm281xx, "brcm,bcm11351-cpu-method", - &bcm_smp_ops); diff --git a/arch/arm/mach-bcm/platsmp.c b/arch/arm/mach-bcm/platsmp.c new file mode 100644 index 0000000..ea4201e --- /dev/null +++ b/arch/arm/mach-bcm/platsmp.c @@ -0,0 +1,290 @@ +/* + * Copyright (C) 2014-2015 Broadcom Corporation + * Copyright 2014 Linaro Limited + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +/* Size of mapped Cortex A9 SCU address space */ +#define CORTEX_A9_SCU_SIZE 0x58 + +#define SECONDARY_TIMEOUT_NS NSEC_PER_MSEC /* 1 msec (in nanoseconds) */ +#define BOOT_ADDR_CPUID_MASK 0x3 + +/* Name of device node property defining secondary boot register location */ +#define OF_SECONDARY_BOOT "secondary-boot-reg" +#define MPIDR_CPUID_BITMASK 0x3 + +/* I/O address of register used to coordinate secondary core startup */ +static u32 secondary_boot_addr; + +/* + * Enable the Cortex A9 Snoop Control Unit + * + * By the time this is called we already know there are multiple + * cores present. We assume we're running on a Cortex A9 processor, + * so any trouble getting the base address register or getting the + * SCU base is a problem. + * + * Return 0 if successful or an error code otherwise. + */ +static int __init scu_a9_enable(void) +{ + unsigned long config_base; + void __iomem *scu_base; + + if (!scu_a9_has_base()) { + pr_err("no configuration base address register!\n"); + return -ENXIO; + } + + /* Config base address register value is zero for uniprocessor */ + config_base = scu_a9_get_base(); + if (!config_base) { + pr_err("hardware reports only one core\n"); + return -ENOENT; + } + + scu_base = ioremap((phys_addr_t)config_base, CORTEX_A9_SCU_SIZE); + if (!scu_base) { + pr_err("failed to remap config base (%lu/%u) for SCU\n", + config_base, CORTEX_A9_SCU_SIZE); + return -ENOMEM; + } + + scu_enable(scu_base); + + iounmap(scu_base); /* That's the last we'll need of this */ + + return 0; +} + +static int nsp_write_lut(void) +{ + void __iomem *sku_rom_lut; + phys_addr_t secondary_startup_phy; + + if (!secondary_boot_addr) { + pr_warn("required secondary boot register not specified\n"); + return -EINVAL; + } + + sku_rom_lut = ioremap_nocache((phys_addr_t)secondary_boot_addr, + sizeof(secondary_boot_addr)); + if (!sku_rom_lut) { + pr_warn("unable to ioremap SKU-ROM LUT register\n"); + return -ENOMEM; + } + + secondary_startup_phy = virt_to_phys(secondary_startup); + BUG_ON(secondary_startup_phy > (phys_addr_t)U32_MAX); + + writel_relaxed(secondary_startup_phy, sku_rom_lut); + + /* Ensure the write is visible to the secondary core */ + smp_wmb(); + + iounmap(sku_rom_lut); + + return 0; +} + +static void __init bcm_smp_prepare_cpus(unsigned int max_cpus) +{ + static cpumask_t only_cpu_0 = { CPU_BITS_CPU0 }; + struct device_node *cpus_node = NULL; + struct device_node *cpu_node = NULL; + int ret; + + /* + * This function is only called via smp_ops->smp_prepare_cpu(). + * That only happens if a "/cpus" device tree node exists + * and has an "enable-method" property that selects the SMP + * operations defined herein. + */ + cpus_node = of_find_node_by_path("/cpus"); + if (!cpus_node) + return; + + for_each_child_of_node(cpus_node, cpu_node) { + u32 cpuid; + + if (of_node_cmp(cpu_node->type, "cpu")) + continue; + + if (of_property_read_u32(cpu_node, "reg", &cpuid)) { + pr_debug("%s: missing reg property\n", + cpu_node->full_name); + ret = -ENOENT; + goto out; + } + + /* + * "secondary-boot-reg" property should be defined only + * for secondary cpu + */ + if ((cpuid & MPIDR_CPUID_BITMASK) == 1) { + /* + * Our secondary enable method requires a + * "secondary-boot-reg" property to specify a register + * address used to request the ROM code boot a secondary + * core. If we have any trouble getting this we fall + * back to uniprocessor mode. + */ + if (of_property_read_u32(cpu_node, + OF_SECONDARY_BOOT, + &secondary_boot_addr)) { + pr_warn("%s: no" OF_SECONDARY_BOOT "property\n", + cpu_node->name); + ret = -ENOENT; + goto out; + } + } + } + + /* + * Enable the SCU on Cortex A9 based SoCs. If -ENOENT is + * returned, the SoC reported a uniprocessor configuration. + * We bail on any other error. + */ + ret = scu_a9_enable(); +out: + of_node_put(cpu_node); + of_node_put(cpus_node); + + if (ret) { + /* Update the CPU present map to reflect uniprocessor mode */ + pr_warn("disabling SMP\n"); + init_cpu_present(&only_cpu_0); + } +} + +/* + * The ROM code has the secondary cores looping, waiting for an event. + * When an event occurs each core examines the bottom two bits of the + * secondary boot register. When a core finds those bits contain its + * own core id, it performs initialization, including computing its boot + * address by clearing the boot register value's bottom two bits. The + * core signals that it is beginning its execution by writing its boot + * address back to the secondary boot register, and finally jumps to + * that address. + * + * So to start a core executing we need to: + * - Encode the (hardware) CPU id with the bottom bits of the secondary + * start address. + * - Write that value into the secondary boot register. + * - Generate an event to wake up the secondary CPU(s). + * - Wait for the secondary boot register to be re-written, which + * indicates the secondary core has started. + */ +static int kona_boot_secondary(unsigned int cpu, struct task_struct *idle) +{ + void __iomem *boot_reg; + phys_addr_t boot_func; + u64 start_clock; + u32 cpu_id; + u32 boot_val; + bool timeout = false; + + cpu_id = cpu_logical_map(cpu); + if (cpu_id & ~BOOT_ADDR_CPUID_MASK) { + pr_err("bad cpu id (%u > %u)\n", cpu_id, BOOT_ADDR_CPUID_MASK); + return -EINVAL; + } + + if (!secondary_boot_addr) { + pr_err("required secondary boot register not specified\n"); + return -EINVAL; + } + + boot_reg = ioremap_nocache( + (phys_addr_t)secondary_boot_addr, sizeof(u32)); + if (!boot_reg) { + pr_err("unable to map boot register for cpu %u\n", cpu_id); + return -ENOMEM; + } + + /* + * Secondary cores will start in secondary_startup(), + * defined in "arch/arm/kernel/head.S" + */ + boot_func = virt_to_phys(secondary_startup); + BUG_ON(boot_func & BOOT_ADDR_CPUID_MASK); + BUG_ON(boot_func > (phys_addr_t)U32_MAX); + + /* The core to start is encoded in the low bits */ + boot_val = (u32)boot_func | cpu_id; + writel_relaxed(boot_val, boot_reg); + + sev(); + + /* The low bits will be cleared once the core has started */ + start_clock = local_clock(); + while (!timeout && readl_relaxed(boot_reg) == boot_val) + timeout = local_clock() - start_clock > SECONDARY_TIMEOUT_NS; + + iounmap(boot_reg); + + if (!timeout) + return 0; + + pr_err("timeout waiting for cpu %u to start\n", cpu_id); + + return -ENXIO; +} + +static int nsp_boot_secondary(unsigned int cpu, struct task_struct *idle) +{ + int ret; + + /* + * After wake up, secondary core branches to the startup + * address programmed at SKU ROM LUT location. + */ + ret = nsp_write_lut(); + if (ret) { + pr_err("unable to write startup addr to SKU ROM LUT\n"); + goto out; + } + + /* Send a CPU wakeup interrupt to the secondary core */ + arch_send_wakeup_ipi_mask(cpumask_of(cpu)); + +out: + return ret; +} + +static struct smp_operations bcm_smp_ops __initdata = { + .smp_prepare_cpus = bcm_smp_prepare_cpus, + .smp_boot_secondary = kona_boot_secondary, +}; +CPU_METHOD_OF_DECLARE(bcm_smp_bcm281xx, "brcm,bcm11351-cpu-method", + &bcm_smp_ops); + +struct smp_operations nsp_smp_ops __initdata = { + .smp_prepare_cpus = bcm_smp_prepare_cpus, + .smp_boot_secondary = nsp_boot_secondary, +}; +CPU_METHOD_OF_DECLARE(bcm_smp_nsp, "brcm,bcm-nsp-smp", &nsp_smp_ops); -- cgit v0.10.2 From 99498905ac1fbc73a97d27d21ea449fb939072e3 Mon Sep 17 00:00:00 2001 From: Jon Mason Date: Tue, 1 Dec 2015 11:24:09 -0500 Subject: ARM: BCM: Add SMP support for Broadcom 4708 Add SMP support for Broadcom's 4708 SoCs. Signed-off-by: Jon Mason Acked-by: Hauke Mehrtens Tested-by: Hauke Mehrtens Signed-off-by: Kapil Hali Signed-off-by: Florian Fainelli diff --git a/arch/arm/boot/dts/bcm4708.dtsi b/arch/arm/boot/dts/bcm4708.dtsi index 31141e8..eed4dd1 100644 --- a/arch/arm/boot/dts/bcm4708.dtsi +++ b/arch/arm/boot/dts/bcm4708.dtsi @@ -15,6 +15,7 @@ cpus { #address-cells = <1>; #size-cells = <0>; + enable-method = "brcm,bcm-nsp-smp"; cpu@0 { device_type = "cpu"; @@ -27,6 +28,7 @@ device_type = "cpu"; compatible = "arm,cortex-a9"; next-level-cache = <&L2>; + secondary-boot-reg = <0xffff0400>; reg = <0x1>; }; }; diff --git a/arch/arm/mach-bcm/Kconfig b/arch/arm/mach-bcm/Kconfig index 6e3e043..0207736 100644 --- a/arch/arm/mach-bcm/Kconfig +++ b/arch/arm/mach-bcm/Kconfig @@ -57,6 +57,7 @@ config ARCH_BCM_5301X select ARM_ERRATA_754322 select ARM_ERRATA_775420 select ARM_ERRATA_764369 if SMP + select HAVE_SMP help Support for Broadcom BCM470X and BCM5301X SoCs with ARM CPU cores. diff --git a/arch/arm/mach-bcm/Makefile b/arch/arm/mach-bcm/Makefile index 5193a25..7d66515 100644 --- a/arch/arm/mach-bcm/Makefile +++ b/arch/arm/mach-bcm/Makefile @@ -43,6 +43,9 @@ obj-$(CONFIG_ARCH_BCM2835) += board_bcm2835.o # BCM5301X obj-$(CONFIG_ARCH_BCM_5301X) += bcm_5301x.o +ifeq ($(CONFIG_ARCH_BCM_5301X),y) +obj-$(CONFIG_SMP) += platsmp.o +endif # BCM63XXx ifeq ($(CONFIG_ARCH_BCM_63XX),y) -- cgit v0.10.2 From 8f039f9a692ab7014e2818a4e372231e134553f9 Mon Sep 17 00:00:00 2001 From: Moritz Fischer Date: Thu, 30 Jul 2015 18:13:57 -0700 Subject: ARM: zynq: Select ARCH_HAS_RESET_CONTROLLER Signed-off-by: Moritz Fischer Signed-off-by: Michal Simek diff --git a/arch/arm/mach-zynq/Kconfig b/arch/arm/mach-zynq/Kconfig index 78e5e00..77d7df7 100644 --- a/arch/arm/mach-zynq/Kconfig +++ b/arch/arm/mach-zynq/Kconfig @@ -1,5 +1,6 @@ config ARCH_ZYNQ bool "Xilinx Zynq ARM Cortex A9 Platform" if ARCH_MULTI_V7 + select ARCH_HAS_RESET_CONTROLLER select ARCH_SUPPORTS_BIG_ENDIAN select ARM_AMBA select ARM_GIC -- cgit v0.10.2 From 26dc88fbb937e61988d86af92ca57544cc2a2087 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Fri, 4 Dec 2015 18:04:44 +0100 Subject: ARM: rockchip: use const and __initconst for rk3036 smp_operations The newly added rk3036 smp operations missed the wholesale fixup from Masahiro Yamada. So fix that now. Reported-by: Mark Brown Signed-off-by: Heiko Stuebner diff --git a/arch/arm/mach-rockchip/platsmp.c b/arch/arm/mach-rockchip/platsmp.c index 5c138f9..9a5b2e0 100644 --- a/arch/arm/mach-rockchip/platsmp.c +++ b/arch/arm/mach-rockchip/platsmp.c @@ -351,7 +351,7 @@ static void rockchip_cpu_die(unsigned int cpu) } #endif -static struct smp_operations rk3036_smp_ops __initdata = { +static const struct smp_operations rk3036_smp_ops __initconst = { .smp_prepare_cpus = rk3036_smp_prepare_cpus, .smp_boot_secondary = rockchip_boot_secondary, #ifdef CONFIG_HOTPLUG_CPU -- cgit v0.10.2 From 2608224c81a7d242a9b451b97011410b182f0da7 Mon Sep 17 00:00:00 2001 From: Jeffy Chen Date: Wed, 9 Dec 2015 17:04:11 +0800 Subject: ARM: rockchip: enable support for RK3228 SoCs Add a rockchip,rk3228 compatible. Signed-off-by: Jeffy Chen Signed-off-by: Heiko Stuebner diff --git a/arch/arm/mach-rockchip/rockchip.c b/arch/arm/mach-rockchip/rockchip.c index 251c7b9..3f07cc5 100644 --- a/arch/arm/mach-rockchip/rockchip.c +++ b/arch/arm/mach-rockchip/rockchip.c @@ -82,6 +82,7 @@ static const char * const rockchip_board_dt_compat[] = { "rockchip,rk3066a", "rockchip,rk3066b", "rockchip,rk3188", + "rockchip,rk3228", "rockchip,rk3288", NULL, }; -- cgit v0.10.2 From 65a52a212adde216a92656a1419ea4ec0a7781c7 Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Fri, 11 Dec 2015 14:50:19 +0200 Subject: ARM: OMAP1: Remove device creation for omap-pcm-audio The omap-pcm in ASoC is no longer a platform device. No need to create this device anymore. Signed-off-by: Peter Ujfalusi Signed-off-by: Tony Lindgren diff --git a/arch/arm/mach-omap1/devices.c b/arch/arm/mach-omap1/devices.c index 325e603..717f13d 100644 --- a/arch/arm/mach-omap1/devices.c +++ b/arch/arm/mach-omap1/devices.c @@ -33,24 +33,6 @@ #include "mmc.h" #include "sram.h" -#if defined(CONFIG_SND_SOC) || defined(CONFIG_SND_SOC_MODULE) - -static struct platform_device omap_pcm = { - .name = "omap-pcm-audio", - .id = -1, -}; - -static void omap_init_audio(void) -{ - platform_device_register(&omap_pcm); -} - -#else -static inline void omap_init_audio(void) {} -#endif - -/*-------------------------------------------------------------------------*/ - #if defined(CONFIG_RTC_DRV_OMAP) || defined(CONFIG_RTC_DRV_OMAP_MODULE) #define OMAP_RTC_BASE 0xfffb4800 @@ -425,7 +407,6 @@ static int __init omap1_init_devices(void) * in alphabetical order so they're easier to sort through. */ - omap_init_audio(); omap_init_mbox(); omap_init_rtc(); omap_init_spi100k(); -- cgit v0.10.2 From f2e6a0a913b53f5af87c7e9a783ceae5bb4ae2c4 Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Fri, 11 Dec 2015 14:50:20 +0200 Subject: ARM: OMAP2+: Remove device creation for omap-pcm-audio The omap-pcm in ASoC is no longer a platform device. No need to create this device anymore. Signed-off-by: Peter Ujfalusi Signed-off-by: Tony Lindgren diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c index 9374da3..9cda974 100644 --- a/arch/arm/mach-omap2/devices.c +++ b/arch/arm/mach-omap2/devices.c @@ -94,22 +94,6 @@ static inline void omap_init_mbox(void) { } static inline void omap_init_sti(void) {} -#if defined(CONFIG_SND_SOC) || defined(CONFIG_SND_SOC_MODULE) - -static struct platform_device omap_pcm = { - .name = "omap-pcm-audio", - .id = -1, -}; - -static void omap_init_audio(void) -{ - platform_device_register(&omap_pcm); -} - -#else -static inline void omap_init_audio(void) {} -#endif - #if defined(CONFIG_SPI_OMAP24XX) || defined(CONFIG_SPI_OMAP24XX_MODULE) #include @@ -239,13 +223,12 @@ static int __init omap2_init_devices(void) if (!of_have_populated_dt()) pinctrl_provide_dummies(); - /* - * please keep these calls, and their implementations above, - * in alphabetical order so they're easier to sort through. - */ - omap_init_audio(); /* If dtb is there, the devices will be created dynamically */ if (!of_have_populated_dt()) { + /* + * please keep these calls, and their implementations above, + * in alphabetical order so they're easier to sort through. + */ omap_init_mbox(); omap_init_mcspi(); omap_init_sham(); -- cgit v0.10.2 From 20f0c63ccb122471c8ee293b74d0a7ff6ea5ba3c Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Thu, 5 Nov 2015 15:47:55 +0900 Subject: ARM: uniphier: select PINCTRL The UniPhier SoCs support pinctrl drivers. Signed-off-by: Masahiro Yamada Signed-off-by: Olof Johansson diff --git a/arch/arm/mach-uniphier/Kconfig b/arch/arm/mach-uniphier/Kconfig index b640458..82dddee 100644 --- a/arch/arm/mach-uniphier/Kconfig +++ b/arch/arm/mach-uniphier/Kconfig @@ -6,6 +6,7 @@ config ARCH_UNIPHIER select ARM_GIC select HAVE_ARM_SCU select HAVE_ARM_TWD if SMP + select PINCTRL help Support for UniPhier SoC family developed by Socionext Inc. (formerly, System LSI Business Division of Panasonic Corporation) -- cgit v0.10.2 From f1858b0e801a45d801dc23bc1ff5be14805022c8 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Fri, 18 Dec 2015 16:40:26 +0100 Subject: ARM: imx: select SRC for i.MX7 The i.MX7 Kconfig option had a couple of missing select lines that I fixed already, but I missed HAVE_IMX_SRC: arch/arm/mach-imx/built-in.o: In function `imx7d_init_irq': platform-spi_imx.c:(.init.text+0x25a8): undefined reference to `imx_src_init' This adds that one as well. Signed-off-by: Arnd Bergmann Fixes: 0be5da9dc249 ("ARM: imx: imx7d requires anatop") Signed-off-by: Shawn Guo diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index 8ceda28..9aa659e 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -562,6 +562,7 @@ config SOC_IMX7D select ARM_GIC select HAVE_IMX_ANATOP select HAVE_IMX_MMDC + select HAVE_IMX_SRC help This enables support for Freescale i.MX7 Dual processor. -- cgit v0.10.2 From 57e5c6d95b2cde884634586d833b02f54ba1c79d Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Tue, 21 Apr 2015 09:42:21 -0700 Subject: dt-bindings: Add root properties for Raspberry Pi 2 Signed-off-by: Eric Anholt Acked-by: Rob Herring diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm2835.txt b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm2835.txt index c78576b..11d3056 100644 --- a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm2835.txt +++ b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm2835.txt @@ -26,6 +26,10 @@ Raspberry Pi Model B+ Required root node properties: compatible = "raspberrypi,model-b-plus", "brcm,bcm2835"; +Raspberry Pi 2 Model B +Required root node properties: +compatible = "raspberrypi,2-model-b", "brcm,bcm2836"; + Raspberry Pi Compute Module Required root node properties: compatible = "raspberrypi,compute-module", "brcm,bcm2835"; -- cgit v0.10.2 From c1be3c1fc6178ca48750b4e66f1acb7c22b64997 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Wed, 16 Dec 2015 15:55:14 -0800 Subject: ARM: bcm2835: Add a compat string for bcm2836 machine probe Supporting the 2836 requires using the new interrupt controller, which we have support for. Signed-off-by: Eric Anholt diff --git a/arch/arm/mach-bcm/board_bcm2835.c b/arch/arm/mach-bcm/board_bcm2835.c index 0f7b9ea..834d676 100644 --- a/arch/arm/mach-bcm/board_bcm2835.c +++ b/arch/arm/mach-bcm/board_bcm2835.c @@ -36,7 +36,12 @@ static void __init bcm2835_init(void) } static const char * const bcm2835_compat[] = { +#ifdef CONFIG_ARCH_MULTI_V6 "brcm,bcm2835", +#endif +#ifdef CONFIG_ARCH_MULTI_V7 + "brcm,bcm2836", +#endif NULL }; -- cgit v0.10.2 From d6de5b0294d74aefa16f78d050d1bcf6d5af84a7 Mon Sep 17 00:00:00 2001 From: Marc Gonzalez Date: Tue, 15 Dec 2015 10:41:13 +0100 Subject: ARM: tango4: Initial platform support Support Sigma Designs ARM-based (specifically, Cortex-A9 MPCore r3p0) Tango4 "Secure Media Processor" platforms: smp8756, smp8758, smp8759 (8756 is single-core, the latter are dual-core). Note: 8758 vs 8759: same chip, different package. Support for older MIPS-based platforms can be found elsewhere: https://github.com/mansr/linux-tangox Signed-off-by: Marc Gonzalez Reviewed-by: Kevin Hilman Signed-off-by: Olof Johansson diff --git a/MAINTAINERS b/MAINTAINERS index cba790b..d5506b0 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1588,6 +1588,13 @@ T: git git://git.kernel.org/pub/scm/linux/kernel/git/mcoquelin/stm32.git N: stm32 F: drivers/clocksource/armv7m_systick.c +ARM/TANGO ARCHITECTURE +M: Marc Gonzalez +L: linux-arm-kernel@lists.infradead.org +S: Maintained +F: arch/arm/mach-tango/ +F: arch/arm/boot/dts/tango* + ARM/TECHNOLOGIC SYSTEMS TS7250 MACHINE SUPPORT M: Lennert Buytenhek L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index e803304..0bdf7a6 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -919,6 +919,8 @@ source "arch/arm/mach-sunxi/Kconfig" source "arch/arm/mach-prima2/Kconfig" +source "arch/arm/mach-tango/Kconfig" + source "arch/arm/mach-tegra/Kconfig" source "arch/arm/mach-u300/Kconfig" diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 2c2b28e..d1da248 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -211,6 +211,7 @@ machine-$(CONFIG_ARCH_SOCFPGA) += socfpga machine-$(CONFIG_ARCH_STI) += sti machine-$(CONFIG_ARCH_STM32) += stm32 machine-$(CONFIG_ARCH_SUNXI) += sunxi +machine-$(CONFIG_ARCH_TANGO) += tango machine-$(CONFIG_ARCH_TEGRA) += tegra machine-$(CONFIG_ARCH_U300) += u300 machine-$(CONFIG_ARCH_U8500) += ux500 diff --git a/arch/arm/mach-tango/Kconfig b/arch/arm/mach-tango/Kconfig new file mode 100644 index 0000000..d6a3714 --- /dev/null +++ b/arch/arm/mach-tango/Kconfig @@ -0,0 +1,12 @@ +config ARCH_TANGO + bool "Sigma Designs Tango4 (SMP87xx)" if ARCH_MULTI_V7 + # Cortex-A9 MPCore r3p0, PL310 r3p2 + select ARCH_HAS_HOLES_MEMORYMODEL + select ARM_ERRATA_754322 + select ARM_ERRATA_764369 if SMP + select ARM_ERRATA_775420 + select ARM_GIC + select CLKSRC_TANGO_XTAL + select HAVE_ARM_SCU + select HAVE_ARM_TWD + select TANGO_IRQ diff --git a/arch/arm/mach-tango/Makefile b/arch/arm/mach-tango/Makefile new file mode 100644 index 0000000..0d7e2b5 --- /dev/null +++ b/arch/arm/mach-tango/Makefile @@ -0,0 +1,2 @@ +asflags-y += -mcpu=cortex-a9 +obj-y += setup.o smc.o diff --git a/arch/arm/mach-tango/setup.c b/arch/arm/mach-tango/setup.c new file mode 100644 index 0000000..d869005 --- /dev/null +++ b/arch/arm/mach-tango/setup.c @@ -0,0 +1,31 @@ +#include +#include +#include +#include "smc.h" + +static int tango4_boot_secondary(unsigned int cpu, struct task_struct *idle) +{ + tango_set_aux_boot_addr(virt_to_phys(secondary_startup)); + tango_start_aux_core(cpu); + return 0; +} + +static struct smp_operations tango4_smp_ops __initdata = { + .smp_boot_secondary = tango4_boot_secondary, +}; + +CPU_METHOD_OF_DECLARE(tango4_smp, "sigma,tango4-smp", &tango4_smp_ops); + +static void tango_l2c_write(unsigned long val, unsigned int reg) +{ + if (reg == L2X0_CTRL) + tango_set_l2_control(val); +} + +static const char *const tango_dt_compat[] = { "sigma,tango4", NULL }; + +DT_MACHINE_START(TANGO_DT, "Sigma Tango DT") + .dt_compat = tango_dt_compat, + .l2c_aux_mask = ~0, + .l2c_write_sec = tango_l2c_write, +MACHINE_END diff --git a/arch/arm/mach-tango/smc.S b/arch/arm/mach-tango/smc.S new file mode 100644 index 0000000..5d932ce --- /dev/null +++ b/arch/arm/mach-tango/smc.S @@ -0,0 +1,9 @@ +#include + +ENTRY(tango_smc) + push {lr} + mov ip, r1 + dsb /* This barrier is probably unnecessary */ + smc #0 + pop {pc} +ENDPROC(tango_smc) diff --git a/arch/arm/mach-tango/smc.h b/arch/arm/mach-tango/smc.h new file mode 100644 index 0000000..7a4af35 --- /dev/null +++ b/arch/arm/mach-tango/smc.h @@ -0,0 +1,5 @@ +extern int tango_smc(unsigned int val, unsigned int service); + +#define tango_set_l2_control(val) tango_smc(val, 0x102) +#define tango_start_aux_core(val) tango_smc(val, 0x104) +#define tango_set_aux_boot_addr(val) tango_smc((unsigned int)val, 0x105) -- cgit v0.10.2 From 68b813bf573c865c5a7b7f7090f535bf4e153c3a Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Tue, 22 Dec 2015 15:39:29 -0800 Subject: ARM: OMAP2+: Fix SoC detection for dra62x j5-eco We can boot dra62x j5-eco using the dm814x code as the clocks and devices are mapped in the device tree. The dra62x is also known as jacinto 5 eco. We may want to add separate soc_is macros for dra62x if needed, but this gets us to the point where we can boot dra62x with just dts changes. Let's also print out the unknown hawkeye register to make things a bit easier for new SoC variants. Signed-off-by: Tony Lindgren diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c index 8a2ae82..d85c249 100644 --- a/arch/arm/mach-omap2/id.c +++ b/arch/arm/mach-omap2/id.c @@ -488,6 +488,7 @@ void __init omap3xxx_check_revision(void) } break; case 0xb8f2: + case 0xb968: switch (rev) { case 0: /* FALLTHROUGH */ @@ -511,7 +512,8 @@ void __init omap3xxx_check_revision(void) /* Unknown default to latest silicon rev as default */ omap_revision = OMAP3630_REV_ES1_2; cpu_rev = "1.2"; - pr_warn("Warning: unknown chip type; assuming OMAP3630ES1.2\n"); + pr_warn("Warning: unknown chip type: hawkeye %04x, assuming OMAP3630ES1.2\n", + hawkeye); } sprintf(soc_rev, "ES%s", cpu_rev); } -- cgit v0.10.2 From 418d4ebcfe45d0e88ea2a41f4d7a529eba0a4598 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Tue, 22 Dec 2015 15:39:52 -0800 Subject: ARM: OMAP2+: Update 81xx clock and power domains for default, active and sgx These offsets seem to be common, so let's rename the defines. And let's set up the default_l3_slow_81xx_clkdm with active and default powerdomains for dm814x. These are needed for usb to work. Cc: Paul Walmsley Cc: Tero Kristo Signed-off-by: Tony Lindgren diff --git a/arch/arm/mach-omap2/clockdomains81xx_data.c b/arch/arm/mach-omap2/clockdomains81xx_data.c index 53442c8..3b5fb05 100644 --- a/arch/arm/mach-omap2/clockdomains81xx_data.c +++ b/arch/arm/mach-omap2/clockdomains81xx_data.c @@ -83,6 +83,14 @@ static struct clockdomain mmu_cfg_81xx_clkdm = { .flags = CLKDM_CAN_SWSUP, }; +static struct clockdomain default_l3_slow_81xx_clkdm = { + .name = "default_l3_slow_clkdm", + .pwrdm = { .name = "default_pwrdm" }, + .cm_inst = TI81XX_CM_DEFAULT_MOD, + .clkdm_offs = TI816X_CM_DEFAULT_L3_SLOW_CLKDM, + .flags = CLKDM_CAN_SWSUP, +}; + /* 816x only */ static struct clockdomain alwon_mpu_816x_clkdm = { @@ -96,7 +104,7 @@ static struct clockdomain alwon_mpu_816x_clkdm = { static struct clockdomain active_gem_816x_clkdm = { .name = "active_gem_clkdm", .pwrdm = { .name = "active_pwrdm" }, - .cm_inst = TI816X_CM_ACTIVE_MOD, + .cm_inst = TI81XX_CM_ACTIVE_MOD, .clkdm_offs = TI816X_CM_ACTIVE_GEM_CLKDM, .flags = CLKDM_CAN_SWSUP, }; @@ -128,7 +136,7 @@ static struct clockdomain ivahd2_816x_clkdm = { static struct clockdomain sgx_816x_clkdm = { .name = "sgx_clkdm", .pwrdm = { .name = "sgx_pwrdm" }, - .cm_inst = TI816X_CM_SGX_MOD, + .cm_inst = TI81XX_CM_SGX_MOD, .clkdm_offs = TI816X_CM_SGX_CLKDM, .flags = CLKDM_CAN_SWSUP, }; @@ -136,7 +144,7 @@ static struct clockdomain sgx_816x_clkdm = { static struct clockdomain default_l3_med_816x_clkdm = { .name = "default_l3_med_clkdm", .pwrdm = { .name = "default_pwrdm" }, - .cm_inst = TI816X_CM_DEFAULT_MOD, + .cm_inst = TI81XX_CM_DEFAULT_MOD, .clkdm_offs = TI816X_CM_DEFAULT_L3_MED_CLKDM, .flags = CLKDM_CAN_SWSUP, }; @@ -144,7 +152,7 @@ static struct clockdomain default_l3_med_816x_clkdm = { static struct clockdomain default_ducati_816x_clkdm = { .name = "default_ducati_clkdm", .pwrdm = { .name = "default_pwrdm" }, - .cm_inst = TI816X_CM_DEFAULT_MOD, + .cm_inst = TI81XX_CM_DEFAULT_MOD, .clkdm_offs = TI816X_CM_DEFAULT_DUCATI_CLKDM, .flags = CLKDM_CAN_SWSUP, }; @@ -152,19 +160,11 @@ static struct clockdomain default_ducati_816x_clkdm = { static struct clockdomain default_pci_816x_clkdm = { .name = "default_pci_clkdm", .pwrdm = { .name = "default_pwrdm" }, - .cm_inst = TI816X_CM_DEFAULT_MOD, + .cm_inst = TI81XX_CM_DEFAULT_MOD, .clkdm_offs = TI816X_CM_DEFAULT_PCI_CLKDM, .flags = CLKDM_CAN_SWSUP, }; -static struct clockdomain default_l3_slow_816x_clkdm = { - .name = "default_l3_slow_clkdm", - .pwrdm = { .name = "default_pwrdm" }, - .cm_inst = TI816X_CM_DEFAULT_MOD, - .clkdm_offs = TI816X_CM_DEFAULT_L3_SLOW_CLKDM, - .flags = CLKDM_CAN_SWSUP, -}; - static struct clockdomain *clockdomains_ti814x[] __initdata = { &alwon_l3_slow_81xx_clkdm, &alwon_l3_med_81xx_clkdm, @@ -172,6 +172,7 @@ static struct clockdomain *clockdomains_ti814x[] __initdata = { &alwon_ethernet_81xx_clkdm, &mmu_81xx_clkdm, &mmu_cfg_81xx_clkdm, + &default_l3_slow_81xx_clkdm, NULL, }; @@ -198,7 +199,7 @@ static struct clockdomain *clockdomains_ti816x[] __initdata = { &default_l3_med_816x_clkdm, &default_ducati_816x_clkdm, &default_pci_816x_clkdm, - &default_l3_slow_816x_clkdm, + &default_l3_slow_81xx_clkdm, NULL, }; diff --git a/arch/arm/mach-omap2/cm81xx.h b/arch/arm/mach-omap2/cm81xx.h index 45cb407..3a0ccf0 100644 --- a/arch/arm/mach-omap2/cm81xx.h +++ b/arch/arm/mach-omap2/cm81xx.h @@ -18,15 +18,15 @@ #define __ARCH_ARM_MACH_OMAP2_CM_TI81XX_H /* TI81XX common CM module offsets */ +#define TI81XX_CM_ACTIVE_MOD 0x0400 /* 256B */ +#define TI81XX_CM_DEFAULT_MOD 0x0500 /* 256B */ #define TI81XX_CM_ALWON_MOD 0x1400 /* 1KB */ +#define TI81XX_CM_SGX_MOD 0x0900 /* 256B */ /* TI816X CM module offsets */ -#define TI816X_CM_ACTIVE_MOD 0x0400 /* 256B */ -#define TI816X_CM_DEFAULT_MOD 0x0500 /* 256B */ #define TI816X_CM_IVAHD0_MOD 0x0600 /* 256B */ #define TI816X_CM_IVAHD1_MOD 0x0700 /* 256B */ #define TI816X_CM_IVAHD2_MOD 0x0800 /* 256B */ -#define TI816X_CM_SGX_MOD 0x0900 /* 256B */ /* ALWON */ #define TI81XX_CM_ALWON_L3_SLOW_CLKDM 0x0000 diff --git a/arch/arm/mach-omap2/powerdomains3xxx_data.c b/arch/arm/mach-omap2/powerdomains3xxx_data.c index 2e00c7f..eb27ae0 100644 --- a/arch/arm/mach-omap2/powerdomains3xxx_data.c +++ b/arch/arm/mach-omap2/powerdomains3xxx_data.c @@ -384,14 +384,14 @@ static struct powerdomain isp_814x_pwrdm = { .voltdm = { .name = "core" }, }; -static struct powerdomain active_816x_pwrdm = { +static struct powerdomain active_81xx_pwrdm = { .name = "active_pwrdm", .prcm_offs = TI816X_PRM_ACTIVE_MOD, .pwrsts = PWRSTS_OFF_ON, .voltdm = { .name = "core" }, }; -static struct powerdomain default_816x_pwrdm = { +static struct powerdomain default_81xx_pwrdm = { .name = "default_pwrdm", .prcm_offs = TI81XX_PRM_DEFAULT_MOD, .pwrsts = PWRSTS_OFF_ON, @@ -486,6 +486,8 @@ static struct powerdomain *powerdomains_am35x[] __initdata = { static struct powerdomain *powerdomains_ti814x[] __initdata = { &alwon_81xx_pwrdm, &device_81xx_pwrdm, + &active_81xx_pwrdm, + &default_81xx_pwrdm, &gem_814x_pwrdm, &ivahd_814x_pwrdm, &hdvpss_814x_pwrdm, @@ -497,8 +499,8 @@ static struct powerdomain *powerdomains_ti814x[] __initdata = { static struct powerdomain *powerdomains_ti816x[] __initdata = { &alwon_81xx_pwrdm, &device_81xx_pwrdm, - &active_816x_pwrdm, - &default_816x_pwrdm, + &active_81xx_pwrdm, + &default_81xx_pwrdm, &ivahd0_816x_pwrdm, &ivahd1_816x_pwrdm, &ivahd2_816x_pwrdm, -- cgit v0.10.2 From c757fda8937b30f0691f7ecfaaa2d3b977aee607 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Tue, 22 Dec 2015 15:39:41 -0800 Subject: ARM: OMAP2+: Add mmc hwmod entries for dm814x Let's add mmc entries for dm814x. To do that, we need to rename some entries to be common for 81xx. Cc: Paul Walmsley Signed-off-by: Tony Lindgren diff --git a/arch/arm/mach-omap2/omap_hwmod_81xx_data.c b/arch/arm/mach-omap2/omap_hwmod_81xx_data.c index 13dfdf6..881d25d 100644 --- a/arch/arm/mach-omap2/omap_hwmod_81xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_81xx_data.c @@ -909,7 +909,7 @@ static struct omap_hwmod_ocp_if dm816x_l4_hs__emac1 = { .user = OCP_USER_MPU, }; -static struct omap_hwmod_class_sysconfig dm816x_mmc_sysc = { +static struct omap_hwmod_class_sysconfig dm81xx_mmc_sysc = { .rev_offs = 0x0, .sysc_offs = 0x110, .syss_offs = 0x114, @@ -920,24 +920,94 @@ static struct omap_hwmod_class_sysconfig dm816x_mmc_sysc = { .sysc_fields = &omap_hwmod_sysc_type1, }; -static struct omap_hwmod_class dm816x_mmc_class = { +static struct omap_hwmod_class dm81xx_mmc_class = { .name = "mmc", - .sysc = &dm816x_mmc_sysc, + .sysc = &dm81xx_mmc_sysc, }; -static struct omap_hwmod_opt_clk dm816x_mmc1_opt_clks[] = { +static struct omap_hwmod_opt_clk dm81xx_mmc_opt_clks[] = { { .role = "dbck", .clk = "sysclk18_ck", }, }; -static struct omap_hsmmc_dev_attr mmc1_dev_attr = { - .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, +static struct omap_hsmmc_dev_attr mmc_dev_attr = { +}; + +static struct omap_hwmod dm814x_mmc1_hwmod = { + .name = "mmc1", + .clkdm_name = "alwon_l3s_clkdm", + .opt_clks = dm81xx_mmc_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(dm81xx_mmc_opt_clks), + .main_clk = "sysclk8_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = DM814X_CM_ALWON_MMCHS_0_CLKCTRL, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .dev_attr = &mmc_dev_attr, + .class = &dm81xx_mmc_class, +}; + +static struct omap_hwmod_ocp_if dm814x_l4_ls__mmc1 = { + .master = &dm81xx_l4_ls_hwmod, + .slave = &dm814x_mmc1_hwmod, + .clk = "sysclk6_ck", + .user = OCP_USER_MPU, + .flags = OMAP_FIREWALL_L4 +}; + +static struct omap_hwmod dm814x_mmc2_hwmod = { + .name = "mmc2", + .clkdm_name = "alwon_l3s_clkdm", + .opt_clks = dm81xx_mmc_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(dm81xx_mmc_opt_clks), + .main_clk = "sysclk8_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = DM814X_CM_ALWON_MMCHS_1_CLKCTRL, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .dev_attr = &mmc_dev_attr, + .class = &dm81xx_mmc_class, +}; + +static struct omap_hwmod_ocp_if dm814x_l4_ls__mmc2 = { + .master = &dm81xx_l4_ls_hwmod, + .slave = &dm814x_mmc2_hwmod, + .clk = "sysclk6_ck", + .user = OCP_USER_MPU, + .flags = OMAP_FIREWALL_L4 +}; + +static struct omap_hwmod dm814x_mmc3_hwmod = { + .name = "mmc3", + .clkdm_name = "alwon_l3_med_clkdm", + .opt_clks = dm81xx_mmc_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(dm81xx_mmc_opt_clks), + .main_clk = "sysclk8_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = DM814X_CM_ALWON_MMCHS_2_CLKCTRL, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .dev_attr = &mmc_dev_attr, + .class = &dm81xx_mmc_class, +}; + +static struct omap_hwmod_ocp_if dm814x_alwon_l3_med__mmc3 = { + .master = &dm81xx_alwon_l3_med_hwmod, + .slave = &dm814x_mmc3_hwmod, + .clk = "sysclk4_ck", + .user = OCP_USER_MPU, }; static struct omap_hwmod dm816x_mmc1_hwmod = { .name = "mmc1", .clkdm_name = "alwon_l3s_clkdm", - .opt_clks = dm816x_mmc1_opt_clks, - .opt_clks_cnt = ARRAY_SIZE(dm816x_mmc1_opt_clks), + .opt_clks = dm81xx_mmc_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(dm81xx_mmc_opt_clks), .main_clk = "sysclk10_ck", .prcm = { .omap4 = { @@ -945,8 +1015,8 @@ static struct omap_hwmod dm816x_mmc1_hwmod = { .modulemode = MODULEMODE_SWCTRL, }, }, - .dev_attr = &mmc1_dev_attr, - .class = &dm816x_mmc_class, + .dev_attr = &mmc_dev_attr, + .class = &dm81xx_mmc_class, }; static struct omap_hwmod_ocp_if dm816x_l4_ls__mmc1 = { @@ -1283,6 +1353,8 @@ static struct omap_hwmod_ocp_if *dm814x_hwmod_ocp_ifs[] __initdata = { &dm81xx_l4_ls__i2c2, &dm81xx_l4_ls__elm, &dm81xx_l4_ls__mcspi1, + &dm814x_l4_ls__mmc1, + &dm814x_l4_ls__mmc2, &dm81xx_alwon_l3_fast__tpcc, &dm81xx_alwon_l3_fast__tptc0, &dm81xx_alwon_l3_fast__tptc1, @@ -1296,6 +1368,7 @@ static struct omap_hwmod_ocp_if *dm814x_hwmod_ocp_ifs[] __initdata = { &dm814x_l4_ls__timer2, &dm814x_l4_hs__cpgmac0, &dm814x_cpgmac0__mdio, + &dm814x_alwon_l3_med__mmc3, NULL, }; -- cgit v0.10.2 From f53850b5dc625ca37ae84b47f4f92b1d55df2aa0 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Tue, 22 Dec 2015 15:40:01 -0800 Subject: ARM: OMAP2+: Add support for dm814x and dra62x usb The usb phys are different on dm814x compared to dm816x so we need to use the clkdcoldo output for usb. Cc: Paul Walmsley Signed-off-by: Tony Lindgren diff --git a/arch/arm/mach-omap2/omap_hwmod_81xx_data.c b/arch/arm/mach-omap2/omap_hwmod_81xx_data.c index 881d25d..c863dc1 100644 --- a/arch/arm/mach-omap2/omap_hwmod_81xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_81xx_data.c @@ -104,8 +104,8 @@ * The default .clkctrl_offs field is offset from CM_DEFAULT, that's * TRM 18.7.6 CM_DEFAULT device register values minus 0x500 */ -#define DM816X_CM_DEFAULT_OFFSET 0x500 -#define DM816X_CM_DEFAULT_USB_CLKCTRL (0x558 - DM816X_CM_DEFAULT_OFFSET) +#define DM81XX_CM_DEFAULT_OFFSET 0x500 +#define DM81XX_CM_DEFAULT_USB_CLKCTRL (0x558 - DM81XX_CM_DEFAULT_OFFSET) /* L3 Interconnect entries clocked at 125, 250 and 500MHz */ static struct omap_hwmod dm81xx_alwon_l3_slow_hwmod = { @@ -555,22 +555,42 @@ static struct omap_hwmod_class dm81xx_usbotg_class = { .sysc = &dm81xx_usbhsotg_sysc, }; -static struct omap_hwmod dm81xx_usbss_hwmod = { +static struct omap_hwmod dm814x_usbss_hwmod = { + .name = "usb_otg_hs", + .clkdm_name = "default_l3_slow_clkdm", + .main_clk = "pll260dcoclkldo", /* 481c5260.adpll.dcoclkldo */ + .prcm = { + .omap4 = { + .clkctrl_offs = DM81XX_CM_DEFAULT_USB_CLKCTRL, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .class = &dm81xx_usbotg_class, +}; + +static struct omap_hwmod_ocp_if dm814x_default_l3_slow__usbss = { + .master = &dm81xx_default_l3_slow_hwmod, + .slave = &dm814x_usbss_hwmod, + .clk = "sysclk6_ck", + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod dm816x_usbss_hwmod = { .name = "usb_otg_hs", .clkdm_name = "default_l3_slow_clkdm", .main_clk = "sysclk6_ck", .prcm = { .omap4 = { - .clkctrl_offs = DM816X_CM_DEFAULT_USB_CLKCTRL, + .clkctrl_offs = DM81XX_CM_DEFAULT_USB_CLKCTRL, .modulemode = MODULEMODE_SWCTRL, }, }, .class = &dm81xx_usbotg_class, }; -static struct omap_hwmod_ocp_if dm81xx_default_l3_slow__usbss = { +static struct omap_hwmod_ocp_if dm816x_default_l3_slow__usbss = { .master = &dm81xx_default_l3_slow_hwmod, - .slave = &dm81xx_usbss_hwmod, + .slave = &dm816x_usbss_hwmod, .clk = "sysclk6_ck", .user = OCP_USER_MPU, }; @@ -1334,8 +1354,6 @@ static struct omap_hwmod_ocp_if dm81xx_tptc3__alwon_l3_fast = { * dm81xx_l4_ls__gpio1 * dm81xx_l4_ls__gpio2 * dm81xx_l4_ls__mailbox - * dm81xx_alwon_l3_slow__gpmc - * dm81xx_default_l3_slow__usbss * * Also note that some devices share a single clkctrl_offs.. * For example, i2c1 and 3 share one, and i2c2 and 4 share one. @@ -1368,6 +1386,8 @@ static struct omap_hwmod_ocp_if *dm814x_hwmod_ocp_ifs[] __initdata = { &dm814x_l4_ls__timer2, &dm814x_l4_hs__cpgmac0, &dm814x_cpgmac0__mdio, + &dm81xx_alwon_l3_slow__gpmc, + &dm814x_default_l3_slow__usbss, &dm814x_alwon_l3_med__mmc3, NULL, }; @@ -1416,7 +1436,7 @@ static struct omap_hwmod_ocp_if *dm816x_hwmod_ocp_ifs[] __initdata = { &dm81xx_tptc2__alwon_l3_fast, &dm81xx_tptc3__alwon_l3_fast, &dm81xx_alwon_l3_slow__gpmc, - &dm81xx_default_l3_slow__usbss, + &dm816x_default_l3_slow__usbss, NULL, }; -- cgit v0.10.2 From 5234c34e4cd7695647ccc1cabb50c3e7720dd3fb Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Tue, 24 Feb 2015 15:07:55 +0000 Subject: ARM: bcm2835: Add Kconfig support for bcm2836 This should be a complete port of bcm2835 functionality to bcm2836 (Raspberry Pi 2). Signed-off-by: Eric Anholt diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug index 259c0ca..957b876 100644 --- a/arch/arm/Kconfig.debug +++ b/arch/arm/Kconfig.debug @@ -143,7 +143,12 @@ choice config DEBUG_BCM2835 bool "Kernel low-level debugging on BCM2835 PL011 UART" - depends on ARCH_BCM2835 + depends on ARCH_BCM2835 && ARCH_MULTI_V6 + select DEBUG_UART_PL01X + + config DEBUG_BCM2836 + bool "Kernel low-level debugging on BCM2836 PL011 UART" + depends on ARCH_BCM2835 && ARCH_MULTI_V7 select DEBUG_UART_PL01X config DEBUG_BCM_5301X @@ -1402,6 +1407,7 @@ config DEBUG_UART_PHYS default 0x20064000 if DEBUG_RK29_UART1 || DEBUG_RK3X_UART2 default 0x20068000 if DEBUG_RK29_UART2 || DEBUG_RK3X_UART3 default 0x20201000 if DEBUG_BCM2835 + default 0x3f201000 if DEBUG_BCM2836 default 0x3e000000 if DEBUG_BCM_KONA_UART default 0x4000e400 if DEBUG_LL_UART_EFM32 default 0x40081000 if DEBUG_LPC18XX_UART0 @@ -1485,7 +1491,7 @@ config DEBUG_UART_VIRT default 0xf0000be0 if ARCH_EBSA110 default 0xf0010000 if DEBUG_ASM9260_UART default 0xf01fb000 if DEBUG_NOMADIK_UART - default 0xf0201000 if DEBUG_BCM2835 + default 0xf0201000 if DEBUG_BCM2835 || DEBUG_BCM2836 default 0xf1000300 if DEBUG_BCM_5301X default 0xf1002000 if DEBUG_MT8127_UART0 default 0xf1006000 if DEBUG_MT6589_UART0 diff --git a/arch/arm/mach-bcm/Kconfig b/arch/arm/mach-bcm/Kconfig index 8c53c55..3b2acf4 100644 --- a/arch/arm/mach-bcm/Kconfig +++ b/arch/arm/mach-bcm/Kconfig @@ -122,17 +122,18 @@ config ARCH_BCM_MOBILE_SMP comment "Other Architectures" config ARCH_BCM2835 - bool "Broadcom BCM2835 family" if ARCH_MULTI_V6 + bool "Broadcom BCM2835 family" if ARCH_MULTI_V6 || ARCH_MULTI_V7 select ARCH_REQUIRE_GPIOLIB select ARM_AMBA - select ARM_ERRATA_411920 + select ARM_ERRATA_411920 if ARCH_MULTI_V6 select ARM_TIMER_SP804 + select HAVE_ARM_ARCH_TIMER if ARCH_MULTI_V7 select CLKSRC_OF select PINCTRL select PINCTRL_BCM2835 help - This enables support for the Broadcom BCM2835 SoC. This SoC is - used in the Raspberry Pi and Roku 2 devices. + This enables support for the Broadcom BCM2835 and BCM2836 SoCs. + This SoC is used in the Raspberry Pi and Roku 2 devices. config ARCH_BCM_63XX bool "Broadcom BCM63xx DSL SoC" if ARCH_MULTI_V7 -- cgit v0.10.2 From 765ff22d54591a24fe81f6a451b953f43e076ced Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Tue, 29 Dec 2015 13:43:35 +0100 Subject: ARM: tango: pass ARM arch level for smc.S allmodconfig is broken by the addition of the -mcpu=cortex-a9 flag for smc.S: arch/arm/mach-tango/smc.S:1:0: warning: switch -mcpu=cortex-a9 conflicts with -march=armv6k switch This sets the flag in the same way that all other platforms do, to fix the compile error. Signed-off-by: Arnd Bergmann diff --git a/arch/arm/mach-tango/Makefile b/arch/arm/mach-tango/Makefile index 0d7e2b5..99422ea 100644 --- a/arch/arm/mach-tango/Makefile +++ b/arch/arm/mach-tango/Makefile @@ -1,2 +1,3 @@ -asflags-y += -mcpu=cortex-a9 +plus_sec := $(call as-instr,.arch_extension sec,+sec) +AFLAGS_smc.o :=-Wa,-march=armv7-a$(plus_sec) obj-y += setup.o smc.o -- cgit v0.10.2 From d6bd05794f18673097ec5e62e577754649a5c632 Mon Sep 17 00:00:00 2001 From: Marc Gonzalez Date: Wed, 6 Jan 2016 10:27:43 +0100 Subject: ARM: tango: Fix UP build issues Move SMP setup to platsmp.c for consistency with other platforms. Signed-off-by: Marc Gonzalez Signed-off-by: Olof Johansson diff --git a/arch/arm/mach-tango/Makefile b/arch/arm/mach-tango/Makefile index 99422ea..f33935e 100644 --- a/arch/arm/mach-tango/Makefile +++ b/arch/arm/mach-tango/Makefile @@ -1,3 +1,5 @@ plus_sec := $(call as-instr,.arch_extension sec,+sec) -AFLAGS_smc.o :=-Wa,-march=armv7-a$(plus_sec) +AFLAGS_smc.o := -Wa,-march=armv7-a$(plus_sec) + obj-y += setup.o smc.o +obj-$(CONFIG_SMP) += platsmp.o diff --git a/arch/arm/mach-tango/platsmp.c b/arch/arm/mach-tango/platsmp.c new file mode 100644 index 0000000..a18d5a3 --- /dev/null +++ b/arch/arm/mach-tango/platsmp.c @@ -0,0 +1,16 @@ +#include +#include +#include "smc.h" + +static int tango_boot_secondary(unsigned int cpu, struct task_struct *idle) +{ + tango_set_aux_boot_addr(virt_to_phys(secondary_startup)); + tango_start_aux_core(cpu); + return 0; +} + +static struct smp_operations tango_smp_ops __initdata = { + .smp_boot_secondary = tango_boot_secondary, +}; + +CPU_METHOD_OF_DECLARE(tango4_smp, "sigma,tango4-smp", &tango_smp_ops); diff --git a/arch/arm/mach-tango/setup.c b/arch/arm/mach-tango/setup.c index d869005..f14b6c7 100644 --- a/arch/arm/mach-tango/setup.c +++ b/arch/arm/mach-tango/setup.c @@ -1,21 +1,7 @@ -#include #include #include #include "smc.h" -static int tango4_boot_secondary(unsigned int cpu, struct task_struct *idle) -{ - tango_set_aux_boot_addr(virt_to_phys(secondary_startup)); - tango_start_aux_core(cpu); - return 0; -} - -static struct smp_operations tango4_smp_ops __initdata = { - .smp_boot_secondary = tango4_boot_secondary, -}; - -CPU_METHOD_OF_DECLARE(tango4_smp, "sigma,tango4-smp", &tango4_smp_ops); - static void tango_l2c_write(unsigned long val, unsigned int reg) { if (reg == L2X0_CTRL) -- cgit v0.10.2