From f9d29f1617eb1b2f1fd41622bd1a0fc51658d2f0 Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Mon, 20 Feb 2012 12:26:06 +0200 Subject: arm: omap3: voltage: fix channel configuration OMAP3 uses the default settings for VDD1 channel, otherwise the settings will overlap with VDD2 and attempting to modify VDD1 voltage will actually change VDD2 voltage. Signed-off-by: Tero Kristo Reviewed-by: Kevin Hilman Signed-off-by: Kevin Hilman diff --git a/arch/arm/mach-omap2/vc3xxx_data.c b/arch/arm/mach-omap2/vc3xxx_data.c index a5ec7f8f..5d8eaf3 100644 --- a/arch/arm/mach-omap2/vc3xxx_data.c +++ b/arch/arm/mach-omap2/vc3xxx_data.c @@ -46,6 +46,7 @@ static struct omap_vc_common omap3_vc_common = { }; struct omap_vc_channel omap3_vc_mpu = { + .flags = OMAP_VC_CHANNEL_DEFAULT, .common = &omap3_vc_common, .smps_sa_reg = OMAP3_PRM_VC_SMPS_SA_OFFSET, .smps_volra_reg = OMAP3_PRM_VC_SMPS_VOL_RA_OFFSET, -- cgit v0.10.2 From 23e22a5ed4a5ad26ef89c30decd414024f871664 Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Mon, 20 Feb 2012 12:26:07 +0200 Subject: arm: omap3: add common twl configurations for vdd1 and vdd2 VDD1 and VDD2 are the core voltage regulators on OMAP3. VDD1 is used to control MPU/IVA voltage, and VDD2 is used for CORE. These regulators are needed by DVFS. Voltage ranges for VDD1 and VDD2 are taken from twl4030/twl5030 data manuals: - SWCS019L : TWL4030 ES3.1 Data Manual rev L - SWCS030E : TWL5030 ES1.2 Data Manual rev E Signed-off-by: Tero Kristo Reviewed-by: Kevin Hilman Signed-off-by: Kevin Hilman diff --git a/arch/arm/mach-omap2/twl-common.c b/arch/arm/mach-omap2/twl-common.c index 10b20c6..913d6c3 100644 --- a/arch/arm/mach-omap2/twl-common.c +++ b/arch/arm/mach-omap2/twl-common.c @@ -126,6 +126,38 @@ static struct regulator_init_data omap3_vpll2_idata = { .consumer_supplies = omap3_vpll2_supplies, }; +static struct regulator_consumer_supply omap3_vdd1_supply[] = { + REGULATOR_SUPPLY("vcc", "mpu.0"), +}; + +static struct regulator_consumer_supply omap3_vdd2_supply[] = { + REGULATOR_SUPPLY("vcc", "l3_main.0"), +}; + +static struct regulator_init_data omap3_vdd1 = { + .constraints = { + .name = "vdd_mpu_iva", + .min_uV = 600000, + .max_uV = 1450000, + .valid_modes_mask = REGULATOR_MODE_NORMAL, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + }, + .num_consumer_supplies = ARRAY_SIZE(omap3_vdd1_supply), + .consumer_supplies = omap3_vdd1_supply, +}; + +static struct regulator_init_data omap3_vdd2 = { + .constraints = { + .name = "vdd_core", + .min_uV = 600000, + .max_uV = 1450000, + .valid_modes_mask = REGULATOR_MODE_NORMAL, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + }, + .num_consumer_supplies = ARRAY_SIZE(omap3_vdd2_supply), + .consumer_supplies = omap3_vdd2_supply, +}; + void __init omap3_pmic_get_config(struct twl4030_platform_data *pmic_data, u32 pdata_flags, u32 regulators_flags) { @@ -133,6 +165,10 @@ void __init omap3_pmic_get_config(struct twl4030_platform_data *pmic_data, pmic_data->irq_base = TWL4030_IRQ_BASE; if (!pmic_data->irq_end) pmic_data->irq_end = TWL4030_IRQ_END; + if (!pmic_data->vdd1) + pmic_data->vdd1 = &omap3_vdd1; + if (!pmic_data->vdd2) + pmic_data->vdd2 = &omap3_vdd2; /* Common platform data configurations */ if (pdata_flags & TWL_COMMON_PDATA_USB && !pmic_data->usb) -- cgit v0.10.2 From 49c008ecce1f9a549c12e8957668d60008ab0d79 Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Mon, 20 Feb 2012 12:26:08 +0200 Subject: arm: omap3: twl: add external controllers for core voltage regulators VDD1 and VDD2 now use voltage processor for controlling the regulators. This is done by passing additional voltdm data during the regulator init. Signed-off-by: Tero Kristo Reviewed-by: Kevin Hilman Signed-off-by: Kevin Hilman diff --git a/arch/arm/mach-omap2/twl-common.c b/arch/arm/mach-omap2/twl-common.c index 913d6c3..618fefb 100644 --- a/arch/arm/mach-omap2/twl-common.c +++ b/arch/arm/mach-omap2/twl-common.c @@ -31,12 +31,25 @@ #include "twl-common.h" #include "pm.h" +#include "voltage.h" static struct i2c_board_info __initdata pmic_i2c_board_info = { .addr = 0x48, .flags = I2C_CLIENT_WAKE, }; +static int twl_set_voltage(void *data, int target_uV) +{ + struct voltagedomain *voltdm = (struct voltagedomain *)data; + return voltdm_scale(voltdm, target_uV); +} + +static int twl_get_voltage(void *data) +{ + struct voltagedomain *voltdm = (struct voltagedomain *)data; + return voltdm_get_voltage(voltdm); +} + void __init omap_pmic_init(int bus, u32 clkrate, const char *pmic_type, int pmic_irq, struct twl4030_platform_data *pmic_data) @@ -158,6 +171,16 @@ static struct regulator_init_data omap3_vdd2 = { .consumer_supplies = omap3_vdd2_supply, }; +static struct twl_regulator_driver_data omap3_vdd1_drvdata = { + .get_voltage = twl_get_voltage, + .set_voltage = twl_set_voltage, +}; + +static struct twl_regulator_driver_data omap3_vdd2_drvdata = { + .get_voltage = twl_get_voltage, + .set_voltage = twl_set_voltage, +}; + void __init omap3_pmic_get_config(struct twl4030_platform_data *pmic_data, u32 pdata_flags, u32 regulators_flags) { @@ -165,10 +188,16 @@ void __init omap3_pmic_get_config(struct twl4030_platform_data *pmic_data, pmic_data->irq_base = TWL4030_IRQ_BASE; if (!pmic_data->irq_end) pmic_data->irq_end = TWL4030_IRQ_END; - if (!pmic_data->vdd1) + if (!pmic_data->vdd1) { + omap3_vdd1.driver_data = &omap3_vdd1_drvdata; + omap3_vdd1_drvdata.data = voltdm_lookup("mpu_iva"); pmic_data->vdd1 = &omap3_vdd1; - if (!pmic_data->vdd2) + } + if (!pmic_data->vdd2) { + omap3_vdd2.driver_data = &omap3_vdd2_drvdata; + omap3_vdd2_drvdata.data = voltdm_lookup("core"); pmic_data->vdd2 = &omap3_vdd2; + } /* Common platform data configurations */ if (pdata_flags & TWL_COMMON_PDATA_USB && !pmic_data->usb) -- cgit v0.10.2 From e160dda0f49f54deddd62e943e449a13430c2e8b Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Wed, 22 Feb 2012 12:40:40 +0200 Subject: arm: omap4: add common twl configurations for vdd1, vdd2 and vdd3 VDD1 is used for MPU voltage, VDD2 is for IVA and VDD3 is for CORE. These are needed by DVFS. This patch also adds external controller support for these regulators, the default I2C control channel can't be used to modify the voltages for these regulators on TWL6030. Signed-off-by: Tero Kristo Reviewed-by: Kevin Hilman Signed-off-by: Kevin Hilman diff --git a/arch/arm/mach-omap2/twl-common.c b/arch/arm/mach-omap2/twl-common.c index 618fefb..1ddad22 100644 --- a/arch/arm/mach-omap2/twl-common.c +++ b/arch/arm/mach-omap2/twl-common.c @@ -349,6 +349,70 @@ static struct regulator_init_data omap4_clk32kg_idata = { }, }; +static struct regulator_consumer_supply omap4_vdd1_supply[] = { + REGULATOR_SUPPLY("vcc", "mpu.0"), +}; + +static struct regulator_consumer_supply omap4_vdd2_supply[] = { + REGULATOR_SUPPLY("vcc", "iva.0"), +}; + +static struct regulator_consumer_supply omap4_vdd3_supply[] = { + REGULATOR_SUPPLY("vcc", "l3_main.0"), +}; + +static struct regulator_init_data omap4_vdd1 = { + .constraints = { + .name = "vdd_mpu", + .min_uV = 500000, + .max_uV = 1500000, + .valid_modes_mask = REGULATOR_MODE_NORMAL, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + }, + .num_consumer_supplies = ARRAY_SIZE(omap4_vdd1_supply), + .consumer_supplies = omap4_vdd1_supply, +}; + +static struct regulator_init_data omap4_vdd2 = { + .constraints = { + .name = "vdd_iva", + .min_uV = 500000, + .max_uV = 1500000, + .valid_modes_mask = REGULATOR_MODE_NORMAL, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + }, + .num_consumer_supplies = ARRAY_SIZE(omap4_vdd2_supply), + .consumer_supplies = omap4_vdd2_supply, +}; + +static struct regulator_init_data omap4_vdd3 = { + .constraints = { + .name = "vdd_core", + .min_uV = 500000, + .max_uV = 1500000, + .valid_modes_mask = REGULATOR_MODE_NORMAL, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + }, + .num_consumer_supplies = ARRAY_SIZE(omap4_vdd3_supply), + .consumer_supplies = omap4_vdd3_supply, +}; + + +static struct twl_regulator_driver_data omap4_vdd1_drvdata = { + .get_voltage = twl_get_voltage, + .set_voltage = twl_set_voltage, +}; + +static struct twl_regulator_driver_data omap4_vdd2_drvdata = { + .get_voltage = twl_get_voltage, + .set_voltage = twl_set_voltage, +}; + +static struct twl_regulator_driver_data omap4_vdd3_drvdata = { + .get_voltage = twl_get_voltage, + .set_voltage = twl_set_voltage, +}; + void __init omap4_pmic_get_config(struct twl4030_platform_data *pmic_data, u32 pdata_flags, u32 regulators_flags) { @@ -357,6 +421,24 @@ void __init omap4_pmic_get_config(struct twl4030_platform_data *pmic_data, if (!pmic_data->irq_end) pmic_data->irq_end = TWL6030_IRQ_END; + if (!pmic_data->vdd1) { + omap4_vdd1.driver_data = &omap4_vdd1_drvdata; + omap4_vdd1_drvdata.data = voltdm_lookup("mpu"); + pmic_data->vdd1 = &omap4_vdd1; + } + + if (!pmic_data->vdd2) { + omap4_vdd2.driver_data = &omap4_vdd2_drvdata; + omap4_vdd2_drvdata.data = voltdm_lookup("iva"); + pmic_data->vdd2 = &omap4_vdd2; + } + + if (!pmic_data->vdd3) { + omap4_vdd3.driver_data = &omap4_vdd3_drvdata; + omap4_vdd3_drvdata.data = voltdm_lookup("core"); + pmic_data->vdd3 = &omap4_vdd3; + } + /* Common platform data configurations */ if (pdata_flags & TWL_COMMON_PDATA_USB && !pmic_data->usb) pmic_data->usb = &omap4_usb_pdata; -- cgit v0.10.2 From c15f1d84bb3ddd668593e9bca53221a2f82e9e99 Mon Sep 17 00:00:00 2001 From: Kevin Hilman Date: Fri, 2 Mar 2012 14:08:57 -0800 Subject: ARM: OMAP2+: voltage: ensure voltage used is exact voltage from OPP table When using the SMPS regulators to scale voltages, the regulator framework may pass a minimum voltage that is not an exact OPP voltage. For the VC/VP controlled voltage domains, we must ensure that the voltage requested is the exact voltage from the OPP table. This is especially critical when using SR. To fix, voltdm_scale() uses the target voltage passed to walk through the OPP voltages until it finds a voltage that is >= one of the OPP voltages. Cc: Tero Kristo Cc: Nishanth Menon Signed-off-by: Kevin Hilman diff --git a/arch/arm/mach-omap2/voltage.c b/arch/arm/mach-omap2/voltage.c index 8a36342..4dc60e8 100644 --- a/arch/arm/mach-omap2/voltage.c +++ b/arch/arm/mach-omap2/voltage.c @@ -73,7 +73,8 @@ unsigned long voltdm_get_voltage(struct voltagedomain *voltdm) int voltdm_scale(struct voltagedomain *voltdm, unsigned long target_volt) { - int ret; + int ret, i; + unsigned long volt = 0; if (!voltdm || IS_ERR(voltdm)) { pr_warning("%s: VDD specified does not exist!\n", __func__); @@ -86,9 +87,23 @@ int voltdm_scale(struct voltagedomain *voltdm, return -ENODATA; } - ret = voltdm->scale(voltdm, target_volt); + /* Adjust voltage to the exact voltage from the OPP table */ + for (i = 0; voltdm->volt_data[i].volt_nominal != 0; i++) { + if (voltdm->volt_data[i].volt_nominal >= target_volt) { + volt = voltdm->volt_data[i].volt_nominal; + break; + } + } + + if (!volt) { + pr_warning("%s: not scaling. OPP voltage for %lu, not found.\n", + __func__, target_volt); + return -EINVAL; + } + + ret = voltdm->scale(voltdm, volt); if (!ret) - voltdm->nominal_volt = target_volt; + voltdm->nominal_volt = volt; return ret; } -- cgit v0.10.2 From 6ba5a69ee92c29c2ffc814dad6ac61c4cd49090c Mon Sep 17 00:00:00 2001 From: Paul Walmsley Date: Thu, 19 Apr 2012 13:33:49 -0600 Subject: ARM: OMAP2+: clockdomains: make {prm,cm}_clkdm common The PRM and CM implicit clockdomains will soon be used by OMAP44xx. So, make them common to OMAP2+ and modify the OMAP4 clockdomains code so use of these clockdomains doesn't crash the system. Signed-off-by: Paul Walmsley Cc: Rajendra Nayak diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index 49f92bc..d8604a3 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -118,16 +118,18 @@ obj-$(CONFIG_ARCH_OMAP4) += $(powerdomain-common) \ powerdomains44xx_data.o # PRCM clockdomain control -obj-$(CONFIG_ARCH_OMAP2) += clockdomain.o \ +clockdomain-common += clockdomain.o \ + clockdomains_common_data.o +obj-$(CONFIG_ARCH_OMAP2) += $(clockdomain-common) \ clockdomain2xxx_3xxx.o \ clockdomains2xxx_3xxx_data.o obj-$(CONFIG_SOC_OMAP2420) += clockdomains2420_data.o obj-$(CONFIG_SOC_OMAP2430) += clockdomains2430_data.o -obj-$(CONFIG_ARCH_OMAP3) += clockdomain.o \ +obj-$(CONFIG_ARCH_OMAP3) += $(clockdomain-common) \ clockdomain2xxx_3xxx.o \ clockdomains2xxx_3xxx_data.o \ clockdomains3xxx_data.o -obj-$(CONFIG_ARCH_OMAP4) += clockdomain.o \ +obj-$(CONFIG_ARCH_OMAP4) += $(clockdomain-common) \ clockdomain44xx.o \ clockdomains44xx_data.o diff --git a/arch/arm/mach-omap2/clockdomain44xx.c b/arch/arm/mach-omap2/clockdomain44xx.c index 935c7f0..4f04dd1 100644 --- a/arch/arm/mach-omap2/clockdomain44xx.c +++ b/arch/arm/mach-omap2/clockdomain44xx.c @@ -51,6 +51,9 @@ static int omap4_clkdm_clear_all_wkup_sleep_deps(struct clockdomain *clkdm) struct clkdm_dep *cd; u32 mask = 0; + if (!clkdm->prcm_partition) + return 0; + for (cd = clkdm->wkdep_srcs; cd && cd->clkdm_name; cd++) { if (!cd->clkdm) continue; /* only happens if data is erroneous */ @@ -103,6 +106,9 @@ static int omap4_clkdm_clk_disable(struct clockdomain *clkdm) { bool hwsup = false; + if (!clkdm->prcm_partition) + return 0; + hwsup = omap4_cminst_is_clkdm_in_hwsup(clkdm->prcm_partition, clkdm->cm_inst, clkdm->clkdm_offs); diff --git a/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c b/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c index 0a6a048..839145e1 100644 --- a/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c +++ b/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c @@ -89,13 +89,3 @@ struct clockdomain wkup_common_clkdm = { .pwrdm = { .name = "wkup_pwrdm" }, .dep_bit = OMAP_EN_WKUP_SHIFT, }; - -struct clockdomain prm_common_clkdm = { - .name = "prm_clkdm", - .pwrdm = { .name = "wkup_pwrdm" }, -}; - -struct clockdomain cm_common_clkdm = { - .name = "cm_clkdm", - .pwrdm = { .name = "core_pwrdm" }, -}; diff --git a/arch/arm/mach-omap2/clockdomains44xx_data.c b/arch/arm/mach-omap2/clockdomains44xx_data.c index bd7ed13..c534258 100644 --- a/arch/arm/mach-omap2/clockdomains44xx_data.c +++ b/arch/arm/mach-omap2/clockdomains44xx_data.c @@ -430,6 +430,8 @@ static struct clockdomain *clockdomains_omap44xx[] __initdata = { &l4_wkup_44xx_clkdm, &emu_sys_44xx_clkdm, &l3_dma_44xx_clkdm, + &prm_common_clkdm, + &cm_common_clkdm, NULL }; diff --git a/arch/arm/mach-omap2/clockdomains_common_data.c b/arch/arm/mach-omap2/clockdomains_common_data.c new file mode 100644 index 0000000..615b1f0 --- /dev/null +++ b/arch/arm/mach-omap2/clockdomains_common_data.c @@ -0,0 +1,24 @@ +/* + * OMAP2+-common clockdomain data + * + * Copyright (C) 2008-2012 Texas Instruments, Inc. + * Copyright (C) 2008-2010 Nokia Corporation + * + * Paul Walmsley, Jouni Högander + */ + +#include +#include + +#include "clockdomain.h" + +/* These are implicit clockdomains - they are never defined as such in TRM */ +struct clockdomain prm_common_clkdm = { + .name = "prm_clkdm", + .pwrdm = { .name = "wkup_pwrdm" }, +}; + +struct clockdomain cm_common_clkdm = { + .name = "cm_clkdm", + .pwrdm = { .name = "core_pwrdm" }, +}; -- cgit v0.10.2 From b050f688e1ef5b10a013d212993b54c67e22d2ec Mon Sep 17 00:00:00 2001 From: Ming Lei Date: Thu, 19 Apr 2012 13:33:50 -0600 Subject: ARM: OMAP4: hwmod data: introduce fdif(face detect module) hwmod MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add hwmod data for the OMAP4 FDIF IP block. This patch also includes a change (originally from Fernando Guzman Lugo ) to set a softreset delay for the FDIF IP block: http://www.spinics.net/lists/arm-kernel/msg161874.html Signed-off-by: Ming Lei Acked-by: Benoît Cousson Cc: Fernando Guzman Lugo [paul@pwsan.com: rearranged to match script output; fixed FDIF end address to match script data; wrote trivial changelog; combined the FDIF portion of Fernando's srst_udelay patch] Signed-off-by: Paul Walmsley diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c index 0d91dec..eb5e98d 100644 --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c @@ -263,7 +263,6 @@ static struct omap_hwmod omap44xx_mpu_private_hwmod = { * elm * emif1 * emif2 - * fdif * gpmc * gpu * hdq1w @@ -816,6 +815,56 @@ static struct omap_hwmod omap44xx_dss_venc_hwmod = { }; /* + * 'fdif' class + * face detection hw accelerator module + */ + +static struct omap_hwmod_class_sysconfig omap44xx_fdif_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + /* + * FDIF needs 100 OCP clk cycles delay after a softreset before + * accessing sysconfig again. + * The lowest frequency at the moment for L3 bus is 100 MHz, so + * 1usec delay is needed. Add an x2 margin to be safe (2 usecs). + * + * TODO: Indicate errata when available. + */ + .srst_udelay = 2, + .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS | + SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | + MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), + .sysc_fields = &omap_hwmod_sysc_type2, +}; + +static struct omap_hwmod_class omap44xx_fdif_hwmod_class = { + .name = "fdif", + .sysc = &omap44xx_fdif_sysc, +}; + +/* fdif */ +static struct omap_hwmod_irq_info omap44xx_fdif_irqs[] = { + { .irq = 69 + OMAP44XX_IRQ_GIC_START }, + { .irq = -1 } +}; + +static struct omap_hwmod omap44xx_fdif_hwmod = { + .name = "fdif", + .class = &omap44xx_fdif_hwmod_class, + .clkdm_name = "iss_clkdm", + .mpu_irqs = omap44xx_fdif_irqs, + .main_clk = "fdif_fck", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP4_CM_CAM_FDIF_CLKCTRL_OFFSET, + .context_offs = OMAP4_RM_CAM_FDIF_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* * 'gpio' class * general purpose io module */ @@ -2980,6 +3029,14 @@ static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; +/* fdif -> l3_main_2 */ +static struct omap_hwmod_ocp_if omap44xx_fdif__l3_main_2 = { + .master = &omap44xx_fdif_hwmod, + .slave = &omap44xx_l3_main_2_hwmod, + .clk = "l3_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + /* hsi -> l3_main_2 */ static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = { .master = &omap44xx_hsi_hwmod, @@ -3530,6 +3587,24 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = { .user = OCP_USER_MPU, }; +static struct omap_hwmod_addr_space omap44xx_fdif_addrs[] = { + { + .pa_start = 0x4a10a000, + .pa_end = 0x4a10a1ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_cfg -> fdif */ +static struct omap_hwmod_ocp_if omap44xx_l4_cfg__fdif = { + .master = &omap44xx_l4_cfg_hwmod, + .slave = &omap44xx_fdif_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_fdif_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = { { .pa_start = 0x4a310000, @@ -4687,6 +4762,7 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = { &omap44xx_mmc2__l3_main_1, &omap44xx_mpu__l3_main_1, &omap44xx_dma_system__l3_main_2, + &omap44xx_fdif__l3_main_2, &omap44xx_hsi__l3_main_2, &omap44xx_ipu__l3_main_2, &omap44xx_iss__l3_main_2, @@ -4728,6 +4804,7 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = { &omap44xx_l4_per__dss_rfbi, &omap44xx_l3_main_2__dss_venc, &omap44xx_l4_per__dss_venc, + &omap44xx_l4_cfg__fdif, &omap44xx_l4_wkup__gpio1, &omap44xx_l4_per__gpio2, &omap44xx_l4_per__gpio3, -- cgit v0.10.2 From a091c08e65ebf7a06c0bdf563f00e77961d3b49c Mon Sep 17 00:00:00 2001 From: Paul Walmsley Date: Thu, 19 Apr 2012 13:33:50 -0600 Subject: ARM: OMAP4: hwmod data: add HDQ/1-wire MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add the HDQ/1-wire hwmod and associated interconnect data. The HDQ/1-wire IP block is a low-speed serial interconnect. Signed-off-by: Paul Walmsley Signed-off-by: Benoît Cousson diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c index eb5e98d..0eeea88 100644 --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c @@ -265,7 +265,6 @@ static struct omap_hwmod omap44xx_mpu_private_hwmod = { * emif2 * gpmc * gpu - * hdq1w * mcasp * mpu_c0 * mpu_c1 @@ -1067,6 +1066,47 @@ static struct omap_hwmod omap44xx_gpio6_hwmod = { }; /* + * 'hdq1w' class + * hdq / 1-wire serial interface controller + */ + +static struct omap_hwmod_class_sysconfig omap44xx_hdq1w_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0014, + .syss_offs = 0x0018, + .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET | + SYSS_HAS_RESET_STATUS), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap44xx_hdq1w_hwmod_class = { + .name = "hdq1w", + .sysc = &omap44xx_hdq1w_sysc, +}; + +/* hdq1w */ +static struct omap_hwmod_irq_info omap44xx_hdq1w_irqs[] = { + { .irq = 58 + OMAP44XX_IRQ_GIC_START }, + { .irq = -1 } +}; + +static struct omap_hwmod omap44xx_hdq1w_hwmod = { + .name = "hdq1w", + .class = &omap44xx_hdq1w_hwmod_class, + .clkdm_name = "l4_per_clkdm", + .flags = HWMOD_INIT_NO_RESET, /* XXX temporary */ + .mpu_irqs = omap44xx_hdq1w_irqs, + .main_clk = "hdq1w_fck", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP4_CM_L4PER_HDQ1W_CLKCTRL_OFFSET, + .context_offs = OMAP4_RM_L4PER_HDQ1W_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* * 'hsi' class * mipi high-speed synchronous serial interface (multichannel and full-duplex * serial if) @@ -3713,6 +3753,24 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; +static struct omap_hwmod_addr_space omap44xx_hdq1w_addrs[] = { + { + .pa_start = 0x480b2000, + .pa_end = 0x480b201f, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> hdq1w */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__hdq1w = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_hdq1w_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_hdq1w_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + static struct omap_hwmod_addr_space omap44xx_hsi_addrs[] = { { .pa_start = 0x4a058000, @@ -4811,6 +4869,7 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = { &omap44xx_l4_per__gpio4, &omap44xx_l4_per__gpio5, &omap44xx_l4_per__gpio6, + &omap44xx_l4_per__hdq1w, &omap44xx_l4_cfg__hsi, &omap44xx_l4_per__i2c1, &omap44xx_l4_per__i2c2, -- cgit v0.10.2 From eb42b5d3997c3a7d0da6c3bb56c1a0055ba3b2be Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Beno=C3=AEt=20Cousson?= Date: Thu, 19 Apr 2012 13:33:51 -0600 Subject: ARM: OMAP4: hwmod data: add GPMC MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add the GPMC hwmod and associated interconnect data. The GPMC is a programmable parallel-bus memory controller. Signed-off-by: Benoît Cousson Signed-off-by: Paul Walmsley diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c index 0eeea88..c31ae9a 100644 --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c @@ -263,7 +263,6 @@ static struct omap_hwmod omap44xx_mpu_private_hwmod = { * elm * emif1 * emif2 - * gpmc * gpu * mcasp * mpu_c0 @@ -1066,6 +1065,53 @@ static struct omap_hwmod omap44xx_gpio6_hwmod = { }; /* + * 'gpmc' class + * general purpose memory controller + */ + +static struct omap_hwmod_class_sysconfig omap44xx_gpmc_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .syss_offs = 0x0014, + .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE | + SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap44xx_gpmc_hwmod_class = { + .name = "gpmc", + .sysc = &omap44xx_gpmc_sysc, +}; + +/* gpmc */ +static struct omap_hwmod_irq_info omap44xx_gpmc_irqs[] = { + { .irq = 20 + OMAP44XX_IRQ_GIC_START }, + { .irq = -1 } +}; + +static struct omap_hwmod_dma_info omap44xx_gpmc_sdma_reqs[] = { + { .dma_req = 3 + OMAP44XX_DMA_REQ_START }, + { .dma_req = -1 } +}; + +static struct omap_hwmod omap44xx_gpmc_hwmod = { + .name = "gpmc", + .class = &omap44xx_gpmc_hwmod_class, + .clkdm_name = "l3_2_clkdm", + .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET, + .mpu_irqs = omap44xx_gpmc_irqs, + .sdma_reqs = omap44xx_gpmc_sdma_reqs, + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET, + .context_offs = OMAP4_RM_L3_2_GPMC_CONTEXT_OFFSET, + .modulemode = MODULEMODE_HWCTRL, + }, + }, +}; + +/* * 'hdq1w' class * hdq / 1-wire serial interface controller */ @@ -3753,6 +3799,24 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; +static struct omap_hwmod_addr_space omap44xx_gpmc_addrs[] = { + { + .pa_start = 0x50000000, + .pa_end = 0x500003ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l3_main_2 -> gpmc */ +static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpmc = { + .master = &omap44xx_l3_main_2_hwmod, + .slave = &omap44xx_gpmc_hwmod, + .clk = "l3_div_ck", + .addr = omap44xx_gpmc_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + static struct omap_hwmod_addr_space omap44xx_hdq1w_addrs[] = { { .pa_start = 0x480b2000, @@ -4869,6 +4933,7 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = { &omap44xx_l4_per__gpio4, &omap44xx_l4_per__gpio5, &omap44xx_l4_per__gpio6, + &omap44xx_l3_main_2__gpmc, &omap44xx_l4_per__hdq1w, &omap44xx_l4_cfg__hsi, &omap44xx_l4_per__i2c1, -- cgit v0.10.2 From bf30f950ac6b3ba904b90afa0fe12de78f2cf5a1 Mon Sep 17 00:00:00 2001 From: Paul Walmsley Date: Thu, 19 Apr 2012 13:33:52 -0600 Subject: ARM: OMAP4: hwmod data: add EMIF1 and 2 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add the EMIF1 and 2 hwmods and associated interconnect data. The EMIFs are SDRAM interface IP blocks. Signed-off-by: Paul Walmsley Signed-off-by: Benoît Cousson diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c index c31ae9a..476e98a 100644 --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c @@ -261,8 +261,6 @@ static struct omap_hwmod omap44xx_mpu_private_hwmod = { * efuse_ctrl_cust * efuse_ctrl_std * elm - * emif1 - * emif2 * gpu * mcasp * mpu_c0 @@ -813,6 +811,64 @@ static struct omap_hwmod omap44xx_dss_venc_hwmod = { }; /* + * 'emif' class + * external memory interface no1 + */ + +static struct omap_hwmod_class_sysconfig omap44xx_emif_sysc = { + .rev_offs = 0x0000, +}; + +static struct omap_hwmod_class omap44xx_emif_hwmod_class = { + .name = "emif", + .sysc = &omap44xx_emif_sysc, +}; + +/* emif1 */ +static struct omap_hwmod_irq_info omap44xx_emif1_irqs[] = { + { .irq = 110 + OMAP44XX_IRQ_GIC_START }, + { .irq = -1 } +}; + +static struct omap_hwmod omap44xx_emif1_hwmod = { + .name = "emif1", + .class = &omap44xx_emif_hwmod_class, + .clkdm_name = "l3_emif_clkdm", + .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET, + .mpu_irqs = omap44xx_emif1_irqs, + .main_clk = "ddrphy_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_1_CLKCTRL_OFFSET, + .context_offs = OMAP4_RM_MEMIF_EMIF_1_CONTEXT_OFFSET, + .modulemode = MODULEMODE_HWCTRL, + }, + }, +}; + +/* emif2 */ +static struct omap_hwmod_irq_info omap44xx_emif2_irqs[] = { + { .irq = 111 + OMAP44XX_IRQ_GIC_START }, + { .irq = -1 } +}; + +static struct omap_hwmod omap44xx_emif2_hwmod = { + .name = "emif2", + .class = &omap44xx_emif_hwmod_class, + .clkdm_name = "l3_emif_clkdm", + .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET, + .mpu_irqs = omap44xx_emif2_irqs, + .main_clk = "ddrphy_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_2_CLKCTRL_OFFSET, + .context_offs = OMAP4_RM_MEMIF_EMIF_2_CONTEXT_OFFSET, + .modulemode = MODULEMODE_HWCTRL, + }, + }, +}; + +/* * 'fdif' class * face detection hw accelerator module */ @@ -3673,6 +3729,42 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = { .user = OCP_USER_MPU, }; +static struct omap_hwmod_addr_space omap44xx_emif1_addrs[] = { + { + .pa_start = 0x4c000000, + .pa_end = 0x4c0000ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* emif_fw -> emif1 */ +static struct omap_hwmod_ocp_if omap44xx_emif_fw__emif1 = { + .master = &omap44xx_emif_fw_hwmod, + .slave = &omap44xx_emif1_hwmod, + .clk = "l3_div_ck", + .addr = omap44xx_emif1_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_emif2_addrs[] = { + { + .pa_start = 0x4d000000, + .pa_end = 0x4d0000ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* emif_fw -> emif2 */ +static struct omap_hwmod_ocp_if omap44xx_emif_fw__emif2 = { + .master = &omap44xx_emif_fw_hwmod, + .slave = &omap44xx_emif2_hwmod, + .clk = "l3_div_ck", + .addr = omap44xx_emif2_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + static struct omap_hwmod_addr_space omap44xx_fdif_addrs[] = { { .pa_start = 0x4a10a000, @@ -4926,6 +5018,8 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = { &omap44xx_l4_per__dss_rfbi, &omap44xx_l3_main_2__dss_venc, &omap44xx_l4_per__dss_venc, + &omap44xx_emif_fw__emif1, + &omap44xx_emif_fw__emif2, &omap44xx_l4_cfg__fdif, &omap44xx_l4_wkup__gpio1, &omap44xx_l4_per__gpio2, -- cgit v0.10.2 From 9def390ea3f7a8a61d33c18f3af1783293b5608f Mon Sep 17 00:00:00 2001 From: Paul Walmsley Date: Thu, 19 Apr 2012 13:33:53 -0600 Subject: ARM: OMAP4: hwmod data: add GPU MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add the GPU hwmod and associated interconnect data. The GPU is a graphics accelerator. Signed-off-by: Paul Walmsley Signed-off-by: Benoît Cousson diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c index 476e98a..2f25772 100644 --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c @@ -261,7 +261,6 @@ static struct omap_hwmod omap44xx_mpu_private_hwmod = { * efuse_ctrl_cust * efuse_ctrl_std * elm - * gpu * mcasp * mpu_c0 * mpu_c1 @@ -1168,6 +1167,47 @@ static struct omap_hwmod omap44xx_gpmc_hwmod = { }; /* + * 'gpu' class + * 2d/3d graphics accelerator + */ + +static struct omap_hwmod_class_sysconfig omap44xx_gpu_sysc = { + .rev_offs = 0x1fc00, + .sysc_offs = 0x1fc10, + .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | + SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | + MSTANDBY_SMART | MSTANDBY_SMART_WKUP), + .sysc_fields = &omap_hwmod_sysc_type2, +}; + +static struct omap_hwmod_class omap44xx_gpu_hwmod_class = { + .name = "gpu", + .sysc = &omap44xx_gpu_sysc, +}; + +/* gpu */ +static struct omap_hwmod_irq_info omap44xx_gpu_irqs[] = { + { .irq = 21 + OMAP44XX_IRQ_GIC_START }, + { .irq = -1 } +}; + +static struct omap_hwmod omap44xx_gpu_hwmod = { + .name = "gpu", + .class = &omap44xx_gpu_hwmod_class, + .clkdm_name = "l3_gfx_clkdm", + .mpu_irqs = omap44xx_gpu_irqs, + .main_clk = "gpu_fck", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP4_CM_GFX_GFX_CLKCTRL_OFFSET, + .context_offs = OMAP4_RM_GFX_GFX_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* * 'hdq1w' class * hdq / 1-wire serial interface controller */ @@ -3179,6 +3219,14 @@ static struct omap_hwmod_ocp_if omap44xx_fdif__l3_main_2 = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; +/* gpu -> l3_main_2 */ +static struct omap_hwmod_ocp_if omap44xx_gpu__l3_main_2 = { + .master = &omap44xx_gpu_hwmod, + .slave = &omap44xx_l3_main_2_hwmod, + .clk = "l3_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + /* hsi -> l3_main_2 */ static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = { .master = &omap44xx_hsi_hwmod, @@ -3909,6 +3957,24 @@ static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpmc = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; +static struct omap_hwmod_addr_space omap44xx_gpu_addrs[] = { + { + .pa_start = 0x56000000, + .pa_end = 0x5600ffff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l3_main_2 -> gpu */ +static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpu = { + .master = &omap44xx_l3_main_2_hwmod, + .slave = &omap44xx_gpu_hwmod, + .clk = "l3_div_ck", + .addr = omap44xx_gpu_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + static struct omap_hwmod_addr_space omap44xx_hdq1w_addrs[] = { { .pa_start = 0x480b2000, @@ -4977,6 +5043,7 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = { &omap44xx_mpu__l3_main_1, &omap44xx_dma_system__l3_main_2, &omap44xx_fdif__l3_main_2, + &omap44xx_gpu__l3_main_2, &omap44xx_hsi__l3_main_2, &omap44xx_ipu__l3_main_2, &omap44xx_iss__l3_main_2, @@ -5028,6 +5095,7 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = { &omap44xx_l4_per__gpio5, &omap44xx_l4_per__gpio6, &omap44xx_l3_main_2__gpmc, + &omap44xx_l3_main_2__gpu, &omap44xx_l4_per__hdq1w, &omap44xx_l4_cfg__hsi, &omap44xx_l4_per__i2c1, -- cgit v0.10.2 From 1e3b5e59532c6f1f57e38b8f8ad7e74bc7cb6f4e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Beno=C3=AEt=20Cousson?= Date: Thu, 19 Apr 2012 13:33:53 -0600 Subject: ARM: OMAP4: hwmod data: add the Slimbus IP blocks MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add the Slimbus hwmods and associated interconnect data. The Slimbus IP blocks implement a two-wire serial interface. Signed-off-by: Benoît Cousson Signed-off-by: Paul Walmsley diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c index 2f25772..4c5add7 100644 --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c @@ -271,8 +271,6 @@ static struct omap_hwmod omap44xx_mpu_private_hwmod = { * prm * scrm * sl2if - * slimbus1 - * slimbus2 * usb_host_fs * usb_host_hs * usb_phy_cm @@ -2248,6 +2246,110 @@ static struct omap_hwmod omap44xx_mpu_hwmod = { }; /* + * 'slimbus' class + * bidirectional, multi-drop, multi-channel two-line serial interface between + * the device and external components + */ + +static struct omap_hwmod_class_sysconfig omap44xx_slimbus_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE | + SYSC_HAS_SOFTRESET), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | + SIDLE_SMART_WKUP), + .sysc_fields = &omap_hwmod_sysc_type2, +}; + +static struct omap_hwmod_class omap44xx_slimbus_hwmod_class = { + .name = "slimbus", + .sysc = &omap44xx_slimbus_sysc, +}; + +/* slimbus1 */ +static struct omap_hwmod_irq_info omap44xx_slimbus1_irqs[] = { + { .irq = 97 + OMAP44XX_IRQ_GIC_START }, + { .irq = -1 } +}; + +static struct omap_hwmod_dma_info omap44xx_slimbus1_sdma_reqs[] = { + { .name = "tx0", .dma_req = 84 + OMAP44XX_DMA_REQ_START }, + { .name = "tx1", .dma_req = 85 + OMAP44XX_DMA_REQ_START }, + { .name = "tx2", .dma_req = 86 + OMAP44XX_DMA_REQ_START }, + { .name = "tx3", .dma_req = 87 + OMAP44XX_DMA_REQ_START }, + { .name = "rx0", .dma_req = 88 + OMAP44XX_DMA_REQ_START }, + { .name = "rx1", .dma_req = 89 + OMAP44XX_DMA_REQ_START }, + { .name = "rx2", .dma_req = 90 + OMAP44XX_DMA_REQ_START }, + { .name = "rx3", .dma_req = 91 + OMAP44XX_DMA_REQ_START }, + { .dma_req = -1 } +}; + +static struct omap_hwmod_opt_clk slimbus1_opt_clks[] = { + { .role = "fclk_1", .clk = "slimbus1_fclk_1" }, + { .role = "fclk_0", .clk = "slimbus1_fclk_0" }, + { .role = "fclk_2", .clk = "slimbus1_fclk_2" }, + { .role = "slimbus_clk", .clk = "slimbus1_slimbus_clk" }, +}; + +static struct omap_hwmod omap44xx_slimbus1_hwmod = { + .name = "slimbus1", + .class = &omap44xx_slimbus_hwmod_class, + .clkdm_name = "abe_clkdm", + .mpu_irqs = omap44xx_slimbus1_irqs, + .sdma_reqs = omap44xx_slimbus1_sdma_reqs, + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP4_CM1_ABE_SLIMBUS_CLKCTRL_OFFSET, + .context_offs = OMAP4_RM_ABE_SLIMBUS_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .opt_clks = slimbus1_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(slimbus1_opt_clks), +}; + +/* slimbus2 */ +static struct omap_hwmod_irq_info omap44xx_slimbus2_irqs[] = { + { .irq = 98 + OMAP44XX_IRQ_GIC_START }, + { .irq = -1 } +}; + +static struct omap_hwmod_dma_info omap44xx_slimbus2_sdma_reqs[] = { + { .name = "tx0", .dma_req = 92 + OMAP44XX_DMA_REQ_START }, + { .name = "tx1", .dma_req = 93 + OMAP44XX_DMA_REQ_START }, + { .name = "tx2", .dma_req = 94 + OMAP44XX_DMA_REQ_START }, + { .name = "tx3", .dma_req = 95 + OMAP44XX_DMA_REQ_START }, + { .name = "rx0", .dma_req = 96 + OMAP44XX_DMA_REQ_START }, + { .name = "rx1", .dma_req = 97 + OMAP44XX_DMA_REQ_START }, + { .name = "rx2", .dma_req = 98 + OMAP44XX_DMA_REQ_START }, + { .name = "rx3", .dma_req = 99 + OMAP44XX_DMA_REQ_START }, + { .dma_req = -1 } +}; + +static struct omap_hwmod_opt_clk slimbus2_opt_clks[] = { + { .role = "fclk_1", .clk = "slimbus2_fclk_1" }, + { .role = "fclk_0", .clk = "slimbus2_fclk_0" }, + { .role = "slimbus_clk", .clk = "slimbus2_slimbus_clk" }, +}; + +static struct omap_hwmod omap44xx_slimbus2_hwmod = { + .name = "slimbus2", + .class = &omap44xx_slimbus_hwmod_class, + .clkdm_name = "l4_per_clkdm", + .mpu_irqs = omap44xx_slimbus2_irqs, + .sdma_reqs = omap44xx_slimbus2_sdma_reqs, + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP4_CM_L4PER_SLIMBUS2_CLKCTRL_OFFSET, + .context_offs = OMAP4_RM_L4PER_SLIMBUS2_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .opt_clks = slimbus2_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(slimbus2_opt_clks), +}; + +/* * 'smartreflex' class * smartreflex module (monitor silicon performance and outputs a measure of * performance error) @@ -4493,6 +4595,60 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; +static struct omap_hwmod_addr_space omap44xx_slimbus1_addrs[] = { + { + .pa_start = 0x4012c000, + .pa_end = 0x4012c3ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_abe -> slimbus1 */ +static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1 = { + .master = &omap44xx_l4_abe_hwmod, + .slave = &omap44xx_slimbus1_hwmod, + .clk = "ocp_abe_iclk", + .addr = omap44xx_slimbus1_addrs, + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_addr_space omap44xx_slimbus1_dma_addrs[] = { + { + .pa_start = 0x4902c000, + .pa_end = 0x4902c3ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_abe -> slimbus1 (dma) */ +static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1_dma = { + .master = &omap44xx_l4_abe_hwmod, + .slave = &omap44xx_slimbus1_hwmod, + .clk = "ocp_abe_iclk", + .addr = omap44xx_slimbus1_dma_addrs, + .user = OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_slimbus2_addrs[] = { + { + .pa_start = 0x48076000, + .pa_end = 0x480763ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> slimbus2 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__slimbus2 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_slimbus2_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_slimbus2_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = { { .pa_start = 0x4a0dd000, @@ -5125,6 +5281,9 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = { &omap44xx_l4_per__mmc3, &omap44xx_l4_per__mmc4, &omap44xx_l4_per__mmc5, + &omap44xx_l4_abe__slimbus1, + &omap44xx_l4_abe__slimbus1_dma, + &omap44xx_l4_per__slimbus2, &omap44xx_l4_cfg__smartreflex_core, &omap44xx_l4_cfg__smartreflex_iva, &omap44xx_l4_cfg__smartreflex_mpu, -- cgit v0.10.2 From 896d4e98c0b5e3a9894b62a88fe4798eef14ba02 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Beno=C3=AEt=20Cousson?= Date: Thu, 19 Apr 2012 13:33:54 -0600 Subject: ARM: OMAP4: hwmod data: add McASP MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add the McASP hwmod and associated interconnect data. The McASP is a general-purpose audio serial port. Signed-off-by: Benoît Cousson Signed-off-by: Paul Walmsley diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c index 4c5add7..330cafe 100644 --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c @@ -261,7 +261,6 @@ static struct omap_hwmod omap44xx_mpu_private_hwmod = { * efuse_ctrl_cust * efuse_ctrl_std * elm - * mcasp * mpu_c0 * mpu_c1 * ocmc_ram @@ -1670,6 +1669,58 @@ static struct omap_hwmod omap44xx_mailbox_hwmod = { }; /* + * 'mcasp' class + * multi-channel audio serial port controller + */ + +/* The IP is not compliant to type1 / type2 scheme */ +static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_mcasp = { + .sidle_shift = 0, +}; + +static struct omap_hwmod_class_sysconfig omap44xx_mcasp_sysc = { + .sysc_offs = 0x0004, + .sysc_flags = SYSC_HAS_SIDLEMODE, + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | + SIDLE_SMART_WKUP), + .sysc_fields = &omap_hwmod_sysc_type_mcasp, +}; + +static struct omap_hwmod_class omap44xx_mcasp_hwmod_class = { + .name = "mcasp", + .sysc = &omap44xx_mcasp_sysc, +}; + +/* mcasp */ +static struct omap_hwmod_irq_info omap44xx_mcasp_irqs[] = { + { .name = "arevt", .irq = 108 + OMAP44XX_IRQ_GIC_START }, + { .name = "axevt", .irq = 109 + OMAP44XX_IRQ_GIC_START }, + { .irq = -1 } +}; + +static struct omap_hwmod_dma_info omap44xx_mcasp_sdma_reqs[] = { + { .name = "axevt", .dma_req = 7 + OMAP44XX_DMA_REQ_START }, + { .name = "arevt", .dma_req = 10 + OMAP44XX_DMA_REQ_START }, + { .dma_req = -1 } +}; + +static struct omap_hwmod omap44xx_mcasp_hwmod = { + .name = "mcasp", + .class = &omap44xx_mcasp_hwmod_class, + .clkdm_name = "abe_clkdm", + .mpu_irqs = omap44xx_mcasp_irqs, + .sdma_reqs = omap44xx_mcasp_sdma_reqs, + .main_clk = "mcasp_fck", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP4_CM1_ABE_MCASP_CLKCTRL_OFFSET, + .context_offs = OMAP4_RM_ABE_MCASP_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* * 'mcbsp' class * multi channel buffered serial port controller */ @@ -4265,6 +4316,42 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; +static struct omap_hwmod_addr_space omap44xx_mcasp_addrs[] = { + { + .pa_start = 0x40128000, + .pa_end = 0x401283ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_abe -> mcasp */ +static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp = { + .master = &omap44xx_l4_abe_hwmod, + .slave = &omap44xx_mcasp_hwmod, + .clk = "ocp_abe_iclk", + .addr = omap44xx_mcasp_addrs, + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_addr_space omap44xx_mcasp_dma_addrs[] = { + { + .pa_start = 0x49028000, + .pa_end = 0x490283ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_abe -> mcasp (dma) */ +static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp_dma = { + .master = &omap44xx_l4_abe_hwmod, + .slave = &omap44xx_mcasp_hwmod, + .clk = "ocp_abe_iclk", + .addr = omap44xx_mcasp_dma_addrs, + .user = OCP_USER_SDMA, +}; + static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = { { .name = "mpu", @@ -5263,6 +5350,8 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = { &omap44xx_l3_main_2__iva, &omap44xx_l4_wkup__kbd, &omap44xx_l4_cfg__mailbox, + &omap44xx_l4_abe__mcasp, + &omap44xx_l4_abe__mcasp_dma, &omap44xx_l4_abe__mcbsp1, &omap44xx_l4_abe__mcbsp1_dma, &omap44xx_l4_abe__mcbsp2, -- cgit v0.10.2 From 42b9e38728d5b810b2f1c1d15d6ee170c8eca9d6 Mon Sep 17 00:00:00 2001 From: Paul Walmsley Date: Thu, 19 Apr 2012 13:33:54 -0600 Subject: ARM: OMAP4: hwmod data: add some interconnect-related IP blocks MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add the SL2 interface IP block and interconnect data. The SL2 is related to the IVA-HD subsystem. Add IP block and interconnect data for the C2C ("Chip-to-chip") interconnect. This can provide a direct system interconnect link to other devices stacked on the OMAP package. Add the ELM IP block and interconnect data. The ELM can be used to locate errors in NAND flash connected to the GPMC. Signed-off-by: Paul Walmsley Signed-off-by: Benoît Cousson diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c index 330cafe..62b283f 100644 --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c @@ -51,6 +51,27 @@ */ /* + * 'c2c_target_fw' class + * instance(s): c2c_target_fw + */ +static struct omap_hwmod_class omap44xx_c2c_target_fw_hwmod_class = { + .name = "c2c_target_fw", +}; + +/* c2c_target_fw */ +static struct omap_hwmod omap44xx_c2c_target_fw_hwmod = { + .name = "c2c_target_fw", + .class = &omap44xx_c2c_target_fw_hwmod_class, + .clkdm_name = "d2d_clkdm", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP4_CM_D2D_SAD2D_FW_CLKCTRL_OFFSET, + .context_offs = OMAP4_RM_D2D_SAD2D_FW_CONTEXT_OFFSET, + }, + }, +}; + +/* * 'dmm' class * instance(s): dmm */ @@ -249,8 +270,6 @@ static struct omap_hwmod omap44xx_mpu_private_hwmod = { * - They still need to be validated with the driver * properly adapted to omap_hwmod / omap_device * - * c2c - * c2c_target_fw * cm_core * cm_core_aon * ctrl_module_core @@ -260,7 +279,6 @@ static struct omap_hwmod omap44xx_mpu_private_hwmod = { * debugss * efuse_ctrl_cust * efuse_ctrl_std - * elm * mpu_c0 * mpu_c1 * ocmc_ram @@ -269,7 +287,6 @@ static struct omap_hwmod omap44xx_mpu_private_hwmod = { * prcm_mpu * prm * scrm - * sl2if * usb_host_fs * usb_host_hs * usb_phy_cm @@ -332,6 +349,41 @@ static struct omap_hwmod omap44xx_aess_hwmod = { }; /* + * 'c2c' class + * chip 2 chip interface used to plug the ape soc (omap) with an external modem + * soc + */ + +static struct omap_hwmod_class omap44xx_c2c_hwmod_class = { + .name = "c2c", +}; + +/* c2c */ +static struct omap_hwmod_irq_info omap44xx_c2c_irqs[] = { + { .irq = 88 + OMAP44XX_IRQ_GIC_START }, + { .irq = -1 } +}; + +static struct omap_hwmod_dma_info omap44xx_c2c_sdma_reqs[] = { + { .dma_req = 68 + OMAP44XX_DMA_REQ_START }, + { .dma_req = -1 } +}; + +static struct omap_hwmod omap44xx_c2c_hwmod = { + .name = "c2c", + .class = &omap44xx_c2c_hwmod_class, + .clkdm_name = "d2d_clkdm", + .mpu_irqs = omap44xx_c2c_irqs, + .sdma_reqs = omap44xx_c2c_sdma_reqs, + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP4_CM_D2D_SAD2D_CLKCTRL_OFFSET, + .context_offs = OMAP4_RM_D2D_SAD2D_CONTEXT_OFFSET, + }, + }, +}; + +/* * 'counter' class * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock */ @@ -807,6 +859,46 @@ static struct omap_hwmod omap44xx_dss_venc_hwmod = { }; /* + * 'elm' class + * bch error location module + */ + +static struct omap_hwmod_class_sysconfig omap44xx_elm_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .syss_offs = 0x0014, + .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | + SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | + SYSS_HAS_RESET_STATUS), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap44xx_elm_hwmod_class = { + .name = "elm", + .sysc = &omap44xx_elm_sysc, +}; + +/* elm */ +static struct omap_hwmod_irq_info omap44xx_elm_irqs[] = { + { .irq = 4 + OMAP44XX_IRQ_GIC_START }, + { .irq = -1 } +}; + +static struct omap_hwmod omap44xx_elm_hwmod = { + .name = "elm", + .class = &omap44xx_elm_hwmod_class, + .clkdm_name = "l4_per_clkdm", + .mpu_irqs = omap44xx_elm_irqs, + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP4_CM_L4PER_ELM_CLKCTRL_OFFSET, + .context_offs = OMAP4_RM_L4PER_ELM_CONTEXT_OFFSET, + }, + }, +}; + +/* * 'emif' class * external memory interface no1 */ @@ -2297,6 +2389,29 @@ static struct omap_hwmod omap44xx_mpu_hwmod = { }; /* + * 'sl2if' class + * shared level 2 memory interface + */ + +static struct omap_hwmod_class omap44xx_sl2if_hwmod_class = { + .name = "sl2if", +}; + +/* sl2if */ +static struct omap_hwmod omap44xx_sl2if_hwmod = { + .name = "sl2if", + .class = &omap44xx_sl2if_hwmod_class, + .clkdm_name = "ivahd_clkdm", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP4_CM_IVAHD_SL2_CLKCTRL_OFFSET, + .context_offs = OMAP4_RM_IVAHD_SL2_CONTEXT_OFFSET, + .modulemode = MODULEMODE_HWCTRL, + }, + }, +}; + +/* * 'slimbus' class * bidirectional, multi-drop, multi-channel two-line serial interface between * the device and external components @@ -3222,6 +3337,32 @@ static struct omap_hwmod omap44xx_wd_timer3_hwmod = { * interfaces */ +static struct omap_hwmod_addr_space omap44xx_c2c_target_fw_addrs[] = { + { + .pa_start = 0x4a204000, + .pa_end = 0x4a2040ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* c2c -> c2c_target_fw */ +static struct omap_hwmod_ocp_if omap44xx_c2c__c2c_target_fw = { + .master = &omap44xx_c2c_hwmod, + .slave = &omap44xx_c2c_target_fw_hwmod, + .clk = "div_core_ck", + .addr = omap44xx_c2c_target_fw_addrs, + .user = OCP_USER_MPU, +}; + +/* l4_cfg -> c2c_target_fw */ +static struct omap_hwmod_ocp_if omap44xx_l4_cfg__c2c_target_fw = { + .master = &omap44xx_l4_cfg_hwmod, + .slave = &omap44xx_c2c_target_fw_hwmod, + .clk = "l4_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + /* l3_main_1 -> dmm */ static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = { .master = &omap44xx_l3_main_1_hwmod, @@ -3248,6 +3389,14 @@ static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = { .user = OCP_USER_MPU, }; +/* c2c -> emif_fw */ +static struct omap_hwmod_ocp_if omap44xx_c2c__emif_fw = { + .master = &omap44xx_c2c_hwmod, + .slave = &omap44xx_emif_fw_hwmod, + .clk = "div_core_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + /* dmm -> emif_fw */ static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = { .master = &omap44xx_dmm_hwmod, @@ -3356,6 +3505,14 @@ static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = { .user = OCP_USER_MPU, }; +/* c2c_target_fw -> l3_main_2 */ +static struct omap_hwmod_ocp_if omap44xx_c2c_target_fw__l3_main_2 = { + .master = &omap44xx_c2c_target_fw_hwmod, + .slave = &omap44xx_l3_main_2_hwmod, + .clk = "l3_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + /* dma_system -> l3_main_2 */ static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = { .master = &omap44xx_dma_system_hwmod, @@ -3588,6 +3745,14 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess_dma = { .user = OCP_USER_SDMA, }; +/* l3_main_2 -> c2c */ +static struct omap_hwmod_ocp_if omap44xx_l3_main_2__c2c = { + .master = &omap44xx_l3_main_2_hwmod, + .slave = &omap44xx_c2c_hwmod, + .clk = "l3_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + static struct omap_hwmod_addr_space omap44xx_counter_32k_addrs[] = { { .pa_start = 0x4a304000, @@ -3670,6 +3835,14 @@ static struct omap_hwmod_ocp_if omap44xx_dsp__iva = { .user = OCP_USER_DSP, }; +/* dsp -> sl2if */ +static struct omap_hwmod_ocp_if omap44xx_dsp__sl2if = { + .master = &omap44xx_dsp_hwmod, + .slave = &omap44xx_sl2if_hwmod, + .clk = "dpll_iva_m5x2_ck", + .user = OCP_USER_DSP, +}; + /* l4_cfg -> dsp */ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = { .master = &omap44xx_l4_cfg_hwmod, @@ -3930,6 +4103,24 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = { .user = OCP_USER_MPU, }; +static struct omap_hwmod_addr_space omap44xx_elm_addrs[] = { + { + .pa_start = 0x48078000, + .pa_end = 0x48078fff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> elm */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__elm = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_elm_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_elm_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + static struct omap_hwmod_addr_space omap44xx_emif1_addrs[] = { { .pa_start = 0x4c000000, @@ -4262,6 +4453,14 @@ static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; +/* iva -> sl2if */ +static struct omap_hwmod_ocp_if omap44xx_iva__sl2if = { + .master = &omap44xx_iva_hwmod, + .slave = &omap44xx_sl2if_hwmod, + .clk = "dpll_iva_m5x2_ck", + .user = OCP_USER_IVA, +}; + static struct omap_hwmod_addr_space omap44xx_iva_addrs[] = { { .pa_start = 0x5a000000, @@ -4682,6 +4881,14 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; +/* l3_main_2 -> sl2if */ +static struct omap_hwmod_ocp_if omap44xx_l3_main_2__sl2if = { + .master = &omap44xx_l3_main_2_hwmod, + .slave = &omap44xx_sl2if_hwmod, + .clk = "l3_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + static struct omap_hwmod_addr_space omap44xx_slimbus1_addrs[] = { { .pa_start = 0x4012c000, @@ -5271,8 +5478,11 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = { }; static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = { + &omap44xx_c2c__c2c_target_fw, + &omap44xx_l4_cfg__c2c_target_fw, &omap44xx_l3_main_1__dmm, &omap44xx_mpu__dmm, + &omap44xx_c2c__emif_fw, &omap44xx_dmm__emif_fw, &omap44xx_l4_cfg__emif_fw, &omap44xx_iva__l3_instr, @@ -5284,6 +5494,7 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = { &omap44xx_mmc1__l3_main_1, &omap44xx_mmc2__l3_main_1, &omap44xx_mpu__l3_main_1, + &omap44xx_c2c_target_fw__l3_main_2, &omap44xx_dma_system__l3_main_2, &omap44xx_fdif__l3_main_2, &omap44xx_gpu__l3_main_2, @@ -5308,11 +5519,13 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = { &omap44xx_mpu__mpu_private, &omap44xx_l4_abe__aess, &omap44xx_l4_abe__aess_dma, + &omap44xx_l3_main_2__c2c, &omap44xx_l4_wkup__counter_32k, &omap44xx_l4_cfg__dma_system, &omap44xx_l4_abe__dmic, &omap44xx_l4_abe__dmic_dma, &omap44xx_dsp__iva, + &omap44xx_dsp__sl2if, &omap44xx_l4_cfg__dsp, &omap44xx_l3_main_2__dss, &omap44xx_l4_per__dss, @@ -5328,6 +5541,7 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = { &omap44xx_l4_per__dss_rfbi, &omap44xx_l3_main_2__dss_venc, &omap44xx_l4_per__dss_venc, + &omap44xx_l4_per__elm, &omap44xx_emif_fw__emif1, &omap44xx_emif_fw__emif2, &omap44xx_l4_cfg__fdif, @@ -5347,6 +5561,7 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = { &omap44xx_l4_per__i2c4, &omap44xx_l3_main_2__ipu, &omap44xx_l3_main_2__iss, + &omap44xx_iva__sl2if, &omap44xx_l3_main_2__iva, &omap44xx_l4_wkup__kbd, &omap44xx_l4_cfg__mailbox, @@ -5370,6 +5585,7 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = { &omap44xx_l4_per__mmc3, &omap44xx_l4_per__mmc4, &omap44xx_l4_per__mmc5, + &omap44xx_l3_main_2__sl2if, &omap44xx_l4_abe__slimbus1, &omap44xx_l4_abe__slimbus1_dma, &omap44xx_l4_per__slimbus2, diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h index 14dde32..c835b71 100644 --- a/arch/arm/plat-omap/include/plat/omap_hwmod.h +++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h @@ -214,6 +214,7 @@ struct omap_hwmod_addr_space { #define OCP_USER_MPU (1 << 0) #define OCP_USER_SDMA (1 << 1) #define OCP_USER_DSP (1 << 2) +#define OCP_USER_IVA (1 << 3) /* omap_hwmod_ocp_if.flags bits */ #define OCPIF_SWSUP_IDLE (1 << 0) -- cgit v0.10.2 From 0c6688753f9912c6a7013549ec31c8844020bbc1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Beno=C3=AEt=20Cousson?= Date: Thu, 19 Apr 2012 13:33:55 -0600 Subject: ARM: OMAP4: hwmod data: add remaining USB-related IP blocks MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add the OCP2SCP IP block and interconnect data. The OCP2SCP can be used in conjunction with the on-chip embedded USB PHY, associated with the OTG controller. Add the on-chip full-speed USB host controller IP block and interconnect data. Cc: Felipe Balbi Signed-off-by: Benoît Cousson Signed-off-by: Paul Walmsley diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c index 62b283f..c080fd6 100644 --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c @@ -282,15 +282,11 @@ static struct omap_hwmod omap44xx_mpu_private_hwmod = { * mpu_c0 * mpu_c1 * ocmc_ram - * ocp2scp_usb_phy * ocp_wp_noc * prcm_mpu * prm * scrm - * usb_host_fs - * usb_host_hs * usb_phy_cm - * usb_tll_hs * usim */ @@ -2389,6 +2385,36 @@ static struct omap_hwmod omap44xx_mpu_hwmod = { }; /* + * 'ocp2scp' class + * bridge to transform ocp interface protocol to scp (serial control port) + * protocol + */ + +static struct omap_hwmod_class omap44xx_ocp2scp_hwmod_class = { + .name = "ocp2scp", +}; + +/* ocp2scp_usb_phy */ +static struct omap_hwmod_opt_clk ocp2scp_usb_phy_opt_clks[] = { + { .role = "phy_48m", .clk = "ocp2scp_usb_phy_phy_48m" }, +}; + +static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = { + .name = "ocp2scp_usb_phy", + .class = &omap44xx_ocp2scp_hwmod_class, + .clkdm_name = "l3_init_clkdm", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP4_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL_OFFSET, + .context_offs = OMAP4_RM_L3INIT_USBPHYOCP2SCP_CONTEXT_OFFSET, + .modulemode = MODULEMODE_HWCTRL, + }, + }, + .opt_clks = ocp2scp_usb_phy_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(ocp2scp_usb_phy_opt_clks), +}; + +/* * 'sl2if' class * shared level 2 memory interface */ @@ -3083,6 +3109,55 @@ static struct omap_hwmod omap44xx_uart4_hwmod = { }; /* + * 'usb_host_fs' class + * full-speed usb host controller + */ + +/* The IP is not compliant to type1 / type2 scheme */ +static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_usb_host_fs = { + .midle_shift = 4, + .sidle_shift = 2, + .srst_shift = 1, +}; + +static struct omap_hwmod_class_sysconfig omap44xx_usb_host_fs_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0210, + .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE | + SYSC_HAS_SOFTRESET), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | + SIDLE_SMART_WKUP), + .sysc_fields = &omap_hwmod_sysc_type_usb_host_fs, +}; + +static struct omap_hwmod_class omap44xx_usb_host_fs_hwmod_class = { + .name = "usb_host_fs", + .sysc = &omap44xx_usb_host_fs_sysc, +}; + +/* usb_host_fs */ +static struct omap_hwmod_irq_info omap44xx_usb_host_fs_irqs[] = { + { .name = "std", .irq = 89 + OMAP44XX_IRQ_GIC_START }, + { .name = "smi", .irq = 90 + OMAP44XX_IRQ_GIC_START }, + { .irq = -1 } +}; + +static struct omap_hwmod omap44xx_usb_host_fs_hwmod = { + .name = "usb_host_fs", + .class = &omap44xx_usb_host_fs_hwmod_class, + .clkdm_name = "l3_init_clkdm", + .mpu_irqs = omap44xx_usb_host_fs_irqs, + .main_clk = "usb_host_fs_fck", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_FS_CLKCTRL_OFFSET, + .context_offs = OMAP4_RM_L3INIT_USB_HOST_FS_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* * 'usb_host_hs' class * high-speed multi-port usb host controller */ @@ -3595,6 +3670,14 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; +/* usb_host_fs -> l3_main_2 */ +static struct omap_hwmod_ocp_if omap44xx_usb_host_fs__l3_main_2 = { + .master = &omap44xx_usb_host_fs_hwmod, + .slave = &omap44xx_l3_main_2_hwmod, + .clk = "l3_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + /* usb_host_hs -> l3_main_2 */ static struct omap_hwmod_ocp_if omap44xx_usb_host_hs__l3_main_2 = { .master = &omap44xx_usb_host_hs_hwmod, @@ -4881,6 +4964,14 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; +/* l4_cfg -> ocp2scp_usb_phy */ +static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp2scp_usb_phy = { + .master = &omap44xx_l4_cfg_hwmod, + .slave = &omap44xx_ocp2scp_usb_phy_hwmod, + .clk = "l4_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + /* l3_main_2 -> sl2if */ static struct omap_hwmod_ocp_if omap44xx_l3_main_2__sl2if = { .master = &omap44xx_l3_main_2_hwmod, @@ -5357,6 +5448,24 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; +static struct omap_hwmod_addr_space omap44xx_usb_host_fs_addrs[] = { + { + .pa_start = 0x4a0a9000, + .pa_end = 0x4a0a93ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_cfg -> usb_host_fs */ +static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_fs = { + .master = &omap44xx_l4_cfg_hwmod, + .slave = &omap44xx_usb_host_fs_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_usb_host_fs_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + static struct omap_hwmod_addr_space omap44xx_usb_host_hs_addrs[] = { { .name = "uhh", @@ -5504,6 +5613,7 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = { &omap44xx_iva__l3_main_2, &omap44xx_l3_main_1__l3_main_2, &omap44xx_l4_cfg__l3_main_2, + &omap44xx_usb_host_fs__l3_main_2, &omap44xx_usb_host_hs__l3_main_2, &omap44xx_usb_otg_hs__l3_main_2, &omap44xx_l3_main_1__l3_main_3, @@ -5585,6 +5695,7 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = { &omap44xx_l4_per__mmc3, &omap44xx_l4_per__mmc4, &omap44xx_l4_per__mmc5, + &omap44xx_l4_cfg__ocp2scp_usb_phy, &omap44xx_l3_main_2__sl2if, &omap44xx_l4_abe__slimbus1, &omap44xx_l4_abe__slimbus1_dma, @@ -5612,6 +5723,7 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = { &omap44xx_l4_per__uart2, &omap44xx_l4_per__uart3, &omap44xx_l4_per__uart4, + &omap44xx_l4_cfg__usb_host_fs, &omap44xx_l4_cfg__usb_host_hs, &omap44xx_l4_cfg__usb_otg_hs, &omap44xx_l4_cfg__usb_tll_hs, -- cgit v0.10.2 From e17f18c007040053babe785f5ba61aa3536bd77d Mon Sep 17 00:00:00 2001 From: Paul Walmsley Date: Thu, 19 Apr 2012 13:33:56 -0600 Subject: ARM: OMAP4: hwmod data: add OCM RAM IP block MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add the OCM RAM IP block and interconnect data. This is an oh-chip block of SRAM connected directly to the L3 bus. Signed-off-by: Paul Walmsley Signed-off-by: Benoît Cousson diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c index c080fd6..b8e2713 100644 --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c @@ -281,7 +281,6 @@ static struct omap_hwmod omap44xx_mpu_private_hwmod = { * efuse_ctrl_std * mpu_c0 * mpu_c1 - * ocmc_ram * ocp_wp_noc * prcm_mpu * prm @@ -2385,6 +2384,28 @@ static struct omap_hwmod omap44xx_mpu_hwmod = { }; /* + * 'ocmc_ram' class + * top-level core on-chip ram + */ + +static struct omap_hwmod_class omap44xx_ocmc_ram_hwmod_class = { + .name = "ocmc_ram", +}; + +/* ocmc_ram */ +static struct omap_hwmod omap44xx_ocmc_ram_hwmod = { + .name = "ocmc_ram", + .class = &omap44xx_ocmc_ram_hwmod_class, + .clkdm_name = "l3_2_clkdm", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP4_CM_L3_2_OCMC_RAM_CLKCTRL_OFFSET, + .context_offs = OMAP4_RM_L3_2_OCMC_RAM_CONTEXT_OFFSET, + }, + }, +}; + +/* * 'ocp2scp' class * bridge to transform ocp interface protocol to scp (serial control port) * protocol @@ -4964,6 +4985,14 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; +/* l3_main_2 -> ocmc_ram */ +static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ocmc_ram = { + .master = &omap44xx_l3_main_2_hwmod, + .slave = &omap44xx_ocmc_ram_hwmod, + .clk = "l3_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + /* l4_cfg -> ocp2scp_usb_phy */ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp2scp_usb_phy = { .master = &omap44xx_l4_cfg_hwmod, @@ -5695,6 +5724,7 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = { &omap44xx_l4_per__mmc3, &omap44xx_l4_per__mmc4, &omap44xx_l4_per__mmc5, + &omap44xx_l3_main_2__ocmc_ram, &omap44xx_l4_cfg__ocp2scp_usb_phy, &omap44xx_l3_main_2__sl2if, &omap44xx_l4_abe__slimbus1, -- cgit v0.10.2 From 9a817bc815c86322386c457ae670c73390776a2d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Beno=C3=AEt=20Cousson?= Date: Thu, 19 Apr 2012 13:33:56 -0600 Subject: ARM: OMAP4: hwmod data: add the OCP-WP IP block MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add the OCP-WP hwmod and associated interconnect data. The OCP-WP, or OCP watchpoint, can be used to collect interconnect data and transmit it via the STM port. Signed-off-by: Benoît Cousson Signed-off-by: Paul Walmsley diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c index b8e2713..6b29f8d 100644 --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c @@ -263,6 +263,28 @@ static struct omap_hwmod omap44xx_mpu_private_hwmod = { }; /* + * 'ocp_wp_noc' class + * instance(s): ocp_wp_noc + */ +static struct omap_hwmod_class omap44xx_ocp_wp_noc_hwmod_class = { + .name = "ocp_wp_noc", +}; + +/* ocp_wp_noc */ +static struct omap_hwmod omap44xx_ocp_wp_noc_hwmod = { + .name = "ocp_wp_noc", + .class = &omap44xx_ocp_wp_noc_hwmod_class, + .clkdm_name = "l3_instr_clkdm", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_OFFSET, + .context_offs = OMAP4_RM_L3INSTR_OCP_WP1_CONTEXT_OFFSET, + .modulemode = MODULEMODE_HWCTRL, + }, + }, +}; + +/* * Modules omap_hwmod structures * * The following IPs are excluded for the moment because: @@ -281,7 +303,6 @@ static struct omap_hwmod omap44xx_mpu_private_hwmod = { * efuse_ctrl_std * mpu_c0 * mpu_c1 - * ocp_wp_noc * prcm_mpu * prm * scrm @@ -3535,6 +3556,14 @@ static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; +/* ocp_wp_noc -> l3_instr */ +static struct omap_hwmod_ocp_if omap44xx_ocp_wp_noc__l3_instr = { + .master = &omap44xx_ocp_wp_noc_hwmod, + .slave = &omap44xx_l3_instr_hwmod, + .clk = "l3_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + /* dsp -> l3_main_1 */ static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = { .master = &omap44xx_dsp_hwmod, @@ -3813,6 +3842,24 @@ static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; +static struct omap_hwmod_addr_space omap44xx_ocp_wp_noc_addrs[] = { + { + .pa_start = 0x4a102000, + .pa_end = 0x4a10207f, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_cfg -> ocp_wp_noc */ +static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp_wp_noc = { + .master = &omap44xx_l4_cfg_hwmod, + .slave = &omap44xx_ocp_wp_noc_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_ocp_wp_noc_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = { { .pa_start = 0x401f1000, @@ -5625,6 +5672,7 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = { &omap44xx_l4_cfg__emif_fw, &omap44xx_iva__l3_instr, &omap44xx_l3_main_3__l3_instr, + &omap44xx_ocp_wp_noc__l3_instr, &omap44xx_dsp__l3_main_1, &omap44xx_dss__l3_main_1, &omap44xx_l3_main_2__l3_main_1, @@ -5656,6 +5704,7 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = { &omap44xx_l3_main_2__l4_per, &omap44xx_l4_cfg__l4_wkup, &omap44xx_mpu__mpu_private, + &omap44xx_l4_cfg__ocp_wp_noc, &omap44xx_l4_abe__aess, &omap44xx_l4_abe__aess_dma, &omap44xx_l3_main_2__c2c, -- cgit v0.10.2 From a0b5d81356c35504213fc58f8e8f8403138b6585 Mon Sep 17 00:00:00 2001 From: Paul Walmsley Date: Thu, 19 Apr 2012 13:33:57 -0600 Subject: ARM: OMAP4: hwmod data: add System Control Module MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add the System Control Module hwmod and associated interconnect data. Signed-off-by: Paul Walmsley Signed-off-by: Benoît Cousson diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c index 6b29f8d..8e915d3 100644 --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c @@ -294,10 +294,6 @@ static struct omap_hwmod omap44xx_ocp_wp_noc_hwmod = { * * cm_core * cm_core_aon - * ctrl_module_core - * ctrl_module_pad_core - * ctrl_module_pad_wkup - * ctrl_module_wkup * debugss * efuse_ctrl_cust * efuse_ctrl_std @@ -434,6 +430,60 @@ static struct omap_hwmod omap44xx_counter_32k_hwmod = { }; /* + * 'ctrl_module' class + * attila core control module + core pad control module + wkup pad control + * module + attila wkup control module + */ + +static struct omap_hwmod_class_sysconfig omap44xx_ctrl_module_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .sysc_flags = SYSC_HAS_SIDLEMODE, + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | + SIDLE_SMART_WKUP), + .sysc_fields = &omap_hwmod_sysc_type2, +}; + +static struct omap_hwmod_class omap44xx_ctrl_module_hwmod_class = { + .name = "ctrl_module", + .sysc = &omap44xx_ctrl_module_sysc, +}; + +/* ctrl_module_core */ +static struct omap_hwmod_irq_info omap44xx_ctrl_module_core_irqs[] = { + { .irq = 8 + OMAP44XX_IRQ_GIC_START }, + { .irq = -1 } +}; + +static struct omap_hwmod omap44xx_ctrl_module_core_hwmod = { + .name = "ctrl_module_core", + .class = &omap44xx_ctrl_module_hwmod_class, + .clkdm_name = "l4_cfg_clkdm", + .mpu_irqs = omap44xx_ctrl_module_core_irqs, +}; + +/* ctrl_module_pad_core */ +static struct omap_hwmod omap44xx_ctrl_module_pad_core_hwmod = { + .name = "ctrl_module_pad_core", + .class = &omap44xx_ctrl_module_hwmod_class, + .clkdm_name = "l4_cfg_clkdm", +}; + +/* ctrl_module_wkup */ +static struct omap_hwmod omap44xx_ctrl_module_wkup_hwmod = { + .name = "ctrl_module_wkup", + .class = &omap44xx_ctrl_module_hwmod_class, + .clkdm_name = "l4_wkup_clkdm", +}; + +/* ctrl_module_pad_wkup */ +static struct omap_hwmod omap44xx_ctrl_module_pad_wkup_hwmod = { + .name = "ctrl_module_pad_wkup", + .class = &omap44xx_ctrl_module_hwmod_class, + .clkdm_name = "l4_wkup_clkdm", +}; + +/* * 'dma' class * dma controller for data exchange between memory to memory (i.e. internal or * external memory) and gp peripherals to memory or memory to gp peripherals @@ -3922,6 +3972,78 @@ static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; +static struct omap_hwmod_addr_space omap44xx_ctrl_module_core_addrs[] = { + { + .pa_start = 0x4a002000, + .pa_end = 0x4a0027ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_cfg -> ctrl_module_core */ +static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_core = { + .master = &omap44xx_l4_cfg_hwmod, + .slave = &omap44xx_ctrl_module_core_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_ctrl_module_core_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_core_addrs[] = { + { + .pa_start = 0x4a100000, + .pa_end = 0x4a1007ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_cfg -> ctrl_module_pad_core */ +static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_pad_core = { + .master = &omap44xx_l4_cfg_hwmod, + .slave = &omap44xx_ctrl_module_pad_core_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_ctrl_module_pad_core_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_ctrl_module_wkup_addrs[] = { + { + .pa_start = 0x4a30c000, + .pa_end = 0x4a30c7ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_wkup -> ctrl_module_wkup */ +static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_wkup = { + .master = &omap44xx_l4_wkup_hwmod, + .slave = &omap44xx_ctrl_module_wkup_hwmod, + .clk = "l4_wkup_clk_mux_ck", + .addr = omap44xx_ctrl_module_wkup_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_wkup_addrs[] = { + { + .pa_start = 0x4a31e000, + .pa_end = 0x4a31e7ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_wkup -> ctrl_module_pad_wkup */ +static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_pad_wkup = { + .master = &omap44xx_l4_wkup_hwmod, + .slave = &omap44xx_ctrl_module_pad_wkup_hwmod, + .clk = "l4_wkup_clk_mux_ck", + .addr = omap44xx_ctrl_module_pad_wkup_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = { { .pa_start = 0x4a056000, @@ -5709,6 +5831,10 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = { &omap44xx_l4_abe__aess_dma, &omap44xx_l3_main_2__c2c, &omap44xx_l4_wkup__counter_32k, + &omap44xx_l4_cfg__ctrl_module_core, + &omap44xx_l4_cfg__ctrl_module_pad_core, + &omap44xx_l4_wkup__ctrl_module_wkup, + &omap44xx_l4_wkup__ctrl_module_pad_wkup, &omap44xx_l4_cfg__dma_system, &omap44xx_l4_abe__dmic, &omap44xx_l4_abe__dmic_dma, -- cgit v0.10.2 From 794b480a37e3d284d6ee7344d8a737ef60476ed5 Mon Sep 17 00:00:00 2001 From: Paul Walmsley Date: Thu, 19 Apr 2012 13:33:58 -0600 Subject: ARM: OMAP4: hwmod data: add PRCM and related IP blocks MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add the PRCM, CM, PRM, and related hwmod and associated interconnect data. These IP blocks handle most of the on-chip power, reset, and clock control. Signed-off-by: Paul Walmsley Signed-off-by: Benoît Cousson diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c index 8e915d3..66b8da2 100644 --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c @@ -292,16 +292,11 @@ static struct omap_hwmod omap44xx_ocp_wp_noc_hwmod = { * - They still need to be validated with the driver * properly adapted to omap_hwmod / omap_device * - * cm_core - * cm_core_aon * debugss * efuse_ctrl_cust * efuse_ctrl_std * mpu_c0 * mpu_c1 - * prcm_mpu - * prm - * scrm * usb_phy_cm * usim */ @@ -2507,6 +2502,73 @@ static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = { }; /* + * 'prcm' class + * power and reset manager (part of the prcm infrastructure) + clock manager 2 + * + clock manager 1 (in always on power domain) + local prm in mpu + */ + +static struct omap_hwmod_class omap44xx_prcm_hwmod_class = { + .name = "prcm", +}; + +/* prcm_mpu */ +static struct omap_hwmod omap44xx_prcm_mpu_hwmod = { + .name = "prcm_mpu", + .class = &omap44xx_prcm_hwmod_class, + .clkdm_name = "l4_wkup_clkdm", +}; + +/* cm_core_aon */ +static struct omap_hwmod omap44xx_cm_core_aon_hwmod = { + .name = "cm_core_aon", + .class = &omap44xx_prcm_hwmod_class, + .clkdm_name = "cm_clkdm", +}; + +/* cm_core */ +static struct omap_hwmod omap44xx_cm_core_hwmod = { + .name = "cm_core", + .class = &omap44xx_prcm_hwmod_class, + .clkdm_name = "cm_clkdm", +}; + +/* prm */ +static struct omap_hwmod_irq_info omap44xx_prm_irqs[] = { + { .irq = 11 + OMAP44XX_IRQ_GIC_START }, + { .irq = -1 } +}; + +static struct omap_hwmod_rst_info omap44xx_prm_resets[] = { + { .name = "rst_global_warm_sw", .rst_shift = 0 }, + { .name = "rst_global_cold_sw", .rst_shift = 1 }, +}; + +static struct omap_hwmod omap44xx_prm_hwmod = { + .name = "prm", + .class = &omap44xx_prcm_hwmod_class, + .clkdm_name = "prm_clkdm", + .mpu_irqs = omap44xx_prm_irqs, + .rst_lines = omap44xx_prm_resets, + .rst_lines_cnt = ARRAY_SIZE(omap44xx_prm_resets), +}; + +/* + * 'scrm' class + * system clock and reset manager + */ + +static struct omap_hwmod_class omap44xx_scrm_hwmod_class = { + .name = "scrm", +}; + +/* scrm */ +static struct omap_hwmod omap44xx_scrm_hwmod = { + .name = "scrm", + .class = &omap44xx_scrm_hwmod_class, + .clkdm_name = "l4_wkup_clkdm", +}; + +/* * 'sl2if' class * shared level 2 memory interface */ @@ -5170,6 +5232,96 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp2scp_usb_phy = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; +static struct omap_hwmod_addr_space omap44xx_prcm_mpu_addrs[] = { + { + .pa_start = 0x48243000, + .pa_end = 0x48243fff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* mpu_private -> prcm_mpu */ +static struct omap_hwmod_ocp_if omap44xx_mpu_private__prcm_mpu = { + .master = &omap44xx_mpu_private_hwmod, + .slave = &omap44xx_prcm_mpu_hwmod, + .clk = "l3_div_ck", + .addr = omap44xx_prcm_mpu_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_cm_core_aon_addrs[] = { + { + .pa_start = 0x4a004000, + .pa_end = 0x4a004fff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_wkup -> cm_core_aon */ +static struct omap_hwmod_ocp_if omap44xx_l4_wkup__cm_core_aon = { + .master = &omap44xx_l4_wkup_hwmod, + .slave = &omap44xx_cm_core_aon_hwmod, + .clk = "l4_wkup_clk_mux_ck", + .addr = omap44xx_cm_core_aon_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_cm_core_addrs[] = { + { + .pa_start = 0x4a008000, + .pa_end = 0x4a009fff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_cfg -> cm_core */ +static struct omap_hwmod_ocp_if omap44xx_l4_cfg__cm_core = { + .master = &omap44xx_l4_cfg_hwmod, + .slave = &omap44xx_cm_core_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_cm_core_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_prm_addrs[] = { + { + .pa_start = 0x4a306000, + .pa_end = 0x4a307fff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_wkup -> prm */ +static struct omap_hwmod_ocp_if omap44xx_l4_wkup__prm = { + .master = &omap44xx_l4_wkup_hwmod, + .slave = &omap44xx_prm_hwmod, + .clk = "l4_wkup_clk_mux_ck", + .addr = omap44xx_prm_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_scrm_addrs[] = { + { + .pa_start = 0x4a30a000, + .pa_end = 0x4a30a7ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_wkup -> scrm */ +static struct omap_hwmod_ocp_if omap44xx_l4_wkup__scrm = { + .master = &omap44xx_l4_wkup_hwmod, + .slave = &omap44xx_scrm_hwmod, + .clk = "l4_wkup_clk_mux_ck", + .addr = omap44xx_scrm_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + /* l3_main_2 -> sl2if */ static struct omap_hwmod_ocp_if omap44xx_l3_main_2__sl2if = { .master = &omap44xx_l3_main_2_hwmod, @@ -5901,6 +6053,11 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = { &omap44xx_l4_per__mmc5, &omap44xx_l3_main_2__ocmc_ram, &omap44xx_l4_cfg__ocp2scp_usb_phy, + &omap44xx_mpu_private__prcm_mpu, + &omap44xx_l4_wkup__cm_core_aon, + &omap44xx_l4_cfg__cm_core, + &omap44xx_l4_wkup__prm, + &omap44xx_l4_wkup__scrm, &omap44xx_l3_main_2__sl2if, &omap44xx_l4_abe__slimbus1, &omap44xx_l4_abe__slimbus1_dma, -- cgit v0.10.2 From 96566043b19ae76d3828ce75cbf28dc6d0bcaaf1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Beno=C3=AEt=20Cousson?= Date: Thu, 19 Apr 2012 13:33:59 -0600 Subject: ARM: OMAP4: hwmod data: add DEBUGSS skeleton MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add a skeleton hwmod for the DEBUGSS and associated interconnect data. This is a basic set of data that will need further additions as further DEBUGSS information becomes available. Signed-off-by: Benoît Cousson Signed-off-by: Paul Walmsley diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c index 66b8da2..4906129 100644 --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c @@ -292,13 +292,7 @@ static struct omap_hwmod omap44xx_ocp_wp_noc_hwmod = { * - They still need to be validated with the driver * properly adapted to omap_hwmod / omap_device * - * debugss - * efuse_ctrl_cust - * efuse_ctrl_std - * mpu_c0 - * mpu_c1 - * usb_phy_cm - * usim + * usim */ /* @@ -479,6 +473,29 @@ static struct omap_hwmod omap44xx_ctrl_module_pad_wkup_hwmod = { }; /* + * 'debugss' class + * debug and emulation sub system + */ + +static struct omap_hwmod_class omap44xx_debugss_hwmod_class = { + .name = "debugss", +}; + +/* debugss */ +static struct omap_hwmod omap44xx_debugss_hwmod = { + .name = "debugss", + .class = &omap44xx_debugss_hwmod_class, + .clkdm_name = "emu_sys_clkdm", + .main_clk = "trace_clk_div_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP4_CM_EMU_DEBUGSS_CLKCTRL_OFFSET, + .context_offs = OMAP4_RM_EMU_DEBUGSS_CONTEXT_OFFSET, + }, + }, +}; + +/* * 'dma' class * dma controller for data exchange between memory to memory (i.e. internal or * external memory) and gp peripherals to memory or memory to gp peripherals @@ -3750,6 +3767,14 @@ static struct omap_hwmod_ocp_if omap44xx_c2c_target_fw__l3_main_2 = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; +/* debugss -> l3_main_2 */ +static struct omap_hwmod_ocp_if omap44xx_debugss__l3_main_2 = { + .master = &omap44xx_debugss_hwmod, + .slave = &omap44xx_l3_main_2_hwmod, + .clk = "dbgclk_mux_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + /* dma_system -> l3_main_2 */ static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = { .master = &omap44xx_dma_system_hwmod, @@ -4106,6 +4131,24 @@ static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_pad_wkup = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; +static struct omap_hwmod_addr_space omap44xx_debugss_addrs[] = { + { + .pa_start = 0x54160000, + .pa_end = 0x54167fff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l3_instr -> debugss */ +static struct omap_hwmod_ocp_if omap44xx_l3_instr__debugss = { + .master = &omap44xx_l3_instr_hwmod, + .slave = &omap44xx_debugss_hwmod, + .clk = "l3_div_ck", + .addr = omap44xx_debugss_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = { { .pa_start = 0x4a056000, @@ -5955,6 +5998,7 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = { &omap44xx_mmc2__l3_main_1, &omap44xx_mpu__l3_main_1, &omap44xx_c2c_target_fw__l3_main_2, + &omap44xx_debugss__l3_main_2, &omap44xx_dma_system__l3_main_2, &omap44xx_fdif__l3_main_2, &omap44xx_gpu__l3_main_2, @@ -5987,6 +6031,7 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = { &omap44xx_l4_cfg__ctrl_module_pad_core, &omap44xx_l4_wkup__ctrl_module_wkup, &omap44xx_l4_wkup__ctrl_module_pad_wkup, + &omap44xx_l3_instr__debugss, &omap44xx_l4_cfg__dma_system, &omap44xx_l4_abe__dmic, &omap44xx_l4_abe__dmic_dma, -- cgit v0.10.2 From 3ebabaa534c79a54c11a4ec1a81e62b76a4ada0c Mon Sep 17 00:00:00 2001 From: Daniel Lezcano Date: Thu, 19 Apr 2012 14:46:32 +0200 Subject: ARM: ux500: add the cpuidle driver for WFI and ARM retention This patch adds the cpuidle driver for the ux500 SoC. The boards saves 12mA with these states. It is based on the latest cpuidle consolidation from Robert Lee. The cpu can go to retention only if the other core is in WFI. If the other cpu is in WFI and we decoupled the gic from the cores, then we have the guarantee, it won't be wake up. It is up to the prcmu firmware to recouple the gic automatically after the power state mode is selected. Signed-off-by: Daniel Lezcano Acked-by: Vincent Guittot Signed-off-by: Linus Walleij diff --git a/arch/arm/mach-ux500/Makefile b/arch/arm/mach-ux500/Makefile index 465b9ec..93a191a 100644 --- a/arch/arm/mach-ux500/Makefile +++ b/arch/arm/mach-ux500/Makefile @@ -4,6 +4,7 @@ obj-y := clock.o cpu.o devices.o devices-common.o \ id.o usb.o timer.o +obj-$(CONFIG_CPU_IDLE) += cpuidle.o obj-$(CONFIG_CACHE_L2X0) += cache-l2x0.o obj-$(CONFIG_UX500_SOC_DB5500) += cpu-db5500.o dma-db5500.o obj-$(CONFIG_UX500_SOC_DB8500) += cpu-db8500.o devices-db8500.o diff --git a/arch/arm/mach-ux500/cpuidle.c b/arch/arm/mach-ux500/cpuidle.c new file mode 100644 index 0000000..b54884bd --- /dev/null +++ b/arch/arm/mach-ux500/cpuidle.c @@ -0,0 +1,171 @@ +/* + * Copyright (c) 2012 Linaro : Daniel Lezcano (IBM) + * + * Based on the work of Rickard Andersson + * and Jonas Aaberg . + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +static atomic_t master = ATOMIC_INIT(0); +static DEFINE_SPINLOCK(master_lock); +static DEFINE_PER_CPU(struct cpuidle_device, ux500_cpuidle_device); + +static inline int ux500_enter_idle(struct cpuidle_device *dev, + struct cpuidle_driver *drv, int index) +{ + int this_cpu = smp_processor_id(); + bool recouple = false; + + clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &this_cpu); + + if (atomic_inc_return(&master) == num_online_cpus()) { + + /* With this lock, we prevent the other cpu to exit and enter + * this function again and become the master */ + if (!spin_trylock(&master_lock)) + goto wfi; + + /* decouple the gic from the A9 cores */ + if (prcmu_gic_decouple()) + goto out; + + /* If an error occur, we will have to recouple the gic + * manually */ + recouple = true; + + /* At this state, as the gic is decoupled, if the other + * cpu is in WFI, we have the guarantee it won't be wake + * up, so we can safely go to retention */ + if (!prcmu_is_cpu_in_wfi(this_cpu ? 0 : 1)) + goto out; + + /* The prcmu will be in charge of watching the interrupts + * and wake up the cpus */ + if (prcmu_copy_gic_settings()) + goto out; + + /* Check in the meantime an interrupt did + * not occur on the gic ... */ + if (prcmu_gic_pending_irq()) + goto out; + + /* ... and the prcmu */ + if (prcmu_pending_irq()) + goto out; + + /* Go to the retention state, the prcmu will wait for the + * cpu to go WFI and this is what happens after exiting this + * 'master' critical section */ + if (prcmu_set_power_state(PRCMU_AP_IDLE, true, true)) + goto out; + + /* When we switch to retention, the prcmu is in charge + * of recoupling the gic automatically */ + recouple = false; + + spin_unlock(&master_lock); + } +wfi: + cpu_do_idle(); +out: + atomic_dec(&master); + + if (recouple) { + prcmu_gic_recouple(); + spin_unlock(&master_lock); + } + + clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &this_cpu); + + return index; +} + +static struct cpuidle_driver ux500_idle_driver = { + .name = "ux500_idle", + .owner = THIS_MODULE, + .en_core_tk_irqen = 1, + .states = { + ARM_CPUIDLE_WFI_STATE, + { + .enter = ux500_enter_idle, + .exit_latency = 70, + .target_residency = 260, + .flags = CPUIDLE_FLAG_TIME_VALID, + .name = "ApIdle", + .desc = "ARM Retention", + }, + }, + .safe_state_index = 0, + .state_count = 2, +}; + +/* + * For each cpu, setup the broadcast timer because we will + * need to migrate the timers for the states >= ApIdle. + */ +static void ux500_setup_broadcast_timer(void *arg) +{ + int cpu = smp_processor_id(); + clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ON, &cpu); +} + +int __init ux500_idle_init(void) +{ + int ret, cpu; + struct cpuidle_device *device; + + /* Configure wake up reasons */ + prcmu_enable_wakeups(PRCMU_WAKEUP(ARM) | PRCMU_WAKEUP(RTC) | + PRCMU_WAKEUP(ABB)); + + /* + * Configure the timer broadcast for each cpu, that must + * be done from the cpu context, so we use a smp cross + * call with 'on_each_cpu'. + */ + on_each_cpu(ux500_setup_broadcast_timer, NULL, 1); + + ret = cpuidle_register_driver(&ux500_idle_driver); + if (ret) { + printk(KERN_ERR "failed to register ux500 idle driver\n"); + return ret; + } + + for_each_online_cpu(cpu) { + device = &per_cpu(ux500_cpuidle_device, cpu); + device->cpu = cpu; + ret = cpuidle_register_device(device); + if (ret) { + printk(KERN_ERR "Failed to register cpuidle " + "device for cpu%d\n", cpu); + goto out_unregister; + } + } +out: + return ret; + +out_unregister: + for_each_online_cpu(cpu) { + device = &per_cpu(ux500_cpuidle_device, cpu); + cpuidle_unregister_device(device); + } + + cpuidle_unregister_driver(&ux500_idle_driver); + goto out; +} + +device_initcall(ux500_idle_init); -- cgit v0.10.2 From 5e5661a872600cb4b12d5292160608fb232efdcd Mon Sep 17 00:00:00 2001 From: Chao Xie Date: Mon, 7 May 2012 11:22:22 +0800 Subject: ARM: mmp: move XX_REG definition to addr-map.h Move APBC_REG, APMU_REG and CIU_REG definition to addr-map.h driver only need include addr-map.h to get access of the registers. Signed-off-by: Chao Xie Signed-off-by: Haojian Zhuang diff --git a/arch/arm/mach-mmp/include/mach/addr-map.h b/arch/arm/mach-mmp/include/mach/addr-map.h index b1ece08..f88a44c 100644 --- a/arch/arm/mach-mmp/include/mach/addr-map.h +++ b/arch/arm/mach-mmp/include/mach/addr-map.h @@ -31,4 +31,16 @@ #define SMC_CS1_PHYS_BASE 0x90000000 #define SMC_CS1_PHYS_SIZE 0x10000000 +#define APMU_VIRT_BASE (AXI_VIRT_BASE + 0x82800) +#define APMU_REG(x) (APMU_VIRT_BASE + (x)) + +#define APBC_VIRT_BASE (APB_VIRT_BASE + 0x015000) +#define APBC_REG(x) (APBC_VIRT_BASE + (x)) + +#define MPMU_VIRT_BASE (APB_VIRT_BASE + 0x50000) +#define MPMU_REG(x) (MPMU_VIRT_BASE + (x)) + +#define CIU_VIRT_BASE (AXI_VIRT_BASE + 0x82c00) +#define CIU_REG(x) (CIU_VIRT_BASE + (x)) + #endif /* __ASM_MACH_ADDR_MAP_H */ diff --git a/arch/arm/mach-mmp/include/mach/regs-apbc.h b/arch/arm/mach-mmp/include/mach/regs-apbc.h index 8a37fb0..68b0c93 100644 --- a/arch/arm/mach-mmp/include/mach/regs-apbc.h +++ b/arch/arm/mach-mmp/include/mach/regs-apbc.h @@ -13,9 +13,6 @@ #include -#define APBC_VIRT_BASE (APB_VIRT_BASE + 0x015000) -#define APBC_REG(x) (APBC_VIRT_BASE + (x)) - /* * APB clock register offsets for PXA168 */ diff --git a/arch/arm/mach-mmp/include/mach/regs-apmu.h b/arch/arm/mach-mmp/include/mach/regs-apmu.h index 8447ac6..7af8deb 100644 --- a/arch/arm/mach-mmp/include/mach/regs-apmu.h +++ b/arch/arm/mach-mmp/include/mach/regs-apmu.h @@ -13,9 +13,6 @@ #include -#define APMU_VIRT_BASE (AXI_VIRT_BASE + 0x82800) -#define APMU_REG(x) (APMU_VIRT_BASE + (x)) - /* Clock Reset Control */ #define APMU_IRE APMU_REG(0x048) #define APMU_LCD APMU_REG(0x04c) -- cgit v0.10.2 From 87046f4f3194ac0a795a10f3368ac73c04c633e3 Mon Sep 17 00:00:00 2001 From: Chao Xie Date: Mon, 7 May 2012 11:22:23 +0800 Subject: ARM: mmp: add PM support for mmp2 MMP2 can enter system sleep level during suspend. It can be waken up by PMIC interrupt, RTC/ALARM. Signed-off-by: Chao Xie Signed-off-by: Haojian Zhuang diff --git a/arch/arm/mach-mmp/Makefile b/arch/arm/mach-mmp/Makefile index b920b9b..7d60cef 100644 --- a/arch/arm/mach-mmp/Makefile +++ b/arch/arm/mach-mmp/Makefile @@ -9,6 +9,10 @@ obj-$(CONFIG_CPU_PXA168) += pxa168.o obj-$(CONFIG_CPU_PXA910) += pxa910.o obj-$(CONFIG_CPU_MMP2) += mmp2.o sram.o +ifeq ($(CONFIG_PM),y) +obj-$(CONFIG_CPU_MMP2) += pm-mmp2.o +endif + # board support obj-$(CONFIG_MACH_ASPENITE) += aspenite.o obj-$(CONFIG_MACH_ZYLONITE2) += aspenite.o diff --git a/arch/arm/mach-mmp/include/mach/pm-mmp2.h b/arch/arm/mach-mmp/include/mach/pm-mmp2.h new file mode 100644 index 0000000..98bd66c --- /dev/null +++ b/arch/arm/mach-mmp/include/mach/pm-mmp2.h @@ -0,0 +1,61 @@ +/* + * MMP2 Power Management Routines + * + * This software program is licensed subject to the GNU General Public License + * (GPL).Version 2,June 1991, available at http://www.fsf.org/copyleft/gpl.html + * + * (C) Copyright 2010 Marvell International Ltd. + * All Rights Reserved + */ + +#ifndef __MMP2_PM_H__ +#define __MMP2_PM_H__ + +#include + +#define APMU_PJ_IDLE_CFG APMU_REG(0x018) +#define APMU_PJ_IDLE_CFG_PJ_IDLE (1 << 1) +#define APMU_PJ_IDLE_CFG_PJ_PWRDWN (1 << 5) +#define APMU_PJ_IDLE_CFG_PWR_SW(x) ((x) << 16) +#define APMU_PJ_IDLE_CFG_L2_PWR_SW (1 << 19) +#define APMU_PJ_IDLE_CFG_ISO_MODE_CNTRL_MASK (3 << 28) + +#define APMU_SRAM_PWR_DWN APMU_REG(0x08c) + +#define MPMU_SCCR MPMU_REG(0x038) +#define MPMU_PCR_PJ MPMU_REG(0x1000) +#define MPMU_PCR_PJ_AXISD (1 << 31) +#define MPMU_PCR_PJ_SLPEN (1 << 29) +#define MPMU_PCR_PJ_SPSD (1 << 28) +#define MPMU_PCR_PJ_DDRCORSD (1 << 27) +#define MPMU_PCR_PJ_APBSD (1 << 26) +#define MPMU_PCR_PJ_INTCLR (1 << 24) +#define MPMU_PCR_PJ_SLPWP0 (1 << 23) +#define MPMU_PCR_PJ_SLPWP1 (1 << 22) +#define MPMU_PCR_PJ_SLPWP2 (1 << 21) +#define MPMU_PCR_PJ_SLPWP3 (1 << 20) +#define MPMU_PCR_PJ_VCTCXOSD (1 << 19) +#define MPMU_PCR_PJ_SLPWP4 (1 << 18) +#define MPMU_PCR_PJ_SLPWP5 (1 << 17) +#define MPMU_PCR_PJ_SLPWP6 (1 << 16) +#define MPMU_PCR_PJ_SLPWP7 (1 << 15) + +#define MPMU_PLL2_CTRL1 MPMU_REG(0x0414) +#define MPMU_CGR_PJ MPMU_REG(0x1024) +#define MPMU_WUCRM_PJ MPMU_REG(0x104c) +#define MPMU_WUCRM_PJ_WAKEUP(x) (1 << (x)) +#define MPMU_WUCRM_PJ_RTC_ALARM (1 << 17) + +enum { + POWER_MODE_ACTIVE = 0, + POWER_MODE_CORE_INTIDLE, + POWER_MODE_CORE_EXTIDLE, + POWER_MODE_APPS_IDLE, + POWER_MODE_APPS_SLEEP, + POWER_MODE_CHIP_SLEEP, + POWER_MODE_SYS_SLEEP, +}; + +extern void mmp2_pm_enter_lowpower_mode(int state); +extern int mmp2_set_wake(struct irq_data *d, unsigned int on); +#endif diff --git a/arch/arm/mach-mmp/irq.c b/arch/arm/mach-mmp/irq.c index 3705470..04935f1 100644 --- a/arch/arm/mach-mmp/irq.c +++ b/arch/arm/mach-mmp/irq.c @@ -23,6 +23,10 @@ #include +#ifdef CONFIG_CPU_MMP2 +#include +#endif + #include "common.h" #define MAX_ICU_NR 16 @@ -305,6 +309,9 @@ void __init mmp2_init_icu(void) set_irq_flags(irq, IRQF_VALID); } irq_set_default_host(icu_data[0].domain); +#ifdef CONFIG_CPU_MMP2 + icu_irq_chip.irq_set_wake = mmp2_set_wake; +#endif } #ifdef CONFIG_OF diff --git a/arch/arm/mach-mmp/pm-mmp2.c b/arch/arm/mach-mmp/pm-mmp2.c new file mode 100644 index 0000000..461a191 --- /dev/null +++ b/arch/arm/mach-mmp/pm-mmp2.c @@ -0,0 +1,264 @@ +/* + * MMP2 Power Management Routines + * + * This software program is licensed subject to the GNU General Public License + * (GPL).Version 2,June 1991, available at http://www.fsf.org/copyleft/gpl.html + * + * (C) Copyright 2012 Marvell International Ltd. + * All Rights Reserved + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +int mmp2_set_wake(struct irq_data *d, unsigned int on) +{ + int irq = d->irq; + struct irq_desc *desc = irq_to_desc(irq); + unsigned long data = 0; + + if (unlikely(irq >= nr_irqs)) { + pr_err("IRQ nubmers are out of boundary!\n"); + return -EINVAL; + } + + if (on) { + if (desc->action) + desc->action->flags |= IRQF_NO_SUSPEND; + } else { + if (desc->action) + desc->action->flags &= ~IRQF_NO_SUSPEND; + } + + /* enable wakeup sources */ + switch (irq) { + case IRQ_MMP2_RTC: + case IRQ_MMP2_RTC_ALARM: + data = MPMU_WUCRM_PJ_WAKEUP(4) | MPMU_WUCRM_PJ_RTC_ALARM; + break; + case IRQ_MMP2_PMIC: + data = MPMU_WUCRM_PJ_WAKEUP(7); + break; + case IRQ_MMP2_MMC2: + /* mmc use WAKEUP2, same as GPIO wakeup source */ + data = MPMU_WUCRM_PJ_WAKEUP(2); + break; + } + if (on) { + if (data) { + data |= __raw_readl(MPMU_WUCRM_PJ); + __raw_writel(data, MPMU_WUCRM_PJ); + } + } else { + if (data) { + data = ~data & __raw_readl(MPMU_WUCRM_PJ); + __raw_writel(data, MPMU_WUCRM_PJ); + } + } + return 0; +} + +static void pm_scu_clk_disable(void) +{ + unsigned int val; + + /* close AXI fabric clock gate */ + __raw_writel(0x0, CIU_REG(0x64)); + __raw_writel(0x0, CIU_REG(0x68)); + + /* close MCB master clock gate */ + val = __raw_readl(CIU_REG(0x1c)); + val |= 0xf0; + __raw_writel(val, CIU_REG(0x1c)); + + return ; +} + +static void pm_scu_clk_enable(void) +{ + unsigned int val; + + /* open AXI fabric clock gate */ + __raw_writel(0x03003003, CIU_REG(0x64)); + __raw_writel(0x00303030, CIU_REG(0x68)); + + /* open MCB master clock gate */ + val = __raw_readl(CIU_REG(0x1c)); + val &= ~(0xf0); + __raw_writel(val, CIU_REG(0x1c)); + + return ; +} + +static void pm_mpmu_clk_disable(void) +{ + /* + * disable clocks in MPMU_CGR_PJ register + * except clock for APMU_PLL1, APMU_PLL1_2 and AP_26M + */ + __raw_writel(0x0000a010, MPMU_CGR_PJ); +} + +static void pm_mpmu_clk_enable(void) +{ + unsigned int val; + + __raw_writel(0xdffefffe, MPMU_CGR_PJ); + val = __raw_readl(MPMU_PLL2_CTRL1); + val |= (1 << 29); + __raw_writel(val, MPMU_PLL2_CTRL1); + + return ; +} + +void mmp2_pm_enter_lowpower_mode(int state) +{ + uint32_t idle_cfg, apcr; + + idle_cfg = __raw_readl(APMU_PJ_IDLE_CFG); + apcr = __raw_readl(MPMU_PCR_PJ); + apcr &= ~(MPMU_PCR_PJ_SLPEN | MPMU_PCR_PJ_DDRCORSD | MPMU_PCR_PJ_APBSD + | MPMU_PCR_PJ_AXISD | MPMU_PCR_PJ_VCTCXOSD | (1 << 13)); + idle_cfg &= ~APMU_PJ_IDLE_CFG_PJ_IDLE; + + switch (state) { + case POWER_MODE_SYS_SLEEP: + apcr |= MPMU_PCR_PJ_SLPEN; /* set the SLPEN bit */ + apcr |= MPMU_PCR_PJ_VCTCXOSD; /* set VCTCXOSD */ + /* fall through */ + case POWER_MODE_CHIP_SLEEP: + apcr |= MPMU_PCR_PJ_SLPEN; + /* fall through */ + case POWER_MODE_APPS_SLEEP: + apcr |= MPMU_PCR_PJ_APBSD; /* set APBSD */ + /* fall through */ + case POWER_MODE_APPS_IDLE: + apcr |= MPMU_PCR_PJ_AXISD; /* set AXISDD bit */ + apcr |= MPMU_PCR_PJ_DDRCORSD; /* set DDRCORSD bit */ + idle_cfg |= APMU_PJ_IDLE_CFG_PJ_PWRDWN; /* PJ power down */ + apcr |= MPMU_PCR_PJ_SPSD; + /* fall through */ + case POWER_MODE_CORE_EXTIDLE: + idle_cfg |= APMU_PJ_IDLE_CFG_PJ_IDLE; /* set the IDLE bit */ + idle_cfg &= ~APMU_PJ_IDLE_CFG_ISO_MODE_CNTRL_MASK; + idle_cfg |= APMU_PJ_IDLE_CFG_PWR_SW(3) + | APMU_PJ_IDLE_CFG_L2_PWR_SW; + break; + case POWER_MODE_CORE_INTIDLE: + apcr &= ~MPMU_PCR_PJ_SPSD; + break; + } + + /* set reserve bits */ + apcr |= (1 << 30) | (1 << 25); + + /* finally write the registers back */ + __raw_writel(idle_cfg, APMU_PJ_IDLE_CFG); + __raw_writel(apcr, MPMU_PCR_PJ); /* 0xfe086000 */ +} + +static int mmp2_pm_enter(suspend_state_t state) +{ + int temp; + + temp = __raw_readl(MMP2_ICU_INT4_MASK); + if (temp & (1 << 1)) { + printk(KERN_ERR "%s: PMIC interrupt is handling\n", __func__); + return -EAGAIN; + } + + temp = __raw_readl(APMU_SRAM_PWR_DWN); + temp |= ((1 << 19) | (1 << 18)); + __raw_writel(temp, APMU_SRAM_PWR_DWN); + pm_mpmu_clk_disable(); + pm_scu_clk_disable(); + + printk(KERN_INFO "%s: before suspend\n", __func__); + cpu_do_idle(); + printk(KERN_INFO "%s: after suspend\n", __func__); + + pm_mpmu_clk_enable(); /* enable clocks in MPMU */ + pm_scu_clk_enable(); /* enable clocks in SCU */ + + return 0; +} + +/* + * Called after processes are frozen, but before we shut down devices. + */ +static int mmp2_pm_prepare(void) +{ + mmp2_pm_enter_lowpower_mode(POWER_MODE_SYS_SLEEP); + + return 0; +} + +/* + * Called after devices are re-setup, but before processes are thawed. + */ +static void mmp2_pm_finish(void) +{ + mmp2_pm_enter_lowpower_mode(POWER_MODE_CORE_INTIDLE); +} + +static int mmp2_pm_valid(suspend_state_t state) +{ + return ((state == PM_SUSPEND_STANDBY) || (state == PM_SUSPEND_MEM)); +} + +/* + * Set to PM_DISK_FIRMWARE so we can quickly veto suspend-to-disk. + */ +static const struct platform_suspend_ops mmp2_pm_ops = { + .valid = mmp2_pm_valid, + .prepare = mmp2_pm_prepare, + .enter = mmp2_pm_enter, + .finish = mmp2_pm_finish, +}; + +static int __init mmp2_pm_init(void) +{ + uint32_t apcr; + + if (!cpu_is_mmp2()) + return -EIO; + + suspend_set_ops(&mmp2_pm_ops); + + /* + * Set bit 0, Slow clock Select 32K clock input instead of VCXO + * VCXO is chosen by default, which would be disabled in suspend + */ + __raw_writel(0x5, MPMU_SCCR); + + /* + * Clear bit 23 of CIU_CPU_CONF + * direct PJ4 to DDR access through Memory Controller slow queue + * fast queue has issue and cause lcd will flick + */ + __raw_writel(__raw_readl(CIU_REG(0x8)) & ~(0x1 << 23), CIU_REG(0x8)); + + /* Clear default low power control bit */ + apcr = __raw_readl(MPMU_PCR_PJ); + apcr &= ~(MPMU_PCR_PJ_SLPEN | MPMU_PCR_PJ_DDRCORSD + | MPMU_PCR_PJ_APBSD | MPMU_PCR_PJ_AXISD | 1 << 13); + __raw_writel(apcr, MPMU_PCR_PJ); + + return 0; +} + +late_initcall(mmp2_pm_init); -- cgit v0.10.2 From 3f5d081957cee794fe2937bb7edafa7ac949044d Mon Sep 17 00:00:00 2001 From: Chao Xie Date: Mon, 7 May 2012 11:23:58 +0800 Subject: ARM: mm: proc-mohawk: add suspend resume for mohawk When enable ARCH_SUSPEND_POSSIBLE, it need defintion of cpu_mohawk_do_suspend and cpu_mohawk_do_resume Signed-off-by: Chao Xie Signed-off-by: Haojian Zhuang < diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 4cf9d42..aaa22f8 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -2275,7 +2275,7 @@ source "kernel/power/Kconfig" config ARCH_SUSPEND_POSSIBLE depends on !ARCH_S5PC100 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \ - CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE + CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK def_bool y config ARM_CPU_SUSPEND diff --git a/arch/arm/mm/proc-mohawk.S b/arch/arm/mm/proc-mohawk.S index cdfedc5..6a050b1 100644 --- a/arch/arm/mm/proc-mohawk.S +++ b/arch/arm/mm/proc-mohawk.S @@ -344,6 +344,41 @@ ENTRY(cpu_mohawk_set_pte_ext) mcr p15, 0, r0, c7, c10, 4 @ drain WB mov pc, lr +.globl cpu_mohawk_suspend_size +.equ cpu_mohawk_suspend_size, 4 * 6 +#ifdef CONFIG_PM_SLEEP +ENTRY(cpu_mohawk_do_suspend) + stmfd sp!, {r4 - r9, lr} + mrc p14, 0, r4, c6, c0, 0 @ clock configuration, for turbo mode + mrc p15, 0, r5, c15, c1, 0 @ CP access reg + mrc p15, 0, r6, c13, c0, 0 @ PID + mrc p15, 0, r7, c3, c0, 0 @ domain ID + mrc p15, 0, r8, c1, c0, 1 @ auxiliary control reg + mrc p15, 0, r9, c1, c0, 0 @ control reg + bic r4, r4, #2 @ clear frequency change bit + stmia r0, {r4 - r9} @ store cp regs + ldmia sp!, {r4 - r9, pc} +ENDPROC(cpu_mohawk_do_suspend) + +ENTRY(cpu_mohawk_do_resume) + ldmia r0, {r4 - r9} @ load cp regs + mov ip, #0 + mcr p15, 0, ip, c7, c7, 0 @ invalidate I & D caches, BTB + mcr p15, 0, ip, c7, c10, 4 @ drain write (&fill) buffer + mcr p15, 0, ip, c7, c5, 4 @ flush prefetch buffer + mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs + mcr p14, 0, r4, c6, c0, 0 @ clock configuration, turbo mode. + mcr p15, 0, r5, c15, c1, 0 @ CP access reg + mcr p15, 0, r6, c13, c0, 0 @ PID + mcr p15, 0, r7, c3, c0, 0 @ domain ID + orr r1, r1, #0x18 @ cache the page table in L2 + mcr p15, 0, r1, c2, c0, 0 @ translation table base addr + mcr p15, 0, r8, c1, c0, 1 @ auxiliary control reg + mov r0, r9 @ control register + b cpu_resume_mmu +ENDPROC(cpu_mohawk_do_resume) +#endif + __CPUINIT .type __mohawk_setup, #function -- cgit v0.10.2 From 89326f76b7ae602eb6a2d3e4cc028190fc8d480f Mon Sep 17 00:00:00 2001 From: Chao Xie Date: Mon, 7 May 2012 11:23:59 +0800 Subject: ARM: cache: tauros2: add disable and resume callback For the SOC chips using tauros2 cache, will need disable and resume tauros2 cache for SOC suspend/resume. Signed-off-by: Chao Xie Signed-off-by: Haojian Zhuang diff --git a/arch/arm/mm/cache-tauros2.c b/arch/arm/mm/cache-tauros2.c index 1fbca05..23a7643 100644 --- a/arch/arm/mm/cache-tauros2.c +++ b/arch/arm/mm/cache-tauros2.c @@ -108,6 +108,26 @@ static void tauros2_flush_range(unsigned long start, unsigned long end) dsb(); } + +static void tauros2_disable(void) +{ + __asm__ __volatile__ ( + "mcr p15, 1, %0, c7, c11, 0 @L2 Cache Clean All\n\t" + "mrc p15, 0, %0, c1, c0, 0\n\t" + "bic %0, %0, #(1 << 26)\n\t" + "mcr p15, 0, %0, c1, c0, 0 @Disable L2 Cache\n\t" + : : "r" (0x0)); +} + +static void tauros2_resume(void) +{ + __asm__ __volatile__ ( + "mcr p15, 1, %0, c7, c7, 0 @L2 Cache Invalidate All\n\t" + "mrc p15, 0, %0, c1, c0, 0\n\t" + "orr %0, %0, #(1 << 26)\n\t" + "mcr p15, 0, %0, c1, c0, 0 @Enable L2 Cache\n\t" + : : "r" (0x0)); +} #endif static inline u32 __init read_extra_features(void) @@ -194,6 +214,8 @@ void __init tauros2_init(void) outer_cache.inv_range = tauros2_inv_range; outer_cache.clean_range = tauros2_clean_range; outer_cache.flush_range = tauros2_flush_range; + outer_cache.disable = tauros2_disable; + outer_cache.resume = tauros2_resume; } #endif @@ -219,6 +241,8 @@ void __init tauros2_init(void) outer_cache.inv_range = tauros2_inv_range; outer_cache.clean_range = tauros2_clean_range; outer_cache.flush_range = tauros2_flush_range; + outer_cache.disable = tauros2_disable; + outer_cache.resume = tauros2_resume; } #endif -- cgit v0.10.2 From f4466946c103372d3dd845ec55af1d2dc89ece33 Mon Sep 17 00:00:00 2001 From: Chao Xie Date: Mon, 7 May 2012 11:24:00 +0800 Subject: ARM: mmp: ttc_dkb: add PMIC support Add 88pm860x into ttc_dkb, and it will impact the suspend/resume of pxa910 Signed-off-by: Chao Xie Signed-off-by: Haojian Zhuang diff --git a/arch/arm/mach-mmp/ttc_dkb.c b/arch/arm/mach-mmp/ttc_dkb.c index 3fc9ed2..e8cf5ea 100644 --- a/arch/arm/mach-mmp/ttc_dkb.c +++ b/arch/arm/mach-mmp/ttc_dkb.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include @@ -135,8 +136,18 @@ static struct pca953x_platform_data max7312_data[] = { }, }; +static struct pm860x_platform_data ttc_dkb_pm8607_info = { + .irq_base = IRQ_BOARD_START, +}; + static struct i2c_board_info ttc_dkb_i2c_info[] = { { + .type = "88PM860x", + .addr = 0x34, + .platform_data = &ttc_dkb_pm8607_info, + .irq = IRQ_PXA910_PMIC_INT, + }, + { .type = "max7312", .addr = 0x23, .irq = MMP_GPIO_TO_IRQ(80), -- cgit v0.10.2 From 902ca2297180fe97f840427c114cc6dc7e77375e Mon Sep 17 00:00:00 2001 From: Chao Xie Date: Mon, 7 May 2012 11:24:01 +0800 Subject: ARM: mmp: add pm support for pxa910 add suspend/resume functionality for pxa910 Signed-off-by: Chao Xie Signed-off-by: Raul Xiong Signed-off-by: Haojian Zhuang diff --git a/arch/arm/mach-mmp/Makefile b/arch/arm/mach-mmp/Makefile index 7d60cef..b786f7e 100644 --- a/arch/arm/mach-mmp/Makefile +++ b/arch/arm/mach-mmp/Makefile @@ -10,6 +10,7 @@ obj-$(CONFIG_CPU_PXA910) += pxa910.o obj-$(CONFIG_CPU_MMP2) += mmp2.o sram.o ifeq ($(CONFIG_PM),y) +obj-$(CONFIG_CPU_PXA910) += pm-pxa910.o obj-$(CONFIG_CPU_MMP2) += pm-mmp2.o endif diff --git a/arch/arm/mach-mmp/include/mach/pm-pxa910.h b/arch/arm/mach-mmp/include/mach/pm-pxa910.h new file mode 100644 index 0000000..8cac8ab --- /dev/null +++ b/arch/arm/mach-mmp/include/mach/pm-pxa910.h @@ -0,0 +1,77 @@ +/* + * PXA910 Power Management Routines + * + * This software program is licensed subject to the GNU General Public License + * (GPL).Version 2,June 1991, available at http://www.fsf.org/copyleft/gpl.html + * + * (C) Copyright 2009 Marvell International Ltd. + * All Rights Reserved + */ + +#ifndef __PXA910_PM_H__ +#define __PXA910_PM_H__ + +#define APMU_MOH_IDLE_CFG APMU_REG(0x0018) +#define APMU_MOH_IDLE_CFG_MOH_IDLE (1 << 1) +#define APMU_MOH_IDLE_CFG_MOH_PWRDWN (1 << 5) +#define APMU_MOH_IDLE_CFG_MOH_SRAM_PWRDWN (1 << 6) +#define APMU_MOH_IDLE_CFG_MOH_PWR_SW(x) (((x) & 0x3) << 16) +#define APMU_MOH_IDLE_CFG_MOH_L2_PWR_SW(x) (((x) & 0x3) << 18) +#define APMU_MOH_IDLE_CFG_MOH_DIS_MC_SW_REQ (1 << 21) +#define APMU_MOH_IDLE_CFG_MOH_MC_WAKE_EN (1 << 20) + +#define APMU_SQU_CLK_GATE_CTRL APMU_REG(0x001c) +#define APMU_MC_HW_SLP_TYPE APMU_REG(0x00b0) + +#define MPMU_FCCR MPMU_REG(0x0008) +#define MPMU_APCR MPMU_REG(0x1000) +#define MPMU_APCR_AXISD (1 << 31) +#define MPMU_APCR_DSPSD (1 << 30) +#define MPMU_APCR_SLPEN (1 << 29) +#define MPMU_APCR_DTCMSD (1 << 28) +#define MPMU_APCR_DDRCORSD (1 << 27) +#define MPMU_APCR_APBSD (1 << 26) +#define MPMU_APCR_BBSD (1 << 25) +#define MPMU_APCR_SLPWP0 (1 << 23) +#define MPMU_APCR_SLPWP1 (1 << 22) +#define MPMU_APCR_SLPWP2 (1 << 21) +#define MPMU_APCR_SLPWP3 (1 << 20) +#define MPMU_APCR_VCTCXOSD (1 << 19) +#define MPMU_APCR_SLPWP4 (1 << 18) +#define MPMU_APCR_SLPWP5 (1 << 17) +#define MPMU_APCR_SLPWP6 (1 << 16) +#define MPMU_APCR_SLPWP7 (1 << 15) +#define MPMU_APCR_MSASLPEN (1 << 14) +#define MPMU_APCR_STBYEN (1 << 13) + +#define MPMU_AWUCRM MPMU_REG(0x104c) +#define MPMU_AWUCRM_AP_ASYNC_INT (1 << 25) +#define MPMU_AWUCRM_AP_FULL_IDLE (1 << 24) +#define MPMU_AWUCRM_SDH1 (1 << 23) +#define MPMU_AWUCRM_SDH2 (1 << 22) +#define MPMU_AWUCRM_KEYPRESS (1 << 21) +#define MPMU_AWUCRM_TRACKBALL (1 << 20) +#define MPMU_AWUCRM_NEWROTARY (1 << 19) +#define MPMU_AWUCRM_RTC_ALARM (1 << 17) +#define MPMU_AWUCRM_AP2_TIMER_3 (1 << 13) +#define MPMU_AWUCRM_AP2_TIMER_2 (1 << 12) +#define MPMU_AWUCRM_AP2_TIMER_1 (1 << 11) +#define MPMU_AWUCRM_AP1_TIMER_3 (1 << 10) +#define MPMU_AWUCRM_AP1_TIMER_2 (1 << 9) +#define MPMU_AWUCRM_AP1_TIMER_1 (1 << 8) +#define MPMU_AWUCRM_WAKEUP(x) (1 << ((x) & 0x7)) + +enum { + POWER_MODE_ACTIVE = 0, + POWER_MODE_CORE_INTIDLE, + POWER_MODE_CORE_EXTIDLE, + POWER_MODE_APPS_IDLE, + POWER_MODE_APPS_SLEEP, + POWER_MODE_SYS_SLEEP, + POWER_MODE_HIBERNATE, + POWER_MODE_UDR, +}; + +extern int pxa910_set_wake(struct irq_data *data, unsigned int on); + +#endif diff --git a/arch/arm/mach-mmp/irq.c b/arch/arm/mach-mmp/irq.c index 04935f1..fcfe0e3 100644 --- a/arch/arm/mach-mmp/irq.c +++ b/arch/arm/mach-mmp/irq.c @@ -26,6 +26,9 @@ #ifdef CONFIG_CPU_MMP2 #include #endif +#ifdef CONFIG_CPU_PXA910 +#include +#endif #include "common.h" @@ -213,6 +216,9 @@ void __init icu_init_irq(void) set_irq_flags(irq, IRQF_VALID); } irq_set_default_host(icu_data[0].domain); +#ifdef CONFIG_CPU_PXA910 + icu_irq_chip.irq_set_wake = pxa910_set_wake; +#endif } /* MMP2 (ARMv7) */ diff --git a/arch/arm/mach-mmp/pm-pxa910.c b/arch/arm/mach-mmp/pm-pxa910.c new file mode 100644 index 0000000..48981ca --- /dev/null +++ b/arch/arm/mach-mmp/pm-pxa910.c @@ -0,0 +1,285 @@ +/* + * PXA910 Power Management Routines + * + * This software program is licensed subject to the GNU General Public License + * (GPL).Version 2,June 1991, available at http://www.fsf.org/copyleft/gpl.html + * + * (C) Copyright 2009 Marvell International Ltd. + * All Rights Reserved + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +int pxa910_set_wake(struct irq_data *data, unsigned int on) +{ + int irq = data->irq; + struct irq_desc *desc = irq_to_desc(data->irq); + uint32_t awucrm = 0, apcr = 0; + + if (unlikely(irq >= nr_irqs)) { + pr_err("IRQ nubmers are out of boundary!\n"); + return -EINVAL; + } + + if (on) { + if (desc->action) + desc->action->flags |= IRQF_NO_SUSPEND; + } else { + if (desc->action) + desc->action->flags &= ~IRQF_NO_SUSPEND; + } + + /* setting wakeup sources */ + switch (irq) { + /* wakeup line 2 */ + case IRQ_PXA910_AP_GPIO: + awucrm = MPMU_AWUCRM_WAKEUP(2); + apcr |= MPMU_APCR_SLPWP2; + break; + /* wakeup line 3 */ + case IRQ_PXA910_KEYPAD: + awucrm = MPMU_AWUCRM_WAKEUP(3) | MPMU_AWUCRM_KEYPRESS; + apcr |= MPMU_APCR_SLPWP3; + break; + case IRQ_PXA910_ROTARY: + awucrm = MPMU_AWUCRM_WAKEUP(3) | MPMU_AWUCRM_NEWROTARY; + apcr |= MPMU_APCR_SLPWP3; + break; + case IRQ_PXA910_TRACKBALL: + awucrm = MPMU_AWUCRM_WAKEUP(3) | MPMU_AWUCRM_TRACKBALL; + apcr |= MPMU_APCR_SLPWP3; + break; + /* wakeup line 4 */ + case IRQ_PXA910_AP1_TIMER1: + awucrm = MPMU_AWUCRM_WAKEUP(4) | MPMU_AWUCRM_AP1_TIMER_1; + apcr |= MPMU_APCR_SLPWP4; + break; + case IRQ_PXA910_AP1_TIMER2: + awucrm = MPMU_AWUCRM_WAKEUP(4) | MPMU_AWUCRM_AP1_TIMER_2; + apcr |= MPMU_APCR_SLPWP4; + break; + case IRQ_PXA910_AP1_TIMER3: + awucrm = MPMU_AWUCRM_WAKEUP(4) | MPMU_AWUCRM_AP1_TIMER_3; + apcr |= MPMU_APCR_SLPWP4; + break; + case IRQ_PXA910_AP2_TIMER1: + awucrm = MPMU_AWUCRM_WAKEUP(4) | MPMU_AWUCRM_AP2_TIMER_1; + apcr |= MPMU_APCR_SLPWP4; + break; + case IRQ_PXA910_AP2_TIMER2: + awucrm = MPMU_AWUCRM_WAKEUP(4) | MPMU_AWUCRM_AP2_TIMER_2; + apcr |= MPMU_APCR_SLPWP4; + break; + case IRQ_PXA910_AP2_TIMER3: + awucrm = MPMU_AWUCRM_WAKEUP(4) | MPMU_AWUCRM_AP2_TIMER_3; + apcr |= MPMU_APCR_SLPWP4; + break; + case IRQ_PXA910_RTC_ALARM: + awucrm = MPMU_AWUCRM_WAKEUP(4) | MPMU_AWUCRM_RTC_ALARM; + apcr |= MPMU_APCR_SLPWP4; + break; + /* wakeup line 5 */ + case IRQ_PXA910_USB1: + case IRQ_PXA910_USB2: + awucrm = MPMU_AWUCRM_WAKEUP(5); + apcr |= MPMU_APCR_SLPWP5; + break; + /* wakeup line 6 */ + case IRQ_PXA910_MMC: + awucrm = MPMU_AWUCRM_WAKEUP(6) + | MPMU_AWUCRM_SDH1 + | MPMU_AWUCRM_SDH2; + apcr |= MPMU_APCR_SLPWP6; + break; + /* wakeup line 7 */ + case IRQ_PXA910_PMIC_INT: + awucrm = MPMU_AWUCRM_WAKEUP(7); + apcr |= MPMU_APCR_SLPWP7; + break; + default: + if (irq >= IRQ_GPIO_START && irq < IRQ_BOARD_START) { + awucrm = MPMU_AWUCRM_WAKEUP(2); + apcr |= MPMU_APCR_SLPWP2; + } else + printk(KERN_ERR "Error: no defined wake up source irq: %d\n", + irq); + } + + if (on) { + if (awucrm) { + awucrm |= __raw_readl(MPMU_AWUCRM); + __raw_writel(awucrm, MPMU_AWUCRM); + } + if (apcr) { + apcr = ~apcr & __raw_readl(MPMU_APCR); + __raw_writel(apcr, MPMU_APCR); + } + } else { + if (awucrm) { + awucrm = ~awucrm & __raw_readl(MPMU_AWUCRM); + __raw_writel(awucrm, MPMU_AWUCRM); + } + if (apcr) { + apcr |= __raw_readl(MPMU_APCR); + __raw_writel(apcr, MPMU_APCR); + } + } + return 0; +} + +void pxa910_pm_enter_lowpower_mode(int state) +{ + uint32_t idle_cfg, apcr; + + idle_cfg = __raw_readl(APMU_MOH_IDLE_CFG); + apcr = __raw_readl(MPMU_APCR); + + apcr &= ~(MPMU_APCR_DDRCORSD | MPMU_APCR_APBSD | MPMU_APCR_AXISD + | MPMU_APCR_VCTCXOSD | MPMU_APCR_STBYEN); + idle_cfg &= ~(APMU_MOH_IDLE_CFG_MOH_IDLE + | APMU_MOH_IDLE_CFG_MOH_PWRDWN); + + switch (state) { + case POWER_MODE_UDR: + /* only shutdown APB in UDR */ + apcr |= MPMU_APCR_STBYEN | MPMU_APCR_APBSD; + /* fall through */ + case POWER_MODE_SYS_SLEEP: + apcr |= MPMU_APCR_SLPEN; /* set the SLPEN bit */ + apcr |= MPMU_APCR_VCTCXOSD; /* set VCTCXOSD */ + /* fall through */ + case POWER_MODE_APPS_SLEEP: + apcr |= MPMU_APCR_DDRCORSD; /* set DDRCORSD */ + /* fall through */ + case POWER_MODE_APPS_IDLE: + apcr |= MPMU_APCR_AXISD; /* set AXISDD bit */ + /* fall through */ + case POWER_MODE_CORE_EXTIDLE: + idle_cfg |= APMU_MOH_IDLE_CFG_MOH_IDLE; + idle_cfg |= APMU_MOH_IDLE_CFG_MOH_PWRDWN; + idle_cfg |= APMU_MOH_IDLE_CFG_MOH_PWR_SW(3) + | APMU_MOH_IDLE_CFG_MOH_L2_PWR_SW(3); + /* fall through */ + case POWER_MODE_CORE_INTIDLE: + break; + } + + /* program the memory controller hardware sleep type and auto wakeup */ + idle_cfg |= APMU_MOH_IDLE_CFG_MOH_DIS_MC_SW_REQ; + idle_cfg |= APMU_MOH_IDLE_CFG_MOH_MC_WAKE_EN; + __raw_writel(0x0, APMU_MC_HW_SLP_TYPE); /* auto refresh */ + + /* set DSPSD, DTCMSD, BBSD, MSASLPEN */ + apcr |= MPMU_APCR_DSPSD | MPMU_APCR_DTCMSD | MPMU_APCR_BBSD + | MPMU_APCR_MSASLPEN; + + /*always set SLEPEN bit mainly for MSA*/ + apcr |= MPMU_APCR_SLPEN; + + /* finally write the registers back */ + __raw_writel(idle_cfg, APMU_MOH_IDLE_CFG); + __raw_writel(apcr, MPMU_APCR); + +} + +static int pxa910_pm_enter(suspend_state_t state) +{ + unsigned int idle_cfg, reg = 0; + + /*pmic thread not completed,exit;otherwise system can't be waked up*/ + reg = __raw_readl(ICU_INT_CONF(IRQ_PXA910_PMIC_INT)); + if ((reg & 0x3) == 0) + return -EAGAIN; + + idle_cfg = __raw_readl(APMU_MOH_IDLE_CFG); + idle_cfg |= APMU_MOH_IDLE_CFG_MOH_PWRDWN + | APMU_MOH_IDLE_CFG_MOH_SRAM_PWRDWN; + __raw_writel(idle_cfg, APMU_MOH_IDLE_CFG); + + /* disable L2 */ + outer_disable(); + /* wait for l2 idle */ + while (!(readl(CIU_REG(0x8)) & (1 << 16))) + udelay(1); + + cpu_do_idle(); + + /* enable L2 */ + outer_resume(); + /* wait for l2 idle */ + while (!(readl(CIU_REG(0x8)) & (1 << 16))) + udelay(1); + + idle_cfg = __raw_readl(APMU_MOH_IDLE_CFG); + idle_cfg &= ~(APMU_MOH_IDLE_CFG_MOH_PWRDWN + | APMU_MOH_IDLE_CFG_MOH_SRAM_PWRDWN); + __raw_writel(idle_cfg, APMU_MOH_IDLE_CFG); + + return 0; +} + +/* + * Called after processes are frozen, but before we shut down devices. + */ +static int pxa910_pm_prepare(void) +{ + pxa910_pm_enter_lowpower_mode(POWER_MODE_UDR); + return 0; +} + +/* + * Called after devices are re-setup, but before processes are thawed. + */ +static void pxa910_pm_finish(void) +{ + pxa910_pm_enter_lowpower_mode(POWER_MODE_CORE_INTIDLE); +} + +static int pxa910_pm_valid(suspend_state_t state) +{ + return ((state == PM_SUSPEND_STANDBY) || (state == PM_SUSPEND_MEM)); +} + +static const struct platform_suspend_ops pxa910_pm_ops = { + .valid = pxa910_pm_valid, + .prepare = pxa910_pm_prepare, + .enter = pxa910_pm_enter, + .finish = pxa910_pm_finish, +}; + +static int __init pxa910_pm_init(void) +{ + uint32_t awucrm = 0; + + if (!cpu_is_pxa910()) + return -EIO; + + suspend_set_ops(&pxa910_pm_ops); + + /* Set the following bits for MMP3 playback with VCTXO on */ + __raw_writel(__raw_readl(APMU_SQU_CLK_GATE_CTRL) | (1 << 30), + APMU_SQU_CLK_GATE_CTRL); + __raw_writel(__raw_readl(MPMU_FCCR) | (1 << 28), MPMU_FCCR); + + awucrm |= MPMU_AWUCRM_AP_ASYNC_INT | MPMU_AWUCRM_AP_FULL_IDLE; + __raw_writel(awucrm, MPMU_AWUCRM); + + return 0; +} + +late_initcall(pxa910_pm_init); -- cgit v0.10.2 From 875e6897e0dc2cf568b0975ea7b5d0e9ca1f1e46 Mon Sep 17 00:00:00 2001 From: Kevin Hilman Date: Mon, 7 May 2012 23:55:10 -0600 Subject: ARM: OMAP3: clock data: replace 3503/3517 flag with AM35x flag for UART4 The AM35x UART4 is common to all AM35x devices, so use CK_AM35XX instead of (CK_3505 | CK_3517), which is equivalent. Acked-by: Vaibhav Hiremath Tested-by: Vaibhav Hiremath Signed-off-by: Kevin Hilman Signed-off-by: Paul Walmsley diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c index f4a626f7..dac076a 100644 --- a/arch/arm/mach-omap2/clock3xxx_data.c +++ b/arch/arm/mach-omap2/clock3xxx_data.c @@ -3419,7 +3419,7 @@ static struct omap_clk omap3xxx_clks[] = { CLK(NULL, "per_48m_fck", &per_48m_fck, CK_3XXX), CLK(NULL, "uart3_fck", &uart3_fck, CK_3XXX), CLK(NULL, "uart4_fck", &uart4_fck, CK_36XX), - CLK(NULL, "uart4_fck", &uart4_fck_am35xx, CK_3505 | CK_3517), + CLK(NULL, "uart4_fck", &uart4_fck_am35xx, CK_AM35XX), CLK(NULL, "gpt2_fck", &gpt2_fck, CK_3XXX), CLK(NULL, "gpt3_fck", &gpt3_fck, CK_3XXX), CLK(NULL, "gpt4_fck", &gpt4_fck, CK_3XXX), -- cgit v0.10.2 From c93a98c9024d687e91a3414cb3d5f74d0abf3068 Mon Sep 17 00:00:00 2001 From: Kevin Hilman Date: Mon, 7 May 2012 23:55:10 -0600 Subject: ARM: OMAP3: clock data: treat all AM35x devices the same The init for 3505/3517 specific clocks depends on the ordering of cpu_is checks, is error prone and confusing (there are 2 separate checks for cpu_is_omap3505()). Remove the 3505-specific checking since CK_3505 flag is not used, and treat all AM35x clocks the same. This means that the SGX clock (the only AM35x clkdev not currently flagged for 3505) will now be registered on 3505, but that is harmless. That can be cleaned up when the clkdev nodes are removed in favor of them being registered by hwmod. Acked-by: Vaibhav Hiremath Tested-by: Vaibhav Hiremath Signed-off-by: Kevin Hilman Signed-off-by: Paul Walmsley diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c index dac076a..23b1e78 100644 --- a/arch/arm/mach-omap2/clock3xxx_data.c +++ b/arch/arm/mach-omap2/clock3xxx_data.c @@ -3513,21 +3513,9 @@ int __init omap3xxx_clk_init(void) struct omap_clk *c; u32 cpu_clkflg = 0; - /* - * 3505 must be tested before 3517, since 3517 returns true - * for both AM3517 chips and AM3517 family chips, which - * includes 3505. Unfortunately there's no obvious family - * test for 3517/3505 :-( - */ - if (cpu_is_omap3505()) { - cpu_mask = RATE_IN_34XX; - cpu_clkflg = CK_3505; - } else if (cpu_is_omap3517()) { + if (cpu_is_omap3517()) { cpu_mask = RATE_IN_34XX; cpu_clkflg = CK_3517; - } else if (cpu_is_omap3505()) { - cpu_mask = RATE_IN_34XX; - cpu_clkflg = CK_3505; } else if (cpu_is_omap3630()) { cpu_mask = (RATE_IN_34XX | RATE_IN_36XX); cpu_clkflg = CK_36XX; -- cgit v0.10.2 From f0c54d31b04243ab761dc0d7a122b77adf8d0a3a Mon Sep 17 00:00:00 2001 From: Kevin Hilman Date: Mon, 7 May 2012 23:55:11 -0600 Subject: ARM: OMAP: clock: convert AM3517/3505 detection/flags to AM35xx To improve the clarity of the code, replace the CK_3517 flag used in the clock data with CK_AM35XX. The CK_3505 flag can also be removed, since it is now unused. Acked-by: Vaibhav Hiremath Signed-off-by: Kevin Hilman Signed-off-by: Paul Walmsley diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c index 23b1e78..8000693 100644 --- a/arch/arm/mach-omap2/clock3xxx_data.c +++ b/arch/arm/mach-omap2/clock3xxx_data.c @@ -3294,8 +3294,8 @@ static struct omap_clk omap3xxx_clks[] = { CLK(NULL, "gfx_l3_ick", &gfx_l3_ick, CK_3430ES1), CLK(NULL, "gfx_cg1_ck", &gfx_cg1_ck, CK_3430ES1), CLK(NULL, "gfx_cg2_ck", &gfx_cg2_ck, CK_3430ES1), - CLK(NULL, "sgx_fck", &sgx_fck, CK_3430ES2PLUS | CK_3517 | CK_36XX), - CLK(NULL, "sgx_ick", &sgx_ick, CK_3430ES2PLUS | CK_3517 | CK_36XX), + CLK(NULL, "sgx_fck", &sgx_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), + CLK(NULL, "sgx_ick", &sgx_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), CLK(NULL, "d2d_26m_fck", &d2d_26m_fck, CK_3430ES1), CLK(NULL, "modem_fck", &modem_fck, CK_34XX | CK_36XX), CLK(NULL, "sad2d_ick", &sad2d_ick, CK_34XX | CK_36XX), @@ -3515,7 +3515,7 @@ int __init omap3xxx_clk_init(void) if (cpu_is_omap3517()) { cpu_mask = RATE_IN_34XX; - cpu_clkflg = CK_3517; + cpu_clkflg = CK_AM35XX; } else if (cpu_is_omap3630()) { cpu_mask = (RATE_IN_34XX | RATE_IN_36XX); cpu_clkflg = CK_36XX; diff --git a/arch/arm/plat-omap/include/plat/clkdev_omap.h b/arch/arm/plat-omap/include/plat/clkdev_omap.h index b299b8d..d0ed8c4 100644 --- a/arch/arm/plat-omap/include/plat/clkdev_omap.h +++ b/arch/arm/plat-omap/include/plat/clkdev_omap.h @@ -34,8 +34,7 @@ struct omap_clk { #define CK_243X (1 << 5) /* 243x, 253x */ #define CK_3430ES1 (1 << 6) /* 34xxES1 only */ #define CK_3430ES2PLUS (1 << 7) /* 34xxES2, ES3, non-Sitara 35xx only */ -#define CK_3505 (1 << 8) -#define CK_3517 (1 << 9) +#define CK_AM35XX (1 << 9) /* Sitara AM35xx */ #define CK_36XX (1 << 10) /* 36xx/37xx-specific clocks */ #define CK_443X (1 << 11) #define CK_TI816X (1 << 12) @@ -44,7 +43,6 @@ struct omap_clk { #define CK_34XX (CK_3430ES1 | CK_3430ES2PLUS) -#define CK_AM35XX (CK_3505 | CK_3517) /* all Sitara AM35xx */ #define CK_3XXX (CK_34XX | CK_AM35XX | CK_36XX) -- cgit v0.10.2 From 4e68f5a79da5b595fc40ceff5ebcfa3e6637bf37 Mon Sep 17 00:00:00 2001 From: Rajendra Nayak Date: Mon, 7 May 2012 23:55:21 -0600 Subject: ARM: OMAP3: Fix CM register bit masks The register bits for MPU_CLK_SRC and IVA2_CLK_SRC in CM_CLKSEL1_PLL register are 3 bits wide. Fix the MASK definition accordingly. Signed-off-by: Rajendra Nayak Signed-off-by: Paul Walmsley diff --git a/arch/arm/mach-omap2/cm-regbits-34xx.h b/arch/arm/mach-omap2/cm-regbits-34xx.h index b912759..8083a8c 100644 --- a/arch/arm/mach-omap2/cm-regbits-34xx.h +++ b/arch/arm/mach-omap2/cm-regbits-34xx.h @@ -79,7 +79,7 @@ /* CM_CLKSEL1_PLL_IVA2 */ #define OMAP3430_IVA2_CLK_SRC_SHIFT 19 -#define OMAP3430_IVA2_CLK_SRC_MASK (0x3 << 19) +#define OMAP3430_IVA2_CLK_SRC_MASK (0x7 << 19) #define OMAP3430_IVA2_DPLL_MULT_SHIFT 8 #define OMAP3430_IVA2_DPLL_MULT_MASK (0x7ff << 8) #define OMAP3430_IVA2_DPLL_DIV_SHIFT 0 @@ -124,7 +124,7 @@ /* CM_CLKSEL1_PLL_MPU */ #define OMAP3430_MPU_CLK_SRC_SHIFT 19 -#define OMAP3430_MPU_CLK_SRC_MASK (0x3 << 19) +#define OMAP3430_MPU_CLK_SRC_MASK (0x7 << 19) #define OMAP3430_MPU_DPLL_MULT_SHIFT 8 #define OMAP3430_MPU_DPLL_MULT_MASK (0x7ff << 8) #define OMAP3430_MPU_DPLL_DIV_SHIFT 0 -- cgit v0.10.2 From 444b3df6b387e6dd55cd9dbc8924e111792d2c42 Mon Sep 17 00:00:00 2001 From: Vaibhav Hiremath Date: Mon, 7 May 2012 23:55:21 -0600 Subject: ARM: OMAP2/3: Add idle_st bits for ST_32KSYNC timer to prcm-common header Add missing idle_st bit for 32k-sync timer into the prcm-common header file, required for hwmod data. Signed-off-by: Vaibhav Hiremath Reviewed-by: Santosh Shilimkar Cc: Felipe Balbi Cc: Benoit Cousson Cc: Tony Lindgren Cc: Paul Walmsley Cc: Kevin Hilman Signed-off-by: Paul Walmsley diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h index 5aa5435..29955d5 100644 --- a/arch/arm/mach-omap2/prcm-common.h +++ b/arch/arm/mach-omap2/prcm-common.h @@ -177,6 +177,8 @@ /* PM_WKST_WKUP, CM_IDLEST_WKUP shared bits */ #define OMAP24XX_ST_GPIOS_SHIFT 2 #define OMAP24XX_ST_GPIOS_MASK (1 << 2) +#define OMAP24XX_ST_32KSYNC_SHIFT 1 +#define OMAP24XX_ST_32KSYNC_MASK (1 << 1) #define OMAP24XX_ST_GPT1_SHIFT 0 #define OMAP24XX_ST_GPT1_MASK (1 << 0) @@ -307,6 +309,8 @@ #define OMAP3430_ST_SR1_MASK (1 << 6) #define OMAP3430_ST_GPIO1_SHIFT 3 #define OMAP3430_ST_GPIO1_MASK (1 << 3) +#define OMAP3430_ST_32KSYNC_SHIFT 2 +#define OMAP3430_ST_32KSYNC_MASK (1 << 2) #define OMAP3430_ST_GPT12_SHIFT 1 #define OMAP3430_ST_GPT12_MASK (1 << 1) #define OMAP3430_ST_GPT1_SHIFT 0 -- cgit v0.10.2 From 610eb8c218ef214594295776275855640d37ab2a Mon Sep 17 00:00:00 2001 From: R Sricharan Date: Mon, 7 May 2012 23:55:22 -0600 Subject: ARM: OMAP4+: Add prm and cm base init function. Instead of statically defining seperate arrays for every OMAP4+ archs, have a generic init function to populate the arrays. This avoids the need for creating new array for every arch added in the future that reuses the prm and cm registers read/write code. Cc: Paul Walmsley Signed-off-by: R Sricharan Signed-off-by: Santosh Shilimkar Signed-off-by: Paul Walmsley diff --git a/arch/arm/mach-omap2/cminst44xx.c b/arch/arm/mach-omap2/cminst44xx.c index bd8810c..8c86d29 100644 --- a/arch/arm/mach-omap2/cminst44xx.c +++ b/arch/arm/mach-omap2/cminst44xx.c @@ -32,6 +32,7 @@ #include "prcm44xx.h" #include "prm44xx.h" #include "prcm_mpu44xx.h" +#include "prcm-common.h" /* * CLKCTRL_IDLEST_*: possible values for the CM_*_CLKCTRL.IDLEST bitfield: @@ -49,14 +50,21 @@ #define CLKCTRL_IDLEST_INTERFACE_IDLE 0x2 #define CLKCTRL_IDLEST_DISABLED 0x3 -static u32 _cm_bases[OMAP4_MAX_PRCM_PARTITIONS] = { - [OMAP4430_INVALID_PRCM_PARTITION] = 0, - [OMAP4430_PRM_PARTITION] = OMAP4430_PRM_BASE, - [OMAP4430_CM1_PARTITION] = OMAP4430_CM1_BASE, - [OMAP4430_CM2_PARTITION] = OMAP4430_CM2_BASE, - [OMAP4430_SCRM_PARTITION] = 0, - [OMAP4430_PRCM_MPU_PARTITION] = OMAP4430_PRCM_MPU_BASE, -}; +static void __iomem *_cm_bases[OMAP4_MAX_PRCM_PARTITIONS]; + +/** + * omap_cm_base_init - Populates the cm partitions + * + * Populates the base addresses of the _cm_bases + * array used for read/write of cm module registers. + */ +void omap_cm_base_init(void) +{ + _cm_bases[OMAP4430_PRM_PARTITION] = prm_base; + _cm_bases[OMAP4430_CM1_PARTITION] = cm_base; + _cm_bases[OMAP4430_CM2_PARTITION] = cm2_base; + _cm_bases[OMAP4430_PRCM_MPU_PARTITION] = prcm_mpu_base; +} /* Private functions */ @@ -106,7 +114,7 @@ u32 omap4_cminst_read_inst_reg(u8 part, s16 inst, u16 idx) BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS || part == OMAP4430_INVALID_PRCM_PARTITION || !_cm_bases[part]); - return __raw_readl(OMAP2_L4_IO_ADDRESS(_cm_bases[part] + inst + idx)); + return __raw_readl(_cm_bases[part] + inst + idx); } /* Write into a register in a CM instance */ @@ -115,7 +123,7 @@ void omap4_cminst_write_inst_reg(u32 val, u8 part, s16 inst, u16 idx) BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS || part == OMAP4430_INVALID_PRCM_PARTITION || !_cm_bases[part]); - __raw_writel(val, OMAP2_L4_IO_ADDRESS(_cm_bases[part] + inst + idx)); + __raw_writel(val, _cm_bases[part] + inst + idx); } /* Read-modify-write a register in CM1. Caller must lock */ diff --git a/arch/arm/mach-omap2/common.c b/arch/arm/mach-omap2/common.c index 1549c11..8a6953a 100644 --- a/arch/arm/mach-omap2/common.c +++ b/arch/arm/mach-omap2/common.c @@ -166,6 +166,7 @@ static struct omap_globals omap4_globals = { .prm = OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE), .cm = OMAP2_L4_IO_ADDRESS(OMAP4430_CM_BASE), .cm2 = OMAP2_L4_IO_ADDRESS(OMAP4430_CM2_BASE), + .prcm_mpu = OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE), }; void __init omap2_set_globals_443x(void) diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h index 57da7f4..0672fc5 100644 --- a/arch/arm/mach-omap2/common.h +++ b/arch/arm/mach-omap2/common.h @@ -111,6 +111,7 @@ struct omap_globals { void __iomem *prm; /* Power and Reset Management */ void __iomem *cm; /* Clock Management */ void __iomem *cm2; + void __iomem *prcm_mpu; }; void omap2_set_globals_242x(void); diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h index 29955d5..6da3ba4 100644 --- a/arch/arm/mach-omap2/prcm-common.h +++ b/arch/arm/mach-omap2/prcm-common.h @@ -414,6 +414,19 @@ extern void __iomem *prm_base; extern void __iomem *cm_base; extern void __iomem *cm2_base; +extern void __iomem *prcm_mpu_base; + +#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_ARCH_OMAP5) +extern void omap_prm_base_init(void); +extern void omap_cm_base_init(void); +#else +static inline void omap_prm_base_init(void) +{ +} +static inline void omap_cm_base_init(void) +{ +} +#endif /** * struct omap_prcm_irq - describes a PRCM interrupt bit diff --git a/arch/arm/mach-omap2/prcm.c b/arch/arm/mach-omap2/prcm.c index 626acfa..480f40a 100644 --- a/arch/arm/mach-omap2/prcm.c +++ b/arch/arm/mach-omap2/prcm.c @@ -42,6 +42,7 @@ void __iomem *prm_base; void __iomem *cm_base; void __iomem *cm2_base; +void __iomem *prcm_mpu_base; #define MAX_MODULE_ENABLE_WAIT 100000 @@ -155,4 +156,11 @@ void __init omap2_set_globals_prcm(struct omap_globals *omap2_globals) cm_base = omap2_globals->cm; if (omap2_globals->cm2) cm2_base = omap2_globals->cm2; + if (omap2_globals->prcm_mpu) + prcm_mpu_base = omap2_globals->prcm_mpu; + + if (cpu_is_omap44xx()) { + omap_prm_base_init(); + omap_cm_base_init(); + } } diff --git a/arch/arm/mach-omap2/prminst44xx.c b/arch/arm/mach-omap2/prminst44xx.c index 9b3898a..c12320c0 100644 --- a/arch/arm/mach-omap2/prminst44xx.c +++ b/arch/arm/mach-omap2/prminst44xx.c @@ -18,20 +18,26 @@ #include "iomap.h" #include "common.h" +#include "prcm-common.h" #include "prm44xx.h" #include "prminst44xx.h" #include "prm-regbits-44xx.h" #include "prcm44xx.h" #include "prcm_mpu44xx.h" -static u32 _prm_bases[OMAP4_MAX_PRCM_PARTITIONS] = { - [OMAP4430_INVALID_PRCM_PARTITION] = 0, - [OMAP4430_PRM_PARTITION] = OMAP4430_PRM_BASE, - [OMAP4430_CM1_PARTITION] = 0, - [OMAP4430_CM2_PARTITION] = 0, - [OMAP4430_SCRM_PARTITION] = 0, - [OMAP4430_PRCM_MPU_PARTITION] = OMAP4430_PRCM_MPU_BASE, -}; +static void __iomem *_prm_bases[OMAP4_MAX_PRCM_PARTITIONS]; + +/** + * omap_prm_base_init - Populates the prm partitions + * + * Populates the base addresses of the _prm_bases + * array used for read/write of prm module registers. + */ +void omap_prm_base_init(void) +{ + _prm_bases[OMAP4430_PRM_PARTITION] = prm_base; + _prm_bases[OMAP4430_PRCM_MPU_PARTITION] = prcm_mpu_base; +} /* Read a register in a PRM instance */ u32 omap4_prminst_read_inst_reg(u8 part, s16 inst, u16 idx) @@ -39,8 +45,7 @@ u32 omap4_prminst_read_inst_reg(u8 part, s16 inst, u16 idx) BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS || part == OMAP4430_INVALID_PRCM_PARTITION || !_prm_bases[part]); - return __raw_readl(OMAP2_L4_IO_ADDRESS(_prm_bases[part] + inst + - idx)); + return __raw_readl(_prm_bases[part] + inst + idx); } /* Write into a register in a PRM instance */ @@ -49,7 +54,7 @@ void omap4_prminst_write_inst_reg(u32 val, u8 part, s16 inst, u16 idx) BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS || part == OMAP4430_INVALID_PRCM_PARTITION || !_prm_bases[part]); - __raw_writel(val, OMAP2_L4_IO_ADDRESS(_prm_bases[part] + inst + idx)); + __raw_writel(val, _prm_bases[part] + inst + idx); } /* Read-modify-write a register in PRM. Caller must lock */ -- cgit v0.10.2 From f1bbbb1365fdb1abe29f31d4ac455f265f9bc2ff Mon Sep 17 00:00:00 2001 From: Tarun Kanti DebBarma Date: Mon, 7 May 2012 23:55:30 -0600 Subject: ARM: OMAP2+: dmtimer: cleanup iclk usage We do not use iclk anywhere in the dmtimer driver and so removing it. Hence removing the timer iclk entries from OMAP4 clkdev table as well. Signed-off-by: Tarun Kanti DebBarma Signed-off-by: Paul Walmsley diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c index fa6ea65..2172f66 100644 --- a/arch/arm/mach-omap2/clock44xx_data.c +++ b/arch/arm/mach-omap2/clock44xx_data.c @@ -3355,17 +3355,6 @@ static struct omap_clk omap44xx_clks[] = { CLK(NULL, "auxclk5_ck", &auxclk5_ck, CK_443X), CLK(NULL, "auxclkreq5_ck", &auxclkreq5_ck, CK_443X), CLK(NULL, "gpmc_ck", &dummy_ck, CK_443X), - CLK(NULL, "gpt1_ick", &dummy_ck, CK_443X), - CLK(NULL, "gpt2_ick", &dummy_ck, CK_443X), - CLK(NULL, "gpt3_ick", &dummy_ck, CK_443X), - CLK(NULL, "gpt4_ick", &dummy_ck, CK_443X), - CLK(NULL, "gpt5_ick", &dummy_ck, CK_443X), - CLK(NULL, "gpt6_ick", &dummy_ck, CK_443X), - CLK(NULL, "gpt7_ick", &dummy_ck, CK_443X), - CLK(NULL, "gpt8_ick", &dummy_ck, CK_443X), - CLK(NULL, "gpt9_ick", &dummy_ck, CK_443X), - CLK(NULL, "gpt10_ick", &dummy_ck, CK_443X), - CLK(NULL, "gpt11_ick", &dummy_ck, CK_443X), CLK("omap_i2c.1", "ick", &dummy_ck, CK_443X), CLK("omap_i2c.2", "ick", &dummy_ck, CK_443X), CLK("omap_i2c.3", "ick", &dummy_ck, CK_443X), diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c index ecec873..1b78358 100644 --- a/arch/arm/mach-omap2/timer.c +++ b/arch/arm/mach-omap2/timer.c @@ -178,13 +178,6 @@ static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer, if (IS_ERR(timer->fclk)) return -ENODEV; - sprintf(name, "gpt%d_ick", gptimer_id); - timer->iclk = clk_get(NULL, name); - if (IS_ERR(timer->iclk)) { - clk_put(timer->fclk); - return -ENODEV; - } - omap_hwmod_enable(oh); sys_timer_reserved |= (1 << (gptimer_id - 1)); diff --git a/arch/arm/plat-omap/include/plat/dmtimer.h b/arch/arm/plat-omap/include/plat/dmtimer.h index 9418f00..be2b8c4 100644 --- a/arch/arm/plat-omap/include/plat/dmtimer.h +++ b/arch/arm/plat-omap/include/plat/dmtimer.h @@ -259,7 +259,7 @@ struct omap_dm_timer { unsigned long phys_base; int id; int irq; - struct clk *iclk, *fclk; + struct clk *fclk; void __iomem *io_base; void __iomem *sys_stat; /* TISTAT timer status */ -- cgit v0.10.2 From d76316fef3f2ecec210b78a38263a06bb4f6c1b9 Mon Sep 17 00:00:00 2001 From: Vaibhav Bedia Date: Mon, 7 May 2012 23:55:30 -0600 Subject: ARM: OMAP3+: dpll: Configure autoidle mode only if it's supported The current DPLL code enables and disables autoidle features without checking whether the autoidle register is available. Fix this by putting a check for the existence of the autoidle register in the DPLL data. With such a check in place, for DPLLs which do not support this feature, simply skipping the autoidle_reg entry in the DPLL data is sufficient. Signed-off-by: Vaibhav Bedia Signed-off-by: Paul Walmsley diff --git a/arch/arm/mach-omap2/dpll3xxx.c b/arch/arm/mach-omap2/dpll3xxx.c index fc56745..f0f10be 100644 --- a/arch/arm/mach-omap2/dpll3xxx.c +++ b/arch/arm/mach-omap2/dpll3xxx.c @@ -142,7 +142,8 @@ static int _omap3_noncore_dpll_lock(struct clk *clk) ai = omap3_dpll_autoidle_read(clk); - omap3_dpll_deny_idle(clk); + if (ai) + omap3_dpll_deny_idle(clk); _omap3_dpll_write_clken(clk, DPLL_LOCKED); @@ -186,8 +187,6 @@ static int _omap3_noncore_dpll_bypass(struct clk *clk) if (ai) omap3_dpll_allow_idle(clk); - else - omap3_dpll_deny_idle(clk); return r; } @@ -216,8 +215,6 @@ static int _omap3_noncore_dpll_stop(struct clk *clk) if (ai) omap3_dpll_allow_idle(clk); - else - omap3_dpll_deny_idle(clk); return 0; } @@ -519,6 +516,9 @@ u32 omap3_dpll_autoidle_read(struct clk *clk) dd = clk->dpll_data; + if (!dd->autoidle_reg) + return -EINVAL; + v = __raw_readl(dd->autoidle_reg); v &= dd->autoidle_mask; v >>= __ffs(dd->autoidle_mask); @@ -545,6 +545,12 @@ void omap3_dpll_allow_idle(struct clk *clk) dd = clk->dpll_data; + if (!dd->autoidle_reg) { + pr_debug("clock: DPLL %s: autoidle not supported\n", + clk->name); + return; + } + /* * REVISIT: CORE DPLL can optionally enter low-power bypass * by writing 0x5 instead of 0x1. Add some mechanism to @@ -554,6 +560,7 @@ void omap3_dpll_allow_idle(struct clk *clk) v &= ~dd->autoidle_mask; v |= DPLL_AUTOIDLE_LOW_POWER_STOP << __ffs(dd->autoidle_mask); __raw_writel(v, dd->autoidle_reg); + } /** @@ -572,6 +579,12 @@ void omap3_dpll_deny_idle(struct clk *clk) dd = clk->dpll_data; + if (!dd->autoidle_reg) { + pr_debug("clock: DPLL %s: autoidle not supported\n", + clk->name); + return; + } + v = __raw_readl(dd->autoidle_reg); v &= ~dd->autoidle_mask; v |= DPLL_AUTOIDLE_DISABLE << __ffs(dd->autoidle_mask); -- cgit v0.10.2 From 8f97437eb54f32bb8678904c2f827a853a3d076c Mon Sep 17 00:00:00 2001 From: Paul Walmsley Date: Mon, 7 May 2012 23:55:31 -0600 Subject: ARM: OMAP3: clock data: add clockdomain for HDQ functional clock Add the correct clockdomain for the HDQ functional clock. This is needed for the clock and hwmod PM code to work correctly. Signed-off-by: Paul Walmsley Cc: NeilBrown diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c index f4a626f7..8fe7d70 100644 --- a/arch/arm/mach-omap2/clock3xxx_data.c +++ b/arch/arm/mach-omap2/clock3xxx_data.c @@ -1,7 +1,7 @@ /* * OMAP3 clock data * - * Copyright (C) 2007-2010 Texas Instruments, Inc. + * Copyright (C) 2007-2010, 2012 Texas Instruments, Inc. * Copyright (C) 2007-2011 Nokia Corporation * * Written by Paul Walmsley @@ -1640,6 +1640,7 @@ static struct clk hdq_fck = { .name = "hdq_fck", .ops = &clkops_omap2_dflt_wait, .parent = &core_12m_fck, + .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP3430_EN_HDQ_SHIFT, .recalc = &followparent_recalc, -- cgit v0.10.2 From 5a68a736581290d10e2ebaf2e5baa8e21eed6dd5 Mon Sep 17 00:00:00 2001 From: Santosh Shilimkar Date: Mon, 7 May 2012 23:55:38 -0600 Subject: ARM: OMAP2+: powerdomain: Get rid off duplicate pwrdm_clkdm_state_switch() API With patch 'ARM: OMAP2+: powerdomain: Wait for powerdomain transition in pwrdm_state_switch()', the pwrdm_clkdm_state_switch() API becomes duplicate of pwrdm_state_switch(). Get rid off duplicate pwrdm_clkdm_state_switch() and update the users of it with pwrdm_state_switch() Signed-off-by: Santosh Shilimkar Cc: Rajendra Nayak Cc: Paul Walmsley Signed-off-by: Paul Walmsley diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index f57ed5b..77db067 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c @@ -439,7 +439,7 @@ void omap2_clk_disable_unused(struct clk *clk) clk->ops->disable(clk); } if (clk->clkdm != NULL) - pwrdm_clkdm_state_switch(clk->clkdm); + pwrdm_state_switch(clk->clkdm->pwrdm.ptr); } #endif diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c index ad07689..8664f5a 100644 --- a/arch/arm/mach-omap2/clockdomain.c +++ b/arch/arm/mach-omap2/clockdomain.c @@ -840,7 +840,7 @@ void clkdm_allow_idle(struct clockdomain *clkdm) spin_lock_irqsave(&clkdm->lock, flags); clkdm->_flags |= _CLKDM_FLAG_HWSUP_ENABLED; arch_clkdm->clkdm_allow_idle(clkdm); - pwrdm_clkdm_state_switch(clkdm); + pwrdm_state_switch(clkdm->pwrdm.ptr); spin_unlock_irqrestore(&clkdm->lock, flags); } @@ -924,8 +924,7 @@ static int _clkdm_clk_hwmod_enable(struct clockdomain *clkdm) spin_lock_irqsave(&clkdm->lock, flags); arch_clkdm->clkdm_clk_enable(clkdm); - pwrdm_wait_transition(clkdm->pwrdm.ptr); - pwrdm_clkdm_state_switch(clkdm); + pwrdm_state_switch(clkdm->pwrdm.ptr); spin_unlock_irqrestore(&clkdm->lock, flags); pr_debug("clockdomain: clkdm %s: enabled\n", clkdm->name); @@ -950,7 +949,7 @@ static int _clkdm_clk_hwmod_disable(struct clockdomain *clkdm) spin_lock_irqsave(&clkdm->lock, flags); arch_clkdm->clkdm_clk_disable(clkdm); - pwrdm_clkdm_state_switch(clkdm); + pwrdm_state_switch(clkdm->pwrdm.ptr); spin_unlock_irqrestore(&clkdm->lock, flags); pr_debug("clockdomain: clkdm %s: disabled\n", clkdm->name); diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c index 96ad3dbe..9611490 100644 --- a/arch/arm/mach-omap2/powerdomain.c +++ b/arch/arm/mach-omap2/powerdomain.c @@ -981,16 +981,6 @@ int pwrdm_state_switch(struct powerdomain *pwrdm) return ret; } -int pwrdm_clkdm_state_switch(struct clockdomain *clkdm) -{ - if (clkdm != NULL && clkdm->pwrdm.ptr != NULL) { - pwrdm_wait_transition(clkdm->pwrdm.ptr); - return pwrdm_state_switch(clkdm->pwrdm.ptr); - } - - return -EINVAL; -} - int pwrdm_pre_transition(void) { pwrdm_for_each(_pwrdm_pre_transition_cb, NULL); diff --git a/arch/arm/mach-omap2/powerdomain.h b/arch/arm/mach-omap2/powerdomain.h index 0d72a8a..8f88d65 100644 --- a/arch/arm/mach-omap2/powerdomain.h +++ b/arch/arm/mach-omap2/powerdomain.h @@ -213,7 +213,6 @@ bool pwrdm_has_hdwr_sar(struct powerdomain *pwrdm); int pwrdm_wait_transition(struct powerdomain *pwrdm); int pwrdm_state_switch(struct powerdomain *pwrdm); -int pwrdm_clkdm_state_switch(struct clockdomain *clkdm); int pwrdm_pre_transition(void); int pwrdm_post_transition(void); int pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm); -- cgit v0.10.2 From 48a6884fd14d6e3c0efc3d97621c662ee6f6ae0f Mon Sep 17 00:00:00 2001 From: "Mark A. Greer" Date: Mon, 7 May 2012 23:55:38 -0600 Subject: arm: omap3: clockdomain data: Remove superfluous commas from gfx_sgx_3xxx_wkdeps[] Clean up clockdomains3xxx_data.c a bit by removing the superfluous commas in gfx_sgx_3xxx_wkdeps[]. Signed-off-by: Mark A. Greer Signed-off-by: Paul Walmsley diff --git a/arch/arm/mach-omap2/clockdomains3xxx_data.c b/arch/arm/mach-omap2/clockdomains3xxx_data.c index b84e138..6038adb 100644 --- a/arch/arm/mach-omap2/clockdomains3xxx_data.c +++ b/arch/arm/mach-omap2/clockdomains3xxx_data.c @@ -53,9 +53,9 @@ * 3430ES2 PM_WKDEP_SGX: adds IVA2, removes CORE */ static struct clkdm_dep gfx_sgx_3xxx_wkdeps[] = { - { .clkdm_name = "iva2_clkdm", }, - { .clkdm_name = "mpu_clkdm", }, - { .clkdm_name = "wkup_clkdm", }, + { .clkdm_name = "iva2_clkdm" }, + { .clkdm_name = "mpu_clkdm" }, + { .clkdm_name = "wkup_clkdm" }, { NULL }, }; -- cgit v0.10.2 From ad1b6662eb5fe293e8b402497b3835710848c389 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Tue, 8 May 2012 17:23:33 -0600 Subject: ARM: OMAP2420: hwmod data: Add MMC hwmod data for 2420 Add MMC for 2420 so we can pass the DMA request lines the same way as we already do on omap2430 and later. Cc: Benoit Cousson Cc: Paul Walmsley Signed-off-by: Tony Lindgren [paul@pwsan.com: updated to apply on top of the 3.5 hwmod cleanup; changed mmc hwmod name/class to "msdi" as documented in the 2420 TRM Rev X; added sysconfig register information; added 16 bit register width flag; added MSDI custom reset code] Signed-off-by: Paul Walmsley diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index d8604a3..4eee0f1 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -189,6 +189,9 @@ ifneq ($(CONFIG_TIDSPBRIDGE),) obj-y += dsp.o endif +# OMAP2420 MSDI controller integration support ("MMC") +obj-$(CONFIG_SOC_OMAP2420) += msdi.o + # Specific board support obj-$(CONFIG_MACH_OMAP_GENERIC) += board-generic.o obj-$(CONFIG_MACH_OMAP_H4) += board-h4.o diff --git a/arch/arm/mach-omap2/msdi.c b/arch/arm/mach-omap2/msdi.c new file mode 100644 index 0000000..ef2a692 --- /dev/null +++ b/arch/arm/mach-omap2/msdi.c @@ -0,0 +1,88 @@ +/* + * MSDI IP block reset + * + * Copyright (C) 2012 Texas Instruments, Inc. + * Paul Walmsley + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA + * 02110-1301 USA + * + * XXX What about pad muxing? + */ + +#include + +#include +#include + +#include "common.h" + +/* + * MSDI_CON_OFFSET: offset in bytes of the MSDI IP block's CON register + * from the IP block's base address + */ +#define MSDI_CON_OFFSET 0x0c + +/* Register bitfields in the CON register */ +#define MSDI_CON_POW_MASK BIT(11) +#define MSDI_CON_CLKD_MASK (0x3f << 0) +#define MSDI_CON_CLKD_SHIFT 0 + +/* Maximum microseconds to wait for OMAP module to softreset */ +#define MAX_MODULE_SOFTRESET_WAIT 10000 + +/* MSDI_TARGET_RESET_CLKD: clock divisor to use throughout the reset */ +#define MSDI_TARGET_RESET_CLKD 0x3ff + +/** + * omap_msdi_reset - reset the MSDI IP block + * @oh: struct omap_hwmod * + * + * The MSDI IP block on OMAP2420 has to have both the POW and CLKD + * fields set inside its CON register for a reset to complete + * successfully. This is not documented in the TRM. For CLKD, we use + * the value that results in the lowest possible clock rate, to attempt + * to avoid disturbing any cards. + */ +int omap_msdi_reset(struct omap_hwmod *oh) +{ + u16 v = 0; + int c = 0; + + /* Write to the SOFTRESET bit */ + omap_hwmod_softreset(oh); + + /* Enable the MSDI core and internal clock */ + v |= MSDI_CON_POW_MASK; + v |= MSDI_TARGET_RESET_CLKD << MSDI_CON_CLKD_SHIFT; + omap_hwmod_write(v, oh, MSDI_CON_OFFSET); + + /* Poll on RESETDONE bit */ + omap_test_timeout((omap_hwmod_read(oh, oh->class->sysc->syss_offs) + & SYSS_RESETDONE_MASK), + MAX_MODULE_SOFTRESET_WAIT, c); + + if (c == MAX_MODULE_SOFTRESET_WAIT) + pr_warning("%s: %s: softreset failed (waited %d usec)\n", + __func__, oh->name, MAX_MODULE_SOFTRESET_WAIT); + else + pr_debug("%s: %s: softreset in %d usec\n", __func__, + oh->name, c); + + /* Disable the MSDI internal clock */ + v &= ~MSDI_CON_CLKD_MASK; + omap_hwmod_write(v, oh, MSDI_CON_OFFSET); + + return 0; +} diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c index 2c087ff..0c08d3f 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c @@ -23,6 +23,7 @@ #include #include #include +#include #include "omap_hwmod_common_data.h" @@ -239,6 +240,50 @@ static struct omap_hwmod omap2420_mcbsp2_hwmod = { }, }; +static struct omap_hwmod_class_sysconfig omap2420_msdi_sysc = { + .rev_offs = 0x3c, + .sysc_offs = 0x64, + .syss_offs = 0x68, + .sysc_flags = (SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap2420_msdi_hwmod_class = { + .name = "msdi", + .sysc = &omap2420_msdi_sysc, + .reset = &omap_msdi_reset, +}; + +/* msdi1 */ +static struct omap_hwmod_irq_info omap2420_msdi1_irqs[] = { + { .irq = 83 }, + { .irq = -1 } +}; + +static struct omap_hwmod_dma_info omap2420_msdi1_sdma_reqs[] = { + { .name = "tx", .dma_req = 61 }, /* OMAP24XX_DMA_MMC1_TX */ + { .name = "rx", .dma_req = 62 }, /* OMAP24XX_DMA_MMC1_RX */ + { .dma_req = -1 } +}; + +static struct omap_hwmod omap2420_msdi1_hwmod = { + .name = "msdi1", + .class = &omap2420_msdi_hwmod_class, + .mpu_irqs = omap2420_msdi1_irqs, + .sdma_reqs = omap2420_msdi1_sdma_reqs, + .main_clk = "mmc_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP2420_EN_MMC_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP2420_ST_MMC_SHIFT, + }, + }, + .flags = HWMOD_16BIT_REG, +}; + /* * interfaces */ @@ -428,6 +473,24 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp2 = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; +static struct omap_hwmod_addr_space omap2420_msdi1_addrs[] = { + { + .pa_start = 0x4809c000, + .pa_end = 0x4809c000 + SZ_128 - 1, + .flags = ADDR_TYPE_RT, + }, + { } +}; + +/* l4_core -> msdi1 */ +static struct omap_hwmod_ocp_if omap2420_l4_core__msdi1 = { + .master = &omap2xxx_l4_core_hwmod, + .slave = &omap2420_msdi1_hwmod, + .clk = "mmc_ick", + .addr = omap2420_msdi1_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + static struct omap_hwmod_ocp_if *omap2420_hwmod_ocp_ifs[] __initdata = { &omap2xxx_l3_main__l4_core, &omap2xxx_mpu__l3_main, @@ -468,6 +531,7 @@ static struct omap_hwmod_ocp_if *omap2420_hwmod_ocp_ifs[] __initdata = { &omap2420_l4_core__mailbox, &omap2420_l4_core__mcbsp1, &omap2420_l4_core__mcbsp2, + &omap2420_l4_core__msdi1, NULL, }; diff --git a/arch/arm/plat-omap/include/plat/mmc.h b/arch/arm/plat-omap/include/plat/mmc.h index 7a38750..3e7ae0f 100644 --- a/arch/arm/plat-omap/include/plat/mmc.h +++ b/arch/arm/plat-omap/include/plat/mmc.h @@ -16,6 +16,7 @@ #include #include +#include #define OMAP15XX_NR_MMC 1 #define OMAP16XX_NR_MMC 2 @@ -195,4 +196,7 @@ static inline int omap_mmc_add(const char *name, int id, unsigned long base, } #endif + +extern int omap_msdi_reset(struct omap_hwmod *oh); + #endif -- cgit v0.10.2 From 9e1b7498d79ab9076791807172d4603c7be63c1b Mon Sep 17 00:00:00 2001 From: Paul Walmsley Date: Tue, 8 May 2012 11:34:27 -0600 Subject: ARM: OMAP2+: HDQ1W: add custom reset function Implement a custom reset function for the HDQ1W IP block. This is because the HDQ1W IP block, like I2C, has an internal clock gating bit that needs to be toggled after setting the SOFTRESET bit to allow the reset to propagate. Signed-off-by: Paul Walmsley Cc: NeilBrown Cc: Avinash.H.M Tested-by: NeilBrown diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index 4eee0f1..385c083 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -4,7 +4,7 @@ # Common support obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer.o pm.o \ - common.o gpio.o dma.o wd_timer.o display.o i2c.o + common.o gpio.o dma.o wd_timer.o display.o i2c.o hdq1w.o omap-2-3-common = irq.o sdrc.o hwmod-common = omap_hwmod.o \ diff --git a/arch/arm/mach-omap2/hdq1w.c b/arch/arm/mach-omap2/hdq1w.c new file mode 100644 index 0000000..297ebe0 --- /dev/null +++ b/arch/arm/mach-omap2/hdq1w.c @@ -0,0 +1,72 @@ +/* + * IP block integration code for the HDQ1W/1-wire IP block + * + * Copyright (C) 2012 Texas Instruments, Inc. + * Paul Walmsley + * + * Based on the I2C reset code in arch/arm/mach-omap2/i2c.c by + * Avinash.H.M + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA + * 02110-1301 USA + */ + +#include +#include + +#include "common.h" + +/* Maximum microseconds to wait for OMAP module to softreset */ +#define MAX_MODULE_SOFTRESET_WAIT 10000 + +/** + * omap_hdq1w_reset - reset the OMAP HDQ1W module + * @oh: struct omap_hwmod * + * + * OCP soft reset the HDQ1W IP block. Section 20.6.1.4 "HDQ1W/1-Wire + * Software Reset" of the OMAP34xx Technical Reference Manual Revision + * ZR (SWPU223R) does not include the rather important fact that, for + * the reset to succeed, the HDQ1W module's internal clock gate must be + * programmed to allow the clock to propagate to the rest of the + * module. In this sense, it's rather similar to the I2C custom reset + * function. Returns 0. + */ +int omap_hdq1w_reset(struct omap_hwmod *oh) +{ + u32 v; + int c = 0; + + /* Write to the SOFTRESET bit */ + omap_hwmod_softreset(oh); + + /* Enable the module's internal clocks */ + v = omap_hwmod_read(oh, HDQ_CTRL_STATUS_OFFSET); + v |= 1 << HDQ_CTRL_STATUS_CLOCKENABLE_SHIFT; + omap_hwmod_write(v, oh, HDQ_CTRL_STATUS_OFFSET); + + /* Poll on RESETDONE bit */ + omap_test_timeout((omap_hwmod_read(oh, + oh->class->sysc->syss_offs) + & SYSS_RESETDONE_MASK), + MAX_MODULE_SOFTRESET_WAIT, c); + + if (c == MAX_MODULE_SOFTRESET_WAIT) + pr_warning("%s: %s: softreset failed (waited %d usec)\n", + __func__, oh->name, MAX_MODULE_SOFTRESET_WAIT); + else + pr_debug("%s: %s: softreset in %d usec\n", __func__, + oh->name, c); + + return 0; +} diff --git a/arch/arm/plat-omap/include/plat/hdq1w.h b/arch/arm/plat-omap/include/plat/hdq1w.h new file mode 100644 index 0000000..0c1efc8 --- /dev/null +++ b/arch/arm/plat-omap/include/plat/hdq1w.h @@ -0,0 +1,36 @@ +/* + * Shared macros and function prototypes for the HDQ1W/1-wire IP block + * + * Copyright (C) 2012 Texas Instruments, Inc. + * Paul Walmsley + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA + * 02110-1301 USA + */ +#ifndef ARCH_ARM_MACH_OMAP2_HDQ1W_H +#define ARCH_ARM_MACH_OMAP2_HDQ1W_H + +#include + +/* + * XXX A future cleanup patch should modify + * drivers/w1/masters/omap_hdq.c to use these macros + */ +#define HDQ_CTRL_STATUS_OFFSET 0x0c +#define HDQ_CTRL_STATUS_CLOCKENABLE_SHIFT 5 + + +extern int omap_hdq1w_reset(struct omap_hwmod *oh); + +#endif -- cgit v0.10.2 From 03d830e8dcbe4e8168a85252fcb639b48342ed3c Mon Sep 17 00:00:00 2001 From: Paul Walmsley Date: Tue, 8 May 2012 11:34:27 -0600 Subject: ARM: OMAP2+: hwmod data: add HDQ/1-wire hwmod shared data Much of the HDQ1W integration data is common between multiple generations of OMAP SoCs, so rather than make several copies, we add it once into files which are compiled for multiple SoCs. Signed-off-by: Paul Walmsley Cc: NeilBrown Tested-by: NeilBrown diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_interconnect_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_interconnect_data.c index 04637fa..cbb4ef6 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_interconnect_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_interconnect_data.c @@ -171,3 +171,12 @@ struct omap_hwmod_addr_space omap2_mcbsp1_addrs[] = { }, { } }; + +struct omap_hwmod_addr_space omap2_hdq1w_addr_space[] = { + { + .pa_start = 0x480b2000, + .pa_end = 0x480b2fff, + .flags = ADDR_TYPE_RT, + }, + { } +}; diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c index f08e442..102d76e 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c @@ -2,6 +2,7 @@ * omap_hwmod_2xxx_3xxx_ipblock_data.c - common IP block data for OMAP2/3 * * Copyright (C) 2011 Nokia Corporation + * Copyright (C) 2012 Texas Instruments, Inc. * Paul Walmsley * * This program is free software; you can redistribute it and/or modify @@ -12,6 +13,7 @@ #include #include #include +#include #include @@ -302,3 +304,23 @@ struct omap_hwmod_irq_info omap2_mcspi2_mpu_irqs[] = { { .irq = -1 } }; +struct omap_hwmod_class_sysconfig omap2_hdq1w_sysc = { + .rev_offs = 0x0, + .sysc_offs = 0x14, + .syss_offs = 0x18, + .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | + SYSS_HAS_RESET_STATUS), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +struct omap_hwmod_class omap2_hdq1w_class = { + .name = "hdq1w", + .sysc = &omap2_hdq1w_sysc, + .reset = &omap_hdq1w_reset, +}; + +struct omap_hwmod_irq_info omap2_hdq1w_mpu_irqs[] = { + { .irq = 58, }, + { .irq = -1 } +}; + diff --git a/arch/arm/mach-omap2/omap_hwmod_common_data.h b/arch/arm/mach-omap2/omap_hwmod_common_data.h index 7aa9156..e244829 100644 --- a/arch/arm/mach-omap2/omap_hwmod_common_data.h +++ b/arch/arm/mach-omap2/omap_hwmod_common_data.h @@ -38,6 +38,7 @@ extern struct omap_hwmod_addr_space omap2430_mcspi3_addr_space[]; extern struct omap_hwmod_addr_space omap2_dma_system_addrs[]; extern struct omap_hwmod_addr_space omap2_mailbox_addrs[]; extern struct omap_hwmod_addr_space omap2_mcbsp1_addrs[]; +extern struct omap_hwmod_addr_space omap2_hdq1w_addr_space[]; /* Common IP block data across OMAP2xxx */ extern struct omap_hwmod_irq_info omap2xxx_timer12_mpu_irqs[]; @@ -141,6 +142,7 @@ extern struct omap_hwmod_irq_info omap2_dma_system_irqs[]; extern struct omap_hwmod_irq_info omap2_mcspi1_mpu_irqs[]; extern struct omap_hwmod_irq_info omap2_mcspi2_mpu_irqs[]; extern struct omap_hwmod_addr_space omap2xxx_timer12_addrs[]; +extern struct omap_hwmod_irq_info omap2_hdq1w_mpu_irqs[]; /* OMAP hwmod classes - forward declarations */ extern struct omap_hwmod_class l3_hwmod_class; @@ -152,6 +154,8 @@ extern struct omap_hwmod_class omap2_dss_hwmod_class; extern struct omap_hwmod_class omap2_dispc_hwmod_class; extern struct omap_hwmod_class omap2_rfbi_hwmod_class; extern struct omap_hwmod_class omap2_venc_hwmod_class; +extern struct omap_hwmod_class_sysconfig omap2_hdq1w_sysc; +extern struct omap_hwmod_class omap2_hdq1w_class; extern struct omap_hwmod_class omap2xxx_timer_hwmod_class; extern struct omap_hwmod_class omap2xxx_wd_timer_hwmod_class; -- cgit v0.10.2 From 45a4bb067c25355b5d362eb09fa97e51a2a519c8 Mon Sep 17 00:00:00 2001 From: Paul Walmsley Date: Tue, 8 May 2012 11:34:28 -0600 Subject: ARM: OMAP3: hwmod data: add HDQ/1-wire hwmod Add the HDQ1W hwmod for OMAP34xx, OMAP36xx, and AM3505/3517 devices. According to the respective TRMs, it doesn't appear to be available for the 816x/814x or the AM335x. The OCPIF_SWSUP_IDLE flag is added to work around an apparent hardware bug: the hardware is not taking the CM_FCLKEN*_CORE.EN_HDQ bit into account when considering whether to go idle: http://www.spinics.net/lists/linux-omap/msg63576.html This causes HDQ transfers to fail or become corrupt. Thanks to NeilBrown for his help diagnosing and testing fixes for this problem. Signed-off-by: Paul Walmsley Cc: NeilBrown Tested-by: NeilBrown diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c index 0c65079..97c6597 100644 --- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c @@ -1980,6 +1980,22 @@ static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod = { }, }; +static struct omap_hwmod omap3xxx_hdq1w_hwmod = { + .name = "hdq1w", + .mpu_irqs = omap2_hdq1w_mpu_irqs, + .main_clk = "hdq_fck", + .prcm = { + .omap2 = { + .module_offs = CORE_MOD, + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_HDQ_SHIFT, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_ST_HDQ_SHIFT, + }, + }, + .class = &omap2_hdq1w_class, +}; + /* * interfaces */ @@ -3059,6 +3075,16 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_tll_hs = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; +/* l4_core -> hdq1w interface */ +static struct omap_hwmod_ocp_if omap3xxx_l4_core__hdq1w = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_hdq1w_hwmod, + .clk = "hdq_ick", + .addr = omap2_hdq1w_addr_space, + .user = OCP_USER_MPU | OCP_USER_SDMA, + .flags = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE, +}; + static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = { &omap3xxx_l3_main__l4_core, &omap3xxx_l3_main__l4_per, @@ -3151,6 +3177,7 @@ static struct omap_hwmod_ocp_if *omap34xx_hwmod_ocp_ifs[] __initdata = { &omap34xx_l4_core__sr1, &omap34xx_l4_core__sr2, &omap3xxx_l4_core__mailbox, + &omap3xxx_l4_core__hdq1w, NULL }; @@ -3170,6 +3197,7 @@ static struct omap_hwmod_ocp_if *omap36xx_hwmod_ocp_ifs[] __initdata = { &omap3xxx_l4_core__usb_tll_hs, &omap3xxx_l4_core__es3plus_mmc1, &omap3xxx_l4_core__es3plus_mmc2, + &omap3xxx_l4_core__hdq1w, NULL }; -- cgit v0.10.2 From f32bd7787561ceb887e45d81ca41d6c7a903751f Mon Sep 17 00:00:00 2001 From: Paul Walmsley Date: Tue, 8 May 2012 11:34:28 -0600 Subject: ARM: OMAP2xxx: hwmod data: add HDQ/1-wire hwmod Add the HDQ1W hwmod for all OMAP2xxx devices. Assume that OMAP2xxx chips have the same HDQ idle handling bug as OMAP3: http://www.spinics.net/lists/linux-omap/msg63576.html and set the OCPIF_SWSUP_IDLE flag accordingly on the HDQ's OCP interface. Signed-off-by: Paul Walmsley diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c index 0c08d3f..85419f8 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c @@ -284,6 +284,23 @@ static struct omap_hwmod omap2420_msdi1_hwmod = { .flags = HWMOD_16BIT_REG, }; +/* HDQ1W/1-wire */ +static struct omap_hwmod omap2420_hdq1w_hwmod = { + .name = "hdq1w", + .mpu_irqs = omap2_hdq1w_mpu_irqs, + .main_clk = "hdq_fck", + .prcm = { + .omap2 = { + .module_offs = CORE_MOD, + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_HDQ_SHIFT, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_HDQ_SHIFT, + }, + }, + .class = &omap2_hdq1w_class, +}; + /* * interfaces */ @@ -491,6 +508,17 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__msdi1 = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; +/* l4_core -> hdq1w interface */ +static struct omap_hwmod_ocp_if omap2420_l4_core__hdq1w = { + .master = &omap2xxx_l4_core_hwmod, + .slave = &omap2420_hdq1w_hwmod, + .clk = "hdq_ick", + .addr = omap2_hdq1w_addr_space, + .user = OCP_USER_MPU | OCP_USER_SDMA, + .flags = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE, +}; + + static struct omap_hwmod_ocp_if *omap2420_hwmod_ocp_ifs[] __initdata = { &omap2xxx_l3_main__l4_core, &omap2xxx_mpu__l3_main, @@ -532,6 +560,7 @@ static struct omap_hwmod_ocp_if *omap2420_hwmod_ocp_ifs[] __initdata = { &omap2420_l4_core__mcbsp1, &omap2420_l4_core__mcbsp2, &omap2420_l4_core__msdi1, + &omap2420_l4_core__hdq1w, NULL, }; diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c index 71d9f88..ff93a8d 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c @@ -528,6 +528,23 @@ static struct omap_hwmod omap2430_mmc2_hwmod = { .class = &omap2430_mmc_class, }; +/* HDQ1W/1-wire */ +static struct omap_hwmod omap2430_hdq1w_hwmod = { + .name = "hdq1w", + .mpu_irqs = omap2_hdq1w_mpu_irqs, + .main_clk = "hdq_fck", + .prcm = { + .omap2 = { + .module_offs = CORE_MOD, + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_HDQ_SHIFT, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_HDQ_SHIFT, + }, + }, + .class = &omap2_hdq1w_class, +}; + /* * interfaces */ @@ -838,6 +855,16 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp5 = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; +/* l4_core -> hdq1w */ +static struct omap_hwmod_ocp_if omap2430_l4_core__hdq1w = { + .master = &omap2xxx_l4_core_hwmod, + .slave = &omap2430_hdq1w_hwmod, + .clk = "hdq_ick", + .addr = omap2_hdq1w_addr_space, + .user = OCP_USER_MPU | OCP_USER_SDMA, + .flags = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE, +}; + static struct omap_hwmod_ocp_if *omap2430_hwmod_ocp_ifs[] __initdata = { &omap2xxx_l3_main__l4_core, &omap2xxx_mpu__l3_main, @@ -886,6 +913,7 @@ static struct omap_hwmod_ocp_if *omap2430_hwmod_ocp_ifs[] __initdata = { &omap2430_l4_core__mcbsp3, &omap2430_l4_core__mcbsp4, &omap2430_l4_core__mcbsp5, + &omap2430_l4_core__hdq1w, NULL, }; -- cgit v0.10.2 From 1c2badc1617661632034d8be5d22c8637b626cb7 Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Tue, 8 May 2012 11:34:28 -0600 Subject: ARM: OMAP3: hwmod_data: Rename the common irq for McBSP ports Use 'common' as name for the common irq number in hwmod data for the McBSP ports. The same name already in use for OMAP2430, and the OMAP4 hwmod data will be using the same name. Signed-off-by: Peter Ujfalusi Signed-off-by: Paul Walmsley diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c index 97c6597..87742e2 100644 --- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c @@ -1075,7 +1075,7 @@ static struct omap_hwmod_class omap3xxx_mcbsp_hwmod_class = { /* mcbsp1 */ static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = { - { .name = "irq", .irq = 16 }, + { .name = "common", .irq = 16 }, { .name = "tx", .irq = 59 }, { .name = "rx", .irq = 60 }, { .irq = -1 } @@ -1100,7 +1100,7 @@ static struct omap_hwmod omap3xxx_mcbsp1_hwmod = { /* mcbsp2 */ static struct omap_hwmod_irq_info omap3xxx_mcbsp2_irqs[] = { - { .name = "irq", .irq = 17 }, + { .name = "common", .irq = 17 }, { .name = "tx", .irq = 62 }, { .name = "rx", .irq = 63 }, { .irq = -1 } @@ -1130,7 +1130,7 @@ static struct omap_hwmod omap3xxx_mcbsp2_hwmod = { /* mcbsp3 */ static struct omap_hwmod_irq_info omap3xxx_mcbsp3_irqs[] = { - { .name = "irq", .irq = 22 }, + { .name = "common", .irq = 22 }, { .name = "tx", .irq = 89 }, { .name = "rx", .irq = 90 }, { .irq = -1 } @@ -1160,7 +1160,7 @@ static struct omap_hwmod omap3xxx_mcbsp3_hwmod = { /* mcbsp4 */ static struct omap_hwmod_irq_info omap3xxx_mcbsp4_irqs[] = { - { .name = "irq", .irq = 23 }, + { .name = "common", .irq = 23 }, { .name = "tx", .irq = 54 }, { .name = "rx", .irq = 55 }, { .irq = -1 } @@ -1191,7 +1191,7 @@ static struct omap_hwmod omap3xxx_mcbsp4_hwmod = { /* mcbsp5 */ static struct omap_hwmod_irq_info omap3xxx_mcbsp5_irqs[] = { - { .name = "irq", .irq = 27 }, + { .name = "common", .irq = 27 }, { .name = "tx", .irq = 81 }, { .name = "rx", .irq = 82 }, { .irq = -1 } -- cgit v0.10.2 From aa8f6cefa1e0ba79deaf76c5a790ad167659c311 Mon Sep 17 00:00:00 2001 From: Shubhrajyoti D Date: Tue, 8 May 2012 11:34:29 -0600 Subject: ARM: OMAP4: hwmod data: I2C: add flag for context restore Restore of context is not done for OMAP4. This patch adds the OMAP_I2C_FLAG_RESET_REGS_POSTIDLE in the OMAP4 hwmod data which activates the restore for OMAP4. Currently the OMAP4 does not hit device off still the driver may have support for it. Cc: Benoit Cousson Cc: Paul Wamsley Reviewed-by: Kevin Hilman Signed-off-by: Shubhrajyoti D Signed-off-by: Paul Walmsley diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c index 4906129..3a67ed0 100644 --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c @@ -1487,7 +1487,8 @@ static struct omap_hwmod_class omap44xx_i2c_hwmod_class = { }; static struct omap_i2c_dev_attr i2c_dev_attr = { - .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE, + .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE | + OMAP_I2C_FLAG_RESET_REGS_POSTIDLE, }; /* i2c1 */ -- cgit v0.10.2 From 437e897083d9e42195c13a96a5bc4d8871649a19 Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Tue, 8 May 2012 11:34:29 -0600 Subject: ARM: OMAP4: hwmod_data: Name the common irq for McBSP ports Use 'common' as name for the common irq number in hwmod data for the McBSP ports. The same name already in use for OMAP2430, and OMAP3. Signed-off-by: Peter Ujfalusi Signed-off-by: Paul Walmsley diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c index 3a67ed0..c997c97 100644 --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c @@ -1912,7 +1912,7 @@ static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = { /* mcbsp1 */ static struct omap_hwmod_irq_info omap44xx_mcbsp1_irqs[] = { - { .irq = 17 + OMAP44XX_IRQ_GIC_START }, + { .name = "common", .irq = 17 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } }; @@ -1947,7 +1947,7 @@ static struct omap_hwmod omap44xx_mcbsp1_hwmod = { /* mcbsp2 */ static struct omap_hwmod_irq_info omap44xx_mcbsp2_irqs[] = { - { .irq = 22 + OMAP44XX_IRQ_GIC_START }, + { .name = "common", .irq = 22 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } }; @@ -1982,7 +1982,7 @@ static struct omap_hwmod omap44xx_mcbsp2_hwmod = { /* mcbsp3 */ static struct omap_hwmod_irq_info omap44xx_mcbsp3_irqs[] = { - { .irq = 23 + OMAP44XX_IRQ_GIC_START }, + { .name = "common", .irq = 23 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } }; @@ -2017,7 +2017,7 @@ static struct omap_hwmod omap44xx_mcbsp3_hwmod = { /* mcbsp4 */ static struct omap_hwmod_irq_info omap44xx_mcbsp4_irqs[] = { - { .irq = 16 + OMAP44XX_IRQ_GIC_START }, + { .name = "common", .irq = 16 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } }; -- cgit v0.10.2 From c8d82ff68fb6873691536cf33021977efbf5593c Mon Sep 17 00:00:00 2001 From: Vaibhav Hiremath Date: Tue, 8 May 2012 11:34:30 -0600 Subject: ARM: OMAP2/3: hwmod data: Add 32k-sync timer data to hwmod database Add 32k-sync timer hwmod-data and add ocp_if details to omap2 & 3 hwmod table. Signed-off-by: Vaibhav Hiremath Signed-off-by: Felipe Balbi Reviewed-by: Santosh Shilimkar Cc: Benoit Cousson Cc: Tony Lindgren Cc: Paul Walmsley Cc: Kevin Hilman Signed-off-by: Paul Walmsley diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c index 85419f8..a7640d1 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c @@ -519,6 +519,24 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__hdq1w = { }; +/* l4_wkup -> 32ksync_counter */ +static struct omap_hwmod_addr_space omap2420_counter_32k_addrs[] = { + { + .pa_start = 0x48004000, + .pa_end = 0x4800401f, + .flags = ADDR_TYPE_RT + }, + { } +}; + +static struct omap_hwmod_ocp_if omap2420_l4_wkup__counter_32k = { + .master = &omap2xxx_l4_wkup_hwmod, + .slave = &omap2xxx_counter_32k_hwmod, + .clk = "sync_32k_ick", + .addr = omap2420_counter_32k_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + static struct omap_hwmod_ocp_if *omap2420_hwmod_ocp_ifs[] __initdata = { &omap2xxx_l3_main__l4_core, &omap2xxx_mpu__l3_main, @@ -561,6 +579,7 @@ static struct omap_hwmod_ocp_if *omap2420_hwmod_ocp_ifs[] __initdata = { &omap2420_l4_core__mcbsp2, &omap2420_l4_core__msdi1, &omap2420_l4_core__hdq1w, + &omap2420_l4_wkup__counter_32k, NULL, }; diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c index ff93a8d..4d72649 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c @@ -865,6 +865,24 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__hdq1w = { .flags = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE, }; +/* l4_wkup -> 32ksync_counter */ +static struct omap_hwmod_addr_space omap2430_counter_32k_addrs[] = { + { + .pa_start = 0x49020000, + .pa_end = 0x4902001f, + .flags = ADDR_TYPE_RT + }, + { } +}; + +static struct omap_hwmod_ocp_if omap2430_l4_wkup__counter_32k = { + .master = &omap2xxx_l4_wkup_hwmod, + .slave = &omap2xxx_counter_32k_hwmod, + .clk = "sync_32k_ick", + .addr = omap2430_counter_32k_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + static struct omap_hwmod_ocp_if *omap2430_hwmod_ocp_ifs[] __initdata = { &omap2xxx_l3_main__l4_core, &omap2xxx_mpu__l3_main, @@ -914,6 +932,7 @@ static struct omap_hwmod_ocp_if *omap2430_hwmod_ocp_ifs[] __initdata = { &omap2430_l4_core__mcbsp4, &omap2430_l4_core__mcbsp5, &omap2430_l4_core__hdq1w, + &omap2430_l4_wkup__counter_32k, NULL, }; diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c index 45aaa07..5941f14 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c @@ -732,3 +732,23 @@ struct omap_hwmod omap2xxx_mcspi2_hwmod = { .class = &omap2xxx_mcspi_class, .dev_attr = &omap_mcspi2_dev_attr, }; + + +static struct omap_hwmod_class omap2xxx_counter_hwmod_class = { + .name = "counter", +}; + +struct omap_hwmod omap2xxx_counter_32k_hwmod = { + .name = "counter_32k", + .main_clk = "func_32k_ck", + .prcm = { + .omap2 = { + .module_offs = WKUP_MOD, + .prcm_reg_id = 1, + .module_bit = OMAP24XX_ST_32KSYNC_SHIFT, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_32KSYNC_SHIFT, + }, + }, + .class = &omap2xxx_counter_hwmod_class, +}; diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c index 87742e2..2432574 100644 --- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c @@ -1997,6 +1997,40 @@ static struct omap_hwmod omap3xxx_hdq1w_hwmod = { }; /* + * '32K sync counter' class + * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock + */ +static struct omap_hwmod_class_sysconfig omap3xxx_counter_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0004, + .sysc_flags = SYSC_HAS_SIDLEMODE, + .idlemodes = (SIDLE_FORCE | SIDLE_NO), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap3xxx_counter_hwmod_class = { + .name = "counter", + .sysc = &omap3xxx_counter_sysc, +}; + +static struct omap_hwmod omap3xxx_counter_32k_hwmod = { + .name = "counter_32k", + .class = &omap3xxx_counter_hwmod_class, + .clkdm_name = "wkup_clkdm", + .flags = HWMOD_SWSUP_SIDLE, + .main_clk = "wkup_32k_fck", + .prcm = { + .omap2 = { + .module_offs = WKUP_MOD, + .prcm_reg_id = 1, + .module_bit = OMAP3430_ST_32KSYNC_SHIFT, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_ST_32KSYNC_SHIFT, + }, + }, +}; + +/* * interfaces */ @@ -3085,6 +3119,24 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__hdq1w = { .flags = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE, }; +/* l4_wkup -> 32ksync_counter */ +static struct omap_hwmod_addr_space omap3xxx_counter_32k_addrs[] = { + { + .pa_start = 0x48320000, + .pa_end = 0x4832001f, + .flags = ADDR_TYPE_RT + }, + { } +}; + +static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__counter_32k = { + .master = &omap3xxx_l4_wkup_hwmod, + .slave = &omap3xxx_counter_32k_hwmod, + .clk = "omap_32ksync_ick", + .addr = omap3xxx_counter_32k_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = { &omap3xxx_l3_main__l4_core, &omap3xxx_l3_main__l4_per, @@ -3129,6 +3181,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = { &omap34xx_l4_core__mcspi2, &omap34xx_l4_core__mcspi3, &omap34xx_l4_core__mcspi4, + &omap3xxx_l4_wkup__counter_32k, NULL, }; diff --git a/arch/arm/mach-omap2/omap_hwmod_common_data.h b/arch/arm/mach-omap2/omap_hwmod_common_data.h index e244829..e7e8eea 100644 --- a/arch/arm/mach-omap2/omap_hwmod_common_data.h +++ b/arch/arm/mach-omap2/omap_hwmod_common_data.h @@ -75,6 +75,7 @@ extern struct omap_hwmod omap2xxx_gpio3_hwmod; extern struct omap_hwmod omap2xxx_gpio4_hwmod; extern struct omap_hwmod omap2xxx_mcspi1_hwmod; extern struct omap_hwmod omap2xxx_mcspi2_hwmod; +extern struct omap_hwmod omap2xxx_counter_32k_hwmod; /* Common interface data across OMAP2xxx */ extern struct omap_hwmod_ocp_if omap2xxx_l3_main__l4_core; -- cgit v0.10.2 From 414e41286e3aeb87de140ef4c75100f9344c32b2 Mon Sep 17 00:00:00 2001 From: Kevin Hilman Date: Tue, 8 May 2012 11:34:30 -0600 Subject: ARM: OMAP2+: WDTIMER integration: fix !PM boot crash, disarm timer after hwmod reset Without runtime PM enabled, hwmod needs to leave all IP blocks in an enabled state by default so any driver access to the HW will succeed. This is accomplished by seting the postsetup_state to enabled for all hwmods during init when runtime PM is disabled. Currently, we have a special case for WDT in that its postsetup_state is always set to disabled. This is done so that the WDT is disabled and the timer is disarmed at boot in case there is no WDT driver. This also means that when runtime PM is disabled, if a WDT driver *is* built in the kernel, the kernel will crash on the first access to the WDT hardware. We can't simply leave the WDT module enabled, because the timer is armed by default after reset. That means that if there is no WDT driver initialzed or loaded before the timer expires, the kernel will reboot. To fix this, a custom reset method is added to the watchdog class of omap_hwmod. This method will *always* disarm the timer after hwmod reset. The WDT timer then will only be rearmed when/if the driver is loaded for the WDT. With the timer disarmed by default, we no longer need a special-case for the postsetup_state of WDT during init, so it is removed. Any platforms wishing to ensure the watchdog remains armed across the entire boot boot can simply disable the reset-on-init feature of the watchdog hwmod using omap_hwmod_no_setup_reset(). Tested on 3530/Overo, 4430/Panda. NOTE: on 4430, the hwmod OCP reset does not seem to rearm the timer as documented in the TRM (and what happens on OMAP3.) I noticed this because testing the HWMOD_INIT_NO_RESET feature with no driver loaded, I expected a reboot part way through the boot, but did not see a reboot. Adding some debug to read the counter, I verified that right after OCP softreset, the counter is not firing. After writing the magic start sequence, the timer starts counting. This means that the timer disarm sequence added here does not seem to be needed for 4430, but is technically the correct way to ensure the timer is disarmed, so it is left in for OMAP4. Special thanks to Paul Walmsley for helping brainstorm ideas to fix this problem. Cc: Paul Walmsley Signed-off-by: Kevin Hilman Cc: Santosh Shilimkar Acked-by: Santosh Shilimkar [paul@pwsan.com: updated the omap2_wd_timer_reset() function in the wake of commit 3c55c1baffa5f719eb2ae9729088bc867f972f53 ("ARM: OMAP2+: hwmod: Revert "ARM: OMAP2+: hwmod: Make omap_hwmod_softreset wait for reset status""); added kerneldoc; rolled in warning fix from Kevin] Signed-off-by: Paul Walmsley diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c index 065bd76..fafcc35 100644 --- a/arch/arm/mach-omap2/io.c +++ b/arch/arm/mach-omap2/io.c @@ -363,24 +363,6 @@ static void __init omap_hwmod_init_postsetup(void) #endif omap_hwmod_for_each(_set_hwmod_postsetup_state, &postsetup_state); - /* - * Set the default postsetup state for unusual modules (like - * MPU WDT). - * - * The postsetup_state is not actually used until - * omap_hwmod_late_init(), so boards that desire full watchdog - * coverage of kernel initialization can reprogram the - * postsetup_state between the calls to - * omap2_init_common_infra() and omap_sdrc_init(). - * - * XXX ideally we could detect whether the MPU WDT was currently - * enabled here and make this conditional - */ - postsetup_state = _HWMOD_STATE_DISABLED; - omap_hwmod_for_each_by_class("wd_timer", - _set_hwmod_postsetup_state, - &postsetup_state); - omap_pm_if_early_init(); } diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c index 5941f14..83eafd9 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c @@ -89,7 +89,8 @@ static struct omap_hwmod_class_sysconfig omap2xxx_wd_timer_sysc = { struct omap_hwmod_class omap2xxx_wd_timer_hwmod_class = { .name = "wd_timer", .sysc = &omap2xxx_wd_timer_sysc, - .pre_shutdown = &omap2_wd_timer_disable + .pre_shutdown = &omap2_wd_timer_disable, + .reset = &omap2_wd_timer_reset, }; /* diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c index 2432574..fd48797 100644 --- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c @@ -418,7 +418,8 @@ static struct omap_hwmod_class_sysconfig i2c_sysc = { static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = { .name = "wd_timer", .sysc = &omap3xxx_wd_timer_sysc, - .pre_shutdown = &omap2_wd_timer_disable + .pre_shutdown = &omap2_wd_timer_disable, + .reset = &omap2_wd_timer_reset, }; static struct omap_hwmod omap3xxx_wd_timer2_hwmod = { diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c index c997c97..950454a 100644 --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c @@ -3535,6 +3535,7 @@ static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = { .name = "wd_timer", .sysc = &omap44xx_wd_timer_sysc, .pre_shutdown = &omap2_wd_timer_disable, + .reset = &omap2_wd_timer_reset, }; /* wd_timer2 */ diff --git a/arch/arm/mach-omap2/wd_timer.c b/arch/arm/mach-omap2/wd_timer.c index 4067669..b2f1c67 100644 --- a/arch/arm/mach-omap2/wd_timer.c +++ b/arch/arm/mach-omap2/wd_timer.c @@ -14,6 +14,7 @@ #include #include "wd_timer.h" +#include "common.h" /* * In order to avoid any assumptions from bootloader regarding WDT @@ -25,6 +26,8 @@ #define OMAP_WDT_WPS 0x34 #define OMAP_WDT_SPR 0x48 +/* Maximum microseconds to wait for OMAP module to softreset */ +#define MAX_MODULE_SOFTRESET_WAIT 10000 int omap2_wd_timer_disable(struct omap_hwmod *oh) { @@ -54,3 +57,45 @@ int omap2_wd_timer_disable(struct omap_hwmod *oh) return 0; } +/** + * omap2_wdtimer_reset - reset and disable the WDTIMER IP block + * @oh: struct omap_hwmod * + * + * After the WDTIMER IP blocks are reset on OMAP2/3, we must also take + * care to execute the special watchdog disable sequence. This is + * because the watchdog is re-armed upon OCP softreset. (On OMAP4, + * this behavior was apparently changed and the watchdog is no longer + * re-armed after an OCP soft-reset.) Returns -ETIMEDOUT if the reset + * did not complete, or 0 upon success. + * + * XXX Most of this code should be moved to the omap_hwmod.c layer + * during a normal merge window. omap_hwmod_softreset() should be + * renamed to omap_hwmod_set_ocp_softreset(), and omap_hwmod_softreset() + * should call the hwmod _ocp_softreset() code. + */ +int omap2_wd_timer_reset(struct omap_hwmod *oh) +{ + int c = 0; + + /* Write to the SOFTRESET bit */ + omap_hwmod_softreset(oh); + + /* Poll on RESETDONE bit */ + omap_test_timeout((omap_hwmod_read(oh, + oh->class->sysc->syss_offs) + & SYSS_RESETDONE_MASK), + MAX_MODULE_SOFTRESET_WAIT, c); + + if (oh->class->sysc->srst_udelay) + udelay(oh->class->sysc->srst_udelay); + + if (c == MAX_MODULE_SOFTRESET_WAIT) + pr_warning("%s: %s: softreset failed (waited %d usec)\n", + __func__, oh->name, MAX_MODULE_SOFTRESET_WAIT); + else + pr_debug("%s: %s: softreset in %d usec\n", __func__, + oh->name, c); + + return (c == MAX_MODULE_SOFTRESET_WAIT) ? -ETIMEDOUT : + omap2_wd_timer_disable(oh); +} diff --git a/arch/arm/mach-omap2/wd_timer.h b/arch/arm/mach-omap2/wd_timer.h index e0054a2..f6bbba7 100644 --- a/arch/arm/mach-omap2/wd_timer.h +++ b/arch/arm/mach-omap2/wd_timer.h @@ -13,5 +13,6 @@ #include extern int omap2_wd_timer_disable(struct omap_hwmod *oh); +extern int omap2_wd_timer_reset(struct omap_hwmod *oh); #endif -- cgit v0.10.2