From 4bd6b24a70f83522f78353e8be0ada8b229a523b Mon Sep 17 00:00:00 2001 From: Bogdan Purcareata Date: Wed, 3 May 2017 14:26:35 +0000 Subject: arm64: dts: fsl/ls1088,ls208x: Add mdio and phy nodes Add mdio and phy nodes for the following FSL platforms: - LS1088A RDB - LS2080A QDS & RDB - LS2088A QDS, RDB & simu Contains contributions from patches by the following authors: Signed-off-by: Shaohui Xie Signed-off-by: Rai Harninder Signed-off-by: Pratiyush Mohan Srivastava Signed-off-by: Raghav Dogra Signed-off-by: Santan Kumar Signed-off-by: Priyanka Jain Signed-off-by: Ashish Kumar Signed-off-by: Abhimanyu Saini Signed-off-by: Ioana Radulescu Signed-off-by: Bogdan Purcareata diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts index bca654c..6486751 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts @@ -126,3 +126,82 @@ &sata { status = "okay"; }; + +&emdio1 { + /* Freescale F104 PHY1 */ + mdio1_phy1: emdio1_phy@1 { + reg = <0x1c>; + phy-connection-type = "qsgmii"; + }; + mdio1_phy2: emdio1_phy@2 { + reg = <0x1d>; + phy-connection-type = "qsgmii"; + }; + mdio1_phy3: emdio1_phy@3 { + reg = <0x1e>; + phy-connection-type = "qsgmii"; + }; + mdio1_phy4: emdio1_phy@4 { + reg = <0x1f>; + phy-connection-type = "qsgmii"; + }; + /* F104 PHY2 */ + mdio1_phy5: emdio1_phy@5 { + reg = <0x0c>; + phy-connection-type = "qsgmii"; + }; + mdio1_phy6: emdio1_phy@6 { + reg = <0x0d>; + phy-connection-type = "qsgmii"; + }; + mdio1_phy7: emdio1_phy@7 { + reg = <0x0e>; + phy-connection-type = "qsgmii"; + }; + mdio1_phy8: emdio1_phy@8 { + reg = <0x0f>; + phy-connection-type = "qsgmii"; + }; +}; + +&emdio2 { + /* Aquantia AQR105 10G PHY */ + mdio2_phy1: emdio2_phy@1 { + compatible = "ethernet-phy-ieee802.3-c45"; + interrupts = <0 2 0x4>; + reg = <0x0>; + phy-connection-type = "xfi"; + }; +}; + +/* DPMAC connections to external PHYs + * based on LS1088A RM RevC - $24.1.2 SerDes Options + */ +/* DPMAC1 is 10G SFP+, fixed link */ +&dpmac2 { + phy-handle = <&mdio2_phy1>; +}; +&dpmac3 { + phy-handle = <&mdio1_phy5>; +}; +&dpmac4 { + phy-handle = <&mdio1_phy6>; +}; +&dpmac5 { + phy-handle = <&mdio1_phy7>; +}; +&dpmac6 { + phy-handle = <&mdio1_phy8>; +}; +&dpmac7 { + phy-handle = <&mdio1_phy1>; +}; +&dpmac8 { + phy-handle = <&mdio1_phy2>; +}; +&dpmac9 { + phy-handle = <&mdio1_phy3>; +}; +&dpmac10 { + phy-handle = <&mdio1_phy4>; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi index e7539c2..bf4c9f8 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi @@ -424,6 +424,32 @@ #interrupt-cells = <2>; }; + /* TODO: WRIOP (CCSR?) */ + emdio1: mdio@0x8B96000 { /* WRIOP0: 0x8B8_0000, + * E-MDIO1: 0x1_6000 + */ + compatible = "fsl,fman-memac-mdio"; + reg = <0x0 0x8B96000 0x0 0x1000>; + device_type = "mdio"; + little-endian; /* force the driver in LE mode */ + + /* Not necessary on the QDS, but needed on the RDB */ + #address-cells = <1>; + #size-cells = <0>; + }; + + emdio2: mdio@0x8B97000 { /* WRIOP0: 0x8B8_0000, + * E-MDIO2: 0x1_7000 + */ + compatible = "fsl,fman-memac-mdio"; + reg = <0x0 0x8B97000 0x0 0x1000>; + device_type = "mdio"; + little-endian; /* force the driver in LE mode */ + + #address-cells = <1>; + #size-cells = <0>; + }; + ifc: ifc@2240000 { compatible = "fsl,ifc", "simple-bus"; reg = <0x0 0x2240000 0x0 0x20000>; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts index ed209cd..9290e14 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts @@ -64,3 +64,65 @@ stdout-path = "serial0:115200n8"; }; }; + +&ifc { + boardctrl: board-control@3,0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,tetra-fpga", "fsl,fpga-qixis", "simple-bus"; + reg = <3 0 0x300>; /* TODO check address */ + ranges = <0 3 0 0x300>; + + mdio_mux_emi1 { + compatible = "mdio-mux-mmioreg", "mdio-mux"; + mdio-parent-bus = <&emdio1>; + reg = <0x54 1>; /* BRDCFG4 */ + mux-mask = <0xe0>; /* EMI1_MDIO */ + + #address-cells=<1>; + #size-cells = <0>; + + /* Child MDIO buses, one for each riser card: + * reg = 0x0, 0x20, 0x40, 0x60, 0x80, 0xa0. + * VSC8234 PHYs on the riser cards. + */ + + mdio_mux3: mdio@60 { + reg = <0x60>; + #address-cells = <1>; + #size-cells = <0>; + + mdio0_phy12: mdio_phy0@1c { + reg = <0x1c>; + phy-connection-type = "sgmii"; + }; + mdio0_phy13: mdio_phy1@1d { + reg = <0x1d>; + phy-connection-type = "sgmii"; + }; + mdio0_phy14: mdio_phy2@1e { + reg = <0x1e>; + phy-connection-type = "sgmii"; + }; + mdio0_phy15: mdio_phy3@1f { + reg = <0x1f>; + phy-connection-type = "sgmii"; + }; + }; + }; + }; +}; + +/* Update DPMAC connections to external PHYs, under SerDes 0x2a_0x49. */ +&dpmac9 { + phy-handle = <&mdio0_phy12>; +}; +&dpmac10 { + phy-handle = <&mdio0_phy13>; +}; +&dpmac11 { + phy-handle = <&mdio0_phy14>; +}; +&dpmac12 { + phy-handle = <&mdio0_phy15>; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts index 67ec3f9..502beb1 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts @@ -64,3 +64,83 @@ stdout-path = "serial1:115200n8"; }; }; + +&emdio1 { + status = "disabled"; + /* CS4340 PHYs */ + mdio1_phy1: emdio1_phy@1 { + reg = <0x10>; + phy-connection-type = "xfi"; + }; + mdio1_phy2: emdio1_phy@2 { + reg = <0x11>; + phy-connection-type = "xfi"; + }; + mdio1_phy3: emdio1_phy@3 { + reg = <0x12>; + phy-connection-type = "xfi"; + }; + mdio1_phy4: emdio1_phy@4 { + reg = <0x13>; + phy-connection-type = "xfi"; + }; +}; + +&emdio2 { + /* AQR405 PHYs */ + mdio2_phy1: emdio2_phy@1 { + compatible = "ethernet-phy-ieee802.3-c45"; + interrupts = <0 1 0x4>; /* Level high type */ + reg = <0x0>; + phy-connection-type = "xfi"; + }; + mdio2_phy2: emdio2_phy@2 { + compatible = "ethernet-phy-ieee802.3-c45"; + interrupts = <0 2 0x4>; /* Level high type */ + reg = <0x1>; + phy-connection-type = "xfi"; + }; + mdio2_phy3: emdio2_phy@3 { + compatible = "ethernet-phy-ieee802.3-c45"; + interrupts = <0 4 0x4>; /* Level high type */ + reg = <0x2>; + phy-connection-type = "xfi"; + }; + mdio2_phy4: emdio2_phy@4 { + compatible = "ethernet-phy-ieee802.3-c45"; + interrupts = <0 5 0x4>; /* Level high type */ + reg = <0x3>; + phy-connection-type = "xfi"; + }; +}; + +/* Update DPMAC connections to external PHYs, under the assumption of + * SerDes 0x2a_0x41. This is currently the only SerDes supported on the board. + */ +/* Leave Cortina nodes commented out until driver is integrated + *&dpmac1 { + * phy-handle = <&mdio1_phy1>; + *}; + *&dpmac2 { + * phy-handle = <&mdio1_phy2>; + *}; + *&dpmac3 { + * phy-handle = <&mdio1_phy3>; + *}; + *&dpmac4 { + * phy-handle = <&mdio1_phy4>; + *}; + */ + +&dpmac5 { + phy-handle = <&mdio2_phy1>; +}; +&dpmac6 { + phy-handle = <&mdio2_phy2>; +}; +&dpmac7 { + phy-handle = <&mdio2_phy3>; +}; +&dpmac8 { + phy-handle = <&mdio2_phy4>; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dts index 0cd6599..6b42eef 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dts @@ -64,6 +64,54 @@ }; }; +&ifc { + boardctrl: board-control@3,0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,tetra-fpga", "fsl,fpga-qixis", "simple-bus"; + reg = <3 0 0x300>; /* TODO check address */ + ranges = <0 3 0 0x300>; + + mdio_mux_emi1 { + compatible = "mdio-mux-mmioreg", "mdio-mux"; + mdio-parent-bus = <&emdio1>; + reg = <0x54 1>; /* BRDCFG4 */ + mux-mask = <0xe0>; /* EMI1_MDIO */ + + #address-cells=<1>; + #size-cells = <0>; + + /* Child MDIO buses, one for each riser card: + * reg = 0x0, 0x20, 0x40, 0x60, 0x80, 0xa0. + * VSC8234 PHYs on the riser cards. + */ + + mdio_mux3: mdio@60 { + reg = <0x60>; + #address-cells = <1>; + #size-cells = <0>; + + mdio0_phy12: mdio_phy0@1c { + reg = <0x1c>; + phy-connection-type = "sgmii"; + }; + mdio0_phy13: mdio_phy1@1d { + reg = <0x1d>; + phy-connection-type = "sgmii"; + }; + mdio0_phy14: mdio_phy2@1e { + reg = <0x1e>; + phy-connection-type = "sgmii"; + }; + mdio0_phy15: mdio_phy3@1f { + reg = <0x1f>; + phy-connection-type = "sgmii"; + }; + }; + }; + }; +}; + &pcs_mdio1 { pcs_phy1: ethernet-phy@0 { backplane-mode = "10gbase-kr"; @@ -103,3 +151,17 @@ fsl,lane-reg = <0x900 0x40>;/* lane E */ }; }; + +/* Update DPMAC connections to external PHYs, under SerDes 0x2a_0x49. */ +&dpmac9 { + phy-handle = <&mdio0_phy12>; +}; +&dpmac10 { + phy-handle = <&mdio0_phy13>; +}; +&dpmac11 { + phy-handle = <&mdio0_phy14>; +}; +&dpmac12 { + phy-handle = <&mdio0_phy15>; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts index a76d4b4..de1360f 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts @@ -63,3 +63,83 @@ stdout-path = "serial1:115200n8"; }; }; + +&emdio1 { + status = "disabled"; + /* CS4340 PHYs */ + mdio1_phy1: emdio1_phy@1 { + reg = <0x10>; + phy-connection-type = "xfi"; + }; + mdio1_phy2: emdio1_phy@2 { + reg = <0x11>; + phy-connection-type = "xfi"; + }; + mdio1_phy3: emdio1_phy@3 { + reg = <0x12>; + phy-connection-type = "xfi"; + }; + mdio1_phy4: emdio1_phy@4 { + reg = <0x13>; + phy-connection-type = "xfi"; + }; +}; + +&emdio2 { + /* AQR405 PHYs */ + mdio2_phy1: emdio2_phy@1 { + compatible = "ethernet-phy-ieee802.3-c45"; + interrupts = <0 1 0x4>; /* Level high type */ + reg = <0x0>; + phy-connection-type = "xfi"; + }; + mdio2_phy2: emdio2_phy@2 { + compatible = "ethernet-phy-ieee802.3-c45"; + interrupts = <0 2 0x4>; /* Level high type */ + reg = <0x1>; + phy-connection-type = "xfi"; + }; + mdio2_phy3: emdio2_phy@3 { + compatible = "ethernet-phy-ieee802.3-c45"; + interrupts = <0 4 0x4>; /* Level high type */ + reg = <0x2>; + phy-connection-type = "xfi"; + }; + mdio2_phy4: emdio2_phy@4 { + compatible = "ethernet-phy-ieee802.3-c45"; + interrupts = <0 5 0x4>; /* Level high type */ + reg = <0x3>; + phy-connection-type = "xfi"; + }; +}; + +/* Update DPMAC connections to external PHYs, under the assumption of + * SerDes 0x2a_0x41. This is currently the only SerDes supported on the board. + */ +/* Leave Cortina PHYs commented out until proper driver is integrated + *&dpmac1 { + * phy-handle = <&mdio1_phy1>; + *}; + *&dpmac2 { + * phy-handle = <&mdio1_phy2>; + *}; + *&dpmac3 { + * phy-handle = <&mdio1_phy3>; + *}; + *&dpmac4 { + * phy-handle = <&mdio1_phy4>; + *}; + */ + +&dpmac5 { + phy-handle = <&mdio2_phy1>; +}; +&dpmac6 { + phy-handle = <&mdio2_phy2>; +}; +&dpmac7 { + phy-handle = <&mdio2_phy3>; +}; +&dpmac8 { + phy-handle = <&mdio2_phy4>; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi index cc6dab9..da5fdfc 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi @@ -525,6 +525,32 @@ #interrupt-cells = <2>; }; + /* TODO: WRIOP (CCSR?) */ + emdio1: mdio@0x8B96000 { /* WRIOP0: 0x8B8_0000, + * E-MDIO1: 0x1_6000 + */ + compatible = "fsl,fman-memac-mdio"; + reg = <0x0 0x8B96000 0x0 0x1000>; + device_type = "mdio"; /* TODO: is this necessary? */ + little-endian; /* force the driver in LE mode */ + + /* Not necessary on the QDS, but needed on the RDB */ + #address-cells = <1>; + #size-cells = <0>; + }; + + emdio2: mdio@0x8B97000 { /* WRIOP0: 0x8B8_0000, + * E-MDIO2: 0x1_7000 + */ + compatible = "fsl,fman-memac-mdio"; + reg = <0x0 0x8B97000 0x0 0x1000>; + device_type = "mdio"; /* TODO: is this necessary? */ + little-endian; /* force the driver in LE mode */ + + #address-cells = <1>; + #size-cells = <0>; + }; + pcs_mdio1: mdio@0x8c07000 { compatible = "fsl,fman-memac-mdio"; reg = <0x0 0x8c07000 0x0 0x1000>; -- cgit v0.10.2