From 3cac478cce564c11f56f30bd16530c2757b3e4f3 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 4 May 2016 10:57:58 +0200 Subject: arm64: dts: salvator-x: SCIF1 supports RTS/CTS hardware flow control On the Salvator-X development board, the RTS and CTS pins of debug serial-1 port SCIF1 are wired to the CP2102 Serial-USB bridge. Reflect this in the DTS by adding the "uart-has-rtscts" property to the scif1 device node. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman diff --git a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts index 9f561c9..76bc94a 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts +++ b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts @@ -208,6 +208,7 @@ pinctrl-0 = <&scif1_pins>; pinctrl-names = "default"; + uart-has-rtscts; status = "okay"; }; -- cgit v0.10.2 From 457f47b7651ccb1828c1d02f7ace0d07e9b16f33 Mon Sep 17 00:00:00 2001 From: Pooya Keshavarzi Date: Tue, 19 Apr 2016 08:29:55 +0200 Subject: arm64: dts: r8a7795: Increase the size of GIC-400 mapped registers There are some requirements about the GIC-400 memory layout and its mapping if using 64k aligned base addresses like on r8a7795. See e.g. http://xenbits.xen.org/gitweb/?p=xen.git;a=commit;h=21550029f709072aacf3b9 Map the whole memory range instead of only 0x2000. This will fix the issue that some hypervisors, e.g. Xen, fail to handle the interrupts correctly. Signed-off-by: Pooya Keshavarzi Signed-off-by: Dirk Behme Acked-by: Geert Uytterhoeven Signed-off-by: Simon Horman diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi index 3285a92..de3e799 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi @@ -157,9 +157,9 @@ #address-cells = <0>; interrupt-controller; reg = <0x0 0xf1010000 0 0x1000>, - <0x0 0xf1020000 0 0x2000>, + <0x0 0xf1020000 0 0x20000>, <0x0 0xf1040000 0 0x20000>, - <0x0 0xf1060000 0 0x2000>; + <0x0 0xf1060000 0 0x20000>; interrupts = ; }; -- cgit v0.10.2 From d78a1cfa61baaeaa1c8976326e47337640633ace Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Niklas=20S=C3=B6derlund?= Date: Tue, 17 May 2016 12:28:01 +0200 Subject: arm64: dts: r8a7795: enable DMA for I2C MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add DMA properties to the I2C nodes. Signed-off-by: Niklas Söderlund Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi index de3e799..f8c7e33 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi @@ -749,6 +749,8 @@ interrupts = ; clocks = <&cpg CPG_MOD 931>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + dmas = <&dmac1 0x91>, <&dmac1 0x90>; + dma-names = "tx", "rx"; i2c-scl-internal-delay-ns = <110>; status = "disabled"; }; @@ -761,6 +763,8 @@ interrupts = ; clocks = <&cpg CPG_MOD 930>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + dmas = <&dmac1 0x93>, <&dmac1 0x92>; + dma-names = "tx", "rx"; i2c-scl-internal-delay-ns = <6>; status = "disabled"; }; @@ -773,6 +777,8 @@ interrupts = ; clocks = <&cpg CPG_MOD 929>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + dmas = <&dmac1 0x95>, <&dmac1 0x94>; + dma-names = "tx", "rx"; i2c-scl-internal-delay-ns = <6>; status = "disabled"; }; @@ -785,6 +791,8 @@ interrupts = ; clocks = <&cpg CPG_MOD 928>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + dmas = <&dmac0 0x97>, <&dmac0 0x96>; + dma-names = "tx", "rx"; i2c-scl-internal-delay-ns = <110>; status = "disabled"; }; @@ -797,6 +805,8 @@ interrupts = ; clocks = <&cpg CPG_MOD 927>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + dmas = <&dmac0 0x99>, <&dmac0 0x98>; + dma-names = "tx", "rx"; i2c-scl-internal-delay-ns = <110>; status = "disabled"; }; @@ -809,6 +819,8 @@ interrupts = ; clocks = <&cpg CPG_MOD 919>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + dmas = <&dmac0 0x9b>, <&dmac0 0x9a>; + dma-names = "tx", "rx"; i2c-scl-internal-delay-ns = <110>; status = "disabled"; }; @@ -821,6 +833,8 @@ interrupts = ; clocks = <&cpg CPG_MOD 918>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + dmas = <&dmac0 0x9d>, <&dmac0 0x9c>; + dma-names = "tx", "rx"; i2c-scl-internal-delay-ns = <6>; status = "disabled"; }; -- cgit v0.10.2 From 3114815f635782102fdd7f47cb270d7f59b3d98f Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Fri, 1 Apr 2016 13:56:24 +0200 Subject: arm64: dts: r8a7795: Add RWDT node This patch adds the RWDT device node for r8a7795. Signed-off-by: Takeshi Kihara Signed-off-by: Wolfram Sang Reviewed-by: Geert Uytterhoeven Acked-by: Guenter Roeck Signed-off-by: Simon Horman diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi index f8c7e33..ba87e03 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi @@ -164,6 +164,14 @@ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; }; + wdt0: watchdog@e6020000 { + compatible = "renesas,r8a7795-wdt", "renesas,rcar-gen3-wdt"; + reg = <0 0xe6020000 0 0x0c>; + clocks = <&cpg CPG_MOD 402>; + power-domains = <&cpg>; + status = "disabled"; + }; + gpio0: gpio@e6050000 { compatible = "renesas,gpio-r8a7795", "renesas,gpio-rcar"; -- cgit v0.10.2 From 329260d5c4fdf9929b889e7badbb6d729edf123a Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Fri, 1 Apr 2016 13:56:25 +0200 Subject: arm64: dts: salvator-x: Enable watchdog timer This patch enables watchdog timer for Salvator-X board. Signed-off-by: Takeshi Kihara Signed-off-by: Wolfram Sang Acked-by: Geert Uytterhoeven Acked-by: Guenter Roeck Signed-off-by: Simon Horman diff --git a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts index 76bc94a..8408292 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts +++ b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts @@ -330,6 +330,11 @@ shared-pin; }; +&wdt0 { + timeout-sec = <60>; + status = "okay"; +}; + &audio_clk_a { clock-frequency = <22579200>; }; -- cgit v0.10.2 From b186fbb6cc5550756a29bc1d0bf259a7aa632c11 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 20 May 2016 09:43:02 +0200 Subject: arm64: dts: r8a7795: Use SYSC "always-on" PM Domain for RWDT node Hook up the RWDT device node to the SYSC "always-on" PM Domain, for a more consistent device-power-area description in DT. Cfr. commit 38dbb45ee4bc ("arm64: dts: r8a7795: Use SYSC "always-on" PM Domain") Fixes: f43838a7ae014cba ("arm64: dts: r8a7795: Add RWDT node") Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi index ba87e03..bf38df3 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi @@ -168,7 +168,7 @@ compatible = "renesas,r8a7795-wdt", "renesas,rcar-gen3-wdt"; reg = <0 0xe6020000 0 0x0c>; clocks = <&cpg CPG_MOD 402>; - power-domains = <&cpg>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; status = "disabled"; }; -- cgit v0.10.2 From 6f7bf82cc912441f5824f0b1a6497164e5ebe079 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 20 May 2016 09:10:13 +0200 Subject: arm64: dts: r8a7795: Fix W=1 dtc warnings Warning (unit_address_vs_reg): Node /cache-controller@0 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /cache-controller@1 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /soc/sound@ec500000/rcar_sound,dvc/dvc@0 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /soc/sound@ec500000/rcar_sound,dvc/dvc@1 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /soc/sound@ec500000/rcar_sound,src/src@0 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /soc/sound@ec500000/rcar_sound,src/src@1 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /soc/sound@ec500000/rcar_sound,src/src@2 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /soc/sound@ec500000/rcar_sound,src/src@3 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /soc/sound@ec500000/rcar_sound,src/src@4 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /soc/sound@ec500000/rcar_sound,src/src@5 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /soc/sound@ec500000/rcar_sound,src/src@6 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /soc/sound@ec500000/rcar_sound,src/src@7 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /soc/sound@ec500000/rcar_sound,src/src@8 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /soc/sound@ec500000/rcar_sound,src/src@9 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /soc/sound@ec500000/rcar_sound,ssi/ssi@0 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /soc/sound@ec500000/rcar_sound,ssi/ssi@1 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /soc/sound@ec500000/rcar_sound,ssi/ssi@2 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /soc/sound@ec500000/rcar_sound,ssi/ssi@3 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /soc/sound@ec500000/rcar_sound,ssi/ssi@4 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /soc/sound@ec500000/rcar_sound,ssi/ssi@5 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /soc/sound@ec500000/rcar_sound,ssi/ssi@6 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /soc/sound@ec500000/rcar_sound,ssi/ssi@7 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /soc/sound@ec500000/rcar_sound,ssi/ssi@8 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /soc/sound@ec500000/rcar_sound,ssi/ssi@9 has a unit name, but no reg property Move the cache-controller nodes under the cpus node, and make their unit names and reg properties match the MPIDR values. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi index bf38df3..a4f4ec8 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi @@ -69,20 +69,22 @@ next-level-cache = <&L2_CA57>; enable-method = "psci"; }; - }; - L2_CA57: cache-controller@0 { - compatible = "cache"; - power-domains = <&sysc R8A7795_PD_CA57_SCU>; - cache-unified; - cache-level = <2>; - }; + L2_CA57: cache-controller@0 { + compatible = "cache"; + reg = <0>; + power-domains = <&sysc R8A7795_PD_CA57_SCU>; + cache-unified; + cache-level = <2>; + }; - L2_CA53: cache-controller@1 { - compatible = "cache"; - power-domains = <&sysc R8A7795_PD_CA53_SCU>; - cache-unified; - cache-level = <2>; + L2_CA53: cache-controller@100 { + compatible = "cache"; + reg = <0x100>; + power-domains = <&sysc R8A7795_PD_CA53_SCU>; + cache-unified; + cache-level = <2>; + }; }; extal_clk: extal { @@ -896,63 +898,63 @@ status = "disabled"; rcar_sound,dvc { - dvc0: dvc@0 { + dvc0: dvc-0 { dmas = <&audma0 0xbc>; dma-names = "tx"; }; - dvc1: dvc@1 { + dvc1: dvc-1 { dmas = <&audma0 0xbe>; dma-names = "tx"; }; }; rcar_sound,src { - src0: src@0 { + src0: src-0 { interrupts = ; dmas = <&audma0 0x85>, <&audma1 0x9a>; dma-names = "rx", "tx"; }; - src1: src@1 { + src1: src-1 { interrupts = ; dmas = <&audma0 0x87>, <&audma1 0x9c>; dma-names = "rx", "tx"; }; - src2: src@2 { + src2: src-2 { interrupts = ; dmas = <&audma0 0x89>, <&audma1 0x9e>; dma-names = "rx", "tx"; }; - src3: src@3 { + src3: src-3 { interrupts = ; dmas = <&audma0 0x8b>, <&audma1 0xa0>; dma-names = "rx", "tx"; }; - src4: src@4 { + src4: src-4 { interrupts = ; dmas = <&audma0 0x8d>, <&audma1 0xb0>; dma-names = "rx", "tx"; }; - src5: src@5 { + src5: src-5 { interrupts = ; dmas = <&audma0 0x8f>, <&audma1 0xb2>; dma-names = "rx", "tx"; }; - src6: src@6 { + src6: src-6 { interrupts = ; dmas = <&audma0 0x91>, <&audma1 0xb4>; dma-names = "rx", "tx"; }; - src7: src@7 { + src7: src-7 { interrupts = ; dmas = <&audma0 0x93>, <&audma1 0xb6>; dma-names = "rx", "tx"; }; - src8: src@8 { + src8: src-8 { interrupts = ; dmas = <&audma0 0x95>, <&audma1 0xb8>; dma-names = "rx", "tx"; }; - src9: src@9 { + src9: src-9 { interrupts = ; dmas = <&audma0 0x97>, <&audma1 0xba>; dma-names = "rx", "tx"; @@ -960,52 +962,52 @@ }; rcar_sound,ssi { - ssi0: ssi@0 { + ssi0: ssi-0 { interrupts = ; dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>; dma-names = "rx", "tx", "rxu", "txu"; }; - ssi1: ssi@1 { + ssi1: ssi-1 { interrupts = ; dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>; dma-names = "rx", "tx", "rxu", "txu"; }; - ssi2: ssi@2 { + ssi2: ssi-2 { interrupts = ; dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>; dma-names = "rx", "tx", "rxu", "txu"; }; - ssi3: ssi@3 { + ssi3: ssi-3 { interrupts = ; dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>; dma-names = "rx", "tx", "rxu", "txu"; }; - ssi4: ssi@4 { + ssi4: ssi-4 { interrupts = ; dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>; dma-names = "rx", "tx", "rxu", "txu"; }; - ssi5: ssi@5 { + ssi5: ssi-5 { interrupts = ; dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>; dma-names = "rx", "tx", "rxu", "txu"; }; - ssi6: ssi@6 { + ssi6: ssi-6 { interrupts = ; dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>; dma-names = "rx", "tx", "rxu", "txu"; }; - ssi7: ssi@7 { + ssi7: ssi-7 { interrupts = ; dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>; dma-names = "rx", "tx", "rxu", "txu"; }; - ssi8: ssi@8 { + ssi8: ssi-8 { interrupts = ; dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>; dma-names = "rx", "tx", "rxu", "txu"; }; - ssi9: ssi@9 { + ssi9: ssi-9 { interrupts = ; dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>; dma-names = "rx", "tx", "rxu", "txu"; -- cgit v0.10.2 From 4a4e2138d6bb5e6b80e283df73c1acabb0b992f7 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 20 May 2016 09:10:14 +0200 Subject: arm64: dts: salvator-x: Fix W=1 dtc warnings Warning (unit_address_vs_reg): Node /regulator@1 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /regulator@2 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /regulator@3 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /regulator@4 has a unit name, but no reg property Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman diff --git a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts index 8408292..98f0263 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts +++ b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts @@ -62,7 +62,7 @@ clock-frequency = <24576000>; }; - vcc_sdhi0: regulator@1 { + vcc_sdhi0: regulator-vcc-sdhi0 { compatible = "regulator-fixed"; regulator-name = "SDHI0 Vcc"; @@ -73,7 +73,7 @@ enable-active-high; }; - vccq_sdhi0: regulator@2 { + vccq_sdhi0: regulator-vccq-sdhi0 { compatible = "regulator-gpio"; regulator-name = "SDHI0 VccQ"; @@ -86,7 +86,7 @@ 1800000 0>; }; - vcc_sdhi3: regulator@3 { + vcc_sdhi3: regulator-vcc-sdhi3 { compatible = "regulator-fixed"; regulator-name = "SDHI3 Vcc"; @@ -97,7 +97,7 @@ enable-active-high; }; - vccq_sdhi3: regulator@4 { + vccq_sdhi3: regulator-vccq-sdhi3 { compatible = "regulator-gpio"; regulator-name = "SDHI3 VccQ"; -- cgit v0.10.2 From 21cc405c8a6332ddad2d2751a9723b2b3e227a05 Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Wed, 25 May 2016 10:11:40 +0900 Subject: arm64: dts: r8a7795: Drop 0x from unit address of gic Drop 0x from unit address of gic as this is the desired form for a unit address. Signed-off-by: Simon Horman Acked-by: Geert Uytterhoeven diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi index a4f4ec8..04eb0bc 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi @@ -153,7 +153,7 @@ #size-cells = <2>; ranges; - gic: interrupt-controller@0xf1010000 { + gic: interrupt-controller@f1010000 { compatible = "arm,gic-400"; #interrupt-cells = <3>; #address-cells = <0>; -- cgit v0.10.2 From a09906cd8c185a9f6493a1364f500f9f2aea6b22 Mon Sep 17 00:00:00 2001 From: Xing Zheng Date: Fri, 13 May 2016 13:50:18 -0700 Subject: arm64: dts: rockchip: assign default rates for core rk3399 clocks These clocks are all core clocks used by many blocks/peripherals, many of whose drivers don't set their clock rates at all. Let's assign reasonable default clock rates for these core clocks, so that these peripherals get something reasonable by default, and also so that if child devices want to select a clock rate themselves, their muxes have some reasonable parent clock rates to branch off of (rather than just the boot-time defaults). This helps the eMMC PHY, for one, to get a reasonable ACLK rate. Signed-off-by: Xing Zheng Signed-off-by: Brian Norris Reviewed-by: Douglas Anderson Signed-off-by: Heiko Stuebner diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index 46f325a..6fa9cc3 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -478,6 +478,22 @@ reg = <0x0 0xff760000 0x0 0x1000>; #clock-cells = <1>; #reset-cells = <1>; + assigned-clocks = + <&cru PLL_GPLL>, <&cru PLL_CPLL>, + <&cru PLL_NPLL>, + <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>, + <&cru PCLK_PERIHP>, + <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>, + <&cru PCLK_PERILP0>, + <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>; + assigned-clock-rates = + <594000000>, <800000000>, + <1000000000>, + <150000000>, <75000000>, + <37500000>, + <100000000>, <100000000>, + <50000000>, + <100000000>, <50000000>; }; grf: syscon@ff770000 { -- cgit v0.10.2 From 16759262492cd79e0f1ee1f61076f180e1c441d1 Mon Sep 17 00:00:00 2001 From: Brian Norris Date: Fri, 13 May 2016 15:12:02 -0700 Subject: arm64: dts: rockchip: make rk3399's grf a "simple-mfd" Per the examples in Documentation/devicetree/bindings/phy/rockchip-emmc-phy.txt, we need the grf node to be a simple-mfd in order to properly enumerate child devices like our eMMC PHY. Signed-off-by: Brian Norris Reviewed-by: Douglas Anderson [directly mimic for the pmugrf, which will need the same change later and there is no need to pollute commit history with another patch] Signed-off-by: Heiko Stuebner diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index 6fa9cc3..f42589f 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -390,8 +390,10 @@ }; pmugrf: syscon@ff320000 { - compatible = "rockchip,rk3399-pmugrf", "syscon"; + compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd"; reg = <0x0 0xff320000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; }; spi3: spi@ff350000 { @@ -497,8 +499,10 @@ }; grf: syscon@ff770000 { - compatible = "rockchip,rk3399-grf", "syscon"; + compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd"; reg = <0x0 0xff770000 0x0 0x10000>; + #address-cells = <1>; + #size-cells = <1>; }; watchdog@ff840000 { -- cgit v0.10.2 From b4e87c097c0858e432ac13010b114e2659ffa70f Mon Sep 17 00:00:00 2001 From: Brian Norris Date: Fri, 13 May 2016 15:12:03 -0700 Subject: arm64: dts: rockchip: add sdhci/emmc for rk3399 Add description for the SDHCI v5.1 eMMC controller on rk3399. Fix it to 200 MHz, to support all supported timing modes. Note that 'rockchip,rk3399-sdhci-5.1' is not documented; we presumably have a compliant Arasan controller, but let's have a rockchip property as the canonical backup/precautionary measure. Per Heiko's previous suggestion, let's not clutter the arasan doc with it. Signed-off-by: Brian Norris Reviewed-by: Shawn Lin Reviewed-by: Douglas Anderson Signed-off-by: Heiko Stuebner diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index f42589f..a6a60fa 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -215,6 +215,19 @@ status = "disabled"; }; + sdhci: sdhci@fe330000 { + compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1"; + reg = <0x0 0xfe330000 0x0 0x10000>; + interrupts = ; + assigned-clocks = <&cru SCLK_EMMC>; + assigned-clock-rates = <200000000>; + clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>; + clock-names = "clk_xin", "clk_ahb"; + phys = <&emmc_phy>; + phy-names = "phy_arasan"; + status = "disabled"; + }; + usb_host0_ehci: usb@fe380000 { compatible = "generic-ehci"; reg = <0x0 0xfe380000 0x0 0x20000>; @@ -503,6 +516,13 @@ reg = <0x0 0xff770000 0x0 0x10000>; #address-cells = <1>; #size-cells = <1>; + + emmc_phy: phy@f780 { + compatible = "rockchip,rk3399-emmc-phy"; + reg = <0xf780 0x24>; + #phy-cells = <0>; + status = "disabled"; + }; }; watchdog@ff840000 { -- cgit v0.10.2 From 13b2b3e23d54ce9120c581697a0ab837b7c088b0 Mon Sep 17 00:00:00 2001 From: Brian Norris Date: Fri, 13 May 2016 15:12:04 -0700 Subject: arm64: dts: rockchip: enable eMMC for rk3399 EVB Rockchip's rk3399 evaluation board has eMMC. Let's enable the newly-added nodes. Signed-off-by: Brian Norris Reviewed-by: Douglas Anderson Signed-off-by: Heiko Stuebner diff --git a/arch/arm64/boot/dts/rockchip/rk3399-evb.dts b/arch/arm64/boot/dts/rockchip/rk3399-evb.dts index 1a3eb14..d33aa06 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-evb.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-evb.dts @@ -77,6 +77,10 @@ }; }; +&emmc_phy { + status = "okay"; +}; + &pwm0 { status = "okay"; }; @@ -89,6 +93,14 @@ status = "okay"; }; +&sdhci { + bus-width = <8>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + non-removable; + status = "okay"; +}; + &uart2 { status = "okay"; }; -- cgit v0.10.2 From 4cca3d9448bcc18b607dce2f962a614a415ddaae Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Mon, 1 Feb 2016 22:09:03 +0100 Subject: arm64: dts: rockchip: make rk3368 grf syscons simple-mfds The general register files do contain a lot of separate functions and while some really are only registers with a lot of different 1-bit settings, there are also a lot of them containing some bigger function blocks. To be able to define these as sub-devices, make them simple-mfds. Signed-off-by: Heiko Stuebner Tested-by: David Wu diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi b/arch/arm64/boot/dts/rockchip/rk3368.dtsi index 8b4a7c9..4fb8484 100644 --- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi @@ -632,7 +632,7 @@ }; pmugrf: syscon@ff738000 { - compatible = "rockchip,rk3368-pmugrf", "syscon"; + compatible = "rockchip,rk3368-pmugrf", "syscon", "simple-mfd"; reg = <0x0 0xff738000 0x0 0x1000>; }; @@ -645,7 +645,7 @@ }; grf: syscon@ff770000 { - compatible = "rockchip,rk3368-grf", "syscon"; + compatible = "rockchip,rk3368-grf", "syscon", "simple-mfd"; reg = <0x0 0xff770000 0x0 0x1000>; }; -- cgit v0.10.2 From d1ab05aba954ec02f087f6908d4e060655bde92c Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Sat, 21 May 2016 12:43:27 +0200 Subject: arm64: dts: rockchip: add rk3368 io-domain core nodes Add the core io-domain nodes to grf and pmugrf which individual boards than just have to enable and add the necessary supplies to. Signed-off-by: Heiko Stuebner diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi b/arch/arm64/boot/dts/rockchip/rk3368.dtsi index 4fb8484..58c2585 100644 --- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi @@ -634,6 +634,11 @@ pmugrf: syscon@ff738000 { compatible = "rockchip,rk3368-pmugrf", "syscon", "simple-mfd"; reg = <0x0 0xff738000 0x0 0x1000>; + + pmu_io_domains: io-domains { + compatible = "rockchip,rk3368-pmu-io-voltage-domain"; + status = "disabled"; + }; }; cru: clock-controller@ff760000 { @@ -647,6 +652,11 @@ grf: syscon@ff770000 { compatible = "rockchip,rk3368-grf", "syscon", "simple-mfd"; reg = <0x0 0xff770000 0x0 0x1000>; + + io_domains: io-domains { + compatible = "rockchip,rk3368-io-voltage-domain"; + status = "disabled"; + }; }; wdt: watchdog@ff800000 { -- cgit v0.10.2 From 39e5f7bb98c979f563e08e8e4cd70989e5369da3 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Wed, 29 Jul 2015 16:13:35 +0200 Subject: arm64: dts: rockchip: add rk3368-r88 iodomains Add the supply-links according to the R88 schematics. Signed-off-by: Heiko Stuebner diff --git a/arch/arm64/boot/dts/rockchip/rk3368-r88.dts b/arch/arm64/boot/dts/rockchip/rk3368-r88.dts index b56b720..82a32e5 100644 --- a/arch/arm64/boot/dts/rockchip/rk3368-r88.dts +++ b/arch/arm64/boot/dts/rockchip/rk3368-r88.dts @@ -236,6 +236,15 @@ }; }; +&io_domains { + status = "ok"; + + audio-supply = <&vcc_io>; + gpio30-supply = <&vcc_io>; + gpio1830-supply = <&vcc_io>; + wifi-supply = <&vccio_wl>; +}; + &sdio0 { assigned-clocks = <&cru SCLK_SDIO0>; assigned-clock-parents = <&cru PLL_CPLL>; @@ -329,6 +338,13 @@ }; }; +&pmu_io_domains { + status = "okay"; + + pmu-supply = <&vcc_io>; + vop-supply = <&vcc_io>; +}; + &saradc { vref-supply = <&vcc_18>; status = "okay"; -- cgit v0.10.2 From 6d0e3a45de95dfabb05968db4a630358d2428a2a Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Sat, 21 May 2016 19:55:28 +0200 Subject: arm64: dts: rockchip: add rk3399 io-domain core nodes Add the core io-domain nodes to grf and pmugrf which individual boards than just have to enable and add the necessary supplies to. Signed-off-by: Heiko Stuebner diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index a6a60fa..12acae6 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -407,6 +407,11 @@ reg = <0x0 0xff320000 0x0 0x1000>; #address-cells = <1>; #size-cells = <1>; + + pmu_io_domains: io-domains { + compatible = "rockchip,rk3399-pmu-io-voltage-domain"; + status = "disabled"; + }; }; spi3: spi@ff350000 { @@ -517,6 +522,11 @@ #address-cells = <1>; #size-cells = <1>; + io_domains: io-domains { + compatible = "rockchip,rk3399-io-voltage-domain"; + status = "disabled"; + }; + emmc_phy: phy@f780 { compatible = "rockchip,rk3399-emmc-phy"; reg = <0xf780 0x24>; -- cgit v0.10.2 From 6e62688c1d0b568fa5451341bdd7f382c80ac338 Mon Sep 17 00:00:00 2001 From: Anup Patel Date: Mon, 28 Mar 2016 10:18:29 +0530 Subject: dt-bindings: ata: add compatible string for iProc AHCI controller The Broadcom iProc SoCs have AHCI compliant SATA controller. This patch adds common compatible string for AHCI SATA controller on iProc SoCs. Signed-off-by: Anup Patel Acked-by: Rob Herring Signed-off-by: Florian Fainelli diff --git a/Documentation/devicetree/bindings/ata/ahci-platform.txt b/Documentation/devicetree/bindings/ata/ahci-platform.txt index 87adfb2..fedc213 100644 --- a/Documentation/devicetree/bindings/ata/ahci-platform.txt +++ b/Documentation/devicetree/bindings/ata/ahci-platform.txt @@ -10,6 +10,7 @@ PHYs. Required properties: - compatible : compatible string, one of: - "allwinner,sun4i-a10-ahci" + - "brcm,iproc-ahci" - "hisilicon,hisi-ahci" - "cavium,octeon-7130-ahci" - "ibm,476gtr-ahci" -- cgit v0.10.2 From ac9aae00f0fc417a481b869b5bdc725df4609ecf Mon Sep 17 00:00:00 2001 From: Anup Patel Date: Mon, 28 Mar 2016 10:18:30 +0530 Subject: arm64: dts: Add SATA3 AHCI and SATA3 PHY DT nodes for NS2 We have one dual-port SATA3 AHCI controller present in NS2 SoC. This patch enables SATA3 AHCI controller and SATA3 PHY for NS2 SoC in NS2 DT. Signed-off-by: Anup Patel Reviewed-by: Ray Jui Reviewed-by: Scott Branden Signed-off-by: Florian Fainelli diff --git a/arch/arm64/boot/dts/broadcom/ns2-svk.dts b/arch/arm64/boot/dts/broadcom/ns2-svk.dts index 54ca40c..71c14c9 100644 --- a/arch/arm64/boot/dts/broadcom/ns2-svk.dts +++ b/arch/arm64/boot/dts/broadcom/ns2-svk.dts @@ -117,6 +117,18 @@ }; }; +&sata_phy0 { + status = "ok"; +}; + +&sata_phy1 { + status = "ok"; +}; + +&sata { + status = "ok"; +}; + &sdio0 { status = "ok"; }; diff --git a/arch/arm64/boot/dts/broadcom/ns2.dtsi b/arch/arm64/boot/dts/broadcom/ns2.dtsi index ec68ec1..0c87965 100644 --- a/arch/arm64/boot/dts/broadcom/ns2.dtsi +++ b/arch/arm64/boot/dts/broadcom/ns2.dtsi @@ -368,6 +368,49 @@ reg = <0x66220000 0x28>; }; + sata_phy: sata_phy@663f0100 { + compatible = "brcm,iproc-ns2-sata-phy"; + reg = <0x663f0100 0x1f00>, + <0x663f004c 0x10>; + reg-names = "phy", "phy-ctrl"; + #address-cells = <1>; + #size-cells = <0>; + + sata_phy0: sata-phy@0 { + reg = <0>; + #phy-cells = <0>; + status = "disabled"; + }; + + sata_phy1: sata-phy@1 { + reg = <1>; + #phy-cells = <0>; + status = "disabled"; + }; + }; + + sata: ahci@663f2000 { + compatible = "brcm,iproc-ahci", "generic-ahci"; + reg = <0x663f2000 0x1000>; + reg-names = "ahci"; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + sata0: sata-port@0 { + reg = <0>; + phys = <&sata_phy0>; + phy-names = "sata-phy"; + }; + + sata1: sata-port@1 { + reg = <1>; + phys = <&sata_phy1>; + phy-names = "sata-phy"; + }; + }; + sdio0: sdhci@66420000 { compatible = "brcm,sdhci-iproc-cygnus"; reg = <0x66420000 0x100>; -- cgit v0.10.2 From 97b1504a30b3b88ffb6a0502c01bf0868a1704c8 Mon Sep 17 00:00:00 2001 From: Yendapally Reddy Dhananjaya Reddy Date: Fri, 29 Apr 2016 08:51:39 -0400 Subject: arm64: dts: enable pinctrl for Broadcom NS2 SoC This enables the pinctrl support for Broadcom NS2 SoC Signed-off-by: Yendapally Reddy Dhananjaya Reddy Reviewed-by: Ray Jui Acked-by: Linus Walleij Signed-off-by: Florian Fainelli diff --git a/arch/arm64/boot/dts/broadcom/ns2-svk.dts b/arch/arm64/boot/dts/broadcom/ns2-svk.dts index 71c14c9..7cd3640 100644 --- a/arch/arm64/boot/dts/broadcom/ns2-svk.dts +++ b/arch/arm64/boot/dts/broadcom/ns2-svk.dts @@ -144,3 +144,12 @@ #size-cells = <1>; }; }; + +&pinctrl { + pinctrl-names = "default"; + pinctrl-0 = <&nand_sel>; + nand_sel: nand_sel { + function = "nand"; + groups = "nand_grp"; + }; +}; diff --git a/arch/arm64/boot/dts/broadcom/ns2.dtsi b/arch/arm64/boot/dts/broadcom/ns2.dtsi index 0c87965..4e48b86a 100644 --- a/arch/arm64/boot/dts/broadcom/ns2.dtsi +++ b/arch/arm64/boot/dts/broadcom/ns2.dtsi @@ -251,6 +251,13 @@ mmu-masters; }; + pinctrl: pinctrl@6501d130 { + compatible = "brcm,ns2-pinmux"; + reg = <0x6501d130 0x08>, + <0x660a0028 0x04>, + <0x660009b0 0x40>; + }; + gic: interrupt-controller@65210000 { compatible = "arm,gic-400"; #interrupt-cells = <3>; -- cgit v0.10.2 From 5f2fb24141b948a3d91f249c7416262362496e54 Mon Sep 17 00:00:00 2001 From: Yendapally Reddy Dhananjaya Reddy Date: Fri, 4 Mar 2016 05:23:30 -0500 Subject: arm64: dts: Enable GPIO for Broadcom NS2 SoC This enables the GPIO support for Broadcom NS2 SoC Signed-off-by: Yendapally Reddy Dhananjaya Reddy Signed-off-by: Florian Fainelli diff --git a/arch/arm64/boot/dts/broadcom/ns2.dtsi b/arch/arm64/boot/dts/broadcom/ns2.dtsi index 4e48b86a..788ed8f 100644 --- a/arch/arm64/boot/dts/broadcom/ns2.dtsi +++ b/arch/arm64/boot/dts/broadcom/ns2.dtsi @@ -258,6 +258,15 @@ <0x660009b0 0x40>; }; + gpio_aon: gpio@65024800 { + compatible = "brcm,iproc-gpio"; + reg = <0x65024800 0x50>, + <0x65024008 0x18>; + ngpios = <6>; + #gpio-cells = <2>; + gpio-controller; + }; + gic: interrupt-controller@65210000 { compatible = "arm,gic-400"; #interrupt-cells = <3>; @@ -328,6 +337,16 @@ clock-names = "wdogclk", "apb_pclk"; }; + gpio_g: gpio@660a0000 { + compatible = "brcm,iproc-gpio"; + reg = <0x660a0000 0x50>; + ngpios = <32>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + interrupts = ; + }; + i2c1: i2c@660b0000 { compatible = "brcm,iproc-i2c"; reg = <0x660b0000 0x100>; -- cgit v0.10.2 From 1e0fdee81e24226dc6805aad00902f9d71c8e28c Mon Sep 17 00:00:00 2001 From: Jon Mason Date: Wed, 11 May 2016 18:56:08 -0400 Subject: arm64: dts: NS2: Add all of the UARTs Add all of the UARTs present on NS2 and enable them in the SVK device tree file. Also, do some magic to make sure that uart3 is discovered as ttyS0 (as that is the console UART). Signed-off-by: Jon Mason Signed-off-by: Florian Fainelli diff --git a/arch/arm64/boot/dts/broadcom/ns2-svk.dts b/arch/arm64/boot/dts/broadcom/ns2-svk.dts index 7cd3640..b062a44 100644 --- a/arch/arm64/boot/dts/broadcom/ns2-svk.dts +++ b/arch/arm64/boot/dts/broadcom/ns2-svk.dts @@ -40,10 +40,14 @@ aliases { serial0 = &uart3; + serial1 = &uart0; + serial2 = &uart1; + serial3 = &uart2; }; chosen { stdout-path = "serial0:115200n8"; + bootargs = "earlycon=uart8250,mmio32,0x66130000"; }; memory { @@ -68,6 +72,18 @@ status = "ok"; }; +&uart0 { + status = "ok"; +}; + +&uart1 { + status = "ok"; +}; + +&uart2 { + status = "ok"; +}; + &uart3 { status = "ok"; }; diff --git a/arch/arm64/boot/dts/broadcom/ns2.dtsi b/arch/arm64/boot/dts/broadcom/ns2.dtsi index 788ed8f..c77a9e8 100644 --- a/arch/arm64/boot/dts/broadcom/ns2.dtsi +++ b/arch/arm64/boot/dts/broadcom/ns2.dtsi @@ -357,6 +357,36 @@ status = "disabled"; }; + uart0: serial@66100000 { + compatible = "snps,dw-apb-uart"; + reg = <0x66100000 0x100>; + interrupts = ; + clocks = <&iprocslow>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart1: serial@66110000 { + compatible = "snps,dw-apb-uart"; + reg = <0x66110000 0x100>; + interrupts = ; + clocks = <&iprocslow>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart2: serial@66120000 { + compatible = "snps,dw-apb-uart"; + reg = <0x66120000 0x100>; + interrupts = ; + clocks = <&iprocslow>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + uart3: serial@66130000 { compatible = "snps,dw-apb-uart"; reg = <0x66130000 0x100>; -- cgit v0.10.2 From 5dcc9c7618dff61de243ca9bbac7de18ef92f49b Mon Sep 17 00:00:00 2001 From: Jon Mason Date: Wed, 11 May 2016 18:56:09 -0400 Subject: arm64: dts: NS2: Add CCI-400 PMU support Add support to the Northstar 2 Device tree file for the ARM CCI-400 PMU. Signed-off-by: Jon Mason Signed-off-by: Florian Fainelli diff --git a/arch/arm64/boot/dts/broadcom/ns2.dtsi b/arch/arm64/boot/dts/broadcom/ns2.dtsi index c77a9e8..d1dc812 100644 --- a/arch/arm64/boot/dts/broadcom/ns2.dtsi +++ b/arch/arm64/boot/dts/broadcom/ns2.dtsi @@ -279,6 +279,26 @@ IRQ_TYPE_LEVEL_HIGH)>; }; + cci@65590000 { + compatible = "arm,cci-400"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x65590000 0x1000>; + ranges = <0 0x65590000 0x10000>; + + pmu@9000 { + compatible = "arm,cci-400-pmu,r1", + "arm,cci-400-pmu"; + reg = <0x9000 0x4000>; + interrupts = , + , + , + , + , + ; + }; + }; + timer0: timer@66030000 { compatible = "arm,sp804", "arm,primecell"; reg = <0x66030000 0x1000>; -- cgit v0.10.2 From fab6b48ccab3a21a4ea397d47eddf1f7fa2305f5 Mon Sep 17 00:00:00 2001 From: Carlo Caione Date: Sun, 3 Apr 2016 19:14:41 +0200 Subject: ARM64: dts: amlogic: Add hiu and periphs buses Add two new buses in the DTS: hiu and periphs buses. In the Amlogic S905/GXBB SoC several devices (clock / eth / pin controllers, etc...) are mapped under these two buses. Add them in the DT before starting to add new devices. Signed-off-by: Carlo Caione Signed-off-by: Kevin Hilman diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi index 832815d..3126f0c 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi @@ -167,6 +167,22 @@ }; }; + periphs: periphs@c8834000 { + compatible = "simple-bus"; + reg = <0x0 0xc8834000 0x0 0x2000>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0xc8834000 0x0 0x2000>; + }; + + hiubus: hiubus@c883c000 { + compatible = "simple-bus"; + reg = <0x0 0xc883c000 0x0 0x2000>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0xc883c000 0x0 0x2000>; + }; + apb: apb@d0000000 { compatible = "simple-bus"; reg = <0x0 0xd0000000 0x0 0x200000>; -- cgit v0.10.2 From 551a626c9b1b2c2d983e75fb75c20935eff67abb Mon Sep 17 00:00:00 2001 From: Carlo Caione Date: Mon, 2 May 2016 10:02:16 +0200 Subject: documentation: Add compatibles for Amlogic Meson GXBB pin controllers Add the two new compatibles for the Amlogic Meson GXBB pin controllers. Signed-off-by: Carlo Caione Signed-off-by: Kevin Hilman diff --git a/Documentation/devicetree/bindings/pinctrl/meson,pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/meson,pinctrl.txt index 32f4a2d..fe7fe0b 100644 --- a/Documentation/devicetree/bindings/pinctrl/meson,pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/meson,pinctrl.txt @@ -5,6 +5,8 @@ Required properties for the root node: "amlogic,meson8b-cbus-pinctrl" "amlogic,meson8-aobus-pinctrl" "amlogic,meson8b-aobus-pinctrl" + "amlogic,meson-gxbb-periphs-pinctrl" + "amlogic,meson-gxbb-aobus-pinctrl" - reg: address and size of registers controlling irq functionality === GPIO sub-nodes === -- cgit v0.10.2 From f40d437f55264b2f48446b9cb9b8d7db5f588770 Mon Sep 17 00:00:00 2001 From: Carlo Caione Date: Mon, 2 May 2016 10:02:18 +0200 Subject: ARM64: dts: amlogic: Enable pin controller on GXBB-based platforms Update DTS and DTSI files to enable the pin controller. We also now support the blinking blue LED on the Odroid-C2. Signed-off-by: Carlo Caione Acked-by: Linus Walleij Signed-off-by: Kevin Hilman diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts index 7f2c674..41e1e66 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts @@ -45,6 +45,7 @@ /dts-v1/; #include "meson-gxbb.dtsi" +#include / { compatible = "hardkernel,odroid-c2", "amlogic,meson-gxbb"; @@ -62,8 +63,20 @@ device_type = "memory"; reg = <0x0 0x0 0x0 0x80000000>; }; + + leds { + compatible = "gpio-leds"; + blue { + label = "c2:blue:alive"; + gpios = <&gpio_ao GPIOAO_13 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + default-state = "off"; + }; + }; }; &uart_AO { status = "okay"; + pinctrl-0 = <&uart_ao_a_pins>; + pinctrl-names = "default"; }; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi index bf7ff1d..22e6298 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi @@ -62,4 +62,6 @@ /* This UART is brought out to the DB9 connector */ &uart_AO { status = "okay"; + pinctrl-0 = <&uart_ao_a_pins>; + pinctrl-names = "default"; }; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi index 012cdcc..54bb7c7 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi @@ -56,4 +56,7 @@ &uart_AO { status = "okay"; + pinctrl-0 = <&uart_ao_a_pins>; + pinctrl-names = "default"; + }; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi index 3126f0c..6dd2768 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi @@ -43,6 +43,7 @@ #include #include #include +#include / { compatible = "amlogic,meson-gxbb"; @@ -158,6 +159,29 @@ #size-cells = <2>; ranges = <0x0 0x0 0x0 0xc8100000 0x0 0x100000>; + pinctrl_aobus: pinctrl@14 { + compatible = "amlogic,meson-gxbb-aobus-pinctrl"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gpio_ao: bank@14 { + reg = <0x0 0x00014 0x0 0x8>, + <0x0 0x0002c 0x0 0x4>, + <0x0 0x00024 0x0 0x8>; + reg-names = "mux", "pull", "gpio"; + gpio-controller; + #gpio-cells = <2>; + }; + + uart_ao_a_pins: uart_ao_a { + mux { + groups = "uart_tx_ao_a", "uart_rx_ao_a"; + function = "uart_ao"; + }; + }; + }; + uart_AO: serial@4c0 { compatible = "amlogic,meson-uart"; reg = <0x0 0x004c0 0x0 0x14>; @@ -173,6 +197,23 @@ #address-cells = <2>; #size-cells = <2>; ranges = <0x0 0x0 0x0 0xc8834000 0x0 0x2000>; + + pinctrl_periphs: pinctrl@4b0 { + compatible = "amlogic,meson-gxbb-periphs-pinctrl"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gpio: bank@4b0 { + reg = <0x0 0x004b0 0x0 0x28>, + <0x0 0x004e8 0x0 0x14>, + <0x0 0x00120 0x0 0x14>, + <0x0 0x00430 0x0 0x40>; + reg-names = "mux", "pull", "pull-enable", "gpio"; + gpio-controller; + #gpio-cells = <2>; + }; + }; }; hiubus: hiubus@c883c000 { -- cgit v0.10.2 From a8025ed6965dc8697ddaea0284e84e3082809940 Mon Sep 17 00:00:00 2001 From: Kevin Hilman Date: Tue, 26 Apr 2016 14:05:19 -0700 Subject: ARM64: dts: amlogic: add pins for EMMC, SD Acked-by: Carlo Caione Signed-off-by: Kevin Hilman diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi index 6dd2768..e01f3b5 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi @@ -213,6 +213,27 @@ gpio-controller; #gpio-cells = <2>; }; + + emmc_pins: emmc { + mux { + groups = "emmc_nand_d07", + "emmc_cmd", + "emmc_clk"; + function = "emmc"; + }; + }; + + sdcard_pins: sdcard { + mux { + groups = "sdcard_d0", + "sdcard_d1", + "sdcard_d2", + "sdcard_d3", + "sdcard_cmd", + "sdcard_clk"; + function = "sdcard"; + }; + }; }; }; -- cgit v0.10.2 From 8e6320dd4aaec53baf2f7e90aac80e520cd45f08 Mon Sep 17 00:00:00 2001 From: Kevin Hilman Date: Wed, 27 Apr 2016 16:12:28 -0700 Subject: ARM64: dts: amlogic: gxbb: pinctrl: add/update UART Add DT nodes for additional UARTs (UART B & C in EE domain) and add pins for all EE domain UARTs. Acked-by: Carlo Caione Signed-off-by: Kevin Hilman diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts index 41e1e66..4577889 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts @@ -80,3 +80,4 @@ pinctrl-0 = <&uart_ao_a_pins>; pinctrl-names = "default"; }; + diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi index e01f3b5..075a8f8 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi @@ -132,11 +132,27 @@ uart_A: serial@84c0 { compatible = "amlogic,meson-uart"; - reg = <0x0 0x084c0 0x0 0x14>; + reg = <0x0 0x84c0 0x0 0x14>; interrupts = ; clocks = <&xtal>; status = "disabled"; }; + + uart_B: serial@84dc { + compatible = "amlogic,meson-uart"; + reg = <0x0 0x84dc 0x0 0x14>; + interrupts = ; + clocks = <&xtal>; + status = "disabled"; + }; + + uart_C: serial@8700 { + compatible = "amlogic,meson-uart"; + reg = <0x0 0x8700 0x0 0x14>; + interrupts = ; + clocks = <&xtal>; + status = "disabled"; + }; }; gic: interrupt-controller@c4301000 { @@ -234,6 +250,30 @@ function = "sdcard"; }; }; + + uart_a_pins: uart_a { + mux { + groups = "uart_tx_a", + "uart_rx_a"; + function = "uart_a"; + }; + }; + + uart_b_pins: uart_b { + mux { + groups = "uart_tx_b", + "uart_rx_b"; + function = "uart_b"; + }; + }; + + uart_c_pins: uart_c { + mux { + groups = "uart_tx_c", + "uart_rx_c"; + function = "uart_c"; + }; + }; }; }; -- cgit v0.10.2 From 8c5509f01932e5144c9282955c33828e9ff8222c Mon Sep 17 00:00:00 2001 From: Kevin Hilman Date: Wed, 27 Apr 2016 16:58:25 -0700 Subject: ARM64: dts: amlogic: gxbb: add ethernet Add node for ethernet interface and pinctrl pins. Enable on odroid-C2 and P20x boards. Acked-by: Carlo Caione Signed-off-by: Kevin Hilman diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts index 4577889..90a84c5 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts @@ -81,3 +81,9 @@ pinctrl-names = "default"; }; +ðmac { + status = "okay"; + pinctrl-0 = <ð_pins>; + pinctrl-names = "default"; +}; + diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi index 22e6298..f4f30f6 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi @@ -65,3 +65,10 @@ pinctrl-0 = <&uart_ao_a_pins>; pinctrl-names = "default"; }; + +ðmac { + status = "okay"; + pinctrl-0 = <ð_pins>; + pinctrl-names = "default"; +}; + diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi index 075a8f8..11f33bf 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi @@ -274,6 +274,26 @@ function = "uart_c"; }; }; + + eth_pins: eth_c { + mux { + groups = "eth_mdio", + "eth_mdc", + "eth_clk_rx_clk", + "eth_rx_dv", + "eth_rxd0", + "eth_rxd1", + "eth_rxd2", + "eth_rxd3", + "eth_rgmii_tx_clk", + "eth_tx_en", + "eth_txd0", + "eth_txd1", + "eth_txd2", + "eth_txd3"; + function = "eth"; + }; + }; }; }; @@ -292,5 +312,17 @@ #size-cells = <2>; ranges = <0x0 0x0 0x0 0xd0000000 0x0 0x200000>; }; + + ethmac: ethernet@c9410000 { + compatible = "amlogic,meson6-dwmac", "snps,dwmac"; + reg = <0x0 0xc9410000 0x0 0x10000 + 0x0 0xc8834540 0x0 0x4>; + interrupts = <0 8 1>; + interrupt-names = "macirq"; + clocks = <&xtal>; + clock-names = "stmmaceth"; + phy-mode = "rgmii"; + status = "disabled"; + }; }; }; -- cgit v0.10.2 From 6d1a5c9381eb022104442b2e036124f12ac748e4 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Mon, 30 May 2016 15:27:17 +0200 Subject: ARM64: dts: amlogic: Enable Reset Controller on GXBB-based platforms Update DTSI file to add the reset controller node. Signed-off-by: Neil Armstrong Signed-off-by: Kevin Hilman diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi index 11f33bf..063e3b6 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi @@ -44,6 +44,7 @@ #include #include #include +#include / { compatible = "amlogic,meson-gxbb"; @@ -130,6 +131,12 @@ #size-cells = <2>; ranges = <0x0 0x0 0x0 0xc1100000 0x0 0x100000>; + reset: reset-controller@4404 { + compatible = "amlogic,meson-gxbb-reset"; + reg = <0x0 0x04404 0x0 0x20>; + #reset-cells = <1>; + }; + uart_A: serial@84c0 { compatible = "amlogic,meson-uart"; reg = <0x0 0x84c0 0x0 0x14>; -- cgit v0.10.2 From 81ad4dbaf7afff590e81c7fe0c519c5a67d1a444 Mon Sep 17 00:00:00 2001 From: CK Hu Date: Fri, 3 Jun 2016 16:59:29 +0200 Subject: arm64: dts: mt8173: Add display subsystem related nodes This patch adds the device nodes for the DISP function blocks comprising the display subsystem. Signed-off-by: CK Hu Signed-off-by: Cawa Cheng Signed-off-by: Jie Qiu Signed-off-by: Daniel Kurtz Signed-off-by: Philipp Zabel Signed-off-by: Matthias Brugger diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi index 05f89c4..78529e4 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi @@ -26,6 +26,23 @@ #address-cells = <2>; #size-cells = <2>; + aliases { + ovl0 = &ovl0; + ovl1 = &ovl1; + rdma0 = &rdma0; + rdma1 = &rdma1; + rdma2 = &rdma2; + wdma0 = &wdma0; + wdma1 = &wdma1; + color0 = &color0; + color1 = &color1; + split0 = &split0; + split1 = &split1; + dpi0 = &dpi0; + dsi0 = &dsi0; + dsi1 = &dsi1; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -343,6 +360,26 @@ #clock-cells = <1>; }; + mipi_tx0: mipi-dphy@10215000 { + compatible = "mediatek,mt8173-mipi-tx"; + reg = <0 0x10215000 0 0x1000>; + clocks = <&clk26m>; + clock-output-names = "mipi_tx0_pll"; + #clock-cells = <0>; + #phy-cells = <0>; + status = "disabled"; + }; + + mipi_tx1: mipi-dphy@10216000 { + compatible = "mediatek,mt8173-mipi-tx"; + reg = <0 0x10216000 0 0x1000>; + clocks = <&clk26m>; + clock-output-names = "mipi_tx1_pll"; + #clock-cells = <0>; + #phy-cells = <0>; + status = "disabled"; + }; + gic: interrupt-controller@10220000 { compatible = "arm,gic-400"; #interrupt-cells = <3>; @@ -652,9 +689,181 @@ mmsys: clock-controller@14000000 { compatible = "mediatek,mt8173-mmsys", "syscon"; reg = <0 0x14000000 0 0x1000>; + power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; #clock-cells = <1>; }; + ovl0: ovl@1400c000 { + compatible = "mediatek,mt8173-disp-ovl"; + reg = <0 0x1400c000 0 0x1000>; + interrupts = ; + power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; + clocks = <&mmsys CLK_MM_DISP_OVL0>; + iommus = <&iommu M4U_PORT_DISP_OVL0>; + mediatek,larb = <&larb0>; + }; + + ovl1: ovl@1400d000 { + compatible = "mediatek,mt8173-disp-ovl"; + reg = <0 0x1400d000 0 0x1000>; + interrupts = ; + power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; + clocks = <&mmsys CLK_MM_DISP_OVL1>; + iommus = <&iommu M4U_PORT_DISP_OVL1>; + mediatek,larb = <&larb4>; + }; + + rdma0: rdma@1400e000 { + compatible = "mediatek,mt8173-disp-rdma"; + reg = <0 0x1400e000 0 0x1000>; + interrupts = ; + power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; + clocks = <&mmsys CLK_MM_DISP_RDMA0>; + iommus = <&iommu M4U_PORT_DISP_RDMA0>; + mediatek,larb = <&larb0>; + }; + + rdma1: rdma@1400f000 { + compatible = "mediatek,mt8173-disp-rdma"; + reg = <0 0x1400f000 0 0x1000>; + interrupts = ; + power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; + clocks = <&mmsys CLK_MM_DISP_RDMA1>; + iommus = <&iommu M4U_PORT_DISP_RDMA1>; + mediatek,larb = <&larb4>; + }; + + rdma2: rdma@14010000 { + compatible = "mediatek,mt8173-disp-rdma"; + reg = <0 0x14010000 0 0x1000>; + interrupts = ; + power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; + clocks = <&mmsys CLK_MM_DISP_RDMA2>; + iommus = <&iommu M4U_PORT_DISP_RDMA2>; + mediatek,larb = <&larb4>; + }; + + wdma0: wdma@14011000 { + compatible = "mediatek,mt8173-disp-wdma"; + reg = <0 0x14011000 0 0x1000>; + interrupts = ; + power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; + clocks = <&mmsys CLK_MM_DISP_WDMA0>; + iommus = <&iommu M4U_PORT_DISP_WDMA0>; + mediatek,larb = <&larb0>; + }; + + wdma1: wdma@14012000 { + compatible = "mediatek,mt8173-disp-wdma"; + reg = <0 0x14012000 0 0x1000>; + interrupts = ; + power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; + clocks = <&mmsys CLK_MM_DISP_WDMA1>; + iommus = <&iommu M4U_PORT_DISP_WDMA1>; + mediatek,larb = <&larb4>; + }; + + color0: color@14013000 { + compatible = "mediatek,mt8173-disp-color"; + reg = <0 0x14013000 0 0x1000>; + interrupts = ; + power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; + clocks = <&mmsys CLK_MM_DISP_COLOR0>; + }; + + color1: color@14014000 { + compatible = "mediatek,mt8173-disp-color"; + reg = <0 0x14014000 0 0x1000>; + interrupts = ; + power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; + clocks = <&mmsys CLK_MM_DISP_COLOR1>; + }; + + aal@14015000 { + compatible = "mediatek,mt8173-disp-aal"; + reg = <0 0x14015000 0 0x1000>; + interrupts = ; + power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; + clocks = <&mmsys CLK_MM_DISP_AAL>; + }; + + gamma@14016000 { + compatible = "mediatek,mt8173-disp-gamma"; + reg = <0 0x14016000 0 0x1000>; + interrupts = ; + power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; + clocks = <&mmsys CLK_MM_DISP_GAMMA>; + }; + + merge@14017000 { + compatible = "mediatek,mt8173-disp-merge"; + reg = <0 0x14017000 0 0x1000>; + power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; + clocks = <&mmsys CLK_MM_DISP_MERGE>; + }; + + split0: split@14018000 { + compatible = "mediatek,mt8173-disp-split"; + reg = <0 0x14018000 0 0x1000>; + power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; + clocks = <&mmsys CLK_MM_DISP_SPLIT0>; + }; + + split1: split@14019000 { + compatible = "mediatek,mt8173-disp-split"; + reg = <0 0x14019000 0 0x1000>; + power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; + clocks = <&mmsys CLK_MM_DISP_SPLIT1>; + }; + + ufoe@1401a000 { + compatible = "mediatek,mt8173-disp-ufoe"; + reg = <0 0x1401a000 0 0x1000>; + interrupts = ; + power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; + clocks = <&mmsys CLK_MM_DISP_UFOE>; + }; + + dsi0: dsi@1401b000 { + compatible = "mediatek,mt8173-dsi"; + reg = <0 0x1401b000 0 0x1000>; + interrupts = ; + power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; + clocks = <&mmsys CLK_MM_DSI0_ENGINE>, + <&mmsys CLK_MM_DSI0_DIGITAL>, + <&mipi_tx0>; + clock-names = "engine", "digital", "hs"; + phys = <&mipi_tx0>; + phy-names = "dphy"; + status = "disabled"; + }; + + dsi1: dsi@1401c000 { + compatible = "mediatek,mt8173-dsi"; + reg = <0 0x1401c000 0 0x1000>; + interrupts = ; + power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; + clocks = <&mmsys CLK_MM_DSI1_ENGINE>, + <&mmsys CLK_MM_DSI1_DIGITAL>, + <&mipi_tx1>; + clock-names = "engine", "digital", "hs"; + phy = <&mipi_tx1>; + phy-names = "dphy"; + status = "disabled"; + }; + + dpi0: dpi@1401d000 { + compatible = "mediatek,mt8173-dpi"; + reg = <0 0x1401d000 0 0x1000>; + interrupts = ; + power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; + clocks = <&mmsys CLK_MM_DPI_PIXEL>, + <&mmsys CLK_MM_DPI_ENGINE>, + <&apmixedsys CLK_APMIXED_TVDPLL>; + clock-names = "pixel", "engine", "pll"; + status = "disabled"; + }; + pwm0: pwm@1401e000 { compatible = "mediatek,mt8173-disp-pwm", "mediatek,mt6595-disp-pwm"; @@ -677,6 +886,14 @@ status = "disabled"; }; + mutex: mutex@14020000 { + compatible = "mediatek,mt8173-disp-mutex"; + reg = <0 0x14020000 0 0x1000>; + interrupts = ; + power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; + clocks = <&mmsys CLK_MM_MUTEX_32K>; + }; + larb0: larb@14021000 { compatible = "mediatek,mt8173-smi-larb"; reg = <0 0x14021000 0 0x1000>; @@ -696,6 +913,12 @@ clock-names = "apb", "smi"; }; + od@14023000 { + compatible = "mediatek,mt8173-disp-od"; + reg = <0 0x14023000 0 0x1000>; + clocks = <&mmsys CLK_MM_DISP_OD>; + }; + larb4: larb@14027000 { compatible = "mediatek,mt8173-smi-larb"; reg = <0 0x14027000 0 0x1000>; -- cgit v0.10.2 From 95b384f91a3f9d5814587e8e8b617020b4544e41 Mon Sep 17 00:00:00 2001 From: Chanho Min Date: Wed, 1 Jun 2016 10:39:58 +0900 Subject: arm64: dts: Add dts files for LG Electronics's lg1313 SoC Add dtsi file to support lg1313 SoC which based on Cortex-A53. Also add dts file to support lg1312 reference board which based on lg1313 SoC. Signed-off-by: Chanho Min Signed-off-by: Olof Johansson diff --git a/arch/arm64/boot/dts/lg/Makefile b/arch/arm64/boot/dts/lg/Makefile index b0cc649..5c7b54c1 100644 --- a/arch/arm64/boot/dts/lg/Makefile +++ b/arch/arm64/boot/dts/lg/Makefile @@ -1,4 +1,5 @@ dtb-$(CONFIG_ARCH_LG1K) += lg1312-ref.dtb +dtb-$(CONFIG_ARCH_LG1K) += lg1313-ref.dtb always := $(dtb-y) subdir-y := $(dts-dirs) diff --git a/arch/arm64/boot/dts/lg/lg1313-ref.dts b/arch/arm64/boot/dts/lg/lg1313-ref.dts new file mode 100644 index 0000000..df0ece4 --- /dev/null +++ b/arch/arm64/boot/dts/lg/lg1313-ref.dts @@ -0,0 +1,36 @@ +/* + * dts file for lg1313 Reference Board. + * + * Copyright (C) 2016, LG Electronics + */ + +/dts-v1/; + +#include "lg1313.dtsi" + +/ { + #address-cells = <2>; + #size-cells = <1>; + + model = "LG Electronics, DTV SoC LG1313 Reference Board"; + compatible = "lge,lg1313-ref", "lge,lg1313"; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + }; + + memory { + device_type = "memory"; + reg = <0x0 0x00000000 0x20000000>; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/lg/lg1313.dtsi b/arch/arm64/boot/dts/lg/lg1313.dtsi new file mode 100644 index 0000000..e703e11 --- /dev/null +++ b/arch/arm64/boot/dts/lg/lg1313.dtsi @@ -0,0 +1,351 @@ +/* + * dts file for lg1313 SoC + * + * Copyright (C) 2016, LG Electronics + */ + +#include +#include + +/ { + #address-cells = <2>; + #size-cells = <2>; + + compatible = "lge,lg1313"; + interrupt-parent = <&gic>; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x0>; + next-level-cache = <&L2_0>; + }; + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x1>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + }; + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x2>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + }; + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x3>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + }; + L2_0: l2-cache0 { + compatible = "cache"; + }; + }; + + psci { + compatible = "arm,psci-0.2", "arm,psci"; + method = "smc"; + cpu_suspend = <0x84000001>; + cpu_off = <0x84000002>; + cpu_on = <0x84000003>; + }; + + gic: interrupt-controller@c0001000 { + #interrupt-cells = <3>; + compatible = "arm,gic-400"; + interrupt-controller; + reg = <0x0 0xc0001000 0x1000>, + <0x0 0xc0002000 0x2000>, + <0x0 0xc0004000 0x2000>, + <0x0 0xc0006000 0x2000>; + }; + + pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = , + , + , + ; + interrupt-affinity = <&cpu0>, + <&cpu1>, + <&cpu2>, + <&cpu3>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; + + clk_bus: clk_bus { + #clock-cells = <0>; + + compatible = "fixed-clock"; + clock-frequency = <198000000>; + clock-output-names = "BUSCLK"; + }; + + soc { + #address-cells = <2>; + #size-cells = <1>; + + compatible = "simple-bus"; + interrupt-parent = <&gic>; + ranges; + + eth0: ethernet@c3700000 { + compatible = "cdns,gem"; + reg = <0x0 0xc3700000 0x1000>; + interrupts = ; + clocks = <&clk_bus>, <&clk_bus>; + clock-names = "hclk", "pclk"; + phy-mode = "rmii"; + /* Filled in by boot */ + mac-address = [ 00 00 00 00 00 00 ]; + }; + }; + + amba { + #address-cells = <2>; + #size-cells = <1>; + #interrupts-cells = <3>; + + compatible = "simple-bus"; + interrupt-parent = <&gic>; + ranges; + + timers: timer@fd100000 { + compatible = "arm,sp804"; + reg = <0x0 0xfd100000 0x1000>; + interrupts = ; + clocks = <&clk_bus>; + clock-names = "apb_pclk"; + }; + wdog: watchdog@fd200000 { + compatible = "arm,sp805", "arm,primecell"; + reg = <0x0 0xfd200000 0x1000>; + interrupts = ; + clocks = <&clk_bus>; + clock-names = "apb_pclk"; + }; + uart0: serial@fe000000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0xfe000000 0x1000>; + interrupts = ; + clocks = <&clk_bus>; + clock-names = "apb_pclk"; + status="disabled"; + }; + uart1: serial@fe100000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0xfe100000 0x1000>; + interrupts = ; + clocks = <&clk_bus>; + clock-names = "apb_pclk"; + status="disabled"; + }; + uart2: serial@fe200000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0xfe200000 0x1000>; + interrupts = ; + clocks = <&clk_bus>; + clock-names = "apb_pclk"; + status="disabled"; + }; + spi0: ssp@fe800000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x0 0xfe800000 0x1000>; + interrupts = ; + clocks = <&clk_bus>; + clock-names = "apb_pclk"; + }; + spi1: ssp@fe900000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x0 0xfe900000 0x1000>; + interrupts = ; + clocks = <&clk_bus>; + clock-names = "apb_pclk"; + }; + dmac0: dma@c1128000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x0 0xc1128000 0x1000>; + interrupts = ; + clocks = <&clk_bus>; + clock-names = "apb_pclk"; + }; + gpio0: gpio@fd400000 { + #gpio-cells = <2>; + compatible = "arm,pl061", "arm,primecell"; + gpio-controller; + reg = <0x0 0xfd400000 0x1000>; + clocks = <&clk_bus>; + clock-names = "apb_pclk"; + status="disabled"; + }; + gpio1: gpio@fd410000 { + #gpio-cells = <2>; + compatible = "arm,pl061", "arm,primecell"; + gpio-controller; + reg = <0x0 0xfd410000 0x1000>; + clocks = <&clk_bus>; + clock-names = "apb_pclk"; + status="disabled"; + }; + gpio2: gpio@fd420000 { + #gpio-cells = <2>; + compatible = "arm,pl061", "arm,primecell"; + gpio-controller; + reg = <0x0 0xfd420000 0x1000>; + clocks = <&clk_bus>; + clock-names = "apb_pclk"; + status="disabled"; + }; + gpio3: gpio@fd430000 { + #gpio-cells = <2>; + compatible = "arm,pl061", "arm,primecell"; + gpio-controller; + reg = <0x0 0xfd430000 0x1000>; + clocks = <&clk_bus>; + clock-names = "apb_pclk"; + }; + gpio4: gpio@fd440000 { + #gpio-cells = <2>; + compatible = "arm,pl061", "arm,primecell"; + gpio-controller; + reg = <0x0 0xfd440000 0x1000>; + clocks = <&clk_bus>; + clock-names = "apb_pclk"; + status="disabled"; + }; + gpio5: gpio@fd450000 { + #gpio-cells = <2>; + compatible = "arm,pl061", "arm,primecell"; + gpio-controller; + reg = <0x0 0xfd450000 0x1000>; + clocks = <&clk_bus>; + clock-names = "apb_pclk"; + status="disabled"; + }; + gpio6: gpio@fd460000 { + #gpio-cells = <2>; + compatible = "arm,pl061", "arm,primecell"; + gpio-controller; + reg = <0x0 0xfd460000 0x1000>; + clocks = <&clk_bus>; + clock-names = "apb_pclk"; + status="disabled"; + }; + gpio7: gpio@fd470000 { + #gpio-cells = <2>; + compatible = "arm,pl061", "arm,primecell"; + gpio-controller; + reg = <0x0 0xfd470000 0x1000>; + clocks = <&clk_bus>; + clock-names = "apb_pclk"; + status="disabled"; + }; + gpio8: gpio@fd480000 { + #gpio-cells = <2>; + compatible = "arm,pl061", "arm,primecell"; + gpio-controller; + reg = <0x0 0xfd480000 0x1000>; + clocks = <&clk_bus>; + clock-names = "apb_pclk"; + status="disabled"; + }; + gpio9: gpio@fd490000 { + #gpio-cells = <2>; + compatible = "arm,pl061", "arm,primecell"; + gpio-controller; + reg = <0x0 0xfd490000 0x1000>; + clocks = <&clk_bus>; + clock-names = "apb_pclk"; + status="disabled"; + }; + gpio10: gpio@fd4a0000 { + #gpio-cells = <2>; + compatible = "arm,pl061", "arm,primecell"; + gpio-controller; + reg = <0x0 0xfd4a0000 0x1000>; + clocks = <&clk_bus>; + clock-names = "apb_pclk"; + status="disabled"; + }; + gpio11: gpio@fd4b0000 { + #gpio-cells = <2>; + compatible = "arm,pl061", "arm,primecell"; + gpio-controller; + reg = <0x0 0xfd4b0000 0x1000>; + clocks = <&clk_bus>; + clock-names = "apb_pclk"; + }; + gpio12: gpio@fd4c0000 { + #gpio-cells = <2>; + compatible = "arm,pl061", "arm,primecell"; + gpio-controller; + reg = <0x0 0xfd4c0000 0x1000>; + clocks = <&clk_bus>; + clock-names = "apb_pclk"; + status="disabled"; + }; + gpio13: gpio@fd4d0000 { + #gpio-cells = <2>; + compatible = "arm,pl061", "arm,primecell"; + gpio-controller; + reg = <0x0 0xfd4d0000 0x1000>; + clocks = <&clk_bus>; + clock-names = "apb_pclk"; + status="disabled"; + }; + gpio14: gpio@fd4e0000 { + #gpio-cells = <2>; + compatible = "arm,pl061", "arm,primecell"; + gpio-controller; + reg = <0x0 0xfd4e0000 0x1000>; + clocks = <&clk_bus>; + clock-names = "apb_pclk"; + status="disabled"; + }; + gpio15: gpio@fd4f0000 { + #gpio-cells = <2>; + compatible = "arm,pl061", "arm,primecell"; + gpio-controller; + reg = <0x0 0xfd4f0000 0x1000>; + clocks = <&clk_bus>; + clock-names = "apb_pclk"; + status="disabled"; + }; + gpio16: gpio@fd500000 { + #gpio-cells = <2>; + compatible = "arm,pl061", "arm,primecell"; + gpio-controller; + reg = <0x0 0xfd500000 0x1000>; + clocks = <&clk_bus>; + clock-names = "apb_pclk"; + status="disabled"; + }; + gpio17: gpio@fd510000 { + #gpio-cells = <2>; + compatible = "arm,pl061", "arm,primecell"; + gpio-controller; + reg = <0x0 0xfd510000 0x1000>; + clocks = <&clk_bus>; + clock-names = "apb_pclk"; + }; + }; +}; -- cgit v0.10.2 From 95c27ba7bd92febbd72a74658db1132f37a52d2f Mon Sep 17 00:00:00 2001 From: Caesar Wang Date: Wed, 25 May 2016 15:39:35 +0800 Subject: arm64: dts: rockchip: add thermal nodes for rk3399 SoCs This adds thermal zone and tsadc nodes to rk3399 dtsi, rk3399 thermal data is including the cpu and gpu sensor zone node. The thermal zone node is the node containing all the required info for describing a thermal zone, including its cooling device bindings. The thermal zone node must contain, apart from its own properties, one sub-node containing trip nodes and one sub-node containing all the zone cooling maps. The following is the parameter is introduced: * polling-delay: The maximum number of milliseconds to wait between polls * polling-delay-passive: The maximum number of milliseconds to wait between polls when performing passive cooling. * trips: A sub-node which is a container of only trip point nodes required to describe the thermal zone. * cooling-maps: A sub-node which is a container of only cooling device map nodes, used to describe the relation between trips and cooling devices. * cooling-device: A phandle of a cooling device with its specifier, referring to which cooling device is used in this cooling specifier binding. In the cooling specifier, the first cell is the minimum cooling state and the second cell is the maximum cooling state used in this map. Signed-off-by: Caesar Wang Signed-off-by: Heiko Stuebner diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index 12acae6..a4383f3 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -45,6 +45,7 @@ #include #include #include +#include / { compatible = "rockchip,rk3399"; @@ -402,6 +403,95 @@ status = "disabled"; }; + thermal-zones { + cpu_thermal: cpu { + polling-delay-passive = <100>; + polling-delay = <1000>; + + thermal-sensors = <&tsadc 0>; + + trips { + cpu_alert0: cpu_alert0 { + temperature = <70000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu_alert1: cpu_alert1 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu_crit: cpu_crit { + temperature = <95000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu_alert0>; + cooling-device = + <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + map1 { + trip = <&cpu_alert1>; + cooling-device = + <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + gpu_thermal: gpu { + polling-delay-passive = <100>; + polling-delay = <1000>; + + thermal-sensors = <&tsadc 1>; + + trips { + gpu_alert0: gpu_alert0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + gpu_crit: gpu_crit { + temperature = <95000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&gpu_alert0>; + cooling-device = + <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + }; + + tsadc: tsadc@ff260000 { + compatible = "rockchip,rk3399-tsadc"; + reg = <0x0 0xff260000 0x0 0x100>; + interrupts = ; + assigned-clocks = <&cru SCLK_TSADC>; + assigned-clock-rates = <750000>; + clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; + clock-names = "tsadc", "apb_pclk"; + resets = <&cru SRST_TSADC>; + reset-names = "tsadc-apb"; + rockchip,grf = <&grf>; + rockchip,hw-tshut-temp = <95000>; + pinctrl-names = "init", "default", "sleep"; + pinctrl-0 = <&otp_gpio>; + pinctrl-1 = <&otp_out>; + pinctrl-2 = <&otp_gpio>; + #thermal-sensor-cells = <1>; + status = "disabled"; + }; + pmugrf: syscon@ff320000 { compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd"; reg = <0x0 0xff320000 0x0 0x1000>; @@ -931,6 +1021,16 @@ }; }; + tsadc { + otp_gpio: otp-gpio { + rockchip,pins = <1 6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + otp_out: otp-out { + rockchip,pins = <1 6 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + uart0 { uart0_xfer: uart0-xfer { rockchip,pins = -- cgit v0.10.2 From 2f4cd8d0a5193bd205f0bf77648763c5f982ae4a Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Tue, 7 Jun 2016 13:05:44 +0200 Subject: dt-bindings: Add root properties for Raspberry Pi 3 Signed-off-by: Eric Anholt Acked-by: Stephen Warren Acked-by: Rob Herring diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm2835.txt b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm2835.txt index 11d3056..6ffe087 100644 --- a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm2835.txt +++ b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm2835.txt @@ -30,6 +30,10 @@ Raspberry Pi 2 Model B Required root node properties: compatible = "raspberrypi,2-model-b", "brcm,bcm2836"; +Raspberry Pi 3 Model B +Required root node properties: +compatible = "raspberrypi,3-model-b", "brcm,bcm2837"; + Raspberry Pi Compute Module Required root node properties: compatible = "raspberrypi,compute-module", "brcm,bcm2835"; -- cgit v0.10.2 From 9d56c22a78616e79b911f8078e883dac75e513e2 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Tue, 7 Jun 2016 13:05:45 +0200 Subject: ARM: bcm2835: Add devicetree for the Raspberry Pi 3. While this devicetree also works for booting in 32-bit mode, it's placed in arm64 since it's a 64-bit CPU (as suggested by Arnd). Signed-off-by: Eric Anholt Acked-by: Stephen Warren (v1) Signed-off-by: Gerd Hoffmann diff --git a/arch/arm64/boot/dts/broadcom/Makefile b/arch/arm64/boot/dts/broadcom/Makefile index bec1f8b..05faf2a 100644 --- a/arch/arm64/boot/dts/broadcom/Makefile +++ b/arch/arm64/boot/dts/broadcom/Makefile @@ -1,3 +1,4 @@ +dtb-$(CONFIG_ARCH_BCM2835) += bcm2837-rpi-3-b.dtb dtb-$(CONFIG_ARCH_BCM_IPROC) += ns2-svk.dtb dtb-$(CONFIG_ARCH_VULCAN) += vulcan-eval.dtb diff --git a/arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-b.dts b/arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-b.dts new file mode 100644 index 0000000..223793d --- /dev/null +++ b/arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-b.dts @@ -0,0 +1,29 @@ +/dts-v1/; +#include "bcm2837.dtsi" +#include "../../../../arm/boot/dts/bcm2835-rpi.dtsi" + +/ { + compatible = "raspberrypi,3-model-b", "brcm,bcm2837"; + model = "Raspberry Pi 3 Model B"; + + memory { + reg = <0 0x40000000>; + }; + + leds { + act { + gpios = <&gpio 47 0>; + }; + + pwr { + label = "PWR"; + gpios = <&gpio 35 0>; + default-state = "keep"; + linux,default-trigger = "default-on"; + }; + }; +}; + +&uart1 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/broadcom/bcm2837.dtsi b/arch/arm64/boot/dts/broadcom/bcm2837.dtsi new file mode 100644 index 0000000..f2a31d0 --- /dev/null +++ b/arch/arm64/boot/dts/broadcom/bcm2837.dtsi @@ -0,0 +1,76 @@ +#include "../../../../arm/boot/dts/bcm283x.dtsi" + +/ { + compatible = "brcm,bcm2836"; + + soc { + ranges = <0x7e000000 0x3f000000 0x1000000>, + <0x40000000 0x40000000 0x00001000>; + dma-ranges = <0xc0000000 0x00000000 0x3f000000>; + + local_intc: local_intc { + compatible = "brcm,bcm2836-l1-intc"; + reg = <0x40000000 0x100>; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&local_intc>; + }; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupt-parent = <&local_intc>; + interrupts = <0>, // PHYS_SECURE_PPI + <1>, // PHYS_NONSECURE_PPI + <3>, // VIRT_PPI + <2>; // HYP_PPI + always-on; + }; + + cpus: cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0>; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x000000d8>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <1>; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x000000e0>; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <2>; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x000000e8>; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <3>; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x000000f0>; + }; + }; +}; + +/* Make the BCM2835-style global interrupt controller be a child of the + * CPU-local interrupt controller. + */ +&intc { + compatible = "brcm,bcm2836-armctrl-ic"; + reg = <0x7e00b200 0x200>; + interrupt-parent = <&local_intc>; + interrupts = <8>; +}; -- cgit v0.10.2 From 02d08603649816a941246c18252e5c41fd07625a Mon Sep 17 00:00:00 2001 From: Gerd Hoffmann Date: Tue, 7 Jun 2016 13:05:48 +0200 Subject: ARM: bcm2837: dt: Add the ethernet to the device trees Signed-off-by: Gerd Hoffmann Reviewed-by: Eric Anholt diff --git a/arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-b.dts b/arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-b.dts index 223793d..6f47dd2 100644 --- a/arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-b.dts +++ b/arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-b.dts @@ -1,6 +1,7 @@ /dts-v1/; #include "bcm2837.dtsi" #include "../../../../arm/boot/dts/bcm2835-rpi.dtsi" +#include "../../../../arm/boot/dts/bcm283x-rpi-smsc9514.dtsi" / { compatible = "raspberrypi,3-model-b", "brcm,bcm2837"; -- cgit v0.10.2 From e6d66c50b997a0c4035659d8a24a3d510c593cef Mon Sep 17 00:00:00 2001 From: Alison Wang Date: Mon, 9 May 2016 17:06:15 +0800 Subject: arm64: dts: fsl: Update address-cells and reg properties of cpu nodes MPIDR_EL1[63:32] value is equal to 0 for the CPUs of the LS1043A and LS2080A SoCs. The ARM CPU binding allows #address-cells to be set to 1, since MPIDR_EL1[63:32] bits are not used for CPUs identification. Update the #address-cells and reg properties accordingly. Signed-off-by: Alison Wang Signed-off-by: Shawn Guo diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi index de0323b..37614b5 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi @@ -51,7 +51,7 @@ #size-cells = <2>; cpus { - #address-cells = <2>; + #address-cells = <1>; #size-cells = <0>; /* @@ -63,28 +63,28 @@ cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a53"; - reg = <0x0 0x0>; + reg = <0x0>; clocks = <&clockgen 1 0>; }; cpu1: cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a53"; - reg = <0x0 0x1>; + reg = <0x1>; clocks = <&clockgen 1 0>; }; cpu2: cpu@2 { device_type = "cpu"; compatible = "arm,cortex-a53"; - reg = <0x0 0x2>; + reg = <0x2>; clocks = <&clockgen 1 0>; }; cpu3: cpu@3 { device_type = "cpu"; compatible = "arm,cortex-a53"; - reg = <0x0 0x3>; + reg = <0x3>; clocks = <&clockgen 1 0>; }; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi index 3187c82..25ff4a8 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi @@ -51,7 +51,7 @@ #size-cells = <2>; cpus { - #address-cells = <2>; + #address-cells = <1>; #size-cells = <0>; /* @@ -65,56 +65,56 @@ cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a57"; - reg = <0x0 0x0>; + reg = <0x0>; clocks = <&clockgen 1 0>; }; cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a57"; - reg = <0x0 0x1>; + reg = <0x1>; clocks = <&clockgen 1 0>; }; cpu@100 { device_type = "cpu"; compatible = "arm,cortex-a57"; - reg = <0x0 0x100>; + reg = <0x100>; clocks = <&clockgen 1 1>; }; cpu@101 { device_type = "cpu"; compatible = "arm,cortex-a57"; - reg = <0x0 0x101>; + reg = <0x101>; clocks = <&clockgen 1 1>; }; cpu@200 { device_type = "cpu"; compatible = "arm,cortex-a57"; - reg = <0x0 0x200>; + reg = <0x200>; clocks = <&clockgen 1 2>; }; cpu@201 { device_type = "cpu"; compatible = "arm,cortex-a57"; - reg = <0x0 0x201>; + reg = <0x201>; clocks = <&clockgen 1 2>; }; cpu@300 { device_type = "cpu"; compatible = "arm,cortex-a57"; - reg = <0x0 0x300>; + reg = <0x300>; clocks = <&clockgen 1 3>; }; cpu@301 { device_type = "cpu"; compatible = "arm,cortex-a57"; - reg = <0x0 0x301>; + reg = <0x301>; clocks = <&clockgen 1 3>; }; }; -- cgit v0.10.2 From 1cd78dd6bd252547012b16cdc56e7fb55b1800f9 Mon Sep 17 00:00:00 2001 From: Rajesh Bhagat Date: Fri, 10 Jun 2016 11:53:45 +0530 Subject: arm64: dts: ls2080a: Add dis_rxdet_inp3_quirk property to USB3 node Add "dis_rxdet_inp3_quirk" boolean property to USB3 node. This property is used to disable rx detection in P3 PHY mode. Signed-off-by: Rajesh Bhagat Signed-off-by: Shawn Guo diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi index 25ff4a8..e8a48f2 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi @@ -672,6 +672,7 @@ interrupts = <0 80 0x4>; /* Level high type */ dr_mode = "host"; snps,quirk-frame-length-adjustment = <0x20>; + snps,dis_rxdet_inp3_quirk; }; usb1: usb3@3110000 { @@ -681,6 +682,7 @@ interrupts = <0 81 0x4>; /* Level high type */ dr_mode = "host"; snps,quirk-frame-length-adjustment = <0x20>; + snps,dis_rxdet_inp3_quirk; }; ccn@4000000 { -- cgit v0.10.2 From bf26225fc622d96f5ec0f40dca8a809d9685a604 Mon Sep 17 00:00:00 2001 From: Rajesh Bhagat Date: Fri, 10 Jun 2016 11:53:46 +0530 Subject: arm64: dts: ls1043a: Add dis_rxdet_inp3_quirk property to USB3 node Add "dis_rxdet_inp3_quirk" boolean property to USB3 node. This property is used to disable rx detection in P3 PHY mode. Signed-off-by: Rajesh Bhagat Signed-off-by: Shawn Guo diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi index 37614b5..2c6832a 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi @@ -422,6 +422,7 @@ interrupts = <0 60 0x4>; dr_mode = "host"; snps,quirk-frame-length-adjustment = <0x20>; + snps,dis_rxdet_inp3_quirk; }; usb1: usb3@3000000 { @@ -430,6 +431,7 @@ interrupts = <0 61 0x4>; dr_mode = "host"; snps,quirk-frame-length-adjustment = <0x20>; + snps,dis_rxdet_inp3_quirk; }; usb2: usb3@3100000 { @@ -438,6 +440,7 @@ interrupts = <0 63 0x4>; dr_mode = "host"; snps,quirk-frame-length-adjustment = <0x20>; + snps,dis_rxdet_inp3_quirk; }; sata: sata@3200000 { -- cgit v0.10.2 From a9f91b40e2f018f262a80371fdce23413613a444 Mon Sep 17 00:00:00 2001 From: Georgi Djakov Date: Thu, 4 Feb 2016 14:53:22 +0200 Subject: arm64: dts: apq8016-sbc: Add DT node for the uSD SDHC interface Add the necessary properties to enable the SD-card on db410c boards. Signed-off-by: Georgi Djakov Tested-by: Kevin Hilman Signed-off-by: Andy Gross diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi index 205ef89..0550b0b 100644 --- a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi +++ b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi @@ -140,6 +140,18 @@ status = "okay"; }; + sdhci@07864000 { + vmmc-supply = <&pm8916_l11>; + vqmmc-supply = <&pm8916_l12>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; + pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; + + cd-gpios = <&msmgpio 38 0x1>; + status = "okay"; + }; + usb@78d9000 { extcon = <&usb_id>, <&usb_id>; status = "okay"; -- cgit v0.10.2 From 3f452fe71ff6bc5d360f7104c8fae37e942d0e39 Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Tue, 23 Feb 2016 16:50:45 +0000 Subject: arm64: dts: qcom: apq8016-sbc: enable bam dma node. This patch enables bam dma node, dma is used for both tx and rx on spi and on high speed serial. Signed-off-by: Srinivas Kandagatla Signed-off-by: Andy Gross diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi index 0550b0b..18639bc 100644 --- a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi +++ b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi @@ -33,6 +33,10 @@ }; soc { + dma@7884000 { + status = "okay"; + }; + serial@78af000 { label = "LS-UART0"; status = "okay"; -- cgit v0.10.2 From a0df399feec49fb7d5cfef325d082ceefc6e613a Mon Sep 17 00:00:00 2001 From: Lina Iyer Date: Tue, 1 Mar 2016 14:15:30 -0700 Subject: ARM64: dts: Add PSCI cpuidle support for MSM8916 Add device bindings for CPUs to suspend using PSCI as the enable-method. Cc: Signed-off-by: Lina Iyer Tested-by: Andy Gross Signed-off-by: Andy Gross diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index 9681200..3029773 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -62,6 +62,8 @@ compatible = "arm,cortex-a53", "arm,armv8"; reg = <0x0>; next-level-cache = <&L2_0>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SPC>; }; CPU1: cpu@1 { @@ -69,6 +71,8 @@ compatible = "arm,cortex-a53", "arm,armv8"; reg = <0x1>; next-level-cache = <&L2_0>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SPC>; }; CPU2: cpu@2 { @@ -76,6 +80,8 @@ compatible = "arm,cortex-a53", "arm,armv8"; reg = <0x2>; next-level-cache = <&L2_0>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SPC>; }; CPU3: cpu@3 { @@ -83,12 +89,30 @@ compatible = "arm,cortex-a53", "arm,armv8"; reg = <0x3>; next-level-cache = <&L2_0>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SPC>; }; L2_0: l2-cache { compatible = "cache"; cache-level = <2>; }; + + idle-states { + CPU_SPC: spc { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x40000002>; + entry-latency-us = <130>; + exit-latency-us = <150>; + min-residency-us = <2000>; + local-timer-stop; + }; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; }; timer { -- cgit v0.10.2 From 5daa7a6031bd04b7ff94e92ccc1fcb161df12686 Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Tue, 10 May 2016 15:01:49 -0700 Subject: arm64: dts: qcom: Add msm8916 PMU node Add the PMU so we can get proper perf event support on this SoC. Signed-off-by: Stephen Boyd Signed-off-by: Andy Gross diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index 3029773..e3ff3ba 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -115,6 +115,11 @@ method = "smc"; }; + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = ; + }; + timer { compatible = "arm,armv8-timer"; interrupts = , -- cgit v0.10.2 From ea49e164b5956ed39150be8ae7e85dd8662d0723 Mon Sep 17 00:00:00 2001 From: Andy Gross Date: Fri, 3 Jun 2016 18:25:28 -0500 Subject: arm64: dts: msm8916: Add SCM firmware node This adds the devicetree node for the SCM firmware. Acked-by: Bjorn Andersson Signed-off-by: Andy Gross Reviewed-by: Stephen Boyd diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index e3ff3ba..4c9c300 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -151,6 +151,14 @@ hwlocks = <&tcsr_mutex 3>; }; + firmware { + scm { + compatible = "qcom,scm"; + clocks = <&gcc GCC_CRYPTO_CLK>, <&gcc GCC_CRYPTO_AXI_CLK>, <&gcc GCC_CRYPTO_AHB_CLK>; + clock-names = "core", "bus", "iface"; + }; + }; + soc: soc { #address-cells = <1>; #size-cells = <1>; -- cgit v0.10.2 From 7258e10e6a0b37fee2f8c310de70d07941a440fe Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Mon, 6 Jun 2016 17:57:24 -0700 Subject: ARM: dts: msm8916: Update reserved-memory Update reserved-memory in accordance with memory the detailed memory map for 8916, so that we will be able to reference the firmware memory regions. Signed-off-by: Bjorn Andersson Signed-off-by: Andy Gross diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index 4c9c300..11bdc24 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -42,13 +42,48 @@ #size-cells = <2>; ranges; - reserve_aligned@86000000 { - reg = <0x0 0x86000000 0x0 0x0300000>; + tz-apps@86000000 { + reg = <0x0 0x86000000 0x0 0x300000>; no-map; }; smem_mem: smem_region@86300000 { - reg = <0x0 0x86300000 0x0 0x0100000>; + reg = <0x0 0x86300000 0x0 0x100000>; + no-map; + }; + + hypervisor@86400000 { + reg = <0x0 0x86400000 0x0 0x100000>; + no-map; + }; + + tz@86500000 { + reg = <0x0 0x86500000 0x0 0x180000>; + no-map; + }; + + reserved@8668000 { + reg = <0x0 0x86680000 0x0 0x80000>; + no-map; + }; + + rmtfs@86700000 { + reg = <0x0 0x86700000 0x0 0xe0000>; + no-map; + }; + + rfsa@867e00000 { + reg = <0x0 0x867e0000 0x0 0x20000>; + no-map; + }; + + mpss@86800000 { + reg = <0x0 0x86800000 0x0 0x2b00000>; + no-map; + }; + + wcnss@89300000 { + reg = <0x0 0x89300000 0x0 0x600000>; no-map; }; }; -- cgit v0.10.2 From ed6cca5f9a69cba9468ed1c467009bb12bc90287 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Tue, 14 Jun 2016 12:01:41 +0900 Subject: arm64: dts: uniphier: add SoC-Glue node to UniPhier 64bit SoCs This node consists of various system-level configuration registers. Signed-off-by: Masahiro Yamada Signed-off-by: Olof Johansson diff --git a/arch/arm64/boot/dts/socionext/uniphier-ph1-ld20.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ph1-ld20.dtsi index 9532880..31dc51b 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-ph1-ld20.dtsi +++ b/arch/arm64/boot/dts/socionext/uniphier-ph1-ld20.dtsi @@ -264,9 +264,13 @@ reg = <0x59801000 0x400>; }; - pinctrl: pinctrl@5f801000 { - compatible = "socionext,ph1-ld20-pinctrl", "syscon"; - reg = <0x5f801000 0xe00>; + soc-glue@5f800000 { + compatible = "simple-mfd", "syscon"; + reg = <0x5f800000 0x2000>; + + pinctrl: pinctrl { + compatible = "socionext,uniphier-ld20-pinctrl"; + }; }; gic: interrupt-controller@5fe00000 { -- cgit v0.10.2 From 1388ea2a8df4ee4c21632a048d575fa7492a8156 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Tue, 14 Jun 2016 12:01:42 +0900 Subject: arm64: dts: uniphier: change cpu-release-address At first, 256 byte of the head of DRAM space was reserved for some reasons. However, as the progress of development, it turned out unnecessary, and it was never used in the end. Move the CPU release address to leave no space. Signed-off-by: Masahiro Yamada Signed-off-by: Olof Johansson diff --git a/arch/arm64/boot/dts/socionext/uniphier-ph1-ld20.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ph1-ld20.dtsi index 31dc51b..644025c 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-ph1-ld20.dtsi +++ b/arch/arm64/boot/dts/socionext/uniphier-ph1-ld20.dtsi @@ -77,7 +77,7 @@ compatible = "arm,cortex-a72", "arm,armv8"; reg = <0 0x000>; enable-method = "spin-table"; - cpu-release-addr = <0 0x80000100>; + cpu-release-addr = <0 0x80000000>; }; cpu1: cpu@1 { @@ -85,7 +85,7 @@ compatible = "arm,cortex-a72", "arm,armv8"; reg = <0 0x001>; enable-method = "spin-table"; - cpu-release-addr = <0 0x80000100>; + cpu-release-addr = <0 0x80000000>; }; cpu2: cpu@100 { @@ -93,7 +93,7 @@ compatible = "arm,cortex-a53", "arm,armv8"; reg = <0 0x100>; enable-method = "spin-table"; - cpu-release-addr = <0 0x80000100>; + cpu-release-addr = <0 0x80000000>; }; cpu3: cpu@101 { @@ -101,7 +101,7 @@ compatible = "arm,cortex-a53", "arm,armv8"; reg = <0 0x101>; enable-method = "spin-table"; - cpu-release-addr = <0 0x80000100>; + cpu-release-addr = <0 0x80000000>; }; }; -- cgit v0.10.2 From ffd8a5ed578b6d6b2ee91febf38d6822cd229e99 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Tue, 14 Jun 2016 12:01:43 +0900 Subject: arm64: dts: uniphier: add /memreserve/ for spin-table release address As Documentation/arm64/booting.txt says, the cpu-release-addr location should be reserved. Signed-off-by: Masahiro Yamada Acked-by: Mark Rutland Signed-off-by: Olof Johansson diff --git a/arch/arm64/boot/dts/socionext/uniphier-ph1-ld20.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ph1-ld20.dtsi index 644025c..c223915 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-ph1-ld20.dtsi +++ b/arch/arm64/boot/dts/socionext/uniphier-ph1-ld20.dtsi @@ -42,6 +42,8 @@ * OTHER DEALINGS IN THE SOFTWARE. */ +/memreserve/ 0x80000000 0x00000008; /* cpu-release-addr */ + / { compatible = "socionext,ph1-ld20"; #address-cells = <2>; -- cgit v0.10.2 From b1ec5b5a93dac0b301a54706573348ed7d9bd7f6 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Wed, 15 Jun 2016 12:01:45 +0200 Subject: dt-bindings: hwrng: Add Amlogic Meson Hardware Random Generator bindings Acked-by: Rob Herring Signed-off-by: Neil Armstrong Signed-off-by: Kevin Hilman diff --git a/Documentation/devicetree/bindings/rng/amlogic,meson-rng.txt b/Documentation/devicetree/bindings/rng/amlogic,meson-rng.txt new file mode 100644 index 0000000..202f2d0 --- /dev/null +++ b/Documentation/devicetree/bindings/rng/amlogic,meson-rng.txt @@ -0,0 +1,14 @@ +Amlogic Meson Random number generator +===================================== + +Required properties: + +- compatible : should be "amlogic,meson-rng" +- reg : Specifies base physical address and size of the registers. + +Example: + +rng { + compatible = "amlogic,meson-rng"; + reg = <0x0 0xc8834000 0x0 0x4>; +}; -- cgit v0.10.2 From 4b7bed38528581796a988f67e168fb2f50cfd969 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Wed, 15 Jun 2016 12:01:46 +0200 Subject: ARM64: dts: meson-gxbb: Add Hardware Random Generator node Signed-off-by: Neil Armstrong Signed-off-by: Kevin Hilman diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi index 063e3b6..806b903 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi @@ -221,6 +221,11 @@ #size-cells = <2>; ranges = <0x0 0x0 0x0 0xc8834000 0x0 0x2000>; + rng { + compatible = "amlogic,meson-rng"; + reg = <0x0 0x0 0x0 0x4>; + }; + pinctrl_periphs: pinctrl@4b0 { compatible = "amlogic,meson-gxbb-periphs-pinctrl"; #address-cells = <2>; -- cgit v0.10.2 From 2f082b13f2ef89548d5629d9bbf8795ed246a0ec Mon Sep 17 00:00:00 2001 From: Liu Gang Date: Tue, 7 Jun 2016 14:55:45 +0800 Subject: bindings: PCI: layerscape: Add 'dma-coherent' property Add 'dma-coherent' description for PCI nodes. The 'dma-coherent' indicates that the hardware IP block can ensure the coherency of the data transferred from/to the IP block. This can avoid the software cache flush/invalid actions, and improve the performance significantly. The PCI IP block of ls1043a has this capability, so adding this feature to improve the PCI performance. Signed-off-by: Liu Gang Acked-by: Rob Herring Signed-off-by: Shawn Guo diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt b/Documentation/devicetree/bindings/pci/layerscape-pci.txt index ef683b2..41e9f55 100644 --- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt +++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt @@ -24,6 +24,9 @@ Required properties: The first entry must be a link to the SCFG device node The second entry must be '0' or '1' based on physical PCIe controller index. This is used to get SCFG PEXN registers +- dma-coherent: Indicates that the hardware IP block can ensure the coherency + of the data transferred from/to the IP block. This can avoid the software + cache flush/invalid actions, and improve the performance significantly. Example: @@ -38,6 +41,7 @@ Example: #address-cells = <3>; #size-cells = <2>; device_type = "pci"; + dma-coherent; num-lanes = <4>; bus-range = <0x0 0xff>; ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */ -- cgit v0.10.2 From f8ed1d9b0f6758db7e2b65b6e88f8a923a3a22ab Mon Sep 17 00:00:00 2001 From: Liu Gang Date: Tue, 7 Jun 2016 14:55:46 +0800 Subject: arm64: dts: ls1043a: Add 'dma-coherent' for ls1043a PCI nodes The 'dma-coherent' indicates that the hardware IP block can ensure the coherency of the data transferred from/to the IP block. This can avoid the software cache flush/invalid actions, and improve the performance significantly. The PCI IP block of ls1043a has this capability, so adding this feature to improve the PCI performance. Signed-off-by: Liu Gang Signed-off-by: Shawn Guo diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi index 2c6832a..c451b81 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi @@ -482,6 +482,7 @@ #address-cells = <3>; #size-cells = <2>; device_type = "pci"; + dma-coherent; num-lanes = <4>; bus-range = <0x0 0xff>; ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */ @@ -506,6 +507,7 @@ #address-cells = <3>; #size-cells = <2>; device_type = "pci"; + dma-coherent; num-lanes = <2>; bus-range = <0x0 0xff>; ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */ @@ -530,6 +532,7 @@ #address-cells = <3>; #size-cells = <2>; device_type = "pci"; + dma-coherent; num-lanes = <2>; bus-range = <0x0 0xff>; ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */ -- cgit v0.10.2 From 69e5a8fe8c54e8d1579f1927ca8c30abeee8862d Mon Sep 17 00:00:00 2001 From: David Wu Date: Mon, 16 May 2016 13:09:31 -0700 Subject: arm64: dts: rockchip: add i2c nodes for rk3399 We've got 9 (count em!) i2c controllers on rk3399, some of which are in the PMU power domain and some of which are normal peripherals. Add them all to the main rk3399 dtsi file so future patches can turn them on in the board dts files. Note: by default we try to set the i2c clock rate to 200 MHz so that we can achieve good i2c functional clock rates. 200 MHz gives us the ability to make very close to 100 kHz / 400 kHz / 1 MHz rates. If boards want to tune clock rates further they can always override. Possibly boards could want to tune this if: - they wanted to save an infinitesimal amount of power and they knew their i2c bus was slow anyway. Since we gate the functional clock when the i2c bus is not active, power savings would only be while i2c transfers were happening and probably won't be very big anyway. - they wanted to eek out a bit more speed by carefully tuning the source clock to make divisions work out perfectly, accounting for the rise / fall time measured on an actual board. Note also that we still request 200 MHz for the PMU i2c busses even though we expect that we won't make that exactly (currently PPLL is 676 MHz which gives us 169 MHz). Signed-off-by: David Wu Signed-off-by: Jianqun Xu [dianders: wrote desc; put in assigned-clocks; reordered nodes] Signed-off-by: Douglas Anderson Signed-off-by: Heiko Stuebner diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index a4383f3..ef472e2 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -55,6 +55,15 @@ #size-cells = <2>; aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; + i2c6 = &i2c6; + i2c7 = &i2c7; + i2c8 = &i2c8; serial0 = &uart0; serial1 = &uart1; serial2 = &uart2; @@ -286,6 +295,96 @@ }; }; + i2c1: i2c@ff110000 { + compatible = "rockchip,rk3399-i2c"; + reg = <0x0 0xff110000 0x0 0x1000>; + assigned-clocks = <&cru SCLK_I2C1>; + assigned-clock-rates = <200000000>; + clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; + clock-names = "i2c", "pclk"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_xfer>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@ff120000 { + compatible = "rockchip,rk3399-i2c"; + reg = <0x0 0xff120000 0x0 0x1000>; + assigned-clocks = <&cru SCLK_I2C2>; + assigned-clock-rates = <200000000>; + clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; + clock-names = "i2c", "pclk"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_xfer>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@ff130000 { + compatible = "rockchip,rk3399-i2c"; + reg = <0x0 0xff130000 0x0 0x1000>; + assigned-clocks = <&cru SCLK_I2C3>; + assigned-clock-rates = <200000000>; + clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; + clock-names = "i2c", "pclk"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_xfer>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c5: i2c@ff140000 { + compatible = "rockchip,rk3399-i2c"; + reg = <0x0 0xff140000 0x0 0x1000>; + assigned-clocks = <&cru SCLK_I2C5>; + assigned-clock-rates = <200000000>; + clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>; + clock-names = "i2c", "pclk"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&i2c5_xfer>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c6: i2c@ff150000 { + compatible = "rockchip,rk3399-i2c"; + reg = <0x0 0xff150000 0x0 0x1000>; + assigned-clocks = <&cru SCLK_I2C6>; + assigned-clock-rates = <200000000>; + clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>; + clock-names = "i2c", "pclk"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&i2c6_xfer>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c7: i2c@ff160000 { + compatible = "rockchip,rk3399-i2c"; + reg = <0x0 0xff160000 0x0 0x1000>; + assigned-clocks = <&cru SCLK_I2C7>; + assigned-clock-rates = <200000000>; + clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>; + clock-names = "i2c", "pclk"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&i2c7_xfer>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + uart0: serial@ff180000 { compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; reg = <0x0 0xff180000 0x0 0x100>; @@ -530,6 +629,51 @@ status = "disabled"; }; + i2c0: i2c@ff3c0000 { + compatible = "rockchip,rk3399-i2c"; + reg = <0x0 0xff3c0000 0x0 0x1000>; + assigned-clocks = <&pmucru SCLK_I2C0_PMU>; + assigned-clock-rates = <200000000>; + clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>; + clock-names = "i2c", "pclk"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_xfer>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c4: i2c@ff3d0000 { + compatible = "rockchip,rk3399-i2c"; + reg = <0x0 0xff3d0000 0x0 0x1000>; + assigned-clocks = <&pmucru SCLK_I2C4_PMU>; + assigned-clock-rates = <200000000>; + clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>; + clock-names = "i2c", "pclk"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_xfer>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c8: i2c@ff3e0000 { + compatible = "rockchip,rk3399-i2c"; + reg = <0x0 0xff3e0000 0x0 0x1000>; + assigned-clocks = <&pmucru SCLK_I2C8_PMU>; + assigned-clock-rates = <200000000>; + clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>; + clock-names = "i2c", "pclk"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&i2c8_xfer>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + pwm0: pwm@ff420000 { compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; reg = <0x0 0xff420000 0x0 0x10>; -- cgit v0.10.2 From ad1cfdf518976447e6b0d31517bad4e3ebbce6bb Mon Sep 17 00:00:00 2001 From: Caesar Wang Date: Wed, 18 May 2016 22:41:50 +0800 Subject: arm64: dts: rockchip: fixes the gic400 2nd region size for rk3368 The 2nd additional region is the GIC virtual cpu interface register base and size. As the gic400 of rk3368 says, the cpu interface register map as below : -0x0000 GICC_CTRL . . . -0x00fc GICC_IIDR -0x1000 GICC_IDR Obviously, the region size should be greater than 0x1000. So we should make sure to include the GICC_IDR since the kernel will access it in some cases. Fixes: b790c2cab5ca ("arm64: dts: add Rockchip rk3368 core dtsi and board dts for the r88 board") Signed-off-by: Caesar Wang Reviewed-by: Shawn Lin Cc: stable@vger.kernel.org [added Fixes and stable-cc] Signed-off-by: Heiko Stuebner diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi b/arch/arm64/boot/dts/rockchip/rk3368.dtsi index 58c2585..d02a9003 100644 --- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi @@ -680,7 +680,7 @@ #address-cells = <0>; reg = <0x0 0xffb71000 0x0 0x1000>, - <0x0 0xffb72000 0x0 0x1000>, + <0x0 0xffb72000 0x0 0x2000>, <0x0 0xffb74000 0x0 0x2000>, <0x0 0xffb76000 0x0 0x2000>; interrupts = Date: Tue, 14 Jun 2016 08:00:20 -0500 Subject: arm64: dts: apm: Use lowercase consistently for hex constants The convention in these files is to use lowercase for "0x" prefixes and for the hex constants themselves, but a few changes didn't follow that convention, which makes the file annoying to read. Use lowercase consistently for the hex constants. No functional change intended. Signed-off-by: Bjorn Helgaas Acked-by: Rob Herring Signed-off-by: Duc Dang diff --git a/Documentation/devicetree/bindings/net/apm-xgene-enet.txt b/Documentation/devicetree/bindings/net/apm-xgene-enet.txt index 05f705e3..e41b2d5 100644 --- a/Documentation/devicetree/bindings/net/apm-xgene-enet.txt +++ b/Documentation/devicetree/bindings/net/apm-xgene-enet.txt @@ -59,8 +59,8 @@ Example: compatible = "apm,xgene-enet"; status = "disabled"; reg = <0x0 0x17020000 0x0 0xd100>, - <0x0 0X17030000 0x0 0X400>, - <0x0 0X10000000 0x0 0X200>; + <0x0 0x17030000 0x0 0x400>, + <0x0 0x10000000 0x0 0x200>; reg-names = "enet_csr", "ring_csr", "ring_cmd"; interrupts = <0x0 0x3c 0x4>; port-id = <0>; diff --git a/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi b/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi index c569f76..9773687 100644 --- a/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi +++ b/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi @@ -106,9 +106,9 @@ interrupts = <1 9 0xf04>; /* GIC Maintenence IRQ */ ranges = <0 0 0 0x79000000 0x0 0x800000>; /* MSI Range */ reg = <0x0 0x78090000 0x0 0x10000>, /* GIC Dist */ - <0x0 0x780A0000 0x0 0x20000>, /* GIC CPU */ - <0x0 0x780C0000 0x0 0x10000>, /* GIC VCPU Control */ - <0x0 0x780E0000 0x0 0x20000>; /* GIC VCPU */ + <0x0 0x780a0000 0x0 0x20000>, /* GIC CPU */ + <0x0 0x780c0000 0x0 0x10000>, /* GIC VCPU Control */ + <0x0 0x780e0000 0x0 0x20000>; /* GIC VCPU */ v2m0: v2m@0x00000 { compatible = "arm,gic-v2m-frame"; msi-controller; @@ -159,35 +159,35 @@ msi-controller; reg = <0x0 0x90000 0x0 0x1000>; }; - v2m10: v2m@0xA0000 { + v2m10: v2m@0xa0000 { compatible = "arm,gic-v2m-frame"; msi-controller; - reg = <0x0 0xA0000 0x0 0x1000>; + reg = <0x0 0xa0000 0x0 0x1000>; }; - v2m11: v2m@0xB0000 { + v2m11: v2m@0xb0000 { compatible = "arm,gic-v2m-frame"; msi-controller; - reg = <0x0 0xB0000 0x0 0x1000>; + reg = <0x0 0xb0000 0x0 0x1000>; }; - v2m12: v2m@0xC0000 { + v2m12: v2m@0xc0000 { compatible = "arm,gic-v2m-frame"; msi-controller; - reg = <0x0 0xC0000 0x0 0x1000>; + reg = <0x0 0xc0000 0x0 0x1000>; }; - v2m13: v2m@0xD0000 { + v2m13: v2m@0xd0000 { compatible = "arm,gic-v2m-frame"; msi-controller; - reg = <0x0 0xD0000 0x0 0x1000>; + reg = <0x0 0xd0000 0x0 0x1000>; }; - v2m14: v2m@0xE0000 { + v2m14: v2m@0xe0000 { compatible = "arm,gic-v2m-frame"; msi-controller; - reg = <0x0 0xE0000 0x0 0x1000>; + reg = <0x0 0xe0000 0x0 0x1000>; }; - v2m15: v2m@0xF0000 { + v2m15: v2m@0xf0000 { compatible = "arm,gic-v2m-frame"; msi-controller; - reg = <0x0 0xF0000 0x0 0x1000>; + reg = <0x0 0xf0000 0x0 0x1000>; }; }; @@ -629,8 +629,8 @@ compatible = "apm,xgene2-sgenet"; status = "disabled"; reg = <0x0 0x1f610000 0x0 0x10000>, - <0x0 0x1f600000 0x0 0Xd100>, - <0x0 0x20000000 0x0 0X20000>; + <0x0 0x1f600000 0x0 0xd100>, + <0x0 0x20000000 0x0 0x20000>; interrupts = <0 96 4>, <0 97 4>; dma-coherent; @@ -643,8 +643,8 @@ compatible = "apm,xgene2-xgenet"; status = "disabled"; reg = <0x0 0x1f620000 0x0 0x10000>, - <0x0 0x1f600000 0x0 0Xd100>, - <0x0 0x20000000 0x0 0X220000>; + <0x0 0x1f600000 0x0 0xd100>, + <0x0 0x20000000 0x0 0x220000>; interrupts = <0 108 4>, <0 109 4>, <0 110 4>, @@ -684,7 +684,7 @@ #size-cells = <0>; compatible = "snps,designware-i2c"; reg = <0x0 0x10640000 0x0 0x1000>; - interrupts = <0 0x3A 0x4>; + interrupts = <0 0x3a 0x4>; clocks = <&i2c4clk 0>; bus_num = <4>; }; diff --git a/arch/arm64/boot/dts/apm/apm-storm.dtsi b/arch/arm64/boot/dts/apm/apm-storm.dtsi index 5147d76..e0e8d2a 100644 --- a/arch/arm64/boot/dts/apm/apm-storm.dtsi +++ b/arch/arm64/boot/dts/apm/apm-storm.dtsi @@ -204,7 +204,7 @@ #clock-cells = <1>; clocks = <&socplldiv2 0>; clock-names = "qmlclk"; - reg = <0x0 0x1703C000 0x0 0x1000>; + reg = <0x0 0x1703c000 0x0 0x1000>; reg-names = "csr-reg"; clock-output-names = "qmlclk"; }; @@ -226,7 +226,7 @@ compatible = "apm,xgene-device-clock"; #clock-cells = <1>; clocks = <ðclk 0>; - reg = <0x0 0x1702C000 0x0 0x1000>; + reg = <0x0 0x1702c000 0x0 0x1000>; reg-names = "csr-reg"; clock-output-names = "menetclk"; }; @@ -925,8 +925,8 @@ compatible = "apm,xgene-enet"; status = "disabled"; reg = <0x0 0x17020000 0x0 0xd100>, - <0x0 0X17030000 0x0 0Xc300>, - <0x0 0X10000000 0x0 0X200>; + <0x0 0x17030000 0x0 0xc300>, + <0x0 0x10000000 0x0 0x200>; reg-names = "enet_csr", "ring_csr", "ring_cmd"; interrupts = <0x0 0x3c 0x4>; dma-coherent; @@ -951,11 +951,11 @@ compatible = "apm,xgene1-sgenet"; status = "disabled"; reg = <0x0 0x1f210000 0x0 0xd100>, - <0x0 0x1f200000 0x0 0Xc300>, - <0x0 0x1B000000 0x0 0X200>; + <0x0 0x1f200000 0x0 0xc300>, + <0x0 0x1b000000 0x0 0x200>; reg-names = "enet_csr", "ring_csr", "ring_cmd"; - interrupts = <0x0 0xA0 0x4>, - <0x0 0xA1 0x4>; + interrupts = <0x0 0xa0 0x4>, + <0x0 0xa1 0x4>; dma-coherent; clocks = <&sge0clk 0>; local-mac-address = [00 00 00 00 00 00]; @@ -966,11 +966,11 @@ compatible = "apm,xgene1-sgenet"; status = "disabled"; reg = <0x0 0x1f210030 0x0 0xd100>, - <0x0 0x1f200000 0x0 0Xc300>, - <0x0 0x1B000000 0x0 0X8000>; + <0x0 0x1f200000 0x0 0xc300>, + <0x0 0x1b000000 0x0 0x8000>; reg-names = "enet_csr", "ring_csr", "ring_cmd"; - interrupts = <0x0 0xAC 0x4>, - <0x0 0xAD 0x4>; + interrupts = <0x0 0xac 0x4>, + <0x0 0xad 0x4>; port-id = <1>; dma-coherent; clocks = <&sge1clk 0>; @@ -982,8 +982,8 @@ compatible = "apm,xgene1-xgenet"; status = "disabled"; reg = <0x0 0x1f610000 0x0 0xd100>, - <0x0 0x1f600000 0x0 0Xc300>, - <0x0 0x18000000 0x0 0X200>; + <0x0 0x1f600000 0x0 0xc300>, + <0x0 0x18000000 0x0 0x200>; reg-names = "enet_csr", "ring_csr", "ring_cmd"; interrupts = <0x0 0x60 0x4>, <0x0 0x61 0x4>, @@ -1005,11 +1005,11 @@ compatible = "apm,xgene1-xgenet"; status = "disabled"; reg = <0x0 0x1f620000 0x0 0xd100>, - <0x0 0x1f600000 0x0 0Xc300>, - <0x0 0x18000000 0x0 0X8000>; + <0x0 0x1f600000 0x0 0xc300>, + <0x0 0x18000000 0x0 0x8000>; reg-names = "enet_csr", "ring_csr", "ring_cmd"; - interrupts = <0x0 0x6C 0x4>, - <0x0 0x6D 0x4>; + interrupts = <0x0 0x6c 0x4>, + <0x0 0x6d 0x4>; port-id = <1>; dma-coherent; clocks = <&xge1clk 0>; -- cgit v0.10.2 From 0e999c79c0a0128abcdbf58b4d0802ad4410bfb9 Mon Sep 17 00:00:00 2001 From: Bjorn Helgaas Date: Tue, 14 Jun 2016 08:00:30 -0500 Subject: arm64: dts: apm: Remove leading '0x' from unit addresses Unit addresses should not have a leading '0x'. Remove them. Signed-off-by: Bjorn Helgaas Acked-by: Rob Herring Signed-off-by: Duc Dang diff --git a/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi b/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi index 9773687..e5ced2a 100644 --- a/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi +++ b/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi @@ -109,82 +109,82 @@ <0x0 0x780a0000 0x0 0x20000>, /* GIC CPU */ <0x0 0x780c0000 0x0 0x10000>, /* GIC VCPU Control */ <0x0 0x780e0000 0x0 0x20000>; /* GIC VCPU */ - v2m0: v2m@0x00000 { + v2m0: v2m@00000 { compatible = "arm,gic-v2m-frame"; msi-controller; reg = <0x0 0x0 0x0 0x1000>; }; - v2m1: v2m@0x10000 { + v2m1: v2m@10000 { compatible = "arm,gic-v2m-frame"; msi-controller; reg = <0x0 0x10000 0x0 0x1000>; }; - v2m2: v2m@0x20000 { + v2m2: v2m@20000 { compatible = "arm,gic-v2m-frame"; msi-controller; reg = <0x0 0x20000 0x0 0x1000>; }; - v2m3: v2m@0x30000 { + v2m3: v2m@30000 { compatible = "arm,gic-v2m-frame"; msi-controller; reg = <0x0 0x30000 0x0 0x1000>; }; - v2m4: v2m@0x40000 { + v2m4: v2m@40000 { compatible = "arm,gic-v2m-frame"; msi-controller; reg = <0x0 0x40000 0x0 0x1000>; }; - v2m5: v2m@0x50000 { + v2m5: v2m@50000 { compatible = "arm,gic-v2m-frame"; msi-controller; reg = <0x0 0x50000 0x0 0x1000>; }; - v2m6: v2m@0x60000 { + v2m6: v2m@60000 { compatible = "arm,gic-v2m-frame"; msi-controller; reg = <0x0 0x60000 0x0 0x1000>; }; - v2m7: v2m@0x70000 { + v2m7: v2m@70000 { compatible = "arm,gic-v2m-frame"; msi-controller; reg = <0x0 0x70000 0x0 0x1000>; }; - v2m8: v2m@0x80000 { + v2m8: v2m@80000 { compatible = "arm,gic-v2m-frame"; msi-controller; reg = <0x0 0x80000 0x0 0x1000>; }; - v2m9: v2m@0x90000 { + v2m9: v2m@90000 { compatible = "arm,gic-v2m-frame"; msi-controller; reg = <0x0 0x90000 0x0 0x1000>; }; - v2m10: v2m@0xa0000 { + v2m10: v2m@a0000 { compatible = "arm,gic-v2m-frame"; msi-controller; reg = <0x0 0xa0000 0x0 0x1000>; }; - v2m11: v2m@0xb0000 { + v2m11: v2m@b0000 { compatible = "arm,gic-v2m-frame"; msi-controller; reg = <0x0 0xb0000 0x0 0x1000>; }; - v2m12: v2m@0xc0000 { + v2m12: v2m@c0000 { compatible = "arm,gic-v2m-frame"; msi-controller; reg = <0x0 0xc0000 0x0 0x1000>; }; - v2m13: v2m@0xd0000 { + v2m13: v2m@d0000 { compatible = "arm,gic-v2m-frame"; msi-controller; reg = <0x0 0xd0000 0x0 0x1000>; }; - v2m14: v2m@0xe0000 { + v2m14: v2m@e0000 { compatible = "arm,gic-v2m-frame"; msi-controller; reg = <0x0 0xe0000 0x0 0x1000>; }; - v2m15: v2m@0xf0000 { + v2m15: v2m@f0000 { compatible = "arm,gic-v2m-frame"; msi-controller; reg = <0x0 0xf0000 0x0 0x1000>; -- cgit v0.10.2 From f0a78909bd6fc48c50d6557bac95a589d2f987d4 Mon Sep 17 00:00:00 2001 From: Duc Dang Date: Mon, 20 Jun 2016 18:26:35 -0700 Subject: arm64: dts: apm: Fix timer interrupt polarity for X-Gene 2 SoC Correct X-Gene 2 timer interrupt polarity as low-level triggered. Signed-off-by: Duc Dang diff --git a/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi b/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi index e5ced2a..21028b1 100644 --- a/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi +++ b/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi @@ -198,10 +198,10 @@ timer { compatible = "arm,armv8-timer"; - interrupts = <1 0 0xff04>, /* Secure Phys IRQ */ - <1 13 0xff04>, /* Non-secure Phys IRQ */ - <1 14 0xff04>, /* Virt IRQ */ - <1 15 0xff04>; /* Hyp IRQ */ + interrupts = <1 0 0xff08>, /* Secure Phys IRQ */ + <1 13 0xff08>, /* Non-secure Phys IRQ */ + <1 14 0xff08>, /* Virt IRQ */ + <1 15 0xff08>; /* Hyp IRQ */ clock-frequency = <50000000>; }; -- cgit v0.10.2 From ddbc71d96012fbcc4b9e42fd1c131f185875f73f Mon Sep 17 00:00:00 2001 From: Duc Dang Date: Mon, 20 Jun 2016 18:41:49 -0700 Subject: arm64: dts: apm: Remove unused qmlclk node on X-Gene 1 Node qmlclk has no consumer, so remove it. Signed-off-by: Duc Dang diff --git a/arch/arm64/boot/dts/apm/apm-storm.dtsi b/arch/arm64/boot/dts/apm/apm-storm.dtsi index e0e8d2a..91c73b8 100644 --- a/arch/arm64/boot/dts/apm/apm-storm.dtsi +++ b/arch/arm64/boot/dts/apm/apm-storm.dtsi @@ -199,16 +199,6 @@ clock-output-names = "sdioclk"; }; - qmlclk: qmlclk { - compatible = "apm,xgene-device-clock"; - #clock-cells = <1>; - clocks = <&socplldiv2 0>; - clock-names = "qmlclk"; - reg = <0x0 0x1703c000 0x0 0x1000>; - reg-names = "csr-reg"; - clock-output-names = "qmlclk"; - }; - ethclk: ethclk { compatible = "apm,xgene-device-clock"; #clock-cells = <1>; -- cgit v0.10.2 From ec049f334872e98332dcf044943f3fa7cea742ee Mon Sep 17 00:00:00 2001 From: Li Yang Date: Thu, 16 Jun 2016 18:35:03 -0500 Subject: arm64: dts: ls1043a: Add cache nodes for cacheinfo support Adds the cache nodes and next-level-cache property for the cacheinfo to work. Signed-off-by: Li Yang Signed-off-by: Shawn Guo diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi index c451b81..19572d8 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi @@ -65,6 +65,7 @@ compatible = "arm,cortex-a53"; reg = <0x0>; clocks = <&clockgen 1 0>; + next-level-cache = <&l2>; }; cpu1: cpu@1 { @@ -72,6 +73,7 @@ compatible = "arm,cortex-a53"; reg = <0x1>; clocks = <&clockgen 1 0>; + next-level-cache = <&l2>; }; cpu2: cpu@2 { @@ -79,6 +81,7 @@ compatible = "arm,cortex-a53"; reg = <0x2>; clocks = <&clockgen 1 0>; + next-level-cache = <&l2>; }; cpu3: cpu@3 { @@ -86,6 +89,11 @@ compatible = "arm,cortex-a53"; reg = <0x3>; clocks = <&clockgen 1 0>; + next-level-cache = <&l2>; + }; + + l2: l2-cache { + compatible = "cache"; }; }; -- cgit v0.10.2 From 2983e625bf2af422a6f55febb784fe34df834322 Mon Sep 17 00:00:00 2001 From: Li Yang Date: Thu, 16 Jun 2016 18:35:04 -0500 Subject: arm64: dts: ls2080a: Add cache nodes for cacheinfo support Adds the cache nodes and next-level-cache property for the cacheinfo to work. Signed-off-by: Li Yang Signed-off-by: Shawn Guo diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi index e8a48f2..21023a3 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi @@ -67,6 +67,7 @@ compatible = "arm,cortex-a57"; reg = <0x0>; clocks = <&clockgen 1 0>; + next-level-cache = <&cluster0_l2>; }; cpu@1 { @@ -74,6 +75,7 @@ compatible = "arm,cortex-a57"; reg = <0x1>; clocks = <&clockgen 1 0>; + next-level-cache = <&cluster0_l2>; }; cpu@100 { @@ -81,6 +83,7 @@ compatible = "arm,cortex-a57"; reg = <0x100>; clocks = <&clockgen 1 1>; + next-level-cache = <&cluster1_l2>; }; cpu@101 { @@ -88,6 +91,7 @@ compatible = "arm,cortex-a57"; reg = <0x101>; clocks = <&clockgen 1 1>; + next-level-cache = <&cluster1_l2>; }; cpu@200 { @@ -95,6 +99,7 @@ compatible = "arm,cortex-a57"; reg = <0x200>; clocks = <&clockgen 1 2>; + next-level-cache = <&cluster2_l2>; }; cpu@201 { @@ -102,6 +107,7 @@ compatible = "arm,cortex-a57"; reg = <0x201>; clocks = <&clockgen 1 2>; + next-level-cache = <&cluster2_l2>; }; cpu@300 { @@ -109,6 +115,7 @@ compatible = "arm,cortex-a57"; reg = <0x300>; clocks = <&clockgen 1 3>; + next-level-cache = <&cluster3_l2>; }; cpu@301 { @@ -116,6 +123,23 @@ compatible = "arm,cortex-a57"; reg = <0x301>; clocks = <&clockgen 1 3>; + next-level-cache = <&cluster3_l2>; + }; + + cluster0_l2: l2-cache0 { + compatible = "cache"; + }; + + cluster1_l2: l2-cache1 { + compatible = "cache"; + }; + + cluster2_l2: l2-cache2 { + compatible = "cache"; + }; + + cluster3_l2: l2-cache3 { + compatible = "cache"; }; }; -- cgit v0.10.2 From 3e287cf6ef954947365a4aca6580ea1d6bee3a18 Mon Sep 17 00:00:00 2001 From: Sudeep Holla Date: Thu, 2 Jun 2016 10:18:41 +0100 Subject: arm64: dts: juno: add coresight support Most of the debug-related components on Juno are located in the coreSight subsystem while others are located in the Cortex-Axx clusters, the SCP subsystem, and in the main system. Each core in the two processor clusters contain an Embedded Trace Macrocell(ETM) which generates real-time trace information that trace tools can use and an ATB trace output that is sent to a funnel before going to the CoreSight subsystem. The trace output signals combine with two trace expansions using another funnel and fed into the Embedded Trace FIFO(ETF0). The output trace data stream of the funnel is then replicated before it is sent to either the: - Trace Port Interface Unit(TPIU), that sends it out using the trace port. - ETR that can write the trace data to memory located in the application memory space Cc: Lorenzo Pieralisi Acked-by: Liviu Dudau Acked-by: Mathieu Poirier Signed-off-by: Sudeep Holla diff --git a/arch/arm64/boot/dts/arm/juno-base.dtsi b/arch/arm64/boot/dts/arm/juno-base.dtsi index dee2386..4ea40a4 100644 --- a/arch/arm64/boot/dts/arm/juno-base.dtsi +++ b/arch/arm64/boot/dts/arm/juno-base.dtsi @@ -56,6 +56,303 @@ ; }; + /* + * Juno TRMs specify the size for these coresight components as 64K. + * The actual size is just 4K though 64K is reserved. Access to the + * unmapped reserved region results in a DECERR response. + */ + etf@20010000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0 0x20010000 0 0x1000>; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + ports { + #address-cells = <1>; + #size-cells = <0>; + + /* input port */ + port@0 { + reg = <0>; + etf_in_port: endpoint { + slave-mode; + remote-endpoint = <&main_funnel_out_port>; + }; + }; + + /* output port */ + port@1 { + reg = <0>; + etf_out_port: endpoint { + remote-endpoint = <&replicator_in_port0>; + }; + }; + }; + }; + + tpiu@20030000 { + compatible = "arm,coresight-tpiu", "arm,primecell"; + reg = <0 0x20030000 0 0x1000>; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + port { + tpiu_in_port: endpoint { + slave-mode; + remote-endpoint = <&replicator_out_port0>; + }; + }; + }; + + main-funnel@20040000 { + compatible = "arm,coresight-funnel", "arm,primecell"; + reg = <0 0x20040000 0 0x1000>; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + main_funnel_out_port: endpoint { + remote-endpoint = <&etf_in_port>; + }; + }; + + port@1 { + reg = <0>; + main_funnel_in_port0: endpoint { + slave-mode; + remote-endpoint = <&cluster0_funnel_out_port>; + }; + }; + + port@2 { + reg = <1>; + main_funnel_in_port1: endpoint { + slave-mode; + remote-endpoint = <&cluster1_funnel_out_port>; + }; + }; + + }; + }; + + etr@20070000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0 0x20070000 0 0x1000>; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + port { + etr_in_port: endpoint { + slave-mode; + remote-endpoint = <&replicator_out_port1>; + }; + }; + }; + + etm0: etm@22040000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0x22040000 0 0x1000>; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + port { + cluster0_etm0_out_port: endpoint { + remote-endpoint = <&cluster0_funnel_in_port0>; + }; + }; + }; + + cluster0-funnel@220c0000 { + compatible = "arm,coresight-funnel", "arm,primecell"; + reg = <0 0x220c0000 0 0x1000>; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + cluster0_funnel_out_port: endpoint { + remote-endpoint = <&main_funnel_in_port0>; + }; + }; + + port@1 { + reg = <0>; + cluster0_funnel_in_port0: endpoint { + slave-mode; + remote-endpoint = <&cluster0_etm0_out_port>; + }; + }; + + port@2 { + reg = <1>; + cluster0_funnel_in_port1: endpoint { + slave-mode; + remote-endpoint = <&cluster0_etm1_out_port>; + }; + }; + }; + }; + + etm1: etm@22140000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0x22140000 0 0x1000>; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + port { + cluster0_etm1_out_port: endpoint { + remote-endpoint = <&cluster0_funnel_in_port1>; + }; + }; + }; + + etm2: etm@23040000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0x23040000 0 0x1000>; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + port { + cluster1_etm0_out_port: endpoint { + remote-endpoint = <&cluster1_funnel_in_port0>; + }; + }; + }; + + cluster1-funnel@230c0000 { + compatible = "arm,coresight-funnel", "arm,primecell"; + reg = <0 0x230c0000 0 0x1000>; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + cluster1_funnel_out_port: endpoint { + remote-endpoint = <&main_funnel_in_port1>; + }; + }; + + port@1 { + reg = <0>; + cluster1_funnel_in_port0: endpoint { + slave-mode; + remote-endpoint = <&cluster1_etm0_out_port>; + }; + }; + + port@2 { + reg = <1>; + cluster1_funnel_in_port1: endpoint { + slave-mode; + remote-endpoint = <&cluster1_etm1_out_port>; + }; + }; + port@3 { + reg = <2>; + cluster1_funnel_in_port2: endpoint { + slave-mode; + remote-endpoint = <&cluster1_etm2_out_port>; + }; + }; + port@4 { + reg = <3>; + cluster1_funnel_in_port3: endpoint { + slave-mode; + remote-endpoint = <&cluster1_etm3_out_port>; + }; + }; + }; + }; + + etm3: etm@23140000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0x23140000 0 0x1000>; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + port { + cluster1_etm1_out_port: endpoint { + remote-endpoint = <&cluster1_funnel_in_port1>; + }; + }; + }; + + etm4: etm@23240000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0x23240000 0 0x1000>; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + port { + cluster1_etm2_out_port: endpoint { + remote-endpoint = <&cluster1_funnel_in_port2>; + }; + }; + }; + + etm5: etm@23340000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0x23340000 0 0x1000>; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + port { + cluster1_etm3_out_port: endpoint { + remote-endpoint = <&cluster1_funnel_in_port3>; + }; + }; + }; + + coresight-replicator { + /* + * Non-configurable replicators don't show up on the + * AMBA bus. As such no need to add "arm,primecell". + */ + compatible = "arm,coresight-replicator"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + /* replicator output ports */ + port@0 { + reg = <0>; + replicator_out_port0: endpoint { + remote-endpoint = <&tpiu_in_port>; + }; + }; + + port@1 { + reg = <1>; + replicator_out_port1: endpoint { + remote-endpoint = <&etr_in_port>; + }; + }; + + /* replicator input port */ + port@2 { + reg = <0>; + replicator_in_port0: endpoint { + slave-mode; + remote-endpoint = <&etf_out_port>; + }; + }; + }; + }; + sram: sram@2e000000 { compatible = "arm,juno-sram-ns", "mmio-sram"; reg = <0x0 0x2e000000 0x0 0x8000>; diff --git a/arch/arm64/boot/dts/arm/juno-r1.dts b/arch/arm64/boot/dts/arm/juno-r1.dts index d95d9e7..f4f8f54 100644 --- a/arch/arm64/boot/dts/arm/juno-r1.dts +++ b/arch/arm64/boot/dts/arm/juno-r1.dts @@ -181,3 +181,27 @@ &pcie_ctlr { status = "okay"; }; + +&etm0 { + cpu = <&A57_0>; +}; + +&etm1 { + cpu = <&A57_1>; +}; + +&etm2 { + cpu = <&A53_0>; +}; + +&etm3 { + cpu = <&A53_1>; +}; + +&etm4 { + cpu = <&A53_2>; +}; + +&etm5 { + cpu = <&A53_3>; +}; diff --git a/arch/arm64/boot/dts/arm/juno-r2.dts b/arch/arm64/boot/dts/arm/juno-r2.dts index 88ecd61..d903e54 100644 --- a/arch/arm64/boot/dts/arm/juno-r2.dts +++ b/arch/arm64/boot/dts/arm/juno-r2.dts @@ -181,3 +181,27 @@ &pcie_ctlr { status = "okay"; }; + +&etm0 { + cpu = <&A72_0>; +}; + +&etm1 { + cpu = <&A72_1>; +}; + +&etm2 { + cpu = <&A53_0>; +}; + +&etm3 { + cpu = <&A53_1>; +}; + +&etm4 { + cpu = <&A53_2>; +}; + +&etm5 { + cpu = <&A53_3>; +}; diff --git a/arch/arm64/boot/dts/arm/juno.dts b/arch/arm64/boot/dts/arm/juno.dts index dcfcf15..a7270ef 100644 --- a/arch/arm64/boot/dts/arm/juno.dts +++ b/arch/arm64/boot/dts/arm/juno.dts @@ -173,3 +173,27 @@ #include "juno-base.dtsi" }; + +&etm0 { + cpu = <&A57_0>; +}; + +&etm1 { + cpu = <&A57_1>; +}; + +&etm2 { + cpu = <&A53_0>; +}; + +&etm3 { + cpu = <&A53_1>; +}; + +&etm4 { + cpu = <&A53_2>; +}; + +&etm5 { + cpu = <&A53_3>; +}; -- cgit v0.10.2 From bdeaa21affa696279ed9b676d6e4f8ddc6f42a54 Mon Sep 17 00:00:00 2001 From: Sudeep Holla Date: Thu, 2 Jun 2016 10:57:06 +0100 Subject: arm64: dts: juno: add SCPI power domains for device power management This patch adds power domain information to coresight devices using SCPI power domains. Cc: Lorenzo Pieralisi Acked-by: Liviu Dudau Signed-off-by: Sudeep Holla diff --git a/arch/arm64/boot/dts/arm/juno-base.dtsi b/arch/arm64/boot/dts/arm/juno-base.dtsi index 4ea40a4..53820fa 100644 --- a/arch/arm64/boot/dts/arm/juno-base.dtsi +++ b/arch/arm64/boot/dts/arm/juno-base.dtsi @@ -67,6 +67,7 @@ clocks = <&soc_smc50mhz>; clock-names = "apb_pclk"; + power-domains = <&scpi_devpd 0>; ports { #address-cells = <1>; #size-cells = <0>; @@ -96,6 +97,7 @@ clocks = <&soc_smc50mhz>; clock-names = "apb_pclk"; + power-domains = <&scpi_devpd 0>; port { tpiu_in_port: endpoint { slave-mode; @@ -110,6 +112,7 @@ clocks = <&soc_smc50mhz>; clock-names = "apb_pclk"; + power-domains = <&scpi_devpd 0>; ports { #address-cells = <1>; #size-cells = <0>; @@ -146,6 +149,7 @@ clocks = <&soc_smc50mhz>; clock-names = "apb_pclk"; + power-domains = <&scpi_devpd 0>; port { etr_in_port: endpoint { slave-mode; @@ -160,6 +164,7 @@ clocks = <&soc_smc50mhz>; clock-names = "apb_pclk"; + power-domains = <&scpi_devpd 0>; port { cluster0_etm0_out_port: endpoint { remote-endpoint = <&cluster0_funnel_in_port0>; @@ -173,6 +178,7 @@ clocks = <&soc_smc50mhz>; clock-names = "apb_pclk"; + power-domains = <&scpi_devpd 0>; ports { #address-cells = <1>; #size-cells = <0>; @@ -208,6 +214,7 @@ clocks = <&soc_smc50mhz>; clock-names = "apb_pclk"; + power-domains = <&scpi_devpd 0>; port { cluster0_etm1_out_port: endpoint { remote-endpoint = <&cluster0_funnel_in_port1>; @@ -221,6 +228,7 @@ clocks = <&soc_smc50mhz>; clock-names = "apb_pclk"; + power-domains = <&scpi_devpd 0>; port { cluster1_etm0_out_port: endpoint { remote-endpoint = <&cluster1_funnel_in_port0>; @@ -234,6 +242,7 @@ clocks = <&soc_smc50mhz>; clock-names = "apb_pclk"; + power-domains = <&scpi_devpd 0>; ports { #address-cells = <1>; #size-cells = <0>; @@ -283,6 +292,7 @@ clocks = <&soc_smc50mhz>; clock-names = "apb_pclk"; + power-domains = <&scpi_devpd 0>; port { cluster1_etm1_out_port: endpoint { remote-endpoint = <&cluster1_funnel_in_port1>; @@ -296,6 +306,7 @@ clocks = <&soc_smc50mhz>; clock-names = "apb_pclk"; + power-domains = <&scpi_devpd 0>; port { cluster1_etm2_out_port: endpoint { remote-endpoint = <&cluster1_funnel_in_port2>; @@ -309,6 +320,7 @@ clocks = <&soc_smc50mhz>; clock-names = "apb_pclk"; + power-domains = <&scpi_devpd 0>; port { cluster1_etm3_out_port: endpoint { remote-endpoint = <&cluster1_funnel_in_port3>; @@ -416,6 +428,12 @@ }; }; + scpi_devpd: scpi-power-domains { + compatible = "arm,scpi-power-domains"; + num-domains = <2>; + #power-domain-cells = <1>; + }; + scpi_sensors0: sensors { compatible = "arm,scpi-sensors"; #thermal-sensor-cells = <1>; -- cgit v0.10.2 From f7b636a8d83c7c1285c55248e35458e03a007df3 Mon Sep 17 00:00:00 2001 From: Javi Merino Date: Mon, 13 Jun 2016 16:15:15 +0100 Subject: arm64: dts: juno: add thermal zones for scpi sensors The juno dts have entries for the hwmon scpi, let's create thermal zones for the temperature sensors described in the Juno ARM Development Platform Implementation Details. Cc: Liviu Dudau Cc: Lorenzo Pieralisi Cc: Rob Herring Cc: Mark Rutland Acked-by: Punit Agrawal Signed-off-by: Javi Merino Signed-off-by: Sudeep Holla diff --git a/arch/arm64/boot/dts/arm/juno-base.dtsi b/arch/arm64/boot/dts/arm/juno-base.dtsi index 53820fa..334271a 100644 --- a/arch/arm64/boot/dts/arm/juno-base.dtsi +++ b/arch/arm64/boot/dts/arm/juno-base.dtsi @@ -440,6 +440,48 @@ }; }; + thermal-zones { + pmic { + polling-delay = <1000>; + polling-delay-passive = <100>; + thermal-sensors = <&scpi_sensors0 0>; + }; + + soc { + polling-delay = <1000>; + polling-delay-passive = <100>; + thermal-sensors = <&scpi_sensors0 3>; + }; + + big_cluster_thermal_zone: big_cluster { + polling-delay = <1000>; + polling-delay-passive = <100>; + thermal-sensors = <&scpi_sensors0 21>; + status = "disabled"; + }; + + little_cluster_thermal_zone: little_cluster { + polling-delay = <1000>; + polling-delay-passive = <100>; + thermal-sensors = <&scpi_sensors0 22>; + status = "disabled"; + }; + + gpu0_thermal_zone: gpu0 { + polling-delay = <1000>; + polling-delay-passive = <100>; + thermal-sensors = <&scpi_sensors0 23>; + status = "disabled"; + }; + + gpu1_thermal_zone: gpu1 { + polling-delay = <1000>; + polling-delay-passive = <100>; + thermal-sensors = <&scpi_sensors0 24>; + status = "disabled"; + }; + }; + /include/ "juno-clocks.dtsi" dma@7ff00000 { diff --git a/arch/arm64/boot/dts/arm/juno-r1.dts b/arch/arm64/boot/dts/arm/juno-r1.dts index f4f8f54..123a58b 100644 --- a/arch/arm64/boot/dts/arm/juno-r1.dts +++ b/arch/arm64/boot/dts/arm/juno-r1.dts @@ -205,3 +205,19 @@ &etm5 { cpu = <&A53_3>; }; + +&big_cluster_thermal_zone { + status = "okay"; +}; + +&little_cluster_thermal_zone { + status = "okay"; +}; + +&gpu0_thermal_zone { + status = "okay"; +}; + +&gpu1_thermal_zone { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/arm/juno-r2.dts b/arch/arm64/boot/dts/arm/juno-r2.dts index d903e54..007be82 100644 --- a/arch/arm64/boot/dts/arm/juno-r2.dts +++ b/arch/arm64/boot/dts/arm/juno-r2.dts @@ -205,3 +205,19 @@ &etm5 { cpu = <&A53_3>; }; + +&big_cluster_thermal_zone { + status = "okay"; +}; + +&little_cluster_thermal_zone { + status = "okay"; +}; + +&gpu0_thermal_zone { + status = "okay"; +}; + +&gpu1_thermal_zone { + status = "okay"; +}; -- cgit v0.10.2 From 64e3481c8ab187a42b68048dbd321e54d182e762 Mon Sep 17 00:00:00 2001 From: Douglas Anderson Date: Mon, 20 Jun 2016 10:56:48 -0700 Subject: arm64: dts: rockchip: Add soc-ctl-syscon to sdhci for rk3399 On rk3399 we'd like to be able to properly set corecfg registers in the Arasan SDHCI component. Specify the syscon to enable that. Signed-off-by: Douglas Anderson Tested-by: Heiko Stuebner Signed-off-by: Heiko Stuebner diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index ef472e2..9833c7d 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -229,6 +229,7 @@ compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1"; reg = <0x0 0xfe330000 0x0 0x10000>; interrupts = ; + arasan,soc-ctl-syscon = <&grf>; assigned-clocks = <&cru SCLK_EMMC>; assigned-clock-rates = <200000000>; clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>; -- cgit v0.10.2 From ed388cdd2ea0655265ff89fe02ded670298a23dc Mon Sep 17 00:00:00 2001 From: Douglas Anderson Date: Mon, 20 Jun 2016 10:56:54 -0700 Subject: arm64: dts: rockchip: Provide emmcclk to PHY for rk3399 Previous changes in this series allowed exposing the card clock from the rk3399 SDHCI device and allowed consuming the card clock in the rk3399 eMMC PHY. Hook things up in the main rk3399 dtsi file. Signed-off-by: Douglas Anderson Tested-by: Heiko Stuebner Signed-off-by: Heiko Stuebner diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index 9833c7d..74fbcce 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -234,6 +234,8 @@ assigned-clock-rates = <200000000>; clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>; clock-names = "clk_xin", "clk_ahb"; + clock-output-names = "emmc_cardclock"; + #clock-cells = <0>; phys = <&emmc_phy>; phy-names = "phy_arasan"; status = "disabled"; @@ -765,6 +767,8 @@ emmc_phy: phy@f780 { compatible = "rockchip,rk3399-emmc-phy"; reg = <0xf780 0x24>; + clocks = <&sdhci>; + clock-names = "emmcclk"; #phy-cells = <0>; status = "disabled"; }; -- cgit v0.10.2 From ba6a6c7fa6de9f3e29f0e15a7e972b2461ac44a5 Mon Sep 17 00:00:00 2001 From: Michael Turquette Date: Wed, 22 Jun 2016 19:12:23 -0700 Subject: arm64: dts: gxbb clock controller Add the clock controller node for the AmLogic GXBB machine. Signed-off-by: Michael Turquette Signed-off-by: Kevin Hilman diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi index 806b903..e502c24 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi @@ -315,6 +315,12 @@ #address-cells = <2>; #size-cells = <2>; ranges = <0x0 0x0 0x0 0xc883c000 0x0 0x2000>; + + clkc: clock-controller@0 { + compatible = "amlogic,gxbb-clkc"; + #clock-cells = <1>; + reg = <0x0 0x0 0x0 0x3db>; + }; }; apb: apb@d0000000 { -- cgit v0.10.2 From f3abd6296168d9d356192b50a92a7a980ca99a2f Mon Sep 17 00:00:00 2001 From: Kevin Hilman Date: Tue, 14 Jun 2016 12:03:39 -0700 Subject: ARM64: DTS: meson-gxbb: switch ethernet to real clock With the clock driver upstream, switch to the real clock. Signed-off-by: Kevin Hilman diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi index e502c24..35c8b2b 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi @@ -45,6 +45,7 @@ #include #include #include +#include / { compatible = "amlogic,meson-gxbb"; @@ -337,7 +338,7 @@ 0x0 0xc8834540 0x0 0x4>; interrupts = <0 8 1>; interrupt-names = "macirq"; - clocks = <&xtal>; + clocks = <&clkc CLKID_ETH>; clock-names = "stmmaceth"; phy-mode = "rgmii"; status = "disabled"; -- cgit v0.10.2 From 84361086dfecff8f3221dfb0d0fd0ea9810e31a1 Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Fri, 17 Jun 2016 16:13:58 +0100 Subject: arm64: dts: msm8996: add msmgpio label This patch adds msmgpio label for pin and gpio controller so that it can referenced in dedicated pins file and other board level gpios. Signed-off-by: Srinivas Kandagatla Signed-off-by: Andy Gross diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 0506fb8..8bf382f 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -161,7 +161,7 @@ status = "disabled"; }; - pinctrl@1010000 { + msmgpio: pinctrl@1010000 { compatible = "qcom,msm8996-pinctrl"; reg = <0x01010000 0x300000>; interrupts = ; -- cgit v0.10.2 From 22e6789f9493d99a062a3bdc3c064b46b8b30e0d Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Fri, 17 Jun 2016 16:13:59 +0100 Subject: arm64: dts: msm8996: add blsp2_uart1 pinctrl This patch adds 2pin and 4 pin uart pinctrl support for blsp2_uart1 Signed-off-by: Srinivas Kandagatla Signed-off-by: Andy Gross diff --git a/arch/arm64/boot/dts/qcom/msm8996-pins.dtsi b/arch/arm64/boot/dts/qcom/msm8996-pins.dtsi new file mode 100644 index 0000000..4d1dba7 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8996-pins.dtsi @@ -0,0 +1,65 @@ +/* + * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&msmgpio { + + blsp2_uart1_2pins_default: blsp2_uart1_2pins { + pinmux { + function = "blsp_uart8"; + pins = "gpio4", "gpio5"; + }; + pinconf { + pins = "gpio4", "gpio5"; + drive-strength = <16>; + bias-disable; + }; + }; + + blsp2_uart1_2pins_sleep: blsp2_uart1_2pins_sleep { + pinmux { + function = "gpio"; + pins = "gpio4", "gpio5"; + }; + pinconf { + pins = "gpio4", "gpio5"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp2_uart1_4pins_default: blsp2_uart1_4pins { + pinmux { + function = "blsp_uart8"; + pins = "gpio4", "gpio5", "gpio6", "gpio7"; + }; + + pinconf { + pins = "gpio4", "gpio5", "gpio6", "gpio7"; + drive-strength = <16>; + bias-disable; + }; + }; + + blsp2_uart1_4pins_sleep: blsp2_uart1_4pins_sleep { + pinmux { + function = "gpio"; + pins = "gpio4", "gpio5", "gpio6", "gpio7"; + }; + + pinconf { + pins = "gpio4", "gpiio5", "gpio6", "gpio7"; + drive-strength = <2>; + bias-disable; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 8bf382f..22b770f 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -267,3 +267,4 @@ }; }; }; +#include "msm8996-pins.dtsi" -- cgit v0.10.2 From 96f86b7d68ebaab448e1de7c9e0965adba983cc7 Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Fri, 17 Jun 2016 16:14:00 +0100 Subject: arm64: dts: msm8996: add blsp2_uart2 pinctrl nodes. This patch adds blsp2_uart2 pinctrl nodes. Signed-off-by: Srinivas Kandagatla Signed-off-by: Andy Gross diff --git a/arch/arm64/boot/dts/qcom/msm8996-pins.dtsi b/arch/arm64/boot/dts/qcom/msm8996-pins.dtsi index 4d1dba7..03c1e0d 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-pins.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996-pins.dtsi @@ -62,4 +62,54 @@ bias-disable; }; }; + + blsp2_uart2_2pins_default: blsp2_uart2_2pins { + pinmux { + function = "blsp_uart9"; + pins = "gpio49", "gpio50"; + }; + pinconf { + pins = "gpio49", "gpio50"; + drive-strength = <16>; + bias-disable; + }; + }; + + blsp2_uart2_2pins_sleep: blsp2_uart2_2pins_sleep { + pinmux { + function = "gpio"; + pins = "gpio49", "gpio50"; + }; + pinconf { + pins = "gpio49", "gpio50"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp2_uart2_4pins_default: blsp2_uart2_4pins { + pinmux { + function = "blsp_uart9"; + pins = "gpio49", "gpio50", "gpio51", "gpio52"; + }; + + pinconf { + pins = "gpio49", "gpio50", "gpio51", "gpio52"; + drive-strength = <16>; + bias-disable; + }; + }; + + blsp2_uart2_4pins_sleep: blsp2_uart2_4pins_sleep { + pinmux { + function = "gpio"; + pins = "gpio49", "gpio50", "gpio51", "gpio52"; + }; + + pinconf { + pins = "gpio49", "gpio50", "gpio51", "gpio52"; + drive-strength = <2>; + bias-disable; + }; + }; }; -- cgit v0.10.2 From fda48e610990d834918de2825cd97c37fb63dc51 Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Fri, 17 Jun 2016 16:14:01 +0100 Subject: arm64: dts: msm8996: add support blsp2_uart2 This patch adds bslp2_uart2 node in soc so that boards that use this uart can enable it. Signed-off-by: Srinivas Kandagatla Signed-off-by: Andy Gross diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 22b770f..a1605f7 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -161,6 +161,16 @@ status = "disabled"; }; + blsp2_uart2: serial@75b1000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0x075b1000 0x1000>; + interrupts = ; + clocks = <&gcc GCC_BLSP2_UART3_APPS_CLK>, + <&gcc GCC_BLSP2_AHB_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + msmgpio: pinctrl@1010000 { compatible = "qcom,msm8996-pinctrl"; reg = <0x01010000 0x300000>; -- cgit v0.10.2 From 5f9d54ffc15fa987f626b8974447b3679abcb778 Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Fri, 17 Jun 2016 16:14:02 +0100 Subject: arm64: dts: msm8996: add blsp1_i2c2 pinctrl nodes. This patch adds pinctrl nodes required for blsp1_i2c2. Signed-off-by: Srinivas Kandagatla Signed-off-by: Andy Gross diff --git a/arch/arm64/boot/dts/qcom/msm8996-pins.dtsi b/arch/arm64/boot/dts/qcom/msm8996-pins.dtsi index 03c1e0d..1f6a0a4 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-pins.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996-pins.dtsi @@ -13,6 +13,30 @@ &msmgpio { + blsp1_i2c2_default: blsp1_i2c2_default { + pinmux { + function = "blsp_i2c3"; + pins = "gpio47", "gpio48"; + }; + pinconf { + pins = "gpio47", "gpio48"; + drive-strength = <16>; + bias-disable = <0>; + }; + }; + + blsp1_i2c2_sleep: blsp1_i2c2_sleep { + pinmux { + function = "gpio"; + pins = "gpio47", "gpio48"; + }; + pinconf { + pins = "gpio47", "gpio48"; + drive-strength = <2>; + bias-disable = <0>; + }; + }; + blsp2_uart1_2pins_default: blsp2_uart1_2pins { pinmux { function = "blsp_uart8"; -- cgit v0.10.2 From 21a40384613cbe0f5c52623eda7ae357e2d0652a Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Fri, 17 Jun 2016 16:14:03 +0100 Subject: arm64: dts: msm8996: add support to blsp1_i2c2 device This patch adds blsp1_i2c2 support, as this bus is used on some of the apq8096 boards. Signed-off-by: Srinivas Kandagatla Signed-off-by: Andy Gross diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index a1605f7..5536bfc 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -171,6 +171,21 @@ status = "disabled"; }; + blsp1_i2c2: i2c@07577000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x07577000 0x1000>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>; + clock-names = "iface", "core"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&blsp1_i2c2_default>; + pinctrl-1 = <&blsp1_i2c2_sleep>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + msmgpio: pinctrl@1010000 { compatible = "qcom,msm8996-pinctrl"; reg = <0x01010000 0x300000>; -- cgit v0.10.2 From 0e7f1960834f8fe782263b45d71fbf2f9ea25cef Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Fri, 17 Jun 2016 16:14:04 +0100 Subject: arm64: dts: msm8996: add blsp2_i2c1 pinctrl This patch adds support to blsp2_i2c1 pinctrl nodes. Signed-off-by: Srinivas Kandagatla Signed-off-by: Andy Gross diff --git a/arch/arm64/boot/dts/qcom/msm8996-pins.dtsi b/arch/arm64/boot/dts/qcom/msm8996-pins.dtsi index 1f6a0a4..7017bb6 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-pins.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996-pins.dtsi @@ -87,6 +87,30 @@ }; }; + blsp2_i2c1_default: blsp2_i2c1 { + pinmux { + function = "blsp_i2c8"; + pins = "gpio6", "gpio7"; + }; + pinconf { + pins = "gpio6", "gpio7"; + drive-strength = <16>; + bias-disable; + }; + }; + + blsp2_i2c1_sleep: blsp2_i2c1_sleep { + pinmux { + function = "gpio"; + pins = "gpio6", "gpio7"; + }; + pinconf { + pins = "gpio6", "gpio7"; + drive-strength = <2>; + bias-disable; + }; + }; + blsp2_uart2_2pins_default: blsp2_uart2_2pins { pinmux { function = "blsp_uart9"; -- cgit v0.10.2 From d41d0cee9a860b64c678e75355a0e0320dbb794a Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Fri, 17 Jun 2016 16:14:05 +0100 Subject: arm64: dts: msm8996: add support to blsp2_i2c1 This patch adds support to blsp2_i2c1, which is used in one of the apq8096 based boards. Signed-off-by: Srinivas Kandagatla Signed-off-by: Andy Gross diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 5536bfc..ef3c370 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -161,6 +161,21 @@ status = "disabled"; }; + blsp2_i2c1: i2c@075b6000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x075b6000 0x1000>; + interrupts = ; + clocks = <&gcc GCC_BLSP2_AHB_CLK>, + <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>; + clock-names = "iface", "core"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&blsp2_i2c1_default>; + pinctrl-1 = <&blsp2_i2c1_sleep>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + blsp2_uart2: serial@75b1000 { compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; reg = <0x075b1000 0x1000>; -- cgit v0.10.2 From e25d57c106e2963f07a22140b7c40d0dc7e52a09 Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Fri, 17 Jun 2016 16:14:06 +0100 Subject: arm64: dts: msm8996: add support to blsp2_i2c0 pinctrl This patch adds support to blsp2_i2c0 pinctrl. Signed-off-by: Srinivas Kandagatla Signed-off-by: Andy Gross diff --git a/arch/arm64/boot/dts/qcom/msm8996-pins.dtsi b/arch/arm64/boot/dts/qcom/msm8996-pins.dtsi index 7017bb6..79ed98c 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-pins.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996-pins.dtsi @@ -37,6 +37,30 @@ }; }; + blsp2_i2c0_default: blsp2_i2c0 { + pinmux { + function = "blsp_i2c7"; + pins = "gpio55", "gpio56"; + }; + pinconf { + pins = "gpio55", "gpio56"; + drive-strength = <16>; + bias-disable; + }; + }; + + blsp2_i2c0_sleep: blsp2_i2c0_sleep { + pinmux { + function = "gpio"; + pins = "gpio55", "gpio56"; + }; + pinconf { + pins = "gpio55", "gpio56"; + drive-strength = <2>; + bias-disable; + }; + }; + blsp2_uart1_2pins_default: blsp2_uart1_2pins { pinmux { function = "blsp_uart8"; -- cgit v0.10.2 From bf5443bcaa45eab238d678c7f70a934a71c15b66 Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Fri, 17 Jun 2016 16:14:07 +0100 Subject: arm64: dts: msm8996: add support to blsp2_i2c0 This patch adds support to blsp2_i2c0, which is used on some of the APQ8096 based boards. Signed-off-by: Srinivas Kandagatla Signed-off-by: Andy Gross diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index ef3c370..675888f 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -151,6 +151,21 @@ reg = <0x300000 0x90000>; }; + blsp2_i2c0: i2c@075b5000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x075b5000 0x1000>; + interrupts = ; + clocks = <&gcc GCC_BLSP2_AHB_CLK>, + <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>; + clock-names = "iface", "core"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&blsp2_i2c0_default>; + pinctrl-1 = <&blsp2_i2c0_sleep>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + blsp2_uart1: serial@75b0000 { compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; reg = <0x75b0000 0x1000>; -- cgit v0.10.2 From 9f05d8ff8a15cef16f43992ea636c98b85585417 Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Fri, 17 Jun 2016 16:14:08 +0100 Subject: arm64: dts: msm8996: add support to blsp1_spi0 pinctrl This patch adds pinctrl nodes required for blsp1_spi0. Signed-off-by: Srinivas Kandagatla Signed-off-by: Andy Gross diff --git a/arch/arm64/boot/dts/qcom/msm8996-pins.dtsi b/arch/arm64/boot/dts/qcom/msm8996-pins.dtsi index 79ed98c..9fd37a0 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-pins.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996-pins.dtsi @@ -13,6 +13,40 @@ &msmgpio { + blsp1_spi0_default: blsp1_spi0_default { + pinmux { + function = "blsp_spi1"; + pins = "gpio0", "gpio1", "gpio3"; + }; + pinmux_cs { + function = "gpio"; + pins = "gpio2"; + }; + pinconf { + pins = "gpio0", "gpio1", "gpio3"; + drive-strength = <12>; + bias-disable; + }; + pinconf_cs { + pins = "gpio2"; + drive-strength = <16>; + bias-disable; + output-high; + }; + }; + + blsp1_spi0_sleep: blsp1_spi0_sleep { + pinmux { + function = "gpio"; + pins = "gpio0", "gpio1", "gpio2", "gpio3"; + }; + pinconf { + pins = "gpio0", "gpio1", "gpio2", "gpio3"; + drive-strength = <2>; + bias-pull-down; + }; + }; + blsp1_i2c2_default: blsp1_i2c2_default { pinmux { function = "blsp_i2c3"; -- cgit v0.10.2 From 604677b415031918a7c780da91c105c41347ba3e Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Fri, 17 Jun 2016 16:14:09 +0100 Subject: arm64: dts: msm8996: add support to blsp1_spi0 This patch adds support to blsp1_spi0 which is used on some of APQ8096 based boards. Signed-off-by: Srinivas Kandagatla Signed-off-by: Andy Gross diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 675888f..e009063 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -151,6 +151,21 @@ reg = <0x300000 0x90000>; }; + blsp1_spi0: spi@07575000 { + compatible = "qcom,spi-qup-v2.2.1"; + reg = <0x07575000 0x600>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&blsp1_spi0_default>; + pinctrl-1 = <&blsp1_spi0_sleep>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + blsp2_i2c0: i2c@075b5000 { compatible = "qcom,i2c-qup-v2.2.1"; reg = <0x075b5000 0x1000>; -- cgit v0.10.2 From 7dba64a23e29b8afa7525bdda4e6929d4a7ff629 Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Fri, 17 Jun 2016 16:14:10 +0100 Subject: arm64: dts: msm8996: add support to blsp2_spi5 pinctrl This patch adds pinctrl required for blsp2_spi5 device. Signed-off-by: Srinivas Kandagatla Signed-off-by: Andy Gross diff --git a/arch/arm64/boot/dts/qcom/msm8996-pins.dtsi b/arch/arm64/boot/dts/qcom/msm8996-pins.dtsi index 9fd37a0..551707a 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-pins.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996-pins.dtsi @@ -218,4 +218,38 @@ bias-disable; }; }; + + blsp2_spi5_default: blsp2_spi5_default { + pinmux { + function = "blsp_spi12"; + pins = "gpio85", "gpio86", "gpio88"; + }; + pinmux_cs { + function = "gpio"; + pins = "gpio87"; + }; + pinconf { + pins = "gpio85", "gpio86", "gpio88"; + drive-strength = <12>; + bias-disable; + }; + pinconf_cs { + pins = "gpio87"; + drive-strength = <16>; + bias-disable; + output-high; + }; + }; + + blsp2_spi5_sleep: blsp2_spi5_sleep { + pinmux { + function = "gpio"; + pins = "gpio85", "gpio86", "gpio87", "gpio88"; + }; + pinconf { + pins = "gpio85", "gpio86", "gpio87", "gpio88"; + drive-strength = <2>; + bias-pull-down; + }; + }; }; -- cgit v0.10.2 From db6c8c83252659e42bb3881521d8bc8607dd7a09 Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Fri, 17 Jun 2016 16:14:11 +0100 Subject: arm64: dts: msm8996: add support to blsp2_spi5 This patch adds support to blsp2_spi5 device, which is used in some of the APQ8096 based boards. Signed-off-by: Srinivas Kandagatla Signed-off-by: Andy Gross diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index e009063..f68b078 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -231,6 +231,21 @@ status = "disabled"; }; + blsp2_spi5: spi@075ba000{ + compatible = "qcom,spi-qup-v2.2.1"; + reg = <0x075ba000 0x600>; + interrupts = ; + clocks = <&gcc GCC_BLSP2_QUP5_SPI_APPS_CLK>, + <&gcc GCC_BLSP2_AHB_CLK>; + clock-names = "core", "iface"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&blsp2_spi5_default>; + pinctrl-1 = <&blsp2_spi5_sleep>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + msmgpio: pinctrl@1010000 { compatible = "qcom,msm8996-pinctrl"; reg = <0x01010000 0x300000>; -- cgit v0.10.2 From 84ddf1ee1e28f790309b6132a572fad16dba4e3a Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Fri, 17 Jun 2016 16:14:12 +0100 Subject: arm64: dts: msm8996: add sdc2 pinctrl This patch adds pinctrl required for sdhci for external sd card controller. Signed-off-by: Srinivas Kandagatla Signed-off-by: Andy Gross diff --git a/arch/arm64/boot/dts/qcom/msm8996-pins.dtsi b/arch/arm64/boot/dts/qcom/msm8996-pins.dtsi index 551707a..6599404 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-pins.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996-pins.dtsi @@ -252,4 +252,52 @@ bias-pull-down; }; }; + + sdc2_clk_on: sdc2_clk_on { + config { + pins = "sdc2_clk"; + bias-disable; /* NO pull */ + drive-strength = <16>; /* 16 MA */ + }; + }; + + sdc2_clk_off: sdc2_clk_off { + config { + pins = "sdc2_clk"; + bias-disable; /* NO pull */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + sdc2_cmd_on: sdc2_cmd_on { + config { + pins = "sdc2_cmd"; + bias-pull-up; /* pull up */ + drive-strength = <10>; /* 10 MA */ + }; + }; + + sdc2_cmd_off: sdc2_cmd_off { + config { + pins = "sdc2_cmd"; + bias-pull-up; /* pull up */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + sdc2_data_on: sdc2_data_on { + config { + pins = "sdc2_data"; + bias-pull-up; /* pull up */ + drive-strength = <10>; /* 10 MA */ + }; + }; + + sdc2_data_off: sdc2_data_off { + config { + pins = "sdc2_data"; + bias-pull-up; /* pull up */ + drive-strength = <2>; /* 2 MA */ + }; + }; }; -- cgit v0.10.2 From a6702798980812c666a5c32e6b12c24f72ef7245 Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Tue, 21 Jun 2016 18:39:53 +0100 Subject: arm64: dts: msm8996: add sdc2 support This patch adds support to sdc2 sdhci controller, which is used on some of the boards. Signed-off-by: Srinivas Kandagatla Signed-off-by: Andy Gross diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index f68b078..55ec3e8 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -246,6 +246,21 @@ status = "disabled"; }; + sdhc2: sdhci@74a4900 { + status = "disabled"; + compatible = "qcom,sdhci-msm-v4"; + reg = <0x74a4900 0x314>, <0x74a4000 0x800>; + reg-names = "hc_mem", "core_mem"; + + interrupts = <0 125 0>, <0 221 0>; + interrupt-names = "hc_irq", "pwr_irq"; + + clock-names = "iface", "core"; + clocks = <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>; + bus-width = <4>; + }; + msmgpio: pinctrl@1010000 { compatible = "qcom,msm8996-pinctrl"; reg = <0x01010000 0x300000>; -- cgit v0.10.2 From 5d26ad9cfb2ebe2aba75342813e7542d5a68d644 Mon Sep 17 00:00:00 2001 From: Douglas Anderson Date: Tue, 14 Jun 2016 13:21:11 -0700 Subject: arm64: dts: rockchip: add ap_pwroff and ddrio_pwroff pins for rk3399 There are two sleep related pins on rk3399: ap_pwroff and ddrio_pwroff. Let's add the definition of these two pins to rk3399's main dtsi file so that boards can use them. These two pins are similar to the global_pwroff and ddrio_pwroff pins in rk3288 and are expected to be used in the same way: boards will likely want to configure these pinctrl settings in their global pinctrl hog list. Note that on rk3288 there were two additional pins in the "sleep" section: "ddr0_retention" and "ddr1_retention". On rk3288 designs these pins appeared to actually route from rk3288 back to rk3288. Presumably on rk3399 this is simply not needed since the pins don't appear to exist there. Signed-off-by: Douglas Anderson Signed-off-by: Heiko Stuebner diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index 74fbcce..80acb38 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -1045,6 +1045,16 @@ }; }; + sleep { + ap_pwroff: ap-pwroff { + rockchip,pins = <1 5 RK_FUNC_1 &pcfg_pull_none>; + }; + + ddrio_pwroff: ddrio-pwroff { + rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + spdif { spdif_bus: spdif-bus { rockchip,pins = -- cgit v0.10.2 From bbaf867e2d3796bca465d07ffcd800a3bd570861 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Fri, 24 Jun 2016 01:06:04 +0200 Subject: arm64: dts: hikey: name the GPIO lines This names the GPIO lines on the HiKey board in accordance with the 96Board Specification for especially the Low Speed External Connector: "GPIO-A" thru "GPIO-L". This will make these line names reflect through to userspace so that they can easily be identified and used with the new character device ABI. Some care has been taken to name all lines, not just those used by the external connectors, also lines that are muxed into some other function than GPIO: these are named "[FOO]" so that users can see with lsgpio what all lines are used for. Cc: devicetree@vger.kernel.org Cc: John Stultz Cc: Rob Herring Cc: David Mandala Cc: Haojian Zhuang Cc: Wei Xu Signed-off-by: Linus Walleij Signed-off-by: Wei Xu diff --git a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts index e92a30c..593c7e4 100644 --- a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts +++ b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts @@ -66,6 +66,149 @@ status = "ok"; }; + /* + * Legend: proper name = the GPIO line is used as GPIO + * NC = not connected (not routed from the SoC) + * "[PER]" = pin is muxed for peripheral (not GPIO) + * "" = no idea, schematic doesn't say, could be + * unrouted (not connected to any external pin) + * LSEC = Low Speed External Connector + * HSEC = High Speed External Connector + * + * Pin assignments taken from LeMaker and CircuitCo Schematics + * Rev A1. + * + * For the lines routed to the external connectors the + * lines are named after the 96Boards CE Specification 1.0, + * Appendix "Expansion Connector Signal Description". + * + * When the 96Board naming of a line and the schematic name of + * the same line are in conflict, the 96Board specification + * takes precedence, which means that the external UART on the + * LSEC is named UART0 while the schematic and SoC names this + * UART2. This is only for the informational lines i.e. "[FOO]", + * the GPIO named lines "GPIO-A" thru "GPIO-L" are the only + * ones actually used for GPIO. + */ + gpio0: gpio@f8011000 { + gpio-line-names = "PWR_HOLD", "DSI_SEL", + "USB_HUB_RESET_N", "USB_SEL", "HDMI_PD", "WL_REG_ON", + "PWRON_DET", "5V_HUB_EN"; + }; + + gpio1: gpio@f8012000 { + gpio-line-names = "SD_DET", "HDMI_INT", "PMU_IRQ_N", + "WL_HOST_WAKE", "NC", "NC", "NC", "BT_REG_ON"; + }; + + gpio2: gpio@f8013000 { + gpio-line-names = + "GPIO-A", /* LSEC Pin 23: GPIO2_0 */ + "GPIO-B", /* LSEC Pin 24: GPIO2_1 */ + "GPIO-C", /* LSEC Pin 25: GPIO2_2 */ + "GPIO-D", /* LSEC Pin 26: GPIO2_3 */ + "GPIO-E", /* LSEC Pin 27: GPIO2_4 */ + "USB_ID_DET", "USB_VBUS_DET", + "GPIO-H"; /* LSEC Pin 30: GPIO2_7 */ + }; + + gpio3: gpio@f8014000 { + gpio-line-names = "GPIO3_0", "NC", "NC", "", "NC", "", + "WLAN_ACTIVE", "NC", "NC"; + }; + + gpio4: gpio@f7020000 { + gpio-line-names = "USER_LED1", "USER_LED2", "USER_LED3", + "USER_LED4", "SD_SEL", "NC", "NC", "BT_ACTIVE"; + }; + + gpio5: gpio@f7021000 { + gpio-line-names = "NC", "NC", + "[UART1_RxD]", /* LSEC Pin 11: UART3_RX */ + "[UART1_TxD]", /* LSEC Pin 13: UART3_TX */ + "[AUX_SSI1]", "NC", + "[PCM_CLK]", /* LSEC Pin 18: MODEM_PCM_XCLK */ + "[PCM_FS]"; /* LSEC Pin 16: MODEM_PCM_XFS */ + }; + + gpio6: gpio@f7022000 { + gpio-line-names = + "[SPI0_DIN]", /* Pin 10: SPI0_DI */ + "[SPI0_DOUT]", /* Pin 14: SPI0_DO */ + "[SPI0_CS]", /* Pin 12: SPI0_CS_N */ + "[SPI0_SCLK]", /* Pin 8: SPI0_SCLK */ + "NC", "NC", "NC", + "GPIO-G"; /* Pin 29: GPIO6_7_DSI_TE0 */ + }; + + gpio7: gpio@f7023000 { + gpio-line-names = "NC", "NC", "NC", "NC", + "[PCM_DI]", /* Pin 22: MODEM_PCM_DI */ + "[PCM_DO]", /* Pin 20: MODEM_PCM_DO */ + "NC", "NC"; + }; + + gpio8: gpio@f7024000 { + gpio-line-names = "NC", "[CEC_CLK_19_2MHZ]", "NC", + "", "", "", "", "", ""; + }; + + gpio9: gpio@f7025000 { + gpio-line-names = "", + "GPIO-J", /* LSEC Pin 32: ISP_PWDN0_GPIO9_1 */ + "GPIO-L", /* LSEC Pin 34: ISP_PWDN1_GPIO9_2 */ + "NC", "NC", "NC", "NC", "[ISP_CCLK0]"; + }; + + gpio10: gpio@f7026000 { + gpio-line-names = "BOOT_SEL", + "[ISP_CCLK1]", + "GPIO-I", /* LSEC Pin 31: ISP_RSTB0_GPIO10_2 */ + "GPIO-K", /* LSEC Pin 33: ISP_RSTB1_GPIO10_3 */ + "NC", "NC", + "[I2C2_SDA]", /* HSEC Pin 34: ISP0_SDA */ + "[I2C2_SCL]"; /* HSEC Pin 32: ISP0_SCL */ + }; + + gpio11: gpio@f7027000 { + gpio-line-names = + "[I2C3_SDA]", /* HSEC Pin 38: ISP1_SDA */ + "[I2C3_SCL]", /* HSEC Pin 36: ISP1_SCL */ + "", "NC", "NC", "NC", "", ""; + }; + + gpio12: gpio@f7028000 { + gpio-line-names = "[BT_PCM_XFS]", "[BT_PCM_DI]", + "[BT_PCM_DO]", + "NC", "NC", "NC", "NC", + "GPIO-F"; /* LSEC Pin 28: BL_PWM_GPIO12_7 */ + }; + + gpio13: gpio@f7029000 { + gpio-line-names = "[UART0_RX]", "[UART0_TX]", + "[BT_UART1_CTS]", "[BT_UART1_RTS]", + "[BT_UART1_RX]", "[BT_UART1_TX]", + "[UART0_CTS]", /* LSEC Pin 3: UART2_CTS_N */ + "[UART0_RTS]"; /* LSEC Pin 9: UART2_RTS_N */ + }; + + gpio14: gpio@f702a000 { + gpio-line-names = + "[UART0_RxD]", /* LSEC Pin 7: UART2_RX */ + "[UART0_TxD]", /* LSEC Pin 5: UART2_TX */ + "[I2C0_SCL]", /* LSEC Pin 15: I2C0_SCL */ + "[I2C0_SDA]", /* LSEC Pin 17: I2C0_SDA */ + "[I2C1_SCL]", /* LSEC Pin 19: I2C1_SCL */ + "[I2C1_SDA]", /* LSEC Pin 21: I2C1_SDA */ + "[I2C2_SCL]", "[I2C2_SDA]"; + }; + + gpio15: gpio@f702b000 { + gpio-line-names = "", "", "", "", "", "", "NC", ""; + }; + + /* GPIO blocks 16 thru 19 do not appear to be routed to pins */ + dwmmc_2: dwmmc2@f723f000 { ti,non-removable; non-removable; -- cgit v0.10.2 From 7eec659478cd78afdd959c2b3ddbfac9a630ee90 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Thu, 16 Jun 2016 14:28:35 +0200 Subject: arm64: dts: marvell: adjust to the latest mv-xor-v2 DT binding As suggested by Rob Herring, we should: 1/ Use a SoC-specific compatible string in addition to the more generic one. 2/ The generic compatible string has been changed from "marvell,mv-xor-v2" to "marvell,xor-v2". We simply reflect the changes made to the Device Tree bindings to the relevant Marvell 7K/8K Device Tree files. Signed-off-by: Thomas Petazzoni Signed-off-by: Gregory CLEMENT diff --git a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi index 20d256b..eab1a42 100644 --- a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi @@ -141,7 +141,7 @@ }; xor@400000 { - compatible = "marvell,mv-xor-v2"; + compatible = "marvell,armada-7k-xor", "marvell,xor-v2"; reg = <0x400000 0x1000>, <0x410000 0x1000>; msi-parent = <&gic_v2m0>; @@ -149,7 +149,7 @@ }; xor@420000 { - compatible = "marvell,mv-xor-v2"; + compatible = "marvell,armada-7k-xor", "marvell,xor-v2"; reg = <0x420000 0x1000>, <0x430000 0x1000>; msi-parent = <&gic_v2m0>; @@ -157,7 +157,7 @@ }; xor@440000 { - compatible = "marvell,mv-xor-v2"; + compatible = "marvell,armada-7k-xor", "marvell,xor-v2"; reg = <0x440000 0x1000>, <0x450000 0x1000>; msi-parent = <&gic_v2m0>; @@ -165,7 +165,7 @@ }; xor@460000 { - compatible = "marvell,mv-xor-v2"; + compatible = "marvell,armada-7k-xor", "marvell,xor-v2"; reg = <0x460000 0x1000>, <0x470000 0x1000>; msi-parent = <&gic_v2m0>; -- cgit v0.10.2 From c7f27355473ad189fd3805a1156f983892cdcba0 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Thu, 16 Jun 2016 14:28:36 +0200 Subject: arm64: dts: marvell: add XOR engine description for Armada 7K/8K CP This commit adds the Device Tree description for the two XOR engines found in the CP part of the Armada 7K/8K SoC. Signed-off-by: Thomas Petazzoni Signed-off-by: Gregory CLEMENT diff --git a/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi index 367138b..da31bbb 100644 --- a/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi @@ -107,6 +107,24 @@ status = "disabled"; }; + cpm_xor0: xor@6a0000 { + compatible = "marvell,armada-7k-xor", "marvell,xor-v2"; + reg = <0x6a0000 0x1000>, + <0x6b0000 0x1000>; + dma-coherent; + msi-parent = <&gic_v2m0>; + clocks = <&cpm_syscon0 1 8>; + }; + + cpm_xor1: xor@6c0000 { + compatible = "marvell,armada-7k-xor", "marvell,xor-v2"; + reg = <0x6c0000 0x1000>, + <0x6d0000 0x1000>; + dma-coherent; + msi-parent = <&gic_v2m0>; + clocks = <&cpm_syscon0 1 7>; + }; + cpm_spi0: spi@700600 { compatible = "marvell,armada-380-spi"; reg = <0x700600 0x50>; -- cgit v0.10.2 From 94613fa63d6492674a4d03c55b22a10a06c0544f Mon Sep 17 00:00:00 2001 From: Mars Cheng Date: Wed, 29 Jun 2016 10:09:32 +0800 Subject: Document: DT: Add bindings for mediatek MT6755 SoC Platform This adds DT binding documentation for Mediatek MT6755. Signed-off-by: Mars Cheng Acked-by: Rob Herring Signed-off-by: Matthias Brugger diff --git a/Documentation/devicetree/bindings/arm/mediatek.txt b/Documentation/devicetree/bindings/arm/mediatek.txt index d9c2a37..c860b24 100644 --- a/Documentation/devicetree/bindings/arm/mediatek.txt +++ b/Documentation/devicetree/bindings/arm/mediatek.txt @@ -10,6 +10,7 @@ compatible: Must contain one of "mediatek,mt6580" "mediatek,mt6589" "mediatek,mt6592" + "mediatek,mt6755" "mediatek,mt6795" "mediatek,mt7623" "mediatek,mt8127" @@ -31,6 +32,9 @@ Supported boards: - Evaluation board for MT6592: Required root node properties: - compatible = "mediatek,mt6592-evb", "mediatek,mt6592"; +- Evaluation phone for MT6755(Helio P10): + Required root node properties: + - compatible = "mediatek,mt6755-evb", "mediatek,mt6755"; - Evaluation board for MT6795(Helio X10): Required root node properties: - compatible = "mediatek,mt6795-evb", "mediatek,mt6795"; diff --git a/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt b/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt index 8cf564d..9d1d72c 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt @@ -9,6 +9,7 @@ Required properties: "mediatek,mt8135-sysirq" "mediatek,mt8127-sysirq" "mediatek,mt6795-sysirq" + "mediatek,mt6755-sysirq" "mediatek,mt6592-sysirq" "mediatek,mt6589-sysirq" "mediatek,mt6582-sysirq" diff --git a/Documentation/devicetree/bindings/serial/mtk-uart.txt b/Documentation/devicetree/bindings/serial/mtk-uart.txt index e99e10a..0015c72 100644 --- a/Documentation/devicetree/bindings/serial/mtk-uart.txt +++ b/Documentation/devicetree/bindings/serial/mtk-uart.txt @@ -6,6 +6,7 @@ Required properties: * "mediatek,mt6580-uart" for MT6580 compatible UARTS * "mediatek,mt6582-uart" for MT6582 compatible UARTS * "mediatek,mt6589-uart" for MT6589 compatible UARTS + * "mediatek,mt6755-uart" for MT6755 compatible UARTS * "mediatek,mt6795-uart" for MT6795 compatible UARTS * "mediatek,mt7623-uart" for MT7623 compatible UARTS * "mediatek,mt8127-uart" for MT8127 compatible UARTS -- cgit v0.10.2 From aea1c315b6395920bbeb69804e0355e57c67e086 Mon Sep 17 00:00:00 2001 From: Mars Cheng Date: Wed, 29 Jun 2016 10:09:33 +0800 Subject: arm64: dts: mediatek: add mt6755 support This adds basic chip support for MT6755 SoC. Signed-off-by: Mars Cheng Signed-off-by: Matthias Brugger diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile index e0a4bff..9fbfd32 100644 --- a/arch/arm64/boot/dts/mediatek/Makefile +++ b/arch/arm64/boot/dts/mediatek/Makefile @@ -1,3 +1,4 @@ +dtb-$(CONFIG_ARCH_MEDIATEK) += mt6755-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt6795-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-evb.dtb diff --git a/arch/arm64/boot/dts/mediatek/mt6755-evb.dts b/arch/arm64/boot/dts/mediatek/mt6755-evb.dts new file mode 100644 index 0000000..c568d49 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt6755-evb.dts @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2016 MediaTek Inc. + * Author: Mars.C + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +#include "mt6755.dtsi" + +/ { + model = "MediaTek MT6755 EVB"; + compatible = "mediatek,mt6755-evb", "mediatek,mt6755"; + + aliases { + serial0 = &uart0; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0 0x40000000 0 0x1e800000>; + }; + + chosen { + stdout-path = "serial0:921600n8"; + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt6755.dtsi b/arch/arm64/boot/dts/mediatek/mt6755.dtsi new file mode 100644 index 0000000..01ba776 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt6755.dtsi @@ -0,0 +1,145 @@ +/* + * Copyright (c) 2016 MediaTek Inc. + * Author: Mars.C + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include + +/ { + compatible = "mediatek,mt6755"; + interrupt-parent = <&sysirq>; + #address-cells = <2>; + #size-cells = <2>; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + enable-method = "psci"; + reg = <0x000>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + enable-method = "psci"; + reg = <0x001>; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + enable-method = "psci"; + reg = <0x002>; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + enable-method = "psci"; + reg = <0x003>; + }; + + cpu4: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + enable-method = "psci"; + reg = <0x100>; + }; + + cpu5: cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + enable-method = "psci"; + reg = <0x101>; + }; + + cpu6: cpu@102 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + enable-method = "psci"; + reg = <0x102>; + }; + + cpu7: cpu@103 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + enable-method = "psci"; + reg = <0x103>; + }; + }; + + uart_clk: dummy26m { + compatible = "fixed-clock"; + clock-frequency = <26000000>; + #clock-cells = <0>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&gic>; + interrupts = , + , + , + ; + }; + + sysirq: intpol-controller@10200620 { + compatible = "mediatek,mt6755-sysirq", + "mediatek,mt6577-sysirq"; + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + reg = <0 0x10200620 0 0x20>; + }; + + gic: interrupt-controller@10231000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + interrupt-controller; + reg = <0 0x10231000 0 0x1000>, + <0 0x10232000 0 0x2000>, + <0 0x10234000 0 0x2000>, + <0 0x10236000 0 0x2000>; + }; + + uart0: serial@11002000 { + compatible = "mediatek,mt6755-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11002000 0 0x400>; + interrupts = ; + clocks = <&uart_clk>; + status = "disabled"; + }; + + uart1: serial@11003000 { + compatible = "mediatek,mt6755-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11003000 0 0x400>; + interrupts = ; + clocks = <&uart_clk>; + status = "disabled"; + }; +}; -- cgit v0.10.2 From ddeba40b057356d60fc7851bf26224ef8e84cadc Mon Sep 17 00:00:00 2001 From: Gregory CLEMENT Date: Wed, 25 May 2016 13:25:52 +0200 Subject: arm64: dts: marvell: Add xtal clock support for Armada 3700 The configuration of the clock depend of the gpio latch. This information is stored in the gpio block registers. That's why the block is shared using a syscon node. Signed-off-by: Gregory CLEMENT diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi index 9e2efb8..7c61e13 100644 --- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi @@ -105,6 +105,18 @@ status = "disabled"; }; + gpio1: gpio@13800 { + compatible = "marvell,mvebu-gpio-3700", + "syscon", "simple-mfd"; + reg = <0x13800 0x500>; + + xtalclk: xtal-clk { + compatible = "marvell,armada-3700-xtal-clock"; + clock-output-names = "xtal"; + #clock-cells = <0>; + }; + }; + usb3: usb@58000 { compatible = "marvell,armada3700-xhci", "generic-xhci"; -- cgit v0.10.2 From e3e1a55edad79aa42a2e5487ac6afadf494cf882 Mon Sep 17 00:00:00 2001 From: Gregory CLEMENT Date: Tue, 17 May 2016 11:28:04 +0200 Subject: arm64: dts: marvell: add tbg clocks for Armada 37xx Add a new block of clocks. The Time Base Generators clocks can be the parent of the peripheral clocks. Signed-off-by: Gregory CLEMENT diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi index 7c61e13..e9f0b97 100644 --- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi @@ -105,6 +105,13 @@ status = "disabled"; }; + tbg: tbg@13200 { + compatible = "marvell,armada-3700-tbg-clock"; + reg = <0x13200 0x100>; + clocks = <&xtalclk>; + #clock-cells = <1>; + }; + gpio1: gpio@13800 { compatible = "marvell,mvebu-gpio-3700", "syscon", "simple-mfd"; -- cgit v0.10.2 From 5f4beef6db3c158ed99573d74e93dfe0611352e4 Mon Sep 17 00:00:00 2001 From: Gregory CLEMENT Date: Wed, 25 May 2016 13:42:43 +0200 Subject: arm64: dts: marvell: add peripherals clocks for Armada 37xx Add two new blocks of clocks. The peripheral clocks are the source clocks of the peripheral of the Armada 3700 SoC. Signed-off-by: Gregory CLEMENT diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi index e9f0b97..eb29280 100644 --- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi @@ -105,6 +105,22 @@ status = "disabled"; }; + nb_perih_clk: nb-periph-clk@13000{ + compatible = "marvell,armada-3700-periph-clock-nb"; + reg = <0x13000 0x100>; + clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>, + <&tbg 3>, <&xtalclk>; + #clock-cells = <1>; + }; + + sb_perih_clk: sb-periph-clk@18000{ + compatible = "marvell,armada-3700-periph-clock-sb"; + reg = <0x18000 0x100>; + clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>, + <&tbg 3>, <&xtalclk>; + #clock-cells = <1>; + }; + tbg: tbg@13200 { compatible = "marvell,armada-3700-tbg-clock"; reg = <0x13200 0x100>; -- cgit v0.10.2 From a1924466b784fbb64f10eeb213d335e3d1728b8b Mon Sep 17 00:00:00 2001 From: Abhilash Kesavan Date: Wed, 6 Jul 2016 01:58:57 +0530 Subject: arm64: dts: exynos: Modify the voltage range for BUCK2 for exynos7 Change the BUCK2 (vdd_atlas) voltage range to '500 - 1200mv' since CPU DVFS requires it. Signed-off-by: Abhilash Kesavan Signed-off-by: Krzysztof Kozlowski diff --git a/arch/arm64/boot/dts/exynos/exynos7-espresso.dts b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts index d8767b0..299f3ce 100644 --- a/arch/arm64/boot/dts/exynos/exynos7-espresso.dts +++ b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts @@ -249,7 +249,7 @@ buck2_reg: BUCK2 { regulator-name = "vdd_atlas"; - regulator-min-microvolt = <1200000>; + regulator-min-microvolt = <500000>; regulator-max-microvolt = <1200000>; regulator-always-on; regulator-boot-on; -- cgit v0.10.2 From a5547642a4e08c98edeaf4b62f6da0ac8ed2f6bd Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 10 Jun 2016 12:06:45 +0200 Subject: arm64: dts: r8a7795: Add missing blank lines between cpu nodes For consistency with a57_0/a57_1 cpu nodes, and all other nodes. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi index 04eb0bc..fad6dd8 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi @@ -53,6 +53,7 @@ next-level-cache = <&L2_CA57>; enable-method = "psci"; }; + a57_2: cpu@2 { compatible = "arm,cortex-a57","arm,armv8"; reg = <0x2>; @@ -61,6 +62,7 @@ next-level-cache = <&L2_CA57>; enable-method = "psci"; }; + a57_3: cpu@3 { compatible = "arm,cortex-a57","arm,armv8"; reg = <0x3>; -- cgit v0.10.2 From 162cd7845d5e9e16663079cc589046b3e588c104 Mon Sep 17 00:00:00 2001 From: Ramesh Shanmugasundaram Date: Fri, 17 Jun 2016 13:35:43 +0100 Subject: arm64: dts: r8a7795: Add CAN FD support Adds CAN FD controller node for r8a7795. Note: CAN FD controller register base address specified in R-Car Gen3 Hardware User Manual v0.5E is incorrect. The correct address is: CAN FD - 0xe66c0000 Signed-off-by: Ramesh Shanmugasundaram Signed-off-by: Simon Horman diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi index fad6dd8..b902356 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi @@ -583,6 +583,30 @@ status = "disabled"; }; + canfd: can@e66c0000 { + compatible = "renesas,r8a7795-canfd", + "renesas,rcar-gen3-canfd"; + reg = <0 0xe66c0000 0 0x8000>; + interrupts = , + ; + clocks = <&cpg CPG_MOD 914>, + <&cpg CPG_CORE R8A7795_CLK_CANFD>, + <&can_clk>; + clock-names = "fck", "canfd", "can_clk"; + assigned-clocks = <&cpg CPG_CORE R8A7795_CLK_CANFD>; + assigned-clock-rates = <40000000>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + status = "disabled"; + + channel0 { + status = "disabled"; + }; + + channel1 { + status = "disabled"; + }; + }; + hscif0: serial@e6540000 { compatible = "renesas,hscif-r8a7795", "renesas,rcar-gen3-hscif", -- cgit v0.10.2 From 1561f20760ec96db4d6808b09f3a691edc22f937 Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Tue, 24 May 2016 10:54:38 +0900 Subject: arm64: dts: r8a7796: Add Renesas R8A7796 SoC support Basic support for the Gen 3 R-Car M3-W SoC. Based on work for the r8a7795 and r8a7796 SoCs by Takeshi Kihara, Dirk Behme and Geert Uytterhoeven. Signed-off-by: Simon Horman Reviewed-by: Geert Uytterhoeven diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt b/Documentation/devicetree/bindings/arm/shmobile.txt index 9cf67e4..d5ed554 100644 --- a/Documentation/devicetree/bindings/arm/shmobile.txt +++ b/Documentation/devicetree/bindings/arm/shmobile.txt @@ -29,6 +29,8 @@ SoCs: compatible = "renesas,r8a7794" - R-Car H3 (R8A77950) compatible = "renesas,r8a7795" + - R-Car M3-W (R8A77960) + compatible = "renesas,r8a7796" Boards: @@ -61,5 +63,7 @@ Boards: compatible = "renesas,porter", "renesas,r8a7791" - Salvator-X (RTP0RC7795SIPB0010S) compatible = "renesas,salvator-x", "renesas,r8a7795"; + - Salvator-X + compatible = "renesas,salvator-x", "renesas,r8a7796"; - SILK (RTP0RC7794LCB00011S) compatible = "renesas,silk", "renesas,r8a7794" diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 7ef1d05..2182fd5 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -121,6 +121,12 @@ config ARCH_R8A7795 help This enables support for the Renesas R-Car H3 SoC. +config ARCH_R8A7796 + bool "Renesas R-Car M3-W SoC Platform" + depends on ARCH_RENESAS + help + This enables support for the Renesas R-Car M3-W SoC. + config ARCH_STRATIX10 bool "Altera's Stratix 10 SoCFPGA Family" help diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi new file mode 100644 index 0000000..178debf --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi @@ -0,0 +1,120 @@ +/* + * Device Tree Source for the r8a7796 SoC + * + * Copyright (C) 2016 Renesas Electronics Corp. + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +#include +#include + +/ { + compatible = "renesas,r8a7796"; + #address-cells = <2>; + #size-cells = <2>; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + /* 1 core only at this point */ + a57_0: cpu@0 { + compatible = "arm,cortex-a57", "arm,armv8"; + reg = <0x0>; + device_type = "cpu"; + next-level-cache = <&L2_CA57>; + enable-method = "psci"; + }; + + L2_CA57: cache-controller@0 { + compatible = "cache"; + reg = <0>; + cache-unified; + cache-level = <2>; + }; + }; + + extal_clk: extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + extalr_clk: extalr { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + /* External SCIF clock - to be overridden by boards that provide it */ + scif_clk: scif { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + soc { + compatible = "simple-bus"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gic: interrupt-controller@f1010000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x0 0xf1010000 0 0x1000>, + <0x0 0xf1020000 0 0x20000>, + <0x0 0xf1040000 0 0x20000>, + <0x0 0xf1060000 0 0x20000>; + interrupts = ; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; + + cpg: clock-controller@e6150000 { + compatible = "renesas,r8a7796-cpg-mssr"; + reg = <0 0xe6150000 0 0x1000>; + clocks = <&extal_clk>, <&extalr_clk>; + clock-names = "extal", "extalr"; + #clock-cells = <2>; + #power-domain-cells = <0>; + }; + + scif2: serial@e6e88000 { + compatible = "renesas,scif-r8a7796", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6e88000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 310>, + <&cpg CPG_CORE R8A7796_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + power-domains = <&cpg>; + status = "disabled"; + }; + }; +}; -- cgit v0.10.2 From 006e1db8f7beb4525639bb82f544e01cc41129a9 Mon Sep 17 00:00:00 2001 From: Takeshi Kihara Date: Tue, 24 May 2016 10:54:39 +0900 Subject: arm64: dts: salvator-x: add Salvator-X board on R8A7796 SoC This patch adds initial board support for R8A7796 Salvator-X. Signed-off-by: Takeshi Kihara Signed-off-by: Simon Horman Reviewed-by: Geert Uytterhoeven diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile index 9ce1890..17139f7 100644 --- a/arch/arm64/boot/dts/renesas/Makefile +++ b/arch/arm64/boot/dts/renesas/Makefile @@ -1,4 +1,5 @@ dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-salvator-x.dtb +dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-salvator-x.dtb always := $(dtb-y) clean-files := *.dtb diff --git a/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts new file mode 100644 index 0000000..9c52613 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts @@ -0,0 +1,45 @@ +/* + * Device Tree Source for the Salvator-X board + * + * Copyright (C) 2016 Renesas Electronics Corp. + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +/dts-v1/; +#include "r8a7796.dtsi" + +/ { + model = "Renesas Salvator-X board based on r8a7796"; + compatible = "renesas,salvator-x", "renesas,r8a7796"; + + aliases { + serial0 = &scif2; + }; + + chosen { + bootargs = "ignore_loglevel"; + stdout-path = "serial0:115200n8"; + }; + + memory@48000000 { + device_type = "memory"; + /* first 128MB is reserved for secure area. */ + reg = <0x0 0x48000000 0x0 0x78000000>; + }; +}; + +&extal_clk { + clock-frequency = <16666666>; +}; + +&scif2 { + status = "okay"; +}; + +&scif_clk { + clock-frequency = <14745600>; + status = "okay"; +}; -- cgit v0.10.2 From 56aebae0003f8987cf1f07238ec9e6243fe88080 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 31 May 2016 11:08:44 +0200 Subject: arm64: dts: r8a7796: Add SYSC PM Domains Add a device node for the System Controller. Hook up the Cortex-A57 CPU core and L2 cache/SCU to their respective PM Domains. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi index 178debf..85f0843 100644 --- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi @@ -10,6 +10,7 @@ #include #include +#include / { compatible = "renesas,r8a7796"; @@ -30,6 +31,7 @@ compatible = "arm,cortex-a57", "arm,armv8"; reg = <0x0>; device_type = "cpu"; + power-domains = <&sysc R8A7796_PD_CA57_CPU0>; next-level-cache = <&L2_CA57>; enable-method = "psci"; }; @@ -37,6 +39,7 @@ L2_CA57: cache-controller@0 { compatible = "cache"; reg = <0>; + power-domains = <&sysc R8A7796_PD_CA57_SCU>; cache-unified; cache-level = <2>; }; @@ -104,6 +107,12 @@ #power-domain-cells = <0>; }; + sysc: system-controller@e6180000 { + compatible = "renesas,r8a7796-sysc"; + reg = <0 0xe6180000 0 0x0400>; + #power-domain-cells = <1>; + }; + scif2: serial@e6e88000 { compatible = "renesas,scif-r8a7796", "renesas,rcar-gen3-scif", "renesas,scif"; -- cgit v0.10.2 From a9003187a984ea835b5533165d97733303c5399e Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 31 May 2016 11:08:45 +0200 Subject: arm64: dts: r8a7796: Use SYSC "always-on" PM Domain Hook up all devices that are part of the CPG/MSSR Clock Domain to the SYSC "always-on" PM Domain, for a more consistent device-power-area description in DT. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi index 85f0843..fab61ed 100644 --- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi @@ -122,7 +122,7 @@ <&cpg CPG_CORE R8A7796_CLK_S3D1>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; - power-domains = <&cpg>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; status = "disabled"; }; }; -- cgit v0.10.2 From c8ce8007e5c0678fe40e3e401f68ee0b9e74ee92 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 27 Jun 2016 19:50:46 +0200 Subject: arm64: dts: r8a7796: Add RWDT node Add a device node for the Watchdog Timer (WDT) controller on the Renesas R-Car M3-W (r8a7796) SoC. Signed-off-by: Geert Uytterhoeven Acked-by: Wolfram Sang Signed-off-by: Simon Horman diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi index fab61ed..1edf824 100644 --- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi @@ -98,6 +98,15 @@ (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; }; + wdt0: watchdog@e6020000 { + compatible = "renesas,r8a7796-wdt", + "renesas,rcar-gen3-wdt"; + reg = <0 0xe6020000 0 0x0c>; + clocks = <&cpg CPG_MOD 402>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + status = "disabled"; + }; + cpg: clock-controller@e6150000 { compatible = "renesas,r8a7796-cpg-mssr"; reg = <0 0xe6150000 0 0x1000>; -- cgit v0.10.2 From c805f1a7013a76ae63c002e52cc667d7c37228ea Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 27 Jun 2016 19:50:47 +0200 Subject: arm64: dts: r8a7796/salvator-x: Enable watchdog timer Enable the Watchdog Timer (WDT) controller on the Renesas Salvator-X board equipped with an R-Car M3-W (r8a7796) SoC. Signed-off-by: Geert Uytterhoeven Acked-by: Wolfram Sang Signed-off-by: Simon Horman diff --git a/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts index 9c52613..e72be38 100644 --- a/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts +++ b/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts @@ -43,3 +43,8 @@ clock-frequency = <14745600>; status = "okay"; }; + +&wdt0 { + timeout-sec = <60>; + status = "okay"; +}; -- cgit v0.10.2 From 810bd15fe0f049233ce6b89e1fbfaaff124be8c2 Mon Sep 17 00:00:00 2001 From: Zhangfei Gao Date: Wed, 29 Jun 2016 17:48:45 -0700 Subject: arm64: dts: hi6220: Add pl031 RTC support Add pl031 rtc0 and rtc1 support to hi6220 dtsi Cc: Michael Turquette Cc: Stephen Boyd Cc: Rob Herring Cc: Pawel Moll Cc: Wei Xu Cc: Guodong Xu Signed-off-by: Zhangfei Gao [jstultz: Forward ported and tweaked commit description, added rtc1 entry as suggested by Guodong] Signed-off-by: John Stultz Signed-off-by: Wei Xu diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi index 189d215..758fd22 100644 --- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi @@ -336,6 +336,22 @@ clock-names = "timer1", "timer2", "apb_pclk"; }; + rtc0: rtc@f8003000 { + compatible = "arm,pl031", "arm,primecell"; + reg = <0x0 0xf8003000 0x0 0x1000>; + interrupts = <0 12 4>; + clocks = <&ao_ctrl HI6220_RTC0_PCLK>; + clock-names = "apb_pclk"; + }; + + rtc1: rtc@f8004000 { + compatible = "arm,pl031", "arm,primecell"; + reg = <0x0 0xf8004000 0x0 0x1000>; + interrupts = <0 8 4>; + clocks = <&ao_ctrl HI6220_RTC1_PCLK>; + clock-names = "apb_pclk"; + }; + pmx0: pinmux@f7010000 { compatible = "pinctrl-single"; reg = <0x0 0xf7010000 0x0 0x27c>; -- cgit v0.10.2 From 8d09251a81ecc22e542c3ff6a7dd3ca2b7e2b0e7 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Thu, 7 Jul 2016 17:51:35 +0200 Subject: Revert "ARM64: DTS: meson-gxbb: switch ethernet to real clock" This reverts commit f3abd6296168, which caused a build regression: arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi:48:41: fatal error: dt-bindings/clock/gxbb-clkc.h: No such file or directory We should apply this patch one merge window later, once the clk branch is merged as well. Signed-off-by: Arnd Bergmann diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi index 35c8b2b..e502c24 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi @@ -45,7 +45,6 @@ #include #include #include -#include / { compatible = "amlogic,meson-gxbb"; @@ -338,7 +337,7 @@ 0x0 0xc8834540 0x0 0x4>; interrupts = <0 8 1>; interrupt-names = "macirq"; - clocks = <&clkc CLKID_ETH>; + clocks = <&xtal>; clock-names = "stmmaceth"; phy-mode = "rgmii"; status = "disabled"; -- cgit v0.10.2 From 77934269438e1a4a32f1b9a357f39422f58dcf89 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Mon, 23 Nov 2015 16:20:35 +0100 Subject: arm64: tegra: Add PMIC support on Jetson TX1 Add a device tree node for the MAX77620 PMIC found on the p2180 processor module (Jetson TX1). Also add supporting power supplies, such as the main 5 V system supply. Signed-off-by: Thierry Reding diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi index 316c92c..8335bbe 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi @@ -1,3 +1,5 @@ +#include + #include "tegra210.dtsi" / { @@ -5,6 +7,7 @@ compatible = "nvidia,p2180", "nvidia,tegra210"; aliases { + rtc0 = "/i2c@7000d000/pmic@3c"; rtc1 = "/rtc@7000e000"; serial0 = &uarta; }; @@ -19,6 +22,248 @@ status = "okay"; }; + i2c@7000d000 { + status = "okay"; + clock-frequency = <400000>; + + pmic: pmic@3c { + compatible = "maxim,max77620"; + reg = <0x3c>; + interrupts = ; + + #interrupt-cells = <2>; + interrupt-controller; + + #gpio-cells = <2>; + gpio-controller; + + pinctrl-names = "default"; + pinctrl-0 = <&max77620_default>; + + max77620_default: pinmux { + gpio0 { + pins = "gpio0"; + function = "gpio"; + }; + + gpio1 { + pins = "gpio1"; + function = "fps-out"; + drive-push-pull = <1>; + maxim,active-fps-source = ; + maxim,active-fps-power-up-slot = <7>; + maxim,active-fps-power-down-slot = <0>; + }; + + gpio2_3 { + pins = "gpio2", "gpio3"; + function = "fps-out"; + drive-open-drain = <1>; + maxim,active-fps-source = ; + }; + + gpio4 { + pins = "gpio4"; + function = "32k-out1"; + }; + + gpio5_6_7 { + pins = "gpio5", "gpio6", "gpio7"; + function = "gpio"; + drive-push-pull = <1>; + }; + }; + + fps { + fps0 { + maxim,fps-event-source = ; + maxim,suspend-fps-time-period-us = <1280>; + }; + + fps1 { + maxim,fps-event-source = ; + maxim,suspend-fps-time-period-us = <1280>; + }; + + fps2 { + maxim,fps-event-source = ; + }; + }; + + regulators { + in-ldo0-1-supply = <&vdd_pre>; + in-ldo7-8-supply = <&vdd_pre>; + in-sd3-supply = <&vdd_5v0_sys>; + + vdd_soc: sd0 { + regulator-name = "VDD_SOC"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1400000>; + regulator-always-on; + regulator-boot-on; + + regulator-enable-ramp-delay = <146>; + regulator-ramp-delay = <27500>; + + maxim,active-fps-source = ; + }; + + vdd_ddr: sd1 { + regulator-name = "VDD_DDR_1V1_PMIC"; + regulator-always-on; + regulator-boot-on; + + regulator-enable-ramp-delay = <130>; + regulator-ramp-delay = <27500>; + + maxim,active-fps-source = ; + }; + + vdd_pre: sd2 { + regulator-name = "VDD_PRE_REG_1V35"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + + regulator-enable-ramp-delay = <176>; + regulator-ramp-delay = <27500>; + + maxim,active-fps-source = ; + }; + + vdd_1v8: sd3 { + regulator-name = "VDD_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + + regulator-enable-ramp-delay = <242>; + regulator-ramp-delay = <27500>; + + maxim,active-fps-source = ; + }; + + vdd_sys_1v2: ldo0 { + regulator-name = "AVDD_SYS_1V2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + + regulator-enable-ramp-delay = <26>; + regulator-ramp-delay = <100000>; + + maxim,active-fps-source = ; + }; + + vdd_pex_1v05: ldo1 { + regulator-name = "VDD_PEX_1V05"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + + regulator-enable-ramp-delay = <22>; + regulator-ramp-delay = <100000>; + + maxim,active-fps-source = ; + }; + + vddio_sdmmc: ldo2 { + regulator-name = "VDDIO_SDMMC"; + /* + * Technically this supply should have + * a supported range from 1.8 - 3.3 V. + * However, that would cause the SDHCI + * driver to request 2.7 V upon access + * and that in turn will cause traffic + * to be broken. Leave it at 3.3 V for + * now. + */ + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + + regulator-enable-ramp-delay = <62>; + regulator-ramp-delay = <100000>; + + maxim,active-fps-source = ; + }; + + vdd_cam_hv: ldo3 { + regulator-name = "VDD_CAM_HV"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + + regulator-enable-ramp-delay = <50>; + regulator-ramp-delay = <100000>; + + maxim,active-fps-source = ; + }; + + vdd_rtc: ldo4 { + regulator-name = "VDD_RTC"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-always-on; + regulator-boot-on; + + regulator-enable-ramp-delay = <22>; + regulator-ramp-delay = <100000>; + + maxim,active-fps-source = ; + }; + + vdd_ts_hv: ldo5 { + regulator-name = "VDD_TS_HV"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-enable-ramp-delay = <62>; + regulator-ramp-delay = <100000>; + + maxim,active-fps-source = ; + }; + + vdd_ts: ldo6 { + regulator-name = "VDD_TS_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-enable-ramp-delay = <36>; + regulator-ramp-delay = <100000>; + + maxim,active-fps-source = ; + maxim,active-fps-power-up-slot = <7>; + maxim,active-fps-power-down-slot = <0>; + }; + + avdd_1v05_pll: ldo7 { + regulator-name = "AVDD_1V05_PLL"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + regulator-always-on; + regulator-boot-on; + + regulator-enable-ramp-delay = <24>; + regulator-ramp-delay = <100000>; + + maxim,active-fps-source = ; + }; + + avdd_1v05: ldo8 { + regulator-name = "AVDD_SATA_HDMI_DP_1V05"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + + regulator-enable-ramp-delay = <22>; + regulator-ramp-delay = <100000>; + + maxim,active-fps-source = ; + }; + }; + }; + }; + pmc@7000e400 { nvidia,invert-interrupt; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi index a2480c0..27bb835 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi @@ -1270,6 +1270,61 @@ cd-gpios = <&gpio TEGRA_GPIO(Z, 1) GPIO_ACTIVE_LOW>; }; + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + vdd_sys_mux: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "VDD_SYS_MUX"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_5v0_sys: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "VDD_5V0_SYS"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + gpio = <&pmic 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_sys_mux>; + }; + + vdd_3v3_sys: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "VDD_3V3_SYS"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + gpio = <&pmic 3 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_sys_mux>; + + regulator-enable-ramp-delay = <160>; + regulator-disable-ramp-delay = <10000>; + }; + + vdd_5v0_io: regulator@3 { + compatible = "regulator-fixed"; + reg = <3>; + regulator-name = "VDD_5V0_IO_SYS"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + }; + gpio-keys { compatible = "gpio-keys"; label = "gpio-keys"; -- cgit v0.10.2 From 6d5aef5b9517974a181d06b0bed4bc66b32f3660 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 4 Mar 2016 15:26:47 +0100 Subject: arm64: tegra: p2597: Add SDMMC power supplies Add power supplies for the SD/MMC card slot. Note that vmmc-supply is currently restricted to 3.3 V because we don't support switching the mode yet. Signed-off-by: Thierry Reding diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi index 27bb835..b28aff5 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi @@ -1268,6 +1268,9 @@ no-1-8-v; cd-gpios = <&gpio TEGRA_GPIO(Z, 1) GPIO_ACTIVE_LOW>; + + vqmmc-supply = <&vddio_sdmmc>; + vmmc-supply = <&vdd_3v3_sd>; }; regulators { @@ -1323,6 +1326,20 @@ regulator-always-on; regulator-boot-on; }; + + vdd_3v3_sd: regulator@4 { + compatible = "regulator-fixed"; + reg = <4>; + regulator-name = "VDD_3V3_SD"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio TEGRA_GPIO(Z, 4) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_3v3_sys>; + + regulator-enable-ramp-delay = <472>; + regulator-disable-ramp-delay = <4880>; + }; }; gpio-keys { -- cgit v0.10.2 From 7596723ecd54456da4b8bc5afc4a961aa09bd34b Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Mon, 23 Nov 2015 16:21:43 +0100 Subject: arm64: tegra: Add DSI panel on Jetson TX1 Some variants of the Jetson TX1 ship with a 8.0" WUXGA TFT LCD panel connected via four DSI lanes. Signed-off-by: Thierry Reding diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts b/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts index 683b339..983775e 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts @@ -6,4 +6,49 @@ / { model = "NVIDIA Jetson TX1 Developer Kit"; compatible = "nvidia,p2371-2180", "nvidia,tegra210"; + + host1x@50000000 { + dsi@54300000 { + status = "okay"; + + avdd-dsi-csi-supply = <&vdd_dsi_csi>; + + panel@0 { + compatible = "auo,b080uan01"; + reg = <0>; + + enable-gpios = <&gpio TEGRA_GPIO(V, 2) + GPIO_ACTIVE_HIGH>; + power-supply = <&vdd_5v0_io>; + backlight = <&backlight>; + }; + }; + }; + + i2c@7000c400 { + backlight: backlight@2c { + compatible = "ti,lp8557"; + reg = <0x2c>; + + dev-ctrl = /bits/ 8 <0x80>; + init-brt = /bits/ 8 <0xff>; + + pwm-period = <29334>; + + pwms = <&pwm 0 29334>; + pwm-names = "lp8557"; + + /* 3 LED string */ + rom_14h { + rom-addr = /bits/ 8 <0x14>; + rom-val = /bits/ 8 <0x87>; + }; + + /* boost frequency 1 MHz */ + rom_13h { + rom-addr = /bits/ 8 <0x13>; + rom-val = /bits/ 8 <0x01>; + }; + }; + }; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi index b28aff5..78a16a5 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi @@ -1261,6 +1261,23 @@ }; }; + pwm@7000a000 { + status = "okay"; + }; + + i2c@7000c400 { + status = "okay"; + clock-frequency = <100000>; + + exp1: gpio@74 { + compatible = "ti,tca9539"; + reg = <0x74>; + + #gpio-cells = <2>; + gpio-controller; + }; + }; + /* MMC/SD */ sdhci@700b0000 { status = "okay"; @@ -1340,6 +1357,39 @@ regulator-enable-ramp-delay = <472>; regulator-disable-ramp-delay = <4880>; }; + + vdd_dsi_csi: regulator@5 { + compatible = "regulator-fixed"; + reg = <5>; + regulator-name = "AVDD_DSI_CSI_1V2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + vin-supply = <&vdd_sys_1v2>; + }; + + vdd_3v3_dis: regulator@6 { + compatible = "regulator-fixed"; + reg = <6>; + regulator-name = "VDD_DIS_3V3_LCD"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + gpio = <&exp1 3 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_3v3_sys>; + }; + + vdd_1v8_dis: regulator@7 { + compatible = "regulator-fixed"; + reg = <7>; + regulator-name = "VDD_LCD_1V8_DIS"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + gpio = <&exp1 14 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_1v8>; + }; }; gpio-keys { -- cgit v0.10.2 From 4e07ac9076beb1341a919c55f3a080d4fe991882 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 12 Nov 2015 11:28:35 +0100 Subject: arm64: tegra: Add Tegra210 XUSB pad controller Add a device tree node for the XUSB pad controller found on Tegra210. Signed-off-by: Thierry Reding diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index 76fe31f..694228b 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -621,6 +621,161 @@ status = "disabled"; }; + padctl: padctl@7009f000 { + compatible = "nvidia,tegra210-xusb-padctl"; + reg = <0x0 0x7009f000 0x0 0x1000>; + resets = <&tegra_car 142>; + reset-names = "padctl"; + + status = "disabled"; + + pads { + usb2 { + clocks = <&tegra_car TEGRA210_CLK_USB2_TRK>; + clock-names = "trk"; + status = "disabled"; + + lanes { + usb2-0 { + status = "disabled"; + #phy-cells = <0>; + }; + + usb2-1 { + status = "disabled"; + #phy-cells = <0>; + }; + + usb2-2 { + status = "disabled"; + #phy-cells = <0>; + }; + + usb2-3 { + status = "disabled"; + #phy-cells = <0>; + }; + }; + }; + + hsic { + clocks = <&tegra_car TEGRA210_CLK_HSIC_TRK>; + clock-names = "trk"; + status = "disabled"; + + lanes { + hsic-0 { + status = "disabled"; + #phy-cells = <0>; + }; + + hsic-1 { + status = "disabled"; + #phy-cells = <0>; + }; + }; + }; + + pcie { + clocks = <&tegra_car TEGRA210_CLK_PLL_E>; + clock-names = "pll"; + resets = <&tegra_car 205>; + reset-names = "phy"; + status = "disabled"; + + lanes { + pcie-0 { + status = "disabled"; + #phy-cells = <0>; + }; + + pcie-1 { + status = "disabled"; + #phy-cells = <0>; + }; + + pcie-2 { + status = "disabled"; + #phy-cells = <0>; + }; + + pcie-3 { + status = "disabled"; + #phy-cells = <0>; + }; + + pcie-4 { + status = "disabled"; + #phy-cells = <0>; + }; + + pcie-5 { + status = "disabled"; + #phy-cells = <0>; + }; + + pcie-6 { + status = "disabled"; + #phy-cells = <0>; + }; + }; + }; + + sata { + clocks = <&tegra_car TEGRA210_CLK_PLL_E>; + clock-names = "pll"; + resets = <&tegra_car 204>; + reset-names = "phy"; + status = "disabled"; + + lanes { + sata-0 { + status = "disabled"; + #phy-cells = <0>; + }; + }; + }; + }; + + ports { + usb2-0 { + status = "disabled"; + }; + + usb2-1 { + status = "disabled"; + }; + + usb2-2 { + status = "disabled"; + }; + + usb2-3 { + status = "disabled"; + }; + + hsic-0 { + status = "disabled"; + }; + + usb3-0 { + status = "disabled"; + }; + + usb3-1 { + status = "disabled"; + }; + + usb3-2 { + status = "disabled"; + }; + + usb3-3 { + status = "disabled"; + }; + }; + }; + sdhci@700b0000 { compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci"; reg = <0x0 0x700b0000 0x0 0x200>; -- cgit v0.10.2 From e7a99ac299924b714e2b7c9f36e435b89c035b3b Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 12 Nov 2015 11:28:36 +0100 Subject: arm64: tegra: Add Tegra210 XUSB controller Add a device tree node for the Tegra XUSB controller. It contains a phandle to the XUSB pad controller for control of the PHYs assigned to the USB ports. Signed-off-by: Thierry Reding diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index 694228b..ac1fb88 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -621,6 +621,41 @@ status = "disabled"; }; + usb@70090000 { + compatible = "nvidia,tegra210-xusb"; + reg = <0x0 0x70090000 0x0 0x8000>, + <0x0 0x70098000 0x0 0x1000>, + <0x0 0x70099000 0x0 0x1000>; + reg-names = "hcd", "fpci", "ipfs"; + + interrupts = , + ; + + clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>, + <&tegra_car TEGRA210_CLK_XUSB_HOST_SRC>, + <&tegra_car TEGRA210_CLK_XUSB_FALCON_SRC>, + <&tegra_car TEGRA210_CLK_XUSB_SS>, + <&tegra_car TEGRA210_CLK_XUSB_SS_DIV2>, + <&tegra_car TEGRA210_CLK_XUSB_SS_SRC>, + <&tegra_car TEGRA210_CLK_XUSB_HS_SRC>, + <&tegra_car TEGRA210_CLK_XUSB_FS_SRC>, + <&tegra_car TEGRA210_CLK_PLL_U_480M>, + <&tegra_car TEGRA210_CLK_CLK_M>, + <&tegra_car TEGRA210_CLK_PLL_E>; + clock-names = "xusb_host", "xusb_host_src", + "xusb_falcon_src", "xusb_ss", + "xusb_ss_div2", "xusb_ss_src", + "xusb_hs_src", "xusb_fs_src", + "pll_u_480m", "clk_m", "pll_e"; + resets = <&tegra_car 89>, <&tegra_car 156>, + <&tegra_car 143>; + reset-names = "xusb_host", "xusb_ss", "xusb_src"; + + nvidia,xusb-padctl = <&padctl>; + + status = "disabled"; + }; + padctl: padctl@7009f000 { compatible = "nvidia,tegra210-xusb-padctl"; reg = <0x0 0x7009f000 0x0 0x1000>; -- cgit v0.10.2 From 5593eb76b602e3ab2d525cdeecd49c0978e3b0e6 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 2 Jun 2016 14:07:47 +0200 Subject: arm64: tegra: Enable debug serial on Jetson TX1 Add a chosen node to the device tree that contains a stdout-path property which defines the debug serial port. Signed-off-by: Thierry Reding diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi index 8335bbe..5fda583 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi @@ -12,6 +12,10 @@ serial0 = &uarta; }; + chosen { + stdout-path = "serial0:115200n8"; + }; + memory { device_type = "memory"; reg = <0x0 0x80000000 0x1 0x0>; -- cgit v0.10.2 From d23e054c66ec3daa91ef4ea43d9a99ea65d4e8da Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 2 Jun 2016 14:22:41 +0200 Subject: arm64: tegra: Enable XUSB controller on Jetson TX1 Enable the XUSB controller on Jetson TX1. One of the USB 3.0 lanes goes to an internal ethernet interface, while a second USB 3.0 lane supports the USB-A receptacle on the I/O board. Signed-off-by: Thierry Reding diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi index 78a16a5..8bba178 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi @@ -1278,6 +1278,146 @@ }; }; + usb@70090000 { + phys = <&{/padctl@7009f000/pads/usb2/lanes/usb2-0}>, + <&{/padctl@7009f000/pads/usb2/lanes/usb2-1}>, + <&{/padctl@7009f000/pads/usb2/lanes/usb2-2}>, + <&{/padctl@7009f000/pads/usb2/lanes/usb2-3}>, + <&{/padctl@7009f000/pads/pcie/lanes/pcie-6}>, + <&{/padctl@7009f000/pads/pcie/lanes/pcie-5}>; + phy-names = "usb2-0", "usb2-1", "usb2-2", "usb2-3", "usb3-0", + "usb3-1"; + + dvddio-pex-supply = <&vdd_pex_1v05>; + hvddio-pex-supply = <&vdd_1v8>; + avdd-usb-supply = <&vdd_3v3_sys>; + /* XXX what are these? */ + avdd-pll-utmip-supply = <&vdd_1v8>; + avdd-pll-uerefe-supply = <&vdd_pex_1v05>; + dvdd-usb-ss-pll-supply = <&vdd_pex_1v05>; + hvdd-usb-ss-pll-e-supply = <&vdd_1v8>; + + status = "okay"; + }; + + padctl@7009f000 { + status = "okay"; + + pads { + usb2 { + status = "okay"; + + lanes { + usb2-0 { + nvidia,function = "xusb"; + status = "okay"; + }; + + usb2-1 { + nvidia,function = "xusb"; + status = "okay"; + }; + + usb2-2 { + nvidia,function = "xusb"; + status = "okay"; + }; + + usb2-3 { + nvidia,function = "xusb"; + status = "okay"; + }; + }; + }; + + pcie { + status = "okay"; + + lanes { + pcie-0 { + nvidia,function = "pcie-x1"; + status = "okay"; + }; + + pcie-1 { + nvidia,function = "pcie-x4"; + status = "okay"; + }; + + pcie-2 { + nvidia,function = "pcie-x4"; + status = "okay"; + }; + + pcie-3 { + nvidia,function = "pcie-x4"; + status = "okay"; + }; + + pcie-4 { + nvidia,function = "pcie-x4"; + status = "okay"; + }; + + pcie-5 { + nvidia,function = "usb3-ss"; + status = "okay"; + }; + + pcie-6 { + nvidia,function = "usb3-ss"; + status = "okay"; + }; + }; + }; + + sata { + status = "okay"; + + lanes { + sata-0 { + nvidia,function = "sata"; + status = "okay"; + }; + }; + }; + }; + + ports { + usb2-0 { + status = "okay"; + mode = "otg"; + }; + + usb2-1 { + status = "okay"; + vbus-supply = <&vdd_5v0_rtl>; + mode = "host"; + }; + + usb2-2 { + status = "okay"; + vbus-supply = <&vdd_usb_vbus>; + mode = "host"; + }; + + usb2-3 { + status = "okay"; + mode = "host"; + }; + + usb3-0 { + nvidia,usb2-companion = <1>; + status = "okay"; + }; + + usb3-1 { + nvidia,usb2-companion = <2>; + status = "okay"; + }; + }; + }; + /* MMC/SD */ sdhci@700b0000 { status = "okay"; @@ -1390,6 +1530,28 @@ enable-active-high; vin-supply = <&vdd_1v8>; }; + + vdd_5v0_rtl: regulator@8 { + compatible = "regulator-fixed"; + reg = <8>; + regulator-name = "RTL_5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_5v0_sys>; + }; + + vdd_usb_vbus: regulator@9 { + compatible = "regulator-fixed"; + reg = <9>; + regulator-name = "USB_VBUS_EN1"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA_GPIO(CC, 5) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_5v0_sys>; + }; }; gpio-keys { -- cgit v0.10.2 From 9168e1db754383ea16b75ffcc1efbb9b09cfae64 Mon Sep 17 00:00:00 2001 From: Jon Hunter Date: Wed, 29 Jun 2016 12:07:33 +0100 Subject: arm64: tegra: Correct Tegra210 XUSB mailbox interrupt The XUSB mailbox interrupt for Tegra210 is 40 and not 49 which is for the XUSB pad controller. For some Tegra210 boards, this is causing USB connect and disconnect events to go undetected. Fix this by changing the interrupt number for the XUSB mailbox to 40. Signed-off-by: Jon Hunter Signed-off-by: Thierry Reding diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index ac1fb88..b731880 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -629,7 +629,7 @@ reg-names = "hcd", "fpci", "ipfs"; interrupts = , - ; + ; clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>, <&tegra_car TEGRA210_CLK_XUSB_HOST_SRC>, -- cgit v0.10.2 From 1b4c8420225cfcc9e94ac62a9779d3de672e96d7 Mon Sep 17 00:00:00 2001 From: Rhyland Klein Date: Tue, 28 Jun 2016 17:28:24 -0400 Subject: arm64: tegra: Add regulators for Tegra210 Smaug Add regulators to the Tegra210 Smaug DTS file including support for the MAX77620 PMIC. Signed-off-by: Rhyland Klein Acked-by: Laxman Dewangan Signed-off-by: Thierry Reding diff --git a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts index 4d89f4e..431266a 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts @@ -1,6 +1,7 @@ /dts-v1/; #include +#include #include #include "tegra210.dtsi" @@ -1327,6 +1328,234 @@ }; }; + i2c@7000d000 { + status = "okay"; + clock-frequency = <1000000>; + + max77620: max77620@3c { + compatible = "maxim,max77620"; + reg = <0x3c>; + interrupts = <0 86 IRQ_TYPE_NONE>; + + #interrupt-cells = <2>; + interrupt-controller; + + gpio-controller; + #gpio-cells = <2>; + + pinctrl-names = "default"; + pinctrl-0 = <&max77620_default>; + + max77620_default: pinmux@0 { + pin_gpio { + pins = "gpio0", "gpio1", "gpio2", "gpio7"; + function = "gpio"; + }; + + /* + * GPIO3 is used to en_pp3300, and it is part of power + * sequence, So it must be sequenced up (automatically + * set by OTP) and down properly. + */ + pin_gpio3 { + pins = "gpio3"; + function = "fps-out"; + drive-open-drain = <1>; + maxim,active-fps-source = ; + maxim,active-fps-power-up-slot = <4>; + maxim,active-fps-power-down-slot = <2>; + }; + + pin_gpio5_6 { + pins = "gpio5", "gpio6"; + function = "gpio"; + drive-push-pull = <1>; + }; + + pin_32k { + pins = "gpio4"; + function = "32k-out1"; + }; + }; + + fps { + fps0 { + maxim,shutdown-fps-time-period-us = <5120>; + maxim,fps-event-source = ; + }; + + fps1 { + maxim,shutdown-fps-time-period-us = <5120>; + maxim,fps-event-source = ; + maxim,device-state-on-disabled-event = ; + }; + + fps2 { + maxim,fps-event-source = ; + }; + }; + + regulators { + in-ldo0-1-supply = <&pp1350>; + in-ldo2-supply = <&pp3300>; + in-ldo3-5-supply = <&pp3300>; + in-ldo7-8-supply = <&pp1350>; + + ppvar_soc: sd0 { + regulator-name = "PPVAR_SOC"; + regulator-min-microvolt = <825000>; + regulator-max-microvolt = <1125000>; + regulator-always-on; + regulator-boot-on; + maxim,active-fps-source = ; + maxim,active-fps-power-up-slot = <1>; + maxim,active-fps-power-down-slot = <7>; + }; + + pp1100_sd1: sd1 { + regulator-name = "PP1100"; + regulator-min-microvolt = <1125000>; + regulator-max-microvolt = <1125000>; + regulator-always-on; + regulator-boot-on; + maxim,active-fps-source = ; + maxim,active-fps-power-up-slot = <5>; + maxim,active-fps-power-down-slot = <1>; + }; + + pp1350: sd2 { + regulator-name = "PP1350"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + maxim,active-fps-source = ; + maxim,active-fps-power-up-slot = <2>; + maxim,active-fps-power-down-slot = <5>; + }; + + pp1800: sd3 { + regulator-name = "PP1800"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + maxim,active-fps-source = ; + maxim,active-fps-power-up-slot = <3>; + maxim,active-fps-power-down-slot = <3>; + }; + + pp1200_avdd: ldo0 { + regulator-name = "PP1200_AVDD"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-enable-ramp-delay = <26>; + regulator-ramp-delay = <100000>; + regulator-boot-on; + maxim,active-fps-source = ; + maxim,active-fps-power-up-slot = <0>; + maxim,active-fps-power-down-slot = <7>; + }; + + pp1200_rcam: ldo1 { + regulator-name = "PP1200_RCAM"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-enable-ramp-delay = <22>; + regulator-ramp-delay = <100000>; + maxim,active-fps-source = ; + maxim,active-fps-power-up-slot = <0>; + maxim,active-fps-power-down-slot = <7>; + }; + + pp_ldo2: ldo2 { + regulator-name = "PP_LDO2"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <62>; + regulator-ramp-delay = <11000>; + regulator-always-on; + regulator-boot-on; + maxim,active-fps-source = ; + maxim,active-fps-power-up-slot = <0>; + maxim,active-fps-power-down-slot = <7>; + }; + + pp2800l_rcam: ldo3 { + regulator-name = "PP2800L_RCAM"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-enable-ramp-delay = <50>; + regulator-ramp-delay = <100000>; + maxim,active-fps-source = ; + maxim,active-fps-power-up-slot = <0>; + maxim,active-fps-power-down-slot = <7>; + }; + + pp100_soc_rtc: ldo4 { + regulator-name = "PP1100_SOC_RTC"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-enable-ramp-delay = <22>; + regulator-ramp-delay = <100000>; + regulator-always-on; /* Check this */ + regulator-boot-on; + maxim,active-fps-source = ; + maxim,active-fps-power-up-slot = <1>; + maxim,active-fps-power-down-slot = <7>; + }; + + pp2800l_fcam: ldo5 { + regulator-name = "PP2800L_FCAM"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-enable-ramp-delay = <62>; + regulator-ramp-delay = <100000>; + maxim,active-fps-source = ; + maxim,active-fps-power-up-slot = <0>; + maxim,active-fps-power-down-slot = <7>; + }; + + ldo6 { + /* Unused. */ + regulator-name = "PP_LDO6"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <36>; + regulator-ramp-delay = <100000>; + maxim,active-fps-source = ; + maxim,active-fps-power-up-slot = <0>; + maxim,active-fps-power-down-slot = <7>; + }; + + pp1050_avdd: ldo7 { + regulator-name = "PP1050_AVDD"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + regulator-enable-ramp-delay = <24>; + regulator-ramp-delay = <100000>; + regulator-always-on; + regulator-boot-on; + maxim,active-fps-source = ; + maxim,active-fps-power-up-slot = <3>; + maxim,active-fps-power-down-slot = <4>; + }; + + avddio_1v05: ldo8 { + regulator-name = "AVDDIO_1V05"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + regulator-enable-ramp-delay = <22>; + regulator-ramp-delay = <100000>; + regulator-boot-on; + maxim,active-fps-source = ; + maxim,active-fps-power-up-slot = <0>; + maxim,active-fps-power-down-slot = <7>; + }; + }; + }; + }; + pmc@7000e400 { nvidia,invert-interrupt; nvidia,suspend-mode = <0>; @@ -1421,4 +1650,89 @@ compatible = "arm,psci-1.0"; method = "smc"; }; + + regulators { + compatible = "simple-bus"; + device_type = "fixed-regulators"; + #address-cells = <1>; + #size-cells = <0>; + + ppvar_sys: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "PPVAR_SYS"; + regulator-min-microvolt = <4400000>; + regulator-max-microvolt = <4400000>; + regulator-always-on; + }; + + pplcd_vdd: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "PPLCD_VDD"; + regulator-min-microvolt = <4400000>; + regulator-max-microvolt = <4400000>; + gpio = <&gpio TEGRA_GPIO(V, 4) 0>; + enable-active-high; + regulator-boot-on; + }; + + pp3000_always: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "PP3000_ALWAYS"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + }; + + pp3300: regulator@3 { + compatible = "regulator-fixed"; + reg = <3>; + regulator-name = "PP3300"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + enable-active-high; + }; + + pp5000: regulator@4 { + compatible = "regulator-fixed"; + reg = <4>; + regulator-name = "PP5000"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + pp1800_lcdio: regulator@5 { + compatible = "regulator-fixed"; + reg = <5>; + regulator-name = "PP1800_LCDIO"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&gpio TEGRA_GPIO(V, 3) 0>; + enable-active-high; + regulator-boot-on; + }; + + pp1800_cam: regulator@6 { + compatible = "regulator-fixed"; + reg= <6>; + regulator-name = "PP1800_CAM"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&gpio TEGRA_GPIO(K, 3) 0>; + enable-active-high; + }; + + usbc_vbus: regulator@7 { + compatible = "regulator-fixed"; + reg = <7>; + regulator-name = "USBC_VBUS"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + }; }; -- cgit v0.10.2 From c2b8244553f05716ac0b439307c8da9e31107ffe Mon Sep 17 00:00:00 2001 From: Jon Hunter Date: Fri, 17 Jun 2016 13:40:33 +0100 Subject: arm64: tegra: Add audio powergate node for Tegra210 Add the audio powergate for Tegra210. Signed-off-by: Jon Hunter Signed-off-by: Thierry Reding diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index b731880..b0fedac 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -584,6 +584,15 @@ reg = <0x0 0x7000e400 0x0 0x400>; clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>; clock-names = "pclk", "clk32k_in"; + + powergates { + pd_audio: aud { + clocks = <&tegra_car TEGRA210_CLK_APE>, + <&tegra_car TEGRA210_CLK_APB2APE>; + resets = <&tegra_car 198>; + #power-domain-cells = <0>; + }; + }; }; fuse@7000f800 { -- cgit v0.10.2 From 0f1330902217b303f87f07c6f83e9105aedee04a Mon Sep 17 00:00:00 2001 From: Jon Hunter Date: Fri, 17 Jun 2016 13:40:34 +0100 Subject: arm64: tegra: Add ACONNECT bus node for Tegra210 Add the ACONNECT bus node for Tegra210 which is used to interface to the various devices in the Audio Processing Engine (APE). Signed-off-by: Jon Hunter Signed-off-by: Thierry Reding diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index b0fedac..cefae3b 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -872,6 +872,18 @@ #nvidia,mipi-calibrate-cells = <1>; }; + aconnect@702c0000 { + compatible = "nvidia,tegra210-aconnect"; + clocks = <&tegra_car TEGRA210_CLK_APE>, + <&tegra_car TEGRA210_CLK_APB2APE>; + clock-names = "ape", "apb2ape"; + power-domains = <&pd_audio>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x702c0000 0x0 0x702c0000 0x00040000>; + status = "disabled"; + }; + spi@70410000 { compatible = "nvidia,tegra210-qspi"; reg = <0x0 0x70410000 0x0 0x1000>; -- cgit v0.10.2 From 66b2d6e9c93bc5bed55afda80c84bf0325c14ad4 Mon Sep 17 00:00:00 2001 From: Jon Hunter Date: Wed, 29 Jun 2016 10:17:57 +0100 Subject: arm64: tegra: Add DPAUX pinctrl bindings Add the DPAUX pinctrl states for the DPAUX nodes defining all three possible states of "aux", "i2c" and "off". Also add the 'i2c-bus' node for the DPAUX nodes so that the I2C driver core does not attempt to parse the pinctrl state nodes. Populate the nodes for the pinctrl clients of the DPAUX pin controller. There are two clients for each DPAUX instance, namely the SOR and one of the I2C adapters. The SOR clients may used the DPAUX pins in either AUX or I2C modes and so for these devices we don't define any of the generic pinctrl states (default, idle, etc) because the SOR driver will directly set the state needed. For I2C clients only the I2C mode is used and so we can simplify matters by using the generic pinctrl states for default and idle. Signed-off-by: Jon Hunter Signed-off-by: Thierry Reding diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index cefae3b..61ec48c 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -35,6 +35,26 @@ resets = <&tegra_car 207>; reset-names = "dpaux"; status = "disabled"; + + state_dpaux1_aux: pinmux-aux { + groups = "dpaux-io"; + function = "aux"; + }; + + state_dpaux1_i2c: pinmux-i2c { + groups = "dpaux-io"; + function = "i2c"; + }; + + state_dpaux1_off: pinmux-off { + groups = "dpaux-io"; + function = "off"; + }; + + i2c-bus { + #address-cells = <1>; + #size-cells = <0>; + }; }; vi@54080000 { @@ -154,6 +174,10 @@ clock-names = "sor", "parent", "dp", "safe"; resets = <&tegra_car 182>; reset-names = "sor"; + pinctrl-0 = <&state_dpaux_aux>; + pinctrl-1 = <&state_dpaux_i2c>; + pinctrl-2 = <&state_dpaux_off>; + pinctrl-names = "aux", "i2c", "off"; status = "disabled"; }; @@ -168,6 +192,10 @@ clock-names = "sor", "parent", "dp", "safe"; resets = <&tegra_car 183>; reset-names = "sor"; + pinctrl-0 = <&state_dpaux1_aux>; + pinctrl-1 = <&state_dpaux1_i2c>; + pinctrl-2 = <&state_dpaux1_off>; + pinctrl-names = "aux", "i2c", "off"; status = "disabled"; }; @@ -181,6 +209,26 @@ resets = <&tegra_car 181>; reset-names = "dpaux"; status = "disabled"; + + state_dpaux_aux: pinmux-aux { + groups = "dpaux-io"; + function = "aux"; + }; + + state_dpaux_i2c: pinmux-i2c { + groups = "dpaux-io"; + function = "i2c"; + }; + + state_dpaux_off: pinmux-off { + groups = "dpaux-io"; + function = "off"; + }; + + i2c-bus { + #address-cells = <1>; + #size-cells = <0>; + }; }; isp@54600000 { @@ -478,6 +526,9 @@ reset-names = "i2c"; dmas = <&apbdma 26>, <&apbdma 26>; dma-names = "rx", "tx"; + pinctrl-0 = <&state_dpaux1_i2c>; + pinctrl-1 = <&state_dpaux1_off>; + pinctrl-names = "default", "idle"; status = "disabled"; }; @@ -508,6 +559,9 @@ reset-names = "i2c"; dmas = <&apbdma 30>, <&apbdma 30>; dma-names = "rx", "tx"; + pinctrl-0 = <&state_dpaux_i2c>; + pinctrl-1 = <&state_dpaux_off>; + pinctrl-names = "default", "idle"; status = "disabled"; }; -- cgit v0.10.2 From 241f02ba987baa7bb11b820f8f2f9b71785470e8 Mon Sep 17 00:00:00 2001 From: Jon Hunter Date: Thu, 30 Jun 2016 11:56:27 +0100 Subject: arm64: tegra: Add XUSB powergates on Tegra210 The Tegra210 XUSB subsystem has 3 power partitions which are XUSBA (super-speed logic), XUSBB (USB device logic) and XUSBC (USB host logic). Populate the device-tree nodes for these XUSB partitions. Signed-off-by: Jon Hunter Signed-off-by: Thierry Reding diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index 61ec48c..443ecd5 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -646,6 +646,30 @@ resets = <&tegra_car 198>; #power-domain-cells = <0>; }; + + pd_xusbss: xusba { + clocks = <&tegra_car TEGRA210_CLK_XUSB_SS>; + clock-names = "xusb-ss"; + resets = <&tegra_car TEGRA210_CLK_XUSB_SS>; + reset-names = "xusb-ss"; + #power-domain-cells = <0>; + }; + + pd_xusbdev: xusbb { + clocks = <&tegra_car TEGRA210_CLK_XUSB_DEV>; + clock-names = "xusb-dev"; + resets = <&tegra_car 95>; + reset-names = "xusb-dev"; + #power-domain-cells = <0>; + }; + + pd_xusbhost: xusbc { + clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>; + clock-names = "xusb-host"; + resets = <&tegra_car TEGRA210_CLK_XUSB_HOST>; + reset-names = "xusb-host"; + #power-domain-cells = <0>; + }; }; }; -- cgit v0.10.2 From 237d5cc779bc506205420846f74f02c40d63f08e Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 9 Jun 2016 17:50:57 +0200 Subject: arm64: tegra: Add sor1_src clock The sor1 IP block needs the sor1_src clock to configure the clock tree depending on whether it's running in HDMI or DP mode. Signed-off-by: Thierry Reding diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index 443ecd5..c4cfdcf 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -186,10 +186,11 @@ reg = <0x0 0x54580000 0x0 0x00040000>; interrupts = ; clocks = <&tegra_car TEGRA210_CLK_SOR1>, + <&tegra_car TEGRA210_CLK_SOR1_SRC>, <&tegra_car TEGRA210_CLK_PLL_D2_OUT0>, <&tegra_car TEGRA210_CLK_PLL_DP>, <&tegra_car TEGRA210_CLK_SOR_SAFE>; - clock-names = "sor", "parent", "dp", "safe"; + clock-names = "sor", "source", "parent", "dp", "safe"; resets = <&tegra_car 183>; reset-names = "sor"; pinctrl-0 = <&state_dpaux1_aux>; -- cgit v0.10.2 From 34993594181dc1b34eaf8e3b878dde5ed810e61f Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 9 Jun 2016 17:48:39 +0200 Subject: arm64: tegra: Enable HDMI on Jetson TX1 Signed-off-by: Thierry Reding diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi index 8bba178..e5fc67b 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi @@ -4,6 +4,24 @@ model = "NVIDIA Tegra210 P2597 I/O board"; compatible = "nvidia,p2597", "nvidia,tegra210"; + host1x@50000000 { + dpaux@54040000 { + status = "okay"; + }; + + sor@54580000 { + status = "okay"; + + avdd-io-supply = <&avdd_1v05>; + vdd-pll-supply = <&vdd_1v8>; + hdmi-supply = <&vdd_hdmi>; + + nvidia,ddc-i2c-bus = <&hdmi_ddc>; + nvidia,hpd-gpio = <&gpio TEGRA_GPIO(CC, 1) + GPIO_ACTIVE_LOW>; + }; + }; + pinmux: pinmux@700008d4 { pinctrl-names = "boot"; pinctrl-0 = <&state_boot>; @@ -1278,6 +1296,12 @@ }; }; + /* HDMI DDC */ + hdmi_ddc: i2c@7000c700 { + status = "okay"; + clock-frequency = <100000>; + }; + usb@70090000 { phys = <&{/padctl@7009f000/pads/usb2/lanes/usb2-0}>, <&{/padctl@7009f000/pads/usb2/lanes/usb2-1}>, @@ -1552,6 +1576,17 @@ enable-active-high; vin-supply = <&vdd_5v0_sys>; }; + + vdd_hdmi: regulator@10 { + compatible = "regulator-fixed"; + reg = <10>; + regulator-name = "VDD_HDMI_5V0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&exp1 12 GPIO_ACTIVE_LOW>; + enable-active-high; + vin-supply = <&vdd_5v0_sys>; + }; }; gpio-keys { -- cgit v0.10.2