From 70896650732afd64c410f85c819281dbce8a0974 Mon Sep 17 00:00:00 2001 From: Kefeng Wang Date: Fri, 8 Apr 2016 15:31:50 +0800 Subject: arm64: dts: hip05: fix its node without msi-cells Fix commit abf9c25d55e8 ("arm64: dts: hip05: Append all gicv3 ITS entries"), it forgets the property msi-cell, see arm,gic-v3.txt. Signed-off-by: Kefeng Wang Signed-off-by: Wei Xu diff --git a/arch/arm64/boot/dts/hisilicon/hip05.dtsi b/arch/arm64/boot/dts/hisilicon/hip05.dtsi index 6319ff3..52d06ab 100644 --- a/arch/arm64/boot/dts/hisilicon/hip05.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hip05.dtsi @@ -249,24 +249,28 @@ its_peri: interrupt-controller@8c000000 { compatible = "arm,gic-v3-its"; msi-controller; + #msi-cells = <1>; reg = <0x0 0x8c000000 0x0 0x40000>; }; its_m3: interrupt-controller@a3000000 { compatible = "arm,gic-v3-its"; msi-controller; + #msi-cells = <1>; reg = <0x0 0xa3000000 0x0 0x40000>; }; its_pcie: interrupt-controller@b7000000 { compatible = "arm,gic-v3-its"; msi-controller; + #msi-cells = <1>; reg = <0x0 0xb7000000 0x0 0x40000>; }; its_dsa: interrupt-controller@c6000000 { compatible = "arm,gic-v3-its"; msi-controller; + #msi-cells = <1>; reg = <0x0 0xc6000000 0x0 0x40000>; }; }; -- cgit v0.10.2 From 162d23bfd18cec10bd5940ff264debf3c6121f34 Mon Sep 17 00:00:00 2001 From: Kefeng Wang Date: Fri, 8 Apr 2016 15:31:51 +0800 Subject: arm64: dts: hip05: Add nor flash support This patch is to add support nor-flash. Notice, the pre-defined partitions may not be used. Signed-off-by: Kefeng Wang Signed-off-by: Wei Xu diff --git a/arch/arm64/boot/dts/hisilicon/hip05-d02.dts b/arch/arm64/boot/dts/hisilicon/hip05-d02.dts index e9436c0..abba750 100644 --- a/arch/arm64/boot/dts/hisilicon/hip05-d02.dts +++ b/arch/arm64/boot/dts/hisilicon/hip05-d02.dts @@ -52,3 +52,37 @@ &peri_gpio0 { status = "ok"; }; + +&lbc { + status = "ok"; + #address-cells = <2>; + #size-cells = <1>; + ranges = <0 0 0x0 0x90000000 0x08000000>, + <1 0 0x0 0x98000000 0x08000000>; + + nor-flash@0,0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "numonyx,js28f00a", "cfi-flash"; + reg = <0 0x0 0x08000000>; + bank-width = <2>; + /* The three parts may not used */ + partition@0 { + label = "BIOS"; + reg = <0x0 0x300000>; + }; + partition@300000 { + label = "Linux"; + reg = <0x300000 0xa00000>; + }; + partition@1000000 { + label = "Rootfs"; + reg = <0x01000000 0x02000000>; + }; + }; + + cpld@1,0 { + compatible = "hisilicon,hip05-cpld"; + reg = <1 0x0 0x100>; + }; +}; diff --git a/arch/arm64/boot/dts/hisilicon/hip05.dtsi b/arch/arm64/boot/dts/hisilicon/hip05.dtsi index 52d06ab..bf322ed 100644 --- a/arch/arm64/boot/dts/hisilicon/hip05.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hip05.dtsi @@ -327,6 +327,12 @@ status = "disabled"; }; + lbc: localbus@80380000 { + compatible = "hisilicon,hisi-localbus", "simple-bus"; + reg = <0x0 0x80380000 0x0 0x10000>; + status = "disabled"; + }; + peri_gpio0: gpio@802e0000 { #address-cells = <1>; #size-cells = <0>; -- cgit v0.10.2 From aa8d3e74f54d0af737c46c77de35b39d9a44592b Mon Sep 17 00:00:00 2001 From: Kefeng Wang Date: Fri, 8 Apr 2016 15:27:11 +0800 Subject: arm64: dts: Add initial dts for Hisilicon Hip06 D03 board The Hip06 soc has same cpu topology compared with Hip05, four clusters and each cluster has quard Cortex-A57, but with different IO part, like HNS, SAS and PCI, they are all upgraded. There are also not same in ITS, MBIGEN and SMMU, etc. This patch adds the initial dts for hip06 d03 board. Note, there is no serial, because the soc use LPC uart, the serial node is not needed. Signed-off-by: Kefeng Wang Signed-off-by: Wei Xu diff --git a/arch/arm64/boot/dts/hisilicon/Makefile b/arch/arm64/boot/dts/hisilicon/Makefile index cd158b8..d5f43a0 100644 --- a/arch/arm64/boot/dts/hisilicon/Makefile +++ b/arch/arm64/boot/dts/hisilicon/Makefile @@ -1,4 +1,6 @@ -dtb-$(CONFIG_ARCH_HISI) += hi6220-hikey.dtb hip05-d02.dtb +dtb-$(CONFIG_ARCH_HISI) += hi6220-hikey.dtb +dtb-$(CONFIG_ARCH_HISI) += hip05-d02.dtb +dtb-$(CONFIG_ARCH_HISI) += hip06-d03.dtb always := $(dtb-y) subdir-y := $(dts-dirs) diff --git a/arch/arm64/boot/dts/hisilicon/hip06-d03.dts b/arch/arm64/boot/dts/hisilicon/hip06-d03.dts new file mode 100644 index 0000000..f3e5323 --- /dev/null +++ b/arch/arm64/boot/dts/hisilicon/hip06-d03.dts @@ -0,0 +1,34 @@ +/** + * dts file for Hisilicon D03 Development Board + * + * Copyright (C) 2016 Hisilicon Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * publishhed by the Free Software Foundation. + * + */ + +/dts-v1/; + +#include "hip06.dtsi" + +/ { + model = "Hisilicon Hip06 D03 Development Board"; + compatible = "hisilicon,hip06-d03"; + + memory@00000000 { + device_type = "memory"; + reg = <0x0 0x00000000 0x0 0x40000000>; + }; + + chosen { }; +}; + +&usb_ohci { + status = "ok"; +}; + +&usb_ehci { + status = "ok"; +}; diff --git a/arch/arm64/boot/dts/hisilicon/hip06.dtsi b/arch/arm64/boot/dts/hisilicon/hip06.dtsi new file mode 100644 index 0000000..5927bc4 --- /dev/null +++ b/arch/arm64/boot/dts/hisilicon/hip06.dtsi @@ -0,0 +1,307 @@ +/** + * dts file for Hisilicon D03 Development Board + * + * Copyright (C) 2016 Hisilicon Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * publishhed by the Free Software Foundation. + * + */ + +#include + +/ { + compatible = "hisilicon,hip06-d03"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + core1 { + cpu = <&cpu1>; + }; + core2 { + cpu = <&cpu2>; + }; + core3 { + cpu = <&cpu3>; + }; + }; + cluster1 { + core0 { + cpu = <&cpu4>; + }; + core1 { + cpu = <&cpu5>; + }; + core2 { + cpu = <&cpu6>; + }; + core3 { + cpu = <&cpu7>; + }; + }; + cluster2 { + core0 { + cpu = <&cpu8>; + }; + core1 { + cpu = <&cpu9>; + }; + core2 { + cpu = <&cpu10>; + }; + core3 { + cpu = <&cpu11>; + }; + }; + cluster3 { + core0 { + cpu = <&cpu12>; + }; + core1 { + cpu = <&cpu13>; + }; + core2 { + cpu = <&cpu14>; + }; + core3 { + cpu = <&cpu15>; + }; + }; + }; + + cpu0: cpu@10000 { + device_type = "cpu"; + compatible = "arm,cortex-a57", "arm,armv8"; + reg = <0x10000>; + enable-method = "psci"; + next-level-cache = <&cluster0_l2>; + }; + + cpu1: cpu@10001 { + device_type = "cpu"; + compatible = "arm,cortex-a57", "arm,armv8"; + reg = <0x10001>; + enable-method = "psci"; + next-level-cache = <&cluster0_l2>; + }; + + cpu2: cpu@10002 { + device_type = "cpu"; + compatible = "arm,cortex-a57", "arm,armv8"; + reg = <0x10002>; + enable-method = "psci"; + next-level-cache = <&cluster0_l2>; + }; + + cpu3: cpu@10003 { + device_type = "cpu"; + compatible = "arm,cortex-a57", "arm,armv8"; + reg = <0x10003>; + enable-method = "psci"; + next-level-cache = <&cluster0_l2>; + }; + + cpu4: cpu@10100 { + device_type = "cpu"; + compatible = "arm,cortex-a57", "arm,armv8"; + reg = <0x10100>; + enable-method = "psci"; + next-level-cache = <&cluster1_l2>; + }; + + cpu5: cpu@10101 { + device_type = "cpu"; + compatible = "arm,cortex-a57", "arm,armv8"; + reg = <0x10101>; + enable-method = "psci"; + next-level-cache = <&cluster1_l2>; + }; + + cpu6: cpu@10102 { + device_type = "cpu"; + compatible = "arm,cortex-a57", "arm,armv8"; + reg = <0x10102>; + enable-method = "psci"; + next-level-cache = <&cluster1_l2>; + }; + + cpu7: cpu@10103 { + device_type = "cpu"; + compatible = "arm,cortex-a57", "arm,armv8"; + reg = <0x10103>; + enable-method = "psci"; + next-level-cache = <&cluster1_l2>; + }; + + cpu8: cpu@10200 { + device_type = "cpu"; + compatible = "arm,cortex-a57", "arm,armv8"; + reg = <0x10200>; + enable-method = "psci"; + next-level-cache = <&cluster2_l2>; + }; + + cpu9: cpu@10201 { + device_type = "cpu"; + compatible = "arm,cortex-a57", "arm,armv8"; + reg = <0x10201>; + enable-method = "psci"; + next-level-cache = <&cluster2_l2>; + }; + + cpu10: cpu@10202 { + device_type = "cpu"; + compatible = "arm,cortex-a57", "arm,armv8"; + reg = <0x10202>; + enable-method = "psci"; + next-level-cache = <&cluster2_l2>; + }; + + cpu11: cpu@10203 { + device_type = "cpu"; + compatible = "arm,cortex-a57", "arm,armv8"; + reg = <0x10203>; + enable-method = "psci"; + next-level-cache = <&cluster2_l2>; + }; + + cpu12: cpu@10300 { + device_type = "cpu"; + compatible = "arm,cortex-a57", "arm,armv8"; + reg = <0x10300>; + enable-method = "psci"; + next-level-cache = <&cluster3_l2>; + }; + + cpu13: cpu@10301 { + device_type = "cpu"; + compatible = "arm,cortex-a57", "arm,armv8"; + reg = <0x10301>; + enable-method = "psci"; + next-level-cache = <&cluster3_l2>; + }; + + cpu14: cpu@10302 { + device_type = "cpu"; + compatible = "arm,cortex-a57", "arm,armv8"; + reg = <0x10302>; + enable-method = "psci"; + next-level-cache = <&cluster3_l2>; + }; + + cpu15: cpu@10303 { + device_type = "cpu"; + compatible = "arm,cortex-a57", "arm,armv8"; + reg = <0x10303>; + enable-method = "psci"; + next-level-cache = <&cluster3_l2>; + }; + + cluster0_l2: l2-cache0 { + compatible = "cache"; + }; + + cluster1_l2: l2-cache1 { + compatible = "cache"; + }; + + cluster2_l2: l2-cache2 { + compatible = "cache"; + }; + + cluster3_l2: l2-cache3 { + compatible = "cache"; + }; + }; + + gic: interrupt-controller@4d000000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + interrupt-controller; + #redistributor-regions = <1>; + redistributor-stride = <0x0 0x30000>; + reg = <0x0 0x4d000000 0 0x10000>, /* GICD */ + <0x0 0x4d100000 0 0x300000>, /* GICR */ + <0x0 0xfe000000 0 0x10000>, /* GICC */ + <0x0 0xfe010000 0 0x10000>, /* GICH */ + <0x0 0xfe020000 0 0x10000>; /* GICV */ + interrupts = ; + + its_dsa: interrupt-controller@c6000000 { + compatible = "arm,gic-v3-its"; + msi-controller; + #msi-cells = <1>; + reg = <0x0 0xc6000000 0x0 0x40000>; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; + + pmu { + compatible = "arm,cortex-a57-pmu"; + interrupts = ; + }; + + mbigen_pcie@a0080000 { + compatible = "hisilicon,mbigen-v2"; + reg = <0x0 0xa0080000 0x0 0x10000>; + + mbigen_usb: intc_usb { + msi-parent = <&its_dsa 0x40080>; + interrupt-controller; + #interrupt-cells = <2>; + num-pins = <2>; + }; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + usb_ohci: ohci@a7030000 { + compatible = "generic-ohci"; + reg = <0x0 0xa7030000 0x0 0x10000>; + interrupt-parent = <&mbigen_usb>; + interrupts = <64 4>; + dma-coherent; + status = "disabled"; + }; + + usb_ehci: ehci@a7020000 { + compatible = "generic-ehci"; + reg = <0x0 0xa7020000 0x0 0x10000>; + interrupt-parent = <&mbigen_usb>; + interrupts = <65 4>; + dma-coherent; + status = "disabled"; + }; + }; + +}; -- cgit v0.10.2 From 4cfcb35189f62ae351194827fca1787053a66235 Mon Sep 17 00:00:00 2001 From: Kefeng Wang Date: Fri, 8 Apr 2016 15:27:12 +0800 Subject: Documentation: arm64: Add Hisilicon Hip06 D03 dts binding This patch adds documentation for the devicetree bindings used by the DT files of Hisilicon Hip06 D03 board. Meanwhile, reorder the soc/board name alphabetically. Signed-off-by: Kefeng Wang Signed-off-by: Wei Xu diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt index e3ccab1..83fe816 100644 --- a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt +++ b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt @@ -1,29 +1,33 @@ Hisilicon Platforms Device Tree Bindings ---------------------------------------------------- -Hi6220 SoC -Required root node properties: - - compatible = "hisilicon,hi6220"; - Hi4511 Board Required root node properties: - compatible = "hisilicon,hi3620-hi4511"; -HiP04 D01 Board +Hi6220 SoC Required root node properties: - - compatible = "hisilicon,hip04-d01"; + - compatible = "hisilicon,hi6220"; + +HiKey Board +Required root node properties: + - compatible = "hisilicon,hi6220-hikey", "hisilicon,hi6220"; HiP01 ca9x2 Board Required root node properties: - compatible = "hisilicon,hip01-ca9x2"; -HiKey Board +HiP04 D01 Board Required root node properties: - - compatible = "hisilicon,hi6220-hikey", "hisilicon,hi6220"; + - compatible = "hisilicon,hip04-d01"; HiP05 D02 Board Required root node properties: - compatible = "hisilicon,hip05-d02"; +HiP06 D03 Board +Required root node properties: + - compatible = "hisilicon,hip06-d03"; + Hisilicon system controller Required properties: -- cgit v0.10.2