From 33c9907535cef6cb5de1269540c04664c393d09c Mon Sep 17 00:00:00 2001 From: Juha Yrjola Date: Wed, 6 Dec 2006 17:13:46 -0800 Subject: ARM: OMAP2: Place SMS and SDRC into smart idle mode Place SMS and SDRC into smart idle mode Signed-off-by: Juha Yrjola Signed-off-by: Tony Lindgren diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c index 82dc70f..a57a429 100644 --- a/arch/arm/mach-omap2/io.c +++ b/arch/arm/mach-omap2/io.c @@ -26,6 +26,7 @@ extern void omap_sram_init(void); extern int omap2_clk_init(void); extern void omap2_check_revision(void); +extern void omap2_init_memory(void); extern void gpmc_init(void); extern void omapfb_reserve_sdram(void); @@ -80,5 +81,6 @@ void __init omap2_init_common_hw(void) { omap2_mux_init(); omap2_clk_init(); + omap2_init_memory(); gpmc_init(); } diff --git a/arch/arm/mach-omap2/memory.c b/arch/arm/mach-omap2/memory.c index 85cbc2a..f173aa8 100644 --- a/arch/arm/mach-omap2/memory.c +++ b/arch/arm/mach-omap2/memory.c @@ -30,6 +30,38 @@ #include "prcm-regs.h" #include "memory.h" +#define SMS_BASE 0x68008000 +#define SMS_SYSCONFIG 0x010 + +#define SDRC_BASE 0x68009000 +#define SDRC_SYSCONFIG 0x010 +#define SDRC_SYSSTATUS 0x014 + +static const u32 sms_base = IO_ADDRESS(SMS_BASE); +static const u32 sdrc_base = IO_ADDRESS(SDRC_BASE); + + +static inline void sms_write_reg(int idx, u32 val) +{ + __raw_writel(val, sms_base + idx); +} + +static inline u32 sms_read_reg(int idx) +{ + return __raw_readl(sms_base + idx); +} + +static inline void sdrc_write_reg(int idx, u32 val) +{ + __raw_writel(val, sdrc_base + idx); +} + +static inline u32 sdrc_read_reg(int idx) +{ + return __raw_readl(sdrc_base + idx); +} + + static struct memory_timings mem_timings; u32 omap2_memory_get_slow_dll_ctrl(void) @@ -99,3 +131,19 @@ void omap2_init_memory_params(u32 force_lock_to_unlock_mode) /* 90 degree phase for anything below 133Mhz + disable DLL filter */ mem_timings.slow_dll_ctrl |= ((1 << 1) | (3 << 8)); } + +void __init omap2_init_memory(void) +{ + u32 l; + + l = sms_read_reg(SMS_SYSCONFIG); + l &= ~(0x3 << 3); + l |= (0x2 << 3); + sms_write_reg(SMS_SYSCONFIG, l); + + l = sdrc_read_reg(SDRC_SYSCONFIG); + l &= ~(0x3 << 3); + l |= (0x2 << 3); + sdrc_write_reg(SDRC_SYSCONFIG, l); + +} -- cgit v0.10.2 From 375e12abceac4e8e20ea54ff6a9e7be58729ac70 Mon Sep 17 00:00:00 2001 From: Juha Yrjola Date: Wed, 6 Dec 2006 17:13:50 -0800 Subject: ARM: OMAP: Optimize INTC register accesses and enable autoidling Use virtual addresses directly instead of physical addresses to avoid having to recalculate the virtual address with every register access. Signed-off-by: Juha Yrjola Signed-off-by: Tony Lindgren diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c index a39d306..f064f72 100644 --- a/arch/arm/mach-omap2/irq.c +++ b/arch/arm/mach-omap2/irq.c @@ -37,7 +37,7 @@ static struct omap_irq_bank { } __attribute__ ((aligned(4))) irq_banks[] = { { /* MPU INTC */ - .base_reg = OMAP24XX_IC_BASE, + .base_reg = IO_ADDRESS(OMAP24XX_IC_BASE), .nr_irqs = 96, }, { /* XXX: DSP INTC */ @@ -47,7 +47,7 @@ static struct omap_irq_bank { /* XXX: FIQ and additional INTC support (only MPU at the moment) */ static void omap_ack_irq(unsigned int irq) { - omap_writel(0x1, irq_banks[0].base_reg + INTC_CONTROL); + __raw_writel(0x1, irq_banks[0].base_reg + INTC_CONTROL); } static void omap_mask_irq(unsigned int irq) @@ -60,7 +60,7 @@ static void omap_mask_irq(unsigned int irq) irq %= 32; } - omap_writel(1 << irq, irq_banks[0].base_reg + INTC_MIR_SET0 + offset); + __raw_writel(1 << irq, irq_banks[0].base_reg + INTC_MIR_SET0 + offset); } static void omap_unmask_irq(unsigned int irq) @@ -73,7 +73,7 @@ static void omap_unmask_irq(unsigned int irq) irq %= 32; } - omap_writel(1 << irq, irq_banks[0].base_reg + INTC_MIR_CLEAR0 + offset); + __raw_writel(1 << irq, irq_banks[0].base_reg + INTC_MIR_CLEAR0 + offset); } static void omap_mask_ack_irq(unsigned int irq) @@ -93,17 +93,20 @@ static void __init omap_irq_bank_init_one(struct omap_irq_bank *bank) { unsigned long tmp; - tmp = omap_readl(bank->base_reg + INTC_REVISION) & 0xff; + tmp = __raw_readl(bank->base_reg + INTC_REVISION) & 0xff; printk(KERN_INFO "IRQ: Found an INTC at 0x%08lx " "(revision %ld.%ld) with %d interrupts\n", bank->base_reg, tmp >> 4, tmp & 0xf, bank->nr_irqs); - tmp = omap_readl(bank->base_reg + INTC_SYSCONFIG); + tmp = __raw_readl(bank->base_reg + INTC_SYSCONFIG); tmp |= 1 << 1; /* soft reset */ - omap_writel(tmp, bank->base_reg + INTC_SYSCONFIG); + __raw_writel(tmp, bank->base_reg + INTC_SYSCONFIG); - while (!(omap_readl(bank->base_reg + INTC_SYSSTATUS) & 0x1)) + while (!(__raw_readl(bank->base_reg + INTC_SYSSTATUS) & 0x1)) /* Wait for reset to complete */; + + /* Enable autoidle */ + __raw_writel(1 << 0, bank->base_reg + INTC_SYSCONFIG); } void __init omap_init_irq(void) -- cgit v0.10.2 From f024840872e76b1fdef324aee8c9176ed7aa0ba4 Mon Sep 17 00:00:00 2001 From: Kyungmin Park Date: Wed, 6 Dec 2006 17:13:53 -0800 Subject: ARM: OMAP: Board Apollon update, fix boot Update Apollon board init to initialize NAND, USB, and LEDs. Also configure GPMC memory for smc91x Ethernet. Signed-off-by: Kyungmin Park Signed-off-by: Tony Lindgren diff --git a/arch/arm/mach-omap2/board-apollon.c b/arch/arm/mach-omap2/board-apollon.c index 878ff91..3bb49c1 100644 --- a/arch/arm/mach-omap2/board-apollon.c +++ b/arch/arm/mach-omap2/board-apollon.c @@ -25,6 +25,8 @@ #include #include #include +#include +#include #include #include @@ -32,10 +34,12 @@ #include #include +#include #include #include #include #include +#include #include "prcm-regs.h" /* LED & Switch macros */ @@ -46,6 +50,9 @@ #define SW_UP_GPIO17 17 #define SW_DOWN_GPIO58 58 +#define APOLLON_FLASH_CS 0 +#define APOLLON_ETH_CS 1 + static struct mtd_partition apollon_partitions[] = { { .name = "X-Loader + U-Boot", @@ -85,10 +92,10 @@ static struct flash_platform_data apollon_flash_data = { .nr_parts = ARRAY_SIZE(apollon_partitions), }; -static struct resource apollon_flash_resource = { - .start = APOLLON_CS0_BASE, - .end = APOLLON_CS0_BASE + SZ_128K, - .flags = IORESOURCE_MEM, +static struct resource apollon_flash_resource[] = { + [0] = { + .flags = IORESOURCE_MEM, + }, }; static struct platform_device apollon_onenand_device = { @@ -97,14 +104,24 @@ static struct platform_device apollon_onenand_device = { .dev = { .platform_data = &apollon_flash_data, }, - .num_resources = ARRAY_SIZE(&apollon_flash_resource), - .resource = &apollon_flash_resource, + .num_resources = ARRAY_SIZE(apollon_flash_resource), + .resource = apollon_flash_resource, }; +static void __init apollon_flash_init(void) +{ + unsigned long base; + + if (gpmc_cs_request(APOLLON_FLASH_CS, SZ_128K, &base) < 0) { + printk(KERN_ERR "Cannot request OneNAND GPMC CS\n"); + return; + } + apollon_flash_resource[0].start = base; + apollon_flash_resource[0].end = base + SZ_128K - 1; +} + static struct resource apollon_smc91x_resources[] = { [0] = { - .start = APOLLON_ETHR_START, /* Physical */ - .end = APOLLON_ETHR_START + 0xf, .flags = IORESOURCE_MEM, }, [1] = { @@ -126,14 +143,51 @@ static struct platform_device apollon_lcd_device = { .id = -1, }; +static struct omap_led_config apollon_led_config[] = { + { + .cdev = { + .name = "apollon:led0", + }, + .gpio = LED0_GPIO13, + }, + { + .cdev = { + .name = "apollon:led1", + }, + .gpio = LED1_GPIO14, + }, + { + .cdev = { + .name = "apollon:led2", + }, + .gpio = LED2_GPIO15, + }, +}; + +static struct omap_led_platform_data apollon_led_data = { + .nr_leds = ARRAY_SIZE(apollon_led_config), + .leds = apollon_led_config, +}; + +static struct platform_device apollon_led_device = { + .name = "omap-led", + .id = -1, + .dev = { + .platform_data = &apollon_led_data, + }, +}; + static struct platform_device *apollon_devices[] __initdata = { &apollon_onenand_device, &apollon_smc91x_device, &apollon_lcd_device, + &apollon_led_device, }; static inline void __init apollon_init_smc91x(void) { + unsigned long base; + /* Make sure CS1 timings are correct */ GPMC_CONFIG1_1 = 0x00011203; GPMC_CONFIG2_1 = 0x001f1f01; @@ -141,13 +195,20 @@ static inline void __init apollon_init_smc91x(void) GPMC_CONFIG4_1 = 0x1c091c09; GPMC_CONFIG5_1 = 0x041f1f1f; GPMC_CONFIG6_1 = 0x000004c4; - GPMC_CONFIG7_1 = 0x00000f40 | (APOLLON_CS1_BASE >> 24); + + if (gpmc_cs_request(APOLLON_ETH_CS, SZ_16M, &base) < 0) { + printk(KERN_ERR "Failed to request GPMC CS for smc91x\n"); + return; + } + apollon_smc91x_resources[0].start = base + 0x300; + apollon_smc91x_resources[0].end = base + 0x30f; udelay(100); omap_cfg_reg(W4__24XX_GPIO74); if (omap_request_gpio(APOLLON_ETHR_GPIO_IRQ) < 0) { printk(KERN_ERR "Failed to request GPIO%d for smc91x IRQ\n", APOLLON_ETHR_GPIO_IRQ); + gpmc_cs_free(APOLLON_ETH_CS); return; } omap_set_gpio_direction(APOLLON_ETHR_GPIO_IRQ, 1); @@ -175,6 +236,13 @@ static struct omap_mmc_config apollon_mmc_config __initdata = { }, }; +static struct omap_usb_config apollon_usb_config __initdata = { + .register_dev = 1, + .hmc_mode = 0x14, /* 0:dev 1:host1 2:disable */ + + .pins[0] = 6, +}; + static struct omap_lcd_config apollon_lcd_config __initdata = { .ctrl_name = "internal", }; @@ -182,6 +250,7 @@ static struct omap_lcd_config apollon_lcd_config __initdata = { static struct omap_board_config_kernel apollon_config[] = { { OMAP_TAG_UART, &apollon_uart_config }, { OMAP_TAG_MMC, &apollon_mmc_config }, + { OMAP_TAG_USB, &apollon_usb_config }, { OMAP_TAG_LCD, &apollon_lcd_config }, }; @@ -250,10 +319,22 @@ static void __init apollon_sw_init(void) return; } +static void __init apollon_usb_init(void) +{ + /* USB device */ + /* DEVICE_SUSPEND */ + omap_cfg_reg(P21_242X_GPIO12); + omap_request_gpio(12); + omap_set_gpio_direction(12, 0); /* OUT */ + omap_set_gpio_dataout(12, 0); +} + static void __init omap_apollon_init(void) { apollon_led_init(); apollon_sw_init(); + apollon_flash_init(); + apollon_usb_init(); /* REVISIT: where's the correct place */ omap_cfg_reg(W19_24XX_SYS_NIRQ); -- cgit v0.10.2 From 742c53e48e5f8e05ec9f0818281fada9c6061023 Mon Sep 17 00:00:00 2001 From: David Brownell Date: Wed, 6 Dec 2006 17:13:54 -0800 Subject: ARM: OMAP: omap2/memory.c compile fixes Remove some conflicting declarations in omap2/memory.c so that the file builds again. Signed-off-by: David Brownell Signed-off-by: Tony Lindgren diff --git a/arch/arm/mach-omap2/memory.c b/arch/arm/mach-omap2/memory.c index f173aa8..3e5d8cd 100644 --- a/arch/arm/mach-omap2/memory.c +++ b/arch/arm/mach-omap2/memory.c @@ -30,37 +30,6 @@ #include "prcm-regs.h" #include "memory.h" -#define SMS_BASE 0x68008000 -#define SMS_SYSCONFIG 0x010 - -#define SDRC_BASE 0x68009000 -#define SDRC_SYSCONFIG 0x010 -#define SDRC_SYSSTATUS 0x014 - -static const u32 sms_base = IO_ADDRESS(SMS_BASE); -static const u32 sdrc_base = IO_ADDRESS(SDRC_BASE); - - -static inline void sms_write_reg(int idx, u32 val) -{ - __raw_writel(val, sms_base + idx); -} - -static inline u32 sms_read_reg(int idx) -{ - return __raw_readl(sms_base + idx); -} - -static inline void sdrc_write_reg(int idx, u32 val) -{ - __raw_writel(val, sdrc_base + idx); -} - -static inline u32 sdrc_read_reg(int idx) -{ - return __raw_readl(sdrc_base + idx); -} - static struct memory_timings mem_timings; @@ -132,18 +101,19 @@ void omap2_init_memory_params(u32 force_lock_to_unlock_mode) mem_timings.slow_dll_ctrl |= ((1 << 1) | (3 << 8)); } +/* turn on smart idle modes for SDRAM scheduler and controller */ void __init omap2_init_memory(void) { u32 l; - l = sms_read_reg(SMS_SYSCONFIG); + l = SMS_SYSCONFIG; l &= ~(0x3 << 3); l |= (0x2 << 3); - sms_write_reg(SMS_SYSCONFIG, l); + SMS_SYSCONFIG = l; - l = sdrc_read_reg(SDRC_SYSCONFIG); + l = SDRC_SYSCONFIG; l &= ~(0x3 << 3); l |= (0x2 << 3); - sdrc_write_reg(SDRC_SYSCONFIG, l); + SDRC_SYSCONFIG = l; } -- cgit v0.10.2 From 1c22cc13256046162bb8e7b44763f6c39790af74 Mon Sep 17 00:00:00 2001 From: David Brownell Date: Wed, 6 Dec 2006 17:13:55 -0800 Subject: ARM: OMAP: omap2/gpmc updates GPMC updates: - bugfixes: wrong/missing flags, omitted write, wrong test - don't map memory segments starting at zero - improve debug messaging - export gpmc_get_fclk_perio]d() since it's needed to calc timings - expect gpmc_cs_set_timings() caller to have initialized sync vs async Note that this API is glitchy; likely the best fix would be to add a member to "struct gpmc_timings" to hold GPMC_CONFIG1, since that holds one key aspect of the GPMC timings (the gpmc_fclk divisor, and sync vs. async == whether that divisor matters). Signed-off-by: David Brownell Signed-off-by: Tony Lindgren diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c index e290b98..6d6b25c 100644 --- a/arch/arm/mach-omap2/gpmc.c +++ b/arch/arm/mach-omap2/gpmc.c @@ -88,7 +88,7 @@ u32 gpmc_cs_read_reg(int cs, int idx) } /* TODO: Add support for gpmc_fck to clock framework and use it */ -static unsigned long gpmc_get_fclk_period(void) +unsigned long gpmc_get_fclk_period(void) { /* In picoseconds */ return 1000000000 / ((clk_get_rate(gpmc_l3_clk)) / 1000); @@ -120,15 +120,21 @@ static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit, else ticks = gpmc_ns_to_ticks(time); nr_bits = end_bit - st_bit + 1; - if (ticks >= 1 << nr_bits) + if (ticks >= 1 << nr_bits) { +#ifdef DEBUG + printk(KERN_INFO "GPMC CS%d: %-10s* %3d ns, %3d ticks >= %d\n", + cs, name, time, ticks, 1 << nr_bits); +#endif return -1; + } mask = (1 << nr_bits) - 1; l = gpmc_cs_read_reg(cs, reg); #ifdef DEBUG - printk(KERN_INFO "GPMC CS%d: %-10s: %d ticks, %3lu ns (was %i ticks)\n", + printk(KERN_INFO + "GPMC CS%d: %-10s: %3d ticks, %3lu ns (was %3i ticks) %3d ns\n", cs, name, ticks, gpmc_get_fclk_period() * ticks / 1000, - (l >> st_bit) & mask); + (l >> st_bit) & mask, time); #endif l &= ~(mask << st_bit); l |= ticks << st_bit; @@ -157,7 +163,7 @@ int gpmc_cs_calc_divider(int cs, unsigned int sync_clk) div = l / gpmc_get_fclk_period(); if (div > 4) return -1; - if (div < 0) + if (div <= 0) div = 1; return div; @@ -191,14 +197,19 @@ int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t) GPMC_SET_ONE(GPMC_CS_CONFIG5, 24, 27, page_burst_access); + /* caller is expected to have initialized CONFIG1 to cover + * at least sync vs async + */ + l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1); + if (l & (GPMC_CONFIG1_READTYPE_SYNC | GPMC_CONFIG1_WRITETYPE_SYNC)) { #ifdef DEBUG - printk(KERN_INFO "GPMC CS%d CLK period is %lu (div %d)\n", - cs, gpmc_get_fclk_period(), div); + printk(KERN_INFO "GPMC CS%d CLK period is %lu ns (div %d)\n", + cs, (div * gpmc_get_fclk_period()) / 1000, div); #endif - - l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1); - l &= ~0x03; - l |= (div - 1); + l &= ~0x03; + l |= (div - 1); + gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, l); + } return 0; } diff --git a/include/asm-arm/arch-omap/gpmc.h b/include/asm-arm/arch-omap/gpmc.h index 995cc83..434672d 100644 --- a/include/asm-arm/arch-omap/gpmc.h +++ b/include/asm-arm/arch-omap/gpmc.h @@ -23,9 +23,10 @@ #define GPMC_CS_NAND_DATA 0x24 #define GPMC_CONFIG1_WRAPBURST_SUPP (1 << 31) -#define GPMC_CONFIG1_READMULTIPLE_SUPP (1 << 20) +#define GPMC_CONFIG1_READMULTIPLE_SUPP (1 << 30) #define GPMC_CONFIG1_READTYPE_ASYNC (0 << 29) #define GPMC_CONFIG1_READTYPE_SYNC (1 << 29) +#define GPMC_CONFIG1_WRITEMULTIPLE_SUPP (1 << 28) #define GPMC_CONFIG1_WRITETYPE_ASYNC (0 << 27) #define GPMC_CONFIG1_WRITETYPE_SYNC (1 << 27) #define GPMC_CONFIG1_CLKACTIVATIONTIME(val) ((val & 3) << 25) -- cgit v0.10.2 From f604931238dff7b44ef52ac2ad1f557e45b25b38 Mon Sep 17 00:00:00 2001 From: David Brownell Date: Wed, 6 Dec 2006 17:14:03 -0800 Subject: ARM: OMAP: abstract debug card setup (smc, leds) Additional cleanup for debug boards on H2/P2/H3/H4: move the init code that's not board-specific into a new file where it can be easily shared between all the different boards (avoiding code duplication, and making it easier to support more devices). Make H4 use that. This should be easy to drop in to the OMAP1 boards using these debug cards; the only difference seems to be that the p2 does an extra reset of the smc using the fpga (probably all boards could do that, if it's necessary) and doesn't use the gpio mux or request APIs. Signed-off-by: David Brownell Signed-off-by: Tony Lindgren diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index 7393109..cf4268e 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig @@ -21,7 +21,7 @@ config MACH_OMAP_GENERIC config MACH_OMAP_H4 bool "OMAP 2420 H4 board" depends on ARCH_OMAP2 && ARCH_OMAP24XX - select OMAP_DEBUG_LEDS if LEDS || LEDS_OMAP_DEBUG + select OMAP_DEBUG_DEVICES config MACH_OMAP_APOLLON bool "OMAP 2420 Apollon board" diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c index 452193f0..f125f43 100644 --- a/arch/arm/mach-omap2/board-h4.c +++ b/arch/arm/mach-omap2/board-h4.c @@ -131,26 +131,6 @@ static struct platform_device h4_flash_device = { .resource = &h4_flash_resource, }; -static struct resource h4_smc91x_resources[] = { - [0] = { - .start = OMAP24XX_ETHR_START, /* Physical */ - .end = OMAP24XX_ETHR_START + 0xf, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = OMAP_GPIO_IRQ(OMAP24XX_ETHR_GPIO_IRQ), - .end = OMAP_GPIO_IRQ(OMAP24XX_ETHR_GPIO_IRQ), - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device h4_smc91x_device = { - .name = "smc91x", - .id = -1, - .num_resources = ARRAY_SIZE(h4_smc91x_resources), - .resource = h4_smc91x_resources, -}; - /* Select between the IrDA and aGPS module */ static int h4_select_irda(struct device *dev, int state) @@ -266,29 +246,14 @@ static struct platform_device h4_lcd_device = { .id = -1, }; -static struct resource h4_led_resources[] = { - [0] = { - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device h4_led_device = { - .name = "omap_dbg_led", - .id = -1, - .num_resources = ARRAY_SIZE(h4_led_resources), - .resource = h4_led_resources, -}; - static struct platform_device *h4_devices[] __initdata = { - &h4_smc91x_device, &h4_flash_device, &h4_irda_device, &h4_kp_device, &h4_lcd_device, - &h4_led_device, }; -static inline void __init h4_init_smc91x(void) +static inline void __init h4_init_debug(void) { /* Make sure CS1 timings are correct */ GPMC_CONFIG1_1 = 0x00011200; @@ -301,12 +266,8 @@ static inline void __init h4_init_smc91x(void) udelay(100); omap_cfg_reg(M15_24XX_GPIO92); - if (omap_request_gpio(OMAP24XX_ETHR_GPIO_IRQ) < 0) { - printk(KERN_ERR "Failed to request GPIO%d for smc91x IRQ\n", - OMAP24XX_ETHR_GPIO_IRQ); - return; - } - omap_set_gpio_direction(OMAP24XX_ETHR_GPIO_IRQ, 1); + if (debug_card_init(cs_mem_base, OMAP24XX_ETHR_GPIO_IRQ) < 0) + gpmc_cs_free(eth_cs); } static void __init omap_h4_init_irq(void) @@ -314,7 +275,6 @@ static void __init omap_h4_init_irq(void) omap2_init_common_hw(); omap_init_irq(); omap_gpio_init(); - h4_init_smc91x(); } static struct omap_uart_config h4_uart_config __initdata = { diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig index cfc69f3..c1f7e5a 100644 --- a/arch/arm/plat-omap/Kconfig +++ b/arch/arm/plat-omap/Kconfig @@ -20,10 +20,15 @@ endchoice comment "OMAP Feature Selections" -config OMAP_DEBUG_LEDS +config OMAP_DEBUG_DEVICES bool help - For debug card leds on TI reference boards. + For debug cards on TI reference boards. + +config OMAP_DEBUG_LEDS + bool + depends on OMAP_DEBUG_DEVICES + default y if LEDS || LEDS_OMAP_DEBUG config OMAP_RESET_CLOCKS bool "Reset unused clocks during boot" diff --git a/arch/arm/plat-omap/Makefile b/arch/arm/plat-omap/Makefile index 41a3c1c..2549129 100644 --- a/arch/arm/plat-omap/Makefile +++ b/arch/arm/plat-omap/Makefile @@ -17,4 +17,5 @@ obj-$(CONFIG_ARCH_OMAP16XX) += ocpi.o obj-$(CONFIG_CPU_FREQ) += cpu-omap.o obj-$(CONFIG_OMAP_DM_TIMER) += dmtimer.o +obj-$(CONFIG_OMAP_DEBUG_DEVICES) += debug-devices.o obj-$(CONFIG_OMAP_DEBUG_LEDS) += debug-leds.o diff --git a/arch/arm/plat-omap/debug-devices.c b/arch/arm/plat-omap/debug-devices.c new file mode 100644 index 0000000..83a5f8b --- /dev/null +++ b/arch/arm/plat-omap/debug-devices.c @@ -0,0 +1,86 @@ +/* + * linux/arch/arm/plat-omap/debug-devices.c + * + * Copyright (C) 2005 Nokia Corporation + * Modified from mach-omap2/board-h4.c + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include + +#include +#include + +#include +#include + + +/* Many OMAP development platforms reuse the same "debug board"; these + * platforms include H2, H3, H4, and Perseus2. + */ + +static struct resource smc91x_resources[] = { + [0] = { + .flags = IORESOURCE_MEM, + }, + [1] = { + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device smc91x_device = { + .name = "smc91x", + .id = -1, + .num_resources = ARRAY_SIZE(smc91x_resources), + .resource = smc91x_resources, +}; + +static struct resource led_resources[] = { + [0] = { + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device led_device = { + .name = "omap_dbg_led", + .id = -1, + .num_resources = ARRAY_SIZE(led_resources), + .resource = led_resources, +}; + +static struct platform_device *debug_devices[] __initdata = { + &smc91x_device, + &led_device, + /* ps2 kbd + mouse ports */ + /* 4 extra uarts */ + /* 6 input dip switches */ + /* 8 output pins */ +}; + +int __init debug_card_init(u32 addr, unsigned gpio) +{ + int status; + + smc91x_resources[0].start = addr + 0x300; + smc91x_resources[0].end = addr + 0x30f; + + smc91x_resources[1].start = OMAP_GPIO_IRQ(gpio); + smc91x_resources[1].end = OMAP_GPIO_IRQ(gpio); + + status = omap_request_gpio(gpio); + if (status < 0) { + printk(KERN_ERR "GPIO%d unavailable for smc91x IRQ\n", gpio); + return status; + } + omap_set_gpio_direction(gpio, 1); + + led_resources[0].start = addr; + led_resources[0].end = addr + SZ_4K - 1; + + return platform_add_devices(debug_devices, ARRAY_SIZE(debug_devices)); +} diff --git a/include/asm-arm/arch-omap/board.h b/include/asm-arm/arch-omap/board.h index 031672c..db44c5d1 100644 --- a/include/asm-arm/arch-omap/board.h +++ b/include/asm-arm/arch-omap/board.h @@ -179,4 +179,8 @@ extern const void *omap_get_var_config(u16 tag, size_t *len); extern struct omap_board_config_kernel *omap_board_config; extern int omap_board_config_size; + +/* for TI reference platforms sharing the same debug card */ +extern int debug_card_init(u32 addr, unsigned gpio); + #endif -- cgit v0.10.2 From 72d0f1c3cdc7c456e1e357359ec6f566d0a5f264 Mon Sep 17 00:00:00 2001 From: Syed Mohammed Khasim Date: Wed, 6 Dec 2006 17:14:05 -0800 Subject: ARM: OMAP: Add minimal OMAP2430 support This patch adds minimal OMAP2430 support to get the kernel booting on 2430SDP. Signed-off-by: Syed Mohammed Khasim Signed-off-by: Tony Lindgren diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index cf4268e..7069c9d 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig @@ -11,6 +11,10 @@ config ARCH_OMAP2420 select OMAP_DM_TIMER select ARCH_OMAP_OTG +config ARCH_OMAP2430 + bool "OMAP2430 support" + depends on ARCH_OMAP24XX + comment "OMAP Board Type" depends on ARCH_OMAP2 @@ -26,3 +30,8 @@ config MACH_OMAP_H4 config MACH_OMAP_APOLLON bool "OMAP 2420 Apollon board" depends on ARCH_OMAP2 && ARCH_OMAP24XX + +config MACH_OMAP_2430SDP + bool "OMAP 2430 SDP board" + depends on ARCH_OMAP2 && ARCH_OMAP24XX + diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index 266d88e..b05b738 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -14,5 +14,6 @@ obj-$(CONFIG_PM) += pm.o pm-domain.o sleep.o # Specific board support obj-$(CONFIG_MACH_OMAP_GENERIC) += board-generic.o obj-$(CONFIG_MACH_OMAP_H4) += board-h4.o +obj-$(CONFIG_MACH_OMAP_2430SDP) += board-2430sdp.o obj-$(CONFIG_MACH_OMAP_APOLLON) += board-apollon.o diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c new file mode 100644 index 0000000..7e76fbf --- /dev/null +++ b/arch/arm/mach-omap2/board-2430sdp.c @@ -0,0 +1,218 @@ +/* + * linux/arch/arm/mach-omap2/board-2430sdp.c + * + * Copyright (C) 2006 Texas Instruments + * + * Modified from mach-omap2/board-generic.c + * + * Initial Code : Based on a patch from Komal Shah and Richard Woodruff + * Updated the Code for 2430 SDP : Syed Mohammed Khasim + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include "prcm-regs.h" + +#include + + +#define SDP2430_FLASH_CS 0 +#define SDP2430_SMC91X_CS 5 + +static struct mtd_partition sdp2430_partitions[] = { + /* bootloader (U-Boot, etc) in first sector */ + { + .name = "bootloader", + .offset = 0, + .size = SZ_256K, + .mask_flags = MTD_WRITEABLE, /* force read-only */ + }, + /* bootloader params in the next sector */ + { + .name = "params", + .offset = MTDPART_OFS_APPEND, + .size = SZ_128K, + .mask_flags = 0, + }, + /* kernel */ + { + .name = "kernel", + .offset = MTDPART_OFS_APPEND, + .size = SZ_2M, + .mask_flags = 0 + }, + /* file system */ + { + .name = "filesystem", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + .mask_flags = 0 + } +}; + +static struct flash_platform_data sdp2430_flash_data = { + .map_name = "cfi_probe", + .width = 2, + .parts = sdp2430_partitions, + .nr_parts = ARRAY_SIZE(sdp2430_partitions), +}; + +static struct resource sdp2430_flash_resource = { + .start = SDP2430_CS0_BASE, + .end = SDP2430_CS0_BASE + SZ_64M - 1, + .flags = IORESOURCE_MEM, +}; + +static struct platform_device sdp2430_flash_device = { + .name = "omapflash", + .id = 0, + .dev = { + .platform_data = &sdp2430_flash_data, + }, + .num_resources = 1, + .resource = &sdp2430_flash_resource, +}; + +static struct resource sdp2430_smc91x_resources[] = { + [0] = { + .start = SDP2430_CS0_BASE, + .end = SDP2430_CS0_BASE + SZ_64M - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = OMAP_GPIO_IRQ(OMAP24XX_ETHR_GPIO_IRQ), + .end = OMAP_GPIO_IRQ(OMAP24XX_ETHR_GPIO_IRQ), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device sdp2430_smc91x_device = { + .name = "smc91x", + .id = -1, + .num_resources = ARRAY_SIZE(sdp2430_smc91x_resources), + .resource = sdp2430_smc91x_resources, +}; + +static struct platform_device *sdp2430_devices[] __initdata = { + &sdp2430_smc91x_device, + &sdp2430_flash_device, +}; + +static inline void __init sdp2430_init_smc91x(void) +{ + int eth_cs; + unsigned long cs_mem_base; + unsigned int rate; + struct clk *l3ck; + + eth_cs = SDP2430_SMC91X_CS; + + l3ck = clk_get(NULL, "core_l3_ck"); + if (IS_ERR(l3ck)) + rate = 100000000; + else + rate = clk_get_rate(l3ck); + + /* Make sure CS1 timings are correct, for 2430 always muxed */ + gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG1, 0x00011200); + + if (rate >= 160000000) { + gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG2, 0x001f1f01); + gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG3, 0x00080803); + gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG4, 0x1c0b1c0a); + gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG5, 0x041f1F1F); + gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG6, 0x000004C4); + } else if (rate >= 130000000) { + gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG2, 0x001f1f00); + gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG3, 0x00080802); + gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG4, 0x1C091C09); + gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG5, 0x041f1F1F); + gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG6, 0x000004C4); + } else { /* rate = 100000000 */ + gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG2, 0x001f1f00); + gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG3, 0x00080802); + gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG4, 0x1C091C09); + gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG5, 0x031A1F1F); + gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG6, 0x000003C2); + } + + if (gpmc_cs_request(eth_cs, SZ_16M, &cs_mem_base) < 0) { + printk(KERN_ERR "Failed to request GPMC mem for smc91x\n"); + return; + } + + sdp2430_smc91x_resources[0].start = cs_mem_base + 0x300; + sdp2430_smc91x_resources[0].end = cs_mem_base + 0x30f; + udelay(100); + + if (omap_request_gpio(OMAP24XX_ETHR_GPIO_IRQ) < 0) { + printk(KERN_ERR "Failed to request GPIO%d for smc91x IRQ\n", + OMAP24XX_ETHR_GPIO_IRQ); + gpmc_cs_free(eth_cs); + return; + } + omap_set_gpio_direction(OMAP24XX_ETHR_GPIO_IRQ, 1); + +} + +static void __init omap_2430sdp_init_irq(void) +{ + omap2_init_common_hw(); + omap_init_irq(); + omap_gpio_init(); + sdp2430_init_smc91x(); +} + +static struct omap_uart_config sdp2430_uart_config __initdata = { + .enabled_uarts = ((1 << 0) | (1 << 1) | (1 << 2)), +}; + +static struct omap_board_config_kernel sdp2430_config[] = { + {OMAP_TAG_UART, &sdp2430_uart_config}, +}; + +static void __init omap_2430sdp_init(void) +{ + platform_add_devices(sdp2430_devices, ARRAY_SIZE(sdp2430_devices)); + omap_board_config = sdp2430_config; + omap_board_config_size = ARRAY_SIZE(sdp2430_config); + omap_serial_init(); +} + +static void __init omap_2430sdp_map_io(void) +{ + omap2_map_common_io(); +} + +MACHINE_START(OMAP_2430SDP, "OMAP2430 sdp2430 board") + /* Maintainer: Syed Khasim - Texas Instruments Inc */ + .phys_io = 0x48000000, + .io_pg_offst = ((0xd8000000) >> 18) & 0xfffc, + .boot_params = 0x80000100, + .map_io = omap_2430sdp_map_io, + .init_irq = omap_2430sdp_init_irq, + .init_machine = omap_2430sdp_init, + .timer = &omap_timer, +MACHINE_END diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c index 52ec2f2..b603bc5 100644 --- a/arch/arm/mach-omap2/devices.c +++ b/arch/arm/mach-omap2/devices.c @@ -55,8 +55,10 @@ static void omap_init_i2c(void) if (machine_is_omap_h4()) return; - omap_cfg_reg(J15_24XX_I2C2_SCL); - omap_cfg_reg(H19_24XX_I2C2_SDA); + if (!cpu_is_omap2430()) { + omap_cfg_reg(J15_24XX_I2C2_SCL); + omap_cfg_reg(H19_24XX_I2C2_SDA); + } (void) platform_device_register(&omap_i2c_device2); } diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c index 6d6b25c..03595ee 100644 --- a/arch/arm/mach-omap2/gpmc.c +++ b/arch/arm/mach-omap2/gpmc.c @@ -22,7 +22,14 @@ #undef DEBUG +#ifdef CONFIG_ARCH_OMAP2420 #define GPMC_BASE 0x6800a000 +#endif + +#ifdef CONFIG_ARCH_OMAP2430 +#define GPMC_BASE 0x6E000000 +#endif + #define GPMC_REVISION 0x00 #define GPMC_SYSCONFIG 0x10 #define GPMC_SYSSTATUS 0x14 diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c index 871ace4..4dfd878 100644 --- a/arch/arm/mach-omap2/id.c +++ b/arch/arm/mach-omap2/id.c @@ -17,7 +17,13 @@ #include +#if defined(CONFIG_ARCH_OMAP2420) #define OMAP24XX_TAP_BASE io_p2v(0x48014000) +#endif + +#if defined(CONFIG_ARCH_OMAP2430) +#define OMAP24XX_TAP_BASE io_p2v(0x4900A000) +#endif #define OMAP_TAP_IDCODE 0x0204 #define OMAP_TAP_PROD_ID 0x0208 diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c index a57a429..5a4091f 100644 --- a/arch/arm/mach-omap2/io.c +++ b/arch/arm/mach-omap2/io.c @@ -5,6 +5,7 @@ * * Copyright (C) 2005 Nokia Corporation * Author: Juha Yrjölä + * Updated map desc to add 2430 support : * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -41,6 +42,20 @@ static struct map_desc omap2_io_desc[] __initdata = { .length = L3_24XX_SIZE, .type = MT_DEVICE }, +#ifdef CONFIG_ARCH_OMAP2430 + { + .virtual = L4_WK_243X_VIRT, + .pfn = __phys_to_pfn(L4_WK_243X_PHYS), + .length = L4_WK_243X_SIZE, + .type = MT_DEVICE + }, + { + .virtual = OMAP243X_GPMC_VIRT, + .pfn = __phys_to_pfn(OMAP243X_GPMC_PHYS), + .length = OMAP243X_GPMC_SIZE, + .type = MT_DEVICE + }, +#endif { .virtual = DSP_MEM_24XX_VIRT, .pfn = __phys_to_pfn(DSP_MEM_24XX_PHYS), @@ -81,6 +96,11 @@ void __init omap2_init_common_hw(void) { omap2_mux_init(); omap2_clk_init(); +/* + * Need to Fix this for 2430 + */ +#ifndef CONFIG_ARCH_OMAP2430 omap2_init_memory(); +#endif gpmc_init(); } diff --git a/include/asm-arm/arch-omap/board-2430sdp.h b/include/asm-arm/arch-omap/board-2430sdp.h new file mode 100644 index 0000000..e9c65ce --- /dev/null +++ b/include/asm-arm/arch-omap/board-2430sdp.h @@ -0,0 +1,44 @@ +/* + * linux/include/asm-arm/arch-omap/board-2430sdp.h + * + * Hardware definitions for TI OMAP2430 SDP board. + * + * Based on board-h4.h by Dirk Behme + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef __ASM_ARCH_OMAP_2430SDP_H +#define __ASM_ARCH_OMAP_2430SDP_H + +/* Placeholder for 2430SDP specific defines */ +#define OMAP24XX_ETHR_START 0x08000300 +#define OMAP24XX_ETHR_GPIO_IRQ 149 +#define SDP2430_CS0_BASE 0x04000000 + +#define TWL4030_IRQNUM INT_24XX_SYS_NIRQ + +/* TWL4030 Primary Interrupt Handler (PIH) interrupts */ +#define IH_TWL4030_BASE IH_BOARD_BASE +#define IH_TWL4030_END (IH_TWL4030_BASE+8) +#define NR_IRQS (IH_TWL4030_END) + +#endif /* __ASM_ARCH_OMAP_2430SDP_H */ diff --git a/include/asm-arm/arch-omap/hardware.h b/include/asm-arm/arch-omap/hardware.h index e225f4f..98a8eb8 100644 --- a/include/asm-arm/arch-omap/hardware.h +++ b/include/asm-arm/arch-omap/hardware.h @@ -318,6 +318,10 @@ #include "board-h4.h" #endif +#ifdef CONFIG_MACH_OMAP_2430SDP +#include "board-2430sdp.h" +#endif + #ifdef CONFIG_MACH_OMAP_APOLLON #include "board-apollon.h" #endif diff --git a/include/asm-arm/arch-omap/io.h b/include/asm-arm/arch-omap/io.h index 4aca7e3..289082d 100644 --- a/include/asm-arm/arch-omap/io.h +++ b/include/asm-arm/arch-omap/io.h @@ -72,6 +72,16 @@ #define L4_24XX_PHYS L4_24XX_BASE /* 0x48000000 */ #define L4_24XX_VIRT 0xd8000000 #define L4_24XX_SIZE SZ_1M /* 1MB of 128MB used, want 1MB sect */ + +#ifdef CONFIG_ARCH_OMAP2430 +#define L4_WK_243X_PHYS L4_WK_243X_BASE /* 0x49000000 */ +#define L4_WK_243X_VIRT 0xd9000000 +#define L4_WK_243X_SIZE SZ_1M +#define OMAP243X_GPMC_PHYS OMAP243X_GPMC_BASE /* 0x49000000 */ +#define OMAP243X_GPMC_VIRT 0xFE000000 +#define OMAP243X_GPMC_SIZE SZ_1M +#endif + #define IO_OFFSET 0x90000000 #define IO_ADDRESS(pa) ((pa) + IO_OFFSET) /* Works for L3 and L4 */ #define io_p2v(pa) ((pa) + IO_OFFSET) /* Works for L3 and L4 */ diff --git a/include/asm-arm/arch-omap/omap24xx.h b/include/asm-arm/arch-omap/omap24xx.h index 708b2fa..14c0f94 100644 --- a/include/asm-arm/arch-omap/omap24xx.h +++ b/include/asm-arm/arch-omap/omap24xx.h @@ -8,6 +8,7 @@ */ #define L4_24XX_BASE 0x48000000 +#define L4_WK_243X_BASE 0x49000000 #define L3_24XX_BASE 0x68000000 /* interrupt controller */ @@ -16,9 +17,20 @@ #define OMAP24XX_IVA_INTC_BASE 0x40000000 #define IRQ_SIR_IRQ 0x0040 +#ifdef CONFIG_ARCH_OMAP2420 #define OMAP24XX_32KSYNCT_BASE (L4_24XX_BASE + 0x4000) #define OMAP24XX_PRCM_BASE (L4_24XX_BASE + 0x8000) #define OMAP24XX_SDRC_BASE (L3_24XX_BASE + 0x9000) +#define OMAP242X_CONTROL_STATUS (L4_24XX_BASE + 0x2f8) +#endif + +#ifdef CONFIG_ARCH_OMAP2430 +#define OMAP24XX_32KSYNCT_BASE (L4_WK_243X_BASE + 0x20000) +#define OMAP24XX_PRCM_BASE (L4_WK_243X_BASE + 0x6000) +#define OMAP24XX_SDRC_BASE (0x6D000000) +#define OMAP242X_CONTROL_STATUS (L4_24XX_BASE + 0x2f8) +#define OMAP243X_GPMC_BASE 0x6E000000 +#endif /* DSP SS */ #define OMAP24XX_DSP_BASE 0x58000000 -- cgit v0.10.2 From 7d34f3b3901cf31611183f158b949d8a823a9762 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Thu, 7 Dec 2006 14:01:29 -0800 Subject: ARM: OMAP: Tabify mux.c Tabify mux.c, no functional changes. Signed-off-by: Tony Lindgren diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c index 0439906..0575097 100644 --- a/arch/arm/mach-omap2/mux.c +++ b/arch/arm/mach-omap2/mux.c @@ -53,8 +53,8 @@ MUX_CFG_24XX("W19_24XX_SYS_NIRQ", 0x12c, 0, 1, 1, 1) MUX_CFG_24XX("W14_24XX_SYS_CLKOUT", 0x137, 0, 1, 1, 1) /* 24xx GPMC chipselects, wait pin monitoring */ -MUX_CFG_24XX("E2_GPMC_NCS2", 0x08e, 0, 1, 1, 1) -MUX_CFG_24XX("L2_GPMC_NCS7", 0x093, 0, 1, 1, 1) +MUX_CFG_24XX("E2_GPMC_NCS2", 0x08e, 0, 1, 1, 1) +MUX_CFG_24XX("L2_GPMC_NCS7", 0x093, 0, 1, 1, 1) MUX_CFG_24XX("L3_GPMC_WAIT0", 0x09a, 0, 1, 1, 1) MUX_CFG_24XX("N7_GPMC_WAIT1", 0x09b, 0, 1, 1, 1) MUX_CFG_24XX("M1_GPMC_WAIT2", 0x09c, 0, 1, 1, 1) @@ -67,18 +67,18 @@ MUX_CFG_24XX("W15_24XX_MCBSP2_DR", 0x126, 1, 1, 0, 1) MUX_CFG_24XX("V15_24XX_MCBSP2_DX", 0x127, 1, 1, 0, 1) /* 24xx GPIO */ -MUX_CFG_24XX("M21_242X_GPIO11", 0x0c9, 3, 1, 1, 1) -MUX_CFG_24XX("P21_242X_GPIO12", 0x0ca, 3, 0, 0, 1) -MUX_CFG_24XX("AA10_242X_GPIO13", 0x0e5, 3, 0, 0, 1) -MUX_CFG_24XX("AA6_242X_GPIO14", 0x0e6, 3, 0, 0, 1) -MUX_CFG_24XX("AA4_242X_GPIO15", 0x0e7, 3, 0, 0, 1) -MUX_CFG_24XX("Y11_242X_GPIO16", 0x0e8, 3, 0, 0, 1) -MUX_CFG_24XX("AA12_242X_GPIO17", 0x0e9, 3, 0, 0, 1) -MUX_CFG_24XX("AA8_242X_GPIO58", 0x0ea, 3, 0, 0, 1) +MUX_CFG_24XX("M21_242X_GPIO11", 0x0c9, 3, 1, 1, 1) +MUX_CFG_24XX("P21_242X_GPIO12", 0x0ca, 3, 0, 0, 1) +MUX_CFG_24XX("AA10_242X_GPIO13", 0x0e5, 3, 0, 0, 1) +MUX_CFG_24XX("AA6_242X_GPIO14", 0x0e6, 3, 0, 0, 1) +MUX_CFG_24XX("AA4_242X_GPIO15", 0x0e7, 3, 0, 0, 1) +MUX_CFG_24XX("Y11_242X_GPIO16", 0x0e8, 3, 0, 0, 1) +MUX_CFG_24XX("AA12_242X_GPIO17", 0x0e9, 3, 0, 0, 1) +MUX_CFG_24XX("AA8_242X_GPIO58", 0x0ea, 3, 0, 0, 1) MUX_CFG_24XX("Y20_24XX_GPIO60", 0x12c, 3, 0, 0, 1) -MUX_CFG_24XX("W4__24XX_GPIO74", 0x0f2, 3, 0, 0, 1) +MUX_CFG_24XX("W4__24XX_GPIO74", 0x0f2, 3, 0, 0, 1) MUX_CFG_24XX("M15_24XX_GPIO92", 0x10a, 3, 0, 0, 1) -MUX_CFG_24XX("J15_24XX_GPIO99", 0x113, 3, 1, 1, 1) +MUX_CFG_24XX("J15_24XX_GPIO99", 0x113, 3, 1, 1, 1) MUX_CFG_24XX("V14_24XX_GPIO117", 0x128, 3, 1, 0, 1) MUX_CFG_24XX("P14_24XX_GPIO125", 0x140, 3, 1, 1, 1) @@ -95,17 +95,17 @@ MUX_CFG_24XX("T3_242X_GPIO55", 0xd9, 3, 0, 0, 1) MUX_CFG_24XX("U2_242X_GPIO56", 0xda, 3, 0, 0, 1) /* 24xx external DMA requests */ -MUX_CFG_24XX("AA10_242X_DMAREQ0", 0x0e5, 2, 0, 0, 1) -MUX_CFG_24XX("AA6_242X_DMAREQ1", 0x0e6, 2, 0, 0, 1) -MUX_CFG_24XX("E4_242X_DMAREQ2", 0x074, 2, 0, 0, 1) -MUX_CFG_24XX("G4_242X_DMAREQ3", 0x073, 2, 0, 0, 1) -MUX_CFG_24XX("D3_242X_DMAREQ4", 0x072, 2, 0, 0, 1) -MUX_CFG_24XX("E3_242X_DMAREQ5", 0x071, 2, 0, 0, 1) +MUX_CFG_24XX("AA10_242X_DMAREQ0", 0x0e5, 2, 0, 0, 1) +MUX_CFG_24XX("AA6_242X_DMAREQ1", 0x0e6, 2, 0, 0, 1) +MUX_CFG_24XX("E4_242X_DMAREQ2", 0x074, 2, 0, 0, 1) +MUX_CFG_24XX("G4_242X_DMAREQ3", 0x073, 2, 0, 0, 1) +MUX_CFG_24XX("D3_242X_DMAREQ4", 0x072, 2, 0, 0, 1) +MUX_CFG_24XX("E3_242X_DMAREQ5", 0x071, 2, 0, 0, 1) /* TSC IRQ */ MUX_CFG_24XX("P20_24XX_TSC_IRQ", 0x108, 0, 0, 0, 1) -/* UART3 */ +/* UART3 */ MUX_CFG_24XX("K15_24XX_UART3_TX", 0x118, 0, 0, 0, 1) MUX_CFG_24XX("K14_24XX_UART3_RX", 0x119, 0, 0, 0, 1) -- cgit v0.10.2 From c1ed6407cddbd87206b860f6207731d51c1d57bf Mon Sep 17 00:00:00 2001 From: David Brownell Date: Thu, 7 Dec 2006 14:03:49 -0800 Subject: ARM: OMAP: TUSB EVM init Add init support for the TUSB6010 EVM board, as connected to H4. Signed-off-by: David Brownell Signed-off-by: Tony Lindgren diff --git a/arch/arm/mach-omap2/usb-tusb6010.c b/arch/arm/mach-omap2/usb-tusb6010.c new file mode 100644 index 0000000..80bb42e --- /dev/null +++ b/arch/arm/mach-omap2/usb-tusb6010.c @@ -0,0 +1,349 @@ +/* + * linux/arch/arm/mach-omap2/usb-tusb6010.c + * + * Copyright (C) 2006 Nokia Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include + +#include + +#include +#include +#include + + +static u8 async_cs, sync_cs; +static unsigned refclk_psec; + + +/* t2_ps, when quantized to fclk units, must happen no earlier than + * the clock after after t1_NS. + * + * Return a possibly updated value of t2_ps, converted to nsec. + */ +static unsigned +next_clk(unsigned t1_NS, unsigned t2_ps, unsigned fclk_ps) +{ + unsigned t1_ps = t1_NS * 1000; + unsigned t1_f, t2_f; + + if ((t1_ps + fclk_ps) < t2_ps) + return t2_ps / 1000; + + t1_f = (t1_ps + fclk_ps - 1) / fclk_ps; + t2_f = (t2_ps + fclk_ps - 1) / fclk_ps; + + if (t1_f >= t2_f) + t2_f = t1_f + 1; + + return (t2_f * fclk_ps) / 1000; +} + +/* NOTE: timings are from tusb 6010 datasheet Rev 1.8, 12-Sept 2006 */ + +static int tusb_set_async_mode(unsigned sysclk_ps, unsigned fclk_ps) +{ + struct gpmc_timings t; + unsigned t_acsnh_advnh = sysclk_ps + 3000; + unsigned tmp; + + memset(&t, 0, sizeof(t)); + + /* CS_ON = t_acsnh_acsnl */ + t.cs_on = 8; + /* ADV_ON = t_acsnh_advnh - t_advn */ + t.adv_on = next_clk(t.cs_on, t_acsnh_advnh - 7000, fclk_ps); + + /* + * READ ... from omap2420 TRM fig 12-13 + */ + + /* ADV_RD_OFF = t_acsnh_advnh */ + t.adv_rd_off = next_clk(t.adv_on, t_acsnh_advnh, fclk_ps); + + /* OE_ON = t_acsnh_advnh + t_advn_oen (then wait for nRDY) */ + t.oe_on = next_clk(t.adv_on, t_acsnh_advnh + 1000, fclk_ps); + + /* ACCESS = counters continue only after nRDY */ + tmp = t.oe_on * 1000 + 300; + t.access = next_clk(t.oe_on, tmp, fclk_ps); + + /* OE_OFF = after data gets sampled */ + tmp = t.access * 1000; + t.oe_off = next_clk(t.access, tmp, fclk_ps); + + t.cs_rd_off = t.oe_off; + + tmp = t.cs_rd_off * 1000 + 7000 /* t_acsn_rdy_z */; + t.rd_cycle = next_clk(t.cs_rd_off, tmp, fclk_ps); + + /* + * WRITE ... from omap2420 TRM fig 12-15 + */ + + /* ADV_WR_OFF = t_acsnh_advnh */ + t.adv_wr_off = t.adv_rd_off; + + /* WE_ON = t_acsnh_advnh + t_advn_wen (then wait for nRDY) */ + t.we_on = next_clk(t.adv_wr_off, t_acsnh_advnh + 1000, fclk_ps); + + /* WE_OFF = after data gets sampled */ + tmp = t.we_on * 1000 + 300; + t.we_off = next_clk(t.we_on, tmp, fclk_ps); + + t.cs_wr_off = t.we_off; + + tmp = t.cs_wr_off * 1000 + 7000 /* t_acsn_rdy_z */; + t.wr_cycle = next_clk(t.cs_wr_off, tmp, fclk_ps); + + return gpmc_cs_set_timings(async_cs, &t); +} + +static int tusb_set_sync_mode(unsigned sysclk_ps, unsigned fclk_ps) +{ + struct gpmc_timings t; + unsigned t_scsnh_advnh = sysclk_ps + 3000; + unsigned tmp; + + memset(&t, 0, sizeof(t)); + t.cs_on = 8; + + /* ADV_ON = t_acsnh_advnh - t_advn */ + t.adv_on = next_clk(t.cs_on, t_scsnh_advnh - 7000, fclk_ps); + + /* GPMC_CLK rate = fclk rate / div */ + t.sync_clk = 12 /* 11.1 nsec */; + tmp = (t.sync_clk * 1000 + fclk_ps - 1) / fclk_ps; + if (tmp > 4) + return -ERANGE; + if (tmp <= 0) + tmp = 1; + t.page_burst_access = (fclk_ps * tmp) / 1000; + + /* + * READ ... based on omap2420 TRM fig 12-19, 12-20 + */ + + /* ADV_RD_OFF = t_scsnh_advnh */ + t.adv_rd_off = next_clk(t.adv_on, t_scsnh_advnh, fclk_ps); + + /* OE_ON = t_scsnh_advnh + t_advn_oen * fclk_ps (then wait for nRDY) */ + tmp = (t.adv_rd_off * 1000) + (3 * fclk_ps); + t.oe_on = next_clk(t.adv_on, tmp, fclk_ps); + + /* ACCESS = number of clock cycles after t_adv_eon */ + tmp = (t.oe_on * 1000) + (5 * fclk_ps); + t.access = next_clk(t.oe_on, tmp, fclk_ps); + + /* OE_OFF = after data gets sampled */ + tmp = (t.access * 1000) + (1 * fclk_ps); + t.oe_off = next_clk(t.access, tmp, fclk_ps); + + t.cs_rd_off = t.oe_off; + + tmp = t.cs_rd_off * 1000 + 7000 /* t_scsn_rdy_z */; + t.rd_cycle = next_clk(t.cs_rd_off, tmp, fclk_ps); + + /* + * WRITE ... based on omap2420 TRM fig 12-21 + */ + + /* ADV_WR_OFF = t_scsnh_advnh */ + t.adv_wr_off = t.adv_rd_off; + + /* WE_ON = t_scsnh_advnh + t_advn_wen * fclk_ps (then wait for nRDY) */ + tmp = (t.adv_wr_off * 1000) + (3 * fclk_ps); + t.we_on = next_clk(t.adv_wr_off, tmp, fclk_ps); + + /* WE_OFF = number of clock cycles after t_adv_wen */ + tmp = (t.we_on * 1000) + (6 * fclk_ps); + t.we_off = next_clk(t.we_on, tmp, fclk_ps); + + t.cs_wr_off = t.we_off; + + tmp = t.cs_wr_off * 1000 + 7000 /* t_scsn_rdy_z */; + t.wr_cycle = next_clk(t.cs_wr_off, tmp, fclk_ps); + + return gpmc_cs_set_timings(sync_cs, &t); +} + +extern unsigned long gpmc_get_fclk_period(void); + +/* tusb driver calls this when it changes the chip's clocking */ +int tusb6010_platform_retime(unsigned is_refclk) +{ + static const char error[] = + KERN_ERR "tusb6010 %s retime error %d\n"; + + unsigned fclk_ps = gpmc_get_fclk_period(); + unsigned sysclk_ps; + int status; + + if (!refclk_psec) + return -ENODEV; + + sysclk_ps = is_refclk ? refclk_psec : TUSB6010_OSCCLK_60; + + status = tusb_set_async_mode(sysclk_ps, fclk_ps); + if (status < 0) { + printk(error, "async", status); + goto done; + } + status = tusb_set_sync_mode(sysclk_ps, fclk_ps); + if (status < 0) + printk(error, "sync", status); +done: + return status; +} +EXPORT_SYMBOL_GPL(tusb6010_platform_retime); + +static struct resource tusb_resources[] = { + /* Order is significant! The start/end fields + * are updated during setup.. + */ + { /* Asynchronous access */ + .flags = IORESOURCE_MEM, + }, + { /* Synchronous access */ + .flags = IORESOURCE_MEM, + }, + { /* IRQ */ + .flags = IORESOURCE_IRQ, + }, +}; + +static u64 tusb_dmamask = ~(u32)0; + +static struct platform_device tusb_device = { + .name = "musb_hdrc", + .id = -1, + .dev = { + .dma_mask = &tusb_dmamask, + .coherent_dma_mask = 0xffffffff, + }, + .num_resources = ARRAY_SIZE(tusb_resources), + .resource = tusb_resources, +}; + + +/* this may be called only from board-*.c setup code */ +int __init +tusb6010_setup_interface(struct musb_hdrc_platform_data *data, + unsigned ps_refclk, unsigned waitpin, + unsigned async, unsigned sync, + unsigned irq, unsigned dmachan) +{ + int status; + static char error[] __initdata = + KERN_ERR "tusb6010 init error %d, %d\n"; + + /* ASYNC region, primarily for PIO */ + status = gpmc_cs_request(async, SZ_16M, (unsigned long *) + &tusb_resources[0].start); + if (status < 0) { + printk(error, 1, status); + return status; + } + tusb_resources[0].end = tusb_resources[0].start + 0x9ff; + async_cs = async; + gpmc_cs_write_reg(async, GPMC_CS_CONFIG1, + GPMC_CONFIG1_PAGE_LEN(2) + | GPMC_CONFIG1_WAIT_READ_MON + | GPMC_CONFIG1_WAIT_WRITE_MON + | GPMC_CONFIG1_WAIT_PIN_SEL(waitpin) + | GPMC_CONFIG1_READTYPE_ASYNC + | GPMC_CONFIG1_WRITETYPE_ASYNC + | GPMC_CONFIG1_DEVICESIZE_16 + | GPMC_CONFIG1_DEVICETYPE_NOR + | GPMC_CONFIG1_MUXADDDATA); + + + /* SYNC region, primarily for DMA */ + status = gpmc_cs_request(sync, SZ_16M, (unsigned long *) + &tusb_resources[1].start); + if (status < 0) { + printk(error, 2, status); + return status; + } + tusb_resources[1].end = tusb_resources[1].start + 0x9ff; + sync_cs = sync; + gpmc_cs_write_reg(sync, GPMC_CS_CONFIG1, + GPMC_CONFIG1_READMULTIPLE_SUPP + | GPMC_CONFIG1_READTYPE_SYNC + | GPMC_CONFIG1_WRITEMULTIPLE_SUPP + | GPMC_CONFIG1_WRITETYPE_SYNC + | GPMC_CONFIG1_CLKACTIVATIONTIME(1) + | GPMC_CONFIG1_PAGE_LEN(2) + | GPMC_CONFIG1_WAIT_READ_MON + | GPMC_CONFIG1_WAIT_WRITE_MON + | GPMC_CONFIG1_WAIT_PIN_SEL(waitpin) + | GPMC_CONFIG1_DEVICESIZE_16 + | GPMC_CONFIG1_DEVICETYPE_NOR + | GPMC_CONFIG1_MUXADDDATA + /* fclk divider gets set later */ + ); + + /* IRQ */ + status = omap_request_gpio(irq); + if (status < 0) { + printk(error, 3, status); + return status; + } + omap_set_gpio_direction(irq, 1); + tusb_resources[2].start = irq + IH_GPIO_BASE; + + /* set up memory timings ... can speed them up later */ + if (!ps_refclk) { + printk(error, 4, status); + return -ENODEV; + } + refclk_psec = ps_refclk; + status = tusb6010_platform_retime(1); + if (status < 0) { + printk(error, 5, status); + return status; + } + + /* finish device setup ... */ + if (!data) { + printk(error, 6, status); + return -ENODEV; + } + data->multipoint = 1; + tusb_device.dev.platform_data = data; + + /* REVISIT let the driver know what DMA channels work */ + if (!dmachan) + tusb_device.dev.dma_mask = NULL; + else { + /* assume OMAP 2420 ES2.0 and later */ + if (dmachan & (1 << 0)) + omap_cfg_reg(AA10_242X_DMAREQ0); + if (dmachan & (1 << 1)) + omap_cfg_reg(AA6_242X_DMAREQ1); + if (dmachan & (1 << 2)) + omap_cfg_reg(E4_242X_DMAREQ2); + if (dmachan & (1 << 3)) + omap_cfg_reg(G4_242X_DMAREQ3); + if (dmachan & (1 << 4)) + omap_cfg_reg(D3_242X_DMAREQ4); + if (dmachan & (1 << 5)) + omap_cfg_reg(E3_242X_DMAREQ5); + } + + /* so far so good ... register the device */ + status = platform_device_register(&tusb_device); + if (status < 0) { + printk(error, 7, status); + return status; + } + return 0; +} -- cgit v0.10.2 From 23300597948131d07eebeb1308c2ba0a1c147494 Mon Sep 17 00:00:00 2001 From: Kai Svahn Date: Fri, 26 Jan 2007 12:29:40 -0800 Subject: ARM: OMAP: Merge gpmc changes from N800 tree This patch merges gpmc changes from N800 tree and adds gpmc_get_fclk_period() to gpmc.h. Signed-off-by: Kai Svahn Signed-off-by: Tony Lindgren diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c index 03595ee..5a4cc20 100644 --- a/arch/arm/mach-omap2/gpmc.c +++ b/arch/arm/mach-omap2/gpmc.c @@ -111,6 +111,13 @@ unsigned int gpmc_ns_to_ticks(unsigned int time_ns) return (time_ns * 1000 + tick_ps - 1) / tick_ps; } +unsigned int gpmc_round_ns_to_ticks(unsigned int time_ns) +{ + unsigned long ticks = gpmc_ns_to_ticks(time_ns); + + return ticks * gpmc_get_fclk_period() / 1000; +} + #ifdef DEBUG static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit, int time, const char *name) diff --git a/include/asm-arm/arch-omap/gpmc.h b/include/asm-arm/arch-omap/gpmc.h index 434672d..6a8e07f 100644 --- a/include/asm-arm/arch-omap/gpmc.h +++ b/include/asm-arm/arch-omap/gpmc.h @@ -81,6 +81,8 @@ struct gpmc_timings { }; extern unsigned int gpmc_ns_to_ticks(unsigned int time_ns); +extern unsigned int gpmc_round_ns_to_ticks(unsigned int time_ns); +extern unsigned long gpmc_get_fclk_period(void); extern void gpmc_cs_write_reg(int cs, int idx, u32 val); extern u32 gpmc_cs_read_reg(int cs, int idx); -- cgit v0.10.2 From 8777297b5e5fb7f908b51b56548b7cf7dbbf2022 Mon Sep 17 00:00:00 2001 From: Kai Svahn Date: Fri, 26 Jan 2007 13:14:34 -0800 Subject: ARM: OMAP: Merge driver headers from N800 tree This patch merges omap specific driver headers from N800 tree. Signed-off-by: Kai Svahn Signed-off-by: Tony Lindgren diff --git a/include/asm-arm/arch-omap/blizzard.h b/include/asm-arm/arch-omap/blizzard.h new file mode 100644 index 0000000..8d160f1 --- /dev/null +++ b/include/asm-arm/arch-omap/blizzard.h @@ -0,0 +1,12 @@ +#ifndef _BLIZZARD_H +#define _BLIZZARD_H + +struct blizzard_platform_data { + void (*power_up)(struct device *dev); + void (*power_down)(struct device *dev); + unsigned long (*get_clock_rate)(struct device *dev); + + unsigned te_connected : 1; +}; + +#endif diff --git a/include/asm-arm/arch-omap/eac.h b/include/asm-arm/arch-omap/eac.h new file mode 100644 index 0000000..6662cb0 --- /dev/null +++ b/include/asm-arm/arch-omap/eac.h @@ -0,0 +1,101 @@ +/* + * linux/include/asm-arm/arch-omap2/eac.h + * + * Defines for Enhanced Audio Controller + * + * Contact: Jarkko Nikula + * + * Copyright (C) 2006 Nokia Corporation + * Copyright (C) 2004 Texas Instruments, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA + * 02110-1301 USA + * + */ + +#ifndef __ASM_ARM_ARCH_OMAP2_EAC_H +#define __ASM_ARM_ARCH_OMAP2_EAC_H + +#include +#include +#include + +#include +#include + +/* master codec clock source */ +#define EAC_MCLK_EXT_MASK 0x100 +enum eac_mclk_src { + EAC_MCLK_INT_11290000, /* internal 96 MHz / 8.5 = 11.29 Mhz */ + EAC_MCLK_EXT_11289600 = EAC_MCLK_EXT_MASK, + EAC_MCLK_EXT_12288000, + EAC_MCLK_EXT_2x11289600, + EAC_MCLK_EXT_2x12288000, +}; + +/* codec port interface mode */ +enum eac_codec_mode { + EAC_CODEC_PCM, + EAC_CODEC_AC97, + EAC_CODEC_I2S_MASTER, /* codec port, I.e. EAC is the master */ + EAC_CODEC_I2S_SLAVE, +}; + +/* configuration structure for I2S mode */ +struct eac_i2s_conf { + /* if enabled, then first data slot (left channel) is signaled as + * positive level of frame sync EAC.AC_FS */ + unsigned polarity_changed_mode:1; + /* if enabled, then serial data starts one clock cycle after the + * of EAC.AC_FS for first audio slot */ + unsigned sync_delay_enable:1; +}; + +/* configuration structure for EAC codec port */ +struct eac_codec { + enum eac_mclk_src mclk_src; + + enum eac_codec_mode codec_mode; + union { + struct eac_i2s_conf i2s; + } codec_conf; + + int default_rate; /* audio sampling rate */ + + int (* set_power)(void *private_data, int dac, int adc); + int (* register_controls)(void *private_data, + struct snd_card *card); + const char *short_name; + + void *private_data; +}; + +/* structure for passing platform dependent data to the EAC driver */ +struct eac_platform_data { + int (* init)(struct device *eac_dev); + void (* cleanup)(struct device *eac_dev); + /* these callbacks are used to configure & control external MCLK + * source. NULL if not used */ + int (* enable_ext_clocks)(struct device *eac_dev); + void (* disable_ext_clocks)(struct device *eac_dev); +}; + +extern void omap_init_eac(struct eac_platform_data *pdata); + +extern int eac_register_codec(struct device *eac_dev, struct eac_codec *codec); +extern void eac_unregister_codec(struct device *eac_dev); + +extern int eac_set_mode(struct device *eac_dev, int play, int rec); + +#endif /* __ASM_ARM_ARCH_OMAP2_EAC_H */ diff --git a/include/asm-arm/arch-omap/menelaus.h b/include/asm-arm/arch-omap/menelaus.h index 82d276a..69ed7ee 100644 --- a/include/asm-arm/arch-omap/menelaus.h +++ b/include/asm-arm/arch-omap/menelaus.h @@ -7,6 +7,12 @@ #ifndef __ASM_ARCH_MENELAUS_H #define __ASM_ARCH_MENELAUS_H +struct device; + +struct menelaus_platform_data { + int (* late_init)(struct device *dev); +}; + extern int menelaus_register_mmc_callback(void (*callback)(void *data, u8 card_mask), void *data); extern void menelaus_unregister_mmc_callback(void); @@ -20,6 +26,19 @@ extern int menelaus_set_vaux(unsigned int mV); extern int menelaus_set_vdcdc(int dcdc, unsigned int mV); extern int menelaus_set_slot_sel(int enable); extern int menelaus_get_slot_pin_states(void); +extern int menelaus_set_vcore_sw(unsigned int mV); +extern int menelaus_set_vcore_hw(unsigned int roof_mV, unsigned int floor_mV); + +#define EN_VPLL_SLEEP (1 << 7) +#define EN_VMMC_SLEEP (1 << 6) +#define EN_VAUX_SLEEP (1 << 5) +#define EN_VIO_SLEEP (1 << 4) +#define EN_VMEM_SLEEP (1 << 3) +#define EN_DC3_SLEEP (1 << 2) +#define EN_DC2_SLEEP (1 << 1) +#define EN_VC_SLEEP (1 << 0) + +extern int menelaus_set_regulator_sleep(int enable, u32 val); #if defined(CONFIG_ARCH_OMAP24XX) && defined(CONFIG_MENELAUS) #define omap_has_menelaus() 1 @@ -28,4 +47,3 @@ extern int menelaus_get_slot_pin_states(void); #endif #endif - diff --git a/include/asm-arm/arch-omap/mmc.h b/include/asm-arm/arch-omap/mmc.h new file mode 100644 index 0000000..b70e37b --- /dev/null +++ b/include/asm-arm/arch-omap/mmc.h @@ -0,0 +1,66 @@ +/* + * MMC definitions for OMAP2 + * + * Copyright (C) 2006 Nokia Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __OMAP2_MMC_H +#define __OMAP2_MMC_H + +#include +#include +#include + +#define OMAP_MMC_MAX_SLOTS 2 + +struct omap_mmc_platform_data { + unsigned enabled:1; + /* number of slots on board */ + unsigned nr_slots:2; + /* nomux means "standard" muxing is wrong on this board, and that + * board-specific code handled it before common init logic. + */ + unsigned nomux:1; + /* 4 wire signaling is optional, and is only used for SD/SDIO and + * MMCv4 */ + unsigned wire4:1; + /* set if your board has components or wiring that limits the + * maximum frequency on the MMC bus */ + unsigned int max_freq; + + /* switch the bus to a new slot */ + int (* switch_slot)(struct device *dev, int slot); + /* initialize board-specific MMC functionality, can be NULL if + * not supported */ + int (* init)(struct device *dev); + void (* cleanup)(struct device *dev); + + struct omap_mmc_slot_data { + int (* set_bus_mode)(struct device *dev, int slot, int bus_mode); + int (* set_power)(struct device *dev, int slot, int power_on, int vdd); + int (* get_ro)(struct device *dev, int slot); + + /* return MMC cover switch state, can be NULL if not supported. + * + * possible return values: + * 0 - open + * 1 - closed + */ + int (* get_cover_state)(struct device *dev, int slot); + + const char *name; + u32 ocr_mask; + } slots[OMAP_MMC_MAX_SLOTS]; +}; + +extern void omap_set_mmc_info(int host, const struct omap_mmc_platform_data *info); + +/* called from board-specific card detection service routine */ +extern void omap_mmc_notify_card_detect(struct device *dev, int slot, int detected); +extern void omap_mmc_notify_cover_event(struct device *dev, int slot, int is_closed); + +#endif diff --git a/include/asm-arm/arch-omap/onenand.h b/include/asm-arm/arch-omap/onenand.h new file mode 100644 index 0000000..6c959d0ce --- /dev/null +++ b/include/asm-arm/arch-omap/onenand.h @@ -0,0 +1,21 @@ +/* + * include/asm-arm/arch-omap/onenand.h + * + * Copyright (C) 2006 Nokia Corporation + * Author: Juha Yrjola + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include + +struct omap_onenand_platform_data { + int cs; + int gpio_irq; + struct mtd_partition *parts; + int nr_parts; + int (*onenand_setup)(void __iomem *); + int dma_channel; +}; -- cgit v0.10.2 From 6017e29536f37045f0897c1afdc5500b21af8243 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 6 Dec 2006 17:13:55 -0800 Subject: ARM: OMAP: Enable DSP clocks for McBSP on omap310 This patch enables some clock on omap310. Signed-off-by: Marek Vasut Signed-off-by: Tony Lindgren diff --git a/arch/arm/mach-omap1/clock.h b/arch/arm/mach-omap1/clock.h index f7df002..4d6060c 100644 --- a/arch/arm/mach-omap1/clock.h +++ b/arch/arm/mach-omap1/clock.h @@ -282,7 +282,7 @@ static struct clk arminth_ck16xx = { static struct clk dsp_ck = { .name = "dsp_ck", .parent = &ck_dpll1, - .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | + .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | RATE_CKCTL, .enable_reg = (void __iomem *)ARM_CKCTL, .enable_bit = EN_DSPCK, @@ -295,7 +295,7 @@ static struct clk dsp_ck = { static struct clk dspmmu_ck = { .name = "dspmmu_ck", .parent = &ck_dpll1, - .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | + .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | RATE_CKCTL | ALWAYS_ENABLED, .rate_offset = CKCTL_DSPMMUDIV_OFFSET, .recalc = &omap1_ckctl_recalc, @@ -306,7 +306,7 @@ static struct clk dspmmu_ck = { static struct clk dspper_ck = { .name = "dspper_ck", .parent = &ck_dpll1, - .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | + .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | RATE_CKCTL | VIRTUAL_IO_ADDRESS, .enable_reg = (void __iomem *)DSP_IDLECT2, .enable_bit = EN_PERCK, @@ -320,7 +320,7 @@ static struct clk dspper_ck = { static struct clk dspxor_ck = { .name = "dspxor_ck", .parent = &ck_ref, - .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | + .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | VIRTUAL_IO_ADDRESS, .enable_reg = (void __iomem *)DSP_IDLECT2, .enable_bit = EN_XORPCK, @@ -332,7 +332,7 @@ static struct clk dspxor_ck = { static struct clk dsptim_ck = { .name = "dsptim_ck", .parent = &ck_ref, - .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | + .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | VIRTUAL_IO_ADDRESS, .enable_reg = (void __iomem *)DSP_IDLECT2, .enable_bit = EN_DSPTIMCK, @@ -374,7 +374,7 @@ static struct clk arminth_ck1510 = { static struct clk tipb_ck = { /* No-idle controlled by "tc_ck" */ - .name = "tibp_ck", + .name = "tipb_ck", .parent = &tc_ck.clk, .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | ALWAYS_ENABLED, @@ -733,7 +733,7 @@ remains active during MPU idle whenever this is enabled */ static struct clk i2c_fck = { .name = "i2c_fck", .id = 1, - .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | + .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | VIRTUAL_CLOCK | CLOCK_NO_IDLE_PARENT | ALWAYS_ENABLED, .parent = &armxor_ck.clk, -- cgit v0.10.2 From c72d8950baf737fe4da1982a8fad1f33fecdde2e Mon Sep 17 00:00:00 2001 From: David Brownell Date: Mon, 11 Dec 2006 14:14:11 -0800 Subject: ARM: OMAP: omap camera builds again; Mistral init and mux Support the camera connector on the OSK Mistral add-on board: - define muxing for both camera controllers - mux both of them for Mistral - teach ov9640 glue about mistral powerup/powerdown Signed-off-by: David Brownell Signed-off-by: Tony Lindgren diff --git a/arch/arm/mach-omap1/board-osk.c b/arch/arm/mach-omap1/board-osk.c index e713029..2bfa088 100644 --- a/arch/arm/mach-omap1/board-osk.c +++ b/arch/arm/mach-omap1/board-osk.c @@ -342,6 +342,38 @@ static void __init osk_mistral_init(void) * can't talk to the ads or even the i2c eeprom. */ + /* parallel camera interface */ + omap_cfg_reg(J15_1610_CAM_LCLK); + omap_cfg_reg(J18_1610_CAM_D7); + omap_cfg_reg(J19_1610_CAM_D6); + omap_cfg_reg(J14_1610_CAM_D5); + omap_cfg_reg(K18_1610_CAM_D4); + omap_cfg_reg(K19_1610_CAM_D3); + omap_cfg_reg(K15_1610_CAM_D2); + omap_cfg_reg(K14_1610_CAM_D1); + omap_cfg_reg(L19_1610_CAM_D0); + omap_cfg_reg(L18_1610_CAM_VS); + omap_cfg_reg(L15_1610_CAM_HS); + omap_cfg_reg(M19_1610_CAM_RSTZ); + omap_cfg_reg(Y15_1610_CAM_OUTCLK); + + /* serial camera interface */ + omap_cfg_reg(H19_1610_CAM_EXCLK); + omap_cfg_reg(W13_1610_CCP_CLKM); + omap_cfg_reg(Y12_1610_CCP_CLKP); + /* CCP_DATAM CONFLICTS WITH UART1.TX (and serial console) */ + // omap_cfg_reg(Y14_1610_CCP_DATAM); + omap_cfg_reg(W14_1610_CCP_DATAP); + + /* CAM_PWDN */ + if (omap_request_gpio(11) == 0) { + omap_cfg_reg(N20_1610_GPIO11); + omap_set_gpio_direction(11, 0 /* out */); + omap_set_gpio_dataout(11, 0 /* off */); + } else + pr_debug("OSK+Mistral: CAM_PWDN is awol\n"); + + // omap_cfg_reg(P19_1610_GPIO6); // BUSY omap_cfg_reg(P20_1610_GPIO4); // PENIRQ set_irq_type(OMAP_GPIO_IRQ(4), IRQT_FALLING); diff --git a/arch/arm/mach-omap1/mux.c b/arch/arm/mach-omap1/mux.c index 5432335..52c70e5 100644 --- a/arch/arm/mach-omap1/mux.c +++ b/arch/arm/mach-omap1/mux.c @@ -283,6 +283,30 @@ MUX_CFG("R11_1610_CF_IOIS16", B, 0, 3, 2, 16, 1, 2, 1, 1) MUX_CFG("V10_1610_CF_IREQ", A, 24, 3, 2, 14, 0, 2, 0, 1) MUX_CFG("W10_1610_CF_RESET", A, 18, 3, 2, 12, 1, 2, 1, 1) MUX_CFG("W11_1610_CF_CD1", 10, 15, 3, 3, 8, 1, 3, 1, 1) + +/* parallel camera */ +MUX_CFG("J15_1610_CAM_LCLK", 4, 24, 0, 0, 18, 1, 0, 0, 0) +MUX_CFG("J18_1610_CAM_D7", 4, 27, 0, 0, 19, 1, 0, 0, 0) +MUX_CFG("J19_1610_CAM_D6", 5, 0, 0, 0, 20, 1, 0, 0, 0) +MUX_CFG("J14_1610_CAM_D5", 5, 3, 0, 0, 21, 1, 0, 0, 0) +MUX_CFG("K18_1610_CAM_D4", 5, 6, 0, 0, 22, 1, 0, 0, 0) +MUX_CFG("K19_1610_CAM_D3", 5, 9, 0, 0, 23, 1, 0, 0, 0) +MUX_CFG("K15_1610_CAM_D2", 5, 12, 0, 0, 24, 1, 0, 0, 0) +MUX_CFG("K14_1610_CAM_D1", 5, 15, 0, 0, 25, 1, 0, 0, 0) +MUX_CFG("L19_1610_CAM_D0", 5, 18, 0, 0, 26, 1, 0, 0, 0) +MUX_CFG("L18_1610_CAM_VS", 5, 21, 0, 0, 27, 1, 0, 0, 0) +MUX_CFG("L15_1610_CAM_HS", 5, 24, 0, 0, 28, 1, 0, 0, 0) +MUX_CFG("M19_1610_CAM_RSTZ", 5, 27, 0, 0, 29, 0, 0, 0, 0) +MUX_CFG("Y15_1610_CAM_OUTCLK", A, 0, 6, 2, 6, 0, 2, 0, 0) + +/* serial camera */ +MUX_CFG("H19_1610_CAM_EXCLK", 4, 21, 0, 0, 17, 0, 0, 0, 0) + /* REVISIT 5912 spec sez CCP_* can't pullup or pulldown ... ? */ +MUX_CFG("Y12_1610_CCP_CLKP", 8, 18, 6, 1, 24, 1, 1, 0, 0) +MUX_CFG("W13_1610_CCP_CLKM", 9, 0, 6, 1, 28, 1, 1, 0, 0) +MUX_CFG("W14_1610_CCP_DATAP", 9, 24, 6, 2, 4, 1, 2, 0, 0) +MUX_CFG("Y14_1610_CCP_DATAM", 9, 21, 6, 2, 3, 1, 2, 0, 0) + }; #endif /* CONFIG_ARCH_OMAP15XX || CONFIG_ARCH_OMAP16XX */ diff --git a/include/asm-arm/arch-omap/mux.h b/include/asm-arm/arch-omap/mux.h index f1ec2ed..b8fff50 100644 --- a/include/asm-arm/arch-omap/mux.h +++ b/include/asm-arm/arch-omap/mux.h @@ -406,6 +406,29 @@ enum omap1xxx_index { V10_1610_CF_IREQ, W10_1610_CF_RESET, W11_1610_CF_CD1, + + /* parallel camera */ + J15_1610_CAM_LCLK, + J18_1610_CAM_D7, + J19_1610_CAM_D6, + J14_1610_CAM_D5, + K18_1610_CAM_D4, + K19_1610_CAM_D3, + K15_1610_CAM_D2, + K14_1610_CAM_D1, + L19_1610_CAM_D0, + L18_1610_CAM_VS, + L15_1610_CAM_HS, + M19_1610_CAM_RSTZ, + Y15_1610_CAM_OUTCLK, + + /* serial camera */ + H19_1610_CAM_EXCLK, + Y12_1610_CCP_CLKP, + W13_1610_CCP_CLKM, + W14_1610_CCP_DATAP, + Y14_1610_CCP_DATAM, + }; enum omap24xx_index { -- cgit v0.10.2 From df2c2e70f0cb3fa2586beffc41fcd7e093453bc5 Mon Sep 17 00:00:00 2001 From: Imre Deak Date: Mon, 5 Mar 2007 17:22:58 +0200 Subject: ARM: OMAP: add SoSSI clock This is needed, so that disabling the SoSSI clock during idle can be prevented. Signed-off-by: Imre Deak Signed-off-by: Tony Lindgren diff --git a/arch/arm/mach-omap1/clock.c b/arch/arm/mach-omap1/clock.c index f625f6d..5d9faa6 100644 --- a/arch/arm/mach-omap1/clock.c +++ b/arch/arm/mach-omap1/clock.c @@ -49,6 +49,15 @@ static void omap1_uart_recalc(struct clk * clk) clk->rate = 12000000; } +static void omap1_sossi_recalc(struct clk *clk) +{ + u32 div = omap_readl(MOD_CONF_CTRL_1); + + div = (div >> 17) & 0x7; + div++; + clk->rate = clk->parent->rate / div; +} + static int omap1_clk_enable_dsp_domain(struct clk *clk) { int retval; @@ -396,6 +405,31 @@ static int omap1_set_ext_clk_rate(struct clk * clk, unsigned long rate) return 0; } +static int omap1_set_sossi_rate(struct clk *clk, unsigned long rate) +{ + u32 l; + int div; + unsigned long p_rate; + + p_rate = clk->parent->rate; + /* Round towards slower frequency */ + div = (p_rate + rate - 1) / rate; + div--; + if (div < 0 || div > 7) + return -EINVAL; + + l = omap_readl(MOD_CONF_CTRL_1); + l &= ~(7 << 17); + l |= div << 17; + omap_writel(l, MOD_CONF_CTRL_1); + + clk->rate = p_rate / (div + 1); + if (unlikely(clk->flags & RATE_PROPAGATES)) + propagate_rate(clk); + + return 0; +} + static long omap1_round_ext_clk_rate(struct clk * clk, unsigned long rate) { return 96000000 / calc_ext_dsor(rate); diff --git a/arch/arm/mach-omap1/clock.h b/arch/arm/mach-omap1/clock.h index 4d6060c..6eadf72 100644 --- a/arch/arm/mach-omap1/clock.h +++ b/arch/arm/mach-omap1/clock.h @@ -17,6 +17,8 @@ static int omap1_clk_enable_generic(struct clk * clk); static void omap1_clk_disable_generic(struct clk * clk); static void omap1_ckctl_recalc(struct clk * clk); static void omap1_watchdog_recalc(struct clk * clk); +static int omap1_set_sossi_rate(struct clk *clk, unsigned long rate); +static void omap1_sossi_recalc(struct clk *clk); static void omap1_ckctl_recalc_dsp_domain(struct clk * clk); static int omap1_clk_enable_dsp_domain(struct clk * clk); static int omap1_clk_set_rate_dsp_domain(struct clk * clk, unsigned long rate); @@ -168,9 +170,10 @@ static struct clk ck_dpll1 = { static struct arm_idlect1_clk ck_dpll1out = { .clk = { - .name = "ck_dpll1out", + .name = "ck_dpll1out", .parent = &ck_dpll1, - .flags = CLOCK_IN_OMAP16XX | CLOCK_IDLE_CONTROL, + .flags = CLOCK_IN_OMAP16XX | CLOCK_IDLE_CONTROL | + ENABLE_REG_32BIT | RATE_PROPAGATES, .enable_reg = (void __iomem *)ARM_IDLECT2, .enable_bit = EN_CKOUT_ARM, .recalc = &followparent_recalc, @@ -180,6 +183,19 @@ static struct arm_idlect1_clk ck_dpll1out = { .idlect_shift = 12, }; +static struct clk sossi_ck = { + .name = "ck_sossi", + .parent = &ck_dpll1out.clk, + .flags = CLOCK_IN_OMAP16XX | CLOCK_NO_IDLE_PARENT | + ENABLE_REG_32BIT, + .enable_reg = (void __iomem *)MOD_CONF_CTRL_1, + .enable_bit = 16, + .recalc = &omap1_sossi_recalc, + .set_rate = &omap1_set_sossi_rate, + .enable = &omap1_clk_enable_generic, + .disable = &omap1_clk_disable_generic, +}; + static struct clk arm_ck = { .name = "arm_ck", .parent = &ck_dpll1, @@ -760,6 +776,7 @@ static struct clk * onchip_clks[] = { &ck_dpll1, /* CK_GEN1 clocks */ &ck_dpll1out.clk, + &sossi_ck, &arm_ck, &armper_ck.clk, &arm_gpio_ck, -- cgit v0.10.2 From 6ea59bb3083dea3b48003ea49de12a3e3c868b05 Mon Sep 17 00:00:00 2001 From: Imre Deak Date: Mon, 5 Mar 2007 17:34:05 +0200 Subject: ARM: OMAP: add SoSSI clock (remove manual checking of SoSSI state from idle) The SoSSI driver should already take care of this by enabling / disabling its clock when necessary, so this legacy callout from the PM idle code is not needed any more. Signed-off-by: Imre Deak Signed-off-by: Tony Lindgren diff --git a/arch/arm/mach-omap1/pm.c b/arch/arm/mach-omap1/pm.c index 2e68be6..089b820 100644 --- a/arch/arm/mach-omap1/pm.c +++ b/arch/arm/mach-omap1/pm.c @@ -153,11 +153,8 @@ void omap_pm_idle(void) use_idlect1 = omap_dm_timer_modify_idlect_mask(use_idlect1); #endif - if (omap_dma_running()) { + if (omap_dma_running()) use_idlect1 &= ~(1 << 6); - if (omap_lcd_dma_ext_running()) - use_idlect1 &= ~(1 << 12); - } /* We should be able to remove the do_sleep variable and multiple * tests above as soon as drivers, timer and DMA code have been fixed. diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c index 88d5b6d..05a3849 100644 --- a/arch/arm/plat-omap/dma.c +++ b/arch/arm/plat-omap/dma.c @@ -1347,11 +1347,6 @@ void omap_stop_lcd_dma(void) omap_writew(w, OMAP1610_DMA_LCD_CTRL); } -int omap_lcd_dma_ext_running(void) -{ - return lcd_dma.ext_ctrl && lcd_dma.active; -} - /*----------------------------------------------------------------------------*/ static int __init omap_init_dma(void) @@ -1493,7 +1488,6 @@ EXPORT_SYMBOL(omap_free_lcd_dma); EXPORT_SYMBOL(omap_enable_lcd_dma); EXPORT_SYMBOL(omap_setup_lcd_dma); EXPORT_SYMBOL(omap_stop_lcd_dma); -EXPORT_SYMBOL(omap_lcd_dma_ext_running); EXPORT_SYMBOL(omap_set_lcd_dma_b1); EXPORT_SYMBOL(omap_set_lcd_dma_single_transfer); EXPORT_SYMBOL(omap_set_lcd_dma_ext_controller); diff --git a/include/asm-arm/arch-omap/dma.h b/include/asm-arm/arch-omap/dma.h index f777419..f33b467 100644 --- a/include/asm-arm/arch-omap/dma.h +++ b/include/asm-arm/arch-omap/dma.h @@ -417,7 +417,6 @@ extern void omap_free_lcd_dma(void); extern void omap_setup_lcd_dma(void); extern void omap_enable_lcd_dma(void); extern void omap_stop_lcd_dma(void); -extern int omap_lcd_dma_ext_running(void); extern void omap_set_lcd_dma_ext_controller(int external); extern void omap_set_lcd_dma_single_transfer(int single); extern void omap_set_lcd_dma_b1(unsigned long addr, u16 fb_xres, u16 fb_yres, -- cgit v0.10.2 From c3695015087e21ff30606bf7fc661de1582af81b Mon Sep 17 00:00:00 2001 From: Andrzej Zaborowski Date: Wed, 6 Dec 2006 17:13:51 -0800 Subject: ARM: OMAP: Palm Tungsten E board update General update of the board file for Palm Tungsten E. Registers the platform devices contained in the PDA (ROM chip, keypad, infra-red) and updates the configuration for USB and MMC, whose config values were previously guessed in most cases due to lack of documentation (and now are confirmed by a number of users). Macros for GPIO pins are moved to a file in include/asm-arm/arch-omap. Signed-off-by: Andrzej Zaborowski Signed-off-by: Tony Lindgren diff --git a/arch/arm/mach-omap1/Kconfig b/arch/arm/mach-omap1/Kconfig index f6ecdd3..84a3b08 100644 --- a/arch/arm/mach-omap1/Kconfig +++ b/arch/arm/mach-omap1/Kconfig @@ -84,11 +84,10 @@ config MACH_OMAP_PALMTE bool "Palm Tungsten E" depends on ARCH_OMAP1 && ARCH_OMAP15XX help - Support for the Palm Tungsten E PDA. Currently only the LCD panel - is supported. To boot the kernel, you'll need a PalmOS compatible - bootloader; check out http://palmtelinux.sourceforge.net for more - information. - Say Y here if you have such a PDA, say NO otherwise. + Support for the Palm Tungsten E PDA. To boot the kernel, you'll + need a PalmOS compatible bootloader; check out + http://palmtelinux.sourceforge.net/ for more information. + Say Y here if you have this PDA model, say N otherwise. config MACH_NOKIA770 bool "Nokia 770" diff --git a/arch/arm/mach-omap1/board-palmte.c b/arch/arm/mach-omap1/board-palmte.c index 0158241..2f9d00a 100644 --- a/arch/arm/mach-omap1/board-palmte.c +++ b/arch/arm/mach-omap1/board-palmte.c @@ -17,49 +17,189 @@ #include #include +#include #include -#include -#include +#include +#include +#include +#include +#include +#include #include #include #include #include +#include #include #include #include +#include +#include #include +#include +#include #include +#include +#include -static void __init omap_generic_init_irq(void) +static void __init omap_palmte_init_irq(void) { omap1_init_common_hw(); omap_init_irq(); + omap_gpio_init(); } +static int palmte_keymap[] = { + KEY(0, 0, KEY_F1), + KEY(0, 1, KEY_F2), + KEY(0, 2, KEY_F3), + KEY(0, 3, KEY_F4), + KEY(0, 4, KEY_POWER), + KEY(1, 0, KEY_LEFT), + KEY(1, 1, KEY_DOWN), + KEY(1, 2, KEY_UP), + KEY(1, 3, KEY_RIGHT), + KEY(1, 4, KEY_CENTER), + 0, +}; + +static struct omap_kp_platform_data palmte_kp_data = { + .rows = 8, + .cols = 8, + .keymap = palmte_keymap, + .rep = 1, + .delay = 12, +}; + +static struct resource palmte_kp_resources[] = { + [0] = { + .start = INT_KEYBOARD, + .end = INT_KEYBOARD, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device palmte_kp_device = { + .name = "omap-keypad", + .id = -1, + .dev = { + .platform_data = &palmte_kp_data, + }, + .num_resources = ARRAY_SIZE(palmte_kp_resources), + .resource = palmte_kp_resources, +}; + +static struct mtd_partition palmte_rom_partitions[] = { + /* PalmOS "Small ROM", contains the bootloader and the debugger */ + { + .name = "smallrom", + .offset = 0, + .size = 0xa000, + .mask_flags = MTD_WRITEABLE, + }, + /* PalmOS "Big ROM", a filesystem with all the OS code and data */ + { + .name = "bigrom", + .offset = SZ_128K, + /* + * 0x5f0000 bytes big in the multi-language ("EFIGS") version, + * 0x7b0000 bytes in the English-only ("enUS") version. + */ + .size = 0x7b0000, + .mask_flags = MTD_WRITEABLE, + }, +}; + +static struct flash_platform_data palmte_rom_data = { + .map_name = "map_rom", + .width = 2, + .parts = palmte_rom_partitions, + .nr_parts = ARRAY_SIZE(palmte_rom_partitions), +}; + +static struct resource palmte_rom_resource = { + .start = OMAP_CS0_PHYS, + .end = OMAP_CS0_PHYS + SZ_8M - 1, + .flags = IORESOURCE_MEM, +}; + +static struct platform_device palmte_rom_device = { + .name = "omapflash", + .id = -1, + .dev = { + .platform_data = &palmte_rom_data, + }, + .num_resources = 1, + .resource = &palmte_rom_resource, +}; + static struct platform_device palmte_lcd_device = { .name = "lcd_palmte", .id = -1, }; +static struct omap_backlight_config palmte_backlight_config = { + .default_intensity = 0xa0, +}; + +static struct platform_device palmte_backlight_device = { + .name = "omap-bl", + .id = -1, + .dev = { + .platform_data = &palmte_backlight_config, + }, +}; + +static struct omap_irda_config palmte_irda_config = { + .transceiver_cap = IR_SIRMODE, + .rx_channel = OMAP_DMA_UART3_RX, + .tx_channel = OMAP_DMA_UART3_TX, + .dest_start = UART3_THR, + .src_start = UART3_RHR, + .tx_trigger = 0, + .rx_trigger = 0, +}; + +static struct resource palmte_irda_resources[] = { + [0] = { + .start = INT_UART3, + .end = INT_UART3, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device palmte_irda_device = { + .name = "omapirda", + .id = -1, + .dev = { + .platform_data = &palmte_irda_config, + }, + .num_resources = ARRAY_SIZE(palmte_irda_resources), + .resource = palmte_irda_resources, +}; + static struct platform_device *devices[] __initdata = { + &palmte_rom_device, + &palmte_kp_device, &palmte_lcd_device, + &palmte_backlight_device, + &palmte_irda_device, }; static struct omap_usb_config palmte_usb_config __initdata = { - .register_dev = 1, + .register_dev = 1, /* Mini-B only receptacle */ .hmc_mode = 0, - .pins[0] = 3, + .pins[0] = 2, }; static struct omap_mmc_config palmte_mmc_config __initdata = { - .mmc [0] = { + .mmc[0] = { .enabled = 1, - .wire4 = 1, - .wp_pin = OMAP_MPUIO(3), - .power_pin = -1, - .switch_pin = -1, + .wp_pin = PALMTE_MMC_WP_GPIO, + .power_pin = PALMTE_MMC_POWER_GPIO, + .switch_pin = PALMTE_MMC_SWITCH_GPIO, }, }; @@ -67,21 +207,222 @@ static struct omap_lcd_config palmte_lcd_config __initdata = { .ctrl_name = "internal", }; +static struct omap_uart_config palmte_uart_config __initdata = { + .enabled_uarts = (1 << 0) | (1 << 1) | (0 << 2), +}; + +static struct omap_mcbsp_reg_cfg palmte_mcbsp1_regs = { + .spcr2 = FRST | GRST | XRST | XINTM(3), + .xcr2 = XDATDLY(1) | XFIG, + .xcr1 = XWDLEN1(OMAP_MCBSP_WORD_32), + .pcr0 = SCLKME | FSXP | CLKXP, +}; + +static struct omap_alsa_codec_config palmte_alsa_config = { + .name = "TSC2102 audio", + .mcbsp_regs_alsa = &palmte_mcbsp1_regs, + .codec_configure_dev = NULL, /* tsc2102_configure, */ + .codec_set_samplerate = NULL, /* tsc2102_set_samplerate, */ + .codec_clock_setup = NULL, /* tsc2102_clock_setup, */ + .codec_clock_on = NULL, /* tsc2102_clock_on, */ + .codec_clock_off = NULL, /* tsc2102_clock_off, */ + .get_default_samplerate = NULL, /* tsc2102_get_default_samplerate, */ +}; + +#ifdef CONFIG_APM +/* + * Values measured in 10 minute intervals averaged over 10 samples. + * May differ slightly from device to device but should be accurate + * enough to give basic idea of battery life left and trigger + * potential alerts. + */ +static const int palmte_battery_sample[] = { + 2194, 2157, 2138, 2120, + 2104, 2089, 2075, 2061, + 2048, 2038, 2026, 2016, + 2008, 1998, 1989, 1980, + 1970, 1958, 1945, 1928, + 1910, 1888, 1860, 1827, + 1791, 1751, 1709, 1656, +}; + +#define INTERVAL 10 +#define BATTERY_HIGH_TRESHOLD 66 +#define BATTERY_LOW_TRESHOLD 33 + +static void palmte_get_power_status(struct apm_power_info *info, int *battery) +{ + int charging, batt, hi, lo, mid; + + charging = !omap_get_gpio_datain(PALMTE_DC_GPIO); + batt = battery[0]; + if (charging) + batt -= 60; + + hi = ARRAY_SIZE(palmte_battery_sample); + lo = 0; + + info->battery_flag = 0; + info->units = APM_UNITS_MINS; + + if (batt > palmte_battery_sample[lo]) { + info->battery_life = 100; + info->time = INTERVAL * ARRAY_SIZE(palmte_battery_sample); + } else if (batt <= palmte_battery_sample[hi - 1]) { + info->battery_life = 0; + info->time = 0; + } else { + while (hi > lo + 1) { + mid = (hi + lo) >> 2; + if (batt <= palmte_battery_sample[mid]) + lo = mid; + else + hi = mid; + } + + mid = palmte_battery_sample[lo] - palmte_battery_sample[hi]; + hi = palmte_battery_sample[lo] - batt; + info->battery_life = 100 - (100 * lo + 100 * hi / mid) / + ARRAY_SIZE(palmte_battery_sample); + info->time = INTERVAL * (ARRAY_SIZE(palmte_battery_sample) - + lo) - INTERVAL * hi / mid; + } + + if (charging) { + info->ac_line_status = APM_AC_ONLINE; + info->battery_status = APM_BATTERY_STATUS_CHARGING; + info->battery_flag |= APM_BATTERY_FLAG_CHARGING; + } else { + info->ac_line_status = APM_AC_OFFLINE; + if (info->battery_life > BATTERY_HIGH_TRESHOLD) + info->battery_status = APM_BATTERY_STATUS_HIGH; + else if (info->battery_life > BATTERY_LOW_TRESHOLD) + info->battery_status = APM_BATTERY_STATUS_LOW; + else + info->battery_status = APM_BATTERY_STATUS_CRITICAL; + } + + if (info->battery_life > BATTERY_HIGH_TRESHOLD) + info->battery_flag |= APM_BATTERY_FLAG_HIGH; + else if (info->battery_life > BATTERY_LOW_TRESHOLD) + info->battery_flag |= APM_BATTERY_FLAG_LOW; + else + info->battery_flag |= APM_BATTERY_FLAG_CRITICAL; +} +#else +#define palmte_get_power_status NULL +#endif + +static struct tsc2102_config palmte_tsc2102_config = { + .use_internal = 0, + .monitor = TSC_BAT1 | TSC_AUX | TSC_TEMP, + .temp_at25c = { 2200, 2615 }, + .apm_report = palmte_get_power_status, + .alsa_config = &palmte_alsa_config, +}; + static struct omap_board_config_kernel palmte_config[] = { - { OMAP_TAG_USB, &palmte_usb_config }, - { OMAP_TAG_MMC, &palmte_mmc_config }, - { OMAP_TAG_LCD, &palmte_lcd_config }, + { OMAP_TAG_USB, &palmte_usb_config }, + { OMAP_TAG_MMC, &palmte_mmc_config }, + { OMAP_TAG_LCD, &palmte_lcd_config }, + { OMAP_TAG_UART, &palmte_uart_config }, }; -static void __init omap_generic_init(void) +static struct spi_board_info palmte_spi_info[] __initdata = { + { + .modalias = "tsc2102", + .bus_num = 2, /* uWire (officially) */ + .chip_select = 0, /* As opposed to 3 */ + .irq = OMAP_GPIO_IRQ(PALMTE_PINTDAV_GPIO), + .platform_data = &palmte_tsc2102_config, + .max_speed_hz = 8000000, + }, +}; + +/* Periodically check for changes on important input pins */ +struct timer_list palmte_pin_timer; +int prev_power, prev_headphones; + +static void palmte_pin_handler(unsigned long data) { + int power, headphones; + + power = !omap_get_gpio_datain(PALMTE_DC_GPIO); + headphones = omap_get_gpio_datain(PALMTE_HEADPHONES_GPIO); + + if (power && !prev_power) + printk(KERN_INFO "PM: cable connected\n"); + else if (!power && prev_power) + printk(KERN_INFO "PM: cable disconnected\n"); + + if (headphones && !prev_headphones) { + /* Headphones connected, disable speaker */ + omap_set_gpio_dataout(PALMTE_SPEAKER_GPIO, 0); + printk(KERN_INFO "PM: speaker off\n"); + } else if (!headphones && prev_headphones) { + /* Headphones unplugged, re-enable speaker */ + omap_set_gpio_dataout(PALMTE_SPEAKER_GPIO, 1); + printk(KERN_INFO "PM: speaker on\n"); + } + + prev_power = power; + prev_headphones = headphones; + mod_timer(&palmte_pin_timer, jiffies + msecs_to_jiffies(500)); +} + +static void __init palmte_gpio_setup(void) +{ + /* Set TSC2102 PINTDAV pin as input */ + if (omap_request_gpio(PALMTE_PINTDAV_GPIO)) { + printk(KERN_ERR "Could not reserve PINTDAV GPIO!\n"); + return; + } + omap_set_gpio_direction(PALMTE_PINTDAV_GPIO, 1); + + /* Monitor cable-connected signals */ + if (omap_request_gpio(PALMTE_DC_GPIO) || + omap_request_gpio(PALMTE_USB_OR_DC_GPIO) || + omap_request_gpio(PALMTE_USBDETECT_GPIO)) { + printk(KERN_ERR "Could not reserve cable signal GPIO!\n"); + return; + } + omap_set_gpio_direction(PALMTE_DC_GPIO, 1); + omap_set_gpio_direction(PALMTE_USB_OR_DC_GPIO, 1); + omap_set_gpio_direction(PALMTE_USBDETECT_GPIO, 1); + + /* Set speaker-enable pin as output */ + if (omap_request_gpio(PALMTE_SPEAKER_GPIO)) { + printk(KERN_ERR "Could not reserve speaker GPIO!\n"); + return; + } + omap_set_gpio_direction(PALMTE_SPEAKER_GPIO, 0); + + /* Monitor the headphones-connected signal */ + if (omap_request_gpio(PALMTE_HEADPHONES_GPIO)) { + printk(KERN_ERR "Could not reserve headphones signal GPIO!\n"); + return; + } + omap_set_gpio_direction(PALMTE_HEADPHONES_GPIO, 1); + + prev_power = omap_get_gpio_datain(PALMTE_DC_GPIO); + prev_headphones = !omap_get_gpio_datain(PALMTE_HEADPHONES_GPIO); + setup_timer(&palmte_pin_timer, palmte_pin_handler, 0); + palmte_pin_handler(0); +} + +static void __init omap_palmte_init(void) { omap_board_config = palmte_config; omap_board_config_size = ARRAY_SIZE(palmte_config); platform_add_devices(devices, ARRAY_SIZE(devices)); + + spi_register_board_info(palmte_spi_info, ARRAY_SIZE(palmte_spi_info)); + + omap_serial_init(); + palmte_gpio_setup(); } -static void __init omap_generic_map_io(void) +static void __init omap_palmte_map_io(void) { omap1_map_common_io(); } @@ -90,8 +431,8 @@ MACHINE_START(OMAP_PALMTE, "OMAP310 based Palm Tungsten E") .phys_io = 0xfff00000, .io_pg_offst = ((0xfef00000) >> 18) & 0xfffc, .boot_params = 0x10000100, - .map_io = omap_generic_map_io, - .init_irq = omap_generic_init_irq, - .init_machine = omap_generic_init, + .map_io = omap_palmte_map_io, + .init_irq = omap_palmte_init_irq, + .init_machine = omap_palmte_init, .timer = &omap_timer, MACHINE_END diff --git a/include/asm-arm/arch-omap/board-palmte.h b/include/asm-arm/arch-omap/board-palmte.h new file mode 100644 index 0000000..cd22035 --- /dev/null +++ b/include/asm-arm/arch-omap/board-palmte.h @@ -0,0 +1,34 @@ +/* + * linux/include/asm-arm/arch-omap/board-palmte.h + * + * Hardware definitions for the Palm Tungsten E device. + * + * Maintainters : http://palmtelinux.sf.net + * palmtelinux-developpers@lists.sf.net + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __OMAP_BOARD_PALMTE_H +#define __OMAP_BOARD_PALMTE_H + +#include + +#define PALMTE_USBDETECT_GPIO 0 +#define PALMTE_USB_OR_DC_GPIO 1 +#define PALMTE_TSC_GPIO 4 +#define PALMTE_PINTDAV_GPIO 6 +#define PALMTE_MMC_WP_GPIO 8 +#define PALMTE_MMC_POWER_GPIO 9 +#define PALMTE_HDQ_GPIO 11 +#define PALMTE_HEADPHONES_GPIO 14 +#define PALMTE_SPEAKER_GPIO 15 +#define PALMTE_DC_GPIO OMAP_MPUIO(2) +#define PALMTE_MMC_SWITCH_GPIO OMAP_MPUIO(4) +#define PALMTE_MMC1_GPIO OMAP_MPUIO(6) +#define PALMTE_MMC2_GPIO OMAP_MPUIO(7) +#define PALMTE_MMC3_GPIO OMAP_MPUIO(11) + +#endif /* __OMAP_BOARD_PALMTE_H */ diff --git a/include/asm-arm/arch-omap/hardware.h b/include/asm-arm/arch-omap/hardware.h index e225f4f..539f16d 100644 --- a/include/asm-arm/arch-omap/hardware.h +++ b/include/asm-arm/arch-omap/hardware.h @@ -330,6 +330,10 @@ #include "board-voiceblue.h" #endif +#ifdef CONFIG_MACH_OMAP_PALMTE +#include "board-palmte.h" +#endif + #endif /* !__ASSEMBLER__ */ #endif /* __ASM_ARCH_OMAP_HARDWARE_H */ -- cgit v0.10.2 From 325d50b660519398dc875b4cffedd0fc2cc4f425 Mon Sep 17 00:00:00 2001 From: Jonathan McDowell Date: Wed, 6 Dec 2006 17:13:52 -0800 Subject: ARM: OMAP: Add support for Amstrad Delta keypad This adds support for the keypad on the top of the Amstrad Delta. It's just a standard omap-keypad so all we need to do is add the keypad layout and platform data to the board definition file. Signed-off-by: Jonathan McDowell Signed-off-by: Tony Lindgren diff --git a/arch/arm/mach-omap1/board-ams-delta.c b/arch/arm/mach-omap1/board-ams-delta.c index 8437d06..fa2da74 100644 --- a/arch/arm/mach-omap1/board-ams-delta.c +++ b/arch/arm/mach-omap1/board-ams-delta.c @@ -14,6 +14,7 @@ #include #include +#include #include #include @@ -23,6 +24,7 @@ #include #include +#include #include #include #include @@ -31,6 +33,86 @@ static u8 ams_delta_latch1_reg; static u16 ams_delta_latch2_reg; +static int ams_delta_keymap[] = { + KEY(0, 0, KEY_F1), /* Advert */ + + KEY(3, 0, KEY_COFFEE), /* Games */ + KEY(2, 0, KEY_QUESTION), /* Directory */ + KEY(3, 2, KEY_CONNECT), /* Internet */ + KEY(2, 1, KEY_SHOP), /* Services */ + KEY(1, 1, KEY_PHONE), /* VoiceMail */ + + KEY(1, 0, KEY_DELETE), /* Delete */ + KEY(2, 2, KEY_PLAY), /* Play */ + KEY(0, 1, KEY_PAGEUP), /* Up */ + KEY(3, 1, KEY_PAGEDOWN), /* Down */ + KEY(0, 2, KEY_EMAIL), /* ReadEmail */ + KEY(1, 2, KEY_STOP), /* Stop */ + + /* Numeric keypad portion */ + KEY(7, 0, KEY_KP1), + KEY(6, 0, KEY_KP2), + KEY(5, 0, KEY_KP3), + KEY(7, 1, KEY_KP4), + KEY(6, 1, KEY_KP5), + KEY(5, 1, KEY_KP6), + KEY(7, 2, KEY_KP7), + KEY(6, 2, KEY_KP8), + KEY(5, 2, KEY_KP9), + KEY(6, 3, KEY_KP0), + KEY(7, 3, KEY_KPASTERISK), + KEY(5, 3, KEY_KPDOT), /* # key */ + KEY(2, 7, KEY_NUMLOCK), /* Mute */ + KEY(1, 7, KEY_KPMINUS), /* Recall */ + KEY(1, 6, KEY_KPPLUS), /* Redial */ + KEY(6, 7, KEY_KPSLASH), /* Handsfree */ + KEY(0, 6, KEY_ENTER), /* Video */ + + KEY(4, 7, KEY_CAMERA), /* Photo */ + + KEY(4, 0, KEY_F2), /* Home */ + KEY(4, 1, KEY_F3), /* Office */ + KEY(4, 2, KEY_F4), /* Mobile */ + KEY(7, 7, KEY_F5), /* SMS */ + KEY(5, 7, KEY_F6), /* Email */ + + /* QWERTY portion of keypad */ + KEY(4, 3, KEY_Q), + KEY(3, 3, KEY_W), + KEY(2, 3, KEY_E), + KEY(1, 3, KEY_R), + KEY(0, 3, KEY_T), + KEY(7, 4, KEY_Y), + KEY(6, 4, KEY_U), + KEY(5, 4, KEY_I), + KEY(4, 4, KEY_O), + KEY(3, 4, KEY_P), + + KEY(2, 4, KEY_A), + KEY(1, 4, KEY_S), + KEY(0, 4, KEY_D), + KEY(7, 5, KEY_F), + KEY(6, 5, KEY_G), + KEY(5, 5, KEY_H), + KEY(4, 5, KEY_J), + KEY(3, 5, KEY_K), + KEY(2, 5, KEY_L), + + KEY(1, 5, KEY_Z), + KEY(0, 5, KEY_X), + KEY(7, 6, KEY_C), + KEY(6, 6, KEY_V), + KEY(5, 6, KEY_B), + KEY(4, 6, KEY_N), + KEY(3, 6, KEY_M), + KEY(2, 6, KEY_SPACE), + + KEY(0, 7, KEY_LEFTSHIFT), /* Vol up */ + KEY(3, 7, KEY_LEFTCTRL), /* Vol down */ + + 0 +}; + void ams_delta_latch1_write(u8 mask, u8 value) { ams_delta_latch1_reg &= ~mask; @@ -91,12 +173,39 @@ static struct omap_board_config_kernel ams_delta_config[] = { { OMAP_TAG_USB, &ams_delta_usb_config }, }; +static struct resource ams_delta_kp_resources[] = { + [0] = { + .start = INT_KEYBOARD, + .end = INT_KEYBOARD, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct omap_kp_platform_data ams_delta_kp_data = { + .rows = 8, + .cols = 8, + .keymap = ams_delta_keymap, + .keymapsize = ARRAY_SIZE(ams_delta_keymap), + .delay = 9, +}; + +static struct platform_device ams_delta_kp_device = { + .name = "omap-keypad", + .id = -1, + .dev = { + .platform_data = &ams_delta_kp_data, + }, + .num_resources = ARRAY_SIZE(ams_delta_kp_resources), + .resource = ams_delta_kp_resources, +}; + static struct platform_device ams_delta_led_device = { .name = "ams-delta-led", .id = -1 }; static struct platform_device *ams_delta_devices[] __initdata = { + &ams_delta_kp_device, &ams_delta_led_device, }; -- cgit v0.10.2 From ec70e8afb9b9818690bc440bc730c08bad4746a9 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 6 Dec 2006 17:13:57 -0800 Subject: ARM: OMAP: PalmZ71 support Palmz71 specific things - board file. Signed-off-by: Marek Vasut Signed-off-by: Tony Lindgren diff --git a/arch/arm/mach-omap1/Kconfig b/arch/arm/mach-omap1/Kconfig index 84a3b08..1085e12c 100644 --- a/arch/arm/mach-omap1/Kconfig +++ b/arch/arm/mach-omap1/Kconfig @@ -89,6 +89,15 @@ config MACH_OMAP_PALMTE http://palmtelinux.sourceforge.net/ for more information. Say Y here if you have this PDA model, say N otherwise. +config MACH_OMAP_PALMZ71 + bool "Palm Zire71" + depends on ARCH_OMAP1 && ARCH_OMAP15XX + help + Support for the Palm Zire71 PDA. To boot the kernel, + you'll need a PalmOS compatible bootloader; check out + http://hackndev.com/palm/z71 for more informations. + Say Y here if you have such a PDA, say N otherwise. + config MACH_NOKIA770 bool "Nokia 770" depends on ARCH_OMAP1 && ARCH_OMAP16XX diff --git a/arch/arm/mach-omap1/Makefile b/arch/arm/mach-omap1/Makefile index a8b9a00..76cbc68 100644 --- a/arch/arm/mach-omap1/Makefile +++ b/arch/arm/mach-omap1/Makefile @@ -22,6 +22,7 @@ obj-$(CONFIG_MACH_OMAP_OSK) += board-osk.o obj-$(CONFIG_MACH_OMAP_H3) += board-h3.o obj-$(CONFIG_MACH_VOICEBLUE) += board-voiceblue.o obj-$(CONFIG_MACH_OMAP_PALMTE) += board-palmte.o +obj-$(CONFIG_MACH_OMAP_PALMZ71) += board-palmz71.o obj-$(CONFIG_MACH_NOKIA770) += board-nokia770.o obj-$(CONFIG_MACH_AMS_DELTA) += board-ams-delta.o diff --git a/arch/arm/mach-omap1/board-palmz71.c b/arch/arm/mach-omap1/board-palmz71.c new file mode 100644 index 0000000..c275d51 --- /dev/null +++ b/arch/arm/mach-omap1/board-palmz71.c @@ -0,0 +1,383 @@ +/* + * linux/arch/arm/mach-omap1/board-palmz71.c + * + * Modified from board-generic.c + * + * Support for the Palm Zire71 PDA. + * + * Original version : Laurent Gonzalez + * + * Modified for zire71 : Marek Vasut + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +static void __init +omap_palmz71_init_irq(void) +{ + omap1_init_common_hw(); + omap_init_irq(); + omap_gpio_init(); +} + +static int palmz71_keymap[] = { + KEY(0, 0, KEY_F1), + KEY(0, 1, KEY_F2), + KEY(0, 2, KEY_F3), + KEY(0, 3, KEY_F4), + KEY(0, 4, KEY_POWER), + KEY(1, 0, KEY_LEFT), + KEY(1, 1, KEY_DOWN), + KEY(1, 2, KEY_UP), + KEY(1, 3, KEY_RIGHT), + KEY(1, 4, KEY_CENTER), + KEY(2, 0, KEY_CAMERA), + 0, +}; + +static struct omap_kp_platform_data palmz71_kp_data = { + .rows = 8, + .cols = 8, + .keymap = palmz71_keymap, + .rep = 1, + .delay = 80, +}; + +static struct resource palmz71_kp_resources[] = { + [0] = { + .start = INT_KEYBOARD, + .end = INT_KEYBOARD, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device palmz71_kp_device = { + .name = "omap-keypad", + .id = -1, + .dev = { + .platform_data = &palmz71_kp_data, + }, + .num_resources = ARRAY_SIZE(palmz71_kp_resources), + .resource = palmz71_kp_resources, +}; + +static struct mtd_partition palmz71_rom_partitions[] = { + /* PalmOS "Small ROM", contains the bootloader and the debugger */ + { + .name = "smallrom", + .offset = 0, + .size = 0xa000, + .mask_flags = MTD_WRITEABLE, + }, + /* PalmOS "Big ROM", a filesystem with all the OS code and data */ + { + .name = "bigrom", + .offset = SZ_128K, + /* + * 0x5f0000 bytes big in the multi-language ("EFIGS") version, + * 0x7b0000 bytes in the English-only ("enUS") version. + */ + .size = 0x7b0000, + .mask_flags = MTD_WRITEABLE, + }, +}; + +static struct flash_platform_data palmz71_rom_data = { + .map_name = "map_rom", + .name = "onboardrom", + .width = 2, + .parts = palmz71_rom_partitions, + .nr_parts = ARRAY_SIZE(palmz71_rom_partitions), +}; + +static struct resource palmz71_rom_resource = { + .start = OMAP_CS0_PHYS, + .end = OMAP_CS0_PHYS + SZ_8M - 1, + .flags = IORESOURCE_MEM, +}; + +static struct platform_device palmz71_rom_device = { + .name = "omapflash", + .id = -1, + .dev = { + .platform_data = &palmz71_rom_data, + }, + .num_resources = 1, + .resource = &palmz71_rom_resource, +}; + +static struct platform_device palmz71_lcd_device = { + .name = "lcd_palmz71", + .id = -1, +}; + +static struct omap_irda_config palmz71_irda_config = { + .transceiver_cap = IR_SIRMODE, + .rx_channel = OMAP_DMA_UART3_RX, + .tx_channel = OMAP_DMA_UART3_TX, + .dest_start = UART3_THR, + .src_start = UART3_RHR, + .tx_trigger = 0, + .rx_trigger = 0, +}; + +static struct resource palmz71_irda_resources[] = { + [0] = { + .start = INT_UART3, + .end = INT_UART3, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device palmz71_irda_device = { + .name = "omapirda", + .id = -1, + .dev = { + .platform_data = &palmz71_irda_config, + }, + .num_resources = ARRAY_SIZE(palmz71_irda_resources), + .resource = palmz71_irda_resources, +}; + +static struct platform_device palmz71_spi_device = { + .name = "spi_palmz71", + .id = -1, +}; + +#define DEFAULT_BITPERSAMPLE 16 + +static struct omap_mcbsp_reg_cfg mcbsp_regs = { + .spcr2 = FREE | FRST | GRST | XRST | XINTM(3), + .spcr1 = RINTM(3) | RRST, + .rcr2 = RPHASE | RFRLEN2(OMAP_MCBSP_WORD_8) | + RWDLEN2(OMAP_MCBSP_WORD_16) | RDATDLY(0), + .rcr1 = RFRLEN1(OMAP_MCBSP_WORD_8) | RWDLEN1(OMAP_MCBSP_WORD_16), + .xcr2 = XPHASE | XFRLEN2(OMAP_MCBSP_WORD_8) | + XWDLEN2(OMAP_MCBSP_WORD_16) | XDATDLY(0) | XFIG, + .xcr1 = XFRLEN1(OMAP_MCBSP_WORD_8) | XWDLEN1(OMAP_MCBSP_WORD_16), + .srgr1 = FWID(DEFAULT_BITPERSAMPLE - 1), + .srgr2 = GSYNC | CLKSP | FSGM | FPER(DEFAULT_BITPERSAMPLE * 2 - 1), + .pcr0 = CLKXP | CLKRP, /* mcbsp: slave */ +}; + +static struct omap_alsa_codec_config alsa_config = { + .name = "PalmZ71 AIC23", + .mcbsp_regs_alsa = &mcbsp_regs, + .codec_configure_dev = NULL, /* aic23_configure */ + .codec_set_samplerate = NULL, /* aic23_set_samplerate */ + .codec_clock_setup = NULL, /* aic23_clock_setup */ + .codec_clock_on = NULL, /* aic23_clock_on */ + .codec_clock_off = NULL, /* aic23_clock_off */ + .get_default_samplerate = NULL, /* aic23_get_default_samplerate */ +}; + +static struct platform_device palmz71_mcbsp1_device = { + .name = "omap_alsa_mcbsp", + .id = 1, + .dev = { + .platform_data = &alsa_config, + }, +}; + +static struct omap_backlight_config palmz71_backlight_config = { + .default_intensity = 0xa0, +}; + +static struct platform_device palmz71_backlight_device = { + .name = "omap-bl", + .id = -1, + .dev = { + .platform_data = &palmz71_backlight_config, + }, +}; + +static struct platform_device *devices[] __initdata = { + &palmz71_rom_device, + &palmz71_kp_device, + &palmz71_mcbsp1_device, + &palmz71_lcd_device, + &palmz71_irda_device, + &palmz71_spi_device, + &palmz71_backlight_device, +}; + +static int +palmz71_get_pendown_state(void) +{ + return !omap_get_gpio_datain(PALMZ71_PENIRQ_GPIO); +} + +static const struct ads7846_platform_data palmz71_ts_info = { + .model = 7846, + .vref_delay_usecs = 100, /* internal, no capacitor */ + .x_plate_ohms = 419, + .y_plate_ohms = 486, + .get_pendown_state = palmz71_get_pendown_state, +}; + +static struct spi_board_info __initdata palmz71_boardinfo[] = { { + /* MicroWire (bus 2) CS0 has an ads7846e */ + .modalias = "ads7846", + .platform_data = &palmz71_ts_info, + .irq = OMAP_GPIO_IRQ(PALMZ71_PENIRQ_GPIO), + .max_speed_hz = 120000 /* max sample rate at 3V */ + * 26 /* command + data + overhead */, + .bus_num = 2, + .chip_select = 0, +} }; + +static struct omap_usb_config palmz71_usb_config __initdata = { + .register_dev = 1, /* Mini-B only receptacle */ + .hmc_mode = 0, + .pins[0] = 2, +}; + +static struct omap_mmc_config palmz71_mmc_config __initdata = { + .mmc[0] = { + .enabled = 1, + .wire4 = 0, + .wp_pin = PALMZ71_MMC_WP_GPIO, + .power_pin = -1, + .switch_pin = PALMZ71_MMC_IN_GPIO, + }, +}; + +static struct omap_lcd_config palmz71_lcd_config __initdata = { + .ctrl_name = "internal", +}; + +static struct omap_uart_config palmz71_uart_config __initdata = { + .enabled_uarts = (1 << 0) | (1 << 1) | (0 << 2), +}; + +static struct omap_board_config_kernel palmz71_config[] = { + {OMAP_TAG_USB, &palmz71_usb_config}, + {OMAP_TAG_MMC, &palmz71_mmc_config}, + {OMAP_TAG_LCD, &palmz71_lcd_config}, + {OMAP_TAG_UART, &palmz71_uart_config}, +}; + +static irqreturn_t +palmz71_powercable(int irq, void *dev_id) +{ + if (omap_get_gpio_datain(PALMZ71_USBDETECT_GPIO)) { + printk(KERN_INFO "PM: Power cable connected\n"); + set_irq_type(OMAP_GPIO_IRQ(PALMZ71_USBDETECT_GPIO), + IRQT_FALLING); + } else { + printk(KERN_INFO "PM: Power cable disconnected\n"); + set_irq_type(OMAP_GPIO_IRQ(PALMZ71_USBDETECT_GPIO), + IRQT_RISING); + } + return IRQ_HANDLED; +} + +static void __init +omap_mpu_wdt_mode(int mode) +{ + if (mode) + omap_writew(0x8000, OMAP_WDT_TIMER_MODE); + else { + omap_writew(0x00f5, OMAP_WDT_TIMER_MODE); + omap_writew(0x00a0, OMAP_WDT_TIMER_MODE); + } +} + +static void __init +palmz71_gpio_setup(int early) +{ + if (early) { + /* Only set GPIO1 so we have a working serial */ + omap_set_gpio_dataout(1, 1); + omap_set_gpio_direction(1, 0); + } else { + /* Set MMC/SD host WP pin as input */ + if (omap_request_gpio(PALMZ71_MMC_WP_GPIO)) { + printk(KERN_ERR "Could not reserve WP GPIO!\n"); + return; + } + omap_set_gpio_direction(PALMZ71_MMC_WP_GPIO, 1); + + /* Monitor the Power-cable-connected signal */ + if (omap_request_gpio(PALMZ71_USBDETECT_GPIO)) { + printk(KERN_ERR + "Could not reserve cable signal GPIO!\n"); + return; + } + omap_set_gpio_direction(PALMZ71_USBDETECT_GPIO, 1); + if (request_irq(OMAP_GPIO_IRQ(PALMZ71_USBDETECT_GPIO), + palmz71_powercable, IRQF_SAMPLE_RANDOM, + "palmz71-cable", 0)) + printk(KERN_ERR + "IRQ request for power cable failed!\n"); + palmz71_powercable(OMAP_GPIO_IRQ(PALMZ71_USBDETECT_GPIO), 0); + } +} + +static void __init +omap_palmz71_init(void) +{ + palmz71_gpio_setup(1); + omap_mpu_wdt_mode(0); + + omap_board_config = palmz71_config; + omap_board_config_size = ARRAY_SIZE(palmz71_config); + + platform_add_devices(devices, ARRAY_SIZE(devices)); + + spi_register_board_info(palmz71_boardinfo, + ARRAY_SIZE(palmz71_boardinfo)); + omap_serial_init(); + palmz71_gpio_setup(0); +} + +static void __init +omap_palmz71_map_io(void) +{ + omap1_map_common_io(); +} + +MACHINE_START(OMAP_PALMZ71, "OMAP310 based Palm Zire71") + .phys_io = 0xfff00000, + .io_pg_offst = ((0xfef00000) >> 18) & 0xfffc, + .boot_params = 0x10000100,.map_io = omap_palmz71_map_io, + .init_irq = omap_palmz71_init_irq, + .init_machine = omap_palmz71_init, + .timer = &omap_timer, +MACHINE_END diff --git a/include/asm-arm/arch-omap/board-palmz71.h b/include/asm-arm/arch-omap/board-palmz71.h new file mode 100644 index 0000000..1252a85 --- /dev/null +++ b/include/asm-arm/arch-omap/board-palmz71.h @@ -0,0 +1,26 @@ +/* + * linux/include/asm-arm/arch-omap/board-palmz71.h + * + * Hardware definitions for the Palm Zire71 device. + * + * Maintainters : Marek Vasut + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __OMAP_BOARD_PALMZ71_H +#define __OMAP_BOARD_PALMZ71_H + +#define PALMZ71_USBDETECT_GPIO 0 +#define PALMZ71_PENIRQ_GPIO 6 +#define PALMZ71_MMC_WP_GPIO 8 +#define PALMZ71_HDQ_GPIO 11 + +#define PALMZ71_HOTSYNC_GPIO OMAP_MPUIO(1) +#define PALMZ71_CABLE_GPIO OMAP_MPUIO(2) +#define PALMZ71_SLIDER_GPIO OMAP_MPUIO(3) +#define PALMZ71_MMC_IN_GPIO OMAP_MPUIO(4) + +#endif /* __OMAP_BOARD_PALMZ71_H */ diff --git a/include/asm-arm/arch-omap/hardware.h b/include/asm-arm/arch-omap/hardware.h index 539f16d..3903a6d 100644 --- a/include/asm-arm/arch-omap/hardware.h +++ b/include/asm-arm/arch-omap/hardware.h @@ -334,6 +334,10 @@ #include "board-palmte.h" #endif +#ifdef CONFIG_MACH_OMAP_PALMZ71 +#include "board-palmz71.h" +#endif + #endif /* !__ASSEMBLER__ */ #endif /* __ASM_ARCH_OMAP_HARDWARE_H */ -- cgit v0.10.2 From cc32658ca0d7ff33a2e5778227a9c6dc3ad29856 Mon Sep 17 00:00:00 2001 From: Andrzej Zaborowski Date: Wed, 6 Dec 2006 17:13:58 -0800 Subject: ARM: OMAP: Register tsc2102 on Palm Tungsten E Add palmte board config bits for TSC2102 controlled devices. This will enable touchscreen, audio and APM code to report battery level. If there are other boards at some point that use a TSC2102, similar code can be used. Signed-off-by: Andrzej Zaborowski Signed-off-by: Tony Lindgren diff --git a/arch/arm/mach-omap1/board-palmte.c b/arch/arm/mach-omap1/board-palmte.c index 2f9d00a..9af031a 100644 --- a/arch/arm/mach-omap1/board-palmte.c +++ b/arch/arm/mach-omap1/board-palmte.c @@ -321,6 +321,116 @@ static struct tsc2102_config palmte_tsc2102_config = { .alsa_config = &palmte_alsa_config, }; +static struct omap_mcbsp_reg_cfg palmte_mcbsp1_regs = { + .spcr2 = FRST | GRST | XRST | XINTM(3), + .xcr2 = XDATDLY(1) | XFIG, + .xcr1 = XWDLEN1(OMAP_MCBSP_WORD_32), + .pcr0 = SCLKME | FSXP | CLKXP, +}; + +static struct omap_alsa_codec_config palmte_alsa_config = { + .name = "TSC2102 audio", + .mcbsp_regs_alsa = &palmte_mcbsp1_regs, + .codec_configure_dev = NULL, /* tsc2102_configure, */ + .codec_set_samplerate = NULL, /* tsc2102_set_samplerate, */ + .codec_clock_setup = NULL, /* tsc2102_clock_setup, */ + .codec_clock_on = NULL, /* tsc2102_clock_on, */ + .codec_clock_off = NULL, /* tsc2102_clock_off, */ + .get_default_samplerate = NULL, /* tsc2102_get_default_samplerate, */ +}; + +#ifdef CONFIG_APM +/* + * Values measured in 10 minute intervals averaged over 10 samples. + * May differ slightly from device to device but should be accurate + * enough to give basic idea of battery life left and trigger + * potential alerts. + */ +static const int palmte_battery_sample[] = { + 2194, 2157, 2138, 2120, + 2104, 2089, 2075, 2061, + 2048, 2038, 2026, 2016, + 2008, 1998, 1989, 1980, + 1970, 1958, 1945, 1928, + 1910, 1888, 1860, 1827, + 1791, 1751, 1709, 1656, +}; + +#define INTERVAL 10 +#define BATTERY_HIGH_TRESHOLD 66 +#define BATTERY_LOW_TRESHOLD 33 + +static void palmte_get_power_status(struct apm_power_info *info, int *battery) +{ + int charging, batt, hi, lo, mid; + + charging = !omap_get_gpio_datain(PALMTE_DC_GPIO); + batt = battery[0]; + if (charging) + batt -= 60; + + hi = ARRAY_SIZE(palmte_battery_sample); + lo = 0; + + info->battery_flag = 0; + info->units = APM_UNITS_MINS; + + if (batt > palmte_battery_sample[lo]) { + info->battery_life = 100; + info->time = INTERVAL * ARRAY_SIZE(palmte_battery_sample); + } else if (batt <= palmte_battery_sample[hi - 1]) { + info->battery_life = 0; + info->time = 0; + } else { + while (hi > lo + 1) { + mid = (hi + lo) >> 2; + if (batt <= palmte_battery_sample[mid]) + lo = mid; + else + hi = mid; + } + + mid = palmte_battery_sample[lo] - palmte_battery_sample[hi]; + hi = palmte_battery_sample[lo] - batt; + info->battery_life = 100 - (100 * lo + 100 * hi / mid) / + ARRAY_SIZE(palmte_battery_sample); + info->time = INTERVAL * (ARRAY_SIZE(palmte_battery_sample) - + lo) - INTERVAL * hi / mid; + } + + if (charging) { + info->ac_line_status = APM_AC_ONLINE; + info->battery_status = APM_BATTERY_STATUS_CHARGING; + info->battery_flag |= APM_BATTERY_FLAG_CHARGING; + } else { + info->ac_line_status = APM_AC_OFFLINE; + if (info->battery_life > BATTERY_HIGH_TRESHOLD) + info->battery_status = APM_BATTERY_STATUS_HIGH; + else if (info->battery_life > BATTERY_LOW_TRESHOLD) + info->battery_status = APM_BATTERY_STATUS_LOW; + else + info->battery_status = APM_BATTERY_STATUS_CRITICAL; + } + + if (info->battery_life > BATTERY_HIGH_TRESHOLD) + info->battery_flag |= APM_BATTERY_FLAG_HIGH; + else if (info->battery_life > BATTERY_LOW_TRESHOLD) + info->battery_flag |= APM_BATTERY_FLAG_LOW; + else + info->battery_flag |= APM_BATTERY_FLAG_CRITICAL; +} +#else +#define palmte_get_power_status NULL +#endif + +static struct tsc2102_config palmte_tsc2102_config = { + .use_internal = 0, + .monitor = TSC_BAT1 | TSC_AUX | TSC_TEMP, + .temp_at25c = { 2200, 2615 }, + .apm_report = palmte_get_power_status, + .alsa_config = &palmte_alsa_config, +}; + static struct omap_board_config_kernel palmte_config[] = { { OMAP_TAG_USB, &palmte_usb_config }, { OMAP_TAG_MMC, &palmte_mmc_config }, @@ -339,6 +449,17 @@ static struct spi_board_info palmte_spi_info[] __initdata = { }, }; +static struct spi_board_info palmte_spi_info[] __initdata = { + { + .modalias = "tsc2102", + .bus_num = 2, /* uWire (officially) */ + .chip_select = 0, /* As opposed to 3 */ + .irq = OMAP_GPIO_IRQ(PALMTE_PINTDAV_GPIO), + .platform_data = &palmte_tsc2102_config, + .max_speed_hz = 8000000, + }, +}; + /* Periodically check for changes on important input pins */ struct timer_list palmte_pin_timer; int prev_power, prev_headphones; @@ -418,6 +539,8 @@ static void __init omap_palmte_init(void) spi_register_board_info(palmte_spi_info, ARRAY_SIZE(palmte_spi_info)); + spi_register_board_info(palmte_spi_info, ARRAY_SIZE(palmte_spi_info)); + omap_serial_init(); palmte_gpio_setup(); } -- cgit v0.10.2 From dc563b4f2de0dd57a8febe26158cdf59bc15534f Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 6 Dec 2006 17:14:07 -0800 Subject: ARM: OMAP: Palm Tungsten|T support This patch adds board file and necessary includes for Palm Tungsten|T. Signed-off-by: Marek Vasut Signed-off-by: Tony Lindgren diff --git a/arch/arm/mach-omap1/Kconfig b/arch/arm/mach-omap1/Kconfig index 1085e12c..7386dc3 100644 --- a/arch/arm/mach-omap1/Kconfig +++ b/arch/arm/mach-omap1/Kconfig @@ -98,6 +98,15 @@ config MACH_OMAP_PALMZ71 http://hackndev.com/palm/z71 for more informations. Say Y here if you have such a PDA, say N otherwise. +config MACH_OMAP_PALMTT + bool "Palm Tungsten|T" + depends on ARCH_OMAP1 && ARCH_OMAP15XX + help + Support for the Palm Tungsten|T PDA. To boot the kernel, you'll + need a PalmOS compatible bootloader (Garux); check out + http://www.hackndev.com/palm/tt/ for more information. + Say Y here if you have this PDA model, say N otherwise. + config MACH_NOKIA770 bool "Nokia 770" depends on ARCH_OMAP1 && ARCH_OMAP16XX diff --git a/arch/arm/mach-omap1/Makefile b/arch/arm/mach-omap1/Makefile index 76cbc68..3a7cd28 100644 --- a/arch/arm/mach-omap1/Makefile +++ b/arch/arm/mach-omap1/Makefile @@ -23,6 +23,7 @@ obj-$(CONFIG_MACH_OMAP_H3) += board-h3.o obj-$(CONFIG_MACH_VOICEBLUE) += board-voiceblue.o obj-$(CONFIG_MACH_OMAP_PALMTE) += board-palmte.o obj-$(CONFIG_MACH_OMAP_PALMZ71) += board-palmz71.o +obj-$(CONFIG_MACH_OMAP_PALMTT) += board-palmtt.o obj-$(CONFIG_MACH_NOKIA770) += board-nokia770.o obj-$(CONFIG_MACH_AMS_DELTA) += board-ams-delta.o diff --git a/arch/arm/mach-omap1/board-palmtt.c b/arch/arm/mach-omap1/board-palmtt.c new file mode 100644 index 0000000..3c9a41a --- /dev/null +++ b/arch/arm/mach-omap1/board-palmtt.c @@ -0,0 +1,357 @@ +/* + * linux/arch/arm/mach-omap1/board-palmtt.c + * + * Modified from board-palmtt2.c + * + * Modified and amended for Palm Tungsten|T + * by Marek Vasut + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +static int palmtt_keymap[] = { + KEY(0, 0, KEY_ESC), + KEY(0, 1, KEY_SPACE), + KEY(0, 2, KEY_LEFTCTRL), + KEY(0, 3, KEY_TAB), + KEY(0, 4, KEY_ENTER), + KEY(1, 0, KEY_LEFT), + KEY(1, 1, KEY_DOWN), + KEY(1, 2, KEY_UP), + KEY(1, 3, KEY_RIGHT), + KEY(2, 0, KEY_SLEEP), + KEY(2, 4, KEY_Y), + 0 +}; + +static struct mtd_partition palmtt_partitions[] = { + { + .name = "write8k", + .offset = 0, + .size = SZ_8K, + .mask_flags = 0, + }, + { + .name = "PalmOS-BootLoader(ro)", + .offset = SZ_8K, + .size = 7 * SZ_8K, + .mask_flags = MTD_WRITEABLE, + }, + { + .name = "u-boot", + .offset = MTDPART_OFS_APPEND, + .size = 8 * SZ_8K, + .mask_flags = 0, + }, + { + .name = "PalmOS-FS(ro)", + .offset = MTDPART_OFS_APPEND, + .size = 7 * SZ_1M + 4 * SZ_64K - 16 * SZ_8K, + .mask_flags = MTD_WRITEABLE, + }, + { + .name = "u-boot(rez)", + .offset = MTDPART_OFS_APPEND, + .size = SZ_128K, + .mask_flags = 0 + }, + { + .name = "empty", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + .mask_flags = 0 + } +}; + +static struct flash_platform_data palmtt_flash_data = { + .map_name = "cfi_probe", + .width = 2, + .parts = palmtt_partitions, + .nr_parts = ARRAY_SIZE(palmtt_partitions), +}; + +static struct resource palmtt_flash_resource = { + .start = OMAP_CS0_PHYS, + .end = OMAP_CS0_PHYS + SZ_8M - 1, + .flags = IORESOURCE_MEM, +}; + +static struct platform_device palmtt_flash_device = { + .name = "omapflash", + .id = 0, + .dev = { + .platform_data = &palmtt_flash_data, + }, + .num_resources = 1, + .resource = &palmtt_flash_resource, +}; + +#define DEFAULT_BITPERSAMPLE 16 + +static struct omap_mcbsp_reg_cfg mcbsp_regs = { + .spcr2 = FREE | FRST | GRST | XRST | XINTM(3), + .spcr1 = RINTM(3) | RRST, + .rcr2 = RPHASE | RFRLEN2(OMAP_MCBSP_WORD_8) | + RWDLEN2(OMAP_MCBSP_WORD_16) | RDATDLY(0), + .rcr1 = RFRLEN1(OMAP_MCBSP_WORD_8) | + RWDLEN1(OMAP_MCBSP_WORD_16), + .xcr2 = XPHASE | XFRLEN2(OMAP_MCBSP_WORD_8) | + XWDLEN2(OMAP_MCBSP_WORD_16) | XDATDLY(0) | XFIG, + .xcr1 = XFRLEN1(OMAP_MCBSP_WORD_8) | + XWDLEN1(OMAP_MCBSP_WORD_16), + .srgr1 = FWID(DEFAULT_BITPERSAMPLE - 1), + .srgr2 = GSYNC | CLKSP | FSGM | + FPER(DEFAULT_BITPERSAMPLE * 2 - 1), + .pcr0 = CLKXP | CLKRP, /* mcbsp: slave */ +}; + +static struct omap_alsa_codec_config alsa_config = { + .name = "PalmTT AIC23", + .mcbsp_regs_alsa = &mcbsp_regs, + .codec_configure_dev = NULL, // aic23_configure, + .codec_set_samplerate = NULL, // aic23_set_samplerate, + .codec_clock_setup = NULL, // aic23_clock_setup, + .codec_clock_on = NULL, // aic23_clock_on, + .codec_clock_off = NULL, // aic23_clock_off, + .get_default_samplerate = NULL, // aic23_get_default_samplerate, +}; + +static struct platform_device palmtt_mcbsp1_device = { + .name = "omap_alsa_mcbsp", + .id = 1, + .dev = { + .platform_data = &alsa_config, + }, +}; + +static struct resource palmtt_kp_resources[] = { + [0] = { + .start = INT_KEYBOARD, + .end = INT_KEYBOARD, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct omap_kp_platform_data palmtt_kp_data = { + .rows = 6, + .cols = 3, + .keymap = palmtt_keymap, +}; + +static struct platform_device palmtt_kp_device = { + .name = "omap-keypad", + .id = -1, + .dev = { + .platform_data = &palmtt_kp_data, + }, + .num_resources = ARRAY_SIZE(palmtt_kp_resources), + .resource = palmtt_kp_resources, +}; + +static struct platform_device palmtt_lcd_device = { + .name = "lcd_palmtt", + .id = -1, +}; +static struct omap_irda_config palmtt_irda_config = { + .transceiver_cap = IR_SIRMODE, + .rx_channel = OMAP_DMA_UART3_RX, + .tx_channel = OMAP_DMA_UART3_TX, + .dest_start = UART3_THR, + .src_start = UART3_RHR, + .tx_trigger = 0, + .rx_trigger = 0, +}; + +static struct resource palmtt_irda_resources[] = { + [0] = { + .start = INT_UART3, + .end = INT_UART3, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device palmtt_irda_device = { + .name = "omapirda", + .id = -1, + .dev = { + .platform_data = &palmtt_irda_config, + }, + .num_resources = ARRAY_SIZE(palmtt_irda_resources), + .resource = palmtt_irda_resources, +}; + +static struct platform_device palmtt_spi_device = { + .name = "spi_palmtt", + .id = -1, +}; + +static struct omap_backlight_config palmtt_backlight_config = { + .default_intensity = 0xa0, +}; + +static struct platform_device palmtt_backlight_device = { + .name = "omap-bl", + .id = -1, + .dev = { + .platform_data= &palmtt_backlight_config, + }, +}; + +static struct omap_led_config palmtt_led_config[] = { + { + .cdev = { + .name = "palmtt:led0", + }, + .gpio = PALMTT_LED_GPIO, + }, +}; + +static struct omap_led_platform_data palmtt_led_data = { + .nr_leds = ARRAY_SIZE(palmtt_led_config), + .leds = palmtt_led_config, +}; + +static struct platform_device palmtt_led_device = { + .name = "omap-led", + .id = -1, + .dev = { + .platform_data = &palmtt_led_data, + }, +}; + +static struct platform_device *palmtt_devices[] __initdata = { + &palmtt_flash_device, + &palmtt_mcbsp1_device, + &palmtt_kp_device, + &palmtt_lcd_device, + &palmtt_irda_device, + &palmtt_spi_device, + &palmtt_backlight_device, + &palmtt_led_device, +}; + +static int palmtt_get_pendown_state(void) +{ + return !omap_get_gpio_datain(6); +} + +static const struct ads7846_platform_data palmtt_ts_info = { + .model = 7846, + .vref_delay_usecs = 100, /* internal, no capacitor */ + .x_plate_ohms = 419, + .y_plate_ohms = 486, + .get_pendown_state = palmtt_get_pendown_state, +}; + +static struct spi_board_info __initdata palmtt_boardinfo[] = { + { + /* MicroWire (bus 2) CS0 has an ads7846e */ + .modalias = "ads7846", + .platform_data = &palmtt_ts_info, + .irq = OMAP_GPIO_IRQ(6), + .max_speed_hz = 120000 /* max sample rate at 3V */ + * 26 /* command + data + overhead */, + .bus_num = 2, + .chip_select = 0, + } +}; + +static void __init omap_palmtt_init_irq(void) +{ + omap1_init_common_hw(); + omap_init_irq(); +} + +static struct omap_usb_config palmtt_usb_config __initdata = { + .register_dev = 1, + .hmc_mode = 0, + .pins[0] = 2, +}; + +static struct omap_lcd_config palmtt_lcd_config __initdata = { + .ctrl_name = "internal", +}; + +static struct omap_uart_config palmtt_uart_config __initdata = { + .enabled_uarts = (1 << 0) | (1 << 1) | (0 << 2), +}; + +static struct omap_board_config_kernel palmtt_config[] = { + { OMAP_TAG_USB, &palmtt_usb_config }, + { OMAP_TAG_LCD, &palmtt_lcd_config }, + { OMAP_TAG_UART, &palmtt_uart_config }, +}; + +static void __init omap_mpu_wdt_mode(int mode) { + if (mode) + omap_writew(0x8000, OMAP_WDT_TIMER_MODE); + else { + omap_writew(0x00f5, OMAP_WDT_TIMER_MODE); + omap_writew(0x00a0, OMAP_WDT_TIMER_MODE); + } +} + +static void __init omap_palmtt_init(void) +{ + omap_mpu_wdt_mode(0); + + omap_board_config = palmtt_config; + omap_board_config_size = ARRAY_SIZE(palmtt_config); + + platform_add_devices(palmtt_devices, ARRAY_SIZE(palmtt_devices)); + + spi_register_board_info(palmtt_boardinfo,ARRAY_SIZE(palmtt_boardinfo)); + omap_serial_init(); +} + +static void __init omap_palmtt_map_io(void) +{ + omap1_map_common_io(); +} + +MACHINE_START(OMAP_PALMTT, "OMAP1510 based Palm Tungsten|T") + .phys_io = 0xfff00000, + .io_pg_offst = ((0xfef00000) >> 18) & 0xfffc, + .boot_params = 0x10000100, + .map_io = omap_palmtt_map_io, + .init_irq = omap_palmtt_init_irq, + .init_machine = omap_palmtt_init, + .timer = &omap_timer, +MACHINE_END diff --git a/include/asm-arm/arch-omap/board-palmtt.h b/include/asm-arm/arch-omap/board-palmtt.h new file mode 100644 index 0000000..d9590b0 --- /dev/null +++ b/include/asm-arm/arch-omap/board-palmtt.h @@ -0,0 +1,23 @@ +/* + * linux/include/asm-arm/arch-omap/board-palmte.h + * + * Hardware definitions for the Palm Tungsten|T device. + * + * Maintainters : Marek Vasut + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __OMAP_BOARD_PALMTT_H +#define __OMAP_BOARD_PALMTT_H + +#define PALMTT_USBDETECT_GPIO 0 +#define PALMTT_CABLE_GPIO 1 +#define PALMTT_LED_GPIO 3 +#define PALMTT_PENIRQ_GPIO 6 +#define PALMTT_MMC_WP_GPIO 8 +#define PALMTT_HDQ_GPIO 11 + +#endif /* __OMAP_BOARD_PALMTT_H */ diff --git a/include/asm-arm/arch-omap/hardware.h b/include/asm-arm/arch-omap/hardware.h index 3903a6d..18c52d7 100644 --- a/include/asm-arm/arch-omap/hardware.h +++ b/include/asm-arm/arch-omap/hardware.h @@ -338,6 +338,10 @@ #include "board-palmz71.h" #endif +#ifdef CONFIG_MACH_OMAP_PALMTT +#include "board-palmtt.h" +#endif + #endif /* !__ASSEMBLER__ */ #endif /* __ASM_ARCH_OMAP_HARDWARE_H */ -- cgit v0.10.2 From c79ed1940ca9a4af5e9c182ac51f28dadd32956d Mon Sep 17 00:00:00 2001 From: Vladimir Ananiev Date: Wed, 6 Dec 2006 17:14:08 -0800 Subject: ARM: OMAP: Basic support for siemens sx1 This adds basic support for Siemens SX1. More patches are available, with video driver, mixer, and serial ports working. That is enough to do gsm calls with right userland. Signed-off-by: Pavel Machek Signed-off-by: Tony Lindgren diff --git a/arch/arm/mach-omap1/Kconfig b/arch/arm/mach-omap1/Kconfig index 7386dc3..79f0b1f 100644 --- a/arch/arm/mach-omap1/Kconfig +++ b/arch/arm/mach-omap1/Kconfig @@ -107,6 +107,17 @@ config MACH_OMAP_PALMTT http://www.hackndev.com/palm/tt/ for more information. Say Y here if you have this PDA model, say N otherwise. +config MACH_SX1 + bool "Siemens SX1" + depends on ARCH_OMAP1 && ARCH_OMAP15XX + help + Support for the Siemens SX1 phone. To boot the kernel, + you'll need a SX1 compatible bootloader; check out + http://forum.oslik.ru and + http://www.handhelds.org/moin/moin.cgi/SiemensSX1 + for more information. + Say Y here if you have such a phone, say NO otherwise. + config MACH_NOKIA770 bool "Nokia 770" depends on ARCH_OMAP1 && ARCH_OMAP16XX diff --git a/arch/arm/mach-omap1/Makefile b/arch/arm/mach-omap1/Makefile index 3a7cd28..391b6f4 100644 --- a/arch/arm/mach-omap1/Makefile +++ b/arch/arm/mach-omap1/Makefile @@ -26,6 +26,7 @@ obj-$(CONFIG_MACH_OMAP_PALMZ71) += board-palmz71.o obj-$(CONFIG_MACH_OMAP_PALMTT) += board-palmtt.o obj-$(CONFIG_MACH_NOKIA770) += board-nokia770.o obj-$(CONFIG_MACH_AMS_DELTA) += board-ams-delta.o +obj-$(CONFIG_MACH_SX1) += board-sx1.o ifeq ($(CONFIG_ARCH_OMAP15XX),y) # Innovator-1510 FPGA diff --git a/arch/arm/mach-omap1/board-sx1.c b/arch/arm/mach-omap1/board-sx1.c new file mode 100644 index 0000000..2743d63 --- /dev/null +++ b/arch/arm/mach-omap1/board-sx1.c @@ -0,0 +1,494 @@ +/* +* linux/arch/arm/mach-omap1/board-sx1.c +* +* Modified from board-generic.c +* +* Support for the Siemens SX1 mobile phone. +* +* Original version : Vladimir Ananiev (Vovan888-at-gmail com) +* +* Maintainters : Vladimir Ananiev (aka Vovan888), Sergge +* oslik.ru +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 as +* published by the Free Software Foundation. +*/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Write to I2C device */ +int i2c_write_byte(u8 devaddr, u8 regoffset, u8 value) +{ + struct i2c_adapter *adap; + int err; + struct i2c_msg msg[1]; + unsigned char data[2]; + + adap = i2c_get_adapter(0); + if (!adap) + return -ENODEV; + msg->addr = devaddr; /* I2C address of chip */ + msg->flags = 0; + msg->len = 2; + msg->buf = data; + data[0] = regoffset; /* register num */ + data[1] = value; /* register data */ + err = i2c_transfer(adap, msg, 1); + if (err >= 0) + return 0; + return err; +} + +/* Read from I2C device */ +int i2c_read_byte(u8 devaddr, u8 regoffset, u8 * value) +{ + struct i2c_adapter *adap; + int err; + struct i2c_msg msg[1]; + unsigned char data[2]; + + adap = i2c_get_adapter(0); + if (!adap) + return -ENODEV; + + msg->addr = devaddr; /* I2C address of chip */ + msg->flags = 0; + msg->len = 1; + msg->buf = data; + data[0] = regoffset; /* register num */ + err = i2c_transfer(adap, msg, 1); + + msg->addr = devaddr; /* I2C address */ + msg->flags = I2C_M_RD; + msg->len = 1; + msg->buf = data; + err = i2c_transfer(adap, msg, 1); + *value = data[0]; + + if (err >= 0) + return 0; + return err; +} +/* set keyboard backlight intensity */ +int sx1_setkeylight(u8 keylight) +{ + if (keylight > SOFIA_MAX_LIGHT_VAL) + keylight = SOFIA_MAX_LIGHT_VAL; + return i2c_write_byte(SOFIA_I2C_ADDR, SOFIA_KEYLIGHT_REG, keylight); +} +/* get current keylight intensity */ +int sx1_getkeylight(u8 * keylight) +{ + return i2c_read_byte(SOFIA_I2C_ADDR, SOFIA_KEYLIGHT_REG, keylight); +} +/* set LCD backlight intensity */ +int sx1_setbacklight(u8 backlight) +{ + if (backlight > SOFIA_MAX_LIGHT_VAL) + backlight = SOFIA_MAX_LIGHT_VAL; + return i2c_write_byte(SOFIA_I2C_ADDR, SOFIA_BACKLIGHT_REG, backlight); +} +/* get current LCD backlight intensity */ +int sx1_getbacklight (u8 * backlight) +{ + return i2c_read_byte(SOFIA_I2C_ADDR, SOFIA_BACKLIGHT_REG, backlight); +} +/* set LCD backlight power on/off */ +int sx1_setmmipower(u8 onoff) +{ + int err; + u8 dat = 0; + err = i2c_read_byte(SOFIA_I2C_ADDR, SOFIA_POWER1_REG, &dat); + if (err < 0) + return err; + if (onoff) + dat |= SOFIA_MMILIGHT_POWER; + else + dat &= ~SOFIA_MMILIGHT_POWER; + return i2c_write_byte(SOFIA_I2C_ADDR, SOFIA_POWER1_REG, dat); +} +/* set MMC power on/off */ +int sx1_setmmcpower(u8 onoff) +{ + int err; + u8 dat = 0; + err = i2c_read_byte(SOFIA_I2C_ADDR, SOFIA_POWER1_REG, &dat); + if (err < 0) + return err; + if (onoff) + dat |= SOFIA_MMC_POWER; + else + dat &= ~SOFIA_MMC_POWER; + return i2c_write_byte(SOFIA_I2C_ADDR, SOFIA_POWER1_REG, dat); +} +/* set USB power on/off */ +int sx1_setusbpower(u8 onoff) +{ + int err; + u8 dat = 0; + err = i2c_read_byte(SOFIA_I2C_ADDR, SOFIA_POWER1_REG, &dat); + if (err < 0) + return err; + if (onoff) + dat |= SOFIA_USB_POWER; + else + dat &= ~SOFIA_USB_POWER; + return i2c_write_byte(SOFIA_I2C_ADDR, SOFIA_POWER1_REG, dat); +} + +EXPORT_SYMBOL(sx1_setkeylight); +EXPORT_SYMBOL(sx1_getkeylight); +EXPORT_SYMBOL(sx1_setbacklight); +EXPORT_SYMBOL(sx1_getbacklight); +EXPORT_SYMBOL(sx1_setmmipower); +EXPORT_SYMBOL(sx1_setmmcpower); +EXPORT_SYMBOL(sx1_setusbpower); + +/*----------- Keypad -------------------------*/ + +static int sx1_keymap[] = { + KEY(5, 3, GROUP_0 | 117), /* camera Qt::Key_F17 */ + KEY(0, 4, GROUP_0 | 114), /* voice memo Qt::Key_F14 */ + KEY(1, 4, GROUP_2 | 114), /* voice memo */ + KEY(2, 4, GROUP_3 | 114), /* voice memo */ + KEY(0, 0, GROUP_1 | KEY_F12), /* red button Qt::Key_Hangup */ + KEY(4, 3, GROUP_1 | KEY_LEFT), + KEY(2, 3, GROUP_1 | KEY_DOWN), + KEY(1, 3, GROUP_1 | KEY_RIGHT), + KEY(0, 3, GROUP_1 | KEY_UP), + KEY(3, 3, GROUP_1 | KEY_POWER), /* joystick press or Qt::Key_Select */ + KEY(5, 0, GROUP_1 | KEY_1), + KEY(4, 0, GROUP_1 | KEY_2), + KEY(3, 0, GROUP_1 | KEY_3), + KEY(3, 4, GROUP_1 | KEY_4), + KEY(4, 4, GROUP_1 | KEY_5), + KEY(5, 4, GROUP_1 | KEY_KPASTERISK),/* "*" */ + KEY(4, 1, GROUP_1 | KEY_6), + KEY(5, 1, GROUP_1 | KEY_7), + KEY(3, 1, GROUP_1 | KEY_8), + KEY(3, 2, GROUP_1 | KEY_9), + KEY(5, 2, GROUP_1 | KEY_0), + KEY(4, 2, GROUP_1 | 113), /* # F13 Toggle input method Qt::Key_F13 */ + KEY(0, 1, GROUP_1 | KEY_F11), /* green button Qt::Key_Call */ + KEY(1, 2, GROUP_1 | KEY_YEN), /* left soft Qt::Key_Context1 */ + KEY(2, 2, GROUP_1 | KEY_F8), /* right soft Qt::Key_Back */ + KEY(2, 1, GROUP_1 | KEY_LEFTSHIFT), /* shift */ + KEY(1, 1, GROUP_1 | KEY_BACKSPACE), /* C (clear) */ + KEY(0, 2, GROUP_1 | KEY_F7), /* menu Qt::Key_Menu */ + 0 +}; + +static struct resource sx1_kp_resources[] = { + [0] = { + .start = INT_KEYBOARD, + .end = INT_KEYBOARD, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct omap_kp_platform_data sx1_kp_data = { + .rows = 6, + .cols = 6, + .keymap = sx1_keymap, + .keymapsize = ARRAY_SIZE(sx1_keymap), + .delay = 80, +}; + +static struct platform_device sx1_kp_device = { + .name = "omap-keypad", + .id = -1, + .dev = { + .platform_data = &sx1_kp_data, + }, + .num_resources = ARRAY_SIZE(sx1_kp_resources), + .resource = sx1_kp_resources, +}; + +/*----------- IRDA -------------------------*/ + +static struct omap_irda_config sx1_irda_data = { + .transceiver_cap = IR_SIRMODE, + .rx_channel = OMAP_DMA_UART3_RX, + .tx_channel = OMAP_DMA_UART3_TX, + .dest_start = UART3_THR, + .src_start = UART3_RHR, + .tx_trigger = 0, + .rx_trigger = 0, +}; + +static struct resource sx1_irda_resources[] = { + [0] = { + .start = INT_UART3, + .end = INT_UART3, + .flags = IORESOURCE_IRQ, + }, +}; + +static u64 irda_dmamask = 0xffffffff; + +static struct platform_device sx1_irda_device = { + .name = "omapirda", + .id = 0, + .dev = { + .platform_data = &sx1_irda_data, + .dma_mask = &irda_dmamask, + }, + .num_resources = ARRAY_SIZE(sx1_irda_resources), + .resource = sx1_irda_resources, +}; + +/*----------- McBSP & Sound -------------------------*/ + +/* Playback interface - McBSP1 */ +static struct omap_mcbsp_reg_cfg mcbsp1_regs = { + .spcr2 = XINTM(3), /* SPCR2=30 */ + .spcr1 = RINTM(3), /* SPCR1=30 */ + .rcr2 = 0, /* RCR2 =00 */ + .rcr1 = RFRLEN1(1) | RWDLEN1(OMAP_MCBSP_WORD_16), /* RCR1=140 */ + .xcr2 = 0, /* XCR2 = 0 */ + .xcr1 = XFRLEN1(1) | XWDLEN1(OMAP_MCBSP_WORD_16), /* XCR1 = 140 */ + .srgr1 = FWID(15) | CLKGDV(12), /* SRGR1=0f0c */ + .srgr2 = FSGM | FPER(31), /* SRGR2=101f */ + .pcr0 = FSXM | FSRM | CLKXM | CLKRM | FSXP | FSRP | CLKXP | CLKRP, + /* PCR0 =0f0f */ +}; + +/* TODO: PCM interface - McBSP2 */ +static struct omap_mcbsp_reg_cfg mcbsp2_regs = { + .spcr2 = FRST | GRST | XRST | XINTM(3), /* SPCR2=F1 */ + .spcr1 = RINTM(3) | RRST, /* SPCR1=30 */ + .rcr2 = 0, /* RCR2 =00 */ + .rcr1 = RFRLEN1(1) | RWDLEN1(OMAP_MCBSP_WORD_16), /* RCR1 = 140 */ + .xcr2 = 0, /* XCR2 = 0 */ + .xcr1 = XFRLEN1(1) | XWDLEN1(OMAP_MCBSP_WORD_16), /* XCR1 = 140 */ + .srgr1 = FWID(15) | CLKGDV(12), /* SRGR1=0f0c */ + .srgr2 = FSGM | FPER(31), /* SRGR2=101f */ + .pcr0 = FSXM | FSRM | CLKXM | CLKRM | FSXP | FSRP | CLKXP | CLKRP, + /* PCR0=0f0f */ + /* mcbsp: slave */ +}; + +static struct omap_alsa_codec_config sx1_alsa_config = { + .name = "SX1 EGold", + .mcbsp_regs_alsa = &mcbsp1_regs, +}; + +static struct platform_device sx1_mcbsp1_device = { + .name = "omap_alsa_mcbsp", + .id = 1, + .dev = { + .platform_data = &sx1_alsa_config, + }, +}; + +/*----------- MTD -------------------------*/ + +static struct mtd_partition sx1_partitions[] = { + /* bootloader (U-Boot, etc) in first sector */ + { + .name = "bootloader", + .offset = 0x01800000, + .size = SZ_128K, + .mask_flags = MTD_WRITEABLE, /* force read-only */ + }, + /* bootloader params in the next sector */ + { + .name = "params", + .offset = MTDPART_OFS_APPEND, + .size = SZ_128K, + .mask_flags = 0, + }, + /* kernel */ + { + .name = "kernel", + .offset = MTDPART_OFS_APPEND, + .size = SZ_2M - 2 * SZ_128K, + .mask_flags = 0 + }, + /* file system */ + { + .name = "filesystem", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + .mask_flags = 0 + } +}; + +static struct flash_platform_data sx1_flash_data = { + .map_name = "cfi_probe", + .width = 2, + .parts = sx1_partitions, + .nr_parts = ARRAY_SIZE(sx1_partitions), +}; + +#ifdef CONFIG_SX1_OLD_FLASH +/* MTD Intel StrataFlash - old flashes */ +static struct resource sx1_old_flash_resource[] = { + [0] = { + .start = OMAP_CS0_PHYS, /* Physical */ + .end = OMAP_CS0_PHYS + SZ_16M - 1,, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = OMAP_CS1_PHYS, + .end = OMAP_CS1_PHYS + SZ_8M - 1, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device sx1_flash_device = { + .name = "omapflash", + .id = 0, + .dev = { + .platform_data = &sx1_flash_data, + }, + .num_resources = 2, + .resource = &sx1_old_flash_resource, +}; +#else +/* MTD Intel 4000 flash - new flashes */ +static struct resource sx1_new_flash_resource = { + .start = OMAP_CS0_PHYS, + .end = OMAP_CS0_PHYS + SZ_32M - 1, + .flags = IORESOURCE_MEM, +}; + +static struct platform_device sx1_flash_device = { + .name = "omapflash", + .id = 0, + .dev = { + .platform_data = &sx1_flash_data, + }, + .num_resources = 1, + .resource = &sx1_new_flash_resource, +}; +#endif + +/*----------- USB -------------------------*/ + +static struct omap_usb_config sx1_usb_config __initdata = { + .otg = 0, + .register_dev = 1, + .register_host = 0, + .hmc_mode = 0, + .pins[0] = 2, + .pins[1] = 0, + .pins[2] = 0, +}; + +/*----------- MMC -------------------------*/ + +static struct omap_mmc_config sx1_mmc_config __initdata = { + .mmc [0] = { + .enabled = 1, + .wire4 = 0, + .wp_pin = -1, + .power_pin = -1, /* power is in Sofia */ + .switch_pin = OMAP_MPUIO(3), + }, +}; + +/*----------- LCD -------------------------*/ + +static struct platform_device sx1_lcd_device = { + .name = "lcd_sx1", + .id = -1, +}; + +static struct omap_lcd_config sx1_lcd_config __initdata = { + .ctrl_name = "internal", +}; + +/*-----------------------------------------*/ +static struct platform_device *sx1_devices[] __initdata = { + &sx1_flash_device, + &sx1_kp_device, + &sx1_lcd_device, + &sx1_mcbsp1_device, + &sx1_irda_device, +}; +/*-----------------------------------------*/ + +static struct omap_uart_config sx1_uart_config __initdata = { + .enabled_uarts = ((1 << 0) | (1 << 1) | (1 << 2)), +}; + +static struct omap_board_config_kernel sx1_config[] = { + { OMAP_TAG_USB, &sx1_usb_config }, + { OMAP_TAG_MMC, &sx1_mmc_config }, + { OMAP_TAG_LCD, &sx1_lcd_config }, + { OMAP_TAG_UART, &sx1_uart_config }, +}; +/*-----------------------------------------*/ +static void __init omap_sx1_init(void) +{ + platform_add_devices(sx1_devices, ARRAY_SIZE(sx1_devices)); + + omap_board_config = sx1_config; + omap_board_config_size = ARRAY_SIZE(sx1_config); + omap_serial_init(); + + /* turn on USB power */ + /* sx1_setusbpower(1); cant do it here because i2c is not ready */ + omap_request_gpio(1); /* A_IRDA_OFF */ + omap_request_gpio(11); /* A_SWITCH */ + omap_request_gpio(15); /* A_USB_ON */ + omap_set_gpio_direction(1, 0);/* gpio1 -> output */ + omap_set_gpio_direction(11, 0);/* gpio11 -> output */ + omap_set_gpio_direction(15, 0);/* gpio15 -> output */ + /* set GPIO data */ + omap_set_gpio_dataout(1, 1);/*A_IRDA_OFF = 1 */ + omap_set_gpio_dataout(11, 0);/*A_SWITCH = 0 */ + omap_set_gpio_dataout(15, 0);/*A_USB_ON = 0 */ + +} +/*----------------------------------------*/ +static void __init omap_sx1_init_irq(void) +{ + omap1_init_common_hw(); + omap_init_irq(); + omap_gpio_init(); +} +/*----------------------------------------*/ + +static void __init omap_sx1_map_io(void) +{ + omap1_map_common_io(); +} + +MACHINE_START(SX1, "OMAP310 based Siemens SX1") + .phys_io = 0xfff00000, + .io_pg_offst = ((0xfef00000) >> 18) & 0xfffc, + .boot_params = 0x10000100, + .map_io = omap_sx1_map_io, + .init_irq = omap_sx1_init_irq, + .init_machine = omap_sx1_init, + .timer = &omap_timer, +MACHINE_END diff --git a/include/asm-arm/arch-omap/board-sx1.h b/include/asm-arm/arch-omap/board-sx1.h new file mode 100644 index 0000000..2bb8dd6 --- /dev/null +++ b/include/asm-arm/arch-omap/board-sx1.h @@ -0,0 +1,46 @@ +/* + * Siemens SX1 board definitions + * + * Copyright: Vovan888 at gmail com + * + * This package is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + */ + +#ifndef __ASM_ARCH_SX1_I2C_CHIPS_H +#define __ASM_ARCH_SX1_I2C_CHIPS_H + +#define SOFIA_MAX_LIGHT_VAL 0x2B + +#define SOFIA_I2C_ADDR 0x32 +/* Sofia reg 3 bits masks */ +#define SOFIA_POWER1_REG 0x03 + +#define SOFIA_USB_POWER 0x01 +#define SOFIA_MMC_POWER 0x04 +#define SOFIA_BLUETOOTH_POWER 0x08 +#define SOFIA_MMILIGHT_POWER 0x20 + +#define SOFIA_POWER2_REG 0x04 +#define SOFIA_BACKLIGHT_REG 0x06 +#define SOFIA_KEYLIGHT_REG 0x07 +#define SOFIA_DIMMING_REG 0x09 + + +/* Function Prototypes for SX1 devices control on I2C bus */ + +int sx1_setbacklight(u8 backlight); +int sx1_getbacklight(u8 *backlight); +int sx1_setkeylight(u8 keylight); +int sx1_getkeylight(u8 *keylight); + +int sx1_setmmipower(u8 onoff); +int sx1_setusbpower(u8 onoff); +int sx1_setmmcpower(u8 onoff); + +#endif /* __ASM_ARCH_SX1_I2C_CHIPS_H */ diff --git a/include/asm-arm/arch-omap/hardware.h b/include/asm-arm/arch-omap/hardware.h index 18c52d7..85e5b5f 100644 --- a/include/asm-arm/arch-omap/hardware.h +++ b/include/asm-arm/arch-omap/hardware.h @@ -342,6 +342,10 @@ #include "board-palmtt.h" #endif +#ifdef CONFIG_MACH_SX1 +#include "board-sx1.h" +#endif + #endif /* !__ASSEMBLER__ */ #endif /* __ASM_ARCH_OMAP_HARDWARE_H */ -- cgit v0.10.2 From a524626b113e36fc70cb456449444018e3045d5f Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Thu, 7 Dec 2006 13:58:17 -0800 Subject: ARM: OMAP: Sync board specific files with linux-omap This patch syncs omap board specific files with linux-omap tree. Patch consists mostly of driver updates done in linux-omap tree for drivers not yet in mainline kernel. Signed-off-by: Tony Lindgren diff --git a/arch/arm/mach-omap1/board-ams-delta.c b/arch/arm/mach-omap1/board-ams-delta.c index fa2da74..c73ca61 100644 --- a/arch/arm/mach-omap1/board-ams-delta.c +++ b/arch/arm/mach-omap1/board-ams-delta.c @@ -34,20 +34,20 @@ static u8 ams_delta_latch1_reg; static u16 ams_delta_latch2_reg; static int ams_delta_keymap[] = { - KEY(0, 0, KEY_F1), /* Advert */ + KEY(0, 0, KEY_F1), /* Advert */ - KEY(3, 0, KEY_COFFEE), /* Games */ + KEY(3, 0, KEY_COFFEE), /* Games */ KEY(2, 0, KEY_QUESTION), /* Directory */ - KEY(3, 2, KEY_CONNECT), /* Internet */ - KEY(2, 1, KEY_SHOP), /* Services */ - KEY(1, 1, KEY_PHONE), /* VoiceMail */ + KEY(3, 2, KEY_CONNECT), /* Internet */ + KEY(2, 1, KEY_SHOP), /* Services */ + KEY(1, 1, KEY_PHONE), /* VoiceMail */ - KEY(1, 0, KEY_DELETE), /* Delete */ - KEY(2, 2, KEY_PLAY), /* Play */ - KEY(0, 1, KEY_PAGEUP), /* Up */ - KEY(3, 1, KEY_PAGEDOWN), /* Down */ - KEY(0, 2, KEY_EMAIL), /* ReadEmail */ - KEY(1, 2, KEY_STOP), /* Stop */ + KEY(1, 0, KEY_DELETE), /* Delete */ + KEY(2, 2, KEY_PLAY), /* Play */ + KEY(0, 1, KEY_PAGEUP), /* Up */ + KEY(3, 1, KEY_PAGEDOWN), /* Down */ + KEY(0, 2, KEY_EMAIL), /* ReadEmail */ + KEY(1, 2, KEY_STOP), /* Stop */ /* Numeric keypad portion */ KEY(7, 0, KEY_KP1), @@ -61,20 +61,20 @@ static int ams_delta_keymap[] = { KEY(5, 2, KEY_KP9), KEY(6, 3, KEY_KP0), KEY(7, 3, KEY_KPASTERISK), - KEY(5, 3, KEY_KPDOT), /* # key */ - KEY(2, 7, KEY_NUMLOCK), /* Mute */ - KEY(1, 7, KEY_KPMINUS), /* Recall */ - KEY(1, 6, KEY_KPPLUS), /* Redial */ - KEY(6, 7, KEY_KPSLASH), /* Handsfree */ - KEY(0, 6, KEY_ENTER), /* Video */ + KEY(5, 3, KEY_KPDOT), /* # key */ + KEY(2, 7, KEY_NUMLOCK), /* Mute */ + KEY(1, 7, KEY_KPMINUS), /* Recall */ + KEY(1, 6, KEY_KPPLUS), /* Redial */ + KEY(6, 7, KEY_KPSLASH), /* Handsfree */ + KEY(0, 6, KEY_ENTER), /* Video */ - KEY(4, 7, KEY_CAMERA), /* Photo */ + KEY(4, 7, KEY_CAMERA), /* Photo */ - KEY(4, 0, KEY_F2), /* Home */ - KEY(4, 1, KEY_F3), /* Office */ - KEY(4, 2, KEY_F4), /* Mobile */ - KEY(7, 7, KEY_F5), /* SMS */ - KEY(5, 7, KEY_F6), /* Email */ + KEY(4, 0, KEY_F2), /* Home */ + KEY(4, 1, KEY_F3), /* Office */ + KEY(4, 2, KEY_F4), /* Mobile */ + KEY(7, 7, KEY_F5), /* SMS */ + KEY(5, 7, KEY_F6), /* Email */ /* QWERTY portion of keypad */ KEY(4, 3, KEY_Q), @@ -107,7 +107,7 @@ static int ams_delta_keymap[] = { KEY(3, 6, KEY_M), KEY(2, 6, KEY_SPACE), - KEY(0, 7, KEY_LEFTSHIFT), /* Vol up */ + KEY(0, 7, KEY_LEFTSHIFT), /* Vol up */ KEY(3, 7, KEY_LEFTCTRL), /* Vol down */ 0 @@ -158,6 +158,10 @@ static struct map_desc ams_delta_io_desc[] __initdata = { } }; +static struct omap_lcd_config ams_delta_lcd_config __initdata = { + .ctrl_name = "internal", +}; + static struct omap_uart_config ams_delta_uart_config __initdata = { .enabled_uarts = 1, }; @@ -169,6 +173,7 @@ static struct omap_usb_config ams_delta_usb_config __initdata = { }; static struct omap_board_config_kernel ams_delta_config[] = { + { OMAP_TAG_LCD, &ams_delta_lcd_config }, { OMAP_TAG_UART, &ams_delta_uart_config }, { OMAP_TAG_USB, &ams_delta_usb_config }, }; @@ -199,6 +204,11 @@ static struct platform_device ams_delta_kp_device = { .resource = ams_delta_kp_resources, }; +static struct platform_device ams_delta_lcd_device = { + .name = "lcd_ams_delta", + .id = -1, +}; + static struct platform_device ams_delta_led_device = { .name = "ams-delta-led", .id = -1 @@ -206,6 +216,7 @@ static struct platform_device ams_delta_led_device = { static struct platform_device *ams_delta_devices[] __initdata = { &ams_delta_kp_device, + &ams_delta_lcd_device, &ams_delta_led_device, }; diff --git a/arch/arm/mach-omap1/board-h2.c b/arch/arm/mach-omap1/board-h2.c index 48c8c91..d901dcb 100644 --- a/arch/arm/mach-omap1/board-h2.c +++ b/arch/arm/mach-omap1/board-h2.c @@ -139,6 +139,66 @@ static struct platform_device h2_nor_device = { .resource = &h2_nor_resource, }; +#if 0 /* REVISIT: Enable when nand_platform_data is applied */ + +static struct mtd_partition h2_nand_partitions[] = { +#if 0 + /* REVISIT: enable these partitions if you make NAND BOOT + * work on your H2 (rev C or newer); published versions of + * x-load only support P2 and H3. + */ + { + .name = "xloader", + .offset = 0, + .size = 64 * 1024, + .mask_flags = MTD_WRITEABLE, /* force read-only */ + }, + { + .name = "bootloader", + .offset = MTDPART_OFS_APPEND, + .size = 256 * 1024, + .mask_flags = MTD_WRITEABLE, /* force read-only */ + }, + { + .name = "params", + .offset = MTDPART_OFS_APPEND, + .size = 192 * 1024, + }, + { + .name = "kernel", + .offset = MTDPART_OFS_APPEND, + .size = 2 * SZ_1M, + }, +#endif + { + .name = "filesystem", + .size = MTDPART_SIZ_FULL, + .offset = MTDPART_OFS_APPEND, + }, +}; + +/* dip switches control NAND chip access: 8 bit, 16 bit, or neither */ +static struct nand_platform_data h2_nand_data = { + .options = NAND_SAMSUNG_LP_OPTIONS, + .parts = h2_nand_partitions, + .nr_parts = ARRAY_SIZE(h2_nand_partitions), +}; + +static struct resource h2_nand_resource = { + .flags = IORESOURCE_MEM, +}; + +static struct platform_device h2_nand_device = { + .name = "omapnand", + .id = 0, + .dev = { + .platform_data = &h2_nand_data, + }, + .num_resources = 1, + .resource = &h2_nand_resource, +}; +#endif + static struct resource h2_smc91x_resources[] = { [0] = { .start = OMAP1610_ETHR_START, /* Physical */ @@ -218,11 +278,15 @@ static struct resource h2_irda_resources[] = { .flags = IORESOURCE_IRQ, }, }; + +static u64 irda_dmamask = 0xffffffff; + static struct platform_device h2_irda_device = { .name = "omapirda", .id = 0, .dev = { .platform_data = &h2_irda_data, + .dma_mask = &irda_dmamask, }, .num_resources = ARRAY_SIZE(h2_irda_resources), .resource = h2_irda_resources, @@ -270,6 +334,7 @@ static struct platform_device h2_mcbsp1_device = { static struct platform_device *h2_devices[] __initdata = { &h2_nor_device, + //&h2_nand_device, &h2_smc91x_device, &h2_irda_device, &h2_kp_device, @@ -333,6 +398,13 @@ static struct omap_board_config_kernel h2_config[] __initdata = { { OMAP_TAG_LCD, &h2_lcd_config }, }; +#define H2_NAND_RB_GPIO_PIN 62 + +static int h2_nand_dev_ready(struct nand_platform_data *data) +{ + return omap_get_gpio_datain(H2_NAND_RB_GPIO_PIN); +} + static void __init h2_init(void) { /* Here we assume the NOR boot config: NOR on CS3 (possibly swapped @@ -347,6 +419,13 @@ static void __init h2_init(void) h2_nor_resource.end = h2_nor_resource.start = omap_cs3_phys(); h2_nor_resource.end += SZ_32M - 1; +#if 0 /* REVISIT: Enable when nand_platform_data is applied */ + h2_nand_resource.end = h2_nand_resource.start = OMAP_CS2B_PHYS; + h2_nand_resource.end += SZ_4K - 1; + if (!(omap_request_gpio(H2_NAND_RB_GPIO_PIN))) + h2_nand_data.dev_ready = h2_nand_dev_ready; +#endif + omap_cfg_reg(L3_1610_FLASH_CS2B_OE); omap_cfg_reg(M8_1610_FLASH_CS2B_WE); diff --git a/arch/arm/mach-omap1/board-h3.c b/arch/arm/mach-omap1/board-h3.c index 79d4ef4..4167f34 100644 --- a/arch/arm/mach-omap1/board-h3.c +++ b/arch/arm/mach-omap1/board-h3.c @@ -44,6 +44,8 @@ #include #include #include +#include +#include extern int omap_gpio_init(void); @@ -351,11 +353,14 @@ static struct resource h3_irda_resources[] = { }, }; +static u64 irda_dmamask = 0xffffffff; + static struct platform_device h3_irda_device = { .name = "omapirda", .id = 0, .dev = { .platform_data = &h3_irda_data, + .dma_mask = &irda_dmamask, }, .num_resources = ARRAY_SIZE(h3_irda_resources), .resource = h3_irda_resources, @@ -366,6 +371,41 @@ static struct platform_device h3_lcd_device = { .id = -1, }; +static struct omap_mcbsp_reg_cfg mcbsp_regs = { + .spcr2 = FREE | FRST | GRST | XRST | XINTM(3), + .spcr1 = RINTM(3) | RRST, + .rcr2 = RPHASE | RFRLEN2(OMAP_MCBSP_WORD_8) | + RWDLEN2(OMAP_MCBSP_WORD_16) | RDATDLY(1), + .rcr1 = RFRLEN1(OMAP_MCBSP_WORD_8) | RWDLEN1(OMAP_MCBSP_WORD_16), + .xcr2 = XPHASE | XFRLEN2(OMAP_MCBSP_WORD_8) | + XWDLEN2(OMAP_MCBSP_WORD_16) | XDATDLY(1) | XFIG, + .xcr1 = XFRLEN1(OMAP_MCBSP_WORD_8) | XWDLEN1(OMAP_MCBSP_WORD_16), + .srgr1 = FWID(15), + .srgr2 = GSYNC | CLKSP | FSGM | FPER(31), + + .pcr0 = CLKRM | SCLKME | FSXP | FSRP | CLKXP | CLKRP, + //.pcr0 = CLKXP | CLKRP, /* mcbsp: slave */ +}; + +static struct omap_alsa_codec_config alsa_config = { + .name = "H3 TSC2101", + .mcbsp_regs_alsa = &mcbsp_regs, + .codec_configure_dev = NULL, // tsc2101_configure, + .codec_set_samplerate = NULL, // tsc2101_set_samplerate, + .codec_clock_setup = NULL, // tsc2101_clock_setup, + .codec_clock_on = NULL, // tsc2101_clock_on, + .codec_clock_off = NULL, // tsc2101_clock_off, + .get_default_samplerate = NULL, // tsc2101_get_default_samplerate, +}; + +static struct platform_device h3_mcbsp1_device = { + .name = "omap_alsa_mcbsp", + .id = 1, + .dev = { + .platform_data = &alsa_config, + }, +}; + static struct platform_device *devices[] __initdata = { &nor_device, &nand_device, @@ -374,6 +414,7 @@ static struct platform_device *devices[] __initdata = { &h3_irda_device, &h3_kp_device, &h3_lcd_device, + &h3_mcbsp1_device, }; static struct omap_usb_config h3_usb_config __initdata = { diff --git a/arch/arm/mach-omap1/board-nokia770.c b/arch/arm/mach-omap1/board-nokia770.c index 70014f7..8ea0cef 100644 --- a/arch/arm/mach-omap1/board-nokia770.c +++ b/arch/arm/mach-omap1/board-nokia770.c @@ -34,6 +34,8 @@ #include #include +#include "../plat-omap/dsp/dsp_common.h" + static void __init omap_nokia770_init_irq(void) { /* On Nokia 770, the SleepX signal is masked with an @@ -91,7 +93,7 @@ static struct platform_device nokia770_kp_device = { }; static struct platform_device *nokia770_devices[] __initdata = { - &nokia770_kp_device, + &nokia770_kp_device, }; static struct ads7846_platform_data nokia770_ads7846_platform_data __initdata = { @@ -105,7 +107,7 @@ static struct ads7846_platform_data nokia770_ads7846_platform_data __initdata = static struct spi_board_info nokia770_spi_board_info[] __initdata = { [0] = { - .modalias = "lcd_mipid", + .modalias = "lcd_mipid", .bus_num = 2, .chip_select = 3, .max_speed_hz = 12000000, @@ -153,6 +155,7 @@ static struct omap_board_config_kernel nokia770_config[] = { { OMAP_TAG_MMC, &nokia770_mmc_config }, }; +#if defined(CONFIG_OMAP_DSP) /* * audio power control */ @@ -183,7 +186,7 @@ static void nokia770_audio_pwr_up(void) clk_enable(dspxor_ck); /* Turn on codec */ - tlv320aic23_power_up(); + aic23_power_up(); if (omap_get_gpio_datain(HEADPHONE_GPIO)) /* HP not connected, turn on amplifier */ @@ -197,7 +200,7 @@ static void codec_delayed_power_down(struct work_struct *work) { down(&audio_pwr_sem); if (audio_pwr_state == -1) - tlv320aic23_power_down(); + aic23_power_down(); clk_disable(dspxor_ck); up(&audio_pwr_sem); } @@ -213,7 +216,8 @@ static void nokia770_audio_pwr_down(void) schedule_delayed_work(&codec_power_down_work, HZ / 20); /* 50ms */ } -void nokia770_audio_pwr_up_request(int stage) +static int +nokia770_audio_pwr_up_request(struct dsp_kfunc_device *kdev, int stage) { down(&audio_pwr_sem); if (audio_pwr_state == -1) @@ -221,9 +225,11 @@ void nokia770_audio_pwr_up_request(int stage) /* force audio_pwr_state = 0, even if it was 1. */ audio_pwr_state = 0; up(&audio_pwr_sem); + return 0; } -void nokia770_audio_pwr_down_request(int stage) +static int +nokia770_audio_pwr_down_request(struct dsp_kfunc_device *kdev, int stage) { down(&audio_pwr_sem); switch (stage) { @@ -239,7 +245,38 @@ void nokia770_audio_pwr_down_request(int stage) break; } up(&audio_pwr_sem); + return 0; +} + +static struct dsp_kfunc_device nokia770_audio_device = { + .name = "audio", + .type = DSP_KFUNC_DEV_TYPE_AUDIO, + .enable = nokia770_audio_pwr_up_request, + .disable = nokia770_audio_pwr_down_request, +}; + +static __init int omap_dsp_init(void) +{ + int ret; + + dspxor_ck = clk_get(0, "dspxor_ck"); + if (IS_ERR(dspxor_ck)) { + printk(KERN_ERR "couldn't acquire dspxor_ck\n"); + return PTR_ERR(dspxor_ck); + } + + ret = dsp_kfunc_device_register(&nokia770_audio_device); + if (ret) { + printk(KERN_ERR + "KFUNC device registration faild: %s\n", + nokia770_audio_device.name); + goto out; + } + return 0; + out: + return ret; } +#endif /* CONFIG_OMAP_DSP */ static void __init omap_nokia770_init(void) { @@ -251,9 +288,7 @@ static void __init omap_nokia770_init(void) omap_board_config = nokia770_config; omap_board_config_size = ARRAY_SIZE(nokia770_config); omap_serial_init(); - omap_dsp_audio_pwr_up_request = nokia770_audio_pwr_up_request; - omap_dsp_audio_pwr_down_request = nokia770_audio_pwr_down_request; - dspxor_ck = clk_get(0, "dspxor_ck"); + omap_dsp_init(); } static void __init omap_nokia770_map_io(void) diff --git a/arch/arm/mach-omap1/board-osk.c b/arch/arm/mach-omap1/board-osk.c index 2bfa088..83f6e09 100644 --- a/arch/arm/mach-omap1/board-osk.c +++ b/arch/arm/mach-omap1/board-osk.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/mach-omap1/board-palmte.c b/arch/arm/mach-omap1/board-palmte.c index 9af031a..2f9d00a 100644 --- a/arch/arm/mach-omap1/board-palmte.c +++ b/arch/arm/mach-omap1/board-palmte.c @@ -321,116 +321,6 @@ static struct tsc2102_config palmte_tsc2102_config = { .alsa_config = &palmte_alsa_config, }; -static struct omap_mcbsp_reg_cfg palmte_mcbsp1_regs = { - .spcr2 = FRST | GRST | XRST | XINTM(3), - .xcr2 = XDATDLY(1) | XFIG, - .xcr1 = XWDLEN1(OMAP_MCBSP_WORD_32), - .pcr0 = SCLKME | FSXP | CLKXP, -}; - -static struct omap_alsa_codec_config palmte_alsa_config = { - .name = "TSC2102 audio", - .mcbsp_regs_alsa = &palmte_mcbsp1_regs, - .codec_configure_dev = NULL, /* tsc2102_configure, */ - .codec_set_samplerate = NULL, /* tsc2102_set_samplerate, */ - .codec_clock_setup = NULL, /* tsc2102_clock_setup, */ - .codec_clock_on = NULL, /* tsc2102_clock_on, */ - .codec_clock_off = NULL, /* tsc2102_clock_off, */ - .get_default_samplerate = NULL, /* tsc2102_get_default_samplerate, */ -}; - -#ifdef CONFIG_APM -/* - * Values measured in 10 minute intervals averaged over 10 samples. - * May differ slightly from device to device but should be accurate - * enough to give basic idea of battery life left and trigger - * potential alerts. - */ -static const int palmte_battery_sample[] = { - 2194, 2157, 2138, 2120, - 2104, 2089, 2075, 2061, - 2048, 2038, 2026, 2016, - 2008, 1998, 1989, 1980, - 1970, 1958, 1945, 1928, - 1910, 1888, 1860, 1827, - 1791, 1751, 1709, 1656, -}; - -#define INTERVAL 10 -#define BATTERY_HIGH_TRESHOLD 66 -#define BATTERY_LOW_TRESHOLD 33 - -static void palmte_get_power_status(struct apm_power_info *info, int *battery) -{ - int charging, batt, hi, lo, mid; - - charging = !omap_get_gpio_datain(PALMTE_DC_GPIO); - batt = battery[0]; - if (charging) - batt -= 60; - - hi = ARRAY_SIZE(palmte_battery_sample); - lo = 0; - - info->battery_flag = 0; - info->units = APM_UNITS_MINS; - - if (batt > palmte_battery_sample[lo]) { - info->battery_life = 100; - info->time = INTERVAL * ARRAY_SIZE(palmte_battery_sample); - } else if (batt <= palmte_battery_sample[hi - 1]) { - info->battery_life = 0; - info->time = 0; - } else { - while (hi > lo + 1) { - mid = (hi + lo) >> 2; - if (batt <= palmte_battery_sample[mid]) - lo = mid; - else - hi = mid; - } - - mid = palmte_battery_sample[lo] - palmte_battery_sample[hi]; - hi = palmte_battery_sample[lo] - batt; - info->battery_life = 100 - (100 * lo + 100 * hi / mid) / - ARRAY_SIZE(palmte_battery_sample); - info->time = INTERVAL * (ARRAY_SIZE(palmte_battery_sample) - - lo) - INTERVAL * hi / mid; - } - - if (charging) { - info->ac_line_status = APM_AC_ONLINE; - info->battery_status = APM_BATTERY_STATUS_CHARGING; - info->battery_flag |= APM_BATTERY_FLAG_CHARGING; - } else { - info->ac_line_status = APM_AC_OFFLINE; - if (info->battery_life > BATTERY_HIGH_TRESHOLD) - info->battery_status = APM_BATTERY_STATUS_HIGH; - else if (info->battery_life > BATTERY_LOW_TRESHOLD) - info->battery_status = APM_BATTERY_STATUS_LOW; - else - info->battery_status = APM_BATTERY_STATUS_CRITICAL; - } - - if (info->battery_life > BATTERY_HIGH_TRESHOLD) - info->battery_flag |= APM_BATTERY_FLAG_HIGH; - else if (info->battery_life > BATTERY_LOW_TRESHOLD) - info->battery_flag |= APM_BATTERY_FLAG_LOW; - else - info->battery_flag |= APM_BATTERY_FLAG_CRITICAL; -} -#else -#define palmte_get_power_status NULL -#endif - -static struct tsc2102_config palmte_tsc2102_config = { - .use_internal = 0, - .monitor = TSC_BAT1 | TSC_AUX | TSC_TEMP, - .temp_at25c = { 2200, 2615 }, - .apm_report = palmte_get_power_status, - .alsa_config = &palmte_alsa_config, -}; - static struct omap_board_config_kernel palmte_config[] = { { OMAP_TAG_USB, &palmte_usb_config }, { OMAP_TAG_MMC, &palmte_mmc_config }, @@ -449,17 +339,6 @@ static struct spi_board_info palmte_spi_info[] __initdata = { }, }; -static struct spi_board_info palmte_spi_info[] __initdata = { - { - .modalias = "tsc2102", - .bus_num = 2, /* uWire (officially) */ - .chip_select = 0, /* As opposed to 3 */ - .irq = OMAP_GPIO_IRQ(PALMTE_PINTDAV_GPIO), - .platform_data = &palmte_tsc2102_config, - .max_speed_hz = 8000000, - }, -}; - /* Periodically check for changes on important input pins */ struct timer_list palmte_pin_timer; int prev_power, prev_headphones; @@ -539,8 +418,6 @@ static void __init omap_palmte_init(void) spi_register_board_info(palmte_spi_info, ARRAY_SIZE(palmte_spi_info)); - spi_register_board_info(palmte_spi_info, ARRAY_SIZE(palmte_spi_info)); - omap_serial_init(); palmte_gpio_setup(); } diff --git a/arch/arm/mach-omap1/board-palmtt.c b/arch/arm/mach-omap1/board-palmtt.c index 3c9a41a..e47010f 100644 --- a/arch/arm/mach-omap1/board-palmtt.c +++ b/arch/arm/mach-omap1/board-palmtt.c @@ -314,8 +314,8 @@ static struct omap_uart_config palmtt_uart_config __initdata = { }; static struct omap_board_config_kernel palmtt_config[] = { - { OMAP_TAG_USB, &palmtt_usb_config }, - { OMAP_TAG_LCD, &palmtt_lcd_config }, + { OMAP_TAG_USB, &palmtt_usb_config }, + { OMAP_TAG_LCD, &palmtt_lcd_config }, { OMAP_TAG_UART, &palmtt_uart_config }, }; diff --git a/arch/arm/mach-omap1/board-voiceblue.c b/arch/arm/mach-omap1/board-voiceblue.c index 447a586..214dd19 100644 --- a/arch/arm/mach-omap1/board-voiceblue.c +++ b/arch/arm/mach-omap1/board-voiceblue.c @@ -235,7 +235,7 @@ static struct notifier_block panic_block = { static int __init voiceblue_setup(void) { /* Setup panic notifier */ - notifier_chain_register(&panic_notifier_list, &panic_block); + atomic_notifier_chain_register(&panic_notifier_list, &panic_block); return 0; } -- cgit v0.10.2 From b250428461130c32c5dde00fd5037ef6fa276004 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Thu, 7 Dec 2006 16:22:18 -0800 Subject: ARM: OMAP: Update omap h2 defconfig Update omap h2 defconfig Signed-off-by: Tony Lindgren diff --git a/arch/arm/configs/omap_h2_1610_defconfig b/arch/arm/configs/omap_h2_1610_defconfig index b0efd4c..b8a78ab 100644 --- a/arch/arm/configs/omap_h2_1610_defconfig +++ b/arch/arm/configs/omap_h2_1610_defconfig @@ -1,41 +1,58 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.17 -# Thu Jun 29 15:25:18 2006 +# Linux kernel version: 2.6.23-rc6 +# Mon Sep 17 14:21:45 2007 # CONFIG_ARM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_GENERIC_GPIO=y +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CLOCKEVENTS=y CONFIG_MMU=y +# CONFIG_NO_IOPORT is not set +CONFIG_GENERIC_HARDIRQS=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_ZONE_DMA=y CONFIG_VECTORS_BASE=0xffff0000 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" # -# Code maturity level options +# General setup # CONFIG_EXPERIMENTAL=y CONFIG_BROKEN_ON_SMP=y CONFIG_LOCK_KERNEL=y CONFIG_INIT_ENV_ARG_LIMIT=32 - -# -# General setup -# CONFIG_LOCALVERSION="" CONFIG_LOCALVERSION_AUTO=y CONFIG_SWAP=y CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y # CONFIG_POSIX_MQUEUE is not set # CONFIG_BSD_PROCESS_ACCT is not set -CONFIG_SYSCTL=y +# CONFIG_TASKSTATS is not set +# CONFIG_USER_NS is not set # CONFIG_AUDIT is not set # CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_SYSFS_DEPRECATED is not set # CONFIG_RELAY is not set +CONFIG_BLK_DEV_INITRD=y CONFIG_INITRAMFS_SOURCE="" -CONFIG_UID16=y CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y # CONFIG_EMBEDDED is not set +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_EXTRA_PASS is not set CONFIG_HOTPLUG=y @@ -44,27 +61,30 @@ CONFIG_BUG=y CONFIG_ELF_CORE=y CONFIG_BASE_FULL=y CONFIG_FUTEX=y +CONFIG_ANON_INODES=y CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y CONFIG_SHMEM=y +CONFIG_VM_EVENT_COUNTERS=y CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_SLOB is not set +CONFIG_RT_MUTEXES=y # CONFIG_TINY_SHMEM is not set CONFIG_BASE_SMALL=0 -# CONFIG_SLOB is not set - -# -# Loadable module support -# CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y # CONFIG_MODULE_FORCE_UNLOAD is not set # CONFIG_MODVERSIONS is not set # CONFIG_MODULE_SRCVERSION_ALL is not set # CONFIG_KMOD is not set - -# -# Block layer -# +CONFIG_BLOCK=y +# CONFIG_LBD is not set # CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_LSF is not set +# CONFIG_BLK_DEV_BSG is not set # # IO Schedulers @@ -86,7 +106,7 @@ CONFIG_DEFAULT_IOSCHED="anticipatory" # CONFIG_ARCH_INTEGRATOR is not set # CONFIG_ARCH_REALVIEW is not set # CONFIG_ARCH_VERSATILE is not set -# CONFIG_ARCH_AT91RM9200 is not set +# CONFIG_ARCH_AT91 is not set # CONFIG_ARCH_CLPS7500 is not set # CONFIG_ARCH_CLPS711X is not set # CONFIG_ARCH_CO285 is not set @@ -96,11 +116,16 @@ CONFIG_DEFAULT_IOSCHED="anticipatory" # CONFIG_ARCH_NETX is not set # CONFIG_ARCH_H720X is not set # CONFIG_ARCH_IMX is not set -# CONFIG_ARCH_IOP3XX is not set -# CONFIG_ARCH_IXP4XX is not set -# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set # CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set # CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_MXC is not set # CONFIG_ARCH_PNX4008 is not set # CONFIG_ARCH_PXA is not set # CONFIG_ARCH_RPC is not set @@ -108,6 +133,7 @@ CONFIG_DEFAULT_IOSCHED="anticipatory" # CONFIG_ARCH_S3C2410 is not set # CONFIG_ARCH_SHARK is not set # CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_DAVINCI is not set CONFIG_ARCH_OMAP=y # @@ -124,6 +150,7 @@ CONFIG_ARCH_OMAP1=y CONFIG_OMAP_MUX=y # CONFIG_OMAP_MUX_DEBUG is not set CONFIG_OMAP_MUX_WARNINGS=y +CONFIG_OMAP_MCBSP=y # CONFIG_OMAP_MPU_TIMER is not set CONFIG_OMAP_32K_TIMER=y CONFIG_OMAP_32K_TIMER_HZ=128 @@ -162,6 +189,14 @@ CONFIG_OMAP_ARM_192MHZ=y # CONFIG_OMAP_ARM_30MHZ is not set # +# Boot options +# + +# +# Power management +# + +# # Processor Type # CONFIG_CPU_32=y @@ -171,6 +206,8 @@ CONFIG_CPU_ABRT_EV5TJ=y CONFIG_CPU_CACHE_VIVT=y CONFIG_CPU_COPY_V4WB=y CONFIG_CPU_TLB_V4WBI=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y # # Processor Features @@ -180,10 +217,13 @@ CONFIG_ARM_THUMB=y # CONFIG_CPU_DCACHE_DISABLE is not set # CONFIG_CPU_DCACHE_WRITETHROUGH is not set # CONFIG_CPU_CACHE_ROUND_ROBIN is not set +# CONFIG_OUTER_CACHE is not set # # Bus support # +# CONFIG_PCI_SYSCALL is not set +# CONFIG_ARCH_SUPPORTS_MSI is not set # # PCCARD (PCMCIA/CardBus) support @@ -193,10 +233,13 @@ CONFIG_ARM_THUMB=y # # Kernel Features # +CONFIG_TICK_ONESHOT=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y CONFIG_PREEMPT=y -CONFIG_NO_IDLE_HZ=y CONFIG_HZ=128 -# CONFIG_AEABI is not set +CONFIG_AEABI=y +CONFIG_OABI_COMPAT=y # CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set CONFIG_SELECT_MEMORY_MODEL=y CONFIG_FLATMEM_MANUAL=y @@ -206,6 +249,10 @@ CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y # CONFIG_SPARSEMEM_STATIC is not set CONFIG_SPLIT_PTLOCK_CPUS=4096 +# CONFIG_RESOURCES_64BIT is not set +CONFIG_ZONE_DMA_FLAG=1 +CONFIG_BOUNCE=y +CONFIG_VIRT_TO_BUS=y # CONFIG_LEDS is not set CONFIG_ALIGNMENT_TRAP=y @@ -216,6 +263,7 @@ CONFIG_ZBOOT_ROM_TEXT=0x0 CONFIG_ZBOOT_ROM_BSS=0x0 CONFIG_CMDLINE="mem=32M console=ttyS0,115200n8 root=0801 ro init=/bin/sh" # CONFIG_XIP_KERNEL is not set +# CONFIG_KEXEC is not set # # CPU Frequency scaling @@ -251,7 +299,6 @@ CONFIG_FPE_NWFPE=y CONFIG_BINFMT_ELF=y CONFIG_BINFMT_AOUT=y # CONFIG_BINFMT_MISC is not set -# CONFIG_ARTHUR is not set # # Power management options @@ -259,7 +306,10 @@ CONFIG_BINFMT_AOUT=y CONFIG_PM=y # CONFIG_PM_LEGACY is not set # CONFIG_PM_DEBUG is not set -# CONFIG_APM is not set +CONFIG_PM_SLEEP=y +CONFIG_SUSPEND_UP_POSSIBLE=y +CONFIG_SUSPEND=y +# CONFIG_APM_EMULATION is not set # # Networking @@ -269,12 +319,13 @@ CONFIG_NET=y # # Networking options # -# CONFIG_NETDEBUG is not set CONFIG_PACKET=y # CONFIG_PACKET_MMAP is not set CONFIG_UNIX=y CONFIG_XFRM=y # CONFIG_XFRM_USER is not set +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set # CONFIG_NET_KEY is not set CONFIG_INET=y # CONFIG_IP_MULTICAST is not set @@ -295,29 +346,20 @@ CONFIG_IP_PNP_BOOTP=y # CONFIG_INET_TUNNEL is not set CONFIG_INET_XFRM_MODE_TRANSPORT=y CONFIG_INET_XFRM_MODE_TUNNEL=y +CONFIG_INET_XFRM_MODE_BEET=y CONFIG_INET_DIAG=y CONFIG_INET_TCP_DIAG=y # CONFIG_TCP_CONG_ADVANCED is not set -CONFIG_TCP_CONG_BIC=y +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set # CONFIG_IPV6 is not set # CONFIG_INET6_XFRM_TUNNEL is not set # CONFIG_INET6_TUNNEL is not set # CONFIG_NETWORK_SECMARK is not set # CONFIG_NETFILTER is not set - -# -# DCCP Configuration (EXPERIMENTAL) -# # CONFIG_IP_DCCP is not set - -# -# SCTP Configuration (EXPERIMENTAL) -# # CONFIG_IP_SCTP is not set - -# -# TIPC Configuration (EXPERIMENTAL) -# # CONFIG_TIPC is not set # CONFIG_ATM is not set # CONFIG_BRIDGE is not set @@ -328,7 +370,6 @@ CONFIG_TCP_CONG_BIC=y # CONFIG_ATALK is not set # CONFIG_X25 is not set # CONFIG_LAPB is not set -# CONFIG_NET_DIVERT is not set # CONFIG_ECONET is not set # CONFIG_WAN_ROUTER is not set @@ -344,7 +385,17 @@ CONFIG_TCP_CONG_BIC=y # CONFIG_HAMRADIO is not set # CONFIG_IRDA is not set # CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set + +# +# Wireless +# +# CONFIG_CFG80211 is not set +# CONFIG_WIRELESS_EXT is not set +# CONFIG_MAC80211 is not set # CONFIG_IEEE80211 is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set # # Device Drivers @@ -357,29 +408,10 @@ CONFIG_STANDALONE=y CONFIG_PREVENT_FIRMWARE_BUILD=y # CONFIG_FW_LOADER is not set # CONFIG_SYS_HYPERVISOR is not set - -# -# Connector - unified userspace <-> kernelspace linker -# # CONFIG_CONNECTOR is not set - -# -# Memory Technology Devices (MTD) -# # CONFIG_MTD is not set - -# -# Parallel port support -# # CONFIG_PARPORT is not set - -# -# Plug and Play support -# - -# -# Block devices -# +CONFIG_BLK_DEV=y # CONFIG_BLK_DEV_COW_COMMON is not set CONFIG_BLK_DEV_LOOP=y # CONFIG_BLK_DEV_CRYPTOLOOP is not set @@ -387,7 +419,7 @@ CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_COUNT=16 CONFIG_BLK_DEV_RAM_SIZE=8192 -CONFIG_BLK_DEV_INITRD=y +CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024 # CONFIG_CDROM_PKTCDVD is not set CONFIG_ATA_OVER_ETH=m @@ -396,6 +428,9 @@ CONFIG_ATA_OVER_ETH=m # # CONFIG_RAID_ATTRS is not set CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_TGT is not set +# CONFIG_SCSI_NETLINK is not set CONFIG_SCSI_PROC_FS=y # @@ -414,82 +449,42 @@ CONFIG_SCSI_PROC_FS=y # CONFIG_SCSI_MULTI_LUN is not set # CONFIG_SCSI_CONSTANTS is not set # CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set +CONFIG_SCSI_WAIT_SCAN=m # -# SCSI Transport Attributes +# SCSI Transports # # CONFIG_SCSI_SPI_ATTRS is not set # CONFIG_SCSI_FC_ATTRS is not set # CONFIG_SCSI_ISCSI_ATTRS is not set -# CONFIG_SCSI_SAS_ATTRS is not set - -# -# SCSI low-level drivers -# +# CONFIG_SCSI_SAS_LIBSAS is not set +CONFIG_SCSI_LOWLEVEL=y # CONFIG_ISCSI_TCP is not set -# CONFIG_SCSI_SATA is not set # CONFIG_SCSI_DEBUG is not set - -# -# Multi-device support (RAID and LVM) -# +# CONFIG_ATA is not set # CONFIG_MD is not set - -# -# Fusion MPT device support -# -# CONFIG_FUSION is not set - -# -# IEEE 1394 (FireWire) support -# - -# -# I2O device support -# - -# -# Network device support -# CONFIG_NETDEVICES=y +# CONFIG_NETDEVICES_MULTIQUEUE is not set # CONFIG_DUMMY is not set # CONFIG_BONDING is not set +# CONFIG_MACVLAN is not set # CONFIG_EQUALIZER is not set # CONFIG_TUN is not set - -# -# PHY device support -# # CONFIG_PHYLIB is not set - -# -# Ethernet (10 or 100Mbit) -# CONFIG_NET_ETHERNET=y CONFIG_MII=y +# CONFIG_AX88796 is not set CONFIG_SMC91X=y # CONFIG_DM9000 is not set +CONFIG_NETDEV_1000=y +CONFIG_NETDEV_10000=y # -# Ethernet (1000 Mbit) -# - -# -# Ethernet (10000 Mbit) -# - -# -# Token Ring devices -# - -# -# Wireless LAN (non-hamradio) -# -# CONFIG_NET_RADIO is not set - -# -# Wan interfaces +# Wireless LAN # +# CONFIG_WLAN_PRE80211 is not set +# CONFIG_WLAN_80211 is not set # CONFIG_WAN is not set CONFIG_PPP=y # CONFIG_PPP_MULTILINK is not set @@ -500,24 +495,24 @@ CONFIG_PPP=y # CONFIG_PPP_BSDCOMP is not set # CONFIG_PPP_MPPE is not set # CONFIG_PPPOE is not set +# CONFIG_PPPOL2TP is not set CONFIG_SLIP=y CONFIG_SLIP_COMPRESSED=y +CONFIG_SLHC=y # CONFIG_SLIP_SMART is not set # CONFIG_SLIP_MODE_SLIP6 is not set # CONFIG_SHAPER is not set # CONFIG_NETCONSOLE is not set # CONFIG_NETPOLL is not set # CONFIG_NET_POLL_CONTROLLER is not set - -# -# ISDN subsystem -# # CONFIG_ISDN is not set # # Input device support # CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set # # Userland interfaces @@ -537,8 +532,14 @@ CONFIG_INPUT_EVBUG=y # CONFIG_INPUT_KEYBOARD is not set # CONFIG_INPUT_MOUSE is not set # CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set # CONFIG_INPUT_TOUCHSCREEN is not set CONFIG_INPUT_MISC=y +# CONFIG_INPUT_ATI_REMOTE is not set +# CONFIG_INPUT_ATI_REMOTE2 is not set +# CONFIG_INPUT_KEYSPAN_REMOTE is not set +# CONFIG_INPUT_POWERMATE is not set +# CONFIG_INPUT_YEALINK is not set CONFIG_INPUT_UINPUT=y # @@ -574,15 +575,7 @@ CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y CONFIG_UNIX98_PTYS=y # CONFIG_LEGACY_PTYS is not set - -# -# IPMI -# # CONFIG_IPMI_HANDLER is not set - -# -# Watchdog Cards -# CONFIG_WATCHDOG=y CONFIG_WATCHDOG_NOWAYOUT=y @@ -590,25 +583,12 @@ CONFIG_WATCHDOG_NOWAYOUT=y # Watchdog Device Drivers # # CONFIG_SOFT_WATCHDOG is not set +# CONFIG_OMAP_WATCHDOG is not set # CONFIG_HW_RANDOM is not set # CONFIG_NVRAM is not set -# CONFIG_DTLK is not set # CONFIG_R3964 is not set - -# -# Ftape, the floppy tape device driver -# # CONFIG_RAW_DRIVER is not set - -# -# TPM devices -# # CONFIG_TCG_TPM is not set -# CONFIG_TELCLOCK is not set - -# -# I2C support -# # CONFIG_I2C is not set # @@ -616,61 +596,70 @@ CONFIG_WATCHDOG_NOWAYOUT=y # # CONFIG_SPI is not set # CONFIG_SPI_MASTER is not set - -# -# Dallas's 1-wire bus -# - -# -# Hardware Monitoring support -# +# CONFIG_W1 is not set CONFIG_HWMON=y # CONFIG_HWMON_VID is not set # CONFIG_SENSORS_ABITUGURU is not set +# CONFIG_SENSORS_ABITUGURU3 is not set # CONFIG_SENSORS_F71805F is not set +# CONFIG_SENSORS_IT87 is not set +# CONFIG_SENSORS_PC87360 is not set +# CONFIG_SENSORS_PC87427 is not set +# CONFIG_SENSORS_SMSC47M1 is not set +# CONFIG_SENSORS_SMSC47B397 is not set +# CONFIG_SENSORS_VT1211 is not set +# CONFIG_SENSORS_W83627HF is not set +# CONFIG_SENSORS_W83627EHF is not set # CONFIG_HWMON_DEBUG_CHIP is not set +CONFIG_MISC_DEVICES=y +# CONFIG_EEPROM_93CX6 is not set # -# Misc devices -# - -# -# LED devices +# Multifunction device drivers # +# CONFIG_MFD_SM501 is not set # CONFIG_NEW_LEDS is not set # -# LED drivers -# - -# -# LED Triggers -# - -# # Multimedia devices # # CONFIG_VIDEO_DEV is not set -CONFIG_VIDEO_V4L2=y +# CONFIG_DVB_CORE is not set +CONFIG_DAB=y # -# Digital Video Broadcasting Devices +# Graphics support # -# CONFIG_DVB is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set # -# Graphics support +# Display device support # -CONFIG_FIRMWARE_EDID=y +# CONFIG_DISPLAY_SUPPORT is not set +# CONFIG_VGASTATE is not set +CONFIG_VIDEO_OUTPUT_CONTROL=m CONFIG_FB=y +CONFIG_FIRMWARE_EDID=y +# CONFIG_FB_DDC is not set # CONFIG_FB_CFB_FILLRECT is not set # CONFIG_FB_CFB_COPYAREA is not set # CONFIG_FB_CFB_IMAGEBLIT is not set +# CONFIG_FB_SYS_FILLRECT is not set +# CONFIG_FB_SYS_COPYAREA is not set +# CONFIG_FB_SYS_IMAGEBLIT is not set +# CONFIG_FB_SYS_FOPS is not set +CONFIG_FB_DEFERRED_IO=y +# CONFIG_FB_SVGALIB is not set # CONFIG_FB_MACMODES is not set # CONFIG_FB_BACKLIGHT is not set CONFIG_FB_MODE_HELPERS=y # CONFIG_FB_TILEBLITTING is not set + +# +# Frame buffer hardware drivers +# # CONFIG_FB_S1D13XXX is not set +# CONFIG_FB_OMAP is not set # CONFIG_FB_VIRTUAL is not set # @@ -679,6 +668,7 @@ CONFIG_FB_MODE_HELPERS=y # CONFIG_VGA_CONSOLE is not set CONFIG_DUMMY_CONSOLE=y CONFIG_FRAMEBUFFER_CONSOLE=y +# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set # CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set CONFIG_FONTS=y CONFIG_FONT_8x8=y @@ -691,15 +681,10 @@ CONFIG_FONT_8x16=y # CONFIG_FONT_SUN8x16 is not set # CONFIG_FONT_SUN12x22 is not set # CONFIG_FONT_10x18 is not set - -# -# Logo configuration -# CONFIG_LOGO=y # CONFIG_LOGO_LINUX_MONO is not set # CONFIG_LOGO_LINUX_VGA16 is not set CONFIG_LOGO_LINUX_CLUT224=y -# CONFIG_BACKLIGHT_LCD_SUPPORT is not set # # Sound @@ -717,10 +702,10 @@ CONFIG_SOUND=y CONFIG_SOUND_PRIME=y # CONFIG_SOUND_MSNDCLAS is not set # CONFIG_SOUND_MSNDPIN is not set - -# -# USB support -# +CONFIG_HID_SUPPORT=y +CONFIG_HID=y +CONFIG_HID_DEBUG=y +CONFIG_USB_SUPPORT=y CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB_ARCH_HAS_OHCI=y # CONFIG_USB_ARCH_HAS_EHCI is not set @@ -734,17 +719,22 @@ CONFIG_USB_ARCH_HAS_OHCI=y # USB Gadget Support # # CONFIG_USB_GADGET is not set +# CONFIG_MMC is not set +CONFIG_RTC_LIB=y +# CONFIG_RTC_CLASS is not set # -# MMC/SD Card support +# DMA Engine support # -# CONFIG_MMC is not set +# CONFIG_DMA_ENGINE is not set # -# Real Time Clock +# DMA Clients +# + +# +# DMA Devices # -CONFIG_RTC_LIB=y -# CONFIG_RTC_CLASS is not set # # File systems @@ -753,10 +743,12 @@ CONFIG_EXT2_FS=y # CONFIG_EXT2_FS_XATTR is not set # CONFIG_EXT2_FS_XIP is not set # CONFIG_EXT3_FS is not set +# CONFIG_EXT4DEV_FS is not set # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set # CONFIG_FS_POSIX_ACL is not set # CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set # CONFIG_OCFS2_FS is not set # CONFIG_MINIX_FS is not set CONFIG_ROMFS_FS=y @@ -787,6 +779,7 @@ CONFIG_FAT_DEFAULT_CODEPAGE=437 # Pseudo filesystems # CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y CONFIG_SYSFS=y # CONFIG_TMPFS is not set # CONFIG_HUGETLB_PAGE is not set @@ -825,6 +818,7 @@ CONFIG_LOCKD_V4=y CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y CONFIG_SUNRPC_GSS=y +# CONFIG_SUNRPC_BIND34 is not set CONFIG_RPCSEC_GSS_KRB5=y # CONFIG_RPCSEC_GSS_SPKM3 is not set # CONFIG_SMB_FS is not set @@ -832,7 +826,6 @@ CONFIG_RPCSEC_GSS_KRB5=y # CONFIG_NCP_FS is not set # CONFIG_CODA_FS is not set # CONFIG_AFS_FS is not set -# CONFIG_9P_FS is not set # # Partition Types @@ -885,6 +878,11 @@ CONFIG_NLS_DEFAULT="iso8859-1" # CONFIG_NLS_UTF8 is not set # +# Distributed Lock Manager +# +# CONFIG_DLM is not set + +# # Profiling support # # CONFIG_PROFILING is not set @@ -893,13 +891,14 @@ CONFIG_NLS_DEFAULT="iso8859-1" # Kernel hacking # # CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_MUST_CHECK=y # CONFIG_MAGIC_SYSRQ is not set +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set # CONFIG_DEBUG_KERNEL is not set -CONFIG_LOG_BUF_SHIFT=14 CONFIG_DEBUG_BUGVERBOSE=y -# CONFIG_DEBUG_FS is not set CONFIG_FRAME_POINTER=y -# CONFIG_UNWIND_INFO is not set # CONFIG_DEBUG_USER is not set # @@ -907,12 +906,12 @@ CONFIG_FRAME_POINTER=y # # CONFIG_KEYS is not set # CONFIG_SECURITY is not set - -# -# Cryptographic options -# CONFIG_CRYPTO=y +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_MANAGER=y # CONFIG_CRYPTO_HMAC is not set +# CONFIG_CRYPTO_XCBC is not set # CONFIG_CRYPTO_NULL is not set # CONFIG_CRYPTO_MD4 is not set CONFIG_CRYPTO_MD5=y @@ -921,7 +920,14 @@ CONFIG_CRYPTO_MD5=y # CONFIG_CRYPTO_SHA512 is not set # CONFIG_CRYPTO_WP512 is not set # CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_GF128MUL is not set +CONFIG_CRYPTO_ECB=m +CONFIG_CRYPTO_CBC=y +CONFIG_CRYPTO_PCBC=m +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_CRYPTD is not set CONFIG_CRYPTO_DES=y +# CONFIG_CRYPTO_FCRYPT is not set # CONFIG_CRYPTO_BLOWFISH is not set # CONFIG_CRYPTO_TWOFISH is not set # CONFIG_CRYPTO_SERPENT is not set @@ -935,17 +941,22 @@ CONFIG_CRYPTO_DES=y # CONFIG_CRYPTO_DEFLATE is not set # CONFIG_CRYPTO_MICHAEL_MIC is not set # CONFIG_CRYPTO_CRC32C is not set +# CONFIG_CRYPTO_CAMELLIA is not set # CONFIG_CRYPTO_TEST is not set - -# -# Hardware crypto devices -# +CONFIG_CRYPTO_HW=y # # Library routines # +CONFIG_BITREVERSE=y # CONFIG_CRC_CCITT is not set # CONFIG_CRC16 is not set +# CONFIG_CRC_ITU_T is not set CONFIG_CRC32=y +# CONFIG_CRC7 is not set # CONFIG_LIBCRC32C is not set CONFIG_ZLIB_INFLATE=y +CONFIG_PLIST=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y -- cgit v0.10.2 From e898088e250d9b0cce671490fb29c5fd82880d5e Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Thu, 7 Dec 2006 16:32:55 -0800 Subject: ARM: OMAP: Add omap osk defconfig Add omap osk defconfig Signed-off-by: Tony Lindgren diff --git a/arch/arm/configs/omap_osk_5912_defconfig b/arch/arm/configs/omap_osk_5912_defconfig new file mode 100644 index 0000000..8c1f15c --- /dev/null +++ b/arch/arm/configs/omap_osk_5912_defconfig @@ -0,0 +1,1073 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.23-rc6 +# Mon Sep 17 14:15:05 2007 +# +CONFIG_ARM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_GENERIC_GPIO=y +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_MMU=y +# CONFIG_NO_IOPORT is not set +CONFIG_GENERIC_HARDIRQS=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_ZONE_DMA=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_POSIX_MQUEUE is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_USER_NS is not set +# CONFIG_AUDIT is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_SYSFS_DEPRECATED is not set +# CONFIG_RELAY is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +# CONFIG_EMBEDDED is not set +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_ANON_INODES=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_SLOB is not set +CONFIG_RT_MUTEXES=y +# CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_KMOD=y +CONFIG_BLOCK=y +# CONFIG_LBD is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_LSF is not set +# CONFIG_BLK_DEV_BSG is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +# CONFIG_DEFAULT_AS is not set +# CONFIG_DEFAULT_DEADLINE is not set +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="cfq" + +# +# System Type +# +# CONFIG_ARCH_AAEC2000 is not set +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_CLPS7500 is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_CO285 is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_IMX is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_MXC is not set +# CONFIG_ARCH_PNX4008 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_DAVINCI is not set +CONFIG_ARCH_OMAP=y + +# +# TI OMAP Implementations +# +CONFIG_ARCH_OMAP_OTG=y +CONFIG_ARCH_OMAP1=y +# CONFIG_ARCH_OMAP2 is not set + +# +# OMAP Feature Selections +# +CONFIG_OMAP_RESET_CLOCKS=y +CONFIG_OMAP_MUX=y +# CONFIG_OMAP_MUX_DEBUG is not set +CONFIG_OMAP_MUX_WARNINGS=y +CONFIG_OMAP_MCBSP=y +# CONFIG_OMAP_MPU_TIMER is not set +CONFIG_OMAP_32K_TIMER=y +CONFIG_OMAP_32K_TIMER_HZ=128 +# CONFIG_OMAP_DM_TIMER is not set +CONFIG_OMAP_LL_DEBUG_UART1=y +# CONFIG_OMAP_LL_DEBUG_UART2 is not set +# CONFIG_OMAP_LL_DEBUG_UART3 is not set +CONFIG_OMAP_SERIAL_WAKE=y + +# +# OMAP Core Type +# +# CONFIG_ARCH_OMAP730 is not set +# CONFIG_ARCH_OMAP15XX is not set +CONFIG_ARCH_OMAP16XX=y + +# +# OMAP Board Type +# +# CONFIG_MACH_OMAP_INNOVATOR is not set +# CONFIG_MACH_OMAP_H2 is not set +# CONFIG_MACH_OMAP_H3 is not set +CONFIG_MACH_OMAP_OSK=y +# CONFIG_OMAP_OSK_MISTRAL is not set +# CONFIG_MACH_NOKIA770 is not set +# CONFIG_MACH_OMAP_GENERIC is not set + +# +# OMAP CPU Speed +# +# CONFIG_OMAP_CLOCKS_SET_BY_BOOTLOADER is not set +# CONFIG_OMAP_ARM_216MHZ is not set +CONFIG_OMAP_ARM_192MHZ=y +# CONFIG_OMAP_ARM_168MHZ is not set +# CONFIG_OMAP_ARM_120MHZ is not set +# CONFIG_OMAP_ARM_60MHZ is not set +# CONFIG_OMAP_ARM_30MHZ is not set + +# +# Boot options +# + +# +# Power management +# + +# +# Processor Type +# +CONFIG_CPU_32=y +CONFIG_CPU_ARM926T=y +CONFIG_CPU_32v5=y +CONFIG_CPU_ABRT_EV5TJ=y +CONFIG_CPU_CACHE_VIVT=y +CONFIG_CPU_COPY_V4WB=y +CONFIG_CPU_TLB_V4WBI=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +# CONFIG_ARM_THUMB is not set +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_WRITETHROUGH is not set +# CONFIG_CPU_CACHE_ROUND_ROBIN is not set +# CONFIG_OUTER_CACHE is not set + +# +# Bus support +# +# CONFIG_PCI_SYSCALL is not set +# CONFIG_ARCH_SUPPORTS_MSI is not set + +# +# PCCARD (PCMCIA/CardBus) support +# +CONFIG_PCCARD=y +# CONFIG_PCMCIA_DEBUG is not set +CONFIG_PCMCIA=y +CONFIG_PCMCIA_LOAD_CIS=y +CONFIG_PCMCIA_IOCTL=y + +# +# PC-card bridges +# +CONFIG_OMAP_CF=y + +# +# Kernel Features +# +CONFIG_TICK_ONESHOT=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +# CONFIG_PREEMPT is not set +CONFIG_HZ=128 +CONFIG_AEABI=y +CONFIG_OABI_COMPAT=y +# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_SPARSEMEM_STATIC is not set +CONFIG_SPLIT_PTLOCK_CPUS=4096 +# CONFIG_RESOURCES_64BIT is not set +CONFIG_ZONE_DMA_FLAG=1 +CONFIG_BOUNCE=y +CONFIG_VIRT_TO_BUS=y +# CONFIG_LEDS is not set +CONFIG_ALIGNMENT_TRAP=y + +# +# Boot options +# +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_CMDLINE="mem=32M console=ttyS0,115200 initrd=0x10400000,8M root=/dev/ram0 rw" +# CONFIG_XIP_KERNEL is not set +# CONFIG_KEXEC is not set + +# +# CPU Frequency scaling +# +# CONFIG_CPU_FREQ is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +CONFIG_FPE_NWFPE=y +# CONFIG_FPE_NWFPE_XP is not set +# CONFIG_FPE_FASTFPE is not set +# CONFIG_VFP is not set + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_BINFMT_AOUT is not set +# CONFIG_BINFMT_MISC is not set + +# +# Power management options +# +CONFIG_PM=y +# CONFIG_PM_LEGACY is not set +# CONFIG_PM_DEBUG is not set +CONFIG_PM_SLEEP=y +CONFIG_SUSPEND_UP_POSSIBLE=y +CONFIG_SUSPEND=y +# CONFIG_APM_EMULATION is not set + +# +# Networking +# +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=m +# CONFIG_PACKET_MMAP is not set +CONFIG_UNIX=y +CONFIG_XFRM=y +# CONFIG_XFRM_USER is not set +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_NET_KEY is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_IP_MROUTE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +# CONFIG_INET_TUNNEL is not set +CONFIG_INET_XFRM_MODE_TRANSPORT=y +CONFIG_INET_XFRM_MODE_TUNNEL=y +CONFIG_INET_XFRM_MODE_BEET=y +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +# CONFIG_IPV6 is not set +# CONFIG_INET6_XFRM_TUNNEL is not set +# CONFIG_INET6_TUNNEL is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set + +# +# QoS and/or fair queueing +# +# CONFIG_NET_SCHED is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set + +# +# Wireless +# +# CONFIG_CFG80211 is not set +# CONFIG_WIRELESS_EXT is not set +# CONFIG_MAC80211 is not set +# CONFIG_IEEE80211 is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_CONNECTOR is not set +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_CONCAT is not set +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_REDBOOT_PARTS is not set +CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_AFS_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set + +# +# RAM/ROM/Flash chip drivers +# +CONFIG_MTD_CFI=y +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_GEN_PROBE=y +# CONFIG_MTD_CFI_ADV_OPTIONS is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +CONFIG_MTD_CFI_INTELEXT=y +# CONFIG_MTD_CFI_AMDSTD is not set +# CONFIG_MTD_CFI_STAA is not set +CONFIG_MTD_CFI_UTIL=y +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_PHYSMAP is not set +# CONFIG_MTD_ARM_INTEGRATOR is not set +CONFIG_MTD_OMAP_NOR=y +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +# CONFIG_MTD_NAND is not set +# CONFIG_MTD_ONENAND is not set + +# +# UBI - Unsorted block images +# +# CONFIG_MTD_UBI is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=y +# CONFIG_BLK_DEV_CRYPTOLOOP is not set +# CONFIG_BLK_DEV_NBD is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=8192 +CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024 +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +CONFIG_IDE=m +CONFIG_BLK_DEV_IDE=m + +# +# Please see Documentation/ide.txt for help/info on IDE drives +# +# CONFIG_BLK_DEV_IDE_SATA is not set +CONFIG_BLK_DEV_IDEDISK=m +# CONFIG_IDEDISK_MULTI_MODE is not set +CONFIG_BLK_DEV_IDECS=m +# CONFIG_BLK_DEV_IDECD is not set +# CONFIG_BLK_DEV_IDETAPE is not set +# CONFIG_BLK_DEV_IDEFLOPPY is not set +# CONFIG_IDE_TASK_IOCTL is not set +CONFIG_IDE_PROC_FS=y + +# +# IDE chipset support/bugfixes +# +# CONFIG_IDE_GENERIC is not set +# CONFIG_IDEPCI_PCIBUS_ORDER is not set +# CONFIG_IDE_ARM is not set +# CONFIG_BLK_DEV_IDEDMA is not set +# CONFIG_BLK_DEV_HD is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +# CONFIG_SCSI is not set +# CONFIG_SCSI_DMA is not set +# CONFIG_SCSI_NETLINK is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set +CONFIG_NETDEVICES=y +# CONFIG_NETDEVICES_MULTIQUEUE is not set +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_MACVLAN is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_PHYLIB is not set +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +# CONFIG_AX88796 is not set +CONFIG_SMC91X=y +# CONFIG_DM9000 is not set +CONFIG_NETDEV_1000=y +CONFIG_NETDEV_10000=y + +# +# Wireless LAN +# +# CONFIG_WLAN_PRE80211 is not set +# CONFIG_WLAN_80211 is not set +# CONFIG_NET_PCMCIA is not set +# CONFIG_WAN is not set +CONFIG_PPP=y +CONFIG_PPP_MULTILINK=y +# CONFIG_PPP_FILTER is not set +# CONFIG_PPP_ASYNC is not set +# CONFIG_PPP_SYNC_TTY is not set +# CONFIG_PPP_DEFLATE is not set +# CONFIG_PPP_BSDCOMP is not set +# CONFIG_PPP_MPPE is not set +# CONFIG_PPPOE is not set +# CONFIG_PPPOL2TP is not set +# CONFIG_SLIP is not set +CONFIG_SLHC=y +# CONFIG_SHAPER is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_ISDN is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_TSDEV is not set +CONFIG_INPUT_EVDEV=y +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +# CONFIG_KEYBOARD_ATKBD is not set +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_LKKBD is not set +# CONFIG_KEYBOARD_XTKBD is not set +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +CONFIG_KEYBOARD_OMAP=y +# CONFIG_KEYBOARD_GPIO is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +CONFIG_INPUT_TOUCHSCREEN=y +# CONFIG_TOUCHSCREEN_FUJITSU is not set +# CONFIG_TOUCHSCREEN_GUNZE is not set +# CONFIG_TOUCHSCREEN_ELO is not set +# CONFIG_TOUCHSCREEN_MTOUCH is not set +# CONFIG_TOUCHSCREEN_MK712 is not set +# CONFIG_TOUCHSCREEN_PENMOUNT is not set +# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set +# CONFIG_TOUCHSCREEN_TOUCHWIN is not set +# CONFIG_TOUCHSCREEN_UCB1400 is not set +# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +# CONFIG_SERIAL_8250_CS is not set +CONFIG_SERIAL_8250_NR_UARTS=4 +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +# CONFIG_SERIAL_8250_EXTENDED is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_UNIX98_PTYS=y +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=256 +# CONFIG_IPMI_HANDLER is not set +# CONFIG_WATCHDOG is not set +CONFIG_HW_RANDOM=m +CONFIG_HW_RANDOM_OMAP=m +# CONFIG_NVRAM is not set +# CONFIG_R3964 is not set + +# +# PCMCIA character devices +# +# CONFIG_SYNCLINK_CS is not set +# CONFIG_CARDMAN_4000 is not set +# CONFIG_CARDMAN_4040 is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_CHARDEV=y + +# +# I2C Algorithms +# +# CONFIG_I2C_ALGOBIT is not set +# CONFIG_I2C_ALGOPCF is not set +# CONFIG_I2C_ALGOPCA is not set + +# +# I2C Hardware Bus support +# +# CONFIG_I2C_GPIO is not set +# CONFIG_I2C_OCORES is not set +CONFIG_I2C_OMAP=y +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_SIMTEC is not set +# CONFIG_I2C_TAOS_EVM is not set +# CONFIG_I2C_STUB is not set + +# +# Miscellaneous I2C Chip support +# +# CONFIG_SENSORS_DS1337 is not set +# CONFIG_SENSORS_DS1374 is not set +# CONFIG_DS1682 is not set +# CONFIG_SENSORS_EEPROM is not set +# CONFIG_SENSORS_PCF8574 is not set +# CONFIG_SENSORS_PCA9539 is not set +# CONFIG_SENSORS_PCF8591 is not set +# CONFIG_ISP1301_OMAP is not set +CONFIG_TPS65010=y +# CONFIG_SENSORS_MAX6875 is not set +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +# CONFIG_I2C_DEBUG_CHIP is not set + +# +# SPI support +# +# CONFIG_SPI is not set +# CONFIG_SPI_MASTER is not set +# CONFIG_W1 is not set +CONFIG_HWMON=y +# CONFIG_HWMON_VID is not set +# CONFIG_SENSORS_ABITUGURU is not set +# CONFIG_SENSORS_ABITUGURU3 is not set +# CONFIG_SENSORS_AD7418 is not set +# CONFIG_SENSORS_ADM1021 is not set +# CONFIG_SENSORS_ADM1025 is not set +# CONFIG_SENSORS_ADM1026 is not set +# CONFIG_SENSORS_ADM1029 is not set +# CONFIG_SENSORS_ADM1031 is not set +# CONFIG_SENSORS_ADM9240 is not set +# CONFIG_SENSORS_ASB100 is not set +# CONFIG_SENSORS_ATXP1 is not set +# CONFIG_SENSORS_DS1621 is not set +# CONFIG_SENSORS_F71805F is not set +# CONFIG_SENSORS_FSCHER is not set +# CONFIG_SENSORS_FSCPOS is not set +# CONFIG_SENSORS_GL518SM is not set +# CONFIG_SENSORS_GL520SM is not set +# CONFIG_SENSORS_IT87 is not set +# CONFIG_SENSORS_LM63 is not set +# CONFIG_SENSORS_LM75 is not set +# CONFIG_SENSORS_LM77 is not set +# CONFIG_SENSORS_LM78 is not set +# CONFIG_SENSORS_LM80 is not set +# CONFIG_SENSORS_LM83 is not set +# CONFIG_SENSORS_LM85 is not set +# CONFIG_SENSORS_LM87 is not set +# CONFIG_SENSORS_LM90 is not set +# CONFIG_SENSORS_LM92 is not set +# CONFIG_SENSORS_LM93 is not set +# CONFIG_SENSORS_MAX1619 is not set +# CONFIG_SENSORS_MAX6650 is not set +# CONFIG_SENSORS_PC87360 is not set +# CONFIG_SENSORS_PC87427 is not set +# CONFIG_SENSORS_DME1737 is not set +# CONFIG_SENSORS_SMSC47M1 is not set +# CONFIG_SENSORS_SMSC47M192 is not set +# CONFIG_SENSORS_SMSC47B397 is not set +# CONFIG_SENSORS_THMC50 is not set +# CONFIG_SENSORS_VT1211 is not set +# CONFIG_SENSORS_W83781D is not set +# CONFIG_SENSORS_W83791D is not set +# CONFIG_SENSORS_W83792D is not set +# CONFIG_SENSORS_W83793 is not set +# CONFIG_SENSORS_W83L785TS is not set +# CONFIG_SENSORS_W83627HF is not set +# CONFIG_SENSORS_W83627EHF is not set +# CONFIG_HWMON_DEBUG_CHIP is not set +CONFIG_MISC_DEVICES=y +# CONFIG_EEPROM_93CX6 is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_SM501 is not set +# CONFIG_NEW_LEDS is not set + +# +# Multimedia devices +# +# CONFIG_VIDEO_DEV is not set +# CONFIG_DVB_CORE is not set +CONFIG_DAB=y + +# +# Graphics support +# +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set +# CONFIG_VGASTATE is not set +CONFIG_VIDEO_OUTPUT_CONTROL=m +CONFIG_FB=y +CONFIG_FIRMWARE_EDID=y +# CONFIG_FB_DDC is not set +# CONFIG_FB_CFB_FILLRECT is not set +# CONFIG_FB_CFB_COPYAREA is not set +# CONFIG_FB_CFB_IMAGEBLIT is not set +# CONFIG_FB_SYS_FILLRECT is not set +# CONFIG_FB_SYS_COPYAREA is not set +# CONFIG_FB_SYS_IMAGEBLIT is not set +# CONFIG_FB_SYS_FOPS is not set +CONFIG_FB_DEFERRED_IO=y +# CONFIG_FB_SVGALIB is not set +# CONFIG_FB_MACMODES is not set +# CONFIG_FB_BACKLIGHT is not set +CONFIG_FB_MODE_HELPERS=y +# CONFIG_FB_TILEBLITTING is not set + +# +# Frame buffer hardware drivers +# +# CONFIG_FB_S1D13XXX is not set +# CONFIG_FB_OMAP is not set +# CONFIG_FB_VIRTUAL is not set + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE=y +# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set +# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set +CONFIG_FONTS=y +CONFIG_FONT_8x8=y +# CONFIG_FONT_8x16 is not set +# CONFIG_FONT_6x11 is not set +# CONFIG_FONT_7x14 is not set +# CONFIG_FONT_PEARL_8x8 is not set +# CONFIG_FONT_ACORN_8x8 is not set +# CONFIG_FONT_MINI_4x6 is not set +# CONFIG_FONT_SUN8x16 is not set +# CONFIG_FONT_SUN12x22 is not set +# CONFIG_FONT_10x18 is not set +CONFIG_LOGO=y +# CONFIG_LOGO_LINUX_MONO is not set +# CONFIG_LOGO_LINUX_VGA16 is not set +CONFIG_LOGO_LINUX_CLUT224=y + +# +# Sound +# +# CONFIG_SOUND is not set +CONFIG_HID_SUPPORT=y +CONFIG_HID=y +CONFIG_HID_DEBUG=y +CONFIG_USB_SUPPORT=y +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB_ARCH_HAS_OHCI=y +# CONFIG_USB_ARCH_HAS_EHCI is not set +# CONFIG_USB is not set + +# +# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' +# + +# +# USB Gadget Support +# +# CONFIG_USB_GADGET is not set +# CONFIG_MMC is not set +CONFIG_RTC_LIB=y +# CONFIG_RTC_CLASS is not set + +# +# DMA Engine support +# +# CONFIG_DMA_ENGINE is not set + +# +# DMA Clients +# + +# +# DMA Devices +# + +# +# File systems +# +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set +# CONFIG_EXT3_FS is not set +# CONFIG_EXT4DEV_FS is not set +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +# CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_ROMFS_FS is not set +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +CONFIG_DNOTIFY=y +CONFIG_AUTOFS_FS=y +CONFIG_AUTOFS4_FS=y +# CONFIG_FUSE_FS is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=m +CONFIG_MSDOS_FS=m +CONFIG_VFAT_FS=m +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_SYSFS=y +# CONFIG_TMPFS is not set +# CONFIG_HUGETLB_PAGE is not set +CONFIG_RAMFS=y +# CONFIG_CONFIGFS_FS is not set + +# +# Miscellaneous filesystems +# +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +CONFIG_JFFS2_FS_WRITEBUFFER=y +# CONFIG_JFFS2_SUMMARY is not set +# CONFIG_JFFS2_FS_XATTR is not set +# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set +CONFIG_JFFS2_ZLIB=y +CONFIG_JFFS2_RTIME=y +# CONFIG_JFFS2_RUBIN is not set +# CONFIG_CRAMFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set + +# +# Network File Systems +# +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +# CONFIG_NFS_V4 is not set +# CONFIG_NFS_DIRECTIO is not set +# CONFIG_NFSD is not set +CONFIG_ROOT_NFS=y +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +# CONFIG_SUNRPC_BIND34 is not set +# CONFIG_RPCSEC_GSS_KRB5 is not set +# CONFIG_RPCSEC_GSS_SPKM3 is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y + +# +# Native Language Support +# +CONFIG_NLS=m +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=m +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ASCII is not set +CONFIG_NLS_ISO8859_1=m +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_UTF8 is not set + +# +# Distributed Lock Manager +# +# CONFIG_DLM is not set + +# +# Profiling support +# +# CONFIG_PROFILING is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_MUST_CHECK=y +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_KERNEL is not set +CONFIG_DEBUG_BUGVERBOSE=y +CONFIG_FRAME_POINTER=y +# CONFIG_DEBUG_USER is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set +# CONFIG_CRYPTO is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +# CONFIG_CRC_CCITT is not set +# CONFIG_CRC16 is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_PLIST=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y -- cgit v0.10.2 From 4dcc6d242ea576aaead9b5fe4b79cf941294855b Mon Sep 17 00:00:00 2001 From: David Brownell Date: Thu, 25 Jan 2007 16:24:01 -0800 Subject: ARM: OMAP: osk+mistral backlight, power, board specific Mistral-specific: - Add PWL-driven LCD backlight device - Apply power to the board even when the LCD isn't configured; things like EEPROM, temperature sensor, and wakeup switch depend on it. Signed-off-by: David Brownell Signed-off-by: Tony Lindgren diff --git a/arch/arm/mach-omap1/board-osk.c b/arch/arm/mach-omap1/board-osk.c index 83f6e09..1825781 100644 --- a/arch/arm/mach-omap1/board-osk.c +++ b/arch/arm/mach-omap1/board-osk.c @@ -293,6 +293,18 @@ static struct platform_device osk5912_kp_device = { .resource = osk5912_kp_resources, }; +static struct omap_backlight_config mistral_bl_data = { + .default_intensity = 0xa0, +}; + +static struct platform_device mistral_bl_device = { + .name = "omap-bl", + .id = -1, + .dev = { + .platform_data = &mistral_bl_data, + }, +}; + static struct platform_device osk5912_lcd_device = { .name = "lcd_osk", .id = -1, @@ -300,6 +312,7 @@ static struct platform_device osk5912_lcd_device = { static struct platform_device *mistral_devices[] __initdata = { &osk5912_kp_device, + &mistral_bl_device, &osk5912_lcd_device, }; @@ -405,6 +418,15 @@ static void __init osk_mistral_init(void) } else printk(KERN_ERR "OSK+Mistral: wakeup button is awol\n"); + /* LCD: backlight, and power; power controls other devices on the + * board, like the touchscreen, EEPROM, and wakeup (!) switch. + */ + omap_cfg_reg(PWL); + if (omap_request_gpio(2) == 0) { + omap_set_gpio_direction(2, 0 /* out */); + omap_set_gpio_dataout(2, 1 /* on */); + } + platform_add_devices(mistral_devices, ARRAY_SIZE(mistral_devices)); } #else -- cgit v0.10.2 From 06767fb2ba5af5542e2ec91e00e292ff93ab58ce Mon Sep 17 00:00:00 2001 From: Imre Deak Date: Tue, 6 Mar 2007 18:20:00 +0200 Subject: ARM: OMAP: N770: add missing LCD, LCD controller, touchscreen device registration These were left out from the board file when merging these drivers, add them here. Call GPIO init from the board file as well, since the platform device init code uses the GPIO API. Signed-off-by: Imre Deak Signed-off-by: Tony Lindgren Removed hwa742 init for now as it needs some clock updates. Signed-off-by: Tony Lindgren diff --git a/arch/arm/mach-omap1/board-nokia770.c b/arch/arm/mach-omap1/board-nokia770.c index 8ea0cef..22db19a 100644 --- a/arch/arm/mach-omap1/board-nokia770.c +++ b/arch/arm/mach-omap1/board-nokia770.c @@ -33,9 +33,13 @@ #include #include #include +#include +#include #include "../plat-omap/dsp/dsp_common.h" +#define ADS7846_PENDOWN_GPIO 15 + static void __init omap_nokia770_init_irq(void) { /* On Nokia 770, the SleepX signal is masked with an @@ -96,6 +100,41 @@ static struct platform_device *nokia770_devices[] __initdata = { &nokia770_kp_device, }; +static void mipid_shutdown(struct mipid_platform_data *pdata) +{ + if (pdata->nreset_gpio != -1) { + printk(KERN_INFO "shutdown LCD\n"); + omap_set_gpio_dataout(pdata->nreset_gpio, 0); + msleep(120); + } +} + +static struct mipid_platform_data nokia770_mipid_platform_data = { + .shutdown = mipid_shutdown, +}; + +static void mipid_dev_init(void) +{ + const struct omap_lcd_config *conf; + + conf = omap_get_config(OMAP_TAG_LCD, struct omap_lcd_config); + if (conf != NULL) { + nokia770_mipid_platform_data.nreset_gpio = conf->nreset_gpio; + nokia770_mipid_platform_data.data_lines = conf->data_lines; + } +} + +static void ads7846_dev_init(void) +{ + if (omap_request_gpio(ADS7846_PENDOWN_GPIO) < 0) + printk(KERN_ERR "can't get ads7846 pen down GPIO\n"); +} + +static int ads7846_get_pendown_state(void) +{ + return !omap_get_gpio_datain(ADS7846_PENDOWN_GPIO); +} + static struct ads7846_platform_data nokia770_ads7846_platform_data __initdata = { .x_max = 0x0fff, .y_max = 0x0fff, @@ -103,6 +142,8 @@ static struct ads7846_platform_data nokia770_ads7846_platform_data __initdata = .pressure_max = 255, .debounce_max = 10, .debounce_tol = 3, + .debounce_rep = 1, + .get_pendown_state = ads7846_get_pendown_state, }; static struct spi_board_info nokia770_spi_board_info[] __initdata = { @@ -111,6 +152,7 @@ static struct spi_board_info nokia770_spi_board_info[] __initdata = { .bus_num = 2, .chip_select = 3, .max_speed_hz = 12000000, + .platform_data = &nokia770_mipid_platform_data, }, [1] = { .modalias = "ads7846", @@ -287,8 +329,11 @@ static void __init omap_nokia770_init(void) ARRAY_SIZE(nokia770_spi_board_info)); omap_board_config = nokia770_config; omap_board_config_size = ARRAY_SIZE(nokia770_config); + omap_gpio_init(); omap_serial_init(); omap_dsp_init(); + ads7846_dev_init(); + mipid_dev_init(); } static void __init omap_nokia770_map_io(void) -- cgit v0.10.2 From 6c3a158316598bfb165b8c83b168fa413d5ae2d8 Mon Sep 17 00:00:00 2001 From: Nicolas Pitre Date: Fri, 17 Aug 2007 16:55:22 +0100 Subject: [ARM] 4550/1: sched_clock on PXA should cope with run time clock rate selection The previous implementation was relying on compile time optimizations based on a constant clock rate. However, support for different PXA flavors in the same kernel binary requires that the clock be selected at run time, so here it is. Let's move this code to a more appropriate location while at it. Signed-off-by: Nicolas Pitre Signed-off-by: Russell King diff --git a/arch/arm/mach-pxa/generic.c b/arch/arm/mach-pxa/generic.c index 5510f6f..9d6a2c0 100644 --- a/arch/arm/mach-pxa/generic.c +++ b/arch/arm/mach-pxa/generic.c @@ -25,10 +25,6 @@ #include #include -#include -#include -#include - #include #include #include @@ -47,64 +43,6 @@ #include "generic.h" /* - * This is the PXA2xx sched_clock implementation. This has a resolution - * of at least 308ns and a maximum value that depends on the value of - * CLOCK_TICK_RATE. - * - * The return value is guaranteed to be monotonic in that range as - * long as there is always less than 582 seconds between successive - * calls to this function. - */ -unsigned long long sched_clock(void) -{ - unsigned long long v = cnt32_to_63(OSCR); - /* Note: top bit ov v needs cleared unless multiplier is even. */ - -#if CLOCK_TICK_RATE == 3686400 - /* 1E9 / 3686400 => 78125 / 288, max value = 32025597s (370 days). */ - /* The <<1 is used to get rid of tick.hi top bit */ - v *= 78125<<1; - do_div(v, 288<<1); -#elif CLOCK_TICK_RATE == 3250000 - /* 1E9 / 3250000 => 4000 / 13, max value = 709490156s (8211 days) */ - v *= 4000; - do_div(v, 13); -#elif CLOCK_TICK_RATE == 3249600 - /* 1E9 / 3249600 => 625000 / 2031, max value = 4541295s (52 days) */ - v *= 625000; - do_div(v, 2031); -#else -#warning "consider fixing sched_clock for your value of CLOCK_TICK_RATE" - /* - * 96-bit math to perform tick * NSEC_PER_SEC / CLOCK_TICK_RATE for - * any value of CLOCK_TICK_RATE. Max value is in the 80 thousand - * years range and truncation to unsigned long long limits it to - * sched_clock's max range of ~584 years. This is nice but with - * higher computation cost. - */ - { - union { - unsigned long long val; - struct { unsigned long lo, hi; }; - } x; - unsigned long long y; - - x.val = v; - x.hi &= 0x7fffffff; - y = (unsigned long long)x.lo * NSEC_PER_SEC; - x.lo = y; - y = (y >> 32) + (unsigned long long)x.hi * NSEC_PER_SEC; - x.hi = do_div(y, CLOCK_TICK_RATE); - do_div(x.val, CLOCK_TICK_RATE); - x.hi += y; - v = x.val; - } -#endif - - return v; -} - -/* * Handy function to set GPIO alternate functions */ diff --git a/arch/arm/mach-pxa/time.c b/arch/arm/mach-pxa/time.c index 98d27e6..7916311 100644 --- a/arch/arm/mach-pxa/time.c +++ b/arch/arm/mach-pxa/time.c @@ -16,11 +16,48 @@ #include #include #include +#include +#include +#include #include #include #include +/* + * This is PXA's sched_clock implementation. This has a resolution + * of at least 308 ns and a maximum value of 208 days. + * + * The return value is guaranteed to be monotonic in that range as + * long as there is always less than 582 seconds between successive + * calls to sched_clock() which should always be the case in practice. + */ + +#define OSCR2NS_SCALE_FACTOR 10 + +static unsigned long oscr2ns_scale; + +static void __init set_oscr2ns_scale(unsigned long oscr_rate) +{ + unsigned long long v = 1000000000ULL << OSCR2NS_SCALE_FACTOR; + do_div(v, oscr_rate); + oscr2ns_scale = v; + /* + * We want an even value to automatically clear the top bit + * returned by cnt32_to_63() without an additional run time + * instruction. So if the LSB is 1 then round it up. + */ + if (oscr2ns_scale & 1) + oscr2ns_scale++; +} + +unsigned long long sched_clock(void) +{ + unsigned long long v = cnt32_to_63(OSCR); + return (v * oscr2ns_scale) >> OSCR2NS_SCALE_FACTOR; +} + + static irqreturn_t pxa_ost0_interrupt(int irq, void *dev_id) { @@ -152,6 +189,8 @@ static void __init pxa_timer_init(void) OIER = 0; OSSR = OSSR_M0 | OSSR_M1 | OSSR_M2 | OSSR_M3; + set_oscr2ns_scale(CLOCK_TICK_RATE); + ckevt_pxa_osmr0.mult = div_sc(CLOCK_TICK_RATE, NSEC_PER_SEC, ckevt_pxa_osmr0.shift); ckevt_pxa_osmr0.max_delta_ns = -- cgit v0.10.2 From 08197f6e3b262f4fb8b164c818d5e54b46c14711 Mon Sep 17 00:00:00 2001 From: Russell King Date: Sat, 1 Sep 2007 21:12:50 +0100 Subject: [ARM] pxa: make pxa timer initialisation select clock rate at runtime Rather than using the compile-time constant CLOCK_TICK_RATE, select the clock tick rate at run time. We organise the selection so that PXA3 automatically falls out with the right tick rate. Signed-off-by: Russell King diff --git a/arch/arm/mach-pxa/time.c b/arch/arm/mach-pxa/time.c index 7916311..ec4286c 100644 --- a/arch/arm/mach-pxa/time.c +++ b/arch/arm/mach-pxa/time.c @@ -23,6 +23,7 @@ #include #include #include +#include /* * This is PXA's sched_clock implementation. This has a resolution @@ -186,20 +187,29 @@ static struct irqaction pxa_ost0_irq = { static void __init pxa_timer_init(void) { + unsigned long clock_tick_rate; + OIER = 0; OSSR = OSSR_M0 | OSSR_M1 | OSSR_M2 | OSSR_M3; - set_oscr2ns_scale(CLOCK_TICK_RATE); + if (cpu_is_pxa21x() || cpu_is_pxa25x()) + clock_tick_rate = 3686400; + else if (machine_is_mainstone()) + clock_tick_rate = 3249600; + else + clock_tick_rate = 3250000; + + set_oscr2ns_scale(clock_tick_rate); ckevt_pxa_osmr0.mult = - div_sc(CLOCK_TICK_RATE, NSEC_PER_SEC, ckevt_pxa_osmr0.shift); + div_sc(clock_tick_rate, NSEC_PER_SEC, ckevt_pxa_osmr0.shift); ckevt_pxa_osmr0.max_delta_ns = clockevent_delta2ns(0x7fffffff, &ckevt_pxa_osmr0); ckevt_pxa_osmr0.min_delta_ns = clockevent_delta2ns(MIN_OSCR_DELTA, &ckevt_pxa_osmr0) + 1; cksrc_pxa_oscr0.mult = - clocksource_hz2mult(CLOCK_TICK_RATE, cksrc_pxa_oscr0.shift); + clocksource_hz2mult(clock_tick_rate, cksrc_pxa_oscr0.shift); setup_irq(IRQ_OST0, &pxa_ost0_irq); -- cgit v0.10.2 From e259a3aecbfb61981175ddc7fc02dd180da7d73e Mon Sep 17 00:00:00 2001 From: Russell King Date: Mon, 20 Aug 2007 09:47:41 +0100 Subject: [ARM] pxa: convert PXA serial drivers to use platform resources Signed-off-by: Russell King diff --git a/arch/arm/mach-pxa/generic.c b/arch/arm/mach-pxa/generic.c index 9d6a2c0..98df638 100644 --- a/arch/arm/mach-pxa/generic.c +++ b/arch/arm/mach-pxa/generic.c @@ -267,21 +267,80 @@ void __init set_pxa_fb_parent(struct device *parent_dev) pxa_device_fb.dev.parent = parent_dev; } +static struct resource pxa_resource_ffuart[] = { + { + .start = __PREG(FFUART), + .end = __PREG(FFUART) + 35, + .flags = IORESOURCE_MEM, + }, { + .start = IRQ_FFUART, + .end = IRQ_FFUART, + .flags = IORESOURCE_IRQ, + } +}; + struct platform_device pxa_device_ffuart= { .name = "pxa2xx-uart", .id = 0, + .resource = pxa_resource_ffuart, + .num_resources = ARRAY_SIZE(pxa_resource_ffuart), +}; + +static struct resource pxa_resource_btuart[] = { + { + .start = __PREG(BTUART), + .end = __PREG(BTUART) + 35, + .flags = IORESOURCE_MEM, + }, { + .start = IRQ_BTUART, + .end = IRQ_BTUART, + .flags = IORESOURCE_IRQ, + } }; + struct platform_device pxa_device_btuart = { .name = "pxa2xx-uart", .id = 1, + .resource = pxa_resource_btuart, + .num_resources = ARRAY_SIZE(pxa_resource_btuart), }; + +static struct resource pxa_resource_stuart[] = { + { + .start = __PREG(STUART), + .end = __PREG(STUART) + 35, + .flags = IORESOURCE_MEM, + }, { + .start = IRQ_STUART, + .end = IRQ_STUART, + .flags = IORESOURCE_IRQ, + } +}; + struct platform_device pxa_device_stuart = { .name = "pxa2xx-uart", .id = 2, + .resource = pxa_resource_stuart, + .num_resources = ARRAY_SIZE(pxa_resource_stuart), }; + +static struct resource pxa_resource_hwuart[] = { + { + .start = __PREG(HWUART), + .end = __PREG(HWUART) + 47, + .flags = IORESOURCE_MEM, + }, { + .start = IRQ_HWUART, + .end = IRQ_HWUART, + .flags = IORESOURCE_IRQ, + } +}; + struct platform_device pxa_device_hwuart = { .name = "pxa2xx-uart", .id = 3, + .resource = pxa_resource_hwuart, + .num_resources = ARRAY_SIZE(pxa_resource_hwuart), }; static struct resource pxai2c_resources[] = { diff --git a/drivers/serial/pxa.c b/drivers/serial/pxa.c index e9c6cb3..59889f6 100644 --- a/drivers/serial/pxa.c +++ b/drivers/serial/pxa.c @@ -582,7 +582,7 @@ serial_pxa_type(struct uart_port *port) #ifdef CONFIG_SERIAL_PXA_CONSOLE -static struct uart_pxa_port serial_pxa_ports[]; +static struct uart_pxa_port *serial_pxa_ports[4]; static struct uart_driver serial_pxa_reg; #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE) @@ -632,7 +632,7 @@ static void serial_pxa_console_putchar(struct uart_port *port, int ch) static void serial_pxa_console_write(struct console *co, const char *s, unsigned int count) { - struct uart_pxa_port *up = &serial_pxa_ports[co->index]; + struct uart_pxa_port *up = serial_pxa_ports[co->index]; unsigned int ier; /* @@ -662,7 +662,9 @@ serial_pxa_console_setup(struct console *co, char *options) if (co->index == -1 || co->index >= serial_pxa_reg.nr) co->index = 0; - up = &serial_pxa_ports[co->index]; + up = serial_pxa_ports[co->index]; + if (!up) + return -ENODEV; if (options) uart_parse_options(options, &baud, &parity, &bits, &flow); @@ -680,15 +682,6 @@ static struct console serial_pxa_console = { .data = &serial_pxa_reg, }; -static int __init -serial_pxa_console_init(void) -{ - register_console(&serial_pxa_console); - return 0; -} - -console_initcall(serial_pxa_console_init); - #define PXA_CONSOLE &serial_pxa_console #else #define PXA_CONSOLE NULL @@ -714,73 +707,13 @@ struct uart_ops serial_pxa_pops = { .verify_port = serial_pxa_verify_port, }; -static struct uart_pxa_port serial_pxa_ports[] = { - { /* FFUART */ - .name = "FFUART", - .cken = CKEN_FFUART, - .port = { - .type = PORT_PXA, - .iotype = UPIO_MEM, - .membase = (void *)&FFUART, - .mapbase = __PREG(FFUART), - .irq = IRQ_FFUART, - .uartclk = 921600 * 16, - .fifosize = 64, - .ops = &serial_pxa_pops, - .line = 0, - }, - }, { /* BTUART */ - .name = "BTUART", - .cken = CKEN_BTUART, - .port = { - .type = PORT_PXA, - .iotype = UPIO_MEM, - .membase = (void *)&BTUART, - .mapbase = __PREG(BTUART), - .irq = IRQ_BTUART, - .uartclk = 921600 * 16, - .fifosize = 64, - .ops = &serial_pxa_pops, - .line = 1, - }, - }, { /* STUART */ - .name = "STUART", - .cken = CKEN_STUART, - .port = { - .type = PORT_PXA, - .iotype = UPIO_MEM, - .membase = (void *)&STUART, - .mapbase = __PREG(STUART), - .irq = IRQ_STUART, - .uartclk = 921600 * 16, - .fifosize = 64, - .ops = &serial_pxa_pops, - .line = 2, - }, - }, { /* HWUART */ - .name = "HWUART", - .cken = CKEN_HWUART, - .port = { - .type = PORT_PXA, - .iotype = UPIO_MEM, - .membase = (void *)&HWUART, - .mapbase = __PREG(HWUART), - .irq = IRQ_HWUART, - .uartclk = 921600 * 16, - .fifosize = 64, - .ops = &serial_pxa_pops, - .line = 3, - }, - } -}; - static struct uart_driver serial_pxa_reg = { .owner = THIS_MODULE, .driver_name = "PXA serial", .dev_name = "ttyS", .major = TTY_MAJOR, .minor = 64, - .nr = ARRAY_SIZE(serial_pxa_ports), + .nr = 4, .cons = PXA_CONSOLE, }; @@ -806,10 +739,60 @@ static int serial_pxa_resume(struct platform_device *dev) static int serial_pxa_probe(struct platform_device *dev) { - serial_pxa_ports[dev->id].port.dev = &dev->dev; - uart_add_one_port(&serial_pxa_reg, &serial_pxa_ports[dev->id].port); - platform_set_drvdata(dev, &serial_pxa_ports[dev->id]); + struct uart_pxa_port *sport; + struct resource *mmres, *irqres; + int ret; + + mmres = platform_get_resource(dev, IORESOURCE_MEM, 0); + irqres = platform_get_resource(dev, IORESOURCE_IRQ, 0); + if (!mmres || !irqres) + return -ENODEV; + + sport = kzalloc(sizeof(struct uart_pxa_port), GFP_KERNEL); + if (!sport) + return -ENOMEM; + + sport->port.type = PORT_PXA; + sport->port.iotype = UPIO_MEM; + sport->port.mapbase = mmres->start; + sport->port.irq = irqres->start; + sport->port.fifosize = 64; + sport->port.ops = &serial_pxa_pops; + sport->port.line = dev->id; + sport->port.dev = &dev->dev; + sport->port.flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF; + sport->port.uartclk = 921600 * 16; + + /* + * Is it worth keeping this? + */ + if (mmres->start == __PREG(FFUART)) + sport->name = "FFUART"; + else if (mmres->start == __PREG(BTUART)) + sport->name = "BTUART"; + else if (mmres->start == __PREG(STUART)) + sport->name = "STUART"; + else if (mmres->start == __PREG(HWUART)) + sport->name = "HWUART"; + else + sport->name = "???"; + + sport->port.membase = ioremap(mmres->start, mmres->end - mmres->start + 1); + if (!sport->port.membase) { + ret = -ENOMEM; + goto err_free; + } + + serial_pxa_ports[dev->id] = sport; + + uart_add_one_port(&serial_pxa_reg, &sport->port); + platform_set_drvdata(dev, sport); + return 0; + + err_free: + kfree(sport); + return ret; } static int serial_pxa_remove(struct platform_device *dev) @@ -818,8 +801,8 @@ static int serial_pxa_remove(struct platform_device *dev) platform_set_drvdata(dev, NULL); - if (sport) - uart_remove_one_port(&serial_pxa_reg, &sport->port); + uart_remove_one_port(&serial_pxa_reg, &sport->port); + kfree(sport); return 0; } -- cgit v0.10.2 From 15a4033354c68eb75e417ab60771f36212610820 Mon Sep 17 00:00:00 2001 From: Russell King Date: Mon, 20 Aug 2007 10:07:44 +0100 Subject: [ARM] pxa: fix naming of memory/lcd/core clock functions Rename pxa25x and pxa27x memory/lcd/core clock functions, and select the correct version at run time. Signed-off-by: Russell King diff --git a/arch/arm/mach-pxa/generic.c b/arch/arm/mach-pxa/generic.c index 98df638..ac2b1fc 100644 --- a/arch/arm/mach-pxa/generic.c +++ b/arch/arm/mach-pxa/generic.c @@ -43,6 +43,44 @@ #include "generic.h" /* + * Get the clock frequency as reflected by CCCR and the turbo flag. + * We assume these values have been applied via a fcs. + * If info is not 0 we also display the current settings. + */ +unsigned int get_clk_frequency_khz(int info) +{ + if (cpu_is_pxa21x() || cpu_is_pxa25x()) + return pxa25x_get_clk_frequency_khz(info); + else + return pxa27x_get_clk_frequency_khz(info); +} +EXPORT_SYMBOL(get_clk_frequency_khz); + +/* + * Return the current memory clock frequency in units of 10kHz + */ +unsigned int get_memclk_frequency_10khz(void) +{ + if (cpu_is_pxa21x() || cpu_is_pxa25x()) + return pxa25x_get_memclk_frequency_10khz(); + else + return pxa27x_get_memclk_frequency_10khz(); +} +EXPORT_SYMBOL(get_memclk_frequency_10khz); + +/* + * Return the current LCD clock frequency in units of 10kHz + */ +unsigned int get_lcdclk_frequency_10khz(void) +{ + if (cpu_is_pxa21x() || cpu_is_pxa25x()) + return pxa25x_get_memclk_frequency_10khz(); + else + return pxa27x_get_lcdclk_frequency_10khz(); +} +EXPORT_SYMBOL(get_lcdclk_frequency_10khz); + +/* * Handy function to set GPIO alternate functions */ diff --git a/arch/arm/mach-pxa/generic.h b/arch/arm/mach-pxa/generic.h index 91ab2ad8..0a8a6f8 100644 --- a/arch/arm/mach-pxa/generic.h +++ b/arch/arm/mach-pxa/generic.h @@ -26,3 +26,21 @@ extern unsigned int get_clk_frequency_khz(int info); mi->bank[__nr].size = (__size), \ mi->bank[__nr].node = (((unsigned)(__start) - PHYS_OFFSET) >> 27) +#ifdef CONFIG_PXA25x +extern unsigned pxa25x_get_clk_frequency_khz(int); +extern unsigned pxa25x_get_memclk_frequency_10khz(void); +#else +#define pxa25x_get_clk_frequency_khz(x) (0) +#define pxa25x_get_memclk_frequency_10khz() (0) +#endif + +#ifdef CONFIG_PXA27x +extern unsigned pxa27x_get_clk_frequency_khz(int); +extern unsigned pxa27x_get_memclk_frequency_10khz(void); +extern unsigned pxa27x_get_lcdclk_frequency_10khz(void); +#else +#define pxa27x_get_clk_frequency_khz(x) (0) +#define pxa27x_get_memclk_frequency_10khz() (0) +#define pxa27x_get_lcdclk_frequency_10khz() (0) +#endif + diff --git a/arch/arm/mach-pxa/pxa25x.c b/arch/arm/mach-pxa/pxa25x.c index 6dfcca7..bcf3f0a 100644 --- a/arch/arm/mach-pxa/pxa25x.c +++ b/arch/arm/mach-pxa/pxa25x.c @@ -53,7 +53,7 @@ static unsigned char N2_clk_mult[8] = { 0, 0, 2, 3, 4, 0, 6, 0 }; * We assume these values have been applied via a fcs. * If info is not 0 we also display the current settings. */ -unsigned int get_clk_frequency_khz(int info) +unsigned int pxa25x_get_clk_frequency_khz(int info) { unsigned long cccr, turbo; unsigned int l, L, m, M, n2, N; @@ -86,28 +86,14 @@ unsigned int get_clk_frequency_khz(int info) return (turbo & 1) ? (N/1000) : (M/1000); } -EXPORT_SYMBOL(get_clk_frequency_khz); - /* * Return the current memory clock frequency in units of 10kHz */ -unsigned int get_memclk_frequency_10khz(void) +unsigned int pxa25x_get_memclk_frequency_10khz(void) { return L_clk_mult[(CCCR >> 0) & 0x1f] * BASE_CLK / 10000; } -EXPORT_SYMBOL(get_memclk_frequency_10khz); - -/* - * Return the current LCD clock frequency in units of 10kHz - */ -unsigned int get_lcdclk_frequency_10khz(void) -{ - return get_memclk_frequency_10khz(); -} - -EXPORT_SYMBOL(get_lcdclk_frequency_10khz); - #ifdef CONFIG_PM #define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x diff --git a/arch/arm/mach-pxa/pxa27x.c b/arch/arm/mach-pxa/pxa27x.c index 203371a..b3bbf3f 100644 --- a/arch/arm/mach-pxa/pxa27x.c +++ b/arch/arm/mach-pxa/pxa27x.c @@ -36,7 +36,7 @@ * We assume these values have been applied via a fcs. * If info is not 0 we also display the current settings. */ -unsigned int get_clk_frequency_khz( int info) +unsigned int pxa27x_get_clk_frequency_khz(int info) { unsigned long ccsr, clkcfg; unsigned int l, L, m, M, n2, N, S; @@ -79,7 +79,7 @@ unsigned int get_clk_frequency_khz( int info) * Return the current mem clock frequency in units of 10kHz as * reflected by CCCR[A], B, and L */ -unsigned int get_memclk_frequency_10khz(void) +unsigned int pxa27x_get_memclk_frequency_10khz(void) { unsigned long ccsr, clkcfg; unsigned int l, L, m, M; @@ -104,7 +104,7 @@ unsigned int get_memclk_frequency_10khz(void) /* * Return the current LCD clock frequency in units of 10kHz as */ -unsigned int get_lcdclk_frequency_10khz(void) +unsigned int pxa27x_get_lcdclk_frequency_10khz(void) { unsigned long ccsr; unsigned int l, L, k, K; @@ -120,10 +120,6 @@ unsigned int get_lcdclk_frequency_10khz(void) return (K / 10000); } -EXPORT_SYMBOL(get_clk_frequency_khz); -EXPORT_SYMBOL(get_memclk_frequency_10khz); -EXPORT_SYMBOL(get_lcdclk_frequency_10khz); - #ifdef CONFIG_PM #define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x -- cgit v0.10.2 From 00dc4f949e7423769de1a160c590840534ea3a70 Mon Sep 17 00:00:00 2001 From: Russell King Date: Mon, 20 Aug 2007 10:09:18 +0100 Subject: [ARM] pxa: make pxa27x devices globally visible Signed-off-by: Russell King diff --git a/arch/arm/mach-pxa/devices.h b/arch/arm/mach-pxa/devices.h index 636fdb1..94c8d5c 100644 --- a/arch/arm/mach-pxa/devices.h +++ b/arch/arm/mach-pxa/devices.h @@ -9,3 +9,6 @@ extern struct platform_device pxa_device_i2c; extern struct platform_device pxa_device_i2s; extern struct platform_device pxa_device_ficp; extern struct platform_device pxa_device_rtc; + +extern struct platform_device pxa27x_device_i2c_power; +extern struct platform_device pxa27x_device_ohci; diff --git a/arch/arm/mach-pxa/pxa27x.c b/arch/arm/mach-pxa/pxa27x.c index b3bbf3f..3710981 100644 --- a/arch/arm/mach-pxa/pxa27x.c +++ b/arch/arm/mach-pxa/pxa27x.c @@ -282,7 +282,7 @@ static struct resource pxa27x_ohci_resources[] = { }, }; -static struct platform_device pxa27x_device_ohci = { +struct platform_device pxa27x_device_ohci = { .name = "pxa27x-ohci", .id = -1, .dev = { @@ -310,7 +310,7 @@ static struct resource i2c_power_resources[] = { }, }; -static struct platform_device pxa27x_device_i2c_power = { +struct platform_device pxa27x_device_i2c_power = { .name = "pxa2xx-i2c", .id = 1, .resource = i2c_power_resources, -- cgit v0.10.2 From a6dba20c5c7b3a18d69bcbd60a1d2ebc0536f0ce Mon Sep 17 00:00:00 2001 From: Russell King Date: Mon, 20 Aug 2007 10:18:02 +0100 Subject: [ARM] pxa: introduce clk support for PXA SoC clocks Signed-off-by: Russell King diff --git a/arch/arm/mach-pxa/clock.c b/arch/arm/mach-pxa/clock.c index 34a31ca..83ef5ec 100644 --- a/arch/arm/mach-pxa/clock.c +++ b/arch/arm/mach-pxa/clock.c @@ -9,19 +9,15 @@ #include #include #include +#include +#include #include #include -struct clk { - struct list_head node; - unsigned long rate; - struct module *owner; - const char *name; - unsigned int enabled; - void (*enable)(void); - void (*disable)(void); -}; +#include "devices.h" +#include "generic.h" +#include "clock.h" static LIST_HEAD(clocks); static DEFINE_MUTEX(clocks_mutex); @@ -33,7 +29,8 @@ struct clk *clk_get(struct device *dev, const char *id) mutex_lock(&clocks_mutex); list_for_each_entry(p, &clocks, node) { - if (strcmp(id, p->name) == 0 && try_module_get(p->owner)) { + if (strcmp(id, p->name) == 0 && + (p->dev == NULL || p->dev == dev)) { clk = p; break; } @@ -46,7 +43,6 @@ EXPORT_SYMBOL(clk_get); void clk_put(struct clk *clk) { - module_put(clk->owner); } EXPORT_SYMBOL(clk_put); @@ -56,8 +52,12 @@ int clk_enable(struct clk *clk) spin_lock_irqsave(&clocks_lock, flags); if (clk->enabled++ == 0) - clk->enable(); + clk->ops->enable(clk); spin_unlock_irqrestore(&clocks_lock, flags); + + if (clk->delay) + udelay(clk->delay); + return 0; } EXPORT_SYMBOL(clk_enable); @@ -70,54 +70,75 @@ void clk_disable(struct clk *clk) spin_lock_irqsave(&clocks_lock, flags); if (--clk->enabled == 0) - clk->disable(); + clk->ops->disable(clk); spin_unlock_irqrestore(&clocks_lock, flags); } EXPORT_SYMBOL(clk_disable); unsigned long clk_get_rate(struct clk *clk) { - return clk->rate; + unsigned long rate; + + rate = clk->rate; + if (clk->ops->getrate) + rate = clk->ops->getrate(clk); + + return rate; } EXPORT_SYMBOL(clk_get_rate); -static void clk_gpio27_enable(void) +static void clk_gpio27_enable(struct clk *clk) { pxa_gpio_mode(GPIO11_3_6MHz_MD); } -static void clk_gpio27_disable(void) +static void clk_gpio27_disable(struct clk *clk) { } -static struct clk clk_gpio27 = { - .name = "GPIO27_CLK", - .rate = 3686400, +static const struct clkops clk_gpio27_ops = { .enable = clk_gpio27_enable, .disable = clk_gpio27_disable, }; -int clk_register(struct clk *clk) + +void clk_cken_enable(struct clk *clk) { - mutex_lock(&clocks_mutex); - list_add(&clk->node, &clocks); - mutex_unlock(&clocks_mutex); - return 0; + CKEN |= 1 << clk->cken; } -EXPORT_SYMBOL(clk_register); -void clk_unregister(struct clk *clk) +void clk_cken_disable(struct clk *clk) { + CKEN &= ~(1 << clk->cken); +} + +const struct clkops clk_cken_ops = { + .enable = clk_cken_enable, + .disable = clk_cken_disable, +}; + +static struct clk common_clks[] = { + { + .name = "GPIO27_CLK", + .ops = &clk_gpio27_ops, + .rate = 3686400, + }, +}; + +void clks_register(struct clk *clks, size_t num) +{ + int i; + mutex_lock(&clocks_mutex); - list_del(&clk->node); + for (i = 0; i < num; i++) + list_add(&clks[i].node, &clocks); mutex_unlock(&clocks_mutex); } -EXPORT_SYMBOL(clk_unregister); static int __init clk_init(void) { - clk_register(&clk_gpio27); + clks_register(common_clks, ARRAY_SIZE(common_clks)); return 0; } arch_initcall(clk_init); diff --git a/arch/arm/mach-pxa/clock.h b/arch/arm/mach-pxa/clock.h new file mode 100644 index 0000000..bc6b77e --- /dev/null +++ b/arch/arm/mach-pxa/clock.h @@ -0,0 +1,43 @@ +struct clk; + +struct clkops { + void (*enable)(struct clk *); + void (*disable)(struct clk *); + unsigned long (*getrate)(struct clk *); +}; + +struct clk { + struct list_head node; + const char *name; + struct device *dev; + const struct clkops *ops; + unsigned long rate; + unsigned int cken; + unsigned int delay; + unsigned int enabled; +}; + +#define INIT_CKEN(_name, _cken, _rate, _delay, _dev) \ + { \ + .name = _name, \ + .dev = _dev, \ + .ops = &clk_cken_ops, \ + .rate = _rate, \ + .cken = CKEN_##_cken, \ + .delay = _delay, \ + } + +#define INIT_CK(_name, _cken, _ops, _dev) \ + { \ + .name = _name, \ + .dev = _dev, \ + .ops = _ops, \ + .cken = CKEN_##_cken, \ + } + +extern const struct clkops clk_cken_ops; + +void clk_cken_enable(struct clk *clk); +void clk_cken_disable(struct clk *clk); + +void clks_register(struct clk *clks, size_t num); diff --git a/arch/arm/mach-pxa/pxa25x.c b/arch/arm/mach-pxa/pxa25x.c index bcf3f0a..62a7701 100644 --- a/arch/arm/mach-pxa/pxa25x.c +++ b/arch/arm/mach-pxa/pxa25x.c @@ -30,6 +30,7 @@ #include "generic.h" #include "devices.h" +#include "clock.h" /* * Various clock factors driven by the CCCR register. @@ -94,6 +95,41 @@ unsigned int pxa25x_get_memclk_frequency_10khz(void) return L_clk_mult[(CCCR >> 0) & 0x1f] * BASE_CLK / 10000; } +static unsigned long clk_pxa25x_lcd_getrate(struct clk *clk) +{ + return pxa25x_get_memclk_frequency_10khz() * 10000; +} + +static const struct clkops clk_pxa25x_lcd_ops = { + .enable = clk_cken_enable, + .disable = clk_cken_disable, + .getrate = clk_pxa25x_lcd_getrate, +}; + +/* + * 3.6864MHz -> OST, GPIO, SSP, PWM, PLLs (95.842MHz, 147.456MHz) + * 95.842MHz -> MMC 19.169MHz, I2C 31.949MHz, FICP 47.923MHz, USB 47.923MHz + * 147.456MHz -> UART 14.7456MHz, AC97 12.288MHz, I2S 5.672MHz (allegedly) + */ +static struct clk pxa25x_clks[] = { + INIT_CK("LCDCLK", LCD, &clk_pxa25x_lcd_ops, &pxa_device_fb.dev), + INIT_CKEN("UARTCLK", FFUART, 14745600, 1, &pxa_device_ffuart.dev), + INIT_CKEN("UARTCLK", BTUART, 14745600, 1, &pxa_device_btuart.dev), + INIT_CKEN("UARTCLK", STUART, 14745600, 1, &pxa_device_stuart.dev), + INIT_CKEN("UARTCLK", BTUART, 14745600, 1, &pxa_device_btuart.dev), + INIT_CKEN("UDCCLK", USB, 47923000, 5, &pxa_device_udc.dev), + INIT_CKEN("MMCCLK", MMC, 19169000, 0, &pxa_device_mci.dev), + INIT_CKEN("I2CCLK", I2C, 31949000, 0, &pxa_device_i2c.dev), + /* + INIT_CKEN("PWMCLK", PWM0, 3686400, 0, NULL), + INIT_CKEN("PWMCLK", PWM0, 3686400, 0, NULL), + INIT_CKEN("SSPCLK", SSP, 3686400, 0, NULL), + INIT_CKEN("I2SCLK", I2S, 14745600, 0, NULL), + INIT_CKEN("NSSPCLK", NSSP, 3686400, 0, NULL), + INIT_CKEN("FICPCLK", FICP, 47923000, 0, NULL), + */ +}; + #ifdef CONFIG_PM #define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x @@ -215,6 +251,8 @@ static int __init pxa25x_init(void) int ret = 0; if (cpu_is_pxa21x() || cpu_is_pxa25x()) { + clks_register(pxa25x_clks, ARRAY_SIZE(pxa25x_clks)); + if ((ret = pxa_init_dma(16))) return ret; #ifdef CONFIG_PM diff --git a/arch/arm/mach-pxa/pxa27x.c b/arch/arm/mach-pxa/pxa27x.c index 3710981..433644e 100644 --- a/arch/arm/mach-pxa/pxa27x.c +++ b/arch/arm/mach-pxa/pxa27x.c @@ -27,6 +27,7 @@ #include "generic.h" #include "devices.h" +#include "clock.h" /* Crystal clock: 13MHz */ #define BASE_CLK 13000000 @@ -120,6 +121,48 @@ unsigned int pxa27x_get_lcdclk_frequency_10khz(void) return (K / 10000); } +static unsigned long clk_pxa27x_lcd_getrate(struct clk *clk) +{ + return pxa27x_get_lcdclk_frequency_10khz() * 10000; +} + +static const struct clkops clk_pxa27x_lcd_ops = { + .enable = clk_cken_enable, + .disable = clk_cken_disable, + .getrate = clk_pxa27x_lcd_getrate, +}; + +static struct clk pxa27x_clks[] = { + INIT_CK("LCDCLK", LCD, &clk_pxa27x_lcd_ops, &pxa_device_fb.dev), + INIT_CK("CAMCLK", CAMERA, &clk_pxa27x_lcd_ops, NULL), + + INIT_CKEN("UARTCLK", STUART, 14857000, 1, &pxa_device_stuart.dev), + INIT_CKEN("UARTCLK", FFUART, 14857000, 1, &pxa_device_ffuart.dev), + INIT_CKEN("UARTCLK", BTUART, 14857000, 1, &pxa_device_btuart.dev), + + INIT_CKEN("I2SCLK", I2S, 14682000, 0, &pxa_device_i2s.dev), + INIT_CKEN("I2CCLK", I2C, 32842000, 0, &pxa_device_i2c.dev), + INIT_CKEN("UDCCLK", USB, 48000000, 5, &pxa_device_udc.dev), + INIT_CKEN("MMCCLK", MMC, 19500000, 0, &pxa_device_mci.dev), + INIT_CKEN("FICPCLK", FICP, 48000000, 0, &pxa_device_ficp.dev), + + INIT_CKEN("USBCLK", USB, 48000000, 0, &pxa27x_device_ohci.dev), + INIT_CKEN("I2CCLK", PWRI2C, 13000000, 0, &pxa27x_device_i2c_power.dev), + INIT_CKEN("KBDCLK", KEYPAD, 32768, 0, NULL), + + /* + INIT_CKEN("PWMCLK", PWM0, 13000000, 0, NULL), + INIT_CKEN("SSPCLK", SSP1, 13000000, 0, NULL), + INIT_CKEN("SSPCLK", SSP2, 13000000, 0, NULL), + INIT_CKEN("SSPCLK", SSP3, 13000000, 0, NULL), + INIT_CKEN("MSLCLK", MSL, 48000000, 0, NULL), + INIT_CKEN("USIMCLK", USIM, 48000000, 0, NULL), + INIT_CKEN("MSTKCLK", MEMSTK, 19500000, 0, NULL), + INIT_CKEN("IMCLK", IM, 0, 0, NULL), + INIT_CKEN("MEMCLK", MEMC, 0, 0, NULL), + */ +}; + #ifdef CONFIG_PM #define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x @@ -343,6 +386,8 @@ static int __init pxa27x_init(void) { int ret = 0; if (cpu_is_pxa27x()) { + clks_register(pxa27x_clks, ARRAY_SIZE(pxa27x_clks)); + if ((ret = pxa_init_dma(32))) return ret; #ifdef CONFIG_PM -- cgit v0.10.2 From 72e3524c0b591c30c3a2e2058dd78327ec99efed Mon Sep 17 00:00:00 2001 From: Russell King Date: Mon, 20 Aug 2007 10:18:42 +0100 Subject: [ARM] pxa: update pxafb to use clk support Signed-off-by: Russell King diff --git a/drivers/video/pxafb.c b/drivers/video/pxafb.c index a280a52..f9b12ab 100644 --- a/drivers/video/pxafb.c +++ b/drivers/video/pxafb.c @@ -37,6 +37,8 @@ #include #include #include +#include +#include #include #include @@ -506,15 +508,15 @@ static struct fb_ops pxafb_ops = { * * Factoring the 10^4 and 10^-12 out gives 10^-8 == 1 / 100000000 as used below. */ -static inline unsigned int get_pcd(unsigned int pixclock) +static inline unsigned int get_pcd(struct pxafb_info *fbi, unsigned int pixclock) { unsigned long long pcd; /* FIXME: Need to take into account Double Pixel Clock mode - * (DPC) bit? or perhaps set it based on the various clock - * speeds */ - - pcd = (unsigned long long)get_lcdclk_frequency_10khz() * pixclock; + * (DPC) bit? or perhaps set it based on the various clock + * speeds */ + pcd = (unsigned long long)(clk_get_rate(fbi->clk) / 10000); + pcd *= pixclock; do_div(pcd, 100000000 * 2); /* no need for this, since we should subtract 1 anyway. they cancel */ /* pcd += 1; */ /* make up for integer math truncations */ @@ -523,19 +525,21 @@ static inline unsigned int get_pcd(unsigned int pixclock) /* * Some touchscreens need hsync information from the video driver to - * function correctly. We export it here. + * function correctly. We export it here. Note that 'hsync_time' and + * the value returned from pxafb_get_hsync_time() is the *reciprocal* + * of the hsync period in seconds. */ static inline void set_hsync_time(struct pxafb_info *fbi, unsigned int pcd) { - unsigned long long htime; + unsigned long htime; if ((pcd == 0) || (fbi->fb.var.hsync_len == 0)) { fbi->hsync_time=0; return; } - htime = (unsigned long long)get_lcdclk_frequency_10khz() * 10000; - do_div(htime, pcd * fbi->fb.var.hsync_len); + htime = clk_get_rate(fbi->clk) / (pcd * fbi->fb.var.hsync_len); + fbi->hsync_time = htime; } @@ -560,7 +564,7 @@ static int pxafb_activate_var(struct fb_var_screeninfo *var, struct pxafb_info * { struct pxafb_lcd_reg new_regs; u_long flags; - u_int lines_per_panel, pcd = get_pcd(var->pixclock); + u_int lines_per_panel, pcd = get_pcd(fbi, var->pixclock); pr_debug("pxafb: Configuring PXA LCD\n"); @@ -803,7 +807,7 @@ static void pxafb_enable_controller(struct pxafb_info *fbi) pr_debug("reg_lccr3 0x%08x\n", (unsigned int) fbi->reg_lccr3); /* enable LCD controller clock */ - pxa_set_cken(CKEN_LCD, 1); + clk_enable(fbi->clk); /* Sequence from 11.7.10 */ LCCR3 = fbi->reg_lccr3; @@ -840,7 +844,7 @@ static void pxafb_disable_controller(struct pxafb_info *fbi) remove_wait_queue(&fbi->ctrlr_wait, &wait); /* disable LCD controller clock */ - pxa_set_cken(CKEN_LCD, 0); + clk_disable(fbi->clk); } /* @@ -994,7 +998,7 @@ pxafb_freq_transition(struct notifier_block *nb, unsigned long val, void *data) break; case CPUFREQ_POSTCHANGE: - pcd = get_pcd(fbi->fb.var.pixclock); + pcd = get_pcd(fbi, fbi->fb.var.pixclock); set_hsync_time(fbi, pcd); fbi->reg_lccr3 = (fbi->reg_lccr3 & ~0xff) | LCCR3_PixClkDiv(pcd); set_ctrlr_state(fbi, C_ENABLE_CLKCHANGE); @@ -1119,6 +1123,12 @@ static struct pxafb_info * __init pxafb_init_fbinfo(struct device *dev) memset(fbi, 0, sizeof(struct pxafb_info)); fbi->dev = dev; + fbi->clk = clk_get(dev, "LCDCLK"); + if (IS_ERR(fbi->clk)) { + kfree(fbi); + return NULL; + } + strcpy(fbi->fb.fix.id, PXA_NAME); fbi->fb.fix.type = FB_TYPE_PACKED_PIXELS; diff --git a/drivers/video/pxafb.h b/drivers/video/pxafb.h index 7499a1c..f8605b8 100644 --- a/drivers/video/pxafb.h +++ b/drivers/video/pxafb.h @@ -40,6 +40,7 @@ struct pxafb_dma_descriptor { struct pxafb_info { struct fb_info fb; struct device *dev; + struct clk *clk; /* * These are the addresses we mapped -- cgit v0.10.2 From c3cef3f3c07bb98e023e4d5441e60538516a4741 Mon Sep 17 00:00:00 2001 From: Russell King Date: Mon, 20 Aug 2007 10:19:10 +0100 Subject: [ARM] pxa: update pxa i2c driver to use clk support Signed-off-by: Russell King diff --git a/drivers/i2c/busses/i2c-pxa.c b/drivers/i2c/busses/i2c-pxa.c index bb5466b..00fad11 100644 --- a/drivers/i2c/busses/i2c-pxa.c +++ b/drivers/i2c/busses/i2c-pxa.c @@ -31,6 +31,8 @@ #include #include #include +#include +#include #include #include @@ -48,6 +50,7 @@ struct pxa_i2c { unsigned int slave_addr; struct i2c_adapter adap; + struct clk *clk; #ifdef CONFIG_I2C_PXA_SLAVE struct i2c_slave_client *slave; #endif @@ -869,6 +872,12 @@ static int i2c_pxa_probe(struct platform_device *dev) sprintf(i2c->adap.name, "pxa_i2c-i2c.%u", dev->id); + i2c->clk = clk_get(&dev->dev, "I2CCLK"); + if (IS_ERR(i2c->clk)) { + ret = PTR_ERR(i2c->clk); + goto eclk; + } + i2c->reg_base = ioremap(res->start, res_len(res)); if (!i2c->reg_base) { ret = -EIO; @@ -889,22 +898,19 @@ static int i2c_pxa_probe(struct platform_device *dev) } #endif + clk_enable(i2c->clk); +#ifdef CONFIG_PXA27x switch (dev->id) { case 0: -#ifdef CONFIG_PXA27x pxa_gpio_mode(GPIO117_I2CSCL_MD); pxa_gpio_mode(GPIO118_I2CSDA_MD); -#endif - pxa_set_cken(CKEN_I2C, 1); break; -#ifdef CONFIG_PXA27x case 1: local_irq_disable(); PCFR |= PCFR_PI2CEN; local_irq_enable(); - pxa_set_cken(CKEN_PWRI2C, 1); -#endif } +#endif ret = request_irq(irq, i2c_pxa_handler, IRQF_DISABLED, i2c->adap.name, i2c); @@ -948,19 +954,18 @@ static int i2c_pxa_probe(struct platform_device *dev) eadapt: free_irq(irq, i2c); ereqirq: - switch (dev->id) { - case 0: - pxa_set_cken(CKEN_I2C, 0); - break; + clk_disable(i2c->clk); + #ifdef CONFIG_PXA27x - case 1: - pxa_set_cken(CKEN_PWRI2C, 0); + if (dev->id == 1) { local_irq_disable(); PCFR &= ~PCFR_PI2CEN; local_irq_enable(); -#endif } +#endif eremap: + clk_put(i2c->clk); +eclk: kfree(i2c); emalloc: release_mem_region(res->start, res_len(res)); @@ -975,18 +980,18 @@ static int i2c_pxa_remove(struct platform_device *dev) i2c_del_adapter(&i2c->adap); free_irq(i2c->irq, i2c); - switch (dev->id) { - case 0: - pxa_set_cken(CKEN_I2C, 0); - break; + + clk_disable(i2c->clk); + clk_put(i2c->clk); + #ifdef CONFIG_PXA27x - case 1: - pxa_set_cken(CKEN_PWRI2C, 0); + if (dev->id == 1) { local_irq_disable(); PCFR &= ~PCFR_PI2CEN; local_irq_enable(); -#endif } +#endif + release_mem_region(i2c->iobase, i2c->iosize); kfree(i2c); -- cgit v0.10.2 From 22d8a73a8b39ef236c80ea73704884f7a7862193 Mon Sep 17 00:00:00 2001 From: Russell King Date: Mon, 20 Aug 2007 10:19:39 +0100 Subject: [ARM] pxa: update pxa27x keypad driver to use clk support Signed-off-by: Russell King diff --git a/drivers/input/keyboard/pxa27x_keyboard.c b/drivers/input/keyboard/pxa27x_keyboard.c index ebe5eac..b7061aa 100644 --- a/drivers/input/keyboard/pxa27x_keyboard.c +++ b/drivers/input/keyboard/pxa27x_keyboard.c @@ -23,6 +23,8 @@ #include #include #include +#include +#include #include #include @@ -40,6 +42,8 @@ col/2 == 2 ? KPASMKP2 : KPASMKP3) #define KPASMKPx_MKC(row, col) (1 << (row + 16 * (col % 2))) +static struct clk *pxakbd_clk; + static irqreturn_t pxakbd_irq_handler(int irq, void *dev_id) { struct platform_device *pdev = dev_id; @@ -104,7 +108,7 @@ static int pxakbd_open(struct input_dev *dev) KPREC = 0x7F; /* Enable unit clock */ - pxa_set_cken(CKEN_KEYPAD, 1); + clk_enable(pxakbd_clk); return 0; } @@ -112,7 +116,7 @@ static int pxakbd_open(struct input_dev *dev) static void pxakbd_close(struct input_dev *dev) { /* Disable clock unit */ - pxa_set_cken(CKEN_KEYPAD, 0); + clk_disable(pxakbd_clk); } #ifdef CONFIG_PM @@ -140,7 +144,8 @@ static int pxakbd_resume(struct platform_device *pdev) KPREC = pdata->reg_kprec; /* Enable unit clock */ - pxa_set_cken(CKEN_KEYPAD, 1); + clk_disable(pxakbd_clk); + clk_enable(pxakbd_clk); } mutex_unlock(&input_dev->mutex); @@ -158,11 +163,18 @@ static int __devinit pxakbd_probe(struct platform_device *pdev) struct input_dev *input_dev; int i, row, col, error; + pxakbd_clk = clk_get(&pdev->dev, "KBDCLK"); + if (IS_ERR(pxakbd_clk)) { + error = PTR_ERR(pxakbd_clk); + goto err_clk; + } + /* Create and register the input driver. */ input_dev = input_allocate_device(); if (!input_dev) { printk(KERN_ERR "Cannot request keypad device\n"); - return -ENOMEM; + error = -ENOMEM; + goto err_alloc; } input_dev->name = DRIVER_NAME; @@ -185,7 +197,6 @@ static int __devinit pxakbd_probe(struct platform_device *pdev) DRIVER_NAME, pdev); if (error) { printk(KERN_ERR "Cannot request keypad IRQ\n"); - pxa_set_cken(CKEN_KEYPAD, 0); goto err_free_dev; } @@ -217,6 +228,9 @@ static int __devinit pxakbd_probe(struct platform_device *pdev) free_irq(IRQ_KEYPAD, pdev); err_free_dev: input_free_device(input_dev); + err_alloc: + clk_put(pxakbd_clk); + err_clk: return error; } @@ -226,6 +240,7 @@ static int __devexit pxakbd_remove(struct platform_device *pdev) input_unregister_device(input_dev); free_irq(IRQ_KEYPAD, pdev); + clk_put(pxakbd_clk); platform_set_drvdata(pdev, NULL); return 0; -- cgit v0.10.2 From ebebd9b0a1463d5de89017ad59a6b9cd4044687f Mon Sep 17 00:00:00 2001 From: Russell King Date: Mon, 20 Aug 2007 10:20:03 +0100 Subject: [ARM] pxa: update PXA MMC interface driver to use clk support Signed-off-by: Russell King diff --git a/drivers/mmc/host/pxamci.c b/drivers/mmc/host/pxamci.c index 657901e..0601e01 100644 --- a/drivers/mmc/host/pxamci.c +++ b/drivers/mmc/host/pxamci.c @@ -23,6 +23,8 @@ #include #include #include +#include +#include #include #include @@ -44,6 +46,8 @@ struct pxamci_host { spinlock_t lock; struct resource *res; void __iomem *base; + struct clk *clk; + unsigned long clkrate; int irq; int dma; unsigned int clkrt; @@ -119,7 +123,7 @@ static void pxamci_setup_data(struct pxamci_host *host, struct mmc_data *data) writel(nob, host->base + MMC_NOB); writel(data->blksz, host->base + MMC_BLKLEN); - clks = (unsigned long long)data->timeout_ns * CLOCKRATE; + clks = (unsigned long long)data->timeout_ns * host->clkrate; do_div(clks, 1000000000UL); timeout = (unsigned int)clks + (data->timeout_clks << host->clkrt); writel((timeout + 255) / 256, host->base + MMC_RDTO); @@ -365,18 +369,25 @@ static void pxamci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) struct pxamci_host *host = mmc_priv(mmc); if (ios->clock) { - unsigned int clk = CLOCKRATE / ios->clock; - if (CLOCKRATE / clk > ios->clock) + unsigned long rate = host->clkrate; + unsigned int clk = rate / ios->clock; + + /* + * clk might result in a lower divisor than we + * desire. check for that condition and adjust + * as appropriate. + */ + if (rate / clk > ios->clock) clk <<= 1; host->clkrt = fls(clk) - 1; - pxa_set_cken(CKEN_MMC, 1); + clk_enable(host->clk); /* * we write clkrt on the next command */ } else { pxamci_stop_clock(host); - pxa_set_cken(CKEN_MMC, 0); + clk_disable(host->clk); } if (host->power_mode != ios->power_mode) { @@ -462,8 +473,6 @@ static int pxamci_probe(struct platform_device *pdev) } mmc->ops = &pxamci_ops; - mmc->f_min = CLOCKRATE_MIN; - mmc->f_max = CLOCKRATE_MAX; /* * We can do SG-DMA, but we don't because we never know how much @@ -490,6 +499,22 @@ static int pxamci_probe(struct platform_device *pdev) host->mmc = mmc; host->dma = -1; host->pdata = pdev->dev.platform_data; + + host->clk = clk_get(&pdev->dev, "MMCCLK"); + if (IS_ERR(host->clk)) { + ret = PTR_ERR(host->clk); + host->clk = NULL; + goto out; + } + + host->clkrate = clk_get_rate(host->clk); + + /* + * Calculate minimum clock rate, rounding up. + */ + mmc->f_min = (host->clkrate + 63) / 64; + mmc->f_max = host->clkrate; + mmc->ocr_avail = host->pdata ? host->pdata->ocr_mask : MMC_VDD_32_33|MMC_VDD_33_34; @@ -554,6 +579,8 @@ static int pxamci_probe(struct platform_device *pdev) iounmap(host->base); if (host->sg_cpu) dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma); + if (host->clk) + clk_put(host->clk); } if (mmc) mmc_free_host(mmc); @@ -588,6 +615,8 @@ static int pxamci_remove(struct platform_device *pdev) iounmap(host->base); dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma); + clk_put(host->clk); + release_resource(host->res); mmc_free_host(mmc); diff --git a/drivers/mmc/host/pxamci.h b/drivers/mmc/host/pxamci.h index 3153e77..748c770 100644 --- a/drivers/mmc/host/pxamci.h +++ b/drivers/mmc/host/pxamci.h @@ -88,17 +88,3 @@ #define MMC_RXFIFO 0x0040 /* 8 bit */ #define MMC_TXFIFO 0x0044 /* 8 bit */ - -/* - * The base MMC clock rate - */ -#ifdef CONFIG_PXA27x -#define CLOCKRATE_MIN 304688 -#define CLOCKRATE_MAX 19500000 -#else -#define CLOCKRATE_MIN 312500 -#define CLOCKRATE_MAX 20000000 -#endif - -#define CLOCKRATE CLOCKRATE_MAX - -- cgit v0.10.2 From b049bd9de4959dd9e4b586d14b6de450a52c6f1f Mon Sep 17 00:00:00 2001 From: Russell King Date: Mon, 20 Aug 2007 10:28:15 +0100 Subject: [ARM] pxa: update pxa serial driver to use clk support Signed-off-by: Russell King diff --git a/drivers/serial/pxa.c b/drivers/serial/pxa.c index 59889f6..af3a011 100644 --- a/drivers/serial/pxa.c +++ b/drivers/serial/pxa.c @@ -42,6 +42,7 @@ #include #include #include +#include #include #include @@ -55,7 +56,7 @@ struct uart_pxa_port { unsigned char lcr; unsigned char mcr; unsigned int lsr_break_flag; - unsigned int cken; + struct clk *clk; char *name; }; @@ -351,6 +352,8 @@ static int serial_pxa_startup(struct uart_port *port) else up->mcr = 0; + up->port.uartclk = clk_get_rate(up->clk); + /* * Allocate the IRQ */ @@ -546,9 +549,11 @@ serial_pxa_pm(struct uart_port *port, unsigned int state, unsigned int oldstate) { struct uart_pxa_port *up = (struct uart_pxa_port *)port; - pxa_set_cken(up->cken, !state); + if (!state) - udelay(1); + clk_enable(up->clk); + else + clk_disable(up->clk); } static void serial_pxa_release_port(struct uart_port *port) @@ -635,6 +640,8 @@ serial_pxa_console_write(struct console *co, const char *s, unsigned int count) struct uart_pxa_port *up = serial_pxa_ports[co->index]; unsigned int ier; + clk_enable(up->clk); + /* * First save the IER then disable the interrupts */ @@ -649,6 +656,8 @@ serial_pxa_console_write(struct console *co, const char *s, unsigned int count) */ wait_for_xmitr(up); serial_out(up, UART_IER, ier); + + clk_disable(up->clk); } static int __init @@ -752,6 +761,12 @@ static int serial_pxa_probe(struct platform_device *dev) if (!sport) return -ENOMEM; + sport->clk = clk_get(&dev->dev, "UARTCLK"); + if (IS_ERR(sport->clk)) { + ret = PTR_ERR(sport->clk); + goto err_free; + } + sport->port.type = PORT_PXA; sport->port.iotype = UPIO_MEM; sport->port.mapbase = mmres->start; @@ -761,7 +776,7 @@ static int serial_pxa_probe(struct platform_device *dev) sport->port.line = dev->id; sport->port.dev = &dev->dev; sport->port.flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF; - sport->port.uartclk = 921600 * 16; + sport->port.uartclk = clk_get_rate(sport->clk); /* * Is it worth keeping this? @@ -780,7 +795,7 @@ static int serial_pxa_probe(struct platform_device *dev) sport->port.membase = ioremap(mmres->start, mmres->end - mmres->start + 1); if (!sport->port.membase) { ret = -ENOMEM; - goto err_free; + goto err_clk; } serial_pxa_ports[dev->id] = sport; @@ -790,6 +805,8 @@ static int serial_pxa_probe(struct platform_device *dev) return 0; + err_clk: + clk_put(sport->clk); err_free: kfree(sport); return ret; @@ -802,6 +819,7 @@ static int serial_pxa_remove(struct platform_device *dev) platform_set_drvdata(dev, NULL); uart_remove_one_port(&serial_pxa_reg, &sport->port); + clk_put(sport->clk); kfree(sport); return 0; -- cgit v0.10.2 From 6549e6c9575c897514b183071a2b5d839cef9469 Mon Sep 17 00:00:00 2001 From: Russell King Date: Mon, 20 Aug 2007 10:33:35 +0100 Subject: [ARM] pxa: update PXA UDC driver to use clk support Note: this produces a WARN() dump. Signed-off-by: Russell King diff --git a/drivers/usb/gadget/pxa2xx_udc.c b/drivers/usb/gadget/pxa2xx_udc.c index 1407ad1..90d0d08 100644 --- a/drivers/usb/gadget/pxa2xx_udc.c +++ b/drivers/usb/gadget/pxa2xx_udc.c @@ -43,6 +43,8 @@ #include #include #include +#include +#include #include #include @@ -1157,7 +1159,7 @@ static void udc_disable(struct pxa2xx_udc *dev) #ifdef CONFIG_ARCH_PXA /* Disable clock for USB device */ - pxa_set_cken(CKEN_USB, 0); + clk_disable(dev->clk); #endif ep0_idle (dev); @@ -1202,8 +1204,7 @@ static void udc_enable (struct pxa2xx_udc *dev) #ifdef CONFIG_ARCH_PXA /* Enable clock for USB device */ - pxa_set_cken(CKEN_USB, 1); - udelay(5); + clk_enable(dev->clk); #endif /* try to clear these bits before we enable the udc */ @@ -2137,6 +2138,14 @@ static int __init pxa2xx_udc_probe(struct platform_device *pdev) if (irq < 0) return -ENODEV; +#ifdef CONFIG_ARCH_PXA + dev->clk = clk_get(&pdev->dev, "UDCCLK"); + if (IS_ERR(dev->clk)) { + retval = PTR_ERR(dev->clk); + goto err_clk; + } +#endif + pr_debug("%s: IRQ %d%s%s\n", driver_name, irq, dev->has_cfr ? "" : " (!cfr)", SIZE_STR "(pio)" @@ -2152,11 +2161,10 @@ static int __init pxa2xx_udc_probe(struct platform_device *pdev) dev_dbg(&pdev->dev, "can't get vbus gpio %d, err: %d\n", dev->mach->gpio_vbus, retval); - return -EBUSY; + goto err_gpio_vbus; } gpio_direction_input(dev->mach->gpio_vbus); vbus_irq = gpio_to_irq(dev->mach->gpio_vbus); - set_irq_type(vbus_irq, IRQT_BOTHEDGE); } else vbus_irq = 0; @@ -2166,9 +2174,7 @@ static int __init pxa2xx_udc_probe(struct platform_device *pdev) dev_dbg(&pdev->dev, "can't get pullup gpio %d, err: %d\n", dev->mach->gpio_pullup, retval); - if (dev->mach->gpio_vbus) - gpio_free(dev->mach->gpio_vbus); - return -EBUSY; + goto err_gpio_pullup; } gpio_direction_output(dev->mach->gpio_pullup, 0); } @@ -2195,11 +2201,7 @@ static int __init pxa2xx_udc_probe(struct platform_device *pdev) if (retval != 0) { printk(KERN_ERR "%s: can't get irq %d, err %d\n", driver_name, irq, retval); - if (dev->mach->gpio_pullup) - gpio_free(dev->mach->gpio_pullup); - if (dev->mach->gpio_vbus) - gpio_free(dev->mach->gpio_vbus); - return -EBUSY; + goto err_irq1; } dev->got_irq = 1; @@ -2213,12 +2215,7 @@ static int __init pxa2xx_udc_probe(struct platform_device *pdev) printk(KERN_ERR "%s: can't get irq %i, err %d\n", driver_name, LUBBOCK_USB_DISC_IRQ, retval); lubbock_fail0: - free_irq(irq, dev); - if (dev->mach->gpio_pullup) - gpio_free(dev->mach->gpio_pullup); - if (dev->mach->gpio_vbus) - gpio_free(dev->mach->gpio_vbus); - return -EBUSY; + goto err_irq_lub; } retval = request_irq(LUBBOCK_USB_IRQ, lubbock_vbus_irq, @@ -2234,22 +2231,37 @@ lubbock_fail0: #endif if (vbus_irq) { retval = request_irq(vbus_irq, udc_vbus_irq, - IRQF_DISABLED | IRQF_SAMPLE_RANDOM, + IRQF_DISABLED | IRQF_SAMPLE_RANDOM | + IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, driver_name, dev); if (retval != 0) { printk(KERN_ERR "%s: can't get irq %i, err %d\n", driver_name, vbus_irq, retval); - free_irq(irq, dev); - if (dev->mach->gpio_pullup) - gpio_free(dev->mach->gpio_pullup); - if (dev->mach->gpio_vbus) - gpio_free(dev->mach->gpio_vbus); - return -EBUSY; + goto err_vbus_irq; } } create_proc_files(); return 0; + + err_vbus_irq: +#ifdef CONFIG_ARCH_LUBBOCK + free_irq(LUBBOCK_USB_DISC_IRQ, dev); + err_irq_lub: +#endif + free_irq(irq, dev); + err_irq1: + if (dev->mach->gpio_pullup) + gpio_free(dev->mach->gpio_pullup); + err_gpio_pullup: + if (dev->mach->gpio_vbus) + gpio_free(dev->mach->gpio_vbus); + err_gpio_vbus: +#ifdef CONFIG_ARCH_PXA + clk_put(dev->clk); + err_clk: +#endif + return retval; } static void pxa2xx_udc_shutdown(struct platform_device *_dev) @@ -2284,6 +2296,10 @@ static int __exit pxa2xx_udc_remove(struct platform_device *pdev) if (dev->mach->gpio_pullup) gpio_free(dev->mach->gpio_pullup); +#ifdef CONFIG_ARCH_PXA + clk_put(dev->clk); +#endif + platform_set_drvdata(pdev, NULL); the_controller = NULL; return 0; diff --git a/drivers/usb/gadget/pxa2xx_udc.h b/drivers/usb/gadget/pxa2xx_udc.h index 0e5d0e6..1db46d7 100644 --- a/drivers/usb/gadget/pxa2xx_udc.h +++ b/drivers/usb/gadget/pxa2xx_udc.h @@ -125,6 +125,7 @@ struct pxa2xx_udc { struct timer_list timer; struct device *dev; + struct clk *clk; struct pxa2xx_udc_mach_info *mach; u64 dma_mask; struct pxa2xx_ep ep [PXA_UDC_NUM_ENDPOINTS]; -- cgit v0.10.2 From 435b6e94b88af96c3f5b5798c087978c3793400c Mon Sep 17 00:00:00 2001 From: Russell King Date: Sun, 2 Sep 2007 17:08:42 +0100 Subject: [ARM] pxa: Make STUART and FICP clocks available Signed-off-by: Russell King diff --git a/arch/arm/mach-pxa/pxa25x.c b/arch/arm/mach-pxa/pxa25x.c index 62a7701..ef40c04 100644 --- a/arch/arm/mach-pxa/pxa25x.c +++ b/arch/arm/mach-pxa/pxa25x.c @@ -115,8 +115,8 @@ static struct clk pxa25x_clks[] = { INIT_CK("LCDCLK", LCD, &clk_pxa25x_lcd_ops, &pxa_device_fb.dev), INIT_CKEN("UARTCLK", FFUART, 14745600, 1, &pxa_device_ffuart.dev), INIT_CKEN("UARTCLK", BTUART, 14745600, 1, &pxa_device_btuart.dev), - INIT_CKEN("UARTCLK", STUART, 14745600, 1, &pxa_device_stuart.dev), INIT_CKEN("UARTCLK", BTUART, 14745600, 1, &pxa_device_btuart.dev), + INIT_CKEN("UARTCLK", STUART, 14745600, 1, NULL), INIT_CKEN("UDCCLK", USB, 47923000, 5, &pxa_device_udc.dev), INIT_CKEN("MMCCLK", MMC, 19169000, 0, &pxa_device_mci.dev), INIT_CKEN("I2CCLK", I2C, 31949000, 0, &pxa_device_i2c.dev), @@ -126,8 +126,8 @@ static struct clk pxa25x_clks[] = { INIT_CKEN("SSPCLK", SSP, 3686400, 0, NULL), INIT_CKEN("I2SCLK", I2S, 14745600, 0, NULL), INIT_CKEN("NSSPCLK", NSSP, 3686400, 0, NULL), - INIT_CKEN("FICPCLK", FICP, 47923000, 0, NULL), */ + INIT_CKEN("FICPCLK", FICP, 47923000, 0, NULL), }; #ifdef CONFIG_PM diff --git a/arch/arm/mach-pxa/pxa27x.c b/arch/arm/mach-pxa/pxa27x.c index 433644e..f7762bf 100644 --- a/arch/arm/mach-pxa/pxa27x.c +++ b/arch/arm/mach-pxa/pxa27x.c @@ -136,9 +136,9 @@ static struct clk pxa27x_clks[] = { INIT_CK("LCDCLK", LCD, &clk_pxa27x_lcd_ops, &pxa_device_fb.dev), INIT_CK("CAMCLK", CAMERA, &clk_pxa27x_lcd_ops, NULL), - INIT_CKEN("UARTCLK", STUART, 14857000, 1, &pxa_device_stuart.dev), INIT_CKEN("UARTCLK", FFUART, 14857000, 1, &pxa_device_ffuart.dev), INIT_CKEN("UARTCLK", BTUART, 14857000, 1, &pxa_device_btuart.dev), + INIT_CKEN("UARTCLK", STUART, 14857000, 1, NULL), INIT_CKEN("I2SCLK", I2S, 14682000, 0, &pxa_device_i2s.dev), INIT_CKEN("I2CCLK", I2C, 32842000, 0, &pxa_device_i2c.dev), -- cgit v0.10.2 From 82d553c67deef92c6c84ecb70afc56e99863060c Mon Sep 17 00:00:00 2001 From: Russell King Date: Sun, 2 Sep 2007 17:09:23 +0100 Subject: [ARM] pxa: update pxa irda driver to use clk support Signed-off-by: Russell King diff --git a/drivers/net/irda/pxaficp_ir.c b/drivers/net/irda/pxaficp_ir.c index 55ff0fb..8c09344 100644 --- a/drivers/net/irda/pxaficp_ir.c +++ b/drivers/net/irda/pxaficp_ir.c @@ -23,6 +23,7 @@ #include #include #include +#include #include #include @@ -87,8 +88,30 @@ struct pxa_irda { struct device *dev; struct pxaficp_platform_data *pdata; + struct clk *fir_clk; + struct clk *sir_clk; + struct clk *cur_clk; }; +static inline void pxa_irda_disable_clk(struct pxa_irda *si) +{ + if (si->cur_clk) + clk_disable(si->cur_clk); + si->cur_clk = NULL; +} + +static inline void pxa_irda_enable_firclk(struct pxa_irda *si) +{ + si->cur_clk = si->fir_clk; + clk_enable(si->fir_clk); +} + +static inline void pxa_irda_enable_sirclk(struct pxa_irda *si) +{ + si->cur_clk = si->sir_clk; + clk_enable(si->sir_clk); +} + #define IS_FIR(si) ((si)->speed >= 4000000) #define IRDA_FRAME_SIZE_LIMIT 2047 @@ -134,7 +157,7 @@ static int pxa_irda_set_speed(struct pxa_irda *si, int speed) DCSR(si->rxdma) &= ~DCSR_RUN; /* disable FICP */ ICCR0 = 0; - pxa_set_cken(CKEN_FICP, 0); + pxa_irda_disable_clk(si); /* set board transceiver to SIR mode */ si->pdata->transceiver_mode(si->dev, IR_SIRMODE); @@ -144,7 +167,7 @@ static int pxa_irda_set_speed(struct pxa_irda *si, int speed) pxa_gpio_mode(GPIO47_STTXD_MD); /* enable the STUART clock */ - pxa_set_cken(CKEN_STUART, 1); + pxa_irda_enable_sirclk(si); } /* disable STUART first */ @@ -169,7 +192,7 @@ static int pxa_irda_set_speed(struct pxa_irda *si, int speed) /* disable STUART */ STIER = 0; STISR = 0; - pxa_set_cken(CKEN_STUART, 0); + pxa_irda_disable_clk(si); /* disable FICP first */ ICCR0 = 0; @@ -182,7 +205,7 @@ static int pxa_irda_set_speed(struct pxa_irda *si, int speed) pxa_gpio_mode(GPIO47_ICPTXD_MD); /* enable the FICP clock */ - pxa_set_cken(CKEN_FICP, 1); + pxa_irda_enable_firclk(si); si->speed = speed; pxa_irda_fir_dma_rx_start(si); @@ -592,16 +615,15 @@ static void pxa_irda_shutdown(struct pxa_irda *si) STIER = 0; /* disable STUART SIR mode */ STISR = 0; - /* disable the STUART clock */ - pxa_set_cken(CKEN_STUART, 0); /* disable DMA */ DCSR(si->txdma) &= ~DCSR_RUN; DCSR(si->rxdma) &= ~DCSR_RUN; /* disable FICP */ ICCR0 = 0; - /* disable the FICP clock */ - pxa_set_cken(CKEN_FICP, 0); + + /* disable the STUART or FICP clocks */ + pxa_irda_disable_clk(si); DRCMR17 = 0; DRCMR18 = 0; @@ -792,6 +814,13 @@ static int pxa_irda_probe(struct platform_device *pdev) si->dev = &pdev->dev; si->pdata = pdev->dev.platform_data; + si->sir_clk = clk_get(&pdev->dev, "UARTCLK"); + si->fir_clk = clk_get(&pdev->dev, "FICPCLK"); + if (IS_ERR(si->sir_clk) || IS_ERR(si->fir_clk)) { + err = PTR_ERR(IS_ERR(si->sir_clk) ? si->sir_clk : si->fir_clk); + goto err_mem_4; + } + /* * Initialise the SIR buffers */ @@ -831,6 +860,10 @@ static int pxa_irda_probe(struct platform_device *pdev) err_mem_5: kfree(si->rx_buff.head); err_mem_4: + if (si->sir_clk && !IS_ERR(si->sir_clk)) + clk_put(si->sir_clk); + if (si->fir_clk && !IS_ERR(si->fir_clk)) + clk_put(si->fir_clk); free_netdev(dev); err_mem_3: release_mem_region(__PREG(FICP), 0x1c); @@ -850,6 +883,8 @@ static int pxa_irda_remove(struct platform_device *_dev) unregister_netdev(dev); kfree(si->tx_buff.head); kfree(si->rx_buff.head); + clk_put(si->fir_clk); + clk_put(si->sir_clk); free_netdev(dev); } -- cgit v0.10.2 From a88a447d44648f1dfba4c40b3f4b6f75597150ed Mon Sep 17 00:00:00 2001 From: Russell King Date: Mon, 20 Aug 2007 10:34:37 +0100 Subject: [ARM] pxa: remove get_lcdclk_frequency_10khz() get_lcdclk_frequency_10khz() is now redundant, remove it. Hide pxa27x_get_lcdclk_frequency_10khz() from public view. Signed-off-by: Russell King diff --git a/arch/arm/mach-pxa/generic.c b/arch/arm/mach-pxa/generic.c index ac2b1fc..2f0cc1c 100644 --- a/arch/arm/mach-pxa/generic.c +++ b/arch/arm/mach-pxa/generic.c @@ -69,18 +69,6 @@ unsigned int get_memclk_frequency_10khz(void) EXPORT_SYMBOL(get_memclk_frequency_10khz); /* - * Return the current LCD clock frequency in units of 10kHz - */ -unsigned int get_lcdclk_frequency_10khz(void) -{ - if (cpu_is_pxa21x() || cpu_is_pxa25x()) - return pxa25x_get_memclk_frequency_10khz(); - else - return pxa27x_get_lcdclk_frequency_10khz(); -} -EXPORT_SYMBOL(get_lcdclk_frequency_10khz); - -/* * Handy function to set GPIO alternate functions */ diff --git a/arch/arm/mach-pxa/generic.h b/arch/arm/mach-pxa/generic.h index 0a8a6f8..5b11741 100644 --- a/arch/arm/mach-pxa/generic.h +++ b/arch/arm/mach-pxa/generic.h @@ -37,10 +37,8 @@ extern unsigned pxa25x_get_memclk_frequency_10khz(void); #ifdef CONFIG_PXA27x extern unsigned pxa27x_get_clk_frequency_khz(int); extern unsigned pxa27x_get_memclk_frequency_10khz(void); -extern unsigned pxa27x_get_lcdclk_frequency_10khz(void); #else #define pxa27x_get_clk_frequency_khz(x) (0) #define pxa27x_get_memclk_frequency_10khz() (0) -#define pxa27x_get_lcdclk_frequency_10khz() (0) #endif diff --git a/arch/arm/mach-pxa/pxa27x.c b/arch/arm/mach-pxa/pxa27x.c index f7762bf..d193755 100644 --- a/arch/arm/mach-pxa/pxa27x.c +++ b/arch/arm/mach-pxa/pxa27x.c @@ -105,7 +105,7 @@ unsigned int pxa27x_get_memclk_frequency_10khz(void) /* * Return the current LCD clock frequency in units of 10kHz as */ -unsigned int pxa27x_get_lcdclk_frequency_10khz(void) +static unsigned int pxa27x_get_lcdclk_frequency_10khz(void) { unsigned long ccsr; unsigned int l, L, k, K; diff --git a/include/asm-arm/arch-pxa/hardware.h b/include/asm-arm/arch-pxa/hardware.h index 3861217..68e7b43 100644 --- a/include/asm-arm/arch-pxa/hardware.h +++ b/include/asm-arm/arch-pxa/hardware.h @@ -122,7 +122,6 @@ extern void pxa_set_cken(int clock, int enable); * return current memory and LCD clock frequency in units of 10kHz */ extern unsigned int get_memclk_frequency_10khz(void); -extern unsigned int get_lcdclk_frequency_10khz(void); #endif -- cgit v0.10.2 From a7073b8b47651ce2ed27564ed8395eff81120c58 Mon Sep 17 00:00:00 2001 From: Russell King Date: Wed, 19 Sep 2007 09:33:55 +0100 Subject: [ARM] pxa: mark pxa_set_cken deprecated Allow the generic clock support code to fiddle with the CKEN register and mark pxa_set_cken() deprecated. Signed-off-by: Russell King diff --git a/arch/arm/mach-pxa/generic.c b/arch/arm/mach-pxa/generic.c index 2f0cc1c..1c5413f 100644 --- a/arch/arm/mach-pxa/generic.c +++ b/arch/arm/mach-pxa/generic.c @@ -123,7 +123,7 @@ EXPORT_SYMBOL(pxa_gpio_set_value); /* * Routine to safely enable or disable a clock in the CKEN */ -void pxa_set_cken(int clock, int enable) +void __pxa_set_cken(int clock, int enable) { unsigned long flags; local_irq_save(flags); @@ -136,7 +136,7 @@ void pxa_set_cken(int clock, int enable) local_irq_restore(flags); } -EXPORT_SYMBOL(pxa_set_cken); +EXPORT_SYMBOL(__pxa_set_cken); /* * Intel PXA2xx internal register mapping. diff --git a/include/asm-arm/arch-pxa/hardware.h b/include/asm-arm/arch-pxa/hardware.h index 68e7b43..538a34e 100644 --- a/include/asm-arm/arch-pxa/hardware.h +++ b/include/asm-arm/arch-pxa/hardware.h @@ -116,7 +116,11 @@ extern void pxa_gpio_set_value(unsigned gpio, int value); /* * Routine to enable or disable CKEN */ -extern void pxa_set_cken(int clock, int enable); +static inline void __deprecated pxa_set_cken(int clock, int enable) +{ + extern void __pxa_set_cken(int clock, int enable); + __pxa_set_cken(clock, enable); +} /* * return current memory and LCD clock frequency in units of 10kHz -- cgit v0.10.2 From fa0b62513b7cb55b6764b794b63c6f583b26e813 Mon Sep 17 00:00:00 2001 From: Russell King Date: Wed, 19 Sep 2007 09:38:32 +0100 Subject: [ARM] pxa: Make CPU_XSCALE depend on PXA25x or PXA27x PXA3 SoCs are supported by the Xscale3 CPU code rather than the Xscale CPU code. Signed-off-by: Russell King diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig index 12161ae..4ca843e 100644 --- a/arch/arm/mm/Kconfig +++ b/arch/arm/mm/Kconfig @@ -322,7 +322,7 @@ config CPU_SA1100 # XScale config CPU_XSCALE bool - depends on ARCH_IOP32X || ARCH_IOP33X || ARCH_PXA || ARCH_IXP4XX || ARCH_IXP2000 + depends on ARCH_IOP32X || ARCH_IOP33X || PXA25x || PXA27x || ARCH_IXP4XX || ARCH_IXP2000 default y select CPU_32v5 select CPU_ABRT_EV5T -- cgit v0.10.2 From cd272ab01141c908ccccb068e6d38b7fcd3240ac Mon Sep 17 00:00:00 2001 From: eric miao Date: Tue, 11 Sep 2007 19:13:17 -0700 Subject: [ARM] pxa: add PXA3 cpu_is_xxx() macros Extracted from patch by Eric Miao, this adds the cpu_is_xxx() macros for identifying PXA3 SoCs. Signed-off-by: eric miao Signed-off-by: Russell King diff --git a/include/asm-arm/arch-pxa/hardware.h b/include/asm-arm/arch-pxa/hardware.h index 538a34e..fc20d72 100644 --- a/include/asm-arm/arch-pxa/hardware.h +++ b/include/asm-arm/arch-pxa/hardware.h @@ -80,6 +80,24 @@ _id == 0x411; \ }) +#define __cpu_is_pxa300(id) \ + ({ \ + unsigned int _id = (id) >> 4 & 0xfff; \ + _id == 0x688; \ + }) + +#define __cpu_is_pxa310(id) \ + ({ \ + unsigned int _id = (id) >> 4 & 0xfff; \ + _id == 0x689; \ + }) + +#define __cpu_is_pxa320(id) \ + ({ \ + unsigned int _id = (id) >> 4 & 0xfff; \ + _id == 0x603 || _id == 0x682; \ + }) + #define cpu_is_pxa21x() \ ({ \ unsigned int id = read_cpuid(CPUID_ID); \ @@ -98,6 +116,53 @@ __cpu_is_pxa27x(id); \ }) +#define cpu_is_pxa300() \ + ({ \ + unsigned int id = read_cpuid(CPUID_ID); \ + __cpu_is_pxa300(id); \ + }) + +#define cpu_is_pxa310() \ + ({ \ + unsigned int id = read_cpuid(CPUID_ID); \ + __cpu_is_pxa310(id); \ + }) + +#define cpu_is_pxa320() \ + ({ \ + unsigned int id = read_cpuid(CPUID_ID); \ + __cpu_is_pxa320(id); \ + }) + +/* + * CPUID Core Generation Bit + * <= 0x2 for pxa21x/pxa25x/pxa26x/pxa27x + * == 0x3 for pxa300/pxa310/pxa320 + */ +#define __cpu_is_pxa2xx(id) \ + ({ \ + unsigned int _id = (id) >> 13 & 0x7; \ + _id <= 0x2; \ + }) + +#define __cpu_is_pxa3xx(id) \ + ({ \ + unsigned int _id = (id) >> 13 & 0x7; \ + _id == 0x3; \ + }) + +#define cpu_is_pxa2xx() \ + ({ \ + unsigned int id = read_cpuid(CPUID_ID); \ + __cpu_is_pxa2xx(id); \ + }) + +#define cpu_is_pxa3xx() \ + ({ \ + unsigned int id = read_cpuid(CPUID_ID); \ + __cpu_is_pxa3xx(id); \ + }) + /* * Handy routine to set GPIO alternate functions */ -- cgit v0.10.2 From 37c2f779a4eabf7c6a39e6f9ded0ec3471ed5995 Mon Sep 17 00:00:00 2001 From: eric miao Date: Wed, 29 Aug 2007 10:15:41 +0100 Subject: [ARM] 4558/1: pxa: remove MACH_TYPE_LUBBOCK assignment and leave it to boot loader since both u-boot and blob support passing MACH_TYPE_LUBBOCK to the kernel, it should be quite safe to remove this Signed-off-by: eric miao Acked-by: Nicolas Pitre Signed-off-by: Russell King diff --git a/arch/arm/boot/compressed/head-xscale.S b/arch/arm/boot/compressed/head-xscale.S index 236bbe5..67ea99e 100644 --- a/arch/arm/boot/compressed/head-xscale.S +++ b/arch/arm/boot/compressed/head-xscale.S @@ -33,10 +33,6 @@ __XScale_start: bic r0, r0, #0x1000 @ clear Icache mcr p15, 0, r0, c1, c0, 0 -#ifdef CONFIG_ARCH_LUBBOCK - mov r7, #MACH_TYPE_LUBBOCK -#endif - #ifdef CONFIG_ARCH_COTULLA_IDP mov r7, #MACH_TYPE_COTULLA_IDP #endif -- cgit v0.10.2 From 30f0b40844e5add7ad879e2f5939ff498f72f3e6 Mon Sep 17 00:00:00 2001 From: eric miao Date: Wed, 29 Aug 2007 10:18:47 +0100 Subject: [ARM] 4559/1: pxa: make PXA_LAST_GPIO a run-time variable This definition produces processor specific code in generic function pxa_gpio_mode(), thus creating inconsistencies for support of pxa25x and pxa27x in a single zImage. As David Brownell suggests, make it a run-time variable and initialize at run-time according to the number of GPIOs on the processor. For now the initialization happens in pxa_init_irq_gpio(), since there is already a parameter for that, besides, this is and MUST be earlier than any subsequent calls to pxa_gpio_mode(). Signed-off-by: eric miao Signed-off-by: Russell King diff --git a/arch/arm/mach-pxa/generic.c b/arch/arm/mach-pxa/generic.c index 1c5413f..eed95eaf 100644 --- a/arch/arm/mach-pxa/generic.c +++ b/arch/arm/mach-pxa/generic.c @@ -71,6 +71,7 @@ EXPORT_SYMBOL(get_memclk_frequency_10khz); /* * Handy function to set GPIO alternate functions */ +int pxa_last_gpio; int pxa_gpio_mode(int gpio_mode) { @@ -79,7 +80,7 @@ int pxa_gpio_mode(int gpio_mode) int fn = (gpio_mode & GPIO_MD_MASK_FN) >> 8; int gafr; - if (gpio > PXA_LAST_GPIO) + if (gpio > pxa_last_gpio) return -EINVAL; local_irq_save(flags); diff --git a/arch/arm/mach-pxa/generic.h b/arch/arm/mach-pxa/generic.h index 5b11741..25bd9bf 100644 --- a/arch/arm/mach-pxa/generic.h +++ b/arch/arm/mach-pxa/generic.h @@ -20,6 +20,7 @@ extern void __init pxa27x_init_irq(void); extern void __init pxa_map_io(void); extern unsigned int get_clk_frequency_khz(int info); +extern int pxa_last_gpio; #define SET_BANK(__nr,__start,__size) \ mi->bank[__nr].start = (__start), \ diff --git a/arch/arm/mach-pxa/irq.c b/arch/arm/mach-pxa/irq.c index ae2ae08..3d95442 100644 --- a/arch/arm/mach-pxa/irq.c +++ b/arch/arm/mach-pxa/irq.c @@ -349,6 +349,8 @@ void __init pxa_init_irq_gpio(int gpio_nr) { int irq, i; + pxa_last_gpio = gpio_nr - 1; + /* clear all GPIO edge detects */ for (i = 0; i < gpio_nr; i += 32) { GFER(i) = 0; diff --git a/include/asm-arm/arch-pxa/irqs.h b/include/asm-arm/arch-pxa/irqs.h index a07fe0f..1bcc763 100644 --- a/include/asm-arm/arch-pxa/irqs.h +++ b/include/asm-arm/arch-pxa/irqs.h @@ -66,12 +66,6 @@ #define IRQ_TO_GPIO_2_x(i) ((i) - PXA_GPIO_IRQ_BASE) #define IRQ_TO_GPIO(i) (((i) < IRQ_GPIO(2)) ? ((i) - IRQ_GPIO0) : IRQ_TO_GPIO_2_x(i)) -#if defined(CONFIG_PXA25x) -#define PXA_LAST_GPIO 84 -#elif defined(CONFIG_PXA27x) -#define PXA_LAST_GPIO 127 -#endif - /* * The next 16 interrupts are for board specific purposes. Since * the kernel can only run on one machine at a time, we can re-use -- cgit v0.10.2 From c95530c7798b760901c5d6212e528b03e323b8ac Mon Sep 17 00:00:00 2001 From: eric miao Date: Wed, 29 Aug 2007 10:22:17 +0100 Subject: [ARM] 4560/1: pxa: move processor specific set_wake logic out of irq.c a function pxa_init_irq_set_wake() was introduced, so that processor specific code could install their own version code setting PFER and PRER registers within pxa_gpio_irq_type are removed, and the edge configuration is postponed to the (*set_wake) and copies the GRER and GFER register, which will always be set up correctly by pxa_gpio_irq_type() Signed-off-by: eric miao Signed-off-by: Russell King diff --git a/arch/arm/mach-pxa/generic.h b/arch/arm/mach-pxa/generic.h index 25bd9bf..2c4fe61 100644 --- a/arch/arm/mach-pxa/generic.h +++ b/arch/arm/mach-pxa/generic.h @@ -15,6 +15,7 @@ extern struct sys_timer pxa_timer; extern void __init pxa_init_irq_low(void); extern void __init pxa_init_irq_high(void); extern void __init pxa_init_irq_gpio(int gpio_nr); +extern void __init pxa_init_irq_set_wake(int (*set_wake)(unsigned int, unsigned int)); extern void __init pxa25x_init_irq(void); extern void __init pxa27x_init_irq(void); extern void __init pxa_map_io(void); diff --git a/arch/arm/mach-pxa/irq.c b/arch/arm/mach-pxa/irq.c index 3d95442..294cc67 100644 --- a/arch/arm/mach-pxa/irq.c +++ b/arch/arm/mach-pxa/irq.c @@ -38,33 +38,11 @@ static void pxa_unmask_low_irq(unsigned int irq) ICMR |= (1 << irq); } -static int pxa_set_wake(unsigned int irq, unsigned int on) -{ - u32 mask; - - switch (irq) { - case IRQ_RTCAlrm: - mask = PWER_RTC; - break; -#ifdef CONFIG_PXA27x - /* REVISIT can handle USBH1, USBH2, USB, MSL, USIM, ... */ -#endif - default: - return -EINVAL; - } - if (on) - PWER |= mask; - else - PWER &= ~mask; - return 0; -} - static struct irq_chip pxa_internal_chip_low = { .name = "SC", .ack = pxa_mask_low_irq, .mask = pxa_mask_low_irq, .unmask = pxa_unmask_low_irq, - .set_wake = pxa_set_wake, }; void __init pxa_init_irq_low(void) @@ -125,26 +103,6 @@ void __init pxa_init_irq_high(void) } #endif -/* Note that if an input/irq line ever gets changed to an output during - * suspend, the relevant PWER, PRER, and PFER bits should be cleared. - */ -#ifdef CONFIG_PXA27x - -/* PXA27x: Various gpios can issue wakeup events. This logic only - * handles the simple cases, not the WEMUX2 and WEMUX3 options - */ -#define PXA27x_GPIO_NOWAKE_MASK \ - ((1 << 8) | (1 << 7) | (1 << 6) | (1 << 5) | (1 << 2)) -#define WAKEMASK(gpio) \ - (((gpio) <= 15) \ - ? ((1 << (gpio)) & ~PXA27x_GPIO_NOWAKE_MASK) \ - : ((gpio == 35) ? (1 << 24) : 0)) -#else - -/* pxa 210, 250, 255, 26x: gpios 0..15 can issue wakeups */ -#define WAKEMASK(gpio) (((gpio) <= 15) ? (1 << (gpio)) : 0) -#endif - /* * PXA GPIO edge detection for IRQs: * IRQs are generated on Falling-Edge, Rising-Edge, or both. @@ -158,11 +116,9 @@ static long GPIO_IRQ_mask[4]; static int pxa_gpio_irq_type(unsigned int irq, unsigned int type) { int gpio, idx; - u32 mask; gpio = IRQ_TO_GPIO(irq); idx = gpio >> 5; - mask = WAKEMASK(gpio); if (type == IRQT_PROBE) { /* Don't mess with enabled GPIOs using preconfigured edges or @@ -182,19 +138,15 @@ static int pxa_gpio_irq_type(unsigned int irq, unsigned int type) if (type & __IRQT_RISEDGE) { /* printk("rising "); */ __set_bit (gpio, GPIO_IRQ_rising_edge); - PRER |= mask; } else { __clear_bit (gpio, GPIO_IRQ_rising_edge); - PRER &= ~mask; } if (type & __IRQT_FALEDGE) { /* printk("falling "); */ __set_bit (gpio, GPIO_IRQ_falling_edge); - PFER |= mask; } else { __clear_bit (gpio, GPIO_IRQ_falling_edge); - PFER &= ~mask; } /* printk("edges\n"); */ @@ -213,29 +165,12 @@ static void pxa_ack_low_gpio(unsigned int irq) GEDR0 = (1 << (irq - IRQ_GPIO0)); } -static int pxa_set_gpio_wake(unsigned int irq, unsigned int on) -{ - int gpio = IRQ_TO_GPIO(irq); - u32 mask = WAKEMASK(gpio); - - if (!mask) - return -EINVAL; - - if (on) - PWER |= mask; - else - PWER &= ~mask; - return 0; -} - - static struct irq_chip pxa_low_gpio_chip = { .name = "GPIO-l", .ack = pxa_ack_low_gpio, .mask = pxa_mask_low_irq, .unmask = pxa_unmask_low_irq, .set_type = pxa_gpio_irq_type, - .set_wake = pxa_set_gpio_wake, }; /* @@ -342,7 +277,6 @@ static struct irq_chip pxa_muxed_gpio_chip = { .mask = pxa_mask_muxed_gpio, .unmask = pxa_unmask_muxed_gpio, .set_type = pxa_gpio_irq_type, - .set_wake = pxa_set_gpio_wake, }; void __init pxa_init_irq_gpio(int gpio_nr) @@ -377,3 +311,13 @@ void __init pxa_init_irq_gpio(int gpio_nr) set_irq_chip(IRQ_GPIO_2_x, &pxa_internal_chip_low); set_irq_chained_handler(IRQ_GPIO_2_x, pxa_gpio_demux_handler); } + +void __init pxa_init_irq_set_wake(int (*set_wake)(unsigned int, unsigned int)) +{ + pxa_internal_chip_low.set_wake = set_wake; +#ifdef CONFIG_PXA27x + pxa_internal_chip_high.set_wake = set_wake; +#endif + pxa_low_gpio_chip.set_wake = set_wake; + pxa_muxed_gpio_chip.set_wake = set_wake; +} diff --git a/arch/arm/mach-pxa/pxa25x.c b/arch/arm/mach-pxa/pxa25x.c index ef40c04..0d6a725 100644 --- a/arch/arm/mach-pxa/pxa25x.c +++ b/arch/arm/mach-pxa/pxa25x.c @@ -227,10 +227,52 @@ static void __init pxa25x_init_pm(void) } #endif +/* PXA25x: supports wakeup from GPIO0..GPIO15 and RTC alarm + */ + +static int pxa25x_set_wake(unsigned int irq, unsigned int on) +{ + int gpio = IRQ_TO_GPIO(irq); + uint32_t gpio_bit, mask = 0; + + if (gpio >= 0 && gpio <= 15) { + gpio_bit = GPIO_bit(gpio); + mask = gpio_bit; + if (on) { + if (GRER(gpio) | gpio_bit) + PRER |= gpio_bit; + else + PRER &= ~gpio_bit; + + if (GFER(gpio) | gpio_bit) + PFER |= gpio_bit; + else + PFER &= ~gpio_bit; + } + goto set_pwer; + } + + if (irq == IRQ_RTCAlrm) { + mask = PWER_RTC; + goto set_pwer; + } + + return -EINVAL; + +set_pwer: + if (on) + PWER |= mask; + else + PWER &=~mask; + + return 0; +} + void __init pxa25x_init_irq(void) { pxa_init_irq_low(); pxa_init_irq_gpio(85); + pxa_init_irq_set_wake(pxa25x_set_wake); } static struct platform_device *pxa25x_devices[] __initdata = { diff --git a/arch/arm/mach-pxa/pxa27x.c b/arch/arm/mach-pxa/pxa27x.c index d193755..2d7fc39 100644 --- a/arch/arm/mach-pxa/pxa27x.c +++ b/arch/arm/mach-pxa/pxa27x.c @@ -306,6 +306,69 @@ static void __init pxa27x_init_pm(void) } #endif +/* PXA27x: Various gpios can issue wakeup events. This logic only + * handles the simple cases, not the WEMUX2 and WEMUX3 options + */ +#define PXA27x_GPIO_NOWAKE_MASK \ + ((1 << 8) | (1 << 7) | (1 << 6) | (1 << 5) | (1 << 2)) +#define WAKEMASK(gpio) \ + (((gpio) <= 15) \ + ? ((1 << (gpio)) & ~PXA27x_GPIO_NOWAKE_MASK) \ + : ((gpio == 35) ? (1 << 24) : 0)) + +static int pxa27x_set_wake(unsigned int irq, unsigned int on) +{ + int gpio = IRQ_TO_GPIO(irq); + uint32_t mask; + + if ((gpio >= 0 && gpio <= 15) || (gpio == 35)) { + if (WAKEMASK(gpio) == 0) + return -EINVAL; + + mask = WAKEMASK(gpio); + + if (on) { + if (GRER(gpio) | GPIO_bit(gpio)) + PRER |= mask; + else + PRER &= ~mask; + + if (GFER(gpio) | GPIO_bit(gpio)) + PFER |= mask; + else + PFER &= ~mask; + } + goto set_pwer; + } + + switch (irq) { + case IRQ_RTCAlrm: + mask = PWER_RTC; + break; + case IRQ_USB: + mask = 1u << 26; + break; + default: + return -EINVAL; + } + +set_pwer: + if (on) + PWER |= mask; + else + PWER &=~mask; + + return 0; +} + +void __init pxa27x_init_irq(void) +{ + pxa_init_irq_low(); + pxa_init_irq_high(); + pxa_init_irq_gpio(128); + pxa_init_irq_set_wake(pxa27x_set_wake); +} + /* * device registration specific to PXA27x. */ @@ -375,13 +438,6 @@ static struct platform_device *devices[] __initdata = { &pxa27x_device_ohci, }; -void __init pxa27x_init_irq(void) -{ - pxa_init_irq_low(); - pxa_init_irq_high(); - pxa_init_irq_gpio(128); -} - static int __init pxa27x_init(void) { int ret = 0; -- cgit v0.10.2 From 7a8be08b1be0bb2a973787bdf888e0a4177cdcd8 Mon Sep 17 00:00:00 2001 From: Greg Ungerer Date: Mon, 30 Jul 2007 02:26:08 +0100 Subject: [ARM] 4532/1: allow configuration of processor ID Allow for configuration of the processor ID for the simplar non-MMU ARM parts. Signed-off-by: Greg Ungerer Signed-off-by: Russell King diff --git a/arch/arm/Kconfig-nommu b/arch/arm/Kconfig-nommu index f087376..901e6df 100644 --- a/arch/arm/Kconfig-nommu +++ b/arch/arm/Kconfig-nommu @@ -26,7 +26,7 @@ config FLASH_SIZE default 0x00400000 config PROCESSOR_ID - hex + hex 'Hard wire the processor ID' default 0x00007700 depends on !CPU_CP15 help -- cgit v0.10.2 From 699a714501f028b1db2bf741111a0df856128899 Mon Sep 17 00:00:00 2001 From: Greg Ungerer Date: Mon, 30 Jul 2007 02:38:47 +0100 Subject: [ARM] 4533/1: AT91x40 timer support Support for the timers in the Atmel AT91x40 family of CPUs. Signed-off-by: Greg Ungerer Acked-by: Andrew Victor Signed-off-by: Russell King diff --git a/arch/arm/mach-at91/at91x40_time.c b/arch/arm/mach-at91/at91x40_time.c new file mode 100644 index 0000000..eddc882 --- /dev/null +++ b/arch/arm/mach-at91/at91x40_time.c @@ -0,0 +1,80 @@ +/* + * arch/arm/mach-at91/at91x40_time.c + * + * (C) Copyright 2007, Greg Ungerer + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * 3 counter/timer units present. + */ +#define AT91_TC_CLK0BASE 0 +#define AT91_TC_CLK1BASE 0x40 +#define AT91_TC_CLK2BASE 0x80 + +static unsigned long at91x40_gettimeoffset(void) +{ + return (at91_sys_read(AT91_TC + AT91_TC_CLK1BASE + AT91_TC_CV) * 1000000 / (AT91X40_MASTER_CLOCK / 128)); +} + +static irqreturn_t at91x40_timer_interrupt(int irq, void *dev_id) +{ + at91_sys_read(AT91_TC + AT91_TC_CLK1BASE + AT91_TC_SR); + timer_tick(); + return IRQ_HANDLED; +} + +static struct irqaction at91x40_timer_irq = { + .name = "at91_tick", + .flags = IRQF_DISABLED | IRQF_TIMER, + .handler = at91x40_timer_interrupt +}; + +void __init at91x40_timer_init(void) +{ + unsigned int v; + + at91_sys_write(AT91_TC + AT91_TC_BCR, 0); + v = at91_sys_read(AT91_TC + AT91_TC_BMR); + v = (v & ~AT91_TC_TC1XC1S) | AT91_TC_TC1XC1S_NONE; + at91_sys_write(AT91_TC + AT91_TC_BMR, v); + + at91_sys_write(AT91_TC + AT91_TC_CLK1BASE + AT91_TC_CCR, AT91_TC_CLKDIS); + at91_sys_write(AT91_TC + AT91_TC_CLK1BASE + AT91_TC_CMR, (AT91_TC_TIMER_CLOCK4 | AT91_TC_CPCTRG)); + at91_sys_write(AT91_TC + AT91_TC_CLK1BASE + AT91_TC_IDR, 0xffffffff); + at91_sys_write(AT91_TC + AT91_TC_CLK1BASE + AT91_TC_RC, (AT91X40_MASTER_CLOCK / 128) / HZ - 1); + at91_sys_write(AT91_TC + AT91_TC_CLK1BASE + AT91_TC_IER, (1<<4)); + + setup_irq(AT91X40_ID_TC1, &at91x40_timer_irq); + + at91_sys_write(AT91_TC + AT91_TC_CLK1BASE + AT91_TC_CCR, (AT91_TC_SWTRG | AT91_TC_CLKEN)); +} + +struct sys_timer at91x40_timer = { + .init = at91x40_timer_init, + .offset = at91x40_gettimeoffset, +}; + -- cgit v0.10.2 From eb1d65aa1b21c9021949c0ece443501b0c135fef Mon Sep 17 00:00:00 2001 From: Greg Ungerer Date: Mon, 30 Jul 2007 02:38:57 +0100 Subject: [ARM] 4534/1: AT91x40 interrupt support Interrupt setup support for the Atmel AT91x40 CPU family. Signed-off-by: Greg Ungerer Acked-by: Andrew Victor Signed-off-by: Russell King diff --git a/arch/arm/mach-at91/at91x40.c b/arch/arm/mach-at91/at91x40.c new file mode 100644 index 0000000..1de121f --- /dev/null +++ b/arch/arm/mach-at91/at91x40.c @@ -0,0 +1,67 @@ +/* + * arch/arm/mach-at91/at91x40.c + * + * (C) Copyright 2007, Greg Ungerer + * Copyright (C) 2005 SAN People + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#include "generic.h" + +/* + * This is used in the gpio code, stub locally. + */ +int clk_enable(struct clk *clk) +{ + return 0; +} + +void __init at91x40_initialize(unsigned long main_clock) +{ + at91_extern_irq = (1 << AT91X40_ID_IRQ0) | (1 << AT91X40_ID_IRQ1) + | (1 << AT91X40_ID_IRQ2); +} + +/* + * The default interrupt priority levels (0 = lowest, 7 = highest). + */ +static unsigned int at91x40_default_irq_priority[NR_AIC_IRQS] __initdata = { + 7, /* Advanced Interrupt Controller (FIQ) */ + 0, /* System Peripherals */ + 0, /* USART 0 */ + 0, /* USART 1 */ + 2, /* Timer Counter 0 */ + 2, /* Timer Counter 1 */ + 2, /* Timer Counter 2 */ + 0, /* Watchdog timer */ + 0, /* Parallel IO Controller A */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* External IRQ0 */ + 0, /* External IRQ1 */ + 0, /* External IRQ2 */ +}; + +void __init at91x40_init_interrupts(unsigned int priority[NR_AIC_IRQS]) +{ + if (!priority) + priority = at91x40_default_irq_priority; + + at91_aic_init(priority); +} + -- cgit v0.10.2 From 9a7e246b53a74ca0eed7c917aa274fbb25f61a68 Mon Sep 17 00:00:00 2001 From: Greg Ungerer Date: Mon, 30 Jul 2007 02:39:02 +0100 Subject: [ARM] 4535/1: AT91x40 function prototypes Prototypes for the at91x40 CPU support functions. Signed-off-by: Greg Ungerer Acked-by: Andrew Victor Signed-off-by: Russell King diff --git a/arch/arm/mach-at91/generic.h b/arch/arm/mach-at91/generic.h index 68ed71a..77d4c0a3 100644 --- a/arch/arm/mach-at91/generic.h +++ b/arch/arm/mach-at91/generic.h @@ -14,6 +14,7 @@ extern void __init at91sam9260_initialize(unsigned long main_clock); extern void __init at91sam9261_initialize(unsigned long main_clock); extern void __init at91sam9263_initialize(unsigned long main_clock); extern void __init at91sam9rl_initialize(unsigned long main_clock); +extern void __init at91x40_initialize(unsigned long main_clock); /* Interrupts */ extern void __init at91rm9200_init_interrupts(unsigned int priority[]); @@ -21,12 +22,14 @@ extern void __init at91sam9260_init_interrupts(unsigned int priority[]); extern void __init at91sam9261_init_interrupts(unsigned int priority[]); extern void __init at91sam9263_init_interrupts(unsigned int priority[]); extern void __init at91sam9rl_init_interrupts(unsigned int priority[]); +extern void __init at91x40_init_interrupts(unsigned int priority[]); extern void __init at91_aic_init(unsigned int priority[]); /* Timer */ struct sys_timer; extern struct sys_timer at91rm9200_timer; extern struct sys_timer at91sam926x_timer; +extern struct sys_timer at91x40_timer; /* Clocks */ extern int __init at91_clock_init(unsigned long main_clock); -- cgit v0.10.2 From d517bd012d866338cdd16884223ee848dfb1e3c0 Mon Sep 17 00:00:00 2001 From: Greg Ungerer Date: Mon, 30 Jul 2007 02:39:10 +0100 Subject: [ARM] 4538/1: Atmel EB01 board support Support for the Atmel EB01 board (based on the Atmel AT91x40 CPU). Signed-off-by: Greg Ungerer Acked-by: Andrew Victor Signed-off-by: Russell King diff --git a/arch/arm/mach-at91/board-eb01.c b/arch/arm/mach-at91/board-eb01.c new file mode 100644 index 0000000..0c1e385 --- /dev/null +++ b/arch/arm/mach-at91/board-eb01.c @@ -0,0 +1,44 @@ +/* + * arch/arm/mach-at91/board-eb01.c + * + * (C) Copyright 2007, Greg Ungerer + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "generic.h" + +static void __init at91eb01_map_io(void) +{ + at91x40_initialize(40000000); +} + +MACHINE_START(AT91EB01, "Atmel AT91 EB01") + /* Maintainer: Greg Ungerer */ + .timer = &at91x40_timer, + .init_irq = at91x40_init_interrupts, + .map_io = at91eb01_map_io, +MACHINE_END + -- cgit v0.10.2 From ea00e30307c9fa4cfe996359982cea2b867b13fc Mon Sep 17 00:00:00 2001 From: Greg Ungerer Date: Mon, 30 Jul 2007 02:39:15 +0100 Subject: [ARM] 4537/1: build support for AT91x40 and EB01 Makefile build support for the Atmel AT91x40 CPU and EB01 board support. Signed-off-by: Greg Ungerer Acked-by: Andrew Victor Signed-off-by: Russell King diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile index a4d80eb..a21f08c 100644 --- a/arch/arm/mach-at91/Makefile +++ b/arch/arm/mach-at91/Makefile @@ -2,11 +2,12 @@ # Makefile for the linux kernel. # -obj-y := clock.o irq.o gpio.o +obj-y := irq.o gpio.o obj-m := obj-n := obj- := +obj-$(CONFIG_AT91_PMC_UNIT) += clock.o obj-$(CONFIG_PM) += pm.o # CPU-specific support @@ -15,6 +16,7 @@ obj-$(CONFIG_ARCH_AT91SAM9260) += at91sam9260.o at91sam926x_time.o at91sam9260_d obj-$(CONFIG_ARCH_AT91SAM9261) += at91sam9261.o at91sam926x_time.o at91sam9261_devices.o obj-$(CONFIG_ARCH_AT91SAM9263) += at91sam9263.o at91sam926x_time.o at91sam9263_devices.o obj-$(CONFIG_ARCH_AT91SAM9RL) += at91sam9rl.o at91sam926x_time.o at91sam9rl_devices.o +obj-$(CONFIG_ARCH_AT91X40) += at91x40.o at91x40_time.o # AT91RM9200 board-specific support obj-$(CONFIG_MACH_ONEARM) += board-1arm.o @@ -27,6 +29,7 @@ obj-$(CONFIG_MACH_KB9200) += board-kb9202.o obj-$(CONFIG_MACH_ATEB9200) += board-eb9200.o obj-$(CONFIG_MACH_KAFA) += board-kafa.o obj-$(CONFIG_MACH_PICOTUX2XX) += board-picotux200.o +obj-$(CONFIG_MACH_AT91EB01) += board-eb01.o # AT91SAM9260 board-specific support obj-$(CONFIG_MACH_AT91SAM9260EK) += board-sam9260ek.o -- cgit v0.10.2 From 9f1ccefe3f74e642515ba58868cfd6924056d9a8 Mon Sep 17 00:00:00 2001 From: Greg Ungerer Date: Mon, 30 Jul 2007 02:39:21 +0100 Subject: [ARM] 4536/1: configure support for AT91x40 and EB01 Configuration support for the AT91x40 CPU and EB01 board. Signed-off-by: Greg Ungerer Acked-by: Andrew Victor Signed-off-by: Russell King diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index a31157f..fd956f1 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -20,8 +20,15 @@ config ARCH_AT91SAM9263 config ARCH_AT91SAM9RL bool "AT91SAM9RL" +config ARCH_AT91X40 + bool "AT91x40" + endchoice +config AT91_PMC_UNIT + bool + default !ARCH_AT91X40 + # ---------------------------------------------------------- if ARCH_AT91RM9200 @@ -169,6 +176,22 @@ endif # ---------------------------------------------------------- +if ARCH_AT91X40 + +comment "AT91X40 Board Type" + +config MACH_AT91EB01 + bool "Atmel AT91EB01 Evaluation Kit" + help + Select this if you are using Atmel's AT91EB01 Evaluation Kit. + It is also a popular target for simulators such as GDB's + ARM simulator (commonly known as the ARMulator) and the + Skyeye simulator. + +endif + +# ---------------------------------------------------------- + comment "AT91 Board Options" config MTD_AT91_DATAFLASH_CARD -- cgit v0.10.2 From bf62e8626963d0002315facb786a8833d404e21e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Tue, 7 Aug 2007 21:08:21 +0100 Subject: [ARM] 4545/1: ns9xxx: simplify irq ack'ing MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Now the drivers are responsible to clear the irq in the respective device, which seems to be the normal thing to do. So the ack'ing of the timer irq moved to time.c. Signed-off-by: Uwe Kleine-König Signed-off-by: Russell King diff --git a/arch/arm/mach-ns9xxx/irq.c b/arch/arm/mach-ns9xxx/irq.c index b8c7b00..24d424e 100644 --- a/arch/arm/mach-ns9xxx/irq.c +++ b/arch/arm/mach-ns9xxx/irq.c @@ -17,33 +17,6 @@ #include "generic.h" -static void ns9xxx_ack_irq_timer(unsigned int irq) -{ - u32 tc = SYS_TC(irq - IRQ_TIMER0); - - /* - * If the timer is programmed to halt on terminal count, the - * timer must be disabled before clearing the interrupt. - */ - if (REGGET(tc, SYS_TCx, REN) == 0) { - REGSET(tc, SYS_TCx, TEN, DIS); - SYS_TC(irq - IRQ_TIMER0) = tc; - } - - REGSET(tc, SYS_TCx, INTC, SET); - SYS_TC(irq - IRQ_TIMER0) = tc; - - REGSET(tc, SYS_TCx, INTC, UNSET); - SYS_TC(irq - IRQ_TIMER0) = tc; -} - -static void (*ns9xxx_ack_irq_functions[NR_IRQS])(unsigned int) = { - [IRQ_TIMER0] = ns9xxx_ack_irq_timer, - [IRQ_TIMER1] = ns9xxx_ack_irq_timer, - [IRQ_TIMER2] = ns9xxx_ack_irq_timer, - [IRQ_TIMER3] = ns9xxx_ack_irq_timer, -}; - static void ns9xxx_mask_irq(unsigned int irq) { /* XXX: better use cpp symbols */ @@ -52,12 +25,6 @@ static void ns9xxx_mask_irq(unsigned int irq) static void ns9xxx_ack_irq(unsigned int irq) { - if (!ns9xxx_ack_irq_functions[irq]) { - printk(KERN_ERR "no ack function for irq %u\n", irq); - BUG(); - } - - ns9xxx_ack_irq_functions[irq](irq); SYS_ISRADDR = 0; } diff --git a/arch/arm/mach-ns9xxx/time.c b/arch/arm/mach-ns9xxx/time.c index b97d0c5..3327d30 100644 --- a/arch/arm/mach-ns9xxx/time.c +++ b/arch/arm/mach-ns9xxx/time.c @@ -24,10 +24,24 @@ static u32 usecs_per_tick; static irqreturn_t ns9xxx_timer_interrupt(int irq, void *dev_id) { + int timerno = irq - IRQ_TIMER0; + u32 tc; + write_seqlock(&xtime_lock); timer_tick(); write_sequnlock(&xtime_lock); + /* clear irq */ + tc = SYS_TC(timerno); + if (REGGET(tc, SYS_TCx, REN) == SYS_TCx_REN_DIS) { + REGSET(tc, SYS_TCx, TEN, DIS); + SYS_TC(timerno) = tc; + } + REGSET(tc, SYS_TCx, INTC, SET); + SYS_TC(timerno) = tc; + REGSET(tc, SYS_TCx, INTC, UNSET); + SYS_TC(timerno) = tc; + return IRQ_HANDLED; } -- cgit v0.10.2 From e16edefe6532c032d86ee802b63972e3a1e953a9 Mon Sep 17 00:00:00 2001 From: Alan Hourihane Date: Sun, 2 Sep 2007 19:59:34 +0100 Subject: [ARM] 4564/1: Add tagged list support for Acorn RiscPC's uncompress code arch_decomp_setup() does not understand the new tagged lists for parameter setup. It's fixed in using the older param struct. This patch adds support for tagged lists and allows the older param struct too. Signed-off-by: Alan Hourihane Signed-off-by: Russell King diff --git a/include/asm-arm/arch-rpc/uncompress.h b/include/asm-arm/arch-rpc/uncompress.h index 06231ed..b8e29ef 100644 --- a/include/asm-arm/arch-rpc/uncompress.h +++ b/include/asm-arm/arch-rpc/uncompress.h @@ -11,9 +11,11 @@ #include #include +#include +#include -int video_num_columns, video_num_lines, video_size_row; -int white, bytes_per_char_h; +int video_size_row; +unsigned char bytes_per_char_h; extern unsigned long con_charconvtable[256]; struct param_struct { @@ -64,6 +66,13 @@ extern __attribute__((pure)) struct param_struct *params(void); #define params (params()) #ifndef STANDALONE_DEBUG +static unsigned long video_num_cols; +static unsigned long video_num_rows; +static unsigned long video_x; +static unsigned long video_y; +static unsigned char bytes_per_char_v; +static int white; + /* * This does not append a newline */ @@ -73,27 +82,27 @@ static void putc(int c) int x,y; char *ptr; - x = params->video_x; - y = params->video_y; + x = video_x; + y = video_y; if (c == '\n') { - if (++y >= video_num_lines) + if (++y >= video_num_rows) y--; } else if (c == '\r') { x = 0; } else { - ptr = VIDMEM + ((y*video_num_columns*params->bytes_per_char_v+x)*bytes_per_char_h); + ptr = VIDMEM + ((y*video_num_cols*bytes_per_char_v+x)*bytes_per_char_h); ll_write_char(ptr, c, white); - if (++x >= video_num_columns) { + if (++x >= video_num_cols) { x = 0; - if ( ++y >= video_num_lines ) { + if ( ++y >= video_num_rows ) { y--; } } } - params->video_x = x; - params->video_y = y; + video_x = x; + video_y = y; } static inline void flush(void) @@ -108,11 +117,44 @@ static void error(char *x); static void arch_decomp_setup(void) { int i; + struct tag *t = (struct tag *)params; + unsigned int nr_pages = 0, page_size = PAGE_SIZE; + + if (t->hdr.tag == ATAG_CORE) + { + for (; t->hdr.size; t = tag_next(t)) + { + if (t->hdr.tag == ATAG_VIDEOTEXT) + { + video_num_rows = t->u.videotext.video_lines; + video_num_cols = t->u.videotext.video_cols; + bytes_per_char_h = t->u.videotext.video_points; + bytes_per_char_v = t->u.videotext.video_points; + video_x = t->u.videotext.x; + video_y = t->u.videotext.y; + } + + if (t->hdr.tag == ATAG_MEM) + { + page_size = PAGE_SIZE; + nr_pages += (t->u.mem.size / PAGE_SIZE); + } + } + } + else + { + nr_pages = params->nr_pages; + page_size = params->page_size; + video_num_rows = params->video_num_rows; + video_num_cols = params->video_num_cols; + video_x = params->video_x; + video_y = params->video_y; + bytes_per_char_h = params->bytes_per_char_h; + bytes_per_char_v = params->bytes_per_char_v; + } + + video_size_row = video_num_cols * bytes_per_char_h; - video_num_lines = params->video_num_rows; - video_num_columns = params->video_num_cols; - bytes_per_char_h = params->bytes_per_char_h; - video_size_row = video_num_columns * bytes_per_char_h; if (bytes_per_char_h == 4) for (i = 0; i < 256; i++) con_charconvtable[i] = @@ -146,7 +188,7 @@ static void arch_decomp_setup(void) white = 7; } - if (params->nr_pages * params->page_size < 4096*1024) error("<4M of mem\n"); + if (nr_pages * page_size < 4096*1024) error("<4M of mem\n"); } #endif -- cgit v0.10.2 From 008d931c45cd39f7b8a8b99926b557b183074858 Mon Sep 17 00:00:00 2001 From: Krzysztof Helt Date: Tue, 4 Sep 2007 17:18:04 +0100 Subject: [ARM] 4565/1: s3c2443: fix section mismatch in irq.c file This patch removes section mismatches related to irq functions. Signed-off-by: Krzysztof Helt Acked-by: Ben Dooks Signed-off-by: Russell King diff --git a/arch/arm/mach-s3c2443/irq.c b/arch/arm/mach-s3c2443/irq.c index 6cd4818..f9ad498 100644 --- a/arch/arm/mach-s3c2443/irq.c +++ b/arch/arm/mach-s3c2443/irq.c @@ -252,7 +252,7 @@ static int __init s3c2443_add_sub(unsigned int base, return 0; } -static int s3c2443_irq_add(struct sys_device *sysdev) +static int __init s3c2443_irq_add(struct sys_device *sysdev) { printk("S3C2443: IRQ Support\n"); @@ -280,7 +280,7 @@ static struct sysdev_driver s3c2443_irq_driver = { .add = s3c2443_irq_add, }; -static int s3c2443_irq_init(void) +static int __init s3c2443_irq_init(void) { return sysdev_driver_register(&s3c2443_sysclass, &s3c2443_irq_driver); } -- cgit v0.10.2 From f2c10d6c669e5b792c48e86da37ec7fde0a2e302 Mon Sep 17 00:00:00 2001 From: Krzysztof Helt Date: Tue, 4 Sep 2007 17:19:33 +0100 Subject: [ARM] 4566/1: s3c24xx: fix dma functions section mismatch This patch removes section mismatches related to DMA functions. Signed-off-by: Krzysztof Helt Acked-by: Ben Dooks Signed-off-by: Russell King diff --git a/arch/arm/mach-s3c2410/dma.c b/arch/arm/mach-s3c2410/dma.c index 80d8373..8f12e85 100644 --- a/arch/arm/mach-s3c2410/dma.c +++ b/arch/arm/mach-s3c2410/dma.c @@ -145,7 +145,7 @@ static struct s3c24xx_dma_order __initdata s3c2410_dma_order = { }, }; -static int s3c2410_dma_add(struct sys_device *sysdev) +static int __init s3c2410_dma_add(struct sys_device *sysdev) { s3c2410_dma_init(); s3c24xx_dma_order_set(&s3c2410_dma_order); diff --git a/arch/arm/mach-s3c2412/dma.c b/arch/arm/mach-s3c2412/dma.c index 4b9425c..53c1d5bb 100644 --- a/arch/arm/mach-s3c2412/dma.c +++ b/arch/arm/mach-s3c2412/dma.c @@ -144,7 +144,7 @@ static struct s3c24xx_dma_selection __initdata s3c2412_dma_sel = { .map_size = ARRAY_SIZE(s3c2412_dma_mappings), }; -static int s3c2412_dma_add(struct sys_device *sysdev) +static int __init s3c2412_dma_add(struct sys_device *sysdev) { s3c2410_dma_init(); return s3c24xx_dma_init_map(&s3c2412_dma_sel); diff --git a/arch/arm/mach-s3c2440/dma.c b/arch/arm/mach-s3c2440/dma.c index f509f06..0b12608 100644 --- a/arch/arm/mach-s3c2440/dma.c +++ b/arch/arm/mach-s3c2440/dma.c @@ -190,7 +190,7 @@ static struct s3c24xx_dma_order __initdata s3c2440_dma_order = { }, }; -static int s3c2440_dma_add(struct sys_device *sysdev) +static int __init s3c2440_dma_add(struct sys_device *sysdev) { s3c2410_dma_init(); s3c24xx_dma_order_set(&s3c2440_dma_order); diff --git a/arch/arm/mach-s3c2443/dma.c b/arch/arm/mach-s3c2443/dma.c index fc3ede8..f6c006d 100644 --- a/arch/arm/mach-s3c2443/dma.c +++ b/arch/arm/mach-s3c2443/dma.c @@ -162,7 +162,7 @@ static struct s3c24xx_dma_selection __initdata s3c2443_dma_sel = { .map_size = ARRAY_SIZE(s3c2443_dma_mappings), }; -static int s3c2443_dma_add(struct sys_device *sysdev) +static int __init s3c2443_dma_add(struct sys_device *sysdev) { s3c24xx_dma_init(6, IRQ_S3C2443_DMA0, 0x100); return s3c24xx_dma_init_map(&s3c2443_dma_sel); diff --git a/arch/arm/plat-s3c24xx/dma.c b/arch/arm/plat-s3c24xx/dma.c index 6d04849..992ca43 100644 --- a/arch/arm/plat-s3c24xx/dma.c +++ b/arch/arm/plat-s3c24xx/dma.c @@ -1372,7 +1372,7 @@ int __init s3c24xx_dma_init(unsigned int channels, unsigned int irq, return ret; } -int s3c2410_dma_init(void) +int __init s3c2410_dma_init(void) { return s3c24xx_dma_init(4, IRQ_DMA0, 0x40); } -- cgit v0.10.2 From 5e802dfab7bbbee1e63607a3e6d1ceb78ec4ceeb Mon Sep 17 00:00:00 2001 From: David Brownell Date: Tue, 31 Jul 2007 01:41:26 +0100 Subject: [ARM] 4539/1: clocksource and clockevents for at91rm9200 GENERIC_TIME and GENERIC_CLOCKEVENTS support for the at91rm9200. - Oneshot mode (used for NO_HZ and high res timers) uses the alarm to emulate a real oneshot timer; the trickiest bit is how to avoid some lowlevel races. Thanks to Remy Bohmer for various fixes to this code. - Tighten up periodic mode support using the PIT. - Streamline reads of the 32KHz counter. Thanks to Marc Pignat for some testing results: the CRTR register has *very* odd behavior. The reread appears to work around stranger glitches than just getting an old clock value (which would quickly self-correct). - Remove the rounding-up of tick_usec to 10.009 msec (32KiHz/100), since that no longer acts correct (time increases too fast). Note that the at91sam9 and at91x40 chips need other solutions, since they don't have the same system timer module. Signed-off-by: David Brownell Acked-by: Bill Gatliff Acked-by:Remy Bohmer Signed-off-by: Russell King diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index fd956f1..05a9f8a 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -7,6 +7,8 @@ choice config ARCH_AT91RM9200 bool "AT91RM9200" + select GENERIC_TIME + select GENERIC_CLOCKEVENTS config ARCH_AT91SAM9260 bool "AT91SAM9260 or AT91SAM9XE" diff --git a/arch/arm/mach-at91/at91rm9200_time.c b/arch/arm/mach-at91/at91rm9200_time.c index a634035..50392ff 100644 --- a/arch/arm/mach-at91/at91rm9200_time.c +++ b/arch/arm/mach-at91/at91rm9200_time.c @@ -19,70 +19,64 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ -#include +#include #include #include -#include -#include -#include +#include -#include -#include #include #include static unsigned long last_crtr; +static u32 irqmask; +static struct clock_event_device clkevt; /* - * The ST_CRTR is updated asynchronously to the master clock. It is therefore - * necessary to read it twice (with the same value) to ensure accuracy. + * The ST_CRTR is updated asynchronously to the master clock ... but + * the updates as seen by the CPU don't seem to be strictly monotonic. + * Waiting until we read the same value twice avoids glitching. */ -static inline unsigned long read_CRTR(void) { +static inline unsigned long read_CRTR(void) +{ unsigned long x1, x2; + x1 = at91_sys_read(AT91_ST_CRTR); do { - x1 = at91_sys_read(AT91_ST_CRTR); x2 = at91_sys_read(AT91_ST_CRTR); - } while (x1 != x2); - + if (x1 == x2) + break; + x1 = x2; + } while (1); return x1; } /* - * Returns number of microseconds since last timer interrupt. Note that interrupts - * will have been disabled by do_gettimeofday() - * 'LATCH' is hwclock ticks (see CLOCK_TICK_RATE in timex.h) per jiffy. - * 'tick' is usecs per jiffy (linux/timex.h). - */ -static unsigned long at91rm9200_gettimeoffset(void) -{ - unsigned long elapsed; - - elapsed = (read_CRTR() - last_crtr) & AT91_ST_ALMV; - - return (unsigned long)(elapsed * (tick_nsec / 1000)) / LATCH; -} - -/* * IRQ handler for the timer. */ static irqreturn_t at91rm9200_timer_interrupt(int irq, void *dev_id) { - if (at91_sys_read(AT91_ST_SR) & AT91_ST_PITS) { /* This is a shared interrupt */ - write_seqlock(&xtime_lock); + u32 sr = at91_sys_read(AT91_ST_SR) & irqmask; - while (((read_CRTR() - last_crtr) & AT91_ST_ALMV) >= LATCH) { - timer_tick(); - last_crtr = (last_crtr + LATCH) & AT91_ST_ALMV; - } + /* simulate "oneshot" timer with alarm */ + if (sr & AT91_ST_ALMS) { + clkevt.event_handler(&clkevt); + return IRQ_HANDLED; + } - write_sequnlock(&xtime_lock); + /* periodic mode should handle delayed ticks */ + if (sr & AT91_ST_PITS) { + u32 crtr = read_CRTR(); + while (((crtr - last_crtr) & AT91_ST_CRTV) >= LATCH) { + last_crtr += LATCH; + clkevt.event_handler(&clkevt); + } return IRQ_HANDLED; } - else - return IRQ_NONE; /* not handled */ + + /* this irq is shared ... */ + return IRQ_NONE; } static struct irqaction at91rm9200_timer_irq = { @@ -91,56 +85,127 @@ static struct irqaction at91rm9200_timer_irq = { .handler = at91rm9200_timer_interrupt }; -void at91rm9200_timer_reset(void) +static cycle_t read_clk32k(void) { - last_crtr = 0; + return read_CRTR(); +} - /* Real time counter incremented every 30.51758 microseconds */ - at91_sys_write(AT91_ST_RTMR, 1); +static struct clocksource clk32k = { + .name = "32k_counter", + .rating = 150, + .read = read_clk32k, + .mask = CLOCKSOURCE_MASK(20), + .shift = 10, + .flags = CLOCK_SOURCE_IS_CONTINUOUS, +}; + +static void +clkevt32k_mode(enum clock_event_mode mode, struct clock_event_device *dev) +{ + /* Disable and flush pending timer interrupts */ + at91_sys_write(AT91_ST_IDR, AT91_ST_PITS | AT91_ST_ALMS); + (void) at91_sys_read(AT91_ST_SR); - /* Set Period Interval timer */ - at91_sys_write(AT91_ST_PIMR, LATCH); + last_crtr = read_CRTR(); + switch (mode) { + case CLOCK_EVT_MODE_PERIODIC: + /* PIT for periodic irqs; fixed rate of 1/HZ */ + irqmask = AT91_ST_PITS; + at91_sys_write(AT91_ST_PIMR, LATCH); + break; + case CLOCK_EVT_MODE_ONESHOT: + /* ALM for oneshot irqs, set by next_event() + * before 32 seconds have passed + */ + irqmask = AT91_ST_ALMS; + at91_sys_write(AT91_ST_RTAR, last_crtr); + break; + case CLOCK_EVT_MODE_SHUTDOWN: + case CLOCK_EVT_MODE_UNUSED: + case CLOCK_EVT_MODE_RESUME: + irqmask = 0; + break; + } + at91_sys_write(AT91_ST_IER, irqmask); +} - /* Clear any pending interrupts */ +static int +clkevt32k_next_event(unsigned long delta, struct clock_event_device *dev) +{ + unsigned long flags; + u32 alm; + int status = 0; + + BUG_ON(delta < 2); + + /* Use "raw" primitives so we behave correctly on RT kernels. */ + raw_local_irq_save(flags); + + /* The alarm IRQ uses absolute time (now+delta), not the relative + * time (delta) in our calling convention. Like all clockevents + * using such "match" hardware, we have a race to defend against. + * + * Our defense here is to have set up the clockevent device so the + * delta is at least two. That way we never end up writing RTAR + * with the value then held in CRTR ... which would mean the match + * wouldn't trigger until 32 seconds later, after CRTR wraps. + */ + alm = read_CRTR(); + + /* Cancel any pending alarm; flush any pending IRQ */ + at91_sys_write(AT91_ST_RTAR, alm); (void) at91_sys_read(AT91_ST_SR); - /* Enable Period Interval Timer interrupt */ - at91_sys_write(AT91_ST_IER, AT91_ST_PITS); + /* Schedule alarm by writing RTAR. */ + alm += delta; + at91_sys_write(AT91_ST_RTAR, alm); + + raw_local_irq_restore(flags); + return status; } +static struct clock_event_device clkevt = { + .name = "at91_tick", + .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, + .shift = 32, + .rating = 150, + .cpumask = CPU_MASK_CPU0, + .set_next_event = clkevt32k_next_event, + .set_mode = clkevt32k_mode, +}; + /* - * Set up timer interrupt. + * ST (system timer) module supports both clockevents and clocksource. */ void __init at91rm9200_timer_init(void) { - /* Disable all timer interrupts */ - at91_sys_write(AT91_ST_IDR, AT91_ST_PITS | AT91_ST_WDOVF | AT91_ST_RTTINC | AT91_ST_ALMS); - (void) at91_sys_read(AT91_ST_SR); /* Clear any pending interrupts */ + /* Disable all timer interrupts, and clear any pending ones */ + at91_sys_write(AT91_ST_IDR, + AT91_ST_PITS | AT91_ST_WDOVF | AT91_ST_RTTINC | AT91_ST_ALMS); + (void) at91_sys_read(AT91_ST_SR); /* Make IRQs happen for the system timer */ setup_irq(AT91_ID_SYS, &at91rm9200_timer_irq); - /* Change the kernel's 'tick' value to 10009 usec. (the default is 10000) */ - tick_usec = (LATCH * 1000000) / CLOCK_TICK_RATE; + /* The 32KiHz "Slow Clock" (tick every 30517.58 nanoseconds) is used + * directly for the clocksource and all clockevents, after adjusting + * its prescaler from the 1 Hz default. + */ + at91_sys_write(AT91_ST_RTMR, 1); - /* Initialize and enable the timer interrupt */ - at91rm9200_timer_reset(); -} + /* Setup timer clockevent, with minimum of two ticks (important!!) */ + clkevt.mult = div_sc(AT91_SLOW_CLOCK, NSEC_PER_SEC, clkevt.shift); + clkevt.max_delta_ns = clockevent_delta2ns(AT91_ST_ALMV, &clkevt); + clkevt.min_delta_ns = clockevent_delta2ns(2, &clkevt) + 1; + clkevt.cpumask = cpumask_of_cpu(0); + clockevents_register_device(&clkevt); -#ifdef CONFIG_PM -static void at91rm9200_timer_suspend(void) -{ - /* disable Period Interval Timer interrupt */ - at91_sys_write(AT91_ST_IDR, AT91_ST_PITS); + /* register clocksource */ + clk32k.mult = clocksource_hz2mult(AT91_SLOW_CLOCK, clk32k.shift); + clocksource_register(&clk32k); } -#else -#define at91rm9200_timer_suspend NULL -#endif struct sys_timer at91rm9200_timer = { .init = at91rm9200_timer_init, - .offset = at91rm9200_gettimeoffset, - .suspend = at91rm9200_timer_suspend, - .resume = at91rm9200_timer_reset, }; -- cgit v0.10.2 From 38598105217f65d21b5f5253c5755af9463c9e9a Mon Sep 17 00:00:00 2001 From: Adrian Bunk Date: Mon, 27 Aug 2007 23:28:17 +0200 Subject: [ARM] "extern inline" -> "static inline" "extern inline" will have different semantics with gcc 4.3. Signed-off-by: Adrian Bunk Signed-off-by: Russell King diff --git a/arch/arm/nwfpe/ARM-gcc.h b/arch/arm/nwfpe/ARM-gcc.h index e659847..436e54a 100644 --- a/arch/arm/nwfpe/ARM-gcc.h +++ b/arch/arm/nwfpe/ARM-gcc.h @@ -68,7 +68,7 @@ a compiler does not support explicit inlining, this macro should be defined to be `static'. ------------------------------------------------------------------------------- */ -#define INLINE extern __inline__ +#define INLINE static inline /* For use as a GCC soft-float library we need some special function names. */ diff --git a/arch/arm/nwfpe/fpa11.inl b/arch/arm/nwfpe/fpa11.inl index 10c3caf..ab8d682 100644 --- a/arch/arm/nwfpe/fpa11.inl +++ b/arch/arm/nwfpe/fpa11.inl @@ -22,13 +22,13 @@ #include "fpa11.h" /* Read and write floating point status register */ -extern __inline__ unsigned int readFPSR(void) +static inline unsigned int readFPSR(void) { FPA11 *fpa11 = GET_FPA11(); return (fpa11->fpsr); } -extern __inline__ void writeFPSR(FPSR reg) +static inline void writeFPSR(FPSR reg) { FPA11 *fpa11 = GET_FPA11(); /* the sysid byte in the status register is readonly */ @@ -36,14 +36,14 @@ extern __inline__ void writeFPSR(FPSR reg) } /* Read and write floating point control register */ -extern __inline__ FPCR readFPCR(void) +static inline FPCR readFPCR(void) { FPA11 *fpa11 = GET_FPA11(); /* clear SB, AB and DA bits before returning FPCR */ return (fpa11->fpcr & ~MASK_RFC); } -extern __inline__ void writeFPCR(FPCR reg) +static inline void writeFPCR(FPCR reg) { FPA11 *fpa11 = GET_FPA11(); fpa11->fpcr &= ~MASK_WFC; /* clear SB, AB and DA bits */ diff --git a/include/asm-arm/arch-ixp23xx/platform.h b/include/asm-arm/arch-ixp23xx/platform.h index 56e16d6..db8aa30 100644 --- a/include/asm-arm/arch-ixp23xx/platform.h +++ b/include/asm-arm/arch-ixp23xx/platform.h @@ -14,17 +14,17 @@ #ifndef __ASSEMBLY__ -extern inline unsigned long ixp2000_reg_read(volatile void *reg) +static inline unsigned long ixp2000_reg_read(volatile void *reg) { return *((volatile unsigned long *)reg); } -extern inline void ixp2000_reg_write(volatile void *reg, unsigned long val) +static inline void ixp2000_reg_write(volatile void *reg, unsigned long val) { *((volatile unsigned long *)reg) = val; } -extern inline void ixp2000_reg_wrb(volatile void *reg, unsigned long val) +static inline void ixp2000_reg_wrb(volatile void *reg, unsigned long val) { *((volatile unsigned long *)reg) = val; } -- cgit v0.10.2 From 4b9ced769177a9e7a96d0e98a09cb5e6b1d506da Mon Sep 17 00:00:00 2001 From: Adrian Bunk Date: Mon, 27 Aug 2007 23:29:21 +0200 Subject: [ARM] omap1/leds-innovator.c: remove dead code This patch removes dead code. Signed-off-by: Adrian Bunk Signed-off-by: Russell King diff --git a/arch/arm/mach-omap1/leds-innovator.c b/arch/arm/mach-omap1/leds-innovator.c index a0cd001..e7835d6 100644 --- a/arch/arm/mach-omap1/leds-innovator.c +++ b/arch/arm/mach-omap1/leds-innovator.c @@ -95,8 +95,5 @@ void innovator_leds_event(led_event_t evt) break; } - if (led_state & LED_STATE_ENABLED) - ; - local_irq_restore(flags); } -- cgit v0.10.2 From 1a10497cfb3ea79bed1470683d4ec5c189febaa6 Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Tue, 28 Aug 2007 09:02:56 +0000 Subject: [ARM] cleanup struct irqaction initializers Signed-off-by: Thomas Gleixner Signed-off-by: Russell King diff --git a/arch/arm/mach-clps7500/core.c b/arch/arm/mach-clps7500/core.c index 4dde34f..986205e 100644 --- a/arch/arm/mach-clps7500/core.c +++ b/arch/arm/mach-clps7500/core.c @@ -193,7 +193,11 @@ static struct irq_chip clps7500_no_chip = { .unmask = cl7500_no_action, }; -static struct irqaction irq_isa = { no_action, 0, CPU_MASK_NONE, "isa", NULL, NULL }; +static struct irqaction irq_isa = { + .handler = no_action, + .mask = CPU_MASK_NONE, + .name = "isa", +}; static void __init clps7500_init_irq(void) { -- cgit v0.10.2 From ec6b1482265ec8430fc38c79205567c3601d8901 Mon Sep 17 00:00:00 2001 From: Mariusz Kozlowski Date: Thu, 20 Sep 2007 20:02:22 +0100 Subject: [ARM] unbalanced parenthesis fix Fix unbalanced parenthesis. Signed-off-by: Mariusz Kozlowski Signed-off-by: Andrew Morton Signed-off-by: Russell King diff --git a/include/asm-arm/arch-sa1100/SA-1101.h b/include/asm-arm/arch-sa1100/SA-1101.h index 527d887..65ca8c7 100644 --- a/include/asm-arm/arch-sa1100/SA-1101.h +++ b/include/asm-arm/arch-sa1100/SA-1101.h @@ -106,7 +106,7 @@ #define SMCR_ColAdrBits( x ) /* col. addr bits 8..11 */ \ (( (x) - 8 ) << FShft (SMCR_DCAC)) #define SMCR_RowAdrBits( x ) /* row addr bits 9..12 */\ - (( (x) - 9 ) << FShft (SMCR_DRAC) + (( (x) - 9 ) << FShft (SMCR_DRAC)) #define SNPR_VFBstart Fld(12,0) /* Video frame buffer addr */ #define SNPR_VFBsize Fld(11,12) /* Video frame buffer size */ @@ -394,7 +394,7 @@ #define VgaStatus (*((volatile Word *) SA1101_p2v (_VgaStatus))) #define VgaInterruptMask (*((volatile Word *) SA1101_p2v (_VgaInterruptMask))) #define VgaPalette (*((volatile Word *) SA1101_p2v (_VgaPalette))) -#define DacControl (*((volatile Word *) SA1101_p2v (_DacControl)) +#define DacControl (*((volatile Word *) SA1101_p2v (_DacControl))) #define VgaTest (*((volatile Word *) SA1101_p2v (_VgaTest))) #define VideoControl_VgaEn 0x00000000 -- cgit v0.10.2 From c1f438f5eec867707022e5f33bec5e91ec12f6e7 Mon Sep 17 00:00:00 2001 From: Catalin Marinas Date: Tue, 25 Sep 2007 15:21:00 +0100 Subject: [ARM] 4581/1: Fix the conditional execution of the NWFPE instructions Starting with ARMv7-A, conditional execution of undefined instructions can trigger an exception even if the condition check fails. This patch modifies the NWFPE support to check the condition before emulating the instruction. Signed-off-by: Catalin Marinas Signed-off-by: Russell King diff --git a/arch/arm/nwfpe/entry.S b/arch/arm/nwfpe/entry.S index 1dc13bc..48bca0d 100644 --- a/arch/arm/nwfpe/entry.S +++ b/arch/arm/nwfpe/entry.S @@ -70,13 +70,24 @@ floating point instructions. GCC attempts to group floating point instructions to allow the emulator to spread the cost of the trap over several floating point instructions. */ +#include + .globl nwfpe_enter nwfpe_enter: mov r4, lr @ save the failure-return addresses mov sl, sp @ we access the registers via 'sl' - ldr r5, [sp, #60] @ get contents of PC; + ldr r5, [sp, #S_PC] @ get contents of PC; + mov r6, r0 @ save the opcode emulate: + ldr r1, [sp, #S_PSR] @ fetch the PSR + bl checkCondition @ check the condition + cmp r0, #0 @ r0 = 0 ==> condition failed + + @ if condition code failed to match, next insn + beq next @ get the next instruction; + + mov r0, r6 @ prepare for EmulateAll() bl EmulateAll @ emulate the instruction cmp r0, #0 @ was emulation successful moveq pc, r4 @ no, return failure @@ -91,18 +102,10 @@ next: teqne r2, #0x0E000000 movne pc, r9 @ return ok if not a fp insn - str r5, [sp, #60] @ update PC copy in regs + str r5, [sp, #S_PC] @ update PC copy in regs mov r0, r6 @ save a copy - ldr r1, [sp, #64] @ fetch the condition codes - bl checkCondition @ check the condition - cmp r0, #0 @ r0 = 0 ==> condition failed - - @ if condition code failed to match, next insn - beq next @ get the next instruction; - - mov r0, r6 @ prepare for EmulateAll() - b emulate @ if r0 != 0, goto EmulateAll + b emulate @ check condition and emulate @ We need to be prepared for the instructions at .Lx1 and .Lx2 @ to fault. Emit the appropriate exception gunk to fix things up. -- cgit v0.10.2 From 180005c4efb76a81fd0abcef4c2412d238eea20c Mon Sep 17 00:00:00 2001 From: Catalin Marinas Date: Tue, 25 Sep 2007 16:49:45 +0100 Subject: [ARM] 4585/1: Correctly identify the CPU architecture version The cpu_architecture() function in arch/arm/kernel/setup.c only works with cores produced by ARM Ltd. The more generic approach is to read the ID_MMFR0 register and check for the VMSA or PMSA version supported. With this patch, the ARM11MPCore would be reported as ARMv7 since its MMU is compatible with ARMv7. Signed-off-by: Catalin Marinas Signed-off-by: Russell King diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c index 4de432e..efac7df 100644 --- a/arch/arm/kernel/setup.c +++ b/arch/arm/kernel/setup.c @@ -304,10 +304,23 @@ int cpu_architecture(void) cpu_arch = (processor_id >> 16) & 7; if (cpu_arch) cpu_arch += CPU_ARCH_ARMv3; - } else { - /* the revised CPUID */ - cpu_arch = ((processor_id >> 12) & 0xf) - 0xb + CPU_ARCH_ARMv6; - } + } else if ((processor_id & 0x000f0000) == 0x000f0000) { + unsigned int mmfr0; + + /* Revised CPUID format. Read the Memory Model Feature + * Register 0 and check for VMSAv7 or PMSAv7 */ + asm("mrc p15, 0, %0, c0, c1, 4" + : "=r" (mmfr0)); + if ((mmfr0 & 0x0000000f) == 0x00000003 || + (mmfr0 & 0x000000f0) == 0x00000030) + cpu_arch = CPU_ARCH_ARMv7; + else if ((mmfr0 & 0x0000000f) == 0x00000002 || + (mmfr0 & 0x000000f0) == 0x00000020) + cpu_arch = CPU_ARCH_ARMv6; + else + cpu_arch = CPU_ARCH_UNKNOWN; + } else + cpu_arch = CPU_ARCH_UNKNOWN; return cpu_arch; } -- cgit v0.10.2 From 987240cc01faf90100ace8f554ac145c2dfb085c Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Sun, 30 Sep 2007 09:56:13 +0100 Subject: [ARM] 4586/1: S3C2412: power register updates Add the INFORM register block which are retained over sleep. Signed-off-by: Ben Dooks Signed-off-by: Russell King diff --git a/include/asm-arm/arch-s3c2410/regs-power.h b/include/asm-arm/arch-s3c2410/regs-power.h index 94ff965..f79987b 100644 --- a/include/asm-arm/arch-s3c2410/regs-power.h +++ b/include/asm-arm/arch-s3c2410/regs-power.h @@ -18,6 +18,11 @@ #define S3C2412_PWRMODECON S3C24XX_PWRREG(0x20) #define S3C2412_PWRCFG S3C24XX_PWRREG(0x24) +#define S3C2412_INFORM0 S3C24XX_PWRREG(0x70) +#define S3C2412_INFORM1 S3C24XX_PWRREG(0x74) +#define S3C2412_INFORM2 S3C24XX_PWRREG(0x78) +#define S3C2412_INFORM3 S3C24XX_PWRREG(0x7C) + #define S3C2412_PWRCFG_BATF_IGNORE (0<<0) #define S3C2412_PWRCFG_BATF_SLEEP (3<<0) #define S3C2412_PWRCFG_BATF_MASK (3<<0) diff --git a/include/asm-arm/arch-s3c2410/regs-s3c2412.h b/include/asm-arm/arch-s3c2410/regs-s3c2412.h index 8ca6a3b..783b18f 100644 --- a/include/asm-arm/arch-s3c2410/regs-s3c2412.h +++ b/include/asm-arm/arch-s3c2410/regs-s3c2412.h @@ -17,5 +17,7 @@ #define S3C2412_SWRST (S3C24XX_VA_CLKPWR + 0x30) #define S3C2412_SWRST_RESET (0x533C2412) +/* see regs-power.h for the other registers in the power block. */ + #endif /* __ASM_ARCH_REGS_S3C2412_H */ -- cgit v0.10.2 From 6c729af9f05c7aae06ce89a27f91e24b1482544d Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Sun, 30 Sep 2007 09:59:15 +0100 Subject: [ARM] 4587/1: S3C24XX: Add magic number before resume code Add a magic number before the resume code so that a bootloader can check that there is an image to resume to. Signed-off-by: Ben Dooks Signed-off-by: Russell King diff --git a/arch/arm/plat-s3c24xx/sleep.S b/arch/arm/plat-s3c24xx/sleep.S index d47113b..a646cbe 100644 --- a/arch/arm/plat-s3c24xx/sleep.S +++ b/arch/arm/plat-s3c24xx/sleep.S @@ -96,6 +96,14 @@ resume_with_mmu: s3c2410_sleep_save_phys: .word 0 + + /* sleep magic, to allow the bootloader to check for an valid + * image to resume to. Must be the first word before the + * s3c2410_cpu_resume entry. + */ + + .word 0x2bedf00d + /* s3c2410_cpu_resume * * resume code entry for bootloader to call -- cgit v0.10.2 From 700dc2b5374cf142da8a2837d162a7b26a2946fc Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Sun, 30 Sep 2007 10:00:10 +0100 Subject: [ARM] 4588/1: S3C2412: Sleep configuration updates Make the S3C2412 sleep configuration clearer. Signed-off-by: Ben Dooks Signed-off-by: Russell King diff --git a/include/asm-arm/arch-s3c2410/regs-gpio.h b/include/asm-arm/arch-s3c2410/regs-gpio.h index dea578b..b693158 100644 --- a/include/asm-arm/arch-s3c2410/regs-gpio.h +++ b/include/asm-arm/arch-s3c2410/regs-gpio.h @@ -1140,10 +1140,16 @@ /* definitions for each pin bit */ #define S3C2412_SLPCON_LOW(x) ( 0x00 << ((x) * 2)) -#define S3C2412_SLPCON_HI(x) ( 0x01 << ((x) * 2)) +#define S3C2412_SLPCON_HIGH(x) ( 0x01 << ((x) * 2)) #define S3C2412_SLPCON_IN(x) ( 0x02 << ((x) * 2)) -#define S3C2412_SLPCON_PDWN(x) ( 0x03 << ((x) * 2)) +#define S3C2412_SLPCON_PULL(x) ( 0x03 << ((x) * 2)) +#define S3C2412_SLPCON_EINT(x) ( 0x02 << ((x) * 2)) /* only IRQ pins */ #define S3C2412_SLPCON_MASK(x) ( 0x03 << ((x) * 2)) +#define S3C2412_SLPCON_ALL_LOW (0x0) +#define S3C2412_SLPCON_ALL_HIGH (0x11111111 | 0x44444444) +#define S3C2412_SLPCON_ALL_IN (0x22222222 | 0x88888888) +#define S3C2412_SLPCON_ALL_PULL (0x33333333) + #endif /* __ASM_ARCH_REGS_GPIO_H */ -- cgit v0.10.2 From 883042d6ea31fcaffb0b8763cadfbcb2862ebc48 Mon Sep 17 00:00:00 2001 From: Russell King Date: Sun, 30 Sep 2007 17:37:24 +0100 Subject: [ARM] Add fallocate syscall entry Signed-off-by: Russell King diff --git a/arch/arm/kernel/calls.S b/arch/arm/kernel/calls.S index a98d0c9..cecf658 100644 --- a/arch/arm/kernel/calls.S +++ b/arch/arm/kernel/calls.S @@ -361,6 +361,7 @@ CALL(sys_signalfd) /* 350 */ CALL(sys_timerfd) CALL(sys_eventfd) + CALL(sys_fallocate) #ifndef syscalls_counted .equ syscalls_padding, ((NR_syscalls + 3) & ~3) - NR_syscalls #define syscalls_counted diff --git a/include/asm-arm/unistd.h b/include/asm-arm/unistd.h index d327b25..88e868b 100644 --- a/include/asm-arm/unistd.h +++ b/include/asm-arm/unistd.h @@ -378,6 +378,7 @@ #define __NR_signalfd (__NR_SYSCALL_BASE+349) #define __NR_timerfd (__NR_SYSCALL_BASE+350) #define __NR_eventfd (__NR_SYSCALL_BASE+351) +#define __NR_fallocate (__NR_SYSCALL_BASE+352) /* * The following SWIs are ARM private. -- cgit v0.10.2 From cba774ae8731699d39cbaf979aa4a0b351045924 Mon Sep 17 00:00:00 2001 From: Russell King Date: Sun, 30 Sep 2007 17:39:05 +0100 Subject: [ARM] Add rtc-cmos driver for ISA-based footbridge platforms ... but the rtc-cmos is rather broken; if PNP is enabled, it assumes that we have ACPI (!) which is quite bogus on these platforms - which may have ISAPNP but not ACPI. Something to be solved in the future. Signed-off-by: Russell King diff --git a/arch/arm/mach-footbridge/isa.c b/arch/arm/mach-footbridge/isa.c index 28846c7..725a219 100644 --- a/arch/arm/mach-footbridge/isa.c +++ b/arch/arm/mach-footbridge/isa.c @@ -12,6 +12,39 @@ #include +static struct resource rtc_resources[] = { + [0] = { + .start = 0x70, + .end = 0x73, + .flags = IORESOURCE_IO, + }, + [1] = { + .start = IRQ_ISA_RTC_ALARM, + .end = IRQ_ISA_RTC_ALARM, + .flags = IORESOURCE_IRQ, + } +}; + +static struct platform_device rtc_device = { + .name = "rtc_cmos", + .id = -1, + .resource = rtc_resources, + .num_resources = ARRAY_SIZE(rtc_resources), +}; + +static struct resource serial_resources[] = { + [0] = { + .start = 0x3f8, + .end = 0x3ff, + .flags = IORESOURCE_IO, + }, + [1] = { + .start = 0x2f8, + .end = 0x2ff, + .flags = IORESOURCE_IO, + }, +}; + static struct plat_serial8250_port serial_platform_data[] = { { .iobase = 0x3f8, @@ -38,11 +71,21 @@ static struct platform_device serial_device = { .dev = { .platform_data = serial_platform_data, }, + .resource = serial_resources, + .num_resources = ARRAY_SIZE(serial_resources), }; static int __init footbridge_isa_init(void) { - return platform_device_register(&serial_device); + int err; + + err = platform_device_register(&rtc_device); + if (err) + printk(KERN_ERR "Unable to register RTC device: %d\n", err); + err = platform_device_register(&serial_device); + if (err) + printk(KERN_ERR "Unable to register serial device: %d\n", err); + return 0; } arch_initcall(footbridge_isa_init); -- cgit v0.10.2 From ff9e76aaba13f6f6bae31c9ac2aa2a50f5cdd801 Mon Sep 17 00:00:00 2001 From: Rob Landley Date: Sun, 30 Sep 2007 22:23:01 -0500 Subject: [ARM] Add missing entries to Documentation/arm/00-INDEX Add several missing entries to Documentation/arm/00-INDEX Signed-off-by: Rob Landley Signed-off-by: Russell King diff --git a/Documentation/arm/00-INDEX b/Documentation/arm/00-INDEX index 2c6a3b3..82e418d 100644 --- a/Documentation/arm/00-INDEX +++ b/Documentation/arm/00-INDEX @@ -4,19 +4,29 @@ Booting - requirements for booting Interrupts - ARM Interrupt subsystem documentation +IXP2000 + - Release Notes for Linux on Intel's IXP2000 Network Processor Netwinder - Netwinder specific documentation +Porting + - Symbol definitions for porting Linux to a new ARM machine. +Setup + - Kernel initialization parameters on ARM Linux README - General ARM documentation -SA1100 +SA1100/ - SA1100 documentation -XScale - - XScale documentation -empeg - - Empeg documentation +Samsung-S3C24XX + - S3C24XX ARM Linux Overview +Sharp-LH + - Linux on Sharp LH79524 and LH7A40X System On a Chip (SOC) +VFP/ + - Release notes for Linux Kernel Vector Floating Point support code +empeg/ + - Ltd's Empeg MP3 Car Audio Player mem_alignment - alignment abort handler documentation memory.txt - description of the virtual memory layout -nwfpe +nwfpe/ - NWFPE floating point emulator documentation -- cgit v0.10.2 From ba7d850a02c7c3357ec488776405470534e7ccf8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Sun, 30 Sep 2007 20:34:41 +0100 Subject: [ARM] 4589/1: ns9xxx: acknowledge IRQ_EXT2 in the demux routine for FPGA irqs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The FPGA on the a9m9750dev board interrupts the CPU via EXT2. So to acknowledge any FPGA interrupt IRQ_EXT2 must be acknowledged. Signed-off-by: Uwe Kleine-König Signed-off-by: Russell King diff --git a/arch/arm/mach-ns9xxx/board-a9m9750dev.c b/arch/arm/mach-ns9xxx/board-a9m9750dev.c index 925048e..88d1f7e 100644 --- a/arch/arm/mach-ns9xxx/board-a9m9750dev.c +++ b/arch/arm/mach-ns9xxx/board-a9m9750dev.c @@ -70,15 +70,20 @@ static void a9m9750dev_fpga_demux_handler(unsigned int irq, { int stat = FPGA_ISR; + desc->chip->mask_ack(irq); + while (stat != 0) { int irqno = fls(stat) - 1; + struct irq_desc *fpgadesc; stat &= ~(1 << irqno); - desc = irq_desc + FPGA_IRQ(irqno); + fpgadesc = irq_desc + FPGA_IRQ(irqno); - desc_handle_irq(FPGA_IRQ(irqno), desc); + desc_handle_irq(FPGA_IRQ(irqno), fpgadesc); } + + desc->chip->unmask(irq); } void __init board_a9m9750dev_init_irq(void) -- cgit v0.10.2 From 689f2a01e68c0033f59055dd816ff27dc51f9dcc Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Sun, 30 Sep 2007 20:35:09 +0100 Subject: [ARM] 4590/1: ns9xxx: add gpio handling functions MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This implementation conforms to the general GPIO API introduced in 2.6.21. This patch was signed-of by David Brownell before I exported the functions using EXPORT_SYMBOL. Signed-off-by: Uwe Kleine-König Signed-off-by: Russell King diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 691aae3..6acc59d 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -318,6 +318,7 @@ config ARCH_KS8695 config ARCH_NS9XXX bool "NetSilicon NS9xxx" + select GENERIC_GPIO help Say Y here if you intend to run this kernel on a NetSilicon NS9xxx System. diff --git a/arch/arm/mach-ns9xxx/Makefile b/arch/arm/mach-ns9xxx/Makefile index 4476411..6fb82b8 100644 --- a/arch/arm/mach-ns9xxx/Makefile +++ b/arch/arm/mach-ns9xxx/Makefile @@ -1,4 +1,4 @@ -obj-y := irq.o time.o generic.o +obj-y := irq.o time.o generic.o gpio.o obj-$(CONFIG_MACH_CC9P9360DEV) += mach-cc9p9360dev.o obj-$(CONFIG_MACH_CC9P9360JS) += mach-cc9p9360js.o diff --git a/arch/arm/mach-ns9xxx/gpio.c b/arch/arm/mach-ns9xxx/gpio.c new file mode 100644 index 0000000..87b872f --- /dev/null +++ b/arch/arm/mach-ns9xxx/gpio.c @@ -0,0 +1,184 @@ +/* + * arch/arm/mach-ns9xxx/gpio.c + * + * Copyright (C) 2006 by Digi International Inc. + * All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published by + * the Free Software Foundation. + */ +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#if defined(CONFIG_PROCESSOR_NS9360) +#define GPIO_MAX 72 +#elif defined(CONFIG_PROCESSOR_NS9750) +#define GPIO_MAX 49 +#endif + +/* protects BBU_GCONFx and BBU_GCTRLx */ +static spinlock_t gpio_lock = __SPIN_LOCK_UNLOCKED(gpio_lock); + +/* only access gpiores with atomic ops */ +static DECLARE_BITMAP(gpiores, GPIO_MAX); + +static inline int ns9xxx_valid_gpio(unsigned gpio) +{ +#if defined(CONFIG_PROCESSOR_NS9360) + if (processor_is_ns9360()) + return gpio <= 72; + else +#endif +#if defined(CONFIG_PROCESSOR_NS9750) + if (processor_is_ns9750()) + return gpio <= 49; + else +#endif + BUG(); +} + +static inline volatile u32 *ns9xxx_gpio_get_gconfaddr(unsigned gpio) +{ + if (gpio < 56) + return &BBU_GCONFb1(gpio / 8); + else + /* + * this could be optimised away on + * ns9750 only builds, but it isn't ... + */ + return &BBU_GCONFb2((gpio - 56) / 8); +} + +static inline volatile u32 *ns9xxx_gpio_get_gctrladdr(unsigned gpio) +{ + if (gpio < 32) + return &BBU_GCTRL1; + else if (gpio < 64) + return &BBU_GCTRL2; + else + /* this could be optimised away on ns9750 only builds */ + return &BBU_GCTRL3; +} + +static inline volatile u32 *ns9xxx_gpio_get_gstataddr(unsigned gpio) +{ + if (gpio < 32) + return &BBU_GSTAT1; + else if (gpio < 64) + return &BBU_GSTAT2; + else + /* this could be optimised away on ns9750 only builds */ + return &BBU_GSTAT3; +} + +int gpio_request(unsigned gpio, const char *label) +{ + if (likely(ns9xxx_valid_gpio(gpio))) + return test_and_set_bit(gpio, gpiores) ? -EBUSY : 0; + else + return -EINVAL; +} +EXPORT_SYMBOL(gpio_request); + +void gpio_free(unsigned gpio) +{ + clear_bit(gpio, gpiores); + return; +} +EXPORT_SYMBOL(gpio_free); + +/* + * each gpio can serve for 4 different purposes [0..3]. These are called + * "functions" and passed in the parameter func. Functions 0-2 are always some + * special things, function 3 is GPIO. If func == 3 dir specifies input or + * output, and with inv you can enable an inverter (independent of func). + */ +static int __ns9xxx_gpio_configure(unsigned gpio, int dir, int inv, int func) +{ + volatile u32 *conf = ns9xxx_gpio_get_gconfaddr(gpio); + u32 confval; + unsigned long flags; + + spin_lock_irqsave(&gpio_lock, flags); + + confval = *conf; + REGSETIM_IDX(confval, BBU_GCONFx, DIR, gpio & 7, dir); + REGSETIM_IDX(confval, BBU_GCONFx, INV, gpio & 7, inv); + REGSETIM_IDX(confval, BBU_GCONFx, FUNC, gpio & 7, func); + *conf = confval; + + spin_unlock_irqrestore(&gpio_lock, flags); + + return 0; +} + +int ns9xxx_gpio_configure(unsigned gpio, int inv, int func) +{ + if (likely(ns9xxx_valid_gpio(gpio))) { + if (func == 3) { + printk(KERN_WARNING "use gpio_direction_input " + "or gpio_direction_output\n"); + return -EINVAL; + } else + return __ns9xxx_gpio_configure(gpio, 0, inv, func); + } else + return -EINVAL; +} +EXPORT_SYMBOL(ns9xxx_gpio_configure); + +int gpio_direction_input(unsigned gpio) +{ + if (likely(ns9xxx_valid_gpio(gpio))) { + return __ns9xxx_gpio_configure(gpio, 0, 0, 3); + } else + return -EINVAL; +} +EXPORT_SYMBOL(gpio_direction_input); + +int gpio_direction_output(unsigned gpio, int value) +{ + if (likely(ns9xxx_valid_gpio(gpio))) { + gpio_set_value(gpio, value); + + return __ns9xxx_gpio_configure(gpio, 1, 0, 3); + } else + return -EINVAL; +} +EXPORT_SYMBOL(gpio_direction_output); + +int gpio_get_value(unsigned gpio) +{ + volatile u32 *stat = ns9xxx_gpio_get_gstataddr(gpio); + int ret; + + ret = 1 & (*stat >> (gpio & 31)); + + return ret; +} +EXPORT_SYMBOL(gpio_get_value); + +void gpio_set_value(unsigned gpio, int value) +{ + volatile u32 *ctrl = ns9xxx_gpio_get_gctrladdr(gpio); + unsigned long flags; + + spin_lock_irqsave(&gpio_lock, flags); + + if (value) + *ctrl |= 1 << (gpio & 31); + else + *ctrl &= ~(1 << (gpio & 31)); + + spin_unlock_irqrestore(&gpio_lock, flags); +} +EXPORT_SYMBOL(gpio_set_value); diff --git a/include/asm-arm/arch-ns9xxx/gpio.h b/include/asm-arm/arch-ns9xxx/gpio.h new file mode 100644 index 0000000..adbca08 --- /dev/null +++ b/include/asm-arm/arch-ns9xxx/gpio.h @@ -0,0 +1,47 @@ +/* + * include/asm-arm/arch-ns9xxx/gpio.h + * + * Copyright (C) 2007 by Digi International Inc. + * All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published by + * the Free Software Foundation. +*/ +#ifndef __ASM_ARCH_GPIO_H +#define __ASM_ARCH_GPIO_H + +#include + +int gpio_request(unsigned gpio, const char *label); + +void gpio_free(unsigned gpio); + +int ns9xxx_gpio_configure(unsigned gpio, int inv, int func); + +int gpio_direction_input(unsigned gpio); + +int gpio_direction_output(unsigned gpio, int value); + +int gpio_get_value(unsigned gpio); + +void gpio_set_value(unsigned gpio, int value); + +/* + * ns9xxx can use gpio pins to trigger an irq, but it's not generic + * enough to be supported by the gpio_to_irq/irq_to_gpio interface + */ +static inline int gpio_to_irq(unsigned gpio) +{ + return -EINVAL; +} + +static inline int irq_to_gpio(unsigned irq) +{ + return -EINVAL; +} + +/* get the cansleep() stubs */ +#include + +#endif /* ifndef __ASM_ARCH_GPIO_H */ -- cgit v0.10.2 From f02e579558cf2aba06ecc7d4515661286b60f411 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Sun, 30 Sep 2007 20:35:27 +0100 Subject: [ARM] 4591/1: ns9xxx: simplify REGSET, REGGET and introduce ..._IDX variants MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The semantic of the REGSET macros didn't change, but hopefully it's more obvious as it's now. REGGET is changed to return the unshifted value, analogous to REGSET. REGGETIM behaves as REGGET before. All callers changed. ..._IDX is used to work with registers that need a parameter like BBU_GCONFb1. Signed-off-by: Uwe Kleine-König Signed-off-by: Russell King diff --git a/include/asm-arm/arch-ns9xxx/clock.h b/include/asm-arm/arch-ns9xxx/clock.h index bf30cbd..90604d4 100644 --- a/include/asm-arm/arch-ns9xxx/clock.h +++ b/include/asm-arm/arch-ns9xxx/clock.h @@ -46,8 +46,8 @@ static inline u32 ns9xxx_systemclock(void) * * Fine. */ - return CRYSTAL * (REGGET(pll, SYS_PLL, ND) + 1) - >> REGGET(pll, SYS_PLL, FS); + return CRYSTAL * (REGGETIM(pll, SYS_PLL, ND) + 1) + >> REGGETIM(pll, SYS_PLL, FS); } static inline u32 ns9xxx_cpuclock(void) __attribute__((const)); diff --git a/include/asm-arm/arch-ns9xxx/hardware.h b/include/asm-arm/arch-ns9xxx/hardware.h index 2560055..b5d66f9 100644 --- a/include/asm-arm/arch-ns9xxx/hardware.h +++ b/include/asm-arm/arch-ns9xxx/hardware.h @@ -27,9 +27,11 @@ #define io_v2p(x) ((((x) & 0x0f000000) << 4) \ + ((x) & 0x00ffffff)) +#define __REGSHIFT(mask) ((mask) & (-(mask))) + #define __REGBIT(bit) ((u32)1 << (bit)) #define __REGBITS(hbit, lbit) ((((u32)1 << ((hbit) - (lbit) + 1)) - 1) << (lbit)) -#define __REGVAL(mask, value) (((value) * ((mask) & (-(mask))) & (mask))) +#define __REGVAL(mask, value) (((value) * __REGSHIFT(mask)) & (mask)) #ifndef __ASSEMBLY__ @@ -39,21 +41,36 @@ # define __REGB(x) (*((volatile u8 *)io_p2v((x)))) # define __REGB2(x) (*((volatile u8 *)io_p2v((x)) + (y))) +# define __REGSET(var, field, value) \ + ((var) = (((var) & ~((field) & ~(value))) | (value))) + # define REGSET(var, reg, field, value) \ - ((var) = (((var) \ - & ~(reg ## _ ## field & \ - ~ reg ## _ ## field ## _ ## value)) \ - | (reg ## _ ## field ## _ ## value))) + __REGSET(var, reg ## _ ## field, reg ## _ ## field ## _ ## value) + +# define REGSET_IDX(var, reg, field, idx, value) \ + __REGSET(var, reg ## _ ## field((idx)), reg ## _ ## field ## _ ## value((idx))) # define REGSETIM(var, reg, field, value) \ - ((var) = (((var) \ - & ~(reg ## _ ## field & \ - ~(__REGVAL(reg ## _ ## field, value)))) \ - | (__REGVAL(reg ## _ ## field, value)))) + __REGSET(var, reg ## _ ## field, __REGVAL(reg ## _ ## field, (value))) + +# define REGSETIM_IDX(var, reg, field, idx, value) \ + __REGSET(var, reg ## _ ## field((idx)), __REGVAL(reg ## _ ## field((idx)), (value))) + +# define __REGGET(var, field) \ + (((var) & (field))) # define REGGET(var, reg, field) \ - ((var & (reg ## _ ## field)) / \ - ((reg ## _ ## field) & (-(reg ## _ ## field)))) + __REGGET(var, reg ## _ ## field) + +# define REGGET_IDX(var, reg, field, idx) \ + __REGGET(var, reg ## _ ## field((idx))) + +# define REGGETIM(var, reg, field) \ + __REGGET(var, reg ## _ ## field) / __REGSHIFT(reg ## _ ## field) + +# define REGGETIM_IDX(var, reg, field, idx) \ + __REGGET(var, reg ## _ ## field((idx))) / \ + __REGSHIFT(reg ## _ ## field((idx))) #else -- cgit v0.10.2 From cef5975d453bbc1bbf29ceb7d80749feebc22a74 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Sun, 30 Sep 2007 20:35:48 +0100 Subject: [ARM] 4592/1: ns9xxx: clocksource driver MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Uwe Kleine-König Signed-off-by: Russell King diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 6acc59d..a43a814 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -319,6 +319,7 @@ config ARCH_KS8695 config ARCH_NS9XXX bool "NetSilicon NS9xxx" select GENERIC_GPIO + select GENERIC_TIME help Say Y here if you intend to run this kernel on a NetSilicon NS9xxx System. diff --git a/arch/arm/mach-ns9xxx/time.c b/arch/arm/mach-ns9xxx/time.c index 3327d30..d293455 100644 --- a/arch/arm/mach-ns9xxx/time.c +++ b/arch/arm/mach-ns9xxx/time.c @@ -11,6 +11,9 @@ #include #include #include +#include +#include + #include #include #include @@ -18,8 +21,7 @@ #include "generic.h" #define TIMERCLOCKSELECT 64 - -static u32 usecs_per_tick; +#define TIMER_CLOCKSOURCE 1 static irqreturn_t ns9xxx_timer_interrupt(int irq, void *dev_id) @@ -45,39 +47,30 @@ ns9xxx_timer_interrupt(int irq, void *dev_id) return IRQ_HANDLED; } -static unsigned long ns9xxx_timer_gettimeoffset(void) -{ - /* return the microseconds which have passed since the last interrupt - * was _serviced_. That is, if an interrupt is pending or the counter - * reloads, return one period more. */ - - u32 counter1 = SYS_TR(0); - int pending = SYS_ISR & (1 << IRQ_TIMER0); - u32 counter2 = SYS_TR(0); - u32 elapsed; - - if (pending || counter2 > counter1) - elapsed = 2 * SYS_TRC(0) - counter2; - else - elapsed = SYS_TRC(0) - counter1; - - return (elapsed * usecs_per_tick) >> 16; - -} - static struct irqaction ns9xxx_timer_irq = { .name = "NS9xxx Timer Tick", .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, .handler = ns9xxx_timer_interrupt, }; +static cycle_t ns9xxx_clocksource_read(void) +{ + return SYS_TR(TIMER_CLOCKSOURCE); +} + +static struct clocksource ns9xxx_clocksource = { + .name = "ns9xxx-timer" __stringify(TIMER_CLOCKSOURCE), + .rating = 300, + .read = ns9xxx_clocksource_read, + .mask = CLOCKSOURCE_MASK(32), + .shift = 20, + .flags = CLOCK_SOURCE_IS_CONTINUOUS, +}; + static void __init ns9xxx_timer_init(void) { int tc; - usecs_per_tick = - SH_DIV(1000000 * TIMERCLOCKSELECT, ns9xxx_cpuclock(), 16); - /* disable timer */ if ((tc = SYS_TC(0)) & SYS_TCx_TEN) SYS_TC(0) = tc & ~SYS_TCx_TEN; @@ -94,9 +87,32 @@ static void __init ns9xxx_timer_init(void) SYS_TC(0) = tc; setup_irq(IRQ_TIMER0, &ns9xxx_timer_irq); + + tc = SYS_TC(TIMER_CLOCKSOURCE); + if (REGGET(tc, SYS_TCx, TEN)) { + REGSET(tc, SYS_TCx, TEN, DIS); + SYS_TC(TIMER_CLOCKSOURCE) = tc; + } + + SYS_TRC(TIMER_CLOCKSOURCE) = 0; + + REGSET(tc, SYS_TCx, TEN, EN); + REGSET(tc, SYS_TCx, TDBG, STOP); + REGSET(tc, SYS_TCx, TLCS, CPU); + REGSET(tc, SYS_TCx, TM, IEE); + REGSET(tc, SYS_TCx, INTS, DIS); + REGSET(tc, SYS_TCx, UDS, UP); + REGSET(tc, SYS_TCx, TSZ, 32); + REGSET(tc, SYS_TCx, REN, EN); + + SYS_TC(TIMER_CLOCKSOURCE) = tc; + + ns9xxx_clocksource.mult = clocksource_hz2mult(ns9xxx_cpuclock(), + ns9xxx_clocksource.shift); + + clocksource_register(&ns9xxx_clocksource); } struct sys_timer ns9xxx_timer = { .init = ns9xxx_timer_init, - .offset = ns9xxx_timer_gettimeoffset, }; -- cgit v0.10.2 From c0bb87f7b8a145b56d45484713e1b1f37ce7e626 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Sun, 30 Sep 2007 20:36:00 +0100 Subject: [ARM] 4593/1: ns9xxx: implement generic clockevents MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Uwe Kleine-König Signed-off-by: Russell King diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index a43a814..4b984b1 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -320,6 +320,7 @@ config ARCH_NS9XXX bool "NetSilicon NS9xxx" select GENERIC_GPIO select GENERIC_TIME + select GENERIC_CLOCKEVENTS help Say Y here if you intend to run this kernel on a NetSilicon NS9xxx System. diff --git a/arch/arm/mach-ns9xxx/time.c b/arch/arm/mach-ns9xxx/time.c index d293455..6f29515 100644 --- a/arch/arm/mach-ns9xxx/time.c +++ b/arch/arm/mach-ns9xxx/time.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include @@ -20,18 +21,87 @@ #include #include "generic.h" -#define TIMERCLOCKSELECT 64 -#define TIMER_CLOCKSOURCE 1 +#define TIMER_CLOCKSOURCE 0 +#define TIMER_CLOCKEVENT 1 +static u32 latch; -static irqreturn_t -ns9xxx_timer_interrupt(int irq, void *dev_id) +static cycle_t ns9xxx_clocksource_read(void) +{ + return SYS_TR(TIMER_CLOCKSOURCE); +} + +static struct clocksource ns9xxx_clocksource = { + .name = "ns9xxx-timer" __stringify(TIMER_CLOCKSOURCE), + .rating = 300, + .read = ns9xxx_clocksource_read, + .mask = CLOCKSOURCE_MASK(32), + .shift = 20, + .flags = CLOCK_SOURCE_IS_CONTINUOUS, +}; + +static void ns9xxx_clockevent_setmode(enum clock_event_mode mode, + struct clock_event_device *clk) +{ + u32 tc = SYS_TC(TIMER_CLOCKEVENT); + + switch(mode) { + case CLOCK_EVT_MODE_PERIODIC: + SYS_TRC(TIMER_CLOCKEVENT) = latch; + REGSET(tc, SYS_TCx, REN, EN); + REGSET(tc, SYS_TCx, INTS, EN); + REGSET(tc, SYS_TCx, TEN, EN); + break; + + case CLOCK_EVT_MODE_ONESHOT: + REGSET(tc, SYS_TCx, REN, DIS); + REGSET(tc, SYS_TCx, INTS, EN); + + /* fall through */ + + case CLOCK_EVT_MODE_UNUSED: + case CLOCK_EVT_MODE_SHUTDOWN: + case CLOCK_EVT_MODE_RESUME: + default: + REGSET(tc, SYS_TCx, TEN, DIS); + break; + } + + SYS_TC(TIMER_CLOCKEVENT) = tc; +} + +static int ns9xxx_clockevent_setnextevent(unsigned long evt, + struct clock_event_device *clk) +{ + u32 tc = SYS_TC(TIMER_CLOCKEVENT); + + if (REGGET(tc, SYS_TCx, TEN)) { + REGSET(tc, SYS_TCx, TEN, DIS); + SYS_TC(TIMER_CLOCKEVENT) = tc; + } + + REGSET(tc, SYS_TCx, TEN, EN); + + SYS_TRC(TIMER_CLOCKEVENT) = evt; + + SYS_TC(TIMER_CLOCKEVENT) = tc; + + return 0; +} + +static struct clock_event_device ns9xxx_clockevent_device = { + .name = "ns9xxx-timer" __stringify(TIMER_CLOCKEVENT), + .shift = 20, + .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, + .set_mode = ns9xxx_clockevent_setmode, + .set_next_event = ns9xxx_clockevent_setnextevent, +}; + +static irqreturn_t ns9xxx_clockevent_handler(int irq, void *dev_id) { int timerno = irq - IRQ_TIMER0; u32 tc; - write_seqlock(&xtime_lock); - timer_tick(); - write_sequnlock(&xtime_lock); + struct clock_event_device *evt = &ns9xxx_clockevent_device; /* clear irq */ tc = SYS_TC(timerno); @@ -44,50 +114,21 @@ ns9xxx_timer_interrupt(int irq, void *dev_id) REGSET(tc, SYS_TCx, INTC, UNSET); SYS_TC(timerno) = tc; - return IRQ_HANDLED; -} - -static struct irqaction ns9xxx_timer_irq = { - .name = "NS9xxx Timer Tick", - .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, - .handler = ns9xxx_timer_interrupt, -}; + evt->event_handler(evt); -static cycle_t ns9xxx_clocksource_read(void) -{ - return SYS_TR(TIMER_CLOCKSOURCE); + return IRQ_HANDLED; } -static struct clocksource ns9xxx_clocksource = { - .name = "ns9xxx-timer" __stringify(TIMER_CLOCKSOURCE), - .rating = 300, - .read = ns9xxx_clocksource_read, - .mask = CLOCKSOURCE_MASK(32), - .shift = 20, - .flags = CLOCK_SOURCE_IS_CONTINUOUS, +static struct irqaction ns9xxx_clockevent_action = { + .name = "ns9xxx-timer" __stringify(TIMER_CLOCKEVENT), + .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, + .handler = ns9xxx_clockevent_handler, }; static void __init ns9xxx_timer_init(void) { int tc; - /* disable timer */ - if ((tc = SYS_TC(0)) & SYS_TCx_TEN) - SYS_TC(0) = tc & ~SYS_TCx_TEN; - - SYS_TRC(0) = SH_DIV(ns9xxx_cpuclock(), (TIMERCLOCKSELECT * HZ), 0); - - REGSET(tc, SYS_TCx, TEN, EN); - REGSET(tc, SYS_TCx, TLCS, DIV64); /* This must match TIMERCLOCKSELECT */ - REGSET(tc, SYS_TCx, INTS, EN); - REGSET(tc, SYS_TCx, UDS, DOWN); - REGSET(tc, SYS_TCx, TDBG, STOP); - REGSET(tc, SYS_TCx, TSZ, 32); - REGSET(tc, SYS_TCx, REN, EN); - SYS_TC(0) = tc; - - setup_irq(IRQ_TIMER0, &ns9xxx_timer_irq); - tc = SYS_TC(TIMER_CLOCKSOURCE); if (REGGET(tc, SYS_TCx, TEN)) { REGSET(tc, SYS_TCx, TEN, DIS); @@ -111,6 +152,31 @@ static void __init ns9xxx_timer_init(void) ns9xxx_clocksource.shift); clocksource_register(&ns9xxx_clocksource); + + latch = SH_DIV(ns9xxx_cpuclock(), HZ, 0); + + tc = SYS_TC(TIMER_CLOCKEVENT); + REGSET(tc, SYS_TCx, TEN, DIS); + REGSET(tc, SYS_TCx, TDBG, STOP); + REGSET(tc, SYS_TCx, TLCS, CPU); + REGSET(tc, SYS_TCx, TM, IEE); + REGSET(tc, SYS_TCx, INTS, DIS); + REGSET(tc, SYS_TCx, UDS, DOWN); + REGSET(tc, SYS_TCx, TSZ, 32); + REGSET(tc, SYS_TCx, REN, EN); + SYS_TC(TIMER_CLOCKEVENT) = tc; + + ns9xxx_clockevent_device.mult = div_sc(ns9xxx_cpuclock(), + NSEC_PER_SEC, ns9xxx_clockevent_device.shift); + ns9xxx_clockevent_device.max_delta_ns = + clockevent_delta2ns(-1, &ns9xxx_clockevent_device); + ns9xxx_clockevent_device.min_delta_ns = + clockevent_delta2ns(1, &ns9xxx_clockevent_device); + + ns9xxx_clockevent_device.cpumask = cpumask_of_cpu(0); + clockevents_register_device(&ns9xxx_clockevent_device); + + setup_irq(IRQ_TIMER0 + TIMER_CLOCKEVENT, &ns9xxx_clockevent_action); } struct sys_timer ns9xxx_timer = { -- cgit v0.10.2 From c54ecb2481d464d50520ce60cf36011b68d1e89a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Sun, 30 Sep 2007 20:36:14 +0100 Subject: [ARM] 4594/1: ns9xxx: use the new gpio functions MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Up to now only board-a9m9750dev.c used GPIOs. It just wrote directly into the corresponding registers. Now it properly reserves the gpio and uses the API function to configure it. Signed-off-by: Uwe Kleine-König Signed-off-by: Russell King diff --git a/arch/arm/mach-ns9xxx/board-a9m9750dev.c b/arch/arm/mach-ns9xxx/board-a9m9750dev.c index 88d1f7e..7fa3fb1 100644 --- a/arch/arm/mach-ns9xxx/board-a9m9750dev.c +++ b/arch/arm/mach-ns9xxx/board-a9m9750dev.c @@ -13,6 +13,7 @@ #include #include +#include #include #include @@ -91,12 +92,11 @@ void __init board_a9m9750dev_init_irq(void) u32 reg; int i; - /* - * configure gpio for IRQ_EXT2 - * use GPIO 11, because GPIO 32 is used for the LCD - */ - /* XXX: proper GPIO handling */ - BBU_GCONFb1(1) &= ~0x2000; + if (gpio_request(11, "board a9m9750dev extirq2") == 0) + ns9xxx_gpio_configure(11, 0, 1); + else + printk(KERN_ERR "%s: cannot get gpio 11 for IRQ_EXT2\n", + __func__); for (i = FPGA_IRQ(0); i <= FPGA_IRQ(7); ++i) { set_irq_chip(i, &a9m9750dev_fpga_chip); -- cgit v0.10.2 From 361c7ad607bc0e84ef0fef8c3f11c47b33c06e41 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Sun, 30 Sep 2007 20:36:33 +0100 Subject: [ARM] 4595/1: ns9xxx: define registers as void __iomem * instead of volatile u32 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit As a consequence registers are now accessed with __raw_{read,write}[bl]. Signed-off-by: Uwe Kleine-König Signed-off-by: Russell King diff --git a/arch/arm/mach-ns9xxx/board-a9m9750dev.c b/arch/arm/mach-ns9xxx/board-a9m9750dev.c index 7fa3fb1..0f65177 100644 --- a/arch/arm/mach-ns9xxx/board-a9m9750dev.c +++ b/arch/arm/mach-ns9xxx/board-a9m9750dev.c @@ -45,7 +45,13 @@ static void a9m9750dev_fpga_ack_irq(unsigned int irq) static void a9m9750dev_fpga_mask_irq(unsigned int irq) { - FPGA_IER &= ~(1 << (irq - FPGA_IRQ(0))); + u8 ier; + + ier = __raw_readb(FPGA_IER); + + ier &= ~(1 << (irq - FPGA_IRQ(0))); + + __raw_writeb(ier, FPGA_IER); } static void a9m9750dev_fpga_maskack_irq(unsigned int irq) @@ -56,7 +62,13 @@ static void a9m9750dev_fpga_maskack_irq(unsigned int irq) static void a9m9750dev_fpga_unmask_irq(unsigned int irq) { - FPGA_IER |= 1 << (irq - FPGA_IRQ(0)); + u8 ier; + + ier = __raw_readb(FPGA_IER); + + ier |= 1 << (irq - FPGA_IRQ(0)); + + __raw_writeb(ier, FPGA_IER); } static struct irq_chip a9m9750dev_fpga_chip = { @@ -69,7 +81,7 @@ static struct irq_chip a9m9750dev_fpga_chip = { static void a9m9750dev_fpga_demux_handler(unsigned int irq, struct irq_desc *desc) { - int stat = FPGA_ISR; + u8 stat = __raw_readb(FPGA_ISR); desc->chip->mask_ack(irq); @@ -89,7 +101,7 @@ static void a9m9750dev_fpga_demux_handler(unsigned int irq, void __init board_a9m9750dev_init_irq(void) { - u32 reg; + u32 eic; int i; if (gpio_request(11, "board a9m9750dev extirq2") == 0) @@ -105,10 +117,10 @@ void __init board_a9m9750dev_init_irq(void) } /* IRQ_EXT2: level sensitive + active low */ - reg = SYS_EIC(2); - REGSET(reg, SYS_EIC, PLTY, AL); - REGSET(reg, SYS_EIC, LVEDG, LEVEL); - SYS_EIC(2) = reg; + eic = __raw_readl(SYS_EIC(2)); + REGSET(eic, SYS_EIC, PLTY, AL); + REGSET(eic, SYS_EIC, LVEDG, LEVEL); + __raw_writel(eic, SYS_EIC(2)); set_irq_chained_handler(IRQ_EXT2, a9m9750dev_fpga_demux_handler); @@ -172,17 +184,18 @@ void __init board_a9m9750dev_init_machine(void) u32 reg; /* setup static CS0: memory base ... */ - REGSETIM(SYS_SMCSSMB(0), SYS_SMCSSMB, CSxB, - NS9XXX_CSxSTAT_PHYS(0) >> 12); + reg = __raw_readl(SYS_SMCSSMB(0)); + REGSETIM(reg, SYS_SMCSSMB, CSxB, NS9XXX_CSxSTAT_PHYS(0) >> 12); + __raw_writel(reg, SYS_SMCSSMB(0)); /* ... and mask */ - reg = SYS_SMCSSMM(0); + reg = __raw_readl(SYS_SMCSSMM(0)); REGSETIM(reg, SYS_SMCSSMM, CSxM, 0xfffff); REGSET(reg, SYS_SMCSSMM, CSEx, EN); - SYS_SMCSSMM(0) = reg; + __raw_writel(reg, SYS_SMCSSMM(0)); /* setup static CS0: memory configuration */ - reg = MEM_SMC(0); + reg = __raw_readl(MEM_SMC(0)); REGSET(reg, MEM_SMC, PSMC, OFF); REGSET(reg, MEM_SMC, BSMC, OFF); REGSET(reg, MEM_SMC, EW, OFF); @@ -190,13 +203,13 @@ void __init board_a9m9750dev_init_machine(void) REGSET(reg, MEM_SMC, PC, AL); REGSET(reg, MEM_SMC, PM, DIS); REGSET(reg, MEM_SMC, MW, 8); - MEM_SMC(0) = reg; + __raw_writel(reg, MEM_SMC(0)); /* setup static CS0: timing */ - MEM_SMWED(0) = 0x2; - MEM_SMOED(0) = 0x2; - MEM_SMRD(0) = 0x6; - MEM_SMWD(0) = 0x6; + __raw_writel(0x2, MEM_SMWED(0)); + __raw_writel(0x2, MEM_SMOED(0)); + __raw_writel(0x6, MEM_SMRD(0)); + __raw_writel(0x6, MEM_SMWD(0)); platform_add_devices(board_a9m9750dev_devices, ARRAY_SIZE(board_a9m9750dev_devices)); diff --git a/arch/arm/mach-ns9xxx/gpio.c b/arch/arm/mach-ns9xxx/gpio.c index 87b872f..b223021 100644 --- a/arch/arm/mach-ns9xxx/gpio.c +++ b/arch/arm/mach-ns9xxx/gpio.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include @@ -47,38 +48,38 @@ static inline int ns9xxx_valid_gpio(unsigned gpio) BUG(); } -static inline volatile u32 *ns9xxx_gpio_get_gconfaddr(unsigned gpio) +static inline void __iomem *ns9xxx_gpio_get_gconfaddr(unsigned gpio) { if (gpio < 56) - return &BBU_GCONFb1(gpio / 8); + return BBU_GCONFb1(gpio / 8); else /* * this could be optimised away on * ns9750 only builds, but it isn't ... */ - return &BBU_GCONFb2((gpio - 56) / 8); + return BBU_GCONFb2((gpio - 56) / 8); } -static inline volatile u32 *ns9xxx_gpio_get_gctrladdr(unsigned gpio) +static inline void __iomem *ns9xxx_gpio_get_gctrladdr(unsigned gpio) { if (gpio < 32) - return &BBU_GCTRL1; + return BBU_GCTRL1; else if (gpio < 64) - return &BBU_GCTRL2; + return BBU_GCTRL2; else /* this could be optimised away on ns9750 only builds */ - return &BBU_GCTRL3; + return BBU_GCTRL3; } -static inline volatile u32 *ns9xxx_gpio_get_gstataddr(unsigned gpio) +static inline void __iomem *ns9xxx_gpio_get_gstataddr(unsigned gpio) { if (gpio < 32) - return &BBU_GSTAT1; + return BBU_GSTAT1; else if (gpio < 64) - return &BBU_GSTAT2; + return BBU_GSTAT2; else /* this could be optimised away on ns9750 only builds */ - return &BBU_GSTAT3; + return BBU_GSTAT3; } int gpio_request(unsigned gpio, const char *label) @@ -105,17 +106,17 @@ EXPORT_SYMBOL(gpio_free); */ static int __ns9xxx_gpio_configure(unsigned gpio, int dir, int inv, int func) { - volatile u32 *conf = ns9xxx_gpio_get_gconfaddr(gpio); + void __iomem *conf = ns9xxx_gpio_get_gconfaddr(gpio); u32 confval; unsigned long flags; spin_lock_irqsave(&gpio_lock, flags); - confval = *conf; + confval = __raw_readl(conf); REGSETIM_IDX(confval, BBU_GCONFx, DIR, gpio & 7, dir); REGSETIM_IDX(confval, BBU_GCONFx, INV, gpio & 7, inv); REGSETIM_IDX(confval, BBU_GCONFx, FUNC, gpio & 7, func); - *conf = confval; + __raw_writel(confval, conf); spin_unlock_irqrestore(&gpio_lock, flags); @@ -158,10 +159,10 @@ EXPORT_SYMBOL(gpio_direction_output); int gpio_get_value(unsigned gpio) { - volatile u32 *stat = ns9xxx_gpio_get_gstataddr(gpio); + void __iomem *stat = ns9xxx_gpio_get_gstataddr(gpio); int ret; - ret = 1 & (*stat >> (gpio & 31)); + ret = 1 & (__raw_readl(stat) >> (gpio & 31)); return ret; } @@ -169,15 +170,20 @@ EXPORT_SYMBOL(gpio_get_value); void gpio_set_value(unsigned gpio, int value) { - volatile u32 *ctrl = ns9xxx_gpio_get_gctrladdr(gpio); + void __iomem *ctrl = ns9xxx_gpio_get_gctrladdr(gpio); + u32 ctrlval; unsigned long flags; spin_lock_irqsave(&gpio_lock, flags); + ctrlval = __raw_readl(ctrl); + if (value) - *ctrl |= 1 << (gpio & 31); + ctrlval |= 1 << (gpio & 31); else - *ctrl &= ~(1 << (gpio & 31)); + ctrlval &= ~(1 << (gpio & 31)); + + __raw_writel(ctrlval, ctrl); spin_unlock_irqrestore(&gpio_lock, flags); } diff --git a/arch/arm/mach-ns9xxx/irq.c b/arch/arm/mach-ns9xxx/irq.c index 24d424e..00001b8 100644 --- a/arch/arm/mach-ns9xxx/irq.c +++ b/arch/arm/mach-ns9xxx/irq.c @@ -9,6 +9,7 @@ * the Free Software Foundation. */ #include +#include #include #include #include @@ -20,12 +21,14 @@ static void ns9xxx_mask_irq(unsigned int irq) { /* XXX: better use cpp symbols */ - SYS_IC(irq / 4) &= ~(1 << (7 + 8 * (3 - (irq & 3)))); + u32 ic = __raw_readl(SYS_IC(irq / 4)); + ic &= ~(1 << (7 + 8 * (3 - (irq & 3)))); + __raw_writel(ic, SYS_IC(irq / 4)); } static void ns9xxx_ack_irq(unsigned int irq) { - SYS_ISRADDR = 0; + __raw_writel(0, SYS_ISRADDR); } static void ns9xxx_maskack_irq(unsigned int irq) @@ -37,7 +40,9 @@ static void ns9xxx_maskack_irq(unsigned int irq) static void ns9xxx_unmask_irq(unsigned int irq) { /* XXX: better use cpp symbols */ - SYS_IC(irq / 4) |= 1 << (7 + 8 * (3 - (irq & 3))); + u32 ic = __raw_readl(SYS_IC(irq / 4)); + ic |= 1 << (7 + 8 * (3 - (irq & 3))); + __raw_writel(ic, SYS_IC(irq / 4)); } static struct irq_chip ns9xxx_chip = { @@ -53,14 +58,14 @@ void __init ns9xxx_init_irq(void) /* disable all IRQs */ for (i = 0; i < 8; ++i) - SYS_IC(i) = (4 * i) << 24 | (4 * i + 1) << 16 | - (4 * i + 2) << 8 | (4 * i + 3); + __raw_writel((4 * i) << 24 | (4 * i + 1) << 16 | + (4 * i + 2) << 8 | (4 * i + 3), SYS_IC(i)); /* simple interrupt prio table: * prio(x) < prio(y) <=> x < y */ for (i = 0; i < 32; ++i) - SYS_IVA(i) = i; + __raw_writel(i, SYS_IVA(i)); for (i = IRQ_WATCHDOG; i <= IRQ_EXT3; ++i) { set_irq_chip(i, &ns9xxx_chip); diff --git a/arch/arm/mach-ns9xxx/time.c b/arch/arm/mach-ns9xxx/time.c index 6f29515..c3dd1f4 100644 --- a/arch/arm/mach-ns9xxx/time.c +++ b/arch/arm/mach-ns9xxx/time.c @@ -27,7 +27,7 @@ static u32 latch; static cycle_t ns9xxx_clocksource_read(void) { - return SYS_TR(TIMER_CLOCKSOURCE); + return __raw_readl(SYS_TR(TIMER_CLOCKSOURCE)); } static struct clocksource ns9xxx_clocksource = { @@ -42,11 +42,11 @@ static struct clocksource ns9xxx_clocksource = { static void ns9xxx_clockevent_setmode(enum clock_event_mode mode, struct clock_event_device *clk) { - u32 tc = SYS_TC(TIMER_CLOCKEVENT); + u32 tc = __raw_readl(SYS_TC(TIMER_CLOCKEVENT)); switch(mode) { case CLOCK_EVT_MODE_PERIODIC: - SYS_TRC(TIMER_CLOCKEVENT) = latch; + __raw_writel(latch, SYS_TRC(TIMER_CLOCKEVENT)); REGSET(tc, SYS_TCx, REN, EN); REGSET(tc, SYS_TCx, INTS, EN); REGSET(tc, SYS_TCx, TEN, EN); @@ -66,24 +66,24 @@ static void ns9xxx_clockevent_setmode(enum clock_event_mode mode, break; } - SYS_TC(TIMER_CLOCKEVENT) = tc; + __raw_writel(tc, SYS_TC(TIMER_CLOCKEVENT)); } static int ns9xxx_clockevent_setnextevent(unsigned long evt, struct clock_event_device *clk) { - u32 tc = SYS_TC(TIMER_CLOCKEVENT); + u32 tc = __raw_readl(SYS_TC(TIMER_CLOCKEVENT)); if (REGGET(tc, SYS_TCx, TEN)) { REGSET(tc, SYS_TCx, TEN, DIS); - SYS_TC(TIMER_CLOCKEVENT) = tc; + __raw_writel(tc, SYS_TC(TIMER_CLOCKEVENT)); } REGSET(tc, SYS_TCx, TEN, EN); - SYS_TRC(TIMER_CLOCKEVENT) = evt; + __raw_writel(evt, SYS_TRC(TIMER_CLOCKEVENT)); - SYS_TC(TIMER_CLOCKEVENT) = tc; + __raw_writel(tc, SYS_TC(TIMER_CLOCKEVENT)); return 0; } @@ -104,15 +104,15 @@ static irqreturn_t ns9xxx_clockevent_handler(int irq, void *dev_id) struct clock_event_device *evt = &ns9xxx_clockevent_device; /* clear irq */ - tc = SYS_TC(timerno); + tc = __raw_readl(SYS_TC(timerno)); if (REGGET(tc, SYS_TCx, REN) == SYS_TCx_REN_DIS) { REGSET(tc, SYS_TCx, TEN, DIS); - SYS_TC(timerno) = tc; + __raw_writel(tc, SYS_TC(timerno)); } REGSET(tc, SYS_TCx, INTC, SET); - SYS_TC(timerno) = tc; + __raw_writel(tc, SYS_TC(timerno)); REGSET(tc, SYS_TCx, INTC, UNSET); - SYS_TC(timerno) = tc; + __raw_writel(tc, SYS_TC(timerno)); evt->event_handler(evt); @@ -129,13 +129,13 @@ static void __init ns9xxx_timer_init(void) { int tc; - tc = SYS_TC(TIMER_CLOCKSOURCE); + tc = __raw_readl(SYS_TC(TIMER_CLOCKSOURCE)); if (REGGET(tc, SYS_TCx, TEN)) { REGSET(tc, SYS_TCx, TEN, DIS); - SYS_TC(TIMER_CLOCKSOURCE) = tc; + __raw_writel(tc, SYS_TC(TIMER_CLOCKSOURCE)); } - SYS_TRC(TIMER_CLOCKSOURCE) = 0; + __raw_writel(0, SYS_TRC(TIMER_CLOCKSOURCE)); REGSET(tc, SYS_TCx, TEN, EN); REGSET(tc, SYS_TCx, TDBG, STOP); @@ -146,7 +146,7 @@ static void __init ns9xxx_timer_init(void) REGSET(tc, SYS_TCx, TSZ, 32); REGSET(tc, SYS_TCx, REN, EN); - SYS_TC(TIMER_CLOCKSOURCE) = tc; + __raw_writel(tc, SYS_TC(TIMER_CLOCKSOURCE)); ns9xxx_clocksource.mult = clocksource_hz2mult(ns9xxx_cpuclock(), ns9xxx_clocksource.shift); @@ -155,7 +155,7 @@ static void __init ns9xxx_timer_init(void) latch = SH_DIV(ns9xxx_cpuclock(), HZ, 0); - tc = SYS_TC(TIMER_CLOCKEVENT); + tc = __raw_readl(SYS_TC(TIMER_CLOCKEVENT)); REGSET(tc, SYS_TCx, TEN, DIS); REGSET(tc, SYS_TCx, TDBG, STOP); REGSET(tc, SYS_TCx, TLCS, CPU); @@ -164,7 +164,7 @@ static void __init ns9xxx_timer_init(void) REGSET(tc, SYS_TCx, UDS, DOWN); REGSET(tc, SYS_TCx, TSZ, 32); REGSET(tc, SYS_TCx, REN, EN); - SYS_TC(TIMER_CLOCKEVENT) = tc; + __raw_writel(tc, SYS_TC(TIMER_CLOCKEVENT)); ns9xxx_clockevent_device.mult = div_sc(ns9xxx_cpuclock(), NSEC_PER_SEC, ns9xxx_clockevent_device.shift); diff --git a/include/asm-arm/arch-ns9xxx/clock.h b/include/asm-arm/arch-ns9xxx/clock.h index 90604d4..b943d3a 100644 --- a/include/asm-arm/arch-ns9xxx/clock.h +++ b/include/asm-arm/arch-ns9xxx/clock.h @@ -19,7 +19,7 @@ static inline u32 ns9xxx_systemclock(void) __attribute__((const)); static inline u32 ns9xxx_systemclock(void) { - u32 pll = SYS_PLL; + u32 pll = __raw_readl(SYS_PLL); /* * The system clock should be a multiple of HZ * TIMERCLOCKSELECT (in diff --git a/include/asm-arm/arch-ns9xxx/hardware.h b/include/asm-arm/arch-ns9xxx/hardware.h index b5d66f9..0b7b346 100644 --- a/include/asm-arm/arch-ns9xxx/hardware.h +++ b/include/asm-arm/arch-ns9xxx/hardware.h @@ -35,11 +35,8 @@ #ifndef __ASSEMBLY__ -# define __REG(x) (*((volatile u32 *)io_p2v((x)))) -# define __REG2(x, y) (*((volatile u32 *)io_p2v((x)) + (y))) - -# define __REGB(x) (*((volatile u8 *)io_p2v((x)))) -# define __REGB2(x) (*((volatile u8 *)io_p2v((x)) + (y))) +# define __REG(x) ((void __iomem __force *)io_p2v((x))) +# define __REG2(x, y) ((void __iomem __force *)(io_p2v((x)) + 4 * (y))) # define __REGSET(var, field, value) \ ((var) = (((var) & ~((field) & ~(value))) | (value))) @@ -77,9 +74,6 @@ # define __REG(x) io_p2v(x) # define __REG2(x, y) io_p2v((x) + (y)) -# define __REGB(x) __REG((x)) -# define __REGB2(x, y) __REG2((x), (y)) - #endif #endif /* ifndef __ASM_ARCH_HARDWARE_H */ diff --git a/include/asm-arm/arch-ns9xxx/regs-board-a9m9750dev.h b/include/asm-arm/arch-ns9xxx/regs-board-a9m9750dev.h index c3dc532..afa3a9d 100644 --- a/include/asm-arm/arch-ns9xxx/regs-board-a9m9750dev.h +++ b/include/asm-arm/arch-ns9xxx/regs-board-a9m9750dev.h @@ -18,7 +18,7 @@ #define FPGA_UARTC_BASE io_p2v(NS9XXX_CSxSTAT_PHYS(0) + 0x10) #define FPGA_UARTD_BASE io_p2v(NS9XXX_CSxSTAT_PHYS(0) + 0x18) -#define FPGA_IER __REGB(NS9XXX_CSxSTAT_PHYS(0) + 0x50) -#define FPGA_ISR __REGB(NS9XXX_CSxSTAT_PHYS(0) + 0x60) +#define FPGA_IER __REG(NS9XXX_CSxSTAT_PHYS(0) + 0x50) +#define FPGA_ISR __REG(NS9XXX_CSxSTAT_PHYS(0) + 0x60) #endif /* ifndef __ASM_ARCH_REGSBOARDA9M9750_H */ diff --git a/include/asm-arm/arch-ns9xxx/system.h b/include/asm-arm/arch-ns9xxx/system.h index e3cd4d3..c1082bd 100644 --- a/include/asm-arm/arch-ns9xxx/system.h +++ b/include/asm-arm/arch-ns9xxx/system.h @@ -24,9 +24,9 @@ static inline void arch_reset(char mode) { u32 reg; - reg = SYS_PLL >> 16; + reg = __raw_readl(SYS_PLL) >> 16; REGSET(reg, SYS_PLL, SWC, YES); - SYS_PLL = reg; + __raw_writel(reg, SYS_PLL); BUG(); } -- cgit v0.10.2 From f3fb5a556c99118186581e6546a9c41e1f73cf6f Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Thu, 4 Oct 2007 21:41:20 +0100 Subject: [ARM] 4596/1: S3C2412: Correct IRQs for SDI+CF and add decoding support Fix the IRQ numbers of the CF and SDI interface on the S3C2412 and S3C2413. Add support to handle these IRQs properly and ensure that the SDI controller platform device is correctly renumbered. Signed-off-by: Ben Dooks Signed-off-by: Russell King diff --git a/arch/arm/mach-s3c2412/irq.c b/arch/arm/mach-s3c2412/irq.c index f0d6682..e9d0c76 100644 --- a/arch/arm/mach-s3c2412/irq.c +++ b/arch/arm/mach-s3c2412/irq.c @@ -38,6 +38,9 @@ #include #include +#define INTMSK(start, end) ((1 << ((end) + 1 - (start))) - 1) +#define INTMSK_SUB(start, end) (INTMSK(start, end) << ((start - S3C2410_IRQSUB(0)))) + /* the s3c2412 changes the behaviour of IRQ_EINT0 through IRQ_EINT3 by * having them turn up in both the INT* and the EINT* registers. Whilst * both show the status, they both now need to be acked when the IRQs @@ -105,6 +108,51 @@ static struct irq_chip s3c2412_irq_eint0t4 = { .set_type = s3c_irqext_type, }; +#define INTBIT(x) (1 << ((x) - S3C2410_IRQSUB(0))) + +/* CF and SDI sub interrupts */ + +static void s3c2412_irq_demux_cfsdi(unsigned int irq, struct irq_desc *desc) +{ + unsigned int subsrc, submsk; + + subsrc = __raw_readl(S3C2410_SUBSRCPND); + submsk = __raw_readl(S3C2410_INTSUBMSK); + + subsrc &= ~submsk; + + if (subsrc & INTBIT(IRQ_S3C2412_SDI)) + desc_handle_irq(IRQ_S3C2412_SDI, irq_desc + IRQ_S3C2412_SDI); + + if (subsrc & INTBIT(IRQ_S3C2412_CF)) + desc_handle_irq(IRQ_S3C2412_CF, irq_desc + IRQ_S3C2412_CF); +} + +#define INTMSK_CFSDI (1UL << (IRQ_S3C2412_CFSDI - IRQ_EINT0)) +#define SUBMSK_CFSDI INTMSK_SUB(IRQ_S3C2412_SDI, IRQ_S3C2412_CF) + +static void s3c2412_irq_cfsdi_mask(unsigned int irqno) +{ + s3c_irqsub_mask(irqno, INTMSK_CFSDI, SUBMSK_CFSDI); +} + +static void s3c2412_irq_cfsdi_unmask(unsigned int irqno) +{ + s3c_irqsub_unmask(irqno, INTMSK_CFSDI); +} + +static void s3c2412_irq_cfsdi_ack(unsigned int irqno) +{ + s3c_irqsub_maskack(irqno, INTMSK_CFSDI, SUBMSK_CFSDI); +} + +static struct irq_chip s3c2412_irq_cfsdi = { + .name = "s3c2412-cfsdi", + .ack = s3c2412_irq_cfsdi_ack, + .mask = s3c2412_irq_cfsdi_mask, + .unmask = s3c2412_irq_cfsdi_unmask, +}; + static int s3c2412_irq_add(struct sys_device *sysdev) { unsigned int irqno; @@ -115,6 +163,16 @@ static int s3c2412_irq_add(struct sys_device *sysdev) set_irq_flags(irqno, IRQF_VALID); } + /* add demux support for CF/SDI */ + + set_irq_chained_handler(IRQ_S3C2412_CFSDI, s3c2412_irq_demux_cfsdi); + + for (irqno = IRQ_S3C2412_SDI; irqno <= IRQ_S3C2412_CF; irqno++) { + set_irq_chip(irqno, &s3c2412_irq_cfsdi); + set_irq_handler(irqno, handle_level_irq); + set_irq_flags(irqno, IRQF_VALID); + } + return 0; } diff --git a/arch/arm/mach-s3c2412/s3c2412.c b/arch/arm/mach-s3c2412/s3c2412.c index e0ccb40..4f92a15 100644 --- a/arch/arm/mach-s3c2412/s3c2412.c +++ b/arch/arm/mach-s3c2412/s3c2412.c @@ -78,6 +78,11 @@ void __init s3c2412_init_uarts(struct s3c2410_uartcfg *cfg, int no) s3c_device_lcd.name = "s3c2412-lcd"; s3c_device_nand.name = "s3c2412-nand"; + /* alter IRQ of SDI controller */ + + s3c_device_sdi.resource[1].start = IRQ_S3C2412_SDI; + s3c_device_sdi.resource[1].end = IRQ_S3C2412_SDI; + /* spi channel related changes, s3c2412/13 specific */ s3c_device_spi0.name = "s3c2412-spi"; s3c_device_spi0.resource[0].end = S3C24XX_PA_SPI + 0x24; diff --git a/include/asm-arm/arch-s3c2410/irqs.h b/include/asm-arm/arch-s3c2410/irqs.h index 3b49cd1..996f654 100644 --- a/include/asm-arm/arch-s3c2410/irqs.h +++ b/include/asm-arm/arch-s3c2410/irqs.h @@ -112,6 +112,13 @@ #define IRQ_TC S3C2410_IRQSUB(9) #define IRQ_ADC S3C2410_IRQSUB(10) +/* extra irqs for s3c2412 */ + +#define IRQ_S3C2412_CFSDI S3C2410_IRQ(21) + +#define IRQ_S3C2412_SDI S3C2410_IRQSUB(13) +#define IRQ_S3C2412_CF S3C2410_IRQSUB(14) + /* extra irqs for s3c2440 */ #define IRQ_S3C2440_CAM_C S3C2410_IRQSUB(11) /* S3C2443 too */ -- cgit v0.10.2 From 353ba84acdd551c737ac71577322393fceb969f0 Mon Sep 17 00:00:00 2001 From: Herbert Valerio Riedel Date: Sun, 23 Sep 2007 08:30:16 +0100 Subject: [ARM] 4572/1: ep93xx: add cirrus logic edb9307 support This patch adds support for the Cirrus Logic EDB9307, an evaluation board based on the Cirrus Logic EP9307 SoC, which features amongst other things 64M RAM, 32M NOR flash, 3 USB host ports, audio in/out, two serial ports and a 10/100 ethernet interface. Signed-off-by: Herbert Valerio Riedel Acked-by: Lennert Buytenhek Signed-off-by: Russell King diff --git a/arch/arm/mach-ep93xx/Kconfig b/arch/arm/mach-ep93xx/Kconfig index 575a21d..ea8549b 100644 --- a/arch/arm/mach-ep93xx/Kconfig +++ b/arch/arm/mach-ep93xx/Kconfig @@ -27,6 +27,12 @@ config MACH_EDB9302A Say 'Y' here if you want your kernel to support the Cirrus Logic EDB9302A Evaluation Board. +config MACH_EDB9307 + bool "Support Cirrus Logic EDB9307" + help + Say 'Y' here if you want your kernel to support the Cirrus + Logic EDB9307 Evaluation Board. + config MACH_EDB9312 bool "Support Cirrus Logic EDB9312" help diff --git a/arch/arm/mach-ep93xx/Makefile b/arch/arm/mach-ep93xx/Makefile index 0d3bf93..0ecf997 100644 --- a/arch/arm/mach-ep93xx/Makefile +++ b/arch/arm/mach-ep93xx/Makefile @@ -9,6 +9,7 @@ obj- := obj-$(CONFIG_MACH_ADSSPHERE) += adssphere.o obj-$(CONFIG_MACH_EDB9302) += edb9302.o obj-$(CONFIG_MACH_EDB9302A) += edb9302a.o +obj-$(CONFIG_MACH_EDB9307) += edb9307.o obj-$(CONFIG_MACH_EDB9312) += edb9312.o obj-$(CONFIG_MACH_EDB9315) += edb9315.o obj-$(CONFIG_MACH_EDB9315A) += edb9315a.o diff --git a/arch/arm/mach-ep93xx/edb9307.c b/arch/arm/mach-ep93xx/edb9307.c new file mode 100644 index 0000000..d6a5698 --- /dev/null +++ b/arch/arm/mach-ep93xx/edb9307.c @@ -0,0 +1,91 @@ +/* + * arch/arm/mach-ep93xx/edb9307.c + * Cirrus Logic EDB9307 support. + * + * Copyright (C) 2007 Herbert Valerio Riedel + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or (at + * your option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static struct physmap_flash_data edb9307_flash_data = { + .width = 4, +}; + +static struct resource edb9307_flash_resource = { + .start = 0x60000000, + .end = 0x61ffffff, + .flags = IORESOURCE_MEM, +}; + +static struct platform_device edb9307_flash = { + .name = "physmap-flash", + .id = 0, + .dev = { + .platform_data = &edb9307_flash_data, + }, + .num_resources = 1, + .resource = &edb9307_flash_resource, +}; + +static struct ep93xx_eth_data edb9307_eth_data = { + .phy_id = 1, +}; + +static struct resource edb9307_eth_resource[] = { + { + .start = EP93XX_ETHERNET_PHYS_BASE, + .end = EP93XX_ETHERNET_PHYS_BASE + 0xffff, + .flags = IORESOURCE_MEM, + }, { + .start = IRQ_EP93XX_ETHERNET, + .end = IRQ_EP93XX_ETHERNET, + .flags = IORESOURCE_IRQ, + } +}; + +static struct platform_device edb9307_eth_device = { + .name = "ep93xx-eth", + .id = -1, + .dev = { + .platform_data = &edb9307_eth_data, + }, + .num_resources = 2, + .resource = edb9307_eth_resource, +}; + +static void __init edb9307_init_machine(void) +{ + ep93xx_init_devices(); + platform_device_register(&edb9307_flash); + + memcpy(edb9307_eth_data.dev_addr, + (void *)(EP93XX_ETHERNET_BASE + 0x50), 6); + platform_device_register(&edb9307_eth_device); +} + +MACHINE_START(EDB9307, "Cirrus Logic EDB9307 Evaluation Board") + /* Maintainer: Herbert Valerio Riedel */ + .phys_io = EP93XX_APB_PHYS_BASE, + .io_pg_offst = ((EP93XX_APB_VIRT_BASE) >> 18) & 0xfffc, + .boot_params = 0x00000100, + .map_io = ep93xx_map_io, + .init_irq = ep93xx_init_irq, + .timer = &ep93xx_timer, + .init_machine = edb9307_init_machine, +MACHINE_END -- cgit v0.10.2 From 84aa462e2c2cd1b921f6b8e283f8d41666e02e8e Mon Sep 17 00:00:00 2001 From: Russell King Date: Tue, 9 Oct 2007 14:17:01 +0100 Subject: [ARM] Rename consistent_sync() as dma_cache_maint() consistent_sync() is used to handle the cache maintainence issues with DMA operations. Since we've now removed the misuse of this function from the two MTD drivers, rename it to prevent future mis-use. Signed-off-by: Russell King diff --git a/arch/arm/common/dmabounce.c b/arch/arm/common/dmabounce.c index b36b1e8..44ab0da 100644 --- a/arch/arm/common/dmabounce.c +++ b/arch/arm/common/dmabounce.c @@ -263,7 +263,7 @@ map_single(struct device *dev, void *ptr, size_t size, * We don't need to sync the DMA buffer since * it was allocated via the coherent allocators. */ - consistent_sync(ptr, size, dir); + dma_cache_maint(ptr, size, dir); } return dma_addr; @@ -383,7 +383,7 @@ sync_single(struct device *dev, dma_addr_t dma_addr, size_t size, * via the coherent allocators. */ } else { - consistent_sync(dma_to_virt(dev, dma_addr), size, dir); + dma_cache_maint(dma_to_virt(dev, dma_addr), size, dir); } } diff --git a/arch/arm/mm/consistent.c b/arch/arm/mm/consistent.c index 1f9f94f..cefdf2f 100644 --- a/arch/arm/mm/consistent.c +++ b/arch/arm/mm/consistent.c @@ -481,7 +481,7 @@ core_initcall(consistent_init); * platforms with CONFIG_DMABOUNCE. * Use the driver DMA support - see dma-mapping.h (dma_sync_*) */ -void consistent_sync(const void *start, size_t size, int direction) +void dma_cache_maint(const void *start, size_t size, int direction) { const void *end = start + size; @@ -504,4 +504,4 @@ void consistent_sync(const void *start, size_t size, int direction) BUG(); } } -EXPORT_SYMBOL(consistent_sync); +EXPORT_SYMBOL(dma_cache_maint); diff --git a/include/asm-arm/dma-mapping.h b/include/asm-arm/dma-mapping.h index c8b5d0d..678134b 100644 --- a/include/asm-arm/dma-mapping.h +++ b/include/asm-arm/dma-mapping.h @@ -17,7 +17,7 @@ * platforms with CONFIG_DMABOUNCE. * Use the driver DMA support - see dma-mapping.h (dma_sync_*) */ -extern void consistent_sync(const void *kaddr, size_t size, int rw); +extern void dma_cache_maint(const void *kaddr, size_t size, int rw); /* * Return whether the given device DMA address mask can be supported @@ -165,7 +165,7 @@ dma_map_single(struct device *dev, void *cpu_addr, size_t size, enum dma_data_direction dir) { if (!arch_is_coherent()) - consistent_sync(cpu_addr, size, dir); + dma_cache_maint(cpu_addr, size, dir); return virt_to_dma(dev, (unsigned long)cpu_addr); } @@ -278,7 +278,7 @@ dma_map_sg(struct device *dev, struct scatterlist *sg, int nents, virt = page_address(sg->page) + sg->offset; if (!arch_is_coherent()) - consistent_sync(virt, sg->length, dir); + dma_cache_maint(virt, sg->length, dir); } return nents; @@ -334,7 +334,7 @@ dma_sync_single_for_cpu(struct device *dev, dma_addr_t handle, size_t size, enum dma_data_direction dir) { if (!arch_is_coherent()) - consistent_sync((void *)dma_to_virt(dev, handle), size, dir); + dma_cache_maint((void *)dma_to_virt(dev, handle), size, dir); } static inline void @@ -342,7 +342,7 @@ dma_sync_single_for_device(struct device *dev, dma_addr_t handle, size_t size, enum dma_data_direction dir) { if (!arch_is_coherent()) - consistent_sync((void *)dma_to_virt(dev, handle), size, dir); + dma_cache_maint((void *)dma_to_virt(dev, handle), size, dir); } #else extern void dma_sync_single_for_cpu(struct device*, dma_addr_t, size_t, enum dma_data_direction); @@ -373,7 +373,7 @@ dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, int nents, for (i = 0; i < nents; i++, sg++) { char *virt = page_address(sg->page) + sg->offset; if (!arch_is_coherent()) - consistent_sync(virt, sg->length, dir); + dma_cache_maint(virt, sg->length, dir); } } @@ -386,7 +386,7 @@ dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg, int nents, for (i = 0; i < nents; i++, sg++) { char *virt = page_address(sg->page) + sg->offset; if (!arch_is_coherent()) - consistent_sync(virt, sg->length, dir); + dma_cache_maint(virt, sg->length, dir); } } #else -- cgit v0.10.2 From 033b8ffe3f1ea8174d51d125838ac6deea60f63f Mon Sep 17 00:00:00 2001 From: Mike Westerhof Date: Thu, 11 Oct 2007 03:18:14 +0100 Subject: [ARM] 4599/1: Preserve ATAG list for use with kexec (2.6.23) This patch resolves a kexec boot failure that can occur because no ATAGs are passed in to the kexec'd kernel. Currently the newly-kexec'd kernel may fail if it requires specific ATAGs, or it may fail because the fixed memory location at which it expects to find the ATAGs may contain random data instead of ATAGs. The patch ensures that any ATAGs passed to the current kernel at boot time are copied to a static buffer, and are copied back when kexec copies the new kernel into place. Thus the new kernel sees the same ATAGs from kexec and the boot loader. The boot parameters are copied without regard to type, content, or length -- this patch's scope is limited soley to saving and restoring a fixed-size block of memory containing the kernel's boot parameters. Additional functionality to examine, alter, or replace the ATAGs (using kexec, for example) can be implemented by manipulating the static buffer containing the preserved ATAGs. Note: the size of the buffer (1.5KB) is selected to comfortably hold one of each ATAG type, including a maximum-length command line and the maximum number of ATAG_MEM structures currently supported by the kernel. Should an ATAG list exceed that limit, the list will be silently truncated to that limit (to do other- wise at that point in the boot process would make a simple problem exceedingly complicated). [Note: this is the same patch as 4579, modified to accomodate the ATAG changes introduced in 2.6.23] Signed-off-by: Mike Westerhof Signed-off-by: Russell King diff --git a/arch/arm/kernel/relocate_kernel.S b/arch/arm/kernel/relocate_kernel.S index 7baadae..062c111 100644 --- a/arch/arm/kernel/relocate_kernel.S +++ b/arch/arm/kernel/relocate_kernel.S @@ -7,6 +7,23 @@ .globl relocate_new_kernel relocate_new_kernel: + /* Move boot params back to where the kernel expects them */ + + ldr r0,kexec_boot_params_address + teq r0,#0 + beq 8f + + ldr r1,kexec_boot_params_copy + mov r6,#KEXEC_BOOT_PARAMS_SIZE/4 +7: + ldr r5,[r1],#4 + str r5,[r0],#4 + subs r6,r6,#1 + bne 7b + +8: + /* Boot params moved, now go on with the kernel */ + ldr r0,kexec_indirection_page ldr r1,kexec_start_address @@ -50,7 +67,7 @@ relocate_new_kernel: mov lr,r1 mov r0,#0 ldr r1,kexec_mach_type - mov r2,#0 + ldr r2,kexec_boot_params_address mov pc,lr .globl kexec_start_address @@ -65,6 +82,16 @@ kexec_indirection_page: kexec_mach_type: .long 0x0 + /* phy addr where new kernel will expect to find boot params */ + .globl kexec_boot_params_address +kexec_boot_params_address: + .long 0x0 + + /* phy addr where old kernel put a copy of orig boot params */ + .globl kexec_boot_params_copy +kexec_boot_params_copy: + .long 0x0 + relocate_new_kernel_end: .globl relocate_new_kernel_size diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c index efac7df..bf56eb3 100644 --- a/arch/arm/kernel/setup.c +++ b/arch/arm/kernel/setup.c @@ -24,6 +24,7 @@ #include #include #include +#include #include #include @@ -783,6 +784,23 @@ static int __init customize_machine(void) } arch_initcall(customize_machine); +#ifdef CONFIG_KEXEC + +/* Physical addr of where the boot params should be for this machine */ +extern unsigned long kexec_boot_params_address; + +/* Physical addr of the buffer into which the boot params are copied */ +extern unsigned long kexec_boot_params_copy; + +/* Pointer to the boot params buffer, for manipulation and display */ +unsigned long kexec_boot_params; +EXPORT_SYMBOL(kexec_boot_params); + +/* The buffer itself - make sure it is sized correctly */ +static unsigned long kexec_boot_params_buf[(KEXEC_BOOT_PARAMS_SIZE + 3) / 4]; + +#endif + void __init setup_arch(char **cmdline_p) { struct tag *tags = (struct tag *)&init_tags; @@ -801,6 +819,18 @@ void __init setup_arch(char **cmdline_p) else if (mdesc->boot_params) tags = phys_to_virt(mdesc->boot_params); +#ifdef CONFIG_KEXEC + kexec_boot_params_copy = virt_to_phys(kexec_boot_params_buf); + kexec_boot_params = (unsigned long)kexec_boot_params_buf; + if (__atags_pointer) { + kexec_boot_params_address = __atags_pointer; + memcpy((void *)kexec_boot_params, tags, KEXEC_BOOT_PARAMS_SIZE); + } else if (mdesc->boot_params) { + kexec_boot_params_address = mdesc->boot_params; + memcpy((void *)kexec_boot_params, tags, KEXEC_BOOT_PARAMS_SIZE); + } +#endif + /* * If we have the old style parameters, convert them to * a tag list. diff --git a/include/asm-arm/kexec.h b/include/asm-arm/kexec.h index b5b030e..46dcc4d 100644 --- a/include/asm-arm/kexec.h +++ b/include/asm-arm/kexec.h @@ -14,6 +14,8 @@ #define KEXEC_ARCH KEXEC_ARCH_ARM +#define KEXEC_BOOT_PARAMS_SIZE 1536 + #ifndef __ASSEMBLY__ struct kimage; -- cgit v0.10.2 From 1e621a8e3752367d4aae78a8ab00a18fb2793f34 Mon Sep 17 00:00:00 2001 From: Lennert Buytenhek Date: Fri, 12 Oct 2007 14:38:54 +0100 Subject: [ARM] 4600/1: fix kernel build failure with build-id-supporting binutils Newer versions of binutils support --build-id, which adds an ELF note section called ".note.gnu.build-id" to the output. On the ARM kernel build, because there is no explicit mention of this section in the shipped ld script, this section is placed at vaddr 0x00000000 (whereas the normal kernel text/data typically starts at vaddr 0xc0008000), causing the output of objcopy (Image) to produce a 3G+ file. This patch makes objcopy strip the .note.gnu.build-id section from the Image file along with all other note sections, which fixes the build. Signed-off-by: Lennert Buytenhek Signed-off-by: Russell King diff --git a/arch/arm/Makefile b/arch/arm/Makefile index fa4ea9f..6c2d539 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -12,7 +12,7 @@ LDFLAGS_vmlinux :=-p --no-undefined -X CPPFLAGS_vmlinux.lds = -DTEXT_OFFSET=$(TEXT_OFFSET) -OBJCOPYFLAGS :=-O binary -R .note -R .comment -S +OBJCOPYFLAGS :=-O binary -R .note -R .note.gnu.build-id -R .comment -S GZFLAGS :=-9 #CFLAGS +=-pipe # Explicitly specifiy 32-bit ARM ISA since toolchain default can be -mthumb: -- cgit v0.10.2 From 58273e553d3d2a6b1a302f1b79eb263190554345 Mon Sep 17 00:00:00 2001 From: Russell King Date: Fri, 12 Oct 2007 22:24:09 +0100 Subject: [ARM] Update arch/arm/Kconfig for drivers/Kconfig changes Signed-off-by: Russell King diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 4b984b1..fcd1d8f 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -997,6 +997,10 @@ source "drivers/pnp/Kconfig" source "drivers/block/Kconfig" +# misc before ide - BLK_DEV_SGIIOC4 depends on SGI_IOC4 + +source "drivers/misc/Kconfig" + if PCMCIA || ARCH_CLPS7500 || ARCH_IOP32X || ARCH_IOP33X || ARCH_IXP4XX \ || ARCH_L7200 || ARCH_LH7A40X || ARCH_PXA || ARCH_RPC \ || ARCH_S3C2410 || ARCH_SA1100 || ARCH_SHARK || FOOTBRIDGE \ @@ -1032,16 +1036,16 @@ source "drivers/spi/Kconfig" source "drivers/w1/Kconfig" +source "drivers/power/Kconfig" + source "drivers/hwmon/Kconfig" -#source "drivers/l3/Kconfig" +source "drivers/ssb/Kconfig" -source "drivers/misc/Kconfig" +#source "drivers/l3/Kconfig" source "drivers/mfd/Kconfig" -source "drivers/leds/Kconfig" - source "drivers/media/Kconfig" source "drivers/video/Kconfig" @@ -1054,6 +1058,8 @@ source "drivers/usb/Kconfig" source "drivers/mmc/Kconfig" +source "drivers/leds/Kconfig" + source "drivers/rtc/Kconfig" source "drivers/dma/Kconfig" -- cgit v0.10.2 From a06748ab546fa95c497f10c290221f4a9f249f9b Mon Sep 17 00:00:00 2001 From: Russell King Date: Wed, 19 Sep 2007 09:21:51 +0100 Subject: [ARM] pxa: tidy up arch/arm/mach-pxa/Makefile Signed-off-by: Russell King diff --git a/arch/arm/mach-pxa/Makefile b/arch/arm/mach-pxa/Makefile index 7d6ab5c..8970928 100644 --- a/arch/arm/mach-pxa/Makefile +++ b/arch/arm/mach-pxa/Makefile @@ -3,36 +3,36 @@ # # Common support (must be linked before board specific support) -obj-y += clock.o generic.o irq.o dma.o time.o -obj-$(CONFIG_PXA25x) += pxa25x.o -obj-$(CONFIG_PXA27x) += pxa27x.o +obj-y += clock.o generic.o irq.o dma.o time.o +obj-$(CONFIG_PXA25x) += pxa25x.o +obj-$(CONFIG_PXA27x) += pxa27x.o # Specific board support -obj-$(CONFIG_ARCH_LUBBOCK) += lubbock.o +obj-$(CONFIG_ARCH_LUBBOCK) += lubbock.o obj-$(CONFIG_MACH_LOGICPD_PXA270) += lpd270.o -obj-$(CONFIG_MACH_MAINSTONE) += mainstone.o -obj-$(CONFIG_ARCH_PXA_IDP) += idp.o +obj-$(CONFIG_MACH_MAINSTONE) += mainstone.o +obj-$(CONFIG_ARCH_PXA_IDP) += idp.o obj-$(CONFIG_MACH_TRIZEPS4) += trizeps4.o obj-$(CONFIG_PXA_SHARP_C7xx) += corgi.o corgi_ssp.o corgi_lcd.o sharpsl_pm.o corgi_pm.o obj-$(CONFIG_PXA_SHARP_Cxx00) += spitz.o corgi_ssp.o corgi_lcd.o sharpsl_pm.o spitz_pm.o obj-$(CONFIG_MACH_AKITA) += akita-ioexp.o obj-$(CONFIG_MACH_POODLE) += poodle.o corgi_ssp.o -obj-$(CONFIG_MACH_TOSA) += tosa.o -obj-$(CONFIG_MACH_EM_X270) += em-x270.o +obj-$(CONFIG_MACH_TOSA) += tosa.o +obj-$(CONFIG_MACH_EM_X270) += em-x270.o # Support for blinky lights led-y := leds.o -led-$(CONFIG_ARCH_LUBBOCK) += leds-lubbock.o -led-$(CONFIG_MACH_MAINSTONE) += leds-mainstone.o -led-$(CONFIG_ARCH_PXA_IDP) += leds-idp.o -led-$(CONFIG_MACH_TRIZEPS4) += leds-trizeps4.o +led-$(CONFIG_ARCH_LUBBOCK) += leds-lubbock.o +led-$(CONFIG_MACH_MAINSTONE) += leds-mainstone.o +led-$(CONFIG_ARCH_PXA_IDP) += leds-idp.o +led-$(CONFIG_MACH_TRIZEPS4) += leds-trizeps4.o -obj-$(CONFIG_LEDS) += $(led-y) +obj-$(CONFIG_LEDS) += $(led-y) # Misc features -obj-$(CONFIG_PM) += pm.o sleep.o -obj-$(CONFIG_PXA_SSP) += ssp.o +obj-$(CONFIG_PM) += pm.o sleep.o +obj-$(CONFIG_PXA_SSP) += ssp.o ifeq ($(CONFIG_PXA27x),y) -obj-$(CONFIG_PM) += standby.o +obj-$(CONFIG_PM) += standby.o endif -- cgit v0.10.2 From 97d97224ff361e08777fb33e0fd193ca877dac28 Mon Sep 17 00:00:00 2001 From: Russell King Date: Sat, 1 Sep 2007 21:25:09 +0100 Subject: [SERIAL] Fix console initialisation ordering Ensure pm callback is called upon initialisation to place port in correct power saving state. Ensure console is initialised prior to deciding whether to power down the port. Signed-off-by: Russell King diff --git a/drivers/serial/serial_core.c b/drivers/serial/serial_core.c index a055f58..a3bd3a3 100644 --- a/drivers/serial/serial_core.c +++ b/drivers/serial/serial_core.c @@ -2127,6 +2127,14 @@ uart_configure_port(struct uart_driver *drv, struct uart_state *state, spin_unlock_irqrestore(&port->lock, flags); /* + * If this driver supports console, and it hasn't been + * successfully registered yet, try to re-register it. + * It may be that the port was not available. + */ + if (port->cons && !(port->cons->flags & CON_ENABLED)) + register_console(port->cons); + + /* * Power down all ports by default, except the * console if we have one. */ @@ -2286,6 +2294,7 @@ int uart_add_one_port(struct uart_driver *drv, struct uart_port *port) } state->port = port; + state->pm_state = -1; port->cons = drv->cons; port->info = state->info; @@ -2308,15 +2317,6 @@ int uart_add_one_port(struct uart_driver *drv, struct uart_port *port) tty_register_device(drv->tty_driver, port->line, port->dev); /* - * If this driver supports console, and it hasn't been - * successfully registered yet, try to re-register it. - * It may be that the port was not available. - */ - if (port->type != PORT_UNKNOWN && - port->cons && !(port->cons->flags & CON_ENABLED)) - register_console(port->cons); - - /* * Ensure UPF_DEAD is not set. */ port->flags &= ~UPF_DEAD; -- cgit v0.10.2 From 073ac8fd4a3e9a9265e8a59e0a79bc4b0b3822c3 Mon Sep 17 00:00:00 2001 From: Russell King Date: Sat, 1 Sep 2007 21:27:18 +0100 Subject: [NET] smc91x: fix PXA DMA support code The PXA DMA support code for smc91x doesn't pass a struct device to the dma_*map_single() functions, which leads to an oops in the dma bounce code. We have a struct device which was used to probe the SMC chip. Use it. (This patch is slightly larger because it requires struct smc_local to move into the header file.) Signed-off-by: Russell King diff --git a/drivers/net/smc91x.c b/drivers/net/smc91x.c index 24e610e..7da7589 100644 --- a/drivers/net/smc91x.c +++ b/drivers/net/smc91x.c @@ -173,49 +173,6 @@ MODULE_LICENSE("GPL"); */ #define MII_DELAY 1 -/* store this information for the driver.. */ -struct smc_local { - /* - * If I have to wait until memory is available to send a - * packet, I will store the skbuff here, until I get the - * desired memory. Then, I'll send it out and free it. - */ - struct sk_buff *pending_tx_skb; - struct tasklet_struct tx_task; - - /* version/revision of the SMC91x chip */ - int version; - - /* Contains the current active transmission mode */ - int tcr_cur_mode; - - /* Contains the current active receive mode */ - int rcr_cur_mode; - - /* Contains the current active receive/phy mode */ - int rpc_cur_mode; - int ctl_rfduplx; - int ctl_rspeed; - - u32 msg_enable; - u32 phy_type; - struct mii_if_info mii; - - /* work queue */ - struct work_struct phy_configure; - struct net_device *dev; - int work_pending; - - spinlock_t lock; - -#ifdef SMC_USE_PXA_DMA - /* DMA needs the physical address of the chip */ - u_long physaddr; -#endif - void __iomem *base; - void __iomem *datacs; -}; - #if SMC_DEBUG > 0 #define DBG(n, args...) \ do { \ @@ -2215,17 +2172,19 @@ static int smc_drv_probe(struct platform_device *pdev) goto out_release_attrib; } - platform_set_drvdata(pdev, ndev); - ret = smc_probe(ndev, addr); - if (ret != 0) - goto out_iounmap; #ifdef SMC_USE_PXA_DMA - else { + { struct smc_local *lp = netdev_priv(ndev); + lp->device = &pdev->dev; lp->physaddr = res->start; } #endif + platform_set_drvdata(pdev, ndev); + ret = smc_probe(ndev, addr); + if (ret != 0) + goto out_iounmap; + smc_request_datacs(pdev, ndev); return 0; diff --git a/drivers/net/smc91x.h b/drivers/net/smc91x.h index af9e6bf..729fd28 100644 --- a/drivers/net/smc91x.h +++ b/drivers/net/smc91x.h @@ -462,6 +462,52 @@ static inline void LPD7_SMC_outsw (unsigned char* a, int r, #endif + +/* store this information for the driver.. */ +struct smc_local { + /* + * If I have to wait until memory is available to send a + * packet, I will store the skbuff here, until I get the + * desired memory. Then, I'll send it out and free it. + */ + struct sk_buff *pending_tx_skb; + struct tasklet_struct tx_task; + + /* version/revision of the SMC91x chip */ + int version; + + /* Contains the current active transmission mode */ + int tcr_cur_mode; + + /* Contains the current active receive mode */ + int rcr_cur_mode; + + /* Contains the current active receive/phy mode */ + int rpc_cur_mode; + int ctl_rfduplx; + int ctl_rspeed; + + u32 msg_enable; + u32 phy_type; + struct mii_if_info mii; + + /* work queue */ + struct work_struct phy_configure; + struct net_device *dev; + int work_pending; + + spinlock_t lock; + +#ifdef SMC_USE_PXA_DMA + /* DMA needs the physical address of the chip */ + u_long physaddr; + struct device *device; +#endif + void __iomem *base; + void __iomem *datacs; +}; + + #ifdef SMC_USE_PXA_DMA /* * Let's use the DMA engine on the XScale PXA2xx for RX packets. This is @@ -476,11 +522,12 @@ static inline void LPD7_SMC_outsw (unsigned char* a, int r, #ifdef SMC_insl #undef SMC_insl #define SMC_insl(a, r, p, l) \ - smc_pxa_dma_insl(a, lp->physaddr, r, dev->dma, p, l) + smc_pxa_dma_insl(a, lp, r, dev->dma, p, l) static inline void -smc_pxa_dma_insl(void __iomem *ioaddr, u_long physaddr, int reg, int dma, +smc_pxa_dma_insl(void __iomem *ioaddr, struct smc_local *lp, int reg, int dma, u_char *buf, int len) { + u_long physaddr = lp->physaddr; dma_addr_t dmabuf; /* fallback if no DMA available */ @@ -497,7 +544,7 @@ smc_pxa_dma_insl(void __iomem *ioaddr, u_long physaddr, int reg, int dma, } len *= 4; - dmabuf = dma_map_single(NULL, buf, len, DMA_FROM_DEVICE); + dmabuf = dma_map_single(lp->device, buf, len, DMA_FROM_DEVICE); DCSR(dma) = DCSR_NODESC; DTADR(dma) = dmabuf; DSADR(dma) = physaddr + reg; @@ -507,18 +554,19 @@ smc_pxa_dma_insl(void __iomem *ioaddr, u_long physaddr, int reg, int dma, while (!(DCSR(dma) & DCSR_STOPSTATE)) cpu_relax(); DCSR(dma) = 0; - dma_unmap_single(NULL, dmabuf, len, DMA_FROM_DEVICE); + dma_unmap_single(lp->device, dmabuf, len, DMA_FROM_DEVICE); } #endif #ifdef SMC_insw #undef SMC_insw #define SMC_insw(a, r, p, l) \ - smc_pxa_dma_insw(a, lp->physaddr, r, dev->dma, p, l) + smc_pxa_dma_insw(a, lp, r, dev->dma, p, l) static inline void -smc_pxa_dma_insw(void __iomem *ioaddr, u_long physaddr, int reg, int dma, +smc_pxa_dma_insw(void __iomem *ioaddr, struct smc_local *lp, int reg, int dma, u_char *buf, int len) { + u_long physaddr = lp->physaddr; dma_addr_t dmabuf; /* fallback if no DMA available */ @@ -535,7 +583,7 @@ smc_pxa_dma_insw(void __iomem *ioaddr, u_long physaddr, int reg, int dma, } len *= 2; - dmabuf = dma_map_single(NULL, buf, len, DMA_FROM_DEVICE); + dmabuf = dma_map_single(lp->device, buf, len, DMA_FROM_DEVICE); DCSR(dma) = DCSR_NODESC; DTADR(dma) = dmabuf; DSADR(dma) = physaddr + reg; @@ -545,7 +593,7 @@ smc_pxa_dma_insw(void __iomem *ioaddr, u_long physaddr, int reg, int dma, while (!(DCSR(dma) & DCSR_STOPSTATE)) cpu_relax(); DCSR(dma) = 0; - dma_unmap_single(NULL, dmabuf, len, DMA_FROM_DEVICE); + dma_unmap_single(lp->device, dmabuf, len, DMA_FROM_DEVICE); } #endif -- cgit v0.10.2 From 2c8086a5d073e8e72122a5b84febde236a39845b Mon Sep 17 00:00:00 2001 From: eric miao Date: Tue, 11 Sep 2007 19:13:17 -0700 Subject: [ARM] pxa: PXA3xx base support Signed-off-by: eric miao Signed-off-by: Russell King diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 691aae3..a25697b 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -336,14 +336,14 @@ config ARCH_PNX4008 This enables support for Philips PNX4008 mobile platform. config ARCH_PXA - bool "PXA2xx-based" + bool "PXA2xx/PXA3xx-based" depends on MMU select ARCH_MTD_XIP select GENERIC_GPIO select GENERIC_TIME select GENERIC_CLOCKEVENTS help - Support for Intel's PXA2XX processor line. + Support for Intel/Marvell's PXA2xx/PXA3xx processor line. config ARCH_RPC bool "RiscPC" @@ -486,7 +486,7 @@ source arch/arm/mm/Kconfig config IWMMXT bool "Enable iWMMXt support" depends on CPU_XSCALE || CPU_XSC3 - default y if PXA27x + default y if PXA27x || PXA3xx help Enable support for iWMMXt context switching at run time if running on a CPU that supports it. diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig index 5ebec6d..e895188 100644 --- a/arch/arm/mach-pxa/Kconfig +++ b/arch/arm/mach-pxa/Kconfig @@ -1,6 +1,24 @@ if ARCH_PXA -menu "Intel PXA2xx Implementations" +menu "Intel PXA2xx/PXA3xx Implementations" + +if PXA3xx + +menu "Supported PXA3xx Processor Variants" + +config CPU_PXA300 + bool "PXA300 (codename Monahans-L)" + +config CPU_PXA310 + bool "PXA310 (codename Monahans-LV)" + select CPU_PXA300 + +config CPU_PXA320 + bool "PXA320 (codename Monahans-P)" + +endmenu + +endif choice prompt "Select target board" @@ -41,6 +59,10 @@ config MACH_EM_X270 bool "CompuLab EM-x270 platform" select PXA27x +config MACH_ZYLONITE + bool "PXA3xx Development Platform" + select PXA3xx + endchoice if PXA_SHARPSL @@ -130,6 +152,11 @@ config PXA27x help Select code specific to PXA27x variants +config PXA3xx + bool + help + Select code specific to PXA3xx variants + config PXA_SHARP_C7xx bool select PXA_SSP diff --git a/arch/arm/mach-pxa/Makefile b/arch/arm/mach-pxa/Makefile index 8970928..bfdd0c5 100644 --- a/arch/arm/mach-pxa/Makefile +++ b/arch/arm/mach-pxa/Makefile @@ -6,6 +6,9 @@ obj-y += clock.o generic.o irq.o dma.o time.o obj-$(CONFIG_PXA25x) += pxa25x.o obj-$(CONFIG_PXA27x) += pxa27x.o +obj-$(CONFIG_PXA3xx) += pxa3xx.o mfp.o +obj-$(CONFIG_CPU_PXA300) += pxa300.o +obj-$(CONFIG_CPU_PXA320) += pxa320.o # Specific board support obj-$(CONFIG_ARCH_LUBBOCK) += lubbock.o @@ -20,6 +23,12 @@ obj-$(CONFIG_MACH_POODLE) += poodle.o corgi_ssp.o obj-$(CONFIG_MACH_TOSA) += tosa.o obj-$(CONFIG_MACH_EM_X270) += em-x270.o +ifeq ($(CONFIG_MACH_ZYLONITE),y) + obj-y += zylonite.o + obj-$(CONFIG_CPU_PXA300) += zylonite_pxa300.o + obj-$(CONFIG_CPU_PXA320) += zylonite_pxa320.o +endif + # Support for blinky lights led-y := leds.o led-$(CONFIG_ARCH_LUBBOCK) += leds-lubbock.o diff --git a/arch/arm/mach-pxa/generic.c b/arch/arm/mach-pxa/generic.c index eed95eaf..2263a84 100644 --- a/arch/arm/mach-pxa/generic.c +++ b/arch/arm/mach-pxa/generic.c @@ -51,8 +51,10 @@ unsigned int get_clk_frequency_khz(int info) { if (cpu_is_pxa21x() || cpu_is_pxa25x()) return pxa25x_get_clk_frequency_khz(info); - else + else if (cpu_is_pxa27x()) return pxa27x_get_clk_frequency_khz(info); + else + return pxa3xx_get_clk_frequency_khz(info); } EXPORT_SYMBOL(get_clk_frequency_khz); @@ -63,8 +65,10 @@ unsigned int get_memclk_frequency_10khz(void) { if (cpu_is_pxa21x() || cpu_is_pxa25x()) return pxa25x_get_memclk_frequency_10khz(); - else + else if (cpu_is_pxa27x()) return pxa27x_get_memclk_frequency_10khz(); + else + return pxa3xx_get_memclk_frequency_10khz(); } EXPORT_SYMBOL(get_memclk_frequency_10khz); diff --git a/arch/arm/mach-pxa/generic.h b/arch/arm/mach-pxa/generic.h index 2c4fe61..b30f240 100644 --- a/arch/arm/mach-pxa/generic.h +++ b/arch/arm/mach-pxa/generic.h @@ -18,6 +18,7 @@ extern void __init pxa_init_irq_gpio(int gpio_nr); extern void __init pxa_init_irq_set_wake(int (*set_wake)(unsigned int, unsigned int)); extern void __init pxa25x_init_irq(void); extern void __init pxa27x_init_irq(void); +extern void __init pxa3xx_init_irq(void); extern void __init pxa_map_io(void); extern unsigned int get_clk_frequency_khz(int info); @@ -44,3 +45,10 @@ extern unsigned pxa27x_get_memclk_frequency_10khz(void); #define pxa27x_get_memclk_frequency_10khz() (0) #endif +#ifdef CONFIG_PXA3xx +extern unsigned pxa3xx_get_clk_frequency_khz(int); +extern unsigned pxa3xx_get_memclk_frequency_10khz(void); +#else +#define pxa3xx_get_clk_frequency_khz(x) (0) +#define pxa3xx_get_memclk_frequency_10khz() (0) +#endif diff --git a/arch/arm/mach-pxa/irq.c b/arch/arm/mach-pxa/irq.c index 294cc67..07acb45 100644 --- a/arch/arm/mach-pxa/irq.c +++ b/arch/arm/mach-pxa/irq.c @@ -65,7 +65,7 @@ void __init pxa_init_irq_low(void) } } -#ifdef CONFIG_PXA27x +#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx) /* * This is for the second set of internal IRQs as found on the PXA27x. diff --git a/arch/arm/mach-pxa/mfp.c b/arch/arm/mach-pxa/mfp.c new file mode 100644 index 0000000..5cd3cad --- /dev/null +++ b/arch/arm/mach-pxa/mfp.c @@ -0,0 +1,235 @@ +/* + * linux/arch/arm/mach-pxa/mfp.c + * + * PXA3xx Multi-Function Pin Support + * + * Copyright (C) 2007 Marvell Internation Ltd. + * + * 2007-08-21: eric miao + * initial version + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include + +#include +#include + +/* mfp_spin_lock is used to ensure that MFP register configuration + * (most likely a read-modify-write operation) is atomic, and that + * mfp_table[] is consistent + */ +static DEFINE_SPINLOCK(mfp_spin_lock); + +static void __iomem *mfpr_mmio_base = (void __iomem *)&__REG(MFPR_BASE); +static struct pxa3xx_mfp_pin mfp_table[MFP_PIN_MAX]; + +#define mfpr_readl(off) \ + __raw_readl(mfpr_mmio_base + (off)) + +#define mfpr_writel(off, val) \ + __raw_writel(val, mfpr_mmio_base + (off)) + +/* + * perform a read-back of any MFPR register to make sure the + * previous writings are finished + */ +#define mfpr_sync() (void)__raw_readl(mfpr_mmio_base + 0) + +static inline void __mfp_config(int pin, unsigned long val) +{ + unsigned long off = mfp_table[pin].mfpr_off; + + mfp_table[pin].mfpr_val = val; + mfpr_writel(off, val); +} + +void pxa3xx_mfp_config(mfp_cfg_t *mfp_cfgs, int num) +{ + int i, pin; + unsigned long val, flags; + mfp_cfg_t *mfp_cfg = mfp_cfgs; + + spin_lock_irqsave(&mfp_spin_lock, flags); + + for (i = 0; i < num; i++, mfp_cfg++) { + pin = MFP_CFG_PIN(*mfp_cfg); + val = MFP_CFG_VAL(*mfp_cfg); + + BUG_ON(pin >= MFP_PIN_MAX); + + __mfp_config(pin, val); + } + + mfpr_sync(); + spin_unlock_irqrestore(&mfp_spin_lock, flags); +} + +unsigned long pxa3xx_mfp_read(int mfp) +{ + unsigned long val, flags; + + BUG_ON(mfp >= MFP_PIN_MAX); + + spin_lock_irqsave(&mfp_spin_lock, flags); + val = mfpr_readl(mfp_table[mfp].mfpr_off); + spin_unlock_irqrestore(&mfp_spin_lock, flags); + + return val; +} + +void pxa3xx_mfp_write(int mfp, unsigned long val) +{ + unsigned long flags; + + BUG_ON(mfp >= MFP_PIN_MAX); + + spin_lock_irqsave(&mfp_spin_lock, flags); + mfpr_writel(mfp_table[mfp].mfpr_off, val); + mfpr_sync(); + spin_unlock_irqrestore(&mfp_spin_lock, flags); +} + +void pxa3xx_mfp_set_afds(int mfp, int af, int ds) +{ + uint32_t mfpr_off, mfpr_val; + unsigned long flags; + + BUG_ON(mfp >= MFP_PIN_MAX); + + spin_lock_irqsave(&mfp_spin_lock, flags); + mfpr_off = mfp_table[mfp].mfpr_off; + + mfpr_val = mfpr_readl(mfpr_off); + mfpr_val &= ~(MFPR_AF_MASK | MFPR_DRV_MASK); + mfpr_val |= (((af & 0x7) << MFPR_ALT_OFFSET) | + ((ds & 0x7) << MFPR_DRV_OFFSET)); + + mfpr_writel(mfpr_off, mfpr_val); + mfpr_sync(); + + spin_unlock_irqrestore(&mfp_spin_lock, flags); +} + +void pxa3xx_mfp_set_rdh(int mfp, int rdh) +{ + uint32_t mfpr_off, mfpr_val; + unsigned long flags; + + BUG_ON(mfp >= MFP_PIN_MAX); + + spin_lock_irqsave(&mfp_spin_lock, flags); + + mfpr_off = mfp_table[mfp].mfpr_off; + + mfpr_val = mfpr_readl(mfpr_off); + mfpr_val &= ~MFPR_RDH_MASK; + + if (likely(rdh)) + mfpr_val |= (1u << MFPR_SS_OFFSET); + + mfpr_writel(mfpr_off, mfpr_val); + mfpr_sync(); + + spin_unlock_irqrestore(&mfp_spin_lock, flags); +} + +void pxa3xx_mfp_set_lpm(int mfp, int lpm) +{ + uint32_t mfpr_off, mfpr_val; + unsigned long flags; + + BUG_ON(mfp >= MFP_PIN_MAX); + + spin_lock_irqsave(&mfp_spin_lock, flags); + + mfpr_off = mfp_table[mfp].mfpr_off; + mfpr_val = mfpr_readl(mfpr_off); + mfpr_val &= ~MFPR_LPM_MASK; + + if (lpm & 0x1) mfpr_val |= 1u << MFPR_SON_OFFSET; + if (lpm & 0x2) mfpr_val |= 1u << MFPR_SD_OFFSET; + if (lpm & 0x4) mfpr_val |= 1u << MFPR_PU_OFFSET; + if (lpm & 0x8) mfpr_val |= 1u << MFPR_PD_OFFSET; + if (lpm &0x10) mfpr_val |= 1u << MFPR_PS_OFFSET; + + mfpr_writel(mfpr_off, mfpr_val); + mfpr_sync(); + + spin_unlock_irqrestore(&mfp_spin_lock, flags); +} + +void pxa3xx_mfp_set_pull(int mfp, int pull) +{ + uint32_t mfpr_off, mfpr_val; + unsigned long flags; + + BUG_ON(mfp >= MFP_PIN_MAX); + + spin_lock_irqsave(&mfp_spin_lock, flags); + + mfpr_off = mfp_table[mfp].mfpr_off; + mfpr_val = mfpr_readl(mfpr_off); + mfpr_val &= ~MFPR_PULL_MASK; + mfpr_val |= ((pull & 0x7u) << MFPR_PD_OFFSET); + + mfpr_writel(mfpr_off, mfpr_val); + mfpr_sync(); + + spin_unlock_irqrestore(&mfp_spin_lock, flags); +} + +void pxa3xx_mfp_set_edge(int mfp, int edge) +{ + uint32_t mfpr_off, mfpr_val; + unsigned long flags; + + BUG_ON(mfp >= MFP_PIN_MAX); + + spin_lock_irqsave(&mfp_spin_lock, flags); + + mfpr_off = mfp_table[mfp].mfpr_off; + mfpr_val = mfpr_readl(mfpr_off); + + mfpr_val &= ~MFPR_EDGE_MASK; + mfpr_val |= (edge & 0x3u) << MFPR_ERE_OFFSET; + mfpr_val |= (!edge & 0x1) << MFPR_EC_OFFSET; + + mfpr_writel(mfpr_off, mfpr_val); + mfpr_sync(); + + spin_unlock_irqrestore(&mfp_spin_lock, flags); +} + +void __init pxa3xx_mfp_init_addr(struct pxa3xx_mfp_addr_map *map) +{ + struct pxa3xx_mfp_addr_map *p; + unsigned long offset, flags; + int i; + + spin_lock_irqsave(&mfp_spin_lock, flags); + + for (p = map; p->start != MFP_PIN_INVALID; p++) { + offset = p->offset; + i = p->start; + + do { + mfp_table[i].mfpr_off = offset; + mfp_table[i].mfpr_val = 0; + offset += 4; i++; + } while ((i <= p->end) && (p->end != -1)); + } + + spin_unlock_irqrestore(&mfp_spin_lock, flags); +} + +void __init pxa3xx_init_mfp(void) +{ + memset(mfp_table, 0, sizeof(mfp_table)); +} diff --git a/arch/arm/mach-pxa/pxa300.c b/arch/arm/mach-pxa/pxa300.c new file mode 100644 index 0000000..5363b13 --- /dev/null +++ b/arch/arm/mach-pxa/pxa300.c @@ -0,0 +1,93 @@ +/* + * linux/arch/arm/mach-pxa/pxa300.c + * + * Code specific to PXA300/PXA310 + * + * Copyright (C) 2007 Marvell Internation Ltd. + * + * 2007-08-21: eric miao + * initial version + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include + +#include +#include + +static struct pxa3xx_mfp_addr_map pxa300_mfp_addr_map[] __initdata = { + + MFP_ADDR_X(GPIO0, GPIO2, 0x00b4), + MFP_ADDR_X(GPIO3, GPIO26, 0x027c), + MFP_ADDR_X(GPIO27, GPIO127, 0x0400), + MFP_ADDR_X(GPIO0_2, GPIO6_2, 0x02ec), + + MFP_ADDR(nBE0, 0x0204), + MFP_ADDR(nBE1, 0x0208), + + MFP_ADDR(nLUA, 0x0244), + MFP_ADDR(nLLA, 0x0254), + + MFP_ADDR(DF_CLE_nOE, 0x0240), + MFP_ADDR(DF_nRE_nOE, 0x0200), + MFP_ADDR(DF_ALE_nWE, 0x020C), + MFP_ADDR(DF_INT_RnB, 0x00C8), + MFP_ADDR(DF_nCS0, 0x0248), + MFP_ADDR(DF_nCS1, 0x0278), + MFP_ADDR(DF_nWE, 0x00CC), + + MFP_ADDR(DF_ADDR0, 0x0210), + MFP_ADDR(DF_ADDR1, 0x0214), + MFP_ADDR(DF_ADDR2, 0x0218), + MFP_ADDR(DF_ADDR3, 0x021C), + + MFP_ADDR(DF_IO0, 0x0220), + MFP_ADDR(DF_IO1, 0x0228), + MFP_ADDR(DF_IO2, 0x0230), + MFP_ADDR(DF_IO3, 0x0238), + MFP_ADDR(DF_IO4, 0x0258), + MFP_ADDR(DF_IO5, 0x0260), + MFP_ADDR(DF_IO6, 0x0268), + MFP_ADDR(DF_IO7, 0x0270), + MFP_ADDR(DF_IO8, 0x0224), + MFP_ADDR(DF_IO9, 0x022C), + MFP_ADDR(DF_IO10, 0x0234), + MFP_ADDR(DF_IO11, 0x023C), + MFP_ADDR(DF_IO12, 0x025C), + MFP_ADDR(DF_IO13, 0x0264), + MFP_ADDR(DF_IO14, 0x026C), + MFP_ADDR(DF_IO15, 0x0274), + + MFP_ADDR_END, +}; + +/* override pxa300 MFP register addresses */ +static struct pxa3xx_mfp_addr_map pxa310_mfp_addr_map[] __initdata = { + MFP_ADDR_X(GPIO30, GPIO98, 0x0418), + MFP_ADDR_X(GPIO7_2, GPIO12_2, 0x052C), + + MFP_ADDR(ULPI_STP, 0x040C), + MFP_ADDR(ULPI_NXT, 0x0410), + MFP_ADDR(ULPI_DIR, 0x0414), + + MFP_ADDR_END, +}; + +static int __init pxa300_init(void) +{ + if (cpu_is_pxa300() || cpu_is_pxa310()) { + pxa3xx_init_mfp(); + pxa3xx_mfp_init_addr(pxa300_mfp_addr_map); + } + + if (cpu_is_pxa310()) + pxa3xx_mfp_init_addr(pxa310_mfp_addr_map); + + return 0; +} + +core_initcall(pxa300_init); diff --git a/arch/arm/mach-pxa/pxa320.c b/arch/arm/mach-pxa/pxa320.c new file mode 100644 index 0000000..cd9eba5 --- /dev/null +++ b/arch/arm/mach-pxa/pxa320.c @@ -0,0 +1,88 @@ +/* + * linux/arch/arm/mach-pxa/pxa320.c + * + * Code specific to PXA320 + * + * Copyright (C) 2007 Marvell Internation Ltd. + * + * 2007-08-21: eric miao + * initial version + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include + +#include +#include +#include + +static struct pxa3xx_mfp_addr_map pxa320_mfp_addr_map[] __initdata = { + + MFP_ADDR_X(GPIO0, GPIO4, 0x0124), + MFP_ADDR_X(GPIO5, GPIO26, 0x028C), + MFP_ADDR_X(GPIO27, GPIO62, 0x0400), + MFP_ADDR_X(GPIO63, GPIO73, 0x04B4), + MFP_ADDR_X(GPIO74, GPIO98, 0x04F0), + MFP_ADDR_X(GPIO99, GPIO127, 0x0600), + MFP_ADDR_X(GPIO0_2, GPIO5_2, 0x0674), + MFP_ADDR_X(GPIO6_2, GPIO13_2, 0x0494), + MFP_ADDR_X(GPIO14_2, GPIO17_2, 0x04E0), + + MFP_ADDR(nXCVREN, 0x0138), + MFP_ADDR(DF_CLE_nOE, 0x0204), + MFP_ADDR(DF_nADV1_ALE, 0x0208), + MFP_ADDR(DF_SCLK_S, 0x020C), + MFP_ADDR(DF_SCLK_E, 0x0210), + MFP_ADDR(nBE0, 0x0214), + MFP_ADDR(nBE1, 0x0218), + MFP_ADDR(DF_nADV2_ALE, 0x021C), + MFP_ADDR(DF_INT_RnB, 0x0220), + MFP_ADDR(DF_nCS0, 0x0224), + MFP_ADDR(DF_nCS1, 0x0228), + MFP_ADDR(DF_nWE, 0x022C), + MFP_ADDR(DF_nRE_nOE, 0x0230), + MFP_ADDR(nLUA, 0x0234), + MFP_ADDR(nLLA, 0x0238), + MFP_ADDR(DF_ADDR0, 0x023C), + MFP_ADDR(DF_ADDR1, 0x0240), + MFP_ADDR(DF_ADDR2, 0x0244), + MFP_ADDR(DF_ADDR3, 0x0248), + MFP_ADDR(DF_IO0, 0x024C), + MFP_ADDR(DF_IO8, 0x0250), + MFP_ADDR(DF_IO1, 0x0254), + MFP_ADDR(DF_IO9, 0x0258), + MFP_ADDR(DF_IO2, 0x025C), + MFP_ADDR(DF_IO10, 0x0260), + MFP_ADDR(DF_IO3, 0x0264), + MFP_ADDR(DF_IO11, 0x0268), + MFP_ADDR(DF_IO4, 0x026C), + MFP_ADDR(DF_IO12, 0x0270), + MFP_ADDR(DF_IO5, 0x0274), + MFP_ADDR(DF_IO13, 0x0278), + MFP_ADDR(DF_IO6, 0x027C), + MFP_ADDR(DF_IO14, 0x0280), + MFP_ADDR(DF_IO7, 0x0284), + MFP_ADDR(DF_IO15, 0x0288), + + MFP_ADDR_END, +}; + +static void __init pxa320_init_mfp(void) +{ + pxa3xx_init_mfp(); + pxa3xx_mfp_init_addr(pxa320_mfp_addr_map); +} + +static int __init pxa320_init(void) +{ + if (cpu_is_pxa320()) + pxa320_init_mfp(); + + return 0; +} + +core_initcall(pxa320_init); diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c new file mode 100644 index 0000000..39f0de8 --- /dev/null +++ b/arch/arm/mach-pxa/pxa3xx.c @@ -0,0 +1,216 @@ +/* + * linux/arch/arm/mach-pxa/pxa3xx.c + * + * code specific to pxa3xx aka Monahans + * + * Copyright (C) 2006 Marvell International Ltd. + * + * 2007-09-02: eric miao + * initial version + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include "generic.h" +#include "devices.h" +#include "clock.h" + +/* Crystal clock: 13MHz */ +#define BASE_CLK 13000000 + +/* Ring Oscillator Clock: 60MHz */ +#define RO_CLK 60000000 + +#define ACCR_D0CS (1 << 26) + +/* crystal frequency to static memory controller multiplier (SMCFS) */ +static unsigned char smcfs_mult[8] = { 6, 0, 8, 0, 0, 16, }; + +/* crystal frequency to HSIO bus frequency multiplier (HSS) */ +static unsigned char hss_mult[4] = { 8, 12, 16, 0 }; + +/* + * Get the clock frequency as reflected by CCSR and the turbo flag. + * We assume these values have been applied via a fcs. + * If info is not 0 we also display the current settings. + */ +unsigned int pxa3xx_get_clk_frequency_khz(int info) +{ + unsigned long acsr, xclkcfg; + unsigned int t, xl, xn, hss, ro, XL, XN, CLK, HSS; + + /* Read XCLKCFG register turbo bit */ + __asm__ __volatile__("mrc\tp14, 0, %0, c6, c0, 0" : "=r"(xclkcfg)); + t = xclkcfg & 0x1; + + acsr = ACSR; + + xl = acsr & 0x1f; + xn = (acsr >> 8) & 0x7; + hss = (acsr >> 14) & 0x3; + + XL = xl * BASE_CLK; + XN = xn * XL; + + ro = acsr & ACCR_D0CS; + + CLK = (ro) ? RO_CLK : ((t) ? XN : XL); + HSS = (ro) ? RO_CLK : hss_mult[hss] * BASE_CLK; + + if (info) { + pr_info("RO Mode clock: %d.%02dMHz (%sactive)\n", + RO_CLK / 1000000, (RO_CLK % 1000000) / 10000, + (ro) ? "" : "in"); + pr_info("Run Mode clock: %d.%02dMHz (*%d)\n", + XL / 1000000, (XL % 1000000) / 10000, xl); + pr_info("Turbo Mode clock: %d.%02dMHz (*%d, %sactive)\n", + XN / 1000000, (XN % 1000000) / 10000, xn, + (t) ? "" : "in"); + pr_info("HSIO bus clock: %d.%02dMHz\n", + HSS / 1000000, (HSS % 1000000) / 10000); + } + + return CLK; +} + +/* + * Return the current static memory controller clock frequency + * in units of 10kHz + */ +unsigned int pxa3xx_get_memclk_frequency_10khz(void) +{ + unsigned long acsr; + unsigned int smcfs, clk = 0; + + acsr = ACSR; + + smcfs = (acsr >> 23) & 0x7; + clk = (acsr & ACCR_D0CS) ? RO_CLK : smcfs_mult[smcfs] * BASE_CLK; + + return (clk / 10000); +} + +/* + * Return the current HSIO bus clock frequency + */ +static unsigned long clk_pxa3xx_hsio_getrate(struct clk *clk) +{ + unsigned long acsr; + unsigned int hss, hsio_clk; + + acsr = ACSR; + + hss = (acsr >> 14) & 0x3; + hsio_clk = (acsr & ACCR_D0CS) ? RO_CLK : hss_mult[hss] * BASE_CLK; + + return hsio_clk; +} + +static void clk_pxa3xx_cken_enable(struct clk *clk) +{ + unsigned long mask = 1ul << (clk->cken & 0x1f); + + local_irq_disable(); + + if (clk->cken < 32) + CKENA |= mask; + else + CKENB |= mask; + + local_irq_enable(); +} + +static void clk_pxa3xx_cken_disable(struct clk *clk) +{ + unsigned long mask = 1ul << (clk->cken & 0x1f); + + local_irq_disable(); + + if (clk->cken < 32) + CKENA &= ~mask; + else + CKENB &= ~mask; + + local_irq_enable(); +} + +static const struct clkops clk_pxa3xx_hsio_ops = { + .enable = clk_pxa3xx_cken_enable, + .disable = clk_pxa3xx_cken_disable, + .getrate = clk_pxa3xx_hsio_getrate, +}; + +static struct clk pxa3xx_clks[] = { + INIT_CK("LCDCLK", LCD, &clk_pxa3xx_hsio_ops, &pxa_device_fb.dev), + INIT_CK("CAMCLK", CAMERA, &clk_pxa3xx_hsio_ops, NULL), + + INIT_CKEN("UARTCLK", FFUART, 14857000, 1, &pxa_device_ffuart.dev), + INIT_CKEN("UARTCLK", BTUART, 14857000, 1, &pxa_device_btuart.dev), + INIT_CKEN("UARTCLK", STUART, 14857000, 1, NULL), + + INIT_CKEN("I2CCLK", I2C, 32842000, 0, &pxa_device_i2c.dev), + INIT_CKEN("UDCCLK", UDC, 48000000, 5, &pxa_device_udc.dev), +}; + +void __init pxa3xx_init_irq(void) +{ + /* enable CP6 access */ + u32 value; + __asm__ __volatile__("mrc p15, 0, %0, c15, c1, 0\n": "=r"(value)); + value |= (1 << 6); + __asm__ __volatile__("mcr p15, 0, %0, c15, c1, 0\n": :"r"(value)); + + pxa_init_irq_low(); + pxa_init_irq_high(); + pxa_init_irq_gpio(128); +} + +/* + * device registration specific to PXA3xx. + */ + +static struct platform_device *devices[] __initdata = { + &pxa_device_mci, + &pxa_device_udc, + &pxa_device_fb, + &pxa_device_ffuart, + &pxa_device_btuart, + &pxa_device_stuart, + &pxa_device_i2c, + &pxa_device_i2s, + &pxa_device_ficp, + &pxa_device_rtc, +}; + +static int __init pxa3xx_init(void) +{ + int ret = 0; + + if (cpu_is_pxa3xx()) { + clks_register(pxa3xx_clks, ARRAY_SIZE(pxa3xx_clks)); + + if ((ret = pxa_init_dma(32))) + return ret; + + return platform_add_devices(devices, ARRAY_SIZE(devices)); + } + return 0; +} + +subsys_initcall(pxa3xx_init); diff --git a/arch/arm/mach-pxa/zylonite.c b/arch/arm/mach-pxa/zylonite.c new file mode 100644 index 0000000..3f18d76 --- /dev/null +++ b/arch/arm/mach-pxa/zylonite.c @@ -0,0 +1,184 @@ +/* + * linux/arch/arm/mach-pxa/zylonite.c + * + * Support for the PXA3xx Development Platform (aka Zylonite) + * + * Copyright (C) 2006 Marvell International Ltd. + * + * 2007-09-04: eric miao + * rewrite to align with latest kernel + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include "generic.h" + +int gpio_backlight; +int gpio_eth_irq; + +int lcd_id; +int lcd_orientation; + +static struct resource smc91x_resources[] = { + [0] = { + .start = ZYLONITE_ETH_PHYS + 0x300, + .end = ZYLONITE_ETH_PHYS + 0xfffff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = -1, /* for run-time assignment */ + .end = -1, + .flags = IORESOURCE_IRQ, + } +}; + +static struct platform_device smc91x_device = { + .name = "smc91x", + .id = 0, + .num_resources = ARRAY_SIZE(smc91x_resources), + .resource = smc91x_resources, +}; + +#if defined(CONFIG_FB_PXA) || (CONFIG_FB_PXA_MODULES) +static void zylonite_backlight_power(int on) +{ + gpio_set_value(gpio_backlight, on); +} + +static struct pxafb_mode_info toshiba_ltm035a776c_mode = { + .pixclock = 110000, + .xres = 240, + .yres = 320, + .bpp = 16, + .hsync_len = 4, + .left_margin = 6, + .right_margin = 4, + .vsync_len = 2, + .upper_margin = 2, + .lower_margin = 3, + .sync = FB_SYNC_VERT_HIGH_ACT, +}; + +static struct pxafb_mode_info toshiba_ltm04c380k_mode = { + .pixclock = 50000, + .xres = 640, + .yres = 480, + .bpp = 16, + .hsync_len = 1, + .left_margin = 0x9f, + .right_margin = 1, + .vsync_len = 44, + .upper_margin = 0, + .lower_margin = 0, + .sync = FB_SYNC_HOR_HIGH_ACT|FB_SYNC_VERT_HIGH_ACT, +}; + +static struct pxafb_mach_info zylonite_toshiba_lcd_info = { + .num_modes = 1, + .lccr0 = LCCR0_Act, + .lccr3 = LCCR3_PCP, + .pxafb_backlight_power = zylonite_backlight_power, +}; + +static struct pxafb_mode_info sharp_ls037_modes[] = { + [0] = { + .pixclock = 158000, + .xres = 240, + .yres = 320, + .bpp = 16, + .hsync_len = 4, + .left_margin = 39, + .right_margin = 39, + .vsync_len = 1, + .upper_margin = 2, + .lower_margin = 3, + .sync = 0, + }, + [1] = { + .pixclock = 39700, + .xres = 480, + .yres = 640, + .bpp = 16, + .hsync_len = 8, + .left_margin = 81, + .right_margin = 81, + .vsync_len = 1, + .upper_margin = 2, + .lower_margin = 7, + .sync = 0, + }, +}; + +static struct pxafb_mach_info zylonite_sharp_lcd_info = { + .modes = sharp_ls037_modes, + .num_modes = 2, + .lccr0 = LCCR0_Act, + .lccr3 = LCCR3_PCP | LCCR3_HSP | LCCR3_VSP, + .pxafb_backlight_power = zylonite_backlight_power, +}; + +static void __init zylonite_init_lcd(void) +{ + /* backlight GPIO: output, default on */ + gpio_direction_output(gpio_backlight, 1); + + if (lcd_id & 0x20) { + set_pxa_fb_info(&zylonite_sharp_lcd_info); + return; + } + + /* legacy LCD panels, it would be handy here if LCD panel type can + * be decided at run-time + */ + if (1) + zylonite_toshiba_lcd_info.modes = &toshiba_ltm035a776c_mode; + else + zylonite_toshiba_lcd_info.modes = &toshiba_ltm04c380k_mode; + + set_pxa_fb_info(&zylonite_toshiba_lcd_info); +} +#else +static inline void zylonite_init_lcd(void) {} +#endif + +static void __init zylonite_init(void) +{ + /* board-processor specific initialization */ + zylonite_pxa300_init(); + zylonite_pxa320_init(); + + /* + * Note: We depend that the bootloader set + * the correct value to MSC register for SMC91x. + */ + smc91x_resources[1].start = gpio_to_irq(gpio_eth_irq); + smc91x_resources[1].end = gpio_to_irq(gpio_eth_irq); + platform_device_register(&smc91x_device); + + zylonite_init_lcd(); +} + +MACHINE_START(ZYLONITE, "PXA3xx Platform Development Kit (aka Zylonite)") + .phys_io = 0x40000000, + .boot_params = 0xa0000100, + .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc, + .map_io = pxa_map_io, + .init_irq = pxa3xx_init_irq, + .timer = &pxa_timer, + .init_machine = zylonite_init, +MACHINE_END diff --git a/arch/arm/mach-pxa/zylonite_pxa300.c b/arch/arm/mach-pxa/zylonite_pxa300.c new file mode 100644 index 0000000..b5fbd2f --- /dev/null +++ b/arch/arm/mach-pxa/zylonite_pxa300.c @@ -0,0 +1,188 @@ +/* + * linux/arch/arm/mach-pxa/zylonite_pxa300.c + * + * PXA300/PXA310 specific support code for the + * PXA3xx Development Platform (aka Zylonite) + * + * Copyright (C) 2007 Marvell Internation Ltd. + * 2007-08-21: eric miao + * initial version + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include + +#include +#include +#include + +#define ARRAY_AND_SIZE(x) (x), ARRAY_SIZE(x) + +/* PXA300/PXA310 common configurations */ +static mfp_cfg_t common_mfp_cfg[] __initdata = { + /* LCD */ + GPIO54_LCD_LDD_0, + GPIO55_LCD_LDD_1, + GPIO56_LCD_LDD_2, + GPIO57_LCD_LDD_3, + GPIO58_LCD_LDD_4, + GPIO59_LCD_LDD_5, + GPIO60_LCD_LDD_6, + GPIO61_LCD_LDD_7, + GPIO62_LCD_LDD_8, + GPIO63_LCD_LDD_9, + GPIO64_LCD_LDD_10, + GPIO65_LCD_LDD_11, + GPIO66_LCD_LDD_12, + GPIO67_LCD_LDD_13, + GPIO68_LCD_LDD_14, + GPIO69_LCD_LDD_15, + GPIO70_LCD_LDD_16, + GPIO71_LCD_LDD_17, + GPIO72_LCD_FCLK, + GPIO73_LCD_LCLK, + GPIO74_LCD_PCLK, + GPIO75_LCD_BIAS, + GPIO76_LCD_VSYNC, + GPIO127_LCD_CS_N, + + /* BTUART */ + GPIO111_UART2_RTS, + GPIO112_UART2_RXD, + GPIO113_UART2_TXD, + GPIO114_UART2_CTS, + + /* STUART */ + GPIO109_UART3_TXD, + GPIO110_UART3_RXD, + + /* AC97 */ + GPIO23_AC97_nACRESET, + GPIO24_AC97_SYSCLK, + GPIO29_AC97_BITCLK, + GPIO25_AC97_SDATA_IN_0, + GPIO27_AC97_SDATA_OUT, + GPIO28_AC97_SYNC, + + /* Keypad */ + GPIO107_KP_DKIN_0, + GPIO108_KP_DKIN_1, + GPIO115_KP_MKIN_0, + GPIO116_KP_MKIN_1, + GPIO117_KP_MKIN_2, + GPIO118_KP_MKIN_3, + GPIO119_KP_MKIN_4, + GPIO120_KP_MKIN_5, + GPIO2_2_KP_MKIN_6, + GPIO3_2_KP_MKIN_7, + GPIO121_KP_MKOUT_0, + GPIO122_KP_MKOUT_1, + GPIO123_KP_MKOUT_2, + GPIO124_KP_MKOUT_3, + GPIO125_KP_MKOUT_4, + GPIO4_2_KP_MKOUT_5, + GPIO5_2_KP_MKOUT_6, + GPIO6_2_KP_MKOUT_7, +}; + +static mfp_cfg_t pxa300_mfp_cfg[] __initdata = { + /* FFUART */ + GPIO30_UART1_RXD, + GPIO31_UART1_TXD, + GPIO32_UART1_CTS, + GPIO37_UART1_RTS, + GPIO33_UART1_DCD, + GPIO34_UART1_DSR, + GPIO35_UART1_RI, + GPIO36_UART1_DTR, + + /* Ethernet */ + GPIO2_nCS3, + GPIO99_GPIO, +}; + +static mfp_cfg_t pxa310_mfp_cfg[] __initdata = { + /* FFUART */ + GPIO99_UART1_RXD, + GPIO100_UART1_TXD, + GPIO101_UART1_CTS, + GPIO106_UART1_RTS, + + /* Ethernet */ + GPIO2_nCS3, + GPIO102_GPIO, +}; + +#define NUM_LCD_DETECT_PINS 7 + +static int lcd_detect_pins[] __initdata = { + MFP_PIN_GPIO71, /* LCD_LDD_17 - ORIENT */ + MFP_PIN_GPIO70, /* LCD_LDD_16 - LCDID[5] */ + MFP_PIN_GPIO75, /* LCD_BIAS - LCDID[4] */ + MFP_PIN_GPIO73, /* LCD_LCLK - LCDID[3] */ + MFP_PIN_GPIO72, /* LCD_FCLK - LCDID[2] */ + MFP_PIN_GPIO127,/* LCD_CS_N - LCDID[1] */ + MFP_PIN_GPIO76, /* LCD_VSYNC - LCDID[0] */ +}; + +static void __init zylonite_detect_lcd_panel(void) +{ + unsigned long mfpr_save[NUM_LCD_DETECT_PINS]; + int i, gpio, id = 0; + + /* save the original MFP settings of these pins and configure + * them as GPIO Input, DS01X, Pull Neither, Edge Clear + */ + for (i = 0; i < NUM_LCD_DETECT_PINS; i++) { + mfpr_save[i] = pxa3xx_mfp_read(lcd_detect_pins[i]); + pxa3xx_mfp_write(lcd_detect_pins[i], 0x8440); + } + + for (i = 0; i < NUM_LCD_DETECT_PINS; i++) { + id = id << 1; + gpio = mfp_to_gpio(lcd_detect_pins[i]); + gpio_direction_input(gpio); + + if (gpio_get_value(gpio)) + id = id | 0x1; + } + + /* lcd id, flush out bit 1 */ + lcd_id = id & 0x3d; + + /* lcd orientation, portrait or landscape */ + lcd_orientation = (id >> 6) & 0x1; + + /* restore the original MFP settings */ + for (i = 0; i < NUM_LCD_DETECT_PINS; i++) + pxa3xx_mfp_write(lcd_detect_pins[i], mfpr_save[i]); +} + +void __init zylonite_pxa300_init(void) +{ + if (cpu_is_pxa300() || cpu_is_pxa310()) { + /* initialize MFP */ + pxa3xx_mfp_config(ARRAY_AND_SIZE(common_mfp_cfg)); + + /* detect LCD panel */ + zylonite_detect_lcd_panel(); + + /* GPIO pin assignment */ + gpio_backlight = mfp_to_gpio(MFP_PIN_GPIO20); + } + + if (cpu_is_pxa300()) { + pxa3xx_mfp_config(ARRAY_AND_SIZE(pxa300_mfp_cfg)); + gpio_eth_irq = mfp_to_gpio(MFP_PIN_GPIO99); + } + + if (cpu_is_pxa310()) { + pxa3xx_mfp_config(ARRAY_AND_SIZE(pxa310_mfp_cfg)); + gpio_eth_irq = mfp_to_gpio(MFP_PIN_GPIO102); + } +} diff --git a/arch/arm/mach-pxa/zylonite_pxa320.c b/arch/arm/mach-pxa/zylonite_pxa320.c new file mode 100644 index 0000000..63cb36b --- /dev/null +++ b/arch/arm/mach-pxa/zylonite_pxa320.c @@ -0,0 +1,173 @@ +/* + * linux/arch/arm/mach-pxa/zylonite_pxa320.c + * + * PXA320 specific support code for the + * PXA3xx Development Platform (aka Zylonite) + * + * Copyright (C) 2007 Marvell Internation Ltd. + * 2007-08-21: eric miao + * initial version + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include + +#include +#include +#include + +#define ARRAY_AND_SIZE(x) (x), ARRAY_SIZE(x) + +static mfp_cfg_t mfp_cfg[] __initdata = { + /* LCD */ + GPIO6_2_LCD_LDD_0, + GPIO7_2_LCD_LDD_1, + GPIO8_2_LCD_LDD_2, + GPIO9_2_LCD_LDD_3, + GPIO10_2_LCD_LDD_4, + GPIO11_2_LCD_LDD_5, + GPIO12_2_LCD_LDD_6, + GPIO13_2_LCD_LDD_7, + GPIO63_LCD_LDD_8, + GPIO64_LCD_LDD_9, + GPIO65_LCD_LDD_10, + GPIO66_LCD_LDD_11, + GPIO67_LCD_LDD_12, + GPIO68_LCD_LDD_13, + GPIO69_LCD_LDD_14, + GPIO70_LCD_LDD_15, + GPIO71_LCD_LDD_16, + GPIO72_LCD_LDD_17, + GPIO73_LCD_CS_N, + GPIO74_LCD_VSYNC, + GPIO14_2_LCD_FCLK, + GPIO15_2_LCD_LCLK, + GPIO16_2_LCD_PCLK, + GPIO17_2_LCD_BIAS, + + /* FFUART */ + GPIO41_UART1_RXD, + GPIO42_UART1_TXD, + GPIO43_UART1_CTS, + GPIO44_UART1_DCD, + GPIO45_UART1_DSR, + GPIO46_UART1_RI, + GPIO47_UART1_DTR, + GPIO48_UART1_RTS, + + /* AC97 */ + GPIO34_AC97_SYSCLK, + GPIO35_AC97_SDATA_IN_0, + GPIO37_AC97_SDATA_OUT, + GPIO38_AC97_SYNC, + GPIO39_AC97_BITCLK, + GPIO40_AC97_nACRESET, + + /* I2C */ + GPIO32_I2C_SCL, + GPIO33_I2C_SDA, + + /* Keypad */ + GPIO105_KP_DKIN_0, + GPIO106_KP_DKIN_1, + GPIO113_KP_MKIN_0, + GPIO114_KP_MKIN_1, + GPIO115_KP_MKIN_2, + GPIO116_KP_MKIN_3, + GPIO117_KP_MKIN_4, + GPIO118_KP_MKIN_5, + GPIO119_KP_MKIN_6, + GPIO120_KP_MKIN_7, + GPIO121_KP_MKOUT_0, + GPIO122_KP_MKOUT_1, + GPIO123_KP_MKOUT_2, + GPIO124_KP_MKOUT_3, + GPIO125_KP_MKOUT_4, + GPIO126_KP_MKOUT_5, + GPIO127_KP_MKOUT_6, + GPIO5_2_KP_MKOUT_7, + + /* Ethernet */ + GPIO4_nCS3, + GPIO90_GPIO, +}; + +#define NUM_LCD_DETECT_PINS 7 + +static int lcd_detect_pins[] __initdata = { + MFP_PIN_GPIO72, /* LCD_LDD_17 - ORIENT */ + MFP_PIN_GPIO71, /* LCD_LDD_16 - LCDID[5] */ + MFP_PIN_GPIO17_2, /* LCD_BIAS - LCDID[4] */ + MFP_PIN_GPIO15_2, /* LCD_LCLK - LCDID[3] */ + MFP_PIN_GPIO14_2, /* LCD_FCLK - LCDID[2] */ + MFP_PIN_GPIO73, /* LCD_CS_N - LCDID[1] */ + MFP_PIN_GPIO74, /* LCD_VSYNC - LCDID[0] */ + /* + * set the MFP_PIN_GPIO 14/15/17 to alternate function other than + * GPIO to avoid input level confliction with 14_2, 15_2, 17_2 + */ + MFP_PIN_GPIO14, + MFP_PIN_GPIO15, + MFP_PIN_GPIO17, +}; + +static int lcd_detect_mfpr[] __initdata = { + /* AF0, DS 1X, Pull Neither, Edge Clear */ + 0x8440, 0x8440, 0x8440, 0x8440, 0x8440, 0x8440, 0x8440, + 0xc442, /* Backlight, Pull-Up, AF2 */ + 0x8445, /* AF5 */ + 0x8445, /* AF5 */ +}; + +static void __init zylonite_detect_lcd_panel(void) +{ + unsigned long mfpr_save[ARRAY_SIZE(lcd_detect_pins)]; + int i, gpio, id = 0; + + /* save the original MFP settings of these pins and configure them + * as GPIO Input, DS01X, Pull Neither, Edge Clear + */ + for (i = 0; i < ARRAY_SIZE(lcd_detect_pins); i++) { + mfpr_save[i] = pxa3xx_mfp_read(lcd_detect_pins[i]); + pxa3xx_mfp_write(lcd_detect_pins[i], lcd_detect_mfpr[i]); + } + + for (i = 0; i < NUM_LCD_DETECT_PINS; i++) { + id = id << 1; + gpio = mfp_to_gpio(lcd_detect_pins[i]); + gpio_direction_input(gpio); + + if (gpio_get_value(gpio)) + id = id | 0x1; + } + + /* lcd id, flush out bit 1 */ + lcd_id = id & 0x3d; + + /* lcd orientation, portrait or landscape */ + lcd_orientation = (id >> 6) & 0x1; + + /* restore the original MFP settings */ + for (i = 0; i < ARRAY_SIZE(lcd_detect_pins); i++) + pxa3xx_mfp_write(lcd_detect_pins[i], mfpr_save[i]); +} + +void __init zylonite_pxa320_init(void) +{ + if (cpu_is_pxa320()) { + /* initialize MFP */ + pxa3xx_mfp_config(ARRAY_AND_SIZE(mfp_cfg)); + + /* detect LCD panel */ + zylonite_detect_lcd_panel(); + + /* GPIO pin assignment */ + gpio_backlight = mfp_to_gpio(MFP_PIN_GPIO14); + gpio_eth_irq = mfp_to_gpio(MFP_PIN_GPIO9); + } +} diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig index 4ca843e..7868f4d 100644 --- a/arch/arm/mm/Kconfig +++ b/arch/arm/mm/Kconfig @@ -333,7 +333,7 @@ config CPU_XSCALE # XScale Core Version 3 config CPU_XSC3 bool - depends on ARCH_IXP23XX || ARCH_IOP13XX + depends on ARCH_IXP23XX || ARCH_IOP13XX || PXA3xx default y select CPU_32v5 select CPU_ABRT_EV5T diff --git a/include/asm-arm/arch-pxa/mfp-pxa300.h b/include/asm-arm/arch-pxa/mfp-pxa300.h new file mode 100644 index 0000000..7513c7a --- /dev/null +++ b/include/asm-arm/arch-pxa/mfp-pxa300.h @@ -0,0 +1,574 @@ +/* + * linux/include/asm-arm/arch-pxa/mfp-pxa300.h + * + * PXA300/PXA310 specific MFP configuration definitions + * + * Copyright (C) 2007 Marvell International Ltd. + * 2007-08-21: eric miao + * initial version + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_ARCH_MFP_PXA300_H +#define __ASM_ARCH_MFP_PXA300_H + +#include + +/* GPIO */ +#define GPIO46_GPIO MFP_CFG(GPIO46, AF1) +#define GPIO49_GPIO MFP_CFG(GPIO49, AF3) +#define GPIO50_GPIO MFP_CFG(GPIO50, AF2) +#define GPIO51_GPIO MFP_CFG(GPIO51, AF3) +#define GPIO52_GPIO MFP_CFG(GPIO52, AF3) +#define GPIO56_GPIO MFP_CFG(GPIO56, AF0) +#define GPIO58_GPIO MFP_CFG(GPIO58, AF0) +#define GPIO59_GPIO MFP_CFG(GPIO59, AF0) +#define GPIO60_GPIO MFP_CFG(GPIO60, AF0) +#define GPIO61_GPIO MFP_CFG(GPIO61, AF0) +#define GPIO62_GPIO MFP_CFG(GPIO62, AF0) + +#ifdef CONFIG_CPU_PXA310 +#define GPIO7_2_GPIO MFP_CFG(GPIO7_2, AF0) +#define GPIO8_2_GPIO MFP_CFG(GPIO8_2, AF0) +#define GPIO9_2_GPIO MFP_CFG(GPIO9_2, AF0) +#define GPIO10_2_GPIO MFP_CFG(GPIO10_2, AF0) +#define GPIO11_2_GPIO MFP_CFG(GPIO11_2, AF0) +#define GPIO12_2_GPIO MFP_CFG(GPIO12_2, AF0) +#endif + +/* Chip Select */ +#define GPIO2_nCS3 MFP_CFG(GPIO2, AF1) + +/* AC97 */ +#define GPIO23_AC97_nACRESET MFP_CFG(GPIO23, AF1) +#define GPIO24_AC97_SYSCLK MFP_CFG(GPIO24, AF1) +#define GPIO29_AC97_BITCLK MFP_CFG(GPIO29, AF1) +#define GPIO25_AC97_SDATA_IN_0 MFP_CFG(GPIO25, AF1) +#define GPIO26_AC97_SDATA_IN_1 MFP_CFG(GPIO26, AF1) +#define GPIO17_AC97_SDATA_IN_2 MFP_CFG(GPIO17, AF3) +#define GPIO21_AC97_SDATA_IN_2 MFP_CFG(GPIO21, AF2) +#define GPIO18_AC97_SDATA_IN_3 MFP_CFG(GPIO18, AF3) +#define GPIO22_AC97_SDATA_IN_3 MFP_CFG(GPIO22, AF2) +#define GPIO27_AC97_SDATA_OUT MFP_CFG(GPIO27, AF1) +#define GPIO28_AC97_SYNC MFP_CFG(GPIO28, AF1) + +/* I2C */ +#define GPIO21_I2C_SCL MFP_CFG_LPM(GPIO21, AF1, PULL_HIGH) +#define GPIO22_I2C_SDA MFP_CFG_LPM(GPIO22, AF1, PULL_HIGH) + +/* QCI */ +#define GPIO39_CI_DD_0 MFP_CFG_DRV(GPIO39, AF1, DS04X) +#define GPIO40_CI_DD_1 MFP_CFG_DRV(GPIO40, AF1, DS04X) +#define GPIO41_CI_DD_2 MFP_CFG_DRV(GPIO41, AF1, DS04X) +#define GPIO42_CI_DD_3 MFP_CFG_DRV(GPIO42, AF1, DS04X) +#define GPIO43_CI_DD_4 MFP_CFG_DRV(GPIO43, AF1, DS04X) +#define GPIO44_CI_DD_5 MFP_CFG_DRV(GPIO44, AF1, DS04X) +#define GPIO45_CI_DD_6 MFP_CFG_DRV(GPIO45, AF1, DS04X) +#define GPIO46_CI_DD_7 MFP_CFG_DRV(GPIO46, AF0, DS04X) +#define GPIO47_CI_DD_8 MFP_CFG_DRV(GPIO47, AF1, DS04X) +#define GPIO48_CI_DD_9 MFP_CFG_DRV(GPIO48, AF1, DS04X) +#define GPIO52_CI_HSYNC MFP_CFG_DRV(GPIO52, AF0, DS04X) +#define GPIO51_CI_VSYNC MFP_CFG_DRV(GPIO51, AF0, DS04X) +#define GPIO49_CI_MCLK MFP_CFG_DRV(GPIO49, AF0, DS04X) +#define GPIO50_CI_PCLK MFP_CFG_DRV(GPIO50, AF0, DS04X) + +/* KEYPAD */ +#define GPIO3_KP_DKIN_6 MFP_CFG_LPM(GPIO3, AF2, FLOAT) +#define GPIO4_KP_DKIN_7 MFP_CFG_LPM(GPIO4, AF2, FLOAT) +#define GPIO16_KP_DKIN_6 MFP_CFG_LPM(GPIO16, AF6, FLOAT) +#define GPIO83_KP_DKIN_2 MFP_CFG_LPM(GPIO83, AF5, FLOAT) +#define GPIO84_KP_DKIN_1 MFP_CFG_LPM(GPIO84, AF5, FLOAT) +#define GPIO85_KP_DKIN_0 MFP_CFG_LPM(GPIO85, AF3, FLOAT) +#define GPIO86_KP_DKIN_1 MFP_CFG_LPM(GPIO86, AF3, FLOAT) +#define GPIO87_KP_DKIN_2 MFP_CFG_LPM(GPIO87, AF3, FLOAT) +#define GPIO88_KP_DKIN_3 MFP_CFG_LPM(GPIO88, AF3, FLOAT) +#define GPIO89_KP_DKIN_3 MFP_CFG_LPM(GPIO89, AF3, FLOAT) +#define GPIO107_KP_DKIN_0 MFP_CFG_LPM(GPIO107, AF2, FLOAT) +#define GPIO108_KP_DKIN_1 MFP_CFG_LPM(GPIO108, AF2, FLOAT) +#define GPIO109_KP_DKIN_2 MFP_CFG_LPM(GPIO109, AF2, FLOAT) +#define GPIO110_KP_DKIN_3 MFP_CFG_LPM(GPIO110, AF2, FLOAT) +#define GPIO111_KP_DKIN_4 MFP_CFG_LPM(GPIO111, AF2, FLOAT) +#define GPIO112_KP_DKIN_5 MFP_CFG_LPM(GPIO112, AF2, FLOAT) +#define GPIO113_KP_DKIN_6 MFP_CFG_LPM(GPIO113, AF2, FLOAT) +#define GPIO114_KP_DKIN_7 MFP_CFG_LPM(GPIO114, AF2, FLOAT) +#define GPIO115_KP_DKIN_0 MFP_CFG_LPM(GPIO115, AF2, FLOAT) +#define GPIO116_KP_DKIN_1 MFP_CFG_LPM(GPIO116, AF2, FLOAT) +#define GPIO117_KP_DKIN_2 MFP_CFG_LPM(GPIO117, AF2, FLOAT) +#define GPIO118_KP_DKIN_3 MFP_CFG_LPM(GPIO118, AF2, FLOAT) +#define GPIO119_KP_DKIN_4 MFP_CFG_LPM(GPIO119, AF2, FLOAT) +#define GPIO120_KP_DKIN_5 MFP_CFG_LPM(GPIO120, AF2, FLOAT) +#define GPIO121_KP_DKIN_6 MFP_CFG_LPM(GPIO121, AF2, FLOAT) +#define GPIO122_KP_DKIN_5 MFP_CFG_LPM(GPIO122, AF2, FLOAT) +#define GPIO123_KP_DKIN_4 MFP_CFG_LPM(GPIO123, AF2, FLOAT) +#define GPIO124_KP_DKIN_3 MFP_CFG_LPM(GPIO124, AF2, FLOAT) +#define GPIO127_KP_DKIN_0 MFP_CFG_LPM(GPIO127, AF5, FLOAT) +#define GPIO0_2_KP_DKIN_0 MFP_CFG_LPM(GPIO0_2, AF2, FLOAT) +#define GPIO1_2_KP_DKIN_1 MFP_CFG_LPM(GPIO1_2, AF2, FLOAT) +#define GPIO2_2_KP_DKIN_6 MFP_CFG_LPM(GPIO2_2, AF2, FLOAT) +#define GPIO3_2_KP_DKIN_7 MFP_CFG_LPM(GPIO3_2, AF2, FLOAT) +#define GPIO4_2_KP_DKIN_1 MFP_CFG_LPM(GPIO4_2, AF2, FLOAT) +#define GPIO5_2_KP_DKIN_0 MFP_CFG_LPM(GPIO5_2, AF2, FLOAT) + +#define GPIO5_KP_MKIN_0 MFP_CFG_LPM(GPIO5, AF2, FLOAT) +#define GPIO6_KP_MKIN_1 MFP_CFG_LPM(GPIO6, AF2, FLOAT) +#define GPIO9_KP_MKIN_6 MFP_CFG_LPM(GPIO9, AF3, FLOAT) +#define GPIO10_KP_MKIN_7 MFP_CFG_LPM(GPIO10, AF3, FLOAT) +#define GPIO70_KP_MKIN_6 MFP_CFG_LPM(GPIO70, AF3, FLOAT) +#define GPIO71_KP_MKIN_7 MFP_CFG_LPM(GPIO71, AF3, FLOAT) +#define GPIO100_KP_MKIN_6 MFP_CFG_LPM(GPIO100, AF7, FLOAT) +#define GPIO101_KP_MKIN_7 MFP_CFG_LPM(GPIO101, AF7, FLOAT) +#define GPIO112_KP_MKIN_6 MFP_CFG_LPM(GPIO112, AF4, FLOAT) +#define GPIO113_KP_MKIN_7 MFP_CFG_LPM(GPIO113, AF4, FLOAT) +#define GPIO115_KP_MKIN_0 MFP_CFG_LPM(GPIO115, AF1, FLOAT) +#define GPIO116_KP_MKIN_1 MFP_CFG_LPM(GPIO116, AF1, FLOAT) +#define GPIO117_KP_MKIN_2 MFP_CFG_LPM(GPIO117, AF1, FLOAT) +#define GPIO118_KP_MKIN_3 MFP_CFG_LPM(GPIO118, AF1, FLOAT) +#define GPIO119_KP_MKIN_4 MFP_CFG_LPM(GPIO119, AF1, FLOAT) +#define GPIO120_KP_MKIN_5 MFP_CFG_LPM(GPIO120, AF1, FLOAT) +#define GPIO125_KP_MKIN_2 MFP_CFG_LPM(GPIO125, AF2, FLOAT) +#define GPIO2_2_KP_MKIN_6 MFP_CFG_LPM(GPIO2_2, AF1, FLOAT) +#define GPIO3_2_KP_MKIN_7 MFP_CFG_LPM(GPIO3_2, AF1, FLOAT) + +#define GPIO7_KP_MKOUT_5 MFP_CFG_LPM(GPIO7, AF1, DRIVE_HIGH) +#define GPIO11_KP_MKOUT_5 MFP_CFG_LPM(GPIO11, AF3, DRIVE_HIGH) +#define GPIO12_KP_MKOUT_6 MFP_CFG_LPM(GPIO12, AF3, DRIVE_HIGH) +#define GPIO13_KP_MKOUT_7 MFP_CFG_LPM(GPIO13, AF3, DRIVE_HIGH) +#define GPIO19_KP_MKOUT_4 MFP_CFG_LPM(GPIO19, AF3, DRIVE_HIGH) +#define GPIO20_KP_MKOUT_5 MFP_CFG_LPM(GPIO20, AF3, DRIVE_HIGH) +#define GPIO38_KP_MKOUT_5 MFP_CFG_LPM(GPIO38, AF5, DRIVE_HIGH) +#define GPIO53_KP_MKOUT_6 MFP_CFG_LPM(GPIO53, AF5, DRIVE_HIGH) +#define GPIO78_KP_MKOUT_7 MFP_CFG_LPM(GPIO78, AF5, DRIVE_HIGH) +#define GPIO85_KP_MKOUT_0 MFP_CFG_LPM(GPIO85, AF2, DRIVE_HIGH) +#define GPIO86_KP_MKOUT_1 MFP_CFG_LPM(GPIO86, AF2, DRIVE_HIGH) +#define GPIO87_KP_MKOUT_2 MFP_CFG_LPM(GPIO87, AF2, DRIVE_HIGH) +#define GPIO88_KP_MKOUT_3 MFP_CFG_LPM(GPIO88, AF2, DRIVE_HIGH) +#define GPIO104_KP_MKOUT_6 MFP_CFG_LPM(GPIO104, AF5, DRIVE_HIGH) +#define GPIO105_KP_MKOUT_7 MFP_CFG_LPM(GPIO105, AF5, DRIVE_HIGH) +#define GPIO121_KP_MKOUT_0 MFP_CFG_LPM(GPIO121, AF1, DRIVE_HIGH) +#define GPIO122_KP_MKOUT_1 MFP_CFG_LPM(GPIO122, AF1, DRIVE_HIGH) +#define GPIO123_KP_MKOUT_2 MFP_CFG_LPM(GPIO123, AF1, DRIVE_HIGH) +#define GPIO124_KP_MKOUT_3 MFP_CFG_LPM(GPIO124, AF1, DRIVE_HIGH) +#define GPIO125_KP_MKOUT_4 MFP_CFG_LPM(GPIO125, AF1, DRIVE_HIGH) +#define GPIO126_KP_MKOUT_7 MFP_CFG_LPM(GPIO126, AF4, DRIVE_HIGH) +#define GPIO5_2_KP_MKOUT_6 MFP_CFG_LPM(GPIO5_2, AF1, DRIVE_HIGH) +#define GPIO4_2_KP_MKOUT_5 MFP_CFG_LPM(GPIO4_2, AF1, DRIVE_HIGH) +#define GPIO6_2_KP_MKOUT_7 MFP_CFG_LPM(GPIO6_2, AF1, DRIVE_HIGH) + +/* LCD */ +#define GPIO54_LCD_LDD_0 MFP_CFG_DRV(GPIO54, AF1, DS01X) +#define GPIO55_LCD_LDD_1 MFP_CFG_DRV(GPIO55, AF1, DS01X) +#define GPIO56_LCD_LDD_2 MFP_CFG_DRV(GPIO56, AF1, DS01X) +#define GPIO57_LCD_LDD_3 MFP_CFG_DRV(GPIO57, AF1, DS01X) +#define GPIO58_LCD_LDD_4 MFP_CFG_DRV(GPIO58, AF1, DS01X) +#define GPIO59_LCD_LDD_5 MFP_CFG_DRV(GPIO59, AF1, DS01X) +#define GPIO60_LCD_LDD_6 MFP_CFG_DRV(GPIO60, AF1, DS01X) +#define GPIO61_LCD_LDD_7 MFP_CFG_DRV(GPIO61, AF1, DS01X) +#define GPIO62_LCD_LDD_8 MFP_CFG_DRV(GPIO62, AF1, DS01X) +#define GPIO63_LCD_LDD_9 MFP_CFG_DRV(GPIO63, AF1, DS01X) +#define GPIO64_LCD_LDD_10 MFP_CFG_DRV(GPIO64, AF1, DS01X) +#define GPIO65_LCD_LDD_11 MFP_CFG_DRV(GPIO65, AF1, DS01X) +#define GPIO66_LCD_LDD_12 MFP_CFG_DRV(GPIO66, AF1, DS01X) +#define GPIO67_LCD_LDD_13 MFP_CFG_DRV(GPIO67, AF1, DS01X) +#define GPIO68_LCD_LDD_14 MFP_CFG_DRV(GPIO68, AF1, DS01X) +#define GPIO69_LCD_LDD_15 MFP_CFG_DRV(GPIO69, AF1, DS01X) +#define GPIO70_LCD_LDD_16 MFP_CFG_DRV(GPIO70, AF1, DS01X) +#define GPIO71_LCD_LDD_17 MFP_CFG_DRV(GPIO71, AF1, DS01X) +#define GPIO62_LCD_CS_N MFP_CFG_DRV(GPIO62, AF2, DS01X) +#define GPIO72_LCD_FCLK MFP_CFG_DRV(GPIO72, AF1, DS01X) +#define GPIO73_LCD_LCLK MFP_CFG_DRV(GPIO73, AF1, DS01X) +#define GPIO74_LCD_PCLK MFP_CFG_DRV(GPIO74, AF1, DS01X) +#define GPIO75_LCD_BIAS MFP_CFG_DRV(GPIO75, AF1, DS01X) +#define GPIO76_LCD_VSYNC MFP_CFG_DRV(GPIO76, AF2, DS01X) + +#define GPIO15_LCD_CS_N MFP_CFG_DRV(GPIO15, AF2, DS01X) +#define GPIO127_LCD_CS_N MFP_CFG_DRV(GPIO127, AF1, DS01X) +#define GPIO63_LCD_VSYNC MFP_CFG_DRV(GPIO63, AF2, DS01X) + +/* Mini-LCD */ +#define GPIO72_MLCD_FCLK MFP_CFG_DRV(GPIO72, AF7, DS08X) +#define GPIO73_MLCD_LCLK MFP_CFG_DRV(GPIO73, AF7, DS08X) +#define GPIO54_MLCD_LDD_0 MFP_CFG_DRV(GPIO54, AF7, DS08X) +#define GPIO55_MLCD_LDD_1 MFP_CFG_DRV(GPIO55, AF7, DS08X) +#define GPIO56_MLCD_LDD_2 MFP_CFG_DRV(GPIO56, AF7, DS08X) +#define GPIO57_MLCD_LDD_3 MFP_CFG_DRV(GPIO57, AF7, DS08X) +#define GPIO58_MLCD_LDD_4 MFP_CFG_DRV(GPIO58, AF7, DS08X) +#define GPIO59_MLCD_LDD_5 MFP_CFG_DRV(GPIO59, AF7, DS08X) +#define GPIO60_MLCD_LDD_6 MFP_CFG_DRV(GPIO60, AF7, DS08X) +#define GPIO61_MLCD_LDD_7 MFP_CFG_DRV(GPIO61, AF7, DS08X) +#define GPIO62_MLCD_LDD_8 MFP_CFG_DRV(GPIO62, AF7, DS08X) +#define GPIO63_MLCD_LDD_9 MFP_CFG_DRV(GPIO63, AF7, DS08X) +#define GPIO64_MLCD_LDD_10 MFP_CFG_DRV(GPIO64, AF7, DS08X) +#define GPIO65_MLCD_LDD_11 MFP_CFG_DRV(GPIO65, AF7, DS08X) +#define GPIO66_MLCD_LDD_12 MFP_CFG_DRV(GPIO66, AF7, DS08X) +#define GPIO67_MLCD_LDD_13 MFP_CFG_DRV(GPIO67, AF7, DS08X) +#define GPIO68_MLCD_LDD_14 MFP_CFG_DRV(GPIO68, AF7, DS08X) +#define GPIO69_MLCD_LDD_15 MFP_CFG_DRV(GPIO69, AF7, DS08X) +#define GPIO74_MLCD_PCLK MFP_CFG_DRV(GPIO74, AF7, DS08X) +#define GPIO75_MLCD_BIAS MFP_CFG_DRV(GPIO75, AF2, DS08X) + +/* MMC1 */ +#define GPIO7_MMC1_CLK MFP_CFG_LPM(GPIO7, AF4, DRIVE_HIGH) +#define GPIO8_MMC1_CMD MFP_CFG_LPM(GPIO8, AF4, DRIVE_HIGH) +#define GPIO14_MMC1_CMD MFP_CFG_LPM(GPIO14, AF5, DRIVE_HIGH) +#define GPIO15_MMC1_CMD MFP_CFG_LPM(GPIO15, AF5, DRIVE_HIGH) +#define GPIO3_MMC1_DAT0 MFP_CFG_LPM(GPIO3, AF4, DRIVE_HIGH) +#define GPIO4_MMC1_DAT1 MFP_CFG_LPM(GPIO4, AF4, DRIVE_HIGH) +#define GPIO5_MMC1_DAT2 MFP_CFG_LPM(GPIO5, AF4, DRIVE_HIGH) +#define GPIO6_MMC1_DAT3 MFP_CFG_LPM(GPIO6, AF4, DRIVE_HIGH) + +/* MMC2 */ +#define GPIO9_MMC2_DAT0 MFP_CFG_LPM(GPIO9, AF4, PULL_HIGH) +#define GPIO10_MMC2_DAT1 MFP_CFG_LPM(GPIO10, AF4, PULL_HIGH) +#define GPIO11_MMC2_DAT2 MFP_CFG_LPM(GPIO11, AF4, PULL_HIGH) +#define GPIO12_MMC2_DAT3 MFP_CFG_LPM(GPIO12, AF4, PULL_HIGH) +#define GPIO13_MMC2_CLK MFP_CFG_LPM(GPIO13, AF4, PULL_HIGH) +#define GPIO14_MMC2_CMD MFP_CFG_LPM(GPIO14, AF4, PULL_HIGH) +#define GPIO77_MMC2_DAT0 MFP_CFG_LPM(GPIO77, AF4, PULL_HIGH) +#define GPIO78_MMC2_DAT1 MFP_CFG_LPM(GPIO78, AF4, PULL_HIGH) +#define GPIO79_MMC2_DAT2 MFP_CFG_LPM(GPIO79, AF4, PULL_HIGH) +#define GPIO80_MMC2_DAT3 MFP_CFG_LPM(GPIO80, AF4, PULL_HIGH) +#define GPIO81_MMC2_CLK MFP_CFG_LPM(GPIO81, AF4, PULL_HIGH) +#define GPIO82_MMC2_CMD MFP_CFG_LPM(GPIO82, AF4, PULL_HIGH) + +/* SSP1 */ +#define GPIO89_SSP1_EXTCLK MFP_CFG(GPIO89, AF1) +#define GPIO90_SSP1_SYSCLK MFP_CFG(GPIO90, AF1) +#define GPIO15_SSP1_SCLK MFP_CFG(GPIO15, AF6) +#define GPIO16_SSP1_FRM MFP_CFG(GPIO16, AF2) +#define GPIO33_SSP1_SCLK MFP_CFG(GPIO33, AF5) +#define GPIO34_SSP1_FRM MFP_CFG(GPIO34, AF5) +#define GPIO85_SSP1_SCLK MFP_CFG(GPIO85, AF1) +#define GPIO86_SSP1_FRM MFP_CFG(GPIO86, AF1) +#define GPIO18_SSP1_TXD MFP_CFG(GPIO18, AF7) +#define GPIO18_SSP1_RXD MFP_CFG(GPIO18, AF2) +#define GPIO20_SSP1_TXD MFP_CFG(GPIO20, AF2) +#define GPIO20_SSP1_RXD MFP_CFG(GPIO20, AF7) +#define GPIO35_SSP1_TXD MFP_CFG(GPIO35, AF5) +#define GPIO35_SSP1_RXD MFP_CFG(GPIO35, AF4) +#define GPIO36_SSP1_TXD MFP_CFG(GPIO36, AF5) +#define GPIO36_SSP1_RXD MFP_CFG(GPIO36, AF6) +#define GPIO87_SSP1_TXD MFP_CFG(GPIO87, AF1) +#define GPIO87_SSP1_RXD MFP_CFG(GPIO87, AF6) +#define GPIO88_SSP1_TXD MFP_CFG(GPIO88, AF6) +#define GPIO88_SSP1_RXD MFP_CFG(GPIO88, AF1) + +/* SSP2 */ +#define GPIO29_SSP2_EXTCLK MFP_CFG(GPIO29, AF2) +#define GPIO23_SSP2_SCLK MFP_CFG(GPIO23, AF2) +#define GPIO17_SSP2_FRM MFP_CFG(GPIO17, AF2) +#define GPIO25_SSP2_SCLK MFP_CFG(GPIO25, AF2) +#define GPIO26_SSP2_FRM MFP_CFG(GPIO26, AF2) +#define GPIO33_SSP2_SCLK MFP_CFG(GPIO33, AF6) +#define GPIO34_SSP2_FRM MFP_CFG(GPIO34, AF6) +#define GPIO64_SSP2_SCLK MFP_CFG(GPIO64, AF2) +#define GPIO65_SSP2_FRM MFP_CFG(GPIO65, AF2) +#define GPIO19_SSP2_TXD MFP_CFG(GPIO19, AF2) +#define GPIO19_SSP2_RXD MFP_CFG(GPIO19, AF7) +#define GPIO24_SSP2_TXD MFP_CFG(GPIO24, AF5) +#define GPIO24_SSP2_RXD MFP_CFG(GPIO24, AF4) +#define GPIO27_SSP2_TXD MFP_CFG(GPIO27, AF2) +#define GPIO27_SSP2_RXD MFP_CFG(GPIO27, AF5) +#define GPIO28_SSP2_TXD MFP_CFG(GPIO28, AF5) +#define GPIO28_SSP2_RXD MFP_CFG(GPIO28, AF2) +#define GPIO35_SSP2_TXD MFP_CFG(GPIO35, AF7) +#define GPIO35_SSP2_RXD MFP_CFG(GPIO35, AF6) +#define GPIO66_SSP2_TXD MFP_CFG(GPIO66, AF4) +#define GPIO66_SSP2_RXD MFP_CFG(GPIO66, AF2) +#define GPIO67_SSP2_TXD MFP_CFG(GPIO67, AF2) +#define GPIO67_SSP2_RXD MFP_CFG(GPIO67, AF4) +#define GPIO36_SSP2_TXD MFP_CFG(GPIO36, AF7) + +/* SSP3 */ +#define GPIO69_SSP3_FRM MFP_CFG_X(GPIO69, AF2, DS08X, DRIVE_LOW) +#define GPIO68_SSP3_SCLK MFP_CFG_X(GPIO68, AF2, DS08X, FLOAT) +#define GPIO92_SSP3_FRM MFP_CFG_X(GPIO92, AF1, DS08X, DRIVE_LOW) +#define GPIO91_SSP3_SCLK MFP_CFG_X(GPIO91, AF1, DS08X, FLOAT) +#define GPIO70_SSP3_TXD MFP_CFG_X(GPIO70, AF2, DS08X, DRIVE_LOW) +#define GPIO70_SSP3_RXD MFP_CFG_X(GPIO70, AF5, DS08X, FLOAT) +#define GPIO71_SSP3_TXD MFP_CFG_X(GPIO71, AF5, DS08X, DRIVE_LOW) +#define GPIO71_SSP3_RXD MFP_CFG_X(GPIO71, AF2, DS08X, FLOAT) +#define GPIO93_SSP3_TXD MFP_CFG_X(GPIO93, AF1, DS08X, DRIVE_LOW) +#define GPIO93_SSP3_RXD MFP_CFG_X(GPIO93, AF5, DS08X, FLOAT) +#define GPIO94_SSP3_TXD MFP_CFG_X(GPIO94, AF5, DS08X, DRIVE_LOW) +#define GPIO94_SSP3_RXD MFP_CFG_X(GPIO94, AF1, DS08X, FLOAT) + +/* SSP4 */ +#define GPIO95_SSP4_SCLK MFP_CFG_LPM(GPIO95, AF1, PULL_HIGH) +#define GPIO96_SSP4_FRM MFP_CFG_LPM(GPIO96, AF1, PULL_HIGH) +#define GPIO97_SSP4_TXD MFP_CFG_LPM(GPIO97, AF1, PULL_HIGH) +#define GPIO97_SSP4_RXD MFP_CFG_LPM(GPIO97, AF5, PULL_HIGH) +#define GPIO98_SSP4_TXD MFP_CFG_LPM(GPIO98, AF5, PULL_HIGH) +#define GPIO98_SSP4_RXD MFP_CFG_LPM(GPIO98, AF1, PULL_HIGH) + +/* UART1 */ +#define GPIO32_UART1_CTS MFP_CFG_LPM(GPIO32, AF2, FLOAT) +#define GPIO37_UART1_CTS MFP_CFG_LPM(GPIO37, AF4, FLOAT) +#define GPIO79_UART1_CTS MFP_CFG_LPM(GPIO79, AF1, FLOAT) +#define GPIO84_UART1_CTS MFP_CFG_LPM(GPIO84, AF3, FLOAT) +#define GPIO101_UART1_CTS MFP_CFG_LPM(GPIO101, AF1, FLOAT) +#define GPIO106_UART1_CTS MFP_CFG_LPM(GPIO106, AF6, FLOAT) + +#define GPIO32_UART1_RTS MFP_CFG_LPM(GPIO32, AF4, FLOAT) +#define GPIO37_UART1_RTS MFP_CFG_LPM(GPIO37, AF2, FLOAT) +#define GPIO79_UART1_RTS MFP_CFG_LPM(GPIO79, AF3, FLOAT) +#define GPIO84_UART1_RTS MFP_CFG_LPM(GPIO84, AF1, FLOAT) +#define GPIO101_UART1_RTS MFP_CFG_LPM(GPIO101, AF6, FLOAT) +#define GPIO106_UART1_RTS MFP_CFG_LPM(GPIO106, AF1, FLOAT) + +#define GPIO34_UART1_DSR MFP_CFG_LPM(GPIO34, AF2, FLOAT) +#define GPIO36_UART1_DSR MFP_CFG_LPM(GPIO36, AF4, FLOAT) +#define GPIO81_UART1_DSR MFP_CFG_LPM(GPIO81, AF1, FLOAT) +#define GPIO83_UART1_DSR MFP_CFG_LPM(GPIO83, AF3, FLOAT) +#define GPIO103_UART1_DSR MFP_CFG_LPM(GPIO103, AF1, FLOAT) +#define GPIO105_UART1_DSR MFP_CFG_LPM(GPIO105, AF6, FLOAT) + +#define GPIO34_UART1_DTR MFP_CFG_LPM(GPIO34, AF4, FLOAT) +#define GPIO36_UART1_DTR MFP_CFG_LPM(GPIO36, AF2, FLOAT) +#define GPIO81_UART1_DTR MFP_CFG_LPM(GPIO81, AF3, FLOAT) +#define GPIO83_UART1_DTR MFP_CFG_LPM(GPIO83, AF1, FLOAT) +#define GPIO103_UART1_DTR MFP_CFG_LPM(GPIO103, AF6, FLOAT) +#define GPIO105_UART1_DTR MFP_CFG_LPM(GPIO105, AF1, FLOAT) + +#define GPIO35_UART1_RI MFP_CFG_LPM(GPIO35, AF2, FLOAT) +#define GPIO82_UART1_RI MFP_CFG_LPM(GPIO82, AF1, FLOAT) +#define GPIO104_UART1_RI MFP_CFG_LPM(GPIO104, AF1, FLOAT) + +#define GPIO33_UART1_DCD MFP_CFG_LPM(GPIO33, AF2, FLOAT) +#define GPIO80_UART1_DCD MFP_CFG_LPM(GPIO80, AF1, FLOAT) +#define GPIO102_UART1_DCD MFP_CFG_LPM(GPIO102, AF1, FLOAT) + +#define GPIO30_UART1_RXD MFP_CFG_LPM(GPIO30, AF2, FLOAT) +#define GPIO31_UART1_RXD MFP_CFG_LPM(GPIO31, AF4, FLOAT) +#define GPIO77_UART1_RXD MFP_CFG_LPM(GPIO77, AF1, FLOAT) +#define GPIO78_UART1_RXD MFP_CFG_LPM(GPIO78, AF3, FLOAT) +#define GPIO99_UART1_RXD MFP_CFG_LPM(GPIO99, AF1, FLOAT) +#define GPIO100_UART1_RXD MFP_CFG_LPM(GPIO100, AF6, FLOAT) +#define GPIO102_UART1_RXD MFP_CFG_LPM(GPIO102, AF6, FLOAT) +#define GPIO104_UART1_RXD MFP_CFG_LPM(GPIO104, AF4, FLOAT) + +#define GPIO30_UART1_TXD MFP_CFG_LPM(GPIO30, AF4, FLOAT) +#define GPIO31_UART1_TXD MFP_CFG_LPM(GPIO31, AF2, FLOAT) +#define GPIO77_UART1_TXD MFP_CFG_LPM(GPIO77, AF3, FLOAT) +#define GPIO78_UART1_TXD MFP_CFG_LPM(GPIO78, AF1, FLOAT) +#define GPIO99_UART1_TXD MFP_CFG_LPM(GPIO99, AF6, FLOAT) +#define GPIO100_UART1_TXD MFP_CFG_LPM(GPIO100, AF1, FLOAT) +#define GPIO102_UART1_TXD MFP_CFG_LPM(GPIO102, AF4, FLOAT) + +/* UART2 */ +#define GPIO15_UART2_CTS MFP_CFG_LPM(GPIO15, AF3, FLOAT) +#define GPIO16_UART2_CTS MFP_CFG_LPM(GPIO16, AF5, FLOAT) +#define GPIO111_UART2_CTS MFP_CFG_LPM(GPIO111, AF3, FLOAT) +#define GPIO114_UART2_CTS MFP_CFG_LPM(GPIO114, AF1, FLOAT) + +#define GPIO15_UART2_RTS MFP_CFG_LPM(GPIO15, AF4, FLOAT) +#define GPIO16_UART2_RTS MFP_CFG_LPM(GPIO16, AF4, FLOAT) +#define GPIO114_UART2_RTS MFP_CFG_LPM(GPIO114, AF3, FLOAT) +#define GPIO111_UART2_RTS MFP_CFG_LPM(GPIO111, AF1, FLOAT) + +#define GPIO18_UART2_RXD MFP_CFG_LPM(GPIO18, AF5, FLOAT) +#define GPIO19_UART2_RXD MFP_CFG_LPM(GPIO19, AF4, FLOAT) +#define GPIO112_UART2_RXD MFP_CFG_LPM(GPIO112, AF1, FLOAT) +#define GPIO113_UART2_RXD MFP_CFG_LPM(GPIO113, AF3, FLOAT) + +#define GPIO18_UART2_TXD MFP_CFG_LPM(GPIO18, AF4, FLOAT) +#define GPIO19_UART2_TXD MFP_CFG_LPM(GPIO19, AF5, FLOAT) +#define GPIO112_UART2_TXD MFP_CFG_LPM(GPIO112, AF3, FLOAT) +#define GPIO113_UART2_TXD MFP_CFG_LPM(GPIO113, AF1, FLOAT) + +/* UART3 */ +#define GPIO91_UART3_CTS MFP_CFG_LPM(GPIO91, AF2, FLOAT) +#define GPIO92_UART3_CTS MFP_CFG_LPM(GPIO92, AF4, FLOAT) +#define GPIO107_UART3_CTS MFP_CFG_LPM(GPIO107, AF1, FLOAT) +#define GPIO108_UART3_CTS MFP_CFG_LPM(GPIO108, AF3, FLOAT) + +#define GPIO91_UART3_RTS MFP_CFG_LPM(GPIO91, AF4, FLOAT) +#define GPIO92_UART3_RTS MFP_CFG_LPM(GPIO92, AF2, FLOAT) +#define GPIO107_UART3_RTS MFP_CFG_LPM(GPIO107, AF3, FLOAT) +#define GPIO108_UART3_RTS MFP_CFG_LPM(GPIO108, AF1, FLOAT) + +#define GPIO7_UART3_RXD MFP_CFG_LPM(GPIO7, AF2, FLOAT) +#define GPIO8_UART3_RXD MFP_CFG_LPM(GPIO8, AF6, FLOAT) +#define GPIO93_UART3_RXD MFP_CFG_LPM(GPIO93, AF4, FLOAT) +#define GPIO94_UART3_RXD MFP_CFG_LPM(GPIO94, AF2, FLOAT) +#define GPIO109_UART3_RXD MFP_CFG_LPM(GPIO109, AF3, FLOAT) +#define GPIO110_UART3_RXD MFP_CFG_LPM(GPIO110, AF1, FLOAT) + +#define GPIO7_UART3_TXD MFP_CFG_LPM(GPIO7, AF6, FLOAT) +#define GPIO8_UART3_TXD MFP_CFG_LPM(GPIO8, AF2, FLOAT) +#define GPIO93_UART3_TXD MFP_CFG_LPM(GPIO93, AF2, FLOAT) +#define GPIO94_UART3_TXD MFP_CFG_LPM(GPIO94, AF4, FLOAT) +#define GPIO109_UART3_TXD MFP_CFG_LPM(GPIO109, AF1, FLOAT) +#define GPIO110_UART3_TXD MFP_CFG_LPM(GPIO110, AF3, FLOAT) + +/* USB Host */ +#define GPIO0_2_USBH_PEN MFP_CFG(GPIO0_2, AF1) +#define GPIO1_2_USBH_PWR MFP_CFG(GPIO1_2, AF1) + +/* USB P3 */ +#define GPIO77_USB_P3_1 MFP_CFG(GPIO77, AF2) +#define GPIO78_USB_P3_2 MFP_CFG(GPIO78, AF2) +#define GPIO79_USB_P3_3 MFP_CFG(GPIO79, AF2) +#define GPIO80_USB_P3_4 MFP_CFG(GPIO80, AF2) +#define GPIO81_USB_P3_5 MFP_CFG(GPIO81, AF2) +#define GPIO82_USB_P3_6 MFP_CFG(GPIO82, AF2) + +/* PWM */ +#define GPIO17_PWM0_OUT MFP_CFG(GPIO17, AF1) +#define GPIO18_PWM1_OUT MFP_CFG(GPIO18, AF1) +#define GPIO19_PWM2_OUT MFP_CFG(GPIO19, AF1) +#define GPIO20_PWM3_OUT MFP_CFG(GPIO20, AF1) + +/* CIR */ +#define GPIO8_CIR_OUT MFP_CFG(GPIO8, AF5) +#define GPIO16_CIR_OUT MFP_CFG(GPIO16, AF3) + +#define GPIO20_OW_DQ_IN MFP_CFG(GPIO20, AF5) +#define GPIO126_OW_DQ MFP_CFG(GPIO126, AF2) + +#define GPIO0_DF_RDY MFP_CFG(GPIO0, AF1) +#define GPIO7_CLK_BYPASS_XSC MFP_CFG(GPIO7, AF7) +#define GPIO17_EXT_SYNC_MVT_0 MFP_CFG(GPIO17, AF6) +#define GPIO18_EXT_SYNC_MVT_1 MFP_CFG(GPIO18, AF6) +#define GPIO19_OST_CHOUT_MVT_0 MFP_CFG(GPIO19, AF6) +#define GPIO20_OST_CHOUT_MVT_1 MFP_CFG(GPIO20, AF6) +#define GPIO49_48M_CLK MFP_CFG(GPIO49, AF2) +#define GPIO126_EXT_CLK MFP_CFG(GPIO126, AF3) +#define GPIO127_CLK_BYPASS_GB MFP_CFG(GPIO127, AF7) +#define GPIO71_EXT_MATCH_MVT MFP_CFG(GPIO71, AF6) + +#define GPIO3_uIO_IN MFP_CFG(GPIO3, AF1) + +#define GPIO4_uSIM_CARD_STATE MFP_CFG(GPIO4, AF1) +#define GPIO5_uSIM_uCLK MFP_CFG(GPIO5, AF1) +#define GPIO6_uSIM_uRST MFP_CFG(GPIO6, AF1) +#define GPIO16_uSIM_UVS_0 MFP_CFG(GPIO16, AF1) + +#define GPIO9_SCIO MFP_CFG(GPIO9, AF1) +#define GPIO20_RTC_MVT MFP_CFG(GPIO20, AF4) +#define GPIO126_RTC_MVT MFP_CFG(GPIO126, AF1) + +/* + * PXA300 specific MFP configurations + */ +#ifdef CONFIG_CPU_PXA300 +#define GPIO99_USB_P2_2 MFP_CFG(GPIO99, AF2) +#define GPIO99_USB_P2_5 MFP_CFG(GPIO99, AF3) +#define GPIO99_USB_P2_6 MFP_CFG(GPIO99, AF4) +#define GPIO100_USB_P2_2 MFP_CFG(GPIO100, AF4) +#define GPIO100_USB_P2_5 MFP_CFG(GPIO100, AF5) +#define GPIO101_USB_P2_1 MFP_CFG(GPIO101, AF2) +#define GPIO102_USB_P2_4 MFP_CFG(GPIO102, AF2) +#define GPIO104_USB_P2_3 MFP_CFG(GPIO104, AF2) +#define GPIO105_USB_P2_5 MFP_CFG(GPIO105, AF2) +#define GPIO100_USB_P2_6 MFP_CFG(GPIO100, AF2) +#define GPIO106_USB_P2_7 MFP_CFG(GPIO106, AF2) +#define GPIO103_USB_P2_8 MFP_CFG(GPIO103, AF2) + +/* U2D UTMI */ +#define GPIO38_UTM_CLK MFP_CFG(GPIO38, AF1) +#define GPIO26_U2D_RXERROR MFP_CFG(GPIO26, AF3) +#define GPIO50_U2D_RXERROR MFP_CFG(GPIO50, AF1) +#define GPIO89_U2D_RXERROR MFP_CFG(GPIO89, AF5) +#define GPIO24_UTM_RXVALID MFP_CFG(GPIO24, AF3) +#define GPIO48_UTM_RXVALID MFP_CFG(GPIO48, AF2) +#define GPIO87_UTM_RXVALID MFP_CFG(GPIO87, AF5) +#define GPIO25_UTM_RXACTIVE MFP_CFG(GPIO25, AF3) +#define GPIO47_UTM_RXACTIVE MFP_CFG(GPIO47, AF2) +#define GPIO49_UTM_RXACTIVE MFP_CFG(GPIO49, AF1) +#define GPIO88_UTM_RXACTIVE MFP_CFG(GPIO88, AF5) +#define GPIO53_UTM_TXREADY MFP_CFG(GPIO53, AF1) +#define GPIO67_UTM_LINESTATE_0 MFP_CFG(GPIO67, AF3) +#define GPIO92_UTM_LINESTATE_0 MFP_CFG(GPIO92, AF3) +#define GPIO104_UTM_LINESTATE_0 MFP_CFG(GPIO104, AF3) +#define GPIO109_UTM_LINESTATE_0 MFP_CFG(GPIO109, AF4) +#define GPIO68_UTM_LINESTATE_1 MFP_CFG(GPIO68, AF3) +#define GPIO93_UTM_LINESTATE_1 MFP_CFG(GPIO93, AF3) +#define GPIO105_UTM_LINESTATE_1 MFP_CFG(GPIO105, AF3) +#define GPIO27_U2D_OPMODE_0 MFP_CFG(GPIO27, AF4) +#define GPIO51_U2D_OPMODE_0 MFP_CFG(GPIO51, AF2) +#define GPIO90_U2D_OPMODE_0 MFP_CFG(GPIO90, AF7) +#define GPIO28_U2D_OPMODE_1 MFP_CFG(GPIO28, AF4) +#define GPIO52_U2D_OPMODE_1 MFP_CFG(GPIO52, AF2) +#define GPIO106_U2D_OPMODE_1 MFP_CFG(GPIO106, AF3) +#define GPIO110_U2D_OPMODE_1 MFP_CFG(GPIO110, AF5) +#define GPIO76_U2D_RESET MFP_CFG(GPIO76, AF1) +#define GPIO95_U2D_RESET MFP_CFG(GPIO95, AF2) +#define GPIO100_U2D_RESET MFP_CFG(GPIO100, AF3) +#define GPIO66_U2D_SUSPEND MFP_CFG(GPIO66, AF3) +#define GPIO98_U2D_SUSPEND MFP_CFG(GPIO98, AF2) +#define GPIO103_U2D_SUSPEND MFP_CFG(GPIO103, AF3) +#define GPIO65_U2D_TERM_SEL MFP_CFG(GPIO65, AF5) +#define GPIO97_U2D_TERM_SEL MFP_CFG(GPIO97, AF3) +#define GPIO102_U2D_TERM_SEL MFP_CFG(GPIO102, AF5) +#define GPIO29_U2D_TXVALID MFP_CFG(GPIO29, AF3) +#define GPIO52_U2D_TXVALID MFP_CFG(GPIO52, AF4) +#define GPIO69_U2D_TXVALID MFP_CFG(GPIO69, AF3) +#define GPIO85_U2D_TXVALID MFP_CFG(GPIO85, AF7) +#define GPIO64_U2D_XCVR_SEL MFP_CFG(GPIO64, AF5) +#define GPIO96_U2D_XCVR_SEL MFP_CFG(GPIO96, AF3) +#define GPIO101_U2D_XCVR_SEL MFP_CFG(GPIO101, AF5) +#define GPIO30_UTM_PHYDATA_0 MFP_CFG(GPIO30, AF3) +#define GPIO31_UTM_PHYDATA_1 MFP_CFG(GPIO31, AF3) +#define GPIO32_UTM_PHYDATA_2 MFP_CFG(GPIO32, AF3) +#define GPIO33_UTM_PHYDATA_3 MFP_CFG(GPIO33, AF3) +#define GPIO34_UTM_PHYDATA_4 MFP_CFG(GPIO34, AF3) +#define GPIO35_UTM_PHYDATA_5 MFP_CFG(GPIO35, AF3) +#define GPIO36_UTM_PHYDATA_6 MFP_CFG(GPIO36, AF3) +#define GPIO37_UTM_PHYDATA_7 MFP_CFG(GPIO37, AF3) +#define GPIO39_UTM_PHYDATA_0 MFP_CFG(GPIO39, AF3) +#define GPIO40_UTM_PHYDATA_1 MFP_CFG(GPIO40, AF3) +#define GPIO41_UTM_PHYDATA_2 MFP_CFG(GPIO41, AF3) +#define GPIO42_UTM_PHYDATA_3 MFP_CFG(GPIO42, AF3) +#define GPIO43_UTM_PHYDATA_4 MFP_CFG(GPIO43, AF3) +#define GPIO44_UTM_PHYDATA_5 MFP_CFG(GPIO44, AF3) +#define GPIO45_UTM_PHYDATA_6 MFP_CFG(GPIO45, AF3) +#define GPIO46_UTM_PHYDATA_7 MFP_CFG(GPIO46, AF3) +#endif /* CONFIG_CPU_PXA300 */ + +/* + * PXA310 specific MFP configurations + */ +#ifdef CONFIG_CPU_PXA310 +/* USB P2 */ +#define GPIO36_USB_P2_1 MFP_CFG(GPIO36, AF1) +#define GPIO30_USB_P2_2 MFP_CFG(GPIO30, AF1) +#define GPIO35_USB_P2_3 MFP_CFG(GPIO35, AF1) +#define GPIO32_USB_P2_4 MFP_CFG(GPIO32, AF1) +#define GPIO34_USB_P2_5 MFP_CFG(GPIO34, AF1) +#define GPIO31_USB_P2_6 MFP_CFG(GPIO31, AF1) + +/* MMC1 */ +#define GPIO24_MMC1_CMD MFP_CFG(GPIO24, AF3) +#define GPIO29_MMC1_DAT0 MFP_CFG(GPIO29, AF3) + +/* MMC3 */ +#define GPIO103_MMC3_CLK MFP_CFG(GPIO103, AF2) +#define GPIO105_MMC3_CMD MFP_CFG(GPIO105, AF2) +#define GPIO11_2_MMC3_CLK MFP_CFG(GPIO11_2, AF1) +#define GPIO12_2_MMC3_CMD MFP_CFG(GPIO12_2, AF1) +#define GPIO7_2_MMC3_DAT0 MFP_CFG(GPIO7_2, AF1) +#define GPIO8_2_MMC3_DAT1 MFP_CFG(GPIO8_2, AF1) +#define GPIO9_2_MMC3_DAT2 MFP_CFG(GPIO9_2, AF1) +#define GPIO10_2_MMC3_DAT3 MFP_CFG(GPIO10_2, AF1) + +/* ULPI */ +#define GPIO38_ULPI_CLK MFP_CFG(GPIO38, AF1) +#define GPIO30_ULPI_DATA_OUT_0 MFP_CFG(GPIO30, AF3) +#define GPIO31_ULPI_DATA_OUT_1 MFP_CFG(GPIO31, AF3) +#define GPIO32_ULPI_DATA_OUT_2 MFP_CFG(GPIO32, AF3) +#define GPIO33_ULPI_DATA_OUT_3 MFP_CFG(GPIO33, AF3) +#define GPIO34_ULPI_DATA_OUT_4 MFP_CFG(GPIO34, AF3) +#define GPIO35_ULPI_DATA_OUT_5 MFP_CFG(GPIO35, AF3) +#define GPIO36_ULPI_DATA_OUT_6 MFP_CFG(GPIO36, AF3) +#define GPIO37_ULPI_DATA_OUT_7 MFP_CFG(GPIO37, AF3) +#define GPIO33_ULPI_OTG_INTR MFP_CFG(GPIO33, AF1) + +#define ULPI_DIR MFP_CFG_DRV(ULPI_DIR, MFP_AF0, MFP_DS01X) +#define ULPI_NXT MFP_CFG_DRV(ULPI_NXT, MFP_AF0, MFP_DS01X) +#define ULPI_STP MFP_CFG_DRV(ULPI_STP, MFP_AF0, MFP_DS01X) +#endif /* CONFIG_CPU_PXA310 */ + +#endif /* __ASM_ARCH_MFP_PXA300_H */ diff --git a/include/asm-arm/arch-pxa/mfp-pxa320.h b/include/asm-arm/arch-pxa/mfp-pxa320.h new file mode 100644 index 0000000..ae8ba34 --- /dev/null +++ b/include/asm-arm/arch-pxa/mfp-pxa320.h @@ -0,0 +1,446 @@ +/* + * linux/include/asm-arm/arch-pxa/mfp-pxa320.h + * + * PXA320 specific MFP configuration definitions + * + * Copyright (C) 2007 Marvell International Ltd. + * 2007-08-21: eric miao + * initial version + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_ARCH_MFP_PXA320_H +#define __ASM_ARCH_MFP_PXA320_H + +#include + +/* GPIO */ +#define GPIO46_GPIO MFP_CFG(GPIO6, AF0) +#define GPIO49_GPIO MFP_CFG(GPIO49, AF0) +#define GPIO50_GPIO MFP_CFG(GPIO50, AF0) +#define GPIO51_GPIO MFP_CFG(GPIO51, AF0) +#define GPIO52_GPIO MFP_CFG(GPIO52, AF0) + +#define GPIO7_2_GPIO MFP_CFG(GPIO7_2, AF0) +#define GPIO8_2_GPIO MFP_CFG(GPIO8_2, AF0) +#define GPIO9_2_GPIO MFP_CFG(GPIO9_2, AF0) +#define GPIO10_2_GPIO MFP_CFG(GPIO10_2, AF0) +#define GPIO11_2_GPIO MFP_CFG(GPIO11_2, AF0) +#define GPIO12_2_GPIO MFP_CFG(GPIO12_2, AF0) +#define GPIO13_2_GPIO MFP_CFG(GPIO13_2, AF0) +#define GPIO14_2_GPIO MFP_CFG(GPIO14_2, AF0) +#define GPIO15_2_GPIO MFP_CFG(GPIO15_2, AF0) +#define GPIO16_2_GPIO MFP_CFG(GPIO16_2, AF0) +#define GPIO17_2_GPIO MFP_CFG(GPIO17_2, AF0) + +/* Chip Select */ +#define GPIO4_nCS3 MFP_CFG(GPIO4, AF1) + +/* AC97 */ +#define GPIO34_AC97_SYSCLK MFP_CFG(GPIO34, AF1) +#define GPIO39_AC97_BITCLK MFP_CFG(GPIO39, AF1) +#define GPIO40_AC97_nACRESET MFP_CFG(GPIO40, AF1) +#define GPIO35_AC97_SDATA_IN_0 MFP_CFG(GPIO35, AF1) +#define GPIO36_AC97_SDATA_IN_1 MFP_CFG(GPIO36, AF1) +#define GPIO32_AC97_SDATA_IN_2 MFP_CFG(GPIO32, AF2) +#define GPIO33_AC97_SDATA_IN_3 MFP_CFG(GPIO33, AF2) +#define GPIO11_AC97_SDATA_IN_2 MFP_CFG(GPIO11, AF3) +#define GPIO12_AC97_SDATA_IN_3 MFP_CFG(GPIO12, AF3) +#define GPIO37_AC97_SDATA_OUT MFP_CFG(GPIO37, AF1) +#define GPIO38_AC97_SYNC MFP_CFG(GPIO38, AF1) + +/* I2C */ +#define GPIO32_I2C_SCL MFP_CFG_LPM(GPIO32, AF1, PULL_HIGH) +#define GPIO33_I2C_SDA MFP_CFG_LPM(GPIO33, AF1, PULL_HIGH) + +/* QCI */ +#define GPIO49_CI_DD_0 MFP_CFG_DRV(GPIO49, AF1, DS04X) +#define GPIO50_CI_DD_1 MFP_CFG_DRV(GPIO50, AF1, DS04X) +#define GPIO51_CI_DD_2 MFP_CFG_DRV(GPIO51, AF1, DS04X) +#define GPIO52_CI_DD_3 MFP_CFG_DRV(GPIO52, AF1, DS04X) +#define GPIO53_CI_DD_4 MFP_CFG_DRV(GPIO53, AF1, DS04X) +#define GPIO54_CI_DD_5 MFP_CFG_DRV(GPIO54, AF1, DS04X) +#define GPIO55_CI_DD_6 MFP_CFG_DRV(GPIO55, AF1, DS04X) +#define GPIO56_CI_DD_7 MFP_CFG_DRV(GPIO56, AF0, DS04X) +#define GPIO57_CI_DD_8 MFP_CFG_DRV(GPIO57, AF1, DS04X) +#define GPIO58_CI_DD_9 MFP_CFG_DRV(GPIO58, AF1, DS04X) +#define GPIO59_CI_MCLK MFP_CFG_DRV(GPIO59, AF0, DS04X) +#define GPIO60_CI_PCLK MFP_CFG_DRV(GPIO60, AF0, DS04X) +#define GPIO61_CI_HSYNC MFP_CFG_DRV(GPIO61, AF0, DS04X) +#define GPIO62_CI_VSYNC MFP_CFG_DRV(GPIO62, AF0, DS04X) + +#define GPIO31_CIR_OUT MFP_CFG(GPIO31, AF5) + +#define GPIO0_2_CLK_EXT MFP_CFG(GPIO0_2, AF3) +#define GPIO0_DRQ MFP_CFG(GPIO0, AF2) +#define GPIO11_EXT_SYNC0 MFP_CFG(GPIO11, AF5) +#define GPIO12_EXT_SYNC1 MFP_CFG(GPIO12, AF6) +#define GPIO0_2_HZ_CLK MFP_CFG(GPIO0_2, AF1) +#define GPIO14_HZ_CLK MFP_CFG(GPIO14, AF4) +#define GPIO30_ICP_RXD MFP_CFG(GPIO30, AF1) +#define GPIO31_ICP_TXD MFP_CFG(GPIO31, AF1) + +#define GPIO83_KP_DKIN_0 MFP_CFG_LPM(GPIO83, AF3, FLOAT) +#define GPIO84_KP_DKIN_1 MFP_CFG_LPM(GPIO84, AF3, FLOAT) +#define GPIO85_KP_DKIN_2 MFP_CFG_LPM(GPIO85, AF3, FLOAT) +#define GPIO86_KP_DKIN_3 MFP_CFG_LPM(GPIO86, AF3, FLOAT) + +#define GPIO105_KP_DKIN_0 MFP_CFG_LPM(GPIO105, AF2, FLOAT) +#define GPIO106_KP_DKIN_1 MFP_CFG_LPM(GPIO106, AF2, FLOAT) +#define GPIO107_KP_DKIN_2 MFP_CFG_LPM(GPIO107, AF2, FLOAT) +#define GPIO108_KP_DKIN_3 MFP_CFG_LPM(GPIO108, AF2, FLOAT) +#define GPIO109_KP_DKIN_4 MFP_CFG_LPM(GPIO109, AF2, FLOAT) +#define GPIO110_KP_DKIN_5 MFP_CFG_LPM(GPIO110, AF2, FLOAT) +#define GPIO111_KP_DKIN_6 MFP_CFG_LPM(GPIO111, AF2, FLOAT) +#define GPIO112_KP_DKIN_7 MFP_CFG_LPM(GPIO112, AF2, FLOAT) + +#define GPIO113_KP_DKIN_0 MFP_CFG_LPM(GPIO113, AF2, FLOAT) +#define GPIO114_KP_DKIN_1 MFP_CFG_LPM(GPIO114, AF2, FLOAT) +#define GPIO115_KP_DKIN_2 MFP_CFG_LPM(GPIO115, AF2, FLOAT) +#define GPIO116_KP_DKIN_3 MFP_CFG_LPM(GPIO116, AF2, FLOAT) +#define GPIO117_KP_DKIN_4 MFP_CFG_LPM(GPIO117, AF2, FLOAT) +#define GPIO118_KP_DKIN_5 MFP_CFG_LPM(GPIO118, AF2, FLOAT) +#define GPIO119_KP_DKIN_6 MFP_CFG_LPM(GPIO119, AF2, FLOAT) +#define GPIO120_KP_DKIN_7 MFP_CFG_LPM(GPIO120, AF2, FLOAT) + +#define GPIO127_KP_DKIN_0 MFP_CFG_LPM(GPIO127, AF2, FLOAT) +#define GPIO126_KP_DKIN_1 MFP_CFG_LPM(GPIO126, AF2, FLOAT) + +#define GPIO2_2_KP_DKIN_0 MFP_CFG_LPM(GPIO2_2, AF2, FLOAT) +#define GPIO3_2_KP_DKIN_1 MFP_CFG_LPM(GPIO3_2, AF2, FLOAT) +#define GPIO125_KP_DKIN_2 MFP_CFG_LPM(GPIO125, AF2, FLOAT) +#define GPIO124_KP_DKIN_3 MFP_CFG_LPM(GPIO124, AF2, FLOAT) +#define GPIO123_KP_DKIN_4 MFP_CFG_LPM(GPIO123, AF2, FLOAT) +#define GPIO122_KP_DKIN_5 MFP_CFG_LPM(GPIO122, AF2, FLOAT) +#define GPIO121_KP_DKIN_6 MFP_CFG_LPM(GPIO121, AF2, FLOAT) +#define GPIO4_2_KP_DKIN_7 MFP_CFG_LPM(GPIO4_2, AF2, FLOAT) + +#define GPIO113_KP_MKIN_0 MFP_CFG_LPM(GPIO113, AF1, FLOAT) +#define GPIO114_KP_MKIN_1 MFP_CFG_LPM(GPIO114, AF1, FLOAT) +#define GPIO115_KP_MKIN_2 MFP_CFG_LPM(GPIO115, AF1, FLOAT) +#define GPIO116_KP_MKIN_3 MFP_CFG_LPM(GPIO116, AF1, FLOAT) +#define GPIO117_KP_MKIN_4 MFP_CFG_LPM(GPIO117, AF1, FLOAT) +#define GPIO118_KP_MKIN_5 MFP_CFG_LPM(GPIO118, AF1, FLOAT) +#define GPIO119_KP_MKIN_6 MFP_CFG_LPM(GPIO119, AF1, FLOAT) +#define GPIO120_KP_MKIN_7 MFP_CFG_LPM(GPIO120, AF1, FLOAT) + +#define GPIO83_KP_MKOUT_0 MFP_CFG_LPM(GPIO83, AF2, DRIVE_HIGH) +#define GPIO84_KP_MKOUT_1 MFP_CFG_LPM(GPIO84, AF2, DRIVE_HIGH) +#define GPIO85_KP_MKOUT_2 MFP_CFG_LPM(GPIO85, AF2, DRIVE_HIGH) +#define GPIO86_KP_MKOUT_3 MFP_CFG_LPM(GPIO86, AF2, DRIVE_HIGH) +#define GPIO13_KP_MKOUT_4 MFP_CFG_LPM(GPIO13, AF3, DRIVE_HIGH) +#define GPIO14_KP_MKOUT_5 MFP_CFG_LPM(GPIO14, AF3, DRIVE_HIGH) + +#define GPIO121_KP_MKOUT_0 MFP_CFG_LPM(GPIO121, AF1, DRIVE_HIGH) +#define GPIO122_KP_MKOUT_1 MFP_CFG_LPM(GPIO122, AF1, DRIVE_HIGH) +#define GPIO123_KP_MKOUT_2 MFP_CFG_LPM(GPIO123, AF1, DRIVE_HIGH) +#define GPIO124_KP_MKOUT_3 MFP_CFG_LPM(GPIO124, AF1, DRIVE_HIGH) +#define GPIO125_KP_MKOUT_4 MFP_CFG_LPM(GPIO125, AF1, DRIVE_HIGH) +#define GPIO126_KP_MKOUT_5 MFP_CFG_LPM(GPIO126, AF1, DRIVE_HIGH) +#define GPIO127_KP_MKOUT_6 MFP_CFG_LPM(GPIO127, AF1, DRIVE_HIGH) +#define GPIO5_2_KP_MKOUT_7 MFP_CFG_LPM(GPIO5_2, AF1, DRIVE_HIGH) + +/* LCD */ +#define GPIO6_2_LCD_LDD_0 MFP_CFG_DRV(GPIO6_2, AF1, DS01X) +#define GPIO7_2_LCD_LDD_1 MFP_CFG_DRV(GPIO7_2, AF1, DS01X) +#define GPIO8_2_LCD_LDD_2 MFP_CFG_DRV(GPIO8_2, AF1, DS01X) +#define GPIO9_2_LCD_LDD_3 MFP_CFG_DRV(GPIO9_2, AF1, DS01X) +#define GPIO10_2_LCD_LDD_4 MFP_CFG_DRV(GPIO10_2, AF1, DS01X) +#define GPIO11_2_LCD_LDD_5 MFP_CFG_DRV(GPIO11_2, AF1, DS01X) +#define GPIO12_2_LCD_LDD_6 MFP_CFG_DRV(GPIO12_2, AF1, DS01X) +#define GPIO13_2_LCD_LDD_7 MFP_CFG_DRV(GPIO13_2, AF1, DS01X) +#define GPIO63_LCD_LDD_8 MFP_CFG_DRV(GPIO63, AF1, DS01X) +#define GPIO64_LCD_LDD_9 MFP_CFG_DRV(GPIO64, AF1, DS01X) +#define GPIO65_LCD_LDD_10 MFP_CFG_DRV(GPIO65, AF1, DS01X) +#define GPIO66_LCD_LDD_11 MFP_CFG_DRV(GPIO66, AF1, DS01X) +#define GPIO67_LCD_LDD_12 MFP_CFG_DRV(GPIO67, AF1, DS01X) +#define GPIO68_LCD_LDD_13 MFP_CFG_DRV(GPIO68, AF1, DS01X) +#define GPIO69_LCD_LDD_14 MFP_CFG_DRV(GPIO69, AF1, DS01X) +#define GPIO70_LCD_LDD_15 MFP_CFG_DRV(GPIO70, AF1, DS01X) +#define GPIO71_LCD_LDD_16 MFP_CFG_DRV(GPIO71, AF1, DS01X) +#define GPIO72_LCD_LDD_17 MFP_CFG_DRV(GPIO72, AF1, DS01X) +#define GPIO73_LCD_CS_N MFP_CFG_DRV(GPIO73, AF2, DS01X) +#define GPIO74_LCD_VSYNC MFP_CFG_DRV(GPIO74, AF2, DS01X) +#define GPIO14_2_LCD_FCLK MFP_CFG_DRV(GPIO14_2, AF1, DS01X) +#define GPIO15_2_LCD_LCLK MFP_CFG_DRV(GPIO15_2, AF1, DS01X) +#define GPIO16_2_LCD_PCLK MFP_CFG_DRV(GPIO16_2, AF1, DS01X) +#define GPIO17_2_LCD_BIAS MFP_CFG_DRV(GPIO17_2, AF1, DS01X) +#define GPIO64_LCD_VSYNC MFP_CFG_DRV(GPIO64, AF2, DS01X) +#define GPIO63_LCD_CS_N MFP_CFG_DRV(GPIO63, AF2, DS01X) + +#define GPIO6_2_MLCD_DD_0 MFP_CFG_DRV(GPIO6_2, AF7, DS08X) +#define GPIO7_2_MLCD_DD_1 MFP_CFG_DRV(GPIO7_2, AF7, DS08X) +#define GPIO8_2_MLCD_DD_2 MFP_CFG_DRV(GPIO8_2, AF7, DS08X) +#define GPIO9_2_MLCD_DD_3 MFP_CFG_DRV(GPIO9_2, AF7, DS08X) +#define GPIO10_2_MLCD_DD_4 MFP_CFG_DRV(GPIO10_2, AF7, DS08X) +#define GPIO11_2_MLCD_DD_5 MFP_CFG_DRV(GPIO11_2, AF7, DS08X) +#define GPIO12_2_MLCD_DD_6 MFP_CFG_DRV(GPIO12_2, AF7, DS08X) +#define GPIO13_2_MLCD_DD_7 MFP_CFG_DRV(GPIO13_2, AF7, DS08X) +#define GPIO63_MLCD_DD_8 MFP_CFG_DRV(GPIO63, AF7, DS08X) +#define GPIO64_MLCD_DD_9 MFP_CFG_DRV(GPIO64, AF7, DS08X) +#define GPIO65_MLCD_DD_10 MFP_CFG_DRV(GPIO65, AF7, DS08X) +#define GPIO66_MLCD_DD_11 MFP_CFG_DRV(GPIO66, AF7, DS08X) +#define GPIO67_MLCD_DD_12 MFP_CFG_DRV(GPIO67, AF7, DS08X) +#define GPIO68_MLCD_DD_13 MFP_CFG_DRV(GPIO68, AF7, DS08X) +#define GPIO69_MLCD_DD_14 MFP_CFG_DRV(GPIO69, AF7, DS08X) +#define GPIO70_MLCD_DD_15 MFP_CFG_DRV(GPIO70, AF7, DS08X) +#define GPIO71_MLCD_DD_16 MFP_CFG_DRV(GPIO71, AF7, DS08X) +#define GPIO72_MLCD_DD_17 MFP_CFG_DRV(GPIO72, AF7, DS08X) +#define GPIO73_MLCD_CS MFP_CFG_DRV(GPIO73, AF7, DS08X) +#define GPIO74_MLCD_VSYNC MFP_CFG_DRV(GPIO74, AF7, DS08X) +#define GPIO14_2_MLCD_FCLK MFP_CFG_DRV(GPIO14_2, AF7, DS08X) +#define GPIO15_2_MLCD_LCLK MFP_CFG_DRV(GPIO15_2, AF7, DS08X) +#define GPIO16_2_MLCD_PCLK MFP_CFG_DRV(GPIO16_2, AF7, DS08X) +#define GPIO17_2_MLCD_BIAS MFP_CFG_DRV(GPIO17_2, AF7, DS08X) + +/* MMC1 */ +#define GPIO9_MMC1_CMD MFP_CFG_LPM(GPIO9, AF4, DRIVE_HIGH) +#define GPIO22_MMC1_CLK MFP_CFG_LPM(GPIO22, AF4, DRIVE_HIGH) +#define GPIO23_MMC1_CMD MFP_CFG_LPM(GPIO23, AF4, DRIVE_HIGH) +#define GPIO30_MMC1_CLK MFP_CFG_LPM(GPIO30, AF4, DRIVE_HIGH) +#define GPIO31_MMC1_CMD MFP_CFG_LPM(GPIO31, AF4, DRIVE_HIGH) +#define GPIO5_MMC1_DAT0 MFP_CFG_LPM(GPIO5, AF4, DRIVE_HIGH) +#define GPIO6_MMC1_DAT1 MFP_CFG_LPM(GPIO6, AF4, DRIVE_HIGH) +#define GPIO7_MMC1_DAT2 MFP_CFG_LPM(GPIO7, AF4, DRIVE_HIGH) +#define GPIO8_MMC1_DAT3 MFP_CFG_LPM(GPIO8, AF4, DRIVE_HIGH) +#define GPIO18_MMC1_DAT0 MFP_CFG_LPM(GPIO18, AF4, DRIVE_HIGH) +#define GPIO19_MMC1_DAT1 MFP_CFG_LPM(GPIO19, AF4, DRIVE_HIGH) +#define GPIO20_MMC1_DAT2 MFP_CFG_LPM(GPIO20, AF4, DRIVE_HIGH) +#define GPIO21_MMC1_DAT3 MFP_CFG_LPM(GPIO21, AF4, DRIVE_HIGH) + +#define GPIO28_MMC2_CLK MFP_CFG_LPM(GPIO28, AF4, PULL_HIGH) +#define GPIO29_MMC2_CMD MFP_CFG_LPM(GPIO29, AF4, PULL_HIGH) +#define GPIO30_MMC2_CLK MFP_CFG_LPM(GPIO30, AF3, PULL_HIGH) +#define GPIO31_MMC2_CMD MFP_CFG_LPM(GPIO31, AF3, PULL_HIGH) +#define GPIO79_MMC2_CLK MFP_CFG_LPM(GPIO79, AF4, PULL_HIGH) +#define GPIO80_MMC2_CMD MFP_CFG_LPM(GPIO80, AF4, PULL_HIGH) + +#define GPIO5_MMC2_DAT0 MFP_CFG_LPM(GPIO5, AF2, PULL_HIGH) +#define GPIO6_MMC2_DAT1 MFP_CFG_LPM(GPIO6, AF2, PULL_HIGH) +#define GPIO7_MMC2_DAT2 MFP_CFG_LPM(GPIO7, AF2, PULL_HIGH) +#define GPIO8_MMC2_DAT3 MFP_CFG_LPM(GPIO8, AF2, PULL_HIGH) +#define GPIO24_MMC2_DAT0 MFP_CFG_LPM(GPIO24, AF4, PULL_HIGH) +#define GPIO75_MMC2_DAT0 MFP_CFG_LPM(GPIO75, AF4, PULL_HIGH) +#define GPIO25_MMC2_DAT1 MFP_CFG_LPM(GPIO25, AF4, PULL_HIGH) +#define GPIO76_MMC2_DAT1 MFP_CFG_LPM(GPIO76, AF4, PULL_HIGH) +#define GPIO26_MMC2_DAT2 MFP_CFG_LPM(GPIO26, AF4, PULL_HIGH) +#define GPIO77_MMC2_DAT2 MFP_CFG_LPM(GPIO77, AF4, PULL_HIGH) +#define GPIO27_MMC2_DAT3 MFP_CFG_LPM(GPIO27, AF4, PULL_HIGH) +#define GPIO78_MMC2_DAT3 MFP_CFG_LPM(GPIO78, AF4, PULL_HIGH) + +/* 1-Wire */ +#define GPIO14_ONE_WIRE MFP_CFG_LPM(GPIO14, AF5, FLOAT) +#define GPIO0_2_ONE_WIRE MFP_CFG_LPM(GPIO0_2, AF2, FLOAT) + +/* SSP1 */ +#define GPIO87_SSP1_EXTCLK MFP_CFG(GPIO87, AF1) +#define GPIO88_SSP1_SYSCLK MFP_CFG(GPIO88, AF1) +#define GPIO83_SSP1_SCLK MFP_CFG(GPIO83, AF1) +#define GPIO84_SSP1_SFRM MFP_CFG(GPIO84, AF1) +#define GPIO85_SSP1_RXD MFP_CFG(GPIO85, AF6) +#define GPIO85_SSP1_TXD MFP_CFG(GPIO85, AF1) +#define GPIO86_SSP1_RXD MFP_CFG(GPIO86, AF1) +#define GPIO86_SSP1_TXD MFP_CFG(GPIO86, AF6) + +/* SSP2 */ +#define GPIO39_SSP2_EXTCLK MFP_CFG(GPIO39, AF2) +#define GPIO40_SSP2_SYSCLK MFP_CFG(GPIO40, AF2) +#define GPIO12_SSP2_SCLK MFP_CFG(GPIO12, AF2) +#define GPIO35_SSP2_SCLK MFP_CFG(GPIO35, AF2) +#define GPIO36_SSP2_SFRM MFP_CFG(GPIO36, AF2) +#define GPIO37_SSP2_RXD MFP_CFG(GPIO37, AF5) +#define GPIO37_SSP2_TXD MFP_CFG(GPIO37, AF2) +#define GPIO38_SSP2_RXD MFP_CFG(GPIO38, AF2) +#define GPIO38_SSP2_TXD MFP_CFG(GPIO38, AF5) + +#define GPIO69_SSP3_SCLK MFP_CFG(GPIO69, AF2, DS08X, FLOAT) +#define GPIO70_SSP3_FRM MFP_CFG(GPIO70, AF2, DS08X, DRIVE_LOW) +#define GPIO89_SSP3_SCLK MFP_CFG(GPIO89, AF1, DS08X, FLOAT) +#define GPIO90_SSP3_FRM MFP_CFG(GPIO90, AF1, DS08X, DRIVE_LOW) +#define GPIO71_SSP3_RXD MFP_CFG_X(GPIO71, AF5, DS08X, FLOAT) +#define GPIO71_SSP3_TXD MFP_CFG_X(GPIO71, AF2, DS08X, DRIVE_LOW) +#define GPIO72_SSP3_RXD MFP_CFG_X(GPIO72, AF2, DS08X, FLOAT) +#define GPIO72_SSP3_TXD MFP_CFG_X(GPIO72, AF5, DS08X, DRIVE_LOW) +#define GPIO91_SSP3_RXD MFP_CFG_X(GPIO91, AF5, DS08X, FLOAT) +#define GPIO91_SSP3_TXD MFP_CFG_X(GPIO91, AF1, DS08X, DRIVE_LOW) +#define GPIO92_SSP3_RXD MFP_CFG_X(GPIO92, AF1, DS08X, FLOAT) +#define GPIO92_SSP3_TXD MFP_CFG_X(GPIO92, AF5, DS08X, DRIVE_LOW) + +#define GPIO93_SSP4_SCLK MFP_CFG_LPM(GPIO93, AF1, PULL_HIGH) +#define GPIO94_SSP4_FRM MFP_CFG_LPM(GPIO94, AF1, PULL_HIGH) +#define GPIO94_SSP4_RXD MFP_CFG_LPM(GPIO94, AF5, PULL_HIGH) +#define GPIO95_SSP4_RXD MFP_CFG_LPM(GPIO95, AF5, PULL_HIGH) +#define GPIO95_SSP4_TXD MFP_CFG_LPM(GPIO95, AF1, PULL_HIGH) +#define GPIO96_SSP4_RXD MFP_CFG_LPM(GPIO96, AF1, PULL_HIGH) +#define GPIO96_SSP4_TXD MFP_CFG_LPM(GPIO96, AF5, PULL_HIGH) + +/* UART1 */ +#define GPIO41_UART1_RXD MFP_CFG_LPM(GPIO41, AF2, FLOAT) +#define GPIO41_UART1_TXD MFP_CFG_LPM(GPIO41, AF4, FLOAT) +#define GPIO42_UART1_RXD MFP_CFG_LPM(GPIO42, AF4, FLOAT) +#define GPIO42_UART1_TXD MFP_CFG_LPM(GPIO42, AF2, FLOAT) +#define GPIO97_UART1_RXD MFP_CFG_LPM(GPIO97, AF1, FLOAT) +#define GPIO97_UART1_TXD MFP_CFG_LPM(GPIO97, AF6, FLOAT) +#define GPIO98_UART1_RXD MFP_CFG_LPM(GPIO98, AF6, FLOAT) +#define GPIO98_UART1_TXD MFP_CFG_LPM(GPIO98, AF1, FLOAT) +#define GPIO43_UART1_CTS MFP_CFG_LPM(GPIO43, AF2, FLOAT) +#define GPIO43_UART1_RTS MFP_CFG_LPM(GPIO43, AF4, FLOAT) +#define GPIO48_UART1_CTS MFP_CFG_LPM(GPIO48, AF4, FLOAT) +#define GPIO48_UART1_RTS MFP_CFG_LPM(GPIO48, AF2, FLOAT) +#define GPIO99_UART1_CTS MFP_CFG_LPM(GPIO99, AF1, FLOAT) +#define GPIO99_UART1_RTS MFP_CFG_LPM(GPIO99, AF6, FLOAT) +#define GPIO104_UART1_CTS MFP_CFG_LPM(GPIO104, AF6, FLOAT) +#define GPIO104_UART1_RTS MFP_CFG_LPM(GPIO104, AF1, FLOAT) +#define GPIO45_UART1_DTR MFP_CFG_LPM(GPIO45, AF4, FLOAT) +#define GPIO45_UART1_DSR MFP_CFG_LPM(GPIO45, AF2, FLOAT) +#define GPIO47_UART1_DTR MFP_CFG_LPM(GPIO47, AF2, FLOAT) +#define GPIO47_UART1_DSR MFP_CFG_LPM(GPIO47, AF4, FLOAT) +#define GPIO101_UART1_DTR MFP_CFG_LPM(GPIO101, AF6, FLOAT) +#define GPIO101_UART1_DSR MFP_CFG_LPM(GPIO101, AF1, FLOAT) +#define GPIO103_UART1_DTR MFP_CFG_LPM(GPIO103, AF1, FLOAT) +#define GPIO103_UART1_DSR MFP_CFG_LPM(GPIO103, AF6, FLOAT) +#define GPIO44_UART1_DCD MFP_CFG_LPM(GPIO44, AF2, FLOAT) +#define GPIO100_UART1_DCD MFP_CFG_LPM(GPIO100, AF1, FLOAT) +#define GPIO46_UART1_RI MFP_CFG_LPM(GPIO46, AF2, FLOAT) +#define GPIO102_UART1_RI MFP_CFG_LPM(GPIO102, AF1, FLOAT) + +/* UART2 */ +#define GPIO109_UART2_CTS MFP_CFG_LPM(GPIO109, AF3, FLOAT) +#define GPIO109_UART2_RTS MFP_CFG_LPM(GPIO109, AF1, FLOAT) +#define GPIO112_UART2_CTS MFP_CFG_LPM(GPIO112, AF1, FLOAT) +#define GPIO112_UART2_RTS MFP_CFG_LPM(GPIO112, AF3, FLOAT) +#define GPIO110_UART2_RXD MFP_CFG_LPM(GPIO110, AF1, FLOAT) +#define GPIO110_UART2_TXD MFP_CFG_LPM(GPIO110, AF3, FLOAT) +#define GPIO111_UART2_RXD MFP_CFG_LPM(GPIO111, AF3, FLOAT) +#define GPIO111_UART2_TXD MFP_CFG_LPM(GPIO111, AF1, FLOAT) + +/* UART3 */ +#define GPIO89_UART3_CTS MFP_CFG_LPM(GPIO89, AF2, FLOAT) +#define GPIO89_UART3_RTS MFP_CFG_LPM(GPIO89, AF4, FLOAT) +#define GPIO90_UART3_CTS MFP_CFG_LPM(GPIO90, AF4, FLOAT) +#define GPIO90_UART3_RTS MFP_CFG_LPM(GPIO90, AF2, FLOAT) +#define GPIO105_UART3_CTS MFP_CFG_LPM(GPIO105, AF1, FLOAT) +#define GPIO105_UART3_RTS MFP_CFG_LPM(GPIO105, AF3, FLOAT) +#define GPIO106_UART3_CTS MFP_CFG_LPM(GPIO106, AF3, FLOAT) +#define GPIO106_UART3_RTS MFP_CFG_LPM(GPIO106, AF1, FLOAT) +#define GPIO30_UART3_RXD MFP_CFG_LPM(GPIO30, AF2, FLOAT) +#define GPIO30_UART3_TXD MFP_CFG_LPM(GPIO30, AF6, FLOAT) +#define GPIO31_UART3_RXD MFP_CFG_LPM(GPIO31, AF6, FLOAT) +#define GPIO31_UART3_TXD MFP_CFG_LPM(GPIO31, AF2, FLOAT) +#define GPIO91_UART3_RXD MFP_CFG_LPM(GPIO91, AF4, FLOAT) +#define GPIO91_UART3_TXD MFP_CFG_LPM(GPIO91, AF2, FLOAT) +#define GPIO92_UART3_RXD MFP_CFG_LPM(GPIO92, AF2, FLOAT) +#define GPIO92_UART3_TXD MFP_CFG_LPM(GPIO92, AF4, FLOAT) +#define GPIO107_UART3_RXD MFP_CFG_LPM(GPIO107, AF3, FLOAT) +#define GPIO107_UART3_TXD MFP_CFG_LPM(GPIO107, AF1, FLOAT) +#define GPIO108_UART3_RXD MFP_CFG_LPM(GPIO108, AF1, FLOAT) +#define GPIO108_UART3_TXD MFP_CFG_LPM(GPIO108, AF3, FLOAT) + + +/* USB 2.0 UTMI */ +#define GPIO10_UTM_CLK MFP_CFG(GPIO10, AF1) +#define GPIO36_U2D_RXERROR MFP_CFG(GPIO36, AF3) +#define GPIO60_U2D_RXERROR MFP_CFG(GPIO60, AF1) +#define GPIO87_U2D_RXERROR MFP_CFG(GPIO87, AF5) +#define GPIO34_UTM_RXVALID MFP_CFG(GPIO34, AF3) +#define GPIO58_UTM_RXVALID MFP_CFG(GPIO58, AF2) +#define GPIO85_UTM_RXVALID MFP_CFG(GPIO85, AF5) +#define GPIO35_UTM_RXACTIVE MFP_CFG(GPIO35, AF3) +#define GPIO59_UTM_RXACTIVE MFP_CFG(GPIO59, AF1) +#define GPIO86_UTM_RXACTIVE MFP_CFG(GPIO86, AF5) +#define GPIO73_UTM_TXREADY MFP_CFG(GPIO73, AF1) +#define GPIO68_UTM_LINESTATE_0 MFP_CFG(GPIO68, AF3) +#define GPIO90_UTM_LINESTATE_0 MFP_CFG(GPIO90, AF3) +#define GPIO102_UTM_LINESTATE_0 MFP_CFG(GPIO102, AF3) +#define GPIO107_UTM_LINESTATE_0 MFP_CFG(GPIO107, AF4) +#define GPIO69_UTM_LINESTATE_1 MFP_CFG(GPIO69, AF3) +#define GPIO91_UTM_LINESTATE_1 MFP_CFG(GPIO91, AF3) +#define GPIO103_UTM_LINESTATE_1 MFP_CFG(GPIO103, AF3) + +#define GPIO41_U2D_PHYDATA_0 MFP_CFG(GPIO41, AF3) +#define GPIO42_U2D_PHYDATA_1 MFP_CFG(GPIO42, AF3) +#define GPIO43_U2D_PHYDATA_2 MFP_CFG(GPIO43, AF3) +#define GPIO44_U2D_PHYDATA_3 MFP_CFG(GPIO44, AF3) +#define GPIO45_U2D_PHYDATA_4 MFP_CFG(GPIO45, AF3) +#define GPIO46_U2D_PHYDATA_5 MFP_CFG(GPIO46, AF3) +#define GPIO47_U2D_PHYDATA_6 MFP_CFG(GPIO47, AF3) +#define GPIO48_U2D_PHYDATA_7 MFP_CFG(GPIO48, AF3) + +#define GPIO49_U2D_PHYDATA_0 MFP_CFG(GPIO49, AF3) +#define GPIO50_U2D_PHYDATA_1 MFP_CFG(GPIO50, AF3) +#define GPIO51_U2D_PHYDATA_2 MFP_CFG(GPIO51, AF3) +#define GPIO52_U2D_PHYDATA_3 MFP_CFG(GPIO52, AF3) +#define GPIO53_U2D_PHYDATA_4 MFP_CFG(GPIO53, AF3) +#define GPIO54_U2D_PHYDATA_5 MFP_CFG(GPIO54, AF3) +#define GPIO55_U2D_PHYDATA_6 MFP_CFG(GPIO55, AF3) +#define GPIO56_U2D_PHYDATA_7 MFP_CFG(GPIO56, AF3) + +#define GPIO37_U2D_OPMODE0 MFP_CFG(GPIO37, AF4) +#define GPIO61_U2D_OPMODE0 MFP_CFG(GPIO61, AF2) +#define GPIO88_U2D_OPMODE0 MFP_CFG(GPIO88, AF7) + +#define GPIO38_U2D_OPMODE1 MFP_CFG(GPIO38, AF4) +#define GPIO62_U2D_OPMODE1 MFP_CFG(GPIO62, AF2) +#define GPIO104_U2D_OPMODE1 MFP_CFG(GPIO104, AF4) +#define GPIO108_U2D_OPMODE1 MFP_CFG(GPIO108, AF5) + +#define GPIO74_U2D_RESET MFP_CFG(GPIO74, AF1) +#define GPIO93_U2D_RESET MFP_CFG(GPIO93, AF2) +#define GPIO98_U2D_RESET MFP_CFG(GPIO98, AF3) + +#define GPIO67_U2D_SUSPEND MFP_CFG(GPIO67, AF3) +#define GPIO96_U2D_SUSPEND MFP_CFG(GPIO96, AF2) +#define GPIO101_U2D_SUSPEND MFP_CFG(GPIO101, AF3) + +#define GPIO66_U2D_TERM_SEL MFP_CFG(GPIO66, AF5) +#define GPIO95_U2D_TERM_SEL MFP_CFG(GPIO95, AF3) +#define GPIO97_U2D_TERM_SEL MFP_CFG(GPIO97, AF7) +#define GPIO100_U2D_TERM_SEL MFP_CFG(GPIO100, AF5) + +#define GPIO39_U2D_TXVALID MFP_CFG(GPIO39, AF4) +#define GPIO70_U2D_TXVALID MFP_CFG(GPIO70, AF5) +#define GPIO83_U2D_TXVALID MFP_CFG(GPIO83, AF7) + +#define GPIO65_U2D_XCVR_SEL MFP_CFG(GPIO65, AF5) +#define GPIO94_U2D_XCVR_SEL MFP_CFG(GPIO94, AF3) +#define GPIO99_U2D_XCVR_SEL MFP_CFG(GPIO99, AF5) + +/* USB Host 1.1 */ +#define GPIO2_2_USBH_PEN MFP_CFG(GPIO2_2, AF1) +#define GPIO3_2_USBH_PWR MFP_CFG(GPIO3_2, AF1) + +/* USB P2 */ +#define GPIO97_USB_P2_2 MFP_CFG(GPIO97, AF2) +#define GPIO97_USB_P2_6 MFP_CFG(GPIO97, AF4) +#define GPIO98_USB_P2_2 MFP_CFG(GPIO98, AF4) +#define GPIO98_USB_P2_6 MFP_CFG(GPIO98, AF2) +#define GPIO99_USB_P2_1 MFP_CFG(GPIO99, AF2) +#define GPIO100_USB_P2_4 MFP_CFG(GPIO100, AF2) +#define GPIO101_USB_P2_8 MFP_CFG(GPIO101, AF2) +#define GPIO102_USB_P2_3 MFP_CFG(GPIO102, AF2) +#define GPIO103_USB_P2_5 MFP_CFG(GPIO103, AF2) +#define GPIO104_USB_P2_7 MFP_CFG(GPIO104, AF2) + +/* USB P3 */ +#define GPIO75_USB_P3_1 MFP_CFG(GPIO75, AF2) +#define GPIO76_USB_P3_2 MFP_CFG(GPIO76, AF2) +#define GPIO77_USB_P3_3 MFP_CFG(GPIO77, AF2) +#define GPIO78_USB_P3_4 MFP_CFG(GPIO78, AF2) +#define GPIO79_USB_P3_5 MFP_CFG(GPIO79, AF2) +#define GPIO80_USB_P3_6 MFP_CFG(GPIO80, AF2) + +#define GPIO13_CHOUT0 MFP_CFG(GPIO13, AF6) +#define GPIO14_CHOUT1 MFP_CFG(GPIO14, AF6) + +#define GPIO2_RDY MFP_CFG(GPIO2, AF1) +#define GPIO5_NPIOR MFP_CFG(GPIO5, AF3) + +#define GPIO11_PWM0_OUT MFP_CFG(GPIO11, AF1) +#define GPIO12_PWM1_OUT MFP_CFG(GPIO12, AF1) +#define GPIO13_PWM2_OUT MFP_CFG(GPIO13, AF1) +#define GPIO14_PWM3_OUT MFP_CFG(GPIO14, AF1) + +#endif /* __ASM_ARCH_MFP_PXA320_H */ diff --git a/include/asm-arm/arch-pxa/mfp.h b/include/asm-arm/arch-pxa/mfp.h new file mode 100644 index 0000000..6029174 --- /dev/null +++ b/include/asm-arm/arch-pxa/mfp.h @@ -0,0 +1,576 @@ +/* + * linux/include/asm-arm/arch-pxa/mfp.h + * + * Multi-Function Pin Definitions + * + * Copyright (C) 2007 Marvell International Ltd. + * + * 2007-8-21: eric miao + * initial version + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_ARCH_MFP_H +#define __ASM_ARCH_MFP_H + +#define MFPR_BASE (0x40e10000) +#define MFPR_SIZE (PAGE_SIZE) + +#define mfp_to_gpio(m) ((m) % 128) + +/* list of all the configurable MFP pins */ +enum { + MFP_PIN_INVALID = -1, + + MFP_PIN_GPIO0 = 0, + MFP_PIN_GPIO1, + MFP_PIN_GPIO2, + MFP_PIN_GPIO3, + MFP_PIN_GPIO4, + MFP_PIN_GPIO5, + MFP_PIN_GPIO6, + MFP_PIN_GPIO7, + MFP_PIN_GPIO8, + MFP_PIN_GPIO9, + MFP_PIN_GPIO10, + MFP_PIN_GPIO11, + MFP_PIN_GPIO12, + MFP_PIN_GPIO13, + MFP_PIN_GPIO14, + MFP_PIN_GPIO15, + MFP_PIN_GPIO16, + MFP_PIN_GPIO17, + MFP_PIN_GPIO18, + MFP_PIN_GPIO19, + MFP_PIN_GPIO20, + MFP_PIN_GPIO21, + MFP_PIN_GPIO22, + MFP_PIN_GPIO23, + MFP_PIN_GPIO24, + MFP_PIN_GPIO25, + MFP_PIN_GPIO26, + MFP_PIN_GPIO27, + MFP_PIN_GPIO28, + MFP_PIN_GPIO29, + MFP_PIN_GPIO30, + MFP_PIN_GPIO31, + MFP_PIN_GPIO32, + MFP_PIN_GPIO33, + MFP_PIN_GPIO34, + MFP_PIN_GPIO35, + MFP_PIN_GPIO36, + MFP_PIN_GPIO37, + MFP_PIN_GPIO38, + MFP_PIN_GPIO39, + MFP_PIN_GPIO40, + MFP_PIN_GPIO41, + MFP_PIN_GPIO42, + MFP_PIN_GPIO43, + MFP_PIN_GPIO44, + MFP_PIN_GPIO45, + MFP_PIN_GPIO46, + MFP_PIN_GPIO47, + MFP_PIN_GPIO48, + MFP_PIN_GPIO49, + MFP_PIN_GPIO50, + MFP_PIN_GPIO51, + MFP_PIN_GPIO52, + MFP_PIN_GPIO53, + MFP_PIN_GPIO54, + MFP_PIN_GPIO55, + MFP_PIN_GPIO56, + MFP_PIN_GPIO57, + MFP_PIN_GPIO58, + MFP_PIN_GPIO59, + MFP_PIN_GPIO60, + MFP_PIN_GPIO61, + MFP_PIN_GPIO62, + MFP_PIN_GPIO63, + MFP_PIN_GPIO64, + MFP_PIN_GPIO65, + MFP_PIN_GPIO66, + MFP_PIN_GPIO67, + MFP_PIN_GPIO68, + MFP_PIN_GPIO69, + MFP_PIN_GPIO70, + MFP_PIN_GPIO71, + MFP_PIN_GPIO72, + MFP_PIN_GPIO73, + MFP_PIN_GPIO74, + MFP_PIN_GPIO75, + MFP_PIN_GPIO76, + MFP_PIN_GPIO77, + MFP_PIN_GPIO78, + MFP_PIN_GPIO79, + MFP_PIN_GPIO80, + MFP_PIN_GPIO81, + MFP_PIN_GPIO82, + MFP_PIN_GPIO83, + MFP_PIN_GPIO84, + MFP_PIN_GPIO85, + MFP_PIN_GPIO86, + MFP_PIN_GPIO87, + MFP_PIN_GPIO88, + MFP_PIN_GPIO89, + MFP_PIN_GPIO90, + MFP_PIN_GPIO91, + MFP_PIN_GPIO92, + MFP_PIN_GPIO93, + MFP_PIN_GPIO94, + MFP_PIN_GPIO95, + MFP_PIN_GPIO96, + MFP_PIN_GPIO97, + MFP_PIN_GPIO98, + MFP_PIN_GPIO99, + MFP_PIN_GPIO100, + MFP_PIN_GPIO101, + MFP_PIN_GPIO102, + MFP_PIN_GPIO103, + MFP_PIN_GPIO104, + MFP_PIN_GPIO105, + MFP_PIN_GPIO106, + MFP_PIN_GPIO107, + MFP_PIN_GPIO108, + MFP_PIN_GPIO109, + MFP_PIN_GPIO110, + MFP_PIN_GPIO111, + MFP_PIN_GPIO112, + MFP_PIN_GPIO113, + MFP_PIN_GPIO114, + MFP_PIN_GPIO115, + MFP_PIN_GPIO116, + MFP_PIN_GPIO117, + MFP_PIN_GPIO118, + MFP_PIN_GPIO119, + MFP_PIN_GPIO120, + MFP_PIN_GPIO121, + MFP_PIN_GPIO122, + MFP_PIN_GPIO123, + MFP_PIN_GPIO124, + MFP_PIN_GPIO125, + MFP_PIN_GPIO126, + MFP_PIN_GPIO127, + MFP_PIN_GPIO0_2, + MFP_PIN_GPIO1_2, + MFP_PIN_GPIO2_2, + MFP_PIN_GPIO3_2, + MFP_PIN_GPIO4_2, + MFP_PIN_GPIO5_2, + MFP_PIN_GPIO6_2, + MFP_PIN_GPIO7_2, + MFP_PIN_GPIO8_2, + MFP_PIN_GPIO9_2, + MFP_PIN_GPIO10_2, + MFP_PIN_GPIO11_2, + MFP_PIN_GPIO12_2, + MFP_PIN_GPIO13_2, + MFP_PIN_GPIO14_2, + MFP_PIN_GPIO15_2, + MFP_PIN_GPIO16_2, + MFP_PIN_GPIO17_2, + + MFP_PIN_ULPI_STP, + MFP_PIN_ULPI_NXT, + MFP_PIN_ULPI_DIR, + + MFP_PIN_nXCVREN, + MFP_PIN_DF_CLE_nOE, + MFP_PIN_DF_nADV1_ALE, + MFP_PIN_DF_SCLK_E, + MFP_PIN_DF_SCLK_S, + MFP_PIN_nBE0, + MFP_PIN_nBE1, + MFP_PIN_DF_nADV2_ALE, + MFP_PIN_DF_INT_RnB, + MFP_PIN_DF_nCS0, + MFP_PIN_DF_nCS1, + MFP_PIN_nLUA, + MFP_PIN_nLLA, + MFP_PIN_DF_nWE, + MFP_PIN_DF_ALE_nWE, + MFP_PIN_DF_nRE_nOE, + MFP_PIN_DF_ADDR0, + MFP_PIN_DF_ADDR1, + MFP_PIN_DF_ADDR2, + MFP_PIN_DF_ADDR3, + MFP_PIN_DF_IO0, + MFP_PIN_DF_IO1, + MFP_PIN_DF_IO2, + MFP_PIN_DF_IO3, + MFP_PIN_DF_IO4, + MFP_PIN_DF_IO5, + MFP_PIN_DF_IO6, + MFP_PIN_DF_IO7, + MFP_PIN_DF_IO8, + MFP_PIN_DF_IO9, + MFP_PIN_DF_IO10, + MFP_PIN_DF_IO11, + MFP_PIN_DF_IO12, + MFP_PIN_DF_IO13, + MFP_PIN_DF_IO14, + MFP_PIN_DF_IO15, + + MFP_PIN_MAX, +}; + +/* + * Table that determines the low power modes outputs, with actual settings + * used in parentheses for don't-care values. Except for the float output, + * the configured driven and pulled levels match, so if there is a need for + * non-LPM pulled output, the same configuration could probably be used. + * + * Output value sleep_oe_n sleep_data pullup_en pulldown_en pull_sel + * (bit 7) (bit 8) (bit 14d) (bit 13d) + * + * Drive 0 0 0 0 X (1) 0 + * Drive 1 0 1 X (1) 0 0 + * Pull hi (1) 1 X(1) 1 0 0 + * Pull lo (0) 1 X(0) 0 1 0 + * Z (float) 1 X(0) 0 0 0 + */ +#define MFP_LPM_DRIVE_LOW 0x8 +#define MFP_LPM_DRIVE_HIGH 0x6 +#define MFP_LPM_PULL_HIGH 0x7 +#define MFP_LPM_PULL_LOW 0x9 +#define MFP_LPM_FLOAT 0x1 +#define MFP_LPM_PULL_NEITHER 0x0 + +/* + * The pullup and pulldown state of the MFP pin is by default determined by + * selected alternate function. In case some buggy devices need to override + * this default behavior, pxa3xx_mfp_set_pull() can be invoked with one of + * the following definition as the parameter. + * + * Definition pull_sel pullup_en pulldown_en + * MFP_PULL_HIGH 1 1 0 + * MFP_PULL_LOW 1 0 1 + * MFP_PULL_BOTH 1 1 1 + * MFP_PULL_NONE 1 0 0 + * MFP_PULL_DEFAULT 0 X X + * + * NOTE: pxa3xx_mfp_set_pull() will modify the PULLUP_EN and PULLDOWN_EN + * bits, which will cause potential conflicts with the low power mode + * setting, device drivers should take care of this + */ +#define MFP_PULL_BOTH (0x7u) +#define MFP_PULL_HIGH (0x6u) +#define MFP_PULL_LOW (0x5u) +#define MFP_PULL_NONE (0x4u) +#define MFP_PULL_DEFAULT (0x0u) + +#define MFP_AF0 (0) +#define MFP_AF1 (1) +#define MFP_AF2 (2) +#define MFP_AF3 (3) +#define MFP_AF4 (4) +#define MFP_AF5 (5) +#define MFP_AF6 (6) +#define MFP_AF7 (7) + +#define MFP_DS01X (0) +#define MFP_DS02X (1) +#define MFP_DS03X (2) +#define MFP_DS04X (3) +#define MFP_DS06X (4) +#define MFP_DS08X (5) +#define MFP_DS10X (6) +#define MFP_DS12X (7) + +#define MFP_EDGE_BOTH 0x3 +#define MFP_EDGE_RISE 0x2 +#define MFP_EDGE_FALL 0x1 +#define MFP_EDGE_NONE 0x0 + +#define MFPR_AF_MASK 0x0007 +#define MFPR_DRV_MASK 0x1c00 +#define MFPR_RDH_MASK 0x0200 +#define MFPR_LPM_MASK 0xe180 +#define MFPR_PULL_MASK 0xe000 +#define MFPR_EDGE_MASK 0x0070 + +#define MFPR_ALT_OFFSET 0 +#define MFPR_ERE_OFFSET 4 +#define MFPR_EFE_OFFSET 5 +#define MFPR_EC_OFFSET 6 +#define MFPR_SON_OFFSET 7 +#define MFPR_SD_OFFSET 8 +#define MFPR_SS_OFFSET 9 +#define MFPR_DRV_OFFSET 10 +#define MFPR_PD_OFFSET 13 +#define MFPR_PU_OFFSET 14 +#define MFPR_PS_OFFSET 15 + +#define MFPR(af, drv, rdh, lpm, edge) \ + (((af) & 0x7) | (((drv) & 0x7) << 10) |\ + (((rdh) & 0x1) << 9) |\ + (((lpm) & 0x3) << 7) |\ + (((lpm) & 0x4) << 12)|\ + (((lpm) & 0x8) << 10)|\ + ((!(edge)) << 6) |\ + (((edge) & 0x1) << 5) |\ + (((edge) & 0x2) << 3)) + +/* + * a possible MFP configuration is represented by a 32-bit integer + * bit 0..15 - MFPR value (16-bit) + * bit 16..31 - mfp pin index (used to obtain the MFPR offset) + * + * to facilitate the definition, the following macros are provided + * + * MFPR_DEFAULT - default MFPR value, with + * alternate function = 0, + * drive strength = fast 1mA (MFP_DS01X) + * low power mode = default + * release dalay hold = false (RDH bit) + * edge detection = none + * + * MFP_CFG - default MFPR value with alternate function + * MFP_CFG_DRV - default MFPR value with alternate function and + * pin drive strength + * MFP_CFG_LPM - default MFPR value with alternate function and + * low power mode + * MFP_CFG_X - default MFPR value with alternate function, + * pin drive strength and low power mode + * + * use + * + * MFP_CFG_PIN - to get the MFP pin index + * MFP_CFG_VAL - to get the corresponding MFPR value + */ + +typedef uint32_t mfp_cfg_t; + +#define MFP_CFG_PIN(mfp_cfg) (((mfp_cfg) >> 16) & 0xffff) +#define MFP_CFG_VAL(mfp_cfg) ((mfp_cfg) & 0xffff) + +#define MFPR_DEFAULT (0x0000) + +#define MFP_CFG(pin, af) \ + ((MFP_PIN_##pin << 16) | MFPR_DEFAULT | (MFP_##af)) + +#define MFP_CFG_DRV(pin, af, drv) \ + ((MFP_PIN_##pin << 16) | MFPR_DEFAULT |\ + ((MFP_##drv) << 10) | (MFP_##af)) + +#define MFP_CFG_LPM(pin, af, lpm) \ + ((MFP_PIN_##pin << 16) | MFPR_DEFAULT | (MFP_##af) |\ + (((MFP_LPM_##lpm) & 0x3) << 7) |\ + (((MFP_LPM_##lpm) & 0x4) << 12) |\ + (((MFP_LPM_##lpm) & 0x8) << 10)) + +#define MFP_CFG_X(pin, af, drv, lpm) \ + ((MFP_PIN_##pin << 16) | MFPR_DEFAULT |\ + ((MFP_##drv) << 10) | (MFP_##af) |\ + (((MFP_LPM_##lpm) & 0x3) << 7) |\ + (((MFP_LPM_##lpm) & 0x4) << 12) |\ + (((MFP_LPM_##lpm) & 0x8) << 10)) + +/* common MFP configurations - processor specific ones defined + * in mfp-pxa3xx.h + */ +#define GPIO0_GPIO MFP_CFG(GPIO0, AF0) +#define GPIO1_GPIO MFP_CFG(GPIO1, AF0) +#define GPIO2_GPIO MFP_CFG(GPIO2, AF0) +#define GPIO3_GPIO MFP_CFG(GPIO3, AF0) +#define GPIO4_GPIO MFP_CFG(GPIO4, AF0) +#define GPIO5_GPIO MFP_CFG(GPIO5, AF0) +#define GPIO6_GPIO MFP_CFG(GPIO6, AF0) +#define GPIO7_GPIO MFP_CFG(GPIO7, AF0) +#define GPIO8_GPIO MFP_CFG(GPIO8, AF0) +#define GPIO9_GPIO MFP_CFG(GPIO9, AF0) +#define GPIO10_GPIO MFP_CFG(GPIO10, AF0) +#define GPIO11_GPIO MFP_CFG(GPIO11, AF0) +#define GPIO12_GPIO MFP_CFG(GPIO12, AF0) +#define GPIO13_GPIO MFP_CFG(GPIO13, AF0) +#define GPIO14_GPIO MFP_CFG(GPIO14, AF0) +#define GPIO15_GPIO MFP_CFG(GPIO15, AF0) +#define GPIO16_GPIO MFP_CFG(GPIO16, AF0) +#define GPIO17_GPIO MFP_CFG(GPIO17, AF0) +#define GPIO18_GPIO MFP_CFG(GPIO18, AF0) +#define GPIO19_GPIO MFP_CFG(GPIO19, AF0) +#define GPIO20_GPIO MFP_CFG(GPIO20, AF0) +#define GPIO21_GPIO MFP_CFG(GPIO21, AF0) +#define GPIO22_GPIO MFP_CFG(GPIO22, AF0) +#define GPIO23_GPIO MFP_CFG(GPIO23, AF0) +#define GPIO24_GPIO MFP_CFG(GPIO24, AF0) +#define GPIO25_GPIO MFP_CFG(GPIO25, AF0) +#define GPIO26_GPIO MFP_CFG(GPIO26, AF0) +#define GPIO27_GPIO MFP_CFG(GPIO27, AF0) +#define GPIO28_GPIO MFP_CFG(GPIO28, AF0) +#define GPIO29_GPIO MFP_CFG(GPIO29, AF0) +#define GPIO30_GPIO MFP_CFG(GPIO30, AF0) +#define GPIO31_GPIO MFP_CFG(GPIO31, AF0) +#define GPIO32_GPIO MFP_CFG(GPIO32, AF0) +#define GPIO33_GPIO MFP_CFG(GPIO33, AF0) +#define GPIO34_GPIO MFP_CFG(GPIO34, AF0) +#define GPIO35_GPIO MFP_CFG(GPIO35, AF0) +#define GPIO36_GPIO MFP_CFG(GPIO36, AF0) +#define GPIO37_GPIO MFP_CFG(GPIO37, AF0) +#define GPIO38_GPIO MFP_CFG(GPIO38, AF0) +#define GPIO39_GPIO MFP_CFG(GPIO39, AF0) +#define GPIO40_GPIO MFP_CFG(GPIO40, AF0) +#define GPIO41_GPIO MFP_CFG(GPIO41, AF0) +#define GPIO42_GPIO MFP_CFG(GPIO42, AF0) +#define GPIO43_GPIO MFP_CFG(GPIO43, AF0) +#define GPIO44_GPIO MFP_CFG(GPIO44, AF0) +#define GPIO45_GPIO MFP_CFG(GPIO45, AF0) + +#define GPIO47_GPIO MFP_CFG(GPIO47, AF0) +#define GPIO48_GPIO MFP_CFG(GPIO48, AF0) + +#define GPIO53_GPIO MFP_CFG(GPIO53, AF0) +#define GPIO54_GPIO MFP_CFG(GPIO54, AF0) +#define GPIO55_GPIO MFP_CFG(GPIO55, AF0) + +#define GPIO57_GPIO MFP_CFG(GPIO57, AF0) + +#define GPIO63_GPIO MFP_CFG(GPIO63, AF0) +#define GPIO64_GPIO MFP_CFG(GPIO64, AF0) +#define GPIO65_GPIO MFP_CFG(GPIO65, AF0) +#define GPIO66_GPIO MFP_CFG(GPIO66, AF0) +#define GPIO67_GPIO MFP_CFG(GPIO67, AF0) +#define GPIO68_GPIO MFP_CFG(GPIO68, AF0) +#define GPIO69_GPIO MFP_CFG(GPIO69, AF0) +#define GPIO70_GPIO MFP_CFG(GPIO70, AF0) +#define GPIO71_GPIO MFP_CFG(GPIO71, AF0) +#define GPIO72_GPIO MFP_CFG(GPIO72, AF0) +#define GPIO73_GPIO MFP_CFG(GPIO73, AF0) +#define GPIO74_GPIO MFP_CFG(GPIO74, AF0) +#define GPIO75_GPIO MFP_CFG(GPIO75, AF0) +#define GPIO76_GPIO MFP_CFG(GPIO76, AF0) +#define GPIO77_GPIO MFP_CFG(GPIO77, AF0) +#define GPIO78_GPIO MFP_CFG(GPIO78, AF0) +#define GPIO79_GPIO MFP_CFG(GPIO79, AF0) +#define GPIO80_GPIO MFP_CFG(GPIO80, AF0) +#define GPIO81_GPIO MFP_CFG(GPIO81, AF0) +#define GPIO82_GPIO MFP_CFG(GPIO82, AF0) +#define GPIO83_GPIO MFP_CFG(GPIO83, AF0) +#define GPIO84_GPIO MFP_CFG(GPIO84, AF0) +#define GPIO85_GPIO MFP_CFG(GPIO85, AF0) +#define GPIO86_GPIO MFP_CFG(GPIO86, AF0) +#define GPIO87_GPIO MFP_CFG(GPIO87, AF0) +#define GPIO88_GPIO MFP_CFG(GPIO88, AF0) +#define GPIO89_GPIO MFP_CFG(GPIO89, AF0) +#define GPIO90_GPIO MFP_CFG(GPIO90, AF0) +#define GPIO91_GPIO MFP_CFG(GPIO91, AF0) +#define GPIO92_GPIO MFP_CFG(GPIO92, AF0) +#define GPIO93_GPIO MFP_CFG(GPIO93, AF0) +#define GPIO94_GPIO MFP_CFG(GPIO94, AF0) +#define GPIO95_GPIO MFP_CFG(GPIO95, AF0) +#define GPIO96_GPIO MFP_CFG(GPIO96, AF0) +#define GPIO97_GPIO MFP_CFG(GPIO97, AF0) +#define GPIO98_GPIO MFP_CFG(GPIO98, AF0) +#define GPIO99_GPIO MFP_CFG(GPIO99, AF0) +#define GPIO100_GPIO MFP_CFG(GPIO100, AF0) +#define GPIO101_GPIO MFP_CFG(GPIO101, AF0) +#define GPIO102_GPIO MFP_CFG(GPIO102, AF0) +#define GPIO103_GPIO MFP_CFG(GPIO103, AF0) +#define GPIO104_GPIO MFP_CFG(GPIO104, AF0) +#define GPIO105_GPIO MFP_CFG(GPIO105, AF0) +#define GPIO106_GPIO MFP_CFG(GPIO106, AF0) +#define GPIO107_GPIO MFP_CFG(GPIO107, AF0) +#define GPIO108_GPIO MFP_CFG(GPIO108, AF0) +#define GPIO109_GPIO MFP_CFG(GPIO109, AF0) +#define GPIO110_GPIO MFP_CFG(GPIO110, AF0) +#define GPIO111_GPIO MFP_CFG(GPIO111, AF0) +#define GPIO112_GPIO MFP_CFG(GPIO112, AF0) +#define GPIO113_GPIO MFP_CFG(GPIO113, AF0) +#define GPIO114_GPIO MFP_CFG(GPIO114, AF0) +#define GPIO115_GPIO MFP_CFG(GPIO115, AF0) +#define GPIO116_GPIO MFP_CFG(GPIO116, AF0) +#define GPIO117_GPIO MFP_CFG(GPIO117, AF0) +#define GPIO118_GPIO MFP_CFG(GPIO118, AF0) +#define GPIO119_GPIO MFP_CFG(GPIO119, AF0) +#define GPIO120_GPIO MFP_CFG(GPIO120, AF0) +#define GPIO121_GPIO MFP_CFG(GPIO121, AF0) +#define GPIO122_GPIO MFP_CFG(GPIO122, AF0) +#define GPIO123_GPIO MFP_CFG(GPIO123, AF0) +#define GPIO124_GPIO MFP_CFG(GPIO124, AF0) +#define GPIO125_GPIO MFP_CFG(GPIO125, AF0) +#define GPIO126_GPIO MFP_CFG(GPIO126, AF0) +#define GPIO127_GPIO MFP_CFG(GPIO127, AF0) + +#define GPIO0_2_GPIO MFP_CFG(GPIO0_2, AF0) +#define GPIO1_2_GPIO MFP_CFG(GPIO1_2, AF0) +#define GPIO2_2_GPIO MFP_CFG(GPIO2_2, AF0) +#define GPIO3_2_GPIO MFP_CFG(GPIO3_2, AF0) +#define GPIO4_2_GPIO MFP_CFG(GPIO4_2, AF0) +#define GPIO5_2_GPIO MFP_CFG(GPIO5_2, AF0) +#define GPIO6_2_GPIO MFP_CFG(GPIO6_2, AF0) + +/* + * each MFP pin will have a MFPR register, since the offset of the + * register varies between processors, the processor specific code + * should initialize the pin offsets by pxa3xx_mfp_init_addr() + * + * pxa3xx_mfp_init_addr - accepts a table of "pxa3xx_mfp_addr_map" + * structure, which represents a range of MFP pins from "start" to + * "end", with the offset begining at "offset", to define a single + * pin, let "end" = -1 + * + * use + * + * MFP_ADDR_X() to define a range of pins + * MFP_ADDR() to define a single pin + * MFP_ADDR_END to signal the end of pin offset definitions + */ +struct pxa3xx_mfp_addr_map { + unsigned int start; + unsigned int end; + unsigned long offset; +}; + +#define MFP_ADDR_X(start, end, offset) \ + { MFP_PIN_##start, MFP_PIN_##end, offset } + +#define MFP_ADDR(pin, offset) \ + { MFP_PIN_##pin, -1, offset } + +#define MFP_ADDR_END { MFP_PIN_INVALID, 0 } + +struct pxa3xx_mfp_pin { + unsigned long mfpr_off; /* MFPRxx register offset */ + unsigned long mfpr_val; /* MFPRxx register value */ +}; + +/* + * pxa3xx_mfp_read()/pxa3xx_mfp_write() - for direct read/write access + * to the MFPR register + */ +unsigned long pxa3xx_mfp_read(int mfp); +void pxa3xx_mfp_write(int mfp, unsigned long mfpr_val); + +/* + * pxa3xx_mfp_set_afds - set MFP alternate function and drive strength + * pxa3xx_mfp_set_rdh - set MFP release delay hold on/off + * pxa3xx_mfp_set_lpm - set MFP low power mode state + * pxa3xx_mfp_set_edge - set MFP edge detection in low power mode + * + * use these functions to override/change the default configuration + * done by pxa3xx_mfp_set_config(s) + */ +void pxa3xx_mfp_set_afds(int mfp, int af, int ds); +void pxa3xx_mfp_set_rdh(int mfp, int rdh); +void pxa3xx_mfp_set_lpm(int mfp, int lpm); +void pxa3xx_mfp_set_edge(int mfp, int edge); + +/* + * pxa3xx_mfp_config - configure the MFPR registers + * + * used by board specific initialization code + */ +void pxa3xx_mfp_config(mfp_cfg_t *mfp_cfgs, int num); + +/* + * pxa3xx_mfp_init_addr() - initialize the mapping between mfp pin + * index and MFPR register offset + * + * used by processor specific code + */ +void __init pxa3xx_mfp_init_addr(struct pxa3xx_mfp_addr_map *); +void __init pxa3xx_init_mfp(void); + +#endif /* __ASM_ARCH_MFP_H */ diff --git a/include/asm-arm/arch-pxa/pxa-regs.h b/include/asm-arm/arch-pxa/pxa-regs.h index e68b593..67f53e0 100644 --- a/include/asm-arm/arch-pxa/pxa-regs.h +++ b/include/asm-arm/arch-pxa/pxa-regs.h @@ -1177,7 +1177,7 @@ #define GPIO_bit(x) (1 << ((x) & 0x1f)) -#ifdef CONFIG_PXA27x +#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx) /* Interrupt Controller */ diff --git a/include/asm-arm/arch-pxa/pxa3xx-regs.h b/include/asm-arm/arch-pxa/pxa3xx-regs.h new file mode 100644 index 0000000..3900a0c --- /dev/null +++ b/include/asm-arm/arch-pxa/pxa3xx-regs.h @@ -0,0 +1,75 @@ +/* + * linux/include/asm-arm/arch-pxa/pxa3xx-regs.h + * + * PXA3xx specific register definitions + * + * Copyright (C) 2007 Marvell International Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_ARCH_PXA3XX_REGS_H +#define __ASM_ARCH_PXA3XX_REGS_H + +/* + * Application Subsystem Clock + */ +#define ACCR __REG(0x41340000) /* Application Subsystem Clock Configuration Register */ +#define ACSR __REG(0x41340004) /* Application Subsystem Clock Status Register */ +#define AICSR __REG(0x41340008) /* Application Subsystem Interrupt Control/Status Register */ +#define CKENA __REG(0x4134000C) /* A Clock Enable Register */ +#define CKENB __REG(0x41340010) /* B Clock Enable Register */ +#define AC97_DIV __REG(0x41340014) /* AC97 clock divisor value register */ + +/* + * Clock Enable Bit + */ +#define CKEN_LCD 1 /* < LCD Clock Enable */ +#define CKEN_USBH 2 /* < USB host clock enable */ +#define CKEN_CAMERA 3 /* < Camera interface clock enable */ +#define CKEN_NAND 4 /* < NAND Flash Controller Clock Enable */ +#define CKEN_USB2 6 /* < USB 2.0 client clock enable. */ +#define CKEN_DMC 8 /* < Dynamic Memory Controller clock enable */ +#define CKEN_SMC 9 /* < Static Memory Controller clock enable */ +#define CKEN_ISC 10 /* < Internal SRAM Controller clock enable */ +#define CKEN_BOOT 11 /* < Boot rom clock enable */ +#define CKEN_MMC1 12 /* < MMC1 Clock enable */ +#define CKEN_MMC2 13 /* < MMC2 clock enable */ +#define CKEN_KEYPAD 14 /* < Keypand Controller Clock Enable */ +#define CKEN_CIR 15 /* < Consumer IR Clock Enable */ +#define CKEN_USIM0 17 /* < USIM[0] Clock Enable */ +#define CKEN_USIM1 18 /* < USIM[1] Clock Enable */ +#define CKEN_TPM 19 /* < TPM clock enable */ +#define CKEN_UDC 20 /* < UDC clock enable */ +#define CKEN_BTUART 21 /* < BTUART clock enable */ +#define CKEN_FFUART 22 /* < FFUART clock enable */ +#define CKEN_STUART 23 /* < STUART clock enable */ +#define CKEN_AC97 24 /* < AC97 clock enable */ +#define CKEN_TOUCH 25 /* < Touch screen Interface Clock Enable */ +#define CKEN_SSP1 26 /* < SSP1 clock enable */ +#define CKEN_SSP2 27 /* < SSP2 clock enable */ +#define CKEN_SSP3 28 /* < SSP3 clock enable */ +#define CKEN_SSP4 29 /* < SSP4 clock enable */ +#define CKEN_MSL0 30 /* < MSL0 clock enable */ +#define CKEN_PWM0 32 /* < PWM[0] clock enable */ +#define CKEN_PWM1 33 /* < PWM[1] clock enable */ +#define CKEN_I2C 36 /* < I2C clock enable */ +#define CKEN_INTC 38 /* < Interrupt controller clock enable */ +#define CKEN_GPIO 39 /* < GPIO clock enable */ +#define CKEN_1WIRE 40 /* < 1-wire clock enable */ +#define CKEN_HSIO2 41 /* < HSIO2 clock enable */ +#define CKEN_MINI_IM 48 /* < Mini-IM */ +#define CKEN_MINI_LCD 49 /* < Mini LCD */ + +#if defined(CONFIG_CPU_PXA310) +#define CKEN_MMC3 5 /* < MMC3 Clock Enable */ +#define CKEN_MVED 43 /* < MVED clock enable */ +#endif + +/* Note: GCU clock enable bit differs on PXA300/PXA310 and PXA320 */ +#define PXA300_CKEN_GRAPHICS 42 /* Graphics controller clock enable */ +#define PXA320_CKEN_GRAPHICS 7 /* Graphics controller clock enable */ + +#endif /* __ASM_ARCH_PXA3XX_REGS_H */ diff --git a/include/asm-arm/arch-pxa/timex.h b/include/asm-arm/arch-pxa/timex.h index 2473bb5..8d882f0 100644 --- a/include/asm-arm/arch-pxa/timex.h +++ b/include/asm-arm/arch-pxa/timex.h @@ -21,4 +21,6 @@ #else #define CLOCK_TICK_RATE 3250000 #endif +#else +#define CLOCK_TICK_RATE 3250000 #endif diff --git a/include/asm-arm/arch-pxa/zylonite.h b/include/asm-arm/arch-pxa/zylonite.h new file mode 100644 index 0000000..f58b591 --- /dev/null +++ b/include/asm-arm/arch-pxa/zylonite.h @@ -0,0 +1,35 @@ +#ifndef __ASM_ARCH_ZYLONITE_H +#define __ASM_ARCH_ZYLONITE_H + +#define ZYLONITE_ETH_PHYS 0x14000000 + +/* the following variables are processor specific and initialized + * by the corresponding zylonite_pxa3xx_init() + */ +extern int gpio_backlight; +extern int gpio_eth_irq; + +extern int lcd_id; +extern int lcd_orientation; + +#ifdef CONFIG_CPU_PXA300 +extern void zylonite_pxa300_init(void); +#else +static inline void zylonite_pxa300_init(void) +{ + if (cpu_is_pxa300() || cpu_is_pxa310()) + panic("%s: PXA300/PXA310 not supported\n", __FUNCTION__); +} +#endif + +#ifdef CONFIG_CPU_PXA320 +extern void zylonite_pxa320_init(void); +#else +static inline void zylonite_pxa320_init(void) +{ + if (cpu_is_pxa320()) + panic("%s: PXA320 not supported\n", __FUNCTION__); +} +#endif + +#endif /* __ASM_ARCH_ZYLONITE_H */ -- cgit v0.10.2 From 36d8b17b4364915615aff312ba20a1b90e22b963 Mon Sep 17 00:00:00 2001 From: Russell King Date: Mon, 1 Oct 2007 16:22:24 +0100 Subject: [ARM] pxa: Make cpu_is_pxaXXX dependent on configuration symbols Make the cpu_is_pxaXXX() macros define to zero when support for a particular CPU is disabled. This allows us to eliminate code for CPUs which aren't enabled. Signed-off-by: Russell King diff --git a/include/asm-arm/arch-pxa/hardware.h b/include/asm-arm/arch-pxa/hardware.h index fc20d72..89df077 100644 --- a/include/asm-arm/arch-pxa/hardware.h +++ b/include/asm-arm/arch-pxa/hardware.h @@ -62,6 +62,7 @@ #ifndef __ASSEMBLY__ +#ifdef CONFIG_PXA25x #define __cpu_is_pxa21x(id) \ ({ \ unsigned int _id = (id) >> 4 & 0xf3f; \ @@ -73,30 +74,50 @@ unsigned int _id = (id) >> 4 & 0xfff; \ _id == 0x2d0 || _id == 0x290; \ }) +#else +#define __cpu_is_pxa21x(id) (0) +#define __cpu_is_pxa25x(id) (0) +#endif +#ifdef CONFIG_PXA27x #define __cpu_is_pxa27x(id) \ ({ \ unsigned int _id = (id) >> 4 & 0xfff; \ _id == 0x411; \ }) +#else +#define __cpu_is_pxa27x(id) (0) +#endif +#ifdef CONFIG_CPU_PXA300 #define __cpu_is_pxa300(id) \ ({ \ unsigned int _id = (id) >> 4 & 0xfff; \ _id == 0x688; \ }) +#else +#define __cpu_is_pxa300(id) (0) +#endif +#ifdef CONFIG_CPU_PXA310 #define __cpu_is_pxa310(id) \ ({ \ unsigned int _id = (id) >> 4 & 0xfff; \ _id == 0x689; \ }) +#else +#define __cpu_is_pxa310(id) (0) +#endif +#ifdef CONFIG_CPU_PXA320 #define __cpu_is_pxa320(id) \ ({ \ unsigned int _id = (id) >> 4 & 0xfff; \ _id == 0x603 || _id == 0x682; \ }) +#else +#define __cpu_is_pxa320(id) (0) +#endif #define cpu_is_pxa21x() \ ({ \ -- cgit v0.10.2 From 693d9d95d6392074d63755b0df67865c63828fa4 Mon Sep 17 00:00:00 2001 From: Russell King Date: Tue, 2 Oct 2007 11:28:26 +0100 Subject: [ARM] pxa: move pxa_set_mode() from pxa2xx_lubbock.c to lubbock.c Signed-off-by: Russell King diff --git a/arch/arm/mach-pxa/lubbock.c b/arch/arm/mach-pxa/lubbock.c index e70048f..011a1a7 100644 --- a/arch/arm/mach-pxa/lubbock.c +++ b/arch/arm/mach-pxa/lubbock.c @@ -512,6 +512,25 @@ static void __init lubbock_map_io(void) pxa_gpio_mode(GPIO44_BTCTS_MD); pxa_gpio_mode(GPIO45_BTRTS_MD); + GPSR(GPIO48_nPOE) = + GPIO_bit(GPIO48_nPOE) | + GPIO_bit(GPIO49_nPWE) | + GPIO_bit(GPIO50_nPIOR) | + GPIO_bit(GPIO51_nPIOW) | + GPIO_bit(GPIO52_nPCE_1) | + GPIO_bit(GPIO53_nPCE_2); + + pxa_gpio_mode(GPIO48_nPOE_MD); + pxa_gpio_mode(GPIO49_nPWE_MD); + pxa_gpio_mode(GPIO50_nPIOR_MD); + pxa_gpio_mode(GPIO51_nPIOW_MD); + pxa_gpio_mode(GPIO52_nPCE_1_MD); + pxa_gpio_mode(GPIO53_nPCE_2_MD); + pxa_gpio_mode(GPIO54_pSKTSEL_MD); + pxa_gpio_mode(GPIO55_nPREG_MD); + pxa_gpio_mode(GPIO56_nPWAIT_MD); + pxa_gpio_mode(GPIO57_nIOIS16_MD); + /* This is for the SMC chip select */ pxa_gpio_mode(GPIO79_nCS_3_MD); diff --git a/drivers/pcmcia/pxa2xx_lubbock.c b/drivers/pcmcia/pxa2xx_lubbock.c index 5e9b9a3..1510d6c 100644 --- a/drivers/pcmcia/pxa2xx_lubbock.c +++ b/drivers/pcmcia/pxa2xx_lubbock.c @@ -30,35 +30,6 @@ #include "sa1111_generic.h" static int -lubbock_pcmcia_hw_init(struct soc_pcmcia_socket *skt) -{ - /* - * Setup default state of GPIO outputs - * before we enable them as outputs. - */ - GPSR(GPIO48_nPOE) = - GPIO_bit(GPIO48_nPOE) | - GPIO_bit(GPIO49_nPWE) | - GPIO_bit(GPIO50_nPIOR) | - GPIO_bit(GPIO51_nPIOW) | - GPIO_bit(GPIO52_nPCE_1) | - GPIO_bit(GPIO53_nPCE_2); - - pxa_gpio_mode(GPIO48_nPOE_MD); - pxa_gpio_mode(GPIO49_nPWE_MD); - pxa_gpio_mode(GPIO50_nPIOR_MD); - pxa_gpio_mode(GPIO51_nPIOW_MD); - pxa_gpio_mode(GPIO52_nPCE_1_MD); - pxa_gpio_mode(GPIO53_nPCE_2_MD); - pxa_gpio_mode(GPIO54_pSKTSEL_MD); - pxa_gpio_mode(GPIO55_nPREG_MD); - pxa_gpio_mode(GPIO56_nPWAIT_MD); - pxa_gpio_mode(GPIO57_nIOIS16_MD); - - return sa1111_pcmcia_hw_init(skt); -} - -static int lubbock_pcmcia_configure_socket(struct soc_pcmcia_socket *skt, const socket_state_t *state) { @@ -230,7 +201,7 @@ lubbock_pcmcia_configure_socket(struct soc_pcmcia_socket *skt, static struct pcmcia_low_level lubbock_pcmcia_ops = { .owner = THIS_MODULE, - .hw_init = lubbock_pcmcia_hw_init, + .hw_init = sa1111_pcmcia_hw_init, .hw_shutdown = sa1111_pcmcia_hw_shutdown, .socket_state = sa1111_pcmcia_socket_state, .configure_socket = lubbock_pcmcia_configure_socket, -- cgit v0.10.2 From 39cbd4896e39e2b93c33635a9abc1a4405827e14 Mon Sep 17 00:00:00 2001 From: Russell King Date: Tue, 2 Oct 2007 11:29:02 +0100 Subject: [ARM] pxa: move pxa_set_mode() from pxa2xx_mainstone.c to mainstone.c Signed-off-by: Russell King diff --git a/arch/arm/mach-pxa/mainstone.c b/arch/arm/mach-pxa/mainstone.c index b02c79c..a4bc348 100644 --- a/arch/arm/mach-pxa/mainstone.c +++ b/arch/arm/mach-pxa/mainstone.c @@ -444,6 +444,25 @@ static void __init mainstone_init(void) */ pxa_gpio_mode(GPIO45_SYSCLK_AC97_MD); + GPSR(GPIO48_nPOE) = + GPIO_bit(GPIO48_nPOE) | + GPIO_bit(GPIO49_nPWE) | + GPIO_bit(GPIO50_nPIOR) | + GPIO_bit(GPIO51_nPIOW) | + GPIO_bit(GPIO85_nPCE_1) | + GPIO_bit(GPIO54_nPCE_2); + + pxa_gpio_mode(GPIO48_nPOE_MD); + pxa_gpio_mode(GPIO49_nPWE_MD); + pxa_gpio_mode(GPIO50_nPIOR_MD); + pxa_gpio_mode(GPIO51_nPIOW_MD); + pxa_gpio_mode(GPIO85_nPCE_1_MD); + pxa_gpio_mode(GPIO54_nPCE_2_MD); + pxa_gpio_mode(GPIO79_pSKTSEL_MD); + pxa_gpio_mode(GPIO55_nPREG_MD); + pxa_gpio_mode(GPIO56_nPWAIT_MD); + pxa_gpio_mode(GPIO57_nIOIS16_MD); + platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); /* reading Mainstone's "Virtual Configuration Register" diff --git a/drivers/pcmcia/pxa2xx_mainstone.c b/drivers/pcmcia/pxa2xx_mainstone.c index 383107b..36c671c 100644 --- a/drivers/pcmcia/pxa2xx_mainstone.c +++ b/drivers/pcmcia/pxa2xx_mainstone.c @@ -43,24 +43,6 @@ static int mst_pcmcia_hw_init(struct soc_pcmcia_socket *skt) * Setup default state of GPIO outputs * before we enable them as outputs. */ - GPSR(GPIO48_nPOE) = - GPIO_bit(GPIO48_nPOE) | - GPIO_bit(GPIO49_nPWE) | - GPIO_bit(GPIO50_nPIOR) | - GPIO_bit(GPIO51_nPIOW) | - GPIO_bit(GPIO85_nPCE_1) | - GPIO_bit(GPIO54_nPCE_2); - - pxa_gpio_mode(GPIO48_nPOE_MD); - pxa_gpio_mode(GPIO49_nPWE_MD); - pxa_gpio_mode(GPIO50_nPIOR_MD); - pxa_gpio_mode(GPIO51_nPIOW_MD); - pxa_gpio_mode(GPIO85_nPCE_1_MD); - pxa_gpio_mode(GPIO54_nPCE_2_MD); - pxa_gpio_mode(GPIO79_pSKTSEL_MD); - pxa_gpio_mode(GPIO55_nPREG_MD); - pxa_gpio_mode(GPIO56_nPWAIT_MD); - pxa_gpio_mode(GPIO57_nIOIS16_MD); skt->irq = (skt->nr == 0) ? MAINSTONE_S0_IRQ : MAINSTONE_S1_IRQ; return soc_pcmcia_request_irqs(skt, irqs, ARRAY_SIZE(irqs)); -- cgit v0.10.2 From 3e0cc7ee045fb53e8215fed7442455c0cee0ee93 Mon Sep 17 00:00:00 2001 From: Russell King Date: Tue, 2 Oct 2007 14:28:01 +0100 Subject: [ARM] pxa: Avoid pxa_gpio_mode() in gpio_direction_{in,out}put() pxa_gpio_mode() is a universal call that fiddles with the GAFR (gpio alternate function register.) GAFR does not exist on PXA3 CPUs, but instead the alternate functions are controlled via the MFP support code. Platforms are expected to configure the MFP according to their needs in their platform support code rather than drivers. We extend this idea to the GAFR, and make the gpio_direction_*() functions purely operate on the GPIO level. This means platform support code is entirely responsible for configuring the GPIOs alternate functions on all PXA CPU types. Signed-off-by: Russell King diff --git a/arch/arm/mach-pxa/generic.c b/arch/arm/mach-pxa/generic.c index 2263a84..1c34946 100644 --- a/arch/arm/mach-pxa/generic.c +++ b/arch/arm/mach-pxa/generic.c @@ -105,6 +105,44 @@ int pxa_gpio_mode(int gpio_mode) EXPORT_SYMBOL(pxa_gpio_mode); +int gpio_direction_input(unsigned gpio) +{ + unsigned long flags; + u32 mask; + + if (gpio > pxa_last_gpio) + return -EINVAL; + + mask = GPIO_bit(gpio); + local_irq_save(flags); + GPDR(gpio) &= ~mask; + local_irq_restore(flags); + + return 0; +} +EXPORT_SYMBOL(gpio_direction_input); + +int gpio_direction_output(unsigned gpio, int value) +{ + unsigned long flags; + u32 mask; + + if (gpio > pxa_last_gpio) + return -EINVAL; + + mask = GPIO_bit(gpio); + local_irq_save(flags); + if (value) + GPSR(gpio) = mask; + else + GPCR(gpio) = mask; + GPDR(gpio) |= mask; + local_irq_restore(flags); + + return 0; +} +EXPORT_SYMBOL(gpio_direction_output); + /* * Return GPIO level */ diff --git a/include/asm-arm/arch-pxa/gpio.h b/include/asm-arm/arch-pxa/gpio.h index 9e99241..9dbc2dc 100644 --- a/include/asm-arm/arch-pxa/gpio.h +++ b/include/asm-arm/arch-pxa/gpio.h @@ -38,16 +38,8 @@ static inline void gpio_free(unsigned gpio) return; } -static inline int gpio_direction_input(unsigned gpio) -{ - return pxa_gpio_mode(gpio | GPIO_IN); -} - -static inline int gpio_direction_output(unsigned gpio, int value) -{ - return pxa_gpio_mode(gpio | GPIO_OUT | - (value ? GPIO_DFLT_HIGH : GPIO_DFLT_LOW)); -} +extern int gpio_direction_input(unsigned gpio); +extern int gpio_direction_output(unsigned gpio, int value); static inline int __gpio_get_value(unsigned gpio) { -- cgit v0.10.2 From 3696a8a426f8caebd97463e9b5cf9f06c1c36759 Mon Sep 17 00:00:00 2001 From: Mike Rapoport Date: Sun, 23 Sep 2007 15:59:26 +0100 Subject: [ARM] 4576/1: CM-X270 machine support This patch provides core support for CM-X270 platform. Signed-off-by: Mike Rapoport Signed-off-by: Russell King diff --git a/arch/arm/configs/cm_x270_defconfig b/arch/arm/configs/cm_x270_defconfig new file mode 100644 index 0000000..5cab083 --- /dev/null +++ b/arch/arm/configs/cm_x270_defconfig @@ -0,0 +1,1410 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.22 +# Wed Jul 18 14:11:48 2007 +# +CONFIG_ARM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_GENERIC_GPIO=y +CONFIG_GENERIC_TIME=y +# CONFIG_GENERIC_CLOCKEVENTS is not set +CONFIG_MMU=y +# CONFIG_NO_IOPORT is not set +CONFIG_GENERIC_HARDIRQS=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_ZONE_DMA=y +CONFIG_ARCH_MTD_XIP=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" + +# +# Code maturity level options +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 + +# +# General setup +# +CONFIG_LOCALVERSION="" +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_POSIX_MQUEUE is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_USER_NS is not set +# CONFIG_AUDIT is not set +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=17 +CONFIG_SYSFS_DEPRECATED=y +# CONFIG_RELAY is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +CONFIG_EMBEDDED=y +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_ALL is not set +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_ANON_INODES=y +# CONFIG_EPOLL is not set +# CONFIG_SIGNALFD is not set +# CONFIG_TIMERFD is not set +# CONFIG_EVENTFD is not set +CONFIG_SHMEM=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_SLOB is not set +CONFIG_RT_MUTEXES=y +# CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_KMOD=y +CONFIG_BLOCK=y +# CONFIG_LBD is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_LSF is not set +# CONFIG_BLK_DEV_BSG is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +CONFIG_DEFAULT_AS=y +# CONFIG_DEFAULT_DEADLINE is not set +# CONFIG_DEFAULT_CFQ is not set +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="anticipatory" + +# +# System Type +# +# CONFIG_ARCH_AAEC2000 is not set +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_CLPS7500 is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_CO285 is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_IMX is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_PNX4008 is not set +CONFIG_ARCH_PXA=y +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP is not set +CONFIG_DMABOUNCE=y + +# +# Intel PXA2xx Implementations +# +# CONFIG_ARCH_LUBBOCK is not set +# CONFIG_MACH_LOGICPD_PXA270 is not set +# CONFIG_MACH_MAINSTONE is not set +# CONFIG_ARCH_PXA_IDP is not set +# CONFIG_PXA_SHARPSL is not set +# CONFIG_MACH_TRIZEPS4 is not set +CONFIG_MACH_ARMCORE=y +CONFIG_PXA27x=y + +# +# Processor Type +# +CONFIG_CPU_32=y +CONFIG_CPU_XSCALE=y +CONFIG_CPU_32v5=y +CONFIG_CPU_ABRT_EV5T=y +CONFIG_CPU_CACHE_VIVT=y +CONFIG_CPU_TLB_V4WBI=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +CONFIG_ARM_THUMB=y +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_OUTER_CACHE is not set +CONFIG_IWMMXT=y +CONFIG_XSCALE_PMU=y + +# +# Bus support +# +CONFIG_PCI=y +CONFIG_PCI_SYSCALL=y +CONFIG_PCI_HOST_ITE8152=y +# CONFIG_ARCH_SUPPORTS_MSI is not set +# CONFIG_PCI_DEBUG is not set + +# +# PCCARD (PCMCIA/CardBus) support +# +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +# CONFIG_TICK_ONESHOT is not set +# CONFIG_PREEMPT is not set +# CONFIG_NO_IDLE_HZ is not set +CONFIG_HZ=100 +# CONFIG_AEABI is not set +# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_SPARSEMEM_STATIC is not set +CONFIG_SPLIT_PTLOCK_CPUS=4096 +# CONFIG_RESOURCES_64BIT is not set +CONFIG_ZONE_DMA_FLAG=1 +CONFIG_BOUNCE=y +CONFIG_VIRT_TO_BUS=y +CONFIG_ALIGNMENT_TRAP=y + +# +# Boot options +# +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_CMDLINE="" +# CONFIG_XIP_KERNEL is not set +# CONFIG_KEXEC is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +CONFIG_FPE_NWFPE=y +# CONFIG_FPE_NWFPE_XP is not set +# CONFIG_FPE_FASTFPE is not set + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_BINFMT_AOUT is not set +# CONFIG_BINFMT_MISC is not set +# CONFIG_ARTHUR is not set + +# +# Power management options +# +CONFIG_PM=y +# CONFIG_PM_LEGACY is not set +# CONFIG_PM_DEBUG is not set +# CONFIG_PM_SYSFS_DEPRECATED is not set +# CONFIG_APM_EMULATION is not set + +# +# Networking +# +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +# CONFIG_PACKET_MMAP is not set +CONFIG_UNIX=y +CONFIG_XFRM=y +# CONFIG_XFRM_USER is not set +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_NET_KEY is not set +CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +# CONFIG_INET_TUNNEL is not set +CONFIG_INET_XFRM_MODE_TRANSPORT=y +CONFIG_INET_XFRM_MODE_TUNNEL=y +CONFIG_INET_XFRM_MODE_BEET=y +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +# CONFIG_IPV6 is not set +# CONFIG_INET6_XFRM_TUNNEL is not set +# CONFIG_INET6_TUNNEL is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set + +# +# QoS and/or fair queueing +# +# CONFIG_NET_SCHED is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set + +# +# Wireless +# +# CONFIG_CFG80211 is not set +CONFIG_WIRELESS_EXT=y +# CONFIG_MAC80211 is not set +CONFIG_IEEE80211=m +# CONFIG_IEEE80211_DEBUG is not set +CONFIG_IEEE80211_CRYPT_WEP=m +CONFIG_IEEE80211_CRYPT_CCMP=m +# CONFIG_IEEE80211_CRYPT_TKIP is not set +# CONFIG_IEEE80211_SOFTMAC is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_CONNECTOR is not set +CONFIG_MTD=m +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_CONCAT is not set +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_REDBOOT_PARTS is not set +# CONFIG_MTD_AFS_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=m +CONFIG_MTD_BLKDEVS=m +CONFIG_MTD_BLOCK=m +# CONFIG_MTD_BLOCK_RO is not set +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set + +# +# RAM/ROM/Flash chip drivers +# +# CONFIG_MTD_CFI is not set +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_SHARP_SL is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_PMC551 is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +CONFIG_MTD_NAND=m +# CONFIG_MTD_NAND_VERIFY_WRITE is not set +# CONFIG_MTD_NAND_ECC_SMC is not set +# CONFIG_MTD_NAND_MUSEUM_IDS is not set +# CONFIG_MTD_NAND_H1900 is not set +CONFIG_MTD_NAND_IDS=m +# CONFIG_MTD_NAND_DISKONCHIP is not set +# CONFIG_MTD_NAND_SHARPSL is not set +# CONFIG_MTD_NAND_CAFE is not set +CONFIG_MTD_NAND_CM_X270=m +# CONFIG_MTD_NAND_NANDSIM is not set +# CONFIG_MTD_NAND_PLATFORM is not set +# CONFIG_MTD_ONENAND is not set + +# +# UBI - Unsorted block images +# +# CONFIG_MTD_UBI is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_CPQ_DA is not set +# CONFIG_BLK_CPQ_CISS_DA is not set +# CONFIG_BLK_DEV_DAC960 is not set +# CONFIG_BLK_DEV_UMEM is not set +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=y +# CONFIG_BLK_DEV_CRYPTOLOOP is not set +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_SX8 is not set +# CONFIG_BLK_DEV_UB is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=12000 +CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024 +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +CONFIG_IDE=m +CONFIG_IDE_MAX_HWIFS=4 +CONFIG_BLK_DEV_IDE=m + +# +# Please see Documentation/ide.txt for help/info on IDE drives +# +# CONFIG_BLK_DEV_IDE_SATA is not set +CONFIG_BLK_DEV_IDEDISK=m +# CONFIG_IDEDISK_MULTI_MODE is not set +CONFIG_BLK_DEV_IDECD=m +# CONFIG_BLK_DEV_IDETAPE is not set +# CONFIG_BLK_DEV_IDEFLOPPY is not set +# CONFIG_BLK_DEV_IDESCSI is not set +# CONFIG_IDE_TASK_IOCTL is not set +CONFIG_IDE_PROC_FS=y + +# +# IDE chipset support/bugfixes +# +# CONFIG_IDE_GENERIC is not set +# CONFIG_BLK_DEV_IDEPCI is not set +# CONFIG_IDEPCI_PCIBUS_ORDER is not set +# CONFIG_IDE_ARM is not set +# CONFIG_BLK_DEV_IDEDMA is not set +# CONFIG_BLK_DEV_HD is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_TGT is not set +# CONFIG_SCSI_NETLINK is not set +# CONFIG_SCSI_PROC_FS is not set + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +# CONFIG_BLK_DEV_SR is not set +# CONFIG_CHR_DEV_SG is not set +# CONFIG_CHR_DEV_SCH is not set + +# +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs +# +# CONFIG_SCSI_MULTI_LUN is not set +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set +CONFIG_SCSI_WAIT_SCAN=m + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set + +# +# SCSI low-level drivers +# +# CONFIG_ISCSI_TCP is not set +# CONFIG_BLK_DEV_3W_XXXX_RAID is not set +# CONFIG_SCSI_3W_9XXX is not set +# CONFIG_SCSI_ACARD is not set +# CONFIG_SCSI_AACRAID is not set +# CONFIG_SCSI_AIC7XXX is not set +# CONFIG_SCSI_AIC7XXX_OLD is not set +# CONFIG_SCSI_AIC79XX is not set +# CONFIG_SCSI_AIC94XX is not set +# CONFIG_SCSI_DPT_I2O is not set +# CONFIG_SCSI_ARCMSR is not set +# CONFIG_MEGARAID_NEWGEN is not set +# CONFIG_MEGARAID_LEGACY is not set +# CONFIG_MEGARAID_SAS is not set +# CONFIG_SCSI_HPTIOP is not set +# CONFIG_SCSI_DMX3191D is not set +# CONFIG_SCSI_FUTURE_DOMAIN is not set +# CONFIG_SCSI_IPS is not set +# CONFIG_SCSI_INITIO is not set +# CONFIG_SCSI_INIA100 is not set +# CONFIG_SCSI_STEX is not set +# CONFIG_SCSI_SYM53C8XX_2 is not set +# CONFIG_SCSI_QLOGIC_1280 is not set +# CONFIG_SCSI_QLA_FC is not set +# CONFIG_SCSI_QLA_ISCSI is not set +# CONFIG_SCSI_LPFC is not set +# CONFIG_SCSI_DC395x is not set +# CONFIG_SCSI_DC390T is not set +# CONFIG_SCSI_NSP32 is not set +# CONFIG_SCSI_DEBUG is not set +# CONFIG_SCSI_SRP is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set + +# +# Fusion MPT device support +# +# CONFIG_FUSION is not set +# CONFIG_FUSION_SPI is not set +# CONFIG_FUSION_FC is not set +# CONFIG_FUSION_SAS is not set + +# +# IEEE 1394 (FireWire) support +# +# CONFIG_FIREWIRE is not set +# CONFIG_IEEE1394 is not set +# CONFIG_I2O is not set +CONFIG_NETDEVICES=y +# CONFIG_NETDEVICES_MULTIQUEUE is not set +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_MACVLAN is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_ARCNET is not set +# CONFIG_PHYLIB is not set +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +# CONFIG_AX88796 is not set +# CONFIG_HAPPYMEAL is not set +# CONFIG_SUNGEM is not set +# CONFIG_CASSINI is not set +# CONFIG_NET_VENDOR_3COM is not set +# CONFIG_SMC91X is not set +CONFIG_DM9000=y +# CONFIG_SMC911X is not set +# CONFIG_NET_TULIP is not set +# CONFIG_HP100 is not set +CONFIG_NET_PCI=y +# CONFIG_PCNET32 is not set +# CONFIG_AMD8111_ETH is not set +# CONFIG_ADAPTEC_STARFIRE is not set +# CONFIG_B44 is not set +# CONFIG_FORCEDETH is not set +# CONFIG_DGRS is not set +# CONFIG_EEPRO100 is not set +# CONFIG_E100 is not set +# CONFIG_FEALNX is not set +# CONFIG_NATSEMI is not set +# CONFIG_NE2K_PCI is not set +# CONFIG_8139CP is not set +CONFIG_8139TOO=m +# CONFIG_8139TOO_PIO is not set +# CONFIG_8139TOO_TUNE_TWISTER is not set +# CONFIG_8139TOO_8129 is not set +# CONFIG_8139_OLD_RX_RESET is not set +# CONFIG_SIS900 is not set +# CONFIG_EPIC100 is not set +# CONFIG_SUNDANCE is not set +# CONFIG_TLAN is not set +# CONFIG_VIA_RHINE is not set +# CONFIG_SC92031 is not set +CONFIG_NETDEV_1000=y +# CONFIG_ACENIC is not set +# CONFIG_DL2K is not set +# CONFIG_E1000 is not set +# CONFIG_NS83820 is not set +# CONFIG_HAMACHI is not set +# CONFIG_YELLOWFIN is not set +# CONFIG_R8169 is not set +# CONFIG_SIS190 is not set +# CONFIG_SKGE is not set +# CONFIG_SKY2 is not set +# CONFIG_VIA_VELOCITY is not set +# CONFIG_TIGON3 is not set +# CONFIG_BNX2 is not set +# CONFIG_QLA3XXX is not set +# CONFIG_ATL1 is not set +CONFIG_NETDEV_10000=y +# CONFIG_CHELSIO_T1 is not set +# CONFIG_CHELSIO_T3 is not set +# CONFIG_IXGB is not set +# CONFIG_S2IO is not set +# CONFIG_MYRI10GE is not set +# CONFIG_NETXEN_NIC is not set +# CONFIG_MLX4_CORE is not set +# CONFIG_TR is not set + +# +# Wireless LAN +# +# CONFIG_WLAN_PRE80211 is not set +# CONFIG_WLAN_80211 is not set + +# +# USB Network Adapters +# +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +# CONFIG_USB_USBNET_MII is not set +# CONFIG_USB_USBNET is not set +# CONFIG_WAN is not set +# CONFIG_FDDI is not set +# CONFIG_HIPPI is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_NET_FC is not set +# CONFIG_SHAPER is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_ISDN is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set + +# +# Userland interfaces +# +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_TSDEV is not set +CONFIG_INPUT_EVDEV=y +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +CONFIG_INPUT_TOUCHSCREEN=y +# CONFIG_TOUCHSCREEN_GUNZE is not set +# CONFIG_TOUCHSCREEN_ELO is not set +# CONFIG_TOUCHSCREEN_MTOUCH is not set +# CONFIG_TOUCHSCREEN_MK712 is not set +# CONFIG_TOUCHSCREEN_PENMOUNT is not set +# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set +# CONFIG_TOUCHSCREEN_TOUCHWIN is not set +CONFIG_TOUCHSCREEN_UCB1400=m +# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_PXA=y +CONFIG_SERIAL_PXA_CONSOLE=y +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_JSM is not set +CONFIG_UNIX98_PTYS=y +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=256 +# CONFIG_IPMI_HANDLER is not set +# CONFIG_WATCHDOG is not set +CONFIG_HW_RANDOM=m +# CONFIG_NVRAM is not set +# CONFIG_R3964 is not set +# CONFIG_APPLICOM is not set +# CONFIG_DRM is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +CONFIG_DEVPORT=y +# CONFIG_I2C is not set + +# +# SPI support +# +# CONFIG_SPI is not set +# CONFIG_SPI_MASTER is not set +# CONFIG_W1 is not set +# CONFIG_HWMON is not set +CONFIG_MISC_DEVICES=y +# CONFIG_PHANTOM is not set +# CONFIG_EEPROM_93CX6 is not set +# CONFIG_SGI_IOC4 is not set +# CONFIG_TIFM_CORE is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_SM501 is not set + +# +# LED devices +# +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y + +# +# LED drivers +# +CONFIG_LEDS_CM_X270=y + +# +# LED Triggers +# +CONFIG_LEDS_TRIGGERS=y +# CONFIG_LEDS_TRIGGER_TIMER is not set +# CONFIG_LEDS_TRIGGER_IDE_DISK is not set +CONFIG_LEDS_TRIGGER_HEARTBEAT=y + +# +# Multimedia devices +# +# CONFIG_VIDEO_DEV is not set +# CONFIG_DVB_CORE is not set +CONFIG_DAB=y +# CONFIG_USB_DABUSB is not set + +# +# Graphics support +# +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set +# CONFIG_VGASTATE is not set +CONFIG_FB=y +# CONFIG_FIRMWARE_EDID is not set +# CONFIG_FB_DDC is not set +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_IMAGEBLIT=y +# CONFIG_FB_SYS_FILLRECT is not set +# CONFIG_FB_SYS_COPYAREA is not set +# CONFIG_FB_SYS_IMAGEBLIT is not set +# CONFIG_FB_SYS_FOPS is not set +CONFIG_FB_DEFERRED_IO=y +# CONFIG_FB_SVGALIB is not set +# CONFIG_FB_MACMODES is not set +# CONFIG_FB_BACKLIGHT is not set +# CONFIG_FB_MODE_HELPERS is not set +# CONFIG_FB_TILEBLITTING is not set + +# +# Frame buffer hardware drivers +# +# CONFIG_FB_CIRRUS is not set +# CONFIG_FB_PM2 is not set +# CONFIG_FB_CYBER2000 is not set +# CONFIG_FB_ASILIANT is not set +# CONFIG_FB_IMSTT is not set +# CONFIG_FB_S1D13XXX is not set +# CONFIG_FB_NVIDIA is not set +# CONFIG_FB_RIVA is not set +# CONFIG_FB_MATROX is not set +# CONFIG_FB_RADEON is not set +# CONFIG_FB_ATY128 is not set +# CONFIG_FB_ATY is not set +# CONFIG_FB_S3 is not set +# CONFIG_FB_SAVAGE is not set +# CONFIG_FB_SIS is not set +# CONFIG_FB_NEOMAGIC is not set +# CONFIG_FB_KYRO is not set +# CONFIG_FB_3DFX is not set +# CONFIG_FB_VOODOO1 is not set +# CONFIG_FB_VT8623 is not set +# CONFIG_FB_TRIDENT is not set +# CONFIG_FB_ARK is not set +# CONFIG_FB_PM3 is not set +CONFIG_FB_PXA=y +# CONFIG_FB_PXA_PARAMETERS is not set +CONFIG_FB_MBX=m +# CONFIG_FB_VIRTUAL is not set + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE=y +# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set +# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set +# CONFIG_FONTS is not set +CONFIG_FONT_8x8=y +CONFIG_FONT_8x16=y +CONFIG_LOGO=y +CONFIG_LOGO_LINUX_MONO=y +CONFIG_LOGO_LINUX_VGA16=y +CONFIG_LOGO_LINUX_CLUT224=y + +# +# Sound +# +CONFIG_SOUND=m + +# +# Advanced Linux Sound Architecture +# +CONFIG_SND=m +CONFIG_SND_TIMER=m +CONFIG_SND_PCM=m +# CONFIG_SND_SEQUENCER is not set +CONFIG_SND_OSSEMUL=y +CONFIG_SND_MIXER_OSS=m +CONFIG_SND_PCM_OSS=m +CONFIG_SND_PCM_OSS_PLUGINS=y +# CONFIG_SND_DYNAMIC_MINORS is not set +CONFIG_SND_SUPPORT_OLD_API=y +CONFIG_SND_VERBOSE_PROCFS=y +# CONFIG_SND_VERBOSE_PRINTK is not set +# CONFIG_SND_DEBUG is not set + +# +# Generic devices +# +CONFIG_SND_AC97_CODEC=m +# CONFIG_SND_DUMMY is not set +# CONFIG_SND_MTPAV is not set +# CONFIG_SND_SERIAL_U16550 is not set +# CONFIG_SND_MPU401 is not set + +# +# PCI devices +# +# CONFIG_SND_AD1889 is not set +# CONFIG_SND_ALS300 is not set +# CONFIG_SND_ALI5451 is not set +# CONFIG_SND_ATIIXP is not set +# CONFIG_SND_ATIIXP_MODEM is not set +# CONFIG_SND_AU8810 is not set +# CONFIG_SND_AU8820 is not set +# CONFIG_SND_AU8830 is not set +# CONFIG_SND_AZT3328 is not set +# CONFIG_SND_BT87X is not set +# CONFIG_SND_CA0106 is not set +# CONFIG_SND_CMIPCI is not set +# CONFIG_SND_CS4281 is not set +# CONFIG_SND_CS46XX is not set +# CONFIG_SND_DARLA20 is not set +# CONFIG_SND_GINA20 is not set +# CONFIG_SND_LAYLA20 is not set +# CONFIG_SND_DARLA24 is not set +# CONFIG_SND_GINA24 is not set +# CONFIG_SND_LAYLA24 is not set +# CONFIG_SND_MONA is not set +# CONFIG_SND_MIA is not set +# CONFIG_SND_ECHO3G is not set +# CONFIG_SND_INDIGO is not set +# CONFIG_SND_INDIGOIO is not set +# CONFIG_SND_INDIGODJ is not set +# CONFIG_SND_EMU10K1 is not set +# CONFIG_SND_EMU10K1X is not set +# CONFIG_SND_ENS1370 is not set +# CONFIG_SND_ENS1371 is not set +# CONFIG_SND_ES1938 is not set +# CONFIG_SND_ES1968 is not set +# CONFIG_SND_FM801 is not set +# CONFIG_SND_HDA_INTEL is not set +# CONFIG_SND_HDSP is not set +# CONFIG_SND_HDSPM is not set +# CONFIG_SND_ICE1712 is not set +# CONFIG_SND_ICE1724 is not set +# CONFIG_SND_INTEL8X0 is not set +# CONFIG_SND_INTEL8X0M is not set +# CONFIG_SND_KORG1212 is not set +# CONFIG_SND_MAESTRO3 is not set +# CONFIG_SND_MIXART is not set +# CONFIG_SND_NM256 is not set +# CONFIG_SND_PCXHR is not set +# CONFIG_SND_RIPTIDE is not set +# CONFIG_SND_RME32 is not set +# CONFIG_SND_RME96 is not set +# CONFIG_SND_RME9652 is not set +# CONFIG_SND_SONICVIBES is not set +# CONFIG_SND_TRIDENT is not set +# CONFIG_SND_VIA82XX is not set +# CONFIG_SND_VIA82XX_MODEM is not set +# CONFIG_SND_VX222 is not set +# CONFIG_SND_YMFPCI is not set +# CONFIG_SND_AC97_POWER_SAVE is not set + +# +# ALSA ARM devices +# +CONFIG_SND_PXA2XX_PCM=m +CONFIG_SND_PXA2XX_AC97=m + +# +# USB devices +# +# CONFIG_SND_USB_AUDIO is not set +# CONFIG_SND_USB_CAIAQ is not set + +# +# System on Chip audio support +# +# CONFIG_SND_SOC is not set + +# +# Open Sound System +# +# CONFIG_SOUND_PRIME is not set +CONFIG_AC97_BUS=m +CONFIG_HID_SUPPORT=y +CONFIG_HID=y +# CONFIG_HID_DEBUG is not set + +# +# USB Input Devices +# +CONFIG_USB_HID=y +# CONFIG_USB_HIDINPUT_POWERBOOK is not set +# CONFIG_HID_FF is not set +# CONFIG_USB_HIDDEV is not set +CONFIG_USB_SUPPORT=y +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB_ARCH_HAS_OHCI=y +CONFIG_USB_ARCH_HAS_EHCI=y +CONFIG_USB=y +# CONFIG_USB_DEBUG is not set + +# +# Miscellaneous USB options +# +CONFIG_USB_DEVICEFS=y +# CONFIG_USB_DEVICE_CLASS is not set +# CONFIG_USB_DYNAMIC_MINORS is not set +# CONFIG_USB_SUSPEND is not set +# CONFIG_USB_PERSIST is not set +# CONFIG_USB_OTG is not set + +# +# USB Host Controller Drivers +# +# CONFIG_USB_EHCI_HCD is not set +# CONFIG_USB_ISP116X_HCD is not set +CONFIG_USB_OHCI_HCD=y +# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set +# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set +CONFIG_USB_OHCI_LITTLE_ENDIAN=y +# CONFIG_USB_UHCI_HCD is not set +# CONFIG_USB_SL811_HCD is not set +# CONFIG_USB_R8A66597_HCD is not set + +# +# USB Device Class drivers +# +# CONFIG_USB_ACM is not set +# CONFIG_USB_PRINTER is not set + +# +# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' +# + +# +# may also be needed; see USB_STORAGE Help for more information +# +CONFIG_USB_STORAGE=y +# CONFIG_USB_STORAGE_DEBUG is not set +# CONFIG_USB_STORAGE_DATAFAB is not set +# CONFIG_USB_STORAGE_FREECOM is not set +# CONFIG_USB_STORAGE_DPCM is not set +# CONFIG_USB_STORAGE_USBAT is not set +# CONFIG_USB_STORAGE_SDDR09 is not set +# CONFIG_USB_STORAGE_SDDR55 is not set +# CONFIG_USB_STORAGE_JUMPSHOT is not set +# CONFIG_USB_STORAGE_ALAUDA is not set +# CONFIG_USB_STORAGE_KARMA is not set +# CONFIG_USB_LIBUSUAL is not set + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_MICROTEK is not set +CONFIG_USB_MON=y + +# +# USB port drivers +# + +# +# USB Serial Converter support +# +# CONFIG_USB_SERIAL is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_AUERSWALD is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_BERRY_CHARGE is not set +# CONFIG_USB_LED is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_PHIDGET is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +# CONFIG_USB_TEST is not set + +# +# USB DSL modem support +# + +# +# USB Gadget Support +# +# CONFIG_USB_GADGET is not set +CONFIG_MMC=m +# CONFIG_MMC_DEBUG is not set +# CONFIG_MMC_UNSAFE_RESUME is not set + +# +# MMC/SD Card Drivers +# +CONFIG_MMC_BLOCK=m +CONFIG_MMC_BLOCK_BOUNCE=y + +# +# MMC/SD Host Controller Drivers +# +CONFIG_MMC_PXA=m +# CONFIG_MMC_SDHCI is not set +# CONFIG_MMC_TIFM_SD is not set + +# +# Real Time Clock +# +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +# CONFIG_RTC_DEBUG is not set + +# +# RTC interfaces +# +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set +# CONFIG_RTC_DRV_TEST is not set + +# +# Platform RTC drivers +# +# CONFIG_RTC_DRV_CMOS is not set +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T59 is not set +CONFIG_RTC_DRV_V3020=y + +# +# on-CPU RTC drivers +# +CONFIG_RTC_DRV_SA1100=y + +# +# DMA Engine support +# +# CONFIG_DMA_ENGINE is not set + +# +# DMA Clients +# + +# +# DMA Devices +# + +# +# File systems +# +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set +CONFIG_EXT3_FS=y +CONFIG_EXT3_FS_XATTR=y +# CONFIG_EXT3_FS_POSIX_ACL is not set +# CONFIG_EXT3_FS_SECURITY is not set +# CONFIG_EXT4DEV_FS is not set +CONFIG_JBD=y +# CONFIG_JBD_DEBUG is not set +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +# CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_ROMFS_FS is not set +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +CONFIG_DNOTIFY=y +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +CONFIG_RAMFS=y +# CONFIG_CONFIGFS_FS is not set + +# +# Miscellaneous filesystems +# +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +# CONFIG_JFFS2_FS is not set +# CONFIG_CRAMFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set + +# +# Network File Systems +# +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +# CONFIG_NFS_V4 is not set +# CONFIG_NFS_DIRECTIO is not set +# CONFIG_NFSD is not set +CONFIG_ROOT_NFS=y +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +# CONFIG_SUNRPC_BIND34 is not set +# CONFIG_RPCSEC_GSS_KRB5 is not set +# CONFIG_RPCSEC_GSS_SPKM3 is not set +CONFIG_SMB_FS=y +# CONFIG_SMB_NLS_DEFAULT is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y + +# +# Native Language Support +# +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ASCII is not set +CONFIG_NLS_ISO8859_1=y +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_UTF8 is not set + +# +# Distributed Lock Manager +# +# CONFIG_DLM is not set + +# +# Profiling support +# +# CONFIG_PROFILING is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_MAGIC_SYSRQ=y +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_SHIRQ is not set +# CONFIG_DETECT_SOFTLOCKUP is not set +CONFIG_SCHED_DEBUG=y +# CONFIG_SCHEDSTATS is not set +# CONFIG_TIMER_STATS is not set +# CONFIG_DEBUG_SLAB is not set +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_RT_MUTEX_TESTER is not set +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_MUTEXES is not set +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_PROVE_LOCKING is not set +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_DEBUG_KOBJECT is not set +# CONFIG_DEBUG_BUGVERBOSE is not set +CONFIG_DEBUG_INFO=y +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_LIST is not set +CONFIG_FRAME_POINTER=y +CONFIG_FORCED_INLINING=y +# CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_FAULT_INJECTION is not set +CONFIG_DEBUG_USER=y +CONFIG_DEBUG_ERRORS=y +CONFIG_DEBUG_LL=y +# CONFIG_DEBUG_ICEDCC is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set +CONFIG_CRYPTO=y +CONFIG_CRYPTO_ALGAPI=m +CONFIG_CRYPTO_BLKCIPHER=m +CONFIG_CRYPTO_MANAGER=m +# CONFIG_CRYPTO_HMAC is not set +# CONFIG_CRYPTO_XCBC is not set +# CONFIG_CRYPTO_NULL is not set +# CONFIG_CRYPTO_MD4 is not set +# CONFIG_CRYPTO_MD5 is not set +# CONFIG_CRYPTO_SHA1 is not set +# CONFIG_CRYPTO_SHA256 is not set +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_WP512 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_GF128MUL is not set +CONFIG_CRYPTO_ECB=m +CONFIG_CRYPTO_CBC=m +CONFIG_CRYPTO_PCBC=m +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_CRYPTD is not set +# CONFIG_CRYPTO_DES is not set +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_TWOFISH is not set +# CONFIG_CRYPTO_SERPENT is not set +CONFIG_CRYPTO_AES=m +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +# CONFIG_CRYPTO_TEA is not set +CONFIG_CRYPTO_ARC4=m +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_ANUBIS is not set +# CONFIG_CRYPTO_DEFLATE is not set +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_CRC32C is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_TEST is not set +CONFIG_CRYPTO_HW=y + +# +# Library routines +# +CONFIG_BITREVERSE=y +# CONFIG_CRC_CCITT is not set +# CONFIG_CRC16 is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +CONFIG_PLIST=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig index e895188..656d496 100644 --- a/arch/arm/mach-pxa/Kconfig +++ b/arch/arm/mach-pxa/Kconfig @@ -63,6 +63,11 @@ config MACH_ZYLONITE bool "PXA3xx Development Platform" select PXA3xx +config MACH_ARMCORE + bool "CompuLab CM-X270 modules" + select PXA27x + select IWMMXT + endchoice if PXA_SHARPSL diff --git a/arch/arm/mach-pxa/Makefile b/arch/arm/mach-pxa/Makefile index bfdd0c5..4263527 100644 --- a/arch/arm/mach-pxa/Makefile +++ b/arch/arm/mach-pxa/Makefile @@ -29,6 +29,8 @@ ifeq ($(CONFIG_MACH_ZYLONITE),y) obj-$(CONFIG_CPU_PXA320) += zylonite_pxa320.o endif +obj-$(CONFIG_MACH_ARMCORE) += cm-x270.o + # Support for blinky lights led-y := leds.o led-$(CONFIG_ARCH_LUBBOCK) += leds-lubbock.o @@ -45,3 +47,7 @@ obj-$(CONFIG_PXA_SSP) += ssp.o ifeq ($(CONFIG_PXA27x),y) obj-$(CONFIG_PM) += standby.o endif + +ifeq ($(CONFIG_PCI),y) +obj-$(CONFIG_MACH_ARMCORE) += cm-x270-pci.o +endif diff --git a/arch/arm/mach-pxa/cm-x270-pci.c b/arch/arm/mach-pxa/cm-x270-pci.c new file mode 100644 index 0000000..878d3b9 --- /dev/null +++ b/arch/arm/mach-pxa/cm-x270-pci.c @@ -0,0 +1,218 @@ +/* + * linux/arch/arm/mach-pxa/cm-x270-pci.c + * + * PCI bios-type initialisation for PCI machines + * + * Bits taken from various places. + * + * Copyright (C) 2007 Compulab, Ltd. + * Mike Rapoport + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include + +unsigned long it8152_base_address = CMX270_IT8152_VIRT; + +/* + * Only first 64MB of memory can be accessed via PCI. + * We use GFP_DMA to allocate safe buffers to do map/unmap. + * This is really ugly and we need a better way of specifying + * DMA-capable regions of memory. + */ +void __init cmx270_pci_adjust_zones(int node, unsigned long *zone_size, + unsigned long *zhole_size) +{ + unsigned int sz = SZ_64M >> PAGE_SHIFT; + + printk(KERN_INFO "Adjusting zones for CM-x270\n"); + + /* + * Only adjust if > 64M on current system + */ + if (node || (zone_size[0] <= sz)) + return; + + zone_size[1] = zone_size[0] - sz; + zone_size[0] = sz; + zhole_size[1] = zhole_size[0]; + zhole_size[0] = 0; +} + +static void cmx270_it8152_irq_demux(unsigned int irq, struct irq_desc *desc) +{ + /* clear our parent irq */ + GEDR(GPIO_IT8152_IRQ) = GPIO_bit(GPIO_IT8152_IRQ); + + it8152_irq_demux(irq, desc); +} + +void __cmx270_pci_init_irq(void) +{ + it8152_init_irq(); + pxa_gpio_mode(IRQ_TO_GPIO(GPIO_IT8152_IRQ)); + set_irq_type(IRQ_GPIO(GPIO_IT8152_IRQ), IRQT_RISING); + + set_irq_chained_handler(IRQ_GPIO(GPIO_IT8152_IRQ), + cmx270_it8152_irq_demux); +} + +#ifdef CONFIG_PM +static unsigned long sleep_save_ite[10]; + +void __cmx270_pci_suspend(void) +{ + /* save ITE state */ + sleep_save_ite[0] = __raw_readl(IT8152_INTC_PDCNIMR); + sleep_save_ite[1] = __raw_readl(IT8152_INTC_LPCNIMR); + sleep_save_ite[2] = __raw_readl(IT8152_INTC_LPNIAR); + + /* Clear ITE IRQ's */ + __raw_writel((0), IT8152_INTC_PDCNIRR); + __raw_writel((0), IT8152_INTC_LPCNIRR); +} + +void __cmx270_pci_resume(void) +{ + /* restore IT8152 state */ + __raw_writel((sleep_save_ite[0]), IT8152_INTC_PDCNIMR); + __raw_writel((sleep_save_ite[1]), IT8152_INTC_LPCNIMR); + __raw_writel((sleep_save_ite[2]), IT8152_INTC_LPNIAR); +} +#else +void cmx270_pci_suspend(void) {} +void cmx270_pci_resume(void) {} +#endif + +/* PCI IRQ mapping*/ +static int __init cmx270_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) +{ + int irq; + + printk(KERN_DEBUG "===> %s: %s slot=%x, pin=%x\n", __FUNCTION__, + pci_name(dev), slot, pin); + + irq = it8152_pci_map_irq(dev, slot, pin); + if (irq) + return irq; + + /* + Here comes the ugly part. The routing is baseboard specific, + but defining a platform for each possible base of CM-x270 is + unrealistic. Here we keep mapping for ATXBase and SB-x270. + */ + /* ATXBASE PCI slot */ + if (slot == 7) + return IT8152_PCI_INTA; + + /* ATXBase/SB-x270 CardBus */ + if (slot == 8 || slot == 0) + return IT8152_PCI_INTB; + + /* ATXBase Ethernet */ + if (slot == 9) + return IT8152_PCI_INTA; + + /* SB-x270 Ethernet */ + if (slot == 16) + return IT8152_PCI_INTA; + + /* PC104+ interrupt routing */ + if ((slot == 17) || (slot == 19)) + return IT8152_PCI_INTA; + if ((slot == 18) || (slot == 20)) + return IT8152_PCI_INTB; + + return(0); +} + +static struct pci_bus * __init +cmx270_pci_scan_bus(int nr, struct pci_sys_data *sys) +{ + printk(KERN_INFO "Initializing CM-X270 PCI subsystem\n"); + + __raw_writel(0x800, IT8152_PCI_CFG_ADDR); + if (__raw_readl(IT8152_PCI_CFG_DATA) == 0x81521283) { + printk(KERN_INFO "PCI Bridge found.\n"); + + /* set PCI I/O base at 0 */ + writel(0x848, IT8152_PCI_CFG_ADDR); + writel(0, IT8152_PCI_CFG_DATA); + + /* set PCI memory base at 0 */ + writel(0x840, IT8152_PCI_CFG_ADDR); + writel(0, IT8152_PCI_CFG_DATA); + + writel(0x20, IT8152_GPIO_GPDR); + + /* CardBus Controller on ATXbase baseboard */ + writel(0x4000, IT8152_PCI_CFG_ADDR); + if (readl(IT8152_PCI_CFG_DATA) == 0xAC51104C) { + printk(KERN_INFO "CardBus Bridge found.\n"); + + /* Configure socket 0 */ + writel(0x408C, IT8152_PCI_CFG_ADDR); + writel(0x1022, IT8152_PCI_CFG_DATA); + + writel(0x4080, IT8152_PCI_CFG_ADDR); + writel(0x3844d060, IT8152_PCI_CFG_DATA); + + writel(0x4090, IT8152_PCI_CFG_ADDR); + writel(((readl(IT8152_PCI_CFG_DATA) & 0xffff) | + 0x60440000), + IT8152_PCI_CFG_DATA); + + writel(0x4018, IT8152_PCI_CFG_ADDR); + writel(0xb0000000, IT8152_PCI_CFG_DATA); + + /* Configure socket 1 */ + writel(0x418C, IT8152_PCI_CFG_ADDR); + writel(0x1022, IT8152_PCI_CFG_DATA); + + writel(0x4180, IT8152_PCI_CFG_ADDR); + writel(0x3844d060, IT8152_PCI_CFG_DATA); + + writel(0x4190, IT8152_PCI_CFG_ADDR); + writel(((readl(IT8152_PCI_CFG_DATA) & 0xffff) | + 0x60440000), + IT8152_PCI_CFG_DATA); + + writel(0x4118, IT8152_PCI_CFG_ADDR); + writel(0xb0000000, IT8152_PCI_CFG_DATA); + } + } + return it8152_pci_scan_bus(nr, sys); +} + +static struct hw_pci cmx270_pci __initdata = { + .swizzle = pci_std_swizzle, + .map_irq = cmx270_pci_map_irq, + .nr_controllers = 1, + .setup = it8152_pci_setup, + .scan = cmx270_pci_scan_bus, +}; + +static int __init cmx270_init_pci(void) +{ + if (machine_is_armcore()) + pci_common_init(&cmx270_pci); + + return 0; +} + +subsys_initcall(cmx270_init_pci); diff --git a/arch/arm/mach-pxa/cm-x270-pci.h b/arch/arm/mach-pxa/cm-x270-pci.h new file mode 100644 index 0000000..ffe37b6 --- /dev/null +++ b/arch/arm/mach-pxa/cm-x270-pci.h @@ -0,0 +1,13 @@ +extern void __cmx270_pci_init_irq(void); +extern void __cmx270_pci_suspend(void); +extern void __cmx270_pci_resume(void); + +#ifdef CONFIG_PCI +#define cmx270_pci_init_irq __cmx270_pci_init_irq +#define cmx270_pci_suspend __cmx270_pci_suspend +#define cmx270_pci_resume __cmx270_pci_resume +#else +#define cmx270_pci_init_irq() do {} while (0) +#define cmx270_pci_suspend() do {} while (0) +#define cmx270_pci_resume() do {} while (0) +#endif diff --git a/arch/arm/mach-pxa/cm-x270.c b/arch/arm/mach-pxa/cm-x270.c new file mode 100644 index 0000000..177664c --- /dev/null +++ b/arch/arm/mach-pxa/cm-x270.c @@ -0,0 +1,645 @@ +/* + * linux/arch/arm/mach-pxa/cm-x270.c + * + * Copyright (C) 2007 CompuLab, Ltd. + * Mike Rapoport + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include