From 8cb2815574278a1bf966f041cbfe5b7c91472dcd Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Mon, 24 Jan 2011 15:22:13 +0100 Subject: ARM: 6632/3: mmci: stop using the blockend interrupts Implement a suggestion from Russell to drop the use of blockend interrupts altogether and instead rely on the data counter. Tested with error-free cards on U300, U8500 and RealView PB1176. Signed-off-by: Ulf Hansson Signed-off-by: Linus Walleij Signed-off-by: Russell King diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c index 5630228..2de12fe 100644 --- a/drivers/mmc/host/mmci.c +++ b/drivers/mmc/host/mmci.c @@ -46,10 +46,6 @@ static unsigned int fmax = 515633; * is asserted (likewise for RX) * @fifohalfsize: number of bytes that can be written when MCI_TXFIFOHALFEMPTY * is asserted (likewise for RX) - * @broken_blockend: the MCI_DATABLOCKEND is broken on the hardware - * and will not work at all. - * @broken_blockend_dma: the MCI_DATABLOCKEND is broken on the hardware when - * using DMA. * @sdio: variant supports SDIO * @st_clkdiv: true if using a ST-specific clock divider algorithm */ @@ -59,8 +55,6 @@ struct variant_data { unsigned int datalength_bits; unsigned int fifosize; unsigned int fifohalfsize; - bool broken_blockend; - bool broken_blockend_dma; bool sdio; bool st_clkdiv; }; @@ -76,7 +70,6 @@ static struct variant_data variant_u300 = { .fifohalfsize = 8 * 4, .clkreg_enable = 1 << 13, /* HWFCEN */ .datalength_bits = 16, - .broken_blockend_dma = true, .sdio = true, }; @@ -86,7 +79,6 @@ static struct variant_data variant_ux500 = { .clkreg = MCI_CLK_ENABLE, .clkreg_enable = 1 << 14, /* HWFCEN */ .datalength_bits = 24, - .broken_blockend = true, .sdio = true, .st_clkdiv = true, }; @@ -210,8 +202,6 @@ static void mmci_start_data(struct mmci_host *host, struct mmc_data *data) host->data = data; host->size = data->blksz * data->blocks; host->data_xfered = 0; - host->blockend = false; - host->dataend = false; mmci_init_sg(host, data); @@ -288,21 +278,26 @@ static void mmci_data_irq(struct mmci_host *host, struct mmc_data *data, unsigned int status) { - struct variant_data *variant = host->variant; - /* First check for errors */ if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_TXUNDERRUN|MCI_RXOVERRUN)) { + u32 remain, success; + + /* Calculate how far we are into the transfer */ + remain = readl(host->base + MMCIDATACNT) << 2; + success = data->blksz * data->blocks - remain; + dev_dbg(mmc_dev(host->mmc), "MCI ERROR IRQ (status %08x)\n", status); - if (status & MCI_DATACRCFAIL) + if (status & MCI_DATACRCFAIL) { + /* Last block was not successful */ + host->data_xfered = ((success / data->blksz) - 1 * data->blksz); data->error = -EILSEQ; - else if (status & MCI_DATATIMEOUT) + } else if (status & MCI_DATATIMEOUT) { + host->data_xfered = success; data->error = -ETIMEDOUT; - else if (status & (MCI_TXUNDERRUN|MCI_RXOVERRUN)) + } else if (status & (MCI_TXUNDERRUN|MCI_RXOVERRUN)) { + host->data_xfered = success; data->error = -EIO; - - /* Force-complete the transaction */ - host->blockend = true; - host->dataend = true; + } /* * We hit an error condition. Ensure that any data @@ -321,61 +316,14 @@ mmci_data_irq(struct mmci_host *host, struct mmc_data *data, } } - /* - * On ARM variants in PIO mode, MCI_DATABLOCKEND - * is always sent first, and we increase the - * transfered number of bytes for that IRQ. Then - * MCI_DATAEND follows and we conclude the transaction. - * - * On the Ux500 single-IRQ variant MCI_DATABLOCKEND - * doesn't seem to immediately clear from the status, - * so we can't use it keep count when only one irq is - * used because the irq will hit for other reasons, and - * then the flag is still up. So we use the MCI_DATAEND - * IRQ at the end of the entire transfer because - * MCI_DATABLOCKEND is broken. - * - * In the U300, the IRQs can arrive out-of-order, - * e.g. MCI_DATABLOCKEND sometimes arrives after MCI_DATAEND, - * so for this case we use the flags "blockend" and - * "dataend" to make sure both IRQs have arrived before - * concluding the transaction. (This does not apply - * to the Ux500 which doesn't fire MCI_DATABLOCKEND - * at all.) In DMA mode it suffers from the same problem - * as the Ux500. - */ - if (status & MCI_DATABLOCKEND) { - /* - * Just being a little over-cautious, we do not - * use this progressive update if the hardware blockend - * flag is unreliable: since it can stay high between - * IRQs it will corrupt the transfer counter. - */ - if (!variant->broken_blockend) - host->data_xfered += data->blksz; - host->blockend = true; - } - - if (status & MCI_DATAEND) - host->dataend = true; + if (status & MCI_DATABLOCKEND) + dev_err(mmc_dev(host->mmc), "stray MCI_DATABLOCKEND interrupt\n"); - /* - * On variants with broken blockend we shall only wait for dataend, - * on others we must sync with the blockend signal since they can - * appear out-of-order. - */ - if (host->dataend && (host->blockend || variant->broken_blockend)) { + if (status & MCI_DATAEND) { mmci_stop_data(host); - /* Reset these flags */ - host->blockend = false; - host->dataend = false; - - /* - * Variants with broken blockend flags need to handle the - * end of the entire transfer here. - */ - if (variant->broken_blockend && !data->error) + if (!data->error) + /* The error clause is handled above, success! */ host->data_xfered += data->blksz * data->blocks; if (!data->stop) { @@ -770,7 +718,6 @@ static int __devinit mmci_probe(struct amba_device *dev, struct amba_id *id) struct variant_data *variant = id->data; struct mmci_host *host; struct mmc_host *mmc; - unsigned int mask; int ret; /* must have platform data */ @@ -951,12 +898,7 @@ static int __devinit mmci_probe(struct amba_device *dev, struct amba_id *id) goto irq0_free; } - mask = MCI_IRQENABLE; - /* Don't use the datablockend flag if it's broken */ - if (variant->broken_blockend) - mask &= ~MCI_DATABLOCKEND; - - writel(mask, host->base + MMCIMASK0); + writel(MCI_IRQENABLE, host->base + MMCIMASK0); amba_set_drvdata(dev, mmc); diff --git a/drivers/mmc/host/mmci.h b/drivers/mmc/host/mmci.h index df06f01..c1df7b8 100644 --- a/drivers/mmc/host/mmci.h +++ b/drivers/mmc/host/mmci.h @@ -137,7 +137,7 @@ #define MCI_IRQENABLE \ (MCI_CMDCRCFAILMASK|MCI_DATACRCFAILMASK|MCI_CMDTIMEOUTMASK| \ MCI_DATATIMEOUTMASK|MCI_TXUNDERRUNMASK|MCI_RXOVERRUNMASK| \ - MCI_CMDRESPENDMASK|MCI_CMDSENTMASK|MCI_DATABLOCKENDMASK) + MCI_CMDRESPENDMASK|MCI_CMDSENTMASK) /* These interrupts are directed to IRQ1 when two IRQ lines are available */ #define MCI_IRQ1MASK \ @@ -177,9 +177,6 @@ struct mmci_host { struct timer_list timer; unsigned int oldstat; - bool blockend; - bool dataend; - /* pio stuff */ struct sg_mapping_iter sg_miter; unsigned int size; -- cgit v0.10.2 From ec15038f2becd710eef7485baff7830abb1c9330 Mon Sep 17 00:00:00 2001 From: Russell King Date: Sat, 22 Jan 2011 17:22:34 +0000 Subject: ARM: realview,vexpress: fix section mismatch warning for pen_release Fix two section mismatch warnings in the platform SMP bringup code for Realview and Versatile Express: WARNING: arch/arm/mach-realview/built-in.o(.text+0x8ac): Section mismatch in reference from the function write_pen_release() to the variable .cpuinit.data:pen_release The function write_pen_release() references the variable __cpuinitdata pen_release. This is often because write_pen_release lacks a __cpuinitdata annotation or the annotation of pen_release is wrong. WARNING: arch/arm/mach-vexpress/built-in.o(.text+0x7b4): Section mismatch in reference from the function write_pen_release() to the variable .cpuinit.data:pen_release The function write_pen_release() references the variable __cpuinitdata pen_release. This is often because write_pen_release lacks a __cpuinitdata annotation or the annotation of pen_release is wrong. Signed-off-by: Russell King diff --git a/arch/arm/mach-realview/platsmp.c b/arch/arm/mach-realview/platsmp.c index a22bf67..6959d13 100644 --- a/arch/arm/mach-realview/platsmp.c +++ b/arch/arm/mach-realview/platsmp.c @@ -41,7 +41,7 @@ volatile int __cpuinitdata pen_release = -1; * observers, irrespective of whether they're taking part in coherency * or not. This is necessary for the hotplug code to work reliably. */ -static void write_pen_release(int val) +static void __cpuinit write_pen_release(int val) { pen_release = val; smp_wmb(); diff --git a/arch/arm/mach-vexpress/platsmp.c b/arch/arm/mach-vexpress/platsmp.c index b1687b6..634bf1d 100644 --- a/arch/arm/mach-vexpress/platsmp.c +++ b/arch/arm/mach-vexpress/platsmp.c @@ -39,7 +39,7 @@ volatile int __cpuinitdata pen_release = -1; * observers, irrespective of whether they're taking part in coherency * or not. This is necessary for the hotplug code to work reliably. */ -static void write_pen_release(int val) +static void __cpuinit write_pen_release(int val) { pen_release = val; smp_wmb(); -- cgit v0.10.2 From d2a1c9ad785897850db0d46f4ba02364d89386b5 Mon Sep 17 00:00:00 2001 From: Russell King Date: Mon, 24 Jan 2011 10:58:24 +0000 Subject: ARM: realview: name configuration options after actual board names As no one seems to really know which configuration options tie up with which boards, I thought I'd do some investigation and try to work it out. After discussion with some folk in linaro, I think I have this nailed. The names are updated to use the name on the front of the appropriate board user guide for the various baseboards, which I've taken to be the official name for each board. I haven't significantly updated the descriptions for the tiles as that is even less clear - as far as I can see on ARMs website, there is no Cortex-A9 tile for Realview EB - only ARM11MPCore, ARM1156T2F-S, ARM1176TZF-S and Cortex-R4F. So exactly what this 'Multicore Cortex-A9 Tile' is... Acked-by: Catalin Marinas Signed-off-by: Russell King diff --git a/arch/arm/mach-realview/Kconfig b/arch/arm/mach-realview/Kconfig index b4575ae..7ca138a 100644 --- a/arch/arm/mach-realview/Kconfig +++ b/arch/arm/mach-realview/Kconfig @@ -2,52 +2,56 @@ menu "RealView platform type" depends on ARCH_REALVIEW config MACH_REALVIEW_EB - bool "Support RealView/EB platform" + bool "Support RealView(R) Emulation Baseboard" select ARM_GIC help - Include support for the ARM(R) RealView Emulation Baseboard platform. + Include support for the ARM(R) RealView(R) Emulation Baseboard + platform. config REALVIEW_EB_A9MP - bool "Support Multicore Cortex-A9" + bool "Support Multicore Cortex-A9 Tile" depends on MACH_REALVIEW_EB select CPU_V7 help - Enable support for the Cortex-A9MPCore tile on the Realview platform. + Enable support for the Cortex-A9MPCore tile fitted to the + Realview(R) Emulation Baseboard platform. config REALVIEW_EB_ARM11MP - bool "Support ARM11MPCore tile" + bool "Support ARM11MPCore Tile" depends on MACH_REALVIEW_EB select CPU_V6 select ARCH_HAS_BARRIERS if SMP help - Enable support for the ARM11MPCore tile on the Realview platform. + Enable support for the ARM11MPCore tile fitted to the Realview(R) + Emulation Baseboard platform. config REALVIEW_EB_ARM11MP_REVB - bool "Support ARM11MPCore RevB tile" + bool "Support ARM11MPCore RevB Tile" depends on REALVIEW_EB_ARM11MP help - Enable support for the ARM11MPCore RevB tile on the Realview - platform. Since there are device address differences, a - kernel built with this option enabled is not compatible with - other revisions of the ARM11MPCore tile. + Enable support for the ARM11MPCore Revision B tile on the + Realview(R) Emulation Baseboard platform. Since there are device + address differences, a kernel built with this option enabled is + not compatible with other revisions of the ARM11MPCore tile. config MACH_REALVIEW_PB11MP - bool "Support RealView/PB11MPCore platform" + bool "Support RealView(R) Platform Baseboard for ARM11MPCore" select CPU_V6 select ARM_GIC select HAVE_PATA_PLATFORM select ARCH_HAS_BARRIERS if SMP help - Include support for the ARM(R) RealView MPCore Platform Baseboard. - PB11MPCore is a platform with an on-board ARM11MPCore and has + Include support for the ARM(R) RealView(R) Platform Baseboard for + the ARM11MPCore. This platform has an on-board ARM11MPCore and has support for PCI-E and Compact Flash. config MACH_REALVIEW_PB1176 - bool "Support RealView/PB1176 platform" + bool "Support RealView(R) Platform Baseboard for ARM1176JZF-S" select CPU_V6 select ARM_GIC help - Include support for the ARM(R) RealView ARM1176 Platform Baseboard. + Include support for the ARM(R) RealView(R) Platform Baseboard for + ARM1176JZF-S. config REALVIEW_PB1176_SECURE_FLASH bool "Allow access to the secure flash memory block" @@ -59,23 +63,24 @@ config REALVIEW_PB1176_SECURE_FLASH block (64MB @ 0x3c000000) is required. config MACH_REALVIEW_PBA8 - bool "Support RealView/PB-A8 platform" + bool "Support RealView(R) Platform Baseboard for Cortex(tm)-A8 platform" select CPU_V7 select ARM_GIC select HAVE_PATA_PLATFORM help - Include support for the ARM(R) RealView Cortex-A8 Platform Baseboard. - PB-A8 is a platform with an on-board Cortex-A8 and has support for - PCI-E and Compact Flash. + Include support for the ARM(R) RealView Platform Baseboard for + Cortex(tm)-A8. This platform has an on-board Cortex-A8 and has + support for PCI-E and Compact Flash. config MACH_REALVIEW_PBX - bool "Support RealView/PBX platform" + bool "Support RealView(R) Platform Baseboard Explore" select ARM_GIC select HAVE_PATA_PLATFORM select ARCH_SPARSEMEM_ENABLE if CPU_V7 && !REALVIEW_HIGH_PHYS_OFFSET select ZONE_DMA if SPARSEMEM help - Include support for the ARM(R) RealView PBX platform. + Include support for the ARM(R) RealView(R) Platform Baseboard + Explore. config REALVIEW_HIGH_PHYS_OFFSET bool "High physical base address for the RealView platform" -- cgit v0.10.2 From e5310f611d17ed4e92e0d4e46fd9f6fb40e66df3 Mon Sep 17 00:00:00 2001 From: Russell King Date: Mon, 24 Jan 2011 12:00:01 +0000 Subject: ARM: versatile: name configuration options after actual board names Update the option text to those which appear on the front of the appropriate board user guides. This gives consistent board naming, and makes it obvious which option is for which platform. Acked-by: Catalin Marinas Signed-off-by: Russell King diff --git a/arch/arm/mach-versatile/Kconfig b/arch/arm/mach-versatile/Kconfig index 3f7b5e9..9cdec5a 100644 --- a/arch/arm/mach-versatile/Kconfig +++ b/arch/arm/mach-versatile/Kconfig @@ -2,17 +2,19 @@ menu "Versatile platform type" depends on ARCH_VERSATILE config ARCH_VERSATILE_PB - bool "Support Versatile/PB platform" + bool "Support Versatile Platform Baseboard for ARM926EJ-S" select CPU_ARM926T select MIGHT_HAVE_PCI default y help - Include support for the ARM(R) Versatile/PB platform. + Include support for the ARM(R) Versatile Platform Baseboard + for the ARM926EJ-S. config MACH_VERSATILE_AB - bool "Support Versatile/AB platform" + bool "Support Versatile Application Baseboard for ARM926EJ-S" select CPU_ARM926T help - Include support for the ARM(R) Versatile/AP platform. + Include support for the ARM(R) Versatile Application Baseboard + for the ARM926EJ-S. endmenu -- cgit v0.10.2 From baaece224570a935210a59257b5d9073e99843ea Mon Sep 17 00:00:00 2001 From: Pawel Moll Date: Tue, 25 Jan 2011 15:53:03 +0100 Subject: ARM: 6635/2: Configure reference clock for Versatile Express timers Timers on Versatile Express mainboard are used as system clock/event sources. Driver assumes that they are clocked with 1MHz signal. Old V2M firmware apparently configured it by default, but on newer boards one can observe that "sleep 1" command takes over 30 seconds to finish, as the timers are fed with 32kHz instead... This patch performs required magic and also removes code clearing timer's control registers, as exactly the same operations are performed by the timer driver few jiffies later. Signed-off-by: Pawel Moll Tested-by: Will Deacon Signed-off-by: Russell King diff --git a/arch/arm/include/asm/hardware/sp810.h b/arch/arm/include/asm/hardware/sp810.h index a101f10..721847d 100644 --- a/arch/arm/include/asm/hardware/sp810.h +++ b/arch/arm/include/asm/hardware/sp810.h @@ -50,6 +50,12 @@ #define SCPCELLID2 0xFF8 #define SCPCELLID3 0xFFC +#define SCCTRL_TIMEREN0SEL_REFCLK (0 << 15) +#define SCCTRL_TIMEREN0SEL_TIMCLK (1 << 15) + +#define SCCTRL_TIMEREN1SEL_REFCLK (0 << 17) +#define SCCTRL_TIMEREN1SEL_TIMCLK (1 << 17) + static inline void sysctl_soft_reset(void __iomem *base) { /* writing any value to SCSYSSTAT reg will reset system */ diff --git a/arch/arm/mach-vexpress/v2m.c b/arch/arm/mach-vexpress/v2m.c index a9ed342..1edae65 100644 --- a/arch/arm/mach-vexpress/v2m.c +++ b/arch/arm/mach-vexpress/v2m.c @@ -19,6 +19,7 @@ #include #include #include +#include #include @@ -50,8 +51,16 @@ void __init v2m_map_io(struct map_desc *tile, size_t num) static void __init v2m_timer_init(void) { + u32 scctrl; + versatile_sched_clock_init(MMIO_P2V(V2M_SYS_24MHZ), 24000000); + /* Select 1MHz TIMCLK as the reference clock for SP804 timers */ + scctrl = readl(MMIO_P2V(V2M_SYSCTL + SCCTRL)); + scctrl |= SCCTRL_TIMEREN0SEL_TIMCLK; + scctrl |= SCCTRL_TIMEREN1SEL_TIMCLK; + writel(scctrl, MMIO_P2V(V2M_SYSCTL + SCCTRL)); + writel(0, MMIO_P2V(V2M_TIMER0) + TIMER_CTRL); writel(0, MMIO_P2V(V2M_TIMER1) + TIMER_CTRL); -- cgit v0.10.2 From 03399c1cb4e2503e92d10c1ce38ac2e69b7d2380 Mon Sep 17 00:00:00 2001 From: Russell King Date: Tue, 25 Jan 2011 10:35:36 +0000 Subject: ARM: twd: ensure timer reload is reprogrammed on entry to periodic mode Ensure that the twd timer reload value is reprogrammed each time we enter periodic mode. This ensures that the reload value is always reset correctly. Tested-by: Santosh Shilimkar Acked-by: Colin Cross Signed-off-by: Russell King diff --git a/arch/arm/kernel/smp_twd.c b/arch/arm/kernel/smp_twd.c index fd91566..60636f4 100644 --- a/arch/arm/kernel/smp_twd.c +++ b/arch/arm/kernel/smp_twd.c @@ -36,6 +36,7 @@ static void twd_set_mode(enum clock_event_mode mode, /* timer load already set up */ ctrl = TWD_TIMER_CONTROL_ENABLE | TWD_TIMER_CONTROL_IT_ENABLE | TWD_TIMER_CONTROL_PERIODIC; + __raw_writel(twd_timer_rate / HZ, twd_base + TWD_TIMER_LOAD); break; case CLOCK_EVT_MODE_ONESHOT: /* period set, and timer enabled in 'next_event' hook */ @@ -81,7 +82,7 @@ int twd_timer_ack(void) static void __cpuinit twd_calibrate_rate(void) { - unsigned long load, count; + unsigned long count; u64 waitjiffies; /* @@ -116,10 +117,6 @@ static void __cpuinit twd_calibrate_rate(void) printk("%lu.%02luMHz.\n", twd_timer_rate / 1000000, (twd_timer_rate / 1000000) % 100); } - - load = twd_timer_rate / HZ; - - __raw_writel(load, twd_base + TWD_TIMER_LOAD); } /* -- cgit v0.10.2 From 05b112ff98070dc1f3293e8cd8e4c6f468d1084a Mon Sep 17 00:00:00 2001 From: Catalin Marinas Date: Tue, 25 Jan 2011 11:18:25 +0100 Subject: ARM: 6637/1: Make the argument to virt_to_phys() "const volatile" Changing the virt_to_phys() argument to "const volatile void *" avoids compiler warnings in some situations where this function is used. Signed-off-by: Catalin Marinas Acked-by: Stephen Boyd Acked-by: Arnd Bergmann Signed-off-by: Russell King diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h index 23c2e8e..d0ee74b 100644 --- a/arch/arm/include/asm/memory.h +++ b/arch/arm/include/asm/memory.h @@ -188,7 +188,7 @@ * translation for translating DMA addresses. Use the driver * DMA support - see dma-mapping.h. */ -static inline unsigned long virt_to_phys(void *x) +static inline unsigned long virt_to_phys(const volatile void *x) { return __virt_to_phys((unsigned long)(x)); } -- cgit v0.10.2 From fd015480c29deb52ae3bfaf41e888c450765edd8 Mon Sep 17 00:00:00 2001 From: Hartley Sweeten Date: Tue, 25 Jan 2011 01:05:35 +0100 Subject: ARM: 6636/1: ep93xx: default multiplexed gpio ports to gpio mode MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The EP93xx C and D GPIO ports are multiplexed with the Keypad Interface peripheral.  At power-up they default into non-GPIO mode with the Key Matrix controller enabled so these ports are unusable for GPIO.  Note that the Keypad Interface peripheral is only available in the EP9307, EP9312, and EP9315 processor variants. The keypad support will clear the DeviceConfig bits appropriately to enable the Keypad Interface when the driver is loaded.  And, when the driver is unloaded it will set the bits to return the ports to GPIO mode. To make these ports available for GPIO after power-up on all EP93xx processor variants, set the KEYS and GONK bits in the DeviceConfig register. Similarly, the E, G, and H ports are multiplexed with the IDE Interface peripheral.  At power-up these also default into non-GPIO mode.  Note that the IDE peripheral is only available in the EP9312 and EP9315 processor variants. Since an IDE driver is not even available in mainline, set the EONIDE, GONIDE, and HONIDE bits in the DeviceConfig register so that these ports will be available for GPIO use after power-up. Signed-off-by: H Hartley Sweeten Acked-by: Ryan Mallon Signed-off-by: Russell King diff --git a/arch/arm/mach-ep93xx/gpio.c b/arch/arm/mach-ep93xx/gpio.c index f3dc76f..bec34b8 100644 --- a/arch/arm/mach-ep93xx/gpio.c +++ b/arch/arm/mach-ep93xx/gpio.c @@ -427,6 +427,13 @@ void __init ep93xx_gpio_init(void) { int i; + /* Set Ports C, D, E, G, and H for GPIO use */ + ep93xx_devcfg_set_bits(EP93XX_SYSCON_DEVCFG_KEYS | + EP93XX_SYSCON_DEVCFG_GONK | + EP93XX_SYSCON_DEVCFG_EONIDE | + EP93XX_SYSCON_DEVCFG_GONIDE | + EP93XX_SYSCON_DEVCFG_HONIDE); + for (i = 0; i < ARRAY_SIZE(ep93xx_gpio_banks); i++) gpiochip_add(&ep93xx_gpio_banks[i].chip); } -- cgit v0.10.2 From 69058cd6d10423126ab6aeb568f4af2bd34c49fe Mon Sep 17 00:00:00 2001 From: Russell King Date: Wed, 12 Jan 2011 23:17:24 +0000 Subject: ALSA: AACI: fix timeout condition checking Ensure that a timeout coincident with the condition being waited for results in success rather than failure. This helps avoid timeout conditions being inappropriately flagged. Signed-off-by: Russell King diff --git a/sound/arm/aaci.c b/sound/arm/aaci.c index 91acc9a..21ff629 100644 --- a/sound/arm/aaci.c +++ b/sound/arm/aaci.c @@ -88,7 +88,7 @@ static void aaci_ac97_write(struct snd_ac97 *ac97, unsigned short reg, v = readl(aaci->base + AACI_SLFR); } while ((v & (SLFR_1TXB|SLFR_2TXB)) && --timeout); - if (!timeout) + if (v & (SLFR_1TXB|SLFR_2TXB)) dev_err(&aaci->dev->dev, "timeout waiting for write to complete\n"); @@ -124,7 +124,7 @@ static unsigned short aaci_ac97_read(struct snd_ac97 *ac97, unsigned short reg) v = readl(aaci->base + AACI_SLFR); } while ((v & SLFR_1TXB) && --timeout); - if (!timeout) { + if (v & SLFR_1TXB) { dev_err(&aaci->dev->dev, "timeout on slot 1 TX busy\n"); v = ~0; goto out; @@ -145,7 +145,7 @@ static unsigned short aaci_ac97_read(struct snd_ac97 *ac97, unsigned short reg) v = readl(aaci->base + AACI_SLFR) & (SLFR_1RXV|SLFR_2RXV); } while ((v != (SLFR_1RXV|SLFR_2RXV)) && --timeout); - if (!timeout) { + if (v != (SLFR_1RXV|SLFR_2RXV)) { dev_err(&aaci->dev->dev, "timeout on RX valid\n"); v = ~0; goto out; -- cgit v0.10.2 From 250c7a61c35a258e2422b3d55c61bfbad33326be Mon Sep 17 00:00:00 2001 From: Russell King Date: Wed, 12 Jan 2011 23:42:57 +0000 Subject: ALSA: AACI: fix timeout duration Relying on the access time of peripherals is unreliable - it depends on the speed of the CPU and the bus. On Versatile Express, these timeouts were expiring, causing the driver to fail. Add udelay(1) to ensure that they don't expire early, and adjust timeouts to give a reasonable margin over the response times. Signed-off-by: Russell King diff --git a/sound/arm/aaci.c b/sound/arm/aaci.c index 21ff629..24d3013 100644 --- a/sound/arm/aaci.c +++ b/sound/arm/aaci.c @@ -30,6 +30,8 @@ #define DRIVER_NAME "aaci-pl041" +#define FRAME_PERIOD_US 21 + /* * PM support is not complete. Turn it off. */ @@ -64,8 +66,8 @@ static void aaci_ac97_write(struct snd_ac97 *ac97, unsigned short reg, unsigned short val) { struct aaci *aaci = ac97->private_data; + int timeout; u32 v; - int timeout = 5000; if (ac97->num >= 4) return; @@ -81,10 +83,13 @@ static void aaci_ac97_write(struct snd_ac97 *ac97, unsigned short reg, writel(val << 4, aaci->base + AACI_SL2TX); writel(reg << 12, aaci->base + AACI_SL1TX); - /* - * Wait for the transmission of both slots to complete. - */ + /* Initially, wait one frame period */ + udelay(FRAME_PERIOD_US); + + /* And then wait an additional eight frame periods for it to be sent */ + timeout = FRAME_PERIOD_US * 8; do { + udelay(1); v = readl(aaci->base + AACI_SLFR); } while ((v & (SLFR_1TXB|SLFR_2TXB)) && --timeout); @@ -101,9 +106,8 @@ static void aaci_ac97_write(struct snd_ac97 *ac97, unsigned short reg, static unsigned short aaci_ac97_read(struct snd_ac97 *ac97, unsigned short reg) { struct aaci *aaci = ac97->private_data; + int timeout, retries = 10; u32 v; - int timeout = 5000; - int retries = 10; if (ac97->num >= 4) return ~0; @@ -117,10 +121,13 @@ static unsigned short aaci_ac97_read(struct snd_ac97 *ac97, unsigned short reg) */ writel((reg << 12) | (1 << 19), aaci->base + AACI_SL1TX); - /* - * Wait for the transmission to complete. - */ + /* Initially, wait one frame period */ + udelay(FRAME_PERIOD_US); + + /* And then wait an additional eight frame periods for it to be sent */ + timeout = FRAME_PERIOD_US * 8; do { + udelay(1); v = readl(aaci->base + AACI_SLFR); } while ((v & SLFR_1TXB) && --timeout); @@ -130,17 +137,13 @@ static unsigned short aaci_ac97_read(struct snd_ac97 *ac97, unsigned short reg) goto out; } - /* - * Give the AC'97 codec more than enough time - * to respond. (42us = ~2 frames at 48kHz.) - */ - udelay(42); + /* Now wait for the response frame */ + udelay(FRAME_PERIOD_US); - /* - * Wait for slot 2 to indicate data. - */ - timeout = 5000; + /* And then wait an additional eight frame periods for data */ + timeout = FRAME_PERIOD_US * 8; do { + udelay(1); cond_resched(); v = readl(aaci->base + AACI_SLFR) & (SLFR_1RXV|SLFR_2RXV); } while ((v != (SLFR_1RXV|SLFR_2RXV)) && --timeout); @@ -179,6 +182,7 @@ aaci_chan_wait_ready(struct aaci_runtime *aacirun, unsigned long mask) int timeout = 5000; do { + udelay(1); val = readl(aacirun->base + AACI_SR); } while (val & mask && timeout--); } @@ -874,7 +878,7 @@ static int __devinit aaci_probe_ac97(struct aaci *aaci) * Give the AC'97 codec more than enough time * to wake up. (42us = ~2 frames at 48kHz.) */ - udelay(42); + udelay(FRAME_PERIOD_US * 2); ret = snd_ac97_bus(aaci->card, 0, &aaci_bus_ops, aaci, &ac97_bus); if (ret) -- cgit v0.10.2