From 7160fc13e36f2321bf89d05264fd5d97dddf78d3 Mon Sep 17 00:00:00 2001 From: Bob Liu Date: Sat, 25 Sep 2010 10:32:38 +0000 Subject: bfin_sport: add support for ADC/DAC. In order to support ADC/DAC demo, add NDSO_MODE mode to bfin_sport.c. After that userspace apps like ndso/awg can work fine. Signed-off-by: Bob Liu diff --git a/arch/blackfin/include/asm/bfin_sport.h b/arch/blackfin/include/asm/bfin_sport.h index f8568a3..0afcfbd 100644 --- a/arch/blackfin/include/asm/bfin_sport.h +++ b/arch/blackfin/include/asm/bfin_sport.h @@ -13,6 +13,7 @@ #define NORM_MODE 0x0 #define TDM_MODE 0x1 #define I2S_MODE 0x2 +#define NDSO_MODE 0x3 /* Data format, normal, a-law or u-law */ #define NORM_FORMAT 0x0 @@ -56,6 +57,8 @@ struct sport_config { /* Userspace interface */ #define SPORT_IOC_MAGIC 'P' #define SPORT_IOC_CONFIG _IOWR('P', 0x01, struct sport_config) +#define SPORT_IOC_GET_SYSTEMCLOCK _IOR('P', 0x02, unsigned long) +#define SPORT_IOC_SET_BAUDRATE _IOW('P', 0x03, unsigned long) #ifdef __KERNEL__ -- cgit v0.10.2 From c72df808d6a89f859ae37b9490af04f3dddcd40e Mon Sep 17 00:00:00 2001 From: Steven Miao Date: Tue, 11 Jan 2011 09:18:48 +0000 Subject: BF561 MDMA : fixed BF561 DMA MMRs definition mismatch MDMA io base defined in arch/blackfin/mach-bf561/dma.c do not match the definition of MDMA MMRs in arch/blackfin/mach-bf561/include/mach/defBF561.h Signed-off-by: Steven Miao Signed-off-by: Bob Liu diff --git a/arch/blackfin/mach-bf561/include/mach/defBF561.h b/arch/blackfin/mach-bf561/include/mach/defBF561.h index 71e805e..7d712ae 100644 --- a/arch/blackfin/mach-bf561/include/mach/defBF561.h +++ b/arch/blackfin/mach-bf561/include/mach/defBF561.h @@ -479,61 +479,61 @@ #define DMA1_11_PERIPHERAL_MAP 0xFFC01EEC /* DMA1 Channel 11 Peripheral Map Register */ /* Memory DMA1 Controller registers (0xFFC0 1E80-0xFFC0 1FFF) */ -#define MDMA_D2_CONFIG 0xFFC01F08 /*MemDMA1 Stream 0 Destination Configuration */ -#define MDMA_D2_NEXT_DESC_PTR 0xFFC01F00 /*MemDMA1 Stream 0 Destination Next Descriptor Ptr Reg */ -#define MDMA_D2_START_ADDR 0xFFC01F04 /*MemDMA1 Stream 0 Destination Start Address */ -#define MDMA_D2_X_COUNT 0xFFC01F10 /*MemDMA1 Stream 0 Destination Inner-Loop Count */ -#define MDMA_D2_Y_COUNT 0xFFC01F18 /*MemDMA1 Stream 0 Destination Outer-Loop Count */ -#define MDMA_D2_X_MODIFY 0xFFC01F14 /*MemDMA1 Stream 0 Dest Inner-Loop Address-Increment */ -#define MDMA_D2_Y_MODIFY 0xFFC01F1C /*MemDMA1 Stream 0 Dest Outer-Loop Address-Increment */ -#define MDMA_D2_CURR_DESC_PTR 0xFFC01F20 /*MemDMA1 Stream 0 Dest Current Descriptor Ptr reg */ -#define MDMA_D2_CURR_ADDR 0xFFC01F24 /*MemDMA1 Stream 0 Destination Current Address */ -#define MDMA_D2_CURR_X_COUNT 0xFFC01F30 /*MemDMA1 Stream 0 Dest Current Inner-Loop Count */ -#define MDMA_D2_CURR_Y_COUNT 0xFFC01F38 /*MemDMA1 Stream 0 Dest Current Outer-Loop Count */ -#define MDMA_D2_IRQ_STATUS 0xFFC01F28 /*MemDMA1 Stream 0 Destination Interrupt/Status */ -#define MDMA_D2_PERIPHERAL_MAP 0xFFC01F2C /*MemDMA1 Stream 0 Destination Peripheral Map */ - -#define MDMA_S2_CONFIG 0xFFC01F48 /*MemDMA1 Stream 0 Source Configuration */ -#define MDMA_S2_NEXT_DESC_PTR 0xFFC01F40 /*MemDMA1 Stream 0 Source Next Descriptor Ptr Reg */ -#define MDMA_S2_START_ADDR 0xFFC01F44 /*MemDMA1 Stream 0 Source Start Address */ -#define MDMA_S2_X_COUNT 0xFFC01F50 /*MemDMA1 Stream 0 Source Inner-Loop Count */ -#define MDMA_S2_Y_COUNT 0xFFC01F58 /*MemDMA1 Stream 0 Source Outer-Loop Count */ -#define MDMA_S2_X_MODIFY 0xFFC01F54 /*MemDMA1 Stream 0 Source Inner-Loop Address-Increment */ -#define MDMA_S2_Y_MODIFY 0xFFC01F5C /*MemDMA1 Stream 0 Source Outer-Loop Address-Increment */ -#define MDMA_S2_CURR_DESC_PTR 0xFFC01F60 /*MemDMA1 Stream 0 Source Current Descriptor Ptr reg */ -#define MDMA_S2_CURR_ADDR 0xFFC01F64 /*MemDMA1 Stream 0 Source Current Address */ -#define MDMA_S2_CURR_X_COUNT 0xFFC01F70 /*MemDMA1 Stream 0 Source Current Inner-Loop Count */ -#define MDMA_S2_CURR_Y_COUNT 0xFFC01F78 /*MemDMA1 Stream 0 Source Current Outer-Loop Count */ -#define MDMA_S2_IRQ_STATUS 0xFFC01F68 /*MemDMA1 Stream 0 Source Interrupt/Status */ -#define MDMA_S2_PERIPHERAL_MAP 0xFFC01F6C /*MemDMA1 Stream 0 Source Peripheral Map */ - -#define MDMA_D3_CONFIG 0xFFC01F88 /*MemDMA1 Stream 1 Destination Configuration */ -#define MDMA_D3_NEXT_DESC_PTR 0xFFC01F80 /*MemDMA1 Stream 1 Destination Next Descriptor Ptr Reg */ -#define MDMA_D3_START_ADDR 0xFFC01F84 /*MemDMA1 Stream 1 Destination Start Address */ -#define MDMA_D3_X_COUNT 0xFFC01F90 /*MemDMA1 Stream 1 Destination Inner-Loop Count */ -#define MDMA_D3_Y_COUNT 0xFFC01F98 /*MemDMA1 Stream 1 Destination Outer-Loop Count */ -#define MDMA_D3_X_MODIFY 0xFFC01F94 /*MemDMA1 Stream 1 Dest Inner-Loop Address-Increment */ -#define MDMA_D3_Y_MODIFY 0xFFC01F9C /*MemDMA1 Stream 1 Dest Outer-Loop Address-Increment */ -#define MDMA_D3_CURR_DESC_PTR 0xFFC01FA0 /*MemDMA1 Stream 1 Dest Current Descriptor Ptr reg */ -#define MDMA_D3_CURR_ADDR 0xFFC01FA4 /*MemDMA1 Stream 1 Dest Current Address */ -#define MDMA_D3_CURR_X_COUNT 0xFFC01FB0 /*MemDMA1 Stream 1 Dest Current Inner-Loop Count */ -#define MDMA_D3_CURR_Y_COUNT 0xFFC01FB8 /*MemDMA1 Stream 1 Dest Current Outer-Loop Count */ -#define MDMA_D3_IRQ_STATUS 0xFFC01FA8 /*MemDMA1 Stream 1 Dest Interrupt/Status */ -#define MDMA_D3_PERIPHERAL_MAP 0xFFC01FAC /*MemDMA1 Stream 1 Dest Peripheral Map */ - -#define MDMA_S3_CONFIG 0xFFC01FC8 /*MemDMA1 Stream 1 Source Configuration */ -#define MDMA_S3_NEXT_DESC_PTR 0xFFC01FC0 /*MemDMA1 Stream 1 Source Next Descriptor Ptr Reg */ -#define MDMA_S3_START_ADDR 0xFFC01FC4 /*MemDMA1 Stream 1 Source Start Address */ -#define MDMA_S3_X_COUNT 0xFFC01FD0 /*MemDMA1 Stream 1 Source Inner-Loop Count */ -#define MDMA_S3_Y_COUNT 0xFFC01FD8 /*MemDMA1 Stream 1 Source Outer-Loop Count */ -#define MDMA_S3_X_MODIFY 0xFFC01FD4 /*MemDMA1 Stream 1 Source Inner-Loop Address-Increment */ -#define MDMA_S3_Y_MODIFY 0xFFC01FDC /*MemDMA1 Stream 1 Source Outer-Loop Address-Increment */ -#define MDMA_S3_CURR_DESC_PTR 0xFFC01FE0 /*MemDMA1 Stream 1 Source Current Descriptor Ptr reg */ -#define MDMA_S3_CURR_ADDR 0xFFC01FE4 /*MemDMA1 Stream 1 Source Current Address */ -#define MDMA_S3_CURR_X_COUNT 0xFFC01FF0 /*MemDMA1 Stream 1 Source Current Inner-Loop Count */ -#define MDMA_S3_CURR_Y_COUNT 0xFFC01FF8 /*MemDMA1 Stream 1 Source Current Outer-Loop Count */ -#define MDMA_S3_IRQ_STATUS 0xFFC01FE8 /*MemDMA1 Stream 1 Source Interrupt/Status */ -#define MDMA_S3_PERIPHERAL_MAP 0xFFC01FEC /*MemDMA1 Stream 1 Source Peripheral Map */ +#define MDMA_D0_CONFIG 0xFFC01F08 /*MemDMA1 Stream 0 Destination Configuration */ +#define MDMA_D0_NEXT_DESC_PTR 0xFFC01F00 /*MemDMA1 Stream 0 Destination Next Descriptor Ptr Reg */ +#define MDMA_D0_START_ADDR 0xFFC01F04 /*MemDMA1 Stream 0 Destination Start Address */ +#define MDMA_D0_X_COUNT 0xFFC01F10 /*MemDMA1 Stream 0 Destination Inner-Loop Count */ +#define MDMA_D0_Y_COUNT 0xFFC01F18 /*MemDMA1 Stream 0 Destination Outer-Loop Count */ +#define MDMA_D0_X_MODIFY 0xFFC01F14 /*MemDMA1 Stream 0 Dest Inner-Loop Address-Increment */ +#define MDMA_D0_Y_MODIFY 0xFFC01F1C /*MemDMA1 Stream 0 Dest Outer-Loop Address-Increment */ +#define MDMA_D0_CURR_DESC_PTR 0xFFC01F20 /*MemDMA1 Stream 0 Dest Current Descriptor Ptr reg */ +#define MDMA_D0_CURR_ADDR 0xFFC01F24 /*MemDMA1 Stream 0 Destination Current Address */ +#define MDMA_D0_CURR_X_COUNT 0xFFC01F30 /*MemDMA1 Stream 0 Dest Current Inner-Loop Count */ +#define MDMA_D0_CURR_Y_COUNT 0xFFC01F38 /*MemDMA1 Stream 0 Dest Current Outer-Loop Count */ +#define MDMA_D0_IRQ_STATUS 0xFFC01F28 /*MemDMA1 Stream 0 Destination Interrupt/Status */ +#define MDMA_D0_PERIPHERAL_MAP 0xFFC01F2C /*MemDMA1 Stream 0 Destination Peripheral Map */ + +#define MDMA_S0_CONFIG 0xFFC01F48 /*MemDMA1 Stream 0 Source Configuration */ +#define MDMA_S0_NEXT_DESC_PTR 0xFFC01F40 /*MemDMA1 Stream 0 Source Next Descriptor Ptr Reg */ +#define MDMA_S0_START_ADDR 0xFFC01F44 /*MemDMA1 Stream 0 Source Start Address */ +#define MDMA_S0_X_COUNT 0xFFC01F50 /*MemDMA1 Stream 0 Source Inner-Loop Count */ +#define MDMA_S0_Y_COUNT 0xFFC01F58 /*MemDMA1 Stream 0 Source Outer-Loop Count */ +#define MDMA_S0_X_MODIFY 0xFFC01F54 /*MemDMA1 Stream 0 Source Inner-Loop Address-Increment */ +#define MDMA_S0_Y_MODIFY 0xFFC01F5C /*MemDMA1 Stream 0 Source Outer-Loop Address-Increment */ +#define MDMA_S0_CURR_DESC_PTR 0xFFC01F60 /*MemDMA1 Stream 0 Source Current Descriptor Ptr reg */ +#define MDMA_S0_CURR_ADDR 0xFFC01F64 /*MemDMA1 Stream 0 Source Current Address */ +#define MDMA_S0_CURR_X_COUNT 0xFFC01F70 /*MemDMA1 Stream 0 Source Current Inner-Loop Count */ +#define MDMA_S0_CURR_Y_COUNT 0xFFC01F78 /*MemDMA1 Stream 0 Source Current Outer-Loop Count */ +#define MDMA_S0_IRQ_STATUS 0xFFC01F68 /*MemDMA1 Stream 0 Source Interrupt/Status */ +#define MDMA_S0_PERIPHERAL_MAP 0xFFC01F6C /*MemDMA1 Stream 0 Source Peripheral Map */ + +#define MDMA_D1_CONFIG 0xFFC01F88 /*MemDMA1 Stream 1 Destination Configuration */ +#define MDMA_D1_NEXT_DESC_PTR 0xFFC01F80 /*MemDMA1 Stream 1 Destination Next Descriptor Ptr Reg */ +#define MDMA_D1_START_ADDR 0xFFC01F84 /*MemDMA1 Stream 1 Destination Start Address */ +#define MDMA_D1_X_COUNT 0xFFC01F90 /*MemDMA1 Stream 1 Destination Inner-Loop Count */ +#define MDMA_D1_Y_COUNT 0xFFC01F98 /*MemDMA1 Stream 1 Destination Outer-Loop Count */ +#define MDMA_D1_X_MODIFY 0xFFC01F94 /*MemDMA1 Stream 1 Dest Inner-Loop Address-Increment */ +#define MDMA_D1_Y_MODIFY 0xFFC01F9C /*MemDMA1 Stream 1 Dest Outer-Loop Address-Increment */ +#define MDMA_D1_CURR_DESC_PTR 0xFFC01FA0 /*MemDMA1 Stream 1 Dest Current Descriptor Ptr reg */ +#define MDMA_D1_CURR_ADDR 0xFFC01FA4 /*MemDMA1 Stream 1 Dest Current Address */ +#define MDMA_D1_CURR_X_COUNT 0xFFC01FB0 /*MemDMA1 Stream 1 Dest Current Inner-Loop Count */ +#define MDMA_D1_CURR_Y_COUNT 0xFFC01FB8 /*MemDMA1 Stream 1 Dest Current Outer-Loop Count */ +#define MDMA_D1_IRQ_STATUS 0xFFC01FA8 /*MemDMA1 Stream 1 Dest Interrupt/Status */ +#define MDMA_D1_PERIPHERAL_MAP 0xFFC01FAC /*MemDMA1 Stream 1 Dest Peripheral Map */ + +#define MDMA_S1_CONFIG 0xFFC01FC8 /*MemDMA1 Stream 1 Source Configuration */ +#define MDMA_S1_NEXT_DESC_PTR 0xFFC01FC0 /*MemDMA1 Stream 1 Source Next Descriptor Ptr Reg */ +#define MDMA_S1_START_ADDR 0xFFC01FC4 /*MemDMA1 Stream 1 Source Start Address */ +#define MDMA_S1_X_COUNT 0xFFC01FD0 /*MemDMA1 Stream 1 Source Inner-Loop Count */ +#define MDMA_S1_Y_COUNT 0xFFC01FD8 /*MemDMA1 Stream 1 Source Outer-Loop Count */ +#define MDMA_S1_X_MODIFY 0xFFC01FD4 /*MemDMA1 Stream 1 Source Inner-Loop Address-Increment */ +#define MDMA_S1_Y_MODIFY 0xFFC01FDC /*MemDMA1 Stream 1 Source Outer-Loop Address-Increment */ +#define MDMA_S1_CURR_DESC_PTR 0xFFC01FE0 /*MemDMA1 Stream 1 Source Current Descriptor Ptr reg */ +#define MDMA_S1_CURR_ADDR 0xFFC01FE4 /*MemDMA1 Stream 1 Source Current Address */ +#define MDMA_S1_CURR_X_COUNT 0xFFC01FF0 /*MemDMA1 Stream 1 Source Current Inner-Loop Count */ +#define MDMA_S1_CURR_Y_COUNT 0xFFC01FF8 /*MemDMA1 Stream 1 Source Current Outer-Loop Count */ +#define MDMA_S1_IRQ_STATUS 0xFFC01FE8 /*MemDMA1 Stream 1 Source Interrupt/Status */ +#define MDMA_S1_PERIPHERAL_MAP 0xFFC01FEC /*MemDMA1 Stream 1 Source Peripheral Map */ /* DMA2 Controller registers (0xFFC0 0C00-0xFFC0 0DFF) */ #define DMA2_0_CONFIG 0xFFC00C08 /* DMA2 Channel 0 Configuration register */ @@ -705,61 +705,61 @@ #define DMA2_11_PERIPHERAL_MAP 0xFFC00EEC /* DMA2 Channel 11 Peripheral Map Register */ /* Memory DMA2 Controller registers (0xFFC0 0E80-0xFFC0 0FFF) */ -#define MDMA_D0_CONFIG 0xFFC00F08 /*MemDMA2 Stream 0 Destination Configuration register */ -#define MDMA_D0_NEXT_DESC_PTR 0xFFC00F00 /*MemDMA2 Stream 0 Destination Next Descriptor Ptr Reg */ -#define MDMA_D0_START_ADDR 0xFFC00F04 /*MemDMA2 Stream 0 Destination Start Address */ -#define MDMA_D0_X_COUNT 0xFFC00F10 /*MemDMA2 Stream 0 Dest Inner-Loop Count register */ -#define MDMA_D0_Y_COUNT 0xFFC00F18 /*MemDMA2 Stream 0 Dest Outer-Loop Count register */ -#define MDMA_D0_X_MODIFY 0xFFC00F14 /*MemDMA2 Stream 0 Dest Inner-Loop Address-Increment */ -#define MDMA_D0_Y_MODIFY 0xFFC00F1C /*MemDMA2 Stream 0 Dest Outer-Loop Address-Increment */ -#define MDMA_D0_CURR_DESC_PTR 0xFFC00F20 /*MemDMA2 Stream 0 Dest Current Descriptor Ptr reg */ -#define MDMA_D0_CURR_ADDR 0xFFC00F24 /*MemDMA2 Stream 0 Destination Current Address */ -#define MDMA_D0_CURR_X_COUNT 0xFFC00F30 /*MemDMA2 Stream 0 Dest Current Inner-Loop Count reg */ -#define MDMA_D0_CURR_Y_COUNT 0xFFC00F38 /*MemDMA2 Stream 0 Dest Current Outer-Loop Count reg */ -#define MDMA_D0_IRQ_STATUS 0xFFC00F28 /*MemDMA2 Stream 0 Dest Interrupt/Status Register */ -#define MDMA_D0_PERIPHERAL_MAP 0xFFC00F2C /*MemDMA2 Stream 0 Destination Peripheral Map register */ - -#define MDMA_S0_CONFIG 0xFFC00F48 /*MemDMA2 Stream 0 Source Configuration register */ -#define MDMA_S0_NEXT_DESC_PTR 0xFFC00F40 /*MemDMA2 Stream 0 Source Next Descriptor Ptr Reg */ -#define MDMA_S0_START_ADDR 0xFFC00F44 /*MemDMA2 Stream 0 Source Start Address */ -#define MDMA_S0_X_COUNT 0xFFC00F50 /*MemDMA2 Stream 0 Source Inner-Loop Count register */ -#define MDMA_S0_Y_COUNT 0xFFC00F58 /*MemDMA2 Stream 0 Source Outer-Loop Count register */ -#define MDMA_S0_X_MODIFY 0xFFC00F54 /*MemDMA2 Stream 0 Src Inner-Loop Addr-Increment reg */ -#define MDMA_S0_Y_MODIFY 0xFFC00F5C /*MemDMA2 Stream 0 Src Outer-Loop Addr-Increment reg */ -#define MDMA_S0_CURR_DESC_PTR 0xFFC00F60 /*MemDMA2 Stream 0 Source Current Descriptor Ptr reg */ -#define MDMA_S0_CURR_ADDR 0xFFC00F64 /*MemDMA2 Stream 0 Source Current Address */ -#define MDMA_S0_CURR_X_COUNT 0xFFC00F70 /*MemDMA2 Stream 0 Src Current Inner-Loop Count reg */ -#define MDMA_S0_CURR_Y_COUNT 0xFFC00F78 /*MemDMA2 Stream 0 Src Current Outer-Loop Count reg */ -#define MDMA_S0_IRQ_STATUS 0xFFC00F68 /*MemDMA2 Stream 0 Source Interrupt/Status Register */ -#define MDMA_S0_PERIPHERAL_MAP 0xFFC00F6C /*MemDMA2 Stream 0 Source Peripheral Map register */ - -#define MDMA_D1_CONFIG 0xFFC00F88 /*MemDMA2 Stream 1 Destination Configuration register */ -#define MDMA_D1_NEXT_DESC_PTR 0xFFC00F80 /*MemDMA2 Stream 1 Destination Next Descriptor Ptr Reg */ -#define MDMA_D1_START_ADDR 0xFFC00F84 /*MemDMA2 Stream 1 Destination Start Address */ -#define MDMA_D1_X_COUNT 0xFFC00F90 /*MemDMA2 Stream 1 Dest Inner-Loop Count register */ -#define MDMA_D1_Y_COUNT 0xFFC00F98 /*MemDMA2 Stream 1 Dest Outer-Loop Count register */ -#define MDMA_D1_X_MODIFY 0xFFC00F94 /*MemDMA2 Stream 1 Dest Inner-Loop Address-Increment */ -#define MDMA_D1_Y_MODIFY 0xFFC00F9C /*MemDMA2 Stream 1 Dest Outer-Loop Address-Increment */ -#define MDMA_D1_CURR_DESC_PTR 0xFFC00FA0 /*MemDMA2 Stream 1 Destination Current Descriptor Ptr */ -#define MDMA_D1_CURR_ADDR 0xFFC00FA4 /*MemDMA2 Stream 1 Destination Current Address reg */ -#define MDMA_D1_CURR_X_COUNT 0xFFC00FB0 /*MemDMA2 Stream 1 Dest Current Inner-Loop Count reg */ -#define MDMA_D1_CURR_Y_COUNT 0xFFC00FB8 /*MemDMA2 Stream 1 Dest Current Outer-Loop Count reg */ -#define MDMA_D1_IRQ_STATUS 0xFFC00FA8 /*MemDMA2 Stream 1 Destination Interrupt/Status Reg */ -#define MDMA_D1_PERIPHERAL_MAP 0xFFC00FAC /*MemDMA2 Stream 1 Destination Peripheral Map register */ - -#define MDMA_S1_CONFIG 0xFFC00FC8 /*MemDMA2 Stream 1 Source Configuration register */ -#define MDMA_S1_NEXT_DESC_PTR 0xFFC00FC0 /*MemDMA2 Stream 1 Source Next Descriptor Ptr Reg */ -#define MDMA_S1_START_ADDR 0xFFC00FC4 /*MemDMA2 Stream 1 Source Start Address */ -#define MDMA_S1_X_COUNT 0xFFC00FD0 /*MemDMA2 Stream 1 Source Inner-Loop Count register */ -#define MDMA_S1_Y_COUNT 0xFFC00FD8 /*MemDMA2 Stream 1 Source Outer-Loop Count register */ -#define MDMA_S1_X_MODIFY 0xFFC00FD4 /*MemDMA2 Stream 1 Src Inner-Loop Address-Increment */ -#define MDMA_S1_Y_MODIFY 0xFFC00FDC /*MemDMA2 Stream 1 Source Outer-Loop Address-Increment */ -#define MDMA_S1_CURR_DESC_PTR 0xFFC00FE0 /*MemDMA2 Stream 1 Source Current Descriptor Ptr reg */ -#define MDMA_S1_CURR_ADDR 0xFFC00FE4 /*MemDMA2 Stream 1 Source Current Address */ -#define MDMA_S1_CURR_X_COUNT 0xFFC00FF0 /*MemDMA2 Stream 1 Source Current Inner-Loop Count */ -#define MDMA_S1_CURR_Y_COUNT 0xFFC00FF8 /*MemDMA2 Stream 1 Source Current Outer-Loop Count */ -#define MDMA_S1_IRQ_STATUS 0xFFC00FE8 /*MemDMA2 Stream 1 Source Interrupt/Status Register */ -#define MDMA_S1_PERIPHERAL_MAP 0xFFC00FEC /*MemDMA2 Stream 1 Source Peripheral Map register */ +#define MDMA_D2_CONFIG 0xFFC00F08 /*MemDMA2 Stream 0 Destination Configuration register */ +#define MDMA_D2_NEXT_DESC_PTR 0xFFC00F00 /*MemDMA2 Stream 0 Destination Next Descriptor Ptr Reg */ +#define MDMA_D2_START_ADDR 0xFFC00F04 /*MemDMA2 Stream 0 Destination Start Address */ +#define MDMA_D2_X_COUNT 0xFFC00F10 /*MemDMA2 Stream 0 Dest Inner-Loop Count register */ +#define MDMA_D2_Y_COUNT 0xFFC00F18 /*MemDMA2 Stream 0 Dest Outer-Loop Count register */ +#define MDMA_D2_X_MODIFY 0xFFC00F14 /*MemDMA2 Stream 0 Dest Inner-Loop Address-Increment */ +#define MDMA_D2_Y_MODIFY 0xFFC00F1C /*MemDMA2 Stream 0 Dest Outer-Loop Address-Increment */ +#define MDMA_D2_CURR_DESC_PTR 0xFFC00F20 /*MemDMA2 Stream 0 Dest Current Descriptor Ptr reg */ +#define MDMA_D2_CURR_ADDR 0xFFC00F24 /*MemDMA2 Stream 0 Destination Current Address */ +#define MDMA_D2_CURR_X_COUNT 0xFFC00F30 /*MemDMA2 Stream 0 Dest Current Inner-Loop Count reg */ +#define MDMA_D2_CURR_Y_COUNT 0xFFC00F38 /*MemDMA2 Stream 0 Dest Current Outer-Loop Count reg */ +#define MDMA_D2_IRQ_STATUS 0xFFC00F28 /*MemDMA2 Stream 0 Dest Interrupt/Status Register */ +#define MDMA_D2_PERIPHERAL_MAP 0xFFC00F2C /*MemDMA2 Stream 0 Destination Peripheral Map register */ + +#define MDMA_S2_CONFIG 0xFFC00F48 /*MemDMA2 Stream 0 Source Configuration register */ +#define MDMA_S2_NEXT_DESC_PTR 0xFFC00F40 /*MemDMA2 Stream 0 Source Next Descriptor Ptr Reg */ +#define MDMA_S2_START_ADDR 0xFFC00F44 /*MemDMA2 Stream 0 Source Start Address */ +#define MDMA_S2_X_COUNT 0xFFC00F50 /*MemDMA2 Stream 0 Source Inner-Loop Count register */ +#define MDMA_S2_Y_COUNT 0xFFC00F58 /*MemDMA2 Stream 0 Source Outer-Loop Count register */ +#define MDMA_S2_X_MODIFY 0xFFC00F54 /*MemDMA2 Stream 0 Src Inner-Loop Addr-Increment reg */ +#define MDMA_S2_Y_MODIFY 0xFFC00F5C /*MemDMA2 Stream 0 Src Outer-Loop Addr-Increment reg */ +#define MDMA_S2_CURR_DESC_PTR 0xFFC00F60 /*MemDMA2 Stream 0 Source Current Descriptor Ptr reg */ +#define MDMA_S2_CURR_ADDR 0xFFC00F64 /*MemDMA2 Stream 0 Source Current Address */ +#define MDMA_S2_CURR_X_COUNT 0xFFC00F70 /*MemDMA2 Stream 0 Src Current Inner-Loop Count reg */ +#define MDMA_S2_CURR_Y_COUNT 0xFFC00F78 /*MemDMA2 Stream 0 Src Current Outer-Loop Count reg */ +#define MDMA_S2_IRQ_STATUS 0xFFC00F68 /*MemDMA2 Stream 0 Source Interrupt/Status Register */ +#define MDMA_S2_PERIPHERAL_MAP 0xFFC00F6C /*MemDMA2 Stream 0 Source Peripheral Map register */ + +#define MDMA_D3_CONFIG 0xFFC00F88 /*MemDMA2 Stream 1 Destination Configuration register */ +#define MDMA_D3_NEXT_DESC_PTR 0xFFC00F80 /*MemDMA2 Stream 1 Destination Next Descriptor Ptr Reg */ +#define MDMA_D3_START_ADDR 0xFFC00F84 /*MemDMA2 Stream 1 Destination Start Address */ +#define MDMA_D3_X_COUNT 0xFFC00F90 /*MemDMA2 Stream 1 Dest Inner-Loop Count register */ +#define MDMA_D3_Y_COUNT 0xFFC00F98 /*MemDMA2 Stream 1 Dest Outer-Loop Count register */ +#define MDMA_D3_X_MODIFY 0xFFC00F94 /*MemDMA2 Stream 1 Dest Inner-Loop Address-Increment */ +#define MDMA_D3_Y_MODIFY 0xFFC00F9C /*MemDMA2 Stream 1 Dest Outer-Loop Address-Increment */ +#define MDMA_D3_CURR_DESC_PTR 0xFFC00FA0 /*MemDMA2 Stream 1 Destination Current Descriptor Ptr */ +#define MDMA_D3_CURR_ADDR 0xFFC00FA4 /*MemDMA2 Stream 1 Destination Current Address reg */ +#define MDMA_D3_CURR_X_COUNT 0xFFC00FB0 /*MemDMA2 Stream 1 Dest Current Inner-Loop Count reg */ +#define MDMA_D3_CURR_Y_COUNT 0xFFC00FB8 /*MemDMA2 Stream 1 Dest Current Outer-Loop Count reg */ +#define MDMA_D3_IRQ_STATUS 0xFFC00FA8 /*MemDMA2 Stream 1 Destination Interrupt/Status Reg */ +#define MDMA_D3_PERIPHERAL_MAP 0xFFC00FAC /*MemDMA2 Stream 1 Destination Peripheral Map register */ + +#define MDMA_S3_CONFIG 0xFFC00FC8 /*MemDMA2 Stream 1 Source Configuration register */ +#define MDMA_S3_NEXT_DESC_PTR 0xFFC00FC0 /*MemDMA2 Stream 1 Source Next Descriptor Ptr Reg */ +#define MDMA_S3_START_ADDR 0xFFC00FC4 /*MemDMA2 Stream 1 Source Start Address */ +#define MDMA_S3_X_COUNT 0xFFC00FD0 /*MemDMA2 Stream 1 Source Inner-Loop Count register */ +#define MDMA_S3_Y_COUNT 0xFFC00FD8 /*MemDMA2 Stream 1 Source Outer-Loop Count register */ +#define MDMA_S3_X_MODIFY 0xFFC00FD4 /*MemDMA2 Stream 1 Src Inner-Loop Address-Increment */ +#define MDMA_S3_Y_MODIFY 0xFFC00FDC /*MemDMA2 Stream 1 Source Outer-Loop Address-Increment */ +#define MDMA_S3_CURR_DESC_PTR 0xFFC00FE0 /*MemDMA2 Stream 1 Source Current Descriptor Ptr reg */ +#define MDMA_S3_CURR_ADDR 0xFFC00FE4 /*MemDMA2 Stream 1 Source Current Address */ +#define MDMA_S3_CURR_X_COUNT 0xFFC00FF0 /*MemDMA2 Stream 1 Source Current Inner-Loop Count */ +#define MDMA_S3_CURR_Y_COUNT 0xFFC00FF8 /*MemDMA2 Stream 1 Source Current Outer-Loop Count */ +#define MDMA_S3_IRQ_STATUS 0xFFC00FE8 /*MemDMA2 Stream 1 Source Interrupt/Status Register */ +#define MDMA_S3_PERIPHERAL_MAP 0xFFC00FEC /*MemDMA2 Stream 1 Source Peripheral Map register */ /* Internal Memory DMA Registers (0xFFC0_1800 - 0xFFC0_19FF) */ #define IMDMA_D0_CONFIG 0xFFC01808 /*IMDMA Stream 0 Destination Configuration */ -- cgit v0.10.2 From f7899f7c1fff3c68f0c896e38714d489845cef57 Mon Sep 17 00:00:00 2001 From: Steven Miao Date: Wed, 11 Jan 2012 14:00:47 +0800 Subject: blackfin: timer: refine bfin simple timer driver Add ioctl cmd for gptimer test app and do some codecleanup(remove spaces). Signed-off-by: Steven Miao Signed-off-by: Bob Liu diff --git a/arch/blackfin/include/asm/bfin_simple_timer.h b/arch/blackfin/include/asm/bfin_simple_timer.h index 5248c13..aadfb1a 100644 --- a/arch/blackfin/include/asm/bfin_simple_timer.h +++ b/arch/blackfin/include/asm/bfin_simple_timer.h @@ -11,9 +11,11 @@ #define BFIN_SIMPLE_TIMER_IOCTL_MAGIC 't' -#define BFIN_SIMPLE_TIMER_SET_PERIOD _IO (BFIN_SIMPLE_TIMER_IOCTL_MAGIC, 2) -#define BFIN_SIMPLE_TIMER_START _IO (BFIN_SIMPLE_TIMER_IOCTL_MAGIC, 6) -#define BFIN_SIMPLE_TIMER_STOP _IO (BFIN_SIMPLE_TIMER_IOCTL_MAGIC, 8) -#define BFIN_SIMPLE_TIMER_READ _IO (BFIN_SIMPLE_TIMER_IOCTL_MAGIC, 10) +#define BFIN_SIMPLE_TIMER_SET_PERIOD _IO(BFIN_SIMPLE_TIMER_IOCTL_MAGIC, 2) +#define BFIN_SIMPLE_TIMER_SET_WIDTH _IO(BFIN_SIMPLE_TIMER_IOCTL_MAGIC, 3) +#define BFIN_SIMPLE_TIMER_SET_MODE _IO(BFIN_SIMPLE_TIMER_IOCTL_MAGIC, 4) +#define BFIN_SIMPLE_TIMER_START _IO(BFIN_SIMPLE_TIMER_IOCTL_MAGIC, 6) +#define BFIN_SIMPLE_TIMER_STOP _IO(BFIN_SIMPLE_TIMER_IOCTL_MAGIC, 8) +#define BFIN_SIMPLE_TIMER_READ _IO(BFIN_SIMPLE_TIMER_IOCTL_MAGIC, 10) #endif -- cgit v0.10.2 From edd8a97e6e89ee2edc86e21db6253a73741f3c72 Mon Sep 17 00:00:00 2001 From: Barry Song Date: Tue, 29 Jun 2010 08:55:29 +0000 Subject: blackfin: restore L1 base address and length Restore L1 base address and length to 0 after free else the value will be wrong. Signed-off-by: Barry Song Signed-off-by: Bob Liu diff --git a/arch/blackfin/include/asm/mmu_context.h b/arch/blackfin/include/asm/mmu_context.h index 3828c70..15b16d3 100644 --- a/arch/blackfin/include/asm/mmu_context.h +++ b/arch/blackfin/include/asm/mmu_context.h @@ -30,8 +30,11 @@ extern void *l1sram_alloc_max(void*); static inline void free_l1stack(void) { nr_l1stack_tasks--; - if (nr_l1stack_tasks == 0) + if (nr_l1stack_tasks == 0) { l1sram_free(l1_stack_base); + l1_stack_base = NULL; + l1_stack_len = 0; + } } static inline unsigned long -- cgit v0.10.2 From 4936afc6510608ddabeb4f562cf1a291cc38faa1 Mon Sep 17 00:00:00 2001 From: Barry Song Date: Sun, 21 Feb 2010 03:01:20 +0000 Subject: blackfin: cplb-mpu: fix page mask table overflow page mask table will overflow without xip related macros. Signed-off-by: Barry Song Signed-off-by: Bob Liu diff --git a/arch/blackfin/kernel/cplb-mpu/cplbmgr.c b/arch/blackfin/kernel/cplb-mpu/cplbmgr.c index 8de9229..b56bd85 100644 --- a/arch/blackfin/kernel/cplb-mpu/cplbmgr.c +++ b/arch/blackfin/kernel/cplb-mpu/cplbmgr.c @@ -120,6 +120,7 @@ MGR_ATTR static noinline int dcplb_miss(unsigned int cpu) d_data = L2_DMEMORY; } else if (addr >= physical_mem_end) { if (addr >= ASYNC_BANK0_BASE && addr < ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE) { +#if defined(CONFIG_ROMFS_ON_MTD) && defined(CONFIG_MTD_ROM) mask = current_rwx_mask[cpu]; if (mask) { int page = (addr - (ASYNC_BANK0_BASE - _ramend)) >> PAGE_SHIFT; @@ -129,6 +130,7 @@ MGR_ATTR static noinline int dcplb_miss(unsigned int cpu) if (mask[idx] & bit) d_data |= CPLB_USER_RD; } +#endif } else if (addr >= BOOT_ROM_START && addr < BOOT_ROM_START + BOOT_ROM_LENGTH && (status & (FAULT_RW | FAULT_USERSUPV)) == FAULT_USERSUPV) { addr &= ~(1 * 1024 * 1024 - 1); -- cgit v0.10.2 From 5d002cce4c8a24234b81033119eda3272ebf7981 Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Mon, 27 Jun 2011 18:16:29 -0400 Subject: spi/bfin_spi: drop bits_per_word from client data No other SPI controller has this field, and SPI clients should be setting this up in their own drivers. So drop it from the Blackfin controller to keep people from using it. Signed-off-by: Mike Frysinger Signed-off-by: Bob Liu diff --git a/arch/blackfin/include/asm/bfin5xx_spi.h b/arch/blackfin/include/asm/bfin5xx_spi.h index 5392583..fb95c85 100644 --- a/arch/blackfin/include/asm/bfin5xx_spi.h +++ b/arch/blackfin/include/asm/bfin5xx_spi.h @@ -77,7 +77,6 @@ struct bfin5xx_spi_master { struct bfin5xx_spi_chip { u16 ctl_reg; u8 enable_dma; - u8 bits_per_word; u16 cs_chg_udelay; /* Some devices require 16-bit delays */ /* Value to send if no TX value is supplied, usually 0x0 or 0xFFFF */ u16 idle_tx_val; -- cgit v0.10.2 From a5e0d8652adfc0530b3fce18e54e429287aeee73 Mon Sep 17 00:00:00 2001 From: Bob Liu Date: Tue, 17 Jan 2012 18:06:34 +0800 Subject: blackfin: bf561: forgot CSYNC in get_core_lock_noflush SMP kgdb runs into dead loop without this CSYNC when one core single steps over get_core_lock_noflush and the other executes get_core_lock as a slave node. Signed-off-by: Sonic Zhang Signed-off-by: Bob Liu diff --git a/arch/blackfin/mach-bf561/atomic.S b/arch/blackfin/mach-bf561/atomic.S index 52d6f73..2a08df8 100644 --- a/arch/blackfin/mach-bf561/atomic.S +++ b/arch/blackfin/mach-bf561/atomic.S @@ -72,6 +72,13 @@ ENTRY(_get_core_lock_noflush) SSYNC(r2); jump .Lretry_corelock_noflush .Ldone_corelock_noflush: + /* + * SMP kgdb runs into dead loop without NOP here, when one core + * single steps over get_core_lock_noflush and the other executes + * get_core_lock as a slave node. + */ + nop; + CSYNC(r2); rts; ENDPROC(_get_core_lock_noflush) -- cgit v0.10.2 From 4e937ac11280ff90ca0246a3b6042acef09154e9 Mon Sep 17 00:00:00 2001 From: Scott Jiang Date: Mon, 9 Jan 2012 17:06:56 -0500 Subject: bf548: add ppi interrupt mask and blanking clocks Signed-off-by: Scott Jiang Signed-off-by: Bob Liu diff --git a/arch/blackfin/mach-bf548/boards/ezkit.c b/arch/blackfin/mach-bf548/boards/ezkit.c index 3ea45f8..4595a40 100644 --- a/arch/blackfin/mach-bf548/boards/ezkit.c +++ b/arch/blackfin/mach-bf548/boards/ezkit.c @@ -1237,6 +1237,8 @@ static struct bfin_capture_config bfin_capture_data = { }, .ppi_info = &ppi_info, .ppi_control = (POLC | PACKEN | DLEN_8 | XFR_TYPE | 0x20), + .int_mask = 0xFFFFFFFF, /* disable error interrupt on eppi */ + .blank_clocks = 8, /* 8 clocks as SAV and EAV */ }; #endif -- cgit v0.10.2 From a5b44eeb38f7f3bd07bf857a26f1ac6193512df5 Mon Sep 17 00:00:00 2001 From: Bob Liu Date: Fri, 13 Jan 2012 18:34:46 +0800 Subject: blackfin: kgdb: skip hardware watchpoint test blackfin doesn't support hardware watchpoint except for over JTAG emulator. Signed-off-by: Sonic Zhang Signed-off-by: Bob Liu diff --git a/arch/blackfin/include/asm/kgdb.h b/arch/blackfin/include/asm/kgdb.h index aaf8845..2703dde 100644 --- a/arch/blackfin/include/asm/kgdb.h +++ b/arch/blackfin/include/asm/kgdb.h @@ -109,6 +109,7 @@ static inline void arch_kgdb_breakpoint(void) # define CACHE_FLUSH_IS_SAFE 1 #endif #define GDB_ADJUSTS_BREAK_OFFSET +#define GDB_SKIP_HW_WATCH_TEST #define HW_INST_WATCHPOINT_NUM 6 #define HW_WATCHPOINT_NUM 8 #define TYPE_INST_WATCHPOINT 0 -- cgit v0.10.2 From 57084ede395bb3c9da7905701d34a3b7d33c9356 Mon Sep 17 00:00:00 2001 From: Bob Liu Date: Mon, 16 Jan 2012 11:18:50 +0800 Subject: blackfin: bf537: stamp: update board file for 193x Signed-off-by: Scott Jiang Signed-off-by: Bob Liu diff --git a/arch/blackfin/mach-bf537/boards/stamp.c b/arch/blackfin/mach-bf537/boards/stamp.c index 2221173..58e17c2 100644 --- a/arch/blackfin/mach-bf537/boards/stamp.c +++ b/arch/blackfin/mach-bf537/boards/stamp.c @@ -975,7 +975,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { }, #endif -#if defined(CONFIG_SND_BF5XX_SOC_AD193X) || defined(CONFIG_SND_BF5XX_SOC_AD193X_MODULE) +#ifdef CONFIG_SND_SOC_AD193X_SPI { .modalias = "ad193x", .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ @@ -2171,7 +2171,7 @@ static unsigned long adt7316_i2c_data[2] = { #endif static struct i2c_board_info __initdata bfin_i2c_board_info[] = { -#if defined(CONFIG_SND_BF5XX_SOC_AD193X) || defined(CONFIG_SND_BF5XX_SOC_AD193X_MODULE) +#ifdef CONFIG_SND_SOC_AD193X_I2C { I2C_BOARD_INFO("ad1937", 0x04), }, -- cgit v0.10.2 From 3268968ddc978f12a4b72c8ebe8eafba68c26aa1 Mon Sep 17 00:00:00 2001 From: Bob Liu Date: Fri, 27 Jan 2012 21:36:21 +0800 Subject: bfin: add bfin_ad73311_machine platform device we can pass sport enable pin through platform data if customer board has reset pin, add it in ad73311_gpio array and modify id to 2 Signed-off-by: Scott Jiang Signed-off-by: Bob Liu diff --git a/arch/blackfin/mach-bf537/boards/stamp.c b/arch/blackfin/mach-bf537/boards/stamp.c index 58e17c2..f2c0629 100644 --- a/arch/blackfin/mach-bf537/boards/stamp.c +++ b/arch/blackfin/mach-bf537/boards/stamp.c @@ -2593,6 +2593,21 @@ static struct platform_device bfin_ac97_pcm = { }; #endif +#if defined(CONFIG_SND_BF5XX_SOC_AD73311) || \ + defined(CONFIG_SND_BF5XX_SOC_AD73311_MODULE) +static const unsigned ad73311_gpio[] = { + GPIO_PF4, +}; + +static struct platform_device bfin_ad73311_machine = { + .name = "bfin-snd-ad73311", + .id = 1, + .dev = { + .platform_data = (void *)ad73311_gpio, + }, +}; +#endif + #if defined(CONFIG_SND_SOC_AD73311) || defined(CONFIG_SND_SOC_AD73311_MODULE) static struct platform_device bfin_ad73311_codec_device = { .name = "ad73311", @@ -2862,6 +2877,11 @@ static struct platform_device *stamp_devices[] __initdata = { &bfin_ac97_pcm, #endif +#if defined(CONFIG_SND_BF5XX_SOC_AD73311) || \ + defined(CONFIG_SND_BF5XX_SOC_AD73311_MODULE) + &bfin_ad73311_machine, +#endif + #if defined(CONFIG_SND_SOC_AD73311) || defined(CONFIG_SND_SOC_AD73311_MODULE) &bfin_ad73311_codec_device, #endif -- cgit v0.10.2 From 563c76ff4ca793fa3246b6857e039155ebd8d386 Mon Sep 17 00:00:00 2001 From: Bob Liu Date: Fri, 27 Jan 2012 21:37:57 +0800 Subject: blackfin: thread_info: add suspend flag Add suspend flag to thread_info for suspend/resume. Signed-off-by: Bob Liu diff --git a/arch/blackfin/include/asm/thread_info.h b/arch/blackfin/include/asm/thread_info.h index 53ad100..02560fd 100644 --- a/arch/blackfin/include/asm/thread_info.h +++ b/arch/blackfin/include/asm/thread_info.h @@ -100,6 +100,7 @@ static inline struct thread_info *current_thread_info(void) TIF_NEED_RESCHED */ #define TIF_MEMDIE 4 /* is terminating due to OOM killer */ #define TIF_RESTORE_SIGMASK 5 /* restore signal mask in do_signal() */ +#define TIF_FREEZE 6 /* is freezing for suspend */ #define TIF_IRQ_SYNC 7 /* sync pipeline stage */ #define TIF_NOTIFY_RESUME 8 /* callback before returning to user */ #define TIF_SINGLESTEP 9 @@ -110,6 +111,7 @@ static inline struct thread_info *current_thread_info(void) #define _TIF_NEED_RESCHED (1< Date: Mon, 16 Jan 2012 13:12:10 +0800 Subject: blackfin: update default defconfig Update default defconfig by selecting correct net device driver. Signed-off-by: Bob Liu diff --git a/arch/blackfin/configs/BF518F-EZBRD_defconfig b/arch/blackfin/configs/BF518F-EZBRD_defconfig index 0b7039c..3830078 100644 --- a/arch/blackfin/configs/BF518F-EZBRD_defconfig +++ b/arch/blackfin/configs/BF518F-EZBRD_defconfig @@ -4,9 +4,7 @@ CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_BLK_DEV_INITRD=y -# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set CONFIG_EXPERT=y -# CONFIG_SYSCTL_SYSCALL is not set # CONFIG_ELF_CORE is not set # CONFIG_FUTEX is not set # CONFIG_SIGNALFD is not set @@ -35,7 +33,6 @@ CONFIG_C_CDPRIO=y CONFIG_BANK_3=0x99B2 CONFIG_BINFMT_FLAT=y CONFIG_BINFMT_ZFLAT=y -CONFIG_PM=y CONFIG_NET=y CONFIG_PACKET=y CONFIG_UNIX=y @@ -51,7 +48,6 @@ CONFIG_IP_PNP=y CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" # CONFIG_FW_LOADER is not set CONFIG_MTD=y -CONFIG_MTD_PARTITIONS=y CONFIG_MTD_CHAR=y CONFIG_MTD_BLOCK=y CONFIG_MTD_JEDECPROBE=m @@ -60,20 +56,28 @@ CONFIG_MTD_ROM=m CONFIG_MTD_COMPLEX_MAPPINGS=y CONFIG_BLK_DEV_RAM=y CONFIG_NETDEVICES=y -CONFIG_NET_ETHERNET=y +CONFIG_NET_BFIN=y CONFIG_BFIN_MAC=y -# CONFIG_NETDEV_1000 is not set -# CONFIG_NETDEV_10000 is not set +# CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_VENDOR_CHELSIO is not set +# CONFIG_NET_VENDOR_INTEL is not set +# CONFIG_NET_VENDOR_MARVELL is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_MICROCHIP is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_SMSC is not set +# CONFIG_NET_VENDOR_STMICRO is not set # CONFIG_WLAN is not set # CONFIG_INPUT is not set # CONFIG_SERIO is not set # CONFIG_VT is not set -# CONFIG_DEVKMEM is not set +# CONFIG_LEGACY_PTYS is not set CONFIG_BFIN_JTAG_COMM=m +# CONFIG_DEVKMEM is not set CONFIG_SERIAL_BFIN=y CONFIG_SERIAL_BFIN_CONSOLE=y CONFIG_SERIAL_BFIN_UART0=y -# CONFIG_LEGACY_PTYS is not set # CONFIG_HW_RANDOM is not set CONFIG_I2C=y CONFIG_I2C_CHARDEV=y @@ -97,16 +101,13 @@ CONFIG_EXT2_FS=m CONFIG_VFAT_FS=m CONFIG_NFS_FS=m CONFIG_NFS_V3=y -CONFIG_SMB_FS=m CONFIG_NLS_CODEPAGE_437=m CONFIG_NLS_CODEPAGE_936=m CONFIG_NLS_ISO8859_1=m CONFIG_NLS_UTF8=m -CONFIG_DEBUG_KERNEL=y CONFIG_DEBUG_SHIRQ=y CONFIG_DETECT_HUNG_TASK=y CONFIG_DEBUG_INFO=y -# CONFIG_RCU_CPU_STALL_DETECTOR is not set # CONFIG_FTRACE is not set CONFIG_DEBUG_MMRS=y CONFIG_DEBUG_HWERR=y diff --git a/arch/blackfin/configs/BF526-EZBRD_defconfig b/arch/blackfin/configs/BF526-EZBRD_defconfig index 5553205..2f2c6ac 100644 --- a/arch/blackfin/configs/BF526-EZBRD_defconfig +++ b/arch/blackfin/configs/BF526-EZBRD_defconfig @@ -4,9 +4,7 @@ CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_BLK_DEV_INITRD=y -# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set CONFIG_EXPERT=y -# CONFIG_SYSCTL_SYSCALL is not set # CONFIG_ELF_CORE is not set # CONFIG_FUTEX is not set # CONFIG_SIGNALFD is not set @@ -40,7 +38,6 @@ CONFIG_C_CDPRIO=y CONFIG_BANK_3=0x99B2 CONFIG_BINFMT_FLAT=y CONFIG_BINFMT_ZFLAT=y -CONFIG_PM=y CONFIG_NET=y CONFIG_PACKET=y CONFIG_UNIX=y @@ -56,7 +53,6 @@ CONFIG_IP_PNP=y CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" # CONFIG_FW_LOADER is not set CONFIG_MTD=y -CONFIG_MTD_PARTITIONS=y CONFIG_MTD_CHAR=y CONFIG_MTD_BLOCK=y CONFIG_MTD_CFI=y @@ -74,10 +70,18 @@ CONFIG_BLK_DEV_SD=y CONFIG_BLK_DEV_SR=m # CONFIG_SCSI_LOWLEVEL is not set CONFIG_NETDEVICES=y -CONFIG_NET_ETHERNET=y +CONFIG_NET_BFIN=y CONFIG_BFIN_MAC=y -# CONFIG_NETDEV_1000 is not set -# CONFIG_NETDEV_10000 is not set +# CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_VENDOR_CHELSIO is not set +# CONFIG_NET_VENDOR_INTEL is not set +# CONFIG_NET_VENDOR_MARVELL is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_MICROCHIP is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_SMSC is not set +# CONFIG_NET_VENDOR_STMICRO is not set # CONFIG_WLAN is not set CONFIG_INPUT_FF_MEMLESS=m # CONFIG_INPUT_MOUSEDEV is not set @@ -85,12 +89,12 @@ CONFIG_INPUT_FF_MEMLESS=m # CONFIG_INPUT_MOUSE is not set CONFIG_INPUT_MISC=y # CONFIG_SERIO is not set -# CONFIG_DEVKMEM is not set +# CONFIG_LEGACY_PTYS is not set CONFIG_BFIN_JTAG_COMM=m +# CONFIG_DEVKMEM is not set CONFIG_SERIAL_BFIN=y CONFIG_SERIAL_BFIN_CONSOLE=y CONFIG_SERIAL_BFIN_UART1=y -# CONFIG_LEGACY_PTYS is not set # CONFIG_HW_RANDOM is not set CONFIG_I2C=y CONFIG_I2C_CHARDEV=m @@ -123,7 +127,6 @@ CONFIG_USB_DEVICEFS=y # CONFIG_USB_DEVICE_CLASS is not set CONFIG_USB_OTG_BLACKLIST_HUB=y CONFIG_USB_MON=y -CONFIG_USB_MUSB_HDRC=y CONFIG_USB_STORAGE=y CONFIG_RTC_CLASS=y CONFIG_RTC_DRV_BFIN=y @@ -135,16 +138,13 @@ CONFIG_VFAT_FS=m CONFIG_JFFS2_FS=m CONFIG_NFS_FS=m CONFIG_NFS_V3=y -CONFIG_SMB_FS=m CONFIG_NLS_CODEPAGE_437=m CONFIG_NLS_CODEPAGE_936=m CONFIG_NLS_ISO8859_1=m CONFIG_NLS_UTF8=m -CONFIG_DEBUG_KERNEL=y CONFIG_DEBUG_SHIRQ=y CONFIG_DETECT_HUNG_TASK=y CONFIG_DEBUG_INFO=y -# CONFIG_RCU_CPU_STALL_DETECTOR is not set # CONFIG_FTRACE is not set CONFIG_DEBUG_MMRS=y CONFIG_DEBUG_HWERR=y diff --git a/arch/blackfin/configs/BF527-EZKIT-V2_defconfig b/arch/blackfin/configs/BF527-EZKIT-V2_defconfig index 498f64a..9325d75 100644 --- a/arch/blackfin/configs/BF527-EZKIT-V2_defconfig +++ b/arch/blackfin/configs/BF527-EZKIT-V2_defconfig @@ -4,9 +4,7 @@ CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_BLK_DEV_INITRD=y -# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set CONFIG_EXPERT=y -# CONFIG_SYSCTL_SYSCALL is not set # CONFIG_ELF_CORE is not set # CONFIG_FUTEX is not set # CONFIG_SIGNALFD is not set @@ -39,7 +37,6 @@ CONFIG_C_CDPRIO=y CONFIG_BANK_3=0x99B2 CONFIG_BINFMT_FLAT=y CONFIG_BINFMT_ZFLAT=y -CONFIG_PM=y CONFIG_NET=y CONFIG_PACKET=y CONFIG_UNIX=y @@ -61,7 +58,6 @@ CONFIG_BFIN_SIR0=y CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" # CONFIG_FW_LOADER is not set CONFIG_MTD=y -CONFIG_MTD_PARTITIONS=y CONFIG_MTD_CHAR=m CONFIG_MTD_BLOCK=y CONFIG_MTD_JEDECPROBE=m @@ -77,10 +73,18 @@ CONFIG_BLK_DEV_SD=y CONFIG_BLK_DEV_SR=m # CONFIG_SCSI_LOWLEVEL is not set CONFIG_NETDEVICES=y -CONFIG_NET_ETHERNET=y +CONFIG_NET_BFIN=y CONFIG_BFIN_MAC=y -# CONFIG_NETDEV_1000 is not set -# CONFIG_NETDEV_10000 is not set +# CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_VENDOR_CHELSIO is not set +# CONFIG_NET_VENDOR_INTEL is not set +# CONFIG_NET_VENDOR_MARVELL is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_MICROCHIP is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_SMSC is not set +# CONFIG_NET_VENDOR_STMICRO is not set # CONFIG_WLAN is not set CONFIG_INPUT_FF_MEMLESS=m # CONFIG_INPUT_MOUSEDEV is not set @@ -93,12 +97,12 @@ CONFIG_TOUCHSCREEN_AD7879=y CONFIG_TOUCHSCREEN_AD7879_I2C=y CONFIG_INPUT_MISC=y # CONFIG_SERIO is not set -# CONFIG_DEVKMEM is not set +# CONFIG_LEGACY_PTYS is not set CONFIG_BFIN_JTAG_COMM=m +# CONFIG_DEVKMEM is not set CONFIG_SERIAL_BFIN=y CONFIG_SERIAL_BFIN_CONSOLE=y CONFIG_SERIAL_BFIN_UART1=y -# CONFIG_LEGACY_PTYS is not set # CONFIG_HW_RANDOM is not set CONFIG_I2C=y CONFIG_I2C_CHARDEV=m @@ -147,7 +151,6 @@ CONFIG_USB_DEVICEFS=y # CONFIG_USB_DEVICE_CLASS is not set CONFIG_USB_OTG_BLACKLIST_HUB=y CONFIG_USB_MON=y -CONFIG_USB_MUSB_HDRC=y CONFIG_USB_STORAGE=y CONFIG_NEW_LEDS=y CONFIG_LEDS_CLASS=y @@ -163,16 +166,13 @@ CONFIG_VFAT_FS=m CONFIG_JFFS2_FS=m CONFIG_NFS_FS=m CONFIG_NFS_V3=y -CONFIG_SMB_FS=m CONFIG_NLS_CODEPAGE_437=m CONFIG_NLS_CODEPAGE_936=m CONFIG_NLS_ISO8859_1=m CONFIG_NLS_UTF8=m -CONFIG_DEBUG_KERNEL=y CONFIG_DEBUG_SHIRQ=y CONFIG_DETECT_HUNG_TASK=y CONFIG_DEBUG_INFO=y -# CONFIG_RCU_CPU_STALL_DETECTOR is not set # CONFIG_FTRACE is not set CONFIG_DEBUG_MMRS=y CONFIG_DEBUG_HWERR=y diff --git a/arch/blackfin/configs/BF527-EZKIT_defconfig b/arch/blackfin/configs/BF527-EZKIT_defconfig index 72e0317..b953be0 100644 --- a/arch/blackfin/configs/BF527-EZKIT_defconfig +++ b/arch/blackfin/configs/BF527-EZKIT_defconfig @@ -4,9 +4,7 @@ CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_BLK_DEV_INITRD=y -# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set CONFIG_EXPERT=y -# CONFIG_SYSCTL_SYSCALL is not set # CONFIG_ELF_CORE is not set # CONFIG_FUTEX is not set # CONFIG_SIGNALFD is not set @@ -38,7 +36,6 @@ CONFIG_C_CDPRIO=y CONFIG_BANK_3=0x99B2 CONFIG_BINFMT_FLAT=y CONFIG_BINFMT_ZFLAT=y -CONFIG_PM=y CONFIG_NET=y CONFIG_PACKET=y CONFIG_UNIX=y @@ -60,7 +57,6 @@ CONFIG_BFIN_SIR0=y CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" # CONFIG_FW_LOADER is not set CONFIG_MTD=y -CONFIG_MTD_PARTITIONS=y CONFIG_MTD_CHAR=m CONFIG_MTD_BLOCK=y CONFIG_MTD_JEDECPROBE=m @@ -76,10 +72,18 @@ CONFIG_BLK_DEV_SD=y CONFIG_BLK_DEV_SR=m # CONFIG_SCSI_LOWLEVEL is not set CONFIG_NETDEVICES=y -CONFIG_NET_ETHERNET=y +CONFIG_NET_BFIN=y CONFIG_BFIN_MAC=y -# CONFIG_NETDEV_1000 is not set -# CONFIG_NETDEV_10000 is not set +# CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_VENDOR_CHELSIO is not set +# CONFIG_NET_VENDOR_INTEL is not set +# CONFIG_NET_VENDOR_MARVELL is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_MICROCHIP is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_SMSC is not set +# CONFIG_NET_VENDOR_STMICRO is not set # CONFIG_WLAN is not set CONFIG_INPUT_FF_MEMLESS=m # CONFIG_INPUT_MOUSEDEV is not set @@ -87,12 +91,12 @@ CONFIG_INPUT_FF_MEMLESS=m # CONFIG_INPUT_MOUSE is not set CONFIG_INPUT_MISC=y # CONFIG_SERIO is not set -# CONFIG_DEVKMEM is not set +# CONFIG_LEGACY_PTYS is not set CONFIG_BFIN_JTAG_COMM=m +# CONFIG_DEVKMEM is not set CONFIG_SERIAL_BFIN=y CONFIG_SERIAL_BFIN_CONSOLE=y CONFIG_SERIAL_BFIN_UART1=y -# CONFIG_LEGACY_PTYS is not set # CONFIG_HW_RANDOM is not set CONFIG_I2C=y CONFIG_I2C_CHARDEV=m @@ -141,8 +145,6 @@ CONFIG_USB_DEVICEFS=y # CONFIG_USB_DEVICE_CLASS is not set CONFIG_USB_OTG_BLACKLIST_HUB=y CONFIG_USB_MON=y -CONFIG_USB_MUSB_HDRC=y -CONFIG_MUSB_PIO_ONLY=y CONFIG_USB_STORAGE=y CONFIG_RTC_CLASS=y CONFIG_RTC_DRV_BFIN=y @@ -155,16 +157,13 @@ CONFIG_VFAT_FS=m CONFIG_JFFS2_FS=m CONFIG_NFS_FS=m CONFIG_NFS_V3=y -CONFIG_SMB_FS=m CONFIG_NLS_CODEPAGE_437=m CONFIG_NLS_CODEPAGE_936=m CONFIG_NLS_ISO8859_1=m CONFIG_NLS_UTF8=m -CONFIG_DEBUG_KERNEL=y CONFIG_DEBUG_SHIRQ=y CONFIG_DETECT_HUNG_TASK=y CONFIG_DEBUG_INFO=y -# CONFIG_RCU_CPU_STALL_DETECTOR is not set # CONFIG_FTRACE is not set CONFIG_DEBUG_MMRS=y CONFIG_DEBUG_HWERR=y diff --git a/arch/blackfin/configs/BF533-EZKIT_defconfig b/arch/blackfin/configs/BF533-EZKIT_defconfig index 2f075e0..127f20d 100644 --- a/arch/blackfin/configs/BF533-EZKIT_defconfig +++ b/arch/blackfin/configs/BF533-EZKIT_defconfig @@ -4,9 +4,7 @@ CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_BLK_DEV_INITRD=y -# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set CONFIG_EXPERT=y -# CONFIG_SYSCTL_SYSCALL is not set # CONFIG_ELF_CORE is not set # CONFIG_FUTEX is not set # CONFIG_SIGNALFD is not set @@ -32,7 +30,6 @@ CONFIG_C_CDPRIO=y CONFIG_BANK_3=0xAAC2 CONFIG_BINFMT_FLAT=y CONFIG_BINFMT_ZFLAT=y -CONFIG_PM=y CONFIG_NET=y CONFIG_PACKET=y CONFIG_UNIX=y @@ -53,7 +50,6 @@ CONFIG_IRTTY_SIR=m CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" # CONFIG_FW_LOADER is not set CONFIG_MTD=y -CONFIG_MTD_PARTITIONS=y CONFIG_MTD_CHAR=m CONFIG_MTD_BLOCK=y CONFIG_MTD_JEDECPROBE=m @@ -62,10 +58,16 @@ CONFIG_MTD_ROM=m CONFIG_MTD_COMPLEX_MAPPINGS=y CONFIG_BLK_DEV_RAM=y CONFIG_NETDEVICES=y -CONFIG_NET_ETHERNET=y +# CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_VENDOR_CHELSIO is not set +# CONFIG_NET_VENDOR_INTEL is not set +# CONFIG_NET_VENDOR_MARVELL is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_MICROCHIP is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_NET_VENDOR_SEEQ is not set CONFIG_SMC91X=y -# CONFIG_NETDEV_1000 is not set -# CONFIG_NETDEV_10000 is not set +# CONFIG_NET_VENDOR_STMICRO is not set # CONFIG_WLAN is not set CONFIG_INPUT=m # CONFIG_INPUT_MOUSEDEV is not set @@ -74,11 +76,11 @@ CONFIG_INPUT_EVDEV=m # CONFIG_INPUT_MOUSE is not set # CONFIG_SERIO is not set # CONFIG_VT is not set -# CONFIG_DEVKMEM is not set +# CONFIG_LEGACY_PTYS is not set CONFIG_BFIN_JTAG_COMM=m +# CONFIG_DEVKMEM is not set CONFIG_SERIAL_BFIN=y CONFIG_SERIAL_BFIN_CONSOLE=y -# CONFIG_LEGACY_PTYS is not set # CONFIG_HW_RANDOM is not set CONFIG_SPI=y CONFIG_SPI_BFIN5XX=y @@ -94,12 +96,9 @@ CONFIG_RTC_DRV_BFIN=y CONFIG_JFFS2_FS=m CONFIG_NFS_FS=m CONFIG_NFS_V3=y -CONFIG_SMB_FS=m -CONFIG_DEBUG_KERNEL=y CONFIG_DEBUG_SHIRQ=y CONFIG_DETECT_HUNG_TASK=y CONFIG_DEBUG_INFO=y -# CONFIG_RCU_CPU_STALL_DETECTOR is not set # CONFIG_FTRACE is not set CONFIG_DEBUG_MMRS=y CONFIG_DEBUG_HWERR=y diff --git a/arch/blackfin/configs/BF533-STAMP_defconfig b/arch/blackfin/configs/BF533-STAMP_defconfig index ab38a82..0df2f92 100644 --- a/arch/blackfin/configs/BF533-STAMP_defconfig +++ b/arch/blackfin/configs/BF533-STAMP_defconfig @@ -4,9 +4,7 @@ CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_BLK_DEV_INITRD=y -# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set CONFIG_EXPERT=y -# CONFIG_SYSCTL_SYSCALL is not set # CONFIG_ELF_CORE is not set # CONFIG_FUTEX is not set # CONFIG_SIGNALFD is not set @@ -30,7 +28,6 @@ CONFIG_C_CDPRIO=y CONFIG_BANK_3=0xAAC2 CONFIG_BINFMT_FLAT=y CONFIG_BINFMT_ZFLAT=y -CONFIG_PM=y CONFIG_NET=y CONFIG_PACKET=y CONFIG_UNIX=y @@ -62,10 +59,16 @@ CONFIG_MTD_ROM=m CONFIG_MTD_COMPLEX_MAPPINGS=y CONFIG_BLK_DEV_RAM=y CONFIG_NETDEVICES=y -CONFIG_NET_ETHERNET=y +# CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_VENDOR_CHELSIO is not set +# CONFIG_NET_VENDOR_INTEL is not set +# CONFIG_NET_VENDOR_MARVELL is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_MICROCHIP is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_NET_VENDOR_SEEQ is not set CONFIG_SMC91X=y -# CONFIG_NETDEV_1000 is not set -# CONFIG_NETDEV_10000 is not set +# CONFIG_NET_VENDOR_STMICRO is not set # CONFIG_WLAN is not set # CONFIG_INPUT_MOUSEDEV is not set CONFIG_INPUT_EVDEV=m @@ -74,11 +77,11 @@ CONFIG_INPUT_EVDEV=m CONFIG_INPUT_MISC=y # CONFIG_SERIO is not set # CONFIG_VT is not set -# CONFIG_DEVKMEM is not set +# CONFIG_LEGACY_PTYS is not set CONFIG_BFIN_JTAG_COMM=m +# CONFIG_DEVKMEM is not set CONFIG_SERIAL_BFIN=y CONFIG_SERIAL_BFIN_CONSOLE=y -# CONFIG_LEGACY_PTYS is not set # CONFIG_HW_RANDOM is not set CONFIG_I2C=m CONFIG_I2C_CHARDEV=m @@ -106,12 +109,9 @@ CONFIG_RTC_DRV_BFIN=y CONFIG_JFFS2_FS=m CONFIG_NFS_FS=m CONFIG_NFS_V3=y -CONFIG_SMB_FS=m -CONFIG_DEBUG_KERNEL=y CONFIG_DEBUG_SHIRQ=y CONFIG_DETECT_HUNG_TASK=y CONFIG_DEBUG_INFO=y -# CONFIG_RCU_CPU_STALL_DETECTOR is not set # CONFIG_FTRACE is not set CONFIG_DEBUG_MMRS=y CONFIG_DEBUG_HWERR=y diff --git a/arch/blackfin/configs/BF537-STAMP_defconfig b/arch/blackfin/configs/BF537-STAMP_defconfig index 5c802d6..91d3eda 100644 --- a/arch/blackfin/configs/BF537-STAMP_defconfig +++ b/arch/blackfin/configs/BF537-STAMP_defconfig @@ -4,9 +4,7 @@ CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_BLK_DEV_INITRD=y -# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set CONFIG_EXPERT=y -# CONFIG_SYSCTL_SYSCALL is not set # CONFIG_ELF_CORE is not set # CONFIG_FUTEX is not set # CONFIG_SIGNALFD is not set @@ -30,7 +28,6 @@ CONFIG_C_CDPRIO=y CONFIG_BANK_3=0x99B2 CONFIG_BINFMT_FLAT=y CONFIG_BINFMT_ZFLAT=y -CONFIG_PM=y CONFIG_NET=y CONFIG_PACKET=y CONFIG_UNIX=y @@ -45,7 +42,6 @@ CONFIG_IP_PNP=y CONFIG_CAN=m CONFIG_CAN_RAW=m CONFIG_CAN_BCM=m -CONFIG_CAN_DEV=m CONFIG_CAN_BFIN=m CONFIG_IRDA=m CONFIG_IRLAN=m @@ -58,7 +54,6 @@ CONFIG_BFIN_SIR1=y CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" # CONFIG_FW_LOADER is not set CONFIG_MTD=y -CONFIG_MTD_PARTITIONS=y CONFIG_MTD_CMDLINE_PARTS=y CONFIG_MTD_CHAR=m CONFIG_MTD_BLOCK=y @@ -69,11 +64,18 @@ CONFIG_MTD_ROM=m CONFIG_MTD_PHYSMAP=m CONFIG_BLK_DEV_RAM=y CONFIG_NETDEVICES=y -CONFIG_SMSC_PHY=y -CONFIG_NET_ETHERNET=y +CONFIG_NET_BFIN=y CONFIG_BFIN_MAC=y -# CONFIG_NETDEV_1000 is not set -# CONFIG_NETDEV_10000 is not set +# CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_VENDOR_CHELSIO is not set +# CONFIG_NET_VENDOR_INTEL is not set +# CONFIG_NET_VENDOR_MARVELL is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_MICROCHIP is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_SMSC is not set +# CONFIG_NET_VENDOR_STMICRO is not set # CONFIG_WLAN is not set # CONFIG_INPUT_MOUSEDEV is not set CONFIG_INPUT_EVDEV=m @@ -82,12 +84,12 @@ CONFIG_INPUT_EVDEV=m CONFIG_INPUT_MISC=y # CONFIG_SERIO is not set # CONFIG_VT is not set -# CONFIG_DEVKMEM is not set +# CONFIG_LEGACY_PTYS is not set CONFIG_BFIN_JTAG_COMM=m +# CONFIG_DEVKMEM is not set CONFIG_SERIAL_BFIN=y CONFIG_SERIAL_BFIN_CONSOLE=y CONFIG_SERIAL_BFIN_UART0=y -# CONFIG_LEGACY_PTYS is not set # CONFIG_HW_RANDOM is not set CONFIG_I2C=m CONFIG_I2C_CHARDEV=m @@ -117,12 +119,9 @@ CONFIG_RTC_DRV_BFIN=y CONFIG_JFFS2_FS=m CONFIG_NFS_FS=m CONFIG_NFS_V3=y -CONFIG_SMB_FS=m -CONFIG_DEBUG_KERNEL=y CONFIG_DEBUG_SHIRQ=y CONFIG_DETECT_HUNG_TASK=y CONFIG_DEBUG_INFO=y -# CONFIG_RCU_CPU_STALL_DETECTOR is not set # CONFIG_FTRACE is not set CONFIG_DEBUG_MMRS=y CONFIG_DEBUG_HWERR=y diff --git a/arch/blackfin/configs/BF548-EZKIT_defconfig b/arch/blackfin/configs/BF548-EZKIT_defconfig index 7a1e3bf..296de92 100644 --- a/arch/blackfin/configs/BF548-EZKIT_defconfig +++ b/arch/blackfin/configs/BF548-EZKIT_defconfig @@ -5,7 +5,6 @@ CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_BLK_DEV_INITRD=y CONFIG_EXPERT=y -# CONFIG_SYSCTL_SYSCALL is not set # CONFIG_ELF_CORE is not set # CONFIG_FUTEX is not set # CONFIG_SIGNALFD is not set @@ -85,10 +84,16 @@ CONFIG_ATA=y # CONFIG_SATA_PMP is not set CONFIG_PATA_BF54X=y CONFIG_NETDEVICES=y -CONFIG_NET_ETHERNET=y +# CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_VENDOR_CHELSIO is not set +# CONFIG_NET_VENDOR_INTEL is not set +# CONFIG_NET_VENDOR_MARVELL is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_MICROCHIP is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_NET_VENDOR_SEEQ is not set CONFIG_SMSC911X=y -# CONFIG_NETDEV_1000 is not set -# CONFIG_NETDEV_10000 is not set +# CONFIG_NET_VENDOR_STMICRO is not set # CONFIG_WLAN is not set CONFIG_INPUT_FF_MEMLESS=m # CONFIG_INPUT_MOUSEDEV is not set @@ -158,8 +163,6 @@ CONFIG_USB_DEVICEFS=y # CONFIG_USB_DEVICE_CLASS is not set CONFIG_USB_OTG_BLACKLIST_HUB=y CONFIG_USB_MON=y -CONFIG_USB_MUSB_HDRC=y -CONFIG_USB_MUSB_BLACKFIN=y CONFIG_USB_STORAGE=y CONFIG_MMC=y CONFIG_MMC_BLOCK=m @@ -187,7 +190,6 @@ CONFIG_NLS_CODEPAGE_437=m CONFIG_NLS_CODEPAGE_936=m CONFIG_NLS_ISO8859_1=m CONFIG_NLS_UTF8=m -CONFIG_DEBUG_KERNEL=y CONFIG_DEBUG_SHIRQ=y CONFIG_DETECT_HUNG_TASK=y CONFIG_DEBUG_INFO=y diff --git a/arch/blackfin/configs/BF561-EZKIT-SMP_defconfig b/arch/blackfin/configs/BF561-EZKIT-SMP_defconfig index 78adbbf..680730e 100644 --- a/arch/blackfin/configs/BF561-EZKIT-SMP_defconfig +++ b/arch/blackfin/configs/BF561-EZKIT-SMP_defconfig @@ -4,9 +4,7 @@ CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_BLK_DEV_INITRD=y -# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set CONFIG_EXPERT=y -# CONFIG_SYSCTL_SYSCALL is not set # CONFIG_ELF_CORE is not set # CONFIG_FUTEX is not set # CONFIG_SIGNALFD is not set @@ -23,17 +21,18 @@ CONFIG_MODULE_UNLOAD=y # CONFIG_IOSCHED_CFQ is not set CONFIG_PREEMPT_VOLUNTARY=y CONFIG_BF561=y -CONFIG_SMP=y CONFIG_IRQ_TIMER0=10 CONFIG_CLKIN_HZ=30000000 CONFIG_HIGH_RES_TIMERS=y CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0 CONFIG_BFIN_GPTIMERS=m +CONFIG_BFIN_EXTMEM_WRITETHROUGH=y +CONFIG_BFIN_L2_DCACHEABLE=y +CONFIG_BFIN_L2_WRITETHROUGH=y CONFIG_C_CDPRIO=y CONFIG_BANK_3=0xAAC2 CONFIG_BINFMT_FLAT=y CONFIG_BINFMT_ZFLAT=y -CONFIG_PM=y CONFIG_NET=y CONFIG_PACKET=y CONFIG_UNIX=y @@ -54,21 +53,26 @@ CONFIG_IRTTY_SIR=m CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" # CONFIG_FW_LOADER is not set CONFIG_MTD=y -CONFIG_MTD_PARTITIONS=y CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_CHAR=m +CONFIG_MTD_CHAR=y CONFIG_MTD_BLOCK=y -CONFIG_MTD_CFI=m -CONFIG_MTD_CFI_AMDSTD=m +CONFIG_MTD_CFI=y +CONFIG_MTD_CFI_AMDSTD=y CONFIG_MTD_RAM=y CONFIG_MTD_ROM=m -CONFIG_MTD_PHYSMAP=m +CONFIG_MTD_PHYSMAP=y CONFIG_BLK_DEV_RAM=y CONFIG_NETDEVICES=y -CONFIG_NET_ETHERNET=y +# CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_VENDOR_CHELSIO is not set +# CONFIG_NET_VENDOR_INTEL is not set +# CONFIG_NET_VENDOR_MARVELL is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_MICROCHIP is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_NET_VENDOR_SEEQ is not set CONFIG_SMC91X=y -# CONFIG_NETDEV_1000 is not set -# CONFIG_NETDEV_10000 is not set +# CONFIG_NET_VENDOR_STMICRO is not set # CONFIG_WLAN is not set CONFIG_INPUT=m # CONFIG_INPUT_MOUSEDEV is not set @@ -77,11 +81,11 @@ CONFIG_INPUT_EVDEV=m # CONFIG_INPUT_MOUSE is not set # CONFIG_SERIO is not set # CONFIG_VT is not set -# CONFIG_DEVKMEM is not set +# CONFIG_LEGACY_PTYS is not set CONFIG_BFIN_JTAG_COMM=m +# CONFIG_DEVKMEM is not set CONFIG_SERIAL_BFIN=y CONFIG_SERIAL_BFIN_CONSOLE=y -# CONFIG_LEGACY_PTYS is not set # CONFIG_HW_RANDOM is not set CONFIG_SPI=y CONFIG_SPI_BFIN5XX=y @@ -95,12 +99,9 @@ CONFIG_BFIN_WDT=y CONFIG_JFFS2_FS=m CONFIG_NFS_FS=m CONFIG_NFS_V3=y -CONFIG_SMB_FS=m -CONFIG_DEBUG_KERNEL=y CONFIG_DEBUG_SHIRQ=y CONFIG_DETECT_HUNG_TASK=y CONFIG_DEBUG_INFO=y -# CONFIG_RCU_CPU_STALL_DETECTOR is not set # CONFIG_FTRACE is not set CONFIG_DEBUG_MMRS=y CONFIG_DEBUG_HWERR=y diff --git a/arch/blackfin/configs/BF561-EZKIT_defconfig b/arch/blackfin/configs/BF561-EZKIT_defconfig index d3cd0f5..680730e 100644 --- a/arch/blackfin/configs/BF561-EZKIT_defconfig +++ b/arch/blackfin/configs/BF561-EZKIT_defconfig @@ -4,9 +4,7 @@ CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_BLK_DEV_INITRD=y -# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set CONFIG_EXPERT=y -# CONFIG_SYSCTL_SYSCALL is not set # CONFIG_ELF_CORE is not set # CONFIG_FUTEX is not set # CONFIG_SIGNALFD is not set @@ -35,7 +33,6 @@ CONFIG_C_CDPRIO=y CONFIG_BANK_3=0xAAC2 CONFIG_BINFMT_FLAT=y CONFIG_BINFMT_ZFLAT=y -CONFIG_PM=y CONFIG_NET=y CONFIG_PACKET=y CONFIG_UNIX=y @@ -56,7 +53,6 @@ CONFIG_IRTTY_SIR=m CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" # CONFIG_FW_LOADER is not set CONFIG_MTD=y -CONFIG_MTD_PARTITIONS=y CONFIG_MTD_CMDLINE_PARTS=y CONFIG_MTD_CHAR=y CONFIG_MTD_BLOCK=y @@ -67,10 +63,16 @@ CONFIG_MTD_ROM=m CONFIG_MTD_PHYSMAP=y CONFIG_BLK_DEV_RAM=y CONFIG_NETDEVICES=y -CONFIG_NET_ETHERNET=y +# CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_VENDOR_CHELSIO is not set +# CONFIG_NET_VENDOR_INTEL is not set +# CONFIG_NET_VENDOR_MARVELL is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_MICROCHIP is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_NET_VENDOR_SEEQ is not set CONFIG_SMC91X=y -# CONFIG_NETDEV_1000 is not set -# CONFIG_NETDEV_10000 is not set +# CONFIG_NET_VENDOR_STMICRO is not set # CONFIG_WLAN is not set CONFIG_INPUT=m # CONFIG_INPUT_MOUSEDEV is not set @@ -79,11 +81,11 @@ CONFIG_INPUT_EVDEV=m # CONFIG_INPUT_MOUSE is not set # CONFIG_SERIO is not set # CONFIG_VT is not set -# CONFIG_DEVKMEM is not set +# CONFIG_LEGACY_PTYS is not set CONFIG_BFIN_JTAG_COMM=m +# CONFIG_DEVKMEM is not set CONFIG_SERIAL_BFIN=y CONFIG_SERIAL_BFIN_CONSOLE=y -# CONFIG_LEGACY_PTYS is not set # CONFIG_HW_RANDOM is not set CONFIG_SPI=y CONFIG_SPI_BFIN5XX=y @@ -97,12 +99,9 @@ CONFIG_BFIN_WDT=y CONFIG_JFFS2_FS=m CONFIG_NFS_FS=m CONFIG_NFS_V3=y -CONFIG_SMB_FS=m -CONFIG_DEBUG_KERNEL=y CONFIG_DEBUG_SHIRQ=y CONFIG_DETECT_HUNG_TASK=y CONFIG_DEBUG_INFO=y -# CONFIG_RCU_CPU_STALL_DETECTOR is not set # CONFIG_FTRACE is not set CONFIG_DEBUG_MMRS=y CONFIG_DEBUG_HWERR=y -- cgit v0.10.2 From 0db07a905628d7f2952691df40853ffd95ceb097 Mon Sep 17 00:00:00 2001 From: Bob Liu Date: Fri, 27 Jan 2012 22:10:04 +0800 Subject: blackfin: cleanup anomaly workarounds cleanup ANOMALY_05000312 and ANOMALY_05000244 Signed-off-by: Robin Getz Signed-off-by: Bob Liu diff --git a/arch/blackfin/include/asm/blackfin.h b/arch/blackfin/include/asm/blackfin.h index 0928700..7be5368 100644 --- a/arch/blackfin/include/asm/blackfin.h +++ b/arch/blackfin/include/asm/blackfin.h @@ -17,22 +17,16 @@ static inline void SSYNC(void) { int _tmp; - if (ANOMALY_05000312) + if (ANOMALY_05000312 || ANOMALY_05000244) __asm__ __volatile__( "cli %0;" "nop;" "nop;" + "nop;" "ssync;" "sti %0;" : "=d" (_tmp) ); - else if (ANOMALY_05000244) - __asm__ __volatile__( - "nop;" - "nop;" - "nop;" - "ssync;" - ); else __asm__ __volatile__("ssync;"); } @@ -41,22 +35,16 @@ static inline void SSYNC(void) static inline void CSYNC(void) { int _tmp; - if (ANOMALY_05000312) + if (ANOMALY_05000312 || ANOMALY_05000244) __asm__ __volatile__( "cli %0;" "nop;" "nop;" + "nop;" "csync;" "sti %0;" : "=d" (_tmp) ); - else if (ANOMALY_05000244) - __asm__ __volatile__( - "nop;" - "nop;" - "nop;" - "csync;" - ); else __asm__ __volatile__("csync;"); } @@ -73,18 +61,26 @@ static inline void CSYNC(void) #define ssync(x) SSYNC(x) #define csync(x) CSYNC(x) -#if ANOMALY_05000312 -#define SSYNC(scratch) cli scratch; nop; nop; SSYNC; sti scratch; -#define CSYNC(scratch) cli scratch; nop; nop; CSYNC; sti scratch; - -#elif ANOMALY_05000244 -#define SSYNC(scratch) nop; nop; nop; SSYNC; -#define CSYNC(scratch) nop; nop; nop; CSYNC; +#if ANOMALY_05000312 || ANOMALY_05000244 +#define SSYNC(scratch) \ +do { \ + cli scratch; \ + nop; nop; nop; \ + SSYNC; \ + sti scratch; \ +} while (0) + +#define CSYNC(scratch) \ +do { \ + cli scratch; \ + nop; nop; nop; \ + CSYNC; \ + sti scratch; \ +} while (0) #else #define SSYNC(scratch) SSYNC; #define CSYNC(scratch) CSYNC; - #endif /* ANOMALY_05000312 & ANOMALY_05000244 handling */ #endif /* __ASSEMBLY__ */ -- cgit v0.10.2 From dd47ba13786f22893d08747c152a2cf1435d0d8c Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Sun, 29 Jan 2012 05:32:39 -0500 Subject: Blackfin: wire up new process_vm syscalls Signed-off-by: Mike Frysinger Signed-off-by: Bob Liu diff --git a/arch/blackfin/include/asm/unistd.h b/arch/blackfin/include/asm/unistd.h index 0ccba60..75ec9df 100644 --- a/arch/blackfin/include/asm/unistd.h +++ b/arch/blackfin/include/asm/unistd.h @@ -399,8 +399,10 @@ #define __NR_syncfs 378 #define __NR_setns 379 #define __NR_sendmmsg 380 +#define __NR_process_vm_readv 381 +#define __NR_process_vm_writev 382 -#define __NR_syscall 381 +#define __NR_syscall 383 #define NR_syscalls __NR_syscall /* Old optional stuff no one actually uses */ diff --git a/arch/blackfin/mach-common/entry.S b/arch/blackfin/mach-common/entry.S index e413729..6d5102c 100644 --- a/arch/blackfin/mach-common/entry.S +++ b/arch/blackfin/mach-common/entry.S @@ -1755,6 +1755,8 @@ ENTRY(_sys_call_table) .long _sys_syncfs .long _sys_setns .long _sys_sendmmsg /* 380 */ + .long _sys_process_vm_readv + .long _sys_process_vm_writev .rept NR_syscalls-(.-_sys_call_table)/4 .long _sys_ni_syscall -- cgit v0.10.2 From 0eceb82f55a9e3756cada9e60ecc3a9b7b5979f5 Mon Sep 17 00:00:00 2001 From: Danny Kukawka Date: Thu, 16 Feb 2012 07:09:30 +0000 Subject: arch/blackfin: don't generate random mac in bfin_get_ether_addr() Changed bfin_get_ether_addr() to return a state and to set no random mac address if the board don't provide one. Let the caller of bfin_get_ether_addr() set a random mac address if the return value is not 0. v2: don't set random mac in bfin_get_ether_addr() Signed-off-by: Danny Kukawka Acked-by: Mike Frysinger Signed-off-by: David S. Miller Signed-off-by: Bob Liu diff --git a/arch/blackfin/mach-bf518/boards/ezbrd.c b/arch/blackfin/mach-bf518/boards/ezbrd.c index a2d96d3..a173957 100644 --- a/arch/blackfin/mach-bf518/boards/ezbrd.c +++ b/arch/blackfin/mach-bf518/boards/ezbrd.c @@ -821,7 +821,7 @@ void native_machine_restart(char *cmd) bfin_reset_boot_spi_cs(P_DEFAULT_BOOT_SPI_CS); } -void bfin_get_ether_addr(char *addr) +int bfin_get_ether_addr(char *addr) { /* the MAC is stored in OTP memory page 0xDF */ u32 ret; @@ -834,5 +834,6 @@ void bfin_get_ether_addr(char *addr) for (ret = 0; ret < 6; ++ret) addr[ret] = otp_mac_p[5 - ret]; } + return 0; } EXPORT_SYMBOL(bfin_get_ether_addr); diff --git a/arch/blackfin/mach-bf518/boards/tcm-bf518.c b/arch/blackfin/mach-bf518/boards/tcm-bf518.c index f271310..6eebee4 100644 --- a/arch/blackfin/mach-bf518/boards/tcm-bf518.c +++ b/arch/blackfin/mach-bf518/boards/tcm-bf518.c @@ -730,9 +730,8 @@ void native_machine_restart(char *cmd) bfin_reset_boot_spi_cs(P_DEFAULT_BOOT_SPI_CS); } -void bfin_get_ether_addr(char *addr) +int bfin_get_ether_addr(char *addr) { - random_ether_addr(addr); - printk(KERN_WARNING "%s:%s: Setting Ethernet MAC to a random one\n", __FILE__, __func__); + return 1; } EXPORT_SYMBOL(bfin_get_ether_addr); diff --git a/arch/blackfin/mach-bf527/boards/ad7160eval.c b/arch/blackfin/mach-bf527/boards/ad7160eval.c index c8d5d2b..fad7fea 100644 --- a/arch/blackfin/mach-bf527/boards/ad7160eval.c +++ b/arch/blackfin/mach-bf527/boards/ad7160eval.c @@ -846,7 +846,7 @@ void native_machine_restart(char *cmd) bfin_reset_boot_spi_cs(P_DEFAULT_BOOT_SPI_CS); } -void bfin_get_ether_addr(char *addr) +int bfin_get_ether_addr(char *addr) { /* the MAC is stored in OTP memory page 0xDF */ u32 ret; @@ -859,5 +859,6 @@ void bfin_get_ether_addr(char *addr) for (ret = 0; ret < 6; ++ret) addr[ret] = otp_mac_p[5 - ret]; } + return 0; } EXPORT_SYMBOL(bfin_get_ether_addr); diff --git a/arch/blackfin/mach-bf527/boards/cm_bf527.c b/arch/blackfin/mach-bf527/boards/cm_bf527.c index 7330607..65b7fbd 100644 --- a/arch/blackfin/mach-bf527/boards/cm_bf527.c +++ b/arch/blackfin/mach-bf527/boards/cm_bf527.c @@ -983,9 +983,8 @@ void native_machine_restart(char *cmd) bfin_reset_boot_spi_cs(P_DEFAULT_BOOT_SPI_CS); } -void bfin_get_ether_addr(char *addr) +int bfin_get_ether_addr(char *addr) { - random_ether_addr(addr); - printk(KERN_WARNING "%s:%s: Setting Ethernet MAC to a random one\n", __FILE__, __func__); + return 1; } EXPORT_SYMBOL(bfin_get_ether_addr); diff --git a/arch/blackfin/mach-bf527/boards/ezbrd.c b/arch/blackfin/mach-bf527/boards/ezbrd.c index db3ecfc..17c6a24 100644 --- a/arch/blackfin/mach-bf527/boards/ezbrd.c +++ b/arch/blackfin/mach-bf527/boards/ezbrd.c @@ -870,7 +870,7 @@ void native_machine_restart(char *cmd) bfin_reset_boot_spi_cs(P_DEFAULT_BOOT_SPI_CS); } -void bfin_get_ether_addr(char *addr) +int bfin_get_ether_addr(char *addr) { /* the MAC is stored in OTP memory page 0xDF */ u32 ret; @@ -883,5 +883,6 @@ void bfin_get_ether_addr(char *addr) for (ret = 0; ret < 6; ++ret) addr[ret] = otp_mac_p[5 - ret]; } + return 0; } EXPORT_SYMBOL(bfin_get_ether_addr); diff --git a/arch/blackfin/mach-bf527/boards/ezkit.c b/arch/blackfin/mach-bf527/boards/ezkit.c index dfdd8e6..2f9a2bd 100644 --- a/arch/blackfin/mach-bf527/boards/ezkit.c +++ b/arch/blackfin/mach-bf527/boards/ezkit.c @@ -1311,7 +1311,7 @@ void native_machine_restart(char *cmd) bfin_reset_boot_spi_cs(P_DEFAULT_BOOT_SPI_CS); } -void bfin_get_ether_addr(char *addr) +int bfin_get_ether_addr(char *addr) { /* the MAC is stored in OTP memory page 0xDF */ u32 ret; @@ -1324,5 +1324,6 @@ void bfin_get_ether_addr(char *addr) for (ret = 0; ret < 6; ++ret) addr[ret] = otp_mac_p[5 - ret]; } + return 0; } EXPORT_SYMBOL(bfin_get_ether_addr); diff --git a/arch/blackfin/mach-bf527/boards/tll6527m.c b/arch/blackfin/mach-bf527/boards/tll6527m.c index 360e97f..d192c0a 100644 --- a/arch/blackfin/mach-bf527/boards/tll6527m.c +++ b/arch/blackfin/mach-bf527/boards/tll6527m.c @@ -931,7 +931,7 @@ void native_machine_restart(char *cmd) bfin_reset_boot_spi_cs(P_DEFAULT_BOOT_SPI_CS); } -void bfin_get_ether_addr(char *addr) +int bfin_get_ether_addr(char *addr) { /* the MAC is stored in OTP memory page 0xDF */ u32 ret; @@ -945,5 +945,6 @@ void bfin_get_ether_addr(char *addr) for (ret = 0; ret < 6; ++ret) addr[ret] = otp_mac_p[5 - ret]; } + return 0; } EXPORT_SYMBOL(bfin_get_ether_addr); diff --git a/arch/blackfin/mach-bf537/boards/cm_bf537e.c b/arch/blackfin/mach-bf537/boards/cm_bf537e.c index 0d4a2f6..27fd2c3 100644 --- a/arch/blackfin/mach-bf537/boards/cm_bf537e.c +++ b/arch/blackfin/mach-bf537/boards/cm_bf537e.c @@ -813,9 +813,8 @@ void __init native_machine_early_platform_add_devices(void) ARRAY_SIZE(cm_bf537e_early_devices)); } -void bfin_get_ether_addr(char *addr) +int bfin_get_ether_addr(char *addr) { - random_ether_addr(addr); - printk(KERN_WARNING "%s:%s: Setting Ethernet MAC to a random one\n", __FILE__, __func__); + return 1; } EXPORT_SYMBOL(bfin_get_ether_addr); diff --git a/arch/blackfin/mach-bf537/boards/cm_bf537u.c b/arch/blackfin/mach-bf537/boards/cm_bf537u.c index f553698..3f3abad 100644 --- a/arch/blackfin/mach-bf537/boards/cm_bf537u.c +++ b/arch/blackfin/mach-bf537/boards/cm_bf537u.c @@ -790,9 +790,8 @@ void __init native_machine_early_platform_add_devices(void) ARRAY_SIZE(cm_bf537u_early_devices)); } -void bfin_get_ether_addr(char *addr) +int bfin_get_ether_addr(char *addr) { - random_ether_addr(addr); - printk(KERN_WARNING "%s:%s: Setting Ethernet MAC to a random one\n", __FILE__, __func__); + return 1; } EXPORT_SYMBOL(bfin_get_ether_addr); diff --git a/arch/blackfin/mach-bf537/boards/dnp5370.c b/arch/blackfin/mach-bf537/boards/dnp5370.c index 11dadeb..6f77bf7 100644 --- a/arch/blackfin/mach-bf537/boards/dnp5370.c +++ b/arch/blackfin/mach-bf537/boards/dnp5370.c @@ -399,9 +399,10 @@ arch_initcall(dnp5370_init); /* * Currently the MAC address is saved in Flash by U-Boot */ -void bfin_get_ether_addr(char *addr) +int bfin_get_ether_addr(char *addr) { *(u32 *)(&(addr[0])) = bfin_read32(FLASH_MAC); *(u16 *)(&(addr[4])) = bfin_read16(FLASH_MAC + 4); + return 0; } EXPORT_SYMBOL(bfin_get_ether_addr); diff --git a/arch/blackfin/mach-bf537/boards/pnav10.c b/arch/blackfin/mach-bf537/boards/pnav10.c index 6fd8470..e9507fe 100644 --- a/arch/blackfin/mach-bf537/boards/pnav10.c +++ b/arch/blackfin/mach-bf537/boards/pnav10.c @@ -535,9 +535,8 @@ void __init native_machine_early_platform_add_devices(void) ARRAY_SIZE(stamp_early_devices)); } -void bfin_get_ether_addr(char *addr) +int bfin_get_ether_addr(char *addr) { - random_ether_addr(addr); - printk(KERN_WARNING "%s:%s: Setting Ethernet MAC to a random one\n", __FILE__, __func__); + return 1; } EXPORT_SYMBOL(bfin_get_ether_addr); diff --git a/arch/blackfin/mach-bf537/boards/stamp.c b/arch/blackfin/mach-bf537/boards/stamp.c index f2c0629..f3562b0 100644 --- a/arch/blackfin/mach-bf537/boards/stamp.c +++ b/arch/blackfin/mach-bf537/boards/stamp.c @@ -3013,9 +3013,10 @@ void native_machine_restart(char *cmd) * Currently the MAC address is saved in Flash by U-Boot */ #define FLASH_MAC 0x203f0000 -void bfin_get_ether_addr(char *addr) +int bfin_get_ether_addr(char *addr) { *(u32 *)(&(addr[0])) = bfin_read32(FLASH_MAC); *(u16 *)(&(addr[4])) = bfin_read16(FLASH_MAC + 4); + return 0; } EXPORT_SYMBOL(bfin_get_ether_addr); diff --git a/arch/blackfin/mach-bf537/boards/tcm_bf537.c b/arch/blackfin/mach-bf537/boards/tcm_bf537.c index 9885176..3fb4218 100644 --- a/arch/blackfin/mach-bf537/boards/tcm_bf537.c +++ b/arch/blackfin/mach-bf537/boards/tcm_bf537.c @@ -780,9 +780,8 @@ void __init native_machine_early_platform_add_devices(void) ARRAY_SIZE(cm_bf537_early_devices)); } -void bfin_get_ether_addr(char *addr) +int bfin_get_ether_addr(char *addr) { - random_ether_addr(addr); - printk(KERN_WARNING "%s:%s: Setting Ethernet MAC to a random one\n", __FILE__, __func__); + return 1; } EXPORT_SYMBOL(bfin_get_ether_addr); -- cgit v0.10.2 From 3bed8d67469cc7129b0babc0211c32fa68408ce0 Mon Sep 17 00:00:00 2001 From: David Howells Date: Mon, 12 Mar 2012 23:36:56 +0000 Subject: Disintegrate asm/system.h for Blackfin [ver #2] Disintegrate asm/system.h for Blackfin. Signed-off-by: David Howells cc: uclinux-dist-devel@blackfin.uclinux.org Signed-off-by: Bob Liu diff --git a/arch/blackfin/include/asm/atomic.h b/arch/blackfin/include/asm/atomic.h index 54c6e28..c8db653 100644 --- a/arch/blackfin/include/asm/atomic.h +++ b/arch/blackfin/include/asm/atomic.h @@ -7,6 +7,8 @@ #ifndef __ARCH_BLACKFIN_ATOMIC__ #define __ARCH_BLACKFIN_ATOMIC__ +#include + #ifdef CONFIG_SMP #include diff --git a/arch/blackfin/include/asm/barrier.h b/arch/blackfin/include/asm/barrier.h new file mode 100644 index 0000000..ebb1895 --- /dev/null +++ b/arch/blackfin/include/asm/barrier.h @@ -0,0 +1,48 @@ +/* + * Copyright 2004-2009 Analog Devices Inc. + * Tony Kou (tonyko@lineo.ca) + * + * Licensed under the GPL-2 or later + */ + +#ifndef _BLACKFIN_BARRIER_H +#define _BLACKFIN_BARRIER_H + +#include + +#define nop() __asm__ __volatile__ ("nop;\n\t" : : ) + +/* + * Force strict CPU ordering. + */ +#ifdef CONFIG_SMP + +#ifdef __ARCH_SYNC_CORE_DCACHE +/* Force Core data cache coherence */ +# define mb() do { barrier(); smp_check_barrier(); smp_mark_barrier(); } while (0) +# define rmb() do { barrier(); smp_check_barrier(); } while (0) +# define wmb() do { barrier(); smp_mark_barrier(); } while (0) +# define read_barrier_depends() do { barrier(); smp_check_barrier(); } while (0) +#else +# define mb() barrier() +# define rmb() barrier() +# define wmb() barrier() +# define read_barrier_depends() do { } while (0) +#endif + +#else /* !CONFIG_SMP */ + +#define mb() barrier() +#define rmb() barrier() +#define wmb() barrier() +#define read_barrier_depends() do { } while (0) + +#endif /* !CONFIG_SMP */ + +#define smp_mb() mb() +#define smp_rmb() rmb() +#define smp_wmb() wmb() +#define set_mb(var, value) do { var = value; mb(); } while (0) +#define smp_read_barrier_depends() read_barrier_depends() + +#endif /* _BLACKFIN_BARRIER_H */ diff --git a/arch/blackfin/include/asm/cmpxchg.h b/arch/blackfin/include/asm/cmpxchg.h new file mode 100644 index 0000000..ba2484f --- /dev/null +++ b/arch/blackfin/include/asm/cmpxchg.h @@ -0,0 +1,132 @@ +/* + * Copyright 2004-2011 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#ifndef __ARCH_BLACKFIN_CMPXCHG__ +#define __ARCH_BLACKFIN_CMPXCHG__ + +#ifdef CONFIG_SMP + +#include + +asmlinkage unsigned long __raw_xchg_1_asm(volatile void *ptr, unsigned long value); +asmlinkage unsigned long __raw_xchg_2_asm(volatile void *ptr, unsigned long value); +asmlinkage unsigned long __raw_xchg_4_asm(volatile void *ptr, unsigned long value); +asmlinkage unsigned long __raw_cmpxchg_1_asm(volatile void *ptr, + unsigned long new, unsigned long old); +asmlinkage unsigned long __raw_cmpxchg_2_asm(volatile void *ptr, + unsigned long new, unsigned long old); +asmlinkage unsigned long __raw_cmpxchg_4_asm(volatile void *ptr, + unsigned long new, unsigned long old); + +static inline unsigned long __xchg(unsigned long x, volatile void *ptr, + int size) +{ + unsigned long tmp; + + switch (size) { + case 1: + tmp = __raw_xchg_1_asm(ptr, x); + break; + case 2: + tmp = __raw_xchg_2_asm(ptr, x); + break; + case 4: + tmp = __raw_xchg_4_asm(ptr, x); + break; + } + + return tmp; +} + +/* + * Atomic compare and exchange. Compare OLD with MEM, if identical, + * store NEW in MEM. Return the initial value in MEM. Success is + * indicated by comparing RETURN with OLD. + */ +static inline unsigned long __cmpxchg(volatile void *ptr, unsigned long old, + unsigned long new, int size) +{ + unsigned long tmp; + + switch (size) { + case 1: + tmp = __raw_cmpxchg_1_asm(ptr, new, old); + break; + case 2: + tmp = __raw_cmpxchg_2_asm(ptr, new, old); + break; + case 4: + tmp = __raw_cmpxchg_4_asm(ptr, new, old); + break; + } + + return tmp; +} +#define cmpxchg(ptr, o, n) \ + ((__typeof__(*(ptr)))__cmpxchg((ptr), (unsigned long)(o), \ + (unsigned long)(n), sizeof(*(ptr)))) + +#else /* !CONFIG_SMP */ + +#include +#include + +struct __xchg_dummy { + unsigned long a[100]; +}; +#define __xg(x) ((volatile struct __xchg_dummy *)(x)) + +static inline unsigned long __xchg(unsigned long x, volatile void *ptr, + int size) +{ + unsigned long tmp = 0; + unsigned long flags; + + flags = hard_local_irq_save(); + + switch (size) { + case 1: + __asm__ __volatile__ + ("%0 = b%2 (z);\n\t" + "b%2 = %1;\n\t" + : "=&d" (tmp) : "d" (x), "m" (*__xg(ptr)) : "memory"); + break; + case 2: + __asm__ __volatile__ + ("%0 = w%2 (z);\n\t" + "w%2 = %1;\n\t" + : "=&d" (tmp) : "d" (x), "m" (*__xg(ptr)) : "memory"); + break; + case 4: + __asm__ __volatile__ + ("%0 = %2;\n\t" + "%2 = %1;\n\t" + : "=&d" (tmp) : "d" (x), "m" (*__xg(ptr)) : "memory"); + break; + } + hard_local_irq_restore(flags); + return tmp; +} + +#include + +/* + * cmpxchg_local and cmpxchg64_local are atomic wrt current CPU. Always make + * them available. + */ +#define cmpxchg_local(ptr, o, n) \ + ((__typeof__(*(ptr)))__cmpxchg_local_generic((ptr), (unsigned long)(o),\ + (unsigned long)(n), sizeof(*(ptr)))) +#define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n)) + +#include + +#endif /* !CONFIG_SMP */ + +#define xchg(ptr, x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x), (ptr), sizeof(*(ptr)))) +#define tas(ptr) ((void)xchg((ptr), 1)) + +#endif /* __ARCH_BLACKFIN_CMPXCHG__ */ diff --git a/arch/blackfin/include/asm/exec.h b/arch/blackfin/include/asm/exec.h new file mode 100644 index 0000000..54c2e1d --- /dev/null +++ b/arch/blackfin/include/asm/exec.h @@ -0,0 +1 @@ +/* define arch_align_stack() here */ diff --git a/arch/blackfin/include/asm/irq_handler.h b/arch/blackfin/include/asm/irq_handler.h index ee73f79..4fbf835 100644 --- a/arch/blackfin/include/asm/irq_handler.h +++ b/arch/blackfin/include/asm/irq_handler.h @@ -9,6 +9,7 @@ #include #include +#include /* init functions only */ extern int __init init_arch_irq(void); diff --git a/arch/blackfin/include/asm/switch_to.h b/arch/blackfin/include/asm/switch_to.h new file mode 100644 index 0000000..aaf671b --- /dev/null +++ b/arch/blackfin/include/asm/switch_to.h @@ -0,0 +1,39 @@ +/* + * Copyright 2004-2009 Analog Devices Inc. + * Tony Kou (tonyko@lineo.ca) + * + * Licensed under the GPL-2 or later + */ + +#ifndef _BLACKFIN_SWITCH_TO_H +#define _BLACKFIN_SWITCH_TO_H + +#define prepare_to_switch() do { } while(0) + +/* + * switch_to(n) should switch tasks to task ptr, first checking that + * ptr isn't the current task, in which case it does nothing. + */ + +#include +#include + +asmlinkage struct task_struct *resume(struct task_struct *prev, struct task_struct *next); + +#ifndef CONFIG_SMP +#define switch_to(prev,next,last) \ +do { \ + memcpy (&task_thread_info(prev)->l1_task_info, L1_SCRATCH_TASK_INFO, \ + sizeof *L1_SCRATCH_TASK_INFO); \ + memcpy (L1_SCRATCH_TASK_INFO, &task_thread_info(next)->l1_task_info, \ + sizeof *L1_SCRATCH_TASK_INFO); \ + (last) = resume (prev, next); \ +} while (0) +#else +#define switch_to(prev, next, last) \ +do { \ + (last) = resume(prev, next); \ +} while (0) +#endif + +#endif /* _BLACKFIN_SWITCH_TO_H */ diff --git a/arch/blackfin/include/asm/system.h b/arch/blackfin/include/asm/system.h index 44bd0cc..a7f4057 100644 --- a/arch/blackfin/include/asm/system.h +++ b/arch/blackfin/include/asm/system.h @@ -1,192 +1,5 @@ -/* - * Copyright 2004-2009 Analog Devices Inc. - * Tony Kou (tonyko@lineo.ca) - * - * Licensed under the GPL-2 or later - */ - -#ifndef _BLACKFIN_SYSTEM_H -#define _BLACKFIN_SYSTEM_H - -#include -#include -#include -#include -#include -#include - -/* - * Force strict CPU ordering. - */ -#define nop() __asm__ __volatile__ ("nop;\n\t" : : ) -#define smp_mb() mb() -#define smp_rmb() rmb() -#define smp_wmb() wmb() -#define set_mb(var, value) do { var = value; mb(); } while (0) -#define smp_read_barrier_depends() read_barrier_depends() - -#ifdef CONFIG_SMP -asmlinkage unsigned long __raw_xchg_1_asm(volatile void *ptr, unsigned long value); -asmlinkage unsigned long __raw_xchg_2_asm(volatile void *ptr, unsigned long value); -asmlinkage unsigned long __raw_xchg_4_asm(volatile void *ptr, unsigned long value); -asmlinkage unsigned long __raw_cmpxchg_1_asm(volatile void *ptr, - unsigned long new, unsigned long old); -asmlinkage unsigned long __raw_cmpxchg_2_asm(volatile void *ptr, - unsigned long new, unsigned long old); -asmlinkage unsigned long __raw_cmpxchg_4_asm(volatile void *ptr, - unsigned long new, unsigned long old); - -#ifdef __ARCH_SYNC_CORE_DCACHE -/* Force Core data cache coherence */ -# define mb() do { barrier(); smp_check_barrier(); smp_mark_barrier(); } while (0) -# define rmb() do { barrier(); smp_check_barrier(); } while (0) -# define wmb() do { barrier(); smp_mark_barrier(); } while (0) -# define read_barrier_depends() do { barrier(); smp_check_barrier(); } while (0) -#else -# define mb() barrier() -# define rmb() barrier() -# define wmb() barrier() -# define read_barrier_depends() do { } while (0) -#endif - -static inline unsigned long __xchg(unsigned long x, volatile void *ptr, - int size) -{ - unsigned long tmp; - - switch (size) { - case 1: - tmp = __raw_xchg_1_asm(ptr, x); - break; - case 2: - tmp = __raw_xchg_2_asm(ptr, x); - break; - case 4: - tmp = __raw_xchg_4_asm(ptr, x); - break; - } - - return tmp; -} - -/* - * Atomic compare and exchange. Compare OLD with MEM, if identical, - * store NEW in MEM. Return the initial value in MEM. Success is - * indicated by comparing RETURN with OLD. - */ -static inline unsigned long __cmpxchg(volatile void *ptr, unsigned long old, - unsigned long new, int size) -{ - unsigned long tmp; - - switch (size) { - case 1: - tmp = __raw_cmpxchg_1_asm(ptr, new, old); - break; - case 2: - tmp = __raw_cmpxchg_2_asm(ptr, new, old); - break; - case 4: - tmp = __raw_cmpxchg_4_asm(ptr, new, old); - break; - } - - return tmp; -} -#define cmpxchg(ptr, o, n) \ - ((__typeof__(*(ptr)))__cmpxchg((ptr), (unsigned long)(o), \ - (unsigned long)(n), sizeof(*(ptr)))) - -#else /* !CONFIG_SMP */ - -#define mb() barrier() -#define rmb() barrier() -#define wmb() barrier() -#define read_barrier_depends() do { } while (0) - -struct __xchg_dummy { - unsigned long a[100]; -}; -#define __xg(x) ((volatile struct __xchg_dummy *)(x)) - -#include - -static inline unsigned long __xchg(unsigned long x, volatile void *ptr, - int size) -{ - unsigned long tmp = 0; - unsigned long flags; - - flags = hard_local_irq_save(); - - switch (size) { - case 1: - __asm__ __volatile__ - ("%0 = b%2 (z);\n\t" - "b%2 = %1;\n\t" - : "=&d" (tmp) : "d" (x), "m" (*__xg(ptr)) : "memory"); - break; - case 2: - __asm__ __volatile__ - ("%0 = w%2 (z);\n\t" - "w%2 = %1;\n\t" - : "=&d" (tmp) : "d" (x), "m" (*__xg(ptr)) : "memory"); - break; - case 4: - __asm__ __volatile__ - ("%0 = %2;\n\t" - "%2 = %1;\n\t" - : "=&d" (tmp) : "d" (x), "m" (*__xg(ptr)) : "memory"); - break; - } - hard_local_irq_restore(flags); - return tmp; -} - -#include - -/* - * cmpxchg_local and cmpxchg64_local are atomic wrt current CPU. Always make - * them available. - */ -#define cmpxchg_local(ptr, o, n) \ - ((__typeof__(*(ptr)))__cmpxchg_local_generic((ptr), (unsigned long)(o),\ - (unsigned long)(n), sizeof(*(ptr)))) -#define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n)) - -#include - -#endif /* !CONFIG_SMP */ - -#define xchg(ptr, x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x), (ptr), sizeof(*(ptr)))) -#define tas(ptr) ((void)xchg((ptr), 1)) - -#define prepare_to_switch() do { } while(0) - -/* - * switch_to(n) should switch tasks to task ptr, first checking that - * ptr isn't the current task, in which case it does nothing. - */ - -#include -#include - -asmlinkage struct task_struct *resume(struct task_struct *prev, struct task_struct *next); - -#ifndef CONFIG_SMP -#define switch_to(prev,next,last) \ -do { \ - memcpy (&task_thread_info(prev)->l1_task_info, L1_SCRATCH_TASK_INFO, \ - sizeof *L1_SCRATCH_TASK_INFO); \ - memcpy (L1_SCRATCH_TASK_INFO, &task_thread_info(next)->l1_task_info, \ - sizeof *L1_SCRATCH_TASK_INFO); \ - (last) = resume (prev, next); \ -} while (0) -#else -#define switch_to(prev, next, last) \ -do { \ - (last) = resume(prev, next); \ -} while (0) -#endif - -#endif /* _BLACKFIN_SYSTEM_H */ +/* FILE TO BE DELETED. DO NOT ADD STUFF HERE! */ +#include +#include +#include +#include diff --git a/arch/blackfin/kernel/asm-offsets.c b/arch/blackfin/kernel/asm-offsets.c index 17e3546..37fcae9 100644 --- a/arch/blackfin/kernel/asm-offsets.c +++ b/arch/blackfin/kernel/asm-offsets.c @@ -14,6 +14,7 @@ #include #include #include +#include int main(void) { diff --git a/arch/blackfin/kernel/ipipe.c b/arch/blackfin/kernel/ipipe.c index dbe1122..f657b38 100644 --- a/arch/blackfin/kernel/ipipe.c +++ b/arch/blackfin/kernel/ipipe.c @@ -31,7 +31,6 @@ #include #include #include -#include #include #include diff --git a/arch/blackfin/kernel/kgdb_test.c b/arch/blackfin/kernel/kgdb_test.c index 4a7dcfe..18ab004 100644 --- a/arch/blackfin/kernel/kgdb_test.c +++ b/arch/blackfin/kernel/kgdb_test.c @@ -13,7 +13,6 @@ #include #include -#include #include diff --git a/arch/blackfin/kernel/process.c b/arch/blackfin/kernel/process.c index a80a643..c0f4fe2 100644 --- a/arch/blackfin/kernel/process.c +++ b/arch/blackfin/kernel/process.c @@ -19,6 +19,7 @@ #include #include #include +#include asmlinkage void ret_from_fork(void); diff --git a/arch/blackfin/kernel/ptrace.c b/arch/blackfin/kernel/ptrace.c index 75089f8..e1f88e0 100644 --- a/arch/blackfin/kernel/ptrace.c +++ b/arch/blackfin/kernel/ptrace.c @@ -20,7 +20,6 @@ #include #include -#include #include #include #include diff --git a/arch/blackfin/kernel/reboot.c b/arch/blackfin/kernel/reboot.c index c4c0081..b0434f8 100644 --- a/arch/blackfin/kernel/reboot.c +++ b/arch/blackfin/kernel/reboot.c @@ -9,7 +9,6 @@ #include #include #include -#include #include /* A system soft reset makes external memory unusable so force diff --git a/arch/blackfin/kernel/setup.c b/arch/blackfin/kernel/setup.c index d6102c8..2aa0193 100644 --- a/arch/blackfin/kernel/setup.c +++ b/arch/blackfin/kernel/setup.c @@ -30,6 +30,7 @@ #include #include #include +#include u16 _bfin_swrst; EXPORT_SYMBOL(_bfin_swrst); diff --git a/arch/blackfin/kernel/trace.c b/arch/blackfin/kernel/trace.c index 050db44..44bbf2f 100644 --- a/arch/blackfin/kernel/trace.c +++ b/arch/blackfin/kernel/trace.c @@ -21,6 +21,7 @@ #include #include #include +#include void decode_address(char *buf, unsigned long address) { diff --git a/arch/blackfin/kernel/traps.c b/arch/blackfin/kernel/traps.c index 655f25d..de5c2c3 100644 --- a/arch/blackfin/kernel/traps.c +++ b/arch/blackfin/kernel/traps.c @@ -17,6 +17,7 @@ #include #include #include +#include #ifdef CONFIG_KGDB # include -- cgit v0.10.2 From 45a93315d829cfafb83eea0bf76b7346b6f0d072 Mon Sep 17 00:00:00 2001 From: Bob Liu Date: Mon, 6 Feb 2012 16:44:33 +0800 Subject: arch: blackfin: udpate defconfig choose musb by default for bf527 and bf548. Signed-off-by: Bob Liu diff --git a/arch/blackfin/configs/BF527-EZKIT-V2_defconfig b/arch/blackfin/configs/BF527-EZKIT-V2_defconfig index 9325d75..91535c3 100644 --- a/arch/blackfin/configs/BF527-EZKIT-V2_defconfig +++ b/arch/blackfin/configs/BF527-EZKIT-V2_defconfig @@ -151,7 +151,10 @@ CONFIG_USB_DEVICEFS=y # CONFIG_USB_DEVICE_CLASS is not set CONFIG_USB_OTG_BLACKLIST_HUB=y CONFIG_USB_MON=y +CONFIG_USB_MUSB_HDRC=y +CONFIG_USB_MUSB_BLACKFIN=y CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y CONFIG_NEW_LEDS=y CONFIG_LEDS_CLASS=y CONFIG_LEDS_ADP5520=y diff --git a/arch/blackfin/configs/BF527-EZKIT_defconfig b/arch/blackfin/configs/BF527-EZKIT_defconfig index b953be0..9ccc18a 100644 --- a/arch/blackfin/configs/BF527-EZKIT_defconfig +++ b/arch/blackfin/configs/BF527-EZKIT_defconfig @@ -145,7 +145,10 @@ CONFIG_USB_DEVICEFS=y # CONFIG_USB_DEVICE_CLASS is not set CONFIG_USB_OTG_BLACKLIST_HUB=y CONFIG_USB_MON=y +CONFIG_USB_MUSB_HDRC=y +CONFIG_USB_MUSB_BLACKFIN=y CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y CONFIG_RTC_CLASS=y CONFIG_RTC_DRV_BFIN=y CONFIG_EXT2_FS=m diff --git a/arch/blackfin/configs/BF548-EZKIT_defconfig b/arch/blackfin/configs/BF548-EZKIT_defconfig index 296de92..e716fdf 100644 --- a/arch/blackfin/configs/BF548-EZKIT_defconfig +++ b/arch/blackfin/configs/BF548-EZKIT_defconfig @@ -163,7 +163,10 @@ CONFIG_USB_DEVICEFS=y # CONFIG_USB_DEVICE_CLASS is not set CONFIG_USB_OTG_BLACKLIST_HUB=y CONFIG_USB_MON=y +CONFIG_USB_MUSB_HDRC=y +CONFIG_USB_MUSB_BLACKFIN=y CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y CONFIG_MMC=y CONFIG_MMC_BLOCK=m CONFIG_SDH_BFIN=y -- cgit v0.10.2 From 1957b665fbbdb720940c5161b27a8b597f5c090a Mon Sep 17 00:00:00 2001 From: Scott Jiang Date: Fri, 10 Feb 2012 15:38:49 -0500 Subject: bf561: add ppi DLEN macro for 10bits to 16bits Signed-off-by: Scott Jiang Signed-off-by: Bob Liu diff --git a/arch/blackfin/mach-bf561/include/mach/defBF561.h b/arch/blackfin/mach-bf561/include/mach/defBF561.h index 7d712ae..5f0ac5a 100644 --- a/arch/blackfin/mach-bf561/include/mach/defBF561.h +++ b/arch/blackfin/mach-bf561/include/mach/defBF561.h @@ -879,6 +879,13 @@ #define DLENGTH 0x00003800 /* PPI Data Length */ #define DLEN_8 0x0 /* PPI Data Length mask for DLEN=8 */ #define DLEN(x) (((x-9) & 0x07) << 11) /* PPI Data Length (only works for x=10-->x=16) */ +#define DLEN_10 0x00000800 /* Data Length = 10 Bits */ +#define DLEN_11 0x00001000 /* Data Length = 11 Bits */ +#define DLEN_12 0x00001800 /* Data Length = 12 Bits */ +#define DLEN_13 0x00002000 /* Data Length = 13 Bits */ +#define DLEN_14 0x00002800 /* Data Length = 14 Bits */ +#define DLEN_15 0x00003000 /* Data Length = 15 Bits */ +#define DLEN_16 0x00003800 /* Data Length = 16 Bits */ #define POL 0x0000C000 /* PPI Signal Polarities */ #define POLC 0x4000 /* PPI Clock Polarity */ #define POLS 0x8000 /* PPI Frame Sync Polarity */ -- cgit v0.10.2 From 0e233fb00dd1dfe5931eafc922e432ab46370bf9 Mon Sep 17 00:00:00 2001 From: Danny Kukawka Date: Thu, 16 Feb 2012 14:56:24 +0100 Subject: Blackfin: pnav: delete duplicate linux/export.h include arch/blackfin/mach-bf537/boards/pnav10.c includes 'linux/export.h' twice. No need to include the file a second time in a #ifdef block if already included at top. Remove the duplicate. Signed-off-by: Danny Kukawka Signed-off-by: Mike Frysinger Signed-off-by: Bob Liu diff --git a/arch/blackfin/mach-bf537/boards/pnav10.c b/arch/blackfin/mach-bf537/boards/pnav10.c index e9507fe..6b39551 100644 --- a/arch/blackfin/mach-bf537/boards/pnav10.c +++ b/arch/blackfin/mach-bf537/boards/pnav10.c @@ -101,7 +101,6 @@ static struct platform_device smc91x_device = { #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE) #include -#include static const unsigned short bfin_mac_peripherals[] = P_RMII0; static struct bfin_phydev_platform_data bfin_phydev_data[] = { -- cgit v0.10.2 From ce6da7cd896b38a68ef0e93e2cdf46a2a7c3762b Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Sun, 19 Feb 2012 16:11:55 +0100 Subject: Blackfin: s/#if CONFIG/#ifdef CONFIG/ Signed-off-by: Geert Uytterhoeven Signed-off-by: Mike Frysinger Signed-off-by: Bob Liu diff --git a/arch/blackfin/mach-common/entry.S b/arch/blackfin/mach-common/entry.S index 6d5102c..4698a98 100644 --- a/arch/blackfin/mach-common/entry.S +++ b/arch/blackfin/mach-common/entry.S @@ -1244,7 +1244,7 @@ ENTRY(_software_trace_buff) .endr #endif /* CONFIG_DEBUG_BFIN_HWTRACE_EXPAND */ -#if CONFIG_EARLY_PRINTK +#ifdef CONFIG_EARLY_PRINTK __INIT ENTRY(_early_trap) SAVE_ALL_SYS -- cgit v0.10.2 From eeec0a13e5d360fe11d8354098b915f0e464b7d3 Mon Sep 17 00:00:00 2001 From: Sonic Zhang Date: Fri, 16 Mar 2012 12:52:34 +0800 Subject: bf548: ssm2602: Add ssm2602 platform data into bf548 ezkit board file. Signed-off-by: Sonic Zhang Signed-off-by: Bob Liu diff --git a/arch/blackfin/mach-bf548/boards/ezkit.c b/arch/blackfin/mach-bf548/boards/ezkit.c index 4595a40..4cadaf8 100644 --- a/arch/blackfin/mach-bf548/boards/ezkit.c +++ b/arch/blackfin/mach-bf548/boards/ezkit.c @@ -1295,6 +1295,11 @@ static struct platform_device i2c_bfin_twi1_device = { #endif static struct i2c_board_info __initdata bfin_i2c_board_info0[] = { +#if defined(CONFIG_SND_SOC_SSM2602) || defined(CONFIG_SND_SOC_SSM2602_MODULE) + { + I2C_BOARD_INFO("ssm2602", 0x1b), + }, +#endif }; #if !defined(CONFIG_BF542) /* The BF542 only has 1 TWI */ @@ -1387,6 +1392,8 @@ static struct platform_device bfin_dpmc = { static const u16 bfin_snd_pin[][7] = { SPORT_REQ(0), SPORT_REQ(1), + SPORT_REQ(2), + SPORT_REQ(3), }; static struct bfin_snd_platform_data bfin_snd_data[] = { @@ -1396,6 +1403,12 @@ static struct bfin_snd_platform_data bfin_snd_data[] = { { .pin_req = &bfin_snd_pin[1][0], }, + { + .pin_req = &bfin_snd_pin[2][0], + }, + { + .pin_req = &bfin_snd_pin[3][0], + }, }; #define BFIN_SND_RES(x) \ @@ -1425,10 +1438,28 @@ static struct bfin_snd_platform_data bfin_snd_data[] = { static struct resource bfin_snd_resources[][4] = { BFIN_SND_RES(0), BFIN_SND_RES(1), + BFIN_SND_RES(2), + BFIN_SND_RES(3), }; +#endif -static struct platform_device bfin_pcm = { - .name = "bfin-pcm-audio", +#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE) +static struct platform_device bfin_i2s_pcm = { + .name = "bfin-i2s-pcm-audio", + .id = -1, +}; +#endif + +#if defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE) +static struct platform_device bfin_tdm_pcm = { + .name = "bfin-tdm-pcm-audio", + .id = -1, +}; +#endif + +#if defined(CONFIG_SND_BF5XX_AC97) || defined(CONFIG_SND_BF5XX_AC97_MODULE) +static struct platform_device bfin_ac97_pcm = { + .name = "bfin-ac97-pcm-audio", .id = -1, }; #endif @@ -1601,10 +1632,14 @@ static struct platform_device *ezkit_devices[] __initdata = { &ezkit_flash_device, #endif -#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE) || \ - defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE) || \ - defined(CONFIG_SND_BF5XX_AC97) || defined(CONFIG_SND_BF5XX_AC97_MODULE) - &bfin_pcm, +#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE) + &bfin_i2s_pcm, +#endif +#if defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE) + &bfin_tdm_pcm, +#endif +#if defined(CONFIG_SND_BF5XX_AC97) || defined(CONFIG_SND_BF5XX_AC97_MODULE) + &bfin_ac97_pcm, #endif #if defined(CONFIG_SND_BF5XX_SOC_AD1980) || defined(CONFIG_SND_BF5XX_SOC_AD1980_MODULE) -- cgit v0.10.2 From 5ddebe576c08b67003b4e2c689891afcc466e3d4 Mon Sep 17 00:00:00 2001 From: Bob Liu Date: Mon, 19 Mar 2012 13:50:27 +0800 Subject: blackfin:dma: rename bfin_dma_5xx.c to bfin_dma.c bfin_dma_5xx is not a generic name for all blackfin chips. Signed-off-by: Sonic Zhang Signed-off-by: Bob Liu diff --git a/arch/blackfin/kernel/Makefile b/arch/blackfin/kernel/Makefile index 1f88edd..9a0d6d7 100644 --- a/arch/blackfin/kernel/Makefile +++ b/arch/blackfin/kernel/Makefile @@ -7,7 +7,7 @@ extra-y := init_task.o vmlinux.lds obj-y := \ entry.o process.o bfin_ksyms.o ptrace.o setup.o signal.o \ sys_bfin.o traps.o irqchip.o dma-mapping.o flat.o \ - fixed_code.o reboot.o bfin_gpio.o bfin_dma_5xx.o \ + fixed_code.o reboot.o bfin_gpio.o bfin_dma.o \ exception.o dumpstack.o ifeq ($(CONFIG_GENERIC_CLOCKEVENTS),y) diff --git a/arch/blackfin/kernel/bfin_dma.c b/arch/blackfin/kernel/bfin_dma.c new file mode 100644 index 0000000..40c2ed6 --- /dev/null +++ b/arch/blackfin/kernel/bfin_dma.c @@ -0,0 +1,542 @@ +/* + * bfin_dma.c - Blackfin DMA implementation + * + * Copyright 2004-2008 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +/* + * To make sure we work around 05000119 - we always check DMA_DONE bit, + * never the DMA_RUN bit + */ + +struct dma_channel dma_ch[MAX_DMA_CHANNELS]; +EXPORT_SYMBOL(dma_ch); + +static int __init blackfin_dma_init(void) +{ + int i; + + printk(KERN_INFO "Blackfin DMA Controller\n"); + + +#if ANOMALY_05000480 + bfin_write_DMAC_TC_PER(0x0111); +#endif + + for (i = 0; i < MAX_DMA_CHANNELS; i++) { + atomic_set(&dma_ch[i].chan_status, 0); + dma_ch[i].regs = dma_io_base_addr[i]; + } + /* Mark MEMDMA Channel 0 as requested since we're using it internally */ + request_dma(CH_MEM_STREAM0_DEST, "Blackfin dma_memcpy"); + request_dma(CH_MEM_STREAM0_SRC, "Blackfin dma_memcpy"); + +#if defined(CONFIG_DEB_DMA_URGENT) + bfin_write_EBIU_DDRQUE(bfin_read_EBIU_DDRQUE() + | DEB1_URGENT | DEB2_URGENT | DEB3_URGENT); +#endif + + return 0; +} +arch_initcall(blackfin_dma_init); + +#ifdef CONFIG_PROC_FS +static int proc_dma_show(struct seq_file *m, void *v) +{ + int i; + + for (i = 0; i < MAX_DMA_CHANNELS; ++i) + if (dma_channel_active(i)) + seq_printf(m, "%2d: %s\n", i, dma_ch[i].device_id); + + return 0; +} + +static int proc_dma_open(struct inode *inode, struct file *file) +{ + return single_open(file, proc_dma_show, NULL); +} + +static const struct file_operations proc_dma_operations = { + .open = proc_dma_open, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, +}; + +static int __init proc_dma_init(void) +{ + return proc_create("dma", 0, NULL, &proc_dma_operations) != NULL; +} +late_initcall(proc_dma_init); +#endif + +static void set_dma_peripheral_map(unsigned int channel, const char *device_id) +{ +#ifdef CONFIG_BF54x + unsigned int per_map; + + switch (channel) { + case CH_UART2_RX: per_map = 0xC << 12; break; + case CH_UART2_TX: per_map = 0xD << 12; break; + case CH_UART3_RX: per_map = 0xE << 12; break; + case CH_UART3_TX: per_map = 0xF << 12; break; + default: return; + } + + if (strncmp(device_id, "BFIN_UART", 9) == 0) + dma_ch[channel].regs->peripheral_map = per_map; +#endif +} + +/** + * request_dma - request a DMA channel + * + * Request the specific DMA channel from the system if it's available. + */ +int request_dma(unsigned int channel, const char *device_id) +{ + pr_debug("request_dma() : BEGIN\n"); + + if (device_id == NULL) + printk(KERN_WARNING "request_dma(%u): no device_id given\n", channel); + +#if defined(CONFIG_BF561) && ANOMALY_05000182 + if (channel >= CH_IMEM_STREAM0_DEST && channel <= CH_IMEM_STREAM1_DEST) { + if (get_cclk() > 500000000) { + printk(KERN_WARNING + "Request IMDMA failed due to ANOMALY 05000182\n"); + return -EFAULT; + } + } +#endif + + if (atomic_cmpxchg(&dma_ch[channel].chan_status, 0, 1)) { + pr_debug("DMA CHANNEL IN USE\n"); + return -EBUSY; + } + + set_dma_peripheral_map(channel, device_id); + dma_ch[channel].device_id = device_id; + dma_ch[channel].irq = 0; + + /* This is to be enabled by putting a restriction - + * you have to request DMA, before doing any operations on + * descriptor/channel + */ + pr_debug("request_dma() : END\n"); + return 0; +} +EXPORT_SYMBOL(request_dma); + +int set_dma_callback(unsigned int channel, irq_handler_t callback, void *data) +{ + int ret; + unsigned int irq; + + BUG_ON(channel >= MAX_DMA_CHANNELS || !callback || + !atomic_read(&dma_ch[channel].chan_status)); + + irq = channel2irq(channel); + ret = request_irq(irq, callback, 0, dma_ch[channel].device_id, data); + if (ret) + return ret; + + dma_ch[channel].irq = irq; + dma_ch[channel].data = data; + + return 0; +} +EXPORT_SYMBOL(set_dma_callback); + +/** + * clear_dma_buffer - clear DMA fifos for specified channel + * + * Set the Buffer Clear bit in the Configuration register of specific DMA + * channel. This will stop the descriptor based DMA operation. + */ +static void clear_dma_buffer(unsigned int channel) +{ + dma_ch[channel].regs->cfg |= RESTART; + SSYNC(); + dma_ch[channel].regs->cfg &= ~RESTART; +} + +void free_dma(unsigned int channel) +{ + pr_debug("freedma() : BEGIN\n"); + BUG_ON(channel >= MAX_DMA_CHANNELS || + !atomic_read(&dma_ch[channel].chan_status)); + + /* Halt the DMA */ + disable_dma(channel); + clear_dma_buffer(channel); + + if (dma_ch[channel].irq) + free_irq(dma_ch[channel].irq, dma_ch[channel].data); + + /* Clear the DMA Variable in the Channel */ + atomic_set(&dma_ch[channel].chan_status, 0); + + pr_debug("freedma() : END\n"); +} +EXPORT_SYMBOL(free_dma); + +#ifdef CONFIG_PM +# ifndef MAX_DMA_SUSPEND_CHANNELS +# define MAX_DMA_SUSPEND_CHANNELS MAX_DMA_CHANNELS +# endif +int blackfin_dma_suspend(void) +{ + int i; + + for (i = 0; i < MAX_DMA_CHANNELS; ++i) { + if (dma_ch[i].regs->cfg & DMAEN) { + printk(KERN_ERR "DMA Channel %d failed to suspend\n", i); + return -EBUSY; + } + + if (i < MAX_DMA_SUSPEND_CHANNELS) + dma_ch[i].saved_peripheral_map = dma_ch[i].regs->peripheral_map; + } + +#if ANOMALY_05000480 + bfin_write_DMAC_TC_PER(0x0); +#endif + return 0; +} + +void blackfin_dma_resume(void) +{ + int i; + + for (i = 0; i < MAX_DMA_CHANNELS; ++i) { + dma_ch[i].regs->cfg = 0; + + if (i < MAX_DMA_SUSPEND_CHANNELS) + dma_ch[i].regs->peripheral_map = dma_ch[i].saved_peripheral_map; + } +#if ANOMALY_05000480 + bfin_write_DMAC_TC_PER(0x0111); +#endif +} +#endif + +/** + * blackfin_dma_early_init - minimal DMA init + * + * Setup a few DMA registers so we can safely do DMA transfers early on in + * the kernel booting process. Really this just means using dma_memcpy(). + */ +void __init blackfin_dma_early_init(void) +{ + early_shadow_stamp(); + bfin_write_MDMA_S0_CONFIG(0); + bfin_write_MDMA_S1_CONFIG(0); +} + +void __init early_dma_memcpy(void *pdst, const void *psrc, size_t size) +{ + unsigned long dst = (unsigned long)pdst; + unsigned long src = (unsigned long)psrc; + struct dma_register *dst_ch, *src_ch; + + early_shadow_stamp(); + + /* We assume that everything is 4 byte aligned, so include + * a basic sanity check + */ + BUG_ON(dst % 4); + BUG_ON(src % 4); + BUG_ON(size % 4); + + src_ch = 0; + /* Find an avalible memDMA channel */ + while (1) { + if (src_ch == (struct dma_register *)MDMA_S0_NEXT_DESC_PTR) { + dst_ch = (struct dma_register *)MDMA_D1_NEXT_DESC_PTR; + src_ch = (struct dma_register *)MDMA_S1_NEXT_DESC_PTR; + } else { + dst_ch = (struct dma_register *)MDMA_D0_NEXT_DESC_PTR; + src_ch = (struct dma_register *)MDMA_S0_NEXT_DESC_PTR; + } + + if (!bfin_read16(&src_ch->cfg)) + break; + else if (bfin_read16(&dst_ch->irq_status) & DMA_DONE) { + bfin_write16(&src_ch->cfg, 0); + break; + } + } + + /* Force a sync in case a previous config reset on this channel + * occurred. This is needed so subsequent writes to DMA registers + * are not spuriously lost/corrupted. + */ + __builtin_bfin_ssync(); + + /* Destination */ + bfin_write32(&dst_ch->start_addr, dst); + bfin_write16(&dst_ch->x_count, size >> 2); + bfin_write16(&dst_ch->x_modify, 1 << 2); + bfin_write16(&dst_ch->irq_status, DMA_DONE | DMA_ERR); + + /* Source */ + bfin_write32(&src_ch->start_addr, src); + bfin_write16(&src_ch->x_count, size >> 2); + bfin_write16(&src_ch->x_modify, 1 << 2); + bfin_write16(&src_ch->irq_status, DMA_DONE | DMA_ERR); + + /* Enable */ + bfin_write16(&src_ch->cfg, DMAEN | WDSIZE_32); + bfin_write16(&dst_ch->cfg, WNR | DI_EN | DMAEN | WDSIZE_32); + + /* Since we are atomic now, don't use the workaround ssync */ + __builtin_bfin_ssync(); +} + +void __init early_dma_memcpy_done(void) +{ + early_shadow_stamp(); + + while ((bfin_read_MDMA_S0_CONFIG() && !(bfin_read_MDMA_D0_IRQ_STATUS() & DMA_DONE)) || + (bfin_read_MDMA_S1_CONFIG() && !(bfin_read_MDMA_D1_IRQ_STATUS() & DMA_DONE))) + continue; + + bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR); + bfin_write_MDMA_D1_IRQ_STATUS(DMA_DONE | DMA_ERR); + /* + * Now that DMA is done, we would normally flush cache, but + * i/d cache isn't running this early, so we don't bother, + * and just clear out the DMA channel for next time + */ + bfin_write_MDMA_S0_CONFIG(0); + bfin_write_MDMA_S1_CONFIG(0); + bfin_write_MDMA_D0_CONFIG(0); + bfin_write_MDMA_D1_CONFIG(0); + + __builtin_bfin_ssync(); +} + +/** + * __dma_memcpy - program the MDMA registers + * + * Actually program MDMA0 and wait for the transfer to finish. Disable IRQs + * while programming registers so that everything is fully configured. Wait + * for DMA to finish with IRQs enabled. If interrupted, the initial DMA_DONE + * check will make sure we don't clobber any existing transfer. + */ +static void __dma_memcpy(u32 daddr, s16 dmod, u32 saddr, s16 smod, size_t cnt, u32 conf) +{ + static DEFINE_SPINLOCK(mdma_lock); + unsigned long flags; + + spin_lock_irqsave(&mdma_lock, flags); + + /* Force a sync in case a previous config reset on this channel + * occurred. This is needed so subsequent writes to DMA registers + * are not spuriously lost/corrupted. Do it under irq lock and + * without the anomaly version (because we are atomic already). + */ + __builtin_bfin_ssync(); + + if (bfin_read_MDMA_S0_CONFIG()) + while (!(bfin_read_MDMA_D0_IRQ_STATUS() & DMA_DONE)) + continue; + + if (conf & DMA2D) { + /* For larger bit sizes, we've already divided down cnt so it + * is no longer a multiple of 64k. So we have to break down + * the limit here so it is a multiple of the incoming size. + * There is no limitation here in terms of total size other + * than the hardware though as the bits lost in the shift are + * made up by MODIFY (== we can hit the whole address space). + * X: (2^(16 - 0)) * 1 == (2^(16 - 1)) * 2 == (2^(16 - 2)) * 4 + */ + u32 shift = abs(dmod) >> 1; + size_t ycnt = cnt >> (16 - shift); + cnt = 1 << (16 - shift); + bfin_write_MDMA_D0_Y_COUNT(ycnt); + bfin_write_MDMA_S0_Y_COUNT(ycnt); + bfin_write_MDMA_D0_Y_MODIFY(dmod); + bfin_write_MDMA_S0_Y_MODIFY(smod); + } + + bfin_write_MDMA_D0_START_ADDR(daddr); + bfin_write_MDMA_D0_X_COUNT(cnt); + bfin_write_MDMA_D0_X_MODIFY(dmod); + bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR); + + bfin_write_MDMA_S0_START_ADDR(saddr); + bfin_write_MDMA_S0_X_COUNT(cnt); + bfin_write_MDMA_S0_X_MODIFY(smod); + bfin_write_MDMA_S0_IRQ_STATUS(DMA_DONE | DMA_ERR); + + bfin_write_MDMA_S0_CONFIG(DMAEN | conf); + bfin_write_MDMA_D0_CONFIG(WNR | DI_EN | DMAEN | conf); + + spin_unlock_irqrestore(&mdma_lock, flags); + + SSYNC(); + + while (!(bfin_read_MDMA_D0_IRQ_STATUS() & DMA_DONE)) + if (bfin_read_MDMA_S0_CONFIG()) + continue; + else + return; + + bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR); + + bfin_write_MDMA_S0_CONFIG(0); + bfin_write_MDMA_D0_CONFIG(0); +} + +/** + * _dma_memcpy - translate C memcpy settings into MDMA settings + * + * Handle all the high level steps before we touch the MDMA registers. So + * handle direction, tweaking of sizes, and formatting of addresses. + */ +static void *_dma_memcpy(void *pdst, const void *psrc, size_t size) +{ + u32 conf, shift; + s16 mod; + unsigned long dst = (unsigned long)pdst; + unsigned long src = (unsigned long)psrc; + + if (size == 0) + return NULL; + + if (dst % 4 == 0 && src % 4 == 0 && size % 4 == 0) { + conf = WDSIZE_32; + shift = 2; + } else if (dst % 2 == 0 && src % 2 == 0 && size % 2 == 0) { + conf = WDSIZE_16; + shift = 1; + } else { + conf = WDSIZE_8; + shift = 0; + } + + /* If the two memory regions have a chance of overlapping, make + * sure the memcpy still works as expected. Do this by having the + * copy run backwards instead. + */ + mod = 1 << shift; + if (src < dst) { + mod *= -1; + dst += size + mod; + src += size + mod; + } + size >>= shift; + + if (size > 0x10000) + conf |= DMA2D; + + __dma_memcpy(dst, mod, src, mod, size, conf); + + return pdst; +} + +/** + * dma_memcpy - DMA memcpy under mutex lock + * + * Do not check arguments before starting the DMA memcpy. Break the transfer + * up into two pieces. The first transfer is in multiples of 64k and the + * second transfer is the piece smaller than 64k. + */ +void *dma_memcpy(void *pdst, const void *psrc, size_t size) +{ + unsigned long dst = (unsigned long)pdst; + unsigned long src = (unsigned long)psrc; + + if (bfin_addr_dcacheable(src)) + blackfin_dcache_flush_range(src, src + size); + + if (bfin_addr_dcacheable(dst)) + blackfin_dcache_invalidate_range(dst, dst + size); + + return dma_memcpy_nocache(pdst, psrc, size); +} +EXPORT_SYMBOL(dma_memcpy); + +/** + * dma_memcpy_nocache - DMA memcpy under mutex lock + * - No cache flush/invalidate + * + * Do not check arguments before starting the DMA memcpy. Break the transfer + * up into two pieces. The first transfer is in multiples of 64k and the + * second transfer is the piece smaller than 64k. + */ +void *dma_memcpy_nocache(void *pdst, const void *psrc, size_t size) +{ + size_t bulk, rest; + + bulk = size & ~0xffff; + rest = size - bulk; + if (bulk) + _dma_memcpy(pdst, psrc, bulk); + _dma_memcpy(pdst + bulk, psrc + bulk, rest); + return pdst; +} +EXPORT_SYMBOL(dma_memcpy_nocache); + +/** + * safe_dma_memcpy - DMA memcpy w/argument checking + * + * Verify arguments are safe before heading to dma_memcpy(). + */ +void *safe_dma_memcpy(void *dst, const void *src, size_t size) +{ + if (!access_ok(VERIFY_WRITE, dst, size)) + return NULL; + if (!access_ok(VERIFY_READ, src, size)) + return NULL; + return dma_memcpy(dst, src, size); +} +EXPORT_SYMBOL(safe_dma_memcpy); + +static void _dma_out(unsigned long addr, unsigned long buf, unsigned short len, + u16 size, u16 dma_size) +{ + blackfin_dcache_flush_range(buf, buf + len * size); + __dma_memcpy(addr, 0, buf, size, len, dma_size); +} + +static void _dma_in(unsigned long addr, unsigned long buf, unsigned short len, + u16 size, u16 dma_size) +{ + blackfin_dcache_invalidate_range(buf, buf + len * size); + __dma_memcpy(buf, size, addr, 0, len, dma_size); +} + +#define MAKE_DMA_IO(io, bwl, isize, dmasize, cnst) \ +void dma_##io##s##bwl(unsigned long addr, cnst void *buf, unsigned short len) \ +{ \ + _dma_##io(addr, (unsigned long)buf, len, isize, WDSIZE_##dmasize); \ +} \ +EXPORT_SYMBOL(dma_##io##s##bwl) +MAKE_DMA_IO(out, b, 1, 8, const); +MAKE_DMA_IO(in, b, 1, 8, ); +MAKE_DMA_IO(out, w, 2, 16, const); +MAKE_DMA_IO(in, w, 2, 16, ); +MAKE_DMA_IO(out, l, 4, 32, const); +MAKE_DMA_IO(in, l, 4, 32, ); diff --git a/arch/blackfin/kernel/bfin_dma_5xx.c b/arch/blackfin/kernel/bfin_dma_5xx.c deleted file mode 100644 index 71dbaa4..0000000 --- a/arch/blackfin/kernel/bfin_dma_5xx.c +++ /dev/null @@ -1,536 +0,0 @@ -/* - * bfin_dma_5xx.c - Blackfin DMA implementation - * - * Copyright 2004-2008 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -/* - * To make sure we work around 05000119 - we always check DMA_DONE bit, - * never the DMA_RUN bit - */ - -struct dma_channel dma_ch[MAX_DMA_CHANNELS]; -EXPORT_SYMBOL(dma_ch); - -static int __init blackfin_dma_init(void) -{ - int i; - - printk(KERN_INFO "Blackfin DMA Controller\n"); - - -#if ANOMALY_05000480 - bfin_write_DMAC_TC_PER(0x0111); -#endif - - for (i = 0; i < MAX_DMA_CHANNELS; i++) { - atomic_set(&dma_ch[i].chan_status, 0); - dma_ch[i].regs = dma_io_base_addr[i]; - } - /* Mark MEMDMA Channel 0 as requested since we're using it internally */ - request_dma(CH_MEM_STREAM0_DEST, "Blackfin dma_memcpy"); - request_dma(CH_MEM_STREAM0_SRC, "Blackfin dma_memcpy"); - -#if defined(CONFIG_DEB_DMA_URGENT) - bfin_write_EBIU_DDRQUE(bfin_read_EBIU_DDRQUE() - | DEB1_URGENT | DEB2_URGENT | DEB3_URGENT); -#endif - - return 0; -} -arch_initcall(blackfin_dma_init); - -#ifdef CONFIG_PROC_FS -static int proc_dma_show(struct seq_file *m, void *v) -{ - int i; - - for (i = 0; i < MAX_DMA_CHANNELS; ++i) - if (dma_channel_active(i)) - seq_printf(m, "%2d: %s\n", i, dma_ch[i].device_id); - - return 0; -} - -static int proc_dma_open(struct inode *inode, struct file *file) -{ - return single_open(file, proc_dma_show, NULL); -} - -static const struct file_operations proc_dma_operations = { - .open = proc_dma_open, - .read = seq_read, - .llseek = seq_lseek, - .release = single_release, -}; - -static int __init proc_dma_init(void) -{ - return proc_create("dma", 0, NULL, &proc_dma_operations) != NULL; -} -late_initcall(proc_dma_init); -#endif - -static void set_dma_peripheral_map(unsigned int channel, const char *device_id) -{ -#ifdef CONFIG_BF54x - unsigned int per_map; - - switch (channel) { - case CH_UART2_RX: per_map = 0xC << 12; break; - case CH_UART2_TX: per_map = 0xD << 12; break; - case CH_UART3_RX: per_map = 0xE << 12; break; - case CH_UART3_TX: per_map = 0xF << 12; break; - default: return; - } - - if (strncmp(device_id, "BFIN_UART", 9) == 0) - dma_ch[channel].regs->peripheral_map = per_map; -#endif -} - -/** - * request_dma - request a DMA channel - * - * Request the specific DMA channel from the system if it's available. - */ -int request_dma(unsigned int channel, const char *device_id) -{ - pr_debug("request_dma() : BEGIN\n"); - - if (device_id == NULL) - printk(KERN_WARNING "request_dma(%u): no device_id given\n", channel); - -#if defined(CONFIG_BF561) && ANOMALY_05000182 - if (channel >= CH_IMEM_STREAM0_DEST && channel <= CH_IMEM_STREAM1_DEST) { - if (get_cclk() > 500000000) { - printk(KERN_WARNING - "Request IMDMA failed due to ANOMALY 05000182\n"); - return -EFAULT; - } - } -#endif - - if (atomic_cmpxchg(&dma_ch[channel].chan_status, 0, 1)) { - pr_debug("DMA CHANNEL IN USE\n"); - return -EBUSY; - } - - set_dma_peripheral_map(channel, device_id); - dma_ch[channel].device_id = device_id; - dma_ch[channel].irq = 0; - - /* This is to be enabled by putting a restriction - - * you have to request DMA, before doing any operations on - * descriptor/channel - */ - pr_debug("request_dma() : END\n"); - return 0; -} -EXPORT_SYMBOL(request_dma); - -int set_dma_callback(unsigned int channel, irq_handler_t callback, void *data) -{ - int ret; - unsigned int irq; - - BUG_ON(channel >= MAX_DMA_CHANNELS || !callback || - !atomic_read(&dma_ch[channel].chan_status)); - - irq = channel2irq(channel); - ret = request_irq(irq, callback, 0, dma_ch[channel].device_id, data); - if (ret) - return ret; - - dma_ch[channel].irq = irq; - dma_ch[channel].data = data; - - return 0; -} -EXPORT_SYMBOL(set_dma_callback); - -/** - * clear_dma_buffer - clear DMA fifos for specified channel - * - * Set the Buffer Clear bit in the Configuration register of specific DMA - * channel. This will stop the descriptor based DMA operation. - */ -static void clear_dma_buffer(unsigned int channel) -{ - dma_ch[channel].regs->cfg |= RESTART; - SSYNC(); - dma_ch[channel].regs->cfg &= ~RESTART; -} - -void free_dma(unsigned int channel) -{ - pr_debug("freedma() : BEGIN\n"); - BUG_ON(channel >= MAX_DMA_CHANNELS || - !atomic_read(&dma_ch[channel].chan_status)); - - /* Halt the DMA */ - disable_dma(channel); - clear_dma_buffer(channel); - - if (dma_ch[channel].irq) - free_irq(dma_ch[channel].irq, dma_ch[channel].data); - - /* Clear the DMA Variable in the Channel */ - atomic_set(&dma_ch[channel].chan_status, 0); - - pr_debug("freedma() : END\n"); -} -EXPORT_SYMBOL(free_dma); - -#ifdef CONFIG_PM -# ifndef MAX_DMA_SUSPEND_CHANNELS -# define MAX_DMA_SUSPEND_CHANNELS MAX_DMA_CHANNELS -# endif -int blackfin_dma_suspend(void) -{ - int i; - - for (i = 0; i < MAX_DMA_CHANNELS; ++i) { - if (dma_ch[i].regs->cfg & DMAEN) { - printk(KERN_ERR "DMA Channel %d failed to suspend\n", i); - return -EBUSY; - } - - if (i < MAX_DMA_SUSPEND_CHANNELS) - dma_ch[i].saved_peripheral_map = dma_ch[i].regs->peripheral_map; - } - - return 0; -} - -void blackfin_dma_resume(void) -{ - int i; - - for (i = 0; i < MAX_DMA_CHANNELS; ++i) { - dma_ch[i].regs->cfg = 0; - - if (i < MAX_DMA_SUSPEND_CHANNELS) - dma_ch[i].regs->peripheral_map = dma_ch[i].saved_peripheral_map; - } -} -#endif - -/** - * blackfin_dma_early_init - minimal DMA init - * - * Setup a few DMA registers so we can safely do DMA transfers early on in - * the kernel booting process. Really this just means using dma_memcpy(). - */ -void __init blackfin_dma_early_init(void) -{ - early_shadow_stamp(); - bfin_write_MDMA_S0_CONFIG(0); - bfin_write_MDMA_S1_CONFIG(0); -} - -void __init early_dma_memcpy(void *pdst, const void *psrc, size_t size) -{ - unsigned long dst = (unsigned long)pdst; - unsigned long src = (unsigned long)psrc; - struct dma_register *dst_ch, *src_ch; - - early_shadow_stamp(); - - /* We assume that everything is 4 byte aligned, so include - * a basic sanity check - */ - BUG_ON(dst % 4); - BUG_ON(src % 4); - BUG_ON(size % 4); - - src_ch = 0; - /* Find an avalible memDMA channel */ - while (1) { - if (src_ch == (struct dma_register *)MDMA_S0_NEXT_DESC_PTR) { - dst_ch = (struct dma_register *)MDMA_D1_NEXT_DESC_PTR; - src_ch = (struct dma_register *)MDMA_S1_NEXT_DESC_PTR; - } else { - dst_ch = (struct dma_register *)MDMA_D0_NEXT_DESC_PTR; - src_ch = (struct dma_register *)MDMA_S0_NEXT_DESC_PTR; - } - - if (!bfin_read16(&src_ch->cfg)) - break; - else if (bfin_read16(&dst_ch->irq_status) & DMA_DONE) { - bfin_write16(&src_ch->cfg, 0); - break; - } - } - - /* Force a sync in case a previous config reset on this channel - * occurred. This is needed so subsequent writes to DMA registers - * are not spuriously lost/corrupted. - */ - __builtin_bfin_ssync(); - - /* Destination */ - bfin_write32(&dst_ch->start_addr, dst); - bfin_write16(&dst_ch->x_count, size >> 2); - bfin_write16(&dst_ch->x_modify, 1 << 2); - bfin_write16(&dst_ch->irq_status, DMA_DONE | DMA_ERR); - - /* Source */ - bfin_write32(&src_ch->start_addr, src); - bfin_write16(&src_ch->x_count, size >> 2); - bfin_write16(&src_ch->x_modify, 1 << 2); - bfin_write16(&src_ch->irq_status, DMA_DONE | DMA_ERR); - - /* Enable */ - bfin_write16(&src_ch->cfg, DMAEN | WDSIZE_32); - bfin_write16(&dst_ch->cfg, WNR | DI_EN | DMAEN | WDSIZE_32); - - /* Since we are atomic now, don't use the workaround ssync */ - __builtin_bfin_ssync(); -} - -void __init early_dma_memcpy_done(void) -{ - early_shadow_stamp(); - - while ((bfin_read_MDMA_S0_CONFIG() && !(bfin_read_MDMA_D0_IRQ_STATUS() & DMA_DONE)) || - (bfin_read_MDMA_S1_CONFIG() && !(bfin_read_MDMA_D1_IRQ_STATUS() & DMA_DONE))) - continue; - - bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR); - bfin_write_MDMA_D1_IRQ_STATUS(DMA_DONE | DMA_ERR); - /* - * Now that DMA is done, we would normally flush cache, but - * i/d cache isn't running this early, so we don't bother, - * and just clear out the DMA channel for next time - */ - bfin_write_MDMA_S0_CONFIG(0); - bfin_write_MDMA_S1_CONFIG(0); - bfin_write_MDMA_D0_CONFIG(0); - bfin_write_MDMA_D1_CONFIG(0); - - __builtin_bfin_ssync(); -} - -/** - * __dma_memcpy - program the MDMA registers - * - * Actually program MDMA0 and wait for the transfer to finish. Disable IRQs - * while programming registers so that everything is fully configured. Wait - * for DMA to finish with IRQs enabled. If interrupted, the initial DMA_DONE - * check will make sure we don't clobber any existing transfer. - */ -static void __dma_memcpy(u32 daddr, s16 dmod, u32 saddr, s16 smod, size_t cnt, u32 conf) -{ - static DEFINE_SPINLOCK(mdma_lock); - unsigned long flags; - - spin_lock_irqsave(&mdma_lock, flags); - - /* Force a sync in case a previous config reset on this channel - * occurred. This is needed so subsequent writes to DMA registers - * are not spuriously lost/corrupted. Do it under irq lock and - * without the anomaly version (because we are atomic already). - */ - __builtin_bfin_ssync(); - - if (bfin_read_MDMA_S0_CONFIG()) - while (!(bfin_read_MDMA_D0_IRQ_STATUS() & DMA_DONE)) - continue; - - if (conf & DMA2D) { - /* For larger bit sizes, we've already divided down cnt so it - * is no longer a multiple of 64k. So we have to break down - * the limit here so it is a multiple of the incoming size. - * There is no limitation here in terms of total size other - * than the hardware though as the bits lost in the shift are - * made up by MODIFY (== we can hit the whole address space). - * X: (2^(16 - 0)) * 1 == (2^(16 - 1)) * 2 == (2^(16 - 2)) * 4 - */ - u32 shift = abs(dmod) >> 1; - size_t ycnt = cnt >> (16 - shift); - cnt = 1 << (16 - shift); - bfin_write_MDMA_D0_Y_COUNT(ycnt); - bfin_write_MDMA_S0_Y_COUNT(ycnt); - bfin_write_MDMA_D0_Y_MODIFY(dmod); - bfin_write_MDMA_S0_Y_MODIFY(smod); - } - - bfin_write_MDMA_D0_START_ADDR(daddr); - bfin_write_MDMA_D0_X_COUNT(cnt); - bfin_write_MDMA_D0_X_MODIFY(dmod); - bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR); - - bfin_write_MDMA_S0_START_ADDR(saddr); - bfin_write_MDMA_S0_X_COUNT(cnt); - bfin_write_MDMA_S0_X_MODIFY(smod); - bfin_write_MDMA_S0_IRQ_STATUS(DMA_DONE | DMA_ERR); - - bfin_write_MDMA_S0_CONFIG(DMAEN | conf); - bfin_write_MDMA_D0_CONFIG(WNR | DI_EN | DMAEN | conf); - - spin_unlock_irqrestore(&mdma_lock, flags); - - SSYNC(); - - while (!(bfin_read_MDMA_D0_IRQ_STATUS() & DMA_DONE)) - if (bfin_read_MDMA_S0_CONFIG()) - continue; - else - return; - - bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR); - - bfin_write_MDMA_S0_CONFIG(0); - bfin_write_MDMA_D0_CONFIG(0); -} - -/** - * _dma_memcpy - translate C memcpy settings into MDMA settings - * - * Handle all the high level steps before we touch the MDMA registers. So - * handle direction, tweaking of sizes, and formatting of addresses. - */ -static void *_dma_memcpy(void *pdst, const void *psrc, size_t size) -{ - u32 conf, shift; - s16 mod; - unsigned long dst = (unsigned long)pdst; - unsigned long src = (unsigned long)psrc; - - if (size == 0) - return NULL; - - if (dst % 4 == 0 && src % 4 == 0 && size % 4 == 0) { - conf = WDSIZE_32; - shift = 2; - } else if (dst % 2 == 0 && src % 2 == 0 && size % 2 == 0) { - conf = WDSIZE_16; - shift = 1; - } else { - conf = WDSIZE_8; - shift = 0; - } - - /* If the two memory regions have a chance of overlapping, make - * sure the memcpy still works as expected. Do this by having the - * copy run backwards instead. - */ - mod = 1 << shift; - if (src < dst) { - mod *= -1; - dst += size + mod; - src += size + mod; - } - size >>= shift; - - if (size > 0x10000) - conf |= DMA2D; - - __dma_memcpy(dst, mod, src, mod, size, conf); - - return pdst; -} - -/** - * dma_memcpy - DMA memcpy under mutex lock - * - * Do not check arguments before starting the DMA memcpy. Break the transfer - * up into two pieces. The first transfer is in multiples of 64k and the - * second transfer is the piece smaller than 64k. - */ -void *dma_memcpy(void *pdst, const void *psrc, size_t size) -{ - unsigned long dst = (unsigned long)pdst; - unsigned long src = (unsigned long)psrc; - - if (bfin_addr_dcacheable(src)) - blackfin_dcache_flush_range(src, src + size); - - if (bfin_addr_dcacheable(dst)) - blackfin_dcache_invalidate_range(dst, dst + size); - - return dma_memcpy_nocache(pdst, psrc, size); -} -EXPORT_SYMBOL(dma_memcpy); - -/** - * dma_memcpy_nocache - DMA memcpy under mutex lock - * - No cache flush/invalidate - * - * Do not check arguments before starting the DMA memcpy. Break the transfer - * up into two pieces. The first transfer is in multiples of 64k and the - * second transfer is the piece smaller than 64k. - */ -void *dma_memcpy_nocache(void *pdst, const void *psrc, size_t size) -{ - size_t bulk, rest; - - bulk = size & ~0xffff; - rest = size - bulk; - if (bulk) - _dma_memcpy(pdst, psrc, bulk); - _dma_memcpy(pdst + bulk, psrc + bulk, rest); - return pdst; -} -EXPORT_SYMBOL(dma_memcpy_nocache); - -/** - * safe_dma_memcpy - DMA memcpy w/argument checking - * - * Verify arguments are safe before heading to dma_memcpy(). - */ -void *safe_dma_memcpy(void *dst, const void *src, size_t size) -{ - if (!access_ok(VERIFY_WRITE, dst, size)) - return NULL; - if (!access_ok(VERIFY_READ, src, size)) - return NULL; - return dma_memcpy(dst, src, size); -} -EXPORT_SYMBOL(safe_dma_memcpy); - -static void _dma_out(unsigned long addr, unsigned long buf, unsigned short len, - u16 size, u16 dma_size) -{ - blackfin_dcache_flush_range(buf, buf + len * size); - __dma_memcpy(addr, 0, buf, size, len, dma_size); -} - -static void _dma_in(unsigned long addr, unsigned long buf, unsigned short len, - u16 size, u16 dma_size) -{ - blackfin_dcache_invalidate_range(buf, buf + len * size); - __dma_memcpy(buf, size, addr, 0, len, dma_size); -} - -#define MAKE_DMA_IO(io, bwl, isize, dmasize, cnst) \ -void dma_##io##s##bwl(unsigned long addr, cnst void *buf, unsigned short len) \ -{ \ - _dma_##io(addr, (unsigned long)buf, len, isize, WDSIZE_##dmasize); \ -} \ -EXPORT_SYMBOL(dma_##io##s##bwl) -MAKE_DMA_IO(out, b, 1, 8, const); -MAKE_DMA_IO(in, b, 1, 8, ); -MAKE_DMA_IO(out, w, 2, 16, const); -MAKE_DMA_IO(in, w, 2, 16, ); -MAKE_DMA_IO(out, l, 4, 32, const); -MAKE_DMA_IO(in, l, 4, 32, ); -- cgit v0.10.2 From 1762275e7a08e808387999f582430172a02758a5 Mon Sep 17 00:00:00 2001 From: Sonic Zhang Date: Wed, 3 Aug 2011 15:16:15 +0800 Subject: blackfin: clean up string bfin_dma_5xx after rename. Signed-off-by: Sonic Zhang Signed-off-by: Bob Liu diff --git a/arch/blackfin/lib/ins.S b/arch/blackfin/lib/ins.S index 79cacce..d59608d 100644 --- a/arch/blackfin/lib/ins.S +++ b/arch/blackfin/lib/ins.S @@ -66,7 +66,7 @@ * - turns interrupts off every loop (low overhead, but longer latency) * - DMA version, which do not suffer from this issue. DMA versions have * different name (prefixed by dma_ ), and are located in - * ../kernel/bfin_dma_5xx.c + * ../kernel/bfin_dma.c * Using the dma related functions are recommended for transferring large * buffers in/out of FIFOs. */ -- cgit v0.10.2