From 12174aac376f2c9390c51e66995d38c9e5e94eff Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Wed, 19 Jan 2011 12:15:29 +0100 Subject: h8300: Convert to new irq_chip functions No functional change, just straight forward conversion. Signed-off-by: Thomas Gleixner Cc: Yoshinori Sato Cc: Paul Mundt diff --git a/arch/h8300/kernel/irq.c b/arch/h8300/kernel/irq.c index c25dc2c..e23f346 100644 --- a/arch/h8300/kernel/irq.c +++ b/arch/h8300/kernel/irq.c @@ -38,34 +38,34 @@ static inline int is_ext_irq(unsigned int irq) return (irq >= EXT_IRQ0 && irq <= (EXT_IRQ0 + EXT_IRQS)); } -static void h8300_enable_irq(unsigned int irq) +static void h8300_enable_irq(struct irq_data *data) { - if (is_ext_irq(irq)) - IER_REGS |= 1 << (irq - EXT_IRQ0); + if (is_ext_irq(data->irq)) + IER_REGS |= 1 << (data->irq - EXT_IRQ0); } -static void h8300_disable_irq(unsigned int irq) +static void h8300_disable_irq(struct irq_data *data) { - if (is_ext_irq(irq)) - IER_REGS &= ~(1 << (irq - EXT_IRQ0)); + if (is_ext_irq(data->irq)) + IER_REGS &= ~(1 << (data->irq - EXT_IRQ0)); } static void h8300_end_irq(unsigned int irq) { } -static unsigned int h8300_startup_irq(unsigned int irq) +static unsigned int h8300_startup_irq(struct irq_data *data) { - if (is_ext_irq(irq)) - return h8300_enable_irq_pin(irq); + if (is_ext_irq(data->irq)) + return h8300_enable_irq_pin(data->irq); else return 0; } -static void h8300_shutdown_irq(unsigned int irq) +static void h8300_shutdown_irq(struct irq_data *data) { - if (is_ext_irq(irq)) - h8300_disable_irq_pin(irq); + if (is_ext_irq(data->irq)) + h8300_disable_irq_pin(data->irq); } /* @@ -73,11 +73,10 @@ static void h8300_shutdown_irq(unsigned int irq) */ struct irq_chip h8300irq_chip = { .name = "H8300-INTC", - .startup = h8300_startup_irq, - .shutdown = h8300_shutdown_irq, - .enable = h8300_enable_irq, - .disable = h8300_disable_irq, - .ack = NULL, + .irq_startup = h8300_startup_irq, + .irq_shutdown = h8300_shutdown_irq, + .irq_enable = h8300_enable_irq, + .irq_disable = h8300_disable_irq, .end = h8300_end_irq, }; -- cgit v0.10.2 From f9f91ef5e3a5bc1d4aa05b5d26c4d9e6dd930750 Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Wed, 19 Jan 2011 12:18:57 +0100 Subject: h8300: Convert interrupt handling to flow handler __do_IRQ is deprecated so h8300 needs to be converted to proper flow handling. The irq chip is simple and does not required any mask/ack/eoi functions, so we can use handle_simple_irq. Signed-off-by: Thomas Gleixner Cc: Yoshinori Sato Cc: Paul Mundt diff --git a/arch/h8300/kernel/irq.c b/arch/h8300/kernel/irq.c index e23f346..0c56735 100644 --- a/arch/h8300/kernel/irq.c +++ b/arch/h8300/kernel/irq.c @@ -50,10 +50,6 @@ static void h8300_disable_irq(struct irq_data *data) IER_REGS &= ~(1 << (data->irq - EXT_IRQ0)); } -static void h8300_end_irq(unsigned int irq) -{ -} - static unsigned int h8300_startup_irq(struct irq_data *data) { if (is_ext_irq(data->irq)) @@ -77,7 +73,6 @@ struct irq_chip h8300irq_chip = { .irq_shutdown = h8300_shutdown_irq, .irq_enable = h8300_enable_irq, .irq_disable = h8300_disable_irq, - .end = h8300_end_irq, }; #if defined(CONFIG_RAMKERNEL) @@ -159,18 +154,14 @@ void __init init_IRQ(void) setup_vector(); - for (c = 0; c < NR_IRQS; c++) { - irq_desc[c].status = IRQ_DISABLED; - irq_desc[c].action = NULL; - irq_desc[c].depth = 1; - irq_desc[c].chip = &h8300irq_chip; - } + for (c = 0; c < NR_IRQS; c++) + set_irq_chip_and_handler(c, &h8300irq_chip, handle_simple_irq); } asmlinkage void do_IRQ(int irq) { irq_enter(); - __do_IRQ(irq); + generic_handle_irq(irq); irq_exit(); } -- cgit v0.10.2 From 51f3f15945aa2ccbc90baf17d912aed9981697b2 Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Wed, 19 Jan 2011 12:26:32 +0100 Subject: h8300: Use generic irq Kconfig Switch to the generic irq Kconfig. h8300 has all irq chips converted to the new functions, so select the GENERIC_HARDIRQS_NO_DEPRECATED switch as well. Fixup the resulting fallout in show_interrupts(). Signed-off-by: Thomas Gleixner Cc: Yoshinori Sato Cc: Paul Mundt diff --git a/arch/h8300/Kconfig b/arch/h8300/Kconfig index 65f897d8..6df692d 100644 --- a/arch/h8300/Kconfig +++ b/arch/h8300/Kconfig @@ -2,6 +2,8 @@ config H8300 bool default y select HAVE_IDE + select HAVE_GENERIC_HARDIRQS + select GENERIC_HARDIRQS_NO_DEPRECATED config SYMBOL_PREFIX string @@ -47,10 +49,6 @@ config GENERIC_HWEIGHT bool default y -config GENERIC_HARDIRQS - bool - default y - config GENERIC_CALIBRATE_DELAY bool default y diff --git a/arch/h8300/kernel/irq.c b/arch/h8300/kernel/irq.c index 0c56735..7643d39 100644 --- a/arch/h8300/kernel/irq.c +++ b/arch/h8300/kernel/irq.c @@ -182,7 +182,7 @@ int show_interrupts(struct seq_file *p, void *v) goto unlock; seq_printf(p, "%3d: ",i); seq_printf(p, "%10u ", kstat_irqs(i)); - seq_printf(p, " %14s", irq_desc[i].chip->name); + seq_printf(p, " %14s", irq_desc[i].irq_data.chip->name); seq_printf(p, "-%-8s", irq_desc[i].name); seq_printf(p, " %s", action->name); -- cgit v0.10.2 From c84077ac29978cbfb42dccbba3fee8523605e839 Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Wed, 19 Jan 2011 13:59:01 +0100 Subject: cris: Use irq handling wrapper Use the wrapper around __do_IRQ() so we can convert V10 and V32 seperately. Signed-off-by: Thomas Gleixner Cc: Mikael Starvik diff --git a/arch/cris/kernel/irq.c b/arch/cris/kernel/irq.c index 469f7f9..b6117b4 100644 --- a/arch/cris/kernel/irq.c +++ b/arch/cris/kernel/irq.c @@ -93,8 +93,8 @@ asmlinkage void do_IRQ(int irq, struct pt_regs * regs) printk("do_IRQ: stack overflow: %lX\n", sp); show_stack(NULL, (unsigned long *)sp); } - __do_IRQ(irq); - irq_exit(); + generic_handle_irq(irq); + irq_exit(); set_irq_regs(old_regs); } -- cgit v0.10.2 From f7a004baa202f919d060c2da250535b085813a4b Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Wed, 19 Jan 2011 13:54:54 +0100 Subject: cris: Convert V10 interrupt handling Convert the irq_chip functions and install handle_simple_irq for each interrupt. This converts V10 to the flow handling and lets us remove __do_IRQ(). Signed-off-by: Thomas Gleixner Cc: Mikael Starvik diff --git a/arch/cris/arch-v10/kernel/irq.c b/arch/cris/arch-v10/kernel/irq.c index a0c0df8..7328a7c 100644 --- a/arch/cris/arch-v10/kernel/irq.c +++ b/arch/cris/arch-v10/kernel/irq.c @@ -104,43 +104,21 @@ static void (*interrupt[NR_IRQS])(void) = { IRQ31_interrupt }; -static void enable_crisv10_irq(unsigned int irq); - -static unsigned int startup_crisv10_irq(unsigned int irq) -{ - enable_crisv10_irq(irq); - return 0; -} - -#define shutdown_crisv10_irq disable_crisv10_irq - -static void enable_crisv10_irq(unsigned int irq) -{ - crisv10_unmask_irq(irq); -} - -static void disable_crisv10_irq(unsigned int irq) -{ - crisv10_mask_irq(irq); -} - -static void ack_crisv10_irq(unsigned int irq) +static void enable_crisv10_irq(struct irq_data *data) { + crisv10_unmask_irq(data->irq); } -static void end_crisv10_irq(unsigned int irq) +static void disable_crisv10_irq(struct irq_data *data) { + crisv10_mask_irq(data->irq); } static struct irq_chip crisv10_irq_type = { - .name = "CRISv10", - .startup = startup_crisv10_irq, - .shutdown = shutdown_crisv10_irq, - .enable = enable_crisv10_irq, - .disable = disable_crisv10_irq, - .ack = ack_crisv10_irq, - .end = end_crisv10_irq, - .set_affinity = NULL + .name = "CRISv10", + .irq_shutdown = disable_crisv10_irq, + .irq_enable = enable_crisv10_irq, + .irq_disable = disable_crisv10_irq, }; void weird_irq(void); @@ -221,7 +199,8 @@ init_IRQ(void) /* Initialize IRQ handler descriptors. */ for(i = 2; i < NR_IRQS; i++) { - irq_desc[i].chip = &crisv10_irq_type; + set_irq_desc_and_handler(i, &crisv10_irq_type, + handle_simple_irq); set_int_vector(i, interrupt[i]); } -- cgit v0.10.2 From 9af7503dbd9c4c5e11fcf253ac93fefc9793dff8 Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Wed, 19 Jan 2011 14:05:30 +0100 Subject: cris: Convert V32 interrupt handling Convert the irq chip functions and install handle_simple_irq for each interrupt to get rid of __do_IRQ() Signed-off-by: Thomas Gleixner Cc: Mikael Starvik diff --git a/arch/cris/arch-v32/kernel/irq.c b/arch/cris/arch-v32/kernel/irq.c index 2ed48ae3d..0ad9db5 100644 --- a/arch/cris/arch-v32/kernel/irq.c +++ b/arch/cris/arch-v32/kernel/irq.c @@ -291,54 +291,33 @@ void crisv32_unmask_irq(int irq) } -static unsigned int startup_crisv32_irq(unsigned int irq) +static void enable_crisv32_irq(struct irq_data *data) { - crisv32_unmask_irq(irq); - return 0; -} - -static void shutdown_crisv32_irq(unsigned int irq) -{ - crisv32_mask_irq(irq); + crisv32_unmask_irq(data->irq); } -static void enable_crisv32_irq(unsigned int irq) +static void disable_crisv32_irq(struct irq_data *data) { - crisv32_unmask_irq(irq); + crisv32_mask_irq(data->irq); } -static void disable_crisv32_irq(unsigned int irq) -{ - crisv32_mask_irq(irq); -} - -static void ack_crisv32_irq(unsigned int irq) -{ -} - -static void end_crisv32_irq(unsigned int irq) -{ -} - -int set_affinity_crisv32_irq(unsigned int irq, const struct cpumask *dest) +static int set_affinity_crisv32_irq(struct irq_data *data, + const struct cpumask *dest, bool force) { unsigned long flags; + spin_lock_irqsave(&irq_lock, flags); - irq_allocations[irq - FIRST_IRQ].mask = *dest; + irq_allocations[data->irq - FIRST_IRQ].mask = *dest; spin_unlock_irqrestore(&irq_lock, flags); - return 0; } static struct irq_chip crisv32_irq_type = { - .name = "CRISv32", - .startup = startup_crisv32_irq, - .shutdown = shutdown_crisv32_irq, - .enable = enable_crisv32_irq, - .disable = disable_crisv32_irq, - .ack = ack_crisv32_irq, - .end = end_crisv32_irq, - .set_affinity = set_affinity_crisv32_irq + .name = "CRISv32", + .irq_shutdown = disable_crisv32_irq, + .irq_enable = enable_crisv32_irq, + .irq_disable = disable_crisv32_irq, + .irq_set_affinity = set_affinity_crisv32_irq, }; void @@ -472,7 +451,8 @@ init_IRQ(void) /* Point all IRQ's to bad handlers. */ for (i = FIRST_IRQ, j = 0; j < NR_IRQS; i++, j++) { - irq_desc[j].chip = &crisv32_irq_type; + set_irq_chip_and_handler(j, &crisv32_irq_type, + handle_simple_irq); set_exception_vector(i, interrupt[j]); } -- cgit v0.10.2 From 30139785e615c97497864a89511db02839fa7bf5 Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Wed, 19 Jan 2011 14:20:13 +0100 Subject: cris: Use generic irq Kconfig Use the generic irq Kconfig. Select GENERIC_HARDIRQS_NO_DEPRECATED as we have converted all irq_chip functions. Fix the fallout in show_interrupts(). Signed-off-by: Thomas Gleixner Cc: Mikael Starvik diff --git a/arch/cris/Kconfig b/arch/cris/Kconfig index 613e628..0a7a4c1 100644 --- a/arch/cris/Kconfig +++ b/arch/cris/Kconfig @@ -54,6 +54,8 @@ config CRIS bool default y select HAVE_IDE + select HAVE_GENERIC_HARDIRQS + select GENERIC_HARDIRQS_NO_DEPRECATED config HZ int @@ -67,10 +69,6 @@ menu "General setup" source "fs/Kconfig.binfmt" -config GENERIC_HARDIRQS - bool - default y - config ETRAX_CMDLINE string "Kernel command line" default "root=/dev/mtdblock3" diff --git a/arch/cris/kernel/irq.c b/arch/cris/kernel/irq.c index b6117b4..c346952 100644 --- a/arch/cris/kernel/irq.c +++ b/arch/cris/kernel/irq.c @@ -62,7 +62,7 @@ int show_interrupts(struct seq_file *p, void *v) for_each_online_cpu(j) seq_printf(p, "%10u ", kstat_irqs_cpu(i, j)); #endif - seq_printf(p, " %14s", irq_desc[i].chip->name); + seq_printf(p, " %14s", irq_desc[i].irq_data.chip->name); seq_printf(p, " %s", action->name); for (action=action->next; action; action = action->next) -- cgit v0.10.2 From 863018a7a24a29c0862c62e70c89244fdd5a08bf Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Wed, 22 Sep 2010 19:13:16 +0200 Subject: m32r: Cleanup direct irq_desc access The irq descriptors are already initialized by the generic code. Remove the redundant init code and set the irq chip with the proper accessor function. Signed-off-by: Thomas Gleixner Cc: Hirokazu Takata Cc: Paul Mundt diff --git a/arch/m32r/kernel/irq.c b/arch/m32r/kernel/irq.c index 7db26f1..f745c12 100644 --- a/arch/m32r/kernel/irq.c +++ b/arch/m32r/kernel/irq.c @@ -40,8 +40,10 @@ int show_interrupts(struct seq_file *p, void *v) } if (i < NR_IRQS) { - raw_spin_lock_irqsave(&irq_desc[i].lock, flags); - action = irq_desc[i].action; + struct irq_desc *desc = irq_to_desc(i); + + raw_spin_lock_irqsave(&desc->lock, flags); + action = desc->action; if (!action) goto skip; seq_printf(p, "%3d: ",i); @@ -51,7 +53,7 @@ int show_interrupts(struct seq_file *p, void *v) for_each_online_cpu(j) seq_printf(p, "%10u ", kstat_irqs_cpu(i, j)); #endif - seq_printf(p, " %14s", irq_desc[i].chip->name); + seq_printf(p, " %14s", desc->irq_data.chip->name); seq_printf(p, " %s", action->name); for (action=action->next; action; action = action->next) @@ -59,7 +61,7 @@ int show_interrupts(struct seq_file *p, void *v) seq_putc(p, '\n'); skip: - raw_spin_unlock_irqrestore(&irq_desc[i].lock, flags); + raw_spin_unlock_irqrestore(&desc->lock, flags); } return 0; } diff --git a/arch/m32r/platforms/m32104ut/setup.c b/arch/m32r/platforms/m32104ut/setup.c index 402a59d..962f38e 100644 --- a/arch/m32r/platforms/m32104ut/setup.c +++ b/arch/m32r/platforms/m32104ut/setup.c @@ -85,36 +85,24 @@ void __init init_IRQ(void) #if defined(CONFIG_SMC91X) /* INT#0: LAN controller on M32104UT-LAN (SMC91C111)*/ - irq_desc[M32R_IRQ_INT0].status = IRQ_DISABLED; - irq_desc[M32R_IRQ_INT0].chip = &m32104ut_irq_type; - irq_desc[M32R_IRQ_INT0].action = 0; - irq_desc[M32R_IRQ_INT0].depth = 1; + set_irq_chip(M32R_IRQ_INT0, &m32104ut_irq_type); icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN | M32R_ICUCR_ISMOD11; /* "H" level sense */ disable_m32104ut_irq(M32R_IRQ_INT0); #endif /* CONFIG_SMC91X */ /* MFT2 : system timer */ - irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED; - irq_desc[M32R_IRQ_MFT2].chip = &m32104ut_irq_type; - irq_desc[M32R_IRQ_MFT2].action = 0; - irq_desc[M32R_IRQ_MFT2].depth = 1; + set_irq_chip(M32R_IRQ_MFT2, &m32104ut_irq_type); icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; disable_m32104ut_irq(M32R_IRQ_MFT2); #ifdef CONFIG_SERIAL_M32R_SIO /* SIO0_R : uart receive data */ - irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED; - irq_desc[M32R_IRQ_SIO0_R].chip = &m32104ut_irq_type; - irq_desc[M32R_IRQ_SIO0_R].action = 0; - irq_desc[M32R_IRQ_SIO0_R].depth = 1; + set_irq_chip(M32R_IRQ_SIO0_R, &m32104ut_irq_type); icu_data[M32R_IRQ_SIO0_R].icucr = M32R_ICUCR_IEN; disable_m32104ut_irq(M32R_IRQ_SIO0_R); /* SIO0_S : uart send data */ - irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED; - irq_desc[M32R_IRQ_SIO0_S].chip = &m32104ut_irq_type; - irq_desc[M32R_IRQ_SIO0_S].action = 0; - irq_desc[M32R_IRQ_SIO0_S].depth = 1; + set_irq_chip(M32R_IRQ_SIO0_S, &m32104ut_irq_type); icu_data[M32R_IRQ_SIO0_S].icucr = M32R_ICUCR_IEN; disable_m32104ut_irq(M32R_IRQ_SIO0_S); #endif /* CONFIG_SERIAL_M32R_SIO */ diff --git a/arch/m32r/platforms/m32700ut/setup.c b/arch/m32r/platforms/m32700ut/setup.c index 80b1a02..433bcbc 100644 --- a/arch/m32r/platforms/m32700ut/setup.c +++ b/arch/m32r/platforms/m32700ut/setup.c @@ -299,101 +299,65 @@ void __init init_IRQ(void) { #if defined(CONFIG_SMC91X) /* INT#0: LAN controller on M32700UT-LAN (SMC91C111)*/ - irq_desc[M32700UT_LAN_IRQ_LAN].status = IRQ_DISABLED; - irq_desc[M32700UT_LAN_IRQ_LAN].chip = &m32700ut_lanpld_irq_type; - irq_desc[M32700UT_LAN_IRQ_LAN].action = 0; - irq_desc[M32700UT_LAN_IRQ_LAN].depth = 1; /* disable nested irq */ + set_irq_chip(M32700UT_LAN_IRQ_LAN, &m32700ut_lanpld_irq_type); lanpld_icu_data[irq2lanpldirq(M32700UT_LAN_IRQ_LAN)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* "H" edge sense */ disable_m32700ut_lanpld_irq(M32700UT_LAN_IRQ_LAN); #endif /* CONFIG_SMC91X */ /* MFT2 : system timer */ - irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED; - irq_desc[M32R_IRQ_MFT2].chip = &m32700ut_irq_type; - irq_desc[M32R_IRQ_MFT2].action = 0; - irq_desc[M32R_IRQ_MFT2].depth = 1; + set_irq_chip(M32R_IRQ_MFT2, &m32700ut_irq_type); icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; disable_m32700ut_irq(M32R_IRQ_MFT2); /* SIO0 : receive */ - irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED; - irq_desc[M32R_IRQ_SIO0_R].chip = &m32700ut_irq_type; - irq_desc[M32R_IRQ_SIO0_R].action = 0; - irq_desc[M32R_IRQ_SIO0_R].depth = 1; + set_irq_chip(M32R_IRQ_SIO0_R, &m32700ut_irq_type); icu_data[M32R_IRQ_SIO0_R].icucr = 0; disable_m32700ut_irq(M32R_IRQ_SIO0_R); /* SIO0 : send */ - irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED; - irq_desc[M32R_IRQ_SIO0_S].chip = &m32700ut_irq_type; - irq_desc[M32R_IRQ_SIO0_S].action = 0; - irq_desc[M32R_IRQ_SIO0_S].depth = 1; + set_irq_chip(M32R_IRQ_SIO0_S, &m32700ut_irq_type); icu_data[M32R_IRQ_SIO0_S].icucr = 0; disable_m32700ut_irq(M32R_IRQ_SIO0_S); /* SIO1 : receive */ - irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED; - irq_desc[M32R_IRQ_SIO1_R].chip = &m32700ut_irq_type; - irq_desc[M32R_IRQ_SIO1_R].action = 0; - irq_desc[M32R_IRQ_SIO1_R].depth = 1; + set_irq_chip(M32R_IRQ_SIO1_R, &m32700ut_irq_type); icu_data[M32R_IRQ_SIO1_R].icucr = 0; disable_m32700ut_irq(M32R_IRQ_SIO1_R); /* SIO1 : send */ - irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED; - irq_desc[M32R_IRQ_SIO1_S].chip = &m32700ut_irq_type; - irq_desc[M32R_IRQ_SIO1_S].action = 0; - irq_desc[M32R_IRQ_SIO1_S].depth = 1; + set_irq_chip(M32R_IRQ_SIO1_S, &m32700ut_irq_type); icu_data[M32R_IRQ_SIO1_S].icucr = 0; disable_m32700ut_irq(M32R_IRQ_SIO1_S); /* DMA1 : */ - irq_desc[M32R_IRQ_DMA1].status = IRQ_DISABLED; - irq_desc[M32R_IRQ_DMA1].chip = &m32700ut_irq_type; - irq_desc[M32R_IRQ_DMA1].action = 0; - irq_desc[M32R_IRQ_DMA1].depth = 1; + set_irq_chip(M32R_IRQ_DMA1, &m32700ut_irq_type); icu_data[M32R_IRQ_DMA1].icucr = 0; disable_m32700ut_irq(M32R_IRQ_DMA1); #ifdef CONFIG_SERIAL_M32R_PLDSIO /* INT#1: SIO0 Receive on PLD */ - irq_desc[PLD_IRQ_SIO0_RCV].status = IRQ_DISABLED; - irq_desc[PLD_IRQ_SIO0_RCV].chip = &m32700ut_pld_irq_type; - irq_desc[PLD_IRQ_SIO0_RCV].action = 0; - irq_desc[PLD_IRQ_SIO0_RCV].depth = 1; /* disable nested irq */ + set_irq_chip(PLD_IRQ_SIO0_RCV, &m32700ut_pld_irq_type); pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_RCV)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03; disable_m32700ut_pld_irq(PLD_IRQ_SIO0_RCV); /* INT#1: SIO0 Send on PLD */ - irq_desc[PLD_IRQ_SIO0_SND].status = IRQ_DISABLED; - irq_desc[PLD_IRQ_SIO0_SND].chip = &m32700ut_pld_irq_type; - irq_desc[PLD_IRQ_SIO0_SND].action = 0; - irq_desc[PLD_IRQ_SIO0_SND].depth = 1; /* disable nested irq */ + set_irq_chip(PLD_IRQ_SIO0_SND, &m32700ut_pld_irq_type); pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_SND)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03; disable_m32700ut_pld_irq(PLD_IRQ_SIO0_SND); #endif /* CONFIG_SERIAL_M32R_PLDSIO */ /* INT#1: CFC IREQ on PLD */ - irq_desc[PLD_IRQ_CFIREQ].status = IRQ_DISABLED; - irq_desc[PLD_IRQ_CFIREQ].chip = &m32700ut_pld_irq_type; - irq_desc[PLD_IRQ_CFIREQ].action = 0; - irq_desc[PLD_IRQ_CFIREQ].depth = 1; /* disable nested irq */ + set_irq_chip(PLD_IRQ_CFIREQ, &m32700ut_pld_irq_type); pld_icu_data[irq2pldirq(PLD_IRQ_CFIREQ)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* 'L' level sense */ disable_m32700ut_pld_irq(PLD_IRQ_CFIREQ); /* INT#1: CFC Insert on PLD */ - irq_desc[PLD_IRQ_CFC_INSERT].status = IRQ_DISABLED; - irq_desc[PLD_IRQ_CFC_INSERT].chip = &m32700ut_pld_irq_type; - irq_desc[PLD_IRQ_CFC_INSERT].action = 0; - irq_desc[PLD_IRQ_CFC_INSERT].depth = 1; /* disable nested irq */ + set_irq_chip(PLD_IRQ_CFC_INSERT, &m32700ut_pld_irq_type); pld_icu_data[irq2pldirq(PLD_IRQ_CFC_INSERT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD00; /* 'L' edge sense */ disable_m32700ut_pld_irq(PLD_IRQ_CFC_INSERT); /* INT#1: CFC Eject on PLD */ - irq_desc[PLD_IRQ_CFC_EJECT].status = IRQ_DISABLED; - irq_desc[PLD_IRQ_CFC_EJECT].chip = &m32700ut_pld_irq_type; - irq_desc[PLD_IRQ_CFC_EJECT].action = 0; - irq_desc[PLD_IRQ_CFC_EJECT].depth = 1; /* disable nested irq */ + set_irq_chip(PLD_IRQ_CFC_EJECT, &m32700ut_pld_irq_type); pld_icu_data[irq2pldirq(PLD_IRQ_CFC_EJECT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* 'H' edge sense */ disable_m32700ut_pld_irq(PLD_IRQ_CFC_EJECT); @@ -413,13 +377,10 @@ void __init init_IRQ(void) #if defined(CONFIG_USB) outw(USBCR_OTGS, USBCR); /* USBCR: non-OTG */ + set_irq_chip(M32700UT_LCD_IRQ_USB_INT1, &m32700ut_lcdpld_irq_type); - irq_desc[M32700UT_LCD_IRQ_USB_INT1].status = IRQ_DISABLED; - irq_desc[M32700UT_LCD_IRQ_USB_INT1].chip = &m32700ut_lcdpld_irq_type; - irq_desc[M32700UT_LCD_IRQ_USB_INT1].action = 0; - irq_desc[M32700UT_LCD_IRQ_USB_INT1].depth = 1; - lcdpld_icu_data[irq2lcdpldirq(M32700UT_LCD_IRQ_USB_INT1)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* "L" level sense */ - disable_m32700ut_lcdpld_irq(M32700UT_LCD_IRQ_USB_INT1); + lcdpld_icu_data[irq2lcdpldirq(M32700UT_LCD_IRQ_USB_INT1)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* "L" level sense */ + disable_m32700ut_lcdpld_irq(M32700UT_LCD_IRQ_USB_INT1); #endif /* * INT2# is used for BAT, USB, AUDIO @@ -432,10 +393,7 @@ void __init init_IRQ(void) /* * INT3# is used for AR */ - irq_desc[M32R_IRQ_INT3].status = IRQ_DISABLED; - irq_desc[M32R_IRQ_INT3].chip = &m32700ut_irq_type; - irq_desc[M32R_IRQ_INT3].action = 0; - irq_desc[M32R_IRQ_INT3].depth = 1; + set_irq_chip(M32R_IRQ_INT3, &m32700ut_irq_type); icu_data[M32R_IRQ_INT3].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; disable_m32700ut_irq(M32R_IRQ_INT3); #endif /* CONFIG_VIDEO_M32R_AR */ diff --git a/arch/m32r/platforms/mappi/setup.c b/arch/m32r/platforms/mappi/setup.c index ea00c84..bc3fdaf 100644 --- a/arch/m32r/platforms/mappi/setup.c +++ b/arch/m32r/platforms/mappi/setup.c @@ -45,7 +45,6 @@ static void mask_and_ack_mappi(unsigned int irq) static void end_mappi_irq(unsigned int irq) { - if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) enable_mappi_irq(irq); } @@ -85,70 +84,46 @@ void __init init_IRQ(void) #ifdef CONFIG_NE2000 /* INT0 : LAN controller (RTL8019AS) */ - irq_desc[M32R_IRQ_INT0].status = IRQ_DISABLED; - irq_desc[M32R_IRQ_INT0].chip = &mappi_irq_type; - irq_desc[M32R_IRQ_INT0].action = NULL; - irq_desc[M32R_IRQ_INT0].depth = 1; + set_irq_chip(M32R_IRQ_INT0, &mappi_irq_type); icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD11; disable_mappi_irq(M32R_IRQ_INT0); #endif /* CONFIG_M32R_NE2000 */ /* MFT2 : system timer */ - irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED; - irq_desc[M32R_IRQ_MFT2].chip = &mappi_irq_type; - irq_desc[M32R_IRQ_MFT2].action = NULL; - irq_desc[M32R_IRQ_MFT2].depth = 1; + set_irq_chip(M32R_IRQ_MFT2, &mappi_irq_type); icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; disable_mappi_irq(M32R_IRQ_MFT2); #ifdef CONFIG_SERIAL_M32R_SIO /* SIO0_R : uart receive data */ - irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED; - irq_desc[M32R_IRQ_SIO0_R].chip = &mappi_irq_type; - irq_desc[M32R_IRQ_SIO0_R].action = NULL; - irq_desc[M32R_IRQ_SIO0_R].depth = 1; + set_irq_chip(M32R_IRQ_SIO0_R, &mappi_irq_type); icu_data[M32R_IRQ_SIO0_R].icucr = 0; disable_mappi_irq(M32R_IRQ_SIO0_R); /* SIO0_S : uart send data */ - irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED; - irq_desc[M32R_IRQ_SIO0_S].chip = &mappi_irq_type; - irq_desc[M32R_IRQ_SIO0_S].action = NULL; - irq_desc[M32R_IRQ_SIO0_S].depth = 1; + set_irq_chip(M32R_IRQ_SIO0_S, &mappi_irq_type); icu_data[M32R_IRQ_SIO0_S].icucr = 0; disable_mappi_irq(M32R_IRQ_SIO0_S); /* SIO1_R : uart receive data */ - irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED; - irq_desc[M32R_IRQ_SIO1_R].chip = &mappi_irq_type; - irq_desc[M32R_IRQ_SIO1_R].action = NULL; - irq_desc[M32R_IRQ_SIO1_R].depth = 1; + set_irq_chip(M32R_IRQ_SIO1_R, &mappi_irq_type); icu_data[M32R_IRQ_SIO1_R].icucr = 0; disable_mappi_irq(M32R_IRQ_SIO1_R); /* SIO1_S : uart send data */ - irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED; - irq_desc[M32R_IRQ_SIO1_S].chip = &mappi_irq_type; - irq_desc[M32R_IRQ_SIO1_S].action = NULL; - irq_desc[M32R_IRQ_SIO1_S].depth = 1; + set_irq_chip(M32R_IRQ_SIO1_S, &mappi_irq_type); icu_data[M32R_IRQ_SIO1_S].icucr = 0; disable_mappi_irq(M32R_IRQ_SIO1_S); #endif /* CONFIG_SERIAL_M32R_SIO */ #if defined(CONFIG_M32R_PCC) /* INT1 : pccard0 interrupt */ - irq_desc[M32R_IRQ_INT1].status = IRQ_DISABLED; - irq_desc[M32R_IRQ_INT1].chip = &mappi_irq_type; - irq_desc[M32R_IRQ_INT1].action = NULL; - irq_desc[M32R_IRQ_INT1].depth = 1; + set_irq_chip(M32R_IRQ_INT1, &mappi_irq_type); icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_IEN | M32R_ICUCR_ISMOD00; disable_mappi_irq(M32R_IRQ_INT1); /* INT2 : pccard1 interrupt */ - irq_desc[M32R_IRQ_INT2].status = IRQ_DISABLED; - irq_desc[M32R_IRQ_INT2].chip = &mappi_irq_type; - irq_desc[M32R_IRQ_INT2].action = NULL; - irq_desc[M32R_IRQ_INT2].depth = 1; + set_irq_chip(M32R_IRQ_INT2, &mappi_irq_type); icu_data[M32R_IRQ_INT2].icucr = M32R_ICUCR_IEN | M32R_ICUCR_ISMOD00; disable_mappi_irq(M32R_IRQ_INT2); #endif /* CONFIG_M32RPCC */ diff --git a/arch/m32r/platforms/mappi2/setup.c b/arch/m32r/platforms/mappi2/setup.c index c049376..87bba1e 100644 --- a/arch/m32r/platforms/mappi2/setup.c +++ b/arch/m32r/platforms/mappi2/setup.c @@ -85,87 +85,57 @@ void __init init_IRQ(void) { #if defined(CONFIG_SMC91X) /* INT0 : LAN controller (SMC91111) */ - irq_desc[M32R_IRQ_INT0].status = IRQ_DISABLED; - irq_desc[M32R_IRQ_INT0].chip = &mappi2_irq_type; - irq_desc[M32R_IRQ_INT0].action = 0; - irq_desc[M32R_IRQ_INT0].depth = 1; + set_irq_chip(M32R_IRQ_INT0, &mappi2_irq_type); icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; disable_mappi2_irq(M32R_IRQ_INT0); #endif /* CONFIG_SMC91X */ /* MFT2 : system timer */ - irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED; - irq_desc[M32R_IRQ_MFT2].chip = &mappi2_irq_type; - irq_desc[M32R_IRQ_MFT2].action = 0; - irq_desc[M32R_IRQ_MFT2].depth = 1; + set_irq_chip(M32R_IRQ_MFT2, &mappi2_irq_type); icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; disable_mappi2_irq(M32R_IRQ_MFT2); #ifdef CONFIG_SERIAL_M32R_SIO /* SIO0_R : uart receive data */ - irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED; - irq_desc[M32R_IRQ_SIO0_R].chip = &mappi2_irq_type; - irq_desc[M32R_IRQ_SIO0_R].action = 0; - irq_desc[M32R_IRQ_SIO0_R].depth = 1; + set_irq_chip(M32R_IRQ_SIO0_R, &mappi2_irq_type); icu_data[M32R_IRQ_SIO0_R].icucr = 0; disable_mappi2_irq(M32R_IRQ_SIO0_R); /* SIO0_S : uart send data */ - irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED; - irq_desc[M32R_IRQ_SIO0_S].chip = &mappi2_irq_type; - irq_desc[M32R_IRQ_SIO0_S].action = 0; - irq_desc[M32R_IRQ_SIO0_S].depth = 1; + set_irq_chip(M32R_IRQ_SIO0_S, &mappi2_irq_type); icu_data[M32R_IRQ_SIO0_S].icucr = 0; disable_mappi2_irq(M32R_IRQ_SIO0_S); /* SIO1_R : uart receive data */ - irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED; - irq_desc[M32R_IRQ_SIO1_R].chip = &mappi2_irq_type; - irq_desc[M32R_IRQ_SIO1_R].action = 0; - irq_desc[M32R_IRQ_SIO1_R].depth = 1; + set_irq_chip(M32R_IRQ_SIO1_R, &mappi2_irq_type); icu_data[M32R_IRQ_SIO1_R].icucr = 0; disable_mappi2_irq(M32R_IRQ_SIO1_R); /* SIO1_S : uart send data */ - irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED; - irq_desc[M32R_IRQ_SIO1_S].chip = &mappi2_irq_type; - irq_desc[M32R_IRQ_SIO1_S].action = 0; - irq_desc[M32R_IRQ_SIO1_S].depth = 1; + set_irq_chip(M32R_IRQ_SIO1_S, &mappi2_irq_type); icu_data[M32R_IRQ_SIO1_S].icucr = 0; disable_mappi2_irq(M32R_IRQ_SIO1_S); #endif /* CONFIG_M32R_USE_DBG_CONSOLE */ #if defined(CONFIG_USB) /* INT1 : USB Host controller interrupt */ - irq_desc[M32R_IRQ_INT1].status = IRQ_DISABLED; - irq_desc[M32R_IRQ_INT1].chip = &mappi2_irq_type; - irq_desc[M32R_IRQ_INT1].action = 0; - irq_desc[M32R_IRQ_INT1].depth = 1; + set_irq_chip(M32R_IRQ_INT1, &mappi2_irq_type); icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_ISMOD01; disable_mappi2_irq(M32R_IRQ_INT1); #endif /* CONFIG_USB */ /* ICUCR40: CFC IREQ */ - irq_desc[PLD_IRQ_CFIREQ].status = IRQ_DISABLED; - irq_desc[PLD_IRQ_CFIREQ].chip = &mappi2_irq_type; - irq_desc[PLD_IRQ_CFIREQ].action = 0; - irq_desc[PLD_IRQ_CFIREQ].depth = 1; /* disable nested irq */ + set_irq_chip(PLD_IRQ_CFIREQ, &mappi2_irq_type); icu_data[PLD_IRQ_CFIREQ].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD01; disable_mappi2_irq(PLD_IRQ_CFIREQ); #if defined(CONFIG_M32R_CFC) /* ICUCR41: CFC Insert */ - irq_desc[PLD_IRQ_CFC_INSERT].status = IRQ_DISABLED; - irq_desc[PLD_IRQ_CFC_INSERT].chip = &mappi2_irq_type; - irq_desc[PLD_IRQ_CFC_INSERT].action = 0; - irq_desc[PLD_IRQ_CFC_INSERT].depth = 1; /* disable nested irq */ + set_irq_chip(PLD_IRQ_CFC_INSERT, &mappi2_irq_type); icu_data[PLD_IRQ_CFC_INSERT].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD00; disable_mappi2_irq(PLD_IRQ_CFC_INSERT); /* ICUCR42: CFC Eject */ - irq_desc[PLD_IRQ_CFC_EJECT].status = IRQ_DISABLED; - irq_desc[PLD_IRQ_CFC_EJECT].chip = &mappi2_irq_type; - irq_desc[PLD_IRQ_CFC_EJECT].action = 0; - irq_desc[PLD_IRQ_CFC_EJECT].depth = 1; /* disable nested irq */ + set_irq_chip(PLD_IRQ_CFC_EJECT, &mappi2_irq_type); icu_data[PLD_IRQ_CFC_EJECT].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; disable_mappi2_irq(PLD_IRQ_CFC_EJECT); #endif /* CONFIG_MAPPI2_CFC */ diff --git a/arch/m32r/platforms/mappi3/setup.c b/arch/m32r/platforms/mappi3/setup.c index 882de25..7409814 100644 --- a/arch/m32r/platforms/mappi3/setup.c +++ b/arch/m32r/platforms/mappi3/setup.c @@ -85,89 +85,59 @@ void __init init_IRQ(void) { #if defined(CONFIG_SMC91X) /* INT0 : LAN controller (SMC91111) */ - irq_desc[M32R_IRQ_INT0].status = IRQ_DISABLED; - irq_desc[M32R_IRQ_INT0].chip = &mappi3_irq_type; - irq_desc[M32R_IRQ_INT0].action = 0; - irq_desc[M32R_IRQ_INT0].depth = 1; + set_irq_chip(M32R_IRQ_INT0, &mappi3_irq_type); icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; disable_mappi3_irq(M32R_IRQ_INT0); #endif /* CONFIG_SMC91X */ /* MFT2 : system timer */ - irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED; - irq_desc[M32R_IRQ_MFT2].chip = &mappi3_irq_type; - irq_desc[M32R_IRQ_MFT2].action = 0; - irq_desc[M32R_IRQ_MFT2].depth = 1; + set_irq_chip(M32R_IRQ_MFT2, &mappi3_irq_type); icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; disable_mappi3_irq(M32R_IRQ_MFT2); #ifdef CONFIG_SERIAL_M32R_SIO /* SIO0_R : uart receive data */ - irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED; - irq_desc[M32R_IRQ_SIO0_R].chip = &mappi3_irq_type; - irq_desc[M32R_IRQ_SIO0_R].action = 0; - irq_desc[M32R_IRQ_SIO0_R].depth = 1; + set_irq_chip(M32R_IRQ_SIO0_R, &mappi3_irq_type); icu_data[M32R_IRQ_SIO0_R].icucr = 0; disable_mappi3_irq(M32R_IRQ_SIO0_R); /* SIO0_S : uart send data */ - irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED; - irq_desc[M32R_IRQ_SIO0_S].chip = &mappi3_irq_type; - irq_desc[M32R_IRQ_SIO0_S].action = 0; - irq_desc[M32R_IRQ_SIO0_S].depth = 1; + set_irq_chip(M32R_IRQ_SIO0_S, &mappi3_irq_type); icu_data[M32R_IRQ_SIO0_S].icucr = 0; disable_mappi3_irq(M32R_IRQ_SIO0_S); /* SIO1_R : uart receive data */ - irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED; - irq_desc[M32R_IRQ_SIO1_R].chip = &mappi3_irq_type; - irq_desc[M32R_IRQ_SIO1_R].action = 0; - irq_desc[M32R_IRQ_SIO1_R].depth = 1; + set_irq_chip(M32R_IRQ_SIO1_R, &mappi3_irq_type); icu_data[M32R_IRQ_SIO1_R].icucr = 0; disable_mappi3_irq(M32R_IRQ_SIO1_R); /* SIO1_S : uart send data */ - irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED; - irq_desc[M32R_IRQ_SIO1_S].chip = &mappi3_irq_type; - irq_desc[M32R_IRQ_SIO1_S].action = 0; - irq_desc[M32R_IRQ_SIO1_S].depth = 1; + set_irq_chip(M32R_IRQ_SIO1_S, &mappi3_irq_type); icu_data[M32R_IRQ_SIO1_S].icucr = 0; disable_mappi3_irq(M32R_IRQ_SIO1_S); #endif /* CONFIG_M32R_USE_DBG_CONSOLE */ #if defined(CONFIG_USB) /* INT1 : USB Host controller interrupt */ - irq_desc[M32R_IRQ_INT1].status = IRQ_DISABLED; - irq_desc[M32R_IRQ_INT1].chip = &mappi3_irq_type; - irq_desc[M32R_IRQ_INT1].action = 0; - irq_desc[M32R_IRQ_INT1].depth = 1; + set_irq_chip(M32R_IRQ_INT1, &mappi3_irq_type); icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_ISMOD01; disable_mappi3_irq(M32R_IRQ_INT1); #endif /* CONFIG_USB */ /* CFC IREQ */ - irq_desc[PLD_IRQ_CFIREQ].status = IRQ_DISABLED; - irq_desc[PLD_IRQ_CFIREQ].chip = &mappi3_irq_type; - irq_desc[PLD_IRQ_CFIREQ].action = 0; - irq_desc[PLD_IRQ_CFIREQ].depth = 1; /* disable nested irq */ + set_irq_chip(PLD_IRQ_CFIREQ, &mappi3_irq_type); icu_data[PLD_IRQ_CFIREQ].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD01; disable_mappi3_irq(PLD_IRQ_CFIREQ); #if defined(CONFIG_M32R_CFC) /* ICUCR41: CFC Insert & eject */ - irq_desc[PLD_IRQ_CFC_INSERT].status = IRQ_DISABLED; - irq_desc[PLD_IRQ_CFC_INSERT].chip = &mappi3_irq_type; - irq_desc[PLD_IRQ_CFC_INSERT].action = 0; - irq_desc[PLD_IRQ_CFC_INSERT].depth = 1; /* disable nested irq */ + set_irq_chip(PLD_IRQ_CFC_INSERT, &mappi3_irq_type); icu_data[PLD_IRQ_CFC_INSERT].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD00; disable_mappi3_irq(PLD_IRQ_CFC_INSERT); #endif /* CONFIG_M32R_CFC */ /* IDE IREQ */ - irq_desc[PLD_IRQ_IDEIREQ].status = IRQ_DISABLED; - irq_desc[PLD_IRQ_IDEIREQ].chip = &mappi3_irq_type; - irq_desc[PLD_IRQ_IDEIREQ].action = 0; - irq_desc[PLD_IRQ_IDEIREQ].depth = 1; /* disable nested irq */ + set_irq_chip(PLD_IRQ_IDEIREQ, &mappi3_irq_type); icu_data[PLD_IRQ_IDEIREQ].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; disable_mappi3_irq(PLD_IRQ_IDEIREQ); diff --git a/arch/m32r/platforms/oaks32r/setup.c b/arch/m32r/platforms/oaks32r/setup.c index d11d93b..43bf5a0 100644 --- a/arch/m32r/platforms/oaks32r/setup.c +++ b/arch/m32r/platforms/oaks32r/setup.c @@ -83,52 +83,34 @@ void __init init_IRQ(void) #ifdef CONFIG_NE2000 /* INT3 : LAN controller (RTL8019AS) */ - irq_desc[M32R_IRQ_INT3].status = IRQ_DISABLED; - irq_desc[M32R_IRQ_INT3].chip = &oaks32r_irq_type; - irq_desc[M32R_IRQ_INT3].action = 0; - irq_desc[M32R_IRQ_INT3].depth = 1; + set_irq_chip(M32R_IRQ_INT3, &oaks32r_irq_type); icu_data[M32R_IRQ_INT3].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; disable_oaks32r_irq(M32R_IRQ_INT3); #endif /* CONFIG_M32R_NE2000 */ /* MFT2 : system timer */ - irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED; - irq_desc[M32R_IRQ_MFT2].chip = &oaks32r_irq_type; - irq_desc[M32R_IRQ_MFT2].action = 0; - irq_desc[M32R_IRQ_MFT2].depth = 1; + set_irq_chip(M32R_IRQ_MFT2, &oaks32r_irq_type); icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; disable_oaks32r_irq(M32R_IRQ_MFT2); #ifdef CONFIG_SERIAL_M32R_SIO /* SIO0_R : uart receive data */ - irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED; - irq_desc[M32R_IRQ_SIO0_R].chip = &oaks32r_irq_type; - irq_desc[M32R_IRQ_SIO0_R].action = 0; - irq_desc[M32R_IRQ_SIO0_R].depth = 1; + set_irq_chip(M32R_IRQ_SIO0_R, &oaks32r_irq_type); icu_data[M32R_IRQ_SIO0_R].icucr = 0; disable_oaks32r_irq(M32R_IRQ_SIO0_R); /* SIO0_S : uart send data */ - irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED; - irq_desc[M32R_IRQ_SIO0_S].chip = &oaks32r_irq_type; - irq_desc[M32R_IRQ_SIO0_S].action = 0; - irq_desc[M32R_IRQ_SIO0_S].depth = 1; + set_irq_chip(M32R_IRQ_SIO0_S, &oaks32r_irq_type); icu_data[M32R_IRQ_SIO0_S].icucr = 0; disable_oaks32r_irq(M32R_IRQ_SIO0_S); /* SIO1_R : uart receive data */ - irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED; - irq_desc[M32R_IRQ_SIO1_R].chip = &oaks32r_irq_type; - irq_desc[M32R_IRQ_SIO1_R].action = 0; - irq_desc[M32R_IRQ_SIO1_R].depth = 1; + set_irq_chip(M32R_IRQ_SIO1_R, &oaks32r_irq_type); icu_data[M32R_IRQ_SIO1_R].icucr = 0; disable_oaks32r_irq(M32R_IRQ_SIO1_R); /* SIO1_S : uart send data */ - irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED; - irq_desc[M32R_IRQ_SIO1_S].chip = &oaks32r_irq_type; - irq_desc[M32R_IRQ_SIO1_S].action = 0; - irq_desc[M32R_IRQ_SIO1_S].depth = 1; + set_irq_chip(M32R_IRQ_SIO1_S, &oaks32r_irq_type); icu_data[M32R_IRQ_SIO1_S].icucr = 0; disable_oaks32r_irq(M32R_IRQ_SIO1_S); #endif /* CONFIG_SERIAL_M32R_SIO */ diff --git a/arch/m32r/platforms/opsput/setup.c b/arch/m32r/platforms/opsput/setup.c index 5f3402a..a16a7fe 100644 --- a/arch/m32r/platforms/opsput/setup.c +++ b/arch/m32r/platforms/opsput/setup.c @@ -300,101 +300,65 @@ void __init init_IRQ(void) { #if defined(CONFIG_SMC91X) /* INT#0: LAN controller on OPSPUT-LAN (SMC91C111)*/ - irq_desc[OPSPUT_LAN_IRQ_LAN].status = IRQ_DISABLED; - irq_desc[OPSPUT_LAN_IRQ_LAN].chip = &opsput_lanpld_irq_type; - irq_desc[OPSPUT_LAN_IRQ_LAN].action = 0; - irq_desc[OPSPUT_LAN_IRQ_LAN].depth = 1; /* disable nested irq */ + set_irq_chip(OPSPUT_LAN_IRQ_LAN, &opsput_lanpld_irq_type); lanpld_icu_data[irq2lanpldirq(OPSPUT_LAN_IRQ_LAN)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* "H" edge sense */ disable_opsput_lanpld_irq(OPSPUT_LAN_IRQ_LAN); #endif /* CONFIG_SMC91X */ /* MFT2 : system timer */ - irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED; - irq_desc[M32R_IRQ_MFT2].chip = &opsput_irq_type; - irq_desc[M32R_IRQ_MFT2].action = 0; - irq_desc[M32R_IRQ_MFT2].depth = 1; + set_irq_chip(M32R_IRQ_MFT2, &opsput_irq_type); icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; disable_opsput_irq(M32R_IRQ_MFT2); /* SIO0 : receive */ - irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED; - irq_desc[M32R_IRQ_SIO0_R].chip = &opsput_irq_type; - irq_desc[M32R_IRQ_SIO0_R].action = 0; - irq_desc[M32R_IRQ_SIO0_R].depth = 1; + set_irq_chip(M32R_IRQ_SIO0_R, &opsput_irq_type); icu_data[M32R_IRQ_SIO0_R].icucr = 0; disable_opsput_irq(M32R_IRQ_SIO0_R); /* SIO0 : send */ - irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED; - irq_desc[M32R_IRQ_SIO0_S].chip = &opsput_irq_type; - irq_desc[M32R_IRQ_SIO0_S].action = 0; - irq_desc[M32R_IRQ_SIO0_S].depth = 1; + set_irq_chip(M32R_IRQ_SIO0_S, &opsput_irq_type); icu_data[M32R_IRQ_SIO0_S].icucr = 0; disable_opsput_irq(M32R_IRQ_SIO0_S); /* SIO1 : receive */ - irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED; - irq_desc[M32R_IRQ_SIO1_R].chip = &opsput_irq_type; - irq_desc[M32R_IRQ_SIO1_R].action = 0; - irq_desc[M32R_IRQ_SIO1_R].depth = 1; + set_irq_chip(M32R_IRQ_SIO1_R, &opsput_irq_type); icu_data[M32R_IRQ_SIO1_R].icucr = 0; disable_opsput_irq(M32R_IRQ_SIO1_R); /* SIO1 : send */ - irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED; - irq_desc[M32R_IRQ_SIO1_S].chip = &opsput_irq_type; - irq_desc[M32R_IRQ_SIO1_S].action = 0; - irq_desc[M32R_IRQ_SIO1_S].depth = 1; + set_irq_chip(M32R_IRQ_SIO1_S, &opsput_irq_type); icu_data[M32R_IRQ_SIO1_S].icucr = 0; disable_opsput_irq(M32R_IRQ_SIO1_S); /* DMA1 : */ - irq_desc[M32R_IRQ_DMA1].status = IRQ_DISABLED; - irq_desc[M32R_IRQ_DMA1].chip = &opsput_irq_type; - irq_desc[M32R_IRQ_DMA1].action = 0; - irq_desc[M32R_IRQ_DMA1].depth = 1; + set_irq_chip(M32R_IRQ_DMA1, &opsput_irq_type); icu_data[M32R_IRQ_DMA1].icucr = 0; disable_opsput_irq(M32R_IRQ_DMA1); #ifdef CONFIG_SERIAL_M32R_PLDSIO /* INT#1: SIO0 Receive on PLD */ - irq_desc[PLD_IRQ_SIO0_RCV].status = IRQ_DISABLED; - irq_desc[PLD_IRQ_SIO0_RCV].chip = &opsput_pld_irq_type; - irq_desc[PLD_IRQ_SIO0_RCV].action = 0; - irq_desc[PLD_IRQ_SIO0_RCV].depth = 1; /* disable nested irq */ + set_irq_chip(PLD_IRQ_SIO0_RCV, &opsput_pld_irq_type); pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_RCV)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03; disable_opsput_pld_irq(PLD_IRQ_SIO0_RCV); /* INT#1: SIO0 Send on PLD */ - irq_desc[PLD_IRQ_SIO0_SND].status = IRQ_DISABLED; - irq_desc[PLD_IRQ_SIO0_SND].chip = &opsput_pld_irq_type; - irq_desc[PLD_IRQ_SIO0_SND].action = 0; - irq_desc[PLD_IRQ_SIO0_SND].depth = 1; /* disable nested irq */ + set_irq_chip(PLD_IRQ_SIO0_SND, &opsput_pld_irq_type); pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_SND)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03; disable_opsput_pld_irq(PLD_IRQ_SIO0_SND); #endif /* CONFIG_SERIAL_M32R_PLDSIO */ /* INT#1: CFC IREQ on PLD */ - irq_desc[PLD_IRQ_CFIREQ].status = IRQ_DISABLED; - irq_desc[PLD_IRQ_CFIREQ].chip = &opsput_pld_irq_type; - irq_desc[PLD_IRQ_CFIREQ].action = 0; - irq_desc[PLD_IRQ_CFIREQ].depth = 1; /* disable nested irq */ + set_irq_chip(PLD_IRQ_CFIREQ, &opsput_pld_irq_type); pld_icu_data[irq2pldirq(PLD_IRQ_CFIREQ)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* 'L' level sense */ disable_opsput_pld_irq(PLD_IRQ_CFIREQ); /* INT#1: CFC Insert on PLD */ - irq_desc[PLD_IRQ_CFC_INSERT].status = IRQ_DISABLED; - irq_desc[PLD_IRQ_CFC_INSERT].chip = &opsput_pld_irq_type; - irq_desc[PLD_IRQ_CFC_INSERT].action = 0; - irq_desc[PLD_IRQ_CFC_INSERT].depth = 1; /* disable nested irq */ + set_irq_chip(PLD_IRQ_CFC_INSERT, &opsput_pld_irq_type); pld_icu_data[irq2pldirq(PLD_IRQ_CFC_INSERT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD00; /* 'L' edge sense */ disable_opsput_pld_irq(PLD_IRQ_CFC_INSERT); /* INT#1: CFC Eject on PLD */ - irq_desc[PLD_IRQ_CFC_EJECT].status = IRQ_DISABLED; - irq_desc[PLD_IRQ_CFC_EJECT].chip = &opsput_pld_irq_type; - irq_desc[PLD_IRQ_CFC_EJECT].action = 0; - irq_desc[PLD_IRQ_CFC_EJECT].depth = 1; /* disable nested irq */ + set_irq_chip(PLD_IRQ_CFC_EJECT, &opsput_pld_irq_type); pld_icu_data[irq2pldirq(PLD_IRQ_CFC_EJECT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* 'H' edge sense */ disable_opsput_pld_irq(PLD_IRQ_CFC_EJECT); @@ -415,10 +379,7 @@ void __init init_IRQ(void) #if defined(CONFIG_USB) outw(USBCR_OTGS, USBCR); /* USBCR: non-OTG */ - irq_desc[OPSPUT_LCD_IRQ_USB_INT1].status = IRQ_DISABLED; - irq_desc[OPSPUT_LCD_IRQ_USB_INT1].chip = &opsput_lcdpld_irq_type; - irq_desc[OPSPUT_LCD_IRQ_USB_INT1].action = 0; - irq_desc[OPSPUT_LCD_IRQ_USB_INT1].depth = 1; + set_irq_chip(OPSPUT_LCD_IRQ_USB_INT1, &opsput_lcdpld_irq_type); lcdpld_icu_data[irq2lcdpldirq(OPSPUT_LCD_IRQ_USB_INT1)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* "L" level sense */ disable_opsput_lcdpld_irq(OPSPUT_LCD_IRQ_USB_INT1); #endif @@ -433,10 +394,7 @@ void __init init_IRQ(void) /* * INT3# is used for AR */ - irq_desc[M32R_IRQ_INT3].status = IRQ_DISABLED; - irq_desc[M32R_IRQ_INT3].chip = &opsput_irq_type; - irq_desc[M32R_IRQ_INT3].action = 0; - irq_desc[M32R_IRQ_INT3].depth = 1; + set_irq_chip(M32R_IRQ_INT3, &opsput_irq_type); icu_data[M32R_IRQ_INT3].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; disable_opsput_irq(M32R_IRQ_INT3); #endif /* CONFIG_VIDEO_M32R_AR */ diff --git a/arch/m32r/platforms/usrv/setup.c b/arch/m32r/platforms/usrv/setup.c index 1beac7a..d6eb586 100644 --- a/arch/m32r/platforms/usrv/setup.c +++ b/arch/m32r/platforms/usrv/setup.c @@ -156,53 +156,35 @@ void __init init_IRQ(void) once++; /* MFT2 : system timer */ - irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED; - irq_desc[M32R_IRQ_MFT2].chip = &mappi_irq_type; - irq_desc[M32R_IRQ_MFT2].action = 0; - irq_desc[M32R_IRQ_MFT2].depth = 1; + set_irq_chip(M32R_IRQ_MFT2, &mappi_irq_type); icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; disable_mappi_irq(M32R_IRQ_MFT2); #if defined(CONFIG_SERIAL_M32R_SIO) /* SIO0_R : uart receive data */ - irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED; - irq_desc[M32R_IRQ_SIO0_R].chip = &mappi_irq_type; - irq_desc[M32R_IRQ_SIO0_R].action = 0; - irq_desc[M32R_IRQ_SIO0_R].depth = 1; + set_irq_chip(M32R_IRQ_SIO0_R, &mappi_irq_type); icu_data[M32R_IRQ_SIO0_R].icucr = 0; disable_mappi_irq(M32R_IRQ_SIO0_R); /* SIO0_S : uart send data */ - irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED; - irq_desc[M32R_IRQ_SIO0_S].chip = &mappi_irq_type; - irq_desc[M32R_IRQ_SIO0_S].action = 0; - irq_desc[M32R_IRQ_SIO0_S].depth = 1; + set_irq_chip(M32R_IRQ_SIO0_S, &mappi_irq_type); icu_data[M32R_IRQ_SIO0_S].icucr = 0; disable_mappi_irq(M32R_IRQ_SIO0_S); /* SIO1_R : uart receive data */ - irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED; - irq_desc[M32R_IRQ_SIO1_R].chip = &mappi_irq_type; - irq_desc[M32R_IRQ_SIO1_R].action = 0; - irq_desc[M32R_IRQ_SIO1_R].depth = 1; + set_irq_chip(M32R_IRQ_SIO1_R, &mappi_irq_type); icu_data[M32R_IRQ_SIO1_R].icucr = 0; disable_mappi_irq(M32R_IRQ_SIO1_R); /* SIO1_S : uart send data */ - irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED; - irq_desc[M32R_IRQ_SIO1_S].chip = &mappi_irq_type; - irq_desc[M32R_IRQ_SIO1_S].action = 0; - irq_desc[M32R_IRQ_SIO1_S].depth = 1; + set_irq_chip(M32R_IRQ_SIO1_S, &mappi_irq_type); icu_data[M32R_IRQ_SIO1_S].icucr = 0; disable_mappi_irq(M32R_IRQ_SIO1_S); #endif /* CONFIG_SERIAL_M32R_SIO */ /* INT#67-#71: CFC#0 IREQ on PLD */ for (i = 0 ; i < CONFIG_M32R_CFC_NUM ; i++ ) { - irq_desc[PLD_IRQ_CF0 + i].status = IRQ_DISABLED; - irq_desc[PLD_IRQ_CF0 + i].chip = &m32700ut_pld_irq_type; - irq_desc[PLD_IRQ_CF0 + i].action = 0; - irq_desc[PLD_IRQ_CF0 + i].depth = 1; /* disable nested irq */ + set_irq_chip(PLD_IRQ_CF0 + i, &m32700ut_pld_irq_type); pld_icu_data[irq2pldirq(PLD_IRQ_CF0 + i)].icucr = PLD_ICUCR_ISMOD01; /* 'L' level sense */ disable_m32700ut_pld_irq(PLD_IRQ_CF0 + i); @@ -210,19 +192,13 @@ void __init init_IRQ(void) #if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE) /* INT#76: 16552D#0 IREQ on PLD */ - irq_desc[PLD_IRQ_UART0].status = IRQ_DISABLED; - irq_desc[PLD_IRQ_UART0].chip = &m32700ut_pld_irq_type; - irq_desc[PLD_IRQ_UART0].action = 0; - irq_desc[PLD_IRQ_UART0].depth = 1; /* disable nested irq */ + set_irq_chip(PLD_IRQ_UART0, &m32700ut_pld_irq_type); pld_icu_data[irq2pldirq(PLD_IRQ_UART0)].icucr = PLD_ICUCR_ISMOD03; /* 'H' level sense */ disable_m32700ut_pld_irq(PLD_IRQ_UART0); /* INT#77: 16552D#1 IREQ on PLD */ - irq_desc[PLD_IRQ_UART1].status = IRQ_DISABLED; - irq_desc[PLD_IRQ_UART1].chip = &m32700ut_pld_irq_type; - irq_desc[PLD_IRQ_UART1].action = 0; - irq_desc[PLD_IRQ_UART1].depth = 1; /* disable nested irq */ + set_irq_chip(PLD_IRQ_UART1, &m32700ut_pld_irq_type); pld_icu_data[irq2pldirq(PLD_IRQ_UART1)].icucr = PLD_ICUCR_ISMOD03; /* 'H' level sense */ disable_m32700ut_pld_irq(PLD_IRQ_UART1); @@ -230,10 +206,7 @@ void __init init_IRQ(void) #if defined(CONFIG_IDC_AK4524) || defined(CONFIG_IDC_AK4524_MODULE) /* INT#80: AK4524 IREQ on PLD */ - irq_desc[PLD_IRQ_SNDINT].status = IRQ_DISABLED; - irq_desc[PLD_IRQ_SNDINT].chip = &m32700ut_pld_irq_type; - irq_desc[PLD_IRQ_SNDINT].action = 0; - irq_desc[PLD_IRQ_SNDINT].depth = 1; /* disable nested irq */ + set_irq_chip(PLD_IRQ_SNDINT, &m32700ut_pld_irq_type); pld_icu_data[irq2pldirq(PLD_IRQ_SNDINT)].icucr = PLD_ICUCR_ISMOD01; /* 'L' level sense */ disable_m32700ut_pld_irq(PLD_IRQ_SNDINT); -- cgit v0.10.2 From 8afb53b9ac0ac196d58b741d7bdfba8702ae7945 Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Wed, 19 Jan 2011 17:02:29 +0100 Subject: m32r: Convert m32104ut irq handling Convert the irq chips to the new functions and use proper flow handlers. handle_level_irq is appropriate. Signed-off-by: Thomas Gleixner Cc: Hirokazu Takata Cc: Paul Mundt diff --git a/arch/m32r/platforms/m32104ut/setup.c b/arch/m32r/platforms/m32104ut/setup.c index 962f38e..4a693d0 100644 --- a/arch/m32r/platforms/m32104ut/setup.c +++ b/arch/m32r/platforms/m32104ut/setup.c @@ -39,39 +39,30 @@ static void enable_m32104ut_irq(unsigned int irq) outl(data, port); } -static void mask_and_ack_m32104ut(unsigned int irq) +static void mask_m32104ut_irq(struct irq_data *data) { - disable_m32104ut_irq(irq); + disable_m32104ut_irq(data->irq); } -static void end_m32104ut_irq(unsigned int irq) +static void unmask_m32104ut_irq(struct irq_data *data) { - enable_m32104ut_irq(irq); + enable_m32104ut_irq(data->irq); } -static unsigned int startup_m32104ut_irq(unsigned int irq) +static void shutdown_m32104ut_irq(struct irq_data *data) { - enable_m32104ut_irq(irq); - return (0); -} - -static void shutdown_m32104ut_irq(unsigned int irq) -{ - unsigned long port; + unsigned int irq = data->irq; + unsigned long port = irq2port(irq); - port = irq2port(irq); outl(M32R_ICUCR_ILEVEL7, port); } static struct irq_chip m32104ut_irq_type = { - .name = "M32104UT-IRQ", - .startup = startup_m32104ut_irq, - .shutdown = shutdown_m32104ut_irq, - .enable = enable_m32104ut_irq, - .disable = disable_m32104ut_irq, - .ack = mask_and_ack_m32104ut, - .end = end_m32104ut_irq + .name = "M32104UT-IRQ", + .irq_shutdown = shutdown_m32104ut_irq, + .irq_unmask = unmask_m32104ut_irq, + .irq_mask = mask_m32104ut_irq, }; void __init init_IRQ(void) @@ -85,24 +76,29 @@ void __init init_IRQ(void) #if defined(CONFIG_SMC91X) /* INT#0: LAN controller on M32104UT-LAN (SMC91C111)*/ - set_irq_chip(M32R_IRQ_INT0, &m32104ut_irq_type); - icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN | M32R_ICUCR_ISMOD11; /* "H" level sense */ + set_irq_chip_and_handler(M32R_IRQ_INT0, &m32104ut_irq_type, + handle_level_irq); + /* "H" level sense */ + cu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN | M32R_ICUCR_ISMOD11; disable_m32104ut_irq(M32R_IRQ_INT0); #endif /* CONFIG_SMC91X */ /* MFT2 : system timer */ - set_irq_chip(M32R_IRQ_MFT2, &m32104ut_irq_type); + set_irq_chip_and_handler(M32R_IRQ_MFT2, &m32104ut_irq_type, + handle_level_irq); icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; disable_m32104ut_irq(M32R_IRQ_MFT2); #ifdef CONFIG_SERIAL_M32R_SIO /* SIO0_R : uart receive data */ - set_irq_chip(M32R_IRQ_SIO0_R, &m32104ut_irq_type); + set_irq_chip_and_handler(M32R_IRQ_SIO0_R, &m32104ut_irq_type, + handle_level_irq); icu_data[M32R_IRQ_SIO0_R].icucr = M32R_ICUCR_IEN; disable_m32104ut_irq(M32R_IRQ_SIO0_R); /* SIO0_S : uart send data */ - set_irq_chip(M32R_IRQ_SIO0_S, &m32104ut_irq_type); + set_irq_chip_and_handler(M32R_IRQ_SIO0_S, &m32104ut_irq_type, + handle_level_irq); icu_data[M32R_IRQ_SIO0_S].icucr = M32R_ICUCR_IEN; disable_m32104ut_irq(M32R_IRQ_SIO0_S); #endif /* CONFIG_SERIAL_M32R_SIO */ -- cgit v0.10.2 From 364a9ba07b0341c7e16809d810a19e06b6e64b05 Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Tue, 11 Jan 2011 10:43:49 +0100 Subject: m32r: Convert m32104ut irq chip Convert the irq chips to the new functions and use proper flow handlers. handle_level_irq is appropriate. Signed-off-by: Thomas Gleixner Cc: Hirokazu Takata Cc: Paul Mundt diff --git a/arch/m32r/platforms/m32700ut/setup.c b/arch/m32r/platforms/m32700ut/setup.c index 433bcbc..812cea9 100644 --- a/arch/m32r/platforms/m32700ut/setup.c +++ b/arch/m32r/platforms/m32700ut/setup.c @@ -45,39 +45,30 @@ static void enable_m32700ut_irq(unsigned int irq) outl(data, port); } -static void mask_and_ack_m32700ut(unsigned int irq) +static void mask_m32700ut(struct irq_data *data) { - disable_m32700ut_irq(irq); + disable_m32700ut_irq(data->irq); } -static void end_m32700ut_irq(unsigned int irq) +static void unmask_m32700ut(struct irq_data *data) { - enable_m32700ut_irq(irq); + enable_m32700ut_irq(data->irq); } -static unsigned int startup_m32700ut_irq(unsigned int irq) -{ - enable_m32700ut_irq(irq); - return (0); -} - -static void shutdown_m32700ut_irq(unsigned int irq) +static void shutdown_m32700ut(struct irq_data *data) { unsigned long port; - port = irq2port(irq); + port = irq2port(data->irq); outl(M32R_ICUCR_ILEVEL7, port); } static struct irq_chip m32700ut_irq_type = { - .name = "M32700UT-IRQ", - .startup = startup_m32700ut_irq, - .shutdown = shutdown_m32700ut_irq, - .enable = enable_m32700ut_irq, - .disable = disable_m32700ut_irq, - .ack = mask_and_ack_m32700ut, - .end = end_m32700ut_irq + .name = "M32700UT-IRQ", + .irq_shutdown = shutdown_m32700ut, + .irq_mask = mask_m32700ut, + .irq_unmask = unmask_m32700ut }; /* @@ -126,7 +117,7 @@ static void mask_and_ack_m32700ut_pld(unsigned int irq) static void end_m32700ut_pld_irq(unsigned int irq) { enable_m32700ut_pld_irq(irq); - end_m32700ut_irq(M32R_IRQ_INT1); + enable_m32700ut_irq(M32R_IRQ_INT1); } static unsigned int startup_m32700ut_pld_irq(unsigned int irq) @@ -196,7 +187,7 @@ static void mask_and_ack_m32700ut_lanpld(unsigned int irq) static void end_m32700ut_lanpld_irq(unsigned int irq) { enable_m32700ut_lanpld_irq(irq); - end_m32700ut_irq(M32R_IRQ_INT0); + enable_m32700ut_irq(M32R_IRQ_INT0); } static unsigned int startup_m32700ut_lanpld_irq(unsigned int irq) @@ -265,7 +256,7 @@ static void mask_and_ack_m32700ut_lcdpld(unsigned int irq) static void end_m32700ut_lcdpld_irq(unsigned int irq) { enable_m32700ut_lcdpld_irq(irq); - end_m32700ut_irq(M32R_IRQ_INT2); + enable_m32700ut_irq(M32R_IRQ_INT2); } static unsigned int startup_m32700ut_lcdpld_irq(unsigned int irq) @@ -305,32 +296,38 @@ void __init init_IRQ(void) #endif /* CONFIG_SMC91X */ /* MFT2 : system timer */ - set_irq_chip(M32R_IRQ_MFT2, &m32700ut_irq_type); + set_irq_chip_and_handler(M32R_IRQ_MFT2, &m32700ut_irq_type, + handle_level_irq); icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; disable_m32700ut_irq(M32R_IRQ_MFT2); /* SIO0 : receive */ - set_irq_chip(M32R_IRQ_SIO0_R, &m32700ut_irq_type); + set_irq_chip_and_handler(M32R_IRQ_SIO0_R, &m32700ut_irq_type, + handle_level_irq); icu_data[M32R_IRQ_SIO0_R].icucr = 0; disable_m32700ut_irq(M32R_IRQ_SIO0_R); /* SIO0 : send */ - set_irq_chip(M32R_IRQ_SIO0_S, &m32700ut_irq_type); + set_irq_chip_and_handler(M32R_IRQ_SIO0_S, &m32700ut_irq_type, + handle_level_irq); icu_data[M32R_IRQ_SIO0_S].icucr = 0; disable_m32700ut_irq(M32R_IRQ_SIO0_S); /* SIO1 : receive */ - set_irq_chip(M32R_IRQ_SIO1_R, &m32700ut_irq_type); + set_irq_chip_and_handler(M32R_IRQ_SIO1_R, &m32700ut_irq_type, + handle_level_irq); icu_data[M32R_IRQ_SIO1_R].icucr = 0; disable_m32700ut_irq(M32R_IRQ_SIO1_R); /* SIO1 : send */ - set_irq_chip(M32R_IRQ_SIO1_S, &m32700ut_irq_type); + set_irq_chip_and_handler(M32R_IRQ_SIO1_S, &m32700ut_irq_type, + handle_level_irq); icu_data[M32R_IRQ_SIO1_S].icucr = 0; disable_m32700ut_irq(M32R_IRQ_SIO1_S); /* DMA1 : */ - set_irq_chip(M32R_IRQ_DMA1, &m32700ut_irq_type); + set_irq_chip_and_handler(M32R_IRQ_DMA1, &m32700ut_irq_type, + handle_level_irq); icu_data[M32R_IRQ_DMA1].icucr = 0; disable_m32700ut_irq(M32R_IRQ_DMA1); @@ -393,7 +390,8 @@ void __init init_IRQ(void) /* * INT3# is used for AR */ - set_irq_chip(M32R_IRQ_INT3, &m32700ut_irq_type); + set_irq_chip_and_handler(M32R_IRQ_INT3, &m32700ut_irq_type, + handle_level_irq); icu_data[M32R_IRQ_INT3].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; disable_m32700ut_irq(M32R_IRQ_INT3); #endif /* CONFIG_VIDEO_M32R_AR */ -- cgit v0.10.2 From 63b549b6552c7869c25a1c60783aa86a3380e06c Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Wed, 19 Jan 2011 17:41:51 +0100 Subject: m32r: Convert m32700ut pld irq chip Convert the irq chips to the new functions and use proper flow handlers. handle_level_irq is appropriate. Signed-off-by: Thomas Gleixner Cc: Hirokazu Takata Cc: Paul Mundt diff --git a/arch/m32r/platforms/m32700ut/setup.c b/arch/m32r/platforms/m32700ut/setup.c index 812cea9..99d9241 100644 --- a/arch/m32r/platforms/m32700ut/setup.c +++ b/arch/m32r/platforms/m32700ut/setup.c @@ -90,7 +90,6 @@ static void disable_m32700ut_pld_irq(unsigned int irq) unsigned int pldirq; pldirq = irq2pldirq(irq); -// disable_m32700ut_irq(M32R_IRQ_INT1); port = pldirq2port(pldirq); data = pld_icu_data[pldirq].icucr|PLD_ICUCR_ILEVEL7; outw(data, port); @@ -102,50 +101,38 @@ static void enable_m32700ut_pld_irq(unsigned int irq) unsigned int pldirq; pldirq = irq2pldirq(irq); -// enable_m32700ut_irq(M32R_IRQ_INT1); port = pldirq2port(pldirq); data = pld_icu_data[pldirq].icucr|PLD_ICUCR_IEN|PLD_ICUCR_ILEVEL6; outw(data, port); } -static void mask_and_ack_m32700ut_pld(unsigned int irq) +static void mask_m32700ut_pld(struct irq_data *data) { - disable_m32700ut_pld_irq(irq); -// mask_and_ack_m32700ut(M32R_IRQ_INT1); + disable_m32700ut_pld_irq(data->irq); } -static void end_m32700ut_pld_irq(unsigned int irq) +static void unmask_m32700ut_pld(struct irq_data *data) { - enable_m32700ut_pld_irq(irq); + enable_m32700ut_pld_irq(data->irq); enable_m32700ut_irq(M32R_IRQ_INT1); } -static unsigned int startup_m32700ut_pld_irq(unsigned int irq) -{ - enable_m32700ut_pld_irq(irq); - return (0); -} - -static void shutdown_m32700ut_pld_irq(unsigned int irq) +static void shutdown_m32700ut_pld_irq(struct irq_data *data) { unsigned long port; unsigned int pldirq; - pldirq = irq2pldirq(irq); -// shutdown_m32700ut_irq(M32R_IRQ_INT1); + pldirq = irq2pldirq(data->irq); port = pldirq2port(pldirq); outw(PLD_ICUCR_ILEVEL7, port); } static struct irq_chip m32700ut_pld_irq_type = { - .name = "M32700UT-PLD-IRQ", - .startup = startup_m32700ut_pld_irq, - .shutdown = shutdown_m32700ut_pld_irq, - .enable = enable_m32700ut_pld_irq, - .disable = disable_m32700ut_pld_irq, - .ack = mask_and_ack_m32700ut_pld, - .end = end_m32700ut_pld_irq + .name = "M32700UT-PLD-IRQ", + .irq_shutdown = shutdown_m32700ut_pld_irq, + .irq_mask = mask_m32700ut_pld, + .irq_unmask = unmask_m32700ut_pld, }; /* @@ -333,28 +320,33 @@ void __init init_IRQ(void) #ifdef CONFIG_SERIAL_M32R_PLDSIO /* INT#1: SIO0 Receive on PLD */ - set_irq_chip(PLD_IRQ_SIO0_RCV, &m32700ut_pld_irq_type); + set_irq_chip_and_handler(PLD_IRQ_SIO0_RCV, &m32700ut_pld_irq_type, + handle_level_irq); pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_RCV)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03; disable_m32700ut_pld_irq(PLD_IRQ_SIO0_RCV); /* INT#1: SIO0 Send on PLD */ - set_irq_chip(PLD_IRQ_SIO0_SND, &m32700ut_pld_irq_type); + set_irq_chip_and_handler(PLD_IRQ_SIO0_SND, &m32700ut_pld_irq_type, + handle_level_irq); pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_SND)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03; disable_m32700ut_pld_irq(PLD_IRQ_SIO0_SND); #endif /* CONFIG_SERIAL_M32R_PLDSIO */ /* INT#1: CFC IREQ on PLD */ - set_irq_chip(PLD_IRQ_CFIREQ, &m32700ut_pld_irq_type); + set_irq_chip_and_handler(PLD_IRQ_CFIREQ, &m32700ut_pld_irq_type, + handle_level_irq); pld_icu_data[irq2pldirq(PLD_IRQ_CFIREQ)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* 'L' level sense */ disable_m32700ut_pld_irq(PLD_IRQ_CFIREQ); /* INT#1: CFC Insert on PLD */ - set_irq_chip(PLD_IRQ_CFC_INSERT, &m32700ut_pld_irq_type); + set_irq_chip_and_handler(PLD_IRQ_CFC_INSERT, &m32700ut_pld_irq_type, + handle_level_irq); pld_icu_data[irq2pldirq(PLD_IRQ_CFC_INSERT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD00; /* 'L' edge sense */ disable_m32700ut_pld_irq(PLD_IRQ_CFC_INSERT); /* INT#1: CFC Eject on PLD */ - set_irq_chip(PLD_IRQ_CFC_EJECT, &m32700ut_pld_irq_type); + set_irq_chip_and_handler(PLD_IRQ_CFC_EJECT, &m32700ut_pld_irq_type, + handle_level_irq); pld_icu_data[irq2pldirq(PLD_IRQ_CFC_EJECT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* 'H' edge sense */ disable_m32700ut_pld_irq(PLD_IRQ_CFC_EJECT); -- cgit v0.10.2 From 72bd198f1d8e3341ea55dc250830a92e2816d16a Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Wed, 19 Jan 2011 18:14:21 +0100 Subject: m32r: Convert m32700ut lanpld irq chip Convert the irq chips to the new functions and use proper flow handlers. handle_level_irq is appropriate. Signed-off-by: Thomas Gleixner Cc: Hirokazu Takata Cc: Paul Mundt diff --git a/arch/m32r/platforms/m32700ut/setup.c b/arch/m32r/platforms/m32700ut/setup.c index 99d9241..bce70e1 100644 --- a/arch/m32r/platforms/m32700ut/setup.c +++ b/arch/m32r/platforms/m32700ut/setup.c @@ -166,42 +166,33 @@ static void enable_m32700ut_lanpld_irq(unsigned int irq) outw(data, port); } -static void mask_and_ack_m32700ut_lanpld(unsigned int irq) +static void mask_m32700ut_lanpld(struct irq_data *data) { - disable_m32700ut_lanpld_irq(irq); + disable_m32700ut_lanpld_irq(data->irq); } -static void end_m32700ut_lanpld_irq(unsigned int irq) +static void unmask_m32700ut_lanpld(struct irq_data *data) { - enable_m32700ut_lanpld_irq(irq); + enable_m32700ut_lanpld_irq(data->irq); enable_m32700ut_irq(M32R_IRQ_INT0); } -static unsigned int startup_m32700ut_lanpld_irq(unsigned int irq) -{ - enable_m32700ut_lanpld_irq(irq); - return (0); -} - -static void shutdown_m32700ut_lanpld_irq(unsigned int irq) +static void shutdown_m32700ut_lanpld(struct irq_data *data) { unsigned long port; unsigned int pldirq; - pldirq = irq2lanpldirq(irq); + pldirq = irq2lanpldirq(data->irq); port = lanpldirq2port(pldirq); outw(PLD_ICUCR_ILEVEL7, port); } static struct irq_chip m32700ut_lanpld_irq_type = { - .name = "M32700UT-PLD-LAN-IRQ", - .startup = startup_m32700ut_lanpld_irq, - .shutdown = shutdown_m32700ut_lanpld_irq, - .enable = enable_m32700ut_lanpld_irq, - .disable = disable_m32700ut_lanpld_irq, - .ack = mask_and_ack_m32700ut_lanpld, - .end = end_m32700ut_lanpld_irq + .name = "M32700UT-PLD-LAN-IRQ", + .irq_shutdown = shutdown_m32700ut_lanpld, + .irq_mask = mask_m32700ut_lanpld, + .irq_unmask = unmask_m32700ut_lanpld, }; /* @@ -277,7 +268,8 @@ void __init init_IRQ(void) { #if defined(CONFIG_SMC91X) /* INT#0: LAN controller on M32700UT-LAN (SMC91C111)*/ - set_irq_chip(M32700UT_LAN_IRQ_LAN, &m32700ut_lanpld_irq_type); + set_irq_chip_and_handler(M32700UT_LAN_IRQ_LAN, + &m32700ut_lanpld_irq_type, handle_level_irq); lanpld_icu_data[irq2lanpldirq(M32700UT_LAN_IRQ_LAN)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* "H" edge sense */ disable_m32700ut_lanpld_irq(M32700UT_LAN_IRQ_LAN); #endif /* CONFIG_SMC91X */ -- cgit v0.10.2 From 37808e47eab064006eb17d46cf15a098655940c4 Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Wed, 19 Jan 2011 18:19:42 +0100 Subject: m32r: Convert m32700ut lcdpld irq chip Convert the irq chip to the new functions and use proper flow handlers. handle_level_irq is appropriate. Signed-off-by: Thomas Gleixner Cc: Hirokazu Takata Cc: Paul Mundt diff --git a/arch/m32r/platforms/m32700ut/setup.c b/arch/m32r/platforms/m32700ut/setup.c index bce70e1..2074bcc 100644 --- a/arch/m32r/platforms/m32700ut/setup.c +++ b/arch/m32r/platforms/m32700ut/setup.c @@ -226,42 +226,33 @@ static void enable_m32700ut_lcdpld_irq(unsigned int irq) outw(data, port); } -static void mask_and_ack_m32700ut_lcdpld(unsigned int irq) +static void mask_m32700ut_lcdpld(struct irq_data *data) { - disable_m32700ut_lcdpld_irq(irq); + disable_m32700ut_lcdpld_irq(data->irq); } -static void end_m32700ut_lcdpld_irq(unsigned int irq) +static void unmask_m32700ut_lcdpld(struct irq_data *data) { - enable_m32700ut_lcdpld_irq(irq); + enable_m32700ut_lcdpld_irq(data->irq); enable_m32700ut_irq(M32R_IRQ_INT2); } -static unsigned int startup_m32700ut_lcdpld_irq(unsigned int irq) -{ - enable_m32700ut_lcdpld_irq(irq); - return (0); -} - -static void shutdown_m32700ut_lcdpld_irq(unsigned int irq) +static void shutdown_m32700ut_lcdpld(struct irq_data *data) { unsigned long port; unsigned int pldirq; - pldirq = irq2lcdpldirq(irq); + pldirq = irq2lcdpldirq(data->irq); port = lcdpldirq2port(pldirq); outw(PLD_ICUCR_ILEVEL7, port); } static struct irq_chip m32700ut_lcdpld_irq_type = { - .name = "M32700UT-PLD-LCD-IRQ", - .startup = startup_m32700ut_lcdpld_irq, - .shutdown = shutdown_m32700ut_lcdpld_irq, - .enable = enable_m32700ut_lcdpld_irq, - .disable = disable_m32700ut_lcdpld_irq, - .ack = mask_and_ack_m32700ut_lcdpld, - .end = end_m32700ut_lcdpld_irq + .name = "M32700UT-PLD-LCD-IRQ", + .irq_shutdown = shutdown_m32700ut_lcdpld, + .irq_mask = mask_m32700ut_lcdpld, + .irq_unmask = unmask_m32700ut_lcdpld, }; void __init init_IRQ(void) @@ -358,7 +349,8 @@ void __init init_IRQ(void) #if defined(CONFIG_USB) outw(USBCR_OTGS, USBCR); /* USBCR: non-OTG */ - set_irq_chip(M32700UT_LCD_IRQ_USB_INT1, &m32700ut_lcdpld_irq_type); + set_irq_chip_and_handler(M32700UT_LCD_IRQ_USB_INT1, + &m32700ut_lcdpld_irq_type, handle_level_irq); lcdpld_icu_data[irq2lcdpldirq(M32700UT_LCD_IRQ_USB_INT1)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* "L" level sense */ disable_m32700ut_lcdpld_irq(M32700UT_LCD_IRQ_USB_INT1); -- cgit v0.10.2 From 1f12681ab1419a68da0f066b95e3e6e9270eb730 Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Wed, 19 Jan 2011 18:27:59 +0100 Subject: m32r: Convert mappi irq chips Convert the irq chips to the new functions and use proper flow handlers. handle_level_irq is appropriate. Signed-off-by: Thomas Gleixner Cc: Hirokazu Takata Cc: Paul Mundt diff --git a/arch/m32r/platforms/mappi/setup.c b/arch/m32r/platforms/mappi/setup.c index bc3fdaf..cdd8c45 100644 --- a/arch/m32r/platforms/mappi/setup.c +++ b/arch/m32r/platforms/mappi/setup.c @@ -38,39 +38,30 @@ static void enable_mappi_irq(unsigned int irq) outl(data, port); } -static void mask_and_ack_mappi(unsigned int irq) +static void mask_mappi(struct irq_data *data) { - disable_mappi_irq(irq); + disable_mappi_irq(data->irq); } -static void end_mappi_irq(unsigned int irq) +static void unmask_mappi(struct irq_data *data) { - enable_mappi_irq(irq); + enable_mappi_irq(data->irq); } -static unsigned int startup_mappi_irq(unsigned int irq) -{ - enable_mappi_irq(irq); - return (0); -} - -static void shutdown_mappi_irq(unsigned int irq) +static void shutdown_mappi(struct irq_data *data) { unsigned long port; - port = irq2port(irq); + port = irq2port(data->irq); outl(M32R_ICUCR_ILEVEL7, port); } static struct irq_chip mappi_irq_type = { - .name = "MAPPI-IRQ", - .startup = startup_mappi_irq, - .shutdown = shutdown_mappi_irq, - .enable = enable_mappi_irq, - .disable = disable_mappi_irq, - .ack = mask_and_ack_mappi, - .end = end_mappi_irq + .name = "MAPPI-IRQ", + .irq_shutdown = shutdown_mappi, + .irq_mask = mask_mappi, + .irq_unmask = unmask_mappi, }; void __init init_IRQ(void) @@ -84,46 +75,54 @@ void __init init_IRQ(void) #ifdef CONFIG_NE2000 /* INT0 : LAN controller (RTL8019AS) */ - set_irq_chip(M32R_IRQ_INT0, &mappi_irq_type); + set_irq_chip_and_handler(M32R_IRQ_INT0, &mappi_irq_type, + handle_level_irq); icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD11; disable_mappi_irq(M32R_IRQ_INT0); #endif /* CONFIG_M32R_NE2000 */ /* MFT2 : system timer */ - set_irq_chip(M32R_IRQ_MFT2, &mappi_irq_type); + set_irq_chip_and_handler(M32R_IRQ_MFT2, &mappi_irq_type, + handle_level_irq); icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; disable_mappi_irq(M32R_IRQ_MFT2); #ifdef CONFIG_SERIAL_M32R_SIO /* SIO0_R : uart receive data */ - set_irq_chip(M32R_IRQ_SIO0_R, &mappi_irq_type); + set_irq_chip_and_handler(M32R_IRQ_SIO0_R, &mappi_irq_type, + handle_level_irq); icu_data[M32R_IRQ_SIO0_R].icucr = 0; disable_mappi_irq(M32R_IRQ_SIO0_R); /* SIO0_S : uart send data */ - set_irq_chip(M32R_IRQ_SIO0_S, &mappi_irq_type); + set_irq_chip_and_handler(M32R_IRQ_SIO0_S, &mappi_irq_type, + handle_level_irq); icu_data[M32R_IRQ_SIO0_S].icucr = 0; disable_mappi_irq(M32R_IRQ_SIO0_S); /* SIO1_R : uart receive data */ - set_irq_chip(M32R_IRQ_SIO1_R, &mappi_irq_type); + set_irq_chip_and_handler(M32R_IRQ_SIO1_R, &mappi_irq_type, + handle_level_irq); icu_data[M32R_IRQ_SIO1_R].icucr = 0; disable_mappi_irq(M32R_IRQ_SIO1_R); /* SIO1_S : uart send data */ - set_irq_chip(M32R_IRQ_SIO1_S, &mappi_irq_type); + set_irq_chip_and_handler(M32R_IRQ_SIO1_S, &mappi_irq_type, + handle_level_irq); icu_data[M32R_IRQ_SIO1_S].icucr = 0; disable_mappi_irq(M32R_IRQ_SIO1_S); #endif /* CONFIG_SERIAL_M32R_SIO */ #if defined(CONFIG_M32R_PCC) /* INT1 : pccard0 interrupt */ - set_irq_chip(M32R_IRQ_INT1, &mappi_irq_type); + set_irq_chip_and_handler(M32R_IRQ_INT1, &mappi_irq_type, + handle_level_irq); icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_IEN | M32R_ICUCR_ISMOD00; disable_mappi_irq(M32R_IRQ_INT1); /* INT2 : pccard1 interrupt */ - set_irq_chip(M32R_IRQ_INT2, &mappi_irq_type); + set_irq_chip_and_handler(M32R_IRQ_INT2, &mappi_irq_type, + handle_level_irq); icu_data[M32R_IRQ_INT2].icucr = M32R_ICUCR_IEN | M32R_ICUCR_ISMOD00; disable_mappi_irq(M32R_IRQ_INT2); #endif /* CONFIG_M32RPCC */ -- cgit v0.10.2 From efa63c6495fb6f83a1cc183f0df2617e383392e9 Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Wed, 19 Jan 2011 18:34:51 +0100 Subject: m32r: Convert mappi2 irq chip Convert the irq chips to the new functions and use proper flow handlers. handle_level_irq is appropriate. Signed-off-by: Thomas Gleixner Cc: Hirokazu Takata Cc: Paul Mundt diff --git a/arch/m32r/platforms/mappi2/setup.c b/arch/m32r/platforms/mappi2/setup.c index 87bba1e..9117c30 100644 --- a/arch/m32r/platforms/mappi2/setup.c +++ b/arch/m32r/platforms/mappi2/setup.c @@ -46,96 +46,97 @@ static void enable_mappi2_irq(unsigned int irq) outl(data, port); } -static void mask_and_ack_mappi2(unsigned int irq) +static void mask_mappi2(struct irq_data *data) { - disable_mappi2_irq(irq); + disable_mappi2_irq(data->irq); } -static void end_mappi2_irq(unsigned int irq) +static void unmask_mappi2(struct irq_data *data) { - enable_mappi2_irq(irq); + enable_mappi2_irq(data->irq); } -static unsigned int startup_mappi2_irq(unsigned int irq) -{ - enable_mappi2_irq(irq); - return (0); -} - -static void shutdown_mappi2_irq(unsigned int irq) +static void shutdown_mappi2(struct irq_data *data) { unsigned long port; - port = irq2port(irq); + port = irq2port(data->irq); outl(M32R_ICUCR_ILEVEL7, port); } static struct irq_chip mappi2_irq_type = { - .name = "MAPPI2-IRQ", - .startup = startup_mappi2_irq, - .shutdown = shutdown_mappi2_irq, - .enable = enable_mappi2_irq, - .disable = disable_mappi2_irq, - .ack = mask_and_ack_mappi2, - .end = end_mappi2_irq + .name = "MAPPI2-IRQ", + .irq_shutdown = shutdown_mappi2, + .irq_mask = mask_mappi2, + .irq_unmask = unmask_mappi2, }; void __init init_IRQ(void) { #if defined(CONFIG_SMC91X) /* INT0 : LAN controller (SMC91111) */ - set_irq_chip(M32R_IRQ_INT0, &mappi2_irq_type); + set_irq_chip_and_handler(M32R_IRQ_INT0, &mappi2_irq_type, + handle_level_irq); icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; disable_mappi2_irq(M32R_IRQ_INT0); #endif /* CONFIG_SMC91X */ /* MFT2 : system timer */ - set_irq_chip(M32R_IRQ_MFT2, &mappi2_irq_type); + set_irq_chip_and_handler(M32R_IRQ_MFT2, &mappi2_irq_type, + handle_level_irq); icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; disable_mappi2_irq(M32R_IRQ_MFT2); #ifdef CONFIG_SERIAL_M32R_SIO /* SIO0_R : uart receive data */ - set_irq_chip(M32R_IRQ_SIO0_R, &mappi2_irq_type); + set_irq_chip_and_handler(M32R_IRQ_SIO0_R, &mappi2_irq_type, + handle_level_irq); icu_data[M32R_IRQ_SIO0_R].icucr = 0; disable_mappi2_irq(M32R_IRQ_SIO0_R); /* SIO0_S : uart send data */ - set_irq_chip(M32R_IRQ_SIO0_S, &mappi2_irq_type); + set_irq_chip_and_handler(M32R_IRQ_SIO0_S, &mappi2_irq_type, + handle_level_irq); icu_data[M32R_IRQ_SIO0_S].icucr = 0; disable_mappi2_irq(M32R_IRQ_SIO0_S); /* SIO1_R : uart receive data */ - set_irq_chip(M32R_IRQ_SIO1_R, &mappi2_irq_type); + set_irq_chip_and_handler(M32R_IRQ_SIO1_R, &mappi2_irq_type, + handle_level_irq); icu_data[M32R_IRQ_SIO1_R].icucr = 0; disable_mappi2_irq(M32R_IRQ_SIO1_R); /* SIO1_S : uart send data */ - set_irq_chip(M32R_IRQ_SIO1_S, &mappi2_irq_type); + set_irq_chip_and_handler(M32R_IRQ_SIO1_S, &mappi2_irq_type, + handle_level_irq); icu_data[M32R_IRQ_SIO1_S].icucr = 0; disable_mappi2_irq(M32R_IRQ_SIO1_S); #endif /* CONFIG_M32R_USE_DBG_CONSOLE */ #if defined(CONFIG_USB) /* INT1 : USB Host controller interrupt */ - set_irq_chip(M32R_IRQ_INT1, &mappi2_irq_type); + set_irq_chip_and_handler(M32R_IRQ_INT1, &mappi2_irq_type, + handle_level_irq); icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_ISMOD01; disable_mappi2_irq(M32R_IRQ_INT1); #endif /* CONFIG_USB */ /* ICUCR40: CFC IREQ */ - set_irq_chip(PLD_IRQ_CFIREQ, &mappi2_irq_type); + set_irq_chip_and_handler(PLD_IRQ_CFIREQ, &mappi2_irq_type, + handle_level_irq); icu_data[PLD_IRQ_CFIREQ].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD01; disable_mappi2_irq(PLD_IRQ_CFIREQ); #if defined(CONFIG_M32R_CFC) /* ICUCR41: CFC Insert */ - set_irq_chip(PLD_IRQ_CFC_INSERT, &mappi2_irq_type); + set_irq_chip_and_handler(PLD_IRQ_CFC_INSERT, &mappi2_irq_type, + handle_level_irq); icu_data[PLD_IRQ_CFC_INSERT].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD00; disable_mappi2_irq(PLD_IRQ_CFC_INSERT); /* ICUCR42: CFC Eject */ - set_irq_chip(PLD_IRQ_CFC_EJECT, &mappi2_irq_type); + set_irq_chip_and_handler(PLD_IRQ_CFC_EJECT, &mappi2_irq_type, + handle_level_irq); icu_data[PLD_IRQ_CFC_EJECT].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; disable_mappi2_irq(PLD_IRQ_CFC_EJECT); #endif /* CONFIG_MAPPI2_CFC */ -- cgit v0.10.2 From b82727ec646578bdd3a6f31f6451f67784874675 Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Wed, 19 Jan 2011 18:39:27 +0100 Subject: m32r: Convert mappi3 irq chip Convert the irq chips to the new functions and use proper flow handlers. handle_level_irq is appropriate. Signed-off-by: Thomas Gleixner Cc: Hirokazu Takata Cc: Paul Mundt diff --git a/arch/m32r/platforms/mappi3/setup.c b/arch/m32r/platforms/mappi3/setup.c index 7409814..b44f5de 100644 --- a/arch/m32r/platforms/mappi3/setup.c +++ b/arch/m32r/platforms/mappi3/setup.c @@ -46,98 +46,98 @@ static void enable_mappi3_irq(unsigned int irq) outl(data, port); } -static void mask_and_ack_mappi3(unsigned int irq) +static void mask_mappi3(struct irq_data *data) { - disable_mappi3_irq(irq); + disable_mappi3_irq(data->irq); } -static void end_mappi3_irq(unsigned int irq) +static void unmask_mappi3(struct irq_data *data) { - enable_mappi3_irq(irq); + enable_mappi3_irq(data->irq); } -static unsigned int startup_mappi3_irq(unsigned int irq) -{ - enable_mappi3_irq(irq); - return (0); -} - -static void shutdown_mappi3_irq(unsigned int irq) +static void shutdown_mappi3(struct irq_data *data) { unsigned long port; - port = irq2port(irq); + port = irq2port(data->irq); outl(M32R_ICUCR_ILEVEL7, port); } -static struct irq_chip mappi3_irq_type = -{ - .name = "MAPPI3-IRQ", - .startup = startup_mappi3_irq, - .shutdown = shutdown_mappi3_irq, - .enable = enable_mappi3_irq, - .disable = disable_mappi3_irq, - .ack = mask_and_ack_mappi3, - .end = end_mappi3_irq +static struct irq_chip mappi3_irq_type = { + .name = "MAPPI3-IRQ", + .irq_shutdown = shutdown_mappi3, + .irq_mask = mask_mappi3, + .irq_unmask = unmask_mappi3, }; void __init init_IRQ(void) { #if defined(CONFIG_SMC91X) /* INT0 : LAN controller (SMC91111) */ - set_irq_chip(M32R_IRQ_INT0, &mappi3_irq_type); + set_irq_chip_and_handler(M32R_IRQ_INT0, &mappi3_irq_type, + handle_level_irq); icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; disable_mappi3_irq(M32R_IRQ_INT0); #endif /* CONFIG_SMC91X */ /* MFT2 : system timer */ - set_irq_chip(M32R_IRQ_MFT2, &mappi3_irq_type); + set_irq_chip_and_handler(M32R_IRQ_MFT2, &mappi3_irq_type, + handle_level_irq); icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; disable_mappi3_irq(M32R_IRQ_MFT2); #ifdef CONFIG_SERIAL_M32R_SIO /* SIO0_R : uart receive data */ - set_irq_chip(M32R_IRQ_SIO0_R, &mappi3_irq_type); + set_irq_chip_and_handler(M32R_IRQ_SIO0_R, &mappi3_irq_type, + handle_level_irq); icu_data[M32R_IRQ_SIO0_R].icucr = 0; disable_mappi3_irq(M32R_IRQ_SIO0_R); /* SIO0_S : uart send data */ - set_irq_chip(M32R_IRQ_SIO0_S, &mappi3_irq_type); + set_irq_chip_and_handler(M32R_IRQ_SIO0_S, &mappi3_irq_type, + handle_level_irq); icu_data[M32R_IRQ_SIO0_S].icucr = 0; disable_mappi3_irq(M32R_IRQ_SIO0_S); /* SIO1_R : uart receive data */ - set_irq_chip(M32R_IRQ_SIO1_R, &mappi3_irq_type); + set_irq_chip_and_handler(M32R_IRQ_SIO1_R, &mappi3_irq_type, + handle_level_irq); icu_data[M32R_IRQ_SIO1_R].icucr = 0; disable_mappi3_irq(M32R_IRQ_SIO1_R); /* SIO1_S : uart send data */ - set_irq_chip(M32R_IRQ_SIO1_S, &mappi3_irq_type); + set_irq_chip_and_handler(M32R_IRQ_SIO1_S, &mappi3_irq_type, + handle_level_irq); icu_data[M32R_IRQ_SIO1_S].icucr = 0; disable_mappi3_irq(M32R_IRQ_SIO1_S); #endif /* CONFIG_M32R_USE_DBG_CONSOLE */ #if defined(CONFIG_USB) /* INT1 : USB Host controller interrupt */ - set_irq_chip(M32R_IRQ_INT1, &mappi3_irq_type); + set_irq_chip_and_handler(M32R_IRQ_INT1, &mappi3_irq_type, + handle_level_irq); icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_ISMOD01; disable_mappi3_irq(M32R_IRQ_INT1); #endif /* CONFIG_USB */ /* CFC IREQ */ - set_irq_chip(PLD_IRQ_CFIREQ, &mappi3_irq_type); + set_irq_chip_and_handler(PLD_IRQ_CFIREQ, &mappi3_irq_type, + handle_level_irq); icu_data[PLD_IRQ_CFIREQ].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD01; disable_mappi3_irq(PLD_IRQ_CFIREQ); #if defined(CONFIG_M32R_CFC) /* ICUCR41: CFC Insert & eject */ - set_irq_chip(PLD_IRQ_CFC_INSERT, &mappi3_irq_type); + set_irq_chip_and_handler(PLD_IRQ_CFC_INSERT, &mappi3_irq_type, + handle_level_irq); icu_data[PLD_IRQ_CFC_INSERT].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD00; disable_mappi3_irq(PLD_IRQ_CFC_INSERT); #endif /* CONFIG_M32R_CFC */ /* IDE IREQ */ - set_irq_chip(PLD_IRQ_IDEIREQ, &mappi3_irq_type); + set_irq_chip_and_handler(PLD_IRQ_IDEIREQ, &mappi3_irq_type, + handle_level_irq); icu_data[PLD_IRQ_IDEIREQ].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; disable_mappi3_irq(PLD_IRQ_IDEIREQ); -- cgit v0.10.2 From ce1104ce67ea186bf5c23de66a2eeaf65823e1ce Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Wed, 19 Jan 2011 18:44:10 +0100 Subject: m32r: Convert oaks32r irq chips Convert the irq chips to the new functions and use proper flow handlers. handle_level_irq is appropriate. Signed-off-by: Thomas Gleixner Cc: Hirokazu Takata Cc: Paul Mundt diff --git a/arch/m32r/platforms/oaks32r/setup.c b/arch/m32r/platforms/oaks32r/setup.c index 43bf5a0..19a02db 100644 --- a/arch/m32r/platforms/oaks32r/setup.c +++ b/arch/m32r/platforms/oaks32r/setup.c @@ -37,39 +37,30 @@ static void enable_oaks32r_irq(unsigned int irq) outl(data, port); } -static void mask_and_ack_mappi(unsigned int irq) +static void mask_oaks32r(struct irq_data *data) { - disable_oaks32r_irq(irq); + disable_oaks32r_irq(data->irq); } -static void end_oaks32r_irq(unsigned int irq) +static void unmask_oaks32r(struct irq_data *data) { - enable_oaks32r_irq(irq); + enable_oaks32r_irq(data->irq); } -static unsigned int startup_oaks32r_irq(unsigned int irq) -{ - enable_oaks32r_irq(irq); - return (0); -} - -static void shutdown_oaks32r_irq(unsigned int irq) +static void shutdown_oaks32r(struct irq_data *data) { unsigned long port; - port = irq2port(irq); + port = irq2port(data->irq); outl(M32R_ICUCR_ILEVEL7, port); } static struct irq_chip oaks32r_irq_type = { - .name = "OAKS32R-IRQ", - .startup = startup_oaks32r_irq, - .shutdown = shutdown_oaks32r_irq, - .enable = enable_oaks32r_irq, - .disable = disable_oaks32r_irq, - .ack = mask_and_ack_mappi, - .end = end_oaks32r_irq + .name = "OAKS32R-IRQ", + .irq_shutdown = shutdown_oaks32r, + .irq_mask = mask_oaks32r, + .irq_unmask = unmask_oaks32r, }; void __init init_IRQ(void) @@ -83,34 +74,40 @@ void __init init_IRQ(void) #ifdef CONFIG_NE2000 /* INT3 : LAN controller (RTL8019AS) */ - set_irq_chip(M32R_IRQ_INT3, &oaks32r_irq_type); + set_irq_chip_and_handler(M32R_IRQ_INT3, &oaks32r_irq_type, + handle_level_irq); icu_data[M32R_IRQ_INT3].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; disable_oaks32r_irq(M32R_IRQ_INT3); #endif /* CONFIG_M32R_NE2000 */ /* MFT2 : system timer */ - set_irq_chip(M32R_IRQ_MFT2, &oaks32r_irq_type); + set_irq_chip_and_handler(M32R_IRQ_MFT2, &oaks32r_irq_type, + handle_level_irq); icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; disable_oaks32r_irq(M32R_IRQ_MFT2); #ifdef CONFIG_SERIAL_M32R_SIO /* SIO0_R : uart receive data */ - set_irq_chip(M32R_IRQ_SIO0_R, &oaks32r_irq_type); + set_irq_chip_and_handler(M32R_IRQ_SIO0_R, &oaks32r_irq_type, + handle_level_irq); icu_data[M32R_IRQ_SIO0_R].icucr = 0; disable_oaks32r_irq(M32R_IRQ_SIO0_R); /* SIO0_S : uart send data */ - set_irq_chip(M32R_IRQ_SIO0_S, &oaks32r_irq_type); + set_irq_chip_and_handler(M32R_IRQ_SIO0_S, &oaks32r_irq_type, + handle_level_irq); icu_data[M32R_IRQ_SIO0_S].icucr = 0; disable_oaks32r_irq(M32R_IRQ_SIO0_S); /* SIO1_R : uart receive data */ - set_irq_chip(M32R_IRQ_SIO1_R, &oaks32r_irq_type); + set_irq_chip_and_handler(M32R_IRQ_SIO1_R, &oaks32r_irq_type, + handle_level_irq); icu_data[M32R_IRQ_SIO1_R].icucr = 0; disable_oaks32r_irq(M32R_IRQ_SIO1_R); /* SIO1_S : uart send data */ - set_irq_chip(M32R_IRQ_SIO1_S, &oaks32r_irq_type); + set_irq_chip_and_handler(M32R_IRQ_SIO1_S, &oaks32r_irq_type, + handle_level_irq); icu_data[M32R_IRQ_SIO1_S].icucr = 0; disable_oaks32r_irq(M32R_IRQ_SIO1_S); #endif /* CONFIG_SERIAL_M32R_SIO */ -- cgit v0.10.2 From 883c0ccde1e12e7721966626983d61ccdbd0ae99 Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Wed, 19 Jan 2011 18:48:15 +0100 Subject: m32r: Convert opsput irq chip Convert the irq chips to the new functions and use proper flow handlers. handle_level_irq is appropriate. Signed-off-by: Thomas Gleixner Cc: Hirokazu Takata Cc: Paul Mundt diff --git a/arch/m32r/platforms/opsput/setup.c b/arch/m32r/platforms/opsput/setup.c index a16a7fe..8c0907d 100644 --- a/arch/m32r/platforms/opsput/setup.c +++ b/arch/m32r/platforms/opsput/setup.c @@ -46,39 +46,30 @@ static void enable_opsput_irq(unsigned int irq) outl(data, port); } -static void mask_and_ack_opsput(unsigned int irq) +static void mask_opsput(struct irq_data *data) { - disable_opsput_irq(irq); + disable_opsput_irq(data->irq); } -static void end_opsput_irq(unsigned int irq) +static void unmask_opsput(struct irq_data *data) { - enable_opsput_irq(irq); + enable_opsput_irq(data->irq); } -static unsigned int startup_opsput_irq(unsigned int irq) -{ - enable_opsput_irq(irq); - return (0); -} - -static void shutdown_opsput_irq(unsigned int irq) +static void shutdown_opsput(struct irq_data *data) { unsigned long port; - port = irq2port(irq); + port = irq2port(data->irq); outl(M32R_ICUCR_ILEVEL7, port); } static struct irq_chip opsput_irq_type = { - .name = "OPSPUT-IRQ", - .startup = startup_opsput_irq, - .shutdown = shutdown_opsput_irq, - .enable = enable_opsput_irq, - .disable = disable_opsput_irq, - .ack = mask_and_ack_opsput, - .end = end_opsput_irq + .name = "OPSPUT-IRQ", + .irq_shutdown = shutdown_opsput, + .irq_mask = mask_opsput, + .irq_unmask = unmask_opsput, }; /* @@ -100,7 +91,6 @@ static void disable_opsput_pld_irq(unsigned int irq) unsigned int pldirq; pldirq = irq2pldirq(irq); -// disable_opsput_irq(M32R_IRQ_INT1); port = pldirq2port(pldirq); data = pld_icu_data[pldirq].icucr|PLD_ICUCR_ILEVEL7; outw(data, port); @@ -112,7 +102,6 @@ static void enable_opsput_pld_irq(unsigned int irq) unsigned int pldirq; pldirq = irq2pldirq(irq); -// enable_opsput_irq(M32R_IRQ_INT1); port = pldirq2port(pldirq); data = pld_icu_data[pldirq].icucr|PLD_ICUCR_IEN|PLD_ICUCR_ILEVEL6; outw(data, port); @@ -127,7 +116,7 @@ static void mask_and_ack_opsput_pld(unsigned int irq) static void end_opsput_pld_irq(unsigned int irq) { enable_opsput_pld_irq(irq); - end_opsput_irq(M32R_IRQ_INT1); + enable_opsput_irq(M32R_IRQ_INT1); } static unsigned int startup_opsput_pld_irq(unsigned int irq) @@ -197,7 +186,7 @@ static void mask_and_ack_opsput_lanpld(unsigned int irq) static void end_opsput_lanpld_irq(unsigned int irq) { enable_opsput_lanpld_irq(irq); - end_opsput_irq(M32R_IRQ_INT0); + enable_opsput_irq(M32R_IRQ_INT0); } static unsigned int startup_opsput_lanpld_irq(unsigned int irq) @@ -266,7 +255,7 @@ static void mask_and_ack_opsput_lcdpld(unsigned int irq) static void end_opsput_lcdpld_irq(unsigned int irq) { enable_opsput_lcdpld_irq(irq); - end_opsput_irq(M32R_IRQ_INT2); + enable_opsput_irq(M32R_IRQ_INT2); } static unsigned int startup_opsput_lcdpld_irq(unsigned int irq) @@ -306,32 +295,38 @@ void __init init_IRQ(void) #endif /* CONFIG_SMC91X */ /* MFT2 : system timer */ - set_irq_chip(M32R_IRQ_MFT2, &opsput_irq_type); + set_irq_chip_and_handler(M32R_IRQ_MFT2, &opsput_irq_type, + handle_level_irq); icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; disable_opsput_irq(M32R_IRQ_MFT2); /* SIO0 : receive */ - set_irq_chip(M32R_IRQ_SIO0_R, &opsput_irq_type); + set_irq_chip_and_handler(M32R_IRQ_SIO0_R, &opsput_irq_type, + handle_level_irq); icu_data[M32R_IRQ_SIO0_R].icucr = 0; disable_opsput_irq(M32R_IRQ_SIO0_R); /* SIO0 : send */ - set_irq_chip(M32R_IRQ_SIO0_S, &opsput_irq_type); + set_irq_chip_and_handler(M32R_IRQ_SIO0_S, &opsput_irq_type, + handle_level_irq); icu_data[M32R_IRQ_SIO0_S].icucr = 0; disable_opsput_irq(M32R_IRQ_SIO0_S); /* SIO1 : receive */ - set_irq_chip(M32R_IRQ_SIO1_R, &opsput_irq_type); + set_irq_chip_and_handler(M32R_IRQ_SIO1_R, &opsput_irq_type, + handle_level_irq); icu_data[M32R_IRQ_SIO1_R].icucr = 0; disable_opsput_irq(M32R_IRQ_SIO1_R); /* SIO1 : send */ - set_irq_chip(M32R_IRQ_SIO1_S, &opsput_irq_type); + set_irq_chip_and_handler(M32R_IRQ_SIO1_S, &opsput_irq_type, + handle_level_irq); icu_data[M32R_IRQ_SIO1_S].icucr = 0; disable_opsput_irq(M32R_IRQ_SIO1_S); /* DMA1 : */ - set_irq_chip(M32R_IRQ_DMA1, &opsput_irq_type); + set_irq_chip_and_handler(M32R_IRQ_DMA1, &opsput_irq_type, + handle_level_irq); icu_data[M32R_IRQ_DMA1].icucr = 0; disable_opsput_irq(M32R_IRQ_DMA1); @@ -394,7 +389,8 @@ void __init init_IRQ(void) /* * INT3# is used for AR */ - set_irq_chip(M32R_IRQ_INT3, &opsput_irq_type); + set_irq_chip_and_handler(M32R_IRQ_INT3, &opsput_irq_type, + handle_level_irq); icu_data[M32R_IRQ_INT3].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; disable_opsput_irq(M32R_IRQ_INT3); #endif /* CONFIG_VIDEO_M32R_AR */ -- cgit v0.10.2 From 22cbc9384a495f2e6eb0d0fda91692431a28468e Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Wed, 19 Jan 2011 18:55:09 +0100 Subject: m32r: Convert opsput pld irq chip Convert the irq chips to the new functions and use proper flow handlers. handle_level_irq is appropriate. Signed-off-by: Thomas Gleixner Cc: Hirokazu Takata Cc: Paul Mundt diff --git a/arch/m32r/platforms/opsput/setup.c b/arch/m32r/platforms/opsput/setup.c index 8c0907d..00eb3b8 100644 --- a/arch/m32r/platforms/opsput/setup.c +++ b/arch/m32r/platforms/opsput/setup.c @@ -107,44 +107,33 @@ static void enable_opsput_pld_irq(unsigned int irq) outw(data, port); } -static void mask_and_ack_opsput_pld(unsigned int irq) +static void mask_opsput_pld(struct irq_data *data) { - disable_opsput_pld_irq(irq); -// mask_and_ack_opsput(M32R_IRQ_INT1); + disable_opsput_pld_irq(data->irq); } -static void end_opsput_pld_irq(unsigned int irq) +static void unmask_opsput_pld(struct irq_data *data) { - enable_opsput_pld_irq(irq); + enable_opsput_pld_irq(data->irq); enable_opsput_irq(M32R_IRQ_INT1); } -static unsigned int startup_opsput_pld_irq(unsigned int irq) -{ - enable_opsput_pld_irq(irq); - return (0); -} - -static void shutdown_opsput_pld_irq(unsigned int irq) +static void shutdown_opsput_pld(struct irq_data *data) { unsigned long port; unsigned int pldirq; - pldirq = irq2pldirq(irq); -// shutdown_opsput_irq(M32R_IRQ_INT1); + pldirq = irq2pldirq(data->irq); port = pldirq2port(pldirq); outw(PLD_ICUCR_ILEVEL7, port); } static struct irq_chip opsput_pld_irq_type = { - .name = "OPSPUT-PLD-IRQ", - .startup = startup_opsput_pld_irq, - .shutdown = shutdown_opsput_pld_irq, - .enable = enable_opsput_pld_irq, - .disable = disable_opsput_pld_irq, - .ack = mask_and_ack_opsput_pld, - .end = end_opsput_pld_irq + .name = "OPSPUT-PLD-IRQ", + .irq_shutdown = shutdown_opsput_pld, + .irq_mask = mask_opsput_pld, + .irq_unmask = unmask_opsput_pld, }; /* @@ -332,28 +321,33 @@ void __init init_IRQ(void) #ifdef CONFIG_SERIAL_M32R_PLDSIO /* INT#1: SIO0 Receive on PLD */ - set_irq_chip(PLD_IRQ_SIO0_RCV, &opsput_pld_irq_type); + set_irq_chip_and_handler(PLD_IRQ_SIO0_RCV, &opsput_pld_irq_type, + handle_level_irq); pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_RCV)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03; disable_opsput_pld_irq(PLD_IRQ_SIO0_RCV); /* INT#1: SIO0 Send on PLD */ - set_irq_chip(PLD_IRQ_SIO0_SND, &opsput_pld_irq_type); + set_irq_chip_and_handler(PLD_IRQ_SIO0_SND, &opsput_pld_irq_type, + handle_level_irq); pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_SND)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03; disable_opsput_pld_irq(PLD_IRQ_SIO0_SND); #endif /* CONFIG_SERIAL_M32R_PLDSIO */ /* INT#1: CFC IREQ on PLD */ - set_irq_chip(PLD_IRQ_CFIREQ, &opsput_pld_irq_type); + set_irq_chip_and_handler(PLD_IRQ_CFIREQ, &opsput_pld_irq_type, + handle_level_irq); pld_icu_data[irq2pldirq(PLD_IRQ_CFIREQ)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* 'L' level sense */ disable_opsput_pld_irq(PLD_IRQ_CFIREQ); /* INT#1: CFC Insert on PLD */ - set_irq_chip(PLD_IRQ_CFC_INSERT, &opsput_pld_irq_type); + set_irq_chip_and_handler(PLD_IRQ_CFC_INSERT, &opsput_pld_irq_type, + handle_level_irq); pld_icu_data[irq2pldirq(PLD_IRQ_CFC_INSERT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD00; /* 'L' edge sense */ disable_opsput_pld_irq(PLD_IRQ_CFC_INSERT); /* INT#1: CFC Eject on PLD */ - set_irq_chip(PLD_IRQ_CFC_EJECT, &opsput_pld_irq_type); + set_irq_chip_and_handler(PLD_IRQ_CFC_EJECT, &opsput_pld_irq_type, + handle_level_irq); pld_icu_data[irq2pldirq(PLD_IRQ_CFC_EJECT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* 'H' edge sense */ disable_opsput_pld_irq(PLD_IRQ_CFC_EJECT); -- cgit v0.10.2 From 1899a493b991cf9ea7a57d15b64588632fe32cf0 Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Wed, 19 Jan 2011 18:58:45 +0100 Subject: m32r: Convert opsput lanpld irq chip Convert the irq chips to the new functions and use proper flow handlers. handle_level_irq is appropriate. Signed-off-by: Thomas Gleixner Cc: Hirokazu Takata Cc: Paul Mundt diff --git a/arch/m32r/platforms/opsput/setup.c b/arch/m32r/platforms/opsput/setup.c index 00eb3b8..7648c1d 100644 --- a/arch/m32r/platforms/opsput/setup.c +++ b/arch/m32r/platforms/opsput/setup.c @@ -167,42 +167,33 @@ static void enable_opsput_lanpld_irq(unsigned int irq) outw(data, port); } -static void mask_and_ack_opsput_lanpld(unsigned int irq) +static void mask_opsput_lanpld(struct irq_data *data) { - disable_opsput_lanpld_irq(irq); + disable_opsput_lanpld_irq(data->irq); } -static void end_opsput_lanpld_irq(unsigned int irq) +static void unmask_opsput_lanpld(struct irq_data *data) { - enable_opsput_lanpld_irq(irq); + enable_opsput_lanpld_irq(data->irq); enable_opsput_irq(M32R_IRQ_INT0); } -static unsigned int startup_opsput_lanpld_irq(unsigned int irq) -{ - enable_opsput_lanpld_irq(irq); - return (0); -} - -static void shutdown_opsput_lanpld_irq(unsigned int irq) +static void shutdown_opsput_lanpld(struct irq_data *data) { unsigned long port; unsigned int pldirq; - pldirq = irq2lanpldirq(irq); + pldirq = irq2lanpldirq(data->irq); port = lanpldirq2port(pldirq); outw(PLD_ICUCR_ILEVEL7, port); } static struct irq_chip opsput_lanpld_irq_type = { - .name = "OPSPUT-PLD-LAN-IRQ", - .startup = startup_opsput_lanpld_irq, - .shutdown = shutdown_opsput_lanpld_irq, - .enable = enable_opsput_lanpld_irq, - .disable = disable_opsput_lanpld_irq, - .ack = mask_and_ack_opsput_lanpld, - .end = end_opsput_lanpld_irq + .name = "OPSPUT-PLD-LAN-IRQ", + .irq_shutdown = shutdown_opsput_lanpld, + .irq_mask = mask_opsput_lanpld, + .irq_unmask = unmask_opsput_lanpld, }; /* @@ -278,7 +269,8 @@ void __init init_IRQ(void) { #if defined(CONFIG_SMC91X) /* INT#0: LAN controller on OPSPUT-LAN (SMC91C111)*/ - set_irq_chip(OPSPUT_LAN_IRQ_LAN, &opsput_lanpld_irq_type); + set_irq_chip_and_handler(OPSPUT_LAN_IRQ_LAN, &opsput_lanpld_irq_type, + handle_level_irq); lanpld_icu_data[irq2lanpldirq(OPSPUT_LAN_IRQ_LAN)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* "H" edge sense */ disable_opsput_lanpld_irq(OPSPUT_LAN_IRQ_LAN); #endif /* CONFIG_SMC91X */ -- cgit v0.10.2 From 9b141fa649b160c6a0854a79fe2cd741c5c99e80 Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Wed, 19 Jan 2011 19:01:23 +0100 Subject: m32r: Convert opsput_lcdpld irq chip Convert the irq chips to the new functions and use proper flow handlers. handle_level_irq is appropriate. Signed-off-by: Thomas Gleixner Cc: Hirokazu Takata Cc: Paul Mundt diff --git a/arch/m32r/platforms/opsput/setup.c b/arch/m32r/platforms/opsput/setup.c index 7648c1d..1273154 100644 --- a/arch/m32r/platforms/opsput/setup.c +++ b/arch/m32r/platforms/opsput/setup.c @@ -227,42 +227,32 @@ static void enable_opsput_lcdpld_irq(unsigned int irq) outw(data, port); } -static void mask_and_ack_opsput_lcdpld(unsigned int irq) +static void mask_opsput_lcdpld(struct irq_data *data) { - disable_opsput_lcdpld_irq(irq); + disable_opsput_lcdpld_irq(data->irq); } -static void end_opsput_lcdpld_irq(unsigned int irq) +static void unmask_opsput_lcdpld(struct irq_data *data) { - enable_opsput_lcdpld_irq(irq); + enable_opsput_lcdpld_irq(data->irq); enable_opsput_irq(M32R_IRQ_INT2); } -static unsigned int startup_opsput_lcdpld_irq(unsigned int irq) -{ - enable_opsput_lcdpld_irq(irq); - return (0); -} - -static void shutdown_opsput_lcdpld_irq(unsigned int irq) +static void shutdown_opsput_lcdpld(struct irq_data *data) { unsigned long port; unsigned int pldirq; - pldirq = irq2lcdpldirq(irq); + pldirq = irq2lcdpldirq(data->irq); port = lcdpldirq2port(pldirq); outw(PLD_ICUCR_ILEVEL7, port); } -static struct irq_chip opsput_lcdpld_irq_type = -{ - "OPSPUT-PLD-LCD-IRQ", - startup_opsput_lcdpld_irq, - shutdown_opsput_lcdpld_irq, - enable_opsput_lcdpld_irq, - disable_opsput_lcdpld_irq, - mask_and_ack_opsput_lcdpld, - end_opsput_lcdpld_irq +static struct irq_chip opsput_lcdpld_irq_type = { + .name = "OPSPUT-PLD-LCD-IRQ", + .irq_shutdown = shutdown_opsput_lcdpld, + .irq_mask = mask_opsput_lcdpld, + .irq_unmask = unmask_opsput_lcdpld, }; void __init init_IRQ(void) @@ -358,11 +348,11 @@ void __init init_IRQ(void) enable_opsput_irq(M32R_IRQ_INT1); #if defined(CONFIG_USB) - outw(USBCR_OTGS, USBCR); /* USBCR: non-OTG */ - - set_irq_chip(OPSPUT_LCD_IRQ_USB_INT1, &opsput_lcdpld_irq_type); - lcdpld_icu_data[irq2lcdpldirq(OPSPUT_LCD_IRQ_USB_INT1)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* "L" level sense */ - disable_opsput_lcdpld_irq(OPSPUT_LCD_IRQ_USB_INT1); + outw(USBCR_OTGS, USBCR); /* USBCR: non-OTG */ + set_irq_chip_and_handler(OPSPUT_LCD_IRQ_USB_INT1, + &opsput_lcdpld_irq_type, handle_level_irq); + lcdpld_icu_data[irq2lcdpldirq(OPSPUT_LCD_IRQ_USB_INT1)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* "L" level sense */ + disable_opsput_lcdpld_irq(OPSPUT_LCD_IRQ_USB_INT1); #endif /* * INT2# is used for BAT, USB, AUDIO -- cgit v0.10.2 From 7a0abc7e7767455c9972de25b6c74e87271d16be Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Wed, 19 Jan 2011 19:10:18 +0100 Subject: m32r: Convert usrv platform irq handling Convert the irq chips to the new functions and use proper flow handlers. handle_level_irq is appropriate. Signed-off-by: Thomas Gleixner Cc: Hirokazu Takata Cc: Paul Mundt diff --git a/arch/m32r/platforms/usrv/setup.c b/arch/m32r/platforms/usrv/setup.c index d6eb586..f3cff26 100644 --- a/arch/m32r/platforms/usrv/setup.c +++ b/arch/m32r/platforms/usrv/setup.c @@ -37,39 +37,30 @@ static void enable_mappi_irq(unsigned int irq) outl(data, port); } -static void mask_and_ack_mappi(unsigned int irq) +static void mask_mappi(struct irq_data *data) { - disable_mappi_irq(irq); + disable_mappi_irq(data->irq); } -static void end_mappi_irq(unsigned int irq) +static void unmask_mappi(struct irq_data *data) { - enable_mappi_irq(irq); + enable_mappi_irq(data->irq); } -static unsigned int startup_mappi_irq(unsigned int irq) -{ - enable_mappi_irq(irq); - return 0; -} - -static void shutdown_mappi_irq(unsigned int irq) +static void shutdown_mappi(struct irq_data *data) { unsigned long port; - port = irq2port(irq); + port = irq2port(data->irq); outl(M32R_ICUCR_ILEVEL7, port); } static struct irq_chip mappi_irq_type = { - .name = "M32700-IRQ", - .startup = startup_mappi_irq, - .shutdown = shutdown_mappi_irq, - .enable = enable_mappi_irq, - .disable = disable_mappi_irq, - .ack = mask_and_ack_mappi, - .end = end_mappi_irq + .name = "M32700-IRQ", + .irq_shutdown = shutdown_mappi, + .irq_mask = mask_mappi, + .irq_unmask = unmask_mappi, }; /* @@ -107,42 +98,33 @@ static void enable_m32700ut_pld_irq(unsigned int irq) outw(data, port); } -static void mask_and_ack_m32700ut_pld(unsigned int irq) +static void mask_m32700ut_pld(struct irq_data *data) { - disable_m32700ut_pld_irq(irq); + disable_m32700ut_pld_irq(data->irq); } -static void end_m32700ut_pld_irq(unsigned int irq) +static void unmask_m32700ut_pld(struct irq_data *data) { - enable_m32700ut_pld_irq(irq); - end_mappi_irq(M32R_IRQ_INT1); -} - -static unsigned int startup_m32700ut_pld_irq(unsigned int irq) -{ - enable_m32700ut_pld_irq(irq); - return 0; + enable_m32700ut_pld_irq(data->irq); + enable_mappi_irq(M32R_IRQ_INT1); } -static void shutdown_m32700ut_pld_irq(unsigned int irq) +static void shutdown_m32700ut_pld(struct irq_data *data) { unsigned long port; unsigned int pldirq; - pldirq = irq2pldirq(irq); + pldirq = irq2pldirq(data->irq); port = pldirq2port(pldirq); outw(PLD_ICUCR_ILEVEL7, port); } static struct irq_chip m32700ut_pld_irq_type = { - .name = "USRV-PLD-IRQ", - .startup = startup_m32700ut_pld_irq, - .shutdown = shutdown_m32700ut_pld_irq, - .enable = enable_m32700ut_pld_irq, - .disable = disable_m32700ut_pld_irq, - .ack = mask_and_ack_m32700ut_pld, - .end = end_m32700ut_pld_irq + .name = "USRV-PLD-IRQ", + .irq_shutdown = shutdown_m32700ut_pld, + .irq_mask = mask_m32700ut_pld, + .irq_unmask = unmask_m32700ut_pld, }; void __init init_IRQ(void) @@ -156,35 +138,42 @@ void __init init_IRQ(void) once++; /* MFT2 : system timer */ - set_irq_chip(M32R_IRQ_MFT2, &mappi_irq_type); + set_irq_chip_and_handler(M32R_IRQ_MFT2, &mappi_irq_type, + handle_level_irq); icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; disable_mappi_irq(M32R_IRQ_MFT2); #if defined(CONFIG_SERIAL_M32R_SIO) /* SIO0_R : uart receive data */ - set_irq_chip(M32R_IRQ_SIO0_R, &mappi_irq_type); + set_irq_chip_and_handler(M32R_IRQ_SIO0_R, &mappi_irq_type, + handle_level_irq); icu_data[M32R_IRQ_SIO0_R].icucr = 0; disable_mappi_irq(M32R_IRQ_SIO0_R); /* SIO0_S : uart send data */ - set_irq_chip(M32R_IRQ_SIO0_S, &mappi_irq_type); + set_irq_chip_and_handler(M32R_IRQ_SIO0_S, &mappi_irq_type, + handle_level_irq); icu_data[M32R_IRQ_SIO0_S].icucr = 0; disable_mappi_irq(M32R_IRQ_SIO0_S); /* SIO1_R : uart receive data */ - set_irq_chip(M32R_IRQ_SIO1_R, &mappi_irq_type); + set_irq_chip_and_handler(M32R_IRQ_SIO1_R, &mappi_irq_type, + handle_level_irq); icu_data[M32R_IRQ_SIO1_R].icucr = 0; disable_mappi_irq(M32R_IRQ_SIO1_R); /* SIO1_S : uart send data */ - set_irq_chip(M32R_IRQ_SIO1_S, &mappi_irq_type); + set_irq_chip_and_handler(M32R_IRQ_SIO1_S, &mappi_irq_type, + handle_level_irq); icu_data[M32R_IRQ_SIO1_S].icucr = 0; disable_mappi_irq(M32R_IRQ_SIO1_S); #endif /* CONFIG_SERIAL_M32R_SIO */ /* INT#67-#71: CFC#0 IREQ on PLD */ for (i = 0 ; i < CONFIG_M32R_CFC_NUM ; i++ ) { - set_irq_chip(PLD_IRQ_CF0 + i, &m32700ut_pld_irq_type); + set_irq_chip_and_handler(PLD_IRQ_CF0 + i, + &m32700ut_pld_irq_type, + handle_level_irq); pld_icu_data[irq2pldirq(PLD_IRQ_CF0 + i)].icucr = PLD_ICUCR_ISMOD01; /* 'L' level sense */ disable_m32700ut_pld_irq(PLD_IRQ_CF0 + i); @@ -192,13 +181,15 @@ void __init init_IRQ(void) #if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE) /* INT#76: 16552D#0 IREQ on PLD */ - set_irq_chip(PLD_IRQ_UART0, &m32700ut_pld_irq_type); + set_irq_chip_and_handler(PLD_IRQ_UART0, &m32700ut_pld_irq_type, + handle_level_irq); pld_icu_data[irq2pldirq(PLD_IRQ_UART0)].icucr = PLD_ICUCR_ISMOD03; /* 'H' level sense */ disable_m32700ut_pld_irq(PLD_IRQ_UART0); /* INT#77: 16552D#1 IREQ on PLD */ - set_irq_chip(PLD_IRQ_UART1, &m32700ut_pld_irq_type); + set_irq_chip_and_handler(PLD_IRQ_UART1, &m32700ut_pld_irq_type, + handle_level_irq); pld_icu_data[irq2pldirq(PLD_IRQ_UART1)].icucr = PLD_ICUCR_ISMOD03; /* 'H' level sense */ disable_m32700ut_pld_irq(PLD_IRQ_UART1); @@ -206,7 +197,8 @@ void __init init_IRQ(void) #if defined(CONFIG_IDC_AK4524) || defined(CONFIG_IDC_AK4524_MODULE) /* INT#80: AK4524 IREQ on PLD */ - set_irq_chip(PLD_IRQ_SNDINT, &m32700ut_pld_irq_type); + set_irq_chip_and_handler(PLD_IRQ_SNDINT, &m32700ut_pld_irq_type, + handle_level_irq); pld_icu_data[irq2pldirq(PLD_IRQ_SNDINT)].icucr = PLD_ICUCR_ISMOD01; /* 'L' level sense */ disable_m32700ut_pld_irq(PLD_IRQ_SNDINT); -- cgit v0.10.2 From 0e155b2ce293382730b8473f6ceeb7ac9b939b7d Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Wed, 19 Jan 2011 19:17:10 +0100 Subject: m32r: Convert to generic irq Kconfig Use the generic irq Kconfig. Select GENERIC_HARDIRQS_NO_DEPRECATED as we have converted all irq_chip functions. Signed-off-by: Thomas Gleixner Cc: Hirokazu Takata Cc: Paul Mundt diff --git a/arch/m32r/Kconfig b/arch/m32r/Kconfig index 5c291d6..ef4c1e4 100644 --- a/arch/m32r/Kconfig +++ b/arch/m32r/Kconfig @@ -7,6 +7,9 @@ config M32R select HAVE_KERNEL_GZIP select HAVE_KERNEL_BZIP2 select HAVE_KERNEL_LZMA + select HAVE_GENERIC_HARDIRQS + select GENERIC_HARDIRQS_NO_DEPRECATED + select GENERIC_IRQ_PROBE config SBUS bool @@ -19,14 +22,6 @@ config ZONE_DMA bool default y -config GENERIC_HARDIRQS - bool - default y - -config GENERIC_IRQ_PROBE - bool - default y - config NO_IOPORT def_bool y -- cgit v0.10.2 From 1c77ff22f539ceaa64ea43d6a26d867e84602cb7 Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Wed, 19 Jan 2011 19:41:35 +0100 Subject: genirq: Remove __do_IRQ All architectures are finally converted. Remove the cruft. Signed-off-by: Thomas Gleixner Cc: Richard Henderson Cc: Mike Frysinger Cc: David Howells Cc: Tony Luck Cc: Greg Ungerer Cc: Michal Simek Acked-by: David Howells Cc: Kyle McMartin Acked-by: Benjamin Herrenschmidt Cc: Chen Liqin Cc: "David S. Miller" Cc: Chris Metcalf Cc: Jeff Dike diff --git a/Documentation/feature-removal-schedule.txt b/Documentation/feature-removal-schedule.txt index 8c594c4..b959659 100644 --- a/Documentation/feature-removal-schedule.txt +++ b/Documentation/feature-removal-schedule.txt @@ -357,14 +357,6 @@ Who: Dave Jones , Matthew Garrett ----------------------------- -What: __do_IRQ all in one fits nothing interrupt handler -When: 2.6.32 -Why: __do_IRQ was kept for easy migration to the type flow handlers. - More than two years of migration time is enough. -Who: Thomas Gleixner - ------------------------------ - What: fakephp and associated sysfs files in /sys/bus/pci/slots/ When: 2011 Why: In 2.6.27, the semantics of /sys/bus/pci/slots was redefined to diff --git a/arch/alpha/Kconfig b/arch/alpha/Kconfig index fc95ee1..943fe69 100644 --- a/arch/alpha/Kconfig +++ b/arch/alpha/Kconfig @@ -68,9 +68,6 @@ config GENERIC_IOMAP bool default n -config GENERIC_HARDIRQS_NO__DO_IRQ - def_bool y - config GENERIC_HARDIRQS bool default y diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig index 0a221d4..a37b2be 100644 --- a/arch/blackfin/Kconfig +++ b/arch/blackfin/Kconfig @@ -50,9 +50,6 @@ config GENERIC_HARDIRQS config GENERIC_IRQ_PROBE def_bool y -config GENERIC_HARDIRQS_NO__DO_IRQ - def_bool y - config GENERIC_GPIO def_bool y diff --git a/arch/frv/Kconfig b/arch/frv/Kconfig index f6bcb03..e504ede 100644 --- a/arch/frv/Kconfig +++ b/arch/frv/Kconfig @@ -33,10 +33,6 @@ config GENERIC_HARDIRQS bool default y -config GENERIC_HARDIRQS_NO__DO_IRQ - bool - default y - config TIME_LOW_RES bool default y diff --git a/arch/ia64/Kconfig b/arch/ia64/Kconfig index e0f5b6d..be1faf9 100644 --- a/arch/ia64/Kconfig +++ b/arch/ia64/Kconfig @@ -684,9 +684,6 @@ source "lib/Kconfig" config GENERIC_HARDIRQS def_bool y -config GENERIC_HARDIRQS_NO__DO_IRQ - def_bool y - config GENERIC_IRQ_PROBE bool default y diff --git a/arch/m68knommu/Kconfig b/arch/m68knommu/Kconfig index 704e7b9..7379cb0 100644 --- a/arch/m68knommu/Kconfig +++ b/arch/m68knommu/Kconfig @@ -52,10 +52,6 @@ config GENERIC_HARDIRQS bool default y -config GENERIC_HARDIRQS_NO__DO_IRQ - bool - default y - config GENERIC_CALIBRATE_DELAY bool default y diff --git a/arch/microblaze/Kconfig b/arch/microblaze/Kconfig index 5f5018a..5a63784 100644 --- a/arch/microblaze/Kconfig +++ b/arch/microblaze/Kconfig @@ -52,9 +52,6 @@ config GENERIC_TIME_VSYSCALL config GENERIC_CLOCKEVENTS def_bool y -config GENERIC_HARDIRQS_NO__DO_IRQ - def_bool y - config GENERIC_GPIO def_bool y diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 548e6cc..f5ecc05 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -793,9 +793,6 @@ config SCHED_OMIT_FRAME_POINTER bool default y -config GENERIC_HARDIRQS_NO__DO_IRQ - def_bool y - # # Select some configuration options automatically based on user selections. # diff --git a/arch/mn10300/Kconfig b/arch/mn10300/Kconfig index 8ed41cf..4638269 100644 --- a/arch/mn10300/Kconfig +++ b/arch/mn10300/Kconfig @@ -34,9 +34,6 @@ config RWSEM_GENERIC_SPINLOCK config RWSEM_XCHGADD_ALGORITHM bool -config GENERIC_HARDIRQS_NO__DO_IRQ - def_bool y - config GENERIC_CALIBRATE_DELAY def_bool y diff --git a/arch/parisc/Kconfig b/arch/parisc/Kconfig index 0888675..4b94ac4 100644 --- a/arch/parisc/Kconfig +++ b/arch/parisc/Kconfig @@ -12,7 +12,6 @@ config PARISC select HAVE_IRQ_WORK select HAVE_PERF_EVENTS select GENERIC_ATOMIC64 if !64BIT - select GENERIC_HARDIRQS_NO__DO_IRQ help The PA-RISC microprocessor is designed by Hewlett-Packard and used in many of their workstations & servers (HP9000 700 and 800 series, @@ -79,9 +78,6 @@ config IRQ_PER_CPU bool default y -config GENERIC_HARDIRQS_NO__DO_IRQ - def_bool y - # unless you want to implement ACPI on PA-RISC ... ;-) config PM bool diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig index 959f38c..e0b185d 100644 --- a/arch/powerpc/Kconfig +++ b/arch/powerpc/Kconfig @@ -40,10 +40,6 @@ config GENERIC_HARDIRQS bool default y -config GENERIC_HARDIRQS_NO__DO_IRQ - bool - default y - config HAVE_SETUP_PER_CPU_AREA def_bool PPC64 diff --git a/arch/score/Kconfig b/arch/score/Kconfig index 4293fdcb..4f159ac 100644 --- a/arch/score/Kconfig +++ b/arch/score/Kconfig @@ -53,9 +53,6 @@ config GENERIC_CLOCKEVENTS config SCHED_NO_NO_OMIT_FRAME_POINTER def_bool y -config GENERIC_HARDIRQS_NO__DO_IRQ - def_bool y - config GENERIC_SYSCALL_TABLE def_bool y diff --git a/arch/sparc/Kconfig b/arch/sparc/Kconfig index 45d9c87..989bb64 100644 --- a/arch/sparc/Kconfig +++ b/arch/sparc/Kconfig @@ -107,10 +107,6 @@ config NEED_PER_CPU_EMBED_FIRST_CHUNK config NEED_PER_CPU_PAGE_FIRST_CHUNK def_bool y if SPARC64 -config GENERIC_HARDIRQS_NO__DO_IRQ - bool - def_bool y if SPARC64 - config MMU bool default y diff --git a/arch/tile/Kconfig b/arch/tile/Kconfig index 4e8b82b..c16b98c 100644 --- a/arch/tile/Kconfig +++ b/arch/tile/Kconfig @@ -10,9 +10,6 @@ config GENERIC_CSUM config GENERIC_HARDIRQS def_bool y -config GENERIC_HARDIRQS_NO__DO_IRQ - def_bool y - config GENERIC_IRQ_PROBE def_bool y diff --git a/arch/um/Kconfig.um b/arch/um/Kconfig.um index f8d1d0d..90a438a 100644 --- a/arch/um/Kconfig.um +++ b/arch/um/Kconfig.um @@ -120,9 +120,6 @@ config SMP If you don't know what to do, say N. -config GENERIC_HARDIRQS_NO__DO_IRQ - def_bool y - config NR_CPUS int "Maximum number of CPUs (2-32)" range 2 32 diff --git a/include/linux/irqdesc.h b/include/linux/irqdesc.h index 6a64c6f..c1a95b7 100644 --- a/include/linux/irqdesc.h +++ b/include/linux/irqdesc.h @@ -101,13 +101,6 @@ static inline struct irq_desc *move_irq_desc(struct irq_desc *desc, int node) #define get_irq_desc_msi(desc) ((desc)->irq_data.msi_desc) /* - * Monolithic do_IRQ implementation. - */ -#ifndef CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ -extern unsigned int __do_IRQ(unsigned int irq); -#endif - -/* * Architectures call this to let the generic IRQ layer * handle an interrupt. If the descriptor is attached to an * irqchip-style controller then we call the ->handle_irq() handler, @@ -115,14 +108,7 @@ extern unsigned int __do_IRQ(unsigned int irq); */ static inline void generic_handle_irq_desc(unsigned int irq, struct irq_desc *desc) { -#ifdef CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ desc->handle_irq(irq, desc); -#else - if (likely(desc->handle_irq)) - desc->handle_irq(irq, desc); - else - __do_IRQ(irq); -#endif } static inline void generic_handle_irq(unsigned int irq) diff --git a/kernel/irq/Kconfig b/kernel/irq/Kconfig index 31d766b..8e42fec 100644 --- a/kernel/irq/Kconfig +++ b/kernel/irq/Kconfig @@ -9,9 +9,6 @@ menu "IRQ subsystem" config GENERIC_HARDIRQS def_bool y -config GENERIC_HARDIRQS_NO__DO_IRQ - def_bool y - # Select this to disable the deprecated stuff config GENERIC_HARDIRQS_NO_DEPRECATED def_bool n diff --git a/kernel/irq/handle.c b/kernel/irq/handle.c index e2347eb..3540a71 100644 --- a/kernel/irq/handle.c +++ b/kernel/irq/handle.c @@ -118,114 +118,3 @@ irqreturn_t handle_IRQ_event(unsigned int irq, struct irqaction *action) return retval; } - -#ifndef CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ - -#ifdef CONFIG_ENABLE_WARN_DEPRECATED -# warning __do_IRQ is deprecated. Please convert to proper flow handlers -#endif - -/** - * __do_IRQ - original all in one highlevel IRQ handler - * @irq: the interrupt number - * - * __do_IRQ handles all normal device IRQ's (the special - * SMP cross-CPU interrupts have their own specific - * handlers). - * - * This is the original x86 implementation which is used for every - * interrupt type. - */ -unsigned int __do_IRQ(unsigned int irq) -{ - struct irq_desc *desc = irq_to_desc(irq); - struct irqaction *action; - unsigned int status; - - kstat_incr_irqs_this_cpu(irq, desc); - - if (CHECK_IRQ_PER_CPU(desc->status)) { - irqreturn_t action_ret; - - /* - * No locking required for CPU-local interrupts: - */ - if (desc->irq_data.chip->ack) - desc->irq_data.chip->ack(irq); - if (likely(!(desc->status & IRQ_DISABLED))) { - action_ret = handle_IRQ_event(irq, desc->action); - if (!noirqdebug) - note_interrupt(irq, desc, action_ret); - } - desc->irq_data.chip->end(irq); - return 1; - } - - raw_spin_lock(&desc->lock); - if (desc->irq_data.chip->ack) - desc->irq_data.chip->ack(irq); - /* - * REPLAY is when Linux resends an IRQ that was dropped earlier - * WAITING is used by probe to mark irqs that are being tested - */ - status = desc->status & ~(IRQ_REPLAY | IRQ_WAITING); - status |= IRQ_PENDING; /* we _want_ to handle it */ - - /* - * If the IRQ is disabled for whatever reason, we cannot - * use the action we have. - */ - action = NULL; - if (likely(!(status & (IRQ_DISABLED | IRQ_INPROGRESS)))) { - action = desc->action; - status &= ~IRQ_PENDING; /* we commit to handling */ - status |= IRQ_INPROGRESS; /* we are handling it */ - } - desc->status = status; - - /* - * If there is no IRQ handler or it was disabled, exit early. - * Since we set PENDING, if another processor is handling - * a different instance of this same irq, the other processor - * will take care of it. - */ - if (unlikely(!action)) - goto out; - - /* - * Edge triggered interrupts need to remember - * pending events. - * This applies to any hw interrupts that allow a second - * instance of the same irq to arrive while we are in do_IRQ - * or in the handler. But the code here only handles the _second_ - * instance of the irq, not the third or fourth. So it is mostly - * useful for irq hardware that does not mask cleanly in an - * SMP environment. - */ - for (;;) { - irqreturn_t action_ret; - - raw_spin_unlock(&desc->lock); - - action_ret = handle_IRQ_event(irq, action); - if (!noirqdebug) - note_interrupt(irq, desc, action_ret); - - raw_spin_lock(&desc->lock); - if (likely(!(desc->status & IRQ_PENDING))) - break; - desc->status &= ~IRQ_PENDING; - } - desc->status &= ~IRQ_INPROGRESS; - -out: - /* - * The ->end() handler has to deal with interrupts which got - * disabled while the handler was running. - */ - desc->irq_data.chip->end(irq); - raw_spin_unlock(&desc->lock); - - return 1; -} -#endif -- cgit v0.10.2 From e27ec649a0dd49741c98173ac5cf4404912d2abf Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Wed, 19 Jan 2011 20:27:11 +0100 Subject: alpha: Use generic irq Kconfig Signed-off-by: Thomas Gleixner Cc: Richard Henderson diff --git a/arch/alpha/Kconfig b/arch/alpha/Kconfig index 943fe69..47f63d4 100644 --- a/arch/alpha/Kconfig +++ b/arch/alpha/Kconfig @@ -8,6 +8,9 @@ config ALPHA select HAVE_IRQ_WORK select HAVE_PERF_EVENTS select HAVE_DMA_ATTRS + select HAVE_GENERIC_HARDIRQS + select GENERIC_IRQ_PROBE + select AUTO_IRQ_AFFINITY if SMP help The Alpha is a 64-bit general-purpose processor designed and marketed by the Digital Equipment Corporation of blessed memory, @@ -68,19 +71,6 @@ config GENERIC_IOMAP bool default n -config GENERIC_HARDIRQS - bool - default y - -config GENERIC_IRQ_PROBE - bool - default y - -config AUTO_IRQ_AFFINITY - bool - depends on SMP - default y - source "init/Kconfig" source "kernel/Kconfig.freezer" -- cgit v0.10.2 From 7b0288634921c748dfeb2ff3e7d04ae7cc94e795 Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Wed, 19 Jan 2011 20:29:58 +0100 Subject: blackfin: Use generic irq Kconfig No functional change. Signed-off-by: Thomas Gleixner Cc: Mike Frysinger diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig index a37b2be..c09577d 100644 --- a/arch/blackfin/Kconfig +++ b/arch/blackfin/Kconfig @@ -30,6 +30,9 @@ config BLACKFIN select HAVE_KERNEL_LZO if RAMKERNEL select HAVE_OPROFILE select ARCH_WANT_OPTIONAL_GPIOLIB + select HAVE_GENERIC_HARDIRQS + select GENERIC_IRQ_PROBE + select IRQ_PER_CPU if SMP config GENERIC_CSUM def_bool y @@ -44,12 +47,6 @@ config ZONE_DMA config GENERIC_FIND_NEXT_BIT def_bool y -config GENERIC_HARDIRQS - def_bool y - -config GENERIC_IRQ_PROBE - def_bool y - config GENERIC_GPIO def_bool y @@ -251,11 +248,6 @@ config HOTPLUG_CPU depends on SMP && HOTPLUG default y -config IRQ_PER_CPU - bool - depends on SMP - default y - config HAVE_LEGACY_PER_CPU_AREA def_bool y depends on SMP -- cgit v0.10.2 From f39b02d6f9af8c942961ef32c2bbce6cb6100c29 Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Wed, 19 Jan 2011 20:32:04 +0100 Subject: frv: Use generic irq Kconfig No functional change. Signed-off-by: Thomas Gleixner Acked-by: David Howells diff --git a/arch/frv/Kconfig b/arch/frv/Kconfig index e504ede..747499a 100644 --- a/arch/frv/Kconfig +++ b/arch/frv/Kconfig @@ -5,6 +5,7 @@ config FRV select HAVE_ARCH_TRACEHOOK select HAVE_IRQ_WORK select HAVE_PERF_EVENTS + select HAVE_GENERIC_HARDIRQS config ZONE_DMA bool @@ -29,10 +30,6 @@ config GENERIC_CALIBRATE_DELAY bool default n -config GENERIC_HARDIRQS - bool - default y - config TIME_LOW_RES bool default y -- cgit v0.10.2 From c5e66129c1b5b6ea73128ce21b3591c00c963c0e Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Wed, 19 Jan 2011 20:32:46 +0100 Subject: ia64: Use generic irq Kconfig No functional change. Signed-off-by: Thomas Gleixner Acked-by: Tony Luck diff --git a/arch/ia64/Kconfig b/arch/ia64/Kconfig index be1faf9..fcf3b43 100644 --- a/arch/ia64/Kconfig +++ b/arch/ia64/Kconfig @@ -22,6 +22,10 @@ config IA64 select HAVE_KVM select HAVE_ARCH_TRACEHOOK select HAVE_DMA_API_DEBUG + select HAVE_GENERIC_HARDIRQS + select GENERIC_IRQ_PROBE + select GENERIC_PENDING_IRQ if SMP + select IRQ_PER_CPU default y help The Itanium Processor Family is Intel's 64-bit successor to @@ -678,25 +682,6 @@ source "arch/ia64/kvm/Kconfig" source "lib/Kconfig" -# -# Use the generic interrupt handling code in kernel/irq/: -# -config GENERIC_HARDIRQS - def_bool y - -config GENERIC_IRQ_PROBE - bool - default y - -config GENERIC_PENDING_IRQ - bool - depends on GENERIC_HARDIRQS && SMP - default y - -config IRQ_PER_CPU - bool - default y - config IOMMU_HELPER def_bool (IA64_HP_ZX1 || IA64_HP_ZX1_SWIOTLB || IA64_GENERIC || SWIOTLB) -- cgit v0.10.2 From d8b19323478af44d243e500656bb6ef2860ced6e Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Wed, 19 Jan 2011 20:34:21 +0100 Subject: m68knommu: Use generic irq Kconfig No functional change. Signed-off-by: Thomas Gleixner Cc: Greg Ungerer diff --git a/arch/m68knommu/Kconfig b/arch/m68knommu/Kconfig index 7379cb0..8b9daca 100644 --- a/arch/m68knommu/Kconfig +++ b/arch/m68knommu/Kconfig @@ -2,6 +2,7 @@ config M68K bool default y select HAVE_IDE + select HAVE_GENERIC_HARDIRQS config MMU bool @@ -48,10 +49,6 @@ config GENERIC_HWEIGHT bool default y -config GENERIC_HARDIRQS - bool - default y - config GENERIC_CALIBRATE_DELAY bool default y -- cgit v0.10.2 From b6e31629e335e8664a11be05992d39b2ee030960 Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Wed, 19 Jan 2011 20:35:05 +0100 Subject: microblaze: Use generic irq Kconfig No functional change. Signed-off-by: Thomas Gleixner Acked-by: Michal Simek diff --git a/arch/microblaze/Kconfig b/arch/microblaze/Kconfig index 5a63784..3168003 100644 --- a/arch/microblaze/Kconfig +++ b/arch/microblaze/Kconfig @@ -15,6 +15,8 @@ config MICROBLAZE select TRACING_SUPPORT select OF select OF_EARLY_FLATTREE + select HAVE_GENERIC_HARDIRQS + select GENERIC_IRQ_PROBE config SWAP def_bool n @@ -37,12 +39,6 @@ config GENERIC_FIND_NEXT_BIT config GENERIC_HWEIGHT def_bool y -config GENERIC_HARDIRQS - def_bool y - -config GENERIC_IRQ_PROBE - def_bool y - config GENERIC_CALIBRATE_DELAY def_bool y -- cgit v0.10.2 From b169c908a51964822dc3aa828a3febb67933f1ac Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Wed, 19 Jan 2011 20:36:02 +0100 Subject: mn10300: Use generic irq Kconfig No functional change. Signed-off-by: Thomas Gleixner Acked-by: David Howells diff --git a/arch/mn10300/Kconfig b/arch/mn10300/Kconfig index 4638269..243bfa2 100644 --- a/arch/mn10300/Kconfig +++ b/arch/mn10300/Kconfig @@ -1,6 +1,7 @@ config MN10300 def_bool y select HAVE_OPROFILE + select GENERIC_HARDIRQS config AM33_2 def_bool n @@ -76,10 +77,6 @@ config QUICKLIST config ARCH_HAS_ILOG2_U32 def_bool y -# Use the generic interrupt handling code in kernel/irq/ -config GENERIC_HARDIRQS - def_bool y - config HOTPLUG_CPU def_bool n -- cgit v0.10.2 From 72e73af1f6546ba08d9314ac0e99dcdb06b7d486 Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Wed, 19 Jan 2011 20:38:30 +0100 Subject: parisc: Use generic irq Kconfig No functional change. Signed-off-by: Thomas Gleixner Cc: Kyle McMartin Acked-by: James Bottomley diff --git a/arch/parisc/Kconfig b/arch/parisc/Kconfig index 4b94ac4..fed2946 100644 --- a/arch/parisc/Kconfig +++ b/arch/parisc/Kconfig @@ -12,6 +12,10 @@ config PARISC select HAVE_IRQ_WORK select HAVE_PERF_EVENTS select GENERIC_ATOMIC64 if !64BIT + select HAVE_GENERIC_HARDIRQS + select GENERIC_IRQ_PROBE + select IRQ_PER_CPU + help The PA-RISC microprocessor is designed by Hewlett-Packard and used in many of their workstations & servers (HP9000 700 and 800 series, @@ -65,19 +69,9 @@ config TIME_LOW_RES depends on SMP default y -config GENERIC_HARDIRQS - def_bool y - -config GENERIC_IRQ_PROBE - def_bool y - config HAVE_LATENCYTOP_SUPPORT def_bool y -config IRQ_PER_CPU - bool - default y - # unless you want to implement ACPI on PA-RISC ... ;-) config PM bool -- cgit v0.10.2 From 2604362b2671cef309f6023e6bea0cec52ee993b Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Wed, 19 Jan 2011 20:39:39 +0100 Subject: powerpc: Use generic irq Kconfig No functional change. Signed-off-by: Thomas Gleixner Cc: Benjamin Herrenschmidt diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig index e0b185d..7d69e9b 100644 --- a/arch/powerpc/Kconfig +++ b/arch/powerpc/Kconfig @@ -36,20 +36,12 @@ config GENERIC_TIME_VSYSCALL config GENERIC_CLOCKEVENTS def_bool y -config GENERIC_HARDIRQS - bool - default y - config HAVE_SETUP_PER_CPU_AREA def_bool PPC64 config NEED_PER_CPU_EMBED_FIRST_CHUNK def_bool PPC64 -config IRQ_PER_CPU - bool - default y - config NR_IRQS int "Number of virtual interrupt numbers" range 32 32768 @@ -139,6 +131,9 @@ config PPC select HAVE_PERF_EVENTS select HAVE_REGS_AND_STACK_ACCESS_API select HAVE_HW_BREAKPOINT if PERF_EVENTS && PPC_BOOK3S_64 + select HAVE_GENERIC_HARDIRQS + select HAVE_SPARSE_IRQ + select IRQ_PER_CPU config EARLY_PRINTK bool @@ -388,19 +383,6 @@ config IRQ_ALL_CPUS CPU. Generally saying Y is safe, although some problems have been reported with SMP Power Macintoshes with this option enabled. -config SPARSE_IRQ - bool "Support sparse irq numbering" - default n - help - This enables support for sparse irqs. This is useful for distro - kernels that want to define a high CONFIG_NR_CPUS value but still - want to have low kernel memory footprint on smaller machines. - - ( Sparse IRQs can also be beneficial on NUMA boxes, as they spread - out the irq_desc[] array in a more NUMA-friendly way. ) - - If you don't know what to do here, say N. - config NUMA bool "NUMA support" depends on PPC64 -- cgit v0.10.2 From 2fc361bfcfce4fd05eb3d2e3d400dd387a5724c4 Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Wed, 19 Jan 2011 20:41:19 +0100 Subject: score: Use generic irq Kconfig No functional change Signed-off-by: Thomas Gleixner Acked-by: Chen Liqin diff --git a/arch/score/Kconfig b/arch/score/Kconfig index 4f159ac..27b2295 100644 --- a/arch/score/Kconfig +++ b/arch/score/Kconfig @@ -1,5 +1,9 @@ menu "Machine selection" +config SCORE + def_bool y + select HAVE_GENERIC_HARDIRQS + choice prompt "System type" default MACH_SPCT6600 @@ -65,9 +69,6 @@ menu "Kernel type" config 32BIT def_bool y -config GENERIC_HARDIRQS - def_bool y - config ARCH_FLATMEM_ENABLE def_bool y -- cgit v0.10.2 From 373b25c3bff14fd9ed30b6ddba49cbeeb7ccdf88 Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Wed, 19 Jan 2011 20:43:56 +0100 Subject: sparc: Use generic irq Kconfig No functional change. Signed-off-by: Thomas Gleixner Acked-by: "David S. Miller" diff --git a/arch/sparc/Kconfig b/arch/sparc/Kconfig index 989bb64..95695e9 100644 --- a/arch/sparc/Kconfig +++ b/arch/sparc/Kconfig @@ -50,6 +50,7 @@ config SPARC64 select RTC_DRV_STARFIRE select HAVE_PERF_EVENTS select PERF_USE_VMALLOC + select HAVE_GENERIC_HARDIRQS config ARCH_DEFCONFIG string @@ -272,10 +273,6 @@ config HOTPLUG_CPU can be controlled through /sys/devices/system/cpu/cpu#. Say N if you want to disable CPU hotplug. -config GENERIC_HARDIRQS - bool - default y if SPARC64 - source "kernel/time/Kconfig" if SPARC64 -- cgit v0.10.2 From 8df274064e02aa8929eb5087dd8841b6601ab0ae Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Wed, 19 Jan 2011 20:44:43 +0100 Subject: tile: Use generic irq Kconfig No functional change. Signed-off-by: Thomas Gleixner Acked-by: Chris Metcalf diff --git a/arch/tile/Kconfig b/arch/tile/Kconfig index c16b98c..08948e4 100644 --- a/arch/tile/Kconfig +++ b/arch/tile/Kconfig @@ -1,21 +1,33 @@ # For a description of the syntax of this configuration file, # see Documentation/kbuild/config-language.txt. -config MMU - def_bool y - -config GENERIC_CSUM +config TILE def_bool y + select HAVE_KVM if !TILEGX + select GENERIC_FIND_FIRST_BIT + select GENERIC_FIND_NEXT_BIT + select USE_GENERIC_SMP_HELPERS + select CC_OPTIMIZE_FOR_SIZE + select HAVE_GENERIC_HARDIRQS + select GENERIC_IRQ_PROBE + select GENERIC_PENDING_IRQ if SMP -config GENERIC_HARDIRQS - def_bool y +# FIXME: investigate whether we need/want these options. +# select HAVE_IOREMAP_PROT +# select HAVE_OPTPROBES +# select HAVE_REGS_AND_STACK_ACCESS_API +# select HAVE_HW_BREAKPOINT +# select PERF_EVENTS +# select HAVE_USER_RETURN_NOTIFIER +# config NO_BOOTMEM +# config ARCH_SUPPORTS_DEBUG_PAGEALLOC +# config HUGETLB_PAGE_SIZE_VARIABLE -config GENERIC_IRQ_PROBE +config MMU def_bool y -config GENERIC_PENDING_IRQ +config GENERIC_CSUM def_bool y - depends on GENERIC_HARDIRQS && SMP config SEMAPHORE_SLEEPERS def_bool y @@ -94,26 +106,6 @@ config HVC_TILE select HVC_DRIVER def_bool y -config TILE - def_bool y - select HAVE_KVM if !TILEGX - select GENERIC_FIND_FIRST_BIT - select GENERIC_FIND_NEXT_BIT - select USE_GENERIC_SMP_HELPERS - select CC_OPTIMIZE_FOR_SIZE - -# FIXME: investigate whether we need/want these options. -# select HAVE_IOREMAP_PROT -# select HAVE_OPTPROBES -# select HAVE_REGS_AND_STACK_ACCESS_API -# select HAVE_HW_BREAKPOINT -# select PERF_EVENTS -# select HAVE_USER_RETURN_NOTIFIER -# config NO_BOOTMEM -# config ARCH_SUPPORTS_DEBUG_PAGEALLOC -# config HUGETLB_PAGE_SIZE_VARIABLE - - # Please note: TILE-Gx support is not yet finalized; this is # the preliminary support. TILE-Gx drivers are only provided # with the alpha or beta test versions for Tilera customers. -- cgit v0.10.2 From dfff95c394b0dd977a6b65bd52b99703fae94d9b Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Wed, 19 Jan 2011 20:46:24 +0100 Subject: um: Use generic irq Kconfig No functional change. Signed-off-by: Thomas Gleixner Cc: Andrew Morton Cc: Jeff Dike diff --git a/arch/um/Kconfig.common b/arch/um/Kconfig.common index 049d048..e351e14 100644 --- a/arch/um/Kconfig.common +++ b/arch/um/Kconfig.common @@ -3,14 +3,10 @@ config DEFCONFIG_LIST option defconfig_list default "arch/$ARCH/defconfig" -# UML uses the generic IRQ subsystem -config GENERIC_HARDIRQS - bool - default y - config UML bool default y + select HAVE_GENERIC_HARDIRQS config MMU bool -- cgit v0.10.2