From c3531b4949137655056cae7b99c9885aaf145ee0 Mon Sep 17 00:00:00 2001
From: Yuantian Tang <andy.tang@nxp.com>
Date: Tue, 20 Jun 2017 16:02:34 +0800
Subject: arm64: dts: ls2088a: add cpu idle support

Signed-off-by: Tang Yuantian <andy.tang@nxp.com>

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi
index 7d26531..65677d1 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi
@@ -55,6 +55,7 @@
 		clocks = <&clockgen 1 0>;
 		next-level-cache = <&cluster0_l2>;
 		#cooling-cells = <2>;
+		cpu-idle-states = <&CPU_PH20>;
 	};
 
 	cpu1: cpu@1 {
@@ -63,6 +64,7 @@
 		reg = <0x1>;
 		clocks = <&clockgen 1 0>;
 		next-level-cache = <&cluster0_l2>;
+		cpu-idle-states = <&CPU_PH20>;
 	};
 
 	cpu2: cpu@100 {
@@ -72,6 +74,7 @@
 		clocks = <&clockgen 1 1>;
 		next-level-cache = <&cluster1_l2>;
 		#cooling-cells = <2>;
+		cpu-idle-states = <&CPU_PH20>;
 	};
 
 	cpu3: cpu@101 {
@@ -80,6 +83,7 @@
 		reg = <0x101>;
 		clocks = <&clockgen 1 1>;
 		next-level-cache = <&cluster1_l2>;
+		cpu-idle-states = <&CPU_PH20>;
 	};
 
 	cpu4: cpu@200 {
@@ -89,6 +93,7 @@
 		clocks = <&clockgen 1 2>;
 		next-level-cache = <&cluster2_l2>;
 		#cooling-cells = <2>;
+		cpu-idle-states = <&CPU_PH20>;
 	};
 
 	cpu5: cpu@201 {
@@ -97,6 +102,7 @@
 		reg = <0x201>;
 		clocks = <&clockgen 1 2>;
 		next-level-cache = <&cluster2_l2>;
+		cpu-idle-states = <&CPU_PH20>;
 	};
 
 	cpu6: cpu@300 {
@@ -106,6 +112,7 @@
 		clocks = <&clockgen 1 3>;
 		next-level-cache = <&cluster3_l2>;
 		#cooling-cells = <2>;
+		cpu-idle-states = <&CPU_PH20>;
 	};
 
 	cpu7: cpu@301 {
@@ -114,6 +121,24 @@
 		reg = <0x301>;
 		clocks = <&clockgen 1 3>;
 		next-level-cache = <&cluster3_l2>;
+		cpu-idle-states = <&CPU_PH20>;
+	};
+
+	idle-states {
+		/*
+		 * PSCI node is not added default, U-boot will add missing
+		 * parts if it determines to use PSCI.
+		 */
+		entry-method = "arm,psci";
+
+		CPU_PH20: cpu-ph20 {
+			compatible = "arm,idle-state";
+			idle-state-name = "PH20";
+			arm,psci-suspend-param = <0x00010000>;
+			entry-latency-us = <1000>;
+			exit-latency-us = <1000>;
+			min-residency-us = <3000>;
+		};
 	};
 
 	cluster0_l2: l2-cache0 {
-- 
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