From 1dbf6a81c845a748e46b4bcaf25d958038624ad8 Mon Sep 17 00:00:00 2001 From: Paul Burton Date: Wed, 3 Feb 2016 16:17:29 +0000 Subject: MIPS: Add M6250 cases to CPU switch statements Add casses supporting the M6250 CPU to various switch statements in the core MIPS kernel code that define behaviour dependent upon the CPU. Signed-off-by: Paul Burton Cc: Joshua Kinard Cc: Leonid Yegoshin Cc: Paul Gortmaker Cc: Maciej W. Rozycki Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/12374/ Signed-off-by: Ralf Baechle diff --git a/arch/mips/include/asm/cpu-type.h b/arch/mips/include/asm/cpu-type.h index 2cb0979..fbe1881 100644 --- a/arch/mips/include/asm/cpu-type.h +++ b/arch/mips/include/asm/cpu-type.h @@ -77,6 +77,10 @@ static inline int __pure __get_cpu_type(const int cpu_type) */ #endif +#ifdef CONFIG_SYS_HAS_CPU_MIPS32_R6 + case CPU_M6250: +#endif + #ifdef CONFIG_SYS_HAS_CPU_MIPS64_R6 case CPU_I6400: case CPU_P6600: diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index 729a7d4..e64d595 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c @@ -1286,6 +1286,7 @@ static void probe_pcache(void) case CPU_QEMU_GENERIC: case CPU_I6400: case CPU_P6600: + case CPU_M6250: if (!(read_c0_config7() & MIPS_CONF7_IAR) && (c->icache.waysize > PAGE_SIZE)) c->icache.flags |= MIPS_CACHE_ALIASES; -- cgit v0.10.2