From bc0c0c302925ff02fab06633ac2f732323b9e6f9 Mon Sep 17 00:00:00 2001 From: Robert Jarzmik Date: Tue, 5 Apr 2016 08:35:50 +0200 Subject: ARM: dts: pxa: add pxa framebuffer device Add the framebuffer device, or display controller, available on pxa2xx and pxa3xx platforms. Signed-off-by: Robert Jarzmik diff --git a/arch/arm/boot/dts/pxa2xx.dtsi b/arch/arm/boot/dts/pxa2xx.dtsi index 5e5af07..3ff077c 100644 --- a/arch/arm/boot/dts/pxa2xx.dtsi +++ b/arch/arm/boot/dts/pxa2xx.dtsi @@ -140,5 +140,13 @@ reg = <0x40900000 0x3c>; interrupts = <30 31>; }; + + lcd-controller@40500000 { + compatible = "marvell,pxa2xx-lcdc"; + reg = <0x44000000 0x10000>; + interrupts = <17>; + clocks = <&clks CLK_LCD>; + status = "disabled"; + }; }; }; -- cgit v0.10.2 From 85deaec8e900a98e0ab422620035803541965ef1 Mon Sep 17 00:00:00 2001 From: Robert Jarzmik Date: Tue, 5 Apr 2016 08:35:51 +0200 Subject: ARM: dts: pxa: add pxa3xx pwm nodes The pxa3xx SoC has 4 PWMs, exactly as the pxa27x does. Add them to the description. Signed-off-by: Robert Jarzmik diff --git a/arch/arm/boot/dts/pxa3xx.dtsi b/arch/arm/boot/dts/pxa3xx.dtsi index fec47bc..5767ed4 100644 --- a/arch/arm/boot/dts/pxa3xx.dtsi +++ b/arch/arm/boot/dts/pxa3xx.dtsi @@ -95,6 +95,38 @@ clocks = <&clks CLK_USBHOST>; status = "disabled"; }; + + pwm0: pwm@40b00000 { + compatible = "marvell,pxa270-pwm"; + reg = <0x40b00000 0x10>; + #pwm-cells = <1>; + clocks = <&clks CLK_PWM0>; + status = "disabled"; + }; + + pwm1: pwm@40b00010 { + compatible = "marvell,pxa270-pwm"; + reg = <0x40b00010 0x10>; + #pwm-cells = <1>; + clocks = <&clks CLK_PWM1>; + status = "disabled"; + }; + + pwm2: pwm@40c00000 { + compatible = "marvell,pxa270-pwm"; + reg = <0x40c00000 0x10>; + #pwm-cells = <1>; + clocks = <&clks CLK_PWM0>; + status = "disabled"; + }; + + pwm3: pwm@40c00010 { + compatible = "marvell,pxa270-pwm"; + reg = <0x40c00010 0x10>; + #pwm-cells = <1>; + clocks = <&clks CLK_PWM1>; + status = "disabled"; + }; }; clocks { -- cgit v0.10.2 From ca91c703aeb192d98cacf733267e0e7c256cd7b6 Mon Sep 17 00:00:00 2001 From: Robert Jarzmik Date: Tue, 5 Apr 2016 08:35:52 +0200 Subject: ARM: dts: add pincontroller to pxa27x Add the new pincontrol driver to pxa27x based boards. Signed-off-by: Robert Jarzmik diff --git a/arch/arm/boot/dts/pxa27x.dtsi b/arch/arm/boot/dts/pxa27x.dtsi index 210192c..9e73dc6 100644 --- a/arch/arm/boot/dts/pxa27x.dtsi +++ b/arch/arm/boot/dts/pxa27x.dtsi @@ -22,8 +22,15 @@ marvell,intc-nr-irqs = <34>; }; + pinctrl: pinctrl@40e00000 { + reg = <0x40e00054 0x20 0x40e0000c 0xc 0x40e0010c 4 + 0x40f00020 0x10>; + compatible = "marvell,pxa27x-pinctrl"; + }; + gpio: gpio@40e00000 { compatible = "intel,pxa27x-gpio"; + gpio-ranges = <&pinctrl 0 0 128>; clocks = <&clks CLK_NONE>; }; -- cgit v0.10.2 From aa71cc501494cef368c439dbb90cd9dba74c8d8e Mon Sep 17 00:00:00 2001 From: Robert Jarzmik Date: Tue, 5 Apr 2016 08:35:53 +0200 Subject: ARM: dts: pxa: fix the ohci clock for pxa3xx Fix the USB host clock, which is CLK_USBH. CLK_USBHOST is the clock of the usb host of pxa27x SoCs. Signed-off-by: Robert Jarzmik diff --git a/arch/arm/boot/dts/pxa3xx.dtsi b/arch/arm/boot/dts/pxa3xx.dtsi index 5767ed4..5e2dea0 100644 --- a/arch/arm/boot/dts/pxa3xx.dtsi +++ b/arch/arm/boot/dts/pxa3xx.dtsi @@ -92,7 +92,7 @@ compatible = "marvell,pxa-ohci"; reg = <0x4c000000 0x10000>; interrupts = <3>; - clocks = <&clks CLK_USBHOST>; + clocks = <&clks CLK_USBH>; status = "disabled"; }; -- cgit v0.10.2 From 3a23249e5f92042e5431643acdb310849c38c8f6 Mon Sep 17 00:00:00 2001 From: Robert Jarzmik Date: Tue, 5 Apr 2016 08:35:54 +0200 Subject: ARM: dts: pxa: add pinctrl to pxa3xx Add pincontrol to pxa3xx, based on pinconf-simple. Signed-off-by: Robert Jarzmik diff --git a/arch/arm/boot/dts/pxa3xx.dtsi b/arch/arm/boot/dts/pxa3xx.dtsi index 5e2dea0..6995b11 100644 --- a/arch/arm/boot/dts/pxa3xx.dtsi +++ b/arch/arm/boot/dts/pxa3xx.dtsi @@ -43,6 +43,15 @@ marvell,intc-nr-irqs = <56>; }; + pinctrl: pinctrl@40e10000 { + compatible = "pinconf-single"; + reg = <0x40e10000 0xffff>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x7>; + }; + gpio: gpio@40e00000 { compatible = "intel,pxa3xx-gpio"; reg = <0x40e00000 0x10000>; -- cgit v0.10.2 From fca43c3f7e6fe421194e9b21eabc72604edac16c Mon Sep 17 00:00:00 2001 From: Robert Jarzmik Date: Tue, 5 Apr 2016 08:35:55 +0200 Subject: ARM: dts: pxa3xx: add pincontrol helpers The various pxa3xx variants have a really weird pin scheme assignement, when you want the pin number relative to a known gpio pin. This change adds the various tools to ease up writing the pinmux and pinconf devicetree parts. Signed-off-by: Robert Jarzmik diff --git a/arch/arm/boot/dts/pxa3xx.dtsi b/arch/arm/boot/dts/pxa3xx.dtsi index 6995b11..9d6f3aa 100644 --- a/arch/arm/boot/dts/pxa3xx.dtsi +++ b/arch/arm/boot/dts/pxa3xx.dtsi @@ -1,6 +1,96 @@ /* The pxa3xx skeleton simply augments the 2xx version */ #include "pxa2xx.dtsi" +#define MFP_PIN_PXA300(gpio) \ + ((gpio <= 2) ? (0x00b4 + 4 * gpio) : \ + (gpio <= 26) ? (0x027c + 4 * (gpio - 3)) : \ + (gpio <= 98) ? (0x0400 + 4 * (gpio - 27)) : \ + (gpio <= 127) ? (0x0600 + 4 * (gpio - 99)) : \ + 0) + +#define MFP_PIN_PXA310(gpio) \ + ((gpio <= 2) ? (0x00b4 + 4 * gpio) : \ + (gpio <= 26) ? (0x027c + 4 * (gpio - 3)) : \ + (gpio <= 29) ? (0x0400 + 4 * (gpio - 27)) : \ + (gpio <= 98) ? (0x0418 + 4 * (gpio - 30)) : \ + (gpio <= 127) ? (0x0600 + 4 * (gpio - 99)) : \ + (gpio <= 262) ? 0 : \ + (gpio <= 268) ? (0x052c + 4 * (gpio - 263)) : \ + 0) + +#define MFP_PIN_PXA320(gpio) \ + ((gpio <= 4) ? (0x0124 + 4 * gpio) : \ + (gpio <= 9) ? (0x028c + 4 * (gpio - 5)) : \ + (gpio <= 10) ? (0x0458 + 4 * (gpio - 10)) : \ + (gpio <= 26) ? (0x02a0 + 4 * (gpio - 11)) : \ + (gpio <= 48) ? (0x0400 + 4 * (gpio - 27)) : \ + (gpio <= 62) ? (0x045c + 4 * (gpio - 49)) : \ + (gpio <= 73) ? (0x04b4 + 4 * (gpio - 63)) : \ + (gpio <= 98) ? (0x04f0 + 4 * (gpio - 74)) : \ + (gpio <= 127) ? (0x0600 + 4 * (gpio - 99)) : \ + 0) + +/* + * MFP Alternate functions for pins having a gpio. + * Example of use: pinctrl-single,pins = < MFP_PIN_PXA310(21) MFP_AF1 > + */ +#define MFP_AF0 (0 << 0) +#define MFP_AF1 (1 << 0) +#define MFP_AF2 (2 << 0) +#define MFP_AF3 (3 << 0) +#define MFP_AF4 (4 << 0) +#define MFP_AF5 (5 << 0) +#define MFP_AF6 (6 << 0) + +/* + * MFP drive strength functions for pins. + * Example of use: pinctrl-single,drive-strength = MFP_DS03X; + */ +#define MFP_DSMSK (0x7 << 10) +#define MFP_DS01X < (0x0 << 10) MFP_DSMSK > +#define MFP_DS02X < (0x1 << 10) MFP_DSMSK > +#define MFP_DS03X < (0x2 << 10) MFP_DSMSK > +#define MFP_DS04X < (0x3 << 10) MFP_DSMSK > +#define MFP_DS06X < (0x4 << 10) MFP_DSMSK > +#define MFP_DS08X < (0x5 << 10) MFP_DSMSK > +#define MFP_DS10X < (0x6 << 10) MFP_DSMSK > +#define MFP_DS13X < (0x7 << 10) MFP_DSMSK > + +/* + * MFP low power mode for pins. + * Example of use: + * pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_PULL_LOW|MFP_LPM_EDGE_FALL); + * + * Table that determines the low power modes outputs, with actual settings + * used in parentheses for don't-care values. Except for the float output, + * the configured driven and pulled levels match, so if there is a need for + * non-LPM pulled output, the same configuration could probably be used. + * + * Output value sleep_oe_n sleep_data pullup_en pulldown_en pull_sel + * (bit 7) (bit 8) (bit 14) (bit 13) (bit 15) + * + * Input 0 X(0) X(0) X(0) 0 + * Drive 0 0 0 0 X(1) 0 + * Drive 1 0 1 X(1) 0 0 + * Pull hi (1) 1 X(1) 1 0 0 + * Pull lo (0) 1 X(0) 0 1 0 + * Z (float) 1 X(0) 0 0 0 + */ +#define MFP_LPM(x) < (x) MFP_LPM_MSK > + +#define MFP_LPM_MSK 0xe1f0 +#define MFP_LPM_INPUT 0x0000 +#define MFP_LPM_DRIVE_LOW 0x2000 +#define MFP_LPM_DRIVE_HIGH 0x4100 +#define MFP_LPM_PULL_LOW 0x2080 +#define MFP_LPM_PULL_HIGH 0x4180 +#define MFP_LPM_FLOAT 0x0080 + +#define MFP_LPM_EDGE_NONE 0x0000 +#define MFP_LPM_EDGE_RISE 0x0010 +#define MFP_LPM_EDGE_FALL 0x0020 +#define MFP_LPM_EDGE_BOTH 0x0030 + / { model = "Marvell PXA3xx familiy SoC"; compatible = "marvell,pxa3xx"; -- cgit v0.10.2 From d9739aab20a147f228b883a56fa61eb4ff620419 Mon Sep 17 00:00:00 2001 From: Ulrich Hecht Date: Thu, 5 May 2016 17:31:45 +0200 Subject: ARM: dts: r8a7793: Add MMCIF0 Same as on r8a7791. Signed-off-by: Ulrich Hecht Acked-by: Geert Uytterhoeven Signed-off-by: Simon Horman diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi index 1dd6d20..76c8435 100644 --- a/arch/arm/boot/dts/r8a7793.dtsi +++ b/arch/arm/boot/dts/r8a7793.dtsi @@ -543,6 +543,19 @@ status = "disabled"; }; + mmcif0: mmc@ee200000 { + compatible = "renesas,mmcif-r8a7793", "renesas,sh-mmcif"; + reg = <0 0xee200000 0 0x80>; + interrupts = ; + clocks = <&mstp3_clks R8A7793_CLK_MMCIF0>; + dmas = <&dmac0 0xd1>, <&dmac0 0xd2>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + reg-io-width = <4>; + status = "disabled"; + max-frequency = <97500000>; + }; + scifa0: serial@e6c40000 { compatible = "renesas,scifa-r8a7793", "renesas,rcar-gen2-scifa", "renesas,scifa"; -- cgit v0.10.2 From 388e9f592c740409ffe55740771389f946796694 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 4 May 2016 10:57:56 +0200 Subject: ARM: dts: bockw: SCIF0 supports RTS/CTS hardware flow control On the BOCK-W development board, the RTS and CTS pins of the console SCIF0 are wired to the "product serial" connector. Reflect this in the DTS by adding the "uart-has-rtscts" property to the scif0 device node. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman diff --git a/arch/arm/boot/dts/r8a7778-bockw.dts b/arch/arm/boot/dts/r8a7778-bockw.dts index e0dab14..982a237 100644 --- a/arch/arm/boot/dts/r8a7778-bockw.dts +++ b/arch/arm/boot/dts/r8a7778-bockw.dts @@ -223,6 +223,7 @@ pinctrl-0 = <&scif0_pins>; pinctrl-names = "default"; + uart-has-rtscts; status = "okay"; }; -- cgit v0.10.2 From d5bb5dcc584109323c4305e5e2a570aa1fa974ce Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 4 May 2016 10:57:57 +0200 Subject: ARM: dts: kzm9g: SCIFA4 supports RTS/CTS hardware flow control On the KZM-A9-GT development board, the RTS and CTS pins of the debug console SCIFA4 are wired to the CP2102 Serial-USB bridge. Reflect this in the DTS by adding the "uart-has-rtscts" property to the scifa4 device node. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman diff --git a/arch/arm/boot/dts/sh73a0-kzm9g.dts b/arch/arm/boot/dts/sh73a0-kzm9g.dts index c2d8a08..9881adf 100644 --- a/arch/arm/boot/dts/sh73a0-kzm9g.dts +++ b/arch/arm/boot/dts/sh73a0-kzm9g.dts @@ -378,6 +378,7 @@ pinctrl-0 = <&scifa4_pins>; pinctrl-names = "default"; + uart-has-rtscts; status = "okay"; }; -- cgit v0.10.2 From 1eed15e411527e058ca6c4b4f5b691aacb608a5e Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 13 May 2016 09:38:33 +0200 Subject: ARM: dts: r8a7790: Correct unit names for cpu nodes Make the unit names for the cpu nodes match their reg properties. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index 83cf23c..3b9e98b 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -92,7 +92,7 @@ next-level-cache = <&L2_CA15>; }; - cpu4: cpu@4 { + cpu4: cpu@100 { device_type = "cpu"; compatible = "arm,cortex-a7"; reg = <0x100>; @@ -101,7 +101,7 @@ next-level-cache = <&L2_CA7>; }; - cpu5: cpu@5 { + cpu5: cpu@101 { device_type = "cpu"; compatible = "arm,cortex-a7"; reg = <0x101>; @@ -110,7 +110,7 @@ next-level-cache = <&L2_CA7>; }; - cpu6: cpu@6 { + cpu6: cpu@102 { device_type = "cpu"; compatible = "arm,cortex-a7"; reg = <0x102>; @@ -119,7 +119,7 @@ next-level-cache = <&L2_CA7>; }; - cpu7: cpu@7 { + cpu7: cpu@103 { device_type = "cpu"; compatible = "arm,cortex-a7"; reg = <0x103>; -- cgit v0.10.2 From badf8570c6377e623f7bb66aa61ab40841087977 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Niklas=20S=C3=B6derlund?= Date: Thu, 12 May 2016 10:54:42 +0200 Subject: ARM: dts: r8a7790: Reference both DMA controllers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit R-Car Gen2 have two DMA controllers, which are equivalent. Add references to both dmac0 and dmac1 so the driver can choose which one to use. Signed-off-by: Niklas Söderlund Signed-off-by: Simon Horman diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index 3b9e98b..97f4c1d 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -517,8 +517,9 @@ reg = <0 0xe6500000 0 0x425>; interrupts = ; clocks = <&mstp3_clks R8A7790_CLK_IIC0>; - dmas = <&dmac0 0x61>, <&dmac0 0x62>; - dma-names = "tx", "rx"; + dmas = <&dmac0 0x61>, <&dmac0 0x62>, + <&dmac1 0x61>, <&dmac1 0x62>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; status = "disabled"; }; @@ -530,8 +531,9 @@ reg = <0 0xe6510000 0 0x425>; interrupts = ; clocks = <&mstp3_clks R8A7790_CLK_IIC1>; - dmas = <&dmac0 0x65>, <&dmac0 0x66>; - dma-names = "tx", "rx"; + dmas = <&dmac0 0x65>, <&dmac0 0x66>, + <&dmac1 0x65>, <&dmac1 0x66>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; status = "disabled"; }; @@ -543,8 +545,9 @@ reg = <0 0xe6520000 0 0x425>; interrupts = ; clocks = <&mstp3_clks R8A7790_CLK_IIC2>; - dmas = <&dmac0 0x69>, <&dmac0 0x6a>; - dma-names = "tx", "rx"; + dmas = <&dmac0 0x69>, <&dmac0 0x6a>, + <&dmac1 0x69>, <&dmac1 0x6a>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; status = "disabled"; }; @@ -556,8 +559,9 @@ reg = <0 0xe60b0000 0 0x425>; interrupts = ; clocks = <&mstp9_clks R8A7790_CLK_IICDVFS>; - dmas = <&dmac0 0x77>, <&dmac0 0x78>; - dma-names = "tx", "rx"; + dmas = <&dmac0 0x77>, <&dmac0 0x78>, + <&dmac1 0x77>, <&dmac1 0x78>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; status = "disabled"; }; @@ -567,8 +571,9 @@ reg = <0 0xee200000 0 0x80>; interrupts = ; clocks = <&mstp3_clks R8A7790_CLK_MMCIF0>; - dmas = <&dmac0 0xd1>, <&dmac0 0xd2>; - dma-names = "tx", "rx"; + dmas = <&dmac0 0xd1>, <&dmac0 0xd2>, + <&dmac1 0xd1>, <&dmac1 0xd2>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; reg-io-width = <4>; status = "disabled"; @@ -580,8 +585,9 @@ reg = <0 0xee220000 0 0x80>; interrupts = ; clocks = <&mstp3_clks R8A7790_CLK_MMCIF1>; - dmas = <&dmac0 0xe1>, <&dmac0 0xe2>; - dma-names = "tx", "rx"; + dmas = <&dmac0 0xe1>, <&dmac0 0xe2>, + <&dmac1 0xe1>, <&dmac1 0xe2>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; reg-io-width = <4>; status = "disabled"; @@ -598,8 +604,9 @@ reg = <0 0xee100000 0 0x328>; interrupts = ; clocks = <&mstp3_clks R8A7790_CLK_SDHI0>; - dmas = <&dmac1 0xcd>, <&dmac1 0xce>; - dma-names = "tx", "rx"; + dmas = <&dmac0 0xcd>, <&dmac0 0xce>, + <&dmac1 0xcd>, <&dmac1 0xce>; + dma-names = "tx", "rx", "tx", "rx"; max-frequency = <195000000>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; status = "disabled"; @@ -610,8 +617,9 @@ reg = <0 0xee120000 0 0x328>; interrupts = ; clocks = <&mstp3_clks R8A7790_CLK_SDHI1>; - dmas = <&dmac1 0xc9>, <&dmac1 0xca>; - dma-names = "tx", "rx"; + dmas = <&dmac0 0xc9>, <&dmac0 0xca>, + <&dmac1 0xc9>, <&dmac1 0xca>; + dma-names = "tx", "rx", "tx", "rx"; max-frequency = <195000000>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; status = "disabled"; @@ -622,8 +630,9 @@ reg = <0 0xee140000 0 0x100>; interrupts = ; clocks = <&mstp3_clks R8A7790_CLK_SDHI2>; - dmas = <&dmac1 0xc1>, <&dmac1 0xc2>; - dma-names = "tx", "rx"; + dmas = <&dmac0 0xc1>, <&dmac0 0xc2>, + <&dmac1 0xc1>, <&dmac1 0xc2>; + dma-names = "tx", "rx", "tx", "rx"; max-frequency = <97500000>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; status = "disabled"; @@ -634,8 +643,9 @@ reg = <0 0xee160000 0 0x100>; interrupts = ; clocks = <&mstp3_clks R8A7790_CLK_SDHI3>; - dmas = <&dmac1 0xd3>, <&dmac1 0xd4>; - dma-names = "tx", "rx"; + dmas = <&dmac0 0xd3>, <&dmac0 0xd4>, + <&dmac1 0xd3>, <&dmac1 0xd4>; + dma-names = "tx", "rx", "tx", "rx"; max-frequency = <97500000>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; status = "disabled"; @@ -648,8 +658,9 @@ interrupts = ; clocks = <&mstp2_clks R8A7790_CLK_SCIFA0>; clock-names = "fck"; - dmas = <&dmac0 0x21>, <&dmac0 0x22>; - dma-names = "tx", "rx"; + dmas = <&dmac0 0x21>, <&dmac0 0x22>, + <&dmac1 0x21>, <&dmac1 0x22>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; status = "disabled"; }; @@ -661,8 +672,9 @@ interrupts = ; clocks = <&mstp2_clks R8A7790_CLK_SCIFA1>; clock-names = "fck"; - dmas = <&dmac0 0x25>, <&dmac0 0x26>; - dma-names = "tx", "rx"; + dmas = <&dmac0 0x25>, <&dmac0 0x26>, + <&dmac1 0x25>, <&dmac1 0x26>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; status = "disabled"; }; @@ -674,8 +686,9 @@ interrupts = ; clocks = <&mstp2_clks R8A7790_CLK_SCIFA2>; clock-names = "fck"; - dmas = <&dmac0 0x27>, <&dmac0 0x28>; - dma-names = "tx", "rx"; + dmas = <&dmac0 0x27>, <&dmac0 0x28>, + <&dmac1 0x27>, <&dmac1 0x28>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; status = "disabled"; }; @@ -687,8 +700,9 @@ interrupts = ; clocks = <&mstp2_clks R8A7790_CLK_SCIFB0>; clock-names = "fck"; - dmas = <&dmac0 0x3d>, <&dmac0 0x3e>; - dma-names = "tx", "rx"; + dmas = <&dmac0 0x3d>, <&dmac0 0x3e>, + <&dmac1 0x3d>, <&dmac1 0x3e>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; status = "disabled"; }; @@ -700,8 +714,9 @@ interrupts = ; clocks = <&mstp2_clks R8A7790_CLK_SCIFB1>; clock-names = "fck"; - dmas = <&dmac0 0x19>, <&dmac0 0x1a>; - dma-names = "tx", "rx"; + dmas = <&dmac0 0x19>, <&dmac0 0x1a>, + <&dmac1 0x19>, <&dmac1 0x1a>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; status = "disabled"; }; @@ -713,8 +728,9 @@ interrupts = ; clocks = <&mstp2_clks R8A7790_CLK_SCIFB2>; clock-names = "fck"; - dmas = <&dmac0 0x1d>, <&dmac0 0x1e>; - dma-names = "tx", "rx"; + dmas = <&dmac0 0x1d>, <&dmac0 0x1e>, + <&dmac1 0x1d>, <&dmac1 0x1e>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; status = "disabled"; }; @@ -727,8 +743,9 @@ clocks = <&mstp7_clks R8A7790_CLK_SCIF0>, <&zs_clk>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x29>, <&dmac0 0x2a>; - dma-names = "tx", "rx"; + dmas = <&dmac0 0x29>, <&dmac0 0x2a>, + <&dmac1 0x29>, <&dmac1 0x2a>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; status = "disabled"; }; @@ -741,8 +758,9 @@ clocks = <&mstp7_clks R8A7790_CLK_SCIF1>, <&zs_clk>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x2d>, <&dmac0 0x2e>; - dma-names = "tx", "rx"; + dmas = <&dmac0 0x2d>, <&dmac0 0x2e>, + <&dmac1 0x2d>, <&dmac1 0x2e>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; status = "disabled"; }; @@ -755,8 +773,9 @@ clocks = <&mstp3_clks R8A7790_CLK_SCIF2>, <&zs_clk>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x2b>, <&dmac0 0x2c>; - dma-names = "tx", "rx"; + dmas = <&dmac0 0x2b>, <&dmac0 0x2c>, + <&dmac1 0x2b>, <&dmac1 0x2c>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; status = "disabled"; }; @@ -769,8 +788,9 @@ clocks = <&mstp7_clks R8A7790_CLK_HSCIF0>, <&zs_clk>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x39>, <&dmac0 0x3a>; - dma-names = "tx", "rx"; + dmas = <&dmac0 0x39>, <&dmac0 0x3a>, + <&dmac1 0x39>, <&dmac1 0x3a>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; status = "disabled"; }; @@ -783,8 +803,9 @@ clocks = <&mstp7_clks R8A7790_CLK_HSCIF1>, <&zs_clk>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x4d>, <&dmac0 0x4e>; - dma-names = "tx", "rx"; + dmas = <&dmac0 0x4d>, <&dmac0 0x4e>, + <&dmac1 0x4d>, <&dmac1 0x4e>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; status = "disabled"; }; @@ -1469,8 +1490,9 @@ reg = <0 0xe6b10000 0 0x2c>; interrupts = ; clocks = <&mstp9_clks R8A7790_CLK_QSPI_MOD>; - dmas = <&dmac0 0x17>, <&dmac0 0x18>; - dma-names = "tx", "rx"; + dmas = <&dmac0 0x17>, <&dmac0 0x18>, + <&dmac1 0x17>, <&dmac1 0x18>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; num-cs = <1>; #address-cells = <1>; @@ -1483,8 +1505,9 @@ reg = <0 0xe6e20000 0 0x0064>; interrupts = ; clocks = <&mstp0_clks R8A7790_CLK_MSIOF0>; - dmas = <&dmac0 0x51>, <&dmac0 0x52>; - dma-names = "tx", "rx"; + dmas = <&dmac0 0x51>, <&dmac0 0x52>, + <&dmac1 0x51>, <&dmac1 0x52>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; #address-cells = <1>; #size-cells = <0>; @@ -1496,8 +1519,9 @@ reg = <0 0xe6e10000 0 0x0064>; interrupts = ; clocks = <&mstp2_clks R8A7790_CLK_MSIOF1>; - dmas = <&dmac0 0x55>, <&dmac0 0x56>; - dma-names = "tx", "rx"; + dmas = <&dmac0 0x55>, <&dmac0 0x56>, + <&dmac1 0x55>, <&dmac1 0x56>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; #address-cells = <1>; #size-cells = <0>; @@ -1509,8 +1533,9 @@ reg = <0 0xe6e00000 0 0x0064>; interrupts = ; clocks = <&mstp2_clks R8A7790_CLK_MSIOF2>; - dmas = <&dmac0 0x41>, <&dmac0 0x42>; - dma-names = "tx", "rx"; + dmas = <&dmac0 0x41>, <&dmac0 0x42>, + <&dmac1 0x41>, <&dmac1 0x42>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; #address-cells = <1>; #size-cells = <0>; @@ -1522,8 +1547,9 @@ reg = <0 0xe6c90000 0 0x0064>; interrupts = ; clocks = <&mstp2_clks R8A7790_CLK_MSIOF3>; - dmas = <&dmac0 0x45>, <&dmac0 0x46>; - dma-names = "tx", "rx"; + dmas = <&dmac0 0x45>, <&dmac0 0x46>, + <&dmac1 0x45>, <&dmac1 0x46>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; #address-cells = <1>; #size-cells = <0>; -- cgit v0.10.2 From 4aed4c9f01e1112d88ec82e666febe49715e5f33 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Niklas=20S=C3=B6derlund?= Date: Thu, 12 May 2016 10:54:43 +0200 Subject: ARM: dts: r8a7791: Reference both DMA controllers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit R-Car Gen2 have two DMA controllers, which are equivalent. Add references to both dmac0 and dmac1 so the driver can choose which one to use. Signed-off-by: Niklas Söderlund Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi index db67e34..2f92414 100644 --- a/arch/arm/boot/dts/r8a7791.dtsi +++ b/arch/arm/boot/dts/r8a7791.dtsi @@ -514,8 +514,9 @@ reg = <0 0xe60b0000 0 0x425>; interrupts = ; clocks = <&mstp9_clks R8A7791_CLK_IICDVFS>; - dmas = <&dmac0 0x77>, <&dmac0 0x78>; - dma-names = "tx", "rx"; + dmas = <&dmac0 0x77>, <&dmac0 0x78>, + <&dmac1 0x77>, <&dmac1 0x78>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; status = "disabled"; }; @@ -527,8 +528,9 @@ reg = <0 0xe6500000 0 0x425>; interrupts = ; clocks = <&mstp3_clks R8A7791_CLK_IIC0>; - dmas = <&dmac0 0x61>, <&dmac0 0x62>; - dma-names = "tx", "rx"; + dmas = <&dmac0 0x61>, <&dmac0 0x62>, + <&dmac1 0x61>, <&dmac1 0x62>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; status = "disabled"; }; @@ -540,8 +542,9 @@ reg = <0 0xe6510000 0 0x425>; interrupts = ; clocks = <&mstp3_clks R8A7791_CLK_IIC1>; - dmas = <&dmac0 0x65>, <&dmac0 0x66>; - dma-names = "tx", "rx"; + dmas = <&dmac0 0x65>, <&dmac0 0x66>, + <&dmac1 0x65>, <&dmac1 0x66>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; status = "disabled"; }; @@ -556,8 +559,9 @@ reg = <0 0xee200000 0 0x80>; interrupts = ; clocks = <&mstp3_clks R8A7791_CLK_MMCIF0>; - dmas = <&dmac0 0xd1>, <&dmac0 0xd2>; - dma-names = "tx", "rx"; + dmas = <&dmac0 0xd1>, <&dmac0 0xd2>, + <&dmac1 0xd1>, <&dmac1 0xd2>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; reg-io-width = <4>; status = "disabled"; @@ -569,8 +573,9 @@ reg = <0 0xee100000 0 0x328>; interrupts = ; clocks = <&mstp3_clks R8A7791_CLK_SDHI0>; - dmas = <&dmac1 0xcd>, <&dmac1 0xce>; - dma-names = "tx", "rx"; + dmas = <&dmac0 0xcd>, <&dmac0 0xce>, + <&dmac1 0xcd>, <&dmac1 0xce>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; status = "disabled"; }; @@ -580,8 +585,9 @@ reg = <0 0xee140000 0 0x100>; interrupts = ; clocks = <&mstp3_clks R8A7791_CLK_SDHI1>; - dmas = <&dmac1 0xc1>, <&dmac1 0xc2>; - dma-names = "tx", "rx"; + dmas = <&dmac0 0xc1>, <&dmac0 0xc2>, + <&dmac1 0xc1>, <&dmac1 0xc2>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; status = "disabled"; }; @@ -591,8 +597,9 @@ reg = <0 0xee160000 0 0x100>; interrupts = ; clocks = <&mstp3_clks R8A7791_CLK_SDHI2>; - dmas = <&dmac1 0xd3>, <&dmac1 0xd4>; - dma-names = "tx", "rx"; + dmas = <&dmac0 0xd3>, <&dmac0 0xd4>, + <&dmac1 0xd3>, <&dmac1 0xd4>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; status = "disabled"; }; @@ -604,8 +611,9 @@ interrupts = ; clocks = <&mstp2_clks R8A7791_CLK_SCIFA0>; clock-names = "fck"; - dmas = <&dmac0 0x21>, <&dmac0 0x22>; - dma-names = "tx", "rx"; + dmas = <&dmac0 0x21>, <&dmac0 0x22>, + <&dmac1 0x21>, <&dmac1 0x22>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; status = "disabled"; }; @@ -617,8 +625,9 @@ interrupts = ; clocks = <&mstp2_clks R8A7791_CLK_SCIFA1>; clock-names = "fck"; - dmas = <&dmac0 0x25>, <&dmac0 0x26>; - dma-names = "tx", "rx"; + dmas = <&dmac0 0x25>, <&dmac0 0x26>, + <&dmac1 0x25>, <&dmac1 0x26>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; status = "disabled"; }; @@ -630,8 +639,9 @@ interrupts = ; clocks = <&mstp2_clks R8A7791_CLK_SCIFA2>; clock-names = "fck"; - dmas = <&dmac0 0x27>, <&dmac0 0x28>; - dma-names = "tx", "rx"; + dmas = <&dmac0 0x27>, <&dmac0 0x28>, + <&dmac1 0x27>, <&dmac1 0x28>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; status = "disabled"; }; @@ -643,8 +653,9 @@ interrupts = ; clocks = <&mstp11_clks R8A7791_CLK_SCIFA3>; clock-names = "fck"; - dmas = <&dmac0 0x1b>, <&dmac0 0x1c>; - dma-names = "tx", "rx"; + dmas = <&dmac0 0x1b>, <&dmac0 0x1c>, + <&dmac1 0x1b>, <&dmac1 0x1c>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; status = "disabled"; }; @@ -656,8 +667,9 @@ interrupts = ; clocks = <&mstp11_clks R8A7791_CLK_SCIFA4>; clock-names = "fck"; - dmas = <&dmac0 0x1f>, <&dmac0 0x20>; - dma-names = "tx", "rx"; + dmas = <&dmac0 0x1f>, <&dmac0 0x20>, + <&dmac1 0x1f>, <&dmac1 0x20>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; status = "disabled"; }; @@ -669,8 +681,9 @@ interrupts = ; clocks = <&mstp11_clks R8A7791_CLK_SCIFA5>; clock-names = "fck"; - dmas = <&dmac0 0x23>, <&dmac0 0x24>; - dma-names = "tx", "rx"; + dmas = <&dmac0 0x23>, <&dmac0 0x24>, + <&dmac1 0x23>, <&dmac1 0x24>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; status = "disabled"; }; @@ -682,8 +695,9 @@ interrupts = ; clocks = <&mstp2_clks R8A7791_CLK_SCIFB0>; clock-names = "fck"; - dmas = <&dmac0 0x3d>, <&dmac0 0x3e>; - dma-names = "tx", "rx"; + dmas = <&dmac0 0x3d>, <&dmac0 0x3e>, + <&dmac1 0x3d>, <&dmac1 0x3e>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; status = "disabled"; }; @@ -695,8 +709,9 @@ interrupts = ; clocks = <&mstp2_clks R8A7791_CLK_SCIFB1>; clock-names = "fck"; - dmas = <&dmac0 0x19>, <&dmac0 0x1a>; - dma-names = "tx", "rx"; + dmas = <&dmac0 0x19>, <&dmac0 0x1a>, + <&dmac1 0x19>, <&dmac1 0x1a>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; status = "disabled"; }; @@ -708,8 +723,9 @@ interrupts = ; clocks = <&mstp2_clks R8A7791_CLK_SCIFB2>; clock-names = "fck"; - dmas = <&dmac0 0x1d>, <&dmac0 0x1e>; - dma-names = "tx", "rx"; + dmas = <&dmac0 0x1d>, <&dmac0 0x1e>, + <&dmac1 0x1d>, <&dmac1 0x1e>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; status = "disabled"; }; @@ -722,8 +738,9 @@ clocks = <&mstp7_clks R8A7791_CLK_SCIF0>, <&zs_clk>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x29>, <&dmac0 0x2a>; - dma-names = "tx", "rx"; + dmas = <&dmac0 0x29>, <&dmac0 0x2a>, + <&dmac1 0x29>, <&dmac1 0x2a>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; status = "disabled"; }; @@ -736,8 +753,9 @@ clocks = <&mstp7_clks R8A7791_CLK_SCIF1>, <&zs_clk>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x2d>, <&dmac0 0x2e>; - dma-names = "tx", "rx"; + dmas = <&dmac0 0x2d>, <&dmac0 0x2e>, + <&dmac1 0x2d>, <&dmac1 0x2e>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; status = "disabled"; }; @@ -750,8 +768,9 @@ clocks = <&mstp7_clks R8A7791_CLK_SCIF2>, <&zs_clk>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x2b>, <&dmac0 0x2c>; - dma-names = "tx", "rx"; + dmas = <&dmac0 0x2b>, <&dmac0 0x2c>, + <&dmac1 0x2b>, <&dmac1 0x2c>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; status = "disabled"; }; @@ -764,8 +783,9 @@ clocks = <&mstp7_clks R8A7791_CLK_SCIF3>, <&zs_clk>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x2f>, <&dmac0 0x30>; - dma-names = "tx", "rx"; + dmas = <&dmac0 0x2f>, <&dmac0 0x30>, + <&dmac1 0x2f>, <&dmac1 0x30>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; status = "disabled"; }; @@ -778,8 +798,9 @@ clocks = <&mstp7_clks R8A7791_CLK_SCIF4>, <&zs_clk>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0xfb>, <&dmac0 0xfc>; - dma-names = "tx", "rx"; + dmas = <&dmac0 0xfb>, <&dmac0 0xfc>, + <&dmac1 0xfb>, <&dmac1 0xfc>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; status = "disabled"; }; @@ -792,8 +813,9 @@ clocks = <&mstp7_clks R8A7791_CLK_SCIF5>, <&zs_clk>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0xfd>, <&dmac0 0xfe>; - dma-names = "tx", "rx"; + dmas = <&dmac0 0xfd>, <&dmac0 0xfe>, + <&dmac1 0xfd>, <&dmac1 0xfe>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; status = "disabled"; }; @@ -806,8 +828,9 @@ clocks = <&mstp7_clks R8A7791_CLK_HSCIF0>, <&zs_clk>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x39>, <&dmac0 0x3a>; - dma-names = "tx", "rx"; + dmas = <&dmac0 0x39>, <&dmac0 0x3a>, + <&dmac1 0x39>, <&dmac1 0x3a>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; status = "disabled"; }; @@ -820,8 +843,9 @@ clocks = <&mstp7_clks R8A7791_CLK_HSCIF1>, <&zs_clk>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x4d>, <&dmac0 0x4e>; - dma-names = "tx", "rx"; + dmas = <&dmac0 0x4d>, <&dmac0 0x4e>, + <&dmac1 0x4d>, <&dmac1 0x4e>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; status = "disabled"; }; @@ -834,8 +858,9 @@ clocks = <&mstp7_clks R8A7791_CLK_HSCIF2>, <&zs_clk>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x3b>, <&dmac0 0x3c>; - dma-names = "tx", "rx"; + dmas = <&dmac0 0x3b>, <&dmac0 0x3c>, + <&dmac1 0x3b>, <&dmac1 0x3c>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; status = "disabled"; }; @@ -1478,8 +1503,9 @@ reg = <0 0xe6b10000 0 0x2c>; interrupts = ; clocks = <&mstp9_clks R8A7791_CLK_QSPI_MOD>; - dmas = <&dmac0 0x17>, <&dmac0 0x18>; - dma-names = "tx", "rx"; + dmas = <&dmac0 0x17>, <&dmac0 0x18>, + <&dmac1 0x17>, <&dmac1 0x18>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; num-cs = <1>; #address-cells = <1>; @@ -1492,8 +1518,9 @@ reg = <0 0xe6e20000 0 0x0064>; interrupts = ; clocks = <&mstp0_clks R8A7791_CLK_MSIOF0>; - dmas = <&dmac0 0x51>, <&dmac0 0x52>; - dma-names = "tx", "rx"; + dmas = <&dmac0 0x51>, <&dmac0 0x52>, + <&dmac1 0x51>, <&dmac1 0x52>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; #address-cells = <1>; #size-cells = <0>; @@ -1505,8 +1532,9 @@ reg = <0 0xe6e10000 0 0x0064>; interrupts = ; clocks = <&mstp2_clks R8A7791_CLK_MSIOF1>; - dmas = <&dmac0 0x55>, <&dmac0 0x56>; - dma-names = "tx", "rx"; + dmas = <&dmac0 0x55>, <&dmac0 0x56>, + <&dmac1 0x55>, <&dmac1 0x56>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; #address-cells = <1>; #size-cells = <0>; @@ -1518,8 +1546,9 @@ reg = <0 0xe6e00000 0 0x0064>; interrupts = ; clocks = <&mstp2_clks R8A7791_CLK_MSIOF2>; - dmas = <&dmac0 0x41>, <&dmac0 0x42>; - dma-names = "tx", "rx"; + dmas = <&dmac0 0x41>, <&dmac0 0x42>, + <&dmac1 0x41>, <&dmac1 0x42>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; #address-cells = <1>; #size-cells = <0>; -- cgit v0.10.2 From a858cd49fe1b040a8f46066ede17464a31f890b1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Niklas=20S=C3=B6derlund?= Date: Thu, 12 May 2016 10:54:44 +0200 Subject: ARM: dts: r8a7793: Reference both DMA controllers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit R-Car Gen2 have two DMA controllers, which are equivalent. Add references to both dmac0 and dmac1 so the driver can choose which one to use. Signed-off-by: Niklas Söderlund Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi index 76c8435..5f50e9b 100644 --- a/arch/arm/boot/dts/r8a7793.dtsi +++ b/arch/arm/boot/dts/r8a7793.dtsi @@ -473,8 +473,9 @@ reg = <0 0xe60b0000 0 0x425>; interrupts = ; clocks = <&mstp9_clks R8A7793_CLK_IICDVFS>; - dmas = <&dmac0 0x77>, <&dmac0 0x78>; - dma-names = "tx", "rx"; + dmas = <&dmac0 0x77>, <&dmac0 0x78>, + <&dmac1 0x77>, <&dmac1 0x78>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; status = "disabled"; }; @@ -486,8 +487,9 @@ reg = <0 0xe6500000 0 0x425>; interrupts = ; clocks = <&mstp3_clks R8A7793_CLK_IIC0>; - dmas = <&dmac0 0x61>, <&dmac0 0x62>; - dma-names = "tx", "rx"; + dmas = <&dmac0 0x61>, <&dmac0 0x62>, + <&dmac1 0x61>, <&dmac1 0x62>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; status = "disabled"; }; @@ -499,8 +501,9 @@ reg = <0 0xe6510000 0 0x425>; interrupts = ; clocks = <&mstp3_clks R8A7793_CLK_IIC1>; - dmas = <&dmac0 0x65>, <&dmac0 0x66>; - dma-names = "tx", "rx"; + dmas = <&dmac0 0x65>, <&dmac0 0x66>, + <&dmac1 0x65>, <&dmac1 0x66>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; status = "disabled"; }; @@ -515,8 +518,9 @@ reg = <0 0xee100000 0 0x328>; interrupts = ; clocks = <&mstp3_clks R8A7793_CLK_SDHI0>; - dmas = <&dmac0 0xcd>, <&dmac0 0xce>; - dma-names = "tx", "rx"; + dmas = <&dmac0 0xcd>, <&dmac0 0xce>, + <&dmac1 0xcd>, <&dmac1 0xce>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; status = "disabled"; }; @@ -526,8 +530,9 @@ reg = <0 0xee140000 0 0x100>; interrupts = ; clocks = <&mstp3_clks R8A7793_CLK_SDHI1>; - dmas = <&dmac0 0xc1>, <&dmac0 0xc2>; - dma-names = "tx", "rx"; + dmas = <&dmac0 0xc1>, <&dmac0 0xc2>, + <&dmac1 0xc1>, <&dmac1 0xc2>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; status = "disabled"; }; @@ -537,8 +542,9 @@ reg = <0 0xee160000 0 0x100>; interrupts = ; clocks = <&mstp3_clks R8A7793_CLK_SDHI2>; - dmas = <&dmac0 0xd3>, <&dmac0 0xd4>; - dma-names = "tx", "rx"; + dmas = <&dmac0 0xd3>, <&dmac0 0xd4>, + <&dmac1 0xd3>, <&dmac1 0xd4>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; status = "disabled"; }; @@ -548,8 +554,9 @@ reg = <0 0xee200000 0 0x80>; interrupts = ; clocks = <&mstp3_clks R8A7793_CLK_MMCIF0>; - dmas = <&dmac0 0xd1>, <&dmac0 0xd2>; - dma-names = "tx", "rx"; + dmas = <&dmac0 0xd1>, <&dmac0 0xd2>, + <&dmac1 0xd1>, <&dmac1 0xd2>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; reg-io-width = <4>; status = "disabled"; @@ -563,8 +570,9 @@ interrupts = ; clocks = <&mstp2_clks R8A7793_CLK_SCIFA0>; clock-names = "fck"; - dmas = <&dmac0 0x21>, <&dmac0 0x22>; - dma-names = "tx", "rx"; + dmas = <&dmac0 0x21>, <&dmac0 0x22>, + <&dmac1 0x21>, <&dmac1 0x22>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; status = "disabled"; }; @@ -576,8 +584,9 @@ interrupts = ; clocks = <&mstp2_clks R8A7793_CLK_SCIFA1>; clock-names = "fck"; - dmas = <&dmac0 0x25>, <&dmac0 0x26>; - dma-names = "tx", "rx"; + dmas = <&dmac0 0x25>, <&dmac0 0x26>, + <&dmac1 0x25>, <&dmac1 0x26>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; status = "disabled"; }; @@ -589,8 +598,9 @@ interrupts = ; clocks = <&mstp2_clks R8A7793_CLK_SCIFA2>; clock-names = "fck"; - dmas = <&dmac0 0x27>, <&dmac0 0x28>; - dma-names = "tx", "rx"; + dmas = <&dmac0 0x27>, <&dmac0 0x28>, + <&dmac1 0x27>, <&dmac1 0x28>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; status = "disabled"; }; @@ -602,8 +612,9 @@ interrupts = ; clocks = <&mstp11_clks R8A7793_CLK_SCIFA3>; clock-names = "fck"; - dmas = <&dmac0 0x1b>, <&dmac0 0x1c>; - dma-names = "tx", "rx"; + dmas = <&dmac0 0x1b>, <&dmac0 0x1c>, + <&dmac1 0x1b>, <&dmac1 0x1c>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; status = "disabled"; }; @@ -615,8 +626,9 @@ interrupts = ; clocks = <&mstp11_clks R8A7793_CLK_SCIFA4>; clock-names = "fck"; - dmas = <&dmac0 0x1f>, <&dmac0 0x20>; - dma-names = "tx", "rx"; + dmas = <&dmac0 0x1f>, <&dmac0 0x20>, + <&dmac1 0x1f>, <&dmac1 0x20>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; status = "disabled"; }; @@ -628,8 +640,9 @@ interrupts = ; clocks = <&mstp11_clks R8A7793_CLK_SCIFA5>; clock-names = "fck"; - dmas = <&dmac0 0x23>, <&dmac0 0x24>; - dma-names = "tx", "rx"; + dmas = <&dmac0 0x23>, <&dmac0 0x24>, + <&dmac1 0x23>, <&dmac1 0x24>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; status = "disabled"; }; @@ -641,8 +654,9 @@ interrupts = ; clocks = <&mstp2_clks R8A7793_CLK_SCIFB0>; clock-names = "fck"; - dmas = <&dmac0 0x3d>, <&dmac0 0x3e>; - dma-names = "tx", "rx"; + dmas = <&dmac0 0x3d>, <&dmac0 0x3e>, + <&dmac1 0x3d>, <&dmac1 0x3e>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; status = "disabled"; }; @@ -654,8 +668,9 @@ interrupts = ; clocks = <&mstp2_clks R8A7793_CLK_SCIFB1>; clock-names = "fck"; - dmas = <&dmac0 0x19>, <&dmac0 0x1a>; - dma-names = "tx", "rx"; + dmas = <&dmac0 0x19>, <&dmac0 0x1a>, + <&dmac1 0x19>, <&dmac1 0x1a>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; status = "disabled"; }; @@ -667,8 +682,9 @@ interrupts = ; clocks = <&mstp2_clks R8A7793_CLK_SCIFB2>; clock-names = "fck"; - dmas = <&dmac0 0x1d>, <&dmac0 0x1e>; - dma-names = "tx", "rx"; + dmas = <&dmac0 0x1d>, <&dmac0 0x1e>, + <&dmac1 0x1d>, <&dmac1 0x1e>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; status = "disabled"; }; @@ -681,8 +697,9 @@ clocks = <&mstp7_clks R8A7793_CLK_SCIF0>, <&zs_clk>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x29>, <&dmac0 0x2a>; - dma-names = "tx", "rx"; + dmas = <&dmac0 0x29>, <&dmac0 0x2a>, + <&dmac1 0x29>, <&dmac1 0x2a>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; status = "disabled"; }; @@ -695,8 +712,9 @@ clocks = <&mstp7_clks R8A7793_CLK_SCIF1>, <&zs_clk>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x2d>, <&dmac0 0x2e>; - dma-names = "tx", "rx"; + dmas = <&dmac0 0x2d>, <&dmac0 0x2e>, + <&dmac1 0x2d>, <&dmac1 0x2e>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; status = "disabled"; }; @@ -709,8 +727,9 @@ clocks = <&mstp7_clks R8A7793_CLK_SCIF2>, <&zs_clk>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x2b>, <&dmac0 0x2c>; - dma-names = "tx", "rx"; + dmas = <&dmac0 0x2b>, <&dmac0 0x2c>, + <&dmac1 0x2b>, <&dmac1 0x2c>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; status = "disabled"; }; @@ -723,8 +742,9 @@ clocks = <&mstp7_clks R8A7793_CLK_SCIF3>, <&zs_clk>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x2f>, <&dmac0 0x30>; - dma-names = "tx", "rx"; + dmas = <&dmac0 0x2f>, <&dmac0 0x30>, + <&dmac1 0x2f>, <&dmac1 0x30>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; status = "disabled"; }; @@ -737,8 +757,9 @@ clocks = <&mstp7_clks R8A7793_CLK_SCIF4>, <&zs_clk>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0xfb>, <&dmac0 0xfc>; - dma-names = "tx", "rx"; + dmas = <&dmac0 0xfb>, <&dmac0 0xfc>, + <&dmac1 0xfb>, <&dmac1 0xfc>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; status = "disabled"; }; @@ -751,8 +772,9 @@ clocks = <&mstp7_clks R8A7793_CLK_SCIF5>, <&zs_clk>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0xfd>, <&dmac0 0xfe>; - dma-names = "tx", "rx"; + dmas = <&dmac0 0xfd>, <&dmac0 0xfe>, + <&dmac1 0xfd>, <&dmac1 0xfe>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; status = "disabled"; }; @@ -765,8 +787,9 @@ clocks = <&mstp7_clks R8A7793_CLK_HSCIF0>, <&zs_clk>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x39>, <&dmac0 0x3a>; - dma-names = "tx", "rx"; + dmas = <&dmac0 0x39>, <&dmac0 0x3a>, + <&dmac1 0x39>, <&dmac1 0x3a>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; status = "disabled"; }; @@ -779,8 +802,9 @@ clocks = <&mstp7_clks R8A7793_CLK_HSCIF1>, <&zs_clk>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x4d>, <&dmac0 0x4e>; - dma-names = "tx", "rx"; + dmas = <&dmac0 0x4d>, <&dmac0 0x4e>, + <&dmac1 0x4d>, <&dmac1 0x4e>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; status = "disabled"; }; @@ -793,8 +817,9 @@ clocks = <&mstp7_clks R8A7793_CLK_HSCIF2>, <&zs_clk>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x3b>, <&dmac0 0x3c>; - dma-names = "tx", "rx"; + dmas = <&dmac0 0x3b>, <&dmac0 0x3c>, + <&dmac1 0x3b>, <&dmac1 0x3c>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; status = "disabled"; }; @@ -816,8 +841,9 @@ reg = <0 0xe6b10000 0 0x2c>; interrupts = ; clocks = <&mstp9_clks R8A7793_CLK_QSPI_MOD>; - dmas = <&dmac0 0x17>, <&dmac0 0x18>; - dma-names = "tx", "rx"; + dmas = <&dmac0 0x17>, <&dmac0 0x18>, + <&dmac1 0x17>, <&dmac1 0x18>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; num-cs = <1>; #address-cells = <1>; -- cgit v0.10.2 From b38605e9aae22c291b0033f93c8f4ffeb14f0806 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Niklas=20S=C3=B6derlund?= Date: Thu, 12 May 2016 10:54:45 +0200 Subject: ARM: dts: r8a7794: Reference both DMA controllers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit R-Car Gen2 have two DMA controllers, which are equivalent. Add references to both dmac0 and dmac1 so the driver can choose which one to use. Signed-off-by: Niklas Söderlund Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi index f334a3a..ad1df83 100644 --- a/arch/arm/boot/dts/r8a7794.dtsi +++ b/arch/arm/boot/dts/r8a7794.dtsi @@ -302,8 +302,9 @@ interrupts = ; clocks = <&mstp2_clks R8A7794_CLK_SCIFA0>; clock-names = "fck"; - dmas = <&dmac0 0x21>, <&dmac0 0x22>; - dma-names = "tx", "rx"; + dmas = <&dmac0 0x21>, <&dmac0 0x22>, + <&dmac1 0x21>, <&dmac1 0x22>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; status = "disabled"; }; @@ -315,8 +316,9 @@ interrupts = ; clocks = <&mstp2_clks R8A7794_CLK_SCIFA1>; clock-names = "fck"; - dmas = <&dmac0 0x25>, <&dmac0 0x26>; - dma-names = "tx", "rx"; + dmas = <&dmac0 0x25>, <&dmac0 0x26>, + <&dmac1 0x25>, <&dmac1 0x26>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; status = "disabled"; }; @@ -328,8 +330,9 @@ interrupts = ; clocks = <&mstp2_clks R8A7794_CLK_SCIFA2>; clock-names = "fck"; - dmas = <&dmac0 0x27>, <&dmac0 0x28>; - dma-names = "tx", "rx"; + dmas = <&dmac0 0x27>, <&dmac0 0x28>, + <&dmac1 0x27>, <&dmac1 0x28>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; status = "disabled"; }; @@ -341,8 +344,9 @@ interrupts = ; clocks = <&mstp11_clks R8A7794_CLK_SCIFA3>; clock-names = "fck"; - dmas = <&dmac0 0x1b>, <&dmac0 0x1c>; - dma-names = "tx", "rx"; + dmas = <&dmac0 0x1b>, <&dmac0 0x1c>, + <&dmac1 0x1b>, <&dmac1 0x1c>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; status = "disabled"; }; @@ -354,8 +358,9 @@ interrupts = ; clocks = <&mstp11_clks R8A7794_CLK_SCIFA4>; clock-names = "fck"; - dmas = <&dmac0 0x1f>, <&dmac0 0x20>; - dma-names = "tx", "rx"; + dmas = <&dmac0 0x1f>, <&dmac0 0x20>, + <&dmac1 0x1f>, <&dmac1 0x20>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; status = "disabled"; }; @@ -367,8 +372,9 @@ interrupts = ; clocks = <&mstp11_clks R8A7794_CLK_SCIFA5>; clock-names = "fck"; - dmas = <&dmac0 0x23>, <&dmac0 0x24>; - dma-names = "tx", "rx"; + dmas = <&dmac0 0x23>, <&dmac0 0x24>, + <&dmac1 0x23>, <&dmac1 0x24>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; status = "disabled"; }; @@ -380,8 +386,9 @@ interrupts = ; clocks = <&mstp2_clks R8A7794_CLK_SCIFB0>; clock-names = "fck"; - dmas = <&dmac0 0x3d>, <&dmac0 0x3e>; - dma-names = "tx", "rx"; + dmas = <&dmac0 0x3d>, <&dmac0 0x3e>, + <&dmac1 0x3d>, <&dmac1 0x3e>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; status = "disabled"; }; @@ -393,8 +400,9 @@ interrupts = ; clocks = <&mstp2_clks R8A7794_CLK_SCIFB1>; clock-names = "fck"; - dmas = <&dmac0 0x19>, <&dmac0 0x1a>; - dma-names = "tx", "rx"; + dmas = <&dmac0 0x19>, <&dmac0 0x1a>, + <&dmac1 0x19>, <&dmac1 0x1a>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; status = "disabled"; }; @@ -406,8 +414,9 @@ interrupts = ; clocks = <&mstp2_clks R8A7794_CLK_SCIFB2>; clock-names = "fck"; - dmas = <&dmac0 0x1d>, <&dmac0 0x1e>; - dma-names = "tx", "rx"; + dmas = <&dmac0 0x1d>, <&dmac0 0x1e>, + <&dmac1 0x1d>, <&dmac1 0x1e>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; status = "disabled"; }; @@ -420,8 +429,9 @@ clocks = <&mstp7_clks R8A7794_CLK_SCIF0>, <&zs_clk>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x29>, <&dmac0 0x2a>; - dma-names = "tx", "rx"; + dmas = <&dmac0 0x29>, <&dmac0 0x2a>, + <&dmac1 0x29>, <&dmac1 0x2a>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; status = "disabled"; }; @@ -434,8 +444,9 @@ clocks = <&mstp7_clks R8A7794_CLK_SCIF1>, <&zs_clk>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x2d>, <&dmac0 0x2e>; - dma-names = "tx", "rx"; + dmas = <&dmac0 0x2d>, <&dmac0 0x2e>, + <&dmac1 0x2d>, <&dmac1 0x2e>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; status = "disabled"; }; @@ -448,8 +459,9 @@ clocks = <&mstp7_clks R8A7794_CLK_SCIF2>, <&zs_clk>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x2b>, <&dmac0 0x2c>; - dma-names = "tx", "rx"; + dmas = <&dmac0 0x2b>, <&dmac0 0x2c>, + <&dmac1 0x2b>, <&dmac1 0x2c>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; status = "disabled"; }; @@ -462,8 +474,9 @@ clocks = <&mstp7_clks R8A7794_CLK_SCIF3>, <&zs_clk>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x2f>, <&dmac0 0x30>; - dma-names = "tx", "rx"; + dmas = <&dmac0 0x2f>, <&dmac0 0x30>, + <&dmac1 0x2f>, <&dmac1 0x30>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; status = "disabled"; }; @@ -476,8 +489,9 @@ clocks = <&mstp7_clks R8A7794_CLK_SCIF4>, <&zs_clk>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0xfb>, <&dmac0 0xfc>; - dma-names = "tx", "rx"; + dmas = <&dmac0 0xfb>, <&dmac0 0xfc>, + <&dmac1 0xfb>, <&dmac1 0xfc>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; status = "disabled"; }; @@ -490,8 +504,9 @@ clocks = <&mstp7_clks R8A7794_CLK_SCIF5>, <&zs_clk>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0xfd>, <&dmac0 0xfe>; - dma-names = "tx", "rx"; + dmas = <&dmac0 0xfd>, <&dmac0 0xfe>, + <&dmac1 0xfd>, <&dmac1 0xfe>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; status = "disabled"; }; @@ -504,8 +519,9 @@ clocks = <&mstp7_clks R8A7794_CLK_HSCIF0>, <&zs_clk>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x39>, <&dmac0 0x3a>; - dma-names = "tx", "rx"; + dmas = <&dmac0 0x39>, <&dmac0 0x3a>, + <&dmac1 0x39>, <&dmac1 0x3a>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; status = "disabled"; }; @@ -518,8 +534,9 @@ clocks = <&mstp7_clks R8A7794_CLK_HSCIF1>, <&zs_clk>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x4d>, <&dmac0 0x4e>; - dma-names = "tx", "rx"; + dmas = <&dmac0 0x4d>, <&dmac0 0x4e>, + <&dmac1 0x4d>, <&dmac1 0x4e>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; status = "disabled"; }; @@ -532,8 +549,9 @@ clocks = <&mstp7_clks R8A7794_CLK_HSCIF2>, <&zs_clk>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x3b>, <&dmac0 0x3c>; - dma-names = "tx", "rx"; + dmas = <&dmac0 0x3b>, <&dmac0 0x3c>, + <&dmac1 0x3b>, <&dmac1 0x3c>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; status = "disabled"; }; @@ -640,8 +658,9 @@ reg = <0 0xe6500000 0 0x425>; interrupts = ; clocks = <&mstp3_clks R8A7794_CLK_IIC0>; - dmas = <&dmac0 0x61>, <&dmac0 0x62>; - dma-names = "tx", "rx"; + dmas = <&dmac0 0x61>, <&dmac0 0x62>, + <&dmac1 0x61>, <&dmac1 0x62>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; #address-cells = <1>; #size-cells = <0>; @@ -653,8 +672,9 @@ reg = <0 0xe6510000 0 0x425>; interrupts = ; clocks = <&mstp3_clks R8A7794_CLK_IIC1>; - dmas = <&dmac0 0x65>, <&dmac0 0x66>; - dma-names = "tx", "rx"; + dmas = <&dmac0 0x65>, <&dmac0 0x66>, + <&dmac1 0x65>, <&dmac1 0x66>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; #address-cells = <1>; #size-cells = <0>; @@ -666,8 +686,9 @@ reg = <0 0xee200000 0 0x80>; interrupts = ; clocks = <&mstp3_clks R8A7794_CLK_MMCIF0>; - dmas = <&dmac0 0xd1>, <&dmac0 0xd2>; - dma-names = "tx", "rx"; + dmas = <&dmac0 0xd1>, <&dmac0 0xd2>, + <&dmac1 0xd1>, <&dmac1 0xd2>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; reg-io-width = <4>; status = "disabled"; @@ -678,6 +699,9 @@ reg = <0 0xee100000 0 0x200>; interrupts = ; clocks = <&mstp3_clks R8A7794_CLK_SDHI0>; + dmas = <&dmac0 0xcd>, <&dmac0 0xce>, + <&dmac1 0xcd>, <&dmac1 0xce>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; status = "disabled"; }; @@ -687,6 +711,9 @@ reg = <0 0xee140000 0 0x100>; interrupts = ; clocks = <&mstp3_clks R8A7794_CLK_SDHI1>; + dmas = <&dmac0 0xc1>, <&dmac0 0xc2>, + <&dmac1 0xc1>, <&dmac1 0xc2>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; status = "disabled"; }; @@ -696,6 +723,9 @@ reg = <0 0xee160000 0 0x100>; interrupts = ; clocks = <&mstp3_clks R8A7794_CLK_SDHI2>; + dmas = <&dmac0 0xd3>, <&dmac0 0xd4>, + <&dmac1 0xd3>, <&dmac1 0xd4>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; status = "disabled"; }; @@ -705,8 +735,9 @@ reg = <0 0xe6b10000 0 0x2c>; interrupts = ; clocks = <&mstp9_clks R8A7794_CLK_QSPI_MOD>; - dmas = <&dmac0 0x17>, <&dmac0 0x18>; - dma-names = "tx", "rx"; + dmas = <&dmac0 0x17>, <&dmac0 0x18>, + <&dmac1 0x17>, <&dmac1 0x18>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; num-cs = <1>; #address-cells = <1>; -- cgit v0.10.2 From 79c530ed4dd374e51f3c8ff75134a1da201952b7 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 19 May 2016 19:45:59 +0200 Subject: ARM: dts: r8a7794: Remove nonexistent thermal sensor clock According to the latest information, there is no thermal IP block present on the r8a7794 SoC. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman diff --git a/include/dt-bindings/clock/r8a7794-clock.h b/include/dt-bindings/clock/r8a7794-clock.h index 4d3ecd6..a3491ba 100644 --- a/include/dt-bindings/clock/r8a7794-clock.h +++ b/include/dt-bindings/clock/r8a7794-clock.h @@ -67,7 +67,6 @@ #define R8A7794_CLK_IRQC 7 /* MSTP5 */ -#define R8A7794_CLK_THERMAL 22 #define R8A7794_CLK_PWM 23 /* MSTP7 */ -- cgit v0.10.2 From 33df2753637b2d59adcfd13c35761ff13ff1c673 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 20 May 2016 09:09:52 +0200 Subject: ARM: dts: emev2: Fix W=1 dtc warnings Warning (unit_address_vs_reg): Node /clocks@e0110000/iic0_sclkdiv has a reg or ranges property, but no unit name Warning (unit_address_vs_reg): Node /clocks@e0110000/iic0_sclk has a reg or ranges property, but no unit name Warning (unit_address_vs_reg): Node /clocks@e0110000/iic1_sclkdiv has a reg or ranges property, but no unit name Warning (unit_address_vs_reg): Node /clocks@e0110000/iic1_sclk has a reg or ranges property, but no unit name Warning (unit_address_vs_reg): Node /clocks@e0110000/usia_u0_sclkdiv has a reg or ranges property, but no unit name Warning (unit_address_vs_reg): Node /clocks@e0110000/usib_u1_sclkdiv has a reg or ranges property, but no unit name Warning (unit_address_vs_reg): Node /clocks@e0110000/usib_u2_sclkdiv has a reg or ranges property, but no unit name Warning (unit_address_vs_reg): Node /clocks@e0110000/usib_u3_sclkdiv has a reg or ranges property, but no unit name Warning (unit_address_vs_reg): Node /clocks@e0110000/usia_u0_sclk has a reg or ranges property, but no unit name Warning (unit_address_vs_reg): Node /clocks@e0110000/usib_u1_sclk has a reg or ranges property, but no unit name Warning (unit_address_vs_reg): Node /clocks@e0110000/usib_u2_sclk has a reg or ranges property, but no unit name Warning (unit_address_vs_reg): Node /clocks@e0110000/usib_u3_sclk has a reg or ranges property, but no unit name Warning (unit_address_vs_reg): Node /clocks@e0110000/sti_sclk has a reg or ranges property, but no unit name Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman diff --git a/arch/arm/boot/dts/emev2.dtsi b/arch/arm/boot/dts/emev2.dtsi index bcce6f5..cd11940 100644 --- a/arch/arm/boot/dts/emev2.dtsi +++ b/arch/arm/boot/dts/emev2.dtsi @@ -69,25 +69,25 @@ clock-frequency = <32768>; #clock-cells = <0>; }; - iic0_sclkdiv: iic0_sclkdiv { + iic0_sclkdiv: iic0_sclkdiv@624,0 { compatible = "renesas,emev2-smu-clkdiv"; reg = <0x624 0>; clocks = <&pll3_fo>; #clock-cells = <0>; }; - iic0_sclk: iic0_sclk { + iic0_sclk: iic0_sclk@48c,1 { compatible = "renesas,emev2-smu-gclk"; reg = <0x48c 1>; clocks = <&iic0_sclkdiv>; #clock-cells = <0>; }; - iic1_sclkdiv: iic1_sclkdiv { + iic1_sclkdiv: iic1_sclkdiv@624,16 { compatible = "renesas,emev2-smu-clkdiv"; reg = <0x624 16>; clocks = <&pll3_fo>; #clock-cells = <0>; }; - iic1_sclk: iic1_sclk { + iic1_sclk: iic1_sclk@490,1 { compatible = "renesas,emev2-smu-gclk"; reg = <0x490 1>; clocks = <&iic1_sclkdiv>; @@ -100,55 +100,55 @@ clock-mult = <7000>; #clock-cells = <0>; }; - usia_u0_sclkdiv: usia_u0_sclkdiv { + usia_u0_sclkdiv: usia_u0_sclkdiv@610,0 { compatible = "renesas,emev2-smu-clkdiv"; reg = <0x610 0>; clocks = <&pll3_fo>; #clock-cells = <0>; }; - usib_u1_sclkdiv: usib_u1_sclkdiv { + usib_u1_sclkdiv: usib_u1_sclkdiv@65c,0 { compatible = "renesas,emev2-smu-clkdiv"; reg = <0x65c 0>; clocks = <&pll3_fo>; #clock-cells = <0>; }; - usib_u2_sclkdiv: usib_u2_sclkdiv { + usib_u2_sclkdiv: usib_u2_sclkdiv@65c,16 { compatible = "renesas,emev2-smu-clkdiv"; reg = <0x65c 16>; clocks = <&pll3_fo>; #clock-cells = <0>; }; - usib_u3_sclkdiv: usib_u3_sclkdiv { + usib_u3_sclkdiv: usib_u3_sclkdiv@660,0 { compatible = "renesas,emev2-smu-clkdiv"; reg = <0x660 0>; clocks = <&pll3_fo>; #clock-cells = <0>; }; - usia_u0_sclk: usia_u0_sclk { + usia_u0_sclk: usia_u0_sclk@4a0,1 { compatible = "renesas,emev2-smu-gclk"; reg = <0x4a0 1>; clocks = <&usia_u0_sclkdiv>; #clock-cells = <0>; }; - usib_u1_sclk: usib_u1_sclk { + usib_u1_sclk: usib_u1_sclk@4b8,1 { compatible = "renesas,emev2-smu-gclk"; reg = <0x4b8 1>; clocks = <&usib_u1_sclkdiv>; #clock-cells = <0>; }; - usib_u2_sclk: usib_u2_sclk { + usib_u2_sclk: usib_u2_sclk@4bc,1 { compatible = "renesas,emev2-smu-gclk"; reg = <0x4bc 1>; clocks = <&usib_u2_sclkdiv>; #clock-cells = <0>; }; - usib_u3_sclk: usib_u3_sclk { + usib_u3_sclk: usib_u3_sclk@4c0,1 { compatible = "renesas,emev2-smu-gclk"; reg = <0x4c0 1>; clocks = <&usib_u3_sclkdiv>; #clock-cells = <0>; }; - sti_sclk: sti_sclk { + sti_sclk: sti_sclk@528,1 { compatible = "renesas,emev2-smu-gclk"; reg = <0x528 1>; clocks = <&c32ki>; -- cgit v0.10.2 From b0da45c60d2f7b08128a6cd1216ac0ac7d8954c7 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 20 May 2016 09:09:53 +0200 Subject: ARM: dts: r8a73a4: Fix W=1 dtc warnings Warning (unit_address_vs_reg): Node /cache-controller@0 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /cache-controller@1 has a unit name, but no reg property Move the cache-controller nodes under the cpus node, and make their unit names and reg properties match the MPIDR values. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman diff --git a/arch/arm/boot/dts/r8a73a4.dtsi b/arch/arm/boot/dts/r8a73a4.dtsi index 6954912..ca86727 100644 --- a/arch/arm/boot/dts/r8a73a4.dtsi +++ b/arch/arm/boot/dts/r8a73a4.dtsi @@ -31,6 +31,24 @@ power-domains = <&pd_a2sl>; next-level-cache = <&L2_CA15>; }; + + L2_CA15: cache-controller@0 { + compatible = "cache"; + reg = <0>; + clocks = <&cpg_clocks R8A73A4_CLK_Z>; + power-domains = <&pd_a3sm>; + cache-unified; + cache-level = <2>; + }; + + L2_CA7: cache-controller@100 { + compatible = "cache"; + reg = <0x100>; + clocks = <&cpg_clocks R8A73A4_CLK_Z2>; + power-domains = <&pd_a3km>; + cache-unified; + cache-level = <2>; + }; }; ptm { @@ -46,22 +64,6 @@ ; }; - L2_CA15: cache-controller@0 { - compatible = "cache"; - clocks = <&cpg_clocks R8A73A4_CLK_Z>; - power-domains = <&pd_a3sm>; - cache-unified; - cache-level = <2>; - }; - - L2_CA7: cache-controller@1 { - compatible = "cache"; - clocks = <&cpg_clocks R8A73A4_CLK_Z2>; - power-domains = <&pd_a3km>; - cache-unified; - cache-level = <2>; - }; - dbsc1: memory-controller@e6790000 { compatible = "renesas,dbsc-r8a73a4"; reg = <0 0xe6790000 0 0x10000>; -- cgit v0.10.2 From 28c8c0aa095360ec14c3bcbe7f3ed378faf1daac Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 20 May 2016 09:09:54 +0200 Subject: ARM: dts: r8a7740: Fix W=1 dtc warnings Warning (unit_address_vs_reg): Node /cache-controller has a reg or ranges property, but no unit name Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman diff --git a/arch/arm/boot/dts/r8a7740.dtsi b/arch/arm/boot/dts/r8a7740.dtsi index 39b2f88..159e04e 100644 --- a/arch/arm/boot/dts/r8a7740.dtsi +++ b/arch/arm/boot/dts/r8a7740.dtsi @@ -39,7 +39,7 @@ <0xc2000000 0x1000>; }; - L2: cache-controller { + L2: cache-controller@f0100000 { compatible = "arm,pl310-cache"; reg = <0xf0100000 0x1000>; interrupts = ; -- cgit v0.10.2 From 51f20c93383805cd4ec9c2f7e180c3dea7aefa81 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 20 May 2016 09:09:55 +0200 Subject: ARM: dts: r8a7778: Fix W=1 dtc warnings Warning (unit_address_vs_reg): Node /sound@ffd90000/rcar_sound,src/src@3 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ffd90000/rcar_sound,src/src@4 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ffd90000/rcar_sound,src/src@5 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ffd90000/rcar_sound,src/src@6 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ffd90000/rcar_sound,src/src@7 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ffd90000/rcar_sound,src/src@8 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ffd90000/rcar_sound,src/src@9 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ffd90000/rcar_sound,ssi/ssi@3 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ffd90000/rcar_sound,ssi/ssi@4 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ffd90000/rcar_sound,ssi/ssi@5 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ffd90000/rcar_sound,ssi/ssi@6 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ffd90000/rcar_sound,ssi/ssi@7 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ffd90000/rcar_sound,ssi/ssi@8 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ffd90000/rcar_sound,ssi/ssi@9 has a unit name, but no reg property Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman diff --git a/arch/arm/boot/dts/r8a7778.dtsi b/arch/arm/boot/dts/r8a7778.dtsi index fe787b4..e571d66 100644 --- a/arch/arm/boot/dts/r8a7778.dtsi +++ b/arch/arm/boot/dts/r8a7778.dtsi @@ -276,23 +276,23 @@ status = "disabled"; rcar_sound,src { - src3: src@3 { }; - src4: src@4 { }; - src5: src@5 { }; - src6: src@6 { }; - src7: src@7 { }; - src8: src@8 { }; - src9: src@9 { }; + src3: src-3 { }; + src4: src-4 { }; + src5: src-5 { }; + src6: src-6 { }; + src7: src-7 { }; + src8: src-8 { }; + src9: src-9 { }; }; rcar_sound,ssi { - ssi3: ssi@3 { interrupts = ; }; - ssi4: ssi@4 { interrupts = ; }; - ssi5: ssi@5 { interrupts = ; }; - ssi6: ssi@6 { interrupts = ; }; - ssi7: ssi@7 { interrupts = ; }; - ssi8: ssi@8 { interrupts = ; }; - ssi9: ssi@9 { interrupts = ; }; + ssi3: ssi-3 { interrupts = ; }; + ssi4: ssi-4 { interrupts = ; }; + ssi5: ssi-5 { interrupts = ; }; + ssi6: ssi-6 { interrupts = ; }; + ssi7: ssi-7 { interrupts = ; }; + ssi8: ssi-8 { interrupts = ; }; + ssi9: ssi-9 { interrupts = ; }; }; }; -- cgit v0.10.2 From 2c3de36700d4f3a5da1eb67e9340bfccfce19fdb Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 20 May 2016 09:09:56 +0200 Subject: ARM: dts: r8a7790: Fix W=1 dtc warnings Warning (unit_address_vs_reg): Node /cache-controller@0 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /cache-controller@1 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,dvc/dvc@0 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,dvc/dvc@1 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,mix/mix@0 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,mix/mix@1 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,ctu/ctu@0 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,ctu/ctu@1 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,ctu/ctu@2 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,ctu/ctu@3 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,ctu/ctu@4 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,ctu/ctu@5 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,ctu/ctu@6 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,ctu/ctu@7 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,src/src@0 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,src/src@1 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,src/src@2 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,src/src@3 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,src/src@4 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,src/src@5 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,src/src@6 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,src/src@7 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,src/src@8 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,src/src@9 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,ssi/ssi@0 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,ssi/ssi@1 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,ssi/ssi@2 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,ssi/ssi@3 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,ssi/ssi@4 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,ssi/ssi@5 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,ssi/ssi@6 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,ssi/ssi@7 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,ssi/ssi@8 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,ssi/ssi@9 has a unit name, but no reg property Move the cache-controller nodes under the cpus node, and make their unit names and reg properties match the MPIDR values. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index 97f4c1d..9997e7d 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -127,6 +127,22 @@ power-domains = <&sysc R8A7790_PD_CA7_CPU3>; next-level-cache = <&L2_CA7>; }; + + L2_CA15: cache-controller@0 { + compatible = "cache"; + reg = <0>; + power-domains = <&sysc R8A7790_PD_CA15_SCU>; + cache-unified; + cache-level = <2>; + }; + + L2_CA7: cache-controller@100 { + compatible = "cache"; + reg = <0x100>; + power-domains = <&sysc R8A7790_PD_CA7_SCU>; + cache-unified; + cache-level = <2>; + }; }; thermal-zones { @@ -148,20 +164,6 @@ }; }; - L2_CA15: cache-controller@0 { - compatible = "cache"; - power-domains = <&sysc R8A7790_PD_CA15_SCU>; - cache-unified; - cache-level = <2>; - }; - - L2_CA7: cache-controller@1 { - compatible = "cache"; - power-domains = <&sysc R8A7790_PD_CA7_SCU>; - cache-unified; - cache-level = <2>; - }; - gic: interrupt-controller@f1001000 { compatible = "arm,gic-400"; #interrupt-cells = <3>; @@ -1728,79 +1730,79 @@ status = "disabled"; rcar_sound,dvc { - dvc0: dvc@0 { + dvc0: dvc-0 { dmas = <&audma0 0xbc>; dma-names = "tx"; }; - dvc1: dvc@1 { + dvc1: dvc-1 { dmas = <&audma0 0xbe>; dma-names = "tx"; }; }; rcar_sound,mix { - mix0: mix@0 { }; - mix1: mix@1 { }; + mix0: mix-0 { }; + mix1: mix-1 { }; }; rcar_sound,ctu { - ctu00: ctu@0 { }; - ctu01: ctu@1 { }; - ctu02: ctu@2 { }; - ctu03: ctu@3 { }; - ctu10: ctu@4 { }; - ctu11: ctu@5 { }; - ctu12: ctu@6 { }; - ctu13: ctu@7 { }; + ctu00: ctu-0 { }; + ctu01: ctu-1 { }; + ctu02: ctu-2 { }; + ctu03: ctu-3 { }; + ctu10: ctu-4 { }; + ctu11: ctu-5 { }; + ctu12: ctu-6 { }; + ctu13: ctu-7 { }; }; rcar_sound,src { - src0: src@0 { + src0: src-0 { interrupts = ; dmas = <&audma0 0x85>, <&audma1 0x9a>; dma-names = "rx", "tx"; }; - src1: src@1 { + src1: src-1 { interrupts = ; dmas = <&audma0 0x87>, <&audma1 0x9c>; dma-names = "rx", "tx"; }; - src2: src@2 { + src2: src-2 { interrupts = ; dmas = <&audma0 0x89>, <&audma1 0x9e>; dma-names = "rx", "tx"; }; - src3: src@3 { + src3: src-3 { interrupts = ; dmas = <&audma0 0x8b>, <&audma1 0xa0>; dma-names = "rx", "tx"; }; - src4: src@4 { + src4: src-4 { interrupts = ; dmas = <&audma0 0x8d>, <&audma1 0xb0>; dma-names = "rx", "tx"; }; - src5: src@5 { + src5: src-5 { interrupts = ; dmas = <&audma0 0x8f>, <&audma1 0xb2>; dma-names = "rx", "tx"; }; - src6: src@6 { + src6: src-6 { interrupts = ; dmas = <&audma0 0x91>, <&audma1 0xb4>; dma-names = "rx", "tx"; }; - src7: src@7 { + src7: src-7 { interrupts = ; dmas = <&audma0 0x93>, <&audma1 0xb6>; dma-names = "rx", "tx"; }; - src8: src@8 { + src8: src-8 { interrupts = ; dmas = <&audma0 0x95>, <&audma1 0xb8>; dma-names = "rx", "tx"; }; - src9: src@9 { + src9: src-9 { interrupts = ; dmas = <&audma0 0x97>, <&audma1 0xba>; dma-names = "rx", "tx"; @@ -1808,52 +1810,52 @@ }; rcar_sound,ssi { - ssi0: ssi@0 { + ssi0: ssi-0 { interrupts = ; dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>; dma-names = "rx", "tx", "rxu", "txu"; }; - ssi1: ssi@1 { + ssi1: ssi-1 { interrupts = ; dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>; dma-names = "rx", "tx", "rxu", "txu"; }; - ssi2: ssi@2 { + ssi2: ssi-2 { interrupts = ; dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>; dma-names = "rx", "tx", "rxu", "txu"; }; - ssi3: ssi@3 { + ssi3: ssi-3 { interrupts = ; dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>; dma-names = "rx", "tx", "rxu", "txu"; }; - ssi4: ssi@4 { + ssi4: ssi-4 { interrupts = ; dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>; dma-names = "rx", "tx", "rxu", "txu"; }; - ssi5: ssi@5 { + ssi5: ssi-5 { interrupts = ; dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>; dma-names = "rx", "tx", "rxu", "txu"; }; - ssi6: ssi@6 { + ssi6: ssi-6 { interrupts = ; dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>; dma-names = "rx", "tx", "rxu", "txu"; }; - ssi7: ssi@7 { + ssi7: ssi-7 { interrupts = ; dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>; dma-names = "rx", "tx", "rxu", "txu"; }; - ssi8: ssi@8 { + ssi8: ssi-8 { interrupts = ; dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>; dma-names = "rx", "tx", "rxu", "txu"; }; - ssi9: ssi@9 { + ssi9: ssi-9 { interrupts = ; dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>; dma-names = "rx", "tx", "rxu", "txu"; -- cgit v0.10.2 From 6f9314ce258c8504975d96fa509763245fff287b Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 20 May 2016 09:09:57 +0200 Subject: ARM: dts: r8a7791: Fix W=1 dtc warnings Warning (unit_address_vs_reg): Node /cache-controller@0 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,dvc/dvc@0 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,dvc/dvc@1 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,mix/mix@0 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,mix/mix@1 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,ctu/ctu@0 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,ctu/ctu@1 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,ctu/ctu@2 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,ctu/ctu@3 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,ctu/ctu@4 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,ctu/ctu@5 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,ctu/ctu@6 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,ctu/ctu@7 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,src/src@0 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,src/src@1 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,src/src@2 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,src/src@3 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,src/src@4 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,src/src@5 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,src/src@6 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,src/src@7 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,src/src@8 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,src/src@9 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,ssi/ssi@0 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,ssi/ssi@1 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,ssi/ssi@2 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,ssi/ssi@3 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,ssi/ssi@4 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,ssi/ssi@5 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,ssi/ssi@6 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,ssi/ssi@7 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,ssi/ssi@8 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,ssi/ssi@9 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /cache-controller@0 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,dvc/dvc@0 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,dvc/dvc@1 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,mix/mix@0 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,mix/mix@1 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,ctu/ctu@0 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,ctu/ctu@1 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,ctu/ctu@2 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,ctu/ctu@3 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,ctu/ctu@4 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,ctu/ctu@5 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,ctu/ctu@6 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,ctu/ctu@7 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,src/src@0 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,src/src@1 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,src/src@2 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,src/src@3 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,src/src@4 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,src/src@5 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,src/src@6 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,src/src@7 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,src/src@8 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,src/src@9 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,ssi/ssi@0 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,ssi/ssi@1 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,ssi/ssi@2 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,ssi/ssi@3 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,ssi/ssi@4 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,ssi/ssi@5 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,ssi/ssi@6 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,ssi/ssi@7 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,ssi/ssi@8 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,ssi/ssi@9 has a unit name, but no reg property Move the cache-controller node under the cpus node, and make its unit name and reg property match the MPIDR values. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi index 2f92414..1985bd0 100644 --- a/arch/arm/boot/dts/r8a7791.dtsi +++ b/arch/arm/boot/dts/r8a7791.dtsi @@ -72,6 +72,14 @@ power-domains = <&sysc R8A7791_PD_CA15_CPU1>; next-level-cache = <&L2_CA15>; }; + + L2_CA15: cache-controller@0 { + compatible = "cache"; + reg = <0>; + power-domains = <&sysc R8A7791_PD_CA15_SCU>; + cache-unified; + cache-level = <2>; + }; }; thermal-zones { @@ -93,13 +101,6 @@ }; }; - L2_CA15: cache-controller@0 { - compatible = "cache"; - power-domains = <&sysc R8A7791_PD_CA15_SCU>; - cache-unified; - cache-level = <2>; - }; - gic: interrupt-controller@f1001000 { compatible = "arm,gic-400"; #interrupt-cells = <3>; @@ -1766,79 +1767,79 @@ status = "disabled"; rcar_sound,dvc { - dvc0: dvc@0 { + dvc0: dvc-0 { dmas = <&audma0 0xbc>; dma-names = "tx"; }; - dvc1: dvc@1 { + dvc1: dvc-1 { dmas = <&audma0 0xbe>; dma-names = "tx"; }; }; rcar_sound,mix { - mix0: mix@0 { }; - mix1: mix@1 { }; + mix0: mix-0 { }; + mix1: mix-1 { }; }; rcar_sound,ctu { - ctu00: ctu@0 { }; - ctu01: ctu@1 { }; - ctu02: ctu@2 { }; - ctu03: ctu@3 { }; - ctu10: ctu@4 { }; - ctu11: ctu@5 { }; - ctu12: ctu@6 { }; - ctu13: ctu@7 { }; + ctu00: ctu-0 { }; + ctu01: ctu-1 { }; + ctu02: ctu-2 { }; + ctu03: ctu-3 { }; + ctu10: ctu-4 { }; + ctu11: ctu-5 { }; + ctu12: ctu-6 { }; + ctu13: ctu-7 { }; }; rcar_sound,src { - src0: src@0 { + src0: src-0 { interrupts = ; dmas = <&audma0 0x85>, <&audma1 0x9a>; dma-names = "rx", "tx"; }; - src1: src@1 { + src1: src-1 { interrupts = ; dmas = <&audma0 0x87>, <&audma1 0x9c>; dma-names = "rx", "tx"; }; - src2: src@2 { + src2: src-2 { interrupts = ; dmas = <&audma0 0x89>, <&audma1 0x9e>; dma-names = "rx", "tx"; }; - src3: src@3 { + src3: src-3 { interrupts = ; dmas = <&audma0 0x8b>, <&audma1 0xa0>; dma-names = "rx", "tx"; }; - src4: src@4 { + src4: src-4 { interrupts = ; dmas = <&audma0 0x8d>, <&audma1 0xb0>; dma-names = "rx", "tx"; }; - src5: src@5 { + src5: src-5 { interrupts = ; dmas = <&audma0 0x8f>, <&audma1 0xb2>; dma-names = "rx", "tx"; }; - src6: src@6 { + src6: src-6 { interrupts = ; dmas = <&audma0 0x91>, <&audma1 0xb4>; dma-names = "rx", "tx"; }; - src7: src@7 { + src7: src-7 { interrupts = ; dmas = <&audma0 0x93>, <&audma1 0xb6>; dma-names = "rx", "tx"; }; - src8: src@8 { + src8: src-8 { interrupts = ; dmas = <&audma0 0x95>, <&audma1 0xb8>; dma-names = "rx", "tx"; }; - src9: src@9 { + src9: src-9 { interrupts = ; dmas = <&audma0 0x97>, <&audma1 0xba>; dma-names = "rx", "tx"; @@ -1846,52 +1847,52 @@ }; rcar_sound,ssi { - ssi0: ssi@0 { + ssi0: ssi-0 { interrupts = ; dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>; dma-names = "rx", "tx", "rxu", "txu"; }; - ssi1: ssi@1 { + ssi1: ssi-1 { interrupts = ; dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>; dma-names = "rx", "tx", "rxu", "txu"; }; - ssi2: ssi@2 { + ssi2: ssi-2 { interrupts = ; dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>; dma-names = "rx", "tx", "rxu", "txu"; }; - ssi3: ssi@3 { + ssi3: ssi-3 { interrupts = ; dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>; dma-names = "rx", "tx", "rxu", "txu"; }; - ssi4: ssi@4 { + ssi4: ssi-4 { interrupts = ; dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>; dma-names = "rx", "tx", "rxu", "txu"; }; - ssi5: ssi@5 { + ssi5: ssi-5 { interrupts = ; dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>; dma-names = "rx", "tx", "rxu", "txu"; }; - ssi6: ssi@6 { + ssi6: ssi-6 { interrupts = ; dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>; dma-names = "rx", "tx", "rxu", "txu"; }; - ssi7: ssi@7 { + ssi7: ssi-7 { interrupts = ; dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>; dma-names = "rx", "tx", "rxu", "txu"; }; - ssi8: ssi@8 { + ssi8: ssi-8 { interrupts = ; dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>; dma-names = "rx", "tx", "rxu", "txu"; }; - ssi9: ssi@9 { + ssi9: ssi-9 { interrupts = ; dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>; dma-names = "rx", "tx", "rxu", "txu"; -- cgit v0.10.2 From ad53f5f00b095a0d42b65bf578eb1c1b026c5b99 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 20 May 2016 09:09:58 +0200 Subject: ARM: dts: r8a7793: Fix W=1 dtc warnings Warning (unit_address_vs_reg): Node /cache-controller@0 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,dvc/dvc@0 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,dvc/dvc@1 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,src/src@0 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,src/src@1 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,src/src@2 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,src/src@3 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,src/src@4 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,src/src@5 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,src/src@6 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,src/src@7 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,src/src@8 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,src/src@9 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,ssi/ssi@0 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,ssi/ssi@1 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,ssi/ssi@2 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,ssi/ssi@3 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,ssi/ssi@4 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,ssi/ssi@5 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,ssi/ssi@6 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,ssi/ssi@7 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,ssi/ssi@8 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,ssi/ssi@9 has a unit name, but no reg property Move the cache-controller node under the cpus node, and make its unit name and reg property match the MPIDR values. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi index 5f50e9b..9b55c1c 100644 --- a/arch/arm/boot/dts/r8a7793.dtsi +++ b/arch/arm/boot/dts/r8a7793.dtsi @@ -55,6 +55,14 @@ < 375000 1000000>; next-level-cache = <&L2_CA15>; }; + + L2_CA15: cache-controller@0 { + compatible = "cache"; + reg = <0>; + power-domains = <&sysc R8A7793_PD_CA15_SCU>; + cache-unified; + cache-level = <2>; + }; }; thermal-zones { @@ -76,13 +84,6 @@ }; }; - L2_CA15: cache-controller@0 { - compatible = "cache"; - power-domains = <&sysc R8A7793_PD_CA15_SCU>; - cache-unified; - cache-level = <2>; - }; - gic: interrupt-controller@f1001000 { compatible = "arm,gic-400"; #interrupt-cells = <3>; @@ -1369,63 +1370,63 @@ status = "disabled"; rcar_sound,dvc { - dvc0: dvc@0 { + dvc0: dvc-0 { dmas = <&audma0 0xbc>; dma-names = "tx"; }; - dvc1: dvc@1 { + dvc1: dvc-1 { dmas = <&audma0 0xbe>; dma-names = "tx"; }; }; rcar_sound,src { - src0: src@0 { + src0: src-0 { interrupts = ; dmas = <&audma0 0x85>, <&audma1 0x9a>; dma-names = "rx", "tx"; }; - src1: src@1 { + src1: src-1 { interrupts = ; dmas = <&audma0 0x87>, <&audma1 0x9c>; dma-names = "rx", "tx"; }; - src2: src@2 { + src2: src-2 { interrupts = ; dmas = <&audma0 0x89>, <&audma1 0x9e>; dma-names = "rx", "tx"; }; - src3: src@3 { + src3: src-3 { interrupts = ; dmas = <&audma0 0x8b>, <&audma1 0xa0>; dma-names = "rx", "tx"; }; - src4: src@4 { + src4: src-4 { interrupts = ; dmas = <&audma0 0x8d>, <&audma1 0xb0>; dma-names = "rx", "tx"; }; - src5: src@5 { + src5: src-5 { interrupts = ; dmas = <&audma0 0x8f>, <&audma1 0xb2>; dma-names = "rx", "tx"; }; - src6: src@6 { + src6: src-6 { interrupts = ; dmas = <&audma0 0x91>, <&audma1 0xb4>; dma-names = "rx", "tx"; }; - src7: src@7 { + src7: src-7 { interrupts = ; dmas = <&audma0 0x93>, <&audma1 0xb6>; dma-names = "rx", "tx"; }; - src8: src@8 { + src8: src-8 { interrupts = ; dmas = <&audma0 0x95>, <&audma1 0xb8>; dma-names = "rx", "tx"; }; - src9: src@9 { + src9: src-9 { interrupts = ; dmas = <&audma0 0x97>, <&audma1 0xba>; dma-names = "rx", "tx"; @@ -1433,52 +1434,52 @@ }; rcar_sound,ssi { - ssi0: ssi@0 { + ssi0: ssi-0 { interrupts = ; dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>; dma-names = "rx", "tx", "rxu", "txu"; }; - ssi1: ssi@1 { + ssi1: ssi-1 { interrupts = ; dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>; dma-names = "rx", "tx", "rxu", "txu"; }; - ssi2: ssi@2 { + ssi2: ssi-2 { interrupts = ; dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>; dma-names = "rx", "tx", "rxu", "txu"; }; - ssi3: ssi@3 { + ssi3: ssi-3 { interrupts = ; dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>; dma-names = "rx", "tx", "rxu", "txu"; }; - ssi4: ssi@4 { + ssi4: ssi-4 { interrupts = ; dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>; dma-names = "rx", "tx", "rxu", "txu"; }; - ssi5: ssi@5 { + ssi5: ssi-5 { interrupts = ; dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>; dma-names = "rx", "tx", "rxu", "txu"; }; - ssi6: ssi@6 { + ssi6: ssi-6 { interrupts = ; dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>; dma-names = "rx", "tx", "rxu", "txu"; }; - ssi7: ssi@7 { + ssi7: ssi-7 { interrupts = ; dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>; dma-names = "rx", "tx", "rxu", "txu"; }; - ssi8: ssi@8 { + ssi8: ssi-8 { interrupts = ; dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>; dma-names = "rx", "tx", "rxu", "txu"; }; - ssi9: ssi@9 { + ssi9: ssi-9 { interrupts = ; dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>; dma-names = "rx", "tx", "rxu", "txu"; -- cgit v0.10.2 From 34ea4b4a827b4ee76295501b7df61fc904ab8ae3 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 20 May 2016 09:09:59 +0200 Subject: ARM: dts: r8a7794: Fix W=1 dtc warnings Warning (unit_address_vs_reg): Node /cache-controller@1 has a unit name, but no reg property Move the cache-controller node under the cpus node, and make its unit name and reg property match the MPIDR value. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi index ad1df83..685f986 100644 --- a/arch/arm/boot/dts/r8a7794.dtsi +++ b/arch/arm/boot/dts/r8a7794.dtsi @@ -55,13 +55,14 @@ power-domains = <&sysc R8A7794_PD_CA7_CPU1>; next-level-cache = <&L2_CA7>; }; - }; - L2_CA7: cache-controller@1 { - compatible = "cache"; - power-domains = <&sysc R8A7794_PD_CA7_SCU>; - cache-unified; - cache-level = <2>; + L2_CA7: cache-controller@0 { + compatible = "cache"; + reg = <0>; + power-domains = <&sysc R8A7794_PD_CA7_SCU>; + cache-unified; + cache-level = <2>; + }; }; gic: interrupt-controller@f1001000 { -- cgit v0.10.2 From 1178814b0fc3649a9c586554e8f6d4f161a97c1f Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 20 May 2016 09:10:00 +0200 Subject: ARM: dts: sh73a0: Fix W=1 dtc warnings Warning (unit_address_vs_reg): Node /cache-controller has a reg or ranges property, but no unit name Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman diff --git a/arch/arm/boot/dts/sh73a0.dtsi b/arch/arm/boot/dts/sh73a0.dtsi index c4f434c..032fe2f 100644 --- a/arch/arm/boot/dts/sh73a0.dtsi +++ b/arch/arm/boot/dts/sh73a0.dtsi @@ -55,7 +55,7 @@ <0xf0000100 0x100>; }; - L2: cache-controller { + L2: cache-controller@f0100000 { compatible = "arm,pl310-cache"; reg = <0xf0100000 0x1000>; interrupts = ; -- cgit v0.10.2 From 4706147211708c7a8c027b798a016fdd5d03c9d2 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 20 May 2016 09:10:01 +0200 Subject: ARM: dts: ape6evm: Fix W=1 dtc warnings Warning (unit_address_vs_reg): Node /regulator@0 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /regulator@1 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /regulator@2 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /regulator@3 has a unit name, but no reg property Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman diff --git a/arch/arm/boot/dts/r8a73a4-ape6evm.dts b/arch/arm/boot/dts/r8a73a4-ape6evm.dts index 93ace33..740e5d2 100644 --- a/arch/arm/boot/dts/r8a73a4-ape6evm.dts +++ b/arch/arm/boot/dts/r8a73a4-ape6evm.dts @@ -36,7 +36,7 @@ reg = <2 0x00000000 0 0x40000000>; }; - vcc_mmc0: regulator@0 { + vcc_mmc0: regulator-mmc0 { compatible = "regulator-fixed"; regulator-name = "MMC0 Vcc"; regulator-min-microvolt = <2800000>; @@ -44,7 +44,7 @@ regulator-always-on; }; - vcc_sdhi0: regulator@1 { + vcc_sdhi0: regulator-sdhi0 { compatible = "regulator-fixed"; regulator-name = "SDHI0 Vcc"; @@ -56,7 +56,7 @@ }; /* Common 1.8V and 3.3V rails, used by several devices on APE6EVM */ - ape6evm_fixed_1v8: regulator@2 { + ape6evm_fixed_1v8: regulator-1v8 { compatible = "regulator-fixed"; regulator-name = "1V8"; regulator-min-microvolt = <1800000>; @@ -64,7 +64,7 @@ regulator-always-on; }; - ape6evm_fixed_3v3: regulator@3 { + ape6evm_fixed_3v3: regulator-3v3 { compatible = "regulator-fixed"; regulator-name = "3V3"; regulator-min-microvolt = <3300000>; -- cgit v0.10.2 From c9c3b7c3029d501402b5ac4817659d6e0a6f11f4 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 20 May 2016 09:10:02 +0200 Subject: ARM: dts: armadillo800eva: Fix W=1 dtc warnings Warning (unit_address_vs_reg): Node /memory has a reg or ranges property, but no unit name Warning (unit_address_vs_reg): Node /regulator@0 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /regulator@1 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /regulator@2 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /regulator@3 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /i2c@2 has a unit name, but no reg property Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman diff --git a/arch/arm/boot/dts/r8a7740-armadillo800eva.dts b/arch/arm/boot/dts/r8a7740-armadillo800eva.dts index 2c82dab..1620495 100644 --- a/arch/arm/boot/dts/r8a7740-armadillo800eva.dts +++ b/arch/arm/boot/dts/r8a7740-armadillo800eva.dts @@ -28,12 +28,12 @@ stdout-path = &scifa1; }; - memory { + memory@40000000 { device_type = "memory"; reg = <0x40000000 0x20000000>; }; - reg_3p3v: regulator@0 { + reg_3p3v: regulator-3p3v { compatible = "regulator-fixed"; regulator-name = "fixed-3.3V"; regulator-min-microvolt = <3300000>; @@ -42,7 +42,7 @@ regulator-boot-on; }; - vcc_sdhi0: regulator@1 { + vcc_sdhi0: regulator-vcc-sdhi0 { compatible = "regulator-fixed"; regulator-name = "SDHI0 Vcc"; @@ -53,7 +53,7 @@ enable-active-high; }; - vccq_sdhi0: regulator@2 { + vccq_sdhi0: regulator-vccq-sdhi0 { compatible = "regulator-gpio"; regulator-name = "SDHI0 VccQ"; @@ -69,7 +69,7 @@ enable-active-high; }; - reg_5p0v: regulator@3 { + reg_5p0v: regulator-5p0v { compatible = "regulator-fixed"; regulator-name = "fixed-5.0V"; regulator-min-microvolt = <5000000>; @@ -127,7 +127,7 @@ }; }; - i2c2: i2c@2 { + i2c2: i2c-2 { #address-cells = <1>; #size-cells = <0>; compatible = "i2c-gpio"; -- cgit v0.10.2 From 40cf49f3a44674643604b8a848e6c10d6f50edfe Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 20 May 2016 09:10:03 +0200 Subject: ARM: dts: bockw: Fix W=1 dtc warnings Warning (unit_address_vs_reg): Node /memory has a reg or ranges property, but no unit name Warning (unit_address_vs_reg): Node /fixedregulator@0 has a unit name, but no reg property Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman diff --git a/arch/arm/boot/dts/r8a7778-bockw.dts b/arch/arm/boot/dts/r8a7778-bockw.dts index 982a237..0a0bd3b 100644 --- a/arch/arm/boot/dts/r8a7778-bockw.dts +++ b/arch/arm/boot/dts/r8a7778-bockw.dts @@ -32,12 +32,12 @@ stdout-path = "serial0:115200n8"; }; - memory { + memory@60000000 { device_type = "memory"; reg = <0x60000000 0x10000000>; }; - fixedregulator3v3: fixedregulator@0 { + fixedregulator3v3: regulator-3v3 { compatible = "regulator-fixed"; regulator-name = "fixed-3.3V"; regulator-min-microvolt = <3300000>; -- cgit v0.10.2 From 4f4942bc6c44cda681ee08b84b62bdacd97559e3 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 20 May 2016 09:10:04 +0200 Subject: ARM: dts: genmai: Fix W=1 dtc warnings Warning (unit_address_vs_reg): Node /memory has a reg or ranges property, but no unit name Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman diff --git a/arch/arm/boot/dts/r7s72100-genmai.dts b/arch/arm/boot/dts/r7s72100-genmai.dts index a9da7a8..05ba995 100644 --- a/arch/arm/boot/dts/r7s72100-genmai.dts +++ b/arch/arm/boot/dts/r7s72100-genmai.dts @@ -25,7 +25,7 @@ stdout-path = &scif2; }; - memory { + memory@8000000 { device_type = "memory"; reg = <0x08000000 0x08000000>; }; -- cgit v0.10.2 From b6dfc0d4016a7d951a073c0761109264790706f8 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 20 May 2016 09:10:05 +0200 Subject: ARM: dts: gose: Fix W=1 dtc warnings Warning (unit_address_vs_reg): Node /regulator@0 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /regulator@1 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /regulator@2 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /regulator@3 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /regulator@4 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /regulator@5 has a unit name, but no reg property Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman diff --git a/arch/arm/boot/dts/r8a7793-gose.dts b/arch/arm/boot/dts/r8a7793-gose.dts index 0ebc3ee..f748360 100644 --- a/arch/arm/boot/dts/r8a7793-gose.dts +++ b/arch/arm/boot/dts/r8a7793-gose.dts @@ -158,7 +158,7 @@ }; }; - vcc_sdhi0: regulator@0 { + vcc_sdhi0: regulator-vcc-sdhi0 { compatible = "regulator-fixed"; regulator-name = "SDHI0 Vcc"; @@ -169,7 +169,7 @@ enable-active-high; }; - vccq_sdhi0: regulator@1 { + vccq_sdhi0: regulator-vccq-sdhi0 { compatible = "regulator-gpio"; regulator-name = "SDHI0 VccQ"; @@ -182,7 +182,7 @@ 1800000 0>; }; - vcc_sdhi1: regulator@2 { + vcc_sdhi1: regulator-vcc-sdhi1 { compatible = "regulator-fixed"; regulator-name = "SDHI1 Vcc"; @@ -193,7 +193,7 @@ enable-active-high; }; - vccq_sdhi1: regulator@3 { + vccq_sdhi1: regulator-vccq-sdhi1 { compatible = "regulator-gpio"; regulator-name = "SDHI1 VccQ"; @@ -206,7 +206,7 @@ 1800000 0>; }; - vcc_sdhi2: regulator@4 { + vcc_sdhi2: regulator-vcc-sdhi2 { compatible = "regulator-fixed"; regulator-name = "SDHI2 Vcc"; @@ -217,7 +217,7 @@ enable-active-high; }; - vccq_sdhi2: regulator@5 { + vccq_sdhi2: regulator-vccq-sdhi2 { compatible = "regulator-gpio"; regulator-name = "SDHI2 VccQ"; -- cgit v0.10.2 From a704b2769fd27e47664f901571fc0f29702721e5 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 20 May 2016 09:10:06 +0200 Subject: ARM: dts: koelsch: Fix W=1 dtc warnings Warning (unit_address_vs_reg): Node /regulator@0 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /regulator@1 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /regulator@2 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /regulator@3 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /regulator@4 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /regulator@5 has a unit name, but no reg property Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman diff --git a/arch/arm/boot/dts/r8a7791-koelsch.dts b/arch/arm/boot/dts/r8a7791-koelsch.dts index da59c28..20fbc8c 100644 --- a/arch/arm/boot/dts/r8a7791-koelsch.dts +++ b/arch/arm/boot/dts/r8a7791-koelsch.dts @@ -170,7 +170,7 @@ }; }; - vcc_sdhi0: regulator@0 { + vcc_sdhi0: regulator-vcc-sdhi0 { compatible = "regulator-fixed"; regulator-name = "SDHI0 Vcc"; @@ -181,7 +181,7 @@ enable-active-high; }; - vccq_sdhi0: regulator@1 { + vccq_sdhi0: regulator-vccq-sdhi0 { compatible = "regulator-gpio"; regulator-name = "SDHI0 VccQ"; @@ -194,7 +194,7 @@ 1800000 0>; }; - vcc_sdhi1: regulator@2 { + vcc_sdhi1: regulator-vcc-sdhi1 { compatible = "regulator-fixed"; regulator-name = "SDHI1 Vcc"; @@ -205,7 +205,7 @@ enable-active-high; }; - vccq_sdhi1: regulator@3 { + vccq_sdhi1: regulator-vccq-sdhi1 { compatible = "regulator-gpio"; regulator-name = "SDHI1 VccQ"; @@ -218,7 +218,7 @@ 1800000 0>; }; - vcc_sdhi2: regulator@4 { + vcc_sdhi2: regulator-vcc-sdhi2 { compatible = "regulator-fixed"; regulator-name = "SDHI2 Vcc"; @@ -229,7 +229,7 @@ enable-active-high; }; - vccq_sdhi2: regulator@5 { + vccq_sdhi2: regulator-vccq-sdhi2 { compatible = "regulator-gpio"; regulator-name = "SDHI2 VccQ"; -- cgit v0.10.2 From 815be9c2a436855227774f77b4d251292792964b Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 20 May 2016 09:10:07 +0200 Subject: ARM: dts: kzm9d: Fix W=1 dtc warnings Warning (unit_address_vs_reg): Node /memory has a reg or ranges property, but no unit name Warning (unit_address_vs_reg): Node /pfc@e0140200/serial@e1030000 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /gpio_keys/button@1 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /gpio_keys/button@2 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /gpio_keys/button@3 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /gpio_keys/button@4 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /regulator@0 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /regulator@1 has a unit name, but no reg property Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman diff --git a/arch/arm/boot/dts/emev2-kzm9d.dts b/arch/arm/boot/dts/emev2-kzm9d.dts index a35b851..9eb86f8 100644 --- a/arch/arm/boot/dts/emev2-kzm9d.dts +++ b/arch/arm/boot/dts/emev2-kzm9d.dts @@ -18,7 +18,7 @@ model = "EMEV2 KZM9D Board"; compatible = "renesas,kzm9d", "renesas,emev2"; - memory { + memory@40000000 { device_type = "memory"; reg = <0x40000000 0x8000000>; }; @@ -33,28 +33,28 @@ #address-cells = <1>; #size-cells = <0>; - button@1 { + one { debounce_interval = <50>; wakeup-source; label = "DSW2-1"; linux,code = ; gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; }; - button@2 { + two { debounce_interval = <50>; wakeup-source; label = "DSW2-2"; linux,code = ; gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>; }; - button@3 { + three { debounce_interval = <50>; wakeup-source; label = "DSW2-3"; linux,code = ; gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>; }; - button@4 { + four { debounce_interval = <50>; wakeup-source; label = "DSW2-4"; @@ -63,7 +63,7 @@ }; }; - reg_1p8v: regulator@0 { + reg_1p8v: regulator-1p8v { compatible = "regulator-fixed"; regulator-name = "fixed-1.8V"; regulator-min-microvolt = <1800000>; @@ -72,7 +72,7 @@ regulator-boot-on; }; - reg_3p3v: regulator@1 { + reg_3p3v: regulator-3p3v { compatible = "regulator-fixed"; regulator-name = "fixed-3.3V"; regulator-min-microvolt = <3300000>; @@ -104,7 +104,7 @@ }; &pfc { - uart1_pins: serial@e1030000 { + uart1_pins: uart1 { groups = "uart1_ctrl", "uart1_data"; function = "uart1"; }; -- cgit v0.10.2 From 8788b2c4f45aa1f4b333970c3dbc915da58d2326 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 20 May 2016 09:10:08 +0200 Subject: ARM: dts: kzm9g: Fix W=1 dtc warnings Warning (unit_address_vs_reg): Node /memory has a reg or ranges property, but no unit name Warning (unit_address_vs_reg): Node /regulator@0 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /regulator@1 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /regulator@2 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /regulator@3 has a unit name, but no reg property Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman diff --git a/arch/arm/boot/dts/sh73a0-kzm9g.dts b/arch/arm/boot/dts/sh73a0-kzm9g.dts index 9881adf..36567cb 100644 --- a/arch/arm/boot/dts/sh73a0-kzm9g.dts +++ b/arch/arm/boot/dts/sh73a0-kzm9g.dts @@ -43,12 +43,12 @@ stdout-path = &scifa4; }; - memory { + memory@40000000 { device_type = "memory"; reg = <0x40000000 0x20000000>; }; - reg_1p8v: regulator@0 { + reg_1p8v: regulator-1p8v { compatible = "regulator-fixed"; regulator-name = "fixed-1.8V"; regulator-min-microvolt = <1800000>; @@ -57,7 +57,7 @@ regulator-boot-on; }; - reg_3p3v: regulator@1 { + reg_3p3v: regulator-3p3v { compatible = "regulator-fixed"; regulator-name = "fixed-3.3V"; regulator-min-microvolt = <3300000>; @@ -66,7 +66,7 @@ regulator-boot-on; }; - vmmc_sdhi0: regulator@2 { + vmmc_sdhi0: regulator-vmmc-sdhi0 { compatible = "regulator-fixed"; regulator-name = "SDHI0 Vcc"; regulator-min-microvolt = <3300000>; @@ -75,7 +75,7 @@ enable-active-high; }; - vmmc_sdhi2: regulator@3 { + vmmc_sdhi2: regulator-vmmc-sdhi2 { compatible = "regulator-fixed"; regulator-name = "SDHI2 Vcc"; regulator-min-microvolt = <3300000>; -- cgit v0.10.2 From affe802c391ff99dcc26baa2bd479905f72b7fdc Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 20 May 2016 09:10:09 +0200 Subject: ARM: dts: lager: Fix W=1 dtc warnings Warning (unit_address_vs_reg): Node /keyboard/button@1 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /keyboard/button@2 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /keyboard/button@3 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /keyboard/button@4 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /fixedregulator@0 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /regulator@1 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /regulator@2 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /regulator@3 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /regulator@4 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /i2c@8 has a unit name, but no reg property Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts index 749ba02..9d20ace 100644 --- a/arch/arm/boot/dts/r8a7790-lager.dts +++ b/arch/arm/boot/dts/r8a7790-lager.dts @@ -76,28 +76,28 @@ keyboard { compatible = "gpio-keys"; - button@1 { + one { linux,code = ; label = "SW2-1"; wakeup-source; debounce-interval = <20>; gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; }; - button@2 { + two { linux,code = ; label = "SW2-2"; wakeup-source; debounce-interval = <20>; gpios = <&gpio1 24 GPIO_ACTIVE_LOW>; }; - button@3 { + three { linux,code = ; label = "SW2-3"; wakeup-source; debounce-interval = <20>; gpios = <&gpio1 26 GPIO_ACTIVE_LOW>; }; - button@4 { + four { linux,code = ; label = "SW2-4"; wakeup-source; @@ -119,7 +119,7 @@ }; }; - fixedregulator3v3: fixedregulator@0 { + fixedregulator3v3: regulator-3v3 { compatible = "regulator-fixed"; regulator-name = "fixed-3.3V"; regulator-min-microvolt = <3300000>; @@ -128,7 +128,7 @@ regulator-always-on; }; - vcc_sdhi0: regulator@1 { + vcc_sdhi0: regulator-vcc-sdhi0 { compatible = "regulator-fixed"; regulator-name = "SDHI0 Vcc"; @@ -139,7 +139,7 @@ enable-active-high; }; - vccq_sdhi0: regulator@2 { + vccq_sdhi0: regulator-vccq-sdhi0 { compatible = "regulator-gpio"; regulator-name = "SDHI0 VccQ"; @@ -152,7 +152,7 @@ 1800000 0>; }; - vcc_sdhi2: regulator@3 { + vcc_sdhi2: regulator-vcc-sdhi2 { compatible = "regulator-fixed"; regulator-name = "SDHI2 Vcc"; @@ -163,7 +163,7 @@ enable-active-high; }; - vccq_sdhi2: regulator@4 { + vccq_sdhi2: regulator-vccq-sdhi2 { compatible = "regulator-gpio"; regulator-name = "SDHI2 VccQ"; @@ -263,7 +263,7 @@ * instantiate the slave device at runtime according to the documentation. * You can then communicate with the slave via IIC3. */ - i2cexio: i2c@8 { + i2cexio: i2c-8 { compatible = "i2c-demux-pinctrl"; i2c-parent = <&iic0>, <&i2c0>; i2c-bus-name = "i2c-exio"; -- cgit v0.10.2 From 983ee3de2cd6963871a1d4b4ca11a9666738731a Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 20 May 2016 09:10:10 +0200 Subject: ARM: dts: marzen: Fix W=1 dtc warnings Warning (unit_address_vs_reg): Node /memory has a reg or ranges property, but no unit name Warning (unit_address_vs_reg): Node /fixedregulator@0 has a unit name, but no reg property Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman diff --git a/arch/arm/boot/dts/r8a7779-marzen.dts b/arch/arm/boot/dts/r8a7779-marzen.dts index b795da6..cec79a6 100644 --- a/arch/arm/boot/dts/r8a7779-marzen.dts +++ b/arch/arm/boot/dts/r8a7779-marzen.dts @@ -28,12 +28,12 @@ stdout-path = &scif2; }; - memory { + memory@60000000 { device_type = "memory"; reg = <0x60000000 0x40000000>; }; - fixedregulator3v3: fixedregulator@0 { + fixedregulator3v3: regulator-3v3 { compatible = "regulator-fixed"; regulator-name = "fixed-3.3V"; regulator-min-microvolt = <3300000>; -- cgit v0.10.2 From afed0c94ee44ea701a849d1c9729f9b711729197 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 20 May 2016 09:10:11 +0200 Subject: ARM: dts: porter: Fix W=1 dtc warnings Warning (unit_address_vs_reg): Node /regulator@0 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /regulator@1 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /regulator@2 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /regulator@3 has a unit name, but no reg property Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman diff --git a/arch/arm/boot/dts/r8a7791-porter.dts b/arch/arm/boot/dts/r8a7791-porter.dts index 6a1bb1a..e9151e9 100644 --- a/arch/arm/boot/dts/r8a7791-porter.dts +++ b/arch/arm/boot/dts/r8a7791-porter.dts @@ -46,7 +46,7 @@ reg = <2 0x00000000 0 0x40000000>; }; - vcc_sdhi0: regulator@0 { + vcc_sdhi0: regulator-vcc-sdhi0 { compatible = "regulator-fixed"; regulator-name = "SDHI0 Vcc"; @@ -55,7 +55,7 @@ regulator-always-on; }; - vccq_sdhi0: regulator@1 { + vccq_sdhi0: regulator-vccq-sdhi0 { compatible = "regulator-gpio"; regulator-name = "SDHI0 VccQ"; @@ -68,7 +68,7 @@ 1800000 0>; }; - vcc_sdhi2: regulator@2 { + vcc_sdhi2: regulator-vcc-sdhi2 { compatible = "regulator-fixed"; regulator-name = "SDHI2 Vcc"; @@ -77,7 +77,7 @@ regulator-always-on; }; - vccq_sdhi2: regulator@3 { + vccq_sdhi2: regulator-vccq-sdhi2 { compatible = "regulator-gpio"; regulator-name = "SDHI2 VccQ"; -- cgit v0.10.2 From b6960f19676e19f37a5e5a8af059fdf3b435d2f4 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 20 May 2016 09:10:12 +0200 Subject: ARM: dts: silk: Fix W=1 dtc warnings Warning (unit_address_vs_reg): Node /regulator@0 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /regulator@3 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /regulator@4 has a unit name, but no reg property Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman diff --git a/arch/arm/boot/dts/r8a7794-silk.dts b/arch/arm/boot/dts/r8a7794-silk.dts index 56d98d5..b8c7a63 100644 --- a/arch/arm/boot/dts/r8a7794-silk.dts +++ b/arch/arm/boot/dts/r8a7794-silk.dts @@ -32,7 +32,7 @@ reg = <0 0x40000000 0 0x40000000>; }; - d3_3v: regulator@0 { + d3_3v: regulator-d3-3v { compatible = "regulator-fixed"; regulator-name = "D3.3V"; regulator-min-microvolt = <3300000>; @@ -41,7 +41,7 @@ regulator-always-on; }; - vcc_sdhi1: regulator@3 { + vcc_sdhi1: regulator-vcc-sdhi1 { compatible = "regulator-fixed"; regulator-name = "SDHI1 Vcc"; @@ -52,7 +52,7 @@ enable-active-high; }; - vccq_sdhi1: regulator@4 { + vccq_sdhi1: regulator-vccq-sdhi1 { compatible = "regulator-gpio"; regulator-name = "SDHI1 VccQ"; -- cgit v0.10.2 From 94aed538e032d82287023beb9c59ee80f03a1493 Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Tue, 24 May 2016 13:41:02 -0400 Subject: ARM: dts: exynos: Add async-bridge clock to MFC power domain for Exynos5420 The MFC IP is also inter-connected by an Async-Bridge so the CLK_ACLK333 has to be ungated during a power domain switch. Trying to do it when the clock is gated will fail and lead to an imprecise external abort error when the driver tries to access the MFC registers with the PD disabled. For example, if the s5p-mfc module is removed and the MFC PD turned off: [ 186.835606] Power domain power-domain@10044060 disable failed [ 186.835671] s5p-mfc 11000000.codec: Removing 11000000.codec [ 186.837670] Power domain power-domain@10044060 disable failed And when the module is inserted again: [ 2395.176956] s5p_mfc_wait_for_done_dev:34: Interrupt (dev->int_type:0, command:12) timed out [ 2395.177031] s5p_mfc_init_hw:272: Failed to load firmware [ 2395.177384] Unhandled fault: imprecise external abort (0x1406) at 0x00000000 [ 2395.177441] pgd = ec3b4000 [ 2395.177467] [00000000] *pgd=00000000 [ 2395.177507] Internal error: : 1406 [#1] PREEMPT SMP ARM [ 2395.177550] Modules linked in: s5p_mfc mwifiex_sdio mwifiex uvcvideo s5p_jpeg v4l2_mem2mem videobuf2_vmalloc videobuf2_dma_contig videobuf2_memops videobuf2_v4l2 videobuf2_core v4l2_common videodev media [last unloaded: s5p_mfc] [ 2395.177774] CPU: 1 PID: 2382 Comm: v4l_id Tainted: G W 4.6.0-rc6-next-20160502-00010-g7730dc64d2c1-dirty #179 [ 2395.177857] Hardware name: SAMSUNG EXYNOS (Flattened Device Tree) [ 2395.177906] task: ed275500 ti: e6c8c000 task.ti: e6c8c000 [ 2395.177996] PC is at s5p_mfc_reset+0x1c4/0x284 [s5p_mfc] [ 2395.178057] LR is at s5p_mfc_reset+0x1a4/0x284 [s5p_mfc] This patch fixes this issue by adding the CLK_ACLK333 as an Async-Bridge clock for the MFC power domain, so the PD configuration works properly. Signed-off-by: Javier Martinez Canillas Reviewed-by: Krzysztof Kozlowski Signed-off-by: Krzysztof Kozlowski diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index c6e05eb..b4d43e3 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -349,8 +349,9 @@ mfc_pd: power-domain@10044060 { compatible = "samsung,exynos4210-pd"; reg = <0x10044060 0x20>; - clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MOUT_USER_ACLK333>; - clock-names = "oscclk", "clk0"; + clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MOUT_USER_ACLK333>, + <&clock CLK_ACLK333>; + clock-names = "oscclk", "clk0","asb0"; #power-domain-cells = <0>; }; -- cgit v0.10.2 From 9a205e33d0dc81121d1a2417b33b55682b81b84d Mon Sep 17 00:00:00 2001 From: Brian Norris Date: Thu, 5 May 2016 18:02:44 -0700 Subject: ARM: dts: rockchip: add SPI flash node for rk3288-veyron This is a standard binding for describing SPI flash that can be identified by reading their JEDEC ID. Let's use it. Tested on Veyron Jaq. Signed-off-by: Brian Norris Signed-off-by: Heiko Stuebner diff --git a/arch/arm/boot/dts/rk3288-veyron.dtsi b/arch/arm/boot/dts/rk3288-veyron.dtsi index b2557bf..5e4c690 100644 --- a/arch/arm/boot/dts/rk3288-veyron.dtsi +++ b/arch/arm/boot/dts/rk3288-veyron.dtsi @@ -383,6 +383,12 @@ status = "okay"; rx-sample-delay-ns = <12>; + + flash@0 { + compatible = "jedec,spi-nor"; + spi-max-frequency = <50000000>; + reg = <0>; + }; }; &tsadc { -- cgit v0.10.2 From 6c42db30d8c808d1d04a8178a29e085b8b5eb475 Mon Sep 17 00:00:00 2001 From: Enric Balletbo i Serra Date: Mon, 9 May 2016 12:46:34 +0200 Subject: ARM: dts: rockchip: Add shared file for audio on rk3288-veyron boards Set i2s block to "okay", add sound node for max98090 with gpios for HP and Mic detect and pinctrl, and add a max98090 device and ts3a227e to the correct i2c bus. Signed-off-by: Enric Balletbo i Serra Signed-off-by: Heiko Stuebner diff --git a/arch/arm/boot/dts/rk3288-veyron-analog-audio.dtsi b/arch/arm/boot/dts/rk3288-veyron-analog-audio.dtsi new file mode 100644 index 0000000..3d57c05 --- /dev/null +++ b/arch/arm/boot/dts/rk3288-veyron-analog-audio.dtsi @@ -0,0 +1,101 @@ +/* + * Google Veyron (and derivatives) fragment for the max98090 audio + * codec and analog headphone jack. + * + * Copyright 2016 Google, Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/ { + sound { + compatible = "rockchip,rockchip-audio-max98090"; + pinctrl-names = "default"; + pinctrl-0 = <&mic_det>, <&hp_det>; + rockchip,model = "ROCKCHIP-I2S"; + rockchip,i2s-controller = <&i2s>; + rockchip,audio-codec = <&max98090>; + rockchip,hp-det-gpios = <&gpio6 5 GPIO_ACTIVE_HIGH>; + rockchip,mic-det-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>; + rockchip,headset-codec = <&headsetcodec>; + }; +}; + +&i2c2 { + max98090: max98090@10 { + compatible = "maxim,max98090"; + reg = <0x10>; + interrupt-parent = <&gpio6>; + interrupts = <7 IRQ_TYPE_EDGE_FALLING>; + clock-names = "mclk"; + clocks = <&cru SCLK_I2S0_OUT>; + pinctrl-names = "default"; + pinctrl-0 = <&int_codec>; + }; +}; + +&i2c4 { + headsetcodec: ts3a227e@3b { + compatible = "ti,ts3a227e"; + reg = <0x3b>; + interrupt-parent = <&gpio0>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&ts3a227e_int_l>; + ti,micbias = <7>; /* MICBIAS = 2.8V */ + }; +}; + +&i2s { + status = "okay"; +}; + +&io_domains { + audio-supply = <&vcc18_codec>; +}; + +&rk808 { + vcc10-supply = <&vcc33_sys>; + + regulators { + vcc18_codec: LDO_REG6 { + regulator-name = "vcc18_codec"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; +}; + +&pinctrl { + codec { + hp_det: hp-det { + rockchip,pins = <6 5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + /* + * HACK: We're going to _pull down_ this _active low_ interrupt + * so that it never fires. We don't need this interrupt because + * we've got a ts3a227e chip but the driver requires it. + */ + int_codec: int-codec { + rockchip,pins = <6 7 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + mic_det: mic-det { + rockchip,pins = <6 11 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + headset { + ts3a227e_int_l: ts3a227e-int-l { + rockchip,pins = <0 3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; -- cgit v0.10.2 From 7dbc2b97ba8aac7168c39a7f9148110f6eaa5053 Mon Sep 17 00:00:00 2001 From: Enric Balletbo i Serra Date: Mon, 9 May 2016 12:46:35 +0200 Subject: ARM: dts: rockchip: Enable analog audio on rk3288-veyron chromebooks Add analog-audio functionality for Veyron devices. Signed-off-by: Enric Balletbo i Serra Signed-off-by: Heiko Stuebner diff --git a/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi b/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi index 2958c36..ce1f879 100644 --- a/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi +++ b/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi @@ -46,6 +46,7 @@ #include #include #include "rk3288-veyron.dtsi" +#include "rk3288-veyron-analog-audio.dtsi" #include "rk3288-veyron-sdmmc.dtsi" / { -- cgit v0.10.2 From 3445b2fae55f1a232e6e4843f4f74de074d8c07f Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Sat, 21 May 2016 01:36:17 +0200 Subject: ARM: dts: rockchip: move rk3288 io-domain nodes to the grf io-voltage control is actually part of the grf, so move the node under the newly available grf simple-mfd. To minimize duplicate code, the core node and compatible property gets placed in the core rk3288.dtsi while the individual boards now only need to enable it and add the necessary supply properties. Signed-off-by: Heiko Stuebner diff --git a/arch/arm/boot/dts/rk3288-firefly.dtsi b/arch/arm/boot/dts/rk3288-firefly.dtsi index d6cf9ad..114c90fb 100644 --- a/arch/arm/boot/dts/rk3288-firefly.dtsi +++ b/arch/arm/boot/dts/rk3288-firefly.dtsi @@ -64,22 +64,6 @@ clock-output-names = "ext_gmac"; }; - io_domains: io-domains { - compatible = "rockchip,rk3288-io-voltage-domain"; - rockchip,grf = <&grf>; - - audio-supply = <&vcca_33>; - bb-supply = <&vcc_io>; - dvp-supply = <&dovdd_1v8>; - flash0-supply = <&vcc_flash>; - flash1-supply = <&vcc_lan>; - gpio30-supply = <&vcc_io>; - gpio1830-supply = <&vcc_io>; - lcdc-supply = <&vcc_io>; - sdcard-supply = <&vccio_sd>; - wifi-supply = <&vccio_wl>; - }; - ir: ir-receiver { compatible = "gpio-ir-receiver"; pinctrl-names = "default"; @@ -397,6 +381,21 @@ status = "okay"; }; +&io_domains { + status = "okay"; + + audio-supply = <&vcca_33>; + bb-supply = <&vcc_io>; + dvp-supply = <&dovdd_1v8>; + flash0-supply = <&vcc_flash>; + flash1-supply = <&vcc_lan>; + gpio30-supply = <&vcc_io>; + gpio1830-supply = <&vcc_io>; + lcdc-supply = <&vcc_io>; + sdcard-supply = <&vccio_sd>; + wifi-supply = <&vccio_wl>; +}; + &pinctrl { pcfg_output_high: pcfg-output-high { output-high; diff --git a/arch/arm/boot/dts/rk3288-miqi.dts b/arch/arm/boot/dts/rk3288-miqi.dts index 8643103..2448842 100644 --- a/arch/arm/boot/dts/rk3288-miqi.dts +++ b/arch/arm/boot/dts/rk3288-miqi.dts @@ -64,19 +64,6 @@ clock-output-names = "ext_gmac"; }; - io_domains: io-domains { - compatible = "rockchip,rk3288-io-voltage-domain"; - - audio-supply = <&vcca_33>; - flash0-supply = <&vcc_flash>; - flash1-supply = <&vcc_lan>; - gpio30-supply = <&vcc_io>; - gpio1830-supply = <&vcc_io>; - lcdc-supply = <&vcc_io>; - sdcard-supply = <&vccio_sd>; - wifi-supply = <&vcc_18>; - }; - leds { compatible = "gpio-leds"; @@ -321,6 +308,19 @@ status = "okay"; }; +&io_domains { + status = "okay"; + + audio-supply = <&vcca_33>; + flash0-supply = <&vcc_flash>; + flash1-supply = <&vcc_lan>; + gpio30-supply = <&vcc_io>; + gpio1830-supply = <&vcc_io>; + lcdc-supply = <&vcc_io>; + sdcard-supply = <&vccio_sd>; + wifi-supply = <&vcc_18>; +}; + &pinctrl { pcfg_output_high: pcfg-output-high { output-high; diff --git a/arch/arm/boot/dts/rk3288-popmetal.dts b/arch/arm/boot/dts/rk3288-popmetal.dts index 720717b..dda8d25 100644 --- a/arch/arm/boot/dts/rk3288-popmetal.dts +++ b/arch/arm/boot/dts/rk3288-popmetal.dts @@ -77,22 +77,6 @@ }; }; - io_domains: io-domains { - compatible = "rockchip,rk3288-io-voltage-domain"; - rockchip,grf = <&grf>; - - audio-supply = <&vcca_33>; - bb-supply = <&vcc_io>; - dvp-supply = <&vcc18_dvp>; - flash0-supply = <&vcc_flash>; - flash1-supply = <&vcc_lan>; - gpio30-supply = <&vcc_io>; - gpio1830-supply = <&vcc_io>; - lcdc-supply = <&vcc_io>; - sdcard-supply = <&vccio_sd>; - wifi-supply = <&vccio_wl>; - }; - ir: ir-receiver { compatible = "gpio-ir-receiver"; gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; @@ -437,6 +421,21 @@ status = "okay"; }; +&io_domains { + status = "okay"; + + audio-supply = <&vcca_33>; + bb-supply = <&vcc_io>; + dvp-supply = <&vcc18_dvp>; + flash0-supply = <&vcc_flash>; + flash1-supply = <&vcc_lan>; + gpio30-supply = <&vcc_io>; + gpio1830-supply = <&vcc_io>; + lcdc-supply = <&vcc_io>; + sdcard-supply = <&vccio_sd>; + wifi-supply = <&vccio_wl>; +}; + &pinctrl { ak8963 { comp_int: comp-int { diff --git a/arch/arm/boot/dts/rk3288-rock2-som.dtsi b/arch/arm/boot/dts/rk3288-rock2-som.dtsi index e1ee9f9..bb1f01e 100644 --- a/arch/arm/boot/dts/rk3288-rock2-som.dtsi +++ b/arch/arm/boot/dts/rk3288-rock2-som.dtsi @@ -61,22 +61,6 @@ clock-output-names = "ext_gmac"; }; - io_domains: io-domains { - compatible = "rockchip,rk3288-io-voltage-domain"; - rockchip,grf = <&grf>; - - audio-supply = <&vcc_io>; - bb-supply = <&vcc_io>; - dvp-supply = <&vcc_18>; - flash0-supply = <&vcc_flash>; - flash1-supply = <&vccio_pmu>; - gpio30-supply = <&vccio_pmu>; - gpio1830 = <&vcc_io>; - lcdc-supply = <&vcc_io>; - sdcard-supply = <&vccio_sd>; - wifi-supply = <&vcc_18>; - }; - vcc_flash: flash-regulator { compatible = "regulator-fixed"; regulator-name = "vcc_sys"; @@ -259,6 +243,21 @@ }; }; +&io_domains { + status = "okay"; + + audio-supply = <&vcc_io>; + bb-supply = <&vcc_io>; + dvp-supply = <&vcc_18>; + flash0-supply = <&vcc_flash>; + flash1-supply = <&vccio_pmu>; + gpio30-supply = <&vccio_pmu>; + gpio1830 = <&vcc_io>; + lcdc-supply = <&vcc_io>; + sdcard-supply = <&vccio_sd>; + wifi-supply = <&vcc_18>; +}; + &pinctrl { pcfg_output_high: pcfg-output-high { output-high; diff --git a/arch/arm/boot/dts/rk3288-veyron.dtsi b/arch/arm/boot/dts/rk3288-veyron.dtsi index 5e4c690..3dd2cca 100644 --- a/arch/arm/boot/dts/rk3288-veyron.dtsi +++ b/arch/arm/boot/dts/rk3288-veyron.dtsi @@ -83,19 +83,6 @@ reset-gpios = <&gpio2 9 GPIO_ACTIVE_HIGH>; }; - io_domains: io-domains { - compatible = "rockchip,rk3288-io-voltage-domain"; - rockchip,grf = <&grf>; - - bb-supply = <&vcc33_io>; - dvp-supply = <&vcc_18>; - flash0-supply = <&vcc18_flashio>; - gpio1830-supply = <&vcc33_io>; - gpio30-supply = <&vcc33_io>; - lcdc-supply = <&vcc33_lcd>; - wifi-supply = <&vcc18_wl>; - }; - sdio_pwrseq: sdio-pwrseq { compatible = "mmc-pwrseq-simple"; clocks = <&rk808 RK808_CLKOUT1>; @@ -355,6 +342,18 @@ i2c-scl-rising-time-ns = <1000>; }; +&io_domains { + status = "okay"; + + bb-supply = <&vcc33_io>; + dvp-supply = <&vcc_18>; + flash0-supply = <&vcc18_flashio>; + gpio1830-supply = <&vcc33_io>; + gpio30-supply = <&vcc33_io>; + lcdc-supply = <&vcc33_lcd>; + wifi-supply = <&vcc18_wl>; +}; + &pwm1 { status = "okay"; }; diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index 3b44ef3..7fa932f 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -826,6 +826,11 @@ #phy-cells = <0>; status = "disabled"; }; + + io_domains: io-domains { + compatible = "rockchip,rk3288-io-voltage-domain"; + status = "disabled"; + }; }; wdt: watchdog@ff800000 { -- cgit v0.10.2 From 0f0677f6eb1797a007dadbad54538fde7102965c Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 4 May 2016 14:43:58 +0200 Subject: ARM: dts: exynos: Define vqmmc for SD card and allow disabling regulators on Odroid X/X2/U3 The SD-card vmmc-supply contained incorrectly two regulators. The second one is ignored. Fix this by defining proper vmmc and vqmmc supplies. Additionally these regulators do not have to be always on, so allow disabling them to reduce energy consumption. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Javier Martinez Canillas diff --git a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi index ec7619a..fe483ba 100644 --- a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi +++ b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi @@ -297,7 +297,6 @@ regulator-name = "VDDQ_MMC2_2.8V"; regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; - regulator-always-on; regulator-boot-on; }; @@ -393,7 +392,6 @@ regulator-name = "LDO21_3.3V"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - regulator-always-on; regulator-boot-on; }; @@ -530,7 +528,8 @@ bus-width = <4>; pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; pinctrl-names = "default"; - vmmc-supply = <&ldo4_reg &ldo21_reg>; + vmmc-supply = <&ldo21_reg>; + vqmmc-supply = <&ldo4_reg>; cd-gpios = <&gpk2 2 GPIO_ACTIVE_HIGH>; cd-inverted; status = "okay"; -- cgit v0.10.2 From 303ce7161c002b44d8d19340862276dce66fb6f5 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 4 May 2016 14:43:59 +0200 Subject: ARM: dts: exynos: Define vqmmc for eMMC card on Odroid X/X2/U3 The eMMC card vmmc-supply contained incorrectly two regulators: LDO20 and buck8. The second one is ignored. Additionally the buck8 is a vqmmc supply only on X and X2. On U3 the buck8 is providing power to the LAN (SMSC95xx) so instead the LDO22 should be used. Fix this by defining proper vmmc and vqmmc supplies for respective boards. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Javier Martinez Canillas diff --git a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi index fe483ba..a31d34e 100644 --- a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi +++ b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi @@ -395,6 +395,15 @@ regulator-boot-on; }; + ldo22_reg: LDO22 { + /* + * Only U3 uses it, so let it define the + * constraints + */ + regulator-name = "LDO22"; + regulator-boot-on; + }; + ldo25_reg: LDO25 { regulator-name = "VDDQ_LCD_1.8V"; regulator-min-microvolt = <1800000>; @@ -458,9 +467,11 @@ }; buck8_reg: BUCK8 { + /* + * Constraints set by specific board: X, + * X2 and U3. + */ regulator-name = "BUCK8_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; }; }; }; @@ -504,7 +515,7 @@ &mshc_0 { pinctrl-0 = <&sd4_clk &sd4_cmd &sd4_bus4 &sd4_bus8>; pinctrl-names = "default"; - vmmc-supply = <&ldo20_reg &buck8_reg>; + vmmc-supply = <&ldo20_reg>; mmc-pwrseq = <&emmc_pwrseq>; status = "okay"; diff --git a/arch/arm/boot/dts/exynos4412-odroidu3.dts b/arch/arm/boot/dts/exynos4412-odroidu3.dts index dd89f7b..d73aa6c 100644 --- a/arch/arm/boot/dts/exynos4412-odroidu3.dts +++ b/arch/arm/boot/dts/exynos4412-odroidu3.dts @@ -69,6 +69,24 @@ }; }; +/* Supply for LAN9730/SMSC95xx */ +&buck8_reg { + regulator-name = "BUCK8_P3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; +}; + +/* VDDQ for MSHC (eMMC card) */ +&ldo22_reg { + regulator-name = "LDO22_VDDQ_MMC4_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; +}; + +&mshc_0 { + vqmmc-supply = <&ldo22_reg>; +}; + &pwm { pinctrl-0 = <&pwm0_out>; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/exynos4412-odroidx.dts b/arch/arm/boot/dts/exynos4412-odroidx.dts index bf7b21b..2af2351 100644 --- a/arch/arm/boot/dts/exynos4412-odroidx.dts +++ b/arch/arm/boot/dts/exynos4412-odroidx.dts @@ -63,12 +63,23 @@ }; }; +/* VDDQ for MSHC (eMMC card) */ +&buck8_reg { + regulator-name = "BUCK8_VDDQ_MMC4_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; +}; + &ehci { port@1 { status = "okay"; }; }; +&mshc_0 { + vqmmc-supply = <&buck8_reg>; +}; + &pinctrl_1 { gpio_home_key: home_key { samsung,pins = "gpx2-2"; diff --git a/arch/arm/boot/dts/exynos4412-odroidx2.dts b/arch/arm/boot/dts/exynos4412-odroidx2.dts index 6e33678..3e35842 100644 --- a/arch/arm/boot/dts/exynos4412-odroidx2.dts +++ b/arch/arm/boot/dts/exynos4412-odroidx2.dts @@ -22,6 +22,17 @@ }; }; +/* VDDQ for MSHC (eMMC card) */ +&buck8_reg { + regulator-name = "BUCK8_VDDQ_MMC4_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; +}; + +&mshc_0 { + vqmmc-supply = <&buck8_reg>; +}; + &sound { simple-audio-card,name = "Odroid-X2"; simple-audio-card,widgets = -- cgit v0.10.2 From 885fdf7b13beb72eacc964345becc0adf811c46c Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 4 May 2016 14:44:00 +0200 Subject: ARM: dts: exynos: Lower SD card interface voltage to 2.8 V on Odroid X/X2/U3 Odroid X/X2/U3 schematics say that SD card vmmc regulator (LDO21/TFLASH) operates on 2.8 V. Mainline U-Boot uses that value as well and 2.8 V is common on Exynos-based boards. Additionally use some descriptive name for this regulator. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Javier Martinez Canillas diff --git a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi index a31d34e..2a7df43 100644 --- a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi +++ b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi @@ -389,9 +389,9 @@ }; ldo21_reg: LDO21 { - regulator-name = "LDO21_3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; + regulator-name = "TFLASH_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; regulator-boot-on; }; -- cgit v0.10.2 From f4715dc7eb89e1e776ab2c260cb008617490f931 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 9 May 2016 08:19:49 +0200 Subject: ARM: dts: exynos: Only Odroid XU3-family boards use DTSI with CPU thermal nodes Include the CPU thermal nodes directly in Odroid XU3-family common DTS because it is the only user of it. Keeping it in separate DTSI file does not bring benefits because: 1. It is not re-usable on other non-fan boards (fan is referenced), 2. It won't be re-used on future Odroid XU board because different CPU cluster behavior. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Javier Martinez Canillas Tested-by: Anand Moon diff --git a/arch/arm/boot/dts/exynos5422-cpu-thermal.dtsi b/arch/arm/boot/dts/exynos5422-cpu-thermal.dtsi deleted file mode 100644 index 3e4c4ad..0000000 --- a/arch/arm/boot/dts/exynos5422-cpu-thermal.dtsi +++ /dev/null @@ -1,103 +0,0 @@ -/* - * Device tree sources for Exynos5422 thermal zone - * - * Copyright (c) 2015 Lukasz Majewski - * Anand Moon - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ - -#include - -/ { - thermal-zones { - cpu0_thermal: cpu0-thermal { - thermal-sensors = <&tmu_cpu0 0>; - polling-delay-passive = <250>; - polling-delay = <0>; - trips { - cpu_alert0: cpu-alert-0 { - temperature = <50000>; /* millicelsius */ - hysteresis = <5000>; /* millicelsius */ - type = "active"; - }; - cpu_alert1: cpu-alert-1 { - temperature = <60000>; /* millicelsius */ - hysteresis = <5000>; /* millicelsius */ - type = "active"; - }; - cpu_alert2: cpu-alert-2 { - temperature = <70000>; /* millicelsius */ - hysteresis = <5000>; /* millicelsius */ - type = "active"; - }; - cpu_crit0: cpu-crit-0 { - temperature = <120000>; /* millicelsius */ - hysteresis = <0>; /* millicelsius */ - type = "critical"; - }; - /* - * Exyunos542x support only 4 trip-points - * so for these polling mode is required. - * Start polling at temperature level of last - * interrupt-driven trip: cpu_alert2 - */ - cpu_alert3: cpu-alert-3 { - temperature = <70000>; /* millicelsius */ - hysteresis = <10000>; /* millicelsius */ - type = "passive"; - }; - cpu_alert4: cpu-alert-4 { - temperature = <85000>; /* millicelsius */ - hysteresis = <10000>; /* millicelsius */ - type = "passive"; - }; - - }; - cooling-maps { - map0 { - trip = <&cpu_alert0>; - cooling-device = <&fan0 0 1>; - }; - map1 { - trip = <&cpu_alert1>; - cooling-device = <&fan0 1 2>; - }; - map2 { - trip = <&cpu_alert2>; - cooling-device = <&fan0 2 3>; - }; - /* - * When reaching cpu_alert3, reduce CPU - * by 2 steps. On Exynos5422/5800 that would - * be: 1500 MHz and 1100 MHz. - */ - map3 { - trip = <&cpu_alert3>; - cooling-device = <&cpu0 0 2>; - }; - map4 { - trip = <&cpu_alert3>; - cooling-device = <&cpu4 0 2>; - }; - - /* - * When reaching cpu_alert4, reduce CPU - * further, down to 600 MHz (11 steps for big, - * 7 steps for LITTLE). - */ - map5 { - trip = <&cpu_alert4>; - cooling-device = <&cpu0 3 7>; - }; - map6 { - trip = <&cpu_alert4>; - cooling-device = <&cpu4 3 11>; - }; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi index 2a4e10b..48c92b4 100644 --- a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi +++ b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi @@ -1,9 +1,11 @@ /* * Hardkernel Odroid XU3 board device tree source * - * Copyright (c) 2014 Collabora Ltd. * Copyright (c) 2013 Samsung Electronics Co., Ltd. * http://www.samsung.com + * Copyright (c) 2014 Collabora Ltd. + * Copyright (c) 2015 Lukasz Majewski + * Anand Moon * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -16,7 +18,6 @@ #include #include "exynos5800.dtsi" #include "exynos5422-cpus.dtsi" -#include "exynos5422-cpu-thermal.dtsi" / { memory { @@ -54,6 +55,94 @@ #cooling-cells = <2>; cooling-levels = <0 130 170 230>; }; + + thermal-zones { + cpu0_thermal: cpu0-thermal { + thermal-sensors = <&tmu_cpu0 0>; + polling-delay-passive = <250>; + polling-delay = <0>; + trips { + cpu_alert0: cpu-alert-0 { + temperature = <50000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "active"; + }; + cpu_alert1: cpu-alert-1 { + temperature = <60000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "active"; + }; + cpu_alert2: cpu-alert-2 { + temperature = <70000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "active"; + }; + cpu_crit0: cpu-crit-0 { + temperature = <120000>; /* millicelsius */ + hysteresis = <0>; /* millicelsius */ + type = "critical"; + }; + /* + * Exynos542x supports only 4 trip-points + * so for these polling mode is required. + * Start polling at temperature level of last + * interrupt-driven trip: cpu_alert2 + */ + cpu_alert3: cpu-alert-3 { + temperature = <70000>; /* millicelsius */ + hysteresis = <10000>; /* millicelsius */ + type = "passive"; + }; + cpu_alert4: cpu-alert-4 { + temperature = <85000>; /* millicelsius */ + hysteresis = <10000>; /* millicelsius */ + type = "passive"; + }; + + }; + cooling-maps { + map0 { + trip = <&cpu_alert0>; + cooling-device = <&fan0 0 1>; + }; + map1 { + trip = <&cpu_alert1>; + cooling-device = <&fan0 1 2>; + }; + map2 { + trip = <&cpu_alert2>; + cooling-device = <&fan0 2 3>; + }; + /* + * When reaching cpu_alert3, reduce CPU + * by 2 steps. On Exynos5422/5800 that would + * be: 1600 MHz and 1100 MHz. + */ + map3 { + trip = <&cpu_alert3>; + cooling-device = <&cpu0 0 2>; + }; + map4 { + trip = <&cpu_alert3>; + cooling-device = <&cpu4 0 2>; + }; + + /* + * When reaching cpu_alert4, reduce CPU + * further, down to 600 MHz (11 steps for big, + * 7 steps for LITTLE). + */ + map5 { + trip = <&cpu_alert4>; + cooling-device = <&cpu0 3 7>; + }; + map6 { + trip = <&cpu_alert4>; + cooling-device = <&cpu4 3 11>; + }; + }; + }; + }; }; &bus_wcore { -- cgit v0.10.2 From 4e8991def565dc46278fe4d320c06ba20af9e0f7 Mon Sep 17 00:00:00 2001 From: Matthew Leach Date: Wed, 11 May 2016 09:06:52 +0200 Subject: ARM: dts: exynos: Enable AX88760 USB hub on Origen board Enable the Origen's usb phy and ohci devices in the device tree. Also add the "samsung,vbus-gpio" property to enable the GPX3(5) gpio pin so the AX88760 hub is powered. Signed-off-by: Matthew Leach [k.kozlowski: Extend nodes by label notation instead of path] Signed-off-by: Krzysztof Kozlowski diff --git a/arch/arm/boot/dts/exynos4412-origen.dts b/arch/arm/boot/dts/exynos4412-origen.dts index 8bca699..7e53b6f 100644 --- a/arch/arm/boot/dts/exynos4412-origen.dts +++ b/arch/arm/boot/dts/exynos4412-origen.dts @@ -83,6 +83,22 @@ cpu0-supply = <&buck2_reg>; }; +&exynos_usbphy { + status = "okay"; +}; + +&ehci { + samsung,vbus-gpio = <&gpx3 5 1>; + status = "okay"; + + port@1{ + status = "okay"; + }; + port@2 { + status = "okay"; + }; +}; + &fimd { pinctrl-0 = <&lcd_clk &lcd_data24 &pwm1_out>; pinctrl-names = "default"; -- cgit v0.10.2 From 665c441eea3d63a4cedf66d3eef5f3ffb26378f5 Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Thu, 19 May 2016 17:52:33 -0400 Subject: ARM: dts: exynos: Remove unneded always-on for regulators on Peach boards The regulator always-on property should only be used for regulators that either can't be disabled or the drivers for the client devices are not enabling the regulator and so being disabled due to unused. There are some max77802 regulators in the Peach Pit and Pi boards that are always-on but shouldn't since they are enabled by drivers: BUCK5 is max77802 inl1 supply BUCK7 is max77802 inl{2,10} supply BUCK9 is max77802 inl{3,4,5,7} supply BUCK10 is mmc1 vqmmc supply LDO9 is adc vdd supply This patch removes the always-on property for these regulators. Some regulators should remain always-on even when they are used as input supplies, because these regulators are also used by other components that are not described in the DT, for example: LDO10 is hdmi vdd_osc supply but it's also used as input supply for the Exynos5420 temperature sensor. LDO8 is hdmi vdd and vdd_pll supply but it's also used as supply for the Exynos5420 Display port. BUCK2 and BUCK6 are the vdd supplies for the EAGLE and KFC clusters. Signed-off-by: Javier Martinez Canillas Reviewed-by: Krzysztof Kozlowski Signed-off-by: Krzysztof Kozlowski diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts b/arch/arm/boot/dts/exynos5420-peach-pit.dts index f9d2e4f..c124740 100644 --- a/arch/arm/boot/dts/exynos5420-peach-pit.dts +++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts @@ -278,7 +278,6 @@ regulator-name = "vdd_1v2"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; - regulator-always-on; regulator-boot-on; regulator-state-mem { regulator-off-in-suspend; @@ -301,7 +300,6 @@ regulator-name = "vdd_1v35"; regulator-min-microvolt = <1350000>; regulator-max-microvolt = <1350000>; - regulator-always-on; regulator-boot-on; regulator-state-mem { regulator-on-in-suspend; @@ -323,7 +321,6 @@ regulator-name = "vdd_2v"; regulator-min-microvolt = <2000000>; regulator-max-microvolt = <2000000>; - regulator-always-on; regulator-boot-on; regulator-state-mem { regulator-on-in-suspend; @@ -334,7 +331,6 @@ regulator-name = "vdd_1v8"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; - regulator-always-on; regulator-boot-on; regulator-state-mem { regulator-on-in-suspend; @@ -419,7 +415,6 @@ regulator-name = "vdd_ldo9"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; - regulator-always-on; regulator-state-mem { regulator-on-in-suspend; regulator-mode = ; diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts b/arch/arm/boot/dts/exynos5800-peach-pi.dts index 62ceb89..af1c9b9 100644 --- a/arch/arm/boot/dts/exynos5800-peach-pi.dts +++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts @@ -278,7 +278,6 @@ regulator-name = "vdd_1v2"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; - regulator-always-on; regulator-boot-on; regulator-state-mem { regulator-off-in-suspend; @@ -301,7 +300,6 @@ regulator-name = "vdd_1v35"; regulator-min-microvolt = <1350000>; regulator-max-microvolt = <1350000>; - regulator-always-on; regulator-boot-on; regulator-state-mem { regulator-on-in-suspend; @@ -323,7 +321,6 @@ regulator-name = "vdd_2v"; regulator-min-microvolt = <2000000>; regulator-max-microvolt = <2000000>; - regulator-always-on; regulator-boot-on; regulator-state-mem { regulator-on-in-suspend; @@ -334,7 +331,6 @@ regulator-name = "vdd_1v8"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; - regulator-always-on; regulator-boot-on; regulator-state-mem { regulator-on-in-suspend; @@ -419,7 +415,6 @@ regulator-name = "vdd_ldo9"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; - regulator-always-on; regulator-state-mem { regulator-on-in-suspend; regulator-mode = ; -- cgit v0.10.2 From dd9ad46863091a926537a0b6d956ff438f0e8332 Mon Sep 17 00:00:00 2001 From: Naveen Krishna Chatradhi Date: Wed, 25 Jun 2014 11:59:32 +0530 Subject: ARM: dts: exynos: Use new compatible string for thermistors in Trats2 As Murata Manufactures the NTC based thermistors. The vendor name in the compatibility is preposed to change to "murata". This patch uses the new compatibility string in Exynos4412 based Trats2 board. Signed-off-by: Naveen Krishna Chatradhi Cc: Chanwoo Choi Reviewed-by: Chanwoo Choi Signed-off-by: Krzysztof Kozlowski diff --git a/arch/arm/boot/dts/exynos4412-trats2.dts b/arch/arm/boot/dts/exynos4412-trats2.dts index 9336fd4..129e973 100644 --- a/arch/arm/boot/dts/exynos4412-trats2.dts +++ b/arch/arm/boot/dts/exynos4412-trats2.dts @@ -253,7 +253,7 @@ }; thermistor-ap { - compatible = "ntc,ncp15wb473"; + compatible = "murata,ncp15wb473"; pullup-uv = <1800000>; /* VCC_1.8V_AP */ pullup-ohm = <100000>; /* 100K */ pulldown-ohm = <100000>; /* 100K */ @@ -261,7 +261,7 @@ }; thermistor-battery { - compatible = "ntc,ncp15wb473"; + compatible = "murata,ncp15wb473"; pullup-uv = <1800000>; /* VCC_1.8V_AP */ pullup-ohm = <100000>; /* 100K */ pulldown-ohm = <100000>; /* 100K */ -- cgit v0.10.2 From 7b336fc88b9e2c981aeb3da33b2d7b4bc1f910f0 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 10 May 2016 20:16:57 +0200 Subject: ARM: dts: exynos: Replace deprecated hsi2c compatible on Exynos5420 Since commit 218e1496135e ("i2c: exynos5: add support for HSI2C on Exynos5260 SoC") the "samsung,exynos5-hsi2c" is deprecated in favor of SoC version specific: "samsung,exynos5250-hsi2c". Signed-off-by: Krzysztof Kozlowski diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index c6e05eb..9d99e43 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -681,7 +681,7 @@ }; hsi2c_4: i2c@12CA0000 { - compatible = "samsung,exynos5-hsi2c"; + compatible = "samsung,exynos5250-hsi2c"; reg = <0x12CA0000 0x1000>; interrupts = <0 60 0>; #address-cells = <1>; @@ -694,7 +694,7 @@ }; hsi2c_5: i2c@12CB0000 { - compatible = "samsung,exynos5-hsi2c"; + compatible = "samsung,exynos5250-hsi2c"; reg = <0x12CB0000 0x1000>; interrupts = <0 61 0>; #address-cells = <1>; @@ -707,7 +707,7 @@ }; hsi2c_6: i2c@12CC0000 { - compatible = "samsung,exynos5-hsi2c"; + compatible = "samsung,exynos5250-hsi2c"; reg = <0x12CC0000 0x1000>; interrupts = <0 62 0>; #address-cells = <1>; @@ -720,7 +720,7 @@ }; hsi2c_7: i2c@12CD0000 { - compatible = "samsung,exynos5-hsi2c"; + compatible = "samsung,exynos5250-hsi2c"; reg = <0x12CD0000 0x1000>; interrupts = <0 63 0>; #address-cells = <1>; @@ -733,7 +733,7 @@ }; hsi2c_8: i2c@12E00000 { - compatible = "samsung,exynos5-hsi2c"; + compatible = "samsung,exynos5250-hsi2c"; reg = <0x12E00000 0x1000>; interrupts = <0 87 0>; #address-cells = <1>; @@ -746,7 +746,7 @@ }; hsi2c_9: i2c@12E10000 { - compatible = "samsung,exynos5-hsi2c"; + compatible = "samsung,exynos5250-hsi2c"; reg = <0x12E10000 0x1000>; interrupts = <0 88 0>; #address-cells = <1>; @@ -759,7 +759,7 @@ }; hsi2c_10: i2c@12E20000 { - compatible = "samsung,exynos5-hsi2c"; + compatible = "samsung,exynos5250-hsi2c"; reg = <0x12E20000 0x1000>; interrupts = <0 203 0>; #address-cells = <1>; -- cgit v0.10.2 From b98485030d165c60f46f1b768043e9dca5db2678 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 3 May 2016 13:55:46 +0200 Subject: ARM: dts: exynos: Re-order alphabetically Exynos5420 SD0/SD1 pinctrl nodes The 'sd0_rclk' was put in the middle of SD1 nodes. Remove the confusion. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Javier Martinez Canillas Tested-by: Javier Martinez Canillas diff --git a/arch/arm/boot/dts/exynos5420-pinctrl.dtsi b/arch/arm/boot/dts/exynos5420-pinctrl.dtsi index 130563b..14beb7e 100644 --- a/arch/arm/boot/dts/exynos5420-pinctrl.dtsi +++ b/arch/arm/boot/dts/exynos5420-pinctrl.dtsi @@ -193,17 +193,17 @@ samsung,pin-drv = <3>; }; - sd1_clk: sd1-clk { - samsung,pins = "gpc1-0"; + sd0_rclk: sd0-rclk { + samsung,pins = "gpc0-7"; samsung,pin-function = <2>; - samsung,pin-pud = <0>; + samsung,pin-pud = <1>; samsung,pin-drv = <3>; }; - sd0_rclk: sd0-rclk { - samsung,pins = "gpc0-7"; + sd1_clk: sd1-clk { + samsung,pins = "gpc1-0"; samsung,pin-function = <2>; - samsung,pin-pud = <1>; + samsung,pin-pud = <0>; samsung,pin-drv = <3>; }; -- cgit v0.10.2 From 2cbc0de15cf800cf88cfcc08c23269c083ae814a Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 16 May 2016 10:26:48 +0200 Subject: ARM: dts: exynos: Enable CLKOUT on Exynos5410 The CLKOUT (which control is provided by PMU) is necessary for some of the drivers using this as a clock, e.g. usb3503 USB HUB on Odroid XU board. Signed-off-by: Krzysztof Kozlowski diff --git a/arch/arm/boot/dts/exynos5410.dtsi b/arch/arm/boot/dts/exynos5410.dtsi index 7a56aec..477c674 100644 --- a/arch/arm/boot/dts/exynos5410.dtsi +++ b/arch/arm/boot/dts/exynos5410.dtsi @@ -116,6 +116,9 @@ pmu_system_controller: system-controller@10040000 { compatible = "samsung,exynos5410-pmu", "syscon"; reg = <0x10040000 0x5000>; + clock-names = "clkout16"; + clocks = <&fin_pll>; + #clock-cells = <1>; }; mct: mct@101C0000 { -- cgit v0.10.2 From c37ccce1e8263925b649ab8a7e787149a208627f Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 3 May 2016 13:56:51 +0200 Subject: ARM: dts: exynos: Use lowercase for Exynos5410 CPU node labels For consistency lowercase node labels are used. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Javier Martinez Canillas diff --git a/arch/arm/boot/dts/exynos5410.dtsi b/arch/arm/boot/dts/exynos5410.dtsi index 477c674..ef60a06 100644 --- a/arch/arm/boot/dts/exynos5410.dtsi +++ b/arch/arm/boot/dts/exynos5410.dtsi @@ -35,28 +35,28 @@ #address-cells = <1>; #size-cells = <0>; - CPU0: cpu@0 { + cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <0x0>; clock-frequency = <1600000000>; }; - CPU1: cpu@1 { + cpu1: cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <0x1>; clock-frequency = <1600000000>; }; - CPU2: cpu@2 { + cpu2: cpu@2 { device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <0x2>; clock-frequency = <1600000000>; }; - CPU3: cpu@3 { + cpu3: cpu@3 { device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <0x3>; -- cgit v0.10.2 From 5e4b134c3cf68f0d5f21993eeffd545c208ab26d Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 3 May 2016 13:59:47 +0200 Subject: ARM: dts: exynos: Configure Exynos5410 pinctrl for eMMC and SD card Configure the pinctrl for MMC0 (eMMC) and MMC2 (microSD card). Signed-off-by: Krzysztof Kozlowski Reviewed-by: Javier Martinez Canillas diff --git a/arch/arm/boot/dts/exynos5410-pinctrl.dtsi b/arch/arm/boot/dts/exynos5410-pinctrl.dtsi index f9aa6bb..ddacafa 100644 --- a/arch/arm/boot/dts/exynos5410-pinctrl.dtsi +++ b/arch/arm/boot/dts/exynos5410-pinctrl.dtsi @@ -277,6 +277,83 @@ interrupt-controller; #interrupt-cells = <2>; }; + + sd0_clk: sd0-clk { + samsung,pins = "gpc0-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <3>; + }; + + sd0_cmd: sd0-cmd { + samsung,pins = "gpc0-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <3>; + }; + + sd0_cd: sd0-cd { + samsung,pins = "gpc0-2"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd0_bus1: sd0-bus-width1 { + samsung,pins = "gpc0-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd0_bus4: sd0-bus-width4 { + samsung,pins = "gpc0-4", "gpc0-5", "gpc0-6"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd2_clk: sd2-clk { + samsung,pins = "gpc2-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <3>; + }; + + sd2_cmd: sd2-cmd { + samsung,pins = "gpc2-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <3>; + }; + + sd2_cd: sd2-cd { + samsung,pins = "gpc2-2"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd2_bus1: sd2-bus-width1 { + samsung,pins = "gpc2-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd2_bus4: sd2-bus-width4 { + samsung,pins = "gpc2-4", "gpc2-5", "gpc2-6"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd0_bus8: sd0-bus-width8 { + samsung,pins = "gpc3-0", "gpc3-1", "gpc3-2", "gpc3-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; }; &pinctrl_1 { -- cgit v0.10.2 From 8c2bd87eefc7869f1782ed4f52f8bb7bbd60951d Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 3 May 2016 14:35:51 +0200 Subject: ARM: dts: exynos: Split Odroid XU3 LEDs to separate DTSI The LED nodes can be shared between Odroid XU3, XU3-Lite and XU (not yet added) thus removing duplication. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Javier Martinez Canillas Tested-by: Javier Martinez Canillas diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts b/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts index 2ae1cf4..03fa88c 100644 --- a/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts +++ b/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts @@ -14,44 +14,11 @@ /dts-v1/; #include "exynos5422-odroidxu3-common.dtsi" #include "exynos5422-odroidxu3-audio.dtsi" +#include "exynos54xx-odroidxu-leds.dtsi" / { model = "Hardkernel Odroid XU3 Lite"; compatible = "hardkernel,odroid-xu3-lite", "samsung,exynos5800", "samsung,exynos5"; - - pwmleds { - compatible = "pwm-leds"; - - greenled { - label = "green:mmc0"; - pwms = <&pwm 1 2000000 0>; - pwm-names = "pwm1"; - /* - * Green LED is much brighter than the others - * so limit its max brightness - */ - max_brightness = <127>; - linux,default-trigger = "mmc0"; - }; - - blueled { - label = "blue:heartbeat"; - pwms = <&pwm 2 2000000 0>; - pwm-names = "pwm2"; - max_brightness = <255>; - linux,default-trigger = "heartbeat"; - }; - }; - - gpioleds { - compatible = "gpio-leds"; - redled { - label = "red:microSD"; - gpios = <&gpx2 3 GPIO_ACTIVE_HIGH>; - default-state = "off"; - linux,default-trigger = "mmc1"; - }; - }; }; &pwm { diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3.dts b/arch/arm/boot/dts/exynos5422-odroidxu3.dts index 432406d..9ed6564 100644 --- a/arch/arm/boot/dts/exynos5422-odroidxu3.dts +++ b/arch/arm/boot/dts/exynos5422-odroidxu3.dts @@ -13,44 +13,11 @@ /dts-v1/; #include "exynos5422-odroidxu3-common.dtsi" #include "exynos5422-odroidxu3-audio.dtsi" +#include "exynos54xx-odroidxu-leds.dtsi" / { model = "Hardkernel Odroid XU3"; compatible = "hardkernel,odroid-xu3", "samsung,exynos5800", "samsung,exynos5"; - - pwmleds { - compatible = "pwm-leds"; - - greenled { - label = "green:mmc0"; - pwms = <&pwm 1 2000000 0>; - pwm-names = "pwm1"; - /* - * Green LED is much brighter than the others - * so limit its max brightness - */ - max_brightness = <127>; - linux,default-trigger = "mmc0"; - }; - - blueled { - label = "blue:heartbeat"; - pwms = <&pwm 2 2000000 0>; - pwm-names = "pwm2"; - max_brightness = <255>; - linux,default-trigger = "heartbeat"; - }; - }; - - gpioleds { - compatible = "gpio-leds"; - redled { - label = "red:microSD"; - gpios = <&gpx2 3 GPIO_ACTIVE_HIGH>; - default-state = "off"; - linux,default-trigger = "mmc1"; - }; - }; }; &i2c_0 { diff --git a/arch/arm/boot/dts/exynos54xx-odroidxu-leds.dtsi b/arch/arm/boot/dts/exynos54xx-odroidxu-leds.dtsi new file mode 100644 index 0000000..0ed3020 --- /dev/null +++ b/arch/arm/boot/dts/exynos54xx-odroidxu-leds.dtsi @@ -0,0 +1,50 @@ +/* + * Hardkernel Odroid XU/XU3 LED device tree source + * + * Copyright (c) 2015,2016 Krzysztof Kozlowski + * Copyright (c) 2014 Collabora Ltd. + * Copyright (c) 2013 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include + +/ { + pwmleds { + compatible = "pwm-leds"; + + greenled { + label = "green:mmc0"; + pwms = <&pwm 1 2000000 0>; + pwm-names = "pwm1"; + /* + * Green LED is much brighter than the others + * so limit its max brightness + */ + max_brightness = <127>; + linux,default-trigger = "mmc0"; + }; + + blueled { + label = "blue:heartbeat"; + pwms = <&pwm 2 2000000 0>; + pwm-names = "pwm2"; + max_brightness = <255>; + linux,default-trigger = "heartbeat"; + }; + }; + + gpioleds { + compatible = "gpio-leds"; + redled { + label = "red:microSD"; + gpios = <&gpx2 3 GPIO_ACTIVE_HIGH>; + default-state = "off"; + linux,default-trigger = "mmc1"; + }; + }; +}; -- cgit v0.10.2 From 5a124fe0b1d7e921d250c0352b48148e280ad9f4 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 3 May 2016 14:51:25 +0200 Subject: ARM: dts: exynos: Move common nodes to exynos5.dtsi Exynos5420 and Exynos5250 share some nodes: the PWM, syscon (sysreg_system_controller) and first four I2C controllers. Move them to parent DTSI to avoid duplication. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Javier Martinez Canillas Tested-by: Javier Martinez Canillas diff --git a/arch/arm/boot/dts/exynos5.dtsi b/arch/arm/boot/dts/exynos5.dtsi index d5c0f18..c5d198c 100644 --- a/arch/arm/boot/dts/exynos5.dtsi +++ b/arch/arm/boot/dts/exynos5.dtsi @@ -20,6 +20,10 @@ interrupt-parent = <&gic>; aliases { + i2c0 = &i2c_0; + i2c1 = &i2c_1; + i2c2 = &i2c_2; + i2c3 = &i2c_3; serial0 = &serial_0; serial1 = &serial_1; serial2 = &serial_2; @@ -63,6 +67,11 @@ interrupts = <1 9 0xf04>; }; + sysreg_system_controller: syscon@10050000 { + compatible = "samsung,exynos5-sysreg", "syscon"; + reg = <0x10050000 0x5000>; + }; + serial_0: serial@12C00000 { compatible = "samsung,exynos4210-uart"; reg = <0x12C00000 0x100>; @@ -87,6 +96,53 @@ interrupts = <0 54 0>; }; + i2c_0: i2c@12C60000 { + compatible = "samsung,s3c2440-i2c"; + reg = <0x12C60000 0x100>; + interrupts = <0 56 0>; + #address-cells = <1>; + #size-cells = <0>; + samsung,sysreg-phandle = <&sysreg_system_controller>; + status = "disabled"; + }; + + i2c_1: i2c@12C70000 { + compatible = "samsung,s3c2440-i2c"; + reg = <0x12C70000 0x100>; + interrupts = <0 57 0>; + #address-cells = <1>; + #size-cells = <0>; + samsung,sysreg-phandle = <&sysreg_system_controller>; + status = "disabled"; + }; + + i2c_2: i2c@12C80000 { + compatible = "samsung,s3c2440-i2c"; + reg = <0x12C80000 0x100>; + interrupts = <0 58 0>; + #address-cells = <1>; + #size-cells = <0>; + samsung,sysreg-phandle = <&sysreg_system_controller>; + status = "disabled"; + }; + + i2c_3: i2c@12C90000 { + compatible = "samsung,s3c2440-i2c"; + reg = <0x12C90000 0x100>; + interrupts = <0 59 0>; + #address-cells = <1>; + #size-cells = <0>; + samsung,sysreg-phandle = <&sysreg_system_controller>; + status = "disabled"; + }; + + pwm: pwm@12DD0000 { + compatible = "samsung,exynos4210-pwm"; + reg = <0x12DD0000 0x100>; + samsung,pwm-outputs = <0>, <1>, <2>, <3>; + #pwm-cells = <3>; + }; + rtc: rtc@101E0000 { compatible = "samsung,s3c6410-rtc"; reg = <0x101E0000 0x100>; diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi index c7158b2..ae4970d 100644 --- a/arch/arm/boot/dts/exynos5250.dtsi +++ b/arch/arm/boot/dts/exynos5250.dtsi @@ -37,10 +37,6 @@ mshc1 = &mmc_1; mshc2 = &mmc_2; mshc3 = &mmc_3; - i2c0 = &i2c_0; - i2c1 = &i2c_1; - i2c2 = &i2c_2; - i2c3 = &i2c_3; i2c4 = &i2c_4; i2c5 = &i2c_5; i2c6 = &i2c_6; @@ -235,11 +231,6 @@ interrupt-parent = <&gic>; }; - sysreg_system_controller: syscon@10050000 { - compatible = "samsung,exynos5-sysreg", "syscon"; - reg = <0x10050000 0x5000>; - }; - watchdog@101D0000 { compatible = "samsung,exynos5250-wdt"; reg = <0x101D0000 0x100>; @@ -328,62 +319,7 @@ status = "disabled"; }; - i2c_0: i2c@12C60000 { - compatible = "samsung,s3c2440-i2c"; - reg = <0x12C60000 0x100>; - interrupts = <0 56 0>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clock CLK_I2C0>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_bus>; - samsung,sysreg-phandle = <&sysreg_system_controller>; - status = "disabled"; - }; - - i2c_1: i2c@12C70000 { - compatible = "samsung,s3c2440-i2c"; - reg = <0x12C70000 0x100>; - interrupts = <0 57 0>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clock CLK_I2C1>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_bus>; - samsung,sysreg-phandle = <&sysreg_system_controller>; - status = "disabled"; - }; - - i2c_2: i2c@12C80000 { - compatible = "samsung,s3c2440-i2c"; - reg = <0x12C80000 0x100>; - interrupts = <0 58 0>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clock CLK_I2C2>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_bus>; - samsung,sysreg-phandle = <&sysreg_system_controller>; - status = "disabled"; - }; - - i2c_3: i2c@12C90000 { - compatible = "samsung,s3c2440-i2c"; - reg = <0x12C90000 0x100>; - interrupts = <0 59 0>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clock CLK_I2C3>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_bus>; - samsung,sysreg-phandle = <&sysreg_system_controller>; - status = "disabled"; - }; - + /* i2c_0-3 are defined in exynos5.dtsi */ i2c_4: i2c@12CA0000 { compatible = "samsung,s3c2440-i2c"; reg = <0x12CA0000 0x100>; @@ -662,15 +598,6 @@ samsung,pmureg-phandle = <&pmu_system_controller>; }; - pwm: pwm@12dd0000 { - compatible = "samsung,exynos4210-pwm"; - reg = <0x12dd0000 0x100>; - samsung,pwm-outputs = <0>, <1>, <2>, <3>; - #pwm-cells = <3>; - clocks = <&clock CLK_PWM>; - clock-names = "timers"; - }; - amba { #address-cells = <1>; #size-cells = <1>; @@ -1070,6 +997,39 @@ iommus = <&sysmmu_fimd1>; }; +&i2c_0 { + clocks = <&clock CLK_I2C0>; + clock-names = "i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_bus>; +}; + +&i2c_1 { + clocks = <&clock CLK_I2C1>; + clock-names = "i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_bus>; +}; + +&i2c_2 { + clocks = <&clock CLK_I2C2>; + clock-names = "i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_bus>; +}; + +&i2c_3 { + clocks = <&clock CLK_I2C3>; + clock-names = "i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_bus>; +}; + +&pwm { + clocks = <&clock CLK_PWM>; + clock-names = "timers"; +}; + &rtc { clocks = <&clock CLK_RTC>; clock-names = "rtc"; diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index 9d99e43..5bf7882 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -30,10 +30,6 @@ pinctrl2 = &pinctrl_2; pinctrl3 = &pinctrl_3; pinctrl4 = &pinctrl_4; - i2c0 = &i2c_0; - i2c1 = &i2c_1; - i2c2 = &i2c_2; - i2c3 = &i2c_3; i2c4 = &hsi2c_4; i2c5 = &hsi2c_5; i2c6 = &hsi2c_6; @@ -578,15 +574,6 @@ status = "disabled"; }; - pwm: pwm@12dd0000 { - compatible = "samsung,exynos4210-pwm"; - reg = <0x12dd0000 0x100>; - samsung,pwm-outputs = <0>, <1>, <2>, <3>; - #pwm-cells = <3>; - clocks = <&clock CLK_PWM>; - clock-names = "timers"; - }; - dp_phy: dp-video-phy { compatible = "samsung,exynos5420-dp-video-phy"; samsung,pmu-syscon = <&pmu_system_controller>; @@ -624,62 +611,7 @@ status = "disabled"; }; - i2c_0: i2c@12C60000 { - compatible = "samsung,s3c2440-i2c"; - reg = <0x12C60000 0x100>; - interrupts = <0 56 0>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clock CLK_I2C0>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_bus>; - samsung,sysreg-phandle = <&sysreg_system_controller>; - status = "disabled"; - }; - - i2c_1: i2c@12C70000 { - compatible = "samsung,s3c2440-i2c"; - reg = <0x12C70000 0x100>; - interrupts = <0 57 0>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clock CLK_I2C1>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_bus>; - samsung,sysreg-phandle = <&sysreg_system_controller>; - status = "disabled"; - }; - - i2c_2: i2c@12C80000 { - compatible = "samsung,s3c2440-i2c"; - reg = <0x12C80000 0x100>; - interrupts = <0 58 0>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clock CLK_I2C2>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_bus>; - samsung,sysreg-phandle = <&sysreg_system_controller>; - status = "disabled"; - }; - - i2c_3: i2c@12C90000 { - compatible = "samsung,s3c2440-i2c"; - reg = <0x12C90000 0x100>; - interrupts = <0 59 0>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clock CLK_I2C3>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_bus>; - samsung,sysreg-phandle = <&sysreg_system_controller>; - status = "disabled"; - }; - + /* i2c_0-3 are defined in exynos5.dtsi */ hsi2c_4: i2c@12CA0000 { compatible = "samsung,exynos5250-hsi2c"; reg = <0x12CA0000 0x1000>; @@ -859,11 +791,6 @@ interrupt-parent = <&gic>; }; - sysreg_system_controller: syscon@10050000 { - compatible = "samsung,exynos5-sysreg", "syscon"; - reg = <0x10050000 0x5000>; - }; - tmu_cpu0: tmu@10060000 { compatible = "samsung,exynos5420-tmu"; reg = <0x10060000 0x100>; @@ -1614,6 +1541,39 @@ iommu-names = "m0", "m1"; }; +&i2c_0 { + clocks = <&clock CLK_I2C0>; + clock-names = "i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_bus>; +}; + +&i2c_1 { + clocks = <&clock CLK_I2C1>; + clock-names = "i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_bus>; +}; + +&i2c_2 { + clocks = <&clock CLK_I2C2>; + clock-names = "i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_bus>; +}; + +&i2c_3 { + clocks = <&clock CLK_I2C3>; + clock-names = "i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_bus>; +}; + +&pwm { + clocks = <&clock CLK_PWM>; + clock-names = "timers"; +}; + &rtc { clocks = <&clock CLK_RTC>; clock-names = "rtc"; -- cgit v0.10.2 From 61e471f88a2d412373bc33bb06c2f20fa6119efa Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 3 May 2016 14:52:38 +0200 Subject: ARM: dts: exynos: Prepare for inclusion of exynos5.dtsi in exynos5410.dtsi Add 'sromc' label to SROM memory controller in common exynos5.dtsi so it can be referenced by inheriting DTSI. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Javier Martinez Canillas Tested-by: Javier Martinez Canillas diff --git a/arch/arm/boot/dts/exynos5.dtsi b/arch/arm/boot/dts/exynos5.dtsi index c5d198c..30a0b63 100644 --- a/arch/arm/boot/dts/exynos5.dtsi +++ b/arch/arm/boot/dts/exynos5.dtsi @@ -35,7 +35,7 @@ reg = <0x10000000 0x100>; }; - memory-controller@12250000 { + sromc: memory-controller@12250000 { compatible = "samsung,exynos4210-srom"; reg = <0x12250000 0x14>; }; -- cgit v0.10.2 From e3daf8e54ce3ce8ad4a6b9d6322db87f700082a0 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 3 May 2016 18:49:00 +0200 Subject: ARM: dts: exynos: Use phandle to get parent node in exynos5250-snow The i2c-arbitrator node in exynos5250-snow-common used absolute path to reference other node (the i2c parent). Use phandle instead, because the depth of the other node may be changed (like moving it under 'soc' node). Signed-off-by: Krzysztof Kozlowski Reviewed-by: Javier Martinez Canillas diff --git a/arch/arm/boot/dts/exynos5250-snow-common.dtsi b/arch/arm/boot/dts/exynos5250-snow-common.dtsi index ddfe1f5..419d59d 100644 --- a/arch/arm/boot/dts/exynos5250-snow-common.dtsi +++ b/arch/arm/boot/dts/exynos5250-snow-common.dtsi @@ -61,7 +61,7 @@ #address-cells = <1>; #size-cells = <0>; - i2c-parent = <&{/i2c@12CA0000}>; + i2c-parent = <&i2c_4>; our-claim-gpio = <&gpf0 3 GPIO_ACTIVE_LOW>; their-claim-gpios = <&gpe0 4 GPIO_ACTIVE_LOW>; -- cgit v0.10.2 From 5d99cc59a3c63489c1b3fbab34a69c01dad4788e Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 3 May 2016 18:53:04 +0200 Subject: ARM: dts: exynos: Move Exynos5250 and Exynos5420 nodes under soc The conventions is to put SoC devices under 'soc' node. In fact other our DTSes (like exynos3250.dtsi or exynos5410.dtsi) already follow it. Adjust exynos5250 and exynos5420 DTSI to follow this convention. This is also necessary for the upcoming change in exynos5410.dtsi to inherit from common exynos5.dtsi. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Javier Martinez Canillas Tested-by: Javier Martinez Canillas diff --git a/arch/arm/boot/dts/exynos5.dtsi b/arch/arm/boot/dts/exynos5.dtsi index 30a0b63..cab9178 100644 --- a/arch/arm/boot/dts/exynos5.dtsi +++ b/arch/arm/boot/dts/exynos5.dtsi @@ -30,143 +30,150 @@ serial3 = &serial_3; }; - chipid@10000000 { - compatible = "samsung,exynos4210-chipid"; - reg = <0x10000000 0x100>; - }; - - sromc: memory-controller@12250000 { - compatible = "samsung,exynos4210-srom"; - reg = <0x12250000 0x14>; - }; - - combiner: interrupt-controller@10440000 { - compatible = "samsung,exynos4210-combiner"; - #interrupt-cells = <2>; - interrupt-controller; - samsung,combiner-nr = <32>; - reg = <0x10440000 0x1000>; - interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>, - <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>, - <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>, - <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>, - <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>, - <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>, - <0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>, - <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>; - }; - - gic: interrupt-controller@10481000 { - compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x10481000 0x1000>, - <0x10482000 0x1000>, - <0x10484000 0x2000>, - <0x10486000 0x2000>; - interrupts = <1 9 0xf04>; - }; - - sysreg_system_controller: syscon@10050000 { - compatible = "samsung,exynos5-sysreg", "syscon"; - reg = <0x10050000 0x5000>; - }; - - serial_0: serial@12C00000 { - compatible = "samsung,exynos4210-uart"; - reg = <0x12C00000 0x100>; - interrupts = <0 51 0>; - }; - - serial_1: serial@12C10000 { - compatible = "samsung,exynos4210-uart"; - reg = <0x12C10000 0x100>; - interrupts = <0 52 0>; - }; - - serial_2: serial@12C20000 { - compatible = "samsung,exynos4210-uart"; - reg = <0x12C20000 0x100>; - interrupts = <0 53 0>; - }; - - serial_3: serial@12C30000 { - compatible = "samsung,exynos4210-uart"; - reg = <0x12C30000 0x100>; - interrupts = <0 54 0>; - }; - - i2c_0: i2c@12C60000 { - compatible = "samsung,s3c2440-i2c"; - reg = <0x12C60000 0x100>; - interrupts = <0 56 0>; - #address-cells = <1>; - #size-cells = <0>; - samsung,sysreg-phandle = <&sysreg_system_controller>; - status = "disabled"; - }; - - i2c_1: i2c@12C70000 { - compatible = "samsung,s3c2440-i2c"; - reg = <0x12C70000 0x100>; - interrupts = <0 57 0>; - #address-cells = <1>; - #size-cells = <0>; - samsung,sysreg-phandle = <&sysreg_system_controller>; - status = "disabled"; - }; - - i2c_2: i2c@12C80000 { - compatible = "samsung,s3c2440-i2c"; - reg = <0x12C80000 0x100>; - interrupts = <0 58 0>; - #address-cells = <1>; - #size-cells = <0>; - samsung,sysreg-phandle = <&sysreg_system_controller>; - status = "disabled"; - }; - - i2c_3: i2c@12C90000 { - compatible = "samsung,s3c2440-i2c"; - reg = <0x12C90000 0x100>; - interrupts = <0 59 0>; - #address-cells = <1>; - #size-cells = <0>; - samsung,sysreg-phandle = <&sysreg_system_controller>; - status = "disabled"; - }; - - pwm: pwm@12DD0000 { - compatible = "samsung,exynos4210-pwm"; - reg = <0x12DD0000 0x100>; - samsung,pwm-outputs = <0>, <1>, <2>, <3>; - #pwm-cells = <3>; - }; - - rtc: rtc@101E0000 { - compatible = "samsung,s3c6410-rtc"; - reg = <0x101E0000 0x100>; - interrupts = <0 43 0>, <0 44 0>; - status = "disabled"; - }; - - fimd: fimd@14400000 { - compatible = "samsung,exynos5250-fimd"; - interrupt-parent = <&combiner>; - reg = <0x14400000 0x40000>; - interrupt-names = "fifo", "vsync", "lcd_sys"; - interrupts = <18 4>, <18 5>, <18 6>; - samsung,sysreg = <&sysreg_system_controller>; - status = "disabled"; - }; - - dp: dp-controller@145B0000 { - compatible = "samsung,exynos5-dp"; - reg = <0x145B0000 0x1000>; - interrupts = <10 3>; - interrupt-parent = <&combiner>; + soc: soc { + compatible = "simple-bus"; #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; + #size-cells = <1>; + ranges; + + chipid@10000000 { + compatible = "samsung,exynos4210-chipid"; + reg = <0x10000000 0x100>; + }; + + sromc: memory-controller@12250000 { + compatible = "samsung,exynos4210-srom"; + reg = <0x12250000 0x14>; + }; + + combiner: interrupt-controller@10440000 { + compatible = "samsung,exynos4210-combiner"; + #interrupt-cells = <2>; + interrupt-controller; + samsung,combiner-nr = <32>; + reg = <0x10440000 0x1000>; + interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>, + <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>, + <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>, + <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>, + <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>, + <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>, + <0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>, + <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>; + }; + + gic: interrupt-controller@10481000 { + compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x10481000 0x1000>, + <0x10482000 0x1000>, + <0x10484000 0x2000>, + <0x10486000 0x2000>; + interrupts = <1 9 0xf04>; + }; + + sysreg_system_controller: syscon@10050000 { + compatible = "samsung,exynos5-sysreg", "syscon"; + reg = <0x10050000 0x5000>; + }; + + serial_0: serial@12C00000 { + compatible = "samsung,exynos4210-uart"; + reg = <0x12C00000 0x100>; + interrupts = <0 51 0>; + }; + + serial_1: serial@12C10000 { + compatible = "samsung,exynos4210-uart"; + reg = <0x12C10000 0x100>; + interrupts = <0 52 0>; + }; + + serial_2: serial@12C20000 { + compatible = "samsung,exynos4210-uart"; + reg = <0x12C20000 0x100>; + interrupts = <0 53 0>; + }; + + serial_3: serial@12C30000 { + compatible = "samsung,exynos4210-uart"; + reg = <0x12C30000 0x100>; + interrupts = <0 54 0>; + }; + + i2c_0: i2c@12C60000 { + compatible = "samsung,s3c2440-i2c"; + reg = <0x12C60000 0x100>; + interrupts = <0 56 0>; + #address-cells = <1>; + #size-cells = <0>; + samsung,sysreg-phandle = <&sysreg_system_controller>; + status = "disabled"; + }; + + i2c_1: i2c@12C70000 { + compatible = "samsung,s3c2440-i2c"; + reg = <0x12C70000 0x100>; + interrupts = <0 57 0>; + #address-cells = <1>; + #size-cells = <0>; + samsung,sysreg-phandle = <&sysreg_system_controller>; + status = "disabled"; + }; + + i2c_2: i2c@12C80000 { + compatible = "samsung,s3c2440-i2c"; + reg = <0x12C80000 0x100>; + interrupts = <0 58 0>; + #address-cells = <1>; + #size-cells = <0>; + samsung,sysreg-phandle = <&sysreg_system_controller>; + status = "disabled"; + }; + + i2c_3: i2c@12C90000 { + compatible = "samsung,s3c2440-i2c"; + reg = <0x12C90000 0x100>; + interrupts = <0 59 0>; + #address-cells = <1>; + #size-cells = <0>; + samsung,sysreg-phandle = <&sysreg_system_controller>; + status = "disabled"; + }; + + pwm: pwm@12DD0000 { + compatible = "samsung,exynos4210-pwm"; + reg = <0x12DD0000 0x100>; + samsung,pwm-outputs = <0>, <1>, <2>, <3>; + #pwm-cells = <3>; + }; + + rtc: rtc@101E0000 { + compatible = "samsung,s3c6410-rtc"; + reg = <0x101E0000 0x100>; + interrupts = <0 43 0>, <0 44 0>; + status = "disabled"; + }; + + fimd: fimd@14400000 { + compatible = "samsung,exynos5250-fimd"; + interrupt-parent = <&combiner>; + reg = <0x14400000 0x40000>; + interrupt-names = "fifo", "vsync", "lcd_sys"; + interrupts = <18 4>, <18 5>, <18 6>; + samsung,sysreg = <&sysreg_system_controller>; + status = "disabled"; + }; + + dp: dp-controller@145B0000 { + compatible = "samsung,exynos5-dp"; + reg = <0x145B0000 0x1000>; + interrupts = <10 3>; + interrupt-parent = <&combiner>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; }; }; diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi index ae4970d..f7357d9 100644 --- a/arch/arm/boot/dts/exynos5250.dtsi +++ b/arch/arm/boot/dts/exynos5250.dtsi @@ -92,893 +92,896 @@ }; }; - sysram@02020000 { - compatible = "mmio-sram"; - reg = <0x02020000 0x30000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x02020000 0x30000>; - - smp-sysram@0 { - compatible = "samsung,exynos4210-sysram"; - reg = <0x0 0x1000>; + soc: soc { + sysram@02020000 { + compatible = "mmio-sram"; + reg = <0x02020000 0x30000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x02020000 0x30000>; + + smp-sysram@0 { + compatible = "samsung,exynos4210-sysram"; + reg = <0x0 0x1000>; + }; + + smp-sysram@2f000 { + compatible = "samsung,exynos4210-sysram-ns"; + reg = <0x2f000 0x1000>; + }; }; - smp-sysram@2f000 { - compatible = "samsung,exynos4210-sysram-ns"; - reg = <0x2f000 0x1000>; + pd_gsc: gsc-power-domain@10044000 { + compatible = "samsung,exynos4210-pd"; + reg = <0x10044000 0x20>; + #power-domain-cells = <0>; }; - }; - - pd_gsc: gsc-power-domain@10044000 { - compatible = "samsung,exynos4210-pd"; - reg = <0x10044000 0x20>; - #power-domain-cells = <0>; - }; - pd_mfc: mfc-power-domain@10044040 { - compatible = "samsung,exynos4210-pd"; - reg = <0x10044040 0x20>; - #power-domain-cells = <0>; - }; + pd_mfc: mfc-power-domain@10044040 { + compatible = "samsung,exynos4210-pd"; + reg = <0x10044040 0x20>; + #power-domain-cells = <0>; + }; - pd_disp1: disp1-power-domain@100440A0 { - compatible = "samsung,exynos4210-pd"; - reg = <0x100440A0 0x20>; - #power-domain-cells = <0>; - clocks = <&clock CLK_FIN_PLL>, - <&clock CLK_MOUT_ACLK200_DISP1_SUB>, - <&clock CLK_MOUT_ACLK300_DISP1_SUB>; - clock-names = "oscclk", "clk0", "clk1"; - }; + pd_disp1: disp1-power-domain@100440A0 { + compatible = "samsung,exynos4210-pd"; + reg = <0x100440A0 0x20>; + #power-domain-cells = <0>; + clocks = <&clock CLK_FIN_PLL>, + <&clock CLK_MOUT_ACLK200_DISP1_SUB>, + <&clock CLK_MOUT_ACLK300_DISP1_SUB>; + clock-names = "oscclk", "clk0", "clk1"; + }; - clock: clock-controller@10010000 { - compatible = "samsung,exynos5250-clock"; - reg = <0x10010000 0x30000>; - #clock-cells = <1>; - }; + clock: clock-controller@10010000 { + compatible = "samsung,exynos5250-clock"; + reg = <0x10010000 0x30000>; + #clock-cells = <1>; + }; - clock_audss: audss-clock-controller@3810000 { - compatible = "samsung,exynos5250-audss-clock"; - reg = <0x03810000 0x0C>; - #clock-cells = <1>; - clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>, - <&clock CLK_SCLK_AUDIO0>, <&clock CLK_DIV_PCM0>; - clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in"; - }; + clock_audss: audss-clock-controller@3810000 { + compatible = "samsung,exynos5250-audss-clock"; + reg = <0x03810000 0x0C>; + #clock-cells = <1>; + clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>, + <&clock CLK_SCLK_AUDIO0>, <&clock CLK_DIV_PCM0>; + clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in"; + }; - timer { - compatible = "arm,armv7-timer"; - interrupts = <1 13 0xf08>, - <1 14 0xf08>, - <1 11 0xf08>, - <1 10 0xf08>; - /* Unfortunately we need this since some versions of U-Boot - * on Exynos don't set the CNTFRQ register, so we need the - * value from DT. - */ - clock-frequency = <24000000>; - }; + timer { + compatible = "arm,armv7-timer"; + interrupts = <1 13 0xf08>, + <1 14 0xf08>, + <1 11 0xf08>, + <1 10 0xf08>; + /* + * Unfortunately we need this since some versions + * of U-Boot on Exynos don't set the CNTFRQ register, + * so we need the value from DT. + */ + clock-frequency = <24000000>; + }; - mct@101C0000 { - compatible = "samsung,exynos4210-mct"; - reg = <0x101C0000 0x800>; - interrupt-controller; - #interrupt-cells = <2>; - interrupt-parent = <&mct_map>; - interrupts = <0 0>, <1 0>, <2 0>, <3 0>, - <4 0>, <5 0>; - clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>; - clock-names = "fin_pll", "mct"; - - mct_map: mct-map { + mct@101C0000 { + compatible = "samsung,exynos4210-mct"; + reg = <0x101C0000 0x800>; + interrupt-controller; #interrupt-cells = <2>; - #address-cells = <0>; - #size-cells = <0>; - interrupt-map = <0x0 0 &combiner 23 3>, - <0x1 0 &combiner 23 4>, - <0x2 0 &combiner 25 2>, - <0x3 0 &combiner 25 3>, - <0x4 0 &gic 0 120 0>, - <0x5 0 &gic 0 121 0>; + interrupt-parent = <&mct_map>; + interrupts = <0 0>, <1 0>, <2 0>, <3 0>, + <4 0>, <5 0>; + clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>; + clock-names = "fin_pll", "mct"; + + mct_map: mct-map { + #interrupt-cells = <2>; + #address-cells = <0>; + #size-cells = <0>; + interrupt-map = <0x0 0 &combiner 23 3>, + <0x1 0 &combiner 23 4>, + <0x2 0 &combiner 25 2>, + <0x3 0 &combiner 25 3>, + <0x4 0 &gic 0 120 0>, + <0x5 0 &gic 0 121 0>; + }; }; - }; - pmu { - compatible = "arm,cortex-a15-pmu"; - interrupt-parent = <&combiner>; - interrupts = <1 2>, <22 4>; - }; + pmu { + compatible = "arm,cortex-a15-pmu"; + interrupt-parent = <&combiner>; + interrupts = <1 2>, <22 4>; + }; - pinctrl_0: pinctrl@11400000 { - compatible = "samsung,exynos5250-pinctrl"; - reg = <0x11400000 0x1000>; - interrupts = <0 46 0>; + pinctrl_0: pinctrl@11400000 { + compatible = "samsung,exynos5250-pinctrl"; + reg = <0x11400000 0x1000>; + interrupts = <0 46 0>; - wakup_eint: wakeup-interrupt-controller { - compatible = "samsung,exynos4210-wakeup-eint"; - interrupt-parent = <&gic>; - interrupts = <0 32 0>; + wakup_eint: wakeup-interrupt-controller { + compatible = "samsung,exynos4210-wakeup-eint"; + interrupt-parent = <&gic>; + interrupts = <0 32 0>; + }; }; - }; - pinctrl_1: pinctrl@13400000 { - compatible = "samsung,exynos5250-pinctrl"; - reg = <0x13400000 0x1000>; - interrupts = <0 45 0>; - }; + pinctrl_1: pinctrl@13400000 { + compatible = "samsung,exynos5250-pinctrl"; + reg = <0x13400000 0x1000>; + interrupts = <0 45 0>; + }; - pinctrl_2: pinctrl@10d10000 { - compatible = "samsung,exynos5250-pinctrl"; - reg = <0x10d10000 0x1000>; - interrupts = <0 50 0>; - }; + pinctrl_2: pinctrl@10d10000 { + compatible = "samsung,exynos5250-pinctrl"; + reg = <0x10d10000 0x1000>; + interrupts = <0 50 0>; + }; - pinctrl_3: pinctrl@03860000 { - compatible = "samsung,exynos5250-pinctrl"; - reg = <0x03860000 0x1000>; - interrupts = <0 47 0>; - }; + pinctrl_3: pinctrl@03860000 { + compatible = "samsung,exynos5250-pinctrl"; + reg = <0x03860000 0x1000>; + interrupts = <0 47 0>; + }; - pmu_system_controller: system-controller@10040000 { - compatible = "samsung,exynos5250-pmu", "syscon"; - reg = <0x10040000 0x5000>; - clock-names = "clkout16"; - clocks = <&clock CLK_FIN_PLL>; - #clock-cells = <1>; - interrupt-controller; - #interrupt-cells = <3>; - interrupt-parent = <&gic>; - }; + pmu_system_controller: system-controller@10040000 { + compatible = "samsung,exynos5250-pmu", "syscon"; + reg = <0x10040000 0x5000>; + clock-names = "clkout16"; + clocks = <&clock CLK_FIN_PLL>; + #clock-cells = <1>; + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + }; - watchdog@101D0000 { - compatible = "samsung,exynos5250-wdt"; - reg = <0x101D0000 0x100>; - interrupts = <0 42 0>; - clocks = <&clock CLK_WDT>; - clock-names = "watchdog"; - samsung,syscon-phandle = <&pmu_system_controller>; - }; + watchdog@101D0000 { + compatible = "samsung,exynos5250-wdt"; + reg = <0x101D0000 0x100>; + interrupts = <0 42 0>; + clocks = <&clock CLK_WDT>; + clock-names = "watchdog"; + samsung,syscon-phandle = <&pmu_system_controller>; + }; - g2d@10850000 { - compatible = "samsung,exynos5250-g2d"; - reg = <0x10850000 0x1000>; - interrupts = <0 91 0>; - clocks = <&clock CLK_G2D>; - clock-names = "fimg2d"; - iommus = <&sysmmu_g2d>; - }; + g2d@10850000 { + compatible = "samsung,exynos5250-g2d"; + reg = <0x10850000 0x1000>; + interrupts = <0 91 0>; + clocks = <&clock CLK_G2D>; + clock-names = "fimg2d"; + iommus = <&sysmmu_g2d>; + }; - mfc: codec@11000000 { - compatible = "samsung,mfc-v6"; - reg = <0x11000000 0x10000>; - interrupts = <0 96 0>; - power-domains = <&pd_mfc>; - clocks = <&clock CLK_MFC>; - clock-names = "mfc"; - iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>; - iommu-names = "left", "right"; - }; + mfc: codec@11000000 { + compatible = "samsung,mfc-v6"; + reg = <0x11000000 0x10000>; + interrupts = <0 96 0>; + power-domains = <&pd_mfc>; + clocks = <&clock CLK_MFC>; + clock-names = "mfc"; + iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>; + iommu-names = "left", "right"; + }; - rotator: rotator@11C00000 { - compatible = "samsung,exynos5250-rotator"; - reg = <0x11C00000 0x64>; - interrupts = <0 84 0>; - clocks = <&clock CLK_ROTATOR>; - clock-names = "rotator"; - iommus = <&sysmmu_rotator>; - }; + rotator: rotator@11C00000 { + compatible = "samsung,exynos5250-rotator"; + reg = <0x11C00000 0x64>; + interrupts = <0 84 0>; + clocks = <&clock CLK_ROTATOR>; + clock-names = "rotator"; + iommus = <&sysmmu_rotator>; + }; - tmu: tmu@10060000 { - compatible = "samsung,exynos5250-tmu"; - reg = <0x10060000 0x100>; - interrupts = <0 65 0>; - clocks = <&clock CLK_TMU>; - clock-names = "tmu_apbif"; - #include "exynos4412-tmu-sensor-conf.dtsi" - }; + tmu: tmu@10060000 { + compatible = "samsung,exynos5250-tmu"; + reg = <0x10060000 0x100>; + interrupts = <0 65 0>; + clocks = <&clock CLK_TMU>; + clock-names = "tmu_apbif"; + #include "exynos4412-tmu-sensor-conf.dtsi" + }; - thermal-zones { - cpu_thermal: cpu-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tmu 0>; + sata: sata@122F0000 { + compatible = "snps,dwc-ahci"; + samsung,sata-freq = <66>; + reg = <0x122F0000 0x1ff>; + interrupts = <0 115 0>; + clocks = <&clock CLK_SATA>, <&clock CLK_SCLK_SATA>; + clock-names = "sata", "sclk_sata"; + phys = <&sata_phy>; + phy-names = "sata-phy"; + status = "disabled"; + }; - cooling-maps { - map0 { - /* Corresponds to 800MHz at freq_table */ - cooling-device = <&cpu0 9 9>; - }; - map1 { - /* Corresponds to 200MHz at freq_table */ - cooling-device = <&cpu0 15 15>; - }; - }; + sata_phy: sata-phy@12170000 { + compatible = "samsung,exynos5250-sata-phy"; + reg = <0x12170000 0x1ff>; + clocks = <&clock CLK_SATA_PHYCTRL>; + clock-names = "sata_phyctrl"; + #phy-cells = <0>; + samsung,syscon-phandle = <&pmu_system_controller>; + status = "disabled"; }; - }; - sata: sata@122F0000 { - compatible = "snps,dwc-ahci"; - samsung,sata-freq = <66>; - reg = <0x122F0000 0x1ff>; - interrupts = <0 115 0>; - clocks = <&clock CLK_SATA>, <&clock CLK_SCLK_SATA>; - clock-names = "sata", "sclk_sata"; - phys = <&sata_phy>; - phy-names = "sata-phy"; - status = "disabled"; - }; + /* i2c_0-3 are defined in exynos5.dtsi */ + i2c_4: i2c@12CA0000 { + compatible = "samsung,s3c2440-i2c"; + reg = <0x12CA0000 0x100>; + interrupts = <0 60 0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clock CLK_I2C4>; + clock-names = "i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_bus>; + status = "disabled"; + }; - sata_phy: sata-phy@12170000 { - compatible = "samsung,exynos5250-sata-phy"; - reg = <0x12170000 0x1ff>; - clocks = <&clock CLK_SATA_PHYCTRL>; - clock-names = "sata_phyctrl"; - #phy-cells = <0>; - samsung,syscon-phandle = <&pmu_system_controller>; - status = "disabled"; - }; + i2c_5: i2c@12CB0000 { + compatible = "samsung,s3c2440-i2c"; + reg = <0x12CB0000 0x100>; + interrupts = <0 61 0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clock CLK_I2C5>; + clock-names = "i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c5_bus>; + status = "disabled"; + }; - /* i2c_0-3 are defined in exynos5.dtsi */ - i2c_4: i2c@12CA0000 { - compatible = "samsung,s3c2440-i2c"; - reg = <0x12CA0000 0x100>; - interrupts = <0 60 0>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clock CLK_I2C4>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c4_bus>; - status = "disabled"; - }; + i2c_6: i2c@12CC0000 { + compatible = "samsung,s3c2440-i2c"; + reg = <0x12CC0000 0x100>; + interrupts = <0 62 0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clock CLK_I2C6>; + clock-names = "i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c6_bus>; + status = "disabled"; + }; - i2c_5: i2c@12CB0000 { - compatible = "samsung,s3c2440-i2c"; - reg = <0x12CB0000 0x100>; - interrupts = <0 61 0>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clock CLK_I2C5>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c5_bus>; - status = "disabled"; - }; + i2c_7: i2c@12CD0000 { + compatible = "samsung,s3c2440-i2c"; + reg = <0x12CD0000 0x100>; + interrupts = <0 63 0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clock CLK_I2C7>; + clock-names = "i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c7_bus>; + status = "disabled"; + }; - i2c_6: i2c@12CC0000 { - compatible = "samsung,s3c2440-i2c"; - reg = <0x12CC0000 0x100>; - interrupts = <0 62 0>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clock CLK_I2C6>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c6_bus>; - status = "disabled"; - }; + i2c_8: i2c@12CE0000 { + compatible = "samsung,s3c2440-hdmiphy-i2c"; + reg = <0x12CE0000 0x1000>; + interrupts = <0 64 0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clock CLK_I2C_HDMI>; + clock-names = "i2c"; + status = "disabled"; + }; - i2c_7: i2c@12CD0000 { - compatible = "samsung,s3c2440-i2c"; - reg = <0x12CD0000 0x100>; - interrupts = <0 63 0>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clock CLK_I2C7>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c7_bus>; - status = "disabled"; - }; + i2c_9: i2c@121D0000 { + compatible = "samsung,exynos5-sata-phy-i2c"; + reg = <0x121D0000 0x100>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clock CLK_SATA_PHYI2C>; + clock-names = "i2c"; + status = "disabled"; + }; - i2c_8: i2c@12CE0000 { - compatible = "samsung,s3c2440-hdmiphy-i2c"; - reg = <0x12CE0000 0x1000>; - interrupts = <0 64 0>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clock CLK_I2C_HDMI>; - clock-names = "i2c"; - status = "disabled"; - }; + spi_0: spi@12d20000 { + compatible = "samsung,exynos4210-spi"; + status = "disabled"; + reg = <0x12d20000 0x100>; + interrupts = <0 66 0>; + dmas = <&pdma0 5 + &pdma0 4>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>; + clock-names = "spi", "spi_busclk0"; + pinctrl-names = "default"; + pinctrl-0 = <&spi0_bus>; + }; - i2c_9: i2c@121D0000 { - compatible = "samsung,exynos5-sata-phy-i2c"; - reg = <0x121D0000 0x100>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clock CLK_SATA_PHYI2C>; - clock-names = "i2c"; - status = "disabled"; - }; + spi_1: spi@12d30000 { + compatible = "samsung,exynos4210-spi"; + status = "disabled"; + reg = <0x12d30000 0x100>; + interrupts = <0 67 0>; + dmas = <&pdma1 5 + &pdma1 4>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>; + clock-names = "spi", "spi_busclk0"; + pinctrl-names = "default"; + pinctrl-0 = <&spi1_bus>; + }; - spi_0: spi@12d20000 { - compatible = "samsung,exynos4210-spi"; - status = "disabled"; - reg = <0x12d20000 0x100>; - interrupts = <0 66 0>; - dmas = <&pdma0 5 - &pdma0 4>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>; - clock-names = "spi", "spi_busclk0"; - pinctrl-names = "default"; - pinctrl-0 = <&spi0_bus>; - }; + spi_2: spi@12d40000 { + compatible = "samsung,exynos4210-spi"; + status = "disabled"; + reg = <0x12d40000 0x100>; + interrupts = <0 68 0>; + dmas = <&pdma0 7 + &pdma0 6>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>; + clock-names = "spi", "spi_busclk0"; + pinctrl-names = "default"; + pinctrl-0 = <&spi2_bus>; + }; - spi_1: spi@12d30000 { - compatible = "samsung,exynos4210-spi"; - status = "disabled"; - reg = <0x12d30000 0x100>; - interrupts = <0 67 0>; - dmas = <&pdma1 5 - &pdma1 4>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>; - clock-names = "spi", "spi_busclk0"; - pinctrl-names = "default"; - pinctrl-0 = <&spi1_bus>; - }; + mmc_0: mmc@12200000 { + compatible = "samsung,exynos5250-dw-mshc"; + interrupts = <0 75 0>; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x12200000 0x1000>; + clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>; + clock-names = "biu", "ciu"; + fifo-depth = <0x80>; + status = "disabled"; + }; - spi_2: spi@12d40000 { - compatible = "samsung,exynos4210-spi"; - status = "disabled"; - reg = <0x12d40000 0x100>; - interrupts = <0 68 0>; - dmas = <&pdma0 7 - &pdma0 6>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>; - clock-names = "spi", "spi_busclk0"; - pinctrl-names = "default"; - pinctrl-0 = <&spi2_bus>; - }; + mmc_1: mmc@12210000 { + compatible = "samsung,exynos5250-dw-mshc"; + interrupts = <0 76 0>; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x12210000 0x1000>; + clocks = <&clock CLK_SDMMC1>, <&clock CLK_SCLK_MMC1>; + clock-names = "biu", "ciu"; + fifo-depth = <0x80>; + status = "disabled"; + }; - mmc_0: mmc@12200000 { - compatible = "samsung,exynos5250-dw-mshc"; - interrupts = <0 75 0>; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x12200000 0x1000>; - clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>; - clock-names = "biu", "ciu"; - fifo-depth = <0x80>; - status = "disabled"; - }; + mmc_2: mmc@12220000 { + compatible = "samsung,exynos5250-dw-mshc"; + interrupts = <0 77 0>; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x12220000 0x1000>; + clocks = <&clock CLK_SDMMC2>, <&clock CLK_SCLK_MMC2>; + clock-names = "biu", "ciu"; + fifo-depth = <0x80>; + status = "disabled"; + }; - mmc_1: mmc@12210000 { - compatible = "samsung,exynos5250-dw-mshc"; - interrupts = <0 76 0>; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x12210000 0x1000>; - clocks = <&clock CLK_SDMMC1>, <&clock CLK_SCLK_MMC1>; - clock-names = "biu", "ciu"; - fifo-depth = <0x80>; - status = "disabled"; - }; + mmc_3: mmc@12230000 { + compatible = "samsung,exynos5250-dw-mshc"; + reg = <0x12230000 0x1000>; + interrupts = <0 78 0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>; + clock-names = "biu", "ciu"; + fifo-depth = <0x80>; + status = "disabled"; + }; - mmc_2: mmc@12220000 { - compatible = "samsung,exynos5250-dw-mshc"; - interrupts = <0 77 0>; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x12220000 0x1000>; - clocks = <&clock CLK_SDMMC2>, <&clock CLK_SCLK_MMC2>; - clock-names = "biu", "ciu"; - fifo-depth = <0x80>; - status = "disabled"; - }; + i2s0: i2s@03830000 { + compatible = "samsung,s5pv210-i2s"; + status = "disabled"; + reg = <0x03830000 0x100>; + dmas = <&pdma0 10 + &pdma0 9 + &pdma0 8>; + dma-names = "tx", "rx", "tx-sec"; + clocks = <&clock_audss EXYNOS_I2S_BUS>, + <&clock_audss EXYNOS_I2S_BUS>, + <&clock_audss EXYNOS_SCLK_I2S>; + clock-names = "iis", "i2s_opclk0", "i2s_opclk1"; + samsung,idma-addr = <0x03000000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_bus>; + }; - mmc_3: mmc@12230000 { - compatible = "samsung,exynos5250-dw-mshc"; - reg = <0x12230000 0x1000>; - interrupts = <0 78 0>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>; - clock-names = "biu", "ciu"; - fifo-depth = <0x80>; - status = "disabled"; - }; + i2s1: i2s@12D60000 { + compatible = "samsung,s3c6410-i2s"; + status = "disabled"; + reg = <0x12D60000 0x100>; + dmas = <&pdma1 12 + &pdma1 11>; + dma-names = "tx", "rx"; + clocks = <&clock CLK_I2S1>, <&clock CLK_DIV_I2S1>; + clock-names = "iis", "i2s_opclk0"; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1_bus>; + }; - i2s0: i2s@03830000 { - compatible = "samsung,s5pv210-i2s"; - status = "disabled"; - reg = <0x03830000 0x100>; - dmas = <&pdma0 10 - &pdma0 9 - &pdma0 8>; - dma-names = "tx", "rx", "tx-sec"; - clocks = <&clock_audss EXYNOS_I2S_BUS>, - <&clock_audss EXYNOS_I2S_BUS>, - <&clock_audss EXYNOS_SCLK_I2S>; - clock-names = "iis", "i2s_opclk0", "i2s_opclk1"; - samsung,idma-addr = <0x03000000>; - pinctrl-names = "default"; - pinctrl-0 = <&i2s0_bus>; - }; + i2s2: i2s@12D70000 { + compatible = "samsung,s3c6410-i2s"; + status = "disabled"; + reg = <0x12D70000 0x100>; + dmas = <&pdma0 12 + &pdma0 11>; + dma-names = "tx", "rx"; + clocks = <&clock CLK_I2S2>, <&clock CLK_DIV_I2S2>; + clock-names = "iis", "i2s_opclk0"; + pinctrl-names = "default"; + pinctrl-0 = <&i2s2_bus>; + }; - i2s1: i2s@12D60000 { - compatible = "samsung,s3c6410-i2s"; - status = "disabled"; - reg = <0x12D60000 0x100>; - dmas = <&pdma1 12 - &pdma1 11>; - dma-names = "tx", "rx"; - clocks = <&clock CLK_I2S1>, <&clock CLK_DIV_I2S1>; - clock-names = "iis", "i2s_opclk0"; - pinctrl-names = "default"; - pinctrl-0 = <&i2s1_bus>; - }; + usb_dwc3 { + compatible = "samsung,exynos5250-dwusb3"; + clocks = <&clock CLK_USB3>; + clock-names = "usbdrd30"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + usbdrd_dwc3: dwc3@12000000 { + compatible = "synopsys,dwc3"; + reg = <0x12000000 0x10000>; + interrupts = <0 72 0>; + phys = <&usbdrd_phy 0>, <&usbdrd_phy 1>; + phy-names = "usb2-phy", "usb3-phy"; + }; + }; - i2s2: i2s@12D70000 { - compatible = "samsung,s3c6410-i2s"; - status = "disabled"; - reg = <0x12D70000 0x100>; - dmas = <&pdma0 12 - &pdma0 11>; - dma-names = "tx", "rx"; - clocks = <&clock CLK_I2S2>, <&clock CLK_DIV_I2S2>; - clock-names = "iis", "i2s_opclk0"; - pinctrl-names = "default"; - pinctrl-0 = <&i2s2_bus>; - }; + usbdrd_phy: phy@12100000 { + compatible = "samsung,exynos5250-usbdrd-phy"; + reg = <0x12100000 0x100>; + clocks = <&clock CLK_USB3>, <&clock CLK_FIN_PLL>; + clock-names = "phy", "ref"; + samsung,pmu-syscon = <&pmu_system_controller>; + #phy-cells = <1>; + }; - usb_dwc3 { - compatible = "samsung,exynos5250-dwusb3"; - clocks = <&clock CLK_USB3>; - clock-names = "usbdrd30"; - #address-cells = <1>; - #size-cells = <1>; - ranges; + ehci: usb@12110000 { + compatible = "samsung,exynos4210-ehci"; + reg = <0x12110000 0x100>; + interrupts = <0 71 0>; - usbdrd_dwc3: dwc3@12000000 { - compatible = "synopsys,dwc3"; - reg = <0x12000000 0x10000>; - interrupts = <0 72 0>; - phys = <&usbdrd_phy 0>, <&usbdrd_phy 1>; - phy-names = "usb2-phy", "usb3-phy"; + clocks = <&clock CLK_USB2>; + clock-names = "usbhost"; + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + phys = <&usb2_phy_gen 1>; + }; }; - }; - - usbdrd_phy: phy@12100000 { - compatible = "samsung,exynos5250-usbdrd-phy"; - reg = <0x12100000 0x100>; - clocks = <&clock CLK_USB3>, <&clock CLK_FIN_PLL>; - clock-names = "phy", "ref"; - samsung,pmu-syscon = <&pmu_system_controller>; - #phy-cells = <1>; - }; - ehci: usb@12110000 { - compatible = "samsung,exynos4210-ehci"; - reg = <0x12110000 0x100>; - interrupts = <0 71 0>; + ohci: usb@12120000 { + compatible = "samsung,exynos4210-ohci"; + reg = <0x12120000 0x100>; + interrupts = <0 71 0>; - clocks = <&clock CLK_USB2>; - clock-names = "usbhost"; - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - phys = <&usb2_phy_gen 1>; + clocks = <&clock CLK_USB2>; + clock-names = "usbhost"; + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + phys = <&usb2_phy_gen 1>; + }; }; - }; - ohci: usb@12120000 { - compatible = "samsung,exynos4210-ohci"; - reg = <0x12120000 0x100>; - interrupts = <0 71 0>; + usb2_phy_gen: phy@12130000 { + compatible = "samsung,exynos5250-usb2-phy"; + reg = <0x12130000 0x100>; + clocks = <&clock CLK_USB2>, <&clock CLK_FIN_PLL>; + clock-names = "phy", "ref"; + #phy-cells = <1>; + samsung,sysreg-phandle = <&sysreg_system_controller>; + samsung,pmureg-phandle = <&pmu_system_controller>; + }; - clocks = <&clock CLK_USB2>; - clock-names = "usbhost"; - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - phys = <&usb2_phy_gen 1>; + amba { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + interrupt-parent = <&gic>; + ranges; + + pdma0: pdma@121A0000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x121A0000 0x1000>; + interrupts = <0 34 0>; + clocks = <&clock CLK_PDMA0>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + #dma-channels = <8>; + #dma-requests = <32>; + }; + + pdma1: pdma@121B0000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x121B0000 0x1000>; + interrupts = <0 35 0>; + clocks = <&clock CLK_PDMA1>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + #dma-channels = <8>; + #dma-requests = <32>; + }; + + mdma0: mdma@10800000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x10800000 0x1000>; + interrupts = <0 33 0>; + clocks = <&clock CLK_MDMA0>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + #dma-channels = <8>; + #dma-requests = <1>; + }; + + mdma1: mdma@11C10000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x11C10000 0x1000>; + interrupts = <0 124 0>; + clocks = <&clock CLK_MDMA1>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + #dma-channels = <8>; + #dma-requests = <1>; + }; }; - }; - usb2_phy_gen: phy@12130000 { - compatible = "samsung,exynos5250-usb2-phy"; - reg = <0x12130000 0x100>; - clocks = <&clock CLK_USB2>, <&clock CLK_FIN_PLL>; - clock-names = "phy", "ref"; - #phy-cells = <1>; - samsung,sysreg-phandle = <&sysreg_system_controller>; - samsung,pmureg-phandle = <&pmu_system_controller>; - }; + gsc_0: gsc@13e00000 { + compatible = "samsung,exynos5-gsc"; + reg = <0x13e00000 0x1000>; + interrupts = <0 85 0>; + power-domains = <&pd_gsc>; + clocks = <&clock CLK_GSCL0>; + clock-names = "gscl"; + iommu = <&sysmmu_gsc0>; + }; - amba { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - interrupt-parent = <&gic>; - ranges; - - pdma0: pdma@121A0000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x121A0000 0x1000>; - interrupts = <0 34 0>; - clocks = <&clock CLK_PDMA0>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; - }; - - pdma1: pdma@121B0000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x121B0000 0x1000>; - interrupts = <0 35 0>; - clocks = <&clock CLK_PDMA1>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; - }; - - mdma0: mdma@10800000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x10800000 0x1000>; - interrupts = <0 33 0>; - clocks = <&clock CLK_MDMA0>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <1>; - }; - - mdma1: mdma@11C10000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x11C10000 0x1000>; - interrupts = <0 124 0>; - clocks = <&clock CLK_MDMA1>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <1>; + gsc_1: gsc@13e10000 { + compatible = "samsung,exynos5-gsc"; + reg = <0x13e10000 0x1000>; + interrupts = <0 86 0>; + power-domains = <&pd_gsc>; + clocks = <&clock CLK_GSCL1>; + clock-names = "gscl"; + iommu = <&sysmmu_gsc1>; }; - }; - gsc_0: gsc@13e00000 { - compatible = "samsung,exynos5-gsc"; - reg = <0x13e00000 0x1000>; - interrupts = <0 85 0>; - power-domains = <&pd_gsc>; - clocks = <&clock CLK_GSCL0>; - clock-names = "gscl"; - iommu = <&sysmmu_gsc0>; - }; + gsc_2: gsc@13e20000 { + compatible = "samsung,exynos5-gsc"; + reg = <0x13e20000 0x1000>; + interrupts = <0 87 0>; + power-domains = <&pd_gsc>; + clocks = <&clock CLK_GSCL2>; + clock-names = "gscl"; + iommu = <&sysmmu_gsc2>; + }; - gsc_1: gsc@13e10000 { - compatible = "samsung,exynos5-gsc"; - reg = <0x13e10000 0x1000>; - interrupts = <0 86 0>; - power-domains = <&pd_gsc>; - clocks = <&clock CLK_GSCL1>; - clock-names = "gscl"; - iommu = <&sysmmu_gsc1>; - }; + gsc_3: gsc@13e30000 { + compatible = "samsung,exynos5-gsc"; + reg = <0x13e30000 0x1000>; + interrupts = <0 88 0>; + power-domains = <&pd_gsc>; + clocks = <&clock CLK_GSCL3>; + clock-names = "gscl"; + iommu = <&sysmmu_gsc3>; + }; - gsc_2: gsc@13e20000 { - compatible = "samsung,exynos5-gsc"; - reg = <0x13e20000 0x1000>; - interrupts = <0 87 0>; - power-domains = <&pd_gsc>; - clocks = <&clock CLK_GSCL2>; - clock-names = "gscl"; - iommu = <&sysmmu_gsc2>; - }; + hdmi: hdmi@14530000 { + compatible = "samsung,exynos4212-hdmi"; + reg = <0x14530000 0x70000>; + power-domains = <&pd_disp1>; + interrupts = <0 95 0>; + clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>, + <&clock CLK_SCLK_PIXEL>, <&clock CLK_SCLK_HDMIPHY>, + <&clock CLK_MOUT_HDMI>; + clock-names = "hdmi", "sclk_hdmi", "sclk_pixel", + "sclk_hdmiphy", "mout_hdmi"; + samsung,syscon-phandle = <&pmu_system_controller>; + }; - gsc_3: gsc@13e30000 { - compatible = "samsung,exynos5-gsc"; - reg = <0x13e30000 0x1000>; - interrupts = <0 88 0>; - power-domains = <&pd_gsc>; - clocks = <&clock CLK_GSCL3>; - clock-names = "gscl"; - iommu = <&sysmmu_gsc3>; - }; + mixer@14450000 { + compatible = "samsung,exynos5250-mixer"; + reg = <0x14450000 0x10000>; + power-domains = <&pd_disp1>; + interrupts = <0 94 0>; + clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>, + <&clock CLK_SCLK_HDMI>; + clock-names = "mixer", "hdmi", "sclk_hdmi"; + iommus = <&sysmmu_tv>; + }; - hdmi: hdmi@14530000 { - compatible = "samsung,exynos4212-hdmi"; - reg = <0x14530000 0x70000>; - power-domains = <&pd_disp1>; - interrupts = <0 95 0>; - clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>, - <&clock CLK_SCLK_PIXEL>, <&clock CLK_SCLK_HDMIPHY>, - <&clock CLK_MOUT_HDMI>; - clock-names = "hdmi", "sclk_hdmi", "sclk_pixel", - "sclk_hdmiphy", "mout_hdmi"; - samsung,syscon-phandle = <&pmu_system_controller>; - }; + dp_phy: video-phy { + compatible = "samsung,exynos5250-dp-video-phy"; + samsung,pmu-syscon = <&pmu_system_controller>; + #phy-cells = <0>; + }; - mixer@14450000 { - compatible = "samsung,exynos5250-mixer"; - reg = <0x14450000 0x10000>; - power-domains = <&pd_disp1>; - interrupts = <0 94 0>; - clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>, - <&clock CLK_SCLK_HDMI>; - clock-names = "mixer", "hdmi", "sclk_hdmi"; - iommus = <&sysmmu_tv>; - }; + adc: adc@12D10000 { + compatible = "samsung,exynos-adc-v1"; + reg = <0x12D10000 0x100>; + interrupts = <0 106 0>; + clocks = <&clock CLK_ADC>; + clock-names = "adc"; + #io-channel-cells = <1>; + io-channel-ranges; + samsung,syscon-phandle = <&pmu_system_controller>; + status = "disabled"; + }; - dp_phy: video-phy { - compatible = "samsung,exynos5250-dp-video-phy"; - samsung,pmu-syscon = <&pmu_system_controller>; - #phy-cells = <0>; - }; + sss@10830000 { + compatible = "samsung,exynos4210-secss"; + reg = <0x10830000 0x300>; + interrupts = <0 112 0>; + clocks = <&clock CLK_SSS>; + clock-names = "secss"; + }; - adc: adc@12D10000 { - compatible = "samsung,exynos-adc-v1"; - reg = <0x12D10000 0x100>; - interrupts = <0 106 0>; - clocks = <&clock CLK_ADC>; - clock-names = "adc"; - #io-channel-cells = <1>; - io-channel-ranges; - samsung,syscon-phandle = <&pmu_system_controller>; - status = "disabled"; - }; + sysmmu_g2d: sysmmu@10A60000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x10A60000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <24 5>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_2D>, <&clock CLK_G2D>; + #iommu-cells = <0>; + }; - sss@10830000 { - compatible = "samsung,exynos4210-secss"; - reg = <0x10830000 0x300>; - interrupts = <0 112 0>; - clocks = <&clock CLK_SSS>; - clock-names = "secss"; - }; + sysmmu_mfc_r: sysmmu@11200000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x11200000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <6 2>; + power-domains = <&pd_mfc>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>; + #iommu-cells = <0>; + }; - sysmmu_g2d: sysmmu@10A60000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x10A60000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <24 5>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_2D>, <&clock CLK_G2D>; - #iommu-cells = <0>; - }; + sysmmu_mfc_l: sysmmu@11210000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x11210000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <8 5>; + power-domains = <&pd_mfc>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>; + #iommu-cells = <0>; + }; - sysmmu_mfc_r: sysmmu@11200000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x11200000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <6 2>; - power-domains = <&pd_mfc>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>; - #iommu-cells = <0>; - }; + sysmmu_rotator: sysmmu@11D40000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x11D40000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <4 0>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_ROTATOR>, <&clock CLK_ROTATOR>; + #iommu-cells = <0>; + }; - sysmmu_mfc_l: sysmmu@11210000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x11210000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <8 5>; - power-domains = <&pd_mfc>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>; - #iommu-cells = <0>; - }; + sysmmu_jpeg: sysmmu@11F20000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x11F20000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <4 2>; + power-domains = <&pd_gsc>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>; + #iommu-cells = <0>; + }; - sysmmu_rotator: sysmmu@11D40000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x11D40000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <4 0>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_ROTATOR>, <&clock CLK_ROTATOR>; - #iommu-cells = <0>; - }; + sysmmu_fimc_isp: sysmmu@13260000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x13260000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <10 6>; + clock-names = "sysmmu"; + clocks = <&clock CLK_SMMU_FIMC_ISP>; + #iommu-cells = <0>; + }; - sysmmu_jpeg: sysmmu@11F20000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x11F20000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <4 2>; - power-domains = <&pd_gsc>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>; - #iommu-cells = <0>; - }; + sysmmu_fimc_drc: sysmmu@13270000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x13270000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <11 6>; + clock-names = "sysmmu"; + clocks = <&clock CLK_SMMU_FIMC_DRC>; + #iommu-cells = <0>; + }; - sysmmu_fimc_isp: sysmmu@13260000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x13260000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <10 6>; - clock-names = "sysmmu"; - clocks = <&clock CLK_SMMU_FIMC_ISP>; - #iommu-cells = <0>; - }; + sysmmu_fimc_fd: sysmmu@132A0000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x132A0000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <5 0>; + clock-names = "sysmmu"; + clocks = <&clock CLK_SMMU_FIMC_FD>; + #iommu-cells = <0>; + }; - sysmmu_fimc_drc: sysmmu@13270000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x13270000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <11 6>; - clock-names = "sysmmu"; - clocks = <&clock CLK_SMMU_FIMC_DRC>; - #iommu-cells = <0>; - }; + sysmmu_fimc_scc: sysmmu@13280000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x13280000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <5 2>; + clock-names = "sysmmu"; + clocks = <&clock CLK_SMMU_FIMC_SCC>; + #iommu-cells = <0>; + }; - sysmmu_fimc_fd: sysmmu@132A0000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x132A0000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <5 0>; - clock-names = "sysmmu"; - clocks = <&clock CLK_SMMU_FIMC_FD>; - #iommu-cells = <0>; - }; + sysmmu_fimc_scp: sysmmu@13290000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x13290000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <3 6>; + clock-names = "sysmmu"; + clocks = <&clock CLK_SMMU_FIMC_SCP>; + #iommu-cells = <0>; + }; - sysmmu_fimc_scc: sysmmu@13280000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x13280000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <5 2>; - clock-names = "sysmmu"; - clocks = <&clock CLK_SMMU_FIMC_SCC>; - #iommu-cells = <0>; - }; + sysmmu_fimc_mcuctl: sysmmu@132B0000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x132B0000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <5 4>; + clock-names = "sysmmu"; + clocks = <&clock CLK_SMMU_FIMC_MCU>; + #iommu-cells = <0>; + }; - sysmmu_fimc_scp: sysmmu@13290000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x13290000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <3 6>; - clock-names = "sysmmu"; - clocks = <&clock CLK_SMMU_FIMC_SCP>; - #iommu-cells = <0>; - }; + sysmmu_fimc_odc: sysmmu@132C0000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x132C0000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <11 0>; + clock-names = "sysmmu"; + clocks = <&clock CLK_SMMU_FIMC_ODC>; + #iommu-cells = <0>; + }; - sysmmu_fimc_mcuctl: sysmmu@132B0000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x132B0000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <5 4>; - clock-names = "sysmmu"; - clocks = <&clock CLK_SMMU_FIMC_MCU>; - #iommu-cells = <0>; - }; + sysmmu_fimc_dis0: sysmmu@132D0000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x132D0000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <10 4>; + clock-names = "sysmmu"; + clocks = <&clock CLK_SMMU_FIMC_DIS0>; + #iommu-cells = <0>; + }; - sysmmu_fimc_odc: sysmmu@132C0000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x132C0000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <11 0>; - clock-names = "sysmmu"; - clocks = <&clock CLK_SMMU_FIMC_ODC>; - #iommu-cells = <0>; - }; + sysmmu_fimc_dis1: sysmmu@132E0000{ + compatible = "samsung,exynos-sysmmu"; + reg = <0x132E0000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <9 4>; + clock-names = "sysmmu"; + clocks = <&clock CLK_SMMU_FIMC_DIS1>; + #iommu-cells = <0>; + }; - sysmmu_fimc_dis0: sysmmu@132D0000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x132D0000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <10 4>; - clock-names = "sysmmu"; - clocks = <&clock CLK_SMMU_FIMC_DIS0>; - #iommu-cells = <0>; - }; + sysmmu_fimc_3dnr: sysmmu@132F0000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x132F0000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <5 6>; + clock-names = "sysmmu"; + clocks = <&clock CLK_SMMU_FIMC_3DNR>; + #iommu-cells = <0>; + }; - sysmmu_fimc_dis1: sysmmu@132E0000{ - compatible = "samsung,exynos-sysmmu"; - reg = <0x132E0000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <9 4>; - clock-names = "sysmmu"; - clocks = <&clock CLK_SMMU_FIMC_DIS1>; - #iommu-cells = <0>; - }; + sysmmu_fimc_lite0: sysmmu@13C40000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x13C40000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <3 4>; + power-domains = <&pd_gsc>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_FIMC_LITE0>, <&clock CLK_CAMIF_TOP>; + #iommu-cells = <0>; + }; - sysmmu_fimc_3dnr: sysmmu@132F0000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x132F0000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <5 6>; - clock-names = "sysmmu"; - clocks = <&clock CLK_SMMU_FIMC_3DNR>; - #iommu-cells = <0>; - }; + sysmmu_fimc_lite1: sysmmu@13C50000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x13C50000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <24 1>; + power-domains = <&pd_gsc>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_FIMC_LITE1>, <&clock CLK_CAMIF_TOP>; + #iommu-cells = <0>; + }; - sysmmu_fimc_lite0: sysmmu@13C40000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x13C40000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <3 4>; - power-domains = <&pd_gsc>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_FIMC_LITE0>, <&clock CLK_CAMIF_TOP>; - #iommu-cells = <0>; - }; + sysmmu_gsc0: sysmmu@13E80000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x13E80000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <2 0>; + power-domains = <&pd_gsc>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_GSCL0>, <&clock CLK_GSCL0>; + #iommu-cells = <0>; + }; - sysmmu_fimc_lite1: sysmmu@13C50000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x13C50000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <24 1>; - power-domains = <&pd_gsc>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_FIMC_LITE1>, <&clock CLK_CAMIF_TOP>; - #iommu-cells = <0>; - }; + sysmmu_gsc1: sysmmu@13E90000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x13E90000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <2 2>; + power-domains = <&pd_gsc>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_GSCL1>, <&clock CLK_GSCL1>; + #iommu-cells = <0>; + }; - sysmmu_gsc0: sysmmu@13E80000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x13E80000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <2 0>; - power-domains = <&pd_gsc>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_GSCL0>, <&clock CLK_GSCL0>; - #iommu-cells = <0>; - }; + sysmmu_gsc2: sysmmu@13EA0000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x13EA0000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <2 4>; + power-domains = <&pd_gsc>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_GSCL2>, <&clock CLK_GSCL2>; + #iommu-cells = <0>; + }; - sysmmu_gsc1: sysmmu@13E90000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x13E90000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <2 2>; - power-domains = <&pd_gsc>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_GSCL1>, <&clock CLK_GSCL1>; - #iommu-cells = <0>; - }; + sysmmu_gsc3: sysmmu@13EB0000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x13EB0000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <2 6>; + power-domains = <&pd_gsc>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_GSCL3>, <&clock CLK_GSCL3>; + #iommu-cells = <0>; + }; - sysmmu_gsc2: sysmmu@13EA0000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x13EA0000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <2 4>; - power-domains = <&pd_gsc>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_GSCL2>, <&clock CLK_GSCL2>; - #iommu-cells = <0>; - }; + sysmmu_fimd1: sysmmu@14640000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x14640000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <3 2>; + power-domains = <&pd_disp1>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_FIMD1>, <&clock CLK_FIMD1>; + #iommu-cells = <0>; + }; - sysmmu_gsc3: sysmmu@13EB0000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x13EB0000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <2 6>; - power-domains = <&pd_gsc>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_GSCL3>, <&clock CLK_GSCL3>; - #iommu-cells = <0>; + sysmmu_tv: sysmmu@14650000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x14650000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <7 4>; + power-domains = <&pd_disp1>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_TV>, <&clock CLK_MIXER>; + #iommu-cells = <0>; + }; }; - sysmmu_fimd1: sysmmu@14640000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x14640000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <3 2>; - power-domains = <&pd_disp1>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_FIMD1>, <&clock CLK_FIMD1>; - #iommu-cells = <0>; - }; + thermal-zones { + cpu_thermal: cpu-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tmu 0>; - sysmmu_tv: sysmmu@14650000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x14650000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <7 4>; - power-domains = <&pd_disp1>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_TV>, <&clock CLK_MIXER>; - #iommu-cells = <0>; + cooling-maps { + map0 { + /* Corresponds to 800MHz at freq_table */ + cooling-device = <&cpu0 9 9>; + }; + map1 { + /* Corresponds to 200MHz at freq_table */ + cooling-device = <&cpu0 15 15>; + }; + }; + }; }; }; diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index 5bf7882..b65bdbe 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -46,1480 +46,1483 @@ usbdrdphy1 = &usbdrd_phy1; }; - cluster_a15_opp_table: opp_table0 { - compatible = "operating-points-v2"; - opp-shared; - opp@1800000000 { - opp-hz = /bits/ 64 <1800000000>; - opp-microvolt = <1250000>; - clock-latency-ns = <140000>; - }; - opp@1700000000 { - opp-hz = /bits/ 64 <1700000000>; - opp-microvolt = <1212500>; - clock-latency-ns = <140000>; - }; - opp@1600000000 { - opp-hz = /bits/ 64 <1600000000>; - opp-microvolt = <1175000>; - clock-latency-ns = <140000>; - }; - opp@1500000000 { - opp-hz = /bits/ 64 <1500000000>; - opp-microvolt = <1137500>; - clock-latency-ns = <140000>; - }; - opp@1400000000 { - opp-hz = /bits/ 64 <1400000000>; - opp-microvolt = <1112500>; - clock-latency-ns = <140000>; - }; - opp@1300000000 { - opp-hz = /bits/ 64 <1300000000>; - opp-microvolt = <1062500>; - clock-latency-ns = <140000>; - }; - opp@1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <1037500>; - clock-latency-ns = <140000>; - }; - opp@1100000000 { - opp-hz = /bits/ 64 <1100000000>; - opp-microvolt = <1012500>; - clock-latency-ns = <140000>; - }; - opp@1000000000 { - opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = < 987500>; - clock-latency-ns = <140000>; - }; - opp@900000000 { - opp-hz = /bits/ 64 <900000000>; - opp-microvolt = < 962500>; - clock-latency-ns = <140000>; - }; - opp@800000000 { - opp-hz = /bits/ 64 <800000000>; - opp-microvolt = < 937500>; - clock-latency-ns = <140000>; - }; - opp@700000000 { - opp-hz = /bits/ 64 <700000000>; - opp-microvolt = < 912500>; - clock-latency-ns = <140000>; - }; - }; - - cluster_a7_opp_table: opp_table1 { - compatible = "operating-points-v2"; - opp-shared; - opp@1300000000 { - opp-hz = /bits/ 64 <1300000000>; - opp-microvolt = <1275000>; - clock-latency-ns = <140000>; - }; - opp@1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <1212500>; - clock-latency-ns = <140000>; - }; - opp@1100000000 { - opp-hz = /bits/ 64 <1100000000>; - opp-microvolt = <1162500>; - clock-latency-ns = <140000>; - }; - opp@1000000000 { - opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <1112500>; - clock-latency-ns = <140000>; - }; - opp@900000000 { - opp-hz = /bits/ 64 <900000000>; - opp-microvolt = <1062500>; - clock-latency-ns = <140000>; - }; - opp@800000000 { - opp-hz = /bits/ 64 <800000000>; - opp-microvolt = <1025000>; - clock-latency-ns = <140000>; - }; - opp@700000000 { - opp-hz = /bits/ 64 <700000000>; - opp-microvolt = <975000>; - clock-latency-ns = <140000>; - }; - opp@600000000 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <937500>; - clock-latency-ns = <140000>; - }; - }; - /* * The 'cpus' node is not present here but instead it is provided * by exynos5420-cpus.dtsi or exynos5422-cpus.dtsi. */ - cci: cci@10d20000 { - compatible = "arm,cci-400"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x10d20000 0x1000>; - ranges = <0x0 0x10d20000 0x6000>; - - cci_control0: slave-if@4000 { - compatible = "arm,cci-400-ctrl-if"; - interface-type = "ace"; - reg = <0x4000 0x1000>; - }; - cci_control1: slave-if@5000 { - compatible = "arm,cci-400-ctrl-if"; - interface-type = "ace"; - reg = <0x5000 0x1000>; + soc: soc { + cluster_a15_opp_table: opp_table0 { + compatible = "operating-points-v2"; + opp-shared; + opp@1800000000 { + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <1250000>; + clock-latency-ns = <140000>; + }; + opp@1700000000 { + opp-hz = /bits/ 64 <1700000000>; + opp-microvolt = <1212500>; + clock-latency-ns = <140000>; + }; + opp@1600000000 { + opp-hz = /bits/ 64 <1600000000>; + opp-microvolt = <1175000>; + clock-latency-ns = <140000>; + }; + opp@1500000000 { + opp-hz = /bits/ 64 <1500000000>; + opp-microvolt = <1137500>; + clock-latency-ns = <140000>; + }; + opp@1400000000 { + opp-hz = /bits/ 64 <1400000000>; + opp-microvolt = <1112500>; + clock-latency-ns = <140000>; + }; + opp@1300000000 { + opp-hz = /bits/ 64 <1300000000>; + opp-microvolt = <1062500>; + clock-latency-ns = <140000>; + }; + opp@1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <1037500>; + clock-latency-ns = <140000>; + }; + opp@1100000000 { + opp-hz = /bits/ 64 <1100000000>; + opp-microvolt = <1012500>; + clock-latency-ns = <140000>; + }; + opp@1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = < 987500>; + clock-latency-ns = <140000>; + }; + opp@900000000 { + opp-hz = /bits/ 64 <900000000>; + opp-microvolt = < 962500>; + clock-latency-ns = <140000>; + }; + opp@800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = < 937500>; + clock-latency-ns = <140000>; + }; + opp@700000000 { + opp-hz = /bits/ 64 <700000000>; + opp-microvolt = < 912500>; + clock-latency-ns = <140000>; + }; + }; + + cluster_a7_opp_table: opp_table1 { + compatible = "operating-points-v2"; + opp-shared; + opp@1300000000 { + opp-hz = /bits/ 64 <1300000000>; + opp-microvolt = <1275000>; + clock-latency-ns = <140000>; + }; + opp@1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <1212500>; + clock-latency-ns = <140000>; + }; + opp@1100000000 { + opp-hz = /bits/ 64 <1100000000>; + opp-microvolt = <1162500>; + clock-latency-ns = <140000>; + }; + opp@1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <1112500>; + clock-latency-ns = <140000>; + }; + opp@900000000 { + opp-hz = /bits/ 64 <900000000>; + opp-microvolt = <1062500>; + clock-latency-ns = <140000>; + }; + opp@800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <1025000>; + clock-latency-ns = <140000>; + }; + opp@700000000 { + opp-hz = /bits/ 64 <700000000>; + opp-microvolt = <975000>; + clock-latency-ns = <140000>; + }; + opp@600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <937500>; + clock-latency-ns = <140000>; + }; + }; + + cci: cci@10d20000 { + compatible = "arm,cci-400"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x10d20000 0x1000>; + ranges = <0x0 0x10d20000 0x6000>; + + cci_control0: slave-if@4000 { + compatible = "arm,cci-400-ctrl-if"; + interface-type = "ace"; + reg = <0x4000 0x1000>; + }; + cci_control1: slave-if@5000 { + compatible = "arm,cci-400-ctrl-if"; + interface-type = "ace"; + reg = <0x5000 0x1000>; + }; + }; + + sysram@02020000 { + compatible = "mmio-sram"; + reg = <0x02020000 0x54000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x02020000 0x54000>; + + smp-sysram@0 { + compatible = "samsung,exynos4210-sysram"; + reg = <0x0 0x1000>; + }; + + smp-sysram@53000 { + compatible = "samsung,exynos4210-sysram-ns"; + reg = <0x53000 0x1000>; + }; + }; + + clock: clock-controller@10010000 { + compatible = "samsung,exynos5420-clock"; + reg = <0x10010000 0x30000>; + #clock-cells = <1>; + }; + + clock_audss: audss-clock-controller@3810000 { + compatible = "samsung,exynos5420-audss-clock"; + reg = <0x03810000 0x0C>; + #clock-cells = <1>; + clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MAU_EPLL>, + <&clock CLK_SCLK_MAUDIO0>, <&clock CLK_SCLK_MAUPCM0>; + clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in"; + }; + + mfc: codec@11000000 { + compatible = "samsung,mfc-v7"; + reg = <0x11000000 0x10000>; + interrupts = <0 96 0>; + clocks = <&clock CLK_MFC>; + clock-names = "mfc"; + power-domains = <&mfc_pd>; + iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>; + iommu-names = "left", "right"; + }; + + mmc_0: mmc@12200000 { + compatible = "samsung,exynos5420-dw-mshc-smu"; + interrupts = <0 75 0>; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x12200000 0x2000>; + clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>; + clock-names = "biu", "ciu"; + fifo-depth = <0x40>; + status = "disabled"; }; - }; - - sysram@02020000 { - compatible = "mmio-sram"; - reg = <0x02020000 0x54000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x02020000 0x54000>; - smp-sysram@0 { - compatible = "samsung,exynos4210-sysram"; - reg = <0x0 0x1000>; + mmc_1: mmc@12210000 { + compatible = "samsung,exynos5420-dw-mshc-smu"; + interrupts = <0 76 0>; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x12210000 0x2000>; + clocks = <&clock CLK_MMC1>, <&clock CLK_SCLK_MMC1>; + clock-names = "biu", "ciu"; + fifo-depth = <0x40>; + status = "disabled"; }; - smp-sysram@53000 { - compatible = "samsung,exynos4210-sysram-ns"; - reg = <0x53000 0x1000>; + mmc_2: mmc@12220000 { + compatible = "samsung,exynos5420-dw-mshc"; + interrupts = <0 77 0>; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x12220000 0x1000>; + clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>; + clock-names = "biu", "ciu"; + fifo-depth = <0x40>; + status = "disabled"; }; - }; - - clock: clock-controller@10010000 { - compatible = "samsung,exynos5420-clock"; - reg = <0x10010000 0x30000>; - #clock-cells = <1>; - }; - - clock_audss: audss-clock-controller@3810000 { - compatible = "samsung,exynos5420-audss-clock"; - reg = <0x03810000 0x0C>; - #clock-cells = <1>; - clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MAU_EPLL>, - <&clock CLK_SCLK_MAUDIO0>, <&clock CLK_SCLK_MAUPCM0>; - clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in"; - }; - - mfc: codec@11000000 { - compatible = "samsung,mfc-v7"; - reg = <0x11000000 0x10000>; - interrupts = <0 96 0>; - clocks = <&clock CLK_MFC>; - clock-names = "mfc"; - power-domains = <&mfc_pd>; - iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>; - iommu-names = "left", "right"; - }; - mmc_0: mmc@12200000 { - compatible = "samsung,exynos5420-dw-mshc-smu"; - interrupts = <0 75 0>; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x12200000 0x2000>; - clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>; - clock-names = "biu", "ciu"; - fifo-depth = <0x40>; - status = "disabled"; - }; - - mmc_1: mmc@12210000 { - compatible = "samsung,exynos5420-dw-mshc-smu"; - interrupts = <0 76 0>; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x12210000 0x2000>; - clocks = <&clock CLK_MMC1>, <&clock CLK_SCLK_MMC1>; - clock-names = "biu", "ciu"; - fifo-depth = <0x40>; - status = "disabled"; - }; - - mmc_2: mmc@12220000 { - compatible = "samsung,exynos5420-dw-mshc"; - interrupts = <0 77 0>; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x12220000 0x1000>; - clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>; - clock-names = "biu", "ciu"; - fifo-depth = <0x40>; - status = "disabled"; - }; - - mct: mct@101C0000 { - compatible = "samsung,exynos4210-mct"; - reg = <0x101C0000 0x800>; - interrupt-controller; - #interrupt-cells = <1>; - interrupt-parent = <&mct_map>; - interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>, - <8>, <9>, <10>, <11>; - clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>; - clock-names = "fin_pll", "mct"; - - mct_map: mct-map { + mct: mct@101C0000 { + compatible = "samsung,exynos4210-mct"; + reg = <0x101C0000 0x800>; + interrupt-controller; #interrupt-cells = <1>; - #address-cells = <0>; - #size-cells = <0>; - interrupt-map = <0 &combiner 23 3>, - <1 &combiner 23 4>, - <2 &combiner 25 2>, - <3 &combiner 25 3>, - <4 &gic 0 120 0>, - <5 &gic 0 121 0>, - <6 &gic 0 122 0>, - <7 &gic 0 123 0>, - <8 &gic 0 128 0>, - <9 &gic 0 129 0>, - <10 &gic 0 130 0>, - <11 &gic 0 131 0>; + interrupt-parent = <&mct_map>; + interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>, + <8>, <9>, <10>, <11>; + clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>; + clock-names = "fin_pll", "mct"; + + mct_map: mct-map { + #interrupt-cells = <1>; + #address-cells = <0>; + #size-cells = <0>; + interrupt-map = <0 &combiner 23 3>, + <1 &combiner 23 4>, + <2 &combiner 25 2>, + <3 &combiner 25 3>, + <4 &gic 0 120 0>, + <5 &gic 0 121 0>, + <6 &gic 0 122 0>, + <7 &gic 0 123 0>, + <8 &gic 0 128 0>, + <9 &gic 0 129 0>, + <10 &gic 0 130 0>, + <11 &gic 0 131 0>; + }; + }; + + nocp_mem0_0: nocp@10CA1000 { + compatible = "samsung,exynos5420-nocp"; + reg = <0x10CA1000 0x200>; + status = "disabled"; }; - }; - - nocp_mem0_0: nocp@10CA1000 { - compatible = "samsung,exynos5420-nocp"; - reg = <0x10CA1000 0x200>; - status = "disabled"; - }; - - nocp_mem0_1: nocp@10CA1400 { - compatible = "samsung,exynos5420-nocp"; - reg = <0x10CA1400 0x200>; - status = "disabled"; - }; - - nocp_mem1_0: nocp@10CA1800 { - compatible = "samsung,exynos5420-nocp"; - reg = <0x10CA1800 0x200>; - status = "disabled"; - }; - - nocp_mem1_1: nocp@10CA1C00 { - compatible = "samsung,exynos5420-nocp"; - reg = <0x10CA1C00 0x200>; - status = "disabled"; - }; - - nocp_g3d_0: nocp@11A51000 { - compatible = "samsung,exynos5420-nocp"; - reg = <0x11A51000 0x200>; - status = "disabled"; - }; - - nocp_g3d_1: nocp@11A51400 { - compatible = "samsung,exynos5420-nocp"; - reg = <0x11A51400 0x200>; - status = "disabled"; - }; - - gsc_pd: power-domain@10044000 { - compatible = "samsung,exynos4210-pd"; - reg = <0x10044000 0x20>; - #power-domain-cells = <0>; - clocks = <&clock CLK_FIN_PLL>, - <&clock CLK_MOUT_USER_ACLK300_GSCL>, - <&clock CLK_GSCL0>, <&clock CLK_GSCL1>; - clock-names = "oscclk", "clk0", "asb0", "asb1"; - }; - - isp_pd: power-domain@10044020 { - compatible = "samsung,exynos4210-pd"; - reg = <0x10044020 0x20>; - #power-domain-cells = <0>; - }; - - mfc_pd: power-domain@10044060 { - compatible = "samsung,exynos4210-pd"; - reg = <0x10044060 0x20>; - clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MOUT_USER_ACLK333>; - clock-names = "oscclk", "clk0"; - #power-domain-cells = <0>; - }; - - msc_pd: power-domain@10044120 { - compatible = "samsung,exynos4210-pd"; - reg = <0x10044120 0x20>; - #power-domain-cells = <0>; - }; - - disp_pd: power-domain@100440C0 { - compatible = "samsung,exynos4210-pd"; - reg = <0x100440C0 0x20>; - #power-domain-cells = <0>; - clocks = <&clock CLK_FIN_PLL>, - <&clock CLK_MOUT_USER_ACLK200_DISP1>, - <&clock CLK_MOUT_USER_ACLK300_DISP1>, - <&clock CLK_MOUT_USER_ACLK400_DISP1>, - <&clock CLK_FIMD1>, <&clock CLK_MIXER>; - clock-names = "oscclk", "clk0", "clk1", "clk2", "asb0", "asb1"; - }; - pinctrl_0: pinctrl@13400000 { - compatible = "samsung,exynos5420-pinctrl"; - reg = <0x13400000 0x1000>; - interrupts = <0 45 0>; - - wakeup-interrupt-controller { - compatible = "samsung,exynos4210-wakeup-eint"; - interrupt-parent = <&gic>; - interrupts = <0 32 0>; + nocp_mem0_1: nocp@10CA1400 { + compatible = "samsung,exynos5420-nocp"; + reg = <0x10CA1400 0x200>; + status = "disabled"; }; - }; - - pinctrl_1: pinctrl@13410000 { - compatible = "samsung,exynos5420-pinctrl"; - reg = <0x13410000 0x1000>; - interrupts = <0 78 0>; - }; - pinctrl_2: pinctrl@14000000 { - compatible = "samsung,exynos5420-pinctrl"; - reg = <0x14000000 0x1000>; - interrupts = <0 46 0>; - }; - - pinctrl_3: pinctrl@14010000 { - compatible = "samsung,exynos5420-pinctrl"; - reg = <0x14010000 0x1000>; - interrupts = <0 50 0>; - }; - - pinctrl_4: pinctrl@03860000 { - compatible = "samsung,exynos5420-pinctrl"; - reg = <0x03860000 0x1000>; - interrupts = <0 47 0>; - }; - - amba { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - interrupt-parent = <&gic>; - ranges; - - adma: adma@03880000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x03880000 0x1000>; - interrupts = <0 110 0>; - clocks = <&clock_audss EXYNOS_ADMA>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - #dma-channels = <6>; - #dma-requests = <16>; - }; - - pdma0: pdma@121A0000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x121A0000 0x1000>; - interrupts = <0 34 0>; - clocks = <&clock CLK_PDMA0>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; - }; - - pdma1: pdma@121B0000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x121B0000 0x1000>; - interrupts = <0 35 0>; - clocks = <&clock CLK_PDMA1>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; - }; - - mdma0: mdma@10800000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x10800000 0x1000>; - interrupts = <0 33 0>; - clocks = <&clock CLK_MDMA0>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <1>; - }; - - mdma1: mdma@11C10000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x11C10000 0x1000>; - interrupts = <0 124 0>; - clocks = <&clock CLK_MDMA1>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <1>; - /* - * MDMA1 can support both secure and non-secure - * AXI transactions. When this is enabled in the kernel - * for boards that run in secure mode, we are getting - * imprecise external aborts causing the kernel to oops. - */ + nocp_mem1_0: nocp@10CA1800 { + compatible = "samsung,exynos5420-nocp"; + reg = <0x10CA1800 0x200>; status = "disabled"; }; - }; - - i2s0: i2s@03830000 { - compatible = "samsung,exynos5420-i2s"; - reg = <0x03830000 0x100>; - dmas = <&adma 0 - &adma 2 - &adma 1>; - dma-names = "tx", "rx", "tx-sec"; - clocks = <&clock_audss EXYNOS_I2S_BUS>, - <&clock_audss EXYNOS_I2S_BUS>, - <&clock_audss EXYNOS_SCLK_I2S>; - clock-names = "iis", "i2s_opclk0", "i2s_opclk1"; - #clock-cells = <1>; - clock-output-names = "i2s_cdclk0"; - #sound-dai-cells = <1>; - samsung,idma-addr = <0x03000000>; - pinctrl-names = "default"; - pinctrl-0 = <&i2s0_bus>; - status = "disabled"; - }; - - i2s1: i2s@12D60000 { - compatible = "samsung,exynos5420-i2s"; - reg = <0x12D60000 0x100>; - dmas = <&pdma1 12 - &pdma1 11>; - dma-names = "tx", "rx"; - clocks = <&clock CLK_I2S1>, <&clock CLK_SCLK_I2S1>; - clock-names = "iis", "i2s_opclk0"; - #clock-cells = <1>; - clock-output-names = "i2s_cdclk1"; - #sound-dai-cells = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&i2s1_bus>; - status = "disabled"; - }; - - i2s2: i2s@12D70000 { - compatible = "samsung,exynos5420-i2s"; - reg = <0x12D70000 0x100>; - dmas = <&pdma0 12 - &pdma0 11>; - dma-names = "tx", "rx"; - clocks = <&clock CLK_I2S2>, <&clock CLK_SCLK_I2S2>; - clock-names = "iis", "i2s_opclk0"; - #clock-cells = <1>; - clock-output-names = "i2s_cdclk2"; - #sound-dai-cells = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&i2s2_bus>; - status = "disabled"; - }; - - spi_0: spi@12d20000 { - compatible = "samsung,exynos4210-spi"; - reg = <0x12d20000 0x100>; - interrupts = <0 68 0>; - dmas = <&pdma0 5 - &pdma0 4>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&spi0_bus>; - clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>; - clock-names = "spi", "spi_busclk0"; - status = "disabled"; - }; - - spi_1: spi@12d30000 { - compatible = "samsung,exynos4210-spi"; - reg = <0x12d30000 0x100>; - interrupts = <0 69 0>; - dmas = <&pdma1 5 - &pdma1 4>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&spi1_bus>; - clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>; - clock-names = "spi", "spi_busclk0"; - status = "disabled"; - }; - - spi_2: spi@12d40000 { - compatible = "samsung,exynos4210-spi"; - reg = <0x12d40000 0x100>; - interrupts = <0 70 0>; - dmas = <&pdma0 7 - &pdma0 6>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&spi2_bus>; - clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>; - clock-names = "spi", "spi_busclk0"; - status = "disabled"; - }; - - dp_phy: dp-video-phy { - compatible = "samsung,exynos5420-dp-video-phy"; - samsung,pmu-syscon = <&pmu_system_controller>; - #phy-cells = <0>; - }; - - mipi_phy: mipi-video-phy { - compatible = "samsung,s5pv210-mipi-video-phy"; - syscon = <&pmu_system_controller>; - #phy-cells = <1>; - }; - - dsi@14500000 { - compatible = "samsung,exynos5410-mipi-dsi"; - reg = <0x14500000 0x10000>; - interrupts = <0 82 0>; - phys = <&mipi_phy 1>; - phy-names = "dsim"; - clocks = <&clock CLK_DSIM1>, <&clock CLK_SCLK_MIPI1>; - clock-names = "bus_clk", "pll_clk"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - adc: adc@12D10000 { - compatible = "samsung,exynos-adc-v2"; - reg = <0x12D10000 0x100>; - interrupts = <0 106 0>; - clocks = <&clock CLK_TSADC>; - clock-names = "adc"; - #io-channel-cells = <1>; - io-channel-ranges; - samsung,syscon-phandle = <&pmu_system_controller>; - status = "disabled"; - }; - - /* i2c_0-3 are defined in exynos5.dtsi */ - hsi2c_4: i2c@12CA0000 { - compatible = "samsung,exynos5250-hsi2c"; - reg = <0x12CA0000 0x1000>; - interrupts = <0 60 0>; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c4_hs_bus>; - clocks = <&clock CLK_USI0>; - clock-names = "hsi2c"; - status = "disabled"; - }; - - hsi2c_5: i2c@12CB0000 { - compatible = "samsung,exynos5250-hsi2c"; - reg = <0x12CB0000 0x1000>; - interrupts = <0 61 0>; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c5_hs_bus>; - clocks = <&clock CLK_USI1>; - clock-names = "hsi2c"; - status = "disabled"; - }; - - hsi2c_6: i2c@12CC0000 { - compatible = "samsung,exynos5250-hsi2c"; - reg = <0x12CC0000 0x1000>; - interrupts = <0 62 0>; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c6_hs_bus>; - clocks = <&clock CLK_USI2>; - clock-names = "hsi2c"; - status = "disabled"; - }; - - hsi2c_7: i2c@12CD0000 { - compatible = "samsung,exynos5250-hsi2c"; - reg = <0x12CD0000 0x1000>; - interrupts = <0 63 0>; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c7_hs_bus>; - clocks = <&clock CLK_USI3>; - clock-names = "hsi2c"; - status = "disabled"; - }; - - hsi2c_8: i2c@12E00000 { - compatible = "samsung,exynos5250-hsi2c"; - reg = <0x12E00000 0x1000>; - interrupts = <0 87 0>; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c8_hs_bus>; - clocks = <&clock CLK_USI4>; - clock-names = "hsi2c"; - status = "disabled"; - }; - - hsi2c_9: i2c@12E10000 { - compatible = "samsung,exynos5250-hsi2c"; - reg = <0x12E10000 0x1000>; - interrupts = <0 88 0>; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c9_hs_bus>; - clocks = <&clock CLK_USI5>; - clock-names = "hsi2c"; - status = "disabled"; - }; - - hsi2c_10: i2c@12E20000 { - compatible = "samsung,exynos5250-hsi2c"; - reg = <0x12E20000 0x1000>; - interrupts = <0 203 0>; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c10_hs_bus>; - clocks = <&clock CLK_USI6>; - clock-names = "hsi2c"; - status = "disabled"; - }; - - hdmi: hdmi@14530000 { - compatible = "samsung,exynos5420-hdmi"; - reg = <0x14530000 0x70000>; - interrupts = <0 95 0>; - clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>, - <&clock CLK_DOUT_PIXEL>, <&clock CLK_SCLK_HDMIPHY>, - <&clock CLK_MOUT_HDMI>; - clock-names = "hdmi", "sclk_hdmi", "sclk_pixel", - "sclk_hdmiphy", "mout_hdmi"; - phy = <&hdmiphy>; - samsung,syscon-phandle = <&pmu_system_controller>; - status = "disabled"; - power-domains = <&disp_pd>; - }; - - hdmiphy: hdmiphy@145D0000 { - reg = <0x145D0000 0x20>; - }; - - mixer: mixer@14450000 { - compatible = "samsung,exynos5420-mixer"; - reg = <0x14450000 0x10000>; - interrupts = <0 94 0>; - clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>, - <&clock CLK_SCLK_HDMI>; - clock-names = "mixer", "hdmi", "sclk_hdmi"; - power-domains = <&disp_pd>; - iommus = <&sysmmu_tv>; - }; - - rotator: rotator@11C00000 { - compatible = "samsung,exynos5250-rotator"; - reg = <0x11C00000 0x64>; - interrupts = <0 84 0>; - clocks = <&clock CLK_ROTATOR>; - clock-names = "rotator"; - iommus = <&sysmmu_rotator>; - }; - - gsc_0: video-scaler@13e00000 { - compatible = "samsung,exynos5-gsc"; - reg = <0x13e00000 0x1000>; - interrupts = <0 85 0>; - clocks = <&clock CLK_GSCL0>; - clock-names = "gscl"; - power-domains = <&gsc_pd>; - iommus = <&sysmmu_gscl0>; - }; - - gsc_1: video-scaler@13e10000 { - compatible = "samsung,exynos5-gsc"; - reg = <0x13e10000 0x1000>; - interrupts = <0 86 0>; - clocks = <&clock CLK_GSCL1>; - clock-names = "gscl"; - power-domains = <&gsc_pd>; - iommus = <&sysmmu_gscl1>; - }; - jpeg_0: jpeg@11F50000 { - compatible = "samsung,exynos5420-jpeg"; - reg = <0x11F50000 0x1000>; - interrupts = <0 89 0>; - clock-names = "jpeg"; - clocks = <&clock CLK_JPEG>; - iommus = <&sysmmu_jpeg0>; - }; - - jpeg_1: jpeg@11F60000 { - compatible = "samsung,exynos5420-jpeg"; - reg = <0x11F60000 0x1000>; - interrupts = <0 168 0>; - clock-names = "jpeg"; - clocks = <&clock CLK_JPEG2>; - iommus = <&sysmmu_jpeg1>; - }; - - pmu_system_controller: system-controller@10040000 { - compatible = "samsung,exynos5420-pmu", "syscon"; - reg = <0x10040000 0x5000>; - clock-names = "clkout16"; - clocks = <&clock CLK_FIN_PLL>; - #clock-cells = <1>; - interrupt-controller; - #interrupt-cells = <3>; - interrupt-parent = <&gic>; - }; - - tmu_cpu0: tmu@10060000 { - compatible = "samsung,exynos5420-tmu"; - reg = <0x10060000 0x100>; - interrupts = <0 65 0>; - clocks = <&clock CLK_TMU>; - clock-names = "tmu_apbif"; - #include "exynos4412-tmu-sensor-conf.dtsi" - }; - - tmu_cpu1: tmu@10064000 { - compatible = "samsung,exynos5420-tmu"; - reg = <0x10064000 0x100>; - interrupts = <0 183 0>; - clocks = <&clock CLK_TMU>; - clock-names = "tmu_apbif"; - #include "exynos4412-tmu-sensor-conf.dtsi" - }; - - tmu_cpu2: tmu@10068000 { - compatible = "samsung,exynos5420-tmu-ext-triminfo"; - reg = <0x10068000 0x100>, <0x1006c000 0x4>; - interrupts = <0 184 0>; - clocks = <&clock CLK_TMU>, <&clock CLK_TMU>; - clock-names = "tmu_apbif", "tmu_triminfo_apbif"; - #include "exynos4412-tmu-sensor-conf.dtsi" - }; - - tmu_cpu3: tmu@1006c000 { - compatible = "samsung,exynos5420-tmu-ext-triminfo"; - reg = <0x1006c000 0x100>, <0x100a0000 0x4>; - interrupts = <0 185 0>; - clocks = <&clock CLK_TMU>, <&clock CLK_TMU_GPU>; - clock-names = "tmu_apbif", "tmu_triminfo_apbif"; - #include "exynos4412-tmu-sensor-conf.dtsi" - }; - - tmu_gpu: tmu@100a0000 { - compatible = "samsung,exynos5420-tmu-ext-triminfo"; - reg = <0x100a0000 0x100>, <0x10068000 0x4>; - interrupts = <0 215 0>; - clocks = <&clock CLK_TMU_GPU>, <&clock CLK_TMU>; - clock-names = "tmu_apbif", "tmu_triminfo_apbif"; - #include "exynos4412-tmu-sensor-conf.dtsi" - }; - - thermal-zones { - cpu0_thermal: cpu0-thermal { - thermal-sensors = <&tmu_cpu0>; - #include "exynos5420-trip-points.dtsi" - }; - cpu1_thermal: cpu1-thermal { - thermal-sensors = <&tmu_cpu1>; - #include "exynos5420-trip-points.dtsi" - }; - cpu2_thermal: cpu2-thermal { - thermal-sensors = <&tmu_cpu2>; - #include "exynos5420-trip-points.dtsi" - }; - cpu3_thermal: cpu3-thermal { - thermal-sensors = <&tmu_cpu3>; - #include "exynos5420-trip-points.dtsi" - }; - gpu_thermal: gpu-thermal { - thermal-sensors = <&tmu_gpu>; - #include "exynos5420-trip-points.dtsi" + nocp_mem1_1: nocp@10CA1C00 { + compatible = "samsung,exynos5420-nocp"; + reg = <0x10CA1C00 0x200>; + status = "disabled"; }; - }; - - watchdog: watchdog@101D0000 { - compatible = "samsung,exynos5420-wdt"; - reg = <0x101D0000 0x100>; - interrupts = <0 42 0>; - clocks = <&clock CLK_WDT>; - clock-names = "watchdog"; - samsung,syscon-phandle = <&pmu_system_controller>; - }; - - sss: sss@10830000 { - compatible = "samsung,exynos4210-secss"; - reg = <0x10830000 0x300>; - interrupts = <0 112 0>; - clocks = <&clock CLK_SSS>; - clock-names = "secss"; - }; - usbdrd3_0: usb3-0 { - compatible = "samsung,exynos5250-dwusb3"; - clocks = <&clock CLK_USBD300>; - clock-names = "usbdrd30"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - usbdrd_dwc3_0: dwc3@12000000 { - compatible = "snps,dwc3"; - reg = <0x12000000 0x10000>; - interrupts = <0 72 0>; - phys = <&usbdrd_phy0 0>, <&usbdrd_phy0 1>; - phy-names = "usb2-phy", "usb3-phy"; + nocp_g3d_0: nocp@11A51000 { + compatible = "samsung,exynos5420-nocp"; + reg = <0x11A51000 0x200>; + status = "disabled"; }; - }; - usbdrd_phy0: phy@12100000 { - compatible = "samsung,exynos5420-usbdrd-phy"; - reg = <0x12100000 0x100>; - clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>; - clock-names = "phy", "ref"; - samsung,pmu-syscon = <&pmu_system_controller>; - #phy-cells = <1>; - }; - - usbdrd3_1: usb3-1 { - compatible = "samsung,exynos5250-dwusb3"; - clocks = <&clock CLK_USBD301>; - clock-names = "usbdrd30"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - usbdrd_dwc3_1: dwc3@12400000 { - compatible = "snps,dwc3"; - reg = <0x12400000 0x10000>; - interrupts = <0 73 0>; - phys = <&usbdrd_phy1 0>, <&usbdrd_phy1 1>; - phy-names = "usb2-phy", "usb3-phy"; + nocp_g3d_1: nocp@11A51400 { + compatible = "samsung,exynos5420-nocp"; + reg = <0x11A51400 0x200>; + status = "disabled"; }; - }; - - usbdrd_phy1: phy@12500000 { - compatible = "samsung,exynos5420-usbdrd-phy"; - reg = <0x12500000 0x100>; - clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBPHY301>; - clock-names = "phy", "ref"; - samsung,pmu-syscon = <&pmu_system_controller>; - #phy-cells = <1>; - }; - usbhost2: usb@12110000 { - compatible = "samsung,exynos4210-ehci"; - reg = <0x12110000 0x100>; - interrupts = <0 71 0>; - - clocks = <&clock CLK_USBH20>; - clock-names = "usbhost"; - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - phys = <&usb2_phy 1>; + gsc_pd: power-domain@10044000 { + compatible = "samsung,exynos4210-pd"; + reg = <0x10044000 0x20>; + #power-domain-cells = <0>; + clocks = <&clock CLK_FIN_PLL>, + <&clock CLK_MOUT_USER_ACLK300_GSCL>, + <&clock CLK_GSCL0>, <&clock CLK_GSCL1>; + clock-names = "oscclk", "clk0", "asb0", "asb1"; }; - }; - - usbhost1: usb@12120000 { - compatible = "samsung,exynos4210-ohci"; - reg = <0x12120000 0x100>; - interrupts = <0 71 0>; - clocks = <&clock CLK_USBH20>; - clock-names = "usbhost"; - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - phys = <&usb2_phy 1>; + isp_pd: power-domain@10044020 { + compatible = "samsung,exynos4210-pd"; + reg = <0x10044020 0x20>; + #power-domain-cells = <0>; }; - }; - - usb2_phy: phy@12130000 { - compatible = "samsung,exynos5250-usb2-phy"; - reg = <0x12130000 0x100>; - clocks = <&clock CLK_USBH20>, <&clock CLK_SCLK_USBPHY300>; - clock-names = "phy", "ref"; - #phy-cells = <1>; - samsung,sysreg-phandle = <&sysreg_system_controller>; - samsung,pmureg-phandle = <&pmu_system_controller>; - }; - - sysmmu_g2dr: sysmmu@0x10A60000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x10A60000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <24 5>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>; - #iommu-cells = <0>; - }; - sysmmu_g2dw: sysmmu@0x10A70000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x10A70000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <22 2>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>; - #iommu-cells = <0>; - }; - - sysmmu_tv: sysmmu@0x14650000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x14650000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <7 4>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_MIXER>, <&clock CLK_MIXER>; - power-domains = <&disp_pd>; - #iommu-cells = <0>; - }; - - sysmmu_gscl0: sysmmu@0x13E80000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x13E80000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <2 0>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_GSCL0>, <&clock CLK_GSCL0>; - power-domains = <&gsc_pd>; - #iommu-cells = <0>; - }; - - sysmmu_gscl1: sysmmu@0x13E90000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x13E90000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <2 2>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_GSCL1>, <&clock CLK_GSCL1>; - power-domains = <&gsc_pd>; - #iommu-cells = <0>; - }; - - sysmmu_scaler0r: sysmmu@0x12880000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x12880000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <22 4>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_MSCL0>, <&clock CLK_MSCL0>; - #iommu-cells = <0>; - }; - - sysmmu_scaler1r: sysmmu@0x12890000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x12890000 0x1000>; - interrupts = <0 186 0>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_MSCL1>, <&clock CLK_MSCL1>; - #iommu-cells = <0>; - }; - - sysmmu_scaler2r: sysmmu@0x128A0000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x128A0000 0x1000>; - interrupts = <0 188 0>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_MSCL2>, <&clock CLK_MSCL2>; - #iommu-cells = <0>; - }; - - sysmmu_scaler0w: sysmmu@0x128C0000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x128C0000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <27 2>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_MSCL0>, <&clock CLK_MSCL0>; - #iommu-cells = <0>; - }; - - sysmmu_scaler1w: sysmmu@0x128D0000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x128D0000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <22 6>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_MSCL1>, <&clock CLK_MSCL1>; - #iommu-cells = <0>; - }; - - sysmmu_scaler2w: sysmmu@0x128E0000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x128E0000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <19 6>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_MSCL2>, <&clock CLK_MSCL2>; - #iommu-cells = <0>; - }; - - sysmmu_rotator: sysmmu@0x11D40000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x11D40000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <4 0>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_ROTATOR>, <&clock CLK_ROTATOR>; - #iommu-cells = <0>; - }; - - sysmmu_jpeg0: sysmmu@0x11F10000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x11F10000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <4 2>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>; - #iommu-cells = <0>; - }; - - sysmmu_jpeg1: sysmmu@0x11F20000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x11F20000 0x1000>; - interrupts = <0 169 0>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_JPEG2>, <&clock CLK_JPEG2>; - #iommu-cells = <0>; - }; - - sysmmu_mfc_l: sysmmu@0x11200000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x11200000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <6 2>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>; - power-domains = <&mfc_pd>; - #iommu-cells = <0>; - }; - - sysmmu_mfc_r: sysmmu@0x11210000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x11210000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <8 5>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>; - power-domains = <&mfc_pd>; - #iommu-cells = <0>; - }; - - sysmmu_fimd1_0: sysmmu@0x14640000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x14640000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <3 2>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_FIMD1M0>, <&clock CLK_FIMD1>; - power-domains = <&disp_pd>; - #iommu-cells = <0>; - }; - - sysmmu_fimd1_1: sysmmu@0x14680000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x14680000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <3 0>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_FIMD1M1>, <&clock CLK_FIMD1>; - power-domains = <&disp_pd>; - #iommu-cells = <0>; - }; - - bus_wcore: bus_wcore { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DOUT_ACLK400_WCORE>; - clock-names = "bus"; - operating-points-v2 = <&bus_wcore_opp_table>; - status = "disabled"; - }; - - bus_noc: bus_noc { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DOUT_ACLK100_NOC>; - clock-names = "bus"; - operating-points-v2 = <&bus_noc_opp_table>; - status = "disabled"; - }; - - bus_fsys_apb: bus_fsys_apb { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DOUT_PCLK200_FSYS>; - clock-names = "bus"; - operating-points-v2 = <&bus_fsys_apb_opp_table>; - status = "disabled"; - }; - - bus_fsys: bus_fsys { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DOUT_ACLK200_FSYS>; - clock-names = "bus"; - operating-points-v2 = <&bus_fsys_apb_opp_table>; - status = "disabled"; - }; - - bus_fsys2: bus_fsys2 { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DOUT_ACLK200_FSYS2>; - clock-names = "bus"; - operating-points-v2 = <&bus_fsys2_opp_table>; - status = "disabled"; - }; - - bus_mfc: bus_mfc { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DOUT_ACLK333>; - clock-names = "bus"; - operating-points-v2 = <&bus_mfc_opp_table>; - status = "disabled"; - }; - - bus_gen: bus_gen { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DOUT_ACLK266>; - clock-names = "bus"; - operating-points-v2 = <&bus_gen_opp_table>; - status = "disabled"; - }; - - bus_peri: bus_peri { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DOUT_ACLK66>; - clock-names = "bus"; - operating-points-v2 = <&bus_peri_opp_table>; - status = "disabled"; - }; - - bus_g2d: bus_g2d { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DOUT_ACLK333_G2D>; - clock-names = "bus"; - operating-points-v2 = <&bus_g2d_opp_table>; - status = "disabled"; - }; - - bus_g2d_acp: bus_g2d_acp { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DOUT_ACLK266_G2D>; - clock-names = "bus"; - operating-points-v2 = <&bus_g2d_acp_opp_table>; - status = "disabled"; - }; - - bus_jpeg: bus_jpeg { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DOUT_ACLK300_JPEG>; - clock-names = "bus"; - operating-points-v2 = <&bus_jpeg_opp_table>; - status = "disabled"; - }; - - bus_jpeg_apb: bus_jpeg_apb { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DOUT_ACLK166>; - clock-names = "bus"; - operating-points-v2 = <&bus_jpeg_apb_opp_table>; - status = "disabled"; - }; - - bus_disp1_fimd: bus_disp1_fimd { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DOUT_ACLK300_DISP1>; - clock-names = "bus"; - operating-points-v2 = <&bus_disp1_fimd_opp_table>; - status = "disabled"; - }; - - bus_disp1: bus_disp1 { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DOUT_ACLK400_DISP1>; - clock-names = "bus"; - operating-points-v2 = <&bus_disp1_opp_table>; - status = "disabled"; - }; - - bus_gscl_scaler: bus_gscl_scaler { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DOUT_ACLK300_GSCL>; - clock-names = "bus"; - operating-points-v2 = <&bus_gscl_opp_table>; - status = "disabled"; - }; - - bus_mscl: bus_mscl { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DOUT_ACLK400_MSCL>; - clock-names = "bus"; - operating-points-v2 = <&bus_mscl_opp_table>; - status = "disabled"; - }; - - bus_wcore_opp_table: opp_table2 { - compatible = "operating-points-v2"; - - opp00 { - opp-hz = /bits/ 64 <84000000>; - opp-microvolt = <925000>; - }; - opp01 { - opp-hz = /bits/ 64 <111000000>; - opp-microvolt = <950000>; + mfc_pd: power-domain@10044060 { + compatible = "samsung,exynos4210-pd"; + reg = <0x10044060 0x20>; + clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MOUT_USER_ACLK333>; + clock-names = "oscclk", "clk0"; + #power-domain-cells = <0>; }; - opp02 { - opp-hz = /bits/ 64 <222000000>; - opp-microvolt = <950000>; - }; - opp03 { - opp-hz = /bits/ 64 <333000000>; - opp-microvolt = <950000>; - }; - opp04 { - opp-hz = /bits/ 64 <400000000>; - opp-microvolt = <987500>; - }; - }; - - bus_noc_opp_table: opp_table3 { - compatible = "operating-points-v2"; - opp00 { - opp-hz = /bits/ 64 <67000000>; - }; - opp01 { - opp-hz = /bits/ 64 <75000000>; + msc_pd: power-domain@10044120 { + compatible = "samsung,exynos4210-pd"; + reg = <0x10044120 0x20>; + #power-domain-cells = <0>; }; - opp02 { - opp-hz = /bits/ 64 <86000000>; - }; - opp03 { - opp-hz = /bits/ 64 <100000000>; - }; - }; - bus_fsys_apb_opp_table: opp_table4 { - compatible = "operating-points-v2"; - opp-shared; - - opp00 { - opp-hz = /bits/ 64 <100000000>; - }; - opp01 { - opp-hz = /bits/ 64 <200000000>; + disp_pd: power-domain@100440C0 { + compatible = "samsung,exynos4210-pd"; + reg = <0x100440C0 0x20>; + #power-domain-cells = <0>; + clocks = <&clock CLK_FIN_PLL>, + <&clock CLK_MOUT_USER_ACLK200_DISP1>, + <&clock CLK_MOUT_USER_ACLK300_DISP1>, + <&clock CLK_MOUT_USER_ACLK400_DISP1>, + <&clock CLK_FIMD1>, <&clock CLK_MIXER>; + clock-names = "oscclk", "clk0", "clk1", "clk2", "asb0", "asb1"; }; - }; - bus_fsys2_opp_table: opp_table5 { - compatible = "operating-points-v2"; + pinctrl_0: pinctrl@13400000 { + compatible = "samsung,exynos5420-pinctrl"; + reg = <0x13400000 0x1000>; + interrupts = <0 45 0>; - opp00 { - opp-hz = /bits/ 64 <75000000>; - }; - opp01 { - opp-hz = /bits/ 64 <100000000>; - }; - opp02 { - opp-hz = /bits/ 64 <150000000>; + wakeup-interrupt-controller { + compatible = "samsung,exynos4210-wakeup-eint"; + interrupt-parent = <&gic>; + interrupts = <0 32 0>; + }; }; - }; - - bus_mfc_opp_table: opp_table6 { - compatible = "operating-points-v2"; - opp00 { - opp-hz = /bits/ 64 <96000000>; + pinctrl_1: pinctrl@13410000 { + compatible = "samsung,exynos5420-pinctrl"; + reg = <0x13410000 0x1000>; + interrupts = <0 78 0>; }; - opp01 { - opp-hz = /bits/ 64 <111000000>; + + pinctrl_2: pinctrl@14000000 { + compatible = "samsung,exynos5420-pinctrl"; + reg = <0x14000000 0x1000>; + interrupts = <0 46 0>; }; - opp02 { - opp-hz = /bits/ 64 <167000000>; + + pinctrl_3: pinctrl@14010000 { + compatible = "samsung,exynos5420-pinctrl"; + reg = <0x14010000 0x1000>; + interrupts = <0 50 0>; }; - opp03 { - opp-hz = /bits/ 64 <222000000>; + + pinctrl_4: pinctrl@03860000 { + compatible = "samsung,exynos5420-pinctrl"; + reg = <0x03860000 0x1000>; + interrupts = <0 47 0>; }; - opp04 { - opp-hz = /bits/ 64 <333000000>; + + amba { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + interrupt-parent = <&gic>; + ranges; + + adma: adma@03880000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x03880000 0x1000>; + interrupts = <0 110 0>; + clocks = <&clock_audss EXYNOS_ADMA>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + #dma-channels = <6>; + #dma-requests = <16>; + }; + + pdma0: pdma@121A0000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x121A0000 0x1000>; + interrupts = <0 34 0>; + clocks = <&clock CLK_PDMA0>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + #dma-channels = <8>; + #dma-requests = <32>; + }; + + pdma1: pdma@121B0000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x121B0000 0x1000>; + interrupts = <0 35 0>; + clocks = <&clock CLK_PDMA1>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + #dma-channels = <8>; + #dma-requests = <32>; + }; + + mdma0: mdma@10800000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x10800000 0x1000>; + interrupts = <0 33 0>; + clocks = <&clock CLK_MDMA0>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + #dma-channels = <8>; + #dma-requests = <1>; + }; + + mdma1: mdma@11C10000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x11C10000 0x1000>; + interrupts = <0 124 0>; + clocks = <&clock CLK_MDMA1>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + #dma-channels = <8>; + #dma-requests = <1>; + /* + * MDMA1 can support both secure and non-secure + * AXI transactions. When this is enabled in + * the kernel for boards that run in secure + * mode, we are getting imprecise external + * aborts causing the kernel to oops. + */ + status = "disabled"; + }; + }; + + i2s0: i2s@03830000 { + compatible = "samsung,exynos5420-i2s"; + reg = <0x03830000 0x100>; + dmas = <&adma 0 + &adma 2 + &adma 1>; + dma-names = "tx", "rx", "tx-sec"; + clocks = <&clock_audss EXYNOS_I2S_BUS>, + <&clock_audss EXYNOS_I2S_BUS>, + <&clock_audss EXYNOS_SCLK_I2S>; + clock-names = "iis", "i2s_opclk0", "i2s_opclk1"; + #clock-cells = <1>; + clock-output-names = "i2s_cdclk0"; + #sound-dai-cells = <1>; + samsung,idma-addr = <0x03000000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_bus>; + status = "disabled"; }; - }; - bus_gen_opp_table: opp_table7 { - compatible = "operating-points-v2"; + i2s1: i2s@12D60000 { + compatible = "samsung,exynos5420-i2s"; + reg = <0x12D60000 0x100>; + dmas = <&pdma1 12 + &pdma1 11>; + dma-names = "tx", "rx"; + clocks = <&clock CLK_I2S1>, <&clock CLK_SCLK_I2S1>; + clock-names = "iis", "i2s_opclk0"; + #clock-cells = <1>; + clock-output-names = "i2s_cdclk1"; + #sound-dai-cells = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1_bus>; + status = "disabled"; + }; - opp00 { - opp-hz = /bits/ 64 <89000000>; + i2s2: i2s@12D70000 { + compatible = "samsung,exynos5420-i2s"; + reg = <0x12D70000 0x100>; + dmas = <&pdma0 12 + &pdma0 11>; + dma-names = "tx", "rx"; + clocks = <&clock CLK_I2S2>, <&clock CLK_SCLK_I2S2>; + clock-names = "iis", "i2s_opclk0"; + #clock-cells = <1>; + clock-output-names = "i2s_cdclk2"; + #sound-dai-cells = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s2_bus>; + status = "disabled"; }; - opp01 { - opp-hz = /bits/ 64 <133000000>; + + spi_0: spi@12d20000 { + compatible = "samsung,exynos4210-spi"; + reg = <0x12d20000 0x100>; + interrupts = <0 68 0>; + dmas = <&pdma0 5 + &pdma0 4>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&spi0_bus>; + clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>; + clock-names = "spi", "spi_busclk0"; + status = "disabled"; }; - opp02 { - opp-hz = /bits/ 64 <178000000>; + + spi_1: spi@12d30000 { + compatible = "samsung,exynos4210-spi"; + reg = <0x12d30000 0x100>; + interrupts = <0 69 0>; + dmas = <&pdma1 5 + &pdma1 4>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&spi1_bus>; + clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>; + clock-names = "spi", "spi_busclk0"; + status = "disabled"; }; - opp03 { - opp-hz = /bits/ 64 <267000000>; + + spi_2: spi@12d40000 { + compatible = "samsung,exynos4210-spi"; + reg = <0x12d40000 0x100>; + interrupts = <0 70 0>; + dmas = <&pdma0 7 + &pdma0 6>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&spi2_bus>; + clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>; + clock-names = "spi", "spi_busclk0"; + status = "disabled"; }; - }; - bus_peri_opp_table: opp_table8 { - compatible = "operating-points-v2"; + dp_phy: dp-video-phy { + compatible = "samsung,exynos5420-dp-video-phy"; + samsung,pmu-syscon = <&pmu_system_controller>; + #phy-cells = <0>; + }; - opp00 { - opp-hz = /bits/ 64 <67000000>; + mipi_phy: mipi-video-phy { + compatible = "samsung,s5pv210-mipi-video-phy"; + syscon = <&pmu_system_controller>; + #phy-cells = <1>; }; - }; - bus_g2d_opp_table: opp_table9 { - compatible = "operating-points-v2"; + dsi@14500000 { + compatible = "samsung,exynos5410-mipi-dsi"; + reg = <0x14500000 0x10000>; + interrupts = <0 82 0>; + phys = <&mipi_phy 1>; + phy-names = "dsim"; + clocks = <&clock CLK_DSIM1>, <&clock CLK_SCLK_MIPI1>; + clock-names = "bus_clk", "pll_clk"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; - opp00 { - opp-hz = /bits/ 64 <84000000>; + adc: adc@12D10000 { + compatible = "samsung,exynos-adc-v2"; + reg = <0x12D10000 0x100>; + interrupts = <0 106 0>; + clocks = <&clock CLK_TSADC>; + clock-names = "adc"; + #io-channel-cells = <1>; + io-channel-ranges; + samsung,syscon-phandle = <&pmu_system_controller>; + status = "disabled"; }; - opp01 { - opp-hz = /bits/ 64 <167000000>; + + /* i2c_0-3 are defined in exynos5.dtsi */ + hsi2c_4: i2c@12CA0000 { + compatible = "samsung,exynos5250-hsi2c"; + reg = <0x12CA0000 0x1000>; + interrupts = <0 60 0>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_hs_bus>; + clocks = <&clock CLK_USI0>; + clock-names = "hsi2c"; + status = "disabled"; }; - opp02 { - opp-hz = /bits/ 64 <222000000>; + + hsi2c_5: i2c@12CB0000 { + compatible = "samsung,exynos5250-hsi2c"; + reg = <0x12CB0000 0x1000>; + interrupts = <0 61 0>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c5_hs_bus>; + clocks = <&clock CLK_USI1>; + clock-names = "hsi2c"; + status = "disabled"; }; - opp03 { - opp-hz = /bits/ 64 <300000000>; + + hsi2c_6: i2c@12CC0000 { + compatible = "samsung,exynos5250-hsi2c"; + reg = <0x12CC0000 0x1000>; + interrupts = <0 62 0>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c6_hs_bus>; + clocks = <&clock CLK_USI2>; + clock-names = "hsi2c"; + status = "disabled"; }; - opp04 { - opp-hz = /bits/ 64 <333000000>; + + hsi2c_7: i2c@12CD0000 { + compatible = "samsung,exynos5250-hsi2c"; + reg = <0x12CD0000 0x1000>; + interrupts = <0 63 0>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c7_hs_bus>; + clocks = <&clock CLK_USI3>; + clock-names = "hsi2c"; + status = "disabled"; }; - }; - bus_g2d_acp_opp_table: opp_table10 { - compatible = "operating-points-v2"; + hsi2c_8: i2c@12E00000 { + compatible = "samsung,exynos5250-hsi2c"; + reg = <0x12E00000 0x1000>; + interrupts = <0 87 0>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c8_hs_bus>; + clocks = <&clock CLK_USI4>; + clock-names = "hsi2c"; + status = "disabled"; + }; - opp00 { - opp-hz = /bits/ 64 <67000000>; + hsi2c_9: i2c@12E10000 { + compatible = "samsung,exynos5250-hsi2c"; + reg = <0x12E10000 0x1000>; + interrupts = <0 88 0>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c9_hs_bus>; + clocks = <&clock CLK_USI5>; + clock-names = "hsi2c"; + status = "disabled"; }; - opp01 { - opp-hz = /bits/ 64 <133000000>; + + hsi2c_10: i2c@12E20000 { + compatible = "samsung,exynos5250-hsi2c"; + reg = <0x12E20000 0x1000>; + interrupts = <0 203 0>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c10_hs_bus>; + clocks = <&clock CLK_USI6>; + clock-names = "hsi2c"; + status = "disabled"; }; - opp02 { - opp-hz = /bits/ 64 <178000000>; + + hdmi: hdmi@14530000 { + compatible = "samsung,exynos5420-hdmi"; + reg = <0x14530000 0x70000>; + interrupts = <0 95 0>; + clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>, + <&clock CLK_DOUT_PIXEL>, <&clock CLK_SCLK_HDMIPHY>, + <&clock CLK_MOUT_HDMI>; + clock-names = "hdmi", "sclk_hdmi", "sclk_pixel", + "sclk_hdmiphy", "mout_hdmi"; + phy = <&hdmiphy>; + samsung,syscon-phandle = <&pmu_system_controller>; + status = "disabled"; + power-domains = <&disp_pd>; + }; + + hdmiphy: hdmiphy@145D0000 { + reg = <0x145D0000 0x20>; + }; + + mixer: mixer@14450000 { + compatible = "samsung,exynos5420-mixer"; + reg = <0x14450000 0x10000>; + interrupts = <0 94 0>; + clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>, + <&clock CLK_SCLK_HDMI>; + clock-names = "mixer", "hdmi", "sclk_hdmi"; + power-domains = <&disp_pd>; + iommus = <&sysmmu_tv>; + }; + + rotator: rotator@11C00000 { + compatible = "samsung,exynos5250-rotator"; + reg = <0x11C00000 0x64>; + interrupts = <0 84 0>; + clocks = <&clock CLK_ROTATOR>; + clock-names = "rotator"; + iommus = <&sysmmu_rotator>; + }; + + gsc_0: video-scaler@13e00000 { + compatible = "samsung,exynos5-gsc"; + reg = <0x13e00000 0x1000>; + interrupts = <0 85 0>; + clocks = <&clock CLK_GSCL0>; + clock-names = "gscl"; + power-domains = <&gsc_pd>; + iommus = <&sysmmu_gscl0>; + }; + + gsc_1: video-scaler@13e10000 { + compatible = "samsung,exynos5-gsc"; + reg = <0x13e10000 0x1000>; + interrupts = <0 86 0>; + clocks = <&clock CLK_GSCL1>; + clock-names = "gscl"; + power-domains = <&gsc_pd>; + iommus = <&sysmmu_gscl1>; + }; + + jpeg_0: jpeg@11F50000 { + compatible = "samsung,exynos5420-jpeg"; + reg = <0x11F50000 0x1000>; + interrupts = <0 89 0>; + clock-names = "jpeg"; + clocks = <&clock CLK_JPEG>; + iommus = <&sysmmu_jpeg0>; + }; + + jpeg_1: jpeg@11F60000 { + compatible = "samsung,exynos5420-jpeg"; + reg = <0x11F60000 0x1000>; + interrupts = <0 168 0>; + clock-names = "jpeg"; + clocks = <&clock CLK_JPEG2>; + iommus = <&sysmmu_jpeg1>; + }; + + pmu_system_controller: system-controller@10040000 { + compatible = "samsung,exynos5420-pmu", "syscon"; + reg = <0x10040000 0x5000>; + clock-names = "clkout16"; + clocks = <&clock CLK_FIN_PLL>; + #clock-cells = <1>; + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; }; - opp03 { - opp-hz = /bits/ 64 <267000000>; + + tmu_cpu0: tmu@10060000 { + compatible = "samsung,exynos5420-tmu"; + reg = <0x10060000 0x100>; + interrupts = <0 65 0>; + clocks = <&clock CLK_TMU>; + clock-names = "tmu_apbif"; + #include "exynos4412-tmu-sensor-conf.dtsi" + }; + + tmu_cpu1: tmu@10064000 { + compatible = "samsung,exynos5420-tmu"; + reg = <0x10064000 0x100>; + interrupts = <0 183 0>; + clocks = <&clock CLK_TMU>; + clock-names = "tmu_apbif"; + #include "exynos4412-tmu-sensor-conf.dtsi" + }; + + tmu_cpu2: tmu@10068000 { + compatible = "samsung,exynos5420-tmu-ext-triminfo"; + reg = <0x10068000 0x100>, <0x1006c000 0x4>; + interrupts = <0 184 0>; + clocks = <&clock CLK_TMU>, <&clock CLK_TMU>; + clock-names = "tmu_apbif", "tmu_triminfo_apbif"; + #include "exynos4412-tmu-sensor-conf.dtsi" + }; + + tmu_cpu3: tmu@1006c000 { + compatible = "samsung,exynos5420-tmu-ext-triminfo"; + reg = <0x1006c000 0x100>, <0x100a0000 0x4>; + interrupts = <0 185 0>; + clocks = <&clock CLK_TMU>, <&clock CLK_TMU_GPU>; + clock-names = "tmu_apbif", "tmu_triminfo_apbif"; + #include "exynos4412-tmu-sensor-conf.dtsi" + }; + + tmu_gpu: tmu@100a0000 { + compatible = "samsung,exynos5420-tmu-ext-triminfo"; + reg = <0x100a0000 0x100>, <0x10068000 0x4>; + interrupts = <0 215 0>; + clocks = <&clock CLK_TMU_GPU>, <&clock CLK_TMU>; + clock-names = "tmu_apbif", "tmu_triminfo_apbif"; + #include "exynos4412-tmu-sensor-conf.dtsi" + }; + + watchdog: watchdog@101D0000 { + compatible = "samsung,exynos5420-wdt"; + reg = <0x101D0000 0x100>; + interrupts = <0 42 0>; + clocks = <&clock CLK_WDT>; + clock-names = "watchdog"; + samsung,syscon-phandle = <&pmu_system_controller>; + }; + + sss: sss@10830000 { + compatible = "samsung,exynos4210-secss"; + reg = <0x10830000 0x300>; + interrupts = <0 112 0>; + clocks = <&clock CLK_SSS>; + clock-names = "secss"; + }; + + usbdrd3_0: usb3-0 { + compatible = "samsung,exynos5250-dwusb3"; + clocks = <&clock CLK_USBD300>; + clock-names = "usbdrd30"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + usbdrd_dwc3_0: dwc3@12000000 { + compatible = "snps,dwc3"; + reg = <0x12000000 0x10000>; + interrupts = <0 72 0>; + phys = <&usbdrd_phy0 0>, <&usbdrd_phy0 1>; + phy-names = "usb2-phy", "usb3-phy"; + }; + }; + + usbdrd_phy0: phy@12100000 { + compatible = "samsung,exynos5420-usbdrd-phy"; + reg = <0x12100000 0x100>; + clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>; + clock-names = "phy", "ref"; + samsung,pmu-syscon = <&pmu_system_controller>; + #phy-cells = <1>; + }; + + usbdrd3_1: usb3-1 { + compatible = "samsung,exynos5250-dwusb3"; + clocks = <&clock CLK_USBD301>; + clock-names = "usbdrd30"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + usbdrd_dwc3_1: dwc3@12400000 { + compatible = "snps,dwc3"; + reg = <0x12400000 0x10000>; + interrupts = <0 73 0>; + phys = <&usbdrd_phy1 0>, <&usbdrd_phy1 1>; + phy-names = "usb2-phy", "usb3-phy"; + }; + }; + + usbdrd_phy1: phy@12500000 { + compatible = "samsung,exynos5420-usbdrd-phy"; + reg = <0x12500000 0x100>; + clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBPHY301>; + clock-names = "phy", "ref"; + samsung,pmu-syscon = <&pmu_system_controller>; + #phy-cells = <1>; + }; + + usbhost2: usb@12110000 { + compatible = "samsung,exynos4210-ehci"; + reg = <0x12110000 0x100>; + interrupts = <0 71 0>; + + clocks = <&clock CLK_USBH20>; + clock-names = "usbhost"; + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + phys = <&usb2_phy 1>; + }; }; - }; - bus_jpeg_opp_table: opp_table11 { - compatible = "operating-points-v2"; + usbhost1: usb@12120000 { + compatible = "samsung,exynos4210-ohci"; + reg = <0x12120000 0x100>; + interrupts = <0 71 0>; - opp00 { - opp-hz = /bits/ 64 <75000000>; - }; - opp01 { - opp-hz = /bits/ 64 <150000000>; - }; - opp02 { - opp-hz = /bits/ 64 <200000000>; - }; - opp03 { - opp-hz = /bits/ 64 <300000000>; + clocks = <&clock CLK_USBH20>; + clock-names = "usbhost"; + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + phys = <&usb2_phy 1>; + }; + }; + + usb2_phy: phy@12130000 { + compatible = "samsung,exynos5250-usb2-phy"; + reg = <0x12130000 0x100>; + clocks = <&clock CLK_USBH20>, <&clock CLK_SCLK_USBPHY300>; + clock-names = "phy", "ref"; + #phy-cells = <1>; + samsung,sysreg-phandle = <&sysreg_system_controller>; + samsung,pmureg-phandle = <&pmu_system_controller>; + }; + + sysmmu_g2dr: sysmmu@0x10A60000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x10A60000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <24 5>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>; + #iommu-cells = <0>; + }; + + sysmmu_g2dw: sysmmu@0x10A70000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x10A70000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <22 2>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>; + #iommu-cells = <0>; + }; + + sysmmu_tv: sysmmu@0x14650000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x14650000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <7 4>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_MIXER>, <&clock CLK_MIXER>; + power-domains = <&disp_pd>; + #iommu-cells = <0>; + }; + + sysmmu_gscl0: sysmmu@0x13E80000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x13E80000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <2 0>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_GSCL0>, <&clock CLK_GSCL0>; + power-domains = <&gsc_pd>; + #iommu-cells = <0>; + }; + + sysmmu_gscl1: sysmmu@0x13E90000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x13E90000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <2 2>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_GSCL1>, <&clock CLK_GSCL1>; + power-domains = <&gsc_pd>; + #iommu-cells = <0>; + }; + + sysmmu_scaler0r: sysmmu@0x12880000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x12880000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <22 4>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_MSCL0>, <&clock CLK_MSCL0>; + #iommu-cells = <0>; + }; + + sysmmu_scaler1r: sysmmu@0x12890000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x12890000 0x1000>; + interrupts = <0 186 0>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_MSCL1>, <&clock CLK_MSCL1>; + #iommu-cells = <0>; + }; + + sysmmu_scaler2r: sysmmu@0x128A0000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x128A0000 0x1000>; + interrupts = <0 188 0>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_MSCL2>, <&clock CLK_MSCL2>; + #iommu-cells = <0>; + }; + + sysmmu_scaler0w: sysmmu@0x128C0000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x128C0000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <27 2>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_MSCL0>, <&clock CLK_MSCL0>; + #iommu-cells = <0>; + }; + + sysmmu_scaler1w: sysmmu@0x128D0000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x128D0000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <22 6>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_MSCL1>, <&clock CLK_MSCL1>; + #iommu-cells = <0>; + }; + + sysmmu_scaler2w: sysmmu@0x128E0000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x128E0000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <19 6>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_MSCL2>, <&clock CLK_MSCL2>; + #iommu-cells = <0>; + }; + + sysmmu_rotator: sysmmu@0x11D40000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x11D40000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <4 0>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_ROTATOR>, <&clock CLK_ROTATOR>; + #iommu-cells = <0>; + }; + + sysmmu_jpeg0: sysmmu@0x11F10000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x11F10000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <4 2>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>; + #iommu-cells = <0>; + }; + + sysmmu_jpeg1: sysmmu@0x11F20000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x11F20000 0x1000>; + interrupts = <0 169 0>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_JPEG2>, <&clock CLK_JPEG2>; + #iommu-cells = <0>; + }; + + sysmmu_mfc_l: sysmmu@0x11200000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x11200000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <6 2>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>; + power-domains = <&mfc_pd>; + #iommu-cells = <0>; + }; + + sysmmu_mfc_r: sysmmu@0x11210000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x11210000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <8 5>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>; + power-domains = <&mfc_pd>; + #iommu-cells = <0>; + }; + + sysmmu_fimd1_0: sysmmu@0x14640000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x14640000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <3 2>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_FIMD1M0>, <&clock CLK_FIMD1>; + power-domains = <&disp_pd>; + #iommu-cells = <0>; + }; + + sysmmu_fimd1_1: sysmmu@0x14680000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x14680000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <3 0>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_FIMD1M1>, <&clock CLK_FIMD1>; + power-domains = <&disp_pd>; + #iommu-cells = <0>; + }; + + bus_wcore: bus_wcore { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DOUT_ACLK400_WCORE>; + clock-names = "bus"; + operating-points-v2 = <&bus_wcore_opp_table>; + status = "disabled"; }; - }; - bus_jpeg_apb_opp_table: opp_table12 { - compatible = "operating-points-v2"; + bus_noc: bus_noc { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DOUT_ACLK100_NOC>; + clock-names = "bus"; + operating-points-v2 = <&bus_noc_opp_table>; + status = "disabled"; + }; - opp00 { - opp-hz = /bits/ 64 <84000000>; + bus_fsys_apb: bus_fsys_apb { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DOUT_PCLK200_FSYS>; + clock-names = "bus"; + operating-points-v2 = <&bus_fsys_apb_opp_table>; + status = "disabled"; }; - opp01 { - opp-hz = /bits/ 64 <111000000>; + + bus_fsys: bus_fsys { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DOUT_ACLK200_FSYS>; + clock-names = "bus"; + operating-points-v2 = <&bus_fsys_apb_opp_table>; + status = "disabled"; }; - opp02 { - opp-hz = /bits/ 64 <134000000>; + + bus_fsys2: bus_fsys2 { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DOUT_ACLK200_FSYS2>; + clock-names = "bus"; + operating-points-v2 = <&bus_fsys2_opp_table>; + status = "disabled"; }; - opp03 { - opp-hz = /bits/ 64 <167000000>; + + bus_mfc: bus_mfc { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DOUT_ACLK333>; + clock-names = "bus"; + operating-points-v2 = <&bus_mfc_opp_table>; + status = "disabled"; }; - }; - bus_disp1_fimd_opp_table: opp_table13 { - compatible = "operating-points-v2"; + bus_gen: bus_gen { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DOUT_ACLK266>; + clock-names = "bus"; + operating-points-v2 = <&bus_gen_opp_table>; + status = "disabled"; + }; - opp00 { - opp-hz = /bits/ 64 <120000000>; + bus_peri: bus_peri { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DOUT_ACLK66>; + clock-names = "bus"; + operating-points-v2 = <&bus_peri_opp_table>; + status = "disabled"; }; - opp01 { - opp-hz = /bits/ 64 <200000000>; + + bus_g2d: bus_g2d { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DOUT_ACLK333_G2D>; + clock-names = "bus"; + operating-points-v2 = <&bus_g2d_opp_table>; + status = "disabled"; }; - }; - bus_disp1_opp_table: opp_table14 { - compatible = "operating-points-v2"; + bus_g2d_acp: bus_g2d_acp { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DOUT_ACLK266_G2D>; + clock-names = "bus"; + operating-points-v2 = <&bus_g2d_acp_opp_table>; + status = "disabled"; + }; - opp00 { - opp-hz = /bits/ 64 <120000000>; + bus_jpeg: bus_jpeg { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DOUT_ACLK300_JPEG>; + clock-names = "bus"; + operating-points-v2 = <&bus_jpeg_opp_table>; + status = "disabled"; }; - opp01 { - opp-hz = /bits/ 64 <200000000>; + + bus_jpeg_apb: bus_jpeg_apb { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DOUT_ACLK166>; + clock-names = "bus"; + operating-points-v2 = <&bus_jpeg_apb_opp_table>; + status = "disabled"; }; - opp02 { - opp-hz = /bits/ 64 <300000000>; + + bus_disp1_fimd: bus_disp1_fimd { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DOUT_ACLK300_DISP1>; + clock-names = "bus"; + operating-points-v2 = <&bus_disp1_fimd_opp_table>; + status = "disabled"; }; - }; - bus_gscl_opp_table: opp_table15 { - compatible = "operating-points-v2"; + bus_disp1: bus_disp1 { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DOUT_ACLK400_DISP1>; + clock-names = "bus"; + operating-points-v2 = <&bus_disp1_opp_table>; + status = "disabled"; + }; - opp00 { - opp-hz = /bits/ 64 <150000000>; + bus_gscl_scaler: bus_gscl_scaler { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DOUT_ACLK300_GSCL>; + clock-names = "bus"; + operating-points-v2 = <&bus_gscl_opp_table>; + status = "disabled"; }; - opp01 { - opp-hz = /bits/ 64 <200000000>; + + bus_mscl: bus_mscl { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DOUT_ACLK400_MSCL>; + clock-names = "bus"; + operating-points-v2 = <&bus_mscl_opp_table>; + status = "disabled"; }; - opp02 { - opp-hz = /bits/ 64 <300000000>; + + bus_wcore_opp_table: opp_table2 { + compatible = "operating-points-v2"; + + opp00 { + opp-hz = /bits/ 64 <84000000>; + opp-microvolt = <925000>; + }; + opp01 { + opp-hz = /bits/ 64 <111000000>; + opp-microvolt = <950000>; + }; + opp02 { + opp-hz = /bits/ 64 <222000000>; + opp-microvolt = <950000>; + }; + opp03 { + opp-hz = /bits/ 64 <333000000>; + opp-microvolt = <950000>; + }; + opp04 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <987500>; + }; + }; + + bus_noc_opp_table: opp_table3 { + compatible = "operating-points-v2"; + + opp00 { + opp-hz = /bits/ 64 <67000000>; + }; + opp01 { + opp-hz = /bits/ 64 <75000000>; + }; + opp02 { + opp-hz = /bits/ 64 <86000000>; + }; + opp03 { + opp-hz = /bits/ 64 <100000000>; + }; + }; + + bus_fsys_apb_opp_table: opp_table4 { + compatible = "operating-points-v2"; + opp-shared; + + opp00 { + opp-hz = /bits/ 64 <100000000>; + }; + opp01 { + opp-hz = /bits/ 64 <200000000>; + }; + }; + + bus_fsys2_opp_table: opp_table5 { + compatible = "operating-points-v2"; + + opp00 { + opp-hz = /bits/ 64 <75000000>; + }; + opp01 { + opp-hz = /bits/ 64 <100000000>; + }; + opp02 { + opp-hz = /bits/ 64 <150000000>; + }; + }; + + bus_mfc_opp_table: opp_table6 { + compatible = "operating-points-v2"; + + opp00 { + opp-hz = /bits/ 64 <96000000>; + }; + opp01 { + opp-hz = /bits/ 64 <111000000>; + }; + opp02 { + opp-hz = /bits/ 64 <167000000>; + }; + opp03 { + opp-hz = /bits/ 64 <222000000>; + }; + opp04 { + opp-hz = /bits/ 64 <333000000>; + }; + }; + + bus_gen_opp_table: opp_table7 { + compatible = "operating-points-v2"; + + opp00 { + opp-hz = /bits/ 64 <89000000>; + }; + opp01 { + opp-hz = /bits/ 64 <133000000>; + }; + opp02 { + opp-hz = /bits/ 64 <178000000>; + }; + opp03 { + opp-hz = /bits/ 64 <267000000>; + }; + }; + + bus_peri_opp_table: opp_table8 { + compatible = "operating-points-v2"; + + opp00 { + opp-hz = /bits/ 64 <67000000>; + }; + }; + + bus_g2d_opp_table: opp_table9 { + compatible = "operating-points-v2"; + + opp00 { + opp-hz = /bits/ 64 <84000000>; + }; + opp01 { + opp-hz = /bits/ 64 <167000000>; + }; + opp02 { + opp-hz = /bits/ 64 <222000000>; + }; + opp03 { + opp-hz = /bits/ 64 <300000000>; + }; + opp04 { + opp-hz = /bits/ 64 <333000000>; + }; + }; + + bus_g2d_acp_opp_table: opp_table10 { + compatible = "operating-points-v2"; + + opp00 { + opp-hz = /bits/ 64 <67000000>; + }; + opp01 { + opp-hz = /bits/ 64 <133000000>; + }; + opp02 { + opp-hz = /bits/ 64 <178000000>; + }; + opp03 { + opp-hz = /bits/ 64 <267000000>; + }; + }; + + bus_jpeg_opp_table: opp_table11 { + compatible = "operating-points-v2"; + + opp00 { + opp-hz = /bits/ 64 <75000000>; + }; + opp01 { + opp-hz = /bits/ 64 <150000000>; + }; + opp02 { + opp-hz = /bits/ 64 <200000000>; + }; + opp03 { + opp-hz = /bits/ 64 <300000000>; + }; + }; + + bus_jpeg_apb_opp_table: opp_table12 { + compatible = "operating-points-v2"; + + opp00 { + opp-hz = /bits/ 64 <84000000>; + }; + opp01 { + opp-hz = /bits/ 64 <111000000>; + }; + opp02 { + opp-hz = /bits/ 64 <134000000>; + }; + opp03 { + opp-hz = /bits/ 64 <167000000>; + }; + }; + + bus_disp1_fimd_opp_table: opp_table13 { + compatible = "operating-points-v2"; + + opp00 { + opp-hz = /bits/ 64 <120000000>; + }; + opp01 { + opp-hz = /bits/ 64 <200000000>; + }; + }; + + bus_disp1_opp_table: opp_table14 { + compatible = "operating-points-v2"; + + opp00 { + opp-hz = /bits/ 64 <120000000>; + }; + opp01 { + opp-hz = /bits/ 64 <200000000>; + }; + opp02 { + opp-hz = /bits/ 64 <300000000>; + }; + }; + + bus_gscl_opp_table: opp_table15 { + compatible = "operating-points-v2"; + + opp00 { + opp-hz = /bits/ 64 <150000000>; + }; + opp01 { + opp-hz = /bits/ 64 <200000000>; + }; + opp02 { + opp-hz = /bits/ 64 <300000000>; + }; + }; + + bus_mscl_opp_table: opp_table16 { + compatible = "operating-points-v2"; + + opp00 { + opp-hz = /bits/ 64 <84000000>; + }; + opp01 { + opp-hz = /bits/ 64 <167000000>; + }; + opp02 { + opp-hz = /bits/ 64 <222000000>; + }; + opp03 { + opp-hz = /bits/ 64 <333000000>; + }; + opp04 { + opp-hz = /bits/ 64 <400000000>; + }; }; }; - bus_mscl_opp_table: opp_table16 { - compatible = "operating-points-v2"; - - opp00 { - opp-hz = /bits/ 64 <84000000>; + thermal-zones { + cpu0_thermal: cpu0-thermal { + thermal-sensors = <&tmu_cpu0>; + #include "exynos5420-trip-points.dtsi" }; - opp01 { - opp-hz = /bits/ 64 <167000000>; + cpu1_thermal: cpu1-thermal { + thermal-sensors = <&tmu_cpu1>; + #include "exynos5420-trip-points.dtsi" }; - opp02 { - opp-hz = /bits/ 64 <222000000>; + cpu2_thermal: cpu2-thermal { + thermal-sensors = <&tmu_cpu2>; + #include "exynos5420-trip-points.dtsi" }; - opp03 { - opp-hz = /bits/ 64 <333000000>; + cpu3_thermal: cpu3-thermal { + thermal-sensors = <&tmu_cpu3>; + #include "exynos5420-trip-points.dtsi" }; - opp04 { - opp-hz = /bits/ 64 <400000000>; + gpu_thermal: gpu-thermal { + thermal-sensors = <&tmu_gpu>; + #include "exynos5420-trip-points.dtsi" }; }; }; -- cgit v0.10.2 From 88ad58baf0d652a095b3255430ab7c10bea1b642 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 3 May 2016 14:53:22 +0200 Subject: ARM: dts: exynos: Include common exynos5 in exynos5410.dtsi The exynos5.dtsi is used for common nodes shared between Exynos5250 and Exynos542x. Since Exynos5410 is very similar to Exynos5420 it can include the common file as well to remove duplication and make everything more consistent. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Javier Martinez Canillas diff --git a/arch/arm/boot/dts/exynos5410-smdk5410.dts b/arch/arm/boot/dts/exynos5410-smdk5410.dts index 0f6429e..777fcf2 100644 --- a/arch/arm/boot/dts/exynos5410-smdk5410.dts +++ b/arch/arm/boot/dts/exynos5410-smdk5410.dts @@ -102,14 +102,14 @@ }; }; -&uart0 { +&serial_0 { status = "okay"; }; -&uart1 { +&serial_1 { status = "okay"; }; -&uart2 { +&serial_2 { status = "okay"; }; diff --git a/arch/arm/boot/dts/exynos5410.dtsi b/arch/arm/boot/dts/exynos5410.dtsi index ef60a06..0d555c5 100644 --- a/arch/arm/boot/dts/exynos5410.dtsi +++ b/arch/arm/boot/dts/exynos5410.dtsi @@ -14,6 +14,7 @@ */ #include "skeleton.dtsi" +#include "exynos5.dtsi" #include "exynos-syscon-restart.dtsi" #include @@ -26,9 +27,6 @@ pinctrl1 = &pinctrl_1; pinctrl2 = &pinctrl_2; pinctrl3 = &pinctrl_3; - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; }; cpus { @@ -70,49 +68,6 @@ #size-cells = <1>; ranges; - combiner: interrupt-controller@10440000 { - compatible = "samsung,exynos4210-combiner"; - #interrupt-cells = <2>; - interrupt-controller; - samsung,combiner-nr = <32>; - reg = <0x10440000 0x1000>; - interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>, - <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>, - <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>, - <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>, - <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>, - <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>, - <0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>, - <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>; - }; - - gic: interrupt-controller@10481000 { - compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x10481000 0x1000>, - <0x10482000 0x1000>, - <0x10484000 0x2000>, - <0x10486000 0x2000>; - interrupts = <1 9 0xf04>; - }; - - chipid@10000000 { - compatible = "samsung,exynos4210-chipid"; - reg = <0x10000000 0x100>; - }; - - sromc: memory-controller@12250000 { - compatible = "samsung,exynos4210-srom"; - reg = <0x12250000 0x14>; - #address-cells = <2>; - #size-cells = <1>; - ranges = <0 0 0x04000000 0x20000 - 1 0 0x05000000 0x20000 - 2 0 0x06000000 0x20000 - 3 0 0x07000000 0x20000>; - }; - pmu_system_controller: system-controller@10040000 { compatible = "samsung,exynos5410-pmu", "syscon"; reg = <0x10040000 0x5000>; @@ -239,34 +194,40 @@ reg = <0x03860000 0x1000>; interrupts = <0 47 0>; }; + }; +}; - uart0: serial@12C00000 { - compatible = "samsung,exynos4210-uart"; - reg = <0x12C00000 0x100>; - interrupts = <0 51 0>; - clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>; - clock-names = "uart", "clk_uart_baud0"; - status = "disabled"; - }; +&pwm { + clocks = <&clock CLK_PWM>; + clock-names = "timers"; +}; - uart1: serial@12C10000 { - compatible = "samsung,exynos4210-uart"; - reg = <0x12C10000 0x100>; - interrupts = <0 52 0>; - clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>; - clock-names = "uart", "clk_uart_baud0"; - status = "disabled"; - }; +&serial_0 { + clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>; + clock-names = "uart", "clk_uart_baud0"; +}; - uart2: serial@12C20000 { - compatible = "samsung,exynos4210-uart"; - reg = <0x12C20000 0x100>; - interrupts = <0 53 0>; - clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>; - clock-names = "uart", "clk_uart_baud0"; - status = "disabled"; - }; - }; +&serial_1 { + clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>; + clock-names = "uart", "clk_uart_baud0"; +}; + +&serial_2 { + clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>; + clock-names = "uart", "clk_uart_baud0"; +}; + +&serial_3 { + status = "disabled"; +}; + +&sromc { + #address-cells = <2>; + #size-cells = <1>; + ranges = <0 0 0x04000000 0x20000 + 1 0 0x05000000 0x20000 + 2 0 0x06000000 0x20000 + 3 0 0x07000000 0x20000>; }; #include "exynos5410-pinctrl.dtsi" -- cgit v0.10.2 From 594127ada6df68306ad5b0307d1e01ffbfe98671 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 3 May 2016 19:37:19 +0200 Subject: ARM: dts: exynos: Enable UART3 on Exynos5410 Just like other Exynos5 family SoCs, this one has four UARTs. Configure clocks for UART3 and enable it. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Javier Martinez Canillas diff --git a/arch/arm/boot/dts/exynos5410.dtsi b/arch/arm/boot/dts/exynos5410.dtsi index 0d555c5..a81a034 100644 --- a/arch/arm/boot/dts/exynos5410.dtsi +++ b/arch/arm/boot/dts/exynos5410.dtsi @@ -218,7 +218,8 @@ }; &serial_3 { - status = "disabled"; + clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>; + clock-names = "uart", "clk_uart_baud0"; }; &sromc { -- cgit v0.10.2 From 3f2f95ff6aa3490ae57364424b59b80cbff6be29 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 8 May 2016 18:41:57 +0200 Subject: ARM: dts: exynos: MCT is not an interrupt controller and extend length of iomap Multi-Core Timer generates interrupts but it is not really an interrupt controller so remove the "interrupt-controller" and "interrupt-cells" properties. Additionally extend the length of mapped memory to cover all registers (last SFR is at 0x0A40). Signed-off-by: Krzysztof Kozlowski Reviewed-by: Javier Martinez Canillas Tested-by: Javier Martinez Canillas diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index b65bdbe..fa8bda8 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -263,9 +263,7 @@ mct: mct@101C0000 { compatible = "samsung,exynos4210-mct"; - reg = <0x101C0000 0x800>; - interrupt-controller; - #interrupt-cells = <1>; + reg = <0x101C0000 0xB00>; interrupt-parent = <&mct_map>; interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>, <8>, <9>, <10>, <11>; -- cgit v0.10.2 From c9cf996d854b8f96d450083d3e0aace457a5a46b Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 8 May 2016 18:41:57 +0200 Subject: ARM: dts: exynos: Move common Exynos5410/542x/5800 nodes to new DTSI The Exynos5410/542x/5800 are very similar designs. Create a new DTSI with common nodes to remove DTS duplication. Although currently only MCT and SysRAM are shared but in future more nodes will be added to the common file. The patch should not have functional impact. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Javier Martinez Canillas Tested-by: Javier Martinez Canillas diff --git a/arch/arm/boot/dts/exynos5410.dtsi b/arch/arm/boot/dts/exynos5410.dtsi index a81a034..1354b5b 100644 --- a/arch/arm/boot/dts/exynos5410.dtsi +++ b/arch/arm/boot/dts/exynos5410.dtsi @@ -13,8 +13,7 @@ * published by the Free Software Foundation. */ -#include "skeleton.dtsi" -#include "exynos5.dtsi" +#include "exynos54xx.dtsi" #include "exynos-syscon-restart.dtsi" #include @@ -76,53 +75,6 @@ #clock-cells = <1>; }; - mct: mct@101C0000 { - compatible = "samsung,exynos4210-mct"; - reg = <0x101C0000 0xB00>; - interrupt-parent = <&interrupt_map>; - interrupts = <0>, <1>, <2>, <3>, - <4>, <5>, <6>, <7>, - <8>, <9>, <10>, <11>; - clocks = <&fin_pll>, <&clock CLK_MCT>; - clock-names = "fin_pll", "mct"; - - interrupt_map: interrupt-map { - #interrupt-cells = <1>; - #address-cells = <0>; - #size-cells = <0>; - interrupt-map = <0 &combiner 23 3>, - <1 &combiner 23 4>, - <2 &combiner 25 2>, - <3 &combiner 25 3>, - <4 &gic 0 120 0>, - <5 &gic 0 121 0>, - <6 &gic 0 122 0>, - <7 &gic 0 123 0>, - <8 &gic 0 128 0>, - <9 &gic 0 129 0>, - <10 &gic 0 130 0>, - <11 &gic 0 131 0>; - }; - }; - - sysram@02020000 { - compatible = "mmio-sram"; - reg = <0x02020000 0x54000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x02020000 0x54000>; - - smp-sysram@0 { - compatible = "samsung,exynos4210-sysram"; - reg = <0x0 0x1000>; - }; - - smp-sysram@53000 { - compatible = "samsung,exynos4210-sysram-ns"; - reg = <0x53000 0x1000>; - }; - }; - clock: clock-controller@10010000 { compatible = "samsung,exynos5410-clock"; reg = <0x10010000 0x30000>; @@ -197,6 +149,11 @@ }; }; +&mct { + clocks = <&fin_pll>, <&clock CLK_MCT>; + clock-names = "fin_pll", "mct"; +}; + &pwm { clocks = <&clock CLK_PWM>; clock-names = "timers"; diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index fa8bda8..2d9f43b 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -13,9 +13,8 @@ * published by the Free Software Foundation. */ +#include "exynos54xx.dtsi" #include -#include "exynos5.dtsi" - #include / { @@ -181,24 +180,6 @@ }; }; - sysram@02020000 { - compatible = "mmio-sram"; - reg = <0x02020000 0x54000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x02020000 0x54000>; - - smp-sysram@0 { - compatible = "samsung,exynos4210-sysram"; - reg = <0x0 0x1000>; - }; - - smp-sysram@53000 { - compatible = "samsung,exynos4210-sysram-ns"; - reg = <0x53000 0x1000>; - }; - }; - clock: clock-controller@10010000 { compatible = "samsung,exynos5420-clock"; reg = <0x10010000 0x30000>; @@ -261,34 +242,6 @@ status = "disabled"; }; - mct: mct@101C0000 { - compatible = "samsung,exynos4210-mct"; - reg = <0x101C0000 0xB00>; - interrupt-parent = <&mct_map>; - interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>, - <8>, <9>, <10>, <11>; - clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>; - clock-names = "fin_pll", "mct"; - - mct_map: mct-map { - #interrupt-cells = <1>; - #address-cells = <0>; - #size-cells = <0>; - interrupt-map = <0 &combiner 23 3>, - <1 &combiner 23 4>, - <2 &combiner 25 2>, - <3 &combiner 25 3>, - <4 &gic 0 120 0>, - <5 &gic 0 121 0>, - <6 &gic 0 122 0>, - <7 &gic 0 123 0>, - <8 &gic 0 128 0>, - <9 &gic 0 129 0>, - <10 &gic 0 130 0>, - <11 &gic 0 131 0>; - }; - }; - nocp_mem0_0: nocp@10CA1000 { compatible = "samsung,exynos5420-nocp"; reg = <0x10CA1000 0x200>; @@ -1570,6 +1523,11 @@ pinctrl-0 = <&i2c3_bus>; }; +&mct { + clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>; + clock-names = "fin_pll", "mct"; +}; + &pwm { clocks = <&clock CLK_PWM>; clock-names = "timers"; diff --git a/arch/arm/boot/dts/exynos54xx.dtsi b/arch/arm/boot/dts/exynos54xx.dtsi new file mode 100644 index 0000000..1bcfb7f --- /dev/null +++ b/arch/arm/boot/dts/exynos54xx.dtsi @@ -0,0 +1,68 @@ +/* + * Samsung's Exynos54xx SoC series common device tree source + * + * Copyright (c) 2012-2013 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * Copyright (c) 2016 Krzysztof Kozlowski + * + * Device nodes common for Samsung Exynos5410/5420/5422/5800. Specific + * Exynos 54xx SoCs should include this file and customize it further + * (e.g. with clocks). + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "skeleton.dtsi" +#include "exynos5.dtsi" + +/ { + compatible = "samsung,exynos5"; + + soc: soc { + sysram@02020000 { + compatible = "mmio-sram"; + reg = <0x02020000 0x54000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x02020000 0x54000>; + + smp-sysram@0 { + compatible = "samsung,exynos4210-sysram"; + reg = <0x0 0x1000>; + }; + + smp-sysram@53000 { + compatible = "samsung,exynos4210-sysram-ns"; + reg = <0x53000 0x1000>; + }; + }; + + mct: mct@101c0000 { + compatible = "samsung,exynos4210-mct"; + reg = <0x101c0000 0xb00>; + interrupt-parent = <&mct_map>; + interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>, + <8>, <9>, <10>, <11>; + + mct_map: mct-map { + #interrupt-cells = <1>; + #address-cells = <0>; + #size-cells = <0>; + interrupt-map = <0 &combiner 23 3>, + <1 &combiner 23 4>, + <2 &combiner 25 2>, + <3 &combiner 25 3>, + <4 &gic 0 120 0>, + <5 &gic 0 121 0>, + <6 &gic 0 122 0>, + <7 &gic 0 123 0>, + <8 &gic 0 128 0>, + <9 &gic 0 129 0>, + <10 &gic 0 130 0>, + <11 &gic 0 131 0>; + }; + }; + }; +}; -- cgit v0.10.2 From cb0896562228703209644e92926ed445150cc594 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 8 May 2016 19:42:11 +0200 Subject: ARM: dts: exynos: Add USB to Exynos5410 Move USB 3.0 DWC and 2.0 EHCI/OHCI nodes from exynos5420.dtsi to exynos54xx.dtsi common for entire family. For Exynos542x/5800 this should not have functional impact but for Exynos5410 this effectively adds USB support. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Javier Martinez Canillas Tested-by: Javier Martinez Canillas diff --git a/arch/arm/boot/dts/exynos5410.dtsi b/arch/arm/boot/dts/exynos5410.dtsi index 1354b5b..6146bf1 100644 --- a/arch/arm/boot/dts/exynos5410.dtsi +++ b/arch/arm/boot/dts/exynos5410.dtsi @@ -188,4 +188,43 @@ 3 0 0x07000000 0x20000>; }; +&usbdrd3_0 { + clocks = <&clock CLK_USBD300>; + clock-names = "usbdrd30"; +}; + +&usbdrd_phy0 { + clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>; + clock-names = "phy", "ref"; + samsung,pmu-syscon = <&pmu_system_controller>; +}; + +&usbdrd3_1 { + clocks = <&clock CLK_USBD301>; + clock-names = "usbdrd30"; +}; + +&usbdrd_phy1 { + clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBPHY301>; + clock-names = "phy", "ref"; + samsung,pmu-syscon = <&pmu_system_controller>; +}; + +&usbhost1 { + clocks = <&clock CLK_USBH20>; + clock-names = "usbhost"; +}; + +&usbhost2 { + clocks = <&clock CLK_USBH20>; + clock-names = "usbhost"; +}; + +&usb2_phy { + clocks = <&clock CLK_USBH20>, <&clock CLK_SCLK_USBPHY300>; + clock-names = "phy", "ref"; + samsung,sysreg-phandle = <&sysreg_system_controller>; + samsung,pmureg-phandle = <&pmu_system_controller>; +}; + #include "exynos5410-pinctrl.dtsi" diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index 2d9f43b..64450f5 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -41,8 +41,6 @@ spi0 = &spi_0; spi1 = &spi_1; spi2 = &spi_2; - usbdrdphy0 = &usbdrd_phy0; - usbdrdphy1 = &usbdrd_phy1; }; /* @@ -806,98 +804,6 @@ clock-names = "secss"; }; - usbdrd3_0: usb3-0 { - compatible = "samsung,exynos5250-dwusb3"; - clocks = <&clock CLK_USBD300>; - clock-names = "usbdrd30"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - usbdrd_dwc3_0: dwc3@12000000 { - compatible = "snps,dwc3"; - reg = <0x12000000 0x10000>; - interrupts = <0 72 0>; - phys = <&usbdrd_phy0 0>, <&usbdrd_phy0 1>; - phy-names = "usb2-phy", "usb3-phy"; - }; - }; - - usbdrd_phy0: phy@12100000 { - compatible = "samsung,exynos5420-usbdrd-phy"; - reg = <0x12100000 0x100>; - clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>; - clock-names = "phy", "ref"; - samsung,pmu-syscon = <&pmu_system_controller>; - #phy-cells = <1>; - }; - - usbdrd3_1: usb3-1 { - compatible = "samsung,exynos5250-dwusb3"; - clocks = <&clock CLK_USBD301>; - clock-names = "usbdrd30"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - usbdrd_dwc3_1: dwc3@12400000 { - compatible = "snps,dwc3"; - reg = <0x12400000 0x10000>; - interrupts = <0 73 0>; - phys = <&usbdrd_phy1 0>, <&usbdrd_phy1 1>; - phy-names = "usb2-phy", "usb3-phy"; - }; - }; - - usbdrd_phy1: phy@12500000 { - compatible = "samsung,exynos5420-usbdrd-phy"; - reg = <0x12500000 0x100>; - clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBPHY301>; - clock-names = "phy", "ref"; - samsung,pmu-syscon = <&pmu_system_controller>; - #phy-cells = <1>; - }; - - usbhost2: usb@12110000 { - compatible = "samsung,exynos4210-ehci"; - reg = <0x12110000 0x100>; - interrupts = <0 71 0>; - - clocks = <&clock CLK_USBH20>; - clock-names = "usbhost"; - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - phys = <&usb2_phy 1>; - }; - }; - - usbhost1: usb@12120000 { - compatible = "samsung,exynos4210-ohci"; - reg = <0x12120000 0x100>; - interrupts = <0 71 0>; - - clocks = <&clock CLK_USBH20>; - clock-names = "usbhost"; - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - phys = <&usb2_phy 1>; - }; - }; - - usb2_phy: phy@12130000 { - compatible = "samsung,exynos5250-usb2-phy"; - reg = <0x12130000 0x100>; - clocks = <&clock CLK_USBH20>, <&clock CLK_SCLK_USBPHY300>; - clock-names = "phy", "ref"; - #phy-cells = <1>; - samsung,sysreg-phandle = <&sysreg_system_controller>; - samsung,pmureg-phandle = <&pmu_system_controller>; - }; - sysmmu_g2dr: sysmmu@0x10A60000 { compatible = "samsung,exynos-sysmmu"; reg = <0x10A60000 0x1000>; @@ -1560,4 +1466,43 @@ clock-names = "uart", "clk_uart_baud0"; }; +&usbdrd3_0 { + clocks = <&clock CLK_USBD300>; + clock-names = "usbdrd30"; +}; + +&usbdrd_phy0 { + clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>; + clock-names = "phy", "ref"; + samsung,pmu-syscon = <&pmu_system_controller>; +}; + +&usbdrd3_1 { + clocks = <&clock CLK_USBD301>; + clock-names = "usbdrd30"; +}; + +&usbdrd_phy1 { + clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBPHY301>; + clock-names = "phy", "ref"; + samsung,pmu-syscon = <&pmu_system_controller>; +}; + +&usbhost1 { + clocks = <&clock CLK_USBH20>; + clock-names = "usbhost"; +}; + +&usbhost2 { + clocks = <&clock CLK_USBH20>; + clock-names = "usbhost"; +}; + +&usb2_phy { + clocks = <&clock CLK_USBH20>, <&clock CLK_SCLK_USBPHY300>; + clock-names = "phy", "ref"; + samsung,sysreg-phandle = <&sysreg_system_controller>; + samsung,pmureg-phandle = <&pmu_system_controller>; +}; + #include "exynos5420-pinctrl.dtsi" diff --git a/arch/arm/boot/dts/exynos54xx.dtsi b/arch/arm/boot/dts/exynos54xx.dtsi index 1bcfb7f..e01d068 100644 --- a/arch/arm/boot/dts/exynos54xx.dtsi +++ b/arch/arm/boot/dts/exynos54xx.dtsi @@ -20,6 +20,11 @@ / { compatible = "samsung,exynos5"; + aliases { + usbdrdphy0 = &usbdrd_phy0; + usbdrdphy1 = &usbdrd_phy1; + }; + soc: soc { sysram@02020000 { compatible = "mmio-sram"; @@ -64,5 +69,79 @@ <11 &gic 0 131 0>; }; }; + + usbdrd3_0: usb3-0 { + compatible = "samsung,exynos5250-dwusb3"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + usbdrd_dwc3_0: dwc3@12000000 { + compatible = "snps,dwc3"; + reg = <0x12000000 0x10000>; + interrupts = <0 72 0>; + phys = <&usbdrd_phy0 0>, <&usbdrd_phy0 1>; + phy-names = "usb2-phy", "usb3-phy"; + }; + }; + + usbdrd_phy0: phy@12100000 { + compatible = "samsung,exynos5420-usbdrd-phy"; + reg = <0x12100000 0x100>; + #phy-cells = <1>; + }; + + usbdrd3_1: usb3-1 { + compatible = "samsung,exynos5250-dwusb3"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + usbdrd_dwc3_1: dwc3@12400000 { + compatible = "snps,dwc3"; + reg = <0x12400000 0x10000>; + interrupts = <0 73 0>; + phys = <&usbdrd_phy1 0>, <&usbdrd_phy1 1>; + phy-names = "usb2-phy", "usb3-phy"; + }; + }; + + usbdrd_phy1: phy@12500000 { + compatible = "samsung,exynos5420-usbdrd-phy"; + reg = <0x12500000 0x100>; + #phy-cells = <1>; + }; + + usbhost2: usb@12110000 { + compatible = "samsung,exynos4210-ehci"; + reg = <0x12110000 0x100>; + interrupts = <0 71 0>; + + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + phys = <&usb2_phy 1>; + }; + }; + + usbhost1: usb@12120000 { + compatible = "samsung,exynos4210-ohci"; + reg = <0x12120000 0x100>; + interrupts = <0 71 0>; + + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + phys = <&usb2_phy 1>; + }; + }; + + usb2_phy: phy@12130000 { + compatible = "samsung,exynos5250-usb2-phy"; + reg = <0x12130000 0x100>; + #phy-cells = <1>; + }; }; }; -- cgit v0.10.2 From 8149afe4dbf91bead5632ac66f54f38b5d8b2391 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 3 May 2016 11:48:18 +0200 Subject: ARM: dts: exynos: Add initial support for Odroid XU board The Hardkernel's Odroid XU board was first design with big.LITTLE SoC from Samsung: the Exynos5410. Details: 1. Exynos5410 octa-core (A15+A7, however as of now only one cluster is enabled), 2. 2 GB DDR3 RAM, 3. PowerVR SGX544MP3 GPU (not enabled in DTS), 4. USB 3.0 Host x 1, USB 3.0 OTG x 1, USB 2.0 Host x 4, 5. HDMI 1.4a, MIPI DSI and Display Port (Display Port not on all of revisions though), 6. eMMC 4.5 and microSD slots. Comparing this board to Odroid XU3 (more popular), the differences are: 1. Exynos5410 instead of 5422, 2. MIPI DSI LCD connector, 3. Main PMIC: Maxim 77802 instead of S2MPS11, 4. USB3503+LAN9730 instead of integrated LAN9514, 5. eMMC 4.5 instead of eMMC 5.0, This patch adds initial support for the XU board with working basic functions, eMMC/SD and USB (including attached ethernet adapter). Signed-off-by: Krzysztof Kozlowski Acked-by: Rob Herring Reviewed-by: Javier Martinez Canillas Link: http://www.hardkernel.com/main/products/prdt_info.php?g_code=G137510300620 diff --git a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt index f5deace..0ea7f14 100644 --- a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt +++ b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt @@ -47,6 +47,7 @@ Required root node properties: - "hardkernel,odroid-u3" - for Exynos4412-based Hardkernel Odroid U3. - "hardkernel,odroid-x" - for Exynos4412-based Hardkernel Odroid X. - "hardkernel,odroid-x2" - for Exynos4412-based Hardkernel Odroid X2. + - "hardkernel,odroid-xu" - for Exynos5410-based Hardkernel Odroid XU. - "hardkernel,odroid-xu3" - for Exynos5422-based Hardkernel Odroid XU3. - "hardkernel,odroid-xu3-lite" - for Exynos5422-based Hardkernel Odroid XU3 Lite board. diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 06b6c2d..9a1fc0d 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -134,6 +134,7 @@ dtb-$(CONFIG_ARCH_EXYNOS5) += \ exynos5250-snow-rev5.dtb \ exynos5250-spring.dtb \ exynos5260-xyref5260.dtb \ + exynos5410-odroidxu.dtb \ exynos5410-smdk5410.dtb \ exynos5420-arndale-octa.dtb \ exynos5420-peach-pit.dtb \ diff --git a/arch/arm/boot/dts/exynos5410-odroidxu.dts b/arch/arm/boot/dts/exynos5410-odroidxu.dts new file mode 100644 index 0000000..9fe0450 --- /dev/null +++ b/arch/arm/boot/dts/exynos5410-odroidxu.dts @@ -0,0 +1,121 @@ +/* + * Hardkernel Odroid XU board device tree source + * + * Copyright (c) 2013 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * Copyright (c) 2016 Krzysztof Kozlowski + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/dts-v1/; +#include "exynos5410.dtsi" +#include +#include +#include "exynos54xx-odroidxu-leds.dtsi" + +/ { + model = "Hardkernel Odroid XU"; + compatible = "hardkernel,odroid-xu", "samsung,exynos5410", "samsung,exynos5"; + + memory { + reg = <0x40000000 0x7ea00000>; + }; + + chosen { + linux,stdout-path = &serial_2; + }; + + emmc_pwrseq: pwrseq { + pinctrl-0 = <&emmc_nrst_pin>; + pinctrl-names = "default"; + compatible = "mmc-pwrseq-emmc"; + reset-gpios = <&gpd1 0 GPIO_ACTIVE_LOW>; + }; + + fan0: pwm-fan { + compatible = "pwm-fan"; + pwms = <&pwm 0 20972 0>; + cooling-min-state = <0>; + cooling-max-state = <3>; + #cooling-cells = <2>; + cooling-levels = <0 130 170 230>; + }; + + fin_pll: xxti { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "fin_pll"; + #clock-cells = <0>; + }; + + firmware@02073000 { + compatible = "samsung,secure-firmware"; + reg = <0x02073000 0x1000>; + }; +}; + +&mmc_0 { + status = "okay"; + mmc-pwrseq = <&emmc_pwrseq>; + cd-gpios = <&gpc0 2 GPIO_ACTIVE_LOW>; + card-detect-delay = <200>; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <0 4>; + samsung,dw-mshc-ddr-timing = <0 2>; + samsung,dw-mshc-hs400-timing = <0 2>; + samsung,read-strobe-delay = <90>; + pinctrl-names = "default"; + pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8 &sd0_cd>; + bus-width = <8>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + mmc-hs400-1_8v; +}; + +&mmc_2 { + status = "okay"; + card-detect-delay = <200>; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <0 4>; + samsung,dw-mshc-ddr-timing = <0 2>; + pinctrl-names = "default"; + pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>; + bus-width = <4>; + cap-sd-highspeed; +}; + +&pinctrl_0 { + emmc_nrst_pin: emmc-nrst { + samsung,pins = "gpd1-0"; + samsung,pin-function = <0>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; +}; + +&serial_0 { + status = "okay"; +}; + +&serial_1 { + status = "okay"; +}; + +&serial_2 { + status = "okay"; +}; + +&serial_3 { + status = "okay"; +}; + +&usbdrd_dwc3_0 { + dr_mode = "host"; +}; + +&usbdrd_dwc3_1 { + dr_mode = "peripheral"; +}; -- cgit v0.10.2 From 538fc7ad51b85bff727a147947300406a5ad220f Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 10 May 2016 20:17:23 +0200 Subject: ARM: dts: exynos: Move HSI2C nodes to exynos54xx.dtsi The USI/HSI2C nodes can be mostly shared between Exynos5420 and Exynos5410 so move them to common DTSI. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Javier Martinez Canillas Tested-by: Javier Martinez Canillas diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index 64450f5..8196194 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -29,10 +29,6 @@ pinctrl2 = &pinctrl_2; pinctrl3 = &pinctrl_3; pinctrl4 = &pinctrl_4; - i2c4 = &hsi2c_4; - i2c5 = &hsi2c_5; - i2c6 = &hsi2c_6; - i2c7 = &hsi2c_7; i2c8 = &hsi2c_8; i2c9 = &hsi2c_9; i2c10 = &hsi2c_10; @@ -562,59 +558,6 @@ status = "disabled"; }; - /* i2c_0-3 are defined in exynos5.dtsi */ - hsi2c_4: i2c@12CA0000 { - compatible = "samsung,exynos5250-hsi2c"; - reg = <0x12CA0000 0x1000>; - interrupts = <0 60 0>; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c4_hs_bus>; - clocks = <&clock CLK_USI0>; - clock-names = "hsi2c"; - status = "disabled"; - }; - - hsi2c_5: i2c@12CB0000 { - compatible = "samsung,exynos5250-hsi2c"; - reg = <0x12CB0000 0x1000>; - interrupts = <0 61 0>; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c5_hs_bus>; - clocks = <&clock CLK_USI1>; - clock-names = "hsi2c"; - status = "disabled"; - }; - - hsi2c_6: i2c@12CC0000 { - compatible = "samsung,exynos5250-hsi2c"; - reg = <0x12CC0000 0x1000>; - interrupts = <0 62 0>; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c6_hs_bus>; - clocks = <&clock CLK_USI2>; - clock-names = "hsi2c"; - status = "disabled"; - }; - - hsi2c_7: i2c@12CD0000 { - compatible = "samsung,exynos5250-hsi2c"; - reg = <0x12CD0000 0x1000>; - interrupts = <0 63 0>; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c7_hs_bus>; - clocks = <&clock CLK_USI3>; - clock-names = "hsi2c"; - status = "disabled"; - }; - hsi2c_8: i2c@12E00000 { compatible = "samsung,exynos5250-hsi2c"; reg = <0x12E00000 0x1000>; @@ -1429,6 +1372,34 @@ pinctrl-0 = <&i2c3_bus>; }; +&hsi2c_4 { + clocks = <&clock CLK_USI0>; + clock-names = "hsi2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_hs_bus>; +}; + +&hsi2c_5 { + clocks = <&clock CLK_USI1>; + clock-names = "hsi2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c5_hs_bus>; +}; + +&hsi2c_6 { + clocks = <&clock CLK_USI2>; + clock-names = "hsi2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c6_hs_bus>; +}; + +&hsi2c_7 { + clocks = <&clock CLK_USI3>; + clock-names = "hsi2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c7_hs_bus>; +}; + &mct { clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>; clock-names = "fin_pll", "mct"; diff --git a/arch/arm/boot/dts/exynos54xx.dtsi b/arch/arm/boot/dts/exynos54xx.dtsi index e01d068..44a8391 100644 --- a/arch/arm/boot/dts/exynos54xx.dtsi +++ b/arch/arm/boot/dts/exynos54xx.dtsi @@ -21,6 +21,10 @@ compatible = "samsung,exynos5"; aliases { + i2c4 = &hsi2c_4; + i2c5 = &hsi2c_5; + i2c6 = &hsi2c_6; + i2c7 = &hsi2c_7; usbdrdphy0 = &usbdrd_phy0; usbdrdphy1 = &usbdrd_phy1; }; @@ -70,6 +74,43 @@ }; }; + /* i2c_0-3 are defined in exynos5.dtsi */ + hsi2c_4: i2c@12ca0000 { + compatible = "samsung,exynos5250-hsi2c"; + reg = <0x12ca0000 0x1000>; + interrupts = <0 60 0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + hsi2c_5: i2c@12cb0000 { + compatible = "samsung,exynos5250-hsi2c"; + reg = <0x12cb0000 0x1000>; + interrupts = <0 61 0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + hsi2c_6: i2c@12cc0000 { + compatible = "samsung,exynos5250-hsi2c"; + reg = <0x12cc0000 0x1000>; + interrupts = <0 62 0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + hsi2c_7: i2c@12cd0000 { + compatible = "samsung,exynos5250-hsi2c"; + reg = <0x12cd0000 0x1000>; + interrupts = <0 63 0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + usbdrd3_0: usb3-0 { compatible = "samsung,exynos5250-dwusb3"; #address-cells = <1>; -- cgit v0.10.2 From b5f5654fd3435fc9c465cec3ebb1aacf086359e4 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 10 May 2016 21:48:18 +0200 Subject: ARM: dts: exynos: Add I2C, PWM and UART pinctrl to Exynos5410 Add pincontrol groups for HSI2C (USI), I2C, PWM and UART to Exynos5410. This allows configuring these pins to specific functions. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Javier Martinez Canillas diff --git a/arch/arm/boot/dts/exynos5410-pinctrl.dtsi b/arch/arm/boot/dts/exynos5410-pinctrl.dtsi index ddacafa..b58a0f2 100644 --- a/arch/arm/boot/dts/exynos5410-pinctrl.dtsi +++ b/arch/arm/boot/dts/exynos5410-pinctrl.dtsi @@ -278,6 +278,139 @@ #interrupt-cells = <2>; }; + uart0_data: uart0-data { + samsung,pins = "gpa0-0", "gpa0-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + uart0_fctl: uart0-fctl { + samsung,pins = "gpa0-2", "gpa0-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + uart1_data: uart1-data { + samsung,pins = "gpa0-4", "gpa0-5"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + uart1_fctl: uart1-fctl { + samsung,pins = "gpa0-6", "gpa0-7"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + i2c2_bus: i2c2-bus { + samsung,pins = "gpa0-6", "gpa0-7"; + samsung,pin-function = <3>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + uart2_data: uart2-data { + samsung,pins = "gpa1-0", "gpa1-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + uart2_fctl: uart2-fctl { + samsung,pins = "gpa1-2", "gpa1-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + i2c3_bus: i2c3-bus { + samsung,pins = "gpa1-2", "gpa1-3"; + samsung,pin-function = <3>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + uart3_data: uart3-data { + samsung,pins = "gpa1-4", "gpa1-5"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + i2c4_hs_bus: i2c4-hs-bus { + samsung,pins = "gpa2-0", "gpa2-1"; + samsung,pin-function = <3>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + i2c5_hs_bus: i2c5-hs-bus { + samsung,pins = "gpa2-2", "gpa2-3"; + samsung,pin-function = <3>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + i2c6_hs_bus: i2c6-hs-bus { + samsung,pins = "gpb1-3", "gpb1-4"; + samsung,pin-function = <4>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + pwm0_out: pwm0-out { + samsung,pins = "gpb2-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + pwm1_out: pwm1-out { + samsung,pins = "gpb2-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + pwm2_out: pwm2-out { + samsung,pins = "gpb2-2"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + pwm3_out: pwm3-out { + samsung,pins = "gpb2-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + i2c7_hs_bus: i2c7-hs-bus { + samsung,pins = "gpb2-2", "gpb2-3"; + samsung,pin-function = <3>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + i2c0_bus: i2c0-bus { + samsung,pins = "gpb3-0", "gpb3-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + i2c1_bus: i2c1-bus { + samsung,pins = "gpb3-2", "gpb3-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + sd0_clk: sd0-clk { samsung,pins = "gpc0-0"; samsung,pin-function = <2>; -- cgit v0.10.2 From e1e146b1b0628865f1ec754f5d21c4da47324544 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 10 May 2016 19:30:26 +0200 Subject: ARM: dts: exynos: Add RTC and I2C to Exynos5410 Configure Exynos5410-specific properties of RTC, I2C and HSI2C nodes. This still does not enable them on the board level though. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Javier Martinez Canillas diff --git a/arch/arm/boot/dts/exynos5410.dtsi b/arch/arm/boot/dts/exynos5410.dtsi index 6146bf1..a937d9b 100644 --- a/arch/arm/boot/dts/exynos5410.dtsi +++ b/arch/arm/boot/dts/exynos5410.dtsi @@ -149,6 +149,62 @@ }; }; +&i2c_0 { + clocks = <&clock CLK_I2C0>; + clock-names = "i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_bus>; +}; + +&i2c_1 { + clocks = <&clock CLK_I2C1>; + clock-names = "i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_bus>; +}; + +&i2c_2 { + clocks = <&clock CLK_I2C2>; + clock-names = "i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_bus>; +}; + +&i2c_3 { + clocks = <&clock CLK_I2C3>; + clock-names = "i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_bus>; +}; + +&hsi2c_4 { + clocks = <&clock CLK_USI0>; + clock-names = "hsi2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_hs_bus>; +}; + +&hsi2c_5 { + clocks = <&clock CLK_USI1>; + clock-names = "hsi2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c5_hs_bus>; +}; + +&hsi2c_6 { + clocks = <&clock CLK_USI2>; + clock-names = "hsi2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c6_hs_bus>; +}; + +&hsi2c_7 { + clocks = <&clock CLK_USI3>; + clock-names = "hsi2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c7_hs_bus>; +}; + &mct { clocks = <&fin_pll>, <&clock CLK_MCT>; clock-names = "fin_pll", "mct"; @@ -159,6 +215,13 @@ clock-names = "timers"; }; +&rtc { + clocks = <&clock CLK_RTC>; + clock-names = "rtc"; + interrupt-parent = <&pmu_system_controller>; + status = "disabled"; +}; + &serial_0 { clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>; clock-names = "uart", "clk_uart_baud0"; -- cgit v0.10.2 From 6a93792774fc72861b7e8efaa3545a88272b4413 Mon Sep 17 00:00:00 2001 From: Lubomir Rintel Date: Mon, 2 May 2016 09:06:51 +0200 Subject: ARM: bcm2835: dt: Add the ethernet to the device trees The hub and the ethernet in its port 1 are hardwired on the board. Compared to the adapters that can be plugged into the USB ports, this one has no serial EEPROM to store its MAC. Nevertheless, the Raspberry Pi has the MAC address for this adapter in its ROM, accessible from its firmware. U-Boot can read out the address and set the local-mac-address property of the node with "ethernet" alias. Let's add the node so that U-Boot can do its business. Model B rev2 and Model B+ entries were verified by me, the hierarchy and pid/vid pair for the Version 2 was provided by Peter Chen. Original Model B is a blind shot, though very likely correct. Signed-off-by: Lubomir Rintel Acked-by: Stephen Warren Signed-off-by: Eric Anholt diff --git a/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts b/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts index 57d313b..d5fdb8e 100644 --- a/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts +++ b/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts @@ -1,6 +1,7 @@ /dts-v1/; #include "bcm2835.dtsi" #include "bcm2835-rpi.dtsi" +#include "bcm283x-rpi-smsc9514.dtsi" / { compatible = "raspberrypi,model-b-plus", "brcm,bcm2835"; diff --git a/arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts b/arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts index cf2774e..bfc4bd9 100644 --- a/arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts +++ b/arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts @@ -1,6 +1,7 @@ /dts-v1/; #include "bcm2835.dtsi" #include "bcm2835-rpi.dtsi" +#include "bcm283x-rpi-smsc9512.dtsi" / { compatible = "raspberrypi,model-b-rev2", "brcm,bcm2835"; diff --git a/arch/arm/boot/dts/bcm2835-rpi-b.dts b/arch/arm/boot/dts/bcm2835-rpi-b.dts index 8b15f9c..0371bb7 100644 --- a/arch/arm/boot/dts/bcm2835-rpi-b.dts +++ b/arch/arm/boot/dts/bcm2835-rpi-b.dts @@ -1,6 +1,7 @@ /dts-v1/; #include "bcm2835.dtsi" #include "bcm2835-rpi.dtsi" +#include "bcm283x-rpi-smsc9512.dtsi" / { compatible = "raspberrypi,model-b", "brcm,bcm2835"; diff --git a/arch/arm/boot/dts/bcm2836-rpi-2-b.dts b/arch/arm/boot/dts/bcm2836-rpi-2-b.dts index c4743f4..29e1cfe 100644 --- a/arch/arm/boot/dts/bcm2836-rpi-2-b.dts +++ b/arch/arm/boot/dts/bcm2836-rpi-2-b.dts @@ -1,6 +1,7 @@ /dts-v1/; #include "bcm2836.dtsi" #include "bcm2835-rpi.dtsi" +#include "bcm283x-rpi-smsc9514.dtsi" / { compatible = "raspberrypi,2-model-b", "brcm,bcm2836"; diff --git a/arch/arm/boot/dts/bcm283x-rpi-smsc9512.dtsi b/arch/arm/boot/dts/bcm283x-rpi-smsc9512.dtsi new file mode 100644 index 0000000..12c981e --- /dev/null +++ b/arch/arm/boot/dts/bcm283x-rpi-smsc9512.dtsi @@ -0,0 +1,19 @@ +/ { + aliases { + ethernet = ðernet; + }; +}; + +&usb { + usb1@1 { + compatible = "usb424,9512"; + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + ethernet: usbether@1 { + compatible = "usb424,ec00"; + reg = <1>; + }; + }; +}; diff --git a/arch/arm/boot/dts/bcm283x-rpi-smsc9514.dtsi b/arch/arm/boot/dts/bcm283x-rpi-smsc9514.dtsi new file mode 100644 index 0000000..3f0a56e --- /dev/null +++ b/arch/arm/boot/dts/bcm283x-rpi-smsc9514.dtsi @@ -0,0 +1,19 @@ +/ { + aliases { + ethernet = ðernet; + }; +}; + +&usb { + usb1@1 { + compatible = "usb424,9514"; + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + ethernet: usbether@1 { + compatible = "usb424,ec00"; + reg = <1>; + }; + }; +}; diff --git a/arch/arm/boot/dts/bcm283x.dtsi b/arch/arm/boot/dts/bcm283x.dtsi index 10b27b9..b982522 100644 --- a/arch/arm/boot/dts/bcm283x.dtsi +++ b/arch/arm/boot/dts/bcm283x.dtsi @@ -287,6 +287,8 @@ compatible = "brcm,bcm2835-usb"; reg = <0x7e980000 0x10000>; interrupts = <1 9>; + #address-cells = <1>; + #size-cells = <0>; }; v3d: v3d@7ec00000 { -- cgit v0.10.2 From 500d336669ae9b2fb605a4ac0b478e2858e75a07 Mon Sep 17 00:00:00 2001 From: Chris Brand Date: Thu, 28 Apr 2016 10:59:57 -0700 Subject: Documentation: Binding docs for bcm11351 enable method Commit 84320e1a635fcf90cff4185f029ce9e31bf1d4a7 ("ARM: BCM: Clean up SMP support for Broadcom Kona") moved the "secondary-boot-reg" property from the "cpus" node to the individual "cpu" nodes but negelected to update brcm,bcm11351-cpu-method.txt to match. bcm11351-cpu-method was apparently never added to the list of methods in bindings/arm/cpus.txt. bindings/arm/cpus.txt states that "enable-method" should be a property of the "cpu" node rather than the "cpus" node. This patch rectifies these two omissions and one inconsistency. Signed-off-by: Chris Brand Acked-by: Rob Herring Signed-off-by: Florian Fainelli diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm11351-cpu-method.txt b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm11351-cpu-method.txt index 8240c02..e3f9969 100644 --- a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm11351-cpu-method.txt +++ b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm11351-cpu-method.txt @@ -5,7 +5,7 @@ CPUs in the following Broadcom SoCs: BCM11130, BCM11140, BCM11351, BCM28145, BCM28155, BCM21664 The enable method is specified by defining the following required -properties in the "cpus" device tree node: +properties in the "cpu" device tree node: - enable-method = "brcm,bcm11351-cpu-method"; - secondary-boot-reg = <...>; @@ -19,8 +19,6 @@ Example: cpus { #address-cells = <1>; #size-cells = <0>; - enable-method = "brcm,bcm11351-cpu-method"; - secondary-boot-reg = <0x3500417c>; cpu0: cpu@0 { device_type = "cpu"; @@ -32,5 +30,7 @@ Example: device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <1>; + enable-method = "brcm,bcm11351-cpu-method"; + secondary-boot-reg = <0x3500417c>; }; }; diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt index 3f0cbbb..e97a456 100644 --- a/Documentation/devicetree/bindings/arm/cpus.txt +++ b/Documentation/devicetree/bindings/arm/cpus.txt @@ -193,6 +193,7 @@ nodes to be present and contain the properties described below. "allwinner,sun6i-a31" "allwinner,sun8i-a23" "arm,realview-smp" + "brcm,bcm11351-cpu-method" "brcm,bcm-nsp-smp" "brcm,brahma-b15" "marvell,armada-375-smp" -- cgit v0.10.2 From f302b57ab0e5ff91a2e90cd1d2b84a27d8d95824 Mon Sep 17 00:00:00 2001 From: Chris Brand Date: Thu, 28 Apr 2016 10:59:58 -0700 Subject: ARM: dts: fix use of bcm11351 enable method bindings/arm/cpus.txt states that "enable-method" should be a property of the "cpu" node rather than the "cpus" node. Signed-off-by: Chris Brand Signed-off-by: Florian Fainelli diff --git a/arch/arm/boot/dts/bcm11351.dtsi b/arch/arm/boot/dts/bcm11351.dtsi index 3dc7a8c..18045c3 100644 --- a/arch/arm/boot/dts/bcm11351.dtsi +++ b/arch/arm/boot/dts/bcm11351.dtsi @@ -30,7 +30,6 @@ cpus { #address-cells = <1>; #size-cells = <0>; - enable-method = "brcm,bcm11351-cpu-method"; cpu0: cpu@0 { device_type = "cpu"; @@ -41,6 +40,7 @@ cpu1: cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a9"; + enable-method = "brcm,bcm11351-cpu-method"; secondary-boot-reg = <0x3500417c>; reg = <1>; }; diff --git a/arch/arm/boot/dts/bcm21664.dtsi b/arch/arm/boot/dts/bcm21664.dtsi index 3f525be..6dde95f 100644 --- a/arch/arm/boot/dts/bcm21664.dtsi +++ b/arch/arm/boot/dts/bcm21664.dtsi @@ -30,7 +30,6 @@ cpus { #address-cells = <1>; #size-cells = <0>; - enable-method = "brcm,bcm11351-cpu-method"; cpu0: cpu@0 { device_type = "cpu"; @@ -41,6 +40,7 @@ cpu1: cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a9"; + enable-method = "brcm,bcm11351-cpu-method"; secondary-boot-reg = <0x35004178>; reg = <1>; }; -- cgit v0.10.2 From 6585cb5a1341cbc5dfcf99a9b4ebda338b03657e Mon Sep 17 00:00:00 2001 From: Chris Brand Date: Thu, 28 Apr 2016 10:59:59 -0700 Subject: ARM: BCM: modify Broadcom CPU enable method Commit 84320e1a635fcf90cff4185f029ce9e31bf1d4a7 ("ARM: BCM: Clean up SMP support for Broadcom Kona") moved the "secondary-boot-reg" property from the "cpus" node to the individual "cpu" nodes but negelected to actually support multiple "secondary-boot-reg" properties. This patchset rectifies that omission. Note that the behaviour is changed slightly in that the "secondary-boot-reg" property is now read in smp_boot_secondary() rather than smp_prepare_cpus(). This means that any omissions will now only be reported when and if the cpu in question is being brought up. It also means that an omission for one cpu will not force uniprocessor mode. Signed-off-by: Chris Brand Reviewed-and-Tested-by: Jon Mason Signed-off-by: Florian Fainelli diff --git a/arch/arm/mach-bcm/platsmp.c b/arch/arm/mach-bcm/platsmp.c index cfae9c7..5e53cf2 100644 --- a/arch/arm/mach-bcm/platsmp.c +++ b/arch/arm/mach-bcm/platsmp.c @@ -37,9 +37,6 @@ #define OF_SECONDARY_BOOT "secondary-boot-reg" #define MPIDR_CPUID_BITMASK 0x3 -/* I/O address of register used to coordinate secondary core startup */ -static u32 secondary_boot_addr; - /* * Enable the Cortex A9 Snoop Control Unit * @@ -81,20 +78,40 @@ static int __init scu_a9_enable(void) return 0; } -static int nsp_write_lut(void) +static u32 secondary_boot_addr_for(unsigned int cpu) +{ + u32 secondary_boot_addr = 0; + struct device_node *cpu_node = of_get_cpu_node(cpu, NULL); + + if (!cpu_node) { + pr_err("Failed to find device tree node for CPU%u\n", cpu); + return 0; + } + + if (of_property_read_u32(cpu_node, + OF_SECONDARY_BOOT, + &secondary_boot_addr)) + pr_err("required secondary boot register not specified for CPU%u\n", + cpu); + + of_node_put(cpu_node); + + return secondary_boot_addr; +} + +static int nsp_write_lut(unsigned int cpu) { void __iomem *sku_rom_lut; phys_addr_t secondary_startup_phy; + const u32 secondary_boot_addr = secondary_boot_addr_for(cpu); - if (!secondary_boot_addr) { - pr_warn("required secondary boot register not specified\n"); + if (!secondary_boot_addr) return -EINVAL; - } sku_rom_lut = ioremap_nocache((phys_addr_t)secondary_boot_addr, - sizeof(secondary_boot_addr)); + sizeof(phys_addr_t)); if (!sku_rom_lut) { - pr_warn("unable to ioremap SKU-ROM LUT register\n"); + pr_warn("unable to ioremap SKU-ROM LUT register for cpu %u\n", cpu); return -ENOMEM; } @@ -113,70 +130,12 @@ static int nsp_write_lut(void) static void __init bcm_smp_prepare_cpus(unsigned int max_cpus) { - static cpumask_t only_cpu_0 = { CPU_BITS_CPU0 }; - struct device_node *cpus_node = NULL; - struct device_node *cpu_node = NULL; - int ret; - - /* - * This function is only called via smp_ops->smp_prepare_cpu(). - * That only happens if a "/cpus" device tree node exists - * and has an "enable-method" property that selects the SMP - * operations defined herein. - */ - cpus_node = of_find_node_by_path("/cpus"); - if (!cpus_node) - return; - - for_each_child_of_node(cpus_node, cpu_node) { - u32 cpuid; - - if (of_node_cmp(cpu_node->type, "cpu")) - continue; - - if (of_property_read_u32(cpu_node, "reg", &cpuid)) { - pr_debug("%s: missing reg property\n", - cpu_node->full_name); - ret = -ENOENT; - goto out; - } - - /* - * "secondary-boot-reg" property should be defined only - * for secondary cpu - */ - if ((cpuid & MPIDR_CPUID_BITMASK) == 1) { - /* - * Our secondary enable method requires a - * "secondary-boot-reg" property to specify a register - * address used to request the ROM code boot a secondary - * core. If we have any trouble getting this we fall - * back to uniprocessor mode. - */ - if (of_property_read_u32(cpu_node, - OF_SECONDARY_BOOT, - &secondary_boot_addr)) { - pr_warn("%s: no" OF_SECONDARY_BOOT "property\n", - cpu_node->name); - ret = -ENOENT; - goto out; - } - } - } - - /* - * Enable the SCU on Cortex A9 based SoCs. If -ENOENT is - * returned, the SoC reported a uniprocessor configuration. - * We bail on any other error. - */ - ret = scu_a9_enable(); -out: - of_node_put(cpu_node); - of_node_put(cpus_node); + const cpumask_t only_cpu_0 = { CPU_BITS_CPU0 }; - if (ret) { + /* Enable the SCU on Cortex A9 based SoCs */ + if (scu_a9_enable()) { /* Update the CPU present map to reflect uniprocessor mode */ - pr_warn("disabling SMP\n"); + pr_warn("failed to enable A9 SCU - disabling SMP\n"); init_cpu_present(&only_cpu_0); } } @@ -207,6 +166,7 @@ static int kona_boot_secondary(unsigned int cpu, struct task_struct *idle) u32 cpu_id; u32 boot_val; bool timeout = false; + const u32 secondary_boot_addr = secondary_boot_addr_for(cpu); cpu_id = cpu_logical_map(cpu); if (cpu_id & ~BOOT_ADDR_CPUID_MASK) { @@ -214,13 +174,11 @@ static int kona_boot_secondary(unsigned int cpu, struct task_struct *idle) return -EINVAL; } - if (!secondary_boot_addr) { - pr_err("required secondary boot register not specified\n"); + if (!secondary_boot_addr) return -EINVAL; - } - boot_reg = ioremap_nocache( - (phys_addr_t)secondary_boot_addr, sizeof(u32)); + boot_reg = ioremap_nocache((phys_addr_t)secondary_boot_addr, + sizeof(phys_addr_t)); if (!boot_reg) { pr_err("unable to map boot register for cpu %u\n", cpu_id); return -ENOMEM; @@ -263,7 +221,7 @@ static int nsp_boot_secondary(unsigned int cpu, struct task_struct *idle) * After wake up, secondary core branches to the startup * address programmed at SKU ROM LUT location. */ - ret = nsp_write_lut(); + ret = nsp_write_lut(cpu); if (ret) { pr_err("unable to write startup addr to SKU ROM LUT\n"); goto out; @@ -276,12 +234,12 @@ out: return ret; } -static const struct smp_operations bcm_smp_ops __initconst = { +static const struct smp_operations kona_smp_ops __initconst = { .smp_prepare_cpus = bcm_smp_prepare_cpus, .smp_boot_secondary = kona_boot_secondary, }; CPU_METHOD_OF_DECLARE(bcm_smp_bcm281xx, "brcm,bcm11351-cpu-method", - &bcm_smp_ops); + &kona_smp_ops); static const struct smp_operations nsp_smp_ops __initconst = { .smp_prepare_cpus = bcm_smp_prepare_cpus, -- cgit v0.10.2 From d71eb941208883404d44380807726afdc20ab98a Mon Sep 17 00:00:00 2001 From: Jon Mason Date: Thu, 5 May 2016 19:29:30 -0400 Subject: ARM: dts: NSP: Add MSI support on PCI Add MSI support to the PCI driver of the Northstar Plus SoC. This uses the existing pcie-iproc driver. So, all that is needed is device tree entries in the DTS. Signed-off-by: Jon Mason Signed-off-by: Florian Fainelli diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi index def9e78..a44bf29 100644 --- a/arch/arm/boot/dts/bcm-nsp.dtsi +++ b/arch/arm/boot/dts/bcm-nsp.dtsi @@ -290,6 +290,18 @@ ranges = <0x82000000 0 0x08000000 0x08000000 0 0x8000000>; status = "disabled"; + + msi-parent = <&msi0>; + msi0: msi@18012000 { + compatible = "brcm,iproc-msi"; + msi-controller; + interrupt-parent = <&gic>; + interrupts = , + , + , + ; + brcm,pcie-msi-inten; + }; }; pcie1: pcie@18013000 { @@ -314,6 +326,18 @@ ranges = <0x82000000 0 0x40000000 0x40000000 0 0x8000000>; status = "disabled"; + + msi-parent = <&msi1>; + msi1: msi@18013000 { + compatible = "brcm,iproc-msi"; + msi-controller; + interrupt-parent = <&gic>; + interrupts = , + , + , + ; + brcm,pcie-msi-inten; + }; }; pcie2: pcie@18014000 { @@ -338,5 +362,17 @@ ranges = <0x82000000 0 0x48000000 0x48000000 0 0x8000000>; status = "disabled"; + + msi-parent = <&msi2>; + msi2: msi@18014000 { + compatible = "brcm,iproc-msi"; + msi-controller; + interrupt-parent = <&gic>; + interrupts = , + , + , + ; + brcm,pcie-msi-inten; + }; }; }; -- cgit v0.10.2 From f7f20cba26b9ee8865156ca9df264510cfcebbf6 Mon Sep 17 00:00:00 2001 From: Jon Mason Date: Thu, 5 May 2016 19:29:31 -0400 Subject: ARM: dts: NSP: modify second CPU address NSP B0 has a different address for the second core. Since there should not be any Ax versions in the field, it should be safe to universally change this. Signed-off-by: Jon Mason Signed-off-by: Florian Fainelli diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi index a44bf29..1759e65 100644 --- a/arch/arm/boot/dts/bcm-nsp.dtsi +++ b/arch/arm/boot/dts/bcm-nsp.dtsi @@ -57,7 +57,7 @@ compatible = "arm,cortex-a9"; next-level-cache = <&L2>; enable-method = "brcm,bcm-nsp-smp"; - secondary-boot-reg = <0xffff042c>; + secondary-boot-reg = <0xffff0fec>; reg = <0x1>; }; }; -- cgit v0.10.2 From a7dd623f55e636e5c8a8b7557c1bc4e16e359ca9 Mon Sep 17 00:00:00 2001 From: Jon Mason Date: Thu, 5 May 2016 19:29:32 -0400 Subject: ARM: dts: NSP: Add new DT file for bcm958625hr Create a new device tree file for the Broadcom Northstar Plus HR SVK. This SVK is a smaller form factor, and thus only has 2 PCI slots and 1 UART. Also, it has the ability to reboot via GPIO (instead of the processor reset). Signed-off-by: Jon Mason Signed-off-by: Florian Fainelli diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 06b6c2d..2afa97e 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -97,6 +97,7 @@ dtb-$(CONFIG_ARCH_BCM_MOBILE) += \ bcm28155-ap.dtb \ bcm21664-garnet.dtb dtb-$(CONFIG_ARCH_BCM_NSP) += \ + bcm958625hr.dtb \ bcm958625k.dtb dtb-$(CONFIG_ARCH_BERLIN) += \ berlin2-sony-nsz-gs7.dtb \ diff --git a/arch/arm/boot/dts/bcm958625hr.dts b/arch/arm/boot/dts/bcm958625hr.dts new file mode 100644 index 0000000..d82cc96 --- /dev/null +++ b/arch/arm/boot/dts/bcm958625hr.dts @@ -0,0 +1,107 @@ +/* + * BSD LICENSE + * + * Copyright (c) 2016 Broadcom. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Broadcom Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/dts-v1/; + +#include "bcm-nsp.dtsi" + +/ { + model = "NorthStar Plus SVK (BCM958625HR)"; + compatible = "brcm,bcm58625", "brcm,nsp"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&nand { + nandcs@0 { + compatible = "brcm,nandcs"; + reg = <0>; + nand-on-flash-bbt; + + #address-cells = <1>; + #size-cells = <1>; + + nand-ecc-strength = <24>; + nand-ecc-step-size = <1024>; + + brcm,nand-oob-sector-size = <27>; + + partition@0 { + label = "nboot"; + reg = <0x00000000 0x00200000>; + read-only; + }; + partition@200000 { + label = "nenv"; + reg = <0x00200000 0x00400000>; + }; + partition@600000 { + label = "nsystem"; + reg = <0x00600000 0x00a00000>; + }; + partition@1000000 { + label = "nrootfs"; + reg = <0x01000000 0x03000000>; + }; + partition@4000000 { + label = "ncustfs"; + reg = <0x04000000 0x3c000000>; + }; + }; +}; + +&uart0 { + status = "okay"; +}; + +&pcie0 { + status = "okay"; +}; + +&pcie1 { + status = "okay"; +}; + +&pinctrl { + pinctrl-names = "default"; + pinctrl-0 = <&nand_sel>; + nand_sel: nand_sel { + function = "nand"; + groups = "nand_grp"; + }; +}; -- cgit v0.10.2 From 5f79985dcfec73d7a09ed99c40c28b64552518fe Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= Date: Wed, 27 Apr 2016 09:05:03 +0200 Subject: ARM: BCM5301X: Enable SPI-NOR on dual flash devices MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Commit 1b47b98acce2 ("ARM: BCM5301X: Add DT entry for SPI controller and NOR flash") enabled SPI-NOR device on routers using serial flash only. However there are also devices with two flash memories: 1) Small SPI attached flash used mostly for booting 2) Bigger NAND used mostly for storing firmware On such devices we still need SPI-NOR e.g. to access NVRAM data. Signed-off-by: Rafał Miłecki Signed-off-by: Florian Fainelli diff --git a/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts b/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts index 5087aa8..9cb186e 100644 --- a/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts +++ b/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts @@ -147,3 +147,7 @@ &usb3 { vcc-gpio = <&chipcommon 10 GPIO_ACTIVE_LOW>; }; + +&spi_nor { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/bcm4708-netgear-r6250.dts b/arch/arm/boot/dts/bcm4708-netgear-r6250.dts index 1049ab1..8ce39d5 100644 --- a/arch/arm/boot/dts/bcm4708-netgear-r6250.dts +++ b/arch/arm/boot/dts/bcm4708-netgear-r6250.dts @@ -90,3 +90,7 @@ &usb3 { vcc-gpio = <&chipcommon 0 GPIO_ACTIVE_HIGH>; }; + +&spi_nor { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts b/arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts index 3a94606..6229ef2 100644 --- a/arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts +++ b/arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts @@ -82,3 +82,7 @@ }; }; }; + +&spi_nor { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts b/arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts index 791d722..0653e7e 100644 --- a/arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts +++ b/arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts @@ -131,3 +131,7 @@ &usb2 { vcc-gpio = <&chipcommon 13 GPIO_ACTIVE_HIGH>; }; + +&spi_nor { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts b/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts index ace38ef..50cf804 100644 --- a/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts +++ b/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts @@ -113,3 +113,7 @@ &usb3 { vcc-gpio = <&chipcommon 18 GPIO_ACTIVE_HIGH>; }; + +&spi_nor { + status = "okay"; +}; -- cgit v0.10.2 From aff138bf8e3736b29a0ec31160d8cb75f55f93ed Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Wed, 1 Jun 2016 09:20:35 -0400 Subject: ARM: dts: exynos: Add TMU nodes regulator supply for Peach boards The Exynos5800 Peach Pi and Exynos5420 Peach Pit Chromebooks have the LDO10 1.8V output connected to the VDD18_TS{01,23,4} Exynos SoC pins. Add this regulator as the input supply of the Thermal Management Unit channels and also remove the always-on property since all the devices using LDO10 as input supply are now defined. Suggested-by: Krzysztof Kozlowski Signed-off-by: Javier Martinez Canillas Signed-off-by: Krzysztof Kozlowski diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts b/arch/arm/boot/dts/exynos5420-peach-pit.dts index c124740..f307843 100644 --- a/arch/arm/boot/dts/exynos5420-peach-pit.dts +++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts @@ -425,7 +425,6 @@ regulator-name = "vdd_ldo10"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; - regulator-always-on; regulator-state-mem { regulator-off-in-suspend; }; @@ -1041,6 +1040,26 @@ status = "okay"; }; +&tmu_cpu0 { + vtmu-supply = <&ldo10_reg>; +}; + +&tmu_cpu1 { + vtmu-supply = <&ldo10_reg>; +}; + +&tmu_cpu2 { + vtmu-supply = <&ldo10_reg>; +}; + +&tmu_cpu3 { + vtmu-supply = <&ldo10_reg>; +}; + +&tmu_gpu { + vtmu-supply = <&ldo10_reg>; +}; + &usbdrd_dwc3_0 { dr_mode = "host"; }; diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts b/arch/arm/boot/dts/exynos5800-peach-pi.dts index af1c9b9..203c8da 100644 --- a/arch/arm/boot/dts/exynos5800-peach-pi.dts +++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts @@ -425,7 +425,6 @@ regulator-name = "vdd_ldo10"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; - regulator-always-on; regulator-state-mem { regulator-off-in-suspend; }; @@ -1017,6 +1016,26 @@ status = "okay"; }; +&tmu_cpu0 { + vtmu-supply = <&ldo10_reg>; +}; + +&tmu_cpu1 { + vtmu-supply = <&ldo10_reg>; +}; + +&tmu_cpu2 { + vtmu-supply = <&ldo10_reg>; +}; + +&tmu_cpu3 { + vtmu-supply = <&ldo10_reg>; +}; + +&tmu_gpu { + vtmu-supply = <&ldo10_reg>; +}; + &usbdrd_dwc3_0 { dr_mode = "host"; }; -- cgit v0.10.2 From a034a8d9e50fda30e0532a0f965bbe70bf8a7bd5 Mon Sep 17 00:00:00 2001 From: Thor Thayer Date: Wed, 25 May 2016 16:29:42 +0000 Subject: ARM: dts: Arria10 ECC Manager IRQ controller changes Changes to support IRQ controller implementation including adding new property irq-controller to eccmgr and adding IRQ property to children. Signed-off-by: Thor Thayer Signed-off-by: Dinh Nguyen diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi index 17e81dc..a2f82bb 100644 --- a/arch/arm/boot/dts/socfpga_arria10.dtsi +++ b/arch/arm/boot/dts/socfpga_arria10.dtsi @@ -610,16 +610,22 @@ #size-cells = <1>; interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>, <0 0 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <2>; ranges; l2-ecc@ffd06010 { compatible = "altr,socfpga-a10-l2-ecc"; reg = <0xffd06010 0x4>; + interrupts = <0 IRQ_TYPE_LEVEL_HIGH>, + <32 IRQ_TYPE_LEVEL_HIGH>; }; ocram-ecc@ff8c3000 { compatible = "altr,socfpga-a10-ocram-ecc"; reg = <0xff8c3000 0x400>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH>, + <33 IRQ_TYPE_LEVEL_HIGH>; }; }; -- cgit v0.10.2 From 4586e4ea7eddb123322e25b63369fad35976d9e6 Mon Sep 17 00:00:00 2001 From: Thor Thayer Date: Wed, 25 May 2016 16:29:43 +0000 Subject: ARM: dts: Move Arria10 SDRAM as child of ECC Manager Changes to support ECC Manager as SDRAM IRQ parent by 1) updating IRQ property values to correct child IRQs 2) moving node under ECC Manager. Signed-off-by: Thor Thayer Signed-off-by: Dinh Nguyen diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi index a2f82bb..21f6c3c 100644 --- a/arch/arm/boot/dts/socfpga_arria10.dtsi +++ b/arch/arm/boot/dts/socfpga_arria10.dtsi @@ -572,12 +572,6 @@ reg = <0xffcfb100 0x80>; }; - sdramedac { - compatible = "altr,sdram-edac-a10"; - altr,sdr-syscon = <&sdr>; - interrupts = <0 2 4>, <0 0 4>; - }; - L2: l2-cache@fffff000 { compatible = "arm,pl310-cache"; reg = <0xfffff000 0x1000>; @@ -614,6 +608,13 @@ #interrupt-cells = <2>; ranges; + sdramedac { + compatible = "altr,sdram-edac-a10"; + altr,sdr-syscon = <&sdr>; + interrupts = <17 IRQ_TYPE_LEVEL_HIGH>, + <49 IRQ_TYPE_LEVEL_HIGH>; + }; + l2-ecc@ffd06010 { compatible = "altr,socfpga-a10-l2-ecc"; reg = <0xffd06010 0x4>; -- cgit v0.10.2 From e5995e6df69e2652d923bbe33174676166b10787 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 31 May 2016 20:39:02 +0200 Subject: ARM: dts: exynos: Interrupt for USB DWC3-1 differs between Exynos5420 and 5410 On Exynos5410 the SPI interrupt for second USB DWC3 (called DRD: Dual Role Device) is different - 200 instead of 73. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Javier Martinez Canillas Signed-off-by: Krzysztof Kozlowski diff --git a/arch/arm/boot/dts/exynos5410.dtsi b/arch/arm/boot/dts/exynos5410.dtsi index a937d9b..1ed83b8 100644 --- a/arch/arm/boot/dts/exynos5410.dtsi +++ b/arch/arm/boot/dts/exynos5410.dtsi @@ -16,6 +16,7 @@ #include "exynos54xx.dtsi" #include "exynos-syscon-restart.dtsi" #include +#include / { compatible = "samsung,exynos5410", "samsung,exynos5"; @@ -267,6 +268,10 @@ clock-names = "usbdrd30"; }; +&usbdrd_dwc3_1 { + interrupts = ; +}; + &usbdrd_phy1 { clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBPHY301>; clock-names = "phy", "ref"; diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index 8196194..b036b46 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -16,6 +16,7 @@ #include "exynos54xx.dtsi" #include #include +#include / { compatible = "samsung,exynos5420", "samsung,exynos5"; @@ -1453,6 +1454,10 @@ clock-names = "usbdrd30"; }; +&usbdrd_dwc3_1 { + interrupts = ; +}; + &usbdrd_phy1 { clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBPHY301>; clock-names = "phy", "ref"; diff --git a/arch/arm/boot/dts/exynos54xx.dtsi b/arch/arm/boot/dts/exynos54xx.dtsi index 44a8391..0eb8aa3 100644 --- a/arch/arm/boot/dts/exynos54xx.dtsi +++ b/arch/arm/boot/dts/exynos54xx.dtsi @@ -141,7 +141,6 @@ usbdrd_dwc3_1: dwc3@12400000 { compatible = "snps,dwc3"; reg = <0x12400000 0x10000>; - interrupts = <0 73 0>; phys = <&usbdrd_phy1 0>, <&usbdrd_phy1 1>; phy-names = "usb2-phy", "usb3-phy"; }; -- cgit v0.10.2 From b8ecd88979dddfc5cb631cec5a2351aae6c935e1 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Thu, 21 Apr 2016 01:26:15 +0800 Subject: ARM: dts: imx6qdl: add clocks property for ocotp node Add clocks property for ocotp node. Signed-off-by: Peng Fan Cc: Sascha Hauer Cc: Rob Herring Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi index ed613eb..16541a7 100644 --- a/arch/arm/boot/dts/imx6qdl.dtsi +++ b/arch/arm/boot/dts/imx6qdl.dtsi @@ -1100,6 +1100,7 @@ ocotp: ocotp@021bc000 { compatible = "fsl,imx6q-ocotp", "syscon"; reg = <0x021bc000 0x4000>; + clocks = <&clks IMX6QDL_CLK_IIM>; }; tzasc@021d0000 { /* TZASC1 */ -- cgit v0.10.2 From d72b7b44f19e072cae4fc8592890c6dc6f590275 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Thu, 21 Apr 2016 01:26:16 +0800 Subject: ARM: dts: imx6sl: add clocks property for ocotp node Add clocks property for ocotp node. Signed-off-by: Peng Fan Cc: Sascha Hauer Cc: Rob Herring Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi index d12b250..b37da94 100644 --- a/arch/arm/boot/dts/imx6sl.dtsi +++ b/arch/arm/boot/dts/imx6sl.dtsi @@ -853,6 +853,7 @@ ocotp: ocotp@021bc000 { compatible = "fsl,imx6sl-ocotp", "syscon"; reg = <0x021bc000 0x4000>; + clocks = <&clks IMX6SL_CLK_OCOTP>; }; audmux: audmux@021d8000 { -- cgit v0.10.2 From 298701ec045867d0cfdda21d407a0ead829c3d36 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 3 May 2016 10:57:31 -0300 Subject: ARM: dts: imx: Remove unneeded unit-addresses Building with W=1 option leads to several warnings like: Warning (unit_address_vs_reg): Node /soc/aips-bus@02000000/anatop@020c8000/regulator-1p1@110 has a unit name, but no reg property Fix them by removing the unneeded unit-addresses. Signed-off-by: Fabio Estevam Acked-by: Rob Herring Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi index b37da94..5425150 100644 --- a/arch/arm/boot/dts/imx6sl.dtsi +++ b/arch/arm/boot/dts/imx6sl.dtsi @@ -461,7 +461,7 @@ <0 54 IRQ_TYPE_LEVEL_HIGH>, <0 127 IRQ_TYPE_LEVEL_HIGH>; - regulator-1p1@110 { + regulator-1p1 { compatible = "fsl,anatop-regulator"; regulator-name = "vdd1p1"; regulator-min-microvolt = <800000>; @@ -475,7 +475,7 @@ anatop-max-voltage = <1375000>; }; - regulator-3p0@120 { + regulator-3p0 { compatible = "fsl,anatop-regulator"; regulator-name = "vdd3p0"; regulator-min-microvolt = <2800000>; @@ -489,7 +489,7 @@ anatop-max-voltage = <3400000>; }; - regulator-2p5@130 { + regulator-2p5 { compatible = "fsl,anatop-regulator"; regulator-name = "vdd2p5"; regulator-min-microvolt = <2100000>; @@ -503,7 +503,7 @@ anatop-max-voltage = <2850000>; }; - reg_arm: regulator-vddcore@140 { + reg_arm: regulator-vddcore { compatible = "fsl,anatop-regulator"; regulator-name = "vddarm"; regulator-min-microvolt = <725000>; @@ -520,7 +520,7 @@ anatop-max-voltage = <1450000>; }; - reg_pu: regulator-vddpu@140 { + reg_pu: regulator-vddpu { compatible = "fsl,anatop-regulator"; regulator-name = "vddpu"; regulator-min-microvolt = <725000>; @@ -537,7 +537,7 @@ anatop-max-voltage = <1450000>; }; - reg_soc: regulator-vddsoc@140 { + reg_soc: regulator-vddsoc { compatible = "fsl,anatop-regulator"; regulator-name = "vddsoc"; regulator-min-microvolt = <725000>; diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi index 6a993bfda..2863c52 100644 --- a/arch/arm/boot/dts/imx6sx.dtsi +++ b/arch/arm/boot/dts/imx6sx.dtsi @@ -547,7 +547,7 @@ , ; - regulator-1p1@110 { + regulator-1p1 { compatible = "fsl,anatop-regulator"; regulator-name = "vdd1p1"; regulator-min-microvolt = <800000>; @@ -561,7 +561,7 @@ anatop-max-voltage = <1375000>; }; - regulator-3p0@120 { + regulator-3p0 { compatible = "fsl,anatop-regulator"; regulator-name = "vdd3p0"; regulator-min-microvolt = <2800000>; @@ -575,7 +575,7 @@ anatop-max-voltage = <3400000>; }; - regulator-2p5@130 { + regulator-2p5 { compatible = "fsl,anatop-regulator"; regulator-name = "vdd2p5"; regulator-min-microvolt = <2100000>; @@ -589,7 +589,7 @@ anatop-max-voltage = <2875000>; }; - reg_arm: regulator-vddcore@140 { + reg_arm: regulator-vddcore { compatible = "fsl,anatop-regulator"; regulator-name = "vddarm"; regulator-min-microvolt = <725000>; @@ -606,7 +606,7 @@ anatop-max-voltage = <1450000>; }; - reg_pcie: regulator-vddpcie@140 { + reg_pcie: regulator-vddpcie { compatible = "fsl,anatop-regulator"; regulator-name = "vddpcie"; regulator-min-microvolt = <725000>; @@ -622,7 +622,7 @@ anatop-max-voltage = <1450000>; }; - reg_soc: regulator-vddsoc@140 { + reg_soc: regulator-vddsoc { compatible = "fsl,anatop-regulator"; regulator-name = "vddsoc"; regulator-min-microvolt = <725000>; diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi index 4356b65..b15ed37 100644 --- a/arch/arm/boot/dts/imx6ul.dtsi +++ b/arch/arm/boot/dts/imx6ul.dtsi @@ -512,7 +512,7 @@ , ; - reg_3p0: regulator-3p0@120 { + reg_3p0: regulator-3p0 { compatible = "fsl,anatop-regulator"; regulator-name = "vdd3p0"; regulator-min-microvolt = <2625000>; @@ -526,7 +526,7 @@ anatop-enable-bit = <0>; }; - reg_arm: regulator-vddcore@140 { + reg_arm: regulator-vddcore { compatible = "fsl,anatop-regulator"; regulator-name = "cpu"; regulator-min-microvolt = <725000>; @@ -543,7 +543,7 @@ anatop-max-voltage = <1450000>; }; - reg_soc: regulator-vddsoc@140 { + reg_soc: regulator-vddsoc { compatible = "fsl,anatop-regulator"; regulator-name = "vddsoc"; regulator-min-microvolt = <725000>; diff --git a/arch/arm/boot/dts/imx7d.dtsi b/arch/arm/boot/dts/imx7d.dtsi index 6b3faa2..d70d55d 100644 --- a/arch/arm/boot/dts/imx7d.dtsi +++ b/arch/arm/boot/dts/imx7d.dtsi @@ -522,7 +522,7 @@ interrupts = , ; - reg_1p0d: regulator-vdd1p0d@210 { + reg_1p0d: regulator-vdd1p0d { compatible = "fsl,anatop-regulator"; regulator-name = "vdd1p0d"; regulator-min-microvolt = <800000>; -- cgit v0.10.2 From fb3239ff0382b0c35df25902d5bf90b23d109168 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 4 May 2016 19:33:17 -0300 Subject: ARM: dts: imx6ul: Add SAI alias Add SAI alias entries, which makes it possibe for the SAI driver to retrieve the port instance. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi index b15ed37..33b95d7 100644 --- a/arch/arm/boot/dts/imx6ul.dtsi +++ b/arch/arm/boot/dts/imx6ul.dtsi @@ -36,6 +36,9 @@ serial5 = &uart6; serial6 = &uart7; serial7 = &uart8; + sai1 = &sai1; + sai2 = &sai2; + sai3 = &sai3; spi0 = &ecspi1; spi1 = &ecspi2; spi2 = &ecspi3; -- cgit v0.10.2 From d805adb21f4c20e633e4fd9c8fac980a9d7f4045 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 4 May 2016 19:33:18 -0300 Subject: ARM: dts: imx6ul-14x14-evk: Pass "fsl, sai-mclk-direction-output" Pass "fsl,sai-mclk-direction-output" to the sai2 node, so that the SAI2_MCLK can be an output. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/imx6ul-14x14-evk.dts b/arch/arm/boot/dts/imx6ul-14x14-evk.dts index 668a729..918c7c8 100644 --- a/arch/arm/boot/dts/imx6ul-14x14-evk.dts +++ b/arch/arm/boot/dts/imx6ul-14x14-evk.dts @@ -146,6 +146,7 @@ <&clks IMX6UL_CLK_SAI2>; assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; assigned-clock-rates = <0>, <12288000>; + fsl,sai-mclk-direction-output; status = "okay"; }; -- cgit v0.10.2 From 97f5c1817b7e3c159b2c079df97415580096b7ad Mon Sep 17 00:00:00 2001 From: Stefan Agner Date: Thu, 5 May 2016 13:12:24 -0700 Subject: ARM: dts: imx7d-pinfunc: add input mux for UART2 RX DTE mode Add input mux for UART2 RX in DTE mode. This allows to use the pad UART2_TX_DATA_ALT0 as UART2 RX. This particular input select seems to be missing in current reference manuals (Rev. B), but when looking at the tables and other UART input select registers (e.g. UART3) it seems naturally that this input mux register also has a fourth pad option for UART2_TX_DATA_ALT0. It has also been proven to be required to use UART2 in DTE mode and the particular pads on the Colibri iMX7 platform. Signed-off-by: Stefan Agner Acked-by: Frank Li Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/imx7d-pinfunc.h b/arch/arm/boot/dts/imx7d-pinfunc.h index eeda783..3f9f0d9 100644 --- a/arch/arm/boot/dts/imx7d-pinfunc.h +++ b/arch/arm/boot/dts/imx7d-pinfunc.h @@ -594,7 +594,7 @@ #define MX7D_PAD_UART2_RX_DATA__GPIO4_IO2 0x0130 0x03A0 0x0000 0x5 0x0 #define MX7D_PAD_UART2_RX_DATA__ENET2_MDIO 0x0130 0x03A0 0x0000 0x6 0x0 #define MX7D_PAD_UART2_TX_DATA__UART2_DCE_TX 0x0134 0x03A4 0x0000 0x0 0x0 -#define MX7D_PAD_UART2_TX_DATA__UART2_DTE_RX 0x0134 0x03A4 0x0000 0x0 0x0 +#define MX7D_PAD_UART2_TX_DATA__UART2_DTE_RX 0x0134 0x03A4 0x06FC 0x0 0x3 #define MX7D_PAD_UART2_TX_DATA__I2C2_SDA 0x0134 0x03A4 0x05E0 0x1 0x0 #define MX7D_PAD_UART2_TX_DATA__SAI3_RX_DATA0 0x0134 0x03A4 0x06C8 0x2 0x0 #define MX7D_PAD_UART2_TX_DATA__ECSPI1_RDY 0x0134 0x03A4 0x0000 0x3 0x0 -- cgit v0.10.2 From c1a3b0681717ee0a4f52d8cb8441842cbda654a6 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 31 May 2016 20:39:03 +0200 Subject: ARM: dts: exynos: Add Thermal Management Unit to Exynos5410 Add nodes for Thermal Management Unit to exynos5410.dtsi. Use the same compatible as for Exynos5420 however without second base for TRIMINFO register and without TMU for GPU. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Javier Martinez Canillas diff --git a/arch/arm/boot/dts/exynos5410.dtsi b/arch/arm/boot/dts/exynos5410.dtsi index 1ed83b8..edd9544 100644 --- a/arch/arm/boot/dts/exynos5410.dtsi +++ b/arch/arm/boot/dts/exynos5410.dtsi @@ -82,6 +82,42 @@ #clock-cells = <1>; }; + tmu_cpu0: tmu@10060000 { + compatible = "samsung,exynos5420-tmu"; + reg = <0x10060000 0x100>; + interrupts = ; + clocks = <&clock CLK_TMU>; + clock-names = "tmu_apbif"; + #include "exynos4412-tmu-sensor-conf.dtsi" + }; + + tmu_cpu1: tmu@10064000 { + compatible = "samsung,exynos5420-tmu"; + reg = <0x10064000 0x100>; + interrupts = ; + clocks = <&clock CLK_TMU>; + clock-names = "tmu_apbif"; + #include "exynos4412-tmu-sensor-conf.dtsi" + }; + + tmu_cpu2: tmu@10068000 { + compatible = "samsung,exynos5420-tmu"; + reg = <0x10068000 0x100>; + interrupts = ; + clocks = <&clock CLK_TMU>; + clock-names = "tmu_apbif"; + #include "exynos4412-tmu-sensor-conf.dtsi" + }; + + tmu_cpu3: tmu@1006c000 { + compatible = "samsung,exynos5420-tmu"; + reg = <0x1006c000 0x100>; + interrupts = ; + clocks = <&clock CLK_TMU>; + clock-names = "tmu_apbif"; + #include "exynos4412-tmu-sensor-conf.dtsi" + }; + mmc_0: mmc@12200000 { compatible = "samsung,exynos5250-dw-mshc"; reg = <0x12200000 0x1000>; @@ -148,6 +184,25 @@ interrupts = <0 47 0>; }; }; + + thermal-zones { + cpu0_thermal: cpu0-thermal { + thermal-sensors = <&tmu_cpu0>; + #include "exynos5420-trip-points.dtsi" + }; + cpu1_thermal: cpu1-thermal { + thermal-sensors = <&tmu_cpu1>; + #include "exynos5420-trip-points.dtsi" + }; + cpu2_thermal: cpu2-thermal { + thermal-sensors = <&tmu_cpu2>; + #include "exynos5420-trip-points.dtsi" + }; + cpu3_thermal: cpu3-thermal { + thermal-sensors = <&tmu_cpu3>; + #include "exynos5420-trip-points.dtsi" + }; + }; }; &i2c_0 { -- cgit v0.10.2 From 88644b4c750b42ee0d053ecfe4d0dc6cff637c12 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 31 May 2016 20:39:04 +0200 Subject: ARM: dts: exynos: Configure PWM, usb3503, PMIC and thermal on Odroid XU board Extend the DTS for Exynos5410-based Odroid XU board with: 1. Proper PWM outputs, 2. usb3503 USB HUB (with integrated LAN9730 ethernet adapter (smsc95xx)), 3. Maxim 77802 PMIC (regulators, 32 kHz clocks, RTC), 4. CPU thermal (trip points are the same as in Odroid XU3/XU4 but cooling maps are different as there is no CPU freq and only one cluster available for now), 5. Regulator supplies for USB 3.0. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Javier Martinez Canillas diff --git a/arch/arm/boot/dts/exynos5410-odroidxu.dts b/arch/arm/boot/dts/exynos5410-odroidxu.dts index 9fe0450..d949931 100644 --- a/arch/arm/boot/dts/exynos5410-odroidxu.dts +++ b/arch/arm/boot/dts/exynos5410-odroidxu.dts @@ -12,6 +12,7 @@ /dts-v1/; #include "exynos5410.dtsi" +#include #include #include #include "exynos54xx-odroidxu-leds.dtsi" @@ -57,6 +58,387 @@ }; }; +&cpu0_thermal { + thermal-sensors = <&tmu_cpu0 0>; + polling-delay-passive = <0>; + polling-delay = <0>; + + trips { + cpu_alert0: cpu-alert-0 { + temperature = <50000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "active"; + }; + cpu_alert1: cpu-alert-1 { + temperature = <60000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "active"; + }; + cpu_alert2: cpu-alert-2 { + temperature = <70000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "active"; + }; + cpu_crit0: cpu-crit-0 { + temperature = <120000>; /* millicelsius */ + hysteresis = <0>; /* millicelsius */ + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu_alert0>; + cooling-device = <&fan0 0 1>; + }; + map1 { + trip = <&cpu_alert1>; + cooling-device = <&fan0 1 2>; + }; + map2 { + trip = <&cpu_alert2>; + cooling-device = <&fan0 2 3>; + }; + }; +}; + +&hsi2c_4 { + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <400000>; + status = "okay"; + + usb3503: usb-hub@08 { + compatible = "smsc,usb3503"; + reg = <0x08>; + + intn-gpios = <&gpx0 7 GPIO_ACTIVE_HIGH>; + connect-gpios = <&gpx0 6 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpx1 4 GPIO_ACTIVE_HIGH>; + initial-mode = <1>; + + clock-names = "refclk"; + clocks = <&pmu_system_controller 0>; + refclk-frequency = <24000000>; + }; + + max77802: pmic@09 { + compatible = "maxim,max77802"; + reg = <0x9>; + interrupt-parent = <&gpx0>; + interrupts = <4 IRQ_TYPE_NONE>; + pinctrl-names = "default"; + pinctrl-0 = <&max77802_irq>, <&pmic_dvs_1>, <&pmic_dvs_2>, + <&pmic_dvs_3>; + #clock-cells = <1>; + + inl1-supply = <&buck5_reg>; + inl2-supply = <&buck7_reg>; + inl3-supply = <&buck9_reg>; + inl4-supply = <&buck9_reg>; + inl5-supply = <&buck9_reg>; + inl6-supply = <&buck10_reg>; + inl7-supply = <&buck9_reg>; + /* inl9 supply is BOOST, not configured here */ + inl10-supply = <&buck7_reg>; + + regulators { + buck1_reg: BUCK1 { + regulator-name = "vdd_mif"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + regulator-boot-on; + }; + + buck2_reg: BUCK2 { + regulator-name = "vdd_arm"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + }; + + buck3_reg: BUCK3 { + regulator-name = "vdd_int"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + regulator-always-on; + regulator-boot-on; + }; + + buck4_reg: BUCK4 { + regulator-name = "vdd_g3d"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + regulator-always-on; + regulator-boot-on; + }; + + buck5_reg: BUCK5 { + regulator-name = "vdd_mem"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + }; + + buck6_reg: BUCK6 { + regulator-name = "vdd_kfc"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + }; + + buck7_reg: BUCK7 { + regulator-name = "buck7"; + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + regulator-boot-on; + }; + + buck8_reg: BUCK8 { + /* vdd_mmc0 */ + regulator-name = "vddf_2v85"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + regulator-always-on; + regulator-boot-on; + }; + + buck9_reg: BUCK9 { + regulator-name = "buck9"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + regulator-boot-on; + }; + + buck10_reg: BUCK10 { + regulator-name = "buck10"; + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo1_reg: LDO1 { + regulator-name = "vdd_alive"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + ldo2_reg: LDO2 { + regulator-name = "vddq_m1_m2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + ldo3_reg: LDO3 { + regulator-name = "vddq_gpio"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo4_reg: LDO4 { + regulator-name = "vddq_mmc2"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3000000>; + /* Having it off prevents reboot */ + regulator-always-on; + }; + + ldo5_reg: LDO5 { + regulator-name = "vdd18_hsic"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo6_reg: LDO6 { + regulator-name = "vdd18_bpll"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo7_reg: LDO7 { + regulator-name = "vddq_lcd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo8_reg: LDO8 { + regulator-name = "vdd10_hdmi"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + ldo9_reg: LDO9 { + regulator-name = "ldo9"; + }; + + ldo10_reg: LDO10 { + regulator-name = "vdd18_mipi"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo11_reg: LDO11 { + regulator-name = "vddq_mmc01"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + /* + * Having it off prevents accessing MMC after + * reboot with error: + * MMC Device 1: Clock OFF has been failed. + */ + regulator-always-on; + }; + + ldo12_reg: LDO12 { + regulator-name = "vdd33_usb3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + ldo13_reg: LDO13 { + regulator-name = "vddq_abbg0"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo14_reg: LDO14 { + regulator-name = "vddq_abbg1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo15_reg: LDO15 { + regulator-name = "vdd10_usb3"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + ldo16_reg: LDO16 { + regulator-name = "ldo16"; + }; + + ldo17_reg: LDO17 { + regulator-name = "cam_sensor_core"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + ldo18_reg: LDO18 { + regulator-name = "ldo18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo19_reg: LDO19 { + regulator-name = "ldo19"; + }; + + ldo20_reg: LDO20 { + regulator-name = "vdd_mmc0"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo21_reg: LDO21 { + /* vdd_mmc2 */ + regulator-name = "vddf_2v8"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; + + ldo22_reg: LDO22 { + regulator-name = "ldo22"; + }; + + ldo23_reg: LDO23 { + regulator-name = "dp_p3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + ldo24_reg: LDO24 { + regulator-name = "cam_af"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + ldo25_reg: LDO25 { + regulator-name = "eth_p3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + ldo26_reg: LDO26 { + regulator-name = "usb30_extclk"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + ldo27_reg: LDO27 { + regulator-name = "ldo27"; + }; + + ldo28_reg: LDO28 { + regulator-name = "ldo28"; + }; + + ldo29_reg: LDO29 { + regulator-name = "ldo29"; + }; + + ldo30_reg: LDO30 { + regulator-name = "vddq_e1_e2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + ldo31_reg: LDO31 { + regulator-name = "ldo31"; + }; + + /* On revisions with ti,ina231 this is sensor VS */ + ldo32_reg: LDO32 { + regulator-name = "vs_power_meter"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + ldo33_reg: LDO33 { + regulator-name = "ldo33"; + }; + + ldo34_reg: LDO34 { + regulator-name = "ldo34"; + }; + + ldo35_reg: LDO35 { + regulator-name = "ldo35"; + }; + }; + }; +}; + &mmc_0 { status = "okay"; mmc-pwrseq = <&emmc_pwrseq>; @@ -73,6 +455,8 @@ cap-mmc-highspeed; mmc-hs200-1_8v; mmc-hs400-1_8v; + vmmc-supply = <&ldo20_reg>; + vqmmc-supply = <&ldo11_reg>; }; &mmc_2 { @@ -85,17 +469,66 @@ pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>; bus-width = <4>; cap-sd-highspeed; + vmmc-supply = <&ldo21_reg>; + vqmmc-supply = <&ldo4_reg>; }; &pinctrl_0 { emmc_nrst_pin: emmc-nrst { samsung,pins = "gpd1-0"; - samsung,pin-function = <0>; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + pmic_dvs_3: pmic-dvs-3 { + samsung,pins = "gpx0-0"; + samsung,pin-function = <1>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + pmic_dvs_2: pmic-dvs-2 { + samsung,pins = "gpx0-1"; + samsung,pin-function = <1>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + pmic_dvs_1: pmic-dvs-1 { + samsung,pins = "gpx0-2"; + samsung,pin-function = <1>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + samsung,pin-val = <1>; + }; + + max77802_irq: max77802-irq { + samsung,pins = "gpx0-4"; + samsung,pin-function = <0xf>; samsung,pin-pud = <0>; samsung,pin-drv = <0>; }; }; +&pwm { + /* + * PWM 0 -- fan + * PWM 1 -- Green LED + * PWM 2 -- Blue LED + * PWM 3 -- on MIPI connector for backlight + */ + pinctrl-0 = <&pwm0_out &pwm1_out &pwm2_out &pwm3_out>; + pinctrl-names = "default"; + status = "okay"; +}; + +&rtc { + status = "okay"; + clocks = <&clock CLK_RTC>, <&max77802 MAX77802_CLK_32K_AP>; + clock-names = "rtc", "rtc_src"; +}; + &serial_0 { status = "okay"; }; @@ -112,6 +545,22 @@ status = "okay"; }; +&tmu_cpu0 { + vtmu-supply = <&ldo10_reg>; +}; + +&tmu_cpu1 { + vtmu-supply = <&ldo10_reg>; +}; + +&tmu_cpu2 { + vtmu-supply = <&ldo10_reg>; +}; + +&tmu_cpu3 { + vtmu-supply = <&ldo10_reg>; +}; + &usbdrd_dwc3_0 { dr_mode = "host"; }; @@ -119,3 +568,13 @@ &usbdrd_dwc3_1 { dr_mode = "peripheral"; }; + +&usbdrd3_0 { + vdd33-supply = <&ldo12_reg>; + vdd10-supply = <&ldo15_reg>; +}; + +&usbdrd3_1 { + vdd33-supply = <&ldo12_reg>; + vdd10-supply = <&ldo15_reg>; +}; -- cgit v0.10.2 From b8bd7e23bb0be762c39510497c931066dc62e62f Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 1 Jun 2016 11:45:51 +0200 Subject: ARM: dts: exynos: Add watchdog and Security SubSystem to Exynos5410 Move watchdog and Security SubSystem nodes from exynos5420.dtsi to file shared with Exynos5410 and configure the clocks on the latter. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Javier Martinez Canillas diff --git a/arch/arm/boot/dts/exynos5410.dtsi b/arch/arm/boot/dts/exynos5410.dtsi index edd9544..137f484 100644 --- a/arch/arm/boot/dts/exynos5410.dtsi +++ b/arch/arm/boot/dts/exynos5410.dtsi @@ -298,6 +298,11 @@ clock-names = "uart", "clk_uart_baud0"; }; +&sss { + clocks = <&clock CLK_SSS>; + clock-names = "secss"; +}; + &sromc { #address-cells = <2>; #size-cells = <1>; @@ -350,4 +355,10 @@ samsung,pmureg-phandle = <&pmu_system_controller>; }; +&watchdog { + clocks = <&clock CLK_WDT>; + clock-names = "watchdog"; + samsung,syscon-phandle = <&pmu_system_controller>; +}; + #include "exynos5410-pinctrl.dtsi" diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index b036b46..fa306a1 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -731,23 +731,6 @@ #include "exynos4412-tmu-sensor-conf.dtsi" }; - watchdog: watchdog@101D0000 { - compatible = "samsung,exynos5420-wdt"; - reg = <0x101D0000 0x100>; - interrupts = <0 42 0>; - clocks = <&clock CLK_WDT>; - clock-names = "watchdog"; - samsung,syscon-phandle = <&pmu_system_controller>; - }; - - sss: sss@10830000 { - compatible = "samsung,exynos4210-secss"; - reg = <0x10830000 0x300>; - interrupts = <0 112 0>; - clocks = <&clock CLK_SSS>; - clock-names = "secss"; - }; - sysmmu_g2dr: sysmmu@0x10A60000 { compatible = "samsung,exynos-sysmmu"; reg = <0x10A60000 0x1000>; @@ -1438,6 +1421,11 @@ clock-names = "uart", "clk_uart_baud0"; }; +&sss { + clocks = <&clock CLK_SSS>; + clock-names = "secss"; +}; + &usbdrd3_0 { clocks = <&clock CLK_USBD300>; clock-names = "usbdrd30"; @@ -1481,4 +1469,10 @@ samsung,pmureg-phandle = <&pmu_system_controller>; }; +&watchdog { + clocks = <&clock CLK_WDT>; + clock-names = "watchdog"; + samsung,syscon-phandle = <&pmu_system_controller>; +}; + #include "exynos5420-pinctrl.dtsi" diff --git a/arch/arm/boot/dts/exynos54xx.dtsi b/arch/arm/boot/dts/exynos54xx.dtsi index 0eb8aa3..06a6049 100644 --- a/arch/arm/boot/dts/exynos54xx.dtsi +++ b/arch/arm/boot/dts/exynos54xx.dtsi @@ -74,6 +74,18 @@ }; }; + watchdog: watchdog@101d0000 { + compatible = "samsung,exynos5420-wdt"; + reg = <0x101d0000 0x100>; + interrupts = <0 42 0>; + }; + + sss: sss@10830000 { + compatible = "samsung,exynos4210-secss"; + reg = <0x10830000 0x300>; + interrupts = <0 112 0>; + }; + /* i2c_0-3 are defined in exynos5.dtsi */ hsi2c_4: i2c@12ca0000 { compatible = "samsung,exynos5250-hsi2c"; -- cgit v0.10.2 From cb0df00040d593e3f56eaafdede568121f962c06 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 31 May 2016 20:39:05 +0200 Subject: ARM: dts: exynos: No need to enable TMU nodes on Odroid XU3 family The thermal nodes are not disabled in exynos5420.dtsi so there is no need to manually enable them on Odroid XU3/XU3-Lite/XU4 boards. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Javier Martinez Canillas diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi index 48c92b4..3f9c1a9 100644 --- a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi +++ b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi @@ -576,27 +576,22 @@ &tmu_cpu0 { vtmu-supply = <&ldo7_reg>; - status = "okay"; }; &tmu_cpu1 { vtmu-supply = <&ldo7_reg>; - status = "okay"; }; &tmu_cpu2 { vtmu-supply = <&ldo7_reg>; - status = "okay"; }; &tmu_cpu3 { vtmu-supply = <&ldo7_reg>; - status = "okay"; }; &tmu_gpu { vtmu-supply = <&ldo7_reg>; - status = "okay"; }; &rtc { -- cgit v0.10.2 From 31bda09d810d6948de31832964160acc002c7afa Mon Sep 17 00:00:00 2001 From: Chris Brand Date: Wed, 11 May 2016 14:36:19 -0700 Subject: Documentation: devicetree: Document BCM23550 bindings Add binding document for Broadcom BCM23550 SoC. BCM23550 has a Cluster Dormant Control IP block that holds cores in an idle state. Introduce a new CPU enable method in which the CDC is accessed to bring the core online. Signed-off-by: Chris Brand Signed-off-by: Florian Fainelli diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm23550-cpu-method.txt b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm23550-cpu-method.txt new file mode 100644 index 0000000..a3af54c --- /dev/null +++ b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm23550-cpu-method.txt @@ -0,0 +1,36 @@ +Broadcom Kona Family CPU Enable Method +-------------------------------------- +This binding defines the enable method used for starting secondary +CPUs in the following Broadcom SoCs: + BCM23550 + +The enable method is specified by defining the following required +properties in the "cpu" device tree node: + - enable-method = "brcm,bcm23550"; + - secondary-boot-reg = <...>; + +The secondary-boot-reg property is a u32 value that specifies the +physical address of the register used to request the ROM holding pen +code release a secondary CPU. The value written to the register is +formed by encoding the target CPU id into the low bits of the +physical start address it should jump to. + +Example: + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <1>; + enable-method = "brcm,bcm23550"; + secondary-boot-reg = <0x3500417c>; + }; + }; diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm23550.txt b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm23550.txt new file mode 100644 index 0000000..080baad --- /dev/null +++ b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm23550.txt @@ -0,0 +1,15 @@ +Broadcom BCM23550 device tree bindings +-------------------------------------- + +This document describes the device tree bindings for boards with the BCM23550 +SoC. + +Required root node property: + - compatible: brcm,bcm23550 + +Example: + / { + model = "BCM23550 SoC"; + compatible = "brcm,bcm23550"; + [...] + } diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt index e97a456..ff76088 100644 --- a/Documentation/devicetree/bindings/arm/cpus.txt +++ b/Documentation/devicetree/bindings/arm/cpus.txt @@ -194,6 +194,7 @@ nodes to be present and contain the properties described below. "allwinner,sun8i-a23" "arm,realview-smp" "brcm,bcm11351-cpu-method" + "brcm,bcm23550" "brcm,bcm-nsp-smp" "brcm,brahma-b15" "marvell,armada-375-smp" -- cgit v0.10.2 From fcd4138653f049c8fa45b48dc5f2806ced68e304 Mon Sep 17 00:00:00 2001 From: Chris Brand Date: Wed, 11 May 2016 14:36:22 -0700 Subject: ARM: dts: bcm23550: Add device tree files Add device tree files for the Broadcom BCM23550 SoC and the Broadcom Sparrow board. Signed-off-by: Chris Brand Signed-off-by: Florian Fainelli diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 2afa97e..cbe1595 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -95,7 +95,8 @@ dtb-$(CONFIG_ARCH_BCM_CYGNUS) += \ bcm958305k.dtb dtb-$(CONFIG_ARCH_BCM_MOBILE) += \ bcm28155-ap.dtb \ - bcm21664-garnet.dtb + bcm21664-garnet.dtb \ + bcm23550-sparrow.dtb dtb-$(CONFIG_ARCH_BCM_NSP) += \ bcm958625hr.dtb \ bcm958625k.dtb diff --git a/arch/arm/boot/dts/bcm23550-sparrow.dts b/arch/arm/boot/dts/bcm23550-sparrow.dts new file mode 100644 index 0000000..4d525cc --- /dev/null +++ b/arch/arm/boot/dts/bcm23550-sparrow.dts @@ -0,0 +1,80 @@ +/* + * BSD LICENSE + * + * Copyright(c) 2016 Broadcom. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Broadcom Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/dts-v1/; + +#include + +#include "bcm23550.dtsi" + +/ { + model = "BCM23550 Sparrow board"; + compatible = "brcm,bcm23550-sparrow", "brcm,bcm23550"; + + chosen { + stdout-path = "/slaves@3e000000/serial@0:115200n8"; + bootargs = "console=ttyS0,115200n8"; + }; + + memory { + reg = <0x80000000 0x20000000>; /* 512 MB */ + }; +}; + +&uartb { + status = "okay"; +}; + +&usbotg { + status = "okay"; +}; + +&usbphy { + status = "okay"; +}; + +&sdio1 { + max-frequency = <48000000>; + status = "okay"; +}; + +&sdio2 { + non-removable; + max-frequency = <48000000>; + status = "okay"; +}; + +&sdio4 { + max-frequency = <48000000>; + cd-gpios = <&gpio 91 GPIO_ACTIVE_LOW>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/bcm23550.dtsi b/arch/arm/boot/dts/bcm23550.dtsi new file mode 100644 index 0000000..a7a643f --- /dev/null +++ b/arch/arm/boot/dts/bcm23550.dtsi @@ -0,0 +1,415 @@ +/* + * BSD LICENSE + * + * Copyright(c) 2016 Broadcom. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Broadcom Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include + +/* BCM23550 and BCM21664 have almost identical clocks */ +#include "dt-bindings/clock/bcm21664.h" + +#include "skeleton.dtsi" + +/ { + model = "BCM23550 SoC"; + compatible = "brcm,bcm23550"; + interrupt-parent = <&gic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0>; + clock-frequency = <1000000000>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + enable-method = "brcm,bcm23550"; + secondary-boot-reg = <0x35004178>; + reg = <1>; + clock-frequency = <1000000000>; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + enable-method = "brcm,bcm23550"; + secondary-boot-reg = <0x35004178>; + reg = <2>; + clock-frequency = <1000000000>; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + enable-method = "brcm,bcm23550"; + secondary-boot-reg = <0x35004178>; + reg = <3>; + clock-frequency = <1000000000>; + }; + }; + + /* Hub bus */ + hub@34000000 { + compatible = "simple-bus"; + ranges = <0 0x34000000 0x102f83ac>; + #address-cells = <1>; + #size-cells = <1>; + + smc@4e000 { + compatible = "brcm,bcm23550-smc", "brcm,kona-smc"; + reg = <0x0004e000 0x400>; /* 1 KiB in SRAM */ + }; + + resetmgr: reset-controller@1001f00 { + compatible = "brcm,bcm21664-resetmgr"; + reg = <0x01001f00 0x24>; + }; + + gpio: gpio@1003000 { + compatible = "brcm,bcm23550-gpio", "brcm,kona-gpio"; + reg = <0x01003000 0x524>; + interrupts = + ; + #gpio-cells = <2>; + #interrupt-cells = <2>; + gpio-controller; + interrupt-controller; + }; + + timer@1006000 { + compatible = "brcm,kona-timer"; + reg = <0x01006000 0x1c>; + interrupts = ; + clocks = <&aon_ccu BCM21664_AON_CCU_HUB_TIMER>; + }; + }; + + /* Slaves bus */ + slaves@3e000000 { + compatible = "simple-bus"; + ranges = <0 0x3e000000 0x0001c070>; + #address-cells = <1>; + #size-cells = <1>; + + uartb: serial@0 { + compatible = "snps,dw-apb-uart"; + status = "disabled"; + reg = <0x00000000 0x118>; + clocks = <&slave_ccu BCM21664_SLAVE_CCU_UARTB>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + }; + + uartb2: serial@1000 { + compatible = "snps,dw-apb-uart"; + status = "disabled"; + reg = <0x00001000 0x118>; + clocks = <&slave_ccu BCM21664_SLAVE_CCU_UARTB2>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + }; + + uartb3: serial@2000 { + compatible = "snps,dw-apb-uart"; + status = "disabled"; + reg = <0x00002000 0x118>; + clocks = <&slave_ccu BCM21664_SLAVE_CCU_UARTB3>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + }; + + bsc1: i2c@16000 { + compatible = "brcm,kona-i2c"; + reg = <0x00016000 0x70>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC1>; + status = "disabled"; + }; + + bsc2: i2c@17000 { + compatible = "brcm,kona-i2c"; + reg = <0x00017000 0x70>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC2>; + status = "disabled"; + }; + + bsc3: i2c@18000 { + compatible = "brcm,kona-i2c"; + reg = <0x00018000 0x70>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC3>; + status = "disabled"; + }; + + bsc4: i2c@1c000 { + compatible = "brcm,kona-i2c"; + reg = <0x0001c000 0x70>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC4>; + status = "disabled"; + }; + }; + + /* Apps bus */ + apps@3e300000 { + compatible = "simple-bus"; + ranges = <0 0x3e300000 0x01b77000>; + #address-cells = <1>; + #size-cells = <1>; + + usbotg: usb@e20000 { + compatible = "snps,dwc2"; + reg = <0x00e20000 0x10000>; + interrupts = ; + clocks = <&usb_otg_ahb_clk>; + clock-names = "otg"; + phys = <&usbphy>; + phy-names = "usb2-phy"; + status = "disabled"; + }; + + usbphy: usb-phy@e30000 { + compatible = "brcm,kona-usb2-phy"; + reg = <0x00e30000 0x28>; + #phy-cells = <0>; + status = "disabled"; + }; + + sdio1: sdio@e80000 { + compatible = "brcm,kona-sdhci"; + reg = <0x00e80000 0x801c>; + interrupts = ; + clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO1>; + status = "disabled"; + }; + + sdio2: sdio@e90000 { + compatible = "brcm,kona-sdhci"; + reg = <0x00e90000 0x801c>; + interrupts = ; + clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO2>; + status = "disabled"; + }; + + sdio3: sdio@ea0000 { + compatible = "brcm,kona-sdhci"; + reg = <0x00ea0000 0x801c>; + interrupts = ; + clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO3>; + status = "disabled"; + }; + + sdio4: sdio@eb0000 { + compatible = "brcm,kona-sdhci"; + reg = <0x00eb0000 0x801c>; + interrupts = ; + clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO4>; + status = "disabled"; + }; + + cdc: cdc@1b0e000 { + compatible = "brcm,bcm23550-cdc"; + reg = <0x01b0e000 0x78>; + }; + + gic: interrupt-controller@1b21000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x01b21000 0x1000>, + <0x01b22000 0x1000>; + }; + }; + + clocks { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + /* + * Fixed clocks are defined before CCUs whose + * clocks may depend on them. + */ + + ref_32k_clk: ref_32k { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + }; + + bbl_32k_clk: bbl_32k { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + }; + + ref_13m_clk: ref_13m { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <13000000>; + }; + + var_13m_clk: var_13m { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <13000000>; + }; + + dft_19_5m_clk: dft_19_5m { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <19500000>; + }; + + ref_crystal_clk: ref_crystal { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <26000000>; + }; + + ref_52m_clk: ref_52m { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <52000000>; + }; + + var_52m_clk: var_52m { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <52000000>; + }; + + usb_otg_ahb_clk: usb_otg_ahb { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <52000000>; + }; + + ref_96m_clk: ref_96m { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <96000000>; + }; + + var_96m_clk: var_96m { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <96000000>; + }; + + ref_104m_clk: ref_104m { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <104000000>; + }; + + var_104m_clk: var_104m { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <104000000>; + }; + + ref_156m_clk: ref_156m { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <156000000>; + }; + + var_156m_clk: var_156m { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <156000000>; + }; + + root_ccu: root_ccu { + compatible = BCM21664_DT_ROOT_CCU_COMPAT; + reg = <0x35001000 0x0f00>; + #clock-cells = <1>; + clock-output-names = "frac_1m"; + }; + + aon_ccu: aon_ccu { + compatible = BCM21664_DT_AON_CCU_COMPAT; + reg = <0x35002000 0x0f00>; + #clock-cells = <1>; + clock-output-names = "hub_timer"; + }; + + slave_ccu: slave_ccu { + compatible = BCM21664_DT_SLAVE_CCU_COMPAT; + reg = <0x3e011000 0x0f00>; + #clock-cells = <1>; + clock-output-names = "uartb", + "uartb2", + "uartb3", + "bsc1", + "bsc2", + "bsc3", + "bsc4"; + }; + + master_ccu: master_ccu { + compatible = BCM21664_DT_MASTER_CCU_COMPAT; + reg = <0x3f001000 0x0f00>; + #clock-cells = <1>; + clock-output-names = "sdio1", + "sdio2", + "sdio3", + "sdio4", + "sdio1_sleep", + "sdio2_sleep", + "sdio3_sleep", + "sdio4_sleep"; + }; + }; +}; -- cgit v0.10.2 From cfdc7fa5daccd2063bd4963cddfe9a6b9eaaa61b Mon Sep 17 00:00:00 2001 From: Raashid Muhammed Date: Fri, 3 Jun 2016 11:45:38 +0530 Subject: ARM: dts: at91: at91sam9260: Remove leading zeros in OHCI node. Remove leading zeros in OHCI node for at91sam9260 based boards. Signed-off-by: Raashid Muhammed Reviewed-by: Vijay Kumar B. Signed-off-by: Alexandre Belloni diff --git a/arch/arm/boot/dts/aks-cdu.dts b/arch/arm/boot/dts/aks-cdu.dts index d9c50fb..5b1bf92 100644 --- a/arch/arm/boot/dts/aks-cdu.dts +++ b/arch/arm/boot/dts/aks-cdu.dts @@ -57,7 +57,7 @@ }; }; - usb0: ohci@00500000 { + usb0: ohci@500000 { num-ports = <2>; status = "okay"; }; diff --git a/arch/arm/boot/dts/animeo_ip.dts b/arch/arm/boot/dts/animeo_ip.dts index 0962f2f..8bcbad3 100644 --- a/arch/arm/boot/dts/animeo_ip.dts +++ b/arch/arm/boot/dts/animeo_ip.dts @@ -114,7 +114,7 @@ }; }; - usb0: ohci@00500000 { + usb0: ohci@500000 { num-ports = <2>; atmel,vbus-gpio = <&pioB 15 GPIO_ACTIVE_LOW>; status = "okay"; diff --git a/arch/arm/boot/dts/at91-foxg20.dts b/arch/arm/boot/dts/at91-foxg20.dts index 6bf873e..42a535d 100644 --- a/arch/arm/boot/dts/at91-foxg20.dts +++ b/arch/arm/boot/dts/at91-foxg20.dts @@ -128,7 +128,7 @@ }; }; - usb0: ohci@00500000 { + usb0: ohci@500000 { num-ports = <2>; status = "okay"; }; diff --git a/arch/arm/boot/dts/at91-kizbox.dts b/arch/arm/boot/dts/at91-kizbox.dts index 229e989..0e3f34e 100644 --- a/arch/arm/boot/dts/at91-kizbox.dts +++ b/arch/arm/boot/dts/at91-kizbox.dts @@ -54,7 +54,7 @@ }; }; - usb0: ohci@00500000 { + usb0: ohci@500000 { num-ports = <1>; status = "okay"; }; diff --git a/arch/arm/boot/dts/at91-qil_a9260.dts b/arch/arm/boot/dts/at91-qil_a9260.dts index 4f2eebf..5309e19 100644 --- a/arch/arm/boot/dts/at91-qil_a9260.dts +++ b/arch/arm/boot/dts/at91-qil_a9260.dts @@ -111,7 +111,7 @@ }; }; - usb0: ohci@00500000 { + usb0: ohci@500000 { num-ports = <2>; status = "okay"; }; diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi index d4884dd..af5ba31 100644 --- a/arch/arm/boot/dts/at91sam9260.dtsi +++ b/arch/arm/boot/dts/at91sam9260.dtsi @@ -1007,7 +1007,7 @@ status = "disabled"; }; - usb0: ohci@00500000 { + usb0: ohci@500000 { compatible = "atmel,at91rm9200-ohci", "usb-ohci"; reg = <0x00500000 0x100000>; interrupts = <20 IRQ_TYPE_LEVEL_HIGH 2>; diff --git a/arch/arm/boot/dts/at91sam9g20ek_common.dtsi b/arch/arm/boot/dts/at91sam9g20ek_common.dtsi index e9cc99b..1395b30 100644 --- a/arch/arm/boot/dts/at91sam9g20ek_common.dtsi +++ b/arch/arm/boot/dts/at91sam9g20ek_common.dtsi @@ -170,7 +170,7 @@ }; }; - usb0: ohci@00500000 { + usb0: ohci@500000 { num-ports = <2>; status = "okay"; }; diff --git a/arch/arm/boot/dts/ethernut5.dts b/arch/arm/boot/dts/ethernut5.dts index 2430443..298ee2f 100644 --- a/arch/arm/boot/dts/ethernut5.dts +++ b/arch/arm/boot/dts/ethernut5.dts @@ -77,7 +77,7 @@ }; }; - usb0: ohci@00500000 { + usb0: ohci@500000 { num-ports = <2>; status = "okay"; }; diff --git a/arch/arm/boot/dts/evk-pro3.dts b/arch/arm/boot/dts/evk-pro3.dts index f72969e..312d3e8 100644 --- a/arch/arm/boot/dts/evk-pro3.dts +++ b/arch/arm/boot/dts/evk-pro3.dts @@ -46,7 +46,7 @@ }; }; - usb0: ohci@00500000 { + usb0: ohci@500000 { num-ports = <2>; status = "okay"; }; diff --git a/arch/arm/boot/dts/usb_a9260_common.dtsi b/arch/arm/boot/dts/usb_a9260_common.dtsi index 9beea89..12119b5 100644 --- a/arch/arm/boot/dts/usb_a9260_common.dtsi +++ b/arch/arm/boot/dts/usb_a9260_common.dtsi @@ -90,7 +90,7 @@ }; }; - usb0: ohci@00500000 { + usb0: ohci@500000 { num-ports = <2>; status = "okay"; }; -- cgit v0.10.2 From 726b4d062e29bacfa686e036f7cd2e3919a20808 Mon Sep 17 00:00:00 2001 From: Raashid Muhammed Date: Fri, 3 Jun 2016 11:45:39 +0530 Subject: ARM: dts: at91: Add DT support for Olimex SAM9-L9260 board. sam9-l9260 is a low cost board designed by Olimex. More information is available at: https://www.olimex.com/Products/ARM/Atmel/SAM9-L9260/ Signed-off-by: Raashid Muhammed Reviewed-by: Vijay Kumar B. Acked-by: Rob Herring Signed-off-by: Alexandre Belloni diff --git a/Documentation/devicetree/bindings/arm/olimex.txt b/Documentation/devicetree/bindings/arm/olimex.txt index 007fb5c..d726aec 100644 --- a/Documentation/devicetree/bindings/arm/olimex.txt +++ b/Documentation/devicetree/bindings/arm/olimex.txt @@ -1,5 +1,9 @@ -Olimex i.MX Platforms Device Tree Bindings ------------------------------------------- +Olimex Device Tree Bindings +--------------------------- + +SAM9-L9260 Board +Required root node properties: + - compatible = "olimex,sam9-l9260", "atmel,at91sam9260"; i.MX23 Olinuxino Low Cost Board Required root node properties: diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 06b6c2d..0ee9e61 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -19,6 +19,7 @@ dtb-$(CONFIG_SOC_SAM_V4_V5) += \ usb_a9260.dtb \ at91sam9261ek.dtb \ at91sam9263ek.dtb \ + at91-sam9_l9260.dtb \ tny_a9263.dtb \ usb_a9263.dtb \ at91-foxg20.dtb \ diff --git a/arch/arm/boot/dts/at91-sam9_l9260.dts b/arch/arm/boot/dts/at91-sam9_l9260.dts new file mode 100644 index 0000000..349a461 --- /dev/null +++ b/arch/arm/boot/dts/at91-sam9_l9260.dts @@ -0,0 +1,115 @@ +/* + * at91-sam9_l9260.dts - Device Tree file for Olimex SAM9-L9260 board + * + * Copyright (C) 2016 Raashid Muhammed + * + * Licensed under GPLv2 or later. + */ +/dts-v1/; +#include "at91sam9260.dtsi" + +/ { + model = "Olimex sam9-l9260"; + compatible = "olimex,sam9-l9260", "atmel,at91sam9260", "atmel,at91sam9"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory { + reg = <0x20000000 0x4000000>; + }; + + clocks { + slow_xtal { + clock-frequency = <32768>; + }; + + main_xtal { + clock-frequency = <18432000>; + }; + }; + + ahb { + apb { + mmc0: mmc@fffa8000 { + pinctrl-0 = < + &pinctrl_board_mmc0 + &pinctrl_mmc0_clk + &pinctrl_mmc0_slot1_cmd_dat0 + &pinctrl_mmc0_slot1_dat1_3>; + status = "okay"; + + slot@1 { + reg = <1>; + bus-width = <4>; + cd-gpios = <&pioC 8 GPIO_ACTIVE_HIGH>; + wp-gpios = <&pioC 4 GPIO_ACTIVE_HIGH>; + }; + }; + + macb0: ethernet@fffc4000 { + phy-mode = "mii"; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + ethernet-phy@1 { + reg = <0x1>; + }; + }; + + spi0: spi@fffc8000 { + cs-gpios = <&pioC 11 0>, <0>, <0>, <0>; + status = "okay"; + + flash@0 { + compatible = "atmel,at45", "atmel,dataflash"; + spi-max-frequency = <15000000>; + reg = <0>; + }; + }; + + dbgu: serial@fffff200 { + status = "okay"; + }; + + pinctrl@fffff400 { + mmc0 { + pinctrl_board_mmc0: mmc0-board { + atmel,pins = + ; /* WP pin */ + }; + }; + }; + }; + + nand0: nand@40000000 { + nand-bus-width = <8>; + nand-ecc-mode = "soft"; + nand-on-flash-bbt = <1>; + status = "okay"; + }; + + usb0: ohci@500000 { + status = "okay"; + }; + + }; + + i2c@0 { + status = "okay"; + }; + + leds { + compatible = "gpio-leds"; + + b0 { + label = "b0"; + gpios = <&pioA 6 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + + }; +}; -- cgit v0.10.2 From ba3fb047fc44e90841b2dd2dbdc1d9c233258bf0 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Thu, 21 Apr 2016 09:59:05 +0200 Subject: ARM: dts: Ux500: move compatible string to chipset Move the compatible string "stericsson,ab8500" from the board definitions into the main node in the chipset file where it belongs. Signed-off-by: Linus Walleij diff --git a/arch/arm/boot/dts/ste-dbx5x0.dtsi b/arch/arm/boot/dts/ste-dbx5x0.dtsi index 6ae5683..d309314 100644 --- a/arch/arm/boot/dts/ste-dbx5x0.dtsi +++ b/arch/arm/boot/dts/ste-dbx5x0.dtsi @@ -604,6 +604,7 @@ #interrupt-cells = <2>; ab8500_gpio: ab8500-gpio { + compatible = "stericsson,ab8500-gpio"; gpio-controller; #gpio-cells = <2>; }; diff --git a/arch/arm/boot/dts/ste-href.dtsi b/arch/arm/boot/dts/ste-href.dtsi index 6d8ce15..48dc384 100644 --- a/arch/arm/boot/dts/ste-href.dtsi +++ b/arch/arm/boot/dts/ste-href.dtsi @@ -223,7 +223,6 @@ prcmu@80157000 { ab8500 { ab8500-gpio { - compatible = "stericsson,ab8500-gpio"; }; ab8500-regulators { diff --git a/arch/arm/boot/dts/ste-snowball.dts b/arch/arm/boot/dts/ste-snowball.dts index 36e84ef..37ae616 100644 --- a/arch/arm/boot/dts/ste-snowball.dts +++ b/arch/arm/boot/dts/ste-snowball.dts @@ -352,7 +352,6 @@ ab8500 { ab8500-gpio { - compatible = "stericsson,ab8500-gpio"; }; ext_regulators: ab8500-ext-regulators { -- cgit v0.10.2 From ad9454b903ab6f6b7551c1dbb1e908dd29dd63d8 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Thu, 21 Apr 2016 11:01:02 +0200 Subject: ARM: dts: Ux500: name the GPIO lines on Snowball Using the new line naming mechanism from the GPIO subsystem, name the GPIO lines on the Snowball board that are connected as GPIO on this design. Signed-off-by: Linus Walleij diff --git a/arch/arm/boot/dts/ste-snowball.dts b/arch/arm/boot/dts/ste-snowball.dts index 37ae616..b3df1c6 100644 --- a/arch/arm/boot/dts/ste-snowball.dts +++ b/arch/arm/boot/dts/ste-snowball.dts @@ -95,6 +95,70 @@ }; soc { + /* Name the GPIO muxed rails on the Snowball board */ + gpio@8012e000 { + /* GPIOs 0 - 31 */ + gpio-line-names = "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", + "AP_GPIO31"; + }; + + gpio@8012e080 { + /* GPIOs 32 - 63 */ + gpio-line-names = "USR PB", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; + }; + + gpio@8000e000 { + /* GPIOs 64 - 95 */ + gpio-line-names = "", "", "", "", "AP_GPIO68", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; + }; + + gpio@8000e100 { + /* GPIOs 128 - 159 */ + gpio-line-names = "", "", "", "", "", "", "", "", + "", "", "", "", "IRQ_LAN", "RSTn_LAN", + "USR_LED", "", "", "", "", "", "", + "", "", "AP_GPIO151", "AP_GPIO152", + "", "", "", "", "", "", ""; + }; + + gpio@8000e180 { + /* GPIOs 160 - 191 */ + gpio-line-names = "", "AP_GPIO161", "AP_GPIO162", + "ACCELEROMETER_INT1_RDY", + "ACCELEROMETER_INT2", "MAG_DRDY", + "GYRO_DRDY", "RSTn_MLC", "RSTn_SLC", + "GYRO_INT", "UART_WAKE", "GBF_RESET", + "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; + }; + + gpio@8011e000 { + /* GPIOs 192 - 223 */ + gpio-line-names = "HDTV_INTn", "", "", "", "HDTV_RST", + "", "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", "", + "WLAN_RESETN", "WLAN_IRQ", "MMC_EN", + "MMC_CD", "", "", "", "", ""; + }; + + gpio@8011e080 { + /* GPIOs 224 - 255 */ + gpio-line-names = "", "", "", "", "SD_SEL", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; + }; + usb_per5@a03e0000 { pinctrl-names = "default", "sleep"; pinctrl-0 = <&musb_default_mode>; @@ -352,6 +416,25 @@ ab8500 { ab8500-gpio { + /* + * AB8500 GPIOs are numbered starting from 1, so the first + * index 0 is what in the datasheet is called "GPIO1", and + * the second is "GPIO2" and so forth. Confusingly, the + * Snowball schematic then names the "GPIO2" line "PM_GPIO1". + * while later naming "GPIO4" as "PM_GPIO4". + */ + gpio-line-names = "", /* AB8500 GPIO1 */ + "PM_GPIO1", /* AB8500 GPIO2 */ + "WLAN_CLK_REQ", /* AB8500 GPIO3 */ + "PM_GPIO4", /* AB8500 GPIO4 */ + "", "", "", "", "", "", "", "", "", "", "", + "EN_3V6", /* AB8500 GPIO16 */ + "", "", "", "" ,"", "", "", "", "", + "EN_3V3", /* AB8500 GPIO26 */ + "", "", "", "", "", "", "", "", "", "", "", "", "", + "PM_GPIO40", /* AB8500 GPIO40 */ + "PM_GPIO41", /* AB8500 GPIO41 */ + "PM_GPIO42"; /* AB8500 GPIO42 */ }; ext_regulators: ab8500-ext-regulators { -- cgit v0.10.2 From ac07a4e02899b332350b95ee190014c88271eaaa Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Thu, 21 Apr 2016 15:18:47 +0200 Subject: ARM: dts: UX500: name the GPIO lines on HREFv60plus Using the new line naming mechanism from the GPIO subsystem, name the GPIO lines on the HREFv60plus board that are connected as GPIO on this design. Signed-off-by: Linus Walleij diff --git a/arch/arm/boot/dts/ste-hrefv60plus.dtsi b/arch/arm/boot/dts/ste-hrefv60plus.dtsi index 45d7af3..7187676 100644 --- a/arch/arm/boot/dts/ste-hrefv60plus.dtsi +++ b/arch/arm/boot/dts/ste-hrefv60plus.dtsi @@ -18,6 +18,126 @@ compatible = "st-ericsson,hrefv60+", "st-ericsson,u8500"; soc { + /* Name the GPIO muxed rails on the HREF boards */ + gpio@8012e000 { + /* GPIOs 0 - 31 */ + gpio-line-names = + /* GPIO0,1 used for UART0 BT RX/TX */ + "", "", + "UART_WAKE", + "BT_WAKE", + "", + "SDMMC_1V8_3V_SEL", + "FLASH_LED_SYNC (FLASH_CTRL_0)", + "XENON_READY (FLASH_CTRL_1)", + "", "", "", "", "", "", "", "", + "", "", "", "", + "", + "FLASH_LED_EN (FLASH_CTRL_3)", + "", "", + "", "", "", "", "", + /* Used by UART2 (console) */ + "", "", + "MAGNETOMETER_INT"; + }; + + gpio@8012e080 { + /* GPIOs 32 - 63 */ + gpio-line-names = + "MAGNETOMETER_DRDY", + "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; + }; + + gpio@8000e000 { + /* GPIOs 64 - 95 */ + gpio-line-names = "XENON_EN2 (FLASH_CTRL_4)", + "DISP1_RST", + "DISP2_RST", + "TOUCH_INT2", + "LCD_VSI0_A", + "LCD_VSI1_A", + /* GPIO 70-77 used for ETM */ + "", "", "", "", "", "", "", "", + /* GPIO 78-81 used for YCBCR */ + "", "", "", "", + "ACCELEROMETER_INT1_RDY", + "ACCELEROMETER_INT2", + "TOUCH_INT", + "WLAN_ENA", + "", "", "", "", "", + "FORCE_SENSING_INT", + "FORCE_SENSING_RESET", + "", "", + "SDMMC_CD"; + }; + + gpio@8000e080 { + /* GPIOs 96 - 127 */ + gpio-line-names = "", + "FORCE_SENSING_WU", + "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; + }; + + gpio@8000e100 { + /* GPIOs 128 - 159 */ + gpio-line-names = "", "", "", "", "", "", "", "", + "", "", "", + "DIPRO_INT", /* GPIO139 */ + "XSHUTDOWN_SECONDARY_SENSOR", + "XSHUTDOWN_PRIMARY_SENSOR", + "NFC_RST (NFC_CTRL_", + "TOUCH_RST", + "NFC_IRQ (NFC_CTRL_1)", + "HAL_SW", + "TOUCH_RST2", + "", "", + "VAUDIO_HF_EN", /* GPIO149 */ + "", "", "", "", "", "", "", "", "", ""; + }; + + gpio@8000e180 { + /* GPIOs 160 - 191 */ + gpio-line-names = "", "", "", "", "", "", "", "", + "", + "SDMMC_EN", + "XENON_CHARGE (FLASH_CONTROL_5)", + "GBF_ENA_RESET", + "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; + }; + + gpio@8011e000 { + /* GPIOs 192 - 223 */ + gpio-line-names = "HDTV_INTN", + "", "", "", + "HDTV_RSTN", + "", "", "", + "", /* GPIO200 */ + "", "", "", "", "", "", "", + /* GPIO208-216 used for WGBF_MC1 */ + "", "", "", "", "", "", "", "", "", + "SW_FRONT_PROXIMITY", /* GPIO217 */ + "KPD_CTRL_INT", /* Keypad controller */ + "", "", "", "", ""; + }; + + gpio@8011e080 { + /* GPIOs 224 - 255 */ + gpio-line-names = "", "", + "HSIT_ACWAKE0", + "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; + }; + // External Micro SD slot sdi0_per1@80126000 { cd-gpios = <&gpio2 31 GPIO_ACTIVE_HIGH>; // 95 -- cgit v0.10.2 From c80a3f69ddefdb5c87f7889ba8910906ca019de2 Mon Sep 17 00:00:00 2001 From: Marek Szyprowski Date: Tue, 7 Jun 2016 14:03:36 +0200 Subject: ARM: dts: exynos: replace hardcoded reserved memory ranges with auto-allocated ones Generic reserved memory regions bindings allow to automatically allocate region of given parameters (alignment and size), so use this feature instead of the hardcoded values, which had no dependency on the real hardware. This patch also increases "left" region from 8MiB to 16MiB to make the codec really usable with nowadays steams (with 8MiB reserved region it was not even possible to decode 480p H264 video). Signed-off-by: Marek Szyprowski Reviewed-by: Javier Martinez Canillas Tested-by: Javier Martinez Canillas Signed-off-by: Krzysztof Kozlowski diff --git a/arch/arm/boot/dts/exynos-mfc-reserved-memory.dtsi b/arch/arm/boot/dts/exynos-mfc-reserved-memory.dtsi index c4d063a..da3ced9 100644 --- a/arch/arm/boot/dts/exynos-mfc-reserved-memory.dtsi +++ b/arch/arm/boot/dts/exynos-mfc-reserved-memory.dtsi @@ -14,16 +14,18 @@ #size-cells = <1>; ranges; - mfc_left: region@51000000 { + mfc_left: region_mfc_left { compatible = "shared-dma-pool"; no-map; - reg = <0x51000000 0x800000>; + size = <0x1000000>; + alignment = <0x100000>; }; - mfc_right: region@43000000 { + mfc_right: region_mfc_right { compatible = "shared-dma-pool"; no-map; - reg = <0x43000000 0x800000>; + size = <0x800000>; + alignment = <0x100000>; }; }; }; -- cgit v0.10.2 From 4ceaa148b05a3a2d475592f9281b9cbb13882e3c Mon Sep 17 00:00:00 2001 From: Marek Szyprowski Date: Tue, 7 Jun 2016 14:03:37 +0200 Subject: ARM: dts: exynos: move MFC reserved memory regions from boards to .dtsi This patch moves assigning reserved memory regions from each board dts to common exynos-mfc-reserved-memory.dtsi file, where those regions are defined. Signed-off-by: Marek Szyprowski Reviewed-by: Javier Martinez Canillas Tested-by: Javier Martinez Canillas Signed-off-by: Krzysztof Kozlowski diff --git a/arch/arm/boot/dts/exynos-mfc-reserved-memory.dtsi b/arch/arm/boot/dts/exynos-mfc-reserved-memory.dtsi index da3ced9..f78c14c 100644 --- a/arch/arm/boot/dts/exynos-mfc-reserved-memory.dtsi +++ b/arch/arm/boot/dts/exynos-mfc-reserved-memory.dtsi @@ -29,3 +29,7 @@ }; }; }; + +&mfc { + memory-region = <&mfc_left>, <&mfc_right>; +}; diff --git a/arch/arm/boot/dts/exynos4210-origen.dts b/arch/arm/boot/dts/exynos4210-origen.dts index f5e4eb2..07a00dd 100644 --- a/arch/arm/boot/dts/exynos4210-origen.dts +++ b/arch/arm/boot/dts/exynos4210-origen.dts @@ -289,7 +289,6 @@ }; &mfc { - memory-region = <&mfc_left>, <&mfc_right>; status = "okay"; }; diff --git a/arch/arm/boot/dts/exynos4210-smdkv310.dts b/arch/arm/boot/dts/exynos4210-smdkv310.dts index de917f0..2fab072 100644 --- a/arch/arm/boot/dts/exynos4210-smdkv310.dts +++ b/arch/arm/boot/dts/exynos4210-smdkv310.dts @@ -134,7 +134,6 @@ }; &mfc { - memory-region = <&mfc_left>, <&mfc_right>; status = "okay"; }; diff --git a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi index 276ac9a..1f36878 100644 --- a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi +++ b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi @@ -501,7 +501,6 @@ }; &mfc { - memory-region = <&mfc_left>, <&mfc_right>; status = "okay"; }; diff --git a/arch/arm/boot/dts/exynos4412-origen.dts b/arch/arm/boot/dts/exynos4412-origen.dts index cd363d7..35988a6 100644 --- a/arch/arm/boot/dts/exynos4412-origen.dts +++ b/arch/arm/boot/dts/exynos4412-origen.dts @@ -467,7 +467,6 @@ }; &mfc { - memory-region = <&mfc_left>, <&mfc_right>; status = "okay"; }; diff --git a/arch/arm/boot/dts/exynos4412-smdk4412.dts b/arch/arm/boot/dts/exynos4412-smdk4412.dts index 9b6d561..d4f9383 100644 --- a/arch/arm/boot/dts/exynos4412-smdk4412.dts +++ b/arch/arm/boot/dts/exynos4412-smdk4412.dts @@ -113,7 +113,6 @@ }; &mfc { - memory-region = <&mfc_left>, <&mfc_right>; status = "okay"; }; diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts index 39940f4..ea70603 100644 --- a/arch/arm/boot/dts/exynos5250-arndale.dts +++ b/arch/arm/boot/dts/exynos5250-arndale.dts @@ -516,10 +516,6 @@ status = "okay"; }; -&mfc { - memory-region = <&mfc_left>, <&mfc_right>; -}; - &mmc_0 { status = "okay"; num-slots = <1>; diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts index 9fac874..381af13 100644 --- a/arch/arm/boot/dts/exynos5250-smdk5250.dts +++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts @@ -344,10 +344,6 @@ status = "okay"; }; -&mfc { - memory-region = <&mfc_left>, <&mfc_right>; -}; - &mmc_0 { status = "okay"; num-slots = <1>; diff --git a/arch/arm/boot/dts/exynos5250-spring.dts b/arch/arm/boot/dts/exynos5250-spring.dts index 784130b..44f4292 100644 --- a/arch/arm/boot/dts/exynos5250-spring.dts +++ b/arch/arm/boot/dts/exynos5250-spring.dts @@ -425,10 +425,6 @@ status = "okay"; }; -&mfc { - memory-region = <&mfc_left>, <&mfc_right>; -}; - &mmc_0 { status = "okay"; num-slots = <1>; diff --git a/arch/arm/boot/dts/exynos5420-arndale-octa.dts b/arch/arm/boot/dts/exynos5420-arndale-octa.dts index b8b5f3a..39a3b81 100644 --- a/arch/arm/boot/dts/exynos5420-arndale-octa.dts +++ b/arch/arm/boot/dts/exynos5420-arndale-octa.dts @@ -347,10 +347,6 @@ }; }; -&mfc { - memory-region = <&mfc_left>, <&mfc_right>; -}; - &mmc_0 { status = "okay"; broken-cd; diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts b/arch/arm/boot/dts/exynos5420-peach-pit.dts index d530b4f..2f16f33 100644 --- a/arch/arm/boot/dts/exynos5420-peach-pit.dts +++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts @@ -695,10 +695,6 @@ status = "okay"; }; -&mfc { - memory-region = <&mfc_left>, <&mfc_right>; -}; - &mmc_0 { status = "okay"; num-slots = <1>; diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts b/arch/arm/boot/dts/exynos5420-smdk5420.dts index 5206f41..ed8f342 100644 --- a/arch/arm/boot/dts/exynos5420-smdk5420.dts +++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts @@ -355,10 +355,6 @@ }; }; -&mfc { - memory-region = <&mfc_left>, <&mfc_right>; -}; - &mmc_0 { status = "okay"; broken-cd; diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi index 7c2335f..530883c 100644 --- a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi +++ b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi @@ -406,10 +406,6 @@ }; }; -&mfc { - memory-region = <&mfc_left>, <&mfc_right>; -}; - &mmc_0 { status = "okay"; mmc-pwrseq = <&emmc_pwrseq>; diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts b/arch/arm/boot/dts/exynos5800-peach-pi.dts index 1f73596..6085b88 100644 --- a/arch/arm/boot/dts/exynos5800-peach-pi.dts +++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts @@ -670,10 +670,6 @@ status = "okay"; }; -&mfc { - memory-region = <&mfc_left>, <&mfc_right>; -}; - &mmc_0 { status = "okay"; num-slots = <1>; -- cgit v0.10.2 From 9f7d27fa1b0b3685471a1a34223a3475943f53e4 Mon Sep 17 00:00:00 2001 From: Marek Szyprowski Date: Tue, 7 Jun 2016 14:03:38 +0200 Subject: ARM: dts: exynos: enable MFC device for all boards MFC device can be used without any external hardware dependencies (when IOMMU is enabled), so it can be enabled by default (like it has been already done for Exynos 542x platforms). This unifies handling of this device for Exynos3250, Exynos4 and Exynos542x platforms. Board can still include exynos-mfc-reserved-memory.dtsi to enable using this device without IOMMU being enabled. Signed-off-by: Marek Szyprowski Reviewed-by: Javier Martinez Canillas Signed-off-by: Krzysztof Kozlowski diff --git a/arch/arm/boot/dts/exynos3250-rinato.dts b/arch/arm/boot/dts/exynos3250-rinato.dts index e4228195..a9218136 100644 --- a/arch/arm/boot/dts/exynos3250-rinato.dts +++ b/arch/arm/boot/dts/exynos3250-rinato.dts @@ -632,10 +632,6 @@ status = "okay"; }; -&mfc { - status = "okay"; -}; - &jpeg { status = "okay"; }; diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi index 62f3dcd..70e3ace 100644 --- a/arch/arm/boot/dts/exynos3250.dtsi +++ b/arch/arm/boot/dts/exynos3250.dtsi @@ -431,7 +431,6 @@ clocks = <&cmu CLK_MFC>, <&cmu CLK_SCLK_MFC>; power-domains = <&pd_mfc>; iommus = <&sysmmu_mfc>; - status = "disabled"; }; sysmmu_mfc: sysmmu@13620000 { diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi index ca8f3e3..32f22e1 100644 --- a/arch/arm/boot/dts/exynos4.dtsi +++ b/arch/arm/boot/dts/exynos4.dtsi @@ -428,7 +428,6 @@ clock-names = "mfc", "sclk_mfc"; iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>; iommu-names = "left", "right"; - status = "disabled"; }; serial_0: serial@13800000 { diff --git a/arch/arm/boot/dts/exynos4210-origen.dts b/arch/arm/boot/dts/exynos4210-origen.dts index 07a00dd..be2751e 100644 --- a/arch/arm/boot/dts/exynos4210-origen.dts +++ b/arch/arm/boot/dts/exynos4210-origen.dts @@ -288,10 +288,6 @@ }; }; -&mfc { - status = "okay"; -}; - &sdhci_0 { bus-width = <4>; pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_cd>; diff --git a/arch/arm/boot/dts/exynos4210-smdkv310.dts b/arch/arm/boot/dts/exynos4210-smdkv310.dts index 2fab072..847fae3 100644 --- a/arch/arm/boot/dts/exynos4210-smdkv310.dts +++ b/arch/arm/boot/dts/exynos4210-smdkv310.dts @@ -133,10 +133,6 @@ }; }; -&mfc { - status = "okay"; -}; - &pinctrl_1 { keypad_rows: keypad-rows { samsung,pins = "gpx2-0", "gpx2-1"; diff --git a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi index 1f36878..c32a62e 100644 --- a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi +++ b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi @@ -500,10 +500,6 @@ clock-names = "iis", "i2s_opclk0", "i2s_opclk1"; }; -&mfc { - status = "okay"; -}; - &mixer { status = "okay"; }; diff --git a/arch/arm/boot/dts/exynos4412-origen.dts b/arch/arm/boot/dts/exynos4412-origen.dts index 35988a6..a5f1476 100644 --- a/arch/arm/boot/dts/exynos4412-origen.dts +++ b/arch/arm/boot/dts/exynos4412-origen.dts @@ -466,10 +466,6 @@ }; }; -&mfc { - status = "okay"; -}; - &mshc_0 { pinctrl-0 = <&sd4_clk &sd4_cmd &sd4_bus4 &sd4_bus8>; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/exynos4412-smdk4412.dts b/arch/arm/boot/dts/exynos4412-smdk4412.dts index d4f9383..231ffbd 100644 --- a/arch/arm/boot/dts/exynos4412-smdk4412.dts +++ b/arch/arm/boot/dts/exynos4412-smdk4412.dts @@ -112,10 +112,6 @@ }; }; -&mfc { - status = "okay"; -}; - &pinctrl_1 { keypad_rows: keypad-rows { samsung,pins = "gpx2-0", "gpx2-1", "gpx2-2"; -- cgit v0.10.2 From efb6672935894e19e30227b2fcc64546b70342ea Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Tue, 3 May 2016 08:59:01 -0500 Subject: ARM: dts: socfpga: add ethernet alias on Arria10 Without having an ethernet alias, ethernet will have a random MAC address, versus take an address that was provided from the bootloader. Signed-off-by: Dinh Nguyen diff --git a/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi b/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi index 567df98..ab33ee3 100644 --- a/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi +++ b/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi @@ -20,6 +20,10 @@ model = "Altera SOCFPGA Arria 10"; compatible = "altr,socfpga-arria10", "altr,socfpga"; + aliases { + ethernet0 = &gmac0; + }; + chosen { bootargs = "earlyprintk"; stdout-path = "serial1:115200n8"; -- cgit v0.10.2 From b65c0efa3508c01116c3ee24a6c37a158f2cb03a Mon Sep 17 00:00:00 2001 From: Matthew Gerlach Date: Thu, 12 May 2016 10:24:42 -0700 Subject: ARM: dts: socfpga: fix definitions of serial console The notion of which uart instance is serial0 or serial1 is board specific rather than generic to the chip. This patch removes the serial aliases from generic chip dtsi and adds an appropriate alias to the board specific dtsi. By making the alias for serial0 point to uart1 for the arria10_socdk, the linux boot command line supports specifying console=ttyS0,115200 for backwards compatibility, and it supports not specifying the console at all. Signed-off-by: Matthew Gerlach Signed-off-by: Dinh Nguyen diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi index 21f6c3c..1c4fc27 100644 --- a/arch/arm/boot/dts/socfpga_arria10.dtsi +++ b/arch/arm/boot/dts/socfpga_arria10.dtsi @@ -22,11 +22,6 @@ #address-cells = <1>; #size-cells = <1>; - aliases { - serial0 = &uart0; - serial1 = &uart1; - }; - cpus { #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi b/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi index ab33ee3..8e3a4ad 100644 --- a/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi +++ b/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi @@ -22,11 +22,12 @@ aliases { ethernet0 = &gmac0; + serial0 = &uart1; }; chosen { bootargs = "earlyprintk"; - stdout-path = "serial1:115200n8"; + stdout-path = "serial0:115200n8"; }; memory { -- cgit v0.10.2 From 59e13aac820cc1e3ca45778f1618070f6e0e0ae2 Mon Sep 17 00:00:00 2001 From: Murali Karicheri Date: Wed, 8 Jun 2016 16:06:43 -0700 Subject: ARM: dts: keystone: remove bogus IO resource entry from PCI binding The PCI DT bindings contain a bogus entry for IO space which is not supported on Keystone. The current bogus entry has an invalid size and throws following error during boot. [0.420713] keystone-pcie 21021000.pcie: error -22: failed to map resource [io 0x0000-0x400000003fff] So remove it from the dts. While at it also add a bus-range value that eliminates following log at boot up. [0.420659] No bus range found for /soc/pcie@21020000, using [bus 00-ff] Signed-off-by: Murali Karicheri Signed-off-by: Santosh Shilimkar diff --git a/arch/arm/boot/dts/keystone-k2e.dtsi b/arch/arm/boot/dts/keystone-k2e.dtsi index 96b349f..5374c9a 100644 --- a/arch/arm/boot/dts/keystone-k2e.dtsi +++ b/arch/arm/boot/dts/keystone-k2e.dtsi @@ -96,12 +96,13 @@ #address-cells = <3>; #size-cells = <2>; reg = <0x21021000 0x2000>, <0x21020000 0x1000>, <0x02620128 4>; - ranges = <0x81000000 0 0 0x23260000 0x4000 0x4000 - 0x82000000 0 0x60000000 0x60000000 0 0x10000000>; + ranges = <0x82000000 0 0x60000000 0x60000000 + 0 0x10000000>; status = "disabled"; device_type = "pci"; num-lanes = <2>; + bus-range = <0x00 0xff>; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 7>; diff --git a/arch/arm/boot/dts/keystone.dtsi b/arch/arm/boot/dts/keystone.dtsi index e34b226..f627a1c 100644 --- a/arch/arm/boot/dts/keystone.dtsi +++ b/arch/arm/boot/dts/keystone.dtsi @@ -294,12 +294,13 @@ #address-cells = <3>; #size-cells = <2>; reg = <0x21801000 0x2000>, <0x21800000 0x1000>, <0x02620128 4>; - ranges = <0x81000000 0 0 0x23250000 0 0x4000 - 0x82000000 0 0x50000000 0x50000000 0 0x10000000>; + ranges = <0x82000000 0 0x50000000 0x50000000 + 0 0x10000000>; status = "disabled"; device_type = "pci"; num-lanes = <2>; + bus-range = <0x00 0xff>; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 7>; -- cgit v0.10.2 From a9e5b20dd9e7e2b3cf742431d7eb446d0e9a6aa1 Mon Sep 17 00:00:00 2001 From: Murali Karicheri Date: Wed, 8 Jun 2016 16:06:43 -0700 Subject: ARM: dts: keystone: add interrupt property to PCI controller bindings Now that Keystone PCIe controller supports error interrupt handling add interrupt property to PCI controller DT bindings to enable error interrupt handling. Signed-off-by: Murali Karicheri Signed-off-by: Santosh Shilimkar diff --git a/arch/arm/boot/dts/keystone-k2e.dtsi b/arch/arm/boot/dts/keystone-k2e.dtsi index 5374c9a..9a51b8c 100644 --- a/arch/arm/boot/dts/keystone-k2e.dtsi +++ b/arch/arm/boot/dts/keystone-k2e.dtsi @@ -104,6 +104,8 @@ num-lanes = <2>; bus-range = <0x00 0xff>; + /* error interrupt */ + interrupts = ; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 7>; interrupt-map = <0 0 0 1 &pcie_intc1 0>, /* INT A */ diff --git a/arch/arm/boot/dts/keystone.dtsi b/arch/arm/boot/dts/keystone.dtsi index f627a1c..e23f46d 100644 --- a/arch/arm/boot/dts/keystone.dtsi +++ b/arch/arm/boot/dts/keystone.dtsi @@ -302,6 +302,8 @@ num-lanes = <2>; bus-range = <0x00 0xff>; + /* error interrupt */ + interrupts = ; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 7>; interrupt-map = <0 0 0 1 &pcie_intc0 0>, /* INT A */ -- cgit v0.10.2 From a6bada65dac6556db3ce3d95822c90c0cfee691c Mon Sep 17 00:00:00 2001 From: Keerthy Date: Wed, 8 Jun 2016 16:06:44 -0700 Subject: ARM: dts: keystone-k2l: Add pinctrl node Add pinctrl node and populate the pinctrl registers with the default values. Signed-off-by: Keerthy Signed-off-by: Santosh Shilimkar diff --git a/arch/arm/boot/dts/keystone-k2l.dtsi b/arch/arm/boot/dts/keystone-k2l.dtsi index ff22ffc..2ee3d0a 100644 --- a/arch/arm/boot/dts/keystone-k2l.dtsi +++ b/arch/arm/boot/dts/keystone-k2l.dtsi @@ -54,6 +54,155 @@ interrupts = ; }; + k2l_pmx: pinmux@02620690 { + compatible = "pinctrl-single"; + reg = <0x02620690 0xc>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-single,bit-per-mux; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x1>; + status = "disabled"; + + uart3_emifa_pins: pinmux_uart3_emifa_pins { + pinctrl-single,bits = < + /* UART3_EMIFA_SEL */ + 0x0 0x0 0xc0 + >; + }; + + uart2_emifa_pins: pinmux_uart2_emifa_pins { + pinctrl-single,bits = < + /* UART2_EMIFA_SEL */ + 0x0 0x0 0x30 + >; + }; + + uart01_spi2_pins: pinmux_uart01_spi2_pins { + pinctrl-single,bits = < + /* UART01_SPI2_SEL */ + 0x0 0x0 0x4 + >; + }; + + dfesync_rp1_pins: pinmux_dfesync_rp1_pins{ + pinctrl-single,bits = < + /* DFESYNC_RP1_SEL */ + 0x0 0x0 0x2 + >; + }; + + avsif_pins: pinmux_avsif_pins { + pinctrl-single,bits = < + /* AVSIF_SEL */ + 0x0 0x0 0x1 + >; + }; + + gpio_emu_pins: pinmux_gpio_emu_pins { + pinctrl-single,bits = < + /* + * GPIO_EMU_SEL[31]: 0-GPIO31, 1-EMU33 + * GPIO_EMU_SEL[30]: 0-GPIO30, 1-EMU32 + * GPIO_EMU_SEL[29]: 0-GPIO29, 1-EMU31 + * GPIO_EMU_SEL[28]: 0-GPIO28, 1-EMU30 + * GPIO_EMU_SEL[27]: 0-GPIO27, 1-EMU29 + * GPIO_EMU_SEL[26]: 0-GPIO26, 1-EMU28 + * GPIO_EMU_SEL[25]: 0-GPIO25, 1-EMU27 + * GPIO_EMU_SEL[24]: 0-GPIO24, 1-EMU26 + * GPIO_EMU_SEL[23]: 0-GPIO23, 1-EMU25 + * GPIO_EMU_SEL[22]: 0-GPIO22, 1-EMU24 + * GPIO_EMU_SEL[21]: 0-GPIO21, 1-EMU23 + * GPIO_EMU_SEL[20]: 0-GPIO20, 1-EMU22 + * GPIO_EMU_SEL[19]: 0-GPIO19, 1-EMU21 + * GPIO_EMU_SEL[18]: 0-GPIO18, 1-EMU20 + * GPIO_EMU_SEL[17]: 0-GPIO17, 1-EMU19 + */ + 0x4 0x0000 0xFFFE0000 + >; + }; + + gpio_timio_pins: pinmux_gpio_timio_pins { + pinctrl-single,bits = < + /* + * GPIO_TIMIO_SEL[15]: 0-GPIO15, 1-TIMO7 + * GPIO_TIMIO_SEL[14]: 0-GPIO14, 1-TIMO6 + * GPIO_TIMIO_SEL[13]: 0-GPIO13, 1-TIMO5 + * GPIO_TIMIO_SEL[12]: 0-GPIO12, 1-TIMO4 + * GPIO_TIMIO_SEL[11]: 0-GPIO11, 1-TIMO3 + * GPIO_TIMIO_SEL[10]: 0-GPIO10, 1-TIMO2 + * GPIO_TIMIO_SEL[9]: 0-GPIO9, 1-TIMI7 + * GPIO_TIMIO_SEL[8]: 0-GPIO8, 1-TIMI6 + * GPIO_TIMIO_SEL[7]: 0-GPIO7, 1-TIMI5 + * GPIO_TIMIO_SEL[6]: 0-GPIO6, 1-TIMI4 + * GPIO_TIMIO_SEL[5]: 0-GPIO5, 1-TIMI3 + * GPIO_TIMIO_SEL[4]: 0-GPIO4, 1-TIMI2 + */ + 0x4 0x0 0xFFF0 + >; + }; + + gpio_spi2cs_pins: pinmux_gpio_spi2cs_pins { + pinctrl-single,bits = < + /* + * GPIO_SPI2CS_SEL[3]: 0-GPIO3, 1-SPI2CS4 + * GPIO_SPI2CS_SEL[2]: 0-GPIO2, 1-SPI2CS3 + * GPIO_SPI2CS_SEL[1]: 0-GPIO1, 1-SPI2CS2 + * GPIO_SPI2CS_SEL[0]: 0-GPIO0, 1-SPI2CS1 + */ + 0x4 0x0 0xF + >; + }; + + gpio_dfeio_pins: pinmux_gpio_dfeio_pins { + pinctrl-single,bits = < + /* + * GPIO_DFEIO_SEL[31]: 0-DFEIO17, 1-GPIO63 + * GPIO_DFEIO_SEL[30]: 0-DFEIO16, 1-GPIO62 + * GPIO_DFEIO_SEL[29]: 0-DFEIO15, 1-GPIO61 + * GPIO_DFEIO_SEL[28]: 0-DFEIO14, 1-GPIO60 + * GPIO_DFEIO_SEL[27]: 0-DFEIO13, 1-GPIO59 + * GPIO_DFEIO_SEL[26]: 0-DFEIO12, 1-GPIO58 + * GPIO_DFEIO_SEL[25]: 0-DFEIO11, 1-GPIO57 + * GPIO_DFEIO_SEL[24]: 0-DFEIO10, 1-GPIO56 + * GPIO_DFEIO_SEL[23]: 0-DFEIO9, 1-GPIO55 + * GPIO_DFEIO_SEL[22]: 0-DFEIO8, 1-GPIO54 + * GPIO_DFEIO_SEL[21]: 0-DFEIO7, 1-GPIO53 + * GPIO_DFEIO_SEL[20]: 0-DFEIO6, 1-GPIO52 + * GPIO_DFEIO_SEL[19]: 0-DFEIO5, 1-GPIO51 + * GPIO_DFEIO_SEL[18]: 0-DFEIO4, 1-GPIO50 + * GPIO_DFEIO_SEL[17]: 0-DFEIO3, 1-GPIO49 + * GPIO_DFEIO_SEL[16]: 0-DFEIO2, 1-GPIO48 + */ + 0x8 0x0 0xFFFF0000 + >; + }; + + gpio_emifa_pins: pinmux_gpio_emifa_pins { + pinctrl-single,bits = < + /* + * GPIO_EMIFA_SEL[15]: 0-EMIFA17, 1-GPIO47 + * GPIO_EMIFA_SEL[14]: 0-EMIFA16, 1-GPIO46 + * GPIO_EMIFA_SEL[13]: 0-EMIFA15, 1-GPIO45 + * GPIO_EMIFA_SEL[12]: 0-EMIFA14, 1-GPIO44 + * GPIO_EMIFA_SEL[11]: 0-EMIFA13, 1-GPIO43 + * GPIO_EMIFA_SEL[10]: 0-EMIFA10, 1-GPIO42 + * GPIO_EMIFA_SEL[9]: 0-EMIFA9, 1-GPIO41 + * GPIO_EMIFA_SEL[8]: 0-EMIFA8, 1-GPIO40 + * GPIO_EMIFA_SEL[7]: 0-EMIFA7, 1-GPIO39 + * GPIO_EMIFA_SEL[6]: 0-EMIFA6, 1-GPIO38 + * GPIO_EMIFA_SEL[5]: 0-EMIFA5, 1-GPIO37 + * GPIO_EMIFA_SEL[4]: 0-EMIFA4, 1-GPIO36 + * GPIO_EMIFA_SEL[3]: 0-EMIFA3, 1-GPIO35 + * GPIO_EMIFA_SEL[2]: 0-EMIFA2, 1-GPIO34 + * GPIO_EMIFA_SEL[1]: 0-EMIFA1, 1-GPIO33 + * GPIO_EMIFA_SEL[0]: 0-EMIFA0, 1-GPIO32 + */ + 0x8 0x0 0xFFFF + >; + }; + }; + dspgpio0: keystone_dsp_gpio@02620240 { compatible = "ti,keystone-dsp-gpio"; gpio-controller; -- cgit v0.10.2 From 7a25d3965726768b0eba9222138d9d47d050bbe1 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Thu, 9 Jun 2016 10:03:36 +0200 Subject: ARM: dts: rockchip: rename i2s model for Veyron devices Commit 6c42db30d8c8 introduced audio support based on alsa ucm profiles taken from the ChromeOS userspace. Both in the kernel as well as alsa they were named (and matched against) ROCKCHIP-I2S. Audio profiles are very much board-specific and hogging the ROCKCHIP-I2S name would make it harder for future boards and also is misleading. For Veyron boards the audio setup is similar over all variants, so VEYRON-I2S is a more suitable name. This rename also was merged into the alsa ucm profile so both userspace and kernel match and the old naming was never released in any alsa or kernel release. Fixes: 6c42db30d8c8 ("ARM: dts: rockchip: Add shared file for audio on rk3288-veyron boards") Signed-off-by: Heiko Stuebner diff --git a/arch/arm/boot/dts/rk3288-veyron-analog-audio.dtsi b/arch/arm/boot/dts/rk3288-veyron-analog-audio.dtsi index 3d57c05..6d105914 100644 --- a/arch/arm/boot/dts/rk3288-veyron-analog-audio.dtsi +++ b/arch/arm/boot/dts/rk3288-veyron-analog-audio.dtsi @@ -14,7 +14,7 @@ compatible = "rockchip,rockchip-audio-max98090"; pinctrl-names = "default"; pinctrl-0 = <&mic_det>, <&hp_det>; - rockchip,model = "ROCKCHIP-I2S"; + rockchip,model = "VEYRON-I2S"; rockchip,i2s-controller = <&i2s>; rockchip,audio-codec = <&max98090>; rockchip,hp-det-gpios = <&gpio6 5 GPIO_ACTIVE_HIGH>; -- cgit v0.10.2 From d6535e6a33168cc0bd49ac0712c32b64292bc1fb Mon Sep 17 00:00:00 2001 From: Damien Riegel Date: Thu, 9 Jun 2016 10:46:49 -0400 Subject: ARM: dts: TS-4800: add FPGA's IRQ controller support Enable FPGA's IRQ controller. It is in charge of dispatching interrupts generated by IPs in the FPGA. The SoC is notified that an interrupt occurred through a GPIO. Signed-off-by: Damien Riegel Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/imx51-ts4800.dts b/arch/arm/boot/dts/imx51-ts4800.dts index 0ff76a1..0e80fb7 100644 --- a/arch/arm/boot/dts/imx51-ts4800.dts +++ b/arch/arm/boot/dts/imx51-ts4800.dts @@ -165,6 +165,17 @@ reg = <0x12000 0x1000>; syscon = <&syscon 0x10 6>; }; + + fpga_irqc: fpga-irqc@15000 { + compatible = "technologic,ts4800-irqc"; + reg = <0x15000 0x1000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_interrupt_fpga>; + interrupt-parent = <&gpio2>; + interrupts= <9 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <1>; + }; }; }; @@ -228,6 +239,12 @@ >; }; + pinctrl_interrupt_fpga: fpgaicgrp { + fsl,pins = < + MX51_PAD_EIM_D27__GPIO2_9 0xe5 + >; + }; + pinctrl_lcd: lcdgrp { fsl,pins = < MX51_PAD_DISP1_DAT0__DISP1_DAT0 0x5 -- cgit v0.10.2 From a059ee7910714e4e637d43324d5b1aff3a0350d9 Mon Sep 17 00:00:00 2001 From: Damien Riegel Date: Thu, 9 Jun 2016 10:46:50 -0400 Subject: ARM: dts: TS-4800: add CAN support This enables support for the CAN controller located in the FPGA. Signed-off-by: Damien Riegel Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/imx51-ts4800.dts b/arch/arm/boot/dts/imx51-ts4800.dts index 0e80fb7..984c71b 100644 --- a/arch/arm/boot/dts/imx51-ts4800.dts +++ b/arch/arm/boot/dts/imx51-ts4800.dts @@ -176,6 +176,16 @@ interrupt-controller; #interrupt-cells = <1>; }; + + can@1a000 { + compatible = "technologic,sja1000"; + reg = <0x1a000 0x100>; + interrupt-parent = <&fpga_irqc>; + interrupts = <1>; + reg-io-width = <2>; + nxp,tx-output-config = <0x06>; + nxp,external-clock-frequency = <24000000>; + }; }; }; -- cgit v0.10.2 From fb25225919c43ced501b8aff366f40575493b515 Mon Sep 17 00:00:00 2001 From: Vitaly Andrianov Date: Thu, 9 Jun 2016 09:40:21 -0700 Subject: ARM: dts: k2g: Add pinctrl support Add pinctrl support. Signed-off-by: Vitaly Andrianov Signed-off-by: Franklin S Cooper Jr Signed-off-by: Lokesh Vutla Signed-off-by: Dave Gerlach Signed-off-by: Santosh Shilimkar diff --git a/arch/arm/boot/dts/keystone-k2g.dtsi b/arch/arm/boot/dts/keystone-k2g.dtsi index 7ff2796..b99e879 100644 --- a/arch/arm/boot/dts/keystone-k2g.dtsi +++ b/arch/arm/boot/dts/keystone-k2g.dtsi @@ -75,6 +75,13 @@ ranges = <0x0 0x0 0x0 0xc0000000>; dma-ranges = <0x80000000 0x8 0x00000000 0x80000000>; + k2g_pinctrl: pinmux@02621000 { + compatible = "pinctrl-single"; + reg = <0x02621000 0x410>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x001b0007>; + }; + uart0: serial@02530c00 { compatible = "ns16550a"; current-speed = <115200>; -- cgit v0.10.2 From eb53a15b1ab820f51603efd76cdc723fdfafaae0 Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Thu, 9 Jun 2016 09:40:21 -0700 Subject: ARM: dts: keystone: Header file for pinctrl constants The pinctrl IP used in some of the Keystone 2 devices differ vs other TI SoCs. Therefore, create a Keystone specific pinctrl header. Signed-off-by: Lokesh Vutla Signed-off-by: Franklin S Cooper Jr Signed-off-by: Tero Kristo Signed-off-by: Dave Gerlach Signed-off-by: Santosh Shilimkar diff --git a/arch/arm/boot/dts/keystone-k2g.dtsi b/arch/arm/boot/dts/keystone-k2g.dtsi index b99e879..3372615 100644 --- a/arch/arm/boot/dts/keystone-k2g.dtsi +++ b/arch/arm/boot/dts/keystone-k2g.dtsi @@ -14,6 +14,7 @@ */ #include +#include #include "skeleton.dtsi" / { diff --git a/include/dt-bindings/pinctrl/keystone.h b/include/dt-bindings/pinctrl/keystone.h new file mode 100644 index 0000000..7f97d77 --- /dev/null +++ b/include/dt-bindings/pinctrl/keystone.h @@ -0,0 +1,39 @@ +/* + * This header provides constants for Keystone pinctrl bindings. + * + * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _DT_BINDINGS_PINCTRL_KEYSTONE_H +#define _DT_BINDINGS_PINCTRL_KEYSTONE_H + +#define MUX_MODE0 0 +#define MUX_MODE1 1 +#define MUX_MODE2 2 +#define MUX_MODE3 3 +#define MUX_MODE4 4 +#define MUX_MODE5 5 + +#define BUFFER_CLASS_B (0 << 19) +#define BUFFER_CLASS_C (1 << 19) +#define BUFFER_CLASS_D (2 << 19) +#define BUFFER_CLASS_E (3 << 19) + +#define PULL_DISABLE (1 << 16) +#define PIN_PULLUP (1 << 17) +#define PIN_PULLDOWN (0 << 17) + +#define KEYSTONE_IOPAD_OFFSET(pa, offset) (((pa) & 0xffff) - (offset)) + +#define K2G_CORE_IOPAD(pa) KEYSTONE_IOPAD_OFFSET((pa), 0x1000) + +#endif -- cgit v0.10.2 From 30220085a4b471e555f9233f861f43e4f24a0750 Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Thu, 9 Jun 2016 09:40:21 -0700 Subject: ARM: dts: k2g-evm: Add pinmuxing for UART0 Avoid depending on the bootloader or the ROM for configuring the pinmux by explicitly setting the pinmux here. Signed-off-by: Lokesh Vutla Signed-off-by: Franklin S Cooper Jr Signed-off-by: Tero Kristo Signed-off-by: Dave Gerlach Signed-off-by: Santosh Shilimkar diff --git a/arch/arm/boot/dts/keystone-k2g-evm.dts b/arch/arm/boot/dts/keystone-k2g-evm.dts index 5bfd9e7..692fcbb 100644 --- a/arch/arm/boot/dts/keystone-k2g-evm.dts +++ b/arch/arm/boot/dts/keystone-k2g-evm.dts @@ -27,6 +27,17 @@ }; +&k2g_pinctrl { + uart0_pins: pinmux_uart0_pins { + pinctrl-single,pins = < + K2G_CORE_IOPAD(0x11cc) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* uart0_rxd.uart0_rxd */ + K2G_CORE_IOPAD(0x11d0) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ + >; + }; +}; + &uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; status = "okay"; }; -- cgit v0.10.2 From 96d5a545374eac8fbd29b23bcd0d624c37e0ab9d Mon Sep 17 00:00:00 2001 From: Franklin S Cooper Jr Date: Tue, 3 May 2016 10:56:48 -0500 Subject: ARM: dts: am437x: Add missing compatibles to PWM binding documents There are several SOC specific compatibles for ECAP, EHRPWM and PWMMS that are in use but aren't properly documented. Therefore, fix this by adding the compatibles to the appropriate binding documents. While at it make minor corrections to the binding document. Signed-off-by: Franklin S Cooper Jr Acked-by: Rob Herring Signed-off-by: Tony Lindgren diff --git a/Documentation/devicetree/bindings/pwm/pwm-tiecap.txt b/Documentation/devicetree/bindings/pwm/pwm-tiecap.txt index fb81179..788da6c 100644 --- a/Documentation/devicetree/bindings/pwm/pwm-tiecap.txt +++ b/Documentation/devicetree/bindings/pwm/pwm-tiecap.txt @@ -2,8 +2,9 @@ TI SOC ECAP based APWM controller Required properties: - compatible: Must be "ti,-ecap". - for am33xx - compatible = "ti,am33xx-ecap"; - for da850 - compatible = "ti,da850-ecap", "ti,am33xx-ecap"; + for am33xx - compatible = "ti,am33xx-ecap"; + for am4372 - compatible = "ti,am4372-ecap", "ti,am33xx-ecap"; + for da850 - compatible = "ti,da850-ecap", "ti,am33xx-ecap"; - #pwm-cells: should be 3. See pwm.txt in this directory for a description of the cells format. The PWM channel index ranges from 0 to 4. The only third cell flag supported by this binding is PWM_POLARITY_INVERTED. @@ -22,6 +23,13 @@ ecap0: ecap@0 { /* ECAP on am33xx */ ti,hwmods = "ecap0"; }; +ecap0: ecap@0 { /* ECAP on am4372 */ + compatible = "ti,am4372-ecap", "ti,am33xx-ecap"; + #pwm-cells = <3>; + reg = <0x48300100 0x80>; + ti,hwmods = "ecap0"; +}; + ecap0: ecap@0 { /* ECAP on da850 */ compatible = "ti,da850-ecap", "ti,am33xx-ecap"; #pwm-cells = <3>; diff --git a/Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt b/Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt index 9c100b2..99b544f 100644 --- a/Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt +++ b/Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt @@ -2,8 +2,9 @@ TI SOC EHRPWM based PWM controller Required properties: - compatible: Must be "ti,-ehrpwm". - for am33xx - compatible = "ti,am33xx-ehrpwm"; - for da850 - compatible = "ti,da850-ehrpwm", "ti,am33xx-ehrpwm"; + for am33xx - compatible = "ti,am33xx-ehrpwm"; + for am4372 - compatible = "ti,am4372-ehrpwm", "ti,am33xx-ehrpwm"; + for da850 - compatible = "ti,da850-ehrpwm", "ti,am33xx-ehrpwm"; - #pwm-cells: should be 3. See pwm.txt in this directory for a description of the cells format. The only third cell flag supported by this binding is PWM_POLARITY_INVERTED. @@ -22,6 +23,13 @@ ehrpwm0: ehrpwm@0 { /* EHRPWM on am33xx */ ti,hwmods = "ehrpwm0"; }; +ehrpwm0: ehrpwm@0 { /* EHRPWM on am4372 */ + compatible = "ti,am4372-ehrpwm", "ti,am33xx-ehrpwm"; + #pwm-cells = <3>; + reg = <0x48300200 0x80>; + ti,hwmods = "ehrpwm0"; +}; + ehrpwm0: ehrpwm@0 { /* EHRPWM on da850 */ compatible = "ti,da850-ehrpwm", "ti,am33xx-ehrpwm"; #pwm-cells = <3>; diff --git a/Documentation/devicetree/bindings/pwm/pwm-tipwmss.txt b/Documentation/devicetree/bindings/pwm/pwm-tipwmss.txt index f7eae77..fd8e87c 100644 --- a/Documentation/devicetree/bindings/pwm/pwm-tipwmss.txt +++ b/Documentation/devicetree/bindings/pwm/pwm-tipwmss.txt @@ -1,7 +1,10 @@ TI SOC based PWM Subsystem Required properties: -- compatible: Must be "ti,am33xx-pwmss"; +- compatible: Must be "ti,-pwmss". + for am33xx - compatible = "ti,am33xx-pwmss"; + for am4372 - compatible = "ti,am4372-pwmss","ti,am33xx-pwmss"; + - reg: physical base address and size of the registers map. - address-cells: Specify the number of u32 entries needed in child nodes. Should set to 1. @@ -16,7 +19,7 @@ Required properties: Also child nodes should also populated under PWMSS DT node. Example: -pwmss0: pwmss@48300000 { +epwmss0: epwmss@48300000 { /* PWMSS for am33xx */ compatible = "ti,am33xx-pwmss"; reg = <0x48300000 0x10>; ti,hwmods = "epwmss0"; @@ -29,3 +32,17 @@ pwmss0: pwmss@48300000 { /* child nodes go here */ }; + +epwmss0: epwmss@48300000 { /* PWMSS for am4372 */ + compatible = "ti,am4372-pwmss","ti,am33xx-pwmss" + reg = <0x48300000 0x10>; + ti,hwmods = "epwmss0"; + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + ranges = <0x48300100 0x48300100 0x80 /* ECAP */ + 0x48300180 0x48300180 0x80 /* EQEP */ + 0x48300200 0x48300200 0x80>; /* EHRPWM */ + + /* child nodes go here */ +}; -- cgit v0.10.2 From 956abfe38cf51f8710bc1289333c0135129cf5fd Mon Sep 17 00:00:00 2001 From: Franklin S Cooper Jr Date: Tue, 3 May 2016 10:56:49 -0500 Subject: pwm: pwm-tiehrpwm: Update dt binding document to use generic node name Now that the node name has been changed from ehrpwm to pwm the document should show this proper usage. Change the unit address in the example from 0 to the proper physical address value that should be used. Also insure that the unit address matches to the reg property. Signed-off-by: Franklin S Cooper Jr Acked-by: Rob Herring Signed-off-by: Tony Lindgren diff --git a/Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt b/Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt index 99b544f..f3bc09e 100644 --- a/Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt +++ b/Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt @@ -16,22 +16,22 @@ Optional properties: Example: -ehrpwm0: ehrpwm@0 { /* EHRPWM on am33xx */ +ehrpwm0: pwm@48300200 { /* EHRPWM on am33xx */ compatible = "ti,am33xx-ehrpwm"; #pwm-cells = <3>; reg = <0x48300200 0x100>; ti,hwmods = "ehrpwm0"; }; -ehrpwm0: ehrpwm@0 { /* EHRPWM on am4372 */ +ehrpwm0: pwm@48300200 { /* EHRPWM on am4372 */ compatible = "ti,am4372-ehrpwm", "ti,am33xx-ehrpwm"; #pwm-cells = <3>; reg = <0x48300200 0x80>; ti,hwmods = "ehrpwm0"; }; -ehrpwm0: ehrpwm@0 { /* EHRPWM on da850 */ +ehrpwm0: pwm@1f00000 { /* EHRPWM on da850 */ compatible = "ti,da850-ehrpwm", "ti,am33xx-ehrpwm"; #pwm-cells = <3>; - reg = <0x300000 0x2000>; + reg = <0x1f00000 0x2000>; }; -- cgit v0.10.2 From 7d68a7f8fed9925437eacf067654ee8e753f8c49 Mon Sep 17 00:00:00 2001 From: Franklin S Cooper Jr Date: Tue, 3 May 2016 10:56:50 -0500 Subject: pwm: pwm-tiecap: Update dt binding document to use proper unit address Replace unit address from 0 to the proper physical address. Also insure that the unit address matches the reg property address. Signed-off-by: Franklin S Cooper Jr Acked-by: Rob Herring Signed-off-by: Tony Lindgren diff --git a/Documentation/devicetree/bindings/pwm/pwm-tiecap.txt b/Documentation/devicetree/bindings/pwm/pwm-tiecap.txt index 788da6c..0d47354 100644 --- a/Documentation/devicetree/bindings/pwm/pwm-tiecap.txt +++ b/Documentation/devicetree/bindings/pwm/pwm-tiecap.txt @@ -16,22 +16,22 @@ Optional properties: Example: -ecap0: ecap@0 { /* ECAP on am33xx */ +ecap0: ecap@48300100 { /* ECAP on am33xx */ compatible = "ti,am33xx-ecap"; #pwm-cells = <3>; reg = <0x48300100 0x80>; ti,hwmods = "ecap0"; }; -ecap0: ecap@0 { /* ECAP on am4372 */ +ecap0: ecap@48300100 { /* ECAP on am4372 */ compatible = "ti,am4372-ecap", "ti,am33xx-ecap"; #pwm-cells = <3>; reg = <0x48300100 0x80>; ti,hwmods = "ecap0"; }; -ecap0: ecap@0 { /* ECAP on da850 */ +ecap0: ecap@1f06000 { /* ECAP on da850 */ compatible = "ti,da850-ecap", "ti,am33xx-ecap"; #pwm-cells = <3>; - reg = <0x306000 0x80>; + reg = <0x1f06000 0x80>; }; -- cgit v0.10.2 From 229110c1aa69134a1ca1e3118cae08fac9d843ad Mon Sep 17 00:00:00 2001 From: Franklin S Cooper Jr Date: Tue, 3 May 2016 10:56:51 -0500 Subject: ARM: dts: am437x/am33xx/da850: Add new ECAP and EPWM bindings Switch to a new ECAP and EPWM bindings that doesn't depend on hwmod to provide the various required clocks. For AM437 and AM335x, add the required clocks explicitly to DT. The hwmod entries for ECAP and EPWM will be removed and this will prevent anything from breaking. Signed-off-by: Franklin S Cooper Jr Acked-by: Rob Herring Signed-off-by: Tony Lindgren diff --git a/Documentation/devicetree/bindings/pwm/pwm-tiecap.txt b/Documentation/devicetree/bindings/pwm/pwm-tiecap.txt index 0d47354..ee0a8bd 100644 --- a/Documentation/devicetree/bindings/pwm/pwm-tiecap.txt +++ b/Documentation/devicetree/bindings/pwm/pwm-tiecap.txt @@ -2,9 +2,9 @@ TI SOC ECAP based APWM controller Required properties: - compatible: Must be "ti,-ecap". - for am33xx - compatible = "ti,am33xx-ecap"; - for am4372 - compatible = "ti,am4372-ecap", "ti,am33xx-ecap"; - for da850 - compatible = "ti,da850-ecap", "ti,am33xx-ecap"; + for am33xx - compatible = "ti,am3352-ecap", "ti,am33xx-ecap"; + for am4372 - compatible = "ti,am4372-ecap", "ti,am3352-ecap", "ti,am33xx-ecap"; + for da850 - compatible = "ti,da850-ecap", "ti,am3352-ecap", "ti,am33xx-ecap"; - #pwm-cells: should be 3. See pwm.txt in this directory for a description of the cells format. The PWM channel index ranges from 0 to 4. The only third cell flag supported by this binding is PWM_POLARITY_INVERTED. @@ -13,25 +13,31 @@ Required properties: Optional properties: - ti,hwmods: Name of the hwmod associated to the ECAP: "ecap", being the 0-based instance number from the HW spec +- clocks: Handle to the ECAP's functional clock. +- clock-names: Must be set to "fck". Example: ecap0: ecap@48300100 { /* ECAP on am33xx */ - compatible = "ti,am33xx-ecap"; + compatible = "ti,am3352-ecap", "ti,am33xx-ecap"; #pwm-cells = <3>; reg = <0x48300100 0x80>; ti,hwmods = "ecap0"; + clocks = <&l4ls_gclk>; + clock-names = "fck"; }; ecap0: ecap@48300100 { /* ECAP on am4372 */ - compatible = "ti,am4372-ecap", "ti,am33xx-ecap"; + compatible = "ti,am4372-ecap", "ti,am3352-ecap", "ti,am33xx-ecap"; #pwm-cells = <3>; reg = <0x48300100 0x80>; ti,hwmods = "ecap0"; + clocks = <&l4ls_gclk>; + clock-names = "fck"; }; ecap0: ecap@1f06000 { /* ECAP on da850 */ - compatible = "ti,da850-ecap", "ti,am33xx-ecap"; + compatible = "ti,da850-ecap", "ti,am3352-ecap", "ti,am33xx-ecap"; #pwm-cells = <3>; reg = <0x1f06000 0x80>; }; diff --git a/Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt b/Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt index f3bc09e..e9a156b 100644 --- a/Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt +++ b/Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt @@ -2,9 +2,9 @@ TI SOC EHRPWM based PWM controller Required properties: - compatible: Must be "ti,-ehrpwm". - for am33xx - compatible = "ti,am33xx-ehrpwm"; - for am4372 - compatible = "ti,am4372-ehrpwm", "ti,am33xx-ehrpwm"; - for da850 - compatible = "ti,da850-ehrpwm", "ti,am33xx-ehrpwm"; + for am33xx - compatible = "ti,am3352-ehrpwm", "ti,am33xx-ehrpwm"; + for am4372 - compatible = "ti,am4372-ehrpwm", "ti-am3352-ehrpwm", "ti,am33xx-ehrpwm"; + for da850 - compatible = "ti,da850-ehrpwm", "ti-am3352-ehrpwm", "ti,am33xx-ehrpwm"; - #pwm-cells: should be 3. See pwm.txt in this directory for a description of the cells format. The only third cell flag supported by this binding is PWM_POLARITY_INVERTED. @@ -13,25 +13,31 @@ Required properties: Optional properties: - ti,hwmods: Name of the hwmod associated to the EHRPWM: "ehrpwm", being the 0-based instance number from the HW spec +- clocks: Handle to the PWM's time-base and functional clock. +- clock-names: Must be set to "tbclk" and "fck". Example: ehrpwm0: pwm@48300200 { /* EHRPWM on am33xx */ - compatible = "ti,am33xx-ehrpwm"; + compatible = "ti,am3352-ehrpwm", "ti,am33xx-ehrpwm"; #pwm-cells = <3>; reg = <0x48300200 0x100>; + clocks = <&ehrpwm0_tbclk>, <&l4ls_gclk>; + clock-names = "tbclk", "fck"; ti,hwmods = "ehrpwm0"; }; ehrpwm0: pwm@48300200 { /* EHRPWM on am4372 */ - compatible = "ti,am4372-ehrpwm", "ti,am33xx-ehrpwm"; + compatible = "ti,am4372-ehrpwm", "ti,am3352-ehrpwm", "ti,am33xx-ehrpwm"; #pwm-cells = <3>; reg = <0x48300200 0x80>; + clocks = <&ehrpwm0_tbclk>, <&l4ls_gclk>; + clock-names = "tbclk", "fck"; ti,hwmods = "ehrpwm0"; }; ehrpwm0: pwm@1f00000 { /* EHRPWM on da850 */ - compatible = "ti,da850-ehrpwm", "ti,am33xx-ehrpwm"; + compatible = "ti,da850-ehrpwm", "ti,am3352-ehrpwm", "ti,am33xx-ehrpwm"; #pwm-cells = <3>; reg = <0x1f00000 0x2000>; }; diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi index 52be48b..999ba2f 100644 --- a/arch/arm/boot/dts/am33xx.dtsi +++ b/arch/arm/boot/dts/am33xx.dtsi @@ -679,9 +679,12 @@ 0x48300200 0x48300200 0x80>; /* EHRPWM */ ecap0: ecap@48300100 { - compatible = "ti,am33xx-ecap"; + compatible = "ti,am3352-ecap", + "ti,am33xx-ecap"; #pwm-cells = <3>; reg = <0x48300100 0x80>; + clocks = <&l4ls_gclk>; + clock-names = "fck"; interrupts = <31>; interrupt-names = "ecap0"; ti,hwmods = "ecap0"; @@ -689,10 +692,13 @@ }; ehrpwm0: pwm@48300200 { - compatible = "ti,am33xx-ehrpwm"; + compatible = "ti,am3352-ehrpwm", + "ti,am33xx-ehrpwm"; #pwm-cells = <3>; reg = <0x48300200 0x80>; ti,hwmods = "ehrpwm0"; + clocks = <&ehrpwm0_tbclk>, <&l4ls_gclk>; + clock-names = "tbclk", "fck"; status = "disabled"; }; }; @@ -709,9 +715,12 @@ 0x48302200 0x48302200 0x80>; /* EHRPWM */ ecap1: ecap@48302100 { - compatible = "ti,am33xx-ecap"; + compatible = "ti,am3352-ecap", + "ti,am33xx-ecap"; #pwm-cells = <3>; reg = <0x48302100 0x80>; + clocks = <&l4ls_gclk>; + clock-names = "fck"; interrupts = <47>; interrupt-names = "ecap1"; ti,hwmods = "ecap1"; @@ -719,10 +728,13 @@ }; ehrpwm1: pwm@48302200 { - compatible = "ti,am33xx-ehrpwm"; + compatible = "ti,am3352-ehrpwm", + "ti,am33xx-ehrpwm"; #pwm-cells = <3>; reg = <0x48302200 0x80>; ti,hwmods = "ehrpwm1"; + clocks = <&ehrpwm1_tbclk>, <&l4ls_gclk>; + clock-names = "tbclk", "fck"; status = "disabled"; }; }; @@ -739,9 +751,12 @@ 0x48304200 0x48304200 0x80>; /* EHRPWM */ ecap2: ecap@48304100 { - compatible = "ti,am33xx-ecap"; + compatible = "ti,am3352-ecap", + "ti,am33xx-ecap"; #pwm-cells = <3>; reg = <0x48304100 0x80>; + clocks = <&l4ls_gclk>; + clock-names = "fck"; interrupts = <61>; interrupt-names = "ecap2"; ti,hwmods = "ecap2"; @@ -749,10 +764,13 @@ }; ehrpwm2: pwm@48304200 { - compatible = "ti,am33xx-ehrpwm"; + compatible = "ti,am3352-ehrpwm", + "ti,am33xx-ehrpwm"; #pwm-cells = <3>; reg = <0x48304200 0x80>; ti,hwmods = "ehrpwm2"; + clocks = <&ehrpwm2_tbclk>, <&l4ls_gclk>; + clock-names = "tbclk", "fck"; status = "disabled"; }; }; diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi index 12fcde4..e858460 100644 --- a/arch/arm/boot/dts/am4372.dtsi +++ b/arch/arm/boot/dts/am4372.dtsi @@ -672,18 +672,26 @@ status = "disabled"; ecap0: ecap@48300100 { - compatible = "ti,am4372-ecap","ti,am33xx-ecap"; + compatible = "ti,am4372-ecap", + "ti,am3352-ecap", + "ti,am33xx-ecap"; #pwm-cells = <3>; reg = <0x48300100 0x80>; ti,hwmods = "ecap0"; + clocks = <&l4ls_gclk>; + clock-names = "fck"; status = "disabled"; }; ehrpwm0: pwm@48300200 { - compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm"; + compatible = "ti,am4372-ehrpwm", + "ti,am3352-ehrpwm", + "ti,am33xx-ehrpwm"; #pwm-cells = <3>; reg = <0x48300200 0x80>; ti,hwmods = "ehrpwm0"; + clocks = <&ehrpwm0_tbclk>, <&l4ls_gclk>; + clock-names = "tbclk", "fck"; status = "disabled"; }; }; @@ -698,18 +706,26 @@ status = "disabled"; ecap1: ecap@48302100 { - compatible = "ti,am4372-ecap","ti,am33xx-ecap"; + compatible = "ti,am4372-ecap", + "ti,am3352-ecap", + "ti,am33xx-ecap"; #pwm-cells = <3>; reg = <0x48302100 0x80>; ti,hwmods = "ecap1"; + clocks = <&l4ls_gclk>; + clock-names = "fck"; status = "disabled"; }; ehrpwm1: pwm@48302200 { - compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm"; + compatible = "ti,am4372-ehrpwm", + "ti,am3352-ehrpwm", + "ti,am33xx-ehrpwm"; #pwm-cells = <3>; reg = <0x48302200 0x80>; ti,hwmods = "ehrpwm1"; + clocks = <&ehrpwm1_tbclk>, <&l4ls_gclk>; + clock-names = "tbclk", "fck"; status = "disabled"; }; }; @@ -724,18 +740,26 @@ status = "disabled"; ecap2: ecap@48304100 { - compatible = "ti,am4372-ecap","ti,am33xx-ecap"; + compatible = "ti,am4372-ecap", + "ti,am3352-ecap", + "ti,am33xx-ecap"; #pwm-cells = <3>; reg = <0x48304100 0x80>; + clocks = <&l4ls_gclk>; + clock-names = "fck"; ti,hwmods = "ecap2"; status = "disabled"; }; ehrpwm2: pwm@48304200 { - compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm"; + compatible = "ti,am4372-ehrpwm", + "ti,am3352-ehrpwm", + "ti,am33xx-ehrpwm"; #pwm-cells = <3>; reg = <0x48304200 0x80>; ti,hwmods = "ehrpwm2"; + clocks = <&ehrpwm2_tbclk>, <&l4ls_gclk>; + clock-names = "tbclk", "fck"; status = "disabled"; }; }; @@ -750,10 +774,14 @@ status = "disabled"; ehrpwm3: pwm@48306200 { - compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm"; + compatible = "ti,am4372-ehrpwm", + "ti,am3352-ehrpwm", + "ti,am33xx-ehrpwm"; #pwm-cells = <3>; reg = <0x48306200 0x80>; ti,hwmods = "ehrpwm3"; + clocks = <&ehrpwm3_tbclk>, <&l4ls_gclk>; + clock-names = "tbclk", "fck"; status = "disabled"; }; }; @@ -768,10 +796,14 @@ status = "disabled"; ehrpwm4: pwm@48308200 { - compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm"; + compatible = "ti,am4372-ehrpwm", + "ti,am3352-ehrpwm", + "ti,am33xx-ehrpwm"; #pwm-cells = <3>; reg = <0x48308200 0x80>; ti,hwmods = "ehrpwm4"; + clocks = <&ehrpwm4_tbclk>, <&l4ls_gclk>; + clock-names = "tbclk", "fck"; status = "disabled"; }; }; @@ -786,9 +818,13 @@ status = "disabled"; ehrpwm5: pwm@4830a200 { - compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm"; + compatible = "ti,am4372-ehrpwm", + "ti,am3352-ehrpwm", + "ti,am33xx-ehrpwm"; #pwm-cells = <3>; reg = <0x4830a200 0x80>; + clocks = <&ehrpwm5_tbclk>, <&l4ls_gclk>; + clock-names = "tbclk", "fck"; ti,hwmods = "ehrpwm5"; status = "disabled"; }; -- cgit v0.10.2 From 58bfbea5b1c6826953d54ee470ab560aba55afce Mon Sep 17 00:00:00 2001 From: Franklin S Cooper Jr Date: Tue, 3 May 2016 10:56:53 -0500 Subject: ARM: dts: am437x/am33xx: Remove hwmod entries for ECAP and EPWM nodes Previous patches switched the ECAP and EPWM to use the new bindings. These bindings explicitly adds the various required clocks via DT rather than depending on hwmod. Therefore, it is safe to remove the hwmod entries since they are no longer needed. Signed-off-by: Franklin S Cooper Jr Acked-by: Rob Herring Acked-by: Paul Walmsley Signed-off-by: Tony Lindgren diff --git a/Documentation/devicetree/bindings/pwm/pwm-tiecap.txt b/Documentation/devicetree/bindings/pwm/pwm-tiecap.txt index ee0a8bd..f2a9a7c 100644 --- a/Documentation/devicetree/bindings/pwm/pwm-tiecap.txt +++ b/Documentation/devicetree/bindings/pwm/pwm-tiecap.txt @@ -11,8 +11,6 @@ Required properties: - reg: physical base address and size of the registers map. Optional properties: -- ti,hwmods: Name of the hwmod associated to the ECAP: - "ecap", being the 0-based instance number from the HW spec - clocks: Handle to the ECAP's functional clock. - clock-names: Must be set to "fck". @@ -22,7 +20,6 @@ ecap0: ecap@48300100 { /* ECAP on am33xx */ compatible = "ti,am3352-ecap", "ti,am33xx-ecap"; #pwm-cells = <3>; reg = <0x48300100 0x80>; - ti,hwmods = "ecap0"; clocks = <&l4ls_gclk>; clock-names = "fck"; }; diff --git a/Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt b/Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt index e9a156b..41a2bd4 100644 --- a/Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt +++ b/Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt @@ -11,8 +11,6 @@ Required properties: - reg: physical base address and size of the registers map. Optional properties: -- ti,hwmods: Name of the hwmod associated to the EHRPWM: - "ehrpwm", being the 0-based instance number from the HW spec - clocks: Handle to the PWM's time-base and functional clock. - clock-names: Must be set to "tbclk" and "fck". @@ -24,7 +22,6 @@ ehrpwm0: pwm@48300200 { /* EHRPWM on am33xx */ reg = <0x48300200 0x100>; clocks = <&ehrpwm0_tbclk>, <&l4ls_gclk>; clock-names = "tbclk", "fck"; - ti,hwmods = "ehrpwm0"; }; ehrpwm0: pwm@48300200 { /* EHRPWM on am4372 */ diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi index 999ba2f..2661acc 100644 --- a/arch/arm/boot/dts/am33xx.dtsi +++ b/arch/arm/boot/dts/am33xx.dtsi @@ -687,7 +687,6 @@ clock-names = "fck"; interrupts = <31>; interrupt-names = "ecap0"; - ti,hwmods = "ecap0"; status = "disabled"; }; @@ -696,7 +695,6 @@ "ti,am33xx-ehrpwm"; #pwm-cells = <3>; reg = <0x48300200 0x80>; - ti,hwmods = "ehrpwm0"; clocks = <&ehrpwm0_tbclk>, <&l4ls_gclk>; clock-names = "tbclk", "fck"; status = "disabled"; @@ -723,7 +721,6 @@ clock-names = "fck"; interrupts = <47>; interrupt-names = "ecap1"; - ti,hwmods = "ecap1"; status = "disabled"; }; @@ -732,7 +729,6 @@ "ti,am33xx-ehrpwm"; #pwm-cells = <3>; reg = <0x48302200 0x80>; - ti,hwmods = "ehrpwm1"; clocks = <&ehrpwm1_tbclk>, <&l4ls_gclk>; clock-names = "tbclk", "fck"; status = "disabled"; @@ -759,7 +755,6 @@ clock-names = "fck"; interrupts = <61>; interrupt-names = "ecap2"; - ti,hwmods = "ecap2"; status = "disabled"; }; @@ -768,7 +763,6 @@ "ti,am33xx-ehrpwm"; #pwm-cells = <3>; reg = <0x48304200 0x80>; - ti,hwmods = "ehrpwm2"; clocks = <&ehrpwm2_tbclk>, <&l4ls_gclk>; clock-names = "tbclk", "fck"; status = "disabled"; diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi index e858460..cfdd4b7 100644 --- a/arch/arm/boot/dts/am4372.dtsi +++ b/arch/arm/boot/dts/am4372.dtsi @@ -677,7 +677,6 @@ "ti,am33xx-ecap"; #pwm-cells = <3>; reg = <0x48300100 0x80>; - ti,hwmods = "ecap0"; clocks = <&l4ls_gclk>; clock-names = "fck"; status = "disabled"; @@ -689,7 +688,6 @@ "ti,am33xx-ehrpwm"; #pwm-cells = <3>; reg = <0x48300200 0x80>; - ti,hwmods = "ehrpwm0"; clocks = <&ehrpwm0_tbclk>, <&l4ls_gclk>; clock-names = "tbclk", "fck"; status = "disabled"; @@ -711,7 +709,6 @@ "ti,am33xx-ecap"; #pwm-cells = <3>; reg = <0x48302100 0x80>; - ti,hwmods = "ecap1"; clocks = <&l4ls_gclk>; clock-names = "fck"; status = "disabled"; @@ -723,7 +720,6 @@ "ti,am33xx-ehrpwm"; #pwm-cells = <3>; reg = <0x48302200 0x80>; - ti,hwmods = "ehrpwm1"; clocks = <&ehrpwm1_tbclk>, <&l4ls_gclk>; clock-names = "tbclk", "fck"; status = "disabled"; @@ -747,7 +743,6 @@ reg = <0x48304100 0x80>; clocks = <&l4ls_gclk>; clock-names = "fck"; - ti,hwmods = "ecap2"; status = "disabled"; }; @@ -757,7 +752,6 @@ "ti,am33xx-ehrpwm"; #pwm-cells = <3>; reg = <0x48304200 0x80>; - ti,hwmods = "ehrpwm2"; clocks = <&ehrpwm2_tbclk>, <&l4ls_gclk>; clock-names = "tbclk", "fck"; status = "disabled"; @@ -779,7 +773,6 @@ "ti,am33xx-ehrpwm"; #pwm-cells = <3>; reg = <0x48306200 0x80>; - ti,hwmods = "ehrpwm3"; clocks = <&ehrpwm3_tbclk>, <&l4ls_gclk>; clock-names = "tbclk", "fck"; status = "disabled"; @@ -801,7 +794,6 @@ "ti,am33xx-ehrpwm"; #pwm-cells = <3>; reg = <0x48308200 0x80>; - ti,hwmods = "ehrpwm4"; clocks = <&ehrpwm4_tbclk>, <&l4ls_gclk>; clock-names = "tbclk", "fck"; status = "disabled"; @@ -825,7 +817,6 @@ reg = <0x4830a200 0x80>; clocks = <&ehrpwm5_tbclk>, <&l4ls_gclk>; clock-names = "tbclk", "fck"; - ti,hwmods = "ehrpwm5"; status = "disabled"; }; }; -- cgit v0.10.2 From 34370142331953146efd1be573696785957a2fa9 Mon Sep 17 00:00:00 2001 From: Vignesh R Date: Tue, 3 May 2016 10:56:55 -0500 Subject: ARM: dts: DRA7: Add dt nodes for PWMSS Add PWMSS device tree nodes for DRA7 SoC family and add documentation for dt bindings. Signed-off-by: Vignesh R [fcooper@ti.com: Add eCAP and use updated bindings for PWMSS and ePWM] Signed-off-by: Franklin S Cooper Jr Acked-by: Rob Herring Signed-off-by: Tony Lindgren diff --git a/Documentation/devicetree/bindings/pwm/pwm-tiecap.txt b/Documentation/devicetree/bindings/pwm/pwm-tiecap.txt index f2a9a7c..8007e83 100644 --- a/Documentation/devicetree/bindings/pwm/pwm-tiecap.txt +++ b/Documentation/devicetree/bindings/pwm/pwm-tiecap.txt @@ -5,6 +5,7 @@ Required properties: for am33xx - compatible = "ti,am3352-ecap", "ti,am33xx-ecap"; for am4372 - compatible = "ti,am4372-ecap", "ti,am3352-ecap", "ti,am33xx-ecap"; for da850 - compatible = "ti,da850-ecap", "ti,am3352-ecap", "ti,am33xx-ecap"; + for dra746 - compatible = "ti,dra746-ecap", "ti,am3352-ecap"; - #pwm-cells: should be 3. See pwm.txt in this directory for a description of the cells format. The PWM channel index ranges from 0 to 4. The only third cell flag supported by this binding is PWM_POLARITY_INVERTED. @@ -38,3 +39,11 @@ ecap0: ecap@1f06000 { /* ECAP on da850 */ #pwm-cells = <3>; reg = <0x1f06000 0x80>; }; + +ecap0: ecap@4843e100 { + compatible = "ti,dra746-ecap", "ti,am3352-ecap"; + #pwm-cells = <3>; + reg = <0x4843e100 0x80>; + clocks = <&l4_root_clk_div>; + clock-names = "fck"; +}; diff --git a/Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt b/Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt index 41a2bd4..944fe35 100644 --- a/Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt +++ b/Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt @@ -5,6 +5,7 @@ Required properties: for am33xx - compatible = "ti,am3352-ehrpwm", "ti,am33xx-ehrpwm"; for am4372 - compatible = "ti,am4372-ehrpwm", "ti-am3352-ehrpwm", "ti,am33xx-ehrpwm"; for da850 - compatible = "ti,da850-ehrpwm", "ti-am3352-ehrpwm", "ti,am33xx-ehrpwm"; + for dra746 - compatible = "ti,dra746-ehrpwm", "ti-am3352-ehrpwm"; - #pwm-cells: should be 3. See pwm.txt in this directory for a description of the cells format. The only third cell flag supported by this binding is PWM_POLARITY_INVERTED. @@ -38,3 +39,11 @@ ehrpwm0: pwm@1f00000 { /* EHRPWM on da850 */ #pwm-cells = <3>; reg = <0x1f00000 0x2000>; }; + +ehrpwm0: pwm@4843e200 { /* EHRPWM on dra746 */ + compatible = "ti,dra746-ehrpwm", "ti,am3352-ehrpwm"; + #pwm-cells = <3>; + reg = <0x4843e200 0x80>; + clocks = <&ehrpwm0_tbclk>, <&l4_root_clk_div>; + clock-names = "tbclk", "fck"; +}; diff --git a/Documentation/devicetree/bindings/pwm/pwm-tipwmss.txt b/Documentation/devicetree/bindings/pwm/pwm-tipwmss.txt index fd8e87c..1a5d7b7 100644 --- a/Documentation/devicetree/bindings/pwm/pwm-tipwmss.txt +++ b/Documentation/devicetree/bindings/pwm/pwm-tipwmss.txt @@ -4,6 +4,7 @@ Required properties: - compatible: Must be "ti,-pwmss". for am33xx - compatible = "ti,am33xx-pwmss"; for am4372 - compatible = "ti,am4372-pwmss","ti,am33xx-pwmss"; + for dra746 - compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss" - reg: physical base address and size of the registers map. - address-cells: Specify the number of u32 entries needed in child nodes. @@ -46,3 +47,14 @@ epwmss0: epwmss@48300000 { /* PWMSS for am4372 */ /* child nodes go here */ }; + +epwmss0: epwmss@4843e000 { /* PWMSS for DRA7xx */ + compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss"; + reg = <0x4843e000 0x30>; + ti,hwmods = "epwmss0"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + /* child nodes go here */ +}; diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index e007401..5a21e46 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -1743,6 +1743,96 @@ clock-names = "fck", "sys_clk"; }; }; + + epwmss0: epwmss@4843e000 { + compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss"; + reg = <0x4843e000 0x30>; + ti,hwmods = "epwmss0"; + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + ranges; + + ehrpwm0: pwm@4843e200 { + compatible = "ti,dra746-ehrpwm", + "ti,am3352-ehrpwm"; + #pwm-cells = <3>; + reg = <0x4843e200 0x80>; + clocks = <&ehrpwm0_tbclk>, <&l4_root_clk_div>; + clock-names = "tbclk", "fck"; + status = "disabled"; + }; + + ecap0: ecap@4843e100 { + compatible = "ti,dra746-ecap", + "ti,am3352-ecap"; + #pwm-cells = <3>; + reg = <0x4843e100 0x80>; + clocks = <&l4_root_clk_div>; + clock-names = "fck"; + status = "disabled"; + }; + }; + + epwmss1: epwmss@48440000 { + compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss"; + reg = <0x48440000 0x30>; + ti,hwmods = "epwmss1"; + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + ranges; + + ehrpwm1: pwm@48440200 { + compatible = "ti,dra746-ehrpwm", + "ti,am3352-ehrpwm"; + #pwm-cells = <3>; + reg = <0x48440200 0x80>; + clocks = <&ehrpwm1_tbclk>, <&l4_root_clk_div>; + clock-names = "tbclk", "fck"; + status = "disabled"; + }; + + ecap1: ecap@48440100 { + compatible = "ti,dra746-ecap", + "ti,am3352-ecap"; + #pwm-cells = <3>; + reg = <0x48440100 0x80>; + clocks = <&l4_root_clk_div>; + clock-names = "fck"; + status = "disabled"; + }; + }; + + epwmss2: epwmss@48442000 { + compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss"; + reg = <0x48442000 0x30>; + ti,hwmods = "epwmss2"; + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + ranges; + + ehrpwm2: pwm@48442200 { + compatible = "ti,dra746-ehrpwm", + "ti,am3352-ehrpwm"; + #pwm-cells = <3>; + reg = <0x48442200 0x80>; + clocks = <&ehrpwm2_tbclk>, <&l4_root_clk_div>; + clock-names = "tbclk", "fck"; + status = "disabled"; + }; + + ecap2: ecap@48442100 { + compatible = "ti,dra746-ecap", + "ti,am3352-ecap"; + #pwm-cells = <3>; + reg = <0x48442100 0x80>; + clocks = <&l4_root_clk_div>; + clock-names = "fck"; + status = "disabled"; + }; + }; }; thermal_zones: thermal-zones { -- cgit v0.10.2 From a5fa09b6943f3304c2a7b2670c896c485fba8cf4 Mon Sep 17 00:00:00 2001 From: Dave Gerlach Date: Tue, 10 May 2016 14:49:41 -0500 Subject: ARM: dts: dra7: Add ocmcram nodes Add all ocmcram nodes to dra7.dtsi using the generic mmio-sram driver. DRA7xx and AM57xx families of SoCs can contain three ocmcram regions of SRAM, one of 512kb and also an optional two additional of 1Mb each. Mark the two additional 1MB regions of SRAM as disabled as only ocmcmram1 is on all variants of the SoCs, then depending on which specific variant is in use the ocmcram2 and ocmcram3 nodes can be enabled in the board dts file if the data manual for that part number indicates the ocmcram region is available. Signed-off-by: Dave Gerlach Reviewed-by: Andreas Dannenberg Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index 5a21e46..4847ef9 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -304,6 +304,38 @@ }; }; + ocmcram1: ocmcram@40300000 { + compatible = "mmio-sram"; + reg = <0x40300000 0x80000>; + ranges = <0x0 0x40300000 0x80000>; + #address-cells = <1>; + #size-cells = <1>; + }; + + /* + * NOTE: ocmcram2 and ocmcram3 are not available on all + * DRA7xx and AM57xx variants. Confirm availability in + * the data manual for the exact part number in use + * before enabling these nodes in the board dts file. + */ + ocmcram2: ocmcram@40400000 { + status = "disabled"; + compatible = "mmio-sram"; + reg = <0x40400000 0x100000>; + ranges = <0x0 0x40400000 0x100000>; + #address-cells = <1>; + #size-cells = <1>; + }; + + ocmcram3: ocmcram@40500000 { + status = "disabled"; + compatible = "mmio-sram"; + reg = <0x40500000 0x100000>; + ranges = <0x0 0x40500000 0x100000>; + #address-cells = <1>; + #size-cells = <1>; + }; + bandgap: bandgap@4a0021e0 { reg = <0x4a0021e0 0xc 0x4a00232c 0xc -- cgit v0.10.2 From fae3a9f023b7903be3d84ae81014b061508480f9 Mon Sep 17 00:00:00 2001 From: Dave Gerlach Date: Tue, 10 May 2016 14:49:42 -0500 Subject: ARM: dts: dra7: Add ti,secure-ram node to ocmcram1 node Secure variants of DRA7xx and AM57xx SoCs may need to reserve a region of the SRAM for use by secure software. To account for this, add a child node to the ocmcram1 node that will act as a placeholder at the start of the SRAM for the reserved region of memory that may be required by secure services. The node is added with size 0 so that by default parts will have the full space available but the bootloader or board dts file is able to resize the node as needed depending on how much reserved space is needed, if any, so end users of the ocmcram1 region on HS parts must be aware that a smaller amount of SRAM than expected may be available. Signed-off-by: Dave Gerlach Reviewed-by: Andreas Dannenberg Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index 4847ef9..d8c0dd1 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -310,6 +310,21 @@ ranges = <0x0 0x40300000 0x80000>; #address-cells = <1>; #size-cells = <1>; + /* + * This is a placeholder for an optional reserved + * region for use by secure software. The size + * of this region is not known until runtime so it + * is set as zero to either be updated to reserve + * space or left unchanged to leave all SRAM for use. + * On HS parts that that require the reserved region + * either the bootloader can update the size to + * the required amount or the node can be overridden + * from the board dts file for the secure platform. + */ + sram-hs@0 { + compatible = "ti,secure-ram"; + reg = <0x0 0x0>; + }; }; /* -- cgit v0.10.2 From e7c8682143db9771bad62626793201eb809cfaf2 Mon Sep 17 00:00:00 2001 From: Ivaylo Dimitrov Date: Mon, 16 May 2016 22:34:14 +0300 Subject: ARM: dts: n900: enable lirc-rx51 driver Add the needed DT data to enable IR TX driver Signed-off-by: Ivaylo Dimitrov Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/omap3-n900.dts b/arch/arm/boot/dts/omap3-n900.dts index d9e2d9c..0ceff5d 100644 --- a/arch/arm/boot/dts/omap3-n900.dts +++ b/arch/arm/boot/dts/omap3-n900.dts @@ -143,6 +143,18 @@ io-channels = <&twl_madc 0>, <&twl_madc 4>, <&twl_madc 12>; io-channel-names = "temp", "bsi", "vbat"; }; + + pwm9: dmtimer-pwm@9 { + compatible = "ti,omap-dmtimer-pwm"; + #pwm-cells = <3>; + ti,timers = <&timer9>; + ti,clock-source = <0x00>; /* timer_sys_ck */ + }; + + ir: n900-ir { + compatible = "nokia,n900-ir"; + pwms = <&pwm9 0 26316 0>; /* 38000 Hz */ + }; }; &omap3_pmx_core { -- cgit v0.10.2 From 28a1b403b28e34e4a4e6ff29925e66d358499622 Mon Sep 17 00:00:00 2001 From: Marek Belisko Date: Tue, 17 May 2016 21:48:47 +0200 Subject: ARM: dts: omap3-gta04: Add backlight support Define pwm backlight node which is using dmtimer pwm. Signed-off-by: Marek Belisko Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/omap3-gta04.dtsi b/arch/arm/boot/dts/omap3-gta04.dtsi index ab9fb8f..cef8b23 100644 --- a/arch/arm/boot/dts/omap3-gta04.dtsi +++ b/arch/arm/boot/dts/omap3-gta04.dtsi @@ -100,6 +100,22 @@ }; }; + backlight { + compatible = "pwm-backlight"; + pwms = <&pwm11 0 2000000 0>; + pwm-names = "backlight"; + brightness-levels = <0 11 20 30 40 50 60 70 80 90 100>; + default-brightness-level = <9>; /* => 90 */ + pinctrl-names = "default"; + pinctrl-0 = <&backlight_pins>; + }; + + pwm11: dmtimer-pwm@11 { + compatible = "ti,omap-dmtimer-pwm"; + ti,timers = <&timer11>; + #pwm-cells = <3>; + }; + hsusb2_phy: hsusb2_phy { compatible = "usb-nop-xceiv"; reset-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>; @@ -190,6 +206,12 @@ >; }; + backlight_pins: backlight_pins_pimnux { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x20ba, MUX_MODE3) /* gpt11/gpio57 */ + >; + }; + dss_dpi_pins: pinmux_dss_dpi_pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ -- cgit v0.10.2 From ee327111953b841280af501c65c976f253884587 Mon Sep 17 00:00:00 2001 From: "H. Nikolaus Schaller" Date: Tue, 17 May 2016 21:48:48 +0200 Subject: ARM: dts: omap3-gta04: Define and use bma180 irq pin Add pinmux and usage of bma180 irq pin. Signed-off-by: H. Nikolaus Schaller Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/omap3-gta04.dtsi b/arch/arm/boot/dts/omap3-gta04.dtsi index cef8b23..e0520cf 100644 --- a/arch/arm/boot/dts/omap3-gta04.dtsi +++ b/arch/arm/boot/dts/omap3-gta04.dtsi @@ -250,6 +250,12 @@ OMAP3_CORE1_IOPAD(0x21c6, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_sda.hdq */ >; }; + + bma180_pins: pinmux_bma180_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x213a, PIN_INPUT_PULLUP | MUX_MODE4) /* gpio115 */ + >; + }; }; &omap3_pmx_core2 { @@ -320,6 +326,8 @@ bma180@41 { compatible = "bosch,bma180"; reg = <0x41>; + pinctrl-names = "default"; + pintcrl-0 = <&bma180_pins>; interrupt-parent = <&gpio4>; interrupts = <19 IRQ_TYPE_LEVEL_HIGH>; /* GPIO_115 */ }; -- cgit v0.10.2 From f6cbf6106ad0fb7f25b39714b30c0e083dbc5612 Mon Sep 17 00:00:00 2001 From: "H. Nikolaus Schaller" Date: Tue, 17 May 2016 21:48:49 +0200 Subject: ARM: dta: omap3-gta04: Define and use itg3200 irq pin Define pinmux and usage if irq pin + fix irq edge. Signed-off-by: H. Nikolaus Schaller Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/omap3-gta04.dtsi b/arch/arm/boot/dts/omap3-gta04.dtsi index e0520cf..094e5e1 100644 --- a/arch/arm/boot/dts/omap3-gta04.dtsi +++ b/arch/arm/boot/dts/omap3-gta04.dtsi @@ -256,6 +256,12 @@ OMAP3_CORE1_IOPAD(0x213a, PIN_INPUT_PULLUP | MUX_MODE4) /* gpio115 */ >; }; + + itg3200_pins: pinmux_itg3200_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x20b8, PIN_INPUT_PULLUP | MUX_MODE4) /* gpio56 */ + >; + }; }; &omap3_pmx_core2 { @@ -336,8 +342,10 @@ itg3200@68 { compatible = "invensense,itg3200"; reg = <0x68>; + pinctrl-names = "default"; + pinctrl-0 = <&itg3200_pins>; interrupt-parent = <&gpio2>; - interrupts = <24 0>; /* GPIO_56 */ + interrupts = <24 IRQ_TYPE_EDGE_FALLING>; /* GPIO_56 */ }; /* leds */ -- cgit v0.10.2 From e14927e265f0d2f50617c87259d5e08f30477d20 Mon Sep 17 00:00:00 2001 From: "H. Nikolaus Schaller" Date: Tue, 17 May 2016 21:48:50 +0200 Subject: ARM: dta: omap3-gta04: Define and use hmc5843 irq pin Define pinmux and usage if irq pin. Signed-off-by: H. Nikolaus Schaller Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/omap3-gta04.dtsi b/arch/arm/boot/dts/omap3-gta04.dtsi index 094e5e1..55b6b88 100644 --- a/arch/arm/boot/dts/omap3-gta04.dtsi +++ b/arch/arm/boot/dts/omap3-gta04.dtsi @@ -262,6 +262,12 @@ OMAP3_CORE1_IOPAD(0x20b8, PIN_INPUT_PULLUP | MUX_MODE4) /* gpio56 */ >; }; + + hmc5843_pins: pinmux_hmc5843_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2134, PIN_INPUT_PULLUP | MUX_MODE4) /* gpio112 */ + >; + }; }; &omap3_pmx_core2 { @@ -389,6 +395,10 @@ hmc5843@1e { compatible = "honeywell,hmc5883l"; reg = <0x1e>; + pinctrl-names = "default"; + pinctrl-0 = <&hmc5843_pins>; + interrupt-parent = <&gpio4>; + interrupts = <16 IRQ_TYPE_EDGE_FALLING>; /* gpio112 */ }; /* touchscreen */ -- cgit v0.10.2 From c2df98c000523789b799cf25798d3c5d6363fa0e Mon Sep 17 00:00:00 2001 From: "H. Nikolaus Schaller" Date: Tue, 17 May 2016 21:48:51 +0200 Subject: ARM: dts: omap3-gat04: Fix wifi handling Without that change wifi card isn't probed because pwrseq is necessary for libertas chip. Signed-off-by: H. Nikolaus Schaller Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/omap3-gta04.dtsi b/arch/arm/boot/dts/omap3-gta04.dtsi index 55b6b88..6349257 100644 --- a/arch/arm/boot/dts/omap3-gta04.dtsi +++ b/arch/arm/boot/dts/omap3-gta04.dtsi @@ -155,6 +155,11 @@ }; }; }; + + wifi_pwrseq: wifi_pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&tca6507 0 GPIO_ACTIVE_LOW>; /* W2CBW003 reset through tca6507 */ + }; }; &omap3_pmx_core { @@ -354,8 +359,8 @@ interrupts = <24 IRQ_TYPE_EDGE_FALLING>; /* GPIO_56 */ }; - /* leds */ - tca6507@45 { + /* leds + gpios */ + tca6507: tca6507@45 { compatible = "ti,tca6507"; #address-cells = <1>; #size-cells = <0>; @@ -446,6 +451,7 @@ bus-width = <4>; ti,non-removable; cap-power-off-card; + mmc-pwrseq = <&wifi_pwrseq>; }; &mmc3 { -- cgit v0.10.2 From fb515b8e384d8b1a46c664c1ff6c57fdf4dcbd6c Mon Sep 17 00:00:00 2001 From: Dave Gerlach Date: Wed, 18 May 2016 18:36:26 -0500 Subject: ARM: dts: am335x: Update MPU regulator range for TI boards Now that we are moving to OPPv2 bindings and able to add 1GHz OPP for MPU, let's update the max MPU voltage range to align with the maximum possible value allowed in the operating-points table, which is max target voltage of 132500 uV + 2%. Signed-off-by: Dave Gerlach Acked-by: Viresh Kumar Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/am335x-bone-common.dtsi b/arch/arm/boot/dts/am335x-bone-common.dtsi index 0cc150b..13133f3 100644 --- a/arch/arm/boot/dts/am335x-bone-common.dtsi +++ b/arch/arm/boot/dts/am335x-bone-common.dtsi @@ -318,7 +318,7 @@ /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ regulator-name = "vdd_mpu"; regulator-min-microvolt = <925000>; - regulator-max-microvolt = <1325000>; + regulator-max-microvolt = <1351500>; regulator-boot-on; regulator-always-on; }; diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts index 516673b..5d28712 100644 --- a/arch/arm/boot/dts/am335x-evm.dts +++ b/arch/arm/boot/dts/am335x-evm.dts @@ -640,7 +640,7 @@ /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ regulator-name = "vdd_mpu"; regulator-min-microvolt = <912500>; - regulator-max-microvolt = <1312500>; + regulator-max-microvolt = <1351500>; regulator-boot-on; regulator-always-on; }; diff --git a/arch/arm/boot/dts/am335x-evmsk.dts b/arch/arm/boot/dts/am335x-evmsk.dts index 282fe1b..09308d6 100644 --- a/arch/arm/boot/dts/am335x-evmsk.dts +++ b/arch/arm/boot/dts/am335x-evmsk.dts @@ -560,7 +560,7 @@ /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ regulator-name = "vdd_mpu"; regulator-min-microvolt = <912500>; - regulator-max-microvolt = <1312500>; + regulator-max-microvolt = <1351500>; regulator-boot-on; regulator-always-on; }; -- cgit v0.10.2 From 4317be1162108bcdf50dc53dfb48eac94dcff25c Mon Sep 17 00:00:00 2001 From: Dave Gerlach Date: Wed, 18 May 2016 18:36:27 -0500 Subject: ARM: dts: am33xx: Move to operating-points-v2 table and ti-cpufreq driver Drop the operating-points table present in am33xx.dtsi and add an operating-points-v2 table with all OPPs available for all silicon revisions along with necessary data for use by ti-cpufreq to selectively enable the appropriate OPPs at runtime. Also, drop the voltage-tolerance value and provide voltages for each OPP using the format instead. Information from AM335x Data Manual, SPRS717i, Revised December 2015, Table 5-7. Signed-off-by: Dave Gerlach Acked-by: Viresh Kumar Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi index 2661acc..2625414 100644 --- a/arch/arm/boot/dts/am33xx.dtsi +++ b/arch/arm/boot/dts/am33xx.dtsi @@ -45,19 +45,9 @@ device_type = "cpu"; reg = <0>; - /* - * To consider voltage drop between PMIC and SoC, - * tolerance value is reduced to 2% from 4% and - * voltage value is increased as a precaution. - */ - operating-points = < - /* kHz uV */ - 720000 1285000 - 600000 1225000 - 500000 1125000 - 275000 1125000 - >; - voltage-tolerance = <2>; /* 2 percentage */ + operating-points-v2 = <&cpu0_opp_table>; + ti,syscon-efuse = <&scm_conf 0x7fc 0x1fff 0>; + ti,syscon-rev = <&scm_conf 0x600>; clocks = <&dpll_mpu_ck>; clock-names = "cpu"; @@ -66,6 +56,78 @@ }; }; + cpu0_opp_table: opp_table0 { + compatible = "operating-points-v2"; + + /* + * The three following nodes are marked with opp-suspend + * because the can not be enabled simultaneously on a + * single SoC. + */ + opp50@300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <950000 931000 969000>; + opp-supported-hw = <0x06 0x0010>; + opp-suspend; + }; + + opp100@275000000 { + opp-hz = /bits/ 64 <275000000>; + opp-microvolt = <1100000 1078000 1122000>; + opp-supported-hw = <0x01 0x00FF>; + opp-suspend; + }; + + opp100@300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <1100000 1078000 1122000>; + opp-supported-hw = <0x06 0x0020>; + opp-suspend; + }; + + opp100@500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <1100000 1078000 1122000>; + opp-supported-hw = <0x01 0xFFFF>; + }; + + opp100@600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <1100000 1078000 1122000>; + opp-supported-hw = <0x06 0x0040>; + }; + + opp120@600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <1200000 1176000 1224000>; + opp-supported-hw = <0x01 0xFFFF>; + }; + + opp120@720000000 { + opp-hz = /bits/ 64 <720000000>; + opp-microvolt = <1200000 1176000 1224000>; + opp-supported-hw = <0x06 0x0080>; + }; + + oppturbo@720000000 { + opp-hz = /bits/ 64 <720000000>; + opp-microvolt = <1260000 1234800 1285200>; + opp-supported-hw = <0x01 0xFFFF>; + }; + + oppturbo@800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <1260000 1234800 1285200>; + opp-supported-hw = <0x06 0x0100>; + }; + + oppnitro@1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <1325000 1298500 1351500>; + opp-supported-hw = <0x04 0x0200>; + }; + }; + pmu { compatible = "arm,cortex-a8-pmu"; interrupts = <3>; -- cgit v0.10.2 From c36e6ec904876de1935b1d74d2d711e6f5ceb572 Mon Sep 17 00:00:00 2001 From: Dave Gerlach Date: Wed, 18 May 2016 18:36:28 -0500 Subject: ARM: dts: am335x-boneblack: Enable 1GHz OPP for cpu Although all PG2.0 silicon may not support 1GHz OPP for the MPU, older Beaglebone Blacks may have PG2.0 silicon populated and these particular parts are guaranteed to support the OPP, so enable it for PG2.0 on am335x-boneblack only. Signed-off-by: Dave Gerlach Acked-by: Viresh Kumar Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/am335x-boneblack.dts b/arch/arm/boot/dts/am335x-boneblack.dts index 55c0e95..ca72167 100644 --- a/arch/arm/boot/dts/am335x-boneblack.dts +++ b/arch/arm/boot/dts/am335x-boneblack.dts @@ -33,6 +33,17 @@ status = "okay"; }; +&cpu0_opp_table { + /* + * All PG 2.0 silicon may not support 1GHz but some of the early + * BeagleBone Blacks have PG 2.0 silicon which is guaranteed + * to support 1GHz OPP so enable it for PG 2.0 on this board. + */ + oppnitro@1000000000 { + opp-supported-hw = <0x06 0x0100>; + }; +}; + &am33xx_pinmux { nxp_hdmi_bonelt_pins: nxp_hdmi_bonelt_pins { pinctrl-single,pins = < -- cgit v0.10.2 From 6da9c792b309bd34f5870943a16ee849975f4e10 Mon Sep 17 00:00:00 2001 From: Dave Gerlach Date: Wed, 18 May 2016 18:36:29 -0500 Subject: ARM: dts: am4372: Add operating-points-v2 table Add an operating-points-v2 table with all OPPs available for all silicon revisions along with necessary data for use by ti-cpufreq to selectively enable the appropriate OPPs at runtime. Information from AM437x Data Manual, SPRS851B, Revised April 2015, Table 5-2. Signed-off-by: Dave Gerlach Acked-by: Viresh Kumar Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi index cfdd4b7..5a065b8 100644 --- a/arch/arm/boot/dts/am4372.dtsi +++ b/arch/arm/boot/dts/am4372.dtsi @@ -44,10 +44,49 @@ clocks = <&dpll_mpu_ck>; clock-names = "cpu"; + operating-points-v2 = <&cpu0_opp_table>; + ti,syscon-efuse = <&scm_conf 0x610 0x3f 0>; + ti,syscon-rev = <&scm_conf 0x600>; + clock-latency = <300000>; /* From omap-cpufreq driver */ }; }; + cpu0_opp_table: opp_table0 { + compatible = "operating-points-v2"; + + opp50@300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <950000 931000 969000>; + opp-supported-hw = <0xFF 0x01>; + opp-suspend; + }; + + opp100@600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <1100000 1078000 1122000>; + opp-supported-hw = <0xFF 0x04>; + }; + + opp120@720000000 { + opp-hz = /bits/ 64 <720000000>; + opp-microvolt = <1200000 1176000 1224000>; + opp-supported-hw = <0xFF 0x08>; + }; + + oppturbo@800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <1260000 1234800 1285200>; + opp-supported-hw = <0xFF 0x10>; + }; + + oppnitro@1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <1325000 1298500 1351500>; + opp-supported-hw = <0xFF 0x20>; + }; + }; + gic: interrupt-controller@48241000 { compatible = "arm,cortex-a9-gic"; interrupt-controller; -- cgit v0.10.2 From 2af84bdd12502f8d61682d7b230cc67aa8ba1499 Mon Sep 17 00:00:00 2001 From: Dave Gerlach Date: Wed, 18 May 2016 18:36:30 -0500 Subject: ARM: dts: am437x-gp-evm: Hook dcdc2 as the cpu0-supply Hook dcdc2 as the cpu0-supply. Signed-off-by: Dave Gerlach Acked-by: Viresh Kumar Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/am437x-gp-evm.dts b/arch/arm/boot/dts/am437x-gp-evm.dts index 5bcd3aa..84832bf 100644 --- a/arch/arm/boot/dts/am437x-gp-evm.dts +++ b/arch/arm/boot/dts/am437x-gp-evm.dts @@ -975,3 +975,7 @@ clock-names = "ext-clk", "int-clk"; status = "okay"; }; + +&cpu { + cpu0-supply = <&dcdc2>; +}; -- cgit v0.10.2 From 62e4feed0b0b9bc73d0aa843a6a6d259cb5197e4 Mon Sep 17 00:00:00 2001 From: Dave Gerlach Date: Wed, 18 May 2016 18:36:31 -0500 Subject: ARM: dts: dra7: Add dt node for the syscon control module wkup Create a system control module node for the control module portion that resides under l4_wkup. Signed-off-by: Dave Gerlach Acked-by: Viresh Kumar Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index d8c0dd1..cc4cb76 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -233,6 +233,11 @@ prm_clockdomains: clockdomains { }; }; + + scm_wkup: scm_conf@c000 { + compatible = "syscon"; + reg = <0xc000 0x1000>; + }; }; axi@0 { -- cgit v0.10.2 From b82ffb337b69947bf82d936827fe5c6e2ad6abdd Mon Sep 17 00:00:00 2001 From: Dave Gerlach Date: Wed, 18 May 2016 18:36:32 -0500 Subject: ARM: dts: dra7: Move cpus node to parent dts for dra74x and dra72x Nearly all of the information in the cpus node, especially for cpu0, is the same between dra74x and dra72x so move the common information to the parent dra7.dtsi to avoid duplication of data. Signed-off-by: Dave Gerlach Acked-by: Viresh Kumar Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index cc4cb76..b1e9f5c 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -73,6 +73,33 @@ interrupt-parent = <&gic>; }; + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0>; + + operating-points = < + /* kHz uV */ + 1000000 1060000 + 1176000 1160000 + >; + + clocks = <&dpll_mpu_ck>; + clock-names = "cpu"; + + clock-latency = <300000>; /* From omap-cpufreq driver */ + + /* cooling options */ + cooling-min-level = <0>; + cooling-max-level = <2>; + #cooling-cells = <2>; /* min followed by max */ + }; + }; + /* * The soc node represents the soc top level view. It is used for IPs * that are not memory mapped in the MPU view or for the MPU itself. diff --git a/arch/arm/boot/dts/dra72x.dtsi b/arch/arm/boot/dts/dra72x.dtsi index 70a2170..6710760 100644 --- a/arch/arm/boot/dts/dra72x.dtsi +++ b/arch/arm/boot/dts/dra72x.dtsi @@ -12,22 +12,6 @@ / { compatible = "ti,dra722", "ti,dra72", "ti,dra7"; - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0>; - - /* cooling options */ - cooling-min-level = <0>; - cooling-max-level = <2>; - #cooling-cells = <2>; /* min followed by max */ - }; - }; - pmu { compatible = "arm,cortex-a15-pmu"; interrupt-parent = <&wakeupgen>; diff --git a/arch/arm/boot/dts/dra74x.dtsi b/arch/arm/boot/dts/dra74x.dtsi index 4220eef..0c31db3 100644 --- a/arch/arm/boot/dts/dra74x.dtsi +++ b/arch/arm/boot/dts/dra74x.dtsi @@ -13,30 +13,6 @@ compatible = "ti,dra742", "ti,dra74", "ti,dra7"; cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0>; - - operating-points = < - /* kHz uV */ - 1000000 1060000 - 1176000 1160000 - >; - - clocks = <&dpll_mpu_ck>; - clock-names = "cpu"; - - clock-latency = <300000>; /* From omap-cpufreq driver */ - - /* cooling options */ - cooling-min-level = <0>; - cooling-max-level = <2>; - #cooling-cells = <2>; /* min followed by max */ - }; cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a15"; -- cgit v0.10.2 From f80bc97fd0a9711ef11bdb3e63c2c01115a82c47 Mon Sep 17 00:00:00 2001 From: Dave Gerlach Date: Wed, 18 May 2016 18:36:33 -0500 Subject: ARM: dts: dra7: Move to operating-points-v2 table Add an operating-points-v2 table with all OPPs available for all silicon revisions along with necessary data for use by ti-opp driver to selectively enable the appropriate OPPs at runtime and handle voltage transitions As we now need to define voltage ranges for each OPP, we define the minimum and maximum voltage to match the ranges possible for AVS class0 voltage as defined by the DRA7/AM57 Data Manual, with the exception of using a range for OPP_OD based on historical data to ensure that SoCs from older lots still continue to boot, even though more optimal voltages are now the standard. Once an AVS Class0 driver is in place it will be possible for these OPP voltages to be adjusted to any voltage within the provided range. Information from SPRS953, Revised December 2015. Signed-off-by: Dave Gerlach Acked-by: Viresh Kumar Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index b1e9f5c..c3e67ee 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -82,11 +82,9 @@ compatible = "arm,cortex-a15"; reg = <0>; - operating-points = < - /* kHz uV */ - 1000000 1060000 - 1176000 1160000 - >; + operating-points-v2 = <&cpu0_opp_table>; + ti,syscon-efuse = <&scm_wkup 0x20c 0xf80000 19>; + ti,syscon-rev = <&scm_wkup 0x204>; clocks = <&dpll_mpu_ck>; clock-names = "cpu"; @@ -100,6 +98,24 @@ }; }; + cpu0_opp_table: opp_table0 { + compatible = "operating-points-v2"; + opp-shared; + + opp_nom@1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <1060000 850000 1150000>; + opp-supported-hw = <0xFF 0x01>; + opp-suspend; + }; + + opp_od@1176000000 { + opp-hz = /bits/ 64 <1176000000>; + opp-microvolt = <1160000 885000 1160000>; + opp-supported-hw = <0xFF 0x02>; + }; + }; + /* * The soc node represents the soc top level view. It is used for IPs * that are not memory mapped in the MPU view or for the MPU itself. diff --git a/arch/arm/boot/dts/dra74x.dtsi b/arch/arm/boot/dts/dra74x.dtsi index 0c31db3..0a8a5ee 100644 --- a/arch/arm/boot/dts/dra74x.dtsi +++ b/arch/arm/boot/dts/dra74x.dtsi @@ -17,6 +17,7 @@ device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <1>; + operating-points-v2 = <&cpu0_opp_table>; }; }; -- cgit v0.10.2 From eaa03e4251196ad9cb70613fb577134814c31f1e Mon Sep 17 00:00:00 2001 From: Vignesh R Date: Thu, 19 May 2016 12:17:30 +0530 Subject: ARM: dts: am335x-icev2: Add DT node for TI PCA9536 AM335x ICE board has a TI PCA9536 chip connected to I2C0 at address 0x41. Add DT entry for the same. Signed-off-by: Vignesh R Acked-by: Kristofer Martinez Acked-by: Linus Walleij Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/am335x-icev2.dts b/arch/arm/boot/dts/am335x-icev2.dts index e271013..7d8b8fe 100644 --- a/arch/arm/boot/dts/am335x-icev2.dts +++ b/arch/arm/boot/dts/am335x-icev2.dts @@ -206,6 +206,13 @@ gpio-controller; #gpio-cells = <2>; }; + + pca9536: gpio@41 { + compatible = "ti,pca9536"; + reg = <0x41>; + gpio-controller; + #gpio-cells = <2>; + }; }; #include "tps65910.dtsi" -- cgit v0.10.2 From 7172e745d5980ace6e068f6037b834922a3eba64 Mon Sep 17 00:00:00 2001 From: Misael Lopez Cruz Date: Tue, 24 May 2016 15:00:40 -0500 Subject: ARM: dts: dra72-evm: Rename 3.3V regulator tag Rename the tag of the 3.3 V regulator used in the DRA72 EVM in order to have a consistent tag name with the DRA7 EVM. This is useful when the regulator needs to be referenced in common dtsi files (i.e. for common companion boards like JAMR3 [1]). [1] http://www.ti.com.cn/cn/lit/ug/sprui52/sprui52.pdf Signed-off-by: Misael Lopez Cruz Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/dra72-evm-common.dtsi b/arch/arm/boot/dts/dra72-evm-common.dtsi index 093538e..9d3cf50 100644 --- a/arch/arm/boot/dts/dra72-evm-common.dtsi +++ b/arch/arm/boot/dts/dra72-evm-common.dtsi @@ -18,7 +18,7 @@ display0 = &hdmi0; }; - evm_3v3: fixedregulator-evm_3v3 { + evm_3v3_sw: fixedregulator-evm_3v3 { compatible = "regulator-fixed"; regulator-name = "evm_3v3"; regulator-min-microvolt = <3300000>; @@ -29,7 +29,7 @@ /* TPS77018DBVT */ compatible = "regulator-fixed"; regulator-name = "aic_dvdd"; - vin-supply = <&evm_3v3>; + vin-supply = <&evm_3v3_sw>; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; @@ -414,9 +414,9 @@ status = "okay"; /* Regulators */ - AVDD-supply = <&evm_3v3>; - IOVDD-supply = <&evm_3v3>; - DRVDD-supply = <&evm_3v3>; + AVDD-supply = <&evm_3v3_sw>; + IOVDD-supply = <&evm_3v3_sw>; + DRVDD-supply = <&evm_3v3_sw>; DVDD-supply = <&aic_dvdd>; }; }; @@ -597,7 +597,7 @@ pinctrl-names = "default"; pinctrl-0 = <&mmc2_pins_default>; - vmmc-supply = <&evm_3v3>; + vmmc-supply = <&evm_3v3_sw>; bus-width = <8>; ti,non-removable; max-frequency = <192000000>; -- cgit v0.10.2 From a5206553bab2a7d5777e0fdfb5ac8c534a28f15a Mon Sep 17 00:00:00 2001 From: "Robert P. J. Day" Date: Tue, 24 May 2016 17:20:28 -0400 Subject: ARM: dts: Correct misspelling, "emda3" -> "edma3" Correct misspelling, "emda3" -> "edma3". Reported-by: Adam J Allison Signed-off-by: Robert P. J. Day Acked-by: Rob Herring Acked-by: Peter Ujfalusi Signed-off-by: Tony Lindgren diff --git a/Documentation/devicetree/bindings/dma/ti-edma.txt b/Documentation/devicetree/bindings/dma/ti-edma.txt index 079b42a..18090e7 100644 --- a/Documentation/devicetree/bindings/dma/ti-edma.txt +++ b/Documentation/devicetree/bindings/dma/ti-edma.txt @@ -15,7 +15,7 @@ Required properties: - reg: Memory map of eDMA CC - reg-names: "edma3_cc" - interrupts: Interrupt lines for CCINT, MPERR and CCERRINT. -- interrupt-names: "edma3_ccint", "emda3_mperr" and "edma3_ccerrint" +- interrupt-names: "edma3_ccint", "edma3_mperr" and "edma3_ccerrint" - ti,tptcs: List of TPTCs associated with the eDMA in the following form: <&tptc_phandle TC_priority_number>. The highest priority is 0. @@ -48,7 +48,7 @@ edma: edma@49000000 { reg = <0x49000000 0x10000>; reg-names = "edma3_cc"; interrupts = <12 13 14>; - interrupt-names = "edma3_ccint", "emda3_mperr", "edma3_ccerrint"; + interrupt-names = "edma3_ccint", "edma3_mperr", "edma3_ccerrint"; dma-requests = <64>; #dma-cells = <2>; diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi index 2625414..af18c47 100644 --- a/arch/arm/boot/dts/am33xx.dtsi +++ b/arch/arm/boot/dts/am33xx.dtsi @@ -249,7 +249,7 @@ reg = <0x49000000 0x10000>; reg-names = "edma3_cc"; interrupts = <12 13 14>; - interrupt-names = "edma3_ccint", "emda3_mperr", + interrupt-names = "edma3_ccint", "edma3_mperr", "edma3_ccerrint"; dma-requests = <64>; #dma-cells = <2>; diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi index 5a065b8..0351466 100644 --- a/arch/arm/boot/dts/am4372.dtsi +++ b/arch/arm/boot/dts/am4372.dtsi @@ -238,7 +238,7 @@ interrupts = , , ; - interrupt-names = "edma3_ccint", "emda3_mperr", + interrupt-names = "edma3_ccint", "edma3_mperr", "edma3_ccerrint"; dma-requests = <64>; #dma-cells = <2>; diff --git a/arch/arm/boot/dts/dm814x.dtsi b/arch/arm/boot/dts/dm814x.dtsi index d4537dc..a6e0aebc 100644 --- a/arch/arm/boot/dts/dm814x.dtsi +++ b/arch/arm/boot/dts/dm814x.dtsi @@ -448,7 +448,7 @@ reg = <0x49000000 0x10000>; reg-names = "edma3_cc"; interrupts = <12 13 14>; - interrupt-names = "edma3_ccint", "emda3_mperr", + interrupt-names = "edma3_ccint", "edma3_mperr", "edma3_ccerrint"; dma-requests = <64>; #dma-cells = <2>; diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index c3e67ee..5f1e029 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -436,7 +436,7 @@ interrupts = , , ; - interrupt-names = "edma3_ccint", "emda3_mperr", + interrupt-names = "edma3_ccint", "edma3_mperr", "edma3_ccerrint"; dma-requests = <64>; #dma-cells = <2>; -- cgit v0.10.2 From 759bc77b9a9ca661ef3edca1554f3edf6c5a5615 Mon Sep 17 00:00:00 2001 From: "Andrew F. Davis" Date: Fri, 27 May 2016 13:17:42 -0500 Subject: ARM: dts: am437x-idk-evm: Mark MAC as having only one PHY Currently am4372.dtsi declares the MAC controller to have two slave ports, on this board we only use one, so set the slave count to one. This eliminates a console error message when the non-existent PHY is not detected. Signed-off-by: Andrew F. Davis Reviewed-by: Grygorii Strashko Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/am437x-idk-evm.dts b/arch/arm/boot/dts/am437x-idk-evm.dts index 76dcfc6..12a6951 100644 --- a/arch/arm/boot/dts/am437x-idk-evm.dts +++ b/arch/arm/boot/dts/am437x-idk-evm.dts @@ -382,6 +382,7 @@ }; &mac { + slaves = <1>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&cpsw_default>; pinctrl-1 = <&cpsw_sleep>; -- cgit v0.10.2 From fd4eeada1bf1264f7ff21fb5368ff1d17703af96 Mon Sep 17 00:00:00 2001 From: "Andrew F. Davis" Date: Fri, 27 May 2016 13:17:43 -0500 Subject: ARM: dts: am335x-bone-common: Mark MAC as having only one PHY Currently am33xx.dtsi declares the MAC controller to have two slave ports, on these boards we only use one, so set the slave count to one. This eliminates a console error message when the non-existent PHY is not detected. Signed-off-by: Andrew F. Davis Reviewed-by: Grygorii Strashko Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/am335x-bone-common.dtsi b/arch/arm/boot/dts/am335x-bone-common.dtsi index 13133f3..6b06096 100644 --- a/arch/arm/boot/dts/am335x-bone-common.dtsi +++ b/arch/arm/boot/dts/am335x-bone-common.dtsi @@ -359,12 +359,8 @@ phy-mode = "mii"; }; -&cpsw_emac1 { - phy_id = <&davinci_mdio>, <1>; - phy-mode = "mii"; -}; - &mac { + slaves = <1>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&cpsw_default>; pinctrl-1 = <&cpsw_sleep>; -- cgit v0.10.2 From 138e996c214b83a8bcc730cb9e52584b278f5204 Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Mon, 30 May 2016 11:23:44 +0300 Subject: ARM: dts: omap3: Add clocks to McBSP nodes Add clock properties to the McBSP nodes. McBSP2 and 3 need to have ick also since the Sidetone block of these modules are operating using the McBSP interface clock. Signed-off-by: Peter Ujfalusi Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi index 9fbda38..4c3c471 100644 --- a/arch/arm/boot/dts/omap3.dtsi +++ b/arch/arm/boot/dts/omap3.dtsi @@ -493,6 +493,8 @@ dmas = <&sdma 31>, <&sdma 32>; dma-names = "tx", "rx"; + clocks = <&mcbsp1_fck>; + clock-names = "fck"; status = "disabled"; }; @@ -511,6 +513,8 @@ dmas = <&sdma 33>, <&sdma 34>; dma-names = "tx", "rx"; + clocks = <&mcbsp2_fck>, <&mcbsp2_ick>; + clock-names = "fck", "ick"; status = "disabled"; }; @@ -529,6 +533,8 @@ dmas = <&sdma 17>, <&sdma 18>; dma-names = "tx", "rx"; + clocks = <&mcbsp3_fck>, <&mcbsp3_ick>; + clock-names = "fck", "ick"; status = "disabled"; }; @@ -545,6 +551,8 @@ dmas = <&sdma 19>, <&sdma 20>; dma-names = "tx", "rx"; + clocks = <&mcbsp4_fck>; + clock-names = "fck"; status = "disabled"; }; @@ -561,6 +569,8 @@ dmas = <&sdma 21>, <&sdma 22>; dma-names = "tx", "rx"; + clocks = <&mcbsp5_fck>; + clock-names = "fck"; status = "disabled"; }; -- cgit v0.10.2 From 9e21c75d9265925718e7ae491443825869a2f30e Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Mon, 30 May 2016 11:55:14 +0300 Subject: ARM: dts: omap5-board-common: Add pdmclk binding for audio The twl6040 codec is generating the pdmclk, which is used by the McPDM as functional clock. Signed-off-by: Peter Ujfalusi Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/omap5-board-common.dtsi b/arch/arm/boot/dts/omap5-board-common.dtsi index dc759a3..b95b221 100644 --- a/arch/arm/boot/dts/omap5-board-common.dtsi +++ b/arch/arm/boot/dts/omap5-board-common.dtsi @@ -594,6 +594,7 @@ twl6040: twl@4b { compatible = "ti,twl6040"; + #clock-cells = <0>; reg = <0x4b>; pinctrl-names = "default"; @@ -614,6 +615,10 @@ &mcpdm { pinctrl-names = "default"; pinctrl-0 = <&mcpdm_pins>; + + clocks = <&twl6040>; + clock-names = "pdmclk"; + status = "okay"; }; -- cgit v0.10.2 From 2ab60a38accebadc2bf531b6c56e12c38b8fa91d Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Mon, 30 May 2016 11:55:15 +0300 Subject: ARM: dts: omap4-panda-common: Add pdmclk binding for audio The twl6040 codec is generating the pdmclk, which is used by the McPDM as functional clock. Signed-off-by: Peter Ujfalusi Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi b/arch/arm/boot/dts/omap4-panda-common.dtsi index df2e356..e1d606f 100644 --- a/arch/arm/boot/dts/omap4-panda-common.dtsi +++ b/arch/arm/boot/dts/omap4-panda-common.dtsi @@ -376,6 +376,7 @@ twl6040: twl@4b { compatible = "ti,twl6040"; + #clock-cells = <0>; reg = <0x4b>; pinctrl-names = "default"; @@ -479,6 +480,10 @@ &mcpdm { pinctrl-names = "default"; pinctrl-0 = <&mcpdm_pins>; + + clocks = <&twl6040>; + clock-names = "pdmclk"; + status = "okay"; }; -- cgit v0.10.2 From 3cec531b47fd6b99f9ecaac807ece06369d5aa88 Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Mon, 30 May 2016 11:55:16 +0300 Subject: ARM: dts: omap4-sdp: Add pdmclk binding for audio The twl6040 codec is generating the pdmclk, which is used by the McPDM as functional clock. Signed-off-by: Peter Ujfalusi Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/omap4-sdp.dts b/arch/arm/boot/dts/omap4-sdp.dts index aae5132..7e6cd2d 100644 --- a/arch/arm/boot/dts/omap4-sdp.dts +++ b/arch/arm/boot/dts/omap4-sdp.dts @@ -367,6 +367,7 @@ twl6040: twl@4b { compatible = "ti,twl6040"; + #clock-cells = <0>; reg = <0x4b>; pinctrl-names = "default"; @@ -620,6 +621,10 @@ &mcpdm { pinctrl-names = "default"; pinctrl-0 = <&mcpdm_pins>; + + clocks = <&twl6040>; + clock-names = "pdmclk"; + status = "okay"; }; -- cgit v0.10.2 From 26b87e04dedb55801a817dd5fb18609e9207eaf3 Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Mon, 30 May 2016 11:55:17 +0300 Subject: ARM: dts: omap4-var-som-om44: Add pdmclk binding for audio The twl6040 codec is generating the pdmclk, which is used by the McPDM as functional clock. Signed-off-by: Peter Ujfalusi Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/omap4-var-som-om44.dtsi b/arch/arm/boot/dts/omap4-var-som-om44.dtsi index a17997f..873cfc8 100644 --- a/arch/arm/boot/dts/omap4-var-som-om44.dtsi +++ b/arch/arm/boot/dts/omap4-var-som-om44.dtsi @@ -189,6 +189,7 @@ twl6040: twl@4b { compatible = "ti,twl6040"; + #clock-cells = <0>; reg = <0x4b>; pinctrl-names = "default"; @@ -252,6 +253,10 @@ &mcpdm { pinctrl-names = "default"; pinctrl-0 = <&mcpdm_pins>; + + clocks = <&twl6040>; + clock-names = "pdmclk"; + status = "okay"; }; -- cgit v0.10.2 From d471c277f495a864c7ca9538513e0f701eb82e39 Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Mon, 30 May 2016 11:55:18 +0300 Subject: ARM: dts: omap4-duovero: Add pdmclk binding for audio The twl6040 codec is generating the pdmclk, which is used by the McPDM as functional clock. Signed-off-by: Peter Ujfalusi Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/omap4-duovero.dtsi b/arch/arm/boot/dts/omap4-duovero.dtsi index f2a94fa..a90b582 100644 --- a/arch/arm/boot/dts/omap4-duovero.dtsi +++ b/arch/arm/boot/dts/omap4-duovero.dtsi @@ -177,6 +177,7 @@ twl6040: twl@4b { compatible = "ti,twl6040"; + #clock-cells = <0>; reg = <0x4b>; interrupts = ; /* IRQ_SYS_2N cascaded to gic */ ti,audpwron-gpio = <&gpio6 0 GPIO_ACTIVE_HIGH>; /* gpio_160 */ @@ -207,6 +208,10 @@ &mcpdm { pinctrl-names = "default"; pinctrl-0 = <&mcpdm_pins>; + + clocks = <&twl6040>; + clock-names = "pdmclk"; + status = "okay"; }; -- cgit v0.10.2 From 4393dd4ecaa729204d2c7eebb970b1412af195ec Mon Sep 17 00:00:00 2001 From: "H. Nikolaus Schaller" Date: Sat, 4 Jun 2016 14:05:55 +0200 Subject: ARM: dts: omap3-gta04: Add RFID eeprom node Define RFID eeprom node which is present on gta04 device. Signed-off-by: H. Nikolaus Schaller Signed-off-by: Marek Belisko Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/omap3-gta04.dtsi b/arch/arm/boot/dts/omap3-gta04.dtsi index 6349257..3eb53bc 100644 --- a/arch/arm/boot/dts/omap3-gta04.dtsi +++ b/arch/arm/boot/dts/omap3-gta04.dtsi @@ -415,6 +415,12 @@ gpios = <&gpio6 0 GPIO_ACTIVE_LOW>; ti,x-plate-ohms = <600>; }; + + /* RFID EEPROM */ + m24lr64@50 { + compatible = "at,24c64"; + reg = <0x50>; + }; }; &i2c3 { -- cgit v0.10.2 From 605b3d302dc6cdeeed95fb9294b7a010b562b1fb Mon Sep 17 00:00:00 2001 From: Kishon Vijay Abraham I Date: Thu, 9 Jun 2016 20:43:55 +0530 Subject: ARM: dts: DRA7: fix unit address of second PCIe instance The unit address of the second PCIe instance is set to be same as that of the first instance (copy-paste error). Fix it. Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Sekhar Nori Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index 5f1e029..3c34a0c 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -324,7 +324,7 @@ ranges = <0x51800000 0x51800000 0x3000 0x0 0x30000000 0x10000000>; status = "disabled"; - pcie@51000000 { + pcie@51800000 { compatible = "ti,dra7-pcie"; reg = <0x51800000 0x2000>, <0x51802000 0x14c>, <0x1000 0x2000>; reg-names = "rc_dbics", "ti_conf", "config"; -- cgit v0.10.2 From 1ebcb168c580ef172007521890aff2a428d77a7f Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 9 Jun 2016 21:43:10 +0200 Subject: ARM: dts: mxs: Add SSP2 SD mux Add pinmux configuration for SSP2 port in SD mode, both for the 4-bit and 8-bit case. Signed-off-by: Marek Vasut Cc: Fabio Estevam Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/imx23.dtsi b/arch/arm/boot/dts/imx23.dtsi index 302d116..c70ebef 100644 --- a/arch/arm/boot/dts/imx23.dtsi +++ b/arch/arm/boot/dts/imx23.dtsi @@ -249,6 +249,40 @@ fsl,pull-up = ; }; + mmc1_4bit_pins_a: mmc1-4bit@0 { + reg = <0>; + fsl,pinmux-ids = < + MX23_PAD_GPMI_D00__SSP2_DATA0 + MX23_PAD_GPMI_D01__SSP2_DATA1 + MX23_PAD_GPMI_D02__SSP2_DATA2 + MX23_PAD_GPMI_D03__SSP2_DATA3 + MX23_PAD_GPMI_RDY1__SSP2_CMD + MX23_PAD_GPMI_WRN__SSP2_SCK + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + mmc1_8bit_pins_a: mmc1-8bit@0 { + reg = <0>; + fsl,pinmux-ids = < + MX23_PAD_GPMI_D00__SSP2_DATA0 + MX23_PAD_GPMI_D01__SSP2_DATA1 + MX23_PAD_GPMI_D02__SSP2_DATA2 + MX23_PAD_GPMI_D03__SSP2_DATA3 + MX23_PAD_GPMI_D04__SSP2_DATA4 + MX23_PAD_GPMI_D05__SSP2_DATA5 + MX23_PAD_GPMI_D06__SSP2_DATA6 + MX23_PAD_GPMI_D07__SSP2_DATA7 + MX23_PAD_GPMI_RDY1__SSP2_CMD + MX23_PAD_GPMI_WRN__SSP2_SCK + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + pwm2_pins_a: pwm2@0 { reg = <0>; fsl,pinmux-ids = < -- cgit v0.10.2 From d33c731b8a506305f160693b7ac7cf188884e673 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 9 Jun 2016 21:43:11 +0200 Subject: ARM: dts: mxs: Add AUART2 pinmux Add 2-pin pinmux settings for AUART2. Signed-off-by: Marek Vasut Cc: Fabio Estevam Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/imx23.dtsi b/arch/arm/boot/dts/imx23.dtsi index c70ebef..0c9a357 100644 --- a/arch/arm/boot/dts/imx23.dtsi +++ b/arch/arm/boot/dts/imx23.dtsi @@ -171,6 +171,17 @@ fsl,pull-up = ; }; + auart1_2pins_a: auart1-2pins@0 { + reg = <0>; + fsl,pinmux-ids = < + MX23_PAD_GPMI_D14__AUART2_RX + MX23_PAD_GPMI_D15__AUART2_TX + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + gpmi_pins_a: gpmi-nand@0 { reg = <0>; fsl,pinmux-ids = < -- cgit v0.10.2 From 053034f0a2c5283a802c2bc0ff485beb99196c2c Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 9 Jun 2016 21:43:12 +0200 Subject: ARM: dts: mxs: Add Creative X-Fi3 support Add support for this small MP3 player based on STMP3780 (rev.4). Currently supported is both external microSD and internal SD-NAND bridge, PWM and USB gadget. Signed-off-by: Marek Vasut Cc: Fabio Estevam Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 06b6c2d..1235934 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -417,6 +417,7 @@ dtb-$(CONFIG_ARCH_MXS) += \ imx23-evk.dtb \ imx23-olinuxino.dtb \ imx23-stmp378x_devb.dtb \ + imx23-xfi3.dtb \ imx28-apf28.dtb \ imx28-apf28dev.dtb \ imx28-apx4devkit.dtb \ diff --git a/arch/arm/boot/dts/imx23-xfi3.dts b/arch/arm/boot/dts/imx23-xfi3.dts new file mode 100644 index 0000000..025cf94 --- /dev/null +++ b/arch/arm/boot/dts/imx23-xfi3.dts @@ -0,0 +1,179 @@ +/* + * Copyright (C) 2013-2016 Marek Vasut + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +/dts-v1/; +#include "imx23.dtsi" + +/ { + model = "Creative ZEN X-Fi3"; + compatible = "creative,x-fi3", "fsl,imx23"; + + memory { + reg = <0x40000000 0x04000000>; + }; + + apb@80000000 { + apbh@80000000 { + ssp0: ssp@80010000 { + compatible = "fsl,imx23-mmc"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_4bit_pins_a &mmc0_pins_fixup>; + bus-width = <4>; + vmmc-supply = <®_vddio_sd0>; + cd-inverted; + status = "okay"; + }; + + ssp1: ssp@80034000 { + compatible = "fsl,imx23-mmc"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_4bit_pins_a>; + bus-width = <4>; + non-removable; + status = "okay"; + }; + + pinctrl@80018000 { + pinctrl-names = "default"; + pinctrl-0 = <&hog_pins_a>; + + hog_pins_a: hog@0 { + reg = <0>; + fsl,pinmux-ids = < + MX23_PAD_GPMI_D07__GPIO_0_7 + >; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; + + key_pins_a: keys@0 { + reg = <0>; + fsl,pinmux-ids = < + MX23_PAD_ROTARYA__GPIO_2_7 + MX23_PAD_ROTARYB__GPIO_2_8 + >; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <1>; + }; + }; + }; + + apbx@80040000 { + i2c: i2c@80058000 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c_pins_a>; + status = "okay"; + }; + + pwm: pwm@80064000 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm2_pins_a>; + status = "okay"; + }; + + duart: serial@80070000 { + pinctrl-names = "default"; + pinctrl-0 = <&duart_pins_a>; + status = "okay"; + }; + + auart1: serial@8006e000 { + pinctrl-names = "default"; + pinctrl-0 = <&auart1_2pins_a>; + status = "okay"; + }; + + usbphy0: usbphy@8007c000 { + status = "okay"; + }; + + lradc@80050000 { + status = "okay"; + }; + }; + }; + + ahb@80080000 { + usb0: usb@80080000 { + dr_mode = "peripheral"; + status = "okay"; + }; + }; + + reg_vddio_sd0: regulator-vddio-sd0 { + compatible = "regulator-fixed"; + regulator-name = "vddio-sd0"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio0 7 0>; + }; + + backlight { + compatible = "pwm-backlight"; + pwms = <&pwm 2 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + }; + + gpio_keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&key_pins_a>; + + voldown { + label = "volume-down"; + linux,code = <114>; + gpios = <&gpio2 7 0>; + debounce-interval = <20>; + }; + + volup { + label = "volume-up"; + linux,code = <115>; + gpios = <&gpio2 8 0>; + debounce-interval = <20>; + }; + }; +}; -- cgit v0.10.2 From 542a8d98f16fd345af690a8a563c5b8218cb88a3 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 9 Jun 2016 21:43:13 +0200 Subject: ARM: dts: mxs: Add SanDisk Sansa Fuze+ support Add support for this small MP3 player based on STMP3780 (rev.3). Currently supported are both external microSD and internal SD-NAND bridge, PWM and USB gadget. Signed-off-by: Marek Vasut Cc: Fabio Estevam Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 1235934..5ead787 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -416,6 +416,7 @@ dtb-$(CONFIG_SOC_VF610) += \ dtb-$(CONFIG_ARCH_MXS) += \ imx23-evk.dtb \ imx23-olinuxino.dtb \ + imx23-sansa.dtb \ imx23-stmp378x_devb.dtb \ imx23-xfi3.dtb \ imx28-apf28.dtb \ diff --git a/arch/arm/boot/dts/imx23-sansa.dts b/arch/arm/boot/dts/imx23-sansa.dts new file mode 100644 index 0000000..4ec32f4 --- /dev/null +++ b/arch/arm/boot/dts/imx23-sansa.dts @@ -0,0 +1,207 @@ +/* + * Copyright (C) 2013-2016 Marek Vasut + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +/dts-v1/; +#include "imx23.dtsi" + +/ { + model = "SanDisk Sansa Fuze+"; + compatible = "sandisk,sansa_fuze_plus", "fsl,imx23"; + + memory { + reg = <0x40000000 0x04000000>; + }; + + apb@80000000 { + apbh@80000000 { + ssp0: ssp@80010000 { + compatible = "fsl,imx23-mmc"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_4bit_pins_a &mmc0_pins_fixup>; + bus-width = <4>; + vmmc-supply = <®_vddio_sd0>; + cd-inverted; + status = "okay"; + }; + + ssp1: ssp@80034000 { + compatible = "fsl,imx23-mmc"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_8bit_pins_a>; + bus-width = <8>; + vmmc-supply = <®_vddio_sd1>; + non-removable; + status = "okay"; + }; + + pinctrl@80018000 { + pinctrl-names = "default"; + pinctrl-0 = <&hog_pins_a>; + + hog_pins_a: hog@0 { + reg = <0>; + fsl,pinmux-ids = < + MX23_PAD_GPMI_D08__GPIO_0_8 + MX23_PAD_PWM3__GPIO_1_29 + MX23_PAD_AUART1_RTS__GPIO_0_27 + MX23_PAD_AUART1_CTS__GPIO_0_26 + MX23_PAD_I2C_SCL__I2C_SCL + MX23_PAD_I2C_SDA__I2C_SDA + MX23_PAD_LCD_DOTCK__GPIO_1_22 + MX23_PAD_LCD_HSYNC__GPIO_1_24 + MX23_PAD_PWM3__GPIO_1_29 + >; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; + }; + }; + + apbx@80040000 { + pwm: pwm@80064000 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm2_pins_a>; + status = "okay"; + }; + + duart: serial@80070000 { + pinctrl-names = "default"; + pinctrl-0 = <&duart_pins_a>; + status = "okay"; + }; + + usbphy0: usbphy@8007c000 { + status = "okay"; + }; + + lradc@80050000 { + status = "okay"; + }; + }; + }; + + ahb@80080000 { + usb0: usb@80080000 { + dr_mode = "peripheral"; + status = "okay"; + }; + }; + + reg_vddio_sd0: regulator-vddio-sd0 { + compatible = "regulator-fixed"; + regulator-name = "vddio-sd0"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio0 8 0>; + }; + + reg_vddio_sd1: regulator-vddio-sd1 { + compatible = "regulator-fixed"; + regulator-name = "vddio-sd1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 29 0>; + }; + + reg_vdd_touchpad: regulator-vdd-touchpad0 { + compatible = "regulator-fixed"; + regulator-name = "vdd-touchpad0"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio0 26 0>; + regulator-always-on; + enable-active-low; + }; + + reg_vdd_tuner: regulator-vdd-tuner0 { + compatible = "regulator-fixed"; + regulator-name = "vdd-tuner0"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio0 29 0>; + regulator-always-on; + enable-active-low; + }; + + backlight { + compatible = "pwm-backlight"; + pwms = <&pwm 2 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + }; + + i2c-0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "i2c-gpio"; + gpios = < + &gpio1 24 0 /* SDA */ + &gpio1 22 0 /* SCL */ + >; + i2c-gpio,delay-us = <2>; /* ~100 kHz */ + }; + + i2c-1 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "i2c-gpio"; + gpios = < + &gpio0 31 0 /* SDA */ + &gpio0 30 0 /* SCL */ + >; + i2c-gpio,delay-us = <2>; /* ~100 kHz */ + + touch: touch@20 { + compatible = "synaptics,synaptics_i2c"; + reg = <0x20>; + }; + + eeprom: eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + pagesize = <32>; + }; + }; + +}; -- cgit v0.10.2 From 4975fb10df8153cff3d6a09479521297e655983c Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Tue, 7 Jun 2016 19:59:10 +0200 Subject: ARM: dts: at91: usb_a9g20: use stdout-path Use stdout-path to specify the console and remove the console argument from the kernel command line. Acked-by: Nicolas Ferre Signed-off-by: Alexandre Belloni diff --git a/arch/arm/boot/dts/usb_a9g20_common.dtsi b/arch/arm/boot/dts/usb_a9g20_common.dtsi index 0b3b361..6156ee8 100644 --- a/arch/arm/boot/dts/usb_a9g20_common.dtsi +++ b/arch/arm/boot/dts/usb_a9g20_common.dtsi @@ -11,7 +11,8 @@ / { chosen { - bootargs = "mem=64M console=ttyS0,115200 root=/dev/mtdblock5 rw rootfstype=ubifs"; + bootargs = "mem=64M root=/dev/mtdblock5 rw rootfstype=ubifs"; + stdout-path = "serial0:115200n8"; }; memory { -- cgit v0.10.2 From ee3e7604095258ec63af3fc837e51065a953a2f7 Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Wed, 8 Jun 2016 01:31:19 +0200 Subject: ARM: dts: at91: ma5d4: properly define crystals frequencies The Denx MA5D4 dts doesn't properly define the slow_xtal and main_xtal frequencies, the PMC then has to fallback to using the RC oscillators whose precision is not really good. As both crystals are populated, define their frequencies, see p17 of http://www.denx-cs.de/sites/all/files/MA5D4.HWM_.002.pdf Also, remove the obsolete main_clock definition. Acked-by: Marek Vasut Signed-off-by: Alexandre Belloni diff --git a/arch/arm/boot/dts/at91-sama5d4_ma5d4.dtsi b/arch/arm/boot/dts/at91-sama5d4_ma5d4.dtsi index e7b2109..99d5713 100644 --- a/arch/arm/boot/dts/at91-sama5d4_ma5d4.dtsi +++ b/arch/arm/boot/dts/at91-sama5d4_ma5d4.dtsi @@ -20,8 +20,11 @@ }; clocks { - main_clock: main_clock { - compatible = "atmel,osc", "fixed-clock"; + slow_xtal { + clock-frequency = <32768>; + }; + + main_xtal { clock-frequency = <12000000>; }; -- cgit v0.10.2 From c6fde4f5aae1121122cfd7fd6d7d60826528b970 Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Wed, 8 Jun 2016 18:31:49 +0200 Subject: ARM: dts: at91: animeo_ip: remove leftovers clock definition The clocks group properties and the clock@0 node have been obsolete for two years, remove them. Acked-by: Nicolas Ferre Signed-off-by: Alexandre Belloni diff --git a/arch/arm/boot/dts/animeo_ip.dts b/arch/arm/boot/dts/animeo_ip.dts index 8bcbad3..9cc372b 100644 --- a/arch/arm/boot/dts/animeo_ip.dts +++ b/arch/arm/boot/dts/animeo_ip.dts @@ -32,15 +32,6 @@ }; clocks { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - main_clock: clock@0 { - compatible = "atmel,osc", "fixed-clock"; - clock-frequency = <18432000>; - }; - slow_xtal { clock-frequency = <32768>; }; -- cgit v0.10.2 From 0860fbdd020a7ce97cb6f5545c304eb49f00b888 Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Wed, 8 Jun 2016 18:31:49 +0200 Subject: ARM: dts: at91: at91-ariag25: remove leftovers clock definition The clocks group properties and the clock@0 node have been obsolete for two years, remove them. Cc: Sergio Tanzilli Cc: Douglas Gilbert Acked-by: Nicolas Ferre Signed-off-by: Alexandre Belloni diff --git a/arch/arm/boot/dts/at91-ariag25.dts b/arch/arm/boot/dts/at91-ariag25.dts index e9ced30..f16a9b8 100644 --- a/arch/arm/boot/dts/at91-ariag25.dts +++ b/arch/arm/boot/dts/at91-ariag25.dts @@ -34,15 +34,6 @@ }; clocks { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - main_clock: clock@0 { - compatible = "atmel,osc", "fixed-clock"; - clock-frequency = <12000000>; - }; - slow_xtal { clock-frequency = <32768>; }; -- cgit v0.10.2 From a1448b80e1f2c9d1d3dd86503e78841be9e19a78 Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Wed, 8 Jun 2016 18:31:50 +0200 Subject: ARM: dts: at91: at91-cosino: remove leftovers clock definition The clocks group properties and the clock@0 node have been obsolete for two years, remove them. Cc: Rodolfo Giometti Acked-by: Nicolas Ferre Signed-off-by: Alexandre Belloni diff --git a/arch/arm/boot/dts/at91-cosino.dtsi b/arch/arm/boot/dts/at91-cosino.dtsi index b6ea3f4..02d8ef4 100644 --- a/arch/arm/boot/dts/at91-cosino.dtsi +++ b/arch/arm/boot/dts/at91-cosino.dtsi @@ -26,15 +26,6 @@ }; clocks { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - main_clock: clock@0 { - compatible = "atmel,osc", "fixed-clock"; - clock-frequency = <12000000>; - }; - slow_xtal { clock-frequency = <32768>; }; -- cgit v0.10.2 From 0955e0d62f6eb8ca60dd0a440e90b448f804ab15 Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Wed, 8 Jun 2016 18:31:50 +0200 Subject: ARM: dts: at91: at91-foxg20: remove leftovers clock definition The clocks group properties and the clock@0 node have been obsolete for two years, remove them. Cc: Sergio Tanzilli Cc: Douglas Gilbert Acked-by: Nicolas Ferre Signed-off-by: Alexandre Belloni diff --git a/arch/arm/boot/dts/at91-foxg20.dts b/arch/arm/boot/dts/at91-foxg20.dts index 42a535d..07c9bac 100644 --- a/arch/arm/boot/dts/at91-foxg20.dts +++ b/arch/arm/boot/dts/at91-foxg20.dts @@ -23,15 +23,6 @@ }; clocks { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - main_clock: clock@0 { - compatible = "atmel,osc", "fixed-clock"; - clock-frequency = <18432000>; - }; - slow_xtal { clock-frequency = <32768>; }; -- cgit v0.10.2 From e7dc74f4a1801217fd9f43d95a8aa52e32e5c805 Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Wed, 8 Jun 2016 18:31:51 +0200 Subject: ARM: dts: at91: ge863-pro3: remove leftovers clock definition The clocks group properties and the clock@0 node have been obsolete for two years, remove them. Cc: Fabio Porcedda Acked-by: Nicolas Ferre Signed-off-by: Alexandre Belloni diff --git a/arch/arm/boot/dts/ge863-pro3.dtsi b/arch/arm/boot/dts/ge863-pro3.dtsi index 0d0e624..4aee5cc 100644 --- a/arch/arm/boot/dts/ge863-pro3.dtsi +++ b/arch/arm/boot/dts/ge863-pro3.dtsi @@ -11,15 +11,6 @@ / { clocks { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - main_clock: clock@0 { - compatible = "atmel,osc", "fixed-clock"; - clock-frequency = <6000000>; - }; - main_xtal { clock-frequency = <6000000>; }; -- cgit v0.10.2 From 05e41d60cb83dcc63bcf10c7c7d18b1e59a46bb0 Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Wed, 8 Jun 2016 18:31:51 +0200 Subject: ARM: dts: at91: mpa1600: remove leftovers clock definition The clocks group properties and the clock@0 node have been obsolete for two years, remove them. Cc: Joachim Eastwood Acked-by: Nicolas Ferre Signed-off-by: Alexandre Belloni diff --git a/arch/arm/boot/dts/mpa1600.dts b/arch/arm/boot/dts/mpa1600.dts index f0f5e10..30e66e5 100644 --- a/arch/arm/boot/dts/mpa1600.dts +++ b/arch/arm/boot/dts/mpa1600.dts @@ -17,15 +17,6 @@ }; clocks { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - main_clock: clock@0 { - compatible = "atmel,osc", "fixed-clock"; - clock-frequency = <18432000>; - }; - slow_xtal { clock-frequency = <32768>; }; -- cgit v0.10.2 From 8a9f16810d5815b5e656cd7a0570ec5acade9236 Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Wed, 8 Jun 2016 18:31:52 +0200 Subject: ARM: dts: at91: pm9g45: remove leftovers clock definition The clocks group properties and the clock@0 node have been obsolete for two years, remove them. Acked-by: Nicolas Ferre Signed-off-by: Alexandre Belloni diff --git a/arch/arm/boot/dts/pm9g45.dts b/arch/arm/boot/dts/pm9g45.dts index 66afcff..0abd7bf 100644 --- a/arch/arm/boot/dts/pm9g45.dts +++ b/arch/arm/boot/dts/pm9g45.dts @@ -21,15 +21,6 @@ }; clocks { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - main_clock: clock@0 { - compatible = "atmel,osc", "fixed-clock"; - clock-frequency = <12000000>; - }; - slow_xtal { clock-frequency = <32768>; }; -- cgit v0.10.2 From 64c0703e269d442f0406b34e64e23744151ea276 Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Wed, 8 Jun 2016 18:31:52 +0200 Subject: ARM: dts: at91: calao: remove leftovers clock definition The clocks group properties and the clock@0 node have been obsolete for two years, remove them. Acked-by: Nicolas Ferre Signed-off-by: Alexandre Belloni diff --git a/arch/arm/boot/dts/at91-qil_a9260.dts b/arch/arm/boot/dts/at91-qil_a9260.dts index 5309e19..5ad3d90 100644 --- a/arch/arm/boot/dts/at91-qil_a9260.dts +++ b/arch/arm/boot/dts/at91-qil_a9260.dts @@ -20,15 +20,6 @@ }; clocks { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - main_clock: clock@0 { - compatible = "atmel,osc", "fixed-clock"; - clock-frequency = <12000000>; - }; - slow_xtal { clock-frequency = <32768>; }; diff --git a/arch/arm/boot/dts/tny_a9260_common.dtsi b/arch/arm/boot/dts/tny_a9260_common.dtsi index ce7138c..f9dc463 100644 --- a/arch/arm/boot/dts/tny_a9260_common.dtsi +++ b/arch/arm/boot/dts/tny_a9260_common.dtsi @@ -16,15 +16,6 @@ }; clocks { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - main_clock: clock@0 { - compatible = "atmel,osc", "fixed-clock"; - clock-frequency = <12000000>; - }; - slow_xtal { clock-frequency = <32768>; }; diff --git a/arch/arm/boot/dts/tny_a9263.dts b/arch/arm/boot/dts/tny_a9263.dts index 3043296..2f39f85 100644 --- a/arch/arm/boot/dts/tny_a9263.dts +++ b/arch/arm/boot/dts/tny_a9263.dts @@ -21,15 +21,6 @@ }; clocks { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - main_clock: clock@0 { - compatible = "atmel,osc", "fixed-clock"; - clock-frequency = <12000000>; - }; - slow_xtal { clock-frequency = <32768>; }; diff --git a/arch/arm/boot/dts/usb_a9260_common.dtsi b/arch/arm/boot/dts/usb_a9260_common.dtsi index 12119b5..0f3a02b 100644 --- a/arch/arm/boot/dts/usb_a9260_common.dtsi +++ b/arch/arm/boot/dts/usb_a9260_common.dtsi @@ -8,15 +8,6 @@ / { clocks { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - main_clock: clock@0 { - compatible = "atmel,osc", "fixed-clock"; - clock-frequency = <12000000>; - }; - slow_xtal { clock-frequency = <32768>; }; diff --git a/arch/arm/boot/dts/usb_a9263.dts b/arch/arm/boot/dts/usb_a9263.dts index 8cc6edb..94c61507 100644 --- a/arch/arm/boot/dts/usb_a9263.dts +++ b/arch/arm/boot/dts/usb_a9263.dts @@ -21,15 +21,6 @@ }; clocks { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - main_clock: clock@0 { - compatible = "atmel,osc", "fixed-clock"; - clock-frequency = <12000000>; - }; - slow_xtal { clock-frequency = <32768>; }; -- cgit v0.10.2 From 707bbc45717c234c07e3870267ede61d15684346 Mon Sep 17 00:00:00 2001 From: Jon Mason Date: Tue, 7 Jun 2016 18:28:06 -0400 Subject: ARM: dts: NSP: Add XMC board support The BCM958525XMC board is a smaller form factor typically used as controller boards for switches. This smaller board has less devices pinned out, so only a few need be populated in the device tree. Signed-off-by: Jon Mason Signed-off-by: Florian Fainelli diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index cbe1595..2654eb6 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -98,6 +98,7 @@ dtb-$(CONFIG_ARCH_BCM_MOBILE) += \ bcm21664-garnet.dtb \ bcm23550-sparrow.dtb dtb-$(CONFIG_ARCH_BCM_NSP) += \ + bcm958525xmc.dtb \ bcm958625hr.dtb \ bcm958625k.dtb dtb-$(CONFIG_ARCH_BERLIN) += \ diff --git a/arch/arm/boot/dts/bcm958525xmc.dts b/arch/arm/boot/dts/bcm958525xmc.dts new file mode 100644 index 0000000..d257e83 --- /dev/null +++ b/arch/arm/boot/dts/bcm958525xmc.dts @@ -0,0 +1,109 @@ +/* + * BSD LICENSE + * + * Copyright(c) 2016 Broadcom. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Broadcom Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/dts-v1/; + +#include "bcm-nsp.dtsi" + +/ { + model = "NorthStar Plus XMC (BCM958525xmc)"; + compatible = "brcm,bcm58525", "brcm,nsp"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&nand { + nandcs@0 { + compatible = "brcm,nandcs"; + reg = <0>; + nand-on-flash-bbt; + + #address-cells = <1>; + #size-cells = <1>; + + nand-ecc-strength = <24>; + nand-ecc-step-size = <1024>; + + brcm,nand-oob-sector-size = <27>; + + partition@0 { + label = "nboot"; + reg = <0x00000000 0x00200000>; + read-only; + }; + partition@200000 { + label = "nenv"; + reg = <0x00200000 0x00400000>; + }; + partition@600000 { + label = "nsystem"; + reg = <0x00600000 0x00a00000>; + }; + partition@1000000 { + label = "nrootfs"; + reg = <0x01000000 0x03000000>; + }; + partition@4000000 { + label = "ncustfs"; + reg = <0x04000000 0x3c000000>; + }; + }; +}; + +/* XHCI, SATA, MMC, and Ethernet support needed to be complete */ + +&uart0 { + status = "okay"; +}; + +&pcie0 { + status = "okay"; +}; + +&pcie1 { + status = "okay"; +}; + +&pinctrl { + pinctrl-names = "default"; + pinctrl-0 = <&nand_sel>; + nand_sel: nand_sel { + function = "nand"; + groups = "nand_grp"; + }; +}; -- cgit v0.10.2 From 5fa1026a3e4dc8fc6c614674615f1e74235b359f Mon Sep 17 00:00:00 2001 From: Jon Mason Date: Tue, 7 Jun 2016 18:28:07 -0400 Subject: ARM: dts: NSP: Add PL330 support Add PL330 support to the the Broadcom Northstar Plus device tree. Signed-off-by: Jon Mason Signed-off-by: Florian Fainelli diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi index 1759e65..8d7b35a 100644 --- a/arch/arm/boot/dts/bcm-nsp.dtsi +++ b/arch/arm/boot/dts/bcm-nsp.dtsi @@ -192,6 +192,23 @@ status = "disabled"; }; + dma@20000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x20000 0x1000>; + interrupts = , + , + , + , + , + , + , + , + ; + clocks = <&iprocslow>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + }; + nand: nand@26000 { compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1"; reg = <0x026000 0x600>, -- cgit v0.10.2 From d44cbb1e9ca3488b5f144a3a71aa58f09b5422a1 Mon Sep 17 00:00:00 2001 From: Andy Gross Date: Thu, 9 Jun 2016 22:45:11 -0500 Subject: Revert "Revert "dts: msm8974: Add blsp2_bam dma node"" This puts back in place the blsp2_bam node. This can be safely added due to the addition of the special qcom,controlled-remotely flag that will be used on specific boards that require it. This reverts commit 338d51889851cb2ac900d2ec75c8185afcde8caf. diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index 6f16426..320564c 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -1,6 +1,6 @@ /dts-v1/; -#include +#include #include #include "skeleton.dtsi" @@ -518,6 +518,16 @@ interrupt-controller; #interrupt-cells = <4>; }; + + blsp2_dma: dma-controller@f9944000 { + compatible = "qcom,bam-v1.4.0"; + reg = <0xf9944000 0x19000>; + interrupts = ; + clocks = <&gcc GCC_BLSP2_AHB_CLK>; + clock-names = "bam_clk"; + #dma-cells = <1>; + qcom,ee = <0>; + }; }; smd { -- cgit v0.10.2 From 938b4d4ea13535d99e6b7bc145b78171bdea7da4 Mon Sep 17 00:00:00 2001 From: Andy Gross Date: Thu, 9 Jun 2016 22:45:27 -0500 Subject: Revert "Revert "dts: msm8974: Add dma channels for blsp2_i2c1 node"" This adds back the dma channels for the i2c1 node. This is safe now that the qcom,controlled-remotely changes are in place and will be used on the boards that require it. This reverts commit 10c0f0e92f019ab8d0c17da3696e35b0eef4ec16. diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index 320564c..e98b373 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -501,6 +501,8 @@ clock-names = "core", "iface"; #address-cells = <1>; #size-cells = <0>; + dmas = <&blsp2_dma 20>, <&blsp2_dma 21>; + dma-names = "tx", "rx"; }; spmi_bus: spmi@fc4cf000 { -- cgit v0.10.2 From aee99111819b1e71dc8d24f63cf742a1734650bf Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 31 May 2016 16:31:50 +0200 Subject: ARM: dts: imx28: Use generic uart-has-rtscts DT property As of commit 182cdcb8bb16e687 ("serial: mxs-auart: Use generic uart-has-rtscts DT property"), the Freescale MXS AUART driver recognizes the generic "uart-has-rtscts" DT property, deprecating the vendor-specific "fsl,uart-has-rtscts" DT property. Hence replace the latter by the former in all DTS files. Signed-off-by: Geert Uytterhoeven Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/imx28-apf28dev.dts b/arch/arm/boot/dts/imx28-apf28dev.dts index 1eaa131..c4fadbc 100644 --- a/arch/arm/boot/dts/imx28-apf28dev.dts +++ b/arch/arm/boot/dts/imx28-apf28dev.dts @@ -140,7 +140,7 @@ auart0: serial@8006a000 { pinctrl-names = "default"; pinctrl-0 = <&auart0_pins_a>; - fsl,uart-has-rtscts; + uart-has-rtscts; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx28-evk.dts b/arch/arm/boot/dts/imx28-evk.dts index e3ef94a..a5ba669 100644 --- a/arch/arm/boot/dts/imx28-evk.dts +++ b/arch/arm/boot/dts/imx28-evk.dts @@ -224,7 +224,7 @@ auart0: serial@8006a000 { pinctrl-names = "default"; pinctrl-0 = <&auart0_pins_a>; - fsl,uart-has-rtscts; + uart-has-rtscts; status = "okay"; }; -- cgit v0.10.2 From 2e7c416cbadf4795b5c1c66eabd3a96ffb199c51 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 31 May 2016 16:31:51 +0200 Subject: ARM: dts: imx: Use generic uart-has-rtscts DT property As of commit 1006ed7e1b258dac ("serial: imx: Use generic uart-has-rtscts DT property"), the Freescale IMX UART driver recognizes the generic "uart-has-rtscts" DT property, deprecating the vendor-specific "fsl,uart-has-rtscts" DT property. Hence replace the latter by the former in all DTS files. Signed-off-by: Geert Uytterhoeven Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/imx1-ads.dts b/arch/arm/boot/dts/imx1-ads.dts index af4eee5..f504986 100644 --- a/arch/arm/boot/dts/imx1-ads.dts +++ b/arch/arm/boot/dts/imx1-ads.dts @@ -66,14 +66,14 @@ &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; - fsl,uart-has-rtscts; + uart-has-rtscts; status = "okay"; }; &uart2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart2>; - fsl,uart-has-rtscts; + uart-has-rtscts; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx1-apf9328.dts b/arch/arm/boot/dts/imx1-apf9328.dts index 07d92fb..e8b4b52c 100644 --- a/arch/arm/boot/dts/imx1-apf9328.dts +++ b/arch/arm/boot/dts/imx1-apf9328.dts @@ -34,14 +34,14 @@ &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; - fsl,uart-has-rtscts; + uart-has-rtscts; status = "okay"; }; &uart2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart2>; - fsl,uart-has-rtscts; + uart-has-rtscts; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts b/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts index cda6907..9300711 100644 --- a/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts +++ b/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts @@ -161,14 +161,14 @@ &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; - fsl,uart-has-rtscts; + uart-has-rtscts; status = "okay"; }; &uart2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart2>; - fsl,uart-has-rtscts; + uart-has-rtscts; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx25-pdk.dts b/arch/arm/boot/dts/imx25-pdk.dts index 9351296..7029210 100644 --- a/arch/arm/boot/dts/imx25-pdk.dts +++ b/arch/arm/boot/dts/imx25-pdk.dts @@ -298,7 +298,7 @@ &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; - fsl,uart-has-rtscts; + uart-has-rtscts; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx27-eukrea-cpuimx27.dtsi b/arch/arm/boot/dts/imx27-eukrea-cpuimx27.dtsi index e224263..2cf896c 100644 --- a/arch/arm/boot/dts/imx27-eukrea-cpuimx27.dtsi +++ b/arch/arm/boot/dts/imx27-eukrea-cpuimx27.dtsi @@ -77,7 +77,7 @@ &uart4 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart4>; - fsl,uart-has-rtscts; + uart-has-rtscts; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx27-eukrea-mbimxsd27-baseboard.dts b/arch/arm/boot/dts/imx27-eukrea-mbimxsd27-baseboard.dts index 2ab65fc..27846ff 100644 --- a/arch/arm/boot/dts/imx27-eukrea-mbimxsd27-baseboard.dts +++ b/arch/arm/boot/dts/imx27-eukrea-mbimxsd27-baseboard.dts @@ -140,21 +140,21 @@ }; &uart1 { - fsl,uart-has-rtscts; + uart-has-rtscts; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; status = "okay"; }; &uart2 { - fsl,uart-has-rtscts; + uart-has-rtscts; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart2>; status = "okay"; }; &uart3 { - fsl,uart-has-rtscts; + uart-has-rtscts; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart3>; status = "okay"; diff --git a/arch/arm/boot/dts/imx27-pdk.dts b/arch/arm/boot/dts/imx27-pdk.dts index 49450db..d0ef496 100644 --- a/arch/arm/boot/dts/imx27-pdk.dts +++ b/arch/arm/boot/dts/imx27-pdk.dts @@ -106,7 +106,7 @@ }; &uart1 { - fsl,uart-has-rtscts; + uart-has-rtscts; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; status = "okay"; diff --git a/arch/arm/boot/dts/imx27-phytec-phycard-s-rdk.dts b/arch/arm/boot/dts/imx27-phytec-phycard-s-rdk.dts index 7c869fe..bfd4946 100644 --- a/arch/arm/boot/dts/imx27-phytec-phycard-s-rdk.dts +++ b/arch/arm/boot/dts/imx27-phytec-phycard-s-rdk.dts @@ -147,21 +147,21 @@ }; &uart1 { - fsl,uart-has-rtscts; + uart-has-rtscts; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; status = "okay"; }; &uart2 { - fsl,uart-has-rtscts; + uart-has-rtscts; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart2>; status = "okay"; }; &uart3 { - fsl,uart-has-rtscts; + uart-has-rtscts; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart3>; status = "okay"; diff --git a/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts b/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts index 538568b..cf09e72 100644 --- a/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts +++ b/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts @@ -283,14 +283,14 @@ }; &uart1 { - fsl,uart-has-rtscts; + uart-has-rtscts; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; status = "okay"; }; &uart2 { - fsl,uart-has-rtscts; + uart-has-rtscts; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart2>; status = "okay"; diff --git a/arch/arm/boot/dts/imx31-bug.dts b/arch/arm/boot/dts/imx31-bug.dts index 2424abf..ae6cebb 100644 --- a/arch/arm/boot/dts/imx31-bug.dts +++ b/arch/arm/boot/dts/imx31-bug.dts @@ -22,6 +22,6 @@ }; &uart5 { - fsl,uart-has-rtscts; + uart-has-rtscts; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx35-eukrea-mbimxsd35-baseboard.dts b/arch/arm/boot/dts/imx35-eukrea-mbimxsd35-baseboard.dts index 4727bbb..e935713 100644 --- a/arch/arm/boot/dts/imx35-eukrea-mbimxsd35-baseboard.dts +++ b/arch/arm/boot/dts/imx35-eukrea-mbimxsd35-baseboard.dts @@ -139,14 +139,14 @@ &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; - fsl,uart-has-rtscts; + uart-has-rtscts; status = "okay"; }; &uart2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart2>; - fsl,uart-has-rtscts; + uart-has-rtscts; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx35-pdk.dts b/arch/arm/boot/dts/imx35-pdk.dts index 8d71552..9bb628f 100644 --- a/arch/arm/boot/dts/imx35-pdk.dts +++ b/arch/arm/boot/dts/imx35-pdk.dts @@ -63,6 +63,6 @@ &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; - fsl,uart-has-rtscts; + uart-has-rtscts; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx51-babbage.dts b/arch/arm/boot/dts/imx51-babbage.dts index 018d24e..f097b4f 100644 --- a/arch/arm/boot/dts/imx51-babbage.dts +++ b/arch/arm/boot/dts/imx51-babbage.dts @@ -388,7 +388,7 @@ &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; - fsl,uart-has-rtscts; + uart-has-rtscts; status = "okay"; }; @@ -401,7 +401,7 @@ &uart3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart3>; - fsl,uart-has-rtscts; + uart-has-rtscts; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard.dts b/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard.dts index d270df3..7282128 100644 --- a/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard.dts +++ b/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard.dts @@ -261,14 +261,14 @@ &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; - fsl,uart-has-rtscts; + uart-has-rtscts; status = "okay"; }; &uart3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart3 &pinctrl_uart3_rtscts>; - fsl,uart-has-rtscts; + uart-has-rtscts; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx53-smd.dts b/arch/arm/boot/dts/imx53-smd.dts index 542ab9e..9f51900 100644 --- a/arch/arm/boot/dts/imx53-smd.dts +++ b/arch/arm/boot/dts/imx53-smd.dts @@ -56,7 +56,7 @@ &uart3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart3>; - fsl,uart-has-rtscts; + uart-has-rtscts; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx53-tqma53.dtsi b/arch/arm/boot/dts/imx53-tqma53.dtsi index e03373a..91a6a9f 100644 --- a/arch/arm/boot/dts/imx53-tqma53.dtsi +++ b/arch/arm/boot/dts/imx53-tqma53.dtsi @@ -218,7 +218,7 @@ &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; - fsl,uart-has-rtscts; + uart-has-rtscts; status = "disabled"; }; diff --git a/arch/arm/boot/dts/imx53-tx53.dtsi b/arch/arm/boot/dts/imx53-tx53.dtsi index bd3dfef..57e75f1 100644 --- a/arch/arm/boot/dts/imx53-tx53.dtsi +++ b/arch/arm/boot/dts/imx53-tx53.dtsi @@ -513,21 +513,21 @@ &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; - fsl,uart-has-rtscts; + uart-has-rtscts; status = "okay"; }; &uart2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart2>; - fsl,uart-has-rtscts; + uart-has-rtscts; status = "okay"; }; &uart3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart3>; - fsl,uart-has-rtscts; + uart-has-rtscts; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6q-arm2.dts b/arch/arm/boot/dts/imx6q-arm2.dts index d6515f7..77191d6 100644 --- a/arch/arm/boot/dts/imx6q-arm2.dts +++ b/arch/arm/boot/dts/imx6q-arm2.dts @@ -218,7 +218,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart2>; fsl,dte-mode; - fsl,uart-has-rtscts; + uart-has-rtscts; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6q-ba16.dtsi b/arch/arm/boot/dts/imx6q-ba16.dtsi index f7e17e2..f2adc60 100644 --- a/arch/arm/boot/dts/imx6q-ba16.dtsi +++ b/arch/arm/boot/dts/imx6q-ba16.dtsi @@ -351,7 +351,7 @@ &uart3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart3>; - fsl,uart-has-rtscts; + uart-has-rtscts; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6qdl-apalis.dtsi b/arch/arm/boot/dts/imx6qdl-apalis.dtsi index 922b1dd..315e033f 100644 --- a/arch/arm/boot/dts/imx6qdl-apalis.dtsi +++ b/arch/arm/boot/dts/imx6qdl-apalis.dtsi @@ -423,7 +423,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_dte &pinctrl_uart1_ctrl>; fsl,dte-mode; - fsl,uart-has-rtscts; + uart-has-rtscts; status = "disabled"; }; @@ -431,7 +431,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart2_dte>; fsl,dte-mode; - fsl,uart-has-rtscts; + uart-has-rtscts; status = "disabled"; }; diff --git a/arch/arm/boot/dts/imx6qdl-apf6dev.dtsi b/arch/arm/boot/dts/imx6qdl-apf6dev.dtsi index 865c9a2..edbce22 100644 --- a/arch/arm/boot/dts/imx6qdl-apf6dev.dtsi +++ b/arch/arm/boot/dts/imx6qdl-apf6dev.dtsi @@ -254,7 +254,7 @@ &uart3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart3 &pinctrl_gsm>; - fsl,uart-has-rtscts; + uart-has-rtscts; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6qdl-aristainetos.dtsi b/arch/arm/boot/dts/imx6qdl-aristainetos.dtsi index ecbc6eb..54f4f01 100644 --- a/arch/arm/boot/dts/imx6qdl-aristainetos.dtsi +++ b/arch/arm/boot/dts/imx6qdl-aristainetos.dtsi @@ -143,14 +143,14 @@ &uart4 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart4>; - fsl,uart-has-rtscts; + uart-has-rtscts; status = "okay"; }; &uart5 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart5>; - fsl,uart-has-rtscts; + uart-has-rtscts; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6qdl-aristainetos2.dtsi b/arch/arm/boot/dts/imx6qdl-aristainetos2.dtsi index 7d81100..7fff02c 100644 --- a/arch/arm/boot/dts/imx6qdl-aristainetos2.dtsi +++ b/arch/arm/boot/dts/imx6qdl-aristainetos2.dtsi @@ -351,7 +351,7 @@ &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; - fsl,uart-has-rtscts; + uart-has-rtscts; status = "okay"; }; @@ -364,7 +364,7 @@ &uart3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart3>; - fsl,uart-has-rtscts; + uart-has-rtscts; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6qdl-microsom.dtsi b/arch/arm/boot/dts/imx6qdl-microsom.dtsi index 86460e4..3d62401 100644 --- a/arch/arm/boot/dts/imx6qdl-microsom.dtsi +++ b/arch/arm/boot/dts/imx6qdl-microsom.dtsi @@ -143,7 +143,7 @@ &uart4 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_microsom_brcm_bt &pinctrl_microsom_uart4>; - fsl,uart-has-rtscts; + uart-has-rtscts; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi b/arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi index e456b5c..00f7202 100644 --- a/arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi +++ b/arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi @@ -591,7 +591,7 @@ &uart3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart3>; - fsl,uart-has-rtscts; + uart-has-rtscts; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6qdl-tx6.dtsi b/arch/arm/boot/dts/imx6qdl-tx6.dtsi index 39b85ae..ac9529f 100644 --- a/arch/arm/boot/dts/imx6qdl-tx6.dtsi +++ b/arch/arm/boot/dts/imx6qdl-tx6.dtsi @@ -689,21 +689,21 @@ &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_rtscts>; - fsl,uart-has-rtscts; + uart-has-rtscts; status = "okay"; }; &uart2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart2 &pinctrl_uart2_rtscts>; - fsl,uart-has-rtscts; + uart-has-rtscts; status = "okay"; }; &uart3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart3 &pinctrl_uart3_rtscts>; - fsl,uart-has-rtscts; + uart-has-rtscts; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6qdl-wandboard.dtsi b/arch/arm/boot/dts/imx6qdl-wandboard.dtsi index 8e7c40e..f262db3 100644 --- a/arch/arm/boot/dts/imx6qdl-wandboard.dtsi +++ b/arch/arm/boot/dts/imx6qdl-wandboard.dtsi @@ -233,7 +233,7 @@ &uart3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart3>; - fsl,uart-has-rtscts; + uart-has-rtscts; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6sl-warp.dts b/arch/arm/boot/dts/imx6sl-warp.dts index 058bcdc..72c7745 100644 --- a/arch/arm/boot/dts/imx6sl-warp.dts +++ b/arch/arm/boot/dts/imx6sl-warp.dts @@ -84,7 +84,7 @@ &uart5 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart5>; - fsl,uart-has-rtscts; + uart-has-rtscts; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6sx-nitrogen6sx.dts b/arch/arm/boot/dts/imx6sx-nitrogen6sx.dts index ba62348..9b817f3 100644 --- a/arch/arm/boot/dts/imx6sx-nitrogen6sx.dts +++ b/arch/arm/boot/dts/imx6sx-nitrogen6sx.dts @@ -326,7 +326,7 @@ &uart3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart3>; - fsl,uart-has-rtscts; + uart-has-rtscts; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6sx-sdb.dtsi b/arch/arm/boot/dts/imx6sx-sdb.dtsi index e5eafe4..fcbaccf 100644 --- a/arch/arm/boot/dts/imx6sx-sdb.dtsi +++ b/arch/arm/boot/dts/imx6sx-sdb.dtsi @@ -273,7 +273,7 @@ &uart5 { /* for bluetooth */ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart5>; - fsl,uart-has-rtscts; + uart-has-rtscts; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6ul-14x14-evk.dts b/arch/arm/boot/dts/imx6ul-14x14-evk.dts index 918c7c8..af1f4fe 100644 --- a/arch/arm/boot/dts/imx6ul-14x14-evk.dts +++ b/arch/arm/boot/dts/imx6ul-14x14-evk.dts @@ -172,7 +172,7 @@ &uart2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart2>; - fsl,uart-has-rtscts; + uart-has-rtscts; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6ul-pico-hobbit.dts b/arch/arm/boot/dts/imx6ul-pico-hobbit.dts index 8ce1fec..e5bff4b 100644 --- a/arch/arm/boot/dts/imx6ul-pico-hobbit.dts +++ b/arch/arm/boot/dts/imx6ul-pico-hobbit.dts @@ -286,7 +286,7 @@ &uart3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart3>; - fsl,uart-has-rtscts; + uart-has-rtscts; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6ul-tx6ul-mainboard.dts b/arch/arm/boot/dts/imx6ul-tx6ul-mainboard.dts index d25899b..7c5dd1b 100644 --- a/arch/arm/boot/dts/imx6ul-tx6ul-mainboard.dts +++ b/arch/arm/boot/dts/imx6ul-tx6ul-mainboard.dts @@ -146,12 +146,12 @@ &uart1 { pinctrl-0 = <&pinctrl_uart1>; - /delete-property/ fsl,uart-has-rtscts; + /delete-property/ uart-has-rtscts; }; &uart2 { pinctrl-0 = <&pinctrl_uart2>; - /delete-property/ fsl,uart-has-rtscts; + /delete-property/ uart-has-rtscts; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6ul-tx6ul.dtsi b/arch/arm/boot/dts/imx6ul-tx6ul.dtsi index 437e9aa..530e9ca 100644 --- a/arch/arm/boot/dts/imx6ul-tx6ul.dtsi +++ b/arch/arm/boot/dts/imx6ul-tx6ul.dtsi @@ -563,21 +563,21 @@ &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_rtscts>; - fsl,uart-has-rtscts; + uart-has-rtscts; status = "okay"; }; &uart2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart2 &pinctrl_uart2_rtscts>; - fsl,uart-has-rtscts; + uart-has-rtscts; status = "okay"; }; &uart5 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart5 &pinctrl_uart5_rtscts>; - fsl,uart-has-rtscts; + uart-has-rtscts; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx7d-nitrogen7.dts b/arch/arm/boot/dts/imx7d-nitrogen7.dts index 1ce9780..bef394e 100644 --- a/arch/arm/boot/dts/imx7d-nitrogen7.dts +++ b/arch/arm/boot/dts/imx7d-nitrogen7.dts @@ -392,7 +392,7 @@ pinctrl-0 = <&pinctrl_uart6>; assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>; assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; - fsl,uart-has-rtscts; + uart-has-rtscts; status = "okay"; }; -- cgit v0.10.2 From e5adcb7c8afdbea10129284205516039fbf5cd1d Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 30 May 2016 14:41:37 -0300 Subject: ARM: dts: imx6ul-14x14-evk: Add LCD and backlight support Add support for the LCD8000-43T display and for the backlight controlled via PWM1. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/imx6ul-14x14-evk.dts b/arch/arm/boot/dts/imx6ul-14x14-evk.dts index af1f4fe..bfe9fb4 100644 --- a/arch/arm/boot/dts/imx6ul-14x14-evk.dts +++ b/arch/arm/boot/dts/imx6ul-14x14-evk.dts @@ -22,6 +22,14 @@ reg = <0x80000000 0x20000000>; }; + backlight { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + status = "okay"; + }; + regulators { compatible = "simple-bus"; #address-cells = <1>; @@ -125,6 +133,46 @@ }; }; + +&lcdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdif_dat + &pinctrl_lcdif_ctrl>; + display = <&display0>; + status = "okay"; + + display0: display { + bits-per-pixel = <16>; + bus-width = <24>; + + display-timings { + native-mode = <&timing0>; + + timing0: timing0 { + clock-frequency = <9200000>; + hactive = <480>; + vactive = <272>; + hfront-porch = <8>; + hback-porch = <4>; + hsync-len = <41>; + vback-porch = <2>; + vfront-porch = <4>; + vsync-len = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + }; + }; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + &qspi { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_qspi>; -- cgit v0.10.2 From f255f89f9355ee9a5cfaafbc9afb24b16d1596e2 Mon Sep 17 00:00:00 2001 From: Juergen Borleis Date: Tue, 31 May 2016 16:49:37 +0200 Subject: ARM: dts: imx6: fix IPU1 DI1 node name This node describes the DI1 port of IPU, fix the node name to reflect this. There's currently no user of this node in mainline, so this change should not break any supported platforms. Signed-off-by: Juergen Borleis Signed-off-by: Lucas Stach Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/imx6q-apalis-ixora.dts b/arch/arm/boot/dts/imx6q-apalis-ixora.dts index 8e67ca2..207b85b 100644 --- a/arch/arm/boot/dts/imx6q-apalis-ixora.dts +++ b/arch/arm/boot/dts/imx6q-apalis-ixora.dts @@ -93,7 +93,7 @@ reg = <0>; lcd_display_in: endpoint { - remote-endpoint = <&ipu1_di0_disp1>; + remote-endpoint = <&ipu1_di1_disp1>; }; }; @@ -210,7 +210,7 @@ }; }; -&ipu1_di0_disp1 { +&ipu1_di1_disp1 { remote-endpoint = <&lcd_display_in>; }; diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi index 16541a7..b20096f 100644 --- a/arch/arm/boot/dts/imx6qdl.dtsi +++ b/arch/arm/boot/dts/imx6qdl.dtsi @@ -1256,7 +1256,7 @@ #size-cells = <0>; reg = <3>; - ipu1_di0_disp1: disp1-endpoint { + ipu1_di1_disp1: disp1-endpoint { }; ipu1_di1_hdmi: hdmi-endpoint { -- cgit v0.10.2 From a28eeb43ee57e0524c59e64760ed28088dd159cb Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Fri, 3 Jun 2016 18:31:20 +0200 Subject: ARM: dts: imx6: tag boards that have the HW workaround for ERR006687 Add the DT property to all boards that have the hardware workaround for erratum ERR006687 present. This allows the CPUidle driver to use the deep idle states, even if the FEC is active. Signed-off-by: Lucas Stach Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/imx6dl-riotboard.dts b/arch/arm/boot/dts/imx6dl-riotboard.dts index bfbed52..2becd7c 100644 --- a/arch/arm/boot/dts/imx6dl-riotboard.dts +++ b/arch/arm/boot/dts/imx6dl-riotboard.dts @@ -97,6 +97,7 @@ phy-reset-gpios = <&gpio3 31 0>; interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; + fsl,err006687-workaround-present; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6q-arm2.dts b/arch/arm/boot/dts/imx6q-arm2.dts index 77191d6..d8acf15 100644 --- a/arch/arm/boot/dts/imx6q-arm2.dts +++ b/arch/arm/boot/dts/imx6q-arm2.dts @@ -185,6 +185,7 @@ phy-mode = "rgmii"; interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; + fsl,err006687-workaround-present; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi b/arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi index 00f7202..cfd50ea 100644 --- a/arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi +++ b/arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi @@ -250,6 +250,7 @@ txd3-skew-ps = <0>; interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; + fsl,err006687-workaround-present; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi b/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi index 657da6b..9677bf3 100644 --- a/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi +++ b/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi @@ -385,6 +385,7 @@ txd3-skew-ps = <0>; interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; + fsl,err006687-workaround-present; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi b/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi index 73915db..97d9c33 100644 --- a/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi +++ b/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi @@ -287,6 +287,7 @@ txd3-skew-ps = <0>; interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; + fsl,err006687-workaround-present; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi index d354d40..6aa193f 100644 --- a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi @@ -155,6 +155,7 @@ phy-mode = "rgmii"; interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; + fsl,err006687-workaround-present; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi b/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi index c47fe6c..f65fdfc 100644 --- a/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi @@ -273,6 +273,7 @@ txd3-skew-ps = <0>; interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; + fsl,err006687-workaround-present; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6qdl-wandboard.dtsi b/arch/arm/boot/dts/imx6qdl-wandboard.dtsi index f262db3..3ffe00c 100644 --- a/arch/arm/boot/dts/imx6qdl-wandboard.dtsi +++ b/arch/arm/boot/dts/imx6qdl-wandboard.dtsi @@ -211,6 +211,7 @@ phy-reset-gpios = <&gpio3 29 0>; interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; + fsl,err006687-workaround-present; status = "okay"; }; -- cgit v0.10.2 From 31836adea27bc27f0f33ebfda964996d0e57f811 Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Fri, 3 Jun 2016 18:40:29 +0200 Subject: ARM: dts: imx6: add support for Auvidea H100 board The Auvidea H100 is a baseboard for the SolidRun MicroSOM. Its primary feature is a Toshiba TC358743 HDMI to CSI decoder, allowing the board to work as HDMI passthrough and framegrabber. Signed-off-by: Lucas Stach Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 5ead787..514b980 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -356,6 +356,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6q-gw54xx.dtb \ imx6q-gw551x.dtb \ imx6q-gw552x.dtb \ + imx6q-h100.dtb \ imx6q-hummingboard.dtb \ imx6q-icore-rqs.dtb \ imx6q-marsboard.dtb \ diff --git a/arch/arm/boot/dts/imx6q-h100.dts b/arch/arm/boot/dts/imx6q-h100.dts new file mode 100644 index 0000000..65e66f9 --- /dev/null +++ b/arch/arm/boot/dts/imx6q-h100.dts @@ -0,0 +1,395 @@ +/* + * Copyright (C) 2015 Lucas Stach + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "imx6q.dtsi" +#include "imx6qdl-microsom.dtsi" +#include "imx6qdl-microsom-ar8035.dtsi" + +/ { + model = "Auvidea H100"; + compatible = "auvidea,h100", "fsl,imx6q"; + + aliases { + rtc0 = &rtc; + rtc1 = &snvs_rtc; + }; + + chosen { + stdout-path = &uart2; + }; + + hdmi_osc: hdmi-osc { + compatible = "fixed-clock"; + clock-output-names = "hdmi-osc"; + clock-frequency = <27000000>; + #clock-cells = <0>; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_h100_leds>; + + led0: power { + label = "power"; + gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; + default-state = "on"; + }; + + led1: stream { + label = "stream"; + gpios = <&gpio2 29 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led2: rec { + label = "rec"; + gpios = <&gpio2 28 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_hdmi: regulator-hdmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_h100_reg_hdmi>; + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio2 20 GPIO_ACTIVE_HIGH>; + regulator-name = "V_HDMI"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + reg_nvcc_sd2: regulator-nvcc-sd2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_h100_reg_nvcc_sd2>; + compatible = "regulator-gpio"; + regulator-name = "NVCC_SD2"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-type = "voltage"; + regulator-boot-on; + regulator-always-on; + gpios = <&gpio4 9 GPIO_ACTIVE_HIGH>; + states = <1800000 0x1 + 3300000 0x0>; + }; + + reg_usbh1_vbus: regulator-usb-h1-vbus { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_h100_usbh1_vbus>; + regulator-name = "USB_H1_VBUS"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_usbotg_vbus: regulator-usb-otg-vbus { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_h100_usbotg_vbus>; + regulator-name = "USB_OTG_VBUS"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + sound-sgtl5000 { + compatible = "fsl,imx-audio-sgtl5000"; + model = "H100 on-board codec"; + audio-codec = <&sgtl5000>; + audio-routing = + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "Headphone Jack", "HP_OUT"; + mux-ext-port = <5>; + mux-int-port = <1>; + ssi-controller = <&ssi1>; + }; +}; + +&audmux { + status = "okay"; +}; + +&hdmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_h100_hdmi>; + ddc-i2c-bus = <&i2c2>; + status = "okay"; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_h100_i2c1>; + status = "okay"; + + eeprom: 24c02@51 { + compatible = "microchip,24c02", "at24"; + reg = <0x51>; + }; + + rtc: pcf8523@68 { + compatible = "nxp,pcf8523"; + reg = <0x68>; + }; + + sgtl5000: sgtl5000@0a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_h100_sgtl5000>; + clocks = <&clks IMX6QDL_CLK_CKO>; + VDDA-supply = <®_3p3v>; + VDDIO-supply = <®_3p3v>; + }; + + tc358743: tc358743@0f { + compatible = "toshiba,tc358743"; + reg = <0x0f>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_h100_tc358743>; + clocks = <&hdmi_osc>; + clock-names = "refclk"; + reset-gpios = <&gpio6 15 GPIO_ACTIVE_LOW>; + /* IRQ has a wrong pull resistor which renders it useless */ + + port@0 { + tc358743_out: endpoint { + remote-endpoint = <&mipi_csi2_in>; + data-lanes = <1 2 3 4>; + clock-lanes = <0>; + clock-noncontinuous; + link-frequencies = /bits/ 64 <297000000>; + }; + }; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_h100_i2c2>; + status = "okay"; +}; + +&iomuxc { + h100 { + pinctrl_h100_hdmi: h100-hdmi { + fsl,pins = < + MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0 + >; + }; + + pinctrl_h100_i2c1: h100-i2c1 { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + >; + }; + + pinctrl_h100_i2c2: h100-i2c2 { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_h100_leds: pinctrl-h100-leds { + fsl,pins = < + MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x1b0b0 + MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x1b0b0 + MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x1b0b0 + >; + }; + + pinctrl_h100_reg_hdmi: h100-reg-hdmi { + fsl,pins = < + MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x1b0b0 + >; + }; + + pinctrl_h100_reg_nvcc_sd2: h100-reg-nvcc-sd2 { + fsl,pins = < + MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x1b0b0 + >; + }; + + pinctrl_h100_sgtl5000: h100-sgtl5000 { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0 + MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x130b0 + MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x110b0 + MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x130b0 + MX6QDL_PAD_GPIO_5__CCM_CLKO1 0x130b0 + >; + }; + + pinctrl_h100_tc358743: h100-tc358743 { + fsl,pins = < + MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x1b0b0 + >; + }; + + pinctrl_h100_uart2: h100-uart2 { + fsl,pins = < + MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 + MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 + >; + }; + + pinctrl_h100_usbh1_vbus: hummingboard-usbh1-vbus { + fsl,pins = < + MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 + >; + }; + + pinctrl_h100_usbotg_id: hummingboard-usbotg-id { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x13059 + >; + }; + + pinctrl_h100_usbotg_vbus: hummingboard-usbotg-vbus { + fsl,pins = < + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 + >; + }; + + pinctrl_h100_usdhc2: h100-usdhc2 { + fsl,pins = < + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1f071 + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x13059 + >; + }; + + pinctrl_h100_usdhc2_100mhz: h100-usdhc2-100mhz { + fsl,pins = < + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1f071 + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170b9 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100b9 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170b9 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170b9 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170b9 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170b9 + >; + }; + + pinctrl_h100_usdhc2_200mhz: h100-usdhc2-200mhz { + fsl,pins = < + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1f071 + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170f9 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100f9 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170f9 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170f9 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170f9 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170f9 + >; + }; + }; +}; + +&mipi_csi { + status = "okay"; + + port@0 { + mipi_csi2_in: endpoint { + remote-endpoint = <&tc358743_out>; + data-lanes = <1 2 3 4>; + clock-lanes = <0>; + clock-noncontinuous; + link-frequencies = /bits/ 64 <297000000>; + }; + }; +}; + +&ssi1 { + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_h100_uart2>; + status = "okay"; +}; + +&usbh1 { + disable-over-current; + vbus-supply = <®_usbh1_vbus>; + status = "okay"; +}; + +&usbotg { + disable-over-current; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_h100_usbotg_id>; + vbus-supply = <®_usbotg_vbus>; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_h100_usdhc2>; + pinctrl-1 = <&pinctrl_h100_usdhc2_100mhz>; + pinctrl-2 = <&pinctrl_h100_usdhc2_200mhz>; + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_nvcc_sd2>; + cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; + status = "okay"; +}; -- cgit v0.10.2 From e57609aa5318cd7cbe011bf0061c4ef79dc41bd4 Mon Sep 17 00:00:00 2001 From: Stefan Wahren Date: Sun, 5 Jun 2016 13:49:27 +0000 Subject: ARM: dts: mxs: add missing reg properties for GPIO banks This patch adds the missing reg properties for the MXS GPIO banks in order to fix the dtc warnings. Signed-off-by: Stefan Wahren Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/imx23.dtsi b/arch/arm/boot/dts/imx23.dtsi index 0c9a357..440ee9a 100644 --- a/arch/arm/boot/dts/imx23.dtsi +++ b/arch/arm/boot/dts/imx23.dtsi @@ -111,6 +111,7 @@ gpio0: gpio@0 { compatible = "fsl,imx23-gpio", "fsl,mxs-gpio"; + reg = <0>; interrupts = <16>; gpio-controller; #gpio-cells = <2>; @@ -120,6 +121,7 @@ gpio1: gpio@1 { compatible = "fsl,imx23-gpio", "fsl,mxs-gpio"; + reg = <1>; interrupts = <17>; gpio-controller; #gpio-cells = <2>; @@ -129,6 +131,7 @@ gpio2: gpio@2 { compatible = "fsl,imx23-gpio", "fsl,mxs-gpio"; + reg = <2>; interrupts = <18>; gpio-controller; #gpio-cells = <2>; diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi index 74aa151..0ad893b 100644 --- a/arch/arm/boot/dts/imx28.dtsi +++ b/arch/arm/boot/dts/imx28.dtsi @@ -165,6 +165,7 @@ gpio0: gpio@0 { compatible = "fsl,imx28-gpio", "fsl,mxs-gpio"; + reg = <0>; interrupts = <127>; gpio-controller; #gpio-cells = <2>; @@ -174,6 +175,7 @@ gpio1: gpio@1 { compatible = "fsl,imx28-gpio", "fsl,mxs-gpio"; + reg = <1>; interrupts = <126>; gpio-controller; #gpio-cells = <2>; @@ -183,6 +185,7 @@ gpio2: gpio@2 { compatible = "fsl,imx28-gpio", "fsl,mxs-gpio"; + reg = <2>; interrupts = <125>; gpio-controller; #gpio-cells = <2>; @@ -192,6 +195,7 @@ gpio3: gpio@3 { compatible = "fsl,imx28-gpio", "fsl,mxs-gpio"; + reg = <3>; interrupts = <124>; gpio-controller; #gpio-cells = <2>; @@ -201,6 +205,7 @@ gpio4: gpio@4 { compatible = "fsl,imx28-gpio", "fsl,mxs-gpio"; + reg = <4>; interrupts = <123>; gpio-controller; #gpio-cells = <2>; -- cgit v0.10.2 From 7cae24dfe9d5cc2360025425a7efcb03fe6e98d8 Mon Sep 17 00:00:00 2001 From: Stefan Wahren Date: Sun, 5 Jun 2016 13:51:06 +0000 Subject: ARM: dts: imx28-eukrea-mbmx28lc: add missing reg properties This patch adds the missing reg properties for the regulator nodes in order to fix the dtc warnings. Signed-off-by: Stefan Wahren Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/imx28-eukrea-mbmx28lc.dtsi b/arch/arm/boot/dts/imx28-eukrea-mbmx28lc.dtsi index 8859474..581e85f 100644 --- a/arch/arm/boot/dts/imx28-eukrea-mbmx28lc.dtsi +++ b/arch/arm/boot/dts/imx28-eukrea-mbmx28lc.dtsi @@ -84,6 +84,7 @@ reg_3p3v: regulator@0 { compatible = "regulator-fixed"; + reg = <0>; regulator-name = "3P3V"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; @@ -92,6 +93,7 @@ reg_lcd_3v3: regulator@1 { compatible = "regulator-fixed"; + reg = <1>; pinctrl-names = "default"; pinctrl-0 = <®_lcd_3v3_pins_mbmx28lc>; regulator-name = "lcd-3v3"; @@ -103,6 +105,7 @@ reg_usb0_vbus: regulator@2 { compatible = "regulator-fixed"; + reg = <2>; pinctrl-names = "default"; pinctrl-0 = <®_usb0_vbus_pins_mbmx28lc>; regulator-name = "usb0_vbus"; @@ -114,6 +117,7 @@ reg_usb1_vbus: regulator@3 { compatible = "regulator-fixed"; + reg = <3>; pinctrl-names = "default"; pinctrl-0 = <®_usb1_vbus_pins_mbmx28lc>; regulator-name = "usb1_vbus"; -- cgit v0.10.2 From 88ab101cd2876a21f691c263f460ffcb18e97e9c Mon Sep 17 00:00:00 2001 From: Stefan Wahren Date: Sun, 5 Jun 2016 13:51:55 +0000 Subject: ARM: dts: imx28-cfa10049: fix dtc warning This fixes the following dtc warning by removing the unnecessary unit: Warning (unit_address_vs_reg): Node /onewire@0 has a unit name, but no reg property Signed-off-by: Stefan Wahren Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/imx28-cfa10049.dts b/arch/arm/boot/dts/imx28-cfa10049.dts index ef944b6..a9c347e 100644 --- a/arch/arm/boot/dts/imx28-cfa10049.dts +++ b/arch/arm/boot/dts/imx28-cfa10049.dts @@ -426,7 +426,7 @@ }; - onewire@0 { + onewire { compatible = "w1-gpio"; pinctrl-names = "default"; pinctrl-0 = <&w1_gpio_pins>; -- cgit v0.10.2 From 17b35f2872915e3cbb041902aeb88a42c9278eea Mon Sep 17 00:00:00 2001 From: Stefan Wahren Date: Sun, 5 Jun 2016 13:52:27 +0000 Subject: ARM: dts: imx28-tx28: fix dtc warning MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This fixes the following dtc warning by removing the unnecessary unit: Warning (unit_address_vs_reg): Node /matrix-keypad@0 has a unit name, but no reg property Signed-off-by: Stefan Wahren Acked-By: Lothar Waßmann Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/imx28-tx28.dts b/arch/arm/boot/dts/imx28-tx28.dts index fd20e99..0ebbc83 100644 --- a/arch/arm/boot/dts/imx28-tx28.dts +++ b/arch/arm/boot/dts/imx28-tx28.dts @@ -173,7 +173,7 @@ default-brightness-level = <50>; }; - matrix_keypad: matrix-keypad@0 { + matrix_keypad: matrix-keypad { compatible = "gpio-matrix-keypad"; col-gpios = < &gpio5 0 GPIO_ACTIVE_HIGH -- cgit v0.10.2 From 0c3bc8c9430a3e821026dd5c5165ac57e69a082e Mon Sep 17 00:00:00 2001 From: Christopher Spinrath Date: Tue, 7 Jun 2016 19:14:15 +0200 Subject: ARM: dts: imx6q-cm-fx6: remove iomuxc container node The imx6q-cm-fx6 iomuxc container node is not required. Remove it. Signed-off-by: Christopher Spinrath Acked-by: Igor Grinberg Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/imx6q-cm-fx6.dts b/arch/arm/boot/dts/imx6q-cm-fx6.dts index 99b46f8..21c513f 100644 --- a/arch/arm/boot/dts/imx6q-cm-fx6.dts +++ b/arch/arm/boot/dts/imx6q-cm-fx6.dts @@ -47,56 +47,54 @@ }; &iomuxc { - imx6q-cm-fx6 { - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 - >; - }; + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 + >; + }; - pinctrl_gpmi_nand: gpminandgrp { - fsl,pins = < - MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 - MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 - MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 - MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 - MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 - MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 - MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 - MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 - MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 - MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 - MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 - MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 - MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 - MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 - MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 - MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 - MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1 - >; - }; + pinctrl_gpmi_nand: gpminandgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 + MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 + MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 + MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 + MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 + MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 + MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 + MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 + MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 + MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 + MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 + MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 + MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 + MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 + MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 + MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 + MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1 + >; + }; - pinctrl_uart4: uart4grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 - >; - }; + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 + >; }; }; -- cgit v0.10.2 From 669c940a46d00e80a1605496724ea50254779290 Mon Sep 17 00:00:00 2001 From: Christopher Spinrath Date: Tue, 7 Jun 2016 19:14:16 +0200 Subject: ARM: dts: imx6q: extend support for the cm-fx6 The cm-fx6 module has an on-board spi-flash chip for its firmware, an eeprom (containing e.g. the mac address of the on-board Ethernet), a sata port, a pcie controller, an USB hub, and an USB otg port. Enable support for them. In addition, enable syscon poweroff support. Signed-off-by: Christopher Spinrath Reviewed-by: Fabio Estevam Acked-by: Igor Grinberg Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/imx6q-cm-fx6.dts b/arch/arm/boot/dts/imx6q-cm-fx6.dts index 21c513f..1ec3186 100644 --- a/arch/arm/boot/dts/imx6q-cm-fx6.dts +++ b/arch/arm/boot/dts/imx6q-cm-fx6.dts @@ -12,6 +12,7 @@ */ /dts-v1/; +#include #include "imx6q.dtsi" / { @@ -31,6 +32,49 @@ linux,default-trigger = "heartbeat"; }; }; + + reg_pcie_power_on_gpio: regulator-pcie-power-on-gpio { + compatible = "regulator-fixed"; + regulator-name = "regulator-pcie-power-on-gpio"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 24 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb_h1_vbus: usb_h1_vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_h1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio7 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb_otg_vbus: usb_otg_vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&ecspi1 { + fsl,spi-num-chipselects = <2>; + cs-gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>, <&gpio3 19 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + status = "okay"; + + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,m25p", "jedec,spi-nor"; + spi-max-frequency = <20000000>; + reg = <0>; + }; }; &fec { @@ -46,7 +90,30 @@ status = "okay"; }; +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + clock-frequency = <100000>; + + eeprom@50 { + compatible = "at24,24c02"; + reg = <0x50>; + pagesize = <16>; + }; +}; + &iomuxc { + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x100b1 + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x100b1 + >; + }; + pinctrl_enet: enetgrp { fsl,pins = < MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 @@ -90,12 +157,55 @@ >; }; + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_pcie: pciegrp { + fsl,pins = < + MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1 + MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x1b0b1 + >; + }; + pinctrl_uart4: uart4grp { fsl,pins = < MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 >; }; + + pinctrl_usbh1: usbh1grp { + fsl,pins = < + MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x1b0b1 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x130b0 + >; + }; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + reset-gpio = <&gpio1 26 GPIO_ACTIVE_LOW>; + vdd-supply = <®_pcie_power_on_gpio>; + status = "okay"; +}; + +&sata { + status = "okay"; +}; + +&snvs_poweroff { + status = "okay"; }; &uart4 { @@ -103,3 +213,18 @@ pinctrl-0 = <&pinctrl_uart4>; status = "okay"; }; + +&usbh1 { + vbus-supply = <®_usb_h1_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1>; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + dr_mode = "otg"; + status = "okay"; +}; -- cgit v0.10.2 From 1ad257d1c8065385554808d2f419a0d6e67559ec Mon Sep 17 00:00:00 2001 From: Christopher Spinrath Date: Tue, 7 Jun 2016 19:14:17 +0200 Subject: ARM: dts: imx6q: add support for the Utilite Pro The CompuLab Utilite Pro is a miniature fanless desktop pc based on the i.MX6 Quad powered cm-fx6 module. It features two serial ports, USB OTG, 4x USB, analog audio and S/PDIF, 2x Gb Ethernet, HDMI and DVI ports, an on-board 32GB SSD, a mmc slot, and on-board wifi/bt. Add initial support for it including USB, Ethernet (both ports), sata and HDMI support. Signed-off-by: Christopher Spinrath Acked-by: Igor Grinberg Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 514b980..146850b 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -378,6 +378,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6q-tx6q-1110.dtb \ imx6q-tx6q-11x0-mb7.dtb \ imx6q-udoo.dtb \ + imx6q-utilite-pro.dtb \ imx6q-wandboard.dtb \ imx6q-wandboard-revb1.dtb \ imx6qp-nitrogen6_max.dtb \ diff --git a/arch/arm/boot/dts/imx6q-utilite-pro.dts b/arch/arm/boot/dts/imx6q-utilite-pro.dts new file mode 100644 index 0000000..7219745 --- /dev/null +++ b/arch/arm/boot/dts/imx6q-utilite-pro.dts @@ -0,0 +1,153 @@ +/* + * Copyright 2013 CompuLab Ltd. + * Copyright 2016 Christopher Spinrath + * + * Based on the devicetree distributed with the vendor kernel for the + * Utilite Pro: + * Copyright 2013 CompuLab Ltd. + * Author: Valentin Raevsky + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include +#include "imx6q-cm-fx6.dts" + +/ { + model = "CompuLab Utilite Pro"; + compatible = "compulab,utilite-pro", "compulab,cm-fx6", "fsl,imx6q"; + + aliases { + ethernet1 = ð1; + rtc0 = &em3027; + rtc1 = &snvs_rtc; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + + power { + label = "Power Button"; + gpios = <&gpio1 29 GPIO_ACTIVE_LOW>; + linux,code = ; + gpio-key,wakeup; + }; + }; +}; + +&hdmi { + ddc-i2c-bus = <&i2c2>; + status = "okay"; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + eeprom@50 { + compatible = "at24,24c02"; + reg = <0x50>; + pagesize = <16>; + }; + + em3027: rtc@56 { + compatible = "emmicro,em3027"; + reg = <0x56>; + }; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + +&iomuxc { + pinctrl_gpio_keys: gpio_keysgrp { + fsl,pins = < + MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_GPIO_7__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_GPIO_8__UART2_RX_DATA 0x1b0b1 + MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b1 + MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b1 + >; + }; +}; + +&pcie { + pcie@0,0 { + reg = <0x000000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + + /* non-removable i211 ethernet card */ + eth1: intel,i211@pcie0,0 { + reg = <0x010000 0 0 0 0>; + }; + }; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + uart-has-rtscts; + status = "okay"; +}; -- cgit v0.10.2 From a98704b46bc159a729edadc20eff78fda639fb3f Mon Sep 17 00:00:00 2001 From: Christopher Spinrath Date: Tue, 7 Jun 2016 19:14:18 +0200 Subject: ARM: dts: imx6q-cm-fx6: Relicense under GPLv2/X11 GPLv2-only devicetrees make reuse difficult for software components licensed under a different license. In particular, the Utilite Pro devicetree file (which includes imx6q-cm-fx6.dts) is already dual licensed under GPLv2/X11. Hence, relicense imx6q-cm-fx6.dts under GPLv2/X11 dual license. Signed-off-by: Christopher Spinrath Acked-by: Igor Grinberg Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/imx6q-cm-fx6.dts b/arch/arm/boot/dts/imx6q-cm-fx6.dts index 1ec3186..6d8d5e9 100644 --- a/arch/arm/boot/dts/imx6q-cm-fx6.dts +++ b/arch/arm/boot/dts/imx6q-cm-fx6.dts @@ -3,12 +3,42 @@ * * Author: Valentin Raevsky * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; -- cgit v0.10.2 From f1472f82cc4d2dd747dc3e5e9c7e0ae3d3911922 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Sun, 5 Jun 2016 23:00:47 -0300 Subject: ARM: dts: imx6qdl-sabresd: Pass the correct PCI reset polarity The PCI reset GPIO is active low, so represent it with the GPIO_ACTIVE_LOW flag. Even though the imx6 PCI driver will not take the polarity into account in this case, it is better to provide a correct description in device-tree. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi index 5248e7b..bea707f 100644 --- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi @@ -533,7 +533,7 @@ &pcie { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pcie>; - reset-gpio = <&gpio7 12 0>; + reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>; status = "okay"; }; -- cgit v0.10.2 From 6f0808c48242c77c32f07c3b695ef560bee97938 Mon Sep 17 00:00:00 2001 From: Rajesh Bhagat Date: Fri, 10 Jun 2016 11:53:44 +0530 Subject: ARM: dts: ls1021a: Add dis_rxdet_inp3_quirk property to USB3 node Add "dis_rxdet_inp3_quirk" boolean property to USB3 node. This property is used to disable rx detection in P3 PHY mode. Signed-off-by: Rajesh Bhagat Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi index 5ae8e92..368e219 100644 --- a/arch/arm/boot/dts/ls1021a.dtsi +++ b/arch/arm/boot/dts/ls1021a.dtsi @@ -626,6 +626,7 @@ interrupts = ; dr_mode = "host"; snps,quirk-frame-length-adjustment = <0x20>; + snps,dis_rxdet_inp3_quirk; }; pcie@3400000 { -- cgit v0.10.2 From d04dc9521c8c929b8a3803ffc24726f150f936ea Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Tue, 10 May 2016 15:45:58 -0700 Subject: ARM: dts: qcom: Enable RPM regulators on apq8074 dragonboard Add the appropriate min/max voltages for the regulators on the apq8074 dragonboard so that they can be used by clients properly. Signed-off-by: Stephen Boyd Signed-off-by: Andy Gross diff --git a/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts b/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts index c0e2053..8d1011d 100644 --- a/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts +++ b/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts @@ -75,4 +75,203 @@ }; }; }; + + smd { + rpm { + rpm_requests { + pm8841-regulators { + s1 { + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <1050000>; + }; + + s2 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1050000>; + }; + + s3 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1050000>; + }; + + s4 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1050000>; + }; + }; + + pm8941-regulators { + vdd_l1_l3-supply = <&pm8941_s1>; + vdd_l2_lvs1_2_3-supply = <&pm8941_s3>; + vdd_l4_l11-supply = <&pm8941_s1>; + vdd_l5_l7-supply = <&pm8941_s2>; + vdd_l6_l12_l14_l15-supply = <&pm8941_s2>; + vin_5vs-supply = <&pm8941_5v>; + + s1 { + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + regulator-boot-on; + }; + + s2 { + regulator-min-microvolt = <2150000>; + regulator-max-microvolt = <2150000>; + regulator-boot-on; + }; + + s3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + l1 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + + regulator-always-on; + regulator-boot-on; + }; + + l2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + l3 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + }; + + l4 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + }; + + l5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + l6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-boot-on; + }; + + l7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-boot-on; + }; + + l8 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + l9 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + + l10 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + l11 { + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + }; + + l12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-always-on; + regulator-boot-on; + }; + + l13 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + + regulator-boot-on; + }; + + l14 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + l15 { + regulator-min-microvolt = <2050000>; + regulator-max-microvolt = <2050000>; + }; + + l16 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + }; + + l17 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + }; + + l18 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; + + l19 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + l20 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + + regulator-allow-set-load; + regulator-boot-on; + regulator-system-load = <200000>; + }; + + l21 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + + regulator-boot-on; + }; + + l22 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; + + l23 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; + + l24 { + regulator-min-microvolt = <3075000>; + regulator-max-microvolt = <3075000>; + + regulator-boot-on; + }; + }; + }; + }; + }; }; -- cgit v0.10.2 From 5fda09b809c20080f5194199bdb6012b774b393e Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Tue, 10 May 2016 15:45:59 -0700 Subject: ARM: dts: qcom: Enable sdcard and emmc on apq8074 dragonboard Enable the sdcard slot and wire up the regulators for the two storage controllers found on the apq8074 dragonboard. Signed-off-by: Stephen Boyd Signed-off-by: Andy Gross diff --git a/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts b/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts index 8d1011d..ad51df2 100644 --- a/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts +++ b/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts @@ -25,11 +25,23 @@ bus-width = <8>; non-removable; status = "ok"; + + vmmc-supply = <&pm8941_l20>; + vqmmc-supply = <&pm8941_s3>; + + pinctrl-names = "default"; + pinctrl-0 = <&sdhc1_pin_a>; }; sdhci@f98a4900 { cd-gpios = <&msmgpio 62 0x1>; + pinctrl-names = "default"; + pinctrl-0 = <&sdhc2_pin_a>, <&sdhc2_cd_pin_a>; bus-width = <4>; + status = "ok"; + + vmmc-supply = <&pm8941_l21>; + vqmmc-supply = <&pm8941_l13>; }; @@ -59,6 +71,42 @@ function = "blsp_spi8"; }; }; + + sdhc1_pin_a: sdhc1-pin-active { + clk { + pins = "sdc1_clk"; + drive-strength = <16>; + bias-disable; + }; + + cmd-data { + pins = "sdc1_cmd", "sdc1_data"; + drive-strength = <10>; + bias-pull-up; + }; + }; + + sdhc2_cd_pin_a: sdhc2-cd-pin-active { + pins = "gpio62"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + }; + + sdhc2_pin_a: sdhc2-pin-active { + clk { + pins = "sdc2_clk"; + drive-strength = <10>; + bias-disable; + }; + + cmd-data { + pins = "sdc2_cmd", "sdc2_data"; + drive-strength = <6>; + bias-pull-up; + }; + }; }; i2c@f9967000 { -- cgit v0.10.2 From a537b8d68e0b6b67ee370f9710c94bfb813b3612 Mon Sep 17 00:00:00 2001 From: Andy Gross Date: Thu, 19 May 2016 00:00:19 -0500 Subject: ARM: dts: qcom: Remove size elements from pmic reg The #size-cells for the pmics are 0, but we specify a size in the reg property so that MPP and GPIO modules can figure out how many pins there are. Now that we've done that by counting irqs, we can remove the size elements in the reg properties and be DT compliant. Signed-off-by: Andy Gross Reviewed-by: Bjorn Andersson diff --git a/arch/arm/boot/dts/qcom-pma8084.dtsi b/arch/arm/boot/dts/qcom-pma8084.dtsi index 4e9bd3f..ea7fce3 100644 --- a/arch/arm/boot/dts/qcom-pma8084.dtsi +++ b/arch/arm/boot/dts/qcom-pma8084.dtsi @@ -12,15 +12,15 @@ rtc@6000 { compatible = "qcom,pm8941-rtc"; - reg = <0x6000 0x100>, - <0x6100 0x100>; + reg = <0x6000>, + <0x6100>; reg-names = "rtc", "alarm"; interrupts = <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>; }; pma8084_gpios: gpios@c000 { compatible = "qcom,pma8084-gpio", "qcom,spmi-gpio"; - reg = <0xc000 0x1600>; + reg = <0xc000>; gpio-controller; #gpio-cells = <2>; interrupts = <0 0xc0 0 IRQ_TYPE_NONE>, @@ -49,7 +49,7 @@ pma8084_mpps: mpps@a000 { compatible = "qcom,pma8084-mpp", "qcom,spmi-mpp"; - reg = <0xa000 0x800>; + reg = <0xa000>; gpio-controller; #gpio-cells = <2>; interrupts = <0 0xa0 0 IRQ_TYPE_NONE>, @@ -64,7 +64,7 @@ pma8084_temp: temp-alarm@2400 { compatible = "qcom,spmi-temp-alarm"; - reg = <0x2400 0x100>; + reg = <0x2400>; interrupts = <0 0x24 0 IRQ_TYPE_EDGE_RISING>; #thermal-sensor-cells = <0>; io-channels = <&pma8084_vadc VADC_DIE_TEMP>; @@ -73,7 +73,7 @@ pma8084_vadc: vadc@3100 { compatible = "qcom,spmi-vadc"; - reg = <0x3100 0x100>; + reg = <0x3100>; interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>; #address-cells = <1>; #size-cells = <0>; -- cgit v0.10.2 From 71c0ed72170dc7589592a26a821c766bd4ba4c05 Mon Sep 17 00:00:00 2001 From: Andy Gross Date: Thu, 19 May 2016 00:00:20 -0500 Subject: ARM: dts: qcom: pma8084: Add pwrkey entry This patch adds the power key device tree node. Signed-off-by: Andy Gross Reviewed-by: Bjorn Andersson diff --git a/arch/arm/boot/dts/qcom-pma8084.dtsi b/arch/arm/boot/dts/qcom-pma8084.dtsi index ea7fce3..82d2580 100644 --- a/arch/arm/boot/dts/qcom-pma8084.dtsi +++ b/arch/arm/boot/dts/qcom-pma8084.dtsi @@ -18,6 +18,14 @@ interrupts = <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>; }; + pwrkey@800 { + compatible = "qcom,pm8941-pwrkey"; + reg = <0x800>; + interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>; + debounce = <15625>; + bias-pull-up; + }; + pma8084_gpios: gpios@c000 { compatible = "qcom,pma8084-gpio", "qcom,spmi-gpio"; reg = <0xc000>; -- cgit v0.10.2 From ece85839d228d8b2948a69b6f9929266bb8d5901 Mon Sep 17 00:00:00 2001 From: Andy Gross Date: Fri, 3 Jun 2016 18:25:21 -0500 Subject: dt/bindings: firmware: Add Qualcomm SCM binding This patch adds the device tree support for the Qualcomm SCM firmware. Signed-off-by: Andy Gross Reviewed-by: Stephen Boyd Acked-by: Bjorn Andersson Acked-by: Rob Herring diff --git a/Documentation/devicetree/bindings/firmware/qcom,scm.txt b/Documentation/devicetree/bindings/firmware/qcom,scm.txt new file mode 100644 index 0000000..3b4436e --- /dev/null +++ b/Documentation/devicetree/bindings/firmware/qcom,scm.txt @@ -0,0 +1,28 @@ +QCOM Secure Channel Manager (SCM) + +Qualcomm processors include an interface to communicate to the secure firmware. +This interface allows for clients to request different types of actions. These +can include CPU power up/down, HDCP requests, loading of firmware, and other +assorted actions. + +Required properties: +- compatible: must contain one of the following: + * "qcom,scm-apq8064" for APQ8064 platforms + * "qcom,scm-msm8660" for MSM8660 platforms + * "qcom,scm-msm8690" for MSM8690 platforms + * "qcom,scm" for later processors (MSM8916, APQ8084, MSM8974, etc) +- clocks: One to three clocks may be required based on compatible. + * Only core clock required for "qcom,scm-apq8064", "qcom,scm-msm8660", and "qcom,scm-msm8960" + * Core, iface, and bus clocks required for "qcom,scm" +- clock-names: Must contain "core" for the core clock, "iface" for the interface + clock and "bus" for the bus clock per the requirements of the compatible. + +Example for MSM8916: + + firmware { + scm { + compatible = "qcom,scm"; + clocks = <&gcc GCC_CRYPTO_CLK> , <&gcc GCC_CRYPTO_AXI_CLK>, <&gcc GCC_CRYPTO_AHB_CLK>; + clock-names = "core", "bus", "iface"; + }; + }; -- cgit v0.10.2 From 2b9b54666caba3a7d9f47c73f4dac22baa292a62 Mon Sep 17 00:00:00 2001 From: Andy Gross Date: Fri, 3 Jun 2016 18:25:27 -0500 Subject: dts: qcom: apq8084: Add SCM firmware node This patch adds the firmware node for the SCM Acked-by: Bjorn Andersson Signed-off-by: Andy Gross Reviewed-by: Stephen Boyd diff --git a/arch/arm/boot/dts/qcom-apq8084.dtsi b/arch/arm/boot/dts/qcom-apq8084.dtsi index a33a09f..7c2df06 100644 --- a/arch/arm/boot/dts/qcom-apq8084.dtsi +++ b/arch/arm/boot/dts/qcom-apq8084.dtsi @@ -86,6 +86,14 @@ }; }; + firmware { + scm { + compatible = "qcom,scm"; + clocks = <&gcc GCC_CE1_CLK> , <&gcc GCC_CE1_AXI_CLK>, <&gcc GCC_CE1_AHB_CLK>; + clock-names = "core", "bus", "iface"; + }; + }; + cpu-pmu { compatible = "qcom,krait-pmu"; interrupts = <1 7 0xf04>; -- cgit v0.10.2 From e0e7da5dfd37413a94c00a279a4cfd9712511675 Mon Sep 17 00:00:00 2001 From: Andy Gross Date: Fri, 3 Jun 2016 18:25:29 -0500 Subject: dts: qcom: msm8974: Add SCM firmware node This patch adds the Qualcomm SCM firmware node. Signed-off-by: Andy Gross Reviewed-by: Stephen Boyd diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index e98b373..55328d6 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -260,6 +260,14 @@ }; }; + firmware { + scm { + compatible = "qcom,scm"; + clocks = <&gcc GCC_CE1_CLK>, <&gcc GCC_CE1_AXI_CLK>, <&gcc GCC_CE1_AHB_CLK>; + clock-names = "core", "bus", "iface"; + }; + }; + soc: soc { #address-cells = <1>; #size-cells = <1>; -- cgit v0.10.2 From 9e5d41d44018bc721329e8314259d4c7f683b7c6 Mon Sep 17 00:00:00 2001 From: Andy Gross Date: Fri, 3 Jun 2016 18:25:30 -0500 Subject: dts: qcom: apq8064: Add SCM firmware node This patch adds the firmware node for the APQ8064 Signed-off-by: Andy Gross Reviewed-by: Stephen Boyd diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index df96ccd..cf37d55 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -213,6 +213,12 @@ }; }; + firmware { + scm { + compatible = "qcom,scm-apq8064"; + }; + }; + soc: soc { #address-cells = <1>; #size-cells = <1>; -- cgit v0.10.2 From c49e9e95f4d1f771e25cf6540503a4ab88798325 Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Mon, 6 Jun 2016 16:58:19 -0700 Subject: dt: binding: Add Qualcomm WCNSS control binding This binding describes the control interface for the Qualcomm WCNSS. Signed-off-by: Bjorn Andersson Acked-by: Rob Herring Signed-off-by: Andy Gross diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,wcnss.txt b/Documentation/devicetree/bindings/soc/qcom/qcom,wcnss.txt new file mode 100644 index 0000000..4ea39e9 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,wcnss.txt @@ -0,0 +1,116 @@ +Qualcomm WCNSS Binding + +This binding describes the Qualcomm WCNSS hardware. It consists of control +block and a BT, WiFi and FM radio block, all using SMD as command channels. + +- compatible: + Usage: required + Value type: + Definition: must be: "qcom,wcnss", + +- qcom,smd-channel: + Usage: required + Value type: + Definition: standard SMD property specifying the SMD channel used for + communication with the WiFi firmware. + Should be "WCNSS_CTRL". + +- qcom,mmio: + Usage: required + Value type: + Definition: reference to a node specifying the wcnss "ccu" and "dxe" + register blocks. The node must be compatible with one of + the following: + "qcom,riva", + "qcom,pronto" + += SUBNODES +The subnodes of the wcnss node are optional and describe the individual blocks in +the WCNSS. + +== Bluetooth +The following properties are defined to the bluetooth node: + +- compatible: + Usage: required + Value type: + Definition: must be: + "qcom,wcnss-bt" + +== WiFi +The following properties are defined to the WiFi node: + +- compatible: + Usage: required + Value type: + Definition: must be one of: + "qcom,wcnss-wlan", + +- interrupts: + Usage: required + Value type: + Definition: should specify the "rx" and "tx" interrupts + +- interrupt-names: + Usage: required + Value type: + Definition: must contain "rx" and "tx" + +- qcom,smem-state: + Usage: required + Value type: + Definition: should reference the tx-enable and tx-rings-empty SMEM states + +- qcom,smem-state-names: + Usage: required + Value type: + Definition: must contain "tx-enable" and "tx-rings-empty" + += EXAMPLE +The following example represents a SMD node, with one edge representing the +"pronto" subsystem, with the wcnss device and its wcn3680 BT and WiFi blocks +described; as found on the 8974 platform. + +smd { + compatible = "qcom,smd"; + + pronto-edge { + interrupts = <0 142 1>; + + qcom,ipc = <&apcs 8 17>; + qcom,smd-edge = <6>; + + wcnss { + compatible = "qcom,wcnss"; + qcom,smd-channels = "WCNSS_CTRL"; + + #address-cells = <1>; + #size-cells = <1>; + + qcom,mmio = <&pronto>; + + bt { + compatible = "qcom,wcnss-bt"; + }; + + wlan { + compatible = "qcom,wcnss-wlan"; + + interrupts = <0 145 0>, <0 146 0>; + interrupt-names = "tx", "rx"; + + qcom,smem-state = <&apps_smsm 10>, <&apps_smsm 9>; + qcom,smem-state-names = "tx-enable", "tx-rings-empty"; + }; + }; + }; +}; + +soc { + pronto: pronto { + compatible = "qcom,pronto"; + + reg = <0xfb204000 0x2000>, <0xfb202000 0x1000>, <0xfb21b000 0x3000>; + reg-names = "ccu", "dxe", "pmu"; + }; +}; -- cgit v0.10.2 From 59f0ce1a3ebb9288fc8c1400aa503e923621161e Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Mon, 23 May 2016 16:38:00 -0700 Subject: ARM: dts: Enable SRAB switch and GMACs on 5301x DTS Add the Switch Register Access Block which is a special piece of hardware allowing us to perform indirect read/writes towards the integrated BCM5301X Ethernet switch. We also add the 4 Gigabit MAC Device Tree nodes within the brcm,bus-axi bus node to get proper binding between the BCMA instantiated core and the Device Tree nodes. We will need that to be able to reference Ethernet Device Tree nodes in a future patch adding the switch ports layout. Signed-off-by: Florian Fainelli diff --git a/arch/arm/boot/dts/bcm5301x.dtsi b/arch/arm/boot/dts/bcm5301x.dtsi index 7d4d29b..9fb5658 100644 --- a/arch/arm/boot/dts/bcm5301x.dtsi +++ b/arch/arm/boot/dts/bcm5301x.dtsi @@ -239,6 +239,22 @@ status = "disabled"; }; }; + + gmac0: ethernet@24000 { + reg = <0x24000 0x800>; + }; + + gmac1: ethernet@25000 { + reg = <0x25000 0x800>; + }; + + gmac2: ethernet@26000 { + reg = <0x26000 0x800>; + }; + + gmac3: ethernet@27000 { + reg = <0x27000 0x800>; + }; }; lcpll0: lcpll0@1800c100 { @@ -260,6 +276,17 @@ "sata2"; }; + srab: srab@18007000 { + compatible = "brcm,bcm5301x-srab"; + reg = <0x18007000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + /* ports are defined in board DTS */ + }; + nand: nand@18028000 { compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1", "brcm,brcmnand"; reg = <0x18028000 0x600>, <0x1811a408 0x600>, <0x18028f00 0x20>; -- cgit v0.10.2 From 2cd0c0202f138fa95b3fbb027e87b191ad0b1884 Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Tue, 24 May 2016 11:41:58 -0700 Subject: ARM: dts: BCM5301X: Add SRAB interrupts Add interrupt mapping for the Switch Register Access Block. Only 12 interrupts are usable at the moment even though up to 32 are dedicated to the SRAB. Signed-off-by: Florian Fainelli diff --git a/arch/arm/boot/dts/bcm5301x.dtsi b/arch/arm/boot/dts/bcm5301x.dtsi index 9fb5658..a20ebd2 100644 --- a/arch/arm/boot/dts/bcm5301x.dtsi +++ b/arch/arm/boot/dts/bcm5301x.dtsi @@ -153,6 +153,21 @@ /* ChipCommon */ <0x00000000 0 &gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, + /* Switch Register Access Block */ + <0x00007000 0 &gic GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, + <0x00007000 1 &gic GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, + <0x00007000 2 &gic GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, + <0x00007000 3 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, + <0x00007000 4 &gic GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, + <0x00007000 5 &gic GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, + <0x00007000 6 &gic GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, + <0x00007000 7 &gic GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, + <0x00007000 8 &gic GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, + <0x00007000 9 &gic GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, + <0x00007000 10 &gic GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, + <0x00007000 11 &gic GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, + <0x00007000 12 &gic GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, + /* PCIe Controller 0 */ <0x00012000 0 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, <0x00012000 1 &gic GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, -- cgit v0.10.2 From 2df1808dc0e2b5358e13beb95192b15200017776 Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Wed, 25 May 2016 16:55:35 -0700 Subject: ARM: dts: BCM5310x: Enable switch ports on SmartRG SR400AC Define the port mapping for the SmartRG SR400ACE device. Reviewed-by: Andrew Lunn Signed-off-by: Florian Fainelli diff --git a/arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts b/arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts index 8b0c440..70f4bb9 100644 --- a/arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts +++ b/arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts @@ -126,3 +126,43 @@ &spi_nor { status = "okay"; }; + +&srab { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "lan4"; + }; + + port@1 { + reg = <1>; + label = "lan3"; + }; + + port@2 { + reg = <2>; + label = "lan2"; + }; + + port@3 { + reg = <3>; + label = "lan1"; + }; + + port@4 { + reg = <4>; + label = "wan"; + }; + + port@5 { + reg = <5>; + label = "cpu"; + ethernet = <&gmac0>; + }; + }; +}; -- cgit v0.10.2 From 94f58eb2a8e840f5ffe06c8392ca96140fb9390e Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 10 Jun 2016 15:00:47 +0200 Subject: ARM: dts: ape6evm: Name serial port pfc subnode after device name Name the Pin Function Controller subnode for SCIFA0 after its device name, instead of after the serial port alias. This avoids conflicts when enabling support for more serial ports later, either here or in a DT overlay. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman diff --git a/arch/arm/boot/dts/r8a73a4-ape6evm.dts b/arch/arm/boot/dts/r8a73a4-ape6evm.dts index 740e5d2..5bccc7d 100644 --- a/arch/arm/boot/dts/r8a73a4-ape6evm.dts +++ b/arch/arm/boot/dts/r8a73a4-ape6evm.dts @@ -188,7 +188,7 @@ }; &pfc { - scifa0_pins: serial0 { + scifa0_pins: scifa0 { groups = "scifa0_data"; function = "scifa0"; }; -- cgit v0.10.2 From 8b68d53ec2c1b4106c3d07781c7773ff3e61c0bf Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 10 Jun 2016 15:00:48 +0200 Subject: ARM: dts: ape6evm: Name mmc pfc subnode after device name Name the Pin Function Controller subnode for MMC0 after its device name, instead of using the generic and indexless "mmc". This avoids conflicts when enabling support for more MMC interfaces later, either here or in a DT overlay. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman diff --git a/arch/arm/boot/dts/r8a73a4-ape6evm.dts b/arch/arm/boot/dts/r8a73a4-ape6evm.dts index 5bccc7d..ec7c86e 100644 --- a/arch/arm/boot/dts/r8a73a4-ape6evm.dts +++ b/arch/arm/boot/dts/r8a73a4-ape6evm.dts @@ -193,7 +193,7 @@ function = "scifa0"; }; - mmc0_pins: mmc { + mmc0_pins: mmc0 { groups = "mmc0_data8", "mmc0_ctrl"; function = "mmc0"; }; -- cgit v0.10.2 From 94667b193c67b3510e644a61243155c234b9f87d Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 10 Jun 2016 15:00:49 +0200 Subject: ARM: dts: armadillo800eva: Name serial port pfc subnode after device name Name the Pin Function Controller subnode for SCIFA1 after its device name, instead of after the serial port alias. This avoids conflicts when enabling support for more serial ports later, either here or in a DT overlay. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman diff --git a/arch/arm/boot/dts/r8a7740-armadillo800eva.dts b/arch/arm/boot/dts/r8a7740-armadillo800eva.dts index 1620495..6866f61 100644 --- a/arch/arm/boot/dts/r8a7740-armadillo800eva.dts +++ b/arch/arm/boot/dts/r8a7740-armadillo800eva.dts @@ -232,7 +232,7 @@ function = "gether"; }; - scifa1_pins: serial1 { + scifa1_pins: scifa1 { groups = "scifa1_data"; function = "scifa1"; }; -- cgit v0.10.2 From c32149c7fd9d3716c38954bc3a99fff90a74abf7 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 10 Jun 2016 15:00:50 +0200 Subject: ARM: dts: bockw: Name serial port pfc subnode after device name Name the Pin Function Controller subnode for SCIF0 after its device name, instead of after the serial port alias. This avoids conflicts when enabling support for more serial ports later, either here or in a DT overlay. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman diff --git a/arch/arm/boot/dts/r8a7778-bockw.dts b/arch/arm/boot/dts/r8a7778-bockw.dts index 0a0bd3b..211d239 100644 --- a/arch/arm/boot/dts/r8a7778-bockw.dts +++ b/arch/arm/boot/dts/r8a7778-bockw.dts @@ -129,7 +129,7 @@ pinctrl-0 = <&scif_clk_pins>; pinctrl-names = "default"; - scif0_pins: serial0 { + scif0_pins: scif0 { groups = "scif0_data_a", "scif0_ctrl"; function = "scif0"; }; -- cgit v0.10.2 From 46344361f5cdffac3c42b9651595f6e0bd609885 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 10 Jun 2016 15:00:51 +0200 Subject: ARM: dts: marzen: Name serial port pfc subnodes after device names Name the Pin Function Controller subnodes for SCIF2 and SCIF4 after their device names, instead of using some arbitrary names that look like serial port aliases, but differ from the actual aliases. This avoids conflicts when enabling support for more serial ports later, either here or in a DT overlay. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman diff --git a/arch/arm/boot/dts/r8a7779-marzen.dts b/arch/arm/boot/dts/r8a7779-marzen.dts index cec79a6..013e6f5 100644 --- a/arch/arm/boot/dts/r8a7779-marzen.dts +++ b/arch/arm/boot/dts/r8a7779-marzen.dts @@ -195,12 +195,12 @@ }; }; - scif2_pins: serial2 { + scif2_pins: scif2 { groups = "scif2_data_c"; function = "scif2"; }; - scif4_pins: serial4 { + scif4_pins: scif4 { groups = "scif4_data"; function = "scif4"; }; -- cgit v0.10.2 From ca34829853779da173785b25531630469d0cef99 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 10 Jun 2016 15:00:52 +0200 Subject: ARM: dts: lager: Name serial port pfc subnodes after device names Name the Pin Function Controller subnodes for SCIF0 and SCIFA1 after their device names, instead of after the serial port aliases. This avoids conflicts when enabling support for more serial ports later, either here or in a DT overlay. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts index 9d20ace..c680397 100644 --- a/arch/arm/boot/dts/r8a7790-lager.dts +++ b/arch/arm/boot/dts/r8a7790-lager.dts @@ -317,7 +317,7 @@ function = "du"; }; - scif0_pins: serial0 { + scif0_pins: scif0 { groups = "scif0_data"; function = "scif0"; }; @@ -337,7 +337,7 @@ function = "intc"; }; - scifa1_pins: serial1 { + scifa1_pins: scifa1 { groups = "scifa1_data"; function = "scifa1"; }; -- cgit v0.10.2 From 85c5e4c4296bc35686334efc4eddf563ba687127 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 10 Jun 2016 15:00:53 +0200 Subject: ARM: dts: lager: Name spi pfc subnodes after device names Name the Pin Function Controller subnodes for QSPI and MSIOF1 after their device names, instead of after the spi interface aliases. This avoids conflicts when enabling support for more spi interfaces later, either here or in a DT overlay. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts index c680397..09b633f 100644 --- a/arch/arm/boot/dts/r8a7790-lager.dts +++ b/arch/arm/boot/dts/r8a7790-lager.dts @@ -371,12 +371,12 @@ function = "mmc1"; }; - qspi_pins: spi0 { + qspi_pins: qspi { groups = "qspi_ctrl", "qspi_data4"; function = "qspi"; }; - msiof1_pins: spi2 { + msiof1_pins: msiof1 { groups = "msiof1_clk", "msiof1_sync", "msiof1_rx", "msiof1_tx"; function = "msiof1"; -- cgit v0.10.2 From da84fd93486b4cd2a32c6a2effc5368bcb2269bc Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 10 Jun 2016 15:00:54 +0200 Subject: ARM: dts: lager: Name vin pfc subnode after device name Name the Pin Function Controller subnode for VIN1 after its device name, instead of using the generic and indexless "vin". This avoids conflicts when enabling support for more video inputs later, either here or in a DT overlay. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts index 09b633f..52b56fc 100644 --- a/arch/arm/boot/dts/r8a7790-lager.dts +++ b/arch/arm/boot/dts/r8a7790-lager.dts @@ -427,7 +427,7 @@ function = "usb2"; }; - vin1_pins: vin { + vin1_pins: vin1 { groups = "vin1_data8", "vin1_clk"; function = "vin1"; }; -- cgit v0.10.2 From b71b8346e2a4f007721d0e0373240bda9e939a7b Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 10 Jun 2016 15:00:55 +0200 Subject: ARM: dts: koelsch: Name serial port pfc subnodes after device names Name the Pin Function Controller subnodes for SCIF0 and SCIF1 after their device names, instead of after the serial port aliases. This avoids conflicts when enabling support for more serial ports later, either here or in a DT overlay. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman diff --git a/arch/arm/boot/dts/r8a7791-koelsch.dts b/arch/arm/boot/dts/r8a7791-koelsch.dts index 20fbc8c..73e5ecf 100644 --- a/arch/arm/boot/dts/r8a7791-koelsch.dts +++ b/arch/arm/boot/dts/r8a7791-koelsch.dts @@ -332,12 +332,12 @@ function = "du"; }; - scif0_pins: serial0 { + scif0_pins: scif0 { groups = "scif0_data_d"; function = "scif0"; }; - scif1_pins: serial1 { + scif1_pins: scif1 { groups = "scif1_data_d"; function = "scif1"; }; -- cgit v0.10.2 From a4d98bed5e697333e5dcf74503cdf560229f69bc Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 10 Jun 2016 15:00:56 +0200 Subject: ARM: dts: koelsch: Name spi pfc subnodes after device names Name the Pin Function Controller subnodes for QSPI and MSIOF0 after their device names, instead of after the spi interface aliases. This avoids conflicts when enabling support for more spi interfaces later, either here or in a DT overlay. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman diff --git a/arch/arm/boot/dts/r8a7791-koelsch.dts b/arch/arm/boot/dts/r8a7791-koelsch.dts index 73e5ecf..f8a7d09 100644 --- a/arch/arm/boot/dts/r8a7791-koelsch.dts +++ b/arch/arm/boot/dts/r8a7791-koelsch.dts @@ -372,12 +372,12 @@ function = "sdhi2"; }; - qspi_pins: spi0 { + qspi_pins: qspi { groups = "qspi_ctrl", "qspi_data4"; function = "qspi"; }; - msiof0_pins: spi1 { + msiof0_pins: msiof0 { groups = "msiof0_clk", "msiof0_sync", "msiof0_rx", "msiof0_tx"; function = "msiof0"; -- cgit v0.10.2 From a1cd3c55d3fcb0003e1dfc5f87131c6689b52944 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 10 Jun 2016 15:00:57 +0200 Subject: ARM: dts: porter: Name serial port pfc subnode after device name Name the Pin Function Controller subnode for SCIF0 after its device name, instead of after the serial port alias. This avoids conflicts when enabling support for more serial ports later, either here or in a DT overlay. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman diff --git a/arch/arm/boot/dts/r8a7791-porter.dts b/arch/arm/boot/dts/r8a7791-porter.dts index e9151e9..85d109a 100644 --- a/arch/arm/boot/dts/r8a7791-porter.dts +++ b/arch/arm/boot/dts/r8a7791-porter.dts @@ -142,7 +142,7 @@ }; &pfc { - scif0_pins: serial0 { + scif0_pins: scif0 { groups = "scif0_data_d"; function = "scif0"; }; -- cgit v0.10.2 From 2d3e17013ba58a5f092133794694d2f50a4f0564 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 10 Jun 2016 15:00:58 +0200 Subject: ARM: dts: porter: Name spi pfc subnode after device name Name the Pin Function Controller subnode for QSPI after its device name, instead of after the spi interface alias. This avoids conflicts when enabling support for more spi interfaces later, either here or in a DT overlay. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman diff --git a/arch/arm/boot/dts/r8a7791-porter.dts b/arch/arm/boot/dts/r8a7791-porter.dts index 85d109a..6761d11 100644 --- a/arch/arm/boot/dts/r8a7791-porter.dts +++ b/arch/arm/boot/dts/r8a7791-porter.dts @@ -167,7 +167,7 @@ function = "sdhi2"; }; - qspi_pins: spi0 { + qspi_pins: qspi { groups = "qspi_ctrl", "qspi_data4"; function = "qspi"; }; -- cgit v0.10.2 From 167d34af3d8b3b66dc57f60f473a1a1f4ca3cb9d Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 10 Jun 2016 15:00:59 +0200 Subject: ARM: dts: gose: Name serial port pfc subnodes after device names Name the Pin Function Controller subnodes for SCIF0 and SCIF1 after their device names, instead of after the serial port aliases. This avoids conflicts when enabling support for more serial ports later, either here or in a DT overlay. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman diff --git a/arch/arm/boot/dts/r8a7793-gose.dts b/arch/arm/boot/dts/r8a7793-gose.dts index f748360..995e1e0 100644 --- a/arch/arm/boot/dts/r8a7793-gose.dts +++ b/arch/arm/boot/dts/r8a7793-gose.dts @@ -320,12 +320,12 @@ function = "du"; }; - scif0_pins: serial0 { + scif0_pins: scif0 { groups = "scif0_data_d"; function = "scif0"; }; - scif1_pins: serial1 { + scif1_pins: scif1 { groups = "scif1_data_d"; function = "scif1"; }; -- cgit v0.10.2 From 740f5c805f39ccfa3ac95983155ab7410ccadd89 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 10 Jun 2016 15:01:00 +0200 Subject: ARM: dts: gose: Name spi pfc subnode after device name Name the Pin Function Controller subnode for QSPI after its device name, instead of after the spi interface alias. This avoids conflicts when enabling support for more spi interfaces later, either here or in a DT overlay. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman diff --git a/arch/arm/boot/dts/r8a7793-gose.dts b/arch/arm/boot/dts/r8a7793-gose.dts index 995e1e0..90af186 100644 --- a/arch/arm/boot/dts/r8a7793-gose.dts +++ b/arch/arm/boot/dts/r8a7793-gose.dts @@ -360,7 +360,7 @@ renesas,function = "sdhi2"; }; - qspi_pins: spi0 { + qspi_pins: qspi { groups = "qspi_ctrl", "qspi_data4"; function = "qspi"; }; -- cgit v0.10.2 From d88f5bc4a92f3a7a825b83708e38dd5c390cfbc6 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 10 Jun 2016 15:01:01 +0200 Subject: ARM: dts: alt: Name serial port pfc subnode after device name Name the Pin Function Controller subnode for SCIF2 after its device name, instead of using some arbitrary name that looks like a serial port alias, but differs from the actual alias. This avoids conflicts when enabling support for more serial ports later, either here or in a DT overlay. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman diff --git a/arch/arm/boot/dts/r8a7794-alt.dts b/arch/arm/boot/dts/r8a7794-alt.dts index 383ad79..1335664 100644 --- a/arch/arm/boot/dts/r8a7794-alt.dts +++ b/arch/arm/boot/dts/r8a7794-alt.dts @@ -111,7 +111,7 @@ function = "du"; }; - scif2_pins: serial2 { + scif2_pins: scif2 { groups = "scif2_data"; function = "scif2"; }; -- cgit v0.10.2 From fc10f3c93b2d32a490fcbf89329179d9d8320beb Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 10 Jun 2016 15:01:02 +0200 Subject: ARM: dts: alt: Name spi pfc subnode after device name Name the Pin Function Controller subnode for QSPI after its device name, instead of after the spi interface alias. This avoids conflicts when enabling support for more spi interfaces later, either here or in a DT overlay. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman diff --git a/arch/arm/boot/dts/r8a7794-alt.dts b/arch/arm/boot/dts/r8a7794-alt.dts index 1335664..1ad37d4 100644 --- a/arch/arm/boot/dts/r8a7794-alt.dts +++ b/arch/arm/boot/dts/r8a7794-alt.dts @@ -147,7 +147,7 @@ }; &pfc { - qspi_pins: spi0 { + qspi_pins: qspi { groups = "qspi_ctrl", "qspi_data4"; function = "qspi"; }; -- cgit v0.10.2 From 092599d69786efd91e874997964a8b2b774d8a27 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 10 Jun 2016 15:01:03 +0200 Subject: ARM: dts: silk: Name serial port pfc subnode after device name Name the Pin Function Controller subnode for SCIF2 after its device name, instead of using some arbitrary name that looks like a serial port alias, but differs from the actual alias. This avoids conflicts when enabling support for more serial ports later, either here or in a DT overlay. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman diff --git a/arch/arm/boot/dts/r8a7794-silk.dts b/arch/arm/boot/dts/r8a7794-silk.dts index b8c7a63..7e88f6fe 100644 --- a/arch/arm/boot/dts/r8a7794-silk.dts +++ b/arch/arm/boot/dts/r8a7794-silk.dts @@ -129,7 +129,7 @@ pinctrl-0 = <&scif_clk_pins>; pinctrl-names = "default"; - scif2_pins: serial2 { + scif2_pins: scif2 { groups = "scif2_data"; function = "scif2"; }; -- cgit v0.10.2 From a35cc9d26260aad5b010f247a1dae5dc8dcdf067 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 10 Jun 2016 15:01:04 +0200 Subject: ARM: dts: silk: Name spi pfc subnode after device name Name the Pin Function Controller subnode for QSPI after its device name, instead of after the spi interface alias. This avoids conflicts when enabling support for more spi interfaces later, either here or in a DT overlay. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman diff --git a/arch/arm/boot/dts/r8a7794-silk.dts b/arch/arm/boot/dts/r8a7794-silk.dts index 7e88f6fe..488de73 100644 --- a/arch/arm/boot/dts/r8a7794-silk.dts +++ b/arch/arm/boot/dts/r8a7794-silk.dts @@ -164,7 +164,7 @@ function = "sdhi1"; }; - qspi_pins: spi0 { + qspi_pins: qspi { groups = "qspi_ctrl", "qspi_data4"; function = "qspi"; }; -- cgit v0.10.2 From 970a62e07e5cfba58a571e4ba671f438065fcb19 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 10 Jun 2016 15:01:05 +0200 Subject: ARM: dts: kzm9g: Name serial port pfc subnode after device name Name the Pin Function Controller subnode for SCIFA4 after its device name, instead of after the serial port alias. This avoids conflicts when adding support for more serial ports later, either here or in a DT overlay. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman diff --git a/arch/arm/boot/dts/sh73a0-kzm9g.dts b/arch/arm/boot/dts/sh73a0-kzm9g.dts index 36567cb..1df68b1 100644 --- a/arch/arm/boot/dts/sh73a0-kzm9g.dts +++ b/arch/arm/boot/dts/sh73a0-kzm9g.dts @@ -352,7 +352,7 @@ }; }; - scifa4_pins: serial4 { + scifa4_pins: scifa4 { groups = "scifa4_data", "scifa4_ctrl"; function = "scifa4"; }; -- cgit v0.10.2 From fdaf72e52fbca9de389f86bd452189f08c6964dd Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Tue, 14 Jun 2016 11:59:44 +0900 Subject: ARM: dts: uniphier: add System Bus pinmux node This pin-muxing is needed to get access to the UniPhier System Bus. Signed-off-by: Masahiro Yamada Signed-off-by: Olof Johansson diff --git a/arch/arm/boot/dts/uniphier-common32.dtsi b/arch/arm/boot/dts/uniphier-common32.dtsi index 61a0955..891327f 100644 --- a/arch/arm/boot/dts/uniphier-common32.dtsi +++ b/arch/arm/boot/dts/uniphier-common32.dtsi @@ -105,6 +105,8 @@ reg = <0x58c00000 0x400>; #address-cells = <2>; #size-cells = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_system_bus>; }; smpctrl@59800000 { diff --git a/arch/arm/boot/dts/uniphier-pinctrl.dtsi b/arch/arm/boot/dts/uniphier-pinctrl.dtsi index f2f3fbe..10a7110 100644 --- a/arch/arm/boot/dts/uniphier-pinctrl.dtsi +++ b/arch/arm/boot/dts/uniphier-pinctrl.dtsi @@ -78,6 +78,11 @@ function = "nand"; }; + pinctrl_system_bus: system_bus_grp { + groups = "system_bus", "system_bus_cs1"; + function = "system_bus"; + }; + pinctrl_uart0: uart0_grp { groups = "uart0"; function = "uart0"; -- cgit v0.10.2 From ebe161d3e4dff446ac806ba1b5e3c8028eaa6d96 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Tue, 14 Jun 2016 11:59:45 +0900 Subject: ARM: dts: uniphier: add SoC-Glue node to UniPhier 32bit SoCs This node consists of various system-level configuration registers. Signed-off-by: Masahiro Yamada Signed-off-by: Olof Johansson diff --git a/arch/arm/boot/dts/uniphier-common32.dtsi b/arch/arm/boot/dts/uniphier-common32.dtsi index 891327f..03f60ec 100644 --- a/arch/arm/boot/dts/uniphier-common32.dtsi +++ b/arch/arm/boot/dts/uniphier-common32.dtsi @@ -136,9 +136,13 @@ interrupt-controller; }; - pinctrl: pinctrl@5f801000 { - /* specify compatible in each SoC DTSI */ - reg = <0x5f801000 0xe00>; + soc-glue@5f800000 { + compatible = "simple-mfd", "syscon"; + reg = <0x5f800000 0x2000>; + + pinctrl: pinctrl { + /* specify compatible in each SoC DTSI */ + }; }; }; }; diff --git a/arch/arm/boot/dts/uniphier-ph1-ld4.dtsi b/arch/arm/boot/dts/uniphier-ph1-ld4.dtsi index dadd860..debad7f 100644 --- a/arch/arm/boot/dts/uniphier-ph1-ld4.dtsi +++ b/arch/arm/boot/dts/uniphier-ph1-ld4.dtsi @@ -182,5 +182,5 @@ }; &pinctrl { - compatible = "socionext,ph1-ld4-pinctrl", "syscon"; + compatible = "socionext,uniphier-ld4-pinctrl"; }; diff --git a/arch/arm/boot/dts/uniphier-ph1-ld6b.dtsi b/arch/arm/boot/dts/uniphier-ph1-ld6b.dtsi index 5321152..19c107c 100644 --- a/arch/arm/boot/dts/uniphier-ph1-ld6b.dtsi +++ b/arch/arm/boot/dts/uniphier-ph1-ld6b.dtsi @@ -63,5 +63,5 @@ * which makes the pinctrl driver unshareable. */ &pinctrl { - compatible = "socionext,ph1-ld6b-pinctrl", "syscon"; + compatible = "socionext,uniphier-ld6b-pinctrl"; }; diff --git a/arch/arm/boot/dts/uniphier-ph1-pro4.dtsi b/arch/arm/boot/dts/uniphier-ph1-pro4.dtsi index 20f3f2a..7b9da08 100644 --- a/arch/arm/boot/dts/uniphier-ph1-pro4.dtsi +++ b/arch/arm/boot/dts/uniphier-ph1-pro4.dtsi @@ -200,5 +200,5 @@ }; &pinctrl { - compatible = "socionext,ph1-pro4-pinctrl", "syscon"; + compatible = "socionext,uniphier-pro4-pinctrl"; }; diff --git a/arch/arm/boot/dts/uniphier-ph1-pro5.dtsi b/arch/arm/boot/dts/uniphier-ph1-pro5.dtsi index 24f6f66..7e4aa2f 100644 --- a/arch/arm/boot/dts/uniphier-ph1-pro5.dtsi +++ b/arch/arm/boot/dts/uniphier-ph1-pro5.dtsi @@ -194,5 +194,5 @@ }; &pinctrl { - compatible = "socionext,ph1-pro5-pinctrl", "syscon"; + compatible = "socionext,uniphier-pro5-pinctrl"; }; diff --git a/arch/arm/boot/dts/uniphier-ph1-sld8.dtsi b/arch/arm/boot/dts/uniphier-ph1-sld8.dtsi index 6bfd29a..467f9d8 100644 --- a/arch/arm/boot/dts/uniphier-ph1-sld8.dtsi +++ b/arch/arm/boot/dts/uniphier-ph1-sld8.dtsi @@ -181,5 +181,5 @@ }; &pinctrl { - compatible = "socionext,ph1-sld8-pinctrl", "syscon"; + compatible = "socionext,uniphier-sld8-pinctrl"; }; diff --git a/arch/arm/boot/dts/uniphier-proxstream2.dtsi b/arch/arm/boot/dts/uniphier-proxstream2.dtsi index 4ac484c..d00d6f5 100644 --- a/arch/arm/boot/dts/uniphier-proxstream2.dtsi +++ b/arch/arm/boot/dts/uniphier-proxstream2.dtsi @@ -205,5 +205,5 @@ }; &pinctrl { - compatible = "socionext,proxstream2-pinctrl", "syscon"; + compatible = "socionext,uniphier-pxs2-pinctrl"; }; -- cgit v0.10.2 From 2a4a2aadbaad9dffdb564a2895348f3d8e825416 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Tue, 14 Jun 2016 11:59:46 +0900 Subject: ARM: dts: uniphier: renumber serial aliases for Gentil/Vodka boards On these two boards, the serial0 is used for inter-chip connection, so cannot be used for login console. The serial2 is used instead for them, but it is tedious to use because upper level deployment projects must switch login console per board. Signed-off-by: Masahiro Yamada Signed-off-by: Olof Johansson diff --git a/arch/arm/boot/dts/uniphier-proxstream2-gentil.dts b/arch/arm/boot/dts/uniphier-proxstream2-gentil.dts index bf2619e..98d895b 100644 --- a/arch/arm/boot/dts/uniphier-proxstream2-gentil.dts +++ b/arch/arm/boot/dts/uniphier-proxstream2-gentil.dts @@ -55,13 +55,13 @@ }; chosen { - stdout-path = "serial2:115200n8"; + stdout-path = "serial0:115200n8"; }; aliases { - serial0 = &serial0; - serial1 = &serial1; - serial2 = &serial2; + serial0 = &serial2; + serial1 = &serial0; + serial2 = &serial1; i2c0 = &i2c0; i2c2 = &i2c2; i2c4 = &i2c4; diff --git a/arch/arm/boot/dts/uniphier-proxstream2-vodka.dts b/arch/arm/boot/dts/uniphier-proxstream2-vodka.dts index 498acac..1fb8bd7 100644 --- a/arch/arm/boot/dts/uniphier-proxstream2-vodka.dts +++ b/arch/arm/boot/dts/uniphier-proxstream2-vodka.dts @@ -55,13 +55,13 @@ }; chosen { - stdout-path = "serial2:115200n8"; + stdout-path = "serial0:115200n8"; }; aliases { - serial0 = &serial0; - serial1 = &serial1; - serial2 = &serial2; + serial0 = &serial2; + serial1 = &serial0; + serial2 = &serial1; i2c0 = &i2c0; i2c4 = &i2c4; i2c5 = &i2c5; -- cgit v0.10.2 From cad059c6e6b2185a068453608f155e9e8a64af39 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Mon, 30 May 2016 15:27:18 +0200 Subject: ARM: dts: amlogic: Enable Reset Controller on Meson8b platforms Update DTSI file to add the reset controller node. Signed-off-by: Neil Armstrong Signed-off-by: Kevin Hilman diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi index 2bfe401..fc4080d 100644 --- a/arch/arm/boot/dts/meson8b.dtsi +++ b/arch/arm/boot/dts/meson8b.dtsi @@ -46,6 +46,7 @@ #include #include +#include #include "skeleton.dtsi" / { @@ -105,6 +106,12 @@ #interrupt-cells = <3>; }; + reset: reset-controller@c1104404 { + compatible = "amlogic,meson8b-reset"; + reg = <0xc1104404 0x20>; + #reset-cells = <1>; + }; + wdt: watchdog@c1109900 { compatible = "amlogic,meson8b-wdt"; reg = <0xc1109900 0x8>; -- cgit v0.10.2 From da4fa6fa8016dba54aef2b20793b8e99c6af022d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Mon, 13 Jun 2016 12:17:54 +0200 Subject: ARM: imx25-pinfunc: document SION being important for MX25_PAD_SD1_CMD__SD1_CMD MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Uwe Kleine-König Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/imx25-pinfunc.h b/arch/arm/boot/dts/imx25-pinfunc.h index f96fa2d..953e646 100644 --- a/arch/arm/boot/dts/imx25-pinfunc.h +++ b/arch/arm/boot/dts/imx25-pinfunc.h @@ -421,6 +421,15 @@ #define MX25_PAD_UART2_CTS__FEC_RX_ERR 0x18c 0x384 0x518 0x12 0x002 #define MX25_PAD_UART2_CTS__GPIO_4_29 0x18c 0x384 0x000 0x15 0x000 +/* + * Removing the SION bit from MX25_PAD_SD1_CMD__SD1_CMD breaks detecting an SD + * card. According to the i.MX25 reference manual (e.g. Figure 23-2 in IMX25RM + * Rev. 2 from 01/2011) this pin is bidirectional. So it seems to be a silicon + * bug that configuring the SD1_CMD function doesn't enable the input path for + * this pin. + * This might have side effects for other hardware units that are connected to + * that pin and use the respective function as input. + */ #define MX25_PAD_SD1_CMD__SD1_CMD 0x190 0x388 0x000 0x10 0x000 #define MX25_PAD_SD1_CMD__CSPI2_MOSI 0x190 0x388 0x4a0 0x11 0x001 #define MX25_PAD_SD1_CMD__FEC_RDATA2 0x190 0x388 0x50c 0x12 0x002 -- cgit v0.10.2 From 67c29a81c2cf06f290ac81d73fdd887ef3c3b971 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Mon, 13 Jun 2016 12:17:55 +0200 Subject: ARM: imx25-pinfunc: remove SION from all modes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit With the SION bit set a pin can be read as GPIO even though it's not muxed as GPIO. This is useful at times. The downside however is that the signal is not only routed to the GPIO IP but also all other IPs that can make use of the pin. This resulted in more than one issue for me in the past. Things like spi transfers that result in usb reenumeration or setting a GPIO to a value that triggers an RTS irq for an UART. This convinces me that the SION bit does more harm than good and so all SION bits are removed that are not known to be needed. Note that this has no influence on GPIOs under Linux as the gpio-mxc driver just reports the level the pin is driven to for outputs and not the level as seen on the pin. If this commit introduces a regression for you, please report which SION bit is essential for your setup. Signed-off-by: Uwe Kleine-König Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/imx25-pinfunc.h b/arch/arm/boot/dts/imx25-pinfunc.h index 953e646..f840f03 100644 --- a/arch/arm/boot/dts/imx25-pinfunc.h +++ b/arch/arm/boot/dts/imx25-pinfunc.h @@ -26,77 +26,77 @@ #define MX25_PAD_A13__GPIO_4_1 0x00c 0x22C 0x000 0x05 0x000 #define MX25_PAD_A13__LCDC_CLS 0x00c 0x22C 0x000 0x07 0x000 -#define MX25_PAD_A14__A14 0x010 0x230 0x000 0x10 0x000 -#define MX25_PAD_A14__GPIO_2_0 0x010 0x230 0x000 0x15 0x000 -#define MX25_PAD_A14__SIM1_CLK1 0x010 0x230 0x000 0x16 0x000 -#define MX25_PAD_A14__LCDC_SPL 0x010 0x230 0x000 0x17 0x000 - -#define MX25_PAD_A15__A15 0x014 0x234 0x000 0x10 0x000 -#define MX25_PAD_A15__GPIO_2_1 0x014 0x234 0x000 0x15 0x000 -#define MX25_PAD_A15__SIM1_RST1 0x014 0x234 0x000 0x16 0x000 -#define MX25_PAD_A15__LCDC_PS 0x014 0x234 0x000 0x17 0x000 - -#define MX25_PAD_A16__A16 0x018 0x000 0x000 0x10 0x000 -#define MX25_PAD_A16__GPIO_2_2 0x018 0x000 0x000 0x15 0x000 -#define MX25_PAD_A16__SIM1_VEN1 0x018 0x000 0x000 0x16 0x000 -#define MX25_PAD_A16__LCDC_REV 0x018 0x000 0x000 0x17 0x000 - -#define MX25_PAD_A17__A17 0x01c 0x238 0x000 0x10 0x000 -#define MX25_PAD_A17__GPIO_2_3 0x01c 0x238 0x000 0x15 0x000 -#define MX25_PAD_A17__SIM1_TX 0x01c 0x238 0x554 0x16 0x000 -#define MX25_PAD_A17__FEC_TX_ERR 0x01c 0x238 0x000 0x17 0x000 - -#define MX25_PAD_A18__A18 0x020 0x23c 0x000 0x10 0x000 -#define MX25_PAD_A18__GPIO_2_4 0x020 0x23c 0x000 0x15 0x000 -#define MX25_PAD_A18__SIM1_PD1 0x020 0x23c 0x550 0x16 0x000 -#define MX25_PAD_A18__FEC_COL 0x020 0x23c 0x504 0x17 0x000 - -#define MX25_PAD_A19__A19 0x024 0x240 0x000 0x10 0x000 -#define MX25_PAD_A19__GPIO_2_5 0x024 0x240 0x000 0x15 0x000 -#define MX25_PAD_A19__SIM1_RX1 0x024 0x240 0x54c 0x16 0x000 -#define MX25_PAD_A19__FEC_RX_ERR 0x024 0x240 0x518 0x17 0x000 - -#define MX25_PAD_A20__A20 0x028 0x244 0x000 0x10 0x000 -#define MX25_PAD_A20__GPIO_2_6 0x028 0x244 0x000 0x15 0x000 -#define MX25_PAD_A20__SIM2_CLK1 0x028 0x244 0x000 0x16 0x000 -#define MX25_PAD_A20__FEC_RDATA2 0x028 0x244 0x50c 0x17 0x000 - -#define MX25_PAD_A21__A21 0x02c 0x248 0x000 0x10 0x000 -#define MX25_PAD_A21__GPIO_2_7 0x02c 0x248 0x000 0x15 0x000 -#define MX25_PAD_A21__SIM2_RST1 0x02c 0x248 0x000 0x16 0x000 -#define MX25_PAD_A21__FEC_RDATA3 0x02c 0x248 0x510 0x17 0x000 - -#define MX25_PAD_A22__A22 0x030 0x000 0x000 0x10 0x000 -#define MX25_PAD_A22__GPIO_2_8 0x030 0x000 0x000 0x15 0x000 -#define MX25_PAD_A22__FEC_TDATA2 0x030 0x000 0x000 0x17 0x000 -#define MX25_PAD_A22__SIM2_VEN1 0x030 0x000 0x000 0x16 0x000 -#define MX25_PAD_A22__FEC_TDATA2 0x030 0x000 0x000 0x17 0x000 - -#define MX25_PAD_A23__A23 0x034 0x24c 0x000 0x10 0x000 -#define MX25_PAD_A23__GPIO_2_9 0x034 0x24c 0x000 0x15 0x000 -#define MX25_PAD_A23__SIM2_TX1 0x034 0x24c 0x560 0x16 0x000 -#define MX25_PAD_A23__FEC_TDATA3 0x034 0x24c 0x000 0x17 0x000 - -#define MX25_PAD_A24__A24 0x038 0x250 0x000 0x10 0x000 -#define MX25_PAD_A24__GPIO_2_10 0x038 0x250 0x000 0x15 0x000 -#define MX25_PAD_A24__SIM2_PD1 0x038 0x250 0x55c 0x16 0x000 -#define MX25_PAD_A24__FEC_RX_CLK 0x038 0x250 0x514 0x17 0x000 - -#define MX25_PAD_A25__A25 0x03c 0x254 0x000 0x10 0x000 -#define MX25_PAD_A25__GPIO_2_11 0x03c 0x254 0x000 0x15 0x000 -#define MX25_PAD_A25__FEC_CRS 0x03c 0x254 0x508 0x17 0x000 - -#define MX25_PAD_EB0__EB0 0x040 0x258 0x000 0x10 0x000 -#define MX25_PAD_EB0__AUD4_TXD 0x040 0x258 0x464 0x14 0x000 -#define MX25_PAD_EB0__GPIO_2_12 0x040 0x258 0x000 0x15 0x000 - -#define MX25_PAD_EB1__EB1 0x044 0x25c 0x000 0x10 0x000 -#define MX25_PAD_EB1__AUD4_RXD 0x044 0x25c 0x460 0x14 0x000 -#define MX25_PAD_EB1__GPIO_2_13 0x044 0x25c 0x000 0x15 0x000 - -#define MX25_PAD_OE__OE 0x048 0x260 0x000 0x10 0x000 -#define MX25_PAD_OE__AUD4_TXC 0x048 0x260 0x000 0x14 0x000 -#define MX25_PAD_OE__GPIO_2_14 0x048 0x260 0x000 0x15 0x000 +#define MX25_PAD_A14__A14 0x010 0x230 0x000 0x00 0x000 +#define MX25_PAD_A14__GPIO_2_0 0x010 0x230 0x000 0x05 0x000 +#define MX25_PAD_A14__SIM1_CLK1 0x010 0x230 0x000 0x06 0x000 +#define MX25_PAD_A14__LCDC_SPL 0x010 0x230 0x000 0x07 0x000 + +#define MX25_PAD_A15__A15 0x014 0x234 0x000 0x00 0x000 +#define MX25_PAD_A15__GPIO_2_1 0x014 0x234 0x000 0x05 0x000 +#define MX25_PAD_A15__SIM1_RST1 0x014 0x234 0x000 0x06 0x000 +#define MX25_PAD_A15__LCDC_PS 0x014 0x234 0x000 0x07 0x000 + +#define MX25_PAD_A16__A16 0x018 0x000 0x000 0x00 0x000 +#define MX25_PAD_A16__GPIO_2_2 0x018 0x000 0x000 0x05 0x000 +#define MX25_PAD_A16__SIM1_VEN1 0x018 0x000 0x000 0x06 0x000 +#define MX25_PAD_A16__LCDC_REV 0x018 0x000 0x000 0x07 0x000 + +#define MX25_PAD_A17__A17 0x01c 0x238 0x000 0x00 0x000 +#define MX25_PAD_A17__GPIO_2_3 0x01c 0x238 0x000 0x05 0x000 +#define MX25_PAD_A17__SIM1_TX 0x01c 0x238 0x554 0x06 0x000 +#define MX25_PAD_A17__FEC_TX_ERR 0x01c 0x238 0x000 0x07 0x000 + +#define MX25_PAD_A18__A18 0x020 0x23c 0x000 0x00 0x000 +#define MX25_PAD_A18__GPIO_2_4 0x020 0x23c 0x000 0x05 0x000 +#define MX25_PAD_A18__SIM1_PD1 0x020 0x23c 0x550 0x06 0x000 +#define MX25_PAD_A18__FEC_COL 0x020 0x23c 0x504 0x07 0x000 + +#define MX25_PAD_A19__A19 0x024 0x240 0x000 0x00 0x000 +#define MX25_PAD_A19__GPIO_2_5 0x024 0x240 0x000 0x05 0x000 +#define MX25_PAD_A19__SIM1_RX1 0x024 0x240 0x54c 0x06 0x000 +#define MX25_PAD_A19__FEC_RX_ERR 0x024 0x240 0x518 0x07 0x000 + +#define MX25_PAD_A20__A20 0x028 0x244 0x000 0x00 0x000 +#define MX25_PAD_A20__GPIO_2_6 0x028 0x244 0x000 0x05 0x000 +#define MX25_PAD_A20__SIM2_CLK1 0x028 0x244 0x000 0x06 0x000 +#define MX25_PAD_A20__FEC_RDATA2 0x028 0x244 0x50c 0x07 0x000 + +#define MX25_PAD_A21__A21 0x02c 0x248 0x000 0x00 0x000 +#define MX25_PAD_A21__GPIO_2_7 0x02c 0x248 0x000 0x05 0x000 +#define MX25_PAD_A21__SIM2_RST1 0x02c 0x248 0x000 0x06 0x000 +#define MX25_PAD_A21__FEC_RDATA3 0x02c 0x248 0x510 0x07 0x000 + +#define MX25_PAD_A22__A22 0x030 0x000 0x000 0x00 0x000 +#define MX25_PAD_A22__GPIO_2_8 0x030 0x000 0x000 0x05 0x000 +#define MX25_PAD_A22__FEC_TDATA2 0x030 0x000 0x000 0x07 0x000 +#define MX25_PAD_A22__SIM2_VEN1 0x030 0x000 0x000 0x06 0x000 +#define MX25_PAD_A22__FEC_TDATA2 0x030 0x000 0x000 0x07 0x000 + +#define MX25_PAD_A23__A23 0x034 0x24c 0x000 0x00 0x000 +#define MX25_PAD_A23__GPIO_2_9 0x034 0x24c 0x000 0x05 0x000 +#define MX25_PAD_A23__SIM2_TX1 0x034 0x24c 0x560 0x06 0x000 +#define MX25_PAD_A23__FEC_TDATA3 0x034 0x24c 0x000 0x07 0x000 + +#define MX25_PAD_A24__A24 0x038 0x250 0x000 0x00 0x000 +#define MX25_PAD_A24__GPIO_2_10 0x038 0x250 0x000 0x05 0x000 +#define MX25_PAD_A24__SIM2_PD1 0x038 0x250 0x55c 0x06 0x000 +#define MX25_PAD_A24__FEC_RX_CLK 0x038 0x250 0x514 0x07 0x000 + +#define MX25_PAD_A25__A25 0x03c 0x254 0x000 0x00 0x000 +#define MX25_PAD_A25__GPIO_2_11 0x03c 0x254 0x000 0x05 0x000 +#define MX25_PAD_A25__FEC_CRS 0x03c 0x254 0x508 0x07 0x000 + +#define MX25_PAD_EB0__EB0 0x040 0x258 0x000 0x00 0x000 +#define MX25_PAD_EB0__AUD4_TXD 0x040 0x258 0x464 0x04 0x000 +#define MX25_PAD_EB0__GPIO_2_12 0x040 0x258 0x000 0x05 0x000 + +#define MX25_PAD_EB1__EB1 0x044 0x25c 0x000 0x00 0x000 +#define MX25_PAD_EB1__AUD4_RXD 0x044 0x25c 0x460 0x04 0x000 +#define MX25_PAD_EB1__GPIO_2_13 0x044 0x25c 0x000 0x05 0x000 + +#define MX25_PAD_OE__OE 0x048 0x260 0x000 0x00 0x000 +#define MX25_PAD_OE__AUD4_TXC 0x048 0x260 0x000 0x04 0x000 +#define MX25_PAD_OE__GPIO_2_14 0x048 0x260 0x000 0x05 0x000 #define MX25_PAD_CS0__CS0 0x04c 0x000 0x000 0x00 0x000 #define MX25_PAD_CS0__GPIO_4_2 0x04c 0x000 0x000 0x05 0x000 @@ -105,51 +105,51 @@ #define MX25_PAD_CS1__NF_CE3 0x050 0x000 0x000 0x01 0x000 #define MX25_PAD_CS1__GPIO_4_3 0x050 0x000 0x000 0x05 0x000 -#define MX25_PAD_CS4__CS4 0x054 0x264 0x000 0x10 0x000 +#define MX25_PAD_CS4__CS4 0x054 0x264 0x000 0x00 0x000 #define MX25_PAD_CS4__NF_CE1 0x054 0x264 0x000 0x01 0x000 -#define MX25_PAD_CS4__UART5_CTS 0x054 0x264 0x000 0x13 0x000 -#define MX25_PAD_CS4__GPIO_3_20 0x054 0x264 0x000 0x15 0x000 +#define MX25_PAD_CS4__UART5_CTS 0x054 0x264 0x000 0x03 0x000 +#define MX25_PAD_CS4__GPIO_3_20 0x054 0x264 0x000 0x05 0x000 #define MX25_PAD_CS5__CS5 0x058 0x268 0x000 0x00 0x000 #define MX25_PAD_CS5__NF_CE2 0x058 0x268 0x000 0x01 0x000 #define MX25_PAD_CS5__UART5_RTS 0x058 0x268 0x574 0x03 0x000 #define MX25_PAD_CS5__GPIO_3_21 0x058 0x268 0x000 0x05 0x000 -#define MX25_PAD_NF_CE0__NF_CE0 0x05c 0x26c 0x000 0x10 0x000 -#define MX25_PAD_NF_CE0__GPIO_3_22 0x05c 0x26c 0x000 0x15 0x000 +#define MX25_PAD_NF_CE0__NF_CE0 0x05c 0x26c 0x000 0x00 0x000 +#define MX25_PAD_NF_CE0__GPIO_3_22 0x05c 0x26c 0x000 0x05 0x000 -#define MX25_PAD_ECB__ECB 0x060 0x270 0x000 0x10 0x000 -#define MX25_PAD_ECB__UART5_TXD 0x060 0x270 0x000 0x13 0x000 -#define MX25_PAD_ECB__GPIO_3_23 0x060 0x270 0x000 0x15 0x000 +#define MX25_PAD_ECB__ECB 0x060 0x270 0x000 0x00 0x000 +#define MX25_PAD_ECB__UART5_TXD 0x060 0x270 0x000 0x03 0x000 +#define MX25_PAD_ECB__GPIO_3_23 0x060 0x270 0x000 0x05 0x000 -#define MX25_PAD_LBA__LBA 0x064 0x274 0x000 0x10 0x000 -#define MX25_PAD_LBA__UART5_RXD 0x064 0x274 0x578 0x13 0x000 -#define MX25_PAD_LBA__GPIO_3_24 0x064 0x274 0x000 0x15 0x000 +#define MX25_PAD_LBA__LBA 0x064 0x274 0x000 0x00 0x000 +#define MX25_PAD_LBA__UART5_RXD 0x064 0x274 0x578 0x03 0x000 +#define MX25_PAD_LBA__GPIO_3_24 0x064 0x274 0x000 0x05 0x000 #define MX25_PAD_BCLK__BCLK 0x068 0x000 0x000 0x00 0x000 #define MX25_PAD_BCLK__GPIO_4_4 0x068 0x000 0x000 0x05 0x000 -#define MX25_PAD_RW__RW 0x06c 0x278 0x000 0x10 0x000 -#define MX25_PAD_RW__AUD4_TXFS 0x06c 0x278 0x474 0x14 0x000 -#define MX25_PAD_RW__GPIO_3_25 0x06c 0x278 0x000 0x15 0x000 +#define MX25_PAD_RW__RW 0x06c 0x278 0x000 0x00 0x000 +#define MX25_PAD_RW__AUD4_TXFS 0x06c 0x278 0x474 0x04 0x000 +#define MX25_PAD_RW__GPIO_3_25 0x06c 0x278 0x000 0x05 0x000 -#define MX25_PAD_NFWE_B__NFWE_B 0x070 0x000 0x000 0x10 0x000 -#define MX25_PAD_NFWE_B__GPIO_3_26 0x070 0x000 0x000 0x15 0x000 +#define MX25_PAD_NFWE_B__NFWE_B 0x070 0x000 0x000 0x00 0x000 +#define MX25_PAD_NFWE_B__GPIO_3_26 0x070 0x000 0x000 0x05 0x000 -#define MX25_PAD_NFRE_B__NFRE_B 0x074 0x000 0x000 0x10 0x000 -#define MX25_PAD_NFRE_B__GPIO_3_27 0x074 0x000 0x000 0x15 0x000 +#define MX25_PAD_NFRE_B__NFRE_B 0x074 0x000 0x000 0x00 0x000 +#define MX25_PAD_NFRE_B__GPIO_3_27 0x074 0x000 0x000 0x05 0x000 -#define MX25_PAD_NFALE__NFALE 0x078 0x000 0x000 0x10 0x000 -#define MX25_PAD_NFALE__GPIO_3_28 0x078 0x000 0x000 0x15 0x000 +#define MX25_PAD_NFALE__NFALE 0x078 0x000 0x000 0x00 0x000 +#define MX25_PAD_NFALE__GPIO_3_28 0x078 0x000 0x000 0x05 0x000 -#define MX25_PAD_NFCLE__NFCLE 0x07c 0x000 0x000 0x10 0x000 -#define MX25_PAD_NFCLE__GPIO_3_29 0x07c 0x000 0x000 0x15 0x000 +#define MX25_PAD_NFCLE__NFCLE 0x07c 0x000 0x000 0x00 0x000 +#define MX25_PAD_NFCLE__GPIO_3_29 0x07c 0x000 0x000 0x05 0x000 -#define MX25_PAD_NFWP_B__NFWP_B 0x080 0x000 0x000 0x10 0x000 -#define MX25_PAD_NFWP_B__GPIO_3_30 0x080 0x000 0x000 0x15 0x000 +#define MX25_PAD_NFWP_B__NFWP_B 0x080 0x000 0x000 0x00 0x000 +#define MX25_PAD_NFWP_B__GPIO_3_30 0x080 0x000 0x000 0x05 0x000 -#define MX25_PAD_NFRB__NFRB 0x084 0x27c 0x000 0x10 0x000 -#define MX25_PAD_NFRB__GPIO_3_31 0x084 0x27c 0x000 0x15 0x000 +#define MX25_PAD_NFRB__NFRB 0x084 0x27c 0x000 0x00 0x000 +#define MX25_PAD_NFRB__GPIO_3_31 0x084 0x27c 0x000 0x05 0x000 #define MX25_PAD_D15__D15 0x088 0x280 0x000 0x00 0x000 #define MX25_PAD_D15__LD16 0x088 0x280 0x000 0x01 0x000 @@ -210,101 +210,101 @@ #define MX25_PAD_D0__D0 0x0c4 0x2bc 0x000 0x00 0x000 #define MX25_PAD_D0__GPIO_4_20 0x0c4 0x2bc 0x000 0x05 0x000 -#define MX25_PAD_LD0__LD0 0x0c8 0x2c0 0x000 0x10 0x000 -#define MX25_PAD_LD0__CSI_D0 0x0c8 0x2c0 0x488 0x12 0x000 -#define MX25_PAD_LD0__GPIO_2_15 0x0c8 0x2c0 0x000 0x15 0x000 +#define MX25_PAD_LD0__LD0 0x0c8 0x2c0 0x000 0x00 0x000 +#define MX25_PAD_LD0__CSI_D0 0x0c8 0x2c0 0x488 0x02 0x000 +#define MX25_PAD_LD0__GPIO_2_15 0x0c8 0x2c0 0x000 0x05 0x000 -#define MX25_PAD_LD1__LD1 0x0cc 0x2c4 0x000 0x10 0x000 -#define MX25_PAD_LD1__CSI_D1 0x0cc 0x2c4 0x48c 0x12 0x000 -#define MX25_PAD_LD1__GPIO_2_16 0x0cc 0x2c4 0x000 0x15 0x000 +#define MX25_PAD_LD1__LD1 0x0cc 0x2c4 0x000 0x00 0x000 +#define MX25_PAD_LD1__CSI_D1 0x0cc 0x2c4 0x48c 0x02 0x000 +#define MX25_PAD_LD1__GPIO_2_16 0x0cc 0x2c4 0x000 0x05 0x000 -#define MX25_PAD_LD2__LD2 0x0d0 0x2c8 0x000 0x10 0x000 -#define MX25_PAD_LD2__GPIO_2_17 0x0d0 0x2c8 0x000 0x15 0x000 +#define MX25_PAD_LD2__LD2 0x0d0 0x2c8 0x000 0x00 0x000 +#define MX25_PAD_LD2__GPIO_2_17 0x0d0 0x2c8 0x000 0x05 0x000 -#define MX25_PAD_LD3__LD3 0x0d4 0x2cc 0x000 0x10 0x000 -#define MX25_PAD_LD3__GPIO_2_18 0x0d4 0x2cc 0x000 0x15 0x000 +#define MX25_PAD_LD3__LD3 0x0d4 0x2cc 0x000 0x00 0x000 +#define MX25_PAD_LD3__GPIO_2_18 0x0d4 0x2cc 0x000 0x05 0x000 -#define MX25_PAD_LD4__LD4 0x0d8 0x2d0 0x000 0x10 0x000 -#define MX25_PAD_LD4__GPIO_2_19 0x0d8 0x2d0 0x000 0x15 0x000 +#define MX25_PAD_LD4__LD4 0x0d8 0x2d0 0x000 0x00 0x000 +#define MX25_PAD_LD4__GPIO_2_19 0x0d8 0x2d0 0x000 0x05 0x000 -#define MX25_PAD_LD5__LD5 0x0dc 0x2d4 0x000 0x10 0x000 -#define MX25_PAD_LD5__GPIO_1_19 0x0dc 0x2d4 0x000 0x15 0x000 +#define MX25_PAD_LD5__LD5 0x0dc 0x2d4 0x000 0x00 0x000 +#define MX25_PAD_LD5__GPIO_1_19 0x0dc 0x2d4 0x000 0x05 0x000 -#define MX25_PAD_LD6__LD6 0x0e0 0x2d8 0x000 0x10 0x000 -#define MX25_PAD_LD6__GPIO_1_20 0x0e0 0x2d8 0x000 0x15 0x000 +#define MX25_PAD_LD6__LD6 0x0e0 0x2d8 0x000 0x00 0x000 +#define MX25_PAD_LD6__GPIO_1_20 0x0e0 0x2d8 0x000 0x05 0x000 -#define MX25_PAD_LD7__LD7 0x0e4 0x2dc 0x000 0x10 0x000 -#define MX25_PAD_LD7__GPIO_1_21 0x0e4 0x2dc 0x000 0x15 0x000 +#define MX25_PAD_LD7__LD7 0x0e4 0x2dc 0x000 0x00 0x000 +#define MX25_PAD_LD7__GPIO_1_21 0x0e4 0x2dc 0x000 0x05 0x000 -#define MX25_PAD_LD8__LD8 0x0e8 0x2e0 0x000 0x10 0x000 -#define MX25_PAD_LD8__UART4_RXD 0x0e8 0x2e0 0x570 0x12 0x000 -#define MX25_PAD_LD8__FEC_TX_ERR 0x0e8 0x2e0 0x000 0x15 0x000 +#define MX25_PAD_LD8__LD8 0x0e8 0x2e0 0x000 0x00 0x000 +#define MX25_PAD_LD8__UART4_RXD 0x0e8 0x2e0 0x570 0x02 0x000 +#define MX25_PAD_LD8__FEC_TX_ERR 0x0e8 0x2e0 0x000 0x05 0x000 #define MX25_PAD_LD8__SDHC2_CMD 0x0e8 0x2e0 0x4e0 0x06 0x000 -#define MX25_PAD_LD9__LD9 0x0ec 0x2e4 0x000 0x10 0x000 -#define MX25_PAD_LD9__UART4_TXD 0x0ec 0x2e4 0x000 0x12 0x000 -#define MX25_PAD_LD9__FEC_COL 0x0ec 0x2e4 0x504 0x15 0x001 +#define MX25_PAD_LD9__LD9 0x0ec 0x2e4 0x000 0x00 0x000 +#define MX25_PAD_LD9__UART4_TXD 0x0ec 0x2e4 0x000 0x02 0x000 +#define MX25_PAD_LD9__FEC_COL 0x0ec 0x2e4 0x504 0x05 0x001 #define MX25_PAD_LD9__SDHC2_CLK 0x0ec 0x2e4 0x4dc 0x06 0x000 #define MX25_PAD_LD10__LD10 0x0f0 0x2e8 0x000 0x00 0x000 #define MX25_PAD_LD10__UART4_RTS 0x0f0 0x2e8 0x56c 0x02 0x000 #define MX25_PAD_LD10__FEC_RX_ERR 0x0f0 0x2e8 0x518 0x05 0x001 -#define MX25_PAD_LD11__LD11 0x0f4 0x2ec 0x000 0x10 0x000 -#define MX25_PAD_LD11__UART4_CTS 0x0f4 0x2ec 0x000 0x12 0x000 -#define MX25_PAD_LD11__FEC_RDATA2 0x0f4 0x2ec 0x50c 0x15 0x001 +#define MX25_PAD_LD11__LD11 0x0f4 0x2ec 0x000 0x00 0x000 +#define MX25_PAD_LD11__UART4_CTS 0x0f4 0x2ec 0x000 0x02 0x000 +#define MX25_PAD_LD11__FEC_RDATA2 0x0f4 0x2ec 0x50c 0x05 0x001 #define MX25_PAD_LD11__SDHC2_DAT1 0x0f4 0x2ec 0x4e8 0x06 0x000 -#define MX25_PAD_LD12__LD12 0x0f8 0x2f0 0x000 0x10 0x000 +#define MX25_PAD_LD12__LD12 0x0f8 0x2f0 0x000 0x00 0x000 #define MX25_PAD_LD12__CSPI2_MOSI 0x0f8 0x2f0 0x4a0 0x02 0x000 -#define MX25_PAD_LD12__FEC_RDATA3 0x0f8 0x2f0 0x510 0x15 0x001 +#define MX25_PAD_LD12__FEC_RDATA3 0x0f8 0x2f0 0x510 0x05 0x001 -#define MX25_PAD_LD13__LD13 0x0fc 0x2f4 0x000 0x10 0x000 +#define MX25_PAD_LD13__LD13 0x0fc 0x2f4 0x000 0x00 0x000 #define MX25_PAD_LD13__CSPI2_MISO 0x0fc 0x2f4 0x49c 0x02 0x000 -#define MX25_PAD_LD13__FEC_TDATA2 0x0fc 0x2f4 0x000 0x15 0x000 +#define MX25_PAD_LD13__FEC_TDATA2 0x0fc 0x2f4 0x000 0x05 0x000 -#define MX25_PAD_LD14__LD14 0x100 0x2f8 0x000 0x10 0x000 +#define MX25_PAD_LD14__LD14 0x100 0x2f8 0x000 0x00 0x000 #define MX25_PAD_LD14__CSPI2_SCLK 0x100 0x2f8 0x494 0x02 0x000 -#define MX25_PAD_LD14__FEC_TDATA3 0x100 0x2f8 0x000 0x15 0x000 +#define MX25_PAD_LD14__FEC_TDATA3 0x100 0x2f8 0x000 0x05 0x000 -#define MX25_PAD_LD15__LD15 0x104 0x2fc 0x000 0x10 0x000 +#define MX25_PAD_LD15__LD15 0x104 0x2fc 0x000 0x00 0x000 #define MX25_PAD_LD15__CSPI2_RDY 0x104 0x2fc 0x498 0x02 0x000 -#define MX25_PAD_LD15__FEC_RX_CLK 0x104 0x2fc 0x514 0x15 0x001 +#define MX25_PAD_LD15__FEC_RX_CLK 0x104 0x2fc 0x514 0x05 0x001 -#define MX25_PAD_HSYNC__HSYNC 0x108 0x300 0x000 0x10 0x000 -#define MX25_PAD_HSYNC__GPIO_1_22 0x108 0x300 0x000 0x15 0x000 +#define MX25_PAD_HSYNC__HSYNC 0x108 0x300 0x000 0x00 0x000 +#define MX25_PAD_HSYNC__GPIO_1_22 0x108 0x300 0x000 0x05 0x000 -#define MX25_PAD_VSYNC__VSYNC 0x10c 0x304 0x000 0x10 0x000 -#define MX25_PAD_VSYNC__GPIO_1_23 0x10c 0x304 0x000 0x15 0x000 +#define MX25_PAD_VSYNC__VSYNC 0x10c 0x304 0x000 0x00 0x000 +#define MX25_PAD_VSYNC__GPIO_1_23 0x10c 0x304 0x000 0x05 0x000 -#define MX25_PAD_LSCLK__LSCLK 0x110 0x308 0x000 0x10 0x000 -#define MX25_PAD_LSCLK__GPIO_1_24 0x110 0x308 0x000 0x15 0x000 +#define MX25_PAD_LSCLK__LSCLK 0x110 0x308 0x000 0x00 0x000 +#define MX25_PAD_LSCLK__GPIO_1_24 0x110 0x308 0x000 0x05 0x000 -#define MX25_PAD_OE_ACD__OE_ACD 0x114 0x30c 0x000 0x10 0x000 +#define MX25_PAD_OE_ACD__OE_ACD 0x114 0x30c 0x000 0x00 0x000 #define MX25_PAD_OE_ACD__CSPI2_SS0 0x114 0x30c 0x4a4 0x02 0x000 -#define MX25_PAD_OE_ACD__GPIO_1_25 0x114 0x30c 0x000 0x15 0x000 +#define MX25_PAD_OE_ACD__GPIO_1_25 0x114 0x30c 0x000 0x05 0x000 -#define MX25_PAD_CONTRAST__CONTRAST 0x118 0x310 0x000 0x10 0x000 -#define MX25_PAD_CONTRAST__CC4 0x118 0x310 0x000 0x11 0x000 -#define MX25_PAD_CONTRAST__PWM4_PWMO 0x118 0x310 0x000 0x14 0x000 -#define MX25_PAD_CONTRAST__FEC_CRS 0x118 0x310 0x508 0x15 0x001 -#define MX25_PAD_CONTRAST__USBH2_PWR 0x118 0x310 0x000 0x16 0x000 +#define MX25_PAD_CONTRAST__CONTRAST 0x118 0x310 0x000 0x00 0x000 +#define MX25_PAD_CONTRAST__CC4 0x118 0x310 0x000 0x01 0x000 +#define MX25_PAD_CONTRAST__PWM4_PWMO 0x118 0x310 0x000 0x04 0x000 +#define MX25_PAD_CONTRAST__FEC_CRS 0x118 0x310 0x508 0x05 0x001 +#define MX25_PAD_CONTRAST__USBH2_PWR 0x118 0x310 0x000 0x06 0x000 -#define MX25_PAD_PWM__PWM 0x11c 0x314 0x000 0x10 0x000 -#define MX25_PAD_PWM__GPIO_1_26 0x11c 0x314 0x000 0x15 0x000 -#define MX25_PAD_PWM__USBH2_OC 0x11c 0x314 0x580 0x16 0x001 +#define MX25_PAD_PWM__PWM 0x11c 0x314 0x000 0x00 0x000 +#define MX25_PAD_PWM__GPIO_1_26 0x11c 0x314 0x000 0x05 0x000 +#define MX25_PAD_PWM__USBH2_OC 0x11c 0x314 0x580 0x06 0x001 -#define MX25_PAD_CSI_D2__CSI_D2 0x120 0x318 0x000 0x10 0x000 -#define MX25_PAD_CSI_D2__UART5_RXD 0x120 0x318 0x578 0x11 0x001 +#define MX25_PAD_CSI_D2__CSI_D2 0x120 0x318 0x000 0x00 0x000 +#define MX25_PAD_CSI_D2__UART5_RXD 0x120 0x318 0x578 0x01 0x001 #define MX25_PAD_CSI_D2__SIM1_CLK0 0x120 0x318 0x000 0x04 0x000 -#define MX25_PAD_CSI_D2__GPIO_1_27 0x120 0x318 0x000 0x15 0x000 -#define MX25_PAD_CSI_D2__CSPI3_MOSI 0x120 0x318 0x000 0x17 0x000 +#define MX25_PAD_CSI_D2__GPIO_1_27 0x120 0x318 0x000 0x05 0x000 +#define MX25_PAD_CSI_D2__CSPI3_MOSI 0x120 0x318 0x000 0x07 0x000 -#define MX25_PAD_CSI_D3__CSI_D3 0x124 0x31c 0x000 0x10 0x000 -#define MX25_PAD_CSI_D3__UART5_TXD 0x124 0x31c 0x000 0x11 0x000 +#define MX25_PAD_CSI_D3__CSI_D3 0x124 0x31c 0x000 0x00 0x000 +#define MX25_PAD_CSI_D3__UART5_TXD 0x124 0x31c 0x000 0x01 0x000 #define MX25_PAD_CSI_D3__SIM1_RST0 0x124 0x31c 0x000 0x04 0x000 -#define MX25_PAD_CSI_D3__GPIO_1_28 0x124 0x31c 0x000 0x15 0x000 -#define MX25_PAD_CSI_D3__CSPI3_MISO 0x124 0x31c 0x4b4 0x17 0x001 +#define MX25_PAD_CSI_D3__GPIO_1_28 0x124 0x31c 0x000 0x05 0x000 +#define MX25_PAD_CSI_D3__CSPI3_MISO 0x124 0x31c 0x4b4 0x07 0x001 #define MX25_PAD_CSI_D4__CSI_D4 0x128 0x320 0x000 0x00 0x000 #define MX25_PAD_CSI_D4__UART5_RTS 0x128 0x320 0x574 0x01 0x001 @@ -312,80 +312,80 @@ #define MX25_PAD_CSI_D4__GPIO_1_29 0x128 0x320 0x000 0x05 0x000 #define MX25_PAD_CSI_D4__CSPI3_SCLK 0x128 0x320 0x000 0x07 0x000 -#define MX25_PAD_CSI_D5__CSI_D5 0x12c 0x324 0x000 0x10 0x000 -#define MX25_PAD_CSI_D5__UART5_CTS 0x12c 0x324 0x000 0x11 0x000 +#define MX25_PAD_CSI_D5__CSI_D5 0x12c 0x324 0x000 0x00 0x000 +#define MX25_PAD_CSI_D5__UART5_CTS 0x12c 0x324 0x000 0x01 0x000 #define MX25_PAD_CSI_D5__SIM1_TX0 0x12c 0x324 0x000 0x04 0x000 -#define MX25_PAD_CSI_D5__GPIO_1_30 0x12c 0x324 0x000 0x15 0x000 -#define MX25_PAD_CSI_D5__CSPI3_RDY 0x12c 0x324 0x000 0x17 0x000 +#define MX25_PAD_CSI_D5__GPIO_1_30 0x12c 0x324 0x000 0x05 0x000 +#define MX25_PAD_CSI_D5__CSPI3_RDY 0x12c 0x324 0x000 0x07 0x000 -#define MX25_PAD_CSI_D6__CSI_D6 0x130 0x328 0x000 0x10 0x000 -#define MX25_PAD_CSI_D6__SDHC2_CMD 0x130 0x328 0x4e0 0x12 0x001 +#define MX25_PAD_CSI_D6__CSI_D6 0x130 0x328 0x000 0x00 0x000 +#define MX25_PAD_CSI_D6__SDHC2_CMD 0x130 0x328 0x4e0 0x02 0x001 #define MX25_PAD_CSI_D6__SIM1_PD0 0x130 0x328 0x000 0x04 0x000 -#define MX25_PAD_CSI_D6__GPIO_1_31 0x130 0x328 0x000 0x15 0x000 +#define MX25_PAD_CSI_D6__GPIO_1_31 0x130 0x328 0x000 0x05 0x000 -#define MX25_PAD_CSI_D7__CSI_D7 0x134 0x32c 0x000 0x10 0x000 -#define MX25_PAD_CSI_D7__SDHC2_DAT_CLK 0x134 0x32C 0x4dc 0x12 0x001 -#define MX25_PAD_CSI_D7__GPIO_1_6 0x134 0x32c 0x000 0x15 0x000 +#define MX25_PAD_CSI_D7__CSI_D7 0x134 0x32c 0x000 0x00 0x000 +#define MX25_PAD_CSI_D7__SDHC2_DAT_CLK 0x134 0x32C 0x4dc 0x02 0x001 +#define MX25_PAD_CSI_D7__GPIO_1_6 0x134 0x32c 0x000 0x05 0x000 -#define MX25_PAD_CSI_D8__CSI_D8 0x138 0x330 0x000 0x10 0x000 -#define MX25_PAD_CSI_D8__AUD6_RXC 0x138 0x330 0x000 0x12 0x000 -#define MX25_PAD_CSI_D8__GPIO_1_7 0x138 0x330 0x000 0x15 0x000 -#define MX25_PAD_CSI_D8__CSPI3_SS2 0x138 0x330 0x4c4 0x17 0x000 +#define MX25_PAD_CSI_D8__CSI_D8 0x138 0x330 0x000 0x00 0x000 +#define MX25_PAD_CSI_D8__AUD6_RXC 0x138 0x330 0x000 0x02 0x000 +#define MX25_PAD_CSI_D8__GPIO_1_7 0x138 0x330 0x000 0x05 0x000 +#define MX25_PAD_CSI_D8__CSPI3_SS2 0x138 0x330 0x4c4 0x07 0x000 -#define MX25_PAD_CSI_D9__CSI_D9 0x13c 0x334 0x000 0x10 0x000 -#define MX25_PAD_CSI_D9__AUD6_RXFS 0x13c 0x334 0x000 0x12 0x000 -#define MX25_PAD_CSI_D9__GPIO_4_21 0x13c 0x334 0x000 0x15 0x000 -#define MX25_PAD_CSI_D9__CSPI3_SS3 0x13c 0x334 0x4c8 0x17 0x000 +#define MX25_PAD_CSI_D9__CSI_D9 0x13c 0x334 0x000 0x00 0x000 +#define MX25_PAD_CSI_D9__AUD6_RXFS 0x13c 0x334 0x000 0x02 0x000 +#define MX25_PAD_CSI_D9__GPIO_4_21 0x13c 0x334 0x000 0x05 0x000 +#define MX25_PAD_CSI_D9__CSPI3_SS3 0x13c 0x334 0x4c8 0x07 0x000 -#define MX25_PAD_CSI_MCLK__CSI_MCLK 0x140 0x338 0x000 0x10 0x000 -#define MX25_PAD_CSI_MCLK__AUD6_TXD 0x140 0x338 0x000 0x11 0x000 -#define MX25_PAD_CSI_MCLK__SDHC2_DAT0 0x140 0x338 0x4e4 0x12 0x001 -#define MX25_PAD_CSI_MCLK__GPIO_1_8 0x140 0x338 0x000 0x15 0x000 +#define MX25_PAD_CSI_MCLK__CSI_MCLK 0x140 0x338 0x000 0x00 0x000 +#define MX25_PAD_CSI_MCLK__AUD6_TXD 0x140 0x338 0x000 0x01 0x000 +#define MX25_PAD_CSI_MCLK__SDHC2_DAT0 0x140 0x338 0x4e4 0x02 0x001 +#define MX25_PAD_CSI_MCLK__GPIO_1_8 0x140 0x338 0x000 0x05 0x000 -#define MX25_PAD_CSI_VSYNC__CSI_VSYNC 0x144 0x33c 0x000 0x10 0x000 -#define MX25_PAD_CSI_VSYNC__AUD6_RXD 0x144 0x33c 0x000 0x11 0x000 -#define MX25_PAD_CSI_VSYNC__SDHC2_DAT1 0x144 0x33c 0x4e8 0x12 0x001 -#define MX25_PAD_CSI_VSYNC__GPIO_1_9 0x144 0x33c 0x000 0x15 0x000 +#define MX25_PAD_CSI_VSYNC__CSI_VSYNC 0x144 0x33c 0x000 0x00 0x000 +#define MX25_PAD_CSI_VSYNC__AUD6_RXD 0x144 0x33c 0x000 0x01 0x000 +#define MX25_PAD_CSI_VSYNC__SDHC2_DAT1 0x144 0x33c 0x4e8 0x02 0x001 +#define MX25_PAD_CSI_VSYNC__GPIO_1_9 0x144 0x33c 0x000 0x05 0x000 -#define MX25_PAD_CSI_HSYNC__CSI_HSYNC 0x148 0x340 0x000 0x10 0x000 -#define MX25_PAD_CSI_HSYNC__AUD6_TXC 0x148 0x340 0x000 0x11 0x000 -#define MX25_PAD_CSI_HSYNC__SDHC2_DAT2 0x148 0x340 0x4ec 0x12 0x001 -#define MX25_PAD_CSI_HSYNC__GPIO_1_10 0x148 0x340 0x000 0x15 0x000 +#define MX25_PAD_CSI_HSYNC__CSI_HSYNC 0x148 0x340 0x000 0x00 0x000 +#define MX25_PAD_CSI_HSYNC__AUD6_TXC 0x148 0x340 0x000 0x01 0x000 +#define MX25_PAD_CSI_HSYNC__SDHC2_DAT2 0x148 0x340 0x4ec 0x02 0x001 +#define MX25_PAD_CSI_HSYNC__GPIO_1_10 0x148 0x340 0x000 0x05 0x000 -#define MX25_PAD_CSI_PIXCLK__CSI_PIXCLK 0x14c 0x344 0x000 0x10 0x000 -#define MX25_PAD_CSI_PIXCLK__AUD6_TXFS 0x14c 0x344 0x000 0x11 0x000 -#define MX25_PAD_CSI_PIXCLK__SDHC2_DAT3 0x14c 0x344 0x4f0 0x12 0x001 -#define MX25_PAD_CSI_PIXCLK__GPIO_1_11 0x14c 0x344 0x000 0x15 0x000 +#define MX25_PAD_CSI_PIXCLK__CSI_PIXCLK 0x14c 0x344 0x000 0x00 0x000 +#define MX25_PAD_CSI_PIXCLK__AUD6_TXFS 0x14c 0x344 0x000 0x01 0x000 +#define MX25_PAD_CSI_PIXCLK__SDHC2_DAT3 0x14c 0x344 0x4f0 0x02 0x001 +#define MX25_PAD_CSI_PIXCLK__GPIO_1_11 0x14c 0x344 0x000 0x05 0x000 -#define MX25_PAD_I2C1_CLK__I2C1_CLK 0x150 0x348 0x000 0x10 0x000 -#define MX25_PAD_I2C1_CLK__GPIO_1_12 0x150 0x348 0x000 0x15 0x000 +#define MX25_PAD_I2C1_CLK__I2C1_CLK 0x150 0x348 0x000 0x00 0x000 +#define MX25_PAD_I2C1_CLK__GPIO_1_12 0x150 0x348 0x000 0x05 0x000 -#define MX25_PAD_I2C1_DAT__I2C1_DAT 0x154 0x34c 0x000 0x10 0x000 -#define MX25_PAD_I2C1_DAT__GPIO_1_13 0x154 0x34c 0x000 0x15 0x000 +#define MX25_PAD_I2C1_DAT__I2C1_DAT 0x154 0x34c 0x000 0x00 0x000 +#define MX25_PAD_I2C1_DAT__GPIO_1_13 0x154 0x34c 0x000 0x05 0x000 -#define MX25_PAD_CSPI1_MOSI__CSPI1_MOSI 0x158 0x350 0x000 0x10 0x000 -#define MX25_PAD_CSPI1_MOSI__UART3_RXD 0x158 0x350 0x568 0x12 0x000 -#define MX25_PAD_CSPI1_MOSI__GPIO_1_14 0x158 0x350 0x000 0x15 0x000 +#define MX25_PAD_CSPI1_MOSI__CSPI1_MOSI 0x158 0x350 0x000 0x00 0x000 +#define MX25_PAD_CSPI1_MOSI__UART3_RXD 0x158 0x350 0x568 0x02 0x000 +#define MX25_PAD_CSPI1_MOSI__GPIO_1_14 0x158 0x350 0x000 0x05 0x000 -#define MX25_PAD_CSPI1_MISO__CSPI1_MISO 0x15c 0x354 0x000 0x10 0x000 -#define MX25_PAD_CSPI1_MISO__UART3_TXD 0x15c 0x354 0x000 0x12 0x000 -#define MX25_PAD_CSPI1_MISO__GPIO_1_15 0x15c 0x354 0x000 0x15 0x000 +#define MX25_PAD_CSPI1_MISO__CSPI1_MISO 0x15c 0x354 0x000 0x00 0x000 +#define MX25_PAD_CSPI1_MISO__UART3_TXD 0x15c 0x354 0x000 0x02 0x000 +#define MX25_PAD_CSPI1_MISO__GPIO_1_15 0x15c 0x354 0x000 0x05 0x000 -#define MX25_PAD_CSPI1_SS0__CSPI1_SS0 0x160 0x358 0x000 0x10 0x000 -#define MX25_PAD_CSPI1_SS0__PWM2_PWMO 0x160 0x358 0x000 0x12 0x000 -#define MX25_PAD_CSPI1_SS0__GPIO_1_16 0x160 0x358 0x000 0x15 0x000 +#define MX25_PAD_CSPI1_SS0__CSPI1_SS0 0x160 0x358 0x000 0x00 0x000 +#define MX25_PAD_CSPI1_SS0__PWM2_PWMO 0x160 0x358 0x000 0x02 0x000 +#define MX25_PAD_CSPI1_SS0__GPIO_1_16 0x160 0x358 0x000 0x05 0x000 #define MX25_PAD_CSPI1_SS1__CSPI1_SS1 0x164 0x35c 0x000 0x00 0x000 #define MX25_PAD_CSPI1_SS1__I2C3_DAT 0x164 0x35C 0x528 0x01 0x001 #define MX25_PAD_CSPI1_SS1__UART3_RTS 0x164 0x35c 0x000 0x02 0x000 #define MX25_PAD_CSPI1_SS1__GPIO_1_17 0x164 0x35c 0x000 0x05 0x000 -#define MX25_PAD_CSPI1_SCLK__CSPI1_SCLK 0x168 0x360 0x000 0x10 0x000 -#define MX25_PAD_CSPI1_SCLK__UART3_CTS 0x168 0x360 0x000 0x12 0x000 -#define MX25_PAD_CSPI1_SCLK__GPIO_1_18 0x168 0x360 0x000 0x15 0x000 +#define MX25_PAD_CSPI1_SCLK__CSPI1_SCLK 0x168 0x360 0x000 0x00 0x000 +#define MX25_PAD_CSPI1_SCLK__UART3_CTS 0x168 0x360 0x000 0x02 0x000 +#define MX25_PAD_CSPI1_SCLK__GPIO_1_18 0x168 0x360 0x000 0x05 0x000 -#define MX25_PAD_CSPI1_RDY__CSPI1_RDY 0x16c 0x364 0x000 0x10 0x000 -#define MX25_PAD_CSPI1_RDY__GPIO_2_22 0x16c 0x364 0x000 0x15 0x000 +#define MX25_PAD_CSPI1_RDY__CSPI1_RDY 0x16c 0x364 0x000 0x00 0x000 +#define MX25_PAD_CSPI1_RDY__GPIO_2_22 0x16c 0x364 0x000 0x05 0x000 #define MX25_PAD_UART1_RXD__UART1_RXD 0x170 0x368 0x000 0x00 0x000 #define MX25_PAD_UART1_RXD__UART2_DTR 0x170 0x368 0x000 0x03 0x000 @@ -406,20 +406,20 @@ #define MX25_PAD_UART1_CTS__UART2_RI 0x17c 0x374 0x000 0x03 0x001 #define MX25_PAD_UART1_CTS__GPIO_4_25 0x17c 0x374 0x000 0x05 0x000 -#define MX25_PAD_UART2_RXD__UART2_RXD 0x180 0x378 0x000 0x10 0x000 -#define MX25_PAD_UART2_RXD__GPIO_4_26 0x180 0x378 0x000 0x15 0x000 +#define MX25_PAD_UART2_RXD__UART2_RXD 0x180 0x378 0x000 0x00 0x000 +#define MX25_PAD_UART2_RXD__GPIO_4_26 0x180 0x378 0x000 0x05 0x000 -#define MX25_PAD_UART2_TXD__UART2_TXD 0x184 0x37c 0x000 0x10 0x000 -#define MX25_PAD_UART2_TXD__GPIO_4_27 0x184 0x37c 0x000 0x15 0x000 +#define MX25_PAD_UART2_TXD__UART2_TXD 0x184 0x37c 0x000 0x00 0x000 +#define MX25_PAD_UART2_TXD__GPIO_4_27 0x184 0x37c 0x000 0x05 0x000 #define MX25_PAD_UART2_RTS__UART2_RTS 0x188 0x380 0x000 0x00 0x000 #define MX25_PAD_UART2_RTS__FEC_COL 0x188 0x380 0x504 0x02 0x002 #define MX25_PAD_UART2_RTS__CC1 0x188 0x380 0x000 0x03 0x000 #define MX25_PAD_UART2_RTS__GPIO_4_28 0x188 0x380 0x000 0x05 0x000 -#define MX25_PAD_UART2_CTS__UART2_CTS 0x18c 0x384 0x000 0x10 0x000 -#define MX25_PAD_UART2_CTS__FEC_RX_ERR 0x18c 0x384 0x518 0x12 0x002 -#define MX25_PAD_UART2_CTS__GPIO_4_29 0x18c 0x384 0x000 0x15 0x000 +#define MX25_PAD_UART2_CTS__UART2_CTS 0x18c 0x384 0x000 0x00 0x000 +#define MX25_PAD_UART2_CTS__FEC_RX_ERR 0x18c 0x384 0x518 0x02 0x002 +#define MX25_PAD_UART2_CTS__GPIO_4_29 0x18c 0x384 0x000 0x05 0x000 /* * Removing the SION bit from MX25_PAD_SD1_CMD__SD1_CMD breaks detecting an SD @@ -431,30 +431,30 @@ * that pin and use the respective function as input. */ #define MX25_PAD_SD1_CMD__SD1_CMD 0x190 0x388 0x000 0x10 0x000 -#define MX25_PAD_SD1_CMD__CSPI2_MOSI 0x190 0x388 0x4a0 0x11 0x001 -#define MX25_PAD_SD1_CMD__FEC_RDATA2 0x190 0x388 0x50c 0x12 0x002 -#define MX25_PAD_SD1_CMD__GPIO_2_23 0x190 0x388 0x000 0x15 0x000 +#define MX25_PAD_SD1_CMD__CSPI2_MOSI 0x190 0x388 0x4a0 0x01 0x001 +#define MX25_PAD_SD1_CMD__FEC_RDATA2 0x190 0x388 0x50c 0x02 0x002 +#define MX25_PAD_SD1_CMD__GPIO_2_23 0x190 0x388 0x000 0x05 0x000 -#define MX25_PAD_SD1_CLK__SD1_CLK 0x194 0x38c 0x000 0x10 0x000 -#define MX25_PAD_SD1_CLK__CSPI2_MISO 0x194 0x38c 0x49c 0x11 0x001 -#define MX25_PAD_SD1_CLK__FEC_RDATA3 0x194 0x38c 0x510 0x12 0x002 -#define MX25_PAD_SD1_CLK__GPIO_2_24 0x194 0x38c 0x000 0x15 0x000 +#define MX25_PAD_SD1_CLK__SD1_CLK 0x194 0x38c 0x000 0x00 0x000 +#define MX25_PAD_SD1_CLK__CSPI2_MISO 0x194 0x38c 0x49c 0x01 0x001 +#define MX25_PAD_SD1_CLK__FEC_RDATA3 0x194 0x38c 0x510 0x02 0x002 +#define MX25_PAD_SD1_CLK__GPIO_2_24 0x194 0x38c 0x000 0x05 0x000 -#define MX25_PAD_SD1_DATA0__SD1_DATA0 0x198 0x390 0x000 0x10 0x000 -#define MX25_PAD_SD1_DATA0__CSPI2_SCLK 0x198 0x390 0x494 0x11 0x001 -#define MX25_PAD_SD1_DATA0__GPIO_2_25 0x198 0x390 0x000 0x15 0x000 +#define MX25_PAD_SD1_DATA0__SD1_DATA0 0x198 0x390 0x000 0x00 0x000 +#define MX25_PAD_SD1_DATA0__CSPI2_SCLK 0x198 0x390 0x494 0x01 0x001 +#define MX25_PAD_SD1_DATA0__GPIO_2_25 0x198 0x390 0x000 0x05 0x000 -#define MX25_PAD_SD1_DATA1__SD1_DATA1 0x19c 0x394 0x000 0x10 0x000 -#define MX25_PAD_SD1_DATA1__AUD7_RXD 0x19c 0x394 0x478 0x13 0x000 -#define MX25_PAD_SD1_DATA1__GPIO_2_26 0x19c 0x394 0x000 0x15 0x000 +#define MX25_PAD_SD1_DATA1__SD1_DATA1 0x19c 0x394 0x000 0x00 0x000 +#define MX25_PAD_SD1_DATA1__AUD7_RXD 0x19c 0x394 0x478 0x03 0x000 +#define MX25_PAD_SD1_DATA1__GPIO_2_26 0x19c 0x394 0x000 0x05 0x000 -#define MX25_PAD_SD1_DATA2__SD1_DATA2 0x1a0 0x398 0x000 0x10 0x000 -#define MX25_PAD_SD1_DATA2__FEC_RX_CLK 0x1a0 0x398 0x514 0x12 0x002 -#define MX25_PAD_SD1_DATA2__GPIO_2_27 0x1a0 0x398 0x000 0x15 0x000 +#define MX25_PAD_SD1_DATA2__SD1_DATA2 0x1a0 0x398 0x000 0x00 0x000 +#define MX25_PAD_SD1_DATA2__FEC_RX_CLK 0x1a0 0x398 0x514 0x02 0x002 +#define MX25_PAD_SD1_DATA2__GPIO_2_27 0x1a0 0x398 0x000 0x05 0x000 -#define MX25_PAD_SD1_DATA3__SD1_DATA3 0x1a4 0x39c 0x000 0x10 0x000 -#define MX25_PAD_SD1_DATA3__FEC_CRS 0x1a4 0x39c 0x508 0x12 0x002 -#define MX25_PAD_SD1_DATA3__GPIO_2_28 0x1a4 0x39c 0x000 0x15 0x000 +#define MX25_PAD_SD1_DATA3__SD1_DATA3 0x1a4 0x39c 0x000 0x00 0x000 +#define MX25_PAD_SD1_DATA3__FEC_CRS 0x1a4 0x39c 0x508 0x02 0x002 +#define MX25_PAD_SD1_DATA3__GPIO_2_28 0x1a4 0x39c 0x000 0x05 0x000 #define MX25_PAD_KPP_ROW0__KPP_ROW0 0x1a8 0x3a0 0x000 0x00 0x000 #define MX25_PAD_KPP_ROW0__UART3_RXD 0x1a8 0x3a0 0x568 0x01 0x001 @@ -478,123 +478,123 @@ #define MX25_PAD_KPP_ROW3__UART1_RI 0x1b4 0x3ac 0x000 0x04 0x000 #define MX25_PAD_KPP_ROW3__GPIO_3_0 0x1b4 0x3ac 0x000 0x05 0x000 -#define MX25_PAD_KPP_COL0__KPP_COL0 0x1b8 0x3b0 0x000 0x10 0x000 -#define MX25_PAD_KPP_COL0__UART4_RXD 0x1b8 0x3b0 0x570 0x11 0x001 -#define MX25_PAD_KPP_COL0__AUD5_TXD 0x1b8 0x3b0 0x000 0x12 0x000 -#define MX25_PAD_KPP_COL0__GPIO_3_1 0x1b8 0x3b0 0x000 0x15 0x000 +#define MX25_PAD_KPP_COL0__KPP_COL0 0x1b8 0x3b0 0x000 0x00 0x000 +#define MX25_PAD_KPP_COL0__UART4_RXD 0x1b8 0x3b0 0x570 0x01 0x001 +#define MX25_PAD_KPP_COL0__AUD5_TXD 0x1b8 0x3b0 0x000 0x02 0x000 +#define MX25_PAD_KPP_COL0__GPIO_3_1 0x1b8 0x3b0 0x000 0x05 0x000 -#define MX25_PAD_KPP_COL1__KPP_COL1 0x1bc 0x3b4 0x000 0x10 0x000 -#define MX25_PAD_KPP_COL1__UART4_TXD 0x1bc 0x3b4 0x000 0x11 0x000 -#define MX25_PAD_KPP_COL1__AUD5_RXD 0x1bc 0x3b4 0x000 0x12 0x000 -#define MX25_PAD_KPP_COL1__GPIO_3_2 0x1bc 0x3b4 0x000 0x15 0x000 +#define MX25_PAD_KPP_COL1__KPP_COL1 0x1bc 0x3b4 0x000 0x00 0x000 +#define MX25_PAD_KPP_COL1__UART4_TXD 0x1bc 0x3b4 0x000 0x01 0x000 +#define MX25_PAD_KPP_COL1__AUD5_RXD 0x1bc 0x3b4 0x000 0x02 0x000 +#define MX25_PAD_KPP_COL1__GPIO_3_2 0x1bc 0x3b4 0x000 0x05 0x000 #define MX25_PAD_KPP_COL2__KPP_COL2 0x1c0 0x3b8 0x000 0x00 0x000 #define MX25_PAD_KPP_COL2__UART4_RTS 0x1c0 0x3b8 0x56c 0x01 0x001 #define MX25_PAD_KPP_COL2__AUD5_TXC 0x1c0 0x3b8 0x000 0x02 0x000 #define MX25_PAD_KPP_COL2__GPIO_3_3 0x1c0 0x3b8 0x000 0x05 0x000 -#define MX25_PAD_KPP_COL3__KPP_COL3 0x1c4 0x3bc 0x000 0x10 0x000 -#define MX25_PAD_KPP_COL3__UART4_CTS 0x1c4 0x3bc 0x000 0x11 0x000 -#define MX25_PAD_KPP_COL3__AUD5_TXFS 0x1c4 0x3bc 0x000 0x12 0x000 -#define MX25_PAD_KPP_COL3__GPIO_3_4 0x1c4 0x3bc 0x000 0x15 0x000 +#define MX25_PAD_KPP_COL3__KPP_COL3 0x1c4 0x3bc 0x000 0x00 0x000 +#define MX25_PAD_KPP_COL3__UART4_CTS 0x1c4 0x3bc 0x000 0x01 0x000 +#define MX25_PAD_KPP_COL3__AUD5_TXFS 0x1c4 0x3bc 0x000 0x02 0x000 +#define MX25_PAD_KPP_COL3__GPIO_3_4 0x1c4 0x3bc 0x000 0x05 0x000 -#define MX25_PAD_FEC_MDC__FEC_MDC 0x1c8 0x3c0 0x000 0x10 0x000 -#define MX25_PAD_FEC_MDC__AUD4_TXD 0x1c8 0x3c0 0x464 0x12 0x001 -#define MX25_PAD_FEC_MDC__GPIO_3_5 0x1c8 0x3c0 0x000 0x15 0x000 +#define MX25_PAD_FEC_MDC__FEC_MDC 0x1c8 0x3c0 0x000 0x00 0x000 +#define MX25_PAD_FEC_MDC__AUD4_TXD 0x1c8 0x3c0 0x464 0x02 0x001 +#define MX25_PAD_FEC_MDC__GPIO_3_5 0x1c8 0x3c0 0x000 0x05 0x000 -#define MX25_PAD_FEC_MDIO__FEC_MDIO 0x1cc 0x3c4 0x000 0x10 0x000 -#define MX25_PAD_FEC_MDIO__AUD4_RXD 0x1cc 0x3c4 0x460 0x12 0x001 -#define MX25_PAD_FEC_MDIO__GPIO_3_6 0x1cc 0x3c4 0x000 0x15 0x000 +#define MX25_PAD_FEC_MDIO__FEC_MDIO 0x1cc 0x3c4 0x000 0x00 0x000 +#define MX25_PAD_FEC_MDIO__AUD4_RXD 0x1cc 0x3c4 0x460 0x02 0x001 +#define MX25_PAD_FEC_MDIO__GPIO_3_6 0x1cc 0x3c4 0x000 0x05 0x000 -#define MX25_PAD_FEC_TDATA0__FEC_TDATA0 0x1d0 0x3c8 0x000 0x10 0x000 -#define MX25_PAD_FEC_TDATA0__GPIO_3_7 0x1d0 0x3c8 0x000 0x15 0x000 +#define MX25_PAD_FEC_TDATA0__FEC_TDATA0 0x1d0 0x3c8 0x000 0x00 0x000 +#define MX25_PAD_FEC_TDATA0__GPIO_3_7 0x1d0 0x3c8 0x000 0x05 0x000 -#define MX25_PAD_FEC_TDATA1__FEC_TDATA1 0x1d4 0x3cc 0x000 0x10 0x000 -#define MX25_PAD_FEC_TDATA1__AUD4_TXFS 0x1d4 0x3cc 0x474 0x12 0x001 -#define MX25_PAD_FEC_TDATA1__GPIO_3_8 0x1d4 0x3cc 0x000 0x15 0x000 +#define MX25_PAD_FEC_TDATA1__FEC_TDATA1 0x1d4 0x3cc 0x000 0x00 0x000 +#define MX25_PAD_FEC_TDATA1__AUD4_TXFS 0x1d4 0x3cc 0x474 0x02 0x001 +#define MX25_PAD_FEC_TDATA1__GPIO_3_8 0x1d4 0x3cc 0x000 0x05 0x000 -#define MX25_PAD_FEC_TX_EN__FEC_TX_EN 0x1d8 0x3d0 0x000 0x10 0x000 -#define MX25_PAD_FEC_TX_EN__GPIO_3_9 0x1d8 0x3d0 0x000 0x15 0x000 +#define MX25_PAD_FEC_TX_EN__FEC_TX_EN 0x1d8 0x3d0 0x000 0x00 0x000 +#define MX25_PAD_FEC_TX_EN__GPIO_3_9 0x1d8 0x3d0 0x000 0x05 0x000 -#define MX25_PAD_FEC_RDATA0__FEC_RDATA0 0x1dc 0x3d4 0x000 0x10 0x000 -#define MX25_PAD_FEC_RDATA0__GPIO_3_10 0x1dc 0x3d4 0x000 0x15 0x000 +#define MX25_PAD_FEC_RDATA0__FEC_RDATA0 0x1dc 0x3d4 0x000 0x00 0x000 +#define MX25_PAD_FEC_RDATA0__GPIO_3_10 0x1dc 0x3d4 0x000 0x05 0x000 -#define MX25_PAD_FEC_RDATA1__FEC_RDATA1 0x1e0 0x3d8 0x000 0x10 0x000 +#define MX25_PAD_FEC_RDATA1__FEC_RDATA1 0x1e0 0x3d8 0x000 0x00 0x000 /* * According to the i.MX25 Reference manual (IMX25RM, Rev. 2, * 01/2011) this is CAN1_TX but that's wrong. */ -#define MX25_PAD_FEC_RDATA1__CAN2_TX 0x1e0 0x3d8 0x000 0x14 0x000 -#define MX25_PAD_FEC_RDATA1__GPIO_3_11 0x1e0 0x3d8 0x000 0x15 0x000 +#define MX25_PAD_FEC_RDATA1__CAN2_TX 0x1e0 0x3d8 0x000 0x04 0x000 +#define MX25_PAD_FEC_RDATA1__GPIO_3_11 0x1e0 0x3d8 0x000 0x05 0x000 -#define MX25_PAD_FEC_RX_DV__FEC_RX_DV 0x1e4 0x3dc 0x000 0x10 0x000 +#define MX25_PAD_FEC_RX_DV__FEC_RX_DV 0x1e4 0x3dc 0x000 0x00 0x000 /* * According to the i.MX25 Reference manual (IMX25RM, Rev. 2, * 01/2011) this is CAN1_RX but that's wrong. */ -#define MX25_PAD_FEC_RX_DV__CAN2_RX 0x1e4 0x3dc 0x484 0x14 0x000 -#define MX25_PAD_FEC_RX_DV__GPIO_3_12 0x1e4 0x3dc 0x000 0x15 0x000 +#define MX25_PAD_FEC_RX_DV__CAN2_RX 0x1e4 0x3dc 0x484 0x04 0x000 +#define MX25_PAD_FEC_RX_DV__GPIO_3_12 0x1e4 0x3dc 0x000 0x05 0x000 -#define MX25_PAD_FEC_TX_CLK__FEC_TX_CLK 0x1e8 0x3e0 0x000 0x10 0x000 -#define MX25_PAD_FEC_TX_CLK__GPIO_3_13 0x1e8 0x3e0 0x000 0x15 0x000 +#define MX25_PAD_FEC_TX_CLK__FEC_TX_CLK 0x1e8 0x3e0 0x000 0x00 0x000 +#define MX25_PAD_FEC_TX_CLK__GPIO_3_13 0x1e8 0x3e0 0x000 0x05 0x000 -#define MX25_PAD_RTCK__RTCK 0x1ec 0x3e4 0x000 0x10 0x000 -#define MX25_PAD_RTCK__OWIRE 0x1ec 0x3e4 0x000 0x11 0x000 -#define MX25_PAD_RTCK__GPIO_3_14 0x1ec 0x3e4 0x000 0x15 0x000 +#define MX25_PAD_RTCK__RTCK 0x1ec 0x3e4 0x000 0x00 0x000 +#define MX25_PAD_RTCK__OWIRE 0x1ec 0x3e4 0x000 0x01 0x000 +#define MX25_PAD_RTCK__GPIO_3_14 0x1ec 0x3e4 0x000 0x05 0x000 -#define MX25_PAD_DE_B__DE_B 0x1f0 0x3ec 0x000 0x10 0x000 -#define MX25_PAD_DE_B__GPIO_2_20 0x1f0 0x3ec 0x000 0x15 0x000 +#define MX25_PAD_DE_B__DE_B 0x1f0 0x3ec 0x000 0x00 0x000 +#define MX25_PAD_DE_B__GPIO_2_20 0x1f0 0x3ec 0x000 0x05 0x000 -#define MX25_PAD_GPIO_A__GPIO_A 0x1f4 0x3f0 0x000 0x10 0x000 -#define MX25_PAD_GPIO_A__CAN1_TX 0x1f4 0x3f0 0x000 0x16 0x000 -#define MX25_PAD_GPIO_A__USBOTG_PWR 0x1f4 0x3f0 0x000 0x12 0x000 +#define MX25_PAD_GPIO_A__GPIO_A 0x1f4 0x3f0 0x000 0x00 0x000 +#define MX25_PAD_GPIO_A__CAN1_TX 0x1f4 0x3f0 0x000 0x06 0x000 +#define MX25_PAD_GPIO_A__USBOTG_PWR 0x1f4 0x3f0 0x000 0x02 0x000 -#define MX25_PAD_GPIO_B__GPIO_B 0x1f8 0x3f4 0x000 0x10 0x000 -#define MX25_PAD_GPIO_B__USBOTG_OC 0x1f8 0x3f4 0x57c 0x12 0x001 -#define MX25_PAD_GPIO_B__CAN1_RX 0x1f8 0x3f4 0x480 0x16 0x001 +#define MX25_PAD_GPIO_B__GPIO_B 0x1f8 0x3f4 0x000 0x00 0x000 +#define MX25_PAD_GPIO_B__USBOTG_OC 0x1f8 0x3f4 0x57c 0x02 0x001 +#define MX25_PAD_GPIO_B__CAN1_RX 0x1f8 0x3f4 0x480 0x06 0x001 -#define MX25_PAD_GPIO_C__GPIO_C 0x1fc 0x3f8 0x000 0x10 0x000 -#define MX25_PAD_GPIO_C__PWM4_PWMO 0x1fc 0x3f8 0x000 0x11 0x000 -#define MX25_PAD_GPIO_C__I2C2_SCL 0x1fc 0x3f8 0x51c 0x12 0x001 -#define MX25_PAD_GPIO_C__KPP_COL4 0x1fc 0x3f8 0x52c 0x13 0x001 -#define MX25_PAD_GPIO_C__CAN2_TX 0x1fc 0x3f8 0x000 0x16 0x000 +#define MX25_PAD_GPIO_C__GPIO_C 0x1fc 0x3f8 0x000 0x00 0x000 +#define MX25_PAD_GPIO_C__PWM4_PWMO 0x1fc 0x3f8 0x000 0x01 0x000 +#define MX25_PAD_GPIO_C__I2C2_SCL 0x1fc 0x3f8 0x51c 0x02 0x001 +#define MX25_PAD_GPIO_C__KPP_COL4 0x1fc 0x3f8 0x52c 0x03 0x001 +#define MX25_PAD_GPIO_C__CAN2_TX 0x1fc 0x3f8 0x000 0x06 0x000 -#define MX25_PAD_GPIO_D__GPIO_D 0x200 0x3fc 0x000 0x10 0x000 -#define MX25_PAD_GPIO_D__I2C2_SDA 0x200 0x3fc 0x520 0x12 0x001 -#define MX25_PAD_GPIO_D__CAN2_RX 0x200 0x3fc 0x484 0x16 0x001 +#define MX25_PAD_GPIO_D__GPIO_D 0x200 0x3fc 0x000 0x00 0x000 +#define MX25_PAD_GPIO_D__I2C2_SDA 0x200 0x3fc 0x520 0x02 0x001 +#define MX25_PAD_GPIO_D__CAN2_RX 0x200 0x3fc 0x484 0x06 0x001 -#define MX25_PAD_GPIO_E__GPIO_E 0x204 0x400 0x000 0x10 0x000 -#define MX25_PAD_GPIO_E__I2C3_CLK 0x204 0x400 0x524 0x11 0x002 -#define MX25_PAD_GPIO_E__LD16 0x204 0x400 0x000 0x12 0x000 -#define MX25_PAD_GPIO_E__AUD7_TXD 0x204 0x400 0x000 0x14 0x000 -#define MX25_PAD_GPIO_E__UART4_RXD 0x204 0x400 0x570 0x16 0x002 +#define MX25_PAD_GPIO_E__GPIO_E 0x204 0x400 0x000 0x00 0x000 +#define MX25_PAD_GPIO_E__I2C3_CLK 0x204 0x400 0x524 0x01 0x002 +#define MX25_PAD_GPIO_E__LD16 0x204 0x400 0x000 0x02 0x000 +#define MX25_PAD_GPIO_E__AUD7_TXD 0x204 0x400 0x000 0x04 0x000 +#define MX25_PAD_GPIO_E__UART4_RXD 0x204 0x400 0x570 0x06 0x002 -#define MX25_PAD_GPIO_F__GPIO_F 0x208 0x404 0x000 0x10 0x000 -#define MX25_PAD_GPIO_F__LD17 0x208 0x404 0x000 0x12 0x000 -#define MX25_PAD_GPIO_F__AUD7_TXC 0x208 0x404 0x000 0x14 0x000 -#define MX25_PAD_GPIO_F__UART4_TXD 0x208 0x404 0x000 0x16 0x000 +#define MX25_PAD_GPIO_F__GPIO_F 0x208 0x404 0x000 0x00 0x000 +#define MX25_PAD_GPIO_F__LD17 0x208 0x404 0x000 0x02 0x000 +#define MX25_PAD_GPIO_F__AUD7_TXC 0x208 0x404 0x000 0x04 0x000 +#define MX25_PAD_GPIO_F__UART4_TXD 0x208 0x404 0x000 0x06 0x000 -#define MX25_PAD_EXT_ARMCLK__EXT_ARMCLK 0x20c 0x000 0x000 0x10 0x000 -#define MX25_PAD_EXT_ARMCLK__GPIO_3_15 0x20c 0x000 0x000 0x15 0x000 +#define MX25_PAD_EXT_ARMCLK__EXT_ARMCLK 0x20c 0x000 0x000 0x00 0x000 +#define MX25_PAD_EXT_ARMCLK__GPIO_3_15 0x20c 0x000 0x000 0x05 0x000 -#define MX25_PAD_UPLL_BYPCLK__UPLL_BYPCLK 0x210 0x000 0x000 0x10 0x000 -#define MX25_PAD_UPLL_BYPCLK__GPIO_3_16 0x210 0x000 0x000 0x15 0x000 +#define MX25_PAD_UPLL_BYPCLK__UPLL_BYPCLK 0x210 0x000 0x000 0x00 0x000 +#define MX25_PAD_UPLL_BYPCLK__GPIO_3_16 0x210 0x000 0x000 0x05 0x000 #define MX25_PAD_VSTBY_REQ__VSTBY_REQ 0x214 0x408 0x000 0x00 0x000 #define MX25_PAD_VSTBY_REQ__AUD7_TXFS 0x214 0x408 0x000 0x04 0x000 #define MX25_PAD_VSTBY_REQ__GPIO_3_17 0x214 0x408 0x000 0x05 0x000 #define MX25_PAD_VSTBY_REQ__UART4_RTS 0x214 0x408 0x56c 0x06 0x002 -#define MX25_PAD_VSTBY_ACK__VSTBY_ACK 0x218 0x40c 0x000 0x10 0x000 -#define MX25_PAD_VSTBY_ACK__GPIO_3_18 0x218 0x40c 0x000 0x15 0x000 +#define MX25_PAD_VSTBY_ACK__VSTBY_ACK 0x218 0x40c 0x000 0x00 0x000 +#define MX25_PAD_VSTBY_ACK__GPIO_3_18 0x218 0x40c 0x000 0x05 0x000 -#define MX25_PAD_POWER_FAIL__POWER_FAIL 0x21c 0x410 0x000 0x10 0x000 -#define MX25_PAD_POWER_FAIL__AUD7_RXD 0x21c 0x410 0x478 0x14 0x001 -#define MX25_PAD_POWER_FAIL__GPIO_3_19 0x21c 0x410 0x000 0x15 0x000 -#define MX25_PAD_POWER_FAIL__UART4_CTS 0x21c 0x410 0x000 0x16 0x000 +#define MX25_PAD_POWER_FAIL__POWER_FAIL 0x21c 0x410 0x000 0x00 0x000 +#define MX25_PAD_POWER_FAIL__AUD7_RXD 0x21c 0x410 0x478 0x04 0x001 +#define MX25_PAD_POWER_FAIL__GPIO_3_19 0x21c 0x410 0x000 0x05 0x000 +#define MX25_PAD_POWER_FAIL__UART4_CTS 0x21c 0x410 0x000 0x06 0x000 -#define MX25_PAD_CLKO__CLKO 0x220 0x414 0x000 0x10 0x000 -#define MX25_PAD_CLKO__GPIO_2_21 0x220 0x414 0x000 0x15 0x000 +#define MX25_PAD_CLKO__CLKO 0x220 0x414 0x000 0x00 0x000 +#define MX25_PAD_CLKO__GPIO_2_21 0x220 0x414 0x000 0x05 0x000 #define MX25_PAD_BOOT_MODE0__BOOT_MODE0 0x224 0x000 0x000 0x00 0x000 #define MX25_PAD_BOOT_MODE0__GPIO_4_30 0x224 0x000 0x000 0x05 0x000 -- cgit v0.10.2 From de0fae60b35d405d3aa2e9acf5914770cd328338 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Sun, 12 Jun 2016 23:53:04 +0300 Subject: ARM: dts: r8a7792: add clock index macros Add macros usable by the device tree sources to reference the R8A7792 clocks by index. Signed-off-by: Sergei Shtylyov Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman diff --git a/include/dt-bindings/clock/r8a7792-clock.h b/include/dt-bindings/clock/r8a7792-clock.h new file mode 100644 index 0000000..949801e --- /dev/null +++ b/include/dt-bindings/clock/r8a7792-clock.h @@ -0,0 +1,102 @@ +/* + * Copyright (C) 2016 Cogent Embedded, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef __DT_BINDINGS_CLOCK_R8A7792_H__ +#define __DT_BINDINGS_CLOCK_R8A7792_H__ + +/* CPG */ +#define R8A7792_CLK_MAIN 0 +#define R8A7792_CLK_PLL0 1 +#define R8A7792_CLK_PLL1 2 +#define R8A7792_CLK_PLL3 3 +#define R8A7792_CLK_LB 4 +#define R8A7792_CLK_QSPI 5 +#define R8A7792_CLK_Z 6 +#define R8A7792_CLK_ADSP 7 + +/* MSTP0 */ +#define R8A7792_CLK_MSIOF0 0 + +/* MSTP1 */ +#define R8A7792_CLK_TMU1 11 +#define R8A7792_CLK_TMU3 21 +#define R8A7792_CLK_TMU2 22 +#define R8A7792_CLK_CMT0 24 +#define R8A7792_CLK_TMU0 25 +#define R8A7792_CLK_VSP1DU1 27 +#define R8A7792_CLK_VSP1DU0 28 +#define R8A7792_CLK_VSP1_SY 31 + +/* MSTP2 */ +#define R8A7792_CLK_MSIOF1 8 +#define R8A7792_CLK_SYS_DMAC1 18 +#define R8A7792_CLK_SYS_DMAC0 19 + +/* MSTP3 */ +#define R8A7792_CLK_TPU0 4 +#define R8A7792_CLK_SDHI0 14 +#define R8A7792_CLK_CMT1 29 + +/* MSTP4 */ +#define R8A7792_CLK_IRQC 7 + +/* MSTP5 */ +#define R8A7792_CLK_AUDIO_DMAC0 2 +#define R8A7792_CLK_THERMAL 22 +#define R8A7792_CLK_PWM 23 + +/* MSTP7 */ +#define R8A7792_CLK_HSCIF1 16 +#define R8A7792_CLK_HSCIF0 17 +#define R8A7792_CLK_SCIF3 18 +#define R8A7792_CLK_SCIF2 19 +#define R8A7792_CLK_SCIF1 20 +#define R8A7792_CLK_SCIF0 21 +#define R8A7792_CLK_DU1 23 +#define R8A7792_CLK_DU0 24 + +/* MSTP8 */ +#define R8A7792_CLK_VIN5 4 +#define R8A7792_CLK_VIN4 5 +#define R8A7792_CLK_VIN3 8 +#define R8A7792_CLK_VIN2 9 +#define R8A7792_CLK_VIN1 10 +#define R8A7792_CLK_VIN0 11 +#define R8A7792_CLK_ETHERAVB 12 + +/* MSTP9 */ +#define R8A7792_CLK_GPIO7 4 +#define R8A7792_CLK_GPIO6 5 +#define R8A7792_CLK_GPIO5 7 +#define R8A7792_CLK_GPIO4 8 +#define R8A7792_CLK_GPIO3 9 +#define R8A7792_CLK_GPIO2 10 +#define R8A7792_CLK_GPIO1 11 +#define R8A7792_CLK_GPIO0 12 +#define R8A7792_CLK_GPIO11 13 +#define R8A7792_CLK_GPIO10 14 +#define R8A7792_CLK_CAN1 15 +#define R8A7792_CLK_CAN0 16 +#define R8A7792_CLK_QSPI_MOD 17 +#define R8A7792_CLK_GPIO9 19 +#define R8A7792_CLK_GPIO8 21 +#define R8A7792_CLK_I2C5 25 +#define R8A7792_CLK_IICDVFS 26 +#define R8A7792_CLK_I2C4 27 +#define R8A7792_CLK_I2C3 28 +#define R8A7792_CLK_I2C2 29 +#define R8A7792_CLK_I2C1 30 +#define R8A7792_CLK_I2C0 31 + +/* MSTP10 */ +#define R8A7792_CLK_SSI_ALL 5 +#define R8A7792_CLK_SSI4 11 +#define R8A7792_CLK_SSI3 12 + +#endif /* __DT_BINDINGS_CLOCK_R8A7792_H__ */ -- cgit v0.10.2 From 5258bb5d980024dae22f4256329caec4fe5e98b3 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Sun, 12 Jun 2016 23:54:49 +0300 Subject: ARM: dts: r8a7792: add power domain index macros Add macros usable by the device tree sources to reference R8A7792 SYSC power domains by index. Signed-off-by: Sergei Shtylyov Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman diff --git a/include/dt-bindings/power/r8a7792-sysc.h b/include/dt-bindings/power/r8a7792-sysc.h new file mode 100644 index 0000000..74f4a78 --- /dev/null +++ b/include/dt-bindings/power/r8a7792-sysc.h @@ -0,0 +1,26 @@ +/* + * Copyright (C) 2016 Cogent Embedded Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + */ +#ifndef __DT_BINDINGS_POWER_R8A7792_SYSC_H__ +#define __DT_BINDINGS_POWER_R8A7792_SYSC_H__ + +/* + * These power domain indices match the numbers of the interrupt bits + * representing the power areas in the various Interrupt Registers + * (e.g. SYSCISR, Interrupt Status Register) + */ + +#define R8A7792_PD_CA15_CPU0 0 +#define R8A7792_PD_CA15_CPU1 1 +#define R8A7792_PD_CA15_SCU 12 +#define R8A7792_PD_SGX 20 +#define R8A7792_PD_IMP 24 + +/* Always-on power area */ +#define R8A7792_PD_ALWAYS_ON 32 + +#endif /* __DT_BINDINGS_POWER_R8A7792_SYSC_H__ */ -- cgit v0.10.2 From 7c4163aae3d8e5b9bd72508f542a44d707f308b5 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Mon, 13 Jun 2016 00:06:52 +0300 Subject: ARM: dts: r8a7792: initial SoC device tree The initial R8A7792 SoC device tree including CPU cores, GIC, timer, SYSC, and the required clock descriptions. Signed-off-by: Sergei Shtylyov Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi new file mode 100644 index 0000000..33f2362 --- /dev/null +++ b/arch/arm/boot/dts/r8a7792.dtsi @@ -0,0 +1,170 @@ +/* + * Device Tree Source for the r8a7792 SoC + * + * Copyright (C) 2016 Cogent Embedded Inc. + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +#include +#include +#include +#include + +/ { + compatible = "renesas,r8a7792"; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0>; + clock-frequency = <1000000000>; + clocks = <&cpg_clocks R8A7792_CLK_Z>; + power-domains = <&sysc R8A7792_PD_CA15_CPU0>; + next-level-cache = <&L2_CA15>; + }; + + L2_CA15: cache-controller@0 { + compatible = "cache"; + reg = <0>; + cache-unified; + cache-level = <2>; + power-domains = <&sysc R8A7792_PD_CA15_SCU>; + }; + }; + + soc { + compatible = "simple-bus"; + interrupt-parent = <&gic>; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gic: interrupt-controller@f1001000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0 0xf1001000 0 0x1000>, + <0 0xf1002000 0 0x1000>, + <0 0xf1004000 0 0x2000>, + <0 0xf1006000 0 0x2000>; + interrupts = ; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = , + , + , + ; + }; + + sysc: system-controller@e6180000 { + compatible = "renesas,r8a7792-sysc"; + reg = <0 0xe6180000 0 0x0200>; + #power-domain-cells = <1>; + }; + + /* Special CPG clocks */ + cpg_clocks: cpg_clocks@e6150000 { + compatible = "renesas,r8a7792-cpg-clocks", + "renesas,rcar-gen2-cpg-clocks"; + reg = <0 0xe6150000 0 0x1000>; + clocks = <&extal_clk>; + #clock-cells = <1>; + clock-output-names = "main", "pll0", "pll1", "pll3", + "lb", "qspi", "z", "adsp"; + #power-domain-cells = <0>; + }; + + /* Fixed factor clocks */ + zs_clk: zs { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7792_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <6>; + clock-mult = <1>; + }; + p_clk: p { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7792_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <24>; + clock-mult = <1>; + }; + cp_clk: cp { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7792_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <48>; + clock-mult = <1>; + }; + + /* Gate clocks */ + mstp2_clks: mstp2_clks@e6150138 { + compatible = "renesas,r8a7792-mstp-clocks", + "renesas,cpg-mstp-clocks"; + reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>; + clocks = <&zs_clk>, <&zs_clk>; + #clock-cells = <1>; + clock-indices = < + R8A7792_CLK_SYS_DMAC1 R8A7792_CLK_SYS_DMAC0 + >; + clock-output-names = "sys-dmac1", "sys-dmac0"; + }; + mstp4_clks: mstp4_clks@e6150140 { + compatible = "renesas,r8a7792-mstp-clocks", + "renesas,cpg-mstp-clocks"; + reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>; + clocks = <&cp_clk>; + #clock-cells = <1>; + clock-indices = ; + clock-output-names = "irqc"; + }; + mstp7_clks: mstp7_clks@e615014c { + compatible = "renesas,r8a7792-mstp-clocks", + "renesas,cpg-mstp-clocks"; + reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>; + clocks = <&zs_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, + <&p_clk>, <&p_clk>; + #clock-cells = <1>; + clock-indices = < + R8A7792_CLK_HSCIF1 R8A7792_CLK_HSCIF0 + R8A7792_CLK_SCIF3 R8A7792_CLK_SCIF2 + R8A7792_CLK_SCIF1 R8A7792_CLK_SCIF0 + >; + clock-output-names = "hscif1", "hscif0", "scif3", + "scif2", "scif1", "scif0"; + }; + }; + + /* External root clock */ + extal_clk: extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; + + /* External SCIF clock */ + scif_clk: scif { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; +}; -- cgit v0.10.2 From fdf8ec0a176ea29e7694ad0edd2cd34c820a3077 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Mon, 13 Jun 2016 00:08:18 +0300 Subject: ARM: dts: r8a7792: add SYS-DMAC support Describe SYS-DMAC0/1 in the R8A7792 device tree. Signed-off-by: Sergei Shtylyov Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi index 33f2362..6017ea5 100644 --- a/arch/arm/boot/dts/r8a7792.dtsi +++ b/arch/arm/boot/dts/r8a7792.dtsi @@ -79,6 +79,70 @@ #power-domain-cells = <1>; }; + dmac0: dma-controller@e6700000 { + compatible = "renesas,dmac-r8a7792", + "renesas,rcar-dmac"; + reg = <0 0xe6700000 0 0x20000>; + interrupts = ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14"; + clocks = <&mstp2_clks R8A7792_CLK_SYS_DMAC0>; + clock-names = "fck"; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + #dma-cells = <1>; + dma-channels = <15>; + }; + + dmac1: dma-controller@e6720000 { + compatible = "renesas,dmac-r8a7792", + "renesas,rcar-dmac"; + reg = <0 0xe6720000 0 0x20000>; + interrupts = ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14"; + clocks = <&mstp2_clks R8A7792_CLK_SYS_DMAC1>; + clock-names = "fck"; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + #dma-cells = <1>; + dma-channels = <15>; + }; + /* Special CPG clocks */ cpg_clocks: cpg_clocks@e6150000 { compatible = "renesas,r8a7792-cpg-clocks", -- cgit v0.10.2 From e66796b9bb87d2c48f68e5eb27dcfbc4c26c18d4 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Mon, 13 Jun 2016 00:09:42 +0300 Subject: ARM: dts: r8a7792: add [H]SCIF support Describe [H]SCIFs in the R8A7792 device tree. Signed-off-by: Sergei Shtylyov Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi index 6017ea5..b6e34b4 100644 --- a/arch/arm/boot/dts/r8a7792.dtsi +++ b/arch/arm/boot/dts/r8a7792.dtsi @@ -143,6 +143,96 @@ dma-channels = <15>; }; + scif0: serial@e6e60000 { + compatible = "renesas,scif-r8a7792", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6e60000 0 64>; + interrupts = ; + clocks = <&mstp7_clks R8A7792_CLK_SCIF0>, <&zs_clk>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x29>, <&dmac0 0x2a>, + <&dmac1 0x29>, <&dmac1 0x2a>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scif1: serial@e6e68000 { + compatible = "renesas,scif-r8a7792", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6e68000 0 64>; + interrupts = ; + clocks = <&mstp7_clks R8A7792_CLK_SCIF1>, <&zs_clk>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x2d>, <&dmac0 0x2e>, + <&dmac1 0x2d>, <&dmac1 0x2e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scif2: serial@e6e58000 { + compatible = "renesas,scif-r8a7792", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6e58000 0 64>; + interrupts = ; + clocks = <&mstp7_clks R8A7792_CLK_SCIF2>, <&zs_clk>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x2b>, <&dmac0 0x2c>, + <&dmac1 0x2b>, <&dmac1 0x2c>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scif3: serial@e6ea8000 { + compatible = "renesas,scif-r8a7792", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6ea8000 0 64>; + interrupts = ; + clocks = <&mstp7_clks R8A7792_CLK_SCIF3>, <&zs_clk>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x2f>, <&dmac0 0x30>, + <&dmac1 0x2f>, <&dmac1 0x30>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + status = "disabled"; + }; + + hscif0: serial@e62c0000 { + compatible = "renesas,hscif-r8a7792", + "renesas,rcar-gen2-hscif", "renesas,hscif"; + reg = <0 0xe62c0000 0 96>; + interrupts = ; + clocks = <&mstp7_clks R8A7792_CLK_HSCIF0>, <&zs_clk>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x39>, <&dmac0 0x3a>, + <&dmac1 0x39>, <&dmac1 0x3a>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + status = "disabled"; + }; + + hscif1: serial@e62c8000 { + compatible = "renesas,hscif-r8a7792", + "renesas,rcar-gen2-hscif", "renesas,hscif"; + reg = <0 0xe62c8000 0 96>; + interrupts = ; + clocks = <&mstp7_clks R8A7792_CLK_HSCIF1>, <&zs_clk>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x4d>, <&dmac0 0x4e>, + <&dmac1 0x4d>, <&dmac1 0x4e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + status = "disabled"; + }; + /* Special CPG clocks */ cpg_clocks: cpg_clocks@e6150000 { compatible = "renesas,r8a7792-cpg-clocks", -- cgit v0.10.2 From 56efdbe56bc674208d01e3afdfb47f6b5b90da3d Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Mon, 13 Jun 2016 00:12:06 +0300 Subject: ARM: dts: r8a7792: add IRQC support Describe the IRQC interrupt controller in the R8A7792 device tree. Signed-off-by: Sergei Shtylyov Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi index b6e34b4..18b4e50 100644 --- a/arch/arm/boot/dts/r8a7792.dtsi +++ b/arch/arm/boot/dts/r8a7792.dtsi @@ -61,6 +61,19 @@ IRQ_TYPE_LEVEL_HIGH)>; }; + irqc: interrupt-controller@e61c0000 { + compatible = "renesas,irqc-r8a7792", "renesas,irqc"; + #interrupt-cells = <2>; + interrupt-controller; + reg = <0 0xe61c0000 0 0x200>; + interrupts = , + , + , + ; + clocks = <&mstp4_clks R8A7792_CLK_IRQC>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + }; + timer { compatible = "arm,armv7-timer"; interrupts = Date: Mon, 13 Jun 2016 00:14:01 +0300 Subject: ARM: dts: blanche: document Blanche board Document the Blanche device tree bindings, listing it as a supported board. This allows to use checkpatch.pl to validate .dts files referring to the Blanche board. Signed-off-by: Sergei Shtylyov Acked-by: Rob Herring Signed-off-by: Simon Horman diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt b/Documentation/devicetree/bindings/arm/shmobile.txt index 9cf67e4..6adb9d5 100644 --- a/Documentation/devicetree/bindings/arm/shmobile.txt +++ b/Documentation/devicetree/bindings/arm/shmobile.txt @@ -39,6 +39,8 @@ Boards: compatible = "renesas,ape6evm", "renesas,r8a73a4" - Atmark Techno Armadillo-800 EVA compatible = "renesas,armadillo800eva" + - Blanche (RTP0RC7792SEB00010S) + compatible = "renesas,blanche", "renesas,r8a7792" - BOCK-W compatible = "renesas,bockw", "renesas,r8a7778" - Genmai (RTK772100BC00000BR) -- cgit v0.10.2 From 4018fba454602cc1d01a216352935d88582353f1 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Mon, 13 Jun 2016 00:15:55 +0300 Subject: ARM: dts: blanche: initial device tree Add the initial device tree for the R8A7792 SoC based Blanche board. The board has 2 debug serial ports: SCIF0 and SCIF3; include support for them, so that the serial console can work. Signed-off-by: Sergei Shtylyov Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 06b6c2d..91630d1 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -638,6 +638,7 @@ dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += \ r8a7790-lager.dtb \ r8a7791-koelsch.dtb \ r8a7791-porter.dtb \ + r8a7792-blanche.dtb \ r8a7793-gose.dtb \ r8a7794-alt.dtb \ r8a7794-silk.dtb \ diff --git a/arch/arm/boot/dts/r8a7792-blanche.dts b/arch/arm/boot/dts/r8a7792-blanche.dts new file mode 100644 index 0000000..e277d92 --- /dev/null +++ b/arch/arm/boot/dts/r8a7792-blanche.dts @@ -0,0 +1,45 @@ +/* + * Device Tree Source for the Blanche board + * + * Copyright (C) 2014 Renesas Electronics Corporation + * Copyright (C) 2016 Cogent Embedded, Inc. + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +/dts-v1/; +#include "r8a7792.dtsi" + +/ { + model = "Blanche"; + compatible = "renesas,blanche", "renesas,r8a7792"; + + aliases { + serial0 = &scif0; + serial1 = &scif3; + }; + + chosen { + bootargs = "ignore_loglevel"; + stdout-path = "serial0:115200n8"; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0 0x40000000 0 0x40000000>; + }; +}; + +&extal_clk { + clock-frequency = <20000000>; +}; + +&scif0 { + status = "okay"; +}; + +&scif3 { + status = "okay"; +}; -- cgit v0.10.2 From f80b6dfd5e56f3908832ce89f96ae94352b616c2 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Mon, 13 Jun 2016 00:17:11 +0300 Subject: ARM: dts: blanche: add Ethernet support R8A7792 SoC doesn't have the EtherMAC core, so SMSC LAN89218 Ethernet chip was used instead on the Blanche board; this chip is compatible with SMSC LAN9115 for which there's a (device tree aware) driver. Describe the chip in the Blanche device tree; enable DHCP and NFS root in the kernel command line for the kernel booting. Signed-off-by: Sergei Shtylyov Signed-off-by: Simon Horman diff --git a/arch/arm/boot/dts/r8a7792-blanche.dts b/arch/arm/boot/dts/r8a7792-blanche.dts index e277d92..e7b40f0 100644 --- a/arch/arm/boot/dts/r8a7792-blanche.dts +++ b/arch/arm/boot/dts/r8a7792-blanche.dts @@ -22,7 +22,7 @@ }; chosen { - bootargs = "ignore_loglevel"; + bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp"; stdout-path = "serial0:115200n8"; }; @@ -30,6 +30,27 @@ device_type = "memory"; reg = <0 0x40000000 0 0x40000000>; }; + + d3_3v: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "D3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ethernet@18000000 { + compatible = "smsc,lan89218", "smsc,lan9115"; + reg = <0 0x18000000 0 0x100>; + phy-mode = "mii"; + interrupt-parent = <&irqc>; + interrupts = <0 IRQ_TYPE_EDGE_FALLING>; + smsc,irq-push-pull; + reg-io-width = <4>; + vddvario-supply = <&d3_3v>; + vdd33a-supply = <&d3_3v>; + }; }; &extal_clk { -- cgit v0.10.2 From 74332d75763e2d2b875fa84b7b98794cb1f74868 Mon Sep 17 00:00:00 2001 From: Peter Chen Date: Tue, 7 Jun 2016 17:39:25 +0800 Subject: ARM: dts: imx6qdl.dtsi: add "arm,shared-override" for pl310 The imx6 SMP system has the same DMA memory coherency issue [1] with pl310 L2 controller. With this shared override bit set, the customer reports the DMA coherency issue is gone. Besides, I have tested the performance using USB ethernet with/without this bit, it shows no difference. [1] http://patchwork.ozlabs.org/patch/469362/ Signed-off-by: Peter Chen Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi index b20096f..b620ac8 100644 --- a/arch/arm/boot/dts/imx6qdl.dtsi +++ b/arch/arm/boot/dts/imx6qdl.dtsi @@ -185,6 +185,7 @@ cache-level = <2>; arm,tag-latency = <4 2 3>; arm,data-latency = <4 2 3>; + arm,shared-override; }; pcie: pcie@0x01000000 { -- cgit v0.10.2 From 5bca20f7fe003c65009b4d49cd13630827dae691 Mon Sep 17 00:00:00 2001 From: Valentin Raevsky Date: Mon, 13 Jun 2016 01:24:55 +0200 Subject: ARM: dts: imx6q-cm-fx6: fix the operation points The current ldo settings of the cm-fx6 do not allow 1.2GHz cpu frequency. At this frequency the module behaves unstable. But the imx6q fuse indicates that 1.2GHz operation is possible. Hence, remove the 1.2GHz operation point in the device tree. Signed-off-by: Valentin Raevsky [christopher.spinrath@rwth-aachen.de: enhance commit message, adjust remaining operation points to match the ones in imx6q.dtsi and add a comment in the device tree] Signed-off-by: Christopher Spinrath Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/imx6q-cm-fx6.dts b/arch/arm/boot/dts/imx6q-cm-fx6.dts index 6d8d5e9..b5de7e6 100644 --- a/arch/arm/boot/dts/imx6q-cm-fx6.dts +++ b/arch/arm/boot/dts/imx6q-cm-fx6.dts @@ -91,6 +91,28 @@ }; }; +&cpu0 { + /* + * Although the imx6q fuse indicates that 1.2GHz operation is possible, + * the module behaves unstable at this frequency. Hence, remove the + * 1.2GHz operation point here. + */ + operating-points = < + /* kHz uV */ + 996000 1250000 + 852000 1250000 + 792000 1175000 + 396000 975000 + >; + fsl,soc-operating-points = < + /* ARM kHz SOC-PU uV */ + 996000 1250000 + 852000 1250000 + 792000 1175000 + 396000 1175000 + >; +}; + &ecspi1 { fsl,spi-num-chipselects = <2>; cs-gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>, <&gpio3 19 GPIO_ACTIVE_HIGH>; -- cgit v0.10.2 From 3cfb411a64b7517bd2039e4d79da27b97179bece Mon Sep 17 00:00:00 2001 From: Christopher Spinrath Date: Mon, 13 Jun 2016 01:24:56 +0200 Subject: ARM: dts: utilite-pro: add mmc card slot support The Utilite Pro has a mmc card slot connected to the usdhc3 controller. There is no card detection until hardware revision 1.3. Add support for it and signal the controller with the broken-cd property that polling has to be used to detect a card. Signed-off-by: Christopher Spinrath Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/imx6q-utilite-pro.dts b/arch/arm/boot/dts/imx6q-utilite-pro.dts index 7219745..6199063 100644 --- a/arch/arm/boot/dts/imx6q-utilite-pro.dts +++ b/arch/arm/boot/dts/imx6q-utilite-pro.dts @@ -130,6 +130,39 @@ MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b1 >; }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3grp-100mhz { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170B9 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100B9 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170B9 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170B9 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170B9 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170B9 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3grp-200mhz { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170F9 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100F9 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170F9 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170F9 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170F9 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170F9 + >; + }; }; &pcie { @@ -151,3 +184,14 @@ uart-has-rtscts; status = "okay"; }; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + no-1-8-v; + broken-cd; + keep-power-in-suspend; + status = "okay"; +}; -- cgit v0.10.2 From 49607ff7a659ae3a78184255a522c0f48f1c705d Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 13 Jun 2016 22:07:56 -0300 Subject: ARM: dts: imx6qdl-sabresd: Use WDOG_B pin reset imx6qdl-sabresd has WDOG2_B pin connected to the PMIC. Pass the 'fsl,ext-reset-output' property so that the watchdog can trigger a system POR reset via the PMIC. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi index bea707f..d77ea94 100644 --- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi @@ -501,6 +501,12 @@ MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 >; }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__WDOG2_B 0x1b0b0 + >; + }; }; gpio_leds { @@ -596,3 +602,14 @@ no-1-8-v; status = "okay"; }; + +&wdog1 { + status = "disabled"; +}; + +&wdog2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; -- cgit v0.10.2 From 51fd03233d1ca6b7ef9a1b4c31c17ebc4aa005cf Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 13 Jun 2016 22:07:57 -0300 Subject: ARM: dts: imx7d-sdb: Use WDOG_B pin reset imx7d-sdb has WDOG1_B pin connected to the PMIC. Pass the 'fsl,ext-reset-output' property so that the watchdog can trigger a system POR reset via the PMIC. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/imx7d-sdb.dts b/arch/arm/boot/dts/imx7d-sdb.dts index b267f79..d6da506 100644 --- a/arch/arm/boot/dts/imx7d-sdb.dts +++ b/arch/arm/boot/dts/imx7d-sdb.dts @@ -314,6 +314,12 @@ status = "okay"; }; +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; +}; + &iomuxc { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_hog>; @@ -512,5 +518,10 @@ >; }; + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX7D_PAD_GPIO1_IO00__WDOD1_WDOG_B 0x74 + >; + }; }; }; -- cgit v0.10.2 From 50e0299809c4211b74013095b6970527a11587d8 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 13 Jun 2016 22:07:58 -0300 Subject: ARM: dts: imx6ul-evk: Use WDOG_B pin reset imx6ul-evk has WDOG1_B pin connected to the PMIC. Pass the 'fsl,ext-reset-output' property so that the watchdog can trigger a system POR reset via the PMIC. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/imx6ul-14x14-evk.dts b/arch/arm/boot/dts/imx6ul-14x14-evk.dts index bfe9fb4..e281d50 100644 --- a/arch/arm/boot/dts/imx6ul-14x14-evk.dts +++ b/arch/arm/boot/dts/imx6ul-14x14-evk.dts @@ -256,6 +256,12 @@ status = "okay"; }; +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; +}; + &iomuxc { pinctrl-names = "default"; @@ -484,4 +490,10 @@ MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 >; }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0 + >; + }; }; -- cgit v0.10.2 From 8c4a18e232851dda93e3308c5d69595c18524c89 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 13 Jun 2016 22:07:59 -0300 Subject: ARM: dts: imx6sx-sdb: Use WDOG_B pin reset imx6sx-sdb has WDOG1_B pin connected to the PMIC. Pass the 'fsl,ext-reset-output' property so that the watchdog can trigger a system POR reset via the PMIC. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/imx6sx-sdb.dtsi b/arch/arm/boot/dts/imx6sx-sdb.dtsi index fcbaccf..9d70cfd 100644 --- a/arch/arm/boot/dts/imx6sx-sdb.dtsi +++ b/arch/arm/boot/dts/imx6sx-sdb.dtsi @@ -322,6 +322,12 @@ status = "okay"; }; +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; +}; + &iomuxc { imx6x-sdb { pinctrl_audmux: audmuxgrp { @@ -588,5 +594,11 @@ MX6SX_PAD_SD4_DATA6__GPIO6_IO_20 0x17059 /* WP */ >; }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6SX_PAD_GPIO1_IO13__WDOG1_WDOG_ANY 0x30b0 + >; + }; }; }; -- cgit v0.10.2 From 771db6c8ba944dca225e9ef507cc917ace7a87c1 Mon Sep 17 00:00:00 2001 From: Soeren Moch Date: Tue, 14 Jun 2016 23:08:32 +0200 Subject: ARM: dts: imx6q-tbs2910: fix pcie reset polarity According to Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt the polarity of "reset-gpio" is assumed to be active-low unless a separate property "reset-gpio-active-high" is available. So replace the inconsistent polarity description to make the correct active-low reset behavior more obvious. Signed-off-by: Soeren Moch Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/imx6q-tbs2910.dts b/arch/arm/boot/dts/imx6q-tbs2910.dts index 1926b13..d7c8ccb 100644 --- a/arch/arm/boot/dts/imx6q-tbs2910.dts +++ b/arch/arm/boot/dts/imx6q-tbs2910.dts @@ -191,7 +191,7 @@ &pcie { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pcie>; - reset-gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>; + reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>; status = "okay"; }; -- cgit v0.10.2 From 6b75a66b6e04e30c0d2c2183b3632a891bffd7bf Mon Sep 17 00:00:00 2001 From: Diego Dorta Date: Wed, 15 Jun 2016 13:34:41 -0300 Subject: ARM: dts: imx6ul-pico-hobbit: Fix Ethernet PHY reset GPIO MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit According to the imx6ul-pico-hobbit schematics the Ethernet PHY reset GPIO is GPIO1_28, so fix it accordingly. Also adjust the reset duration to 1ms, because the KSZ8081 datasheet requires 500μs. Signed-off-by: Diego Dorta Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/imx6ul-pico-hobbit.dts b/arch/arm/boot/dts/imx6ul-pico-hobbit.dts index e5bff4b..86f68fa 100644 --- a/arch/arm/boot/dts/imx6ul-pico-hobbit.dts +++ b/arch/arm/boot/dts/imx6ul-pico-hobbit.dts @@ -151,8 +151,8 @@ phy-mode = "rmii"; phy-handle = <ðphy1>; status = "okay"; - phy-reset-gpios = <&gpio2 15 GPIO_ACTIVE_LOW>; - phy-reset-duration = <11>; + phy-reset-gpios = <&gpio1 28 GPIO_ACTIVE_LOW>; + phy-reset-duration = <1>; mdio { #address-cells = <1>; -- cgit v0.10.2 From f03a881a8a8de26b09949b89d6a7177afbc5754d Mon Sep 17 00:00:00 2001 From: Enric Balletbo i Serra Date: Fri, 17 Jun 2016 13:10:10 +0200 Subject: ARM: dts: am335x-bone-common: use stdout-path in Beaglebone boards. This commit adds the stdout-path propety in /chosen for all Beaglebone boards. Signed-off-by: Enric Balletbo i Serra Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/am335x-bone-common.dtsi b/arch/arm/boot/dts/am335x-bone-common.dtsi index 6b06096..e247c15 100644 --- a/arch/arm/boot/dts/am335x-bone-common.dtsi +++ b/arch/arm/boot/dts/am335x-bone-common.dtsi @@ -18,6 +18,10 @@ reg = <0x80000000 0x10000000>; /* 256 MB */ }; + chosen { + stdout-path = &uart0; + }; + leds { pinctrl-names = "default"; pinctrl-0 = <&user_leds_s0>; -- cgit v0.10.2 From bac9d0b847a18ff9a0bb77711a8ad1db7400a948 Mon Sep 17 00:00:00 2001 From: Joel Fernandes Date: Wed, 1 Jun 2016 12:06:41 +0300 Subject: ARM: dts: DRA7: Add DT node for DES IP DRA7xx SoCs have a DES3DES IP. Add DT data for the same. Signed-off-by: Joel Fernandes Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index 3c34a0c..f5a83c4 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -1928,6 +1928,17 @@ status = "disabled"; }; }; + + des: des@480a5000 { + compatible = "ti,omap4-des"; + ti,hwmods = "des"; + reg = <0x480a5000 0xa0>; + interrupts = ; + dmas = <&sdma_xbar 117>, <&sdma_xbar 116>; + dma-names = "tx", "rx"; + clocks = <&l3_iclk_div>; + clock-names = "fck"; + }; }; thermal_zones: thermal-zones { -- cgit v0.10.2 From e7fd15c1d0580e1c5b35f808d064e5460bdaa7fc Mon Sep 17 00:00:00 2001 From: Joel Fernandes Date: Wed, 1 Jun 2016 12:06:42 +0300 Subject: ARM: dts: DRA7: Add DT nodes for AES IP DRA7 SoC has the same AES IP as OMAP4. Add DT entries for both AES cores. Signed-off-by: Joel Fernandes Signed-off-by: Lokesh Vutla [t-kristo@ti.com: squashed in the change to use EDMA, squashed in support for two AES cores] Signed-off-by: Tero Kristo Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index f5a83c4..1809096 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -1929,6 +1929,28 @@ }; }; + aes1: aes@4b500000 { + compatible = "ti,omap4-aes"; + ti,hwmods = "aes1"; + reg = <0x4b500000 0xa0>; + interrupts = ; + dmas = <&edma_xbar 111 0>, <&edma_xbar 110 0>; + dma-names = "tx", "rx"; + clocks = <&l3_iclk_div>; + clock-names = "fck"; + }; + + aes2: aes@4b700000 { + compatible = "ti,omap4-aes"; + ti,hwmods = "aes2"; + reg = <0x4b700000 0xa0>; + interrupts = ; + dmas = <&edma_xbar 114 0>, <&edma_xbar 113 0>; + dma-names = "tx", "rx"; + clocks = <&l3_iclk_div>; + clock-names = "fck"; + }; + des: des@480a5000 { compatible = "ti,omap4-des"; ti,hwmods = "des"; -- cgit v0.10.2 From da34609df5bc4cfac28154970d9191fbcac17fab Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Wed, 1 Jun 2016 12:06:43 +0300 Subject: ARM: dts: DRA7: Add support for SHA IP DRA7 SoC has the same SHA IP as OMAP5. Add DT entry for the same. Signed-off-by: Lokesh Vutla [t-kristo@ti.com: changed SHA to use EDMA instead of SDMA] Signed-off-by: Tero Kristo Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index 1809096..b603e92 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -1961,6 +1961,17 @@ clocks = <&l3_iclk_div>; clock-names = "fck"; }; + + sham: sham@53100000 { + compatible = "ti,omap5-sham"; + ti,hwmods = "sham"; + reg = <0x4b101000 0x300>; + interrupts = ; + dmas = <&edma_xbar 119 0>; + dma-names = "rx"; + clocks = <&l3_iclk_div>; + clock-names = "fck"; + }; }; thermal_zones: thermal-zones { -- cgit v0.10.2 From 610e9c4aec6acdb44230e9bd96d12393650333ff Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Wed, 1 Jun 2016 12:06:44 +0300 Subject: ARM: dts: DRA7: Add DT node for RNG IP Adding dt node for hardware random number generator IP. Signed-off-by: Lokesh Vutla Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index b603e92..60680a1 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -1972,6 +1972,15 @@ clocks = <&l3_iclk_div>; clock-names = "fck"; }; + + rng: rng@48090000 { + compatible = "ti,omap4-rng"; + ti,hwmods = "rng"; + reg = <0x48090000 0x2000>; + interrupts = ; + clocks = <&l3_iclk_div>; + clock-names = "fck"; + }; }; thermal_zones: thermal-zones { -- cgit v0.10.2 From 8ed607a7490172733936a50a2231509dbde4f3b9 Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Wed, 1 Jun 2016 12:06:45 +0300 Subject: ARM: dts: AM43xx: clk: Add RNG clk node Add clk node for RNG module. Signed-off-by: Lokesh Vutla Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/am43xx-clocks.dtsi b/arch/arm/boot/dts/am43xx-clocks.dtsi index 7630ba1..d1d73b7 100644 --- a/arch/arm/boot/dts/am43xx-clocks.dtsi +++ b/arch/arm/boot/dts/am43xx-clocks.dtsi @@ -104,6 +104,14 @@ clock-div = <1>; }; + rng_fck: rng_fck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&sys_clkin_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + ehrpwm0_tbclk: ehrpwm0_tbclk@664 { #clock-cells = <0>; compatible = "ti,gate-clock"; diff --git a/drivers/clk/ti/clk-43xx.c b/drivers/clk/ti/clk-43xx.c index 097fc90..3f157a4 100644 --- a/drivers/clk/ti/clk-43xx.c +++ b/drivers/clk/ti/clk-43xx.c @@ -58,6 +58,7 @@ static struct ti_dt_clk am43xx_clks[] = { DT_CLK(NULL, "smartreflex1_fck", "smartreflex1_fck"), DT_CLK(NULL, "sha0_fck", "sha0_fck"), DT_CLK(NULL, "aes0_fck", "aes0_fck"), + DT_CLK(NULL, "rng_fck", "rng_fck"), DT_CLK(NULL, "timer1_fck", "timer1_fck"), DT_CLK(NULL, "timer2_fck", "timer2_fck"), DT_CLK(NULL, "timer3_fck", "timer3_fck"), -- cgit v0.10.2 From 52c7c91319e469142628199548852198bcc3150f Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Wed, 1 Jun 2016 12:06:46 +0300 Subject: ARM: dts: AM43xx: Add node for RNG Adding DT node for hardware random number generator. Signed-off-by: Lokesh Vutla Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi index 0351466..e7b53ef 100644 --- a/arch/arm/boot/dts/am4372.dtsi +++ b/arch/arm/boot/dts/am4372.dtsi @@ -909,6 +909,13 @@ dma-names = "tx", "rx"; }; + rng: rng@48310000 { + compatible = "ti,omap4-rng"; + ti,hwmods = "rng"; + reg = <0x48310000 0x2000>; + interrupts = ; + }; + mcasp0: mcasp@48038000 { compatible = "ti,am33xx-mcasp-audio"; ti,hwmods = "mcasp0"; -- cgit v0.10.2 From adc47ecf5a8d35f8060c88ac818cd5404268f3ed Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Wed, 13 Apr 2016 22:36:21 +0300 Subject: ARM: dts: silk: add DU pins Add the (previously omitted) DU pin data to the SILK board's device tree. Signed-off-by: Sergei Shtylyov Signed-off-by: Simon Horman diff --git a/arch/arm/boot/dts/r8a7794-silk.dts b/arch/arm/boot/dts/r8a7794-silk.dts index 488de73..cf24f45 100644 --- a/arch/arm/boot/dts/r8a7794-silk.dts +++ b/arch/arm/boot/dts/r8a7794-silk.dts @@ -183,6 +183,16 @@ groups = "usb1"; function = "usb1"; }; + + du0_pins: du0 { + groups = "du0_rgb888", "du0_sync", "du0_disp", "du0_clk0_out"; + function = "du0"; + }; + + du1_pins: du1 { + groups = "du1_rgb666", "du1_sync", "du1_disp", "du1_clk0_out"; + function = "du1"; + }; }; &scif2 { @@ -360,6 +370,8 @@ }; &du { + pinctrl-0 = <&du0_pins &du1_pins>; + pinctrl-names = "default"; status = "okay"; clocks = <&mstp7_clks R8A7794_CLK_DU0>, -- cgit v0.10.2 From eebc8e2c5b7a3db19075a02730db8b73be933485 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Fri, 17 Jun 2016 01:02:48 +0300 Subject: ARM: dts: r8a7792: add JPU clocks Add JPU clock and its parent, M2 clock to the R8A7792 device tree. Signed-off-by: Sergei Shtylyov Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi index 18b4e50..7077c5d 100644 --- a/arch/arm/boot/dts/r8a7792.dtsi +++ b/arch/arm/boot/dts/r8a7792.dtsi @@ -280,8 +280,24 @@ clock-div = <48>; clock-mult = <1>; }; + m2_clk: m2 { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7792_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <8>; + clock-mult = <1>; + }; /* Gate clocks */ + mstp1_clks: mstp1_clks@e6150134 { + compatible = "renesas,r8a7792-mstp-clocks", + "renesas,cpg-mstp-clocks"; + reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>; + clocks = <&m2_clk>; + #clock-cells = <1>; + clock-indices = ; + clock-output-names = "jpu"; + }; mstp2_clks: mstp2_clks@e6150138 { compatible = "renesas,r8a7792-mstp-clocks", "renesas,cpg-mstp-clocks"; diff --git a/include/dt-bindings/clock/r8a7792-clock.h b/include/dt-bindings/clock/r8a7792-clock.h index 949801e..89a5155 100644 --- a/include/dt-bindings/clock/r8a7792-clock.h +++ b/include/dt-bindings/clock/r8a7792-clock.h @@ -24,6 +24,7 @@ #define R8A7792_CLK_MSIOF0 0 /* MSTP1 */ +#define R8A7792_CLK_JPU 6 #define R8A7792_CLK_TMU1 11 #define R8A7792_CLK_TMU3 21 #define R8A7792_CLK_TMU2 22 -- cgit v0.10.2 From 3e1839e91dfcb50cf5c1c9a7ac2ed61891400b92 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Fri, 17 Jun 2016 01:03:53 +0300 Subject: ARM: dts: r8a7792: add JPU support Describe JPEG Processing Unit (JPU) in the R8A7792 device tree. Signed-off-by: Sergei Shtylyov Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi index 7077c5d..ad895f8 100644 --- a/arch/arm/boot/dts/r8a7792.dtsi +++ b/arch/arm/boot/dts/r8a7792.dtsi @@ -246,6 +246,15 @@ status = "disabled"; }; + jpu: jpeg-codec@fe980000 { + compatible = "renesas,jpu-r8a7792", + "renesas,rcar-gen2-jpu"; + reg = <0 0xfe980000 0 0x10300>; + interrupts = ; + clocks = <&mstp1_clks R8A7792_CLK_JPU>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + }; + /* Special CPG clocks */ cpg_clocks: cpg_clocks@e6150000 { compatible = "renesas,r8a7792-cpg-clocks", -- cgit v0.10.2 From 36e55669ebdef9eaf3f4ab4e82a07bb4b95a4813 Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Wed, 22 Jun 2016 17:27:03 -0700 Subject: ARM: dts: BCM5301x: Add RNG Device Tree node Add the DT node for the random number generator peripheral. Acked-by: Scott Branden Signed-off-by: Florian Fainelli diff --git a/arch/arm/boot/dts/bcm5301x.dtsi b/arch/arm/boot/dts/bcm5301x.dtsi index a20ebd2..8af4791 100644 --- a/arch/arm/boot/dts/bcm5301x.dtsi +++ b/arch/arm/boot/dts/bcm5301x.dtsi @@ -302,6 +302,11 @@ /* ports are defined in board DTS */ }; + rng: rng@18004000 { + compatible = "brcm,bcm5301x-rng"; + reg = <0x18004000 0x14>; + }; + nand: nand@18028000 { compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1", "brcm,brcmnand"; reg = <0x18028000 0x600>, <0x1811a408 0x600>, <0x18028f00 0x20>; -- cgit v0.10.2 From 8372d93df7c265a67676dcd329da9588cc769192 Mon Sep 17 00:00:00 2001 From: Xing Zheng Date: Wed, 22 Jun 2016 11:16:50 +0800 Subject: ARM: dts: rockchip: rename rk3228.dtsi to rk322x.dtsi We have the brother chipset that RK3228 and RK3229, they share most of dts configuration, but there are a number of different features. In order to develop the future when they are easy to distinguish, we need them to be independent. Signed-off-by: Xing Zheng Signed-off-by: Heiko Stuebner diff --git a/arch/arm/boot/dts/rk3228-evb.dts b/arch/arm/boot/dts/rk3228-evb.dts index 5956e82..904668e 100644 --- a/arch/arm/boot/dts/rk3228-evb.dts +++ b/arch/arm/boot/dts/rk3228-evb.dts @@ -40,7 +40,7 @@ /dts-v1/; -#include "rk3228.dtsi" +#include "rk322x.dtsi" / { model = "Rockchip RK3228 Evaluation board"; diff --git a/arch/arm/boot/dts/rk3228.dtsi b/arch/arm/boot/dts/rk3228.dtsi deleted file mode 100644 index e23a22e..0000000 --- a/arch/arm/boot/dts/rk3228.dtsi +++ /dev/null @@ -1,591 +0,0 @@ -/* - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include -#include -#include -#include -#include -#include -#include "skeleton.dtsi" - -/ { - compatible = "rockchip,rk3228"; - - interrupt-parent = <&gic>; - - aliases { - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@f00 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0xf00>; - resets = <&cru SRST_CORE0>; - operating-points = < - /* KHz uV */ - 816000 1000000 - >; - #cooling-cells = <2>; /* min followed by max */ - clock-latency = <40000>; - clocks = <&cru ARMCLK>; - }; - - cpu1: cpu@f01 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0xf01>; - resets = <&cru SRST_CORE1>; - }; - - cpu2: cpu@f02 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0xf02>; - resets = <&cru SRST_CORE2>; - }; - - cpu3: cpu@f03 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0xf03>; - resets = <&cru SRST_CORE3>; - }; - }; - - amba { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - pdma: pdma@110f0000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x110f0000 0x4000>; - interrupts = , - ; - #dma-cells = <1>; - clocks = <&cru ACLK_DMAC>; - clock-names = "apb_pclk"; - }; - }; - - arm-pmu { - compatible = "arm,cortex-a7-pmu"; - interrupts = , - , - , - ; - interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; - }; - - timer { - compatible = "arm,armv7-timer"; - arm,cpu-registers-not-fw-configured; - interrupts = , - , - , - ; - clock-frequency = <24000000>; - }; - - xin24m: oscillator { - compatible = "fixed-clock"; - clock-frequency = <24000000>; - clock-output-names = "xin24m"; - #clock-cells = <0>; - }; - - grf: syscon@11000000 { - compatible = "syscon"; - reg = <0x11000000 0x1000>; - }; - - uart0: serial@11010000 { - compatible = "snps,dw-apb-uart"; - reg = <0x11010000 0x100>; - interrupts = ; - clock-frequency = <24000000>; - clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; - clock-names = "baudclk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - uart1: serial@11020000 { - compatible = "snps,dw-apb-uart"; - reg = <0x11020000 0x100>; - interrupts = ; - clock-frequency = <24000000>; - clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; - clock-names = "baudclk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&uart1_xfer>; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - uart2: serial@11030000 { - compatible = "snps,dw-apb-uart"; - reg = <0x11030000 0x100>; - interrupts = ; - clock-frequency = <24000000>; - clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; - clock-names = "baudclk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&uart2_xfer>; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - i2c0: i2c@11050000 { - compatible = "rockchip,rk3228-i2c"; - reg = <0x11050000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "i2c"; - clocks = <&cru PCLK_I2C0>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_xfer>; - status = "disabled"; - }; - - i2c1: i2c@11060000 { - compatible = "rockchip,rk3228-i2c"; - reg = <0x11060000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "i2c"; - clocks = <&cru PCLK_I2C1>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_xfer>; - status = "disabled"; - }; - - i2c2: i2c@11070000 { - compatible = "rockchip,rk3228-i2c"; - reg = <0x11070000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "i2c"; - clocks = <&cru PCLK_I2C2>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_xfer>; - status = "disabled"; - }; - - i2c3: i2c@11080000 { - compatible = "rockchip,rk3228-i2c"; - reg = <0x11080000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "i2c"; - clocks = <&cru PCLK_I2C3>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_xfer>; - status = "disabled"; - }; - - pwm0: pwm@110b0000 { - compatible = "rockchip,rk3288-pwm"; - reg = <0x110b0000 0x10>; - #pwm-cells = <3>; - clocks = <&cru PCLK_PWM>; - clock-names = "pwm"; - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_pin>; - status = "disabled"; - }; - - pwm1: pwm@110b0010 { - compatible = "rockchip,rk3288-pwm"; - reg = <0x110b0010 0x10>; - #pwm-cells = <3>; - clocks = <&cru PCLK_PWM>; - clock-names = "pwm"; - pinctrl-names = "default"; - pinctrl-0 = <&pwm1_pin>; - status = "disabled"; - }; - - pwm2: pwm@110b0020 { - compatible = "rockchip,rk3288-pwm"; - reg = <0x110b0020 0x10>; - #pwm-cells = <3>; - clocks = <&cru PCLK_PWM>; - clock-names = "pwm"; - pinctrl-names = "default"; - pinctrl-0 = <&pwm2_pin>; - status = "disabled"; - }; - - pwm3: pwm@110b0030 { - compatible = "rockchip,rk3288-pwm"; - reg = <0x110b0030 0x10>; - #pwm-cells = <2>; - clocks = <&cru PCLK_PWM>; - clock-names = "pwm"; - pinctrl-names = "default"; - pinctrl-0 = <&pwm3_pin>; - status = "disabled"; - }; - - timer: timer@110c0000 { - compatible = "rockchip,rk3288-timer"; - reg = <0x110c0000 0x20>; - interrupts = ; - clocks = <&xin24m>, <&cru PCLK_TIMER>; - clock-names = "timer", "pclk"; - }; - - cru: clock-controller@110e0000 { - compatible = "rockchip,rk3228-cru"; - reg = <0x110e0000 0x1000>; - rockchip,grf = <&grf>; - #clock-cells = <1>; - #reset-cells = <1>; - assigned-clocks = <&cru PLL_GPLL>; - assigned-clock-rates = <594000000>; - }; - - thermal-zones { - cpu_thermal: cpu-thermal { - polling-delay-passive = <100>; /* milliseconds */ - polling-delay = <5000>; /* milliseconds */ - - thermal-sensors = <&tsadc 0>; - - trips { - cpu_alert0: cpu_alert0 { - temperature = <70000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - cpu_alert1: cpu_alert1 { - temperature = <75000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - cpu_crit: cpu_crit { - temperature = <90000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu_alert0>; - cooling-device = - <&cpu0 THERMAL_NO_LIMIT 6>; - }; - map1 { - trip = <&cpu_alert1>; - cooling-device = - <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - }; - - tsadc: tsadc@11150000 { - compatible = "rockchip,rk3228-tsadc"; - reg = <0x11150000 0x100>; - interrupts = ; - clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; - clock-names = "tsadc", "apb_pclk"; - resets = <&cru SRST_TSADC>; - reset-names = "tsadc-apb"; - pinctrl-names = "init", "default", "sleep"; - pinctrl-0 = <&otp_gpio>; - pinctrl-1 = <&otp_out>; - pinctrl-2 = <&otp_gpio>; - #thermal-sensor-cells = <0>; - rockchip,hw-tshut-temp = <95000>; - status = "disabled"; - }; - - emmc: dwmmc@30020000 { - compatible = "rockchip,rk3288-dw-mshc"; - reg = <0x30020000 0x4000>; - interrupts = ; - clock-frequency = <37500000>; - clock-freq-min-max = <400000 37500000>; - clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, - <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; - clock-names = "biu", "ciu", "ciu_drv", "ciu_sample"; - bus-width = <8>; - default-sample-phase = <158>; - num-slots = <1>; - fifo-depth = <0x100>; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; - status = "disabled"; - }; - - gic: interrupt-controller@32010000 { - compatible = "arm,gic-400"; - interrupt-controller; - #interrupt-cells = <3>; - #address-cells = <0>; - - reg = <0x32011000 0x1000>, - <0x32012000 0x1000>, - <0x32014000 0x2000>, - <0x32016000 0x2000>; - interrupts = ; - }; - - pinctrl: pinctrl { - compatible = "rockchip,rk3228-pinctrl"; - rockchip,grf = <&grf>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - gpio0: gpio0@11110000 { - compatible = "rockchip,gpio-bank"; - reg = <0x11110000 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO0>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio1: gpio1@11120000 { - compatible = "rockchip,gpio-bank"; - reg = <0x11120000 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO1>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio2@11130000 { - compatible = "rockchip,gpio-bank"; - reg = <0x11130000 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO2>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio3: gpio3@11140000 { - compatible = "rockchip,gpio-bank"; - reg = <0x11140000 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO3>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - pcfg_pull_up: pcfg-pull-up { - bias-pull-up; - }; - - pcfg_pull_down: pcfg-pull-down { - bias-pull-down; - }; - - pcfg_pull_none: pcfg-pull-none { - bias-disable; - }; - - emmc { - emmc_clk: emmc-clk { - rockchip,pins = <2 7 RK_FUNC_2 &pcfg_pull_none>; - }; - - emmc_cmd: emmc-cmd { - rockchip,pins = <1 22 RK_FUNC_2 &pcfg_pull_none>; - }; - - emmc_bus8: emmc-bus8 { - rockchip,pins = <1 24 RK_FUNC_2 &pcfg_pull_none>, - <1 25 RK_FUNC_2 &pcfg_pull_none>, - <1 26 RK_FUNC_2 &pcfg_pull_none>, - <1 27 RK_FUNC_2 &pcfg_pull_none>, - <1 28 RK_FUNC_2 &pcfg_pull_none>, - <1 29 RK_FUNC_2 &pcfg_pull_none>, - <1 30 RK_FUNC_2 &pcfg_pull_none>, - <1 31 RK_FUNC_2 &pcfg_pull_none>; - }; - }; - - i2c0 { - i2c0_xfer: i2c0-xfer { - rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>, - <0 1 RK_FUNC_1 &pcfg_pull_none>; - }; - }; - - i2c1 { - i2c1_xfer: i2c1-xfer { - rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_none>, - <0 3 RK_FUNC_1 &pcfg_pull_none>; - }; - }; - - i2c2 { - i2c2_xfer: i2c2-xfer { - rockchip,pins = <2 20 RK_FUNC_1 &pcfg_pull_none>, - <2 21 RK_FUNC_1 &pcfg_pull_none>; - }; - }; - - i2c3 { - i2c3_xfer: i2c3-xfer { - rockchip,pins = <0 6 RK_FUNC_1 &pcfg_pull_none>, - <0 7 RK_FUNC_1 &pcfg_pull_none>; - }; - }; - - pwm0 { - pwm0_pin: pwm0-pin { - rockchip,pins = <3 21 RK_FUNC_1 &pcfg_pull_none>; - }; - }; - - pwm1 { - pwm1_pin: pwm1-pin { - rockchip,pins = <0 30 RK_FUNC_2 &pcfg_pull_none>; - }; - }; - - pwm2 { - pwm2_pin: pwm2-pin { - rockchip,pins = <1 12 RK_FUNC_2 &pcfg_pull_none>; - }; - }; - - pwm3 { - pwm3_pin: pwm3-pin { - rockchip,pins = <1 11 RK_FUNC_2 &pcfg_pull_none>; - }; - }; - - tsadc { - otp_gpio: otp-gpio { - rockchip,pins = <0 24 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - otp_out: otp-out { - rockchip,pins = <0 24 RK_FUNC_2 &pcfg_pull_none>; - }; - }; - - uart0 { - uart0_xfer: uart0-xfer { - rockchip,pins = <2 26 RK_FUNC_1 &pcfg_pull_none>, - <2 27 RK_FUNC_1 &pcfg_pull_none>; - }; - - uart0_cts: uart0-cts { - rockchip,pins = <2 29 RK_FUNC_1 &pcfg_pull_none>; - }; - - uart0_rts: uart0-rts { - rockchip,pins = <0 17 RK_FUNC_1 &pcfg_pull_none>; - }; - }; - - uart1 { - uart1_xfer: uart1-xfer { - rockchip,pins = <1 9 RK_FUNC_1 &pcfg_pull_none>, - <1 10 RK_FUNC_1 &pcfg_pull_none>; - }; - - uart1_cts: uart1-cts { - rockchip,pins = <1 8 RK_FUNC_1 &pcfg_pull_none>; - }; - - uart1_rts: uart1-rts { - rockchip,pins = <1 11 RK_FUNC_1 &pcfg_pull_none>; - }; - }; - - uart2 { - uart2_xfer: uart2-xfer { - rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_none>, - <1 19 RK_FUNC_2 &pcfg_pull_none>; - }; - - uart2_cts: uart2-cts { - rockchip,pins = <0 25 RK_FUNC_1 &pcfg_pull_none>; - }; - - uart2_rts: uart2-rts { - rockchip,pins = <0 24 RK_FUNC_1 &pcfg_pull_none>; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi new file mode 100644 index 0000000..a68fdcaf --- /dev/null +++ b/arch/arm/boot/dts/rk322x.dtsi @@ -0,0 +1,589 @@ +/* + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include +#include +#include +#include +#include +#include +#include "skeleton.dtsi" + +/ { + interrupt-parent = <&gic>; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@f00 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0xf00>; + resets = <&cru SRST_CORE0>; + operating-points = < + /* KHz uV */ + 816000 1000000 + >; + #cooling-cells = <2>; /* min followed by max */ + clock-latency = <40000>; + clocks = <&cru ARMCLK>; + }; + + cpu1: cpu@f01 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0xf01>; + resets = <&cru SRST_CORE1>; + }; + + cpu2: cpu@f02 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0xf02>; + resets = <&cru SRST_CORE2>; + }; + + cpu3: cpu@f03 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0xf03>; + resets = <&cru SRST_CORE3>; + }; + }; + + amba { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + pdma: pdma@110f0000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x110f0000 0x4000>; + interrupts = , + ; + #dma-cells = <1>; + clocks = <&cru ACLK_DMAC>; + clock-names = "apb_pclk"; + }; + }; + + arm-pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts = , + , + , + ; + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; + }; + + timer { + compatible = "arm,armv7-timer"; + arm,cpu-registers-not-fw-configured; + interrupts = , + , + , + ; + clock-frequency = <24000000>; + }; + + xin24m: oscillator { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "xin24m"; + #clock-cells = <0>; + }; + + grf: syscon@11000000 { + compatible = "syscon"; + reg = <0x11000000 0x1000>; + }; + + uart0: serial@11010000 { + compatible = "snps,dw-apb-uart"; + reg = <0x11010000 0x100>; + interrupts = ; + clock-frequency = <24000000>; + clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; + clock-names = "baudclk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart1: serial@11020000 { + compatible = "snps,dw-apb-uart"; + reg = <0x11020000 0x100>; + interrupts = ; + clock-frequency = <24000000>; + clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; + clock-names = "baudclk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1_xfer>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart2: serial@11030000 { + compatible = "snps,dw-apb-uart"; + reg = <0x11030000 0x100>; + interrupts = ; + clock-frequency = <24000000>; + clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; + clock-names = "baudclk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&uart2_xfer>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + i2c0: i2c@11050000 { + compatible = "rockchip,rk3228-i2c"; + reg = <0x11050000 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "i2c"; + clocks = <&cru PCLK_I2C0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_xfer>; + status = "disabled"; + }; + + i2c1: i2c@11060000 { + compatible = "rockchip,rk3228-i2c"; + reg = <0x11060000 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "i2c"; + clocks = <&cru PCLK_I2C1>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_xfer>; + status = "disabled"; + }; + + i2c2: i2c@11070000 { + compatible = "rockchip,rk3228-i2c"; + reg = <0x11070000 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "i2c"; + clocks = <&cru PCLK_I2C2>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_xfer>; + status = "disabled"; + }; + + i2c3: i2c@11080000 { + compatible = "rockchip,rk3228-i2c"; + reg = <0x11080000 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "i2c"; + clocks = <&cru PCLK_I2C3>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_xfer>; + status = "disabled"; + }; + + pwm0: pwm@110b0000 { + compatible = "rockchip,rk3288-pwm"; + reg = <0x110b0000 0x10>; + #pwm-cells = <3>; + clocks = <&cru PCLK_PWM>; + clock-names = "pwm"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_pin>; + status = "disabled"; + }; + + pwm1: pwm@110b0010 { + compatible = "rockchip,rk3288-pwm"; + reg = <0x110b0010 0x10>; + #pwm-cells = <3>; + clocks = <&cru PCLK_PWM>; + clock-names = "pwm"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm1_pin>; + status = "disabled"; + }; + + pwm2: pwm@110b0020 { + compatible = "rockchip,rk3288-pwm"; + reg = <0x110b0020 0x10>; + #pwm-cells = <3>; + clocks = <&cru PCLK_PWM>; + clock-names = "pwm"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm2_pin>; + status = "disabled"; + }; + + pwm3: pwm@110b0030 { + compatible = "rockchip,rk3288-pwm"; + reg = <0x110b0030 0x10>; + #pwm-cells = <2>; + clocks = <&cru PCLK_PWM>; + clock-names = "pwm"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm3_pin>; + status = "disabled"; + }; + + timer: timer@110c0000 { + compatible = "rockchip,rk3288-timer"; + reg = <0x110c0000 0x20>; + interrupts = ; + clocks = <&xin24m>, <&cru PCLK_TIMER>; + clock-names = "timer", "pclk"; + }; + + cru: clock-controller@110e0000 { + compatible = "rockchip,rk3228-cru"; + reg = <0x110e0000 0x1000>; + rockchip,grf = <&grf>; + #clock-cells = <1>; + #reset-cells = <1>; + assigned-clocks = <&cru PLL_GPLL>; + assigned-clock-rates = <594000000>; + }; + + thermal-zones { + cpu_thermal: cpu-thermal { + polling-delay-passive = <100>; /* milliseconds */ + polling-delay = <5000>; /* milliseconds */ + + thermal-sensors = <&tsadc 0>; + + trips { + cpu_alert0: cpu_alert0 { + temperature = <70000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + cpu_alert1: cpu_alert1 { + temperature = <75000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + cpu_crit: cpu_crit { + temperature = <90000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu_alert0>; + cooling-device = + <&cpu0 THERMAL_NO_LIMIT 6>; + }; + map1 { + trip = <&cpu_alert1>; + cooling-device = + <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + }; + + tsadc: tsadc@11150000 { + compatible = "rockchip,rk3228-tsadc"; + reg = <0x11150000 0x100>; + interrupts = ; + clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; + clock-names = "tsadc", "apb_pclk"; + resets = <&cru SRST_TSADC>; + reset-names = "tsadc-apb"; + pinctrl-names = "init", "default", "sleep"; + pinctrl-0 = <&otp_gpio>; + pinctrl-1 = <&otp_out>; + pinctrl-2 = <&otp_gpio>; + #thermal-sensor-cells = <0>; + rockchip,hw-tshut-temp = <95000>; + status = "disabled"; + }; + + emmc: dwmmc@30020000 { + compatible = "rockchip,rk3288-dw-mshc"; + reg = <0x30020000 0x4000>; + interrupts = ; + clock-frequency = <37500000>; + clock-freq-min-max = <400000 37500000>; + clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, + <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; + clock-names = "biu", "ciu", "ciu_drv", "ciu_sample"; + bus-width = <8>; + default-sample-phase = <158>; + num-slots = <1>; + fifo-depth = <0x100>; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; + status = "disabled"; + }; + + gic: interrupt-controller@32010000 { + compatible = "arm,gic-400"; + interrupt-controller; + #interrupt-cells = <3>; + #address-cells = <0>; + + reg = <0x32011000 0x1000>, + <0x32012000 0x1000>, + <0x32014000 0x2000>, + <0x32016000 0x2000>; + interrupts = ; + }; + + pinctrl: pinctrl { + compatible = "rockchip,rk3228-pinctrl"; + rockchip,grf = <&grf>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + gpio0: gpio0@11110000 { + compatible = "rockchip,gpio-bank"; + reg = <0x11110000 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO0>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio1: gpio1@11120000 { + compatible = "rockchip,gpio-bank"; + reg = <0x11120000 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO1>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio2@11130000 { + compatible = "rockchip,gpio-bank"; + reg = <0x11130000 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO2>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio3@11140000 { + compatible = "rockchip,gpio-bank"; + reg = <0x11140000 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO3>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + pcfg_pull_up: pcfg-pull-up { + bias-pull-up; + }; + + pcfg_pull_down: pcfg-pull-down { + bias-pull-down; + }; + + pcfg_pull_none: pcfg-pull-none { + bias-disable; + }; + + emmc { + emmc_clk: emmc-clk { + rockchip,pins = <2 7 RK_FUNC_2 &pcfg_pull_none>; + }; + + emmc_cmd: emmc-cmd { + rockchip,pins = <1 22 RK_FUNC_2 &pcfg_pull_none>; + }; + + emmc_bus8: emmc-bus8 { + rockchip,pins = <1 24 RK_FUNC_2 &pcfg_pull_none>, + <1 25 RK_FUNC_2 &pcfg_pull_none>, + <1 26 RK_FUNC_2 &pcfg_pull_none>, + <1 27 RK_FUNC_2 &pcfg_pull_none>, + <1 28 RK_FUNC_2 &pcfg_pull_none>, + <1 29 RK_FUNC_2 &pcfg_pull_none>, + <1 30 RK_FUNC_2 &pcfg_pull_none>, + <1 31 RK_FUNC_2 &pcfg_pull_none>; + }; + }; + + i2c0 { + i2c0_xfer: i2c0-xfer { + rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>, + <0 1 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + i2c1 { + i2c1_xfer: i2c1-xfer { + rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_none>, + <0 3 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + i2c2 { + i2c2_xfer: i2c2-xfer { + rockchip,pins = <2 20 RK_FUNC_1 &pcfg_pull_none>, + <2 21 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + i2c3 { + i2c3_xfer: i2c3-xfer { + rockchip,pins = <0 6 RK_FUNC_1 &pcfg_pull_none>, + <0 7 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + pwm0 { + pwm0_pin: pwm0-pin { + rockchip,pins = <3 21 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + pwm1 { + pwm1_pin: pwm1-pin { + rockchip,pins = <0 30 RK_FUNC_2 &pcfg_pull_none>; + }; + }; + + pwm2 { + pwm2_pin: pwm2-pin { + rockchip,pins = <1 12 RK_FUNC_2 &pcfg_pull_none>; + }; + }; + + pwm3 { + pwm3_pin: pwm3-pin { + rockchip,pins = <1 11 RK_FUNC_2 &pcfg_pull_none>; + }; + }; + + tsadc { + otp_gpio: otp-gpio { + rockchip,pins = <0 24 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + otp_out: otp-out { + rockchip,pins = <0 24 RK_FUNC_2 &pcfg_pull_none>; + }; + }; + + uart0 { + uart0_xfer: uart0-xfer { + rockchip,pins = <2 26 RK_FUNC_1 &pcfg_pull_none>, + <2 27 RK_FUNC_1 &pcfg_pull_none>; + }; + + uart0_cts: uart0-cts { + rockchip,pins = <2 29 RK_FUNC_1 &pcfg_pull_none>; + }; + + uart0_rts: uart0-rts { + rockchip,pins = <0 17 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + uart1 { + uart1_xfer: uart1-xfer { + rockchip,pins = <1 9 RK_FUNC_1 &pcfg_pull_none>, + <1 10 RK_FUNC_1 &pcfg_pull_none>; + }; + + uart1_cts: uart1-cts { + rockchip,pins = <1 8 RK_FUNC_1 &pcfg_pull_none>; + }; + + uart1_rts: uart1-rts { + rockchip,pins = <1 11 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + uart2 { + uart2_xfer: uart2-xfer { + rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_none>, + <1 19 RK_FUNC_2 &pcfg_pull_none>; + }; + + uart2_cts: uart2-cts { + rockchip,pins = <0 25 RK_FUNC_1 &pcfg_pull_none>; + }; + + uart2_rts: uart2-rts { + rockchip,pins = <0 24 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + }; +}; -- cgit v0.10.2 From ccada2489206b5f1870ac132408bf41ffe51995a Mon Sep 17 00:00:00 2001 From: Xing Zheng Date: Wed, 22 Jun 2016 11:16:51 +0800 Subject: ARM: dts: rockchip: add i2s nodes for RK322x SoCs This patch add the i2s dt nodes for rk322x SoCs. Signed-off-by: Xing Zheng Signed-off-by: Heiko Stuebner diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi index a68fdcaf..26f3bec 100644 --- a/arch/arm/boot/dts/rk322x.dtsi +++ b/arch/arm/boot/dts/rk322x.dtsi @@ -138,6 +138,47 @@ #clock-cells = <0>; }; + i2s1: i2s1@100b0000 { + compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s"; + reg = <0x100b0000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "i2s_clk", "i2s_hclk"; + clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>; + dmas = <&pdma 14>, <&pdma 15>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1_bus>; + status = "disabled"; + }; + + i2s0: i2s0@100c0000 { + compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s"; + reg = <0x100c0000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "i2s_clk", "i2s_hclk"; + clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>; + dmas = <&pdma 11>, <&pdma 12>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + i2s2: i2s2@100e0000 { + compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s"; + reg = <0x100e0000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "i2s_clk", "i2s_hclk"; + clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>; + dmas = <&pdma 0>, <&pdma 1>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + grf: syscon@11000000 { compatible = "syscon"; reg = <0x11000000 0x1000>; @@ -507,6 +548,20 @@ }; }; + i2s1 { + i2s1_bus: i2s1-bus { + rockchip,pins = <0 8 RK_FUNC_1 &pcfg_pull_none>, + <0 9 RK_FUNC_1 &pcfg_pull_none>, + <0 11 RK_FUNC_1 &pcfg_pull_none>, + <0 12 RK_FUNC_1 &pcfg_pull_none>, + <0 13 RK_FUNC_1 &pcfg_pull_none>, + <0 14 RK_FUNC_1 &pcfg_pull_none>, + <1 2 RK_FUNC_1 &pcfg_pull_none>, + <1 4 RK_FUNC_1 &pcfg_pull_none>, + <1 5 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + pwm0 { pwm0_pin: pwm0-pin { rockchip,pins = <3 21 RK_FUNC_1 &pcfg_pull_none>; -- cgit v0.10.2 From 5d3d7c72b920f9aa44f9b64cdd8a1c5bf5cbea07 Mon Sep 17 00:00:00 2001 From: Xing Zheng Date: Wed, 22 Jun 2016 11:16:52 +0800 Subject: ARM: dts: rockchip: add GMAC nodes for RK322x SoCs This patch add the GMAC dt nodes for rk322x SoCs. Signed-off-by: Xing Zheng Signed-off-by: Heiko Stuebner diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi index 26f3bec..9e6bf0e 100644 --- a/arch/arm/boot/dts/rk322x.dtsi +++ b/arch/arm/boot/dts/rk322x.dtsi @@ -415,6 +415,25 @@ status = "disabled"; }; + gmac: ethernet@30200000 { + compatible = "rockchip,rk3228-gmac"; + reg = <0x30200000 0x10000>; + interrupts = ; + interrupt-names = "macirq"; + clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>, + <&cru SCLK_MAC_TX>, <&cru SCLK_MAC_REF>, + <&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>, + <&cru PCLK_GMAC>; + clock-names = "stmmaceth", "mac_clk_rx", + "mac_clk_tx", "clk_mac_ref", + "clk_mac_refout", "aclk_mac", + "pclk_mac"; + resets = <&cru SRST_GMAC>; + reset-names = "stmmaceth"; + rockchip,grf = <&grf>; + status = "disabled"; + }; + gic: interrupt-controller@32010000 { compatible = "arm,gic-400"; interrupt-controller; @@ -499,6 +518,10 @@ bias-disable; }; + pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma { + drive-strength = <12>; + }; + emmc { emmc_clk: emmc-clk { rockchip,pins = <2 7 RK_FUNC_2 &pcfg_pull_none>; @@ -520,6 +543,44 @@ }; }; + gmac { + rgmii_pins: rgmii-pins { + rockchip,pins = <2 14 RK_FUNC_1 &pcfg_pull_none>, + <2 12 RK_FUNC_1 &pcfg_pull_none>, + <2 25 RK_FUNC_1 &pcfg_pull_none>, + <2 19 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, + <2 18 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, + <2 22 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, + <2 23 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, + <2 9 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, + <2 13 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, + <2 17 RK_FUNC_1 &pcfg_pull_none>, + <2 16 RK_FUNC_1 &pcfg_pull_none>, + <2 21 RK_FUNC_2 &pcfg_pull_none>, + <2 20 RK_FUNC_2 &pcfg_pull_none>, + <2 11 RK_FUNC_1 &pcfg_pull_none>, + <2 8 RK_FUNC_1 &pcfg_pull_none>; + }; + + rmii_pins: rmii-pins { + rockchip,pins = <2 14 RK_FUNC_1 &pcfg_pull_none>, + <2 12 RK_FUNC_1 &pcfg_pull_none>, + <2 25 RK_FUNC_1 &pcfg_pull_none>, + <2 19 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, + <2 18 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, + <2 13 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, + <2 17 RK_FUNC_1 &pcfg_pull_none>, + <2 16 RK_FUNC_1 &pcfg_pull_none>, + <2 8 RK_FUNC_1 &pcfg_pull_none>, + <2 15 RK_FUNC_1 &pcfg_pull_none>; + }; + + phy_pins: phy-pins { + rockchip,pins = <2 14 RK_FUNC_2 &pcfg_pull_none>, + <2 8 RK_FUNC_2 &pcfg_pull_none>; + }; + }; + i2c0 { i2c0_xfer: i2c0-xfer { rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>, -- cgit v0.10.2 From 241eff3c198492b2d63e75723b774f2836fee8a3 Mon Sep 17 00:00:00 2001 From: Xing Zheng Date: Wed, 22 Jun 2016 11:16:53 +0800 Subject: ARM: dts: rockchip: add support rk3229 evb board Initial release for rk3229 evb board, and turn the GMAC on. Signed-off-by: Xing Zheng Signed-off-by: Heiko Stuebner diff --git a/Documentation/devicetree/bindings/arm/rockchip.txt b/Documentation/devicetree/bindings/arm/rockchip.txt index 715d960..6668645 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.txt +++ b/Documentation/devicetree/bindings/arm/rockchip.txt @@ -107,6 +107,9 @@ Rockchip platforms device tree bindings Required root node properties: - compatible = "rockchip,rk3228-evb", "rockchip,rk3228"; +- Rockchip RK3229 Evaluation board: + - compatible = "rockchip,rk3229-evb", "rockchip,rk3229"; + - Rockchip RK3399 evb: Required root node properties: - compatible = "rockchip,rk3399-evb", "rockchip,rk3399"; diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 06b6c2d..5e0833f 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -602,6 +602,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \ rk3066a-rayeager.dtb \ rk3188-radxarock.dtb \ rk3228-evb.dtb \ + rk3229-evb.dtb \ rk3288-evb-act8846.dtb \ rk3288-evb-rk808.dtb \ rk3288-firefly-beta.dtb \ diff --git a/arch/arm/boot/dts/rk3229-evb.dts b/arch/arm/boot/dts/rk3229-evb.dts new file mode 100644 index 0000000..b6a1203 --- /dev/null +++ b/arch/arm/boot/dts/rk3229-evb.dts @@ -0,0 +1,90 @@ +/* + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "rk322x.dtsi" + +/ { + model = "Rockchip RK3229 Evaluation board"; + compatible = "rockchip,rk3229-evb", "rockchip,rk3229"; + + memory { + device_type = "memory"; + reg = <0x60000000 0x40000000>; + }; + + ext_gmac: ext_gmac { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "ext_gmac"; + #clock-cells = <0>; + }; + + vcc_phy: vcc-phy-regulator { + compatible = "regulator-fixed"; + enable-active-high; + regulator-name = "vcc_phy"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; +}; + +&gmac { + assigned-clocks = <&cru SCLK_MAC_EXTCLK>, <&cru SCLK_MAC>; + assigned-clock-parents = <&ext_gmac>, <&cru SCLK_MAC_EXTCLK>; + clock_in_out = "input"; + phy-supply = <&vcc_phy>; + phy-mode = "rgmii"; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>; + snps,reset-gpio = <&gpio2 24 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 1000000>; + tx_delay = <0x30>; + rx_delay = <0x10>; + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; -- cgit v0.10.2 From ccd140b574e28a8f622fa53d8bac99e585d7ced6 Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Fri, 10 Jun 2016 10:38:34 +0100 Subject: ARM: dts: apq8064: move sdcc1 pinctrl nodes to soc file This patch moves out the sdcc1 pinctrl nodes out of board files to soc file, so that it will be duplicated in other board files. Signed-off-by: Srinivas Kandagatla Signed-off-by: Andy Gross diff --git a/arch/arm/boot/dts/qcom-apq8064-pins.dtsi b/arch/arm/boot/dts/qcom-apq8064-pins.dtsi index 4102a98..ca683e5 100644 --- a/arch/arm/boot/dts/qcom-apq8064-pins.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064-pins.dtsi @@ -7,6 +7,26 @@ }; }; + sdcc1_pins: sdcc1-pin-active { + clk { + pins = "sdc1_clk"; + drive-strengh = <16>; + bias-disable; + }; + + cmd { + pins = "sdc1_cmd"; + drive-strengh = <10>; + bias-pull-up; + }; + + data { + pins = "sdc1_data"; + drive-strengh = <10>; + bias-pull-up; + }; + }; + ps_hold: ps_hold { mux { pins = "gpio78"; diff --git a/arch/arm/boot/dts/qcom-apq8064-sony-xperia-yuga.dts b/arch/arm/boot/dts/qcom-apq8064-sony-xperia-yuga.dts index 06b3c76..93d08b9 100644 --- a/arch/arm/boot/dts/qcom-apq8064-sony-xperia-yuga.dts +++ b/arch/arm/boot/dts/qcom-apq8064-sony-xperia-yuga.dts @@ -70,25 +70,6 @@ }; }; - sdcc1_pin_a: sdcc1-pin-active { - clk { - pins = "sdc1_clk"; - drive-strengh = <16>; - bias-disable; - }; - - cmd { - pins = "sdc1_cmd"; - drive-strengh = <10>; - bias-pull-up; - }; - - data { - pins = "sdc1_data"; - drive-strengh = <10>; - bias-pull-up; - }; - }; sdcc3_pin_a: sdcc3-pin-active { clk { @@ -417,9 +398,6 @@ vmmc-supply = <&pm8921_l5>; vqmmc-supply = <&pm8921_s4>; - - pinctrl-names = "default"; - pinctrl-0 = <&sdcc1_pin_a>; }; sdcc3: sdcc@12180000 { diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index cf37d55..ce7ce84 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -859,6 +859,8 @@ sdcc1: sdcc@12400000 { status = "disabled"; compatible = "arm,pl18x", "arm,primecell"; + pinctrl-names = "default"; + pinctrl-0 = <&sdcc1_pins>; arm,primecell-periphid = <0x00051180>; reg = <0x12400000 0x2000>; interrupts = ; -- cgit v0.10.2 From c351c254ac676d79282512d2f692ab0ccce479a6 Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Fri, 10 Jun 2016 10:38:35 +0100 Subject: ARM: dts: apq8064: move sdcc3 pinctrls out of baord file This patch move sdcc3 pinctrl nodes out of board file, so that other boards do not duplicate the same thing. Signed-off-by: Srinivas Kandagatla Signed-off-by: Andy Gross diff --git a/arch/arm/boot/dts/qcom-apq8064-pins.dtsi b/arch/arm/boot/dts/qcom-apq8064-pins.dtsi index ca683e5..6b801e7 100644 --- a/arch/arm/boot/dts/qcom-apq8064-pins.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064-pins.dtsi @@ -27,6 +27,26 @@ }; }; + sdcc3_pins: sdcc3-pin-active { + clk { + pins = "sdc3_clk"; + drive-strengh = <8>; + bias-disable; + }; + + cmd { + pins = "sdc3_cmd"; + drive-strengh = <8>; + bias-pull-up; + }; + + data { + pins = "sdc3_data"; + drive-strengh = <8>; + bias-pull-up; + }; + }; + ps_hold: ps_hold { mux { pins = "gpio78"; diff --git a/arch/arm/boot/dts/qcom-apq8064-sony-xperia-yuga.dts b/arch/arm/boot/dts/qcom-apq8064-sony-xperia-yuga.dts index 93d08b9..ebd675c 100644 --- a/arch/arm/boot/dts/qcom-apq8064-sony-xperia-yuga.dts +++ b/arch/arm/boot/dts/qcom-apq8064-sony-xperia-yuga.dts @@ -71,26 +71,6 @@ }; - sdcc3_pin_a: sdcc3-pin-active { - clk { - pins = "sdc3_clk"; - drive-strengh = <8>; - bias-disable; - }; - - cmd { - pins = "sdc3_cmd"; - drive-strengh = <8>; - bias-pull-up; - }; - - data { - pins = "sdc3_data"; - drive-strengh = <8>; - bias-pull-up; - }; - }; - sdcc3_cd_pin_a: sdcc3-cd-pin-active { pins = "gpio26"; function = "gpio"; @@ -407,7 +387,7 @@ cd-gpios = <&tlmm_pinmux 26 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; - pinctrl-0 = <&sdcc3_pin_a>, <&sdcc3_cd_pin_a>; + pinctrl-0 = <&sdcc3_pins>, <&sdcc3_cd_pin_a>; }; }; }; -- cgit v0.10.2 From 5f963e2951d019bc217fdc722dba765ac494eec2 Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Fri, 10 Jun 2016 19:19:54 +0100 Subject: ARM: dts: apq8064: rename db600c to SD_600eval This board has been renamed recently and announced at https://eragon.einfochips.com/products/sd-600eval.html So rename this board files so that it reflects actual product in market. Signed-off-by: Srinivas Kandagatla Signed-off-by: Andy Gross diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 06b6c2d..5b7c17a 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -572,7 +572,7 @@ dtb-$(CONFIG_ARCH_PRIMA2) += \ dtb-$(CONFIG_ARCH_OXNAS) += \ wd-mbwe.dtb dtb-$(CONFIG_ARCH_QCOM) += \ - qcom-apq8064-arrow-db600c.dtb \ + qcom-apq8064-arrow-sd-600eval.dtb \ qcom-apq8064-cm-qs600.dtb \ qcom-apq8064-ifc6410.dtb \ qcom-apq8064-sony-xperia-yuga.dtb \ diff --git a/arch/arm/boot/dts/qcom-apq8064-arrow-db600c-pins.dtsi b/arch/arm/boot/dts/qcom-apq8064-arrow-db600c-pins.dtsi deleted file mode 100644 index a3efb97..0000000 --- a/arch/arm/boot/dts/qcom-apq8064-arrow-db600c-pins.dtsi +++ /dev/null @@ -1,52 +0,0 @@ -&tlmm_pinmux { - card_detect: card-detect { - mux { - pins = "gpio26"; - function = "gpio"; - bias-disable; - }; - }; - - pcie_pins: pcie-pinmux { - mux { - pins = "gpio27"; - function = "gpio"; - }; - conf { - pins = "gpio27"; - drive-strength = <12>; - bias-disable; - }; - }; - - user_leds: user-leds { - mux { - pins = "gpio3", "gpio7", "gpio10", "gpio11"; - function = "gpio"; - }; - - conf { - pins = "gpio3", "gpio7", "gpio10", "gpio11"; - function = "gpio"; - output-low; - }; - }; - - magneto_pins: magneto-pins { - mux { - pins = "gpio31", "gpio48"; - function = "gpio"; - bias-disable; - }; - }; -}; - -&pm8921_mpps { - mpp_leds: mpp-leds { - pinconf { - pins = "mpp7", "mpp8"; - function = "digital"; - output-low; - }; - }; -}; diff --git a/arch/arm/boot/dts/qcom-apq8064-arrow-db600c.dts b/arch/arm/boot/dts/qcom-apq8064-arrow-db600c.dts deleted file mode 100644 index e01b27e..0000000 --- a/arch/arm/boot/dts/qcom-apq8064-arrow-db600c.dts +++ /dev/null @@ -1,349 +0,0 @@ -#include "qcom-apq8064-v2.0.dtsi" -#include "qcom-apq8064-arrow-db600c-pins.dtsi" -#include - -/ { - model = "Arrow Electronics, APQ8064 DB600c"; - compatible = "arrow,db600c", "qcom,apq8064"; - - aliases { - serial0 = &gsbi7_serial; - serial1 = &gsbi1_serial; - i2c0 = &gsbi2_i2c; - i2c1 = &gsbi3_i2c; - i2c2 = &gsbi4_i2c; - i2c3 = &gsbi7_i2c; - spi0 = &gsbi5_spi; - }; - - regulators { - compatible = "simple-bus"; - vph: regulator-fixed@1 { - compatible = "regulator-fixed"; - regulator-min-microvolt = <4500000>; - regulator-max-microvolt = <4500000>; - regulator-name = "VPH"; - regulator-type = "voltage"; - regulator-boot-on; - }; - - /* on board fixed 3.3v supply */ - vcc3v3: vcc3v3 { - compatible = "regulator-fixed"; - regulator-name = "VCC3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - }; - - soc { - rpm@108000 { - regulators { - vdd_s1-supply = <&vph>; - vdd_s2-supply = <&vph>; - vdd_s3-supply = <&vph>; - vdd_s4-supply = <&vph>; - vdd_s5-supply = <&vph>; - vdd_s6-supply = <&vph>; - vdd_s7-supply = <&vph>; - vdd_l1_l2_l12_l18-supply = <&pm8921_s4>; - vdd_l3_l15_l17-supply = <&vph>; - vdd_l4_l14-supply = <&vph>; - vdd_l5_l8_l16-supply = <&vph>; - vdd_l6_l7-supply = <&vph>; - vdd_l9_l11-supply = <&vph>; - vdd_l10_l22-supply = <&vph>; - vdd_l21_l23_l29-supply = <&vph>; - vdd_l24-supply = <&pm8921_s1>; - vdd_l25-supply = <&pm8921_s1>; - vdd_l26-supply = <&pm8921_s7>; - vdd_l27-supply = <&pm8921_s7>; - vdd_l28-supply = <&pm8921_s7>; - vin_lvs1_3_6-supply = <&pm8921_s4>; - vin_lvs2-supply = <&pm8921_s1>; - vin_lvs4_5_7-supply = <&pm8921_s4>; - - s1 { - regulator-always-on; - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - qcom,switch-mode-frequency = <3200000>; - bias-pull-down; - }; - - s3 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - qcom,switch-mode-frequency = <4800000>; - }; - - s4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - qcom,switch-mode-frequency = <3200000>; - bias-pull-down; - regulator-always-on; - }; - - s7 { - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1300000>; - qcom,switch-mode-frequency = <3200000>; - }; - - l3 { - regulator-min-microvolt = <3050000>; - regulator-max-microvolt = <3300000>; - bias-pull-down; - }; - - l4 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1800000>; - bias-pull-down; - }; - - l5 { - regulator-min-microvolt = <2750000>; - regulator-max-microvolt = <3000000>; - bias-pull-down; - regulator-boot-on; - regulator-always-on; - }; - - l6 { - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - bias-pull-down; - }; - - l23 { - regulator-min-microvolt = <1700000>; - regulator-max-microvolt = <1900000>; - bias-pull-down; - }; - - lvs6 { - bias-pull-down; - }; - - lvs7 { - bias-pull-down; - }; - }; - }; - - gsbi@12440000 { - status = "okay"; - qcom,mode = ; - serial@12450000 { - label = "LS-UART1"; - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&gsbi1_uart_4pins>; - }; - }; - - gsbi@12480000 { - status = "okay"; - qcom,mode = ; - i2c@124a0000 { - /* On Low speed expansion and Sensors */ - label = "LS-I2C0"; - status = "okay"; - lis3mdl_mag@1e { - compatible = "st,lis3mdl-magn"; - reg = <0x1e>; - vdd-supply = <&vcc3v3>; - vddio-supply = <&pm8921_s4>; - pinctrl-names = "default"; - pinctrl-0 = <&magneto_pins>; - interrupt-parent = <&tlmm_pinmux>; - - st,drdy-int-pin = <2>; - interrupts = <48 IRQ_TYPE_EDGE_RISING>, /* DRDY line */ - <31 IRQ_TYPE_EDGE_RISING>; /* INT */ - }; - }; - }; - - gsbi@16200000 { - status = "okay"; - qcom,mode = ; - i2c@16280000 { - /* On Low speed expansion */ - status = "okay"; - label = "LS-I2C1"; - clock-frequency = <200000>; - eeprom@52 { - compatible = "atmel,24c128"; - reg = <0x52>; - pagesize = <64>; - }; - }; - }; - - gsbi@16300000 { - status = "okay"; - qcom,mode = ; - i2c@16380000 { - /* On High speed expansion */ - label = "HS-CAM-I2C3"; - status = "okay"; - }; - }; - - gsbi@1a200000 { - status = "okay"; - spi@1a280000 { - /* On Low speed expansion */ - label = "LS-SPI0"; - status = "okay"; - }; - }; - - /* DEBUG UART */ - gsbi@16600000 { - status = "okay"; - qcom,mode = ; - serial@16640000 { - label = "LS-UART0"; - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&gsbi7_uart_2pins>; - }; - - i2c@16680000 { - /* On High speed expansion */ - status = "okay"; - label = "HS-CAM-I2C2"; - }; - }; - - leds { - pinctrl-names = "default"; - pinctrl-0 = <&user_leds>, <&mpp_leds>; - - compatible = "gpio-leds"; - - user-led0 { - label = "user0-led"; - gpios = <&tlmm_pinmux 3 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - default-state = "off"; - }; - - user-led1 { - label = "user1-led"; - gpios = <&tlmm_pinmux 7 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "mmc0"; - default-state = "off"; - }; - - user-led2 { - label = "user2-led"; - gpios = <&tlmm_pinmux 10 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "mmc1"; - default-state = "off"; - }; - - user-led3 { - label = "user3-led"; - gpios = <&tlmm_pinmux 11 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "none"; - default-state = "off"; - }; - - wifi-led { - label = "WiFi-led"; - gpios = <&pm8921_mpps 7 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - bt-led { - label = "BT-led"; - gpios = <&pm8921_mpps 8 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - }; - - pci@1b500000 { - status = "okay"; - vdda-supply = <&pm8921_s3>; - vdda_phy-supply = <&pm8921_lvs6>; - vdda_refclk-supply = <&vcc3v3>; - pinctrl-0 = <&pcie_pins>; - pinctrl-names = "default"; - perst-gpio = <&tlmm_pinmux 27 GPIO_ACTIVE_LOW>; - }; - - phy@1b400000 { - status = "okay"; - }; - - sata@29000000 { - status = "okay"; - target-supply = <&pm8921_lvs7>; - }; - - /* OTG */ - phy@12500000 { - status = "okay"; - dr_mode = "peripheral"; - vddcx-supply = <&pm8921_s3>; - v3p3-supply = <&pm8921_l3>; - v1p8-supply = <&pm8921_l4>; - }; - - phy@12520000 { - status = "okay"; - vddcx-supply = <&pm8921_s3>; - v3p3-supply = <&pm8921_l3>; - v1p8-supply = <&pm8921_l23>; - }; - - phy@12530000 { - status = "okay"; - vddcx-supply = <&pm8921_s3>; - v3p3-supply = <&pm8921_l3>; - v1p8-supply = <&pm8921_l23>; - }; - - gadget@12500000 { - status = "okay"; - }; - - /* OTG */ - usb@12500000 { - status = "okay"; - }; - - usb@12520000 { - status = "okay"; - }; - - usb@12530000 { - status = "okay"; - }; - - amba { - /* eMMC */ - sdcc@12400000 { - status = "okay"; - vmmc-supply = <&pm8921_l5>; - vqmmc-supply = <&pm8921_s4>; - }; - - /* External micro SD card */ - sdcc@12180000 { - status = "okay"; - vmmc-supply = <&pm8921_l6>; - pinctrl-names = "default"; - pinctrl-0 = <&card_detect>; - cd-gpios = <&tlmm_pinmux 26 GPIO_ACTIVE_HIGH>; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/qcom-apq8064-arrow-sd-600eval-pins.dtsi b/arch/arm/boot/dts/qcom-apq8064-arrow-sd-600eval-pins.dtsi new file mode 100644 index 0000000..a3efb97 --- /dev/null +++ b/arch/arm/boot/dts/qcom-apq8064-arrow-sd-600eval-pins.dtsi @@ -0,0 +1,52 @@ +&tlmm_pinmux { + card_detect: card-detect { + mux { + pins = "gpio26"; + function = "gpio"; + bias-disable; + }; + }; + + pcie_pins: pcie-pinmux { + mux { + pins = "gpio27"; + function = "gpio"; + }; + conf { + pins = "gpio27"; + drive-strength = <12>; + bias-disable; + }; + }; + + user_leds: user-leds { + mux { + pins = "gpio3", "gpio7", "gpio10", "gpio11"; + function = "gpio"; + }; + + conf { + pins = "gpio3", "gpio7", "gpio10", "gpio11"; + function = "gpio"; + output-low; + }; + }; + + magneto_pins: magneto-pins { + mux { + pins = "gpio31", "gpio48"; + function = "gpio"; + bias-disable; + }; + }; +}; + +&pm8921_mpps { + mpp_leds: mpp-leds { + pinconf { + pins = "mpp7", "mpp8"; + function = "digital"; + output-low; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom-apq8064-arrow-sd-600eval.dts b/arch/arm/boot/dts/qcom-apq8064-arrow-sd-600eval.dts new file mode 100644 index 0000000..7df0108 --- /dev/null +++ b/arch/arm/boot/dts/qcom-apq8064-arrow-sd-600eval.dts @@ -0,0 +1,349 @@ +#include "qcom-apq8064-v2.0.dtsi" +#include "qcom-apq8064-arrow-sd-600eval-pins.dtsi" +#include + +/ { + model = "Arrow Electronics, APQ8064 SD_600eval"; + compatible = "arrow,sd_600eval", "qcom,apq8064"; + + aliases { + serial0 = &gsbi7_serial; + serial1 = &gsbi1_serial; + i2c0 = &gsbi2_i2c; + i2c1 = &gsbi3_i2c; + i2c2 = &gsbi4_i2c; + i2c3 = &gsbi7_i2c; + spi0 = &gsbi5_spi; + }; + + regulators { + compatible = "simple-bus"; + vph: regulator-fixed@1 { + compatible = "regulator-fixed"; + regulator-min-microvolt = <4500000>; + regulator-max-microvolt = <4500000>; + regulator-name = "VPH"; + regulator-type = "voltage"; + regulator-boot-on; + }; + + /* on board fixed 3.3v supply */ + vcc3v3: vcc3v3 { + compatible = "regulator-fixed"; + regulator-name = "VCC3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + }; + + soc { + rpm@108000 { + regulators { + vdd_s1-supply = <&vph>; + vdd_s2-supply = <&vph>; + vdd_s3-supply = <&vph>; + vdd_s4-supply = <&vph>; + vdd_s5-supply = <&vph>; + vdd_s6-supply = <&vph>; + vdd_s7-supply = <&vph>; + vdd_l1_l2_l12_l18-supply = <&pm8921_s4>; + vdd_l3_l15_l17-supply = <&vph>; + vdd_l4_l14-supply = <&vph>; + vdd_l5_l8_l16-supply = <&vph>; + vdd_l6_l7-supply = <&vph>; + vdd_l9_l11-supply = <&vph>; + vdd_l10_l22-supply = <&vph>; + vdd_l21_l23_l29-supply = <&vph>; + vdd_l24-supply = <&pm8921_s1>; + vdd_l25-supply = <&pm8921_s1>; + vdd_l26-supply = <&pm8921_s7>; + vdd_l27-supply = <&pm8921_s7>; + vdd_l28-supply = <&pm8921_s7>; + vin_lvs1_3_6-supply = <&pm8921_s4>; + vin_lvs2-supply = <&pm8921_s1>; + vin_lvs4_5_7-supply = <&pm8921_s4>; + + s1 { + regulator-always-on; + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + qcom,switch-mode-frequency = <3200000>; + bias-pull-down; + }; + + s3 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1400000>; + qcom,switch-mode-frequency = <4800000>; + }; + + s4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,switch-mode-frequency = <3200000>; + bias-pull-down; + regulator-always-on; + }; + + s7 { + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + qcom,switch-mode-frequency = <3200000>; + }; + + l3 { + regulator-min-microvolt = <3050000>; + regulator-max-microvolt = <3300000>; + bias-pull-down; + }; + + l4 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1800000>; + bias-pull-down; + }; + + l5 { + regulator-min-microvolt = <2750000>; + regulator-max-microvolt = <3000000>; + bias-pull-down; + regulator-boot-on; + regulator-always-on; + }; + + l6 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + bias-pull-down; + }; + + l23 { + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <1900000>; + bias-pull-down; + }; + + lvs6 { + bias-pull-down; + }; + + lvs7 { + bias-pull-down; + }; + }; + }; + + gsbi@12440000 { + status = "okay"; + qcom,mode = ; + serial@12450000 { + label = "LS-UART1"; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&gsbi1_uart_4pins>; + }; + }; + + gsbi@12480000 { + status = "okay"; + qcom,mode = ; + i2c@124a0000 { + /* On Low speed expansion and Sensors */ + label = "LS-I2C0"; + status = "okay"; + lis3mdl_mag@1e { + compatible = "st,lis3mdl-magn"; + reg = <0x1e>; + vdd-supply = <&vcc3v3>; + vddio-supply = <&pm8921_s4>; + pinctrl-names = "default"; + pinctrl-0 = <&magneto_pins>; + interrupt-parent = <&tlmm_pinmux>; + + st,drdy-int-pin = <2>; + interrupts = <48 IRQ_TYPE_EDGE_RISING>, /* DRDY line */ + <31 IRQ_TYPE_EDGE_RISING>; /* INT */ + }; + }; + }; + + gsbi@16200000 { + status = "okay"; + qcom,mode = ; + i2c@16280000 { + /* On Low speed expansion */ + status = "okay"; + label = "LS-I2C1"; + clock-frequency = <200000>; + eeprom@52 { + compatible = "atmel,24c128"; + reg = <0x52>; + pagesize = <64>; + }; + }; + }; + + gsbi@16300000 { + status = "okay"; + qcom,mode = ; + i2c@16380000 { + /* On High speed expansion */ + label = "HS-CAM-I2C3"; + status = "okay"; + }; + }; + + gsbi@1a200000 { + status = "okay"; + spi@1a280000 { + /* On Low speed expansion */ + label = "LS-SPI0"; + status = "okay"; + }; + }; + + /* DEBUG UART */ + gsbi@16600000 { + status = "okay"; + qcom,mode = ; + serial@16640000 { + label = "LS-UART0"; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&gsbi7_uart_2pins>; + }; + + i2c@16680000 { + /* On High speed expansion */ + status = "okay"; + label = "HS-CAM-I2C2"; + }; + }; + + leds { + pinctrl-names = "default"; + pinctrl-0 = <&user_leds>, <&mpp_leds>; + + compatible = "gpio-leds"; + + user-led0 { + label = "user0-led"; + gpios = <&tlmm_pinmux 3 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + default-state = "off"; + }; + + user-led1 { + label = "user1-led"; + gpios = <&tlmm_pinmux 7 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc0"; + default-state = "off"; + }; + + user-led2 { + label = "user2-led"; + gpios = <&tlmm_pinmux 10 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc1"; + default-state = "off"; + }; + + user-led3 { + label = "user3-led"; + gpios = <&tlmm_pinmux 11 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "none"; + default-state = "off"; + }; + + wifi-led { + label = "WiFi-led"; + gpios = <&pm8921_mpps 7 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + bt-led { + label = "BT-led"; + gpios = <&pm8921_mpps 8 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; + + pci@1b500000 { + status = "okay"; + vdda-supply = <&pm8921_s3>; + vdda_phy-supply = <&pm8921_lvs6>; + vdda_refclk-supply = <&vcc3v3>; + pinctrl-0 = <&pcie_pins>; + pinctrl-names = "default"; + perst-gpio = <&tlmm_pinmux 27 GPIO_ACTIVE_LOW>; + }; + + phy@1b400000 { + status = "okay"; + }; + + sata@29000000 { + status = "okay"; + target-supply = <&pm8921_lvs7>; + }; + + /* OTG */ + phy@12500000 { + status = "okay"; + dr_mode = "peripheral"; + vddcx-supply = <&pm8921_s3>; + v3p3-supply = <&pm8921_l3>; + v1p8-supply = <&pm8921_l4>; + }; + + phy@12520000 { + status = "okay"; + vddcx-supply = <&pm8921_s3>; + v3p3-supply = <&pm8921_l3>; + v1p8-supply = <&pm8921_l23>; + }; + + phy@12530000 { + status = "okay"; + vddcx-supply = <&pm8921_s3>; + v3p3-supply = <&pm8921_l3>; + v1p8-supply = <&pm8921_l23>; + }; + + gadget@12500000 { + status = "okay"; + }; + + /* OTG */ + usb@12500000 { + status = "okay"; + }; + + usb@12520000 { + status = "okay"; + }; + + usb@12530000 { + status = "okay"; + }; + + amba { + /* eMMC */ + sdcc@12400000 { + status = "okay"; + vmmc-supply = <&pm8921_l5>; + vqmmc-supply = <&pm8921_s4>; + }; + + /* External micro SD card */ + sdcc@12180000 { + status = "okay"; + vmmc-supply = <&pm8921_l6>; + pinctrl-names = "default"; + pinctrl-0 = <&card_detect>; + cd-gpios = <&tlmm_pinmux 26 GPIO_ACTIVE_HIGH>; + }; + }; + }; +}; -- cgit v0.10.2 From 93b8e6fda11757a20df21f3fc18e12789841f173 Mon Sep 17 00:00:00 2001 From: Parth Pancholi Date: Fri, 10 Jun 2016 19:19:55 +0100 Subject: ARM: dts: sd_600eval: Fix eMMC lockup issue This board locks up if we stress test the eMMC, as the regulator s4 is unable to supply enough current for all the peripherials attached to it. As this supply is wired up to most of the peripherials including DDR, it resulted in such lockup. This patch fixes this issue by setting s4 regulator correctly with Auto power mode. Reported-by: Srinivas Kandagatla [Srinivas Kandagatla: rewrote the change log] Tested-by: Girish Sharma Signed-off-by: Parth Pancholi Signed-off-by: Andy Gross diff --git a/arch/arm/boot/dts/qcom-apq8064-arrow-sd-600eval.dts b/arch/arm/boot/dts/qcom-apq8064-arrow-sd-600eval.dts index 7df0108..39ae2bc 100644 --- a/arch/arm/boot/dts/qcom-apq8064-arrow-sd-600eval.dts +++ b/arch/arm/boot/dts/qcom-apq8064-arrow-sd-600eval.dts @@ -1,6 +1,7 @@ #include "qcom-apq8064-v2.0.dtsi" #include "qcom-apq8064-arrow-sd-600eval-pins.dtsi" #include +#include / { model = "Arrow Electronics, APQ8064 SD_600eval"; @@ -82,7 +83,8 @@ s4 { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; - qcom,switch-mode-frequency = <3200000>; + qcom,switch-mode-frequency = <1600000>; + qcom,force-mode = ; bias-pull-down; regulator-always-on; }; -- cgit v0.10.2 From d32bfe101f73f5764a871c551460e12480477e63 Mon Sep 17 00:00:00 2001 From: Andy Gross Date: Fri, 10 Jun 2016 17:15:28 -0500 Subject: ARM: dts: qcom: msm8974-honami: Set DMA as remotely controlled This patch adds the qcom,controlled-remotely property for the blsp2_bam controller node. This board requires this, otherwise the board fails to boot due to access of protected registers during BAM initialization. Fixes: 62bc81792223 dts: msm8974: Add blsp2_bam dma node Signed-off-by: Andy Gross Acked-by: Bjorn Andersson diff --git a/arch/arm/boot/dts/qcom-msm8974-sony-xperia-honami.dts b/arch/arm/boot/dts/qcom-msm8974-sony-xperia-honami.dts index a0398b6..3fb4dad 100644 --- a/arch/arm/boot/dts/qcom-msm8974-sony-xperia-honami.dts +++ b/arch/arm/boot/dts/qcom-msm8974-sony-xperia-honami.dts @@ -367,6 +367,10 @@ }; }; + + dma-controller@f9944000 { + qcom,controlled-remotely; + }; }; &spmi_bus { -- cgit v0.10.2 From 30f1e2dde68d22022a77a9c1c4ddfdcf2fc3b4f3 Mon Sep 17 00:00:00 2001 From: Andy Gross Date: Sun, 12 Jun 2016 01:20:11 -0500 Subject: arm: dts: qcom: Update smem state cells usage This patch updates the qcom,state-cells to qcom,smem-state-cells to match recent changes to the binding. Signed-off-by: Andy Gross diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index ce7ce84..906bb81 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -177,7 +177,7 @@ apps_smsm: apps@0 { reg = <0>; - #qcom,state-cells = <1>; + #qcom,smem-state-cells = <1>; }; modem_smsm: modem@1 { diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index 55328d6..561d4d1 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -182,7 +182,7 @@ modem_smp2p_out: master-kernel { qcom,entry-name = "master-kernel"; - #qcom,state-cells = <1>; + #qcom,smem-state-cells = <1>; }; modem_smp2p_in: slave-kernel { @@ -208,7 +208,7 @@ wcnss_smp2p_out: master-kernel { qcom,entry-name = "master-kernel"; - #qcom,state-cells = <1>; + #qcom,smem-state-cells = <1>; }; wcnss_smp2p_in: slave-kernel { @@ -232,7 +232,7 @@ apps_smsm: apps@0 { reg = <0>; - #qcom,state-cells = <1>; + #qcom,smem-state-cells = <1>; }; modem_smsm: modem@1 { -- cgit v0.10.2 From 72f3cd64dccf663b0a1705bf215987cd5a2a11d2 Mon Sep 17 00:00:00 2001 From: John Stultz Date: Tue, 26 Apr 2016 10:44:13 -0700 Subject: device-tree: nexus7: Remove power gpio key entry and use pmic8xxx-pwrkey Since the pmic8xxx-pwrkey driver is already supported in the qcom-apq8064.dtsi, and the pmic8xxx-pwrkey supports logic to configure proper device shutdown when ps_hold goes low, it is better to use that driver then a generic gpio button. Thus this patch remove the gpio power key entry here, so we don't get double input events from having two drivers enabled. Cc: Rob Herring Cc: Andy Gross Cc: Bjorn Andersson Cc: Stephen Boyd Cc: linux-arm-msm@vger.kernel.org Cc: devicetree@vger.kernel.org Acked-by: Rob Herring Acked-by: Bjorn Andersson Signed-off-by: John Stultz Signed-off-by: Andy Gross diff --git a/arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts b/arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts index 32fedfa..7b05f07 100644 --- a/arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts +++ b/arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts @@ -29,12 +29,6 @@ gpio-keys { compatible = "gpio-keys"; - power { - label = "Power"; - gpios = <&tlmm_pinmux 26 GPIO_ACTIVE_LOW>; - linux,code = ; - gpio-key,wakeup; - }; volume_up { label = "Volume Up"; gpios = <&pm8921_gpio 4 GPIO_ACTIVE_HIGH>; -- cgit v0.10.2 From 0840ea9e4457abedf92d3a89ab372fbb091e7a3c Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Fri, 17 Jun 2016 22:28:05 +0200 Subject: ARM: dts: add GPIO and MPP to MSM8660 PMIC This adds the 8660 PMIC GPIO and MPP blocks to the MSM8660 DTSI. Verified against the vendor tree to be in these locations with these interrupts, tested on the APQ8060 Dragonboard. Reviewed-by: Stephen Boyd Signed-off-by: Linus Walleij Signed-off-by: Andy Gross diff --git a/arch/arm/boot/dts/qcom-msm8660.dtsi b/arch/arm/boot/dts/qcom-msm8660.dtsi index cd21403..6a62b62 100644 --- a/arch/arm/boot/dts/qcom-msm8660.dtsi +++ b/arch/arm/boot/dts/qcom-msm8660.dtsi @@ -143,6 +143,44 @@ #address-cells = <1>; #size-cells = <0>; + pm8058_gpio: gpio@150 { + compatible = "qcom,pm8058-gpio", + "qcom,ssbi-gpio"; + reg = <0x150>; + interrupt-parent = <&pmicintc>; + interrupts = <192 1>, <193 1>, <194 1>, + <195 1>, <196 1>, <197 1>, + <198 1>, <199 1>, <200 1>, + <201 1>, <202 1>, <203 1>, + <204 1>, <205 1>, <206 1>, + <207 1>, <208 1>, <209 1>, + <210 1>, <211 1>, <212 1>, + <213 1>, <214 1>, <215 1>, + <216 1>, <217 1>, <218 1>, + <219 1>, <220 1>, <221 1>, + <222 1>, <223 1>, <224 1>, + <225 1>, <226 1>, <227 1>, + <228 1>, <229 1>, <230 1>, + <231 1>, <232 1>, <233 1>, + <234 1>, <235 1>; + gpio-controller; + #gpio-cells = <2>; + + }; + + pm8058_mpps: mpps@50 { + compatible = "qcom,pm8058-mpp", + "qcom,ssbi-mpp"; + reg = <0x50>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&pmicintc>; + interrupts = + <128 1>, <129 1>, <130 1>, <131 1>, + <132 1>, <133 1>, <134 1>, <135 1>, + <136 1>, <137 1>, <138 1>, <139 1>; + }; + pwrkey@1c { compatible = "qcom,pm8058-pwrkey"; reg = <0x1c>; -- cgit v0.10.2 From 5f7610076e5bbfde4b837c018a674170bcb26a92 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Fri, 17 Jun 2016 22:28:06 +0200 Subject: ARM: dts: add SDCC5 to Qualcomm MSM8660 The SDCC5 SD/MMC controller is used for a second uSD slot on the APQ8060 Dragonboard. On most other systems it is just dark silicon so define it and leave it as "disabled" in the core SoC file. Reviewed-by: Stephen Boyd Signed-off-by: Linus Walleij Signed-off-by: Andy Gross diff --git a/arch/arm/boot/dts/qcom-msm8660.dtsi b/arch/arm/boot/dts/qcom-msm8660.dtsi index 6a62b62..a5a3882 100644 --- a/arch/arm/boot/dts/qcom-msm8660.dtsi +++ b/arch/arm/boot/dts/qcom-msm8660.dtsi @@ -262,6 +262,22 @@ no-1-8-v; vmmc-supply = <&vsdcc_fixed>; }; + + sdcc5: sdcc@12200000 { + compatible = "arm,pl18x", "arm,primecell"; + arm,primecell-periphid = <0x00051180>; + status = "disabled"; + reg = <0x12200000 0x8000>; + interrupts = ; + interrupt-names = "cmd_irq"; + clocks = <&gcc SDC5_CLK>, <&gcc SDC5_H_CLK>; + clock-names = "mclk", "apb_pclk"; + bus-width = <4>; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency = <48000000>; + vmmc-supply = <&vsdcc_fixed>; + }; }; tcsr: syscon@1a400000 { -- cgit v0.10.2 From 30b4fb1cc40a0ee35f84e2431cadfe9ced40076a Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Fri, 17 Jun 2016 22:28:07 +0200 Subject: ARM: dts: add L2CC and RPM with regulators for MSM8660 This adds the L2CC IPC resource and RPM devices plus the nodes for the PM8901 and PM8058 regulators to the MSM8660 device tree. This was tested on the APQ8060 Dragonboard. Signed-off-by: Linus Walleij Reviewed-by: Stephen Boyd Signed-off-by: Andy Gross diff --git a/arch/arm/boot/dts/qcom-msm8660.dtsi b/arch/arm/boot/dts/qcom-msm8660.dtsi index a5a3882..e7c6e29 100644 --- a/arch/arm/boot/dts/qcom-msm8660.dtsi +++ b/arch/arm/boot/dts/qcom-msm8660.dtsi @@ -215,6 +215,95 @@ }; }; + l2cc: clock-controller@2082000 { + compatible = "syscon"; + reg = <0x02082000 0x1000>; + }; + + rpm: rpm@104000 { + compatible = "qcom,rpm-msm8660"; + reg = <0x00104000 0x1000>; + qcom,ipc = <&l2cc 0x8 2>; + + interrupts = , + , + ; + interrupt-names = "ack", "err", "wakeup"; + clocks = <&gcc RPM_MSG_RAM_H_CLK>; + clock-names = "ram"; + + rpmcc: clock-controller { + compatible = "qcom,rpmcc-apq8660", "qcom,rpmcc"; + #clock-cells = <1>; + }; + + pm8901-regulators { + compatible = "qcom,rpm-pm8901-regulators"; + + pm8901_l0: l0 {}; + pm8901_l1: l1 {}; + pm8901_l2: l2 {}; + pm8901_l3: l3 {}; + pm8901_l4: l4 {}; + pm8901_l5: l5 {}; + pm8901_l6: l6 {}; + + /* S0 and S1 Handled as SAW regulators by SPM */ + pm8901_s2: s2 {}; + pm8901_s3: s3 {}; + pm8901_s4: s4 {}; + + pm8901_lvs0: lvs0 {}; + pm8901_lvs1: lvs1 {}; + pm8901_lvs2: lvs2 {}; + pm8901_lvs3: lvs3 {}; + + pm8901_mvs: mvs {}; + }; + + pm8058-regulators { + compatible = "qcom,rpm-pm8058-regulators"; + + pm8058_l0: l0 {}; + pm8058_l1: l1 {}; + pm8058_l2: l2 {}; + pm8058_l3: l3 {}; + pm8058_l4: l4 {}; + pm8058_l5: l5 {}; + pm8058_l6: l6 {}; + pm8058_l7: l7 {}; + pm8058_l8: l8 {}; + pm8058_l9: l9 {}; + pm8058_l10: l10 {}; + pm8058_l11: l11 {}; + pm8058_l12: l12 {}; + pm8058_l13: l13 {}; + pm8058_l14: l14 {}; + pm8058_l15: l15 {}; + pm8058_l16: l16 {}; + pm8058_l17: l17 {}; + pm8058_l18: l18 {}; + pm8058_l19: l19 {}; + pm8058_l20: l20 {}; + pm8058_l21: l21 {}; + pm8058_l22: l22 {}; + pm8058_l23: l23 {}; + pm8058_l24: l24 {}; + pm8058_l25: l25 {}; + + pm8058_s0: s0 {}; + pm8058_s1: s1 {}; + pm8058_s2: s2 {}; + pm8058_s3: s3 {}; + pm8058_s4: s4 {}; + + pm8058_lvs0: lvs0 {}; + pm8058_lvs1: lvs1 {}; + + pm8058_ncp: ncp {}; + }; + }; + /* Temporary fixed regulator */ vsdcc_fixed: vsdcc-regulator { compatible = "regulator-fixed"; -- cgit v0.10.2 From c51cb1a15676daed1d1a7fc8a0f2d1e3ae125361 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Fri, 17 Jun 2016 22:28:09 +0200 Subject: ARM: dts: add I2C block in GSBI12 The I2C block on the GSBI12 is used on the APQ8060 Dragonboard for sensors. Make it available in the chipset file. Take this opportunity to fix the IRQ flag "0" to "NONE" using the IRQ DT include. Signed-off-by: Linus Walleij Signed-off-by: Andy Gross diff --git a/arch/arm/boot/dts/qcom-msm8660.dtsi b/arch/arm/boot/dts/qcom-msm8660.dtsi index e7c6e29..8ee3045 100644 --- a/arch/arm/boot/dts/qcom-msm8660.dtsi +++ b/arch/arm/boot/dts/qcom-msm8660.dtsi @@ -122,11 +122,22 @@ compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; reg = <0x19c40000 0x1000>, <0x19c00000 0x1000>; - interrupts = <0 195 0x0>; + interrupts = <0 195 IRQ_TYPE_NONE>; clocks = <&gcc GSBI12_UART_CLK>, <&gcc GSBI12_H_CLK>; clock-names = "core", "iface"; status = "disabled"; }; + + gsbi12_i2c: i2c@19c80000 { + compatible = "qcom,i2c-qup-v1.1.1"; + reg = <0x19c80000 0x1000>; + interrupts = <0 196 IRQ_TYPE_NONE>; + clocks = <&gcc GSBI12_QUP_CLK>, <&gcc GSBI12_H_CLK>; + clock-names = "core", "iface"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; }; qcom,ssbi@500000 { -- cgit v0.10.2 From e20fd3364c0222a582cb45e061c677e232116236 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Fri, 17 Jun 2016 22:28:10 +0200 Subject: ARM: dts: fix the MSM8660 RTC base address The RTC was defined on 0x11d but on the MSM8660/APQ8060 it is actually on 0x1e8. We were saved by the fact that the driver does not use the reg parameter: instead it uses the compatible string to figure out where the RTC is. Signed-off-by: Linus Walleij Reviewed-by: Stephen Boyd Signed-off-by: Andy Gross diff --git a/arch/arm/boot/dts/qcom-msm8660.dtsi b/arch/arm/boot/dts/qcom-msm8660.dtsi index 8ee3045..b7d7f0c 100644 --- a/arch/arm/boot/dts/qcom-msm8660.dtsi +++ b/arch/arm/boot/dts/qcom-msm8660.dtsi @@ -211,11 +211,11 @@ row-hold = <91500>; }; - rtc@11d { + rtc@1e8 { compatible = "qcom,pm8058-rtc"; + reg = <0x1e8>; interrupt-parent = <&pmicintc>; interrupts = <39 1>; - reg = <0x11d>; allow-set-time; }; -- cgit v0.10.2 From 1758b35808ce451b6c1bca05d60031fbcf3cb5ca Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Fri, 17 Jun 2016 22:28:11 +0200 Subject: ARM: dts: move the fixed MMC regulator to SURF board There is currently a fixed regulator in the .dtsi file for the MSM8660 chipset, used by the SURF board. We want to define real regulators for a board using this chipset, so push the fixed regulator down to the SURF board which is the only user. Reviewed-by: Stephen Boyd Signed-off-by: Linus Walleij Signed-off-by: Andy Gross diff --git a/arch/arm/boot/dts/qcom-msm8660-surf.dts b/arch/arm/boot/dts/qcom-msm8660-surf.dts index b17f379..23de764 100644 --- a/arch/arm/boot/dts/qcom-msm8660-surf.dts +++ b/arch/arm/boot/dts/qcom-msm8660-surf.dts @@ -23,15 +23,26 @@ }; }; + /* Temporary fixed regulator */ + vsdcc_fixed: vsdcc-regulator { + compatible = "regulator-fixed"; + regulator-name = "SDCC Power"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + regulator-always-on; + }; + amba { /* eMMC */ sdcc1: sdcc@12400000 { status = "okay"; + vmmc-supply = <&vsdcc_fixed>; }; /* External micro SD card */ sdcc3: sdcc@12180000 { status = "okay"; + vmmc-supply = <&vsdcc_fixed>; }; }; }; diff --git a/arch/arm/boot/dts/qcom-msm8660.dtsi b/arch/arm/boot/dts/qcom-msm8660.dtsi index b7d7f0c..acbe71f 100644 --- a/arch/arm/boot/dts/qcom-msm8660.dtsi +++ b/arch/arm/boot/dts/qcom-msm8660.dtsi @@ -315,15 +315,6 @@ }; }; - /* Temporary fixed regulator */ - vsdcc_fixed: vsdcc-regulator { - compatible = "regulator-fixed"; - regulator-name = "SDCC Power"; - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2700000>; - regulator-always-on; - }; - amba { compatible = "simple-bus"; #address-cells = <1>; @@ -343,7 +334,6 @@ non-removable; cap-sd-highspeed; cap-mmc-highspeed; - vmmc-supply = <&vsdcc_fixed>; }; sdcc3: sdcc@12180000 { @@ -360,7 +350,6 @@ cap-mmc-highspeed; max-frequency = <48000000>; no-1-8-v; - vmmc-supply = <&vsdcc_fixed>; }; sdcc5: sdcc@12200000 { @@ -376,7 +365,6 @@ cap-sd-highspeed; cap-mmc-highspeed; max-frequency = <48000000>; - vmmc-supply = <&vsdcc_fixed>; }; }; -- cgit v0.10.2 From 4892e0756c65d6e248e7e8ff94845e8e26bcf896 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Fri, 17 Jun 2016 22:28:12 +0200 Subject: ARM: dts: add Qualcomm APQ8060-based Dragonboard This is the first Dragonboard based on APQ8060 and PM8058. It was produced in 2011 in cooperation between Qualcomm and BSQUARE. Signed-off-by: Linus Walleij Signed-off-by: Andy Gross diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 5b7c17a..b359dce 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -572,6 +572,7 @@ dtb-$(CONFIG_ARCH_PRIMA2) += \ dtb-$(CONFIG_ARCH_OXNAS) += \ wd-mbwe.dtb dtb-$(CONFIG_ARCH_QCOM) += \ + qcom-apq8060-dragonboard.dtb \ qcom-apq8064-arrow-sd-600eval.dtb \ qcom-apq8064-cm-qs600.dtb \ qcom-apq8064-ifc6410.dtb \ diff --git a/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts b/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts new file mode 100644 index 0000000..0abc93e --- /dev/null +++ b/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts @@ -0,0 +1,626 @@ +/* + * Copyright 2016 Linaro Ltd + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include +#include +#include +#include "qcom-msm8660.dtsi" + +/ { + model = "Qualcomm APQ8060 Dragonboard"; + compatible = "qcom,apq8060-dragonboard", "qcom,msm8660"; + + aliases { + serial0 = &gsbi12_serial; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + regulators { + compatible = "simple-bus"; + + /* Main power of the board: 3.7V */ + vph: regulator-fixed { + compatible = "regulator-fixed"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + regulator-name = "VPH"; + regulator-type = "voltage"; + regulator-always-on; + regulator-boot-on; + }; + + /* This is a levelshifter for SDCC5 */ + dragon_vio_txb: txb0104rgyr { + compatible = "regulator-fixed"; + regulator-name = "Dragon SDCC levelshifter"; + vin-supply = <&pm8058_l14>; + regulator-always-on; + }; + }; + + soc { + pinctrl@800000 { + /* eMMMC pins, all 8 data lines connected */ + dragon_sdcc1_pins: sdcc1 { + mux { + pins = "gpio159", "gpio160", "gpio161", + "gpio162", "gpio163", "gpio164", + "gpio165", "gpio166", "gpio167", + "gpio168"; + function = "sdc1"; + }; + clk { + pins = "gpio167"; /* SDC5 CLK */ + drive-strength = <16>; + bias-disable; + }; + cmd { + pins = "gpio168"; /* SDC5 CMD */ + drive-strength = <10>; + bias-pull-up; + }; + data { + /* SDC5 D0 to D7 */ + pins = "gpio159", "gpio160", "gpio161", "gpio162", + "gpio163", "gpio164", "gpio165", "gpio166"; + drive-strength = <10>; + bias-pull-up; + }; + }; + + /* + * The SDCC3 pins are hardcoded (non-muxable) but need some pin + * configuration. + */ + dragon_sdcc3_pins: sdcc3 { + clk { + pins = "sdc3_clk"; + drive-strength = <8>; + bias-disable; + }; + cmd { + pins = "sdc3_cmd"; + drive-strength = <8>; + bias-pull-up; + }; + data { + pins = "sdc3_data"; + drive-strength = <8>; + bias-pull-up; + }; + }; + + /* Second SD card slot pins */ + dragon_sdcc5_pins: sdcc5 { + mux { + pins = "gpio95", "gpio96", "gpio97", + "gpio98", "gpio99", "gpio100"; + function = "sdc5"; + }; + clk { + pins = "gpio97"; /* SDC5 CLK */ + drive-strength = <16>; + bias-disable; + }; + cmd { + pins = "gpio95"; /* SDC5 CMD */ + drive-strength = <10>; + bias-pull-up; + }; + data { + /* SDC5 D0 to D3 */ + pins = "gpio96", "gpio98", "gpio99", "gpio100"; + drive-strength = <10>; + bias-pull-up; + }; + }; + + dragon_gsbi12_i2c_pins: gsbi12_i2c { + mux { + pins = "gpio115", "gpio116"; + function = "gsbi12"; + }; + pinconf { + pins = "gpio115", "gpio116"; + drive-strength = <16>; + /* These have external pull-up 4.7kOhm to 1.8V */ + bias-disable; + }; + }; + + /* Primary serial port uart 0 pins */ + dragon_gsbi12_serial_pins: gsbi12_serial { + mux { + pins = "gpio117", "gpio118"; + function = "gsbi12"; + }; + tx { + pins = "gpio117"; + drive-strength = <8>; + bias-disable; + }; + rx { + pins = "gpio118"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + qcom,ssbi@500000 { + pmic@0 { + keypad@148 { + linux,keymap = < + MATRIX_KEY(0, 0, KEY_MENU) + MATRIX_KEY(0, 2, KEY_1) + MATRIX_KEY(0, 3, KEY_4) + MATRIX_KEY(0, 4, KEY_7) + MATRIX_KEY(1, 0, KEY_UP) + MATRIX_KEY(1, 1, KEY_LEFT) + MATRIX_KEY(1, 2, KEY_DOWN) + MATRIX_KEY(1, 3, KEY_5) + MATRIX_KEY(1, 3, KEY_8) + MATRIX_KEY(2, 0, KEY_HOME) + MATRIX_KEY(2, 1, KEY_REPLY) + MATRIX_KEY(2, 2, KEY_2) + MATRIX_KEY(2, 3, KEY_6) + MATRIX_KEY(3, 0, KEY_VOLUMEUP) + MATRIX_KEY(3, 1, KEY_RIGHT) + MATRIX_KEY(3, 2, KEY_3) + MATRIX_KEY(3, 3, KEY_9) + MATRIX_KEY(3, 4, KEY_SWITCHVIDEOMODE) + MATRIX_KEY(4, 0, KEY_VOLUMEDOWN) + MATRIX_KEY(4, 1, KEY_BACK) + MATRIX_KEY(4, 2, KEY_CAMERA) + MATRIX_KEY(4, 3, KEY_KBDILLUMTOGGLE) + >; + keypad,num-rows = <6>; + keypad,num-columns = <5>; + }; + + gpio@150 { + dragon_bmp085_gpios: bmp085-gpios { + pinconf { + pins = "gpio16"; + function = "normal"; + input-enable; + bias-disable; + power-source = ; + }; + }; + dragon_sdcc3_gpios: sdcc3-gpios { + pinconf { + pins = "gpio22"; + function = "normal"; + input-enable; + bias-disable; + power-source = ; + }; + }; + dragon_sdcc5_gpios: sdcc5-gpios { + pinconf { + pins = "gpio26"; + function = "normal"; + input-enable; + bias-pull-up; + qcom,pull-up-strength = ; + power-source = ; + }; + }; + dragon_ak8975_gpios: ak8975-gpios { + pinconf { + pins = "gpio33"; + function = "normal"; + input-enable; + bias-disable; + power-source = ; + }; + }; + }; + }; + }; + + gsbi@19c00000 { + status = "ok"; + qcom,mode = ; + + serial@19c40000 { + status = "ok"; + pinctrl-names = "default"; + pinctrl-0 = <&dragon_gsbi12_serial_pins>; + }; + + i2c@19c80000 { + status = "ok"; + pinctrl-names = "default"; + pinctrl-0 = <&dragon_gsbi12_i2c_pins>; + + ak8975@0c { + compatible = "asahi-kasei,ak8975"; + reg = <0x0c>; + /* GPIO33 has interrupt 224 on the PM8058 */ + interrupt-parent = <&pm8058_gpio>; + interrupts = <224 IRQ_TYPE_EDGE_RISING>; + pinctrl-names = "default"; + pinctrl-0 = <&dragon_ak8975_gpios>; + vid-supply = <&pm8058_lvs0>; // 1.8V + vdd-supply = <&pm8058_l14>; // 2.85V + }; + bmp085@77 { + compatible = "bosch,bmp085"; + reg = <0x77>; + /* GPIO16 has interrupt 207 on the PM8058 */ + interrupt-parent = <&pm8058_gpio>; + interrupts = <207 IRQ_TYPE_EDGE_RISING>; + reset-gpios = <&tlmm 86 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&dragon_bmp085_gpios>; + vddd-supply = <&pm8058_lvs0>; // 1.8V + vdda-supply = <&pm8058_l14>; // 2.85V + }; + }; + }; + + rpm@104000 { + /* + * Set up of the PMIC RPM regulators for this board + * PM8901 supplies "preliminary regulators" whatever + * that means + */ + pm8901-regulators { + vdd_l0-supply = <&pm8901_s4>; + vdd_l1-supply = <&vph>; + vdd_l2-supply = <&vph>; + vdd_l3-supply = <&vph>; + vdd_l4-supply = <&vph>; + vdd_l5-supply = <&vph>; + vdd_l6-supply = <&vph>; + /* vdd_s0-supply, vdd_s1-supply: SAW regulators */ + vdd_s2-supply = <&vph>; + vdd_s3-supply = <&vph>; + vdd_s4-supply = <&vph>; + lvs0_in-supply = <&pm8058_s3>; + lvs1_in-supply = <&pm8901_s4>; + lvs2_in-supply = <&pm8058_l0>; + lvs3_in-supply = <&pm8058_s2>; + mvs_in-supply = <&pm8058_s3>; + + l0 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + bias-pull-down; + }; + l1 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + bias-pull-down; + }; + l2 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3300000>; + bias-pull-down; + }; + l3 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + bias-pull-down; + }; + l4 { + regulator-min-microvolt = <2600000>; + regulator-max-microvolt = <2600000>; + bias-pull-down; + }; + l5 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + bias-pull-down; + }; + l6 { + regulator-min-microvolt = <2200000>; + regulator-max-microvolt = <2200000>; + bias-pull-down; + }; + + /* s0 and s1 are SAW regulators controlled over SPM */ + s2 { + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + qcom,switch-mode-frequency = <1600000>; + bias-pull-down; + }; + s3 { + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + qcom,switch-mode-frequency = <1600000>; + bias-pull-down; + }; + s4 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + qcom,switch-mode-frequency = <1600000>; + bias-pull-down; + }; + + /* LVS0 thru 3 and mvs0 are just switches */ + lvs0 { + regulator-always-on; + }; + lvs1 { }; + lvs2 { }; + lvs3 { }; + mvs0 {}; + + }; + + pm8058-regulators { + vdd_l0_l1_lvs-supply = <&pm8058_s3>; + vdd_l2_l11_l12-supply = <&vph>; + vdd_l3_l4_l5-supply = <&vph>; + vdd_l6_l7-supply = <&vph>; + vdd_l8-supply = <&vph>; + vdd_l9-supply = <&vph>; + vdd_l10-supply = <&vph>; + vdd_l13_l16-supply = <&pm8058_s4>; + vdd_l14_l15-supply = <&vph>; + vdd_l17_l18-supply = <&vph>; + vdd_l19_l20-supply = <&vph>; + vdd_l21-supply = <&pm8058_s3>; + vdd_l22-supply = <&pm8058_s3>; + vdd_l23_l24_l25-supply = <&pm8058_s3>; + vdd_s0-supply = <&vph>; + vdd_s1-supply = <&vph>; + vdd_s2-supply = <&vph>; + vdd_s3-supply = <&vph>; + vdd_s4-supply = <&vph>; + vdd_ncp-supply = <&vph>; + + l0 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + bias-pull-down; + }; + l1 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + bias-pull-down; + }; + l2 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2600000>; + bias-pull-down; + }; + l3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + bias-pull-down; + }; + l4 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + bias-pull-down; + }; + l5 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + bias-pull-down; + }; + l6 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3600000>; + bias-pull-down; + }; + l7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + bias-pull-down; + }; + l8 { + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <3050000>; + bias-pull-down; + }; + l9 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + bias-pull-down; + }; + l10 { + regulator-min-microvolt = <2600000>; + regulator-max-microvolt = <2600000>; + bias-pull-down; + }; + l11 { + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + bias-pull-down; + }; + l12 { + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + bias-pull-down; + }; + l13 { + regulator-min-microvolt = <2050000>; + regulator-max-microvolt = <2050000>; + bias-pull-down; + }; + l14 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; + l15 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + bias-pull-down; + }; + l16 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + bias-pull-down; + regulator-always-on; + }; + l17 { + // 1.5V according to schematic + regulator-min-microvolt = <2600000>; + regulator-max-microvolt = <2600000>; + bias-pull-down; + }; + l18 { + regulator-min-microvolt = <2200000>; + regulator-max-microvolt = <2200000>; + bias-pull-down; + }; + l19 { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + bias-pull-down; + }; + l20 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + bias-pull-down; + }; + l21 { + // 1.1 V according to schematic + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + bias-pull-down; + regulator-always-on; + }; + l22 { + // 1.2 V according to schematic + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1150000>; + bias-pull-down; + }; + l23 { + // Unused + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + bias-pull-down; + }; + l24 { + // Unused + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + bias-pull-down; + }; + l25 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + bias-pull-down; + }; + + s0 { + // regulator-min-microvolt = <500000>; + // regulator-max-microvolt = <1325000>; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + qcom,switch-mode-frequency = <1600000>; + bias-pull-down; + }; + s1 { + // regulator-min-microvolt = <500000>; + // regulator-max-microvolt = <1250000>; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + qcom,switch-mode-frequency = <1600000>; + bias-pull-down; + }; + s2 { + // 1.3 V according to schematic + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1400000>; + qcom,switch-mode-frequency = <1600000>; + bias-pull-down; + }; + s3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,switch-mode-frequency = <1600000>; + regulator-always-on; + bias-pull-down; + }; + s4 { + regulator-min-microvolt = <2200000>; + regulator-max-microvolt = <2200000>; + qcom,switch-mode-frequency = <1600000>; + regulator-always-on; + bias-pull-down; + }; + + /* LVS0 and LVS1 are just switches */ + lvs0 { + bias-pull-down; + }; + lvs1 { + bias-pull-down; + }; + + ncp { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,switch-mode-frequency = <1600000>; + }; + }; + }; + amba { + /* Internal 3.69 GiB eMMC */ + sdcc@12400000 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&dragon_sdcc1_pins>; + vmmc-supply = <&pm8901_l5>; + vqmmc-supply = <&pm8901_lvs0>; + }; + + /* External micro SD card, directly connected, pulled up to 2.85 V */ + sdcc@12180000 { + status = "okay"; + /* Enable SSBI GPIO 22 as input, use for card detect */ + pinctrl-names = "default"; + pinctrl-0 = <&dragon_sdcc3_pins>, <&dragon_sdcc3_gpios>; + cd-gpios = <&pm8058_gpio 22 GPIO_ACTIVE_LOW>; + wp-gpios = <&tlmm 110 GPIO_ACTIVE_HIGH>; + vmmc-supply = <&pm8058_l14>; + }; + + /* + * Second external micro SD card, using two TXB104RGYR levelshifters + * to lift from 1.8 V to 2.85 V + */ + sdcc@12200000 { + status = "okay"; + /* Enable SSBI GPIO 26 as input, use for card detect */ + pinctrl-names = "default"; + pinctrl-0 = <&dragon_sdcc5_pins>, <&dragon_sdcc5_gpios>; + cd-gpios = <&pm8058_gpio 26 GPIO_ACTIVE_LOW>; + wp-gpios = <&tlmm 106 GPIO_ACTIVE_HIGH>; + vmmc-supply = <&pm8058_l14>; + vqmmc-supply = <&dragon_vio_txb>; + }; + }; + }; +}; -- cgit v0.10.2 From c3d5313001b0c8e9f70807e58438c3dcd30a4817 Mon Sep 17 00:00:00 2001 From: "twp@codeaurora.org" Date: Mon, 20 Jun 2016 11:19:23 -0700 Subject: dts: ipq4019: support ARMv7 PMU Add support for cortex-a7-pmu present on ipq4019 SoCs. Signed-off-by: Thomas Pedersen Signed-off-by: Andy Gross diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi index 5c08d19..a520ef5 100644 --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi @@ -84,6 +84,12 @@ }; }; + pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts = ; + }; + clocks { sleep_clk: sleep_clk { compatible = "fixed-clock"; -- cgit v0.10.2 From fe4b467da62a1541ff9d7f7479e5a1d3787154b5 Mon Sep 17 00:00:00 2001 From: Ken Lin Date: Wed, 22 Jun 2016 10:25:56 -0400 Subject: ARM: dts: imx6q-bx50v3: Add gpio power off support bx50v3 boards can be powered off via GPIO, this patch specifies the GPIO to be used with the gpio-poweroff driver. Signed-off-by: Ken Lin Signed-off-by: Akshay Bhat Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/imx6q-bx50v3.dtsi b/arch/arm/boot/dts/imx6q-bx50v3.dtsi index bb66dfd..cf3fd31 100644 --- a/arch/arm/boot/dts/imx6q-bx50v3.dtsi +++ b/arch/arm/boot/dts/imx6q-bx50v3.dtsi @@ -52,6 +52,12 @@ }; }; + gpio-poweroff { + compatible = "gpio-poweroff"; + gpios = <&gpio4 11 GPIO_ACTIVE_LOW>; + status = "okay"; + }; + reg_wl18xx_vmmc: regulator-wl18xx { compatible = "regulator-fixed"; regulator-name = "vwl1807"; -- cgit v0.10.2 From b754af313fb4997552809cc8d47d1e0b2b8455ec Mon Sep 17 00:00:00 2001 From: Diego Dorta Date: Wed, 22 Jun 2016 16:37:07 -0300 Subject: ARM: dts: imx7d: Add SPI support Add ecspi nodes and aliases. Signed-off-by: Diego Dorta Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/imx7d.dtsi b/arch/arm/boot/dts/imx7d.dtsi index d70d55d..9f088a8 100644 --- a/arch/arm/boot/dts/imx7d.dtsi +++ b/arch/arm/boot/dts/imx7d.dtsi @@ -69,6 +69,10 @@ serial4 = &uart5; serial5 = &uart6; serial6 = &uart7; + spi0 = &ecspi1; + spi1 = &ecspi2; + spi2 = &ecspi3; + spi3 = &ecspi4; }; cpus { @@ -608,6 +612,18 @@ status = "disabled"; }; + ecspi4: ecspi@30630000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi"; + reg = <0x30630000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_ECSPI4_ROOT_CLK>, + <&clks IMX7D_ECSPI4_ROOT_CLK>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + pwm1: pwm@30660000 { compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm"; reg = <0x30660000 0x10000>; @@ -671,6 +687,42 @@ reg = <0x30800000 0x400000>; ranges; + ecspi1: ecspi@30820000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi"; + reg = <0x30820000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_ECSPI1_ROOT_CLK>, + <&clks IMX7D_ECSPI1_ROOT_CLK>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + ecspi2: ecspi@30830000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi"; + reg = <0x30830000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_ECSPI2_ROOT_CLK>, + <&clks IMX7D_ECSPI2_ROOT_CLK>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + ecspi3: ecspi@30840000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi"; + reg = <0x30840000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_ECSPI3_ROOT_CLK>, + <&clks IMX7D_ECSPI3_ROOT_CLK>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + uart1: serial@30860000 { compatible = "fsl,imx7d-uart", "fsl,imx6q-uart"; -- cgit v0.10.2 From 419690556fc4697aedfeecd19ba6aff8f6be38a2 Mon Sep 17 00:00:00 2001 From: Diego Dorta Date: Wed, 22 Jun 2016 16:37:08 -0300 Subject: ARM: dts: imx7d-sdb: Add display support Add support for the LCD8000-43T display. Signed-off-by: Diego Dorta Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/imx7d-sdb.dts b/arch/arm/boot/dts/imx7d-sdb.dts index d6da506..8f6a539 100644 --- a/arch/arm/boot/dts/imx7d-sdb.dts +++ b/arch/arm/boot/dts/imx7d-sdb.dts @@ -272,6 +272,44 @@ }; }; +&lcdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdif>; + display = <&display0>; + status = "okay"; + + display0: display { + bits-per-pixel = <16>; + bus-width = <24>; + + display-timings { + native-mode = <&timing0>; + + timing0: timing0 { + clock-frequency = <9200000>; + hactive = <480>; + vactive = <272>; + hfront-porch = <8>; + hback-porch = <4>; + hsync-len = <41>; + vback-porch = <2>; + vfront-porch = <4>; + vsync-len = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + }; + }; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; @@ -396,6 +434,46 @@ >; }; + pinctrl_lcdif: lcdifgrp { + fsl,pins = < + MX7D_PAD_LCD_DATA00__LCD_DATA0 0x79 + MX7D_PAD_LCD_DATA01__LCD_DATA1 0x79 + MX7D_PAD_LCD_DATA02__LCD_DATA2 0x79 + MX7D_PAD_LCD_DATA03__LCD_DATA3 0x79 + MX7D_PAD_LCD_DATA04__LCD_DATA4 0x79 + MX7D_PAD_LCD_DATA05__LCD_DATA5 0x79 + MX7D_PAD_LCD_DATA06__LCD_DATA6 0x79 + MX7D_PAD_LCD_DATA07__LCD_DATA7 0x79 + MX7D_PAD_LCD_DATA08__LCD_DATA8 0x79 + MX7D_PAD_LCD_DATA09__LCD_DATA9 0x79 + MX7D_PAD_LCD_DATA10__LCD_DATA10 0x79 + MX7D_PAD_LCD_DATA11__LCD_DATA11 0x79 + MX7D_PAD_LCD_DATA12__LCD_DATA12 0x79 + MX7D_PAD_LCD_DATA13__LCD_DATA13 0x79 + MX7D_PAD_LCD_DATA14__LCD_DATA14 0x79 + MX7D_PAD_LCD_DATA15__LCD_DATA15 0x79 + MX7D_PAD_LCD_DATA16__LCD_DATA16 0x79 + MX7D_PAD_LCD_DATA17__LCD_DATA17 0x79 + MX7D_PAD_LCD_DATA18__LCD_DATA18 0x79 + MX7D_PAD_LCD_DATA19__LCD_DATA19 0x79 + MX7D_PAD_LCD_DATA20__LCD_DATA20 0x79 + MX7D_PAD_LCD_DATA21__LCD_DATA21 0x79 + MX7D_PAD_LCD_DATA22__LCD_DATA22 0x79 + MX7D_PAD_LCD_DATA23__LCD_DATA23 0x79 + MX7D_PAD_LCD_CLK__LCD_CLK 0x79 + MX7D_PAD_LCD_ENABLE__LCD_ENABLE 0x79 + MX7D_PAD_LCD_VSYNC__LCD_VSYNC 0x79 + MX7D_PAD_LCD_HSYNC__LCD_HSYNC 0x79 + MX7D_PAD_LCD_RESET__LCD_RESET 0x79 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX7D_PAD_GPIO1_IO01__PWM1_OUT 0x110b0 + >; + }; + pinctrl_uart1: uart1grp { fsl,pins = < MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79 -- cgit v0.10.2 From d09e6beafa231c0fb160c3b2bd4c03bef8429a72 Mon Sep 17 00:00:00 2001 From: Diego Dorta Date: Wed, 22 Jun 2016 16:37:09 -0300 Subject: ARM: dts: imx7d-sdb: Add support for touchscreen Add support for tsc2046 touchscreen. Signed-off-by: Diego Dorta Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/imx7d-sdb.dts b/arch/arm/boot/dts/imx7d-sdb.dts index 8f6a539..6bd8203 100644 --- a/arch/arm/boot/dts/imx7d-sdb.dts +++ b/arch/arm/boot/dts/imx7d-sdb.dts @@ -111,6 +111,32 @@ arm-supply = <&sw1a_reg>; }; +&ecspi3 { + fsl,spi-num-chipselects = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi3>; + cs-gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>; + status = "okay"; + + tsc2046@0 { + compatible = "ti,tsc2046"; + reg = <0>; + spi-max-frequency = <1000000>; + pinctrl-names ="default"; + pinctrl-0 = <&pinctrl_tsc2046_pendown>; + interrupt-parent = <&gpio2>; + interrupts = <29 0>; + pendown-gpio = <&gpio2 29 GPIO_ACTIVE_HIGH>; + ti,x-min = /bits/ 16 <0>; + ti,x-max = /bits/ 16 <0>; + ti,y-min = /bits/ 16 <0>; + ti,y-max = /bits/ 16 <0>; + ti,pressure-max = /bits/ 16 <0>; + ti,x-plat-ohms = /bits/ 16 <400>; + wakeup-source; + }; +}; + &fec1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet1>; @@ -363,6 +389,15 @@ pinctrl-0 = <&pinctrl_hog>; imx7d-sdb { + pinctrl_ecspi3: ecspi3grp { + fsl,pins = < + MX7D_PAD_SAI2_TX_SYNC__ECSPI3_MISO 0x2 + MX7D_PAD_SAI2_TX_BCLK__ECSPI3_MOSI 0x2 + MX7D_PAD_SAI2_RX_DATA__ECSPI3_SCLK 0x2 + MX7D_PAD_SD2_CD_B__GPIO5_IO9 0x59 + >; + }; + pinctrl_enet1: enet1grp { fsl,pins = < MX7D_PAD_GPIO1_IO10__ENET1_MDIO 0x3 @@ -474,6 +509,12 @@ >; }; + pinctrl_tsc2046_pendown: tsc2046_pendown { + fsl,pins = < + MX7D_PAD_EPDC_BDR1__GPIO2_IO29 0x59 + >; + }; + pinctrl_uart1: uart1grp { fsl,pins = < MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79 -- cgit v0.10.2 From 3ef79ca6bd1d6c79203f84c5cd876bcaa957f082 Mon Sep 17 00:00:00 2001 From: Stefan Agner Date: Sun, 26 Jun 2016 01:47:52 -0700 Subject: ARM: dts: imx7d: use imx7s.dtsi as base device tree The i.MX 7 series currently consists of two SoCs: i.MX 7Solo and 7Dual. The former has a subset of features of the latter, hence use imx7s.dtsi as the new base device tree. To keep diffstat nice, just move imx7d.dtsi to imx7s.dtsi temporarily and recreate imx7d.dtsi in a second commit. Signed-off-by: Stefan Agner Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/imx7d-cl-som-imx7.dts b/arch/arm/boot/dts/imx7d-cl-som-imx7.dts index 4863451..3942c7d 100644 --- a/arch/arm/boot/dts/imx7d-cl-som-imx7.dts +++ b/arch/arm/boot/dts/imx7d-cl-som-imx7.dts @@ -13,7 +13,7 @@ /dts-v1/; #include -#include "imx7d.dtsi" +#include "imx7s.dtsi" / { model = "CompuLab CL-SOM-iMX7"; diff --git a/arch/arm/boot/dts/imx7d-nitrogen7.dts b/arch/arm/boot/dts/imx7d-nitrogen7.dts index bef394e..8e993cb 100644 --- a/arch/arm/boot/dts/imx7d-nitrogen7.dts +++ b/arch/arm/boot/dts/imx7d-nitrogen7.dts @@ -43,7 +43,7 @@ /dts-v1/; #include -#include "imx7d.dtsi" +#include "imx7s.dtsi" / { model = "Boundary Devices i.MX7 Nitrogen7 Board"; diff --git a/arch/arm/boot/dts/imx7d-sdb.dts b/arch/arm/boot/dts/imx7d-sdb.dts index 6bd8203..8852a84 100644 --- a/arch/arm/boot/dts/imx7d-sdb.dts +++ b/arch/arm/boot/dts/imx7d-sdb.dts @@ -43,7 +43,7 @@ /dts-v1/; #include -#include "imx7d.dtsi" +#include "imx7s.dtsi" / { model = "Freescale i.MX7 SabreSD Board"; diff --git a/arch/arm/boot/dts/imx7d.dtsi b/arch/arm/boot/dts/imx7d.dtsi deleted file mode 100644 index 9f088a8..0000000 --- a/arch/arm/boot/dts/imx7d.dtsi +++ /dev/null @@ -1,1007 +0,0 @@ -/* - * Copyright 2015 Freescale Semiconductor, Inc. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include -#include -#include -#include "imx7d-pinfunc.h" -#include "skeleton.dtsi" - -/ { - aliases { - gpio0 = &gpio1; - gpio1 = &gpio2; - gpio2 = &gpio3; - gpio3 = &gpio4; - gpio4 = &gpio5; - gpio5 = &gpio6; - gpio6 = &gpio7; - i2c0 = &i2c1; - i2c1 = &i2c2; - i2c2 = &i2c3; - i2c3 = &i2c4; - mmc0 = &usdhc1; - mmc1 = &usdhc2; - mmc2 = &usdhc3; - serial0 = &uart1; - serial1 = &uart2; - serial2 = &uart3; - serial3 = &uart4; - serial4 = &uart5; - serial5 = &uart6; - serial6 = &uart7; - spi0 = &ecspi1; - spi1 = &ecspi2; - spi2 = &ecspi3; - spi3 = &ecspi4; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - reg = <0>; - operating-points = < - /* KHz uV */ - 996000 1075000 - 792000 975000 - >; - clock-latency = <61036>; /* two CLK32 periods */ - clocks = <&clks IMX7D_CLK_ARM>; - }; - - cpu1: cpu@1 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - reg = <1>; - }; - }; - - intc: interrupt-controller@31001000 { - compatible = "arm,cortex-a7-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x31001000 0x1000>, - <0x31002000 0x1000>, - <0x31004000 0x2000>, - <0x31006000 0x2000>; - }; - - ckil: clock-cki { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "ckil"; - }; - - osc: clock-osc { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - clock-output-names = "osc"; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = , - , - , - ; - interrupt-parent = <&intc>; - }; - - etr@30086000 { - compatible = "arm,coresight-tmc", "arm,primecell"; - reg = <0x30086000 0x1000>; - clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; - clock-names = "apb_pclk"; - - port { - etr_in_port: endpoint { - slave-mode; - remote-endpoint = <&replicator_out_port1>; - }; - }; - }; - - tpiu@30087000 { - compatible = "arm,coresight-tpiu", "arm,primecell"; - reg = <0x30087000 0x1000>; - clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; - clock-names = "apb_pclk"; - - port { - tpiu_in_port: endpoint { - slave-mode; - remote-endpoint = <&replicator_out_port1>; - }; - }; - }; - - replicator { - /* - * non-configurable replicators don't show up on the - * AMBA bus. As such no need to add "arm,primecell" - */ - compatible = "arm,coresight-replicator"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - /* replicator output ports */ - port@0 { - reg = <0>; - replicator_out_port0: endpoint { - remote-endpoint = <&tpiu_in_port>; - }; - }; - - port@1 { - reg = <1>; - replicator_out_port1: endpoint { - remote-endpoint = <&etr_in_port>; - }; - }; - - /* replicator input port */ - port@2 { - reg = <0>; - replicator_in_port0: endpoint { - slave-mode; - remote-endpoint = <&etf_out_port>; - }; - }; - }; - }; - - etf@30084000 { - compatible = "arm,coresight-tmc", "arm,primecell"; - reg = <0x30084000 0x1000>; - clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; - clock-names = "apb_pclk"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - etf_in_port: endpoint { - slave-mode; - remote-endpoint = <&hugo_funnel_out_port0>; - }; - }; - - port@1 { - reg = <0>; - etf_out_port: endpoint { - remote-endpoint = <&replicator_in_port0>; - }; - }; - }; - }; - - funnel@30083000 { - compatible = "arm,coresight-funnel", "arm,primecell"; - reg = <0x30083000 0x1000>; - clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; - clock-names = "apb_pclk"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - /* funnel input ports */ - port@0 { - reg = <0>; - hugo_funnel_in_port0: endpoint { - slave-mode; - remote-endpoint = <&ca_funnel_out_port0>; - }; - }; - - port@1 { - reg = <1>; - hugo_funnel_in_port1: endpoint { - slave-mode; /* M4 input */ - }; - }; - - port@2 { - reg = <0>; - hugo_funnel_out_port0: endpoint { - remote-endpoint = <&etf_in_port>; - }; - }; - - /* the other input ports are not connect to anything */ - }; - }; - - funnel@30041000 { - compatible = "arm,coresight-funnel", "arm,primecell"; - reg = <0x30041000 0x1000>; - clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; - clock-names = "apb_pclk"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - /* funnel input ports */ - port@0 { - reg = <0>; - ca_funnel_in_port0: endpoint { - slave-mode; - remote-endpoint = <&etm0_out_port>; - }; - }; - - port@1 { - reg = <1>; - ca_funnel_in_port1: endpoint { - slave-mode; - remote-endpoint = <&etm1_out_port>; - }; - }; - - /* funnel output port */ - port@2 { - reg = <0>; - ca_funnel_out_port0: endpoint { - remote-endpoint = <&hugo_funnel_in_port0>; - }; - }; - - /* the other input ports are not connect to anything */ - }; - }; - - etm@3007c000 { - compatible = "arm,coresight-etm3x", "arm,primecell"; - reg = <0x3007c000 0x1000>; - cpu = <&cpu0>; - clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; - clock-names = "apb_pclk"; - - port { - etm0_out_port: endpoint { - remote-endpoint = <&ca_funnel_in_port0>; - }; - }; - }; - - etm@3007d000 { - compatible = "arm,coresight-etm3x", "arm,primecell"; - reg = <0x3007d000 0x1000>; - - /* - * System will hang if added nosmp in kernel command line - * without arm,primecell-periphid because amba bus try to - * read id and core1 power off at this time. - */ - arm,primecell-periphid = <0xbb956>; - cpu = <&cpu1>; - clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; - clock-names = "apb_pclk"; - - port { - etm1_out_port: endpoint { - remote-endpoint = <&ca_funnel_in_port1>; - }; - }; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - interrupt-parent = <&intc>; - ranges; - - aips1: aips-bus@30000000 { - compatible = "fsl,aips-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x30000000 0x400000>; - ranges; - - gpio1: gpio@30200000 { - compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; - reg = <0x30200000 0x10000>; - interrupts = , /* GPIO1_INT15_0 */ - ; /* GPIO1_INT31_16 */ - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio@30210000 { - compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; - reg = <0x30210000 0x10000>; - interrupts = , - ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio3: gpio@30220000 { - compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; - reg = <0x30220000 0x10000>; - interrupts = , - ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio4: gpio@30230000 { - compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; - reg = <0x30230000 0x10000>; - interrupts = , - ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio5: gpio@30240000 { - compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; - reg = <0x30240000 0x10000>; - interrupts = , - ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio6: gpio@30250000 { - compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; - reg = <0x30250000 0x10000>; - interrupts = , - ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio7: gpio@30260000 { - compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; - reg = <0x30260000 0x10000>; - interrupts = , - ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - wdog1: wdog@30280000 { - compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt"; - reg = <0x30280000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_WDOG1_ROOT_CLK>; - }; - - wdog2: wdog@30290000 { - compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt"; - reg = <0x30290000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_WDOG2_ROOT_CLK>; - status = "disabled"; - }; - - wdog3: wdog@302a0000 { - compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt"; - reg = <0x302a0000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_WDOG3_ROOT_CLK>; - status = "disabled"; - }; - - wdog4: wdog@302b0000 { - compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt"; - reg = <0x302b0000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_WDOG4_ROOT_CLK>; - status = "disabled"; - }; - - iomuxc_lpsr: iomuxc-lpsr@302c0000 { - compatible = "fsl,imx7d-iomuxc-lpsr"; - reg = <0x302c0000 0x10000>; - fsl,input-sel = <&iomuxc>; - }; - - gpt1: gpt@302d0000 { - compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt"; - reg = <0x302d0000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_CLK_DUMMY>, - <&clks IMX7D_GPT1_ROOT_CLK>; - clock-names = "ipg", "per"; - }; - - gpt2: gpt@302e0000 { - compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt"; - reg = <0x302e0000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_CLK_DUMMY>, - <&clks IMX7D_GPT2_ROOT_CLK>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - gpt3: gpt@302f0000 { - compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt"; - reg = <0x302f0000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_CLK_DUMMY>, - <&clks IMX7D_GPT3_ROOT_CLK>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - gpt4: gpt@30300000 { - compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt"; - reg = <0x30300000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_CLK_DUMMY>, - <&clks IMX7D_GPT4_ROOT_CLK>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - iomuxc: iomuxc@30330000 { - compatible = "fsl,imx7d-iomuxc"; - reg = <0x30330000 0x10000>; - }; - - gpr: iomuxc-gpr@30340000 { - compatible = "fsl,imx7d-iomuxc-gpr", "syscon"; - reg = <0x30340000 0x10000>; - }; - - ocotp: ocotp-ctrl@30350000 { - compatible = "syscon"; - reg = <0x30350000 0x10000>; - clocks = <&clks IMX7D_CLK_DUMMY>; - status = "disabled"; - }; - - anatop: anatop@30360000 { - compatible = "fsl,imx7d-anatop", "fsl,imx6q-anatop", - "syscon", "simple-bus"; - reg = <0x30360000 0x10000>; - interrupts = , - ; - - reg_1p0d: regulator-vdd1p0d { - compatible = "fsl,anatop-regulator"; - regulator-name = "vdd1p0d"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1200000>; - anatop-reg-offset = <0x210>; - anatop-vol-bit-shift = <8>; - anatop-vol-bit-width = <5>; - anatop-min-bit-val = <8>; - anatop-min-voltage = <800000>; - anatop-max-voltage = <1200000>; - anatop-enable-bit = <31>; - }; - }; - - snvs: snvs@30370000 { - compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; - reg = <0x30370000 0x10000>; - - snvs_rtc: snvs-rtc-lp { - compatible = "fsl,sec-v4.0-mon-rtc-lp"; - regmap = <&snvs>; - offset = <0x34>; - interrupts = , - ; - }; - - snvs_poweroff: snvs-poweroff { - compatible = "syscon-poweroff"; - regmap = <&snvs>; - offset = <0x38>; - mask = <0x60>; - }; - - snvs_pwrkey: snvs-powerkey { - compatible = "fsl,sec-v4.0-pwrkey"; - regmap = <&snvs>; - interrupts = ; - linux,keycode = ; - wakeup-source; - }; - }; - - clks: ccm@30380000 { - compatible = "fsl,imx7d-ccm"; - reg = <0x30380000 0x10000>; - interrupts = , - ; - #clock-cells = <1>; - clocks = <&ckil>, <&osc>; - clock-names = "ckil", "osc"; - }; - - src: src@30390000 { - compatible = "fsl,imx7d-src", "fsl,imx51-src", "syscon"; - reg = <0x30390000 0x10000>; - interrupts = ; - #reset-cells = <1>; - }; - }; - - aips2: aips-bus@30400000 { - compatible = "fsl,aips-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x30400000 0x400000>; - ranges; - - adc1: adc@30610000 { - compatible = "fsl,imx7d-adc"; - reg = <0x30610000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_ADC_ROOT_CLK>; - clock-names = "adc"; - status = "disabled"; - }; - - adc2: adc@30620000 { - compatible = "fsl,imx7d-adc"; - reg = <0x30620000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_ADC_ROOT_CLK>; - clock-names = "adc"; - status = "disabled"; - }; - - ecspi4: ecspi@30630000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi"; - reg = <0x30630000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_ECSPI4_ROOT_CLK>, - <&clks IMX7D_ECSPI4_ROOT_CLK>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - pwm1: pwm@30660000 { - compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm"; - reg = <0x30660000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_PWM1_ROOT_CLK>, - <&clks IMX7D_PWM1_ROOT_CLK>; - clock-names = "ipg", "per"; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm2: pwm@30670000 { - compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm"; - reg = <0x30670000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_PWM2_ROOT_CLK>, - <&clks IMX7D_PWM2_ROOT_CLK>; - clock-names = "ipg", "per"; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm3: pwm@30680000 { - compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm"; - reg = <0x30680000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_PWM3_ROOT_CLK>, - <&clks IMX7D_PWM3_ROOT_CLK>; - clock-names = "ipg", "per"; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm4: pwm@30690000 { - compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm"; - reg = <0x30690000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_PWM4_ROOT_CLK>, - <&clks IMX7D_PWM4_ROOT_CLK>; - clock-names = "ipg", "per"; - #pwm-cells = <2>; - status = "disabled"; - }; - - lcdif: lcdif@30730000 { - compatible = "fsl,imx7d-lcdif", "fsl,imx28-lcdif"; - reg = <0x30730000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>, - <&clks IMX7D_CLK_DUMMY>, - <&clks IMX7D_CLK_DUMMY>; - clock-names = "pix", "axi", "disp_axi"; - status = "disabled"; - }; - }; - - aips3: aips-bus@30800000 { - compatible = "fsl,aips-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x30800000 0x400000>; - ranges; - - ecspi1: ecspi@30820000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi"; - reg = <0x30820000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_ECSPI1_ROOT_CLK>, - <&clks IMX7D_ECSPI1_ROOT_CLK>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - ecspi2: ecspi@30830000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi"; - reg = <0x30830000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_ECSPI2_ROOT_CLK>, - <&clks IMX7D_ECSPI2_ROOT_CLK>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - ecspi3: ecspi@30840000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi"; - reg = <0x30840000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_ECSPI3_ROOT_CLK>, - <&clks IMX7D_ECSPI3_ROOT_CLK>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - uart1: serial@30860000 { - compatible = "fsl,imx7d-uart", - "fsl,imx6q-uart"; - reg = <0x30860000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_UART1_ROOT_CLK>, - <&clks IMX7D_UART1_ROOT_CLK>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - uart2: serial@30890000 { - compatible = "fsl,imx7d-uart", - "fsl,imx6q-uart"; - reg = <0x30890000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_UART2_ROOT_CLK>, - <&clks IMX7D_UART2_ROOT_CLK>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - uart3: serial@30880000 { - compatible = "fsl,imx7d-uart", - "fsl,imx6q-uart"; - reg = <0x30880000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_UART3_ROOT_CLK>, - <&clks IMX7D_UART3_ROOT_CLK>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - flexcan1: can@30a00000 { - compatible = "fsl,imx7d-flexcan", "fsl,imx6q-flexcan"; - reg = <0x30a00000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_CLK_DUMMY>, - <&clks IMX7D_CAN1_ROOT_CLK>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - flexcan2: can@30a10000 { - compatible = "fsl,imx7d-flexcan", "fsl,imx6q-flexcan"; - reg = <0x30a10000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_CLK_DUMMY>, - <&clks IMX7D_CAN2_ROOT_CLK>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - i2c1: i2c@30a20000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; - reg = <0x30a20000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_I2C1_ROOT_CLK>; - status = "disabled"; - }; - - i2c2: i2c@30a30000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; - reg = <0x30a30000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_I2C2_ROOT_CLK>; - status = "disabled"; - }; - - i2c3: i2c@30a40000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; - reg = <0x30a40000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_I2C3_ROOT_CLK>; - status = "disabled"; - }; - - i2c4: i2c@30a50000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; - reg = <0x30a50000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_I2C4_ROOT_CLK>; - status = "disabled"; - }; - - uart4: serial@30a60000 { - compatible = "fsl,imx7d-uart", - "fsl,imx6q-uart"; - reg = <0x30a60000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_UART4_ROOT_CLK>, - <&clks IMX7D_UART4_ROOT_CLK>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - uart5: serial@30a70000 { - compatible = "fsl,imx7d-uart", - "fsl,imx6q-uart"; - reg = <0x30a70000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_UART5_ROOT_CLK>, - <&clks IMX7D_UART5_ROOT_CLK>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - uart6: serial@30a80000 { - compatible = "fsl,imx7d-uart", - "fsl,imx6q-uart"; - reg = <0x30a80000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_UART6_ROOT_CLK>, - <&clks IMX7D_UART6_ROOT_CLK>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - uart7: serial@30a90000 { - compatible = "fsl,imx7d-uart", - "fsl,imx6q-uart"; - reg = <0x30a90000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_UART7_ROOT_CLK>, - <&clks IMX7D_UART7_ROOT_CLK>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - usbotg1: usb@30b10000 { - compatible = "fsl,imx7d-usb", "fsl,imx27-usb"; - reg = <0x30b10000 0x200>; - interrupts = ; - clocks = <&clks IMX7D_USB_CTRL_CLK>; - fsl,usbphy = <&usbphynop1>; - fsl,usbmisc = <&usbmisc1 0>; - phy-clkgate-delay-us = <400>; - status = "disabled"; - }; - - usbotg2: usb@30b20000 { - compatible = "fsl,imx7d-usb", "fsl,imx27-usb"; - reg = <0x30b20000 0x200>; - interrupts = ; - clocks = <&clks IMX7D_USB_CTRL_CLK>; - fsl,usbphy = <&usbphynop2>; - fsl,usbmisc = <&usbmisc2 0>; - phy-clkgate-delay-us = <400>; - status = "disabled"; - }; - - usbh: usb@30b30000 { - compatible = "fsl,imx7d-usb", "fsl,imx27-usb"; - reg = <0x30b30000 0x200>; - interrupts = ; - clocks = <&clks IMX7D_USB_CTRL_CLK>; - fsl,usbphy = <&usbphynop3>; - fsl,usbmisc = <&usbmisc3 0>; - phy_type = "hsic"; - dr_mode = "host"; - phy-clkgate-delay-us = <400>; - status = "disabled"; - }; - - usbmisc1: usbmisc@30b10200 { - #index-cells = <1>; - compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc"; - reg = <0x30b10200 0x200>; - }; - - usbmisc2: usbmisc@30b20200 { - #index-cells = <1>; - compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc"; - reg = <0x30b20200 0x200>; - }; - - usbmisc3: usbmisc@30b30200 { - #index-cells = <1>; - compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc"; - reg = <0x30b30200 0x200>; - }; - - usbphynop1: usbphynop1 { - compatible = "usb-nop-xceiv"; - clocks = <&clks IMX7D_USB_PHY1_CLK>; - clock-names = "main_clk"; - }; - - usbphynop2: usbphynop2 { - compatible = "usb-nop-xceiv"; - clocks = <&clks IMX7D_USB_PHY2_CLK>; - clock-names = "main_clk"; - }; - - usbphynop3: usbphynop3 { - compatible = "usb-nop-xceiv"; - clocks = <&clks IMX7D_USB_HSIC_ROOT_CLK>; - clock-names = "main_clk"; - }; - - usdhc1: usdhc@30b40000 { - compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc"; - reg = <0x30b40000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_CLK_DUMMY>, - <&clks IMX7D_CLK_DUMMY>, - <&clks IMX7D_USDHC1_ROOT_CLK>; - clock-names = "ipg", "ahb", "per"; - bus-width = <4>; - status = "disabled"; - }; - - usdhc2: usdhc@30b50000 { - compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc"; - reg = <0x30b50000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_CLK_DUMMY>, - <&clks IMX7D_CLK_DUMMY>, - <&clks IMX7D_USDHC2_ROOT_CLK>; - clock-names = "ipg", "ahb", "per"; - bus-width = <4>; - status = "disabled"; - }; - - usdhc3: usdhc@30b60000 { - compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc"; - reg = <0x30b60000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_CLK_DUMMY>, - <&clks IMX7D_CLK_DUMMY>, - <&clks IMX7D_USDHC3_ROOT_CLK>; - clock-names = "ipg", "ahb", "per"; - bus-width = <4>; - status = "disabled"; - }; - - fec1: ethernet@30be0000 { - compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec"; - reg = <0x30be0000 0x10000>; - interrupts = , - , - ; - clocks = <&clks IMX7D_ENET_AXI_ROOT_CLK>, - <&clks IMX7D_ENET_AXI_ROOT_CLK>, - <&clks IMX7D_ENET1_TIME_ROOT_CLK>, - <&clks IMX7D_PLL_ENET_MAIN_125M_CLK>, - <&clks IMX7D_ENET_PHY_REF_ROOT_CLK>; - clock-names = "ipg", "ahb", "ptp", - "enet_clk_ref", "enet_out"; - fsl,num-tx-queues=<3>; - fsl,num-rx-queues=<3>; - status = "disabled"; - }; - - fec2: ethernet@30bf0000 { - compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec"; - reg = <0x30bf0000 0x10000>; - interrupts = , - , - ; - clocks = <&clks IMX7D_ENET_AXI_ROOT_CLK>, - <&clks IMX7D_ENET_AXI_ROOT_CLK>, - <&clks IMX7D_ENET2_TIME_ROOT_CLK>, - <&clks IMX7D_PLL_ENET_MAIN_125M_CLK>, - <&clks IMX7D_ENET_PHY_REF_ROOT_CLK>; - clock-names = "ipg", "ahb", "ptp", - "enet_clk_ref", "enet_out"; - fsl,num-tx-queues=<3>; - fsl,num-rx-queues=<3>; - status = "disabled"; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi new file mode 100644 index 0000000..9f088a8 --- /dev/null +++ b/arch/arm/boot/dts/imx7s.dtsi @@ -0,0 +1,1007 @@ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include +#include +#include +#include "imx7d-pinfunc.h" +#include "skeleton.dtsi" + +/ { + aliases { + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + gpio3 = &gpio4; + gpio4 = &gpio5; + gpio5 = &gpio6; + gpio6 = &gpio7; + i2c0 = &i2c1; + i2c1 = &i2c2; + i2c2 = &i2c3; + i2c3 = &i2c4; + mmc0 = &usdhc1; + mmc1 = &usdhc2; + mmc2 = &usdhc3; + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + serial3 = &uart4; + serial4 = &uart5; + serial5 = &uart6; + serial6 = &uart7; + spi0 = &ecspi1; + spi1 = &ecspi2; + spi2 = &ecspi3; + spi3 = &ecspi4; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <0>; + operating-points = < + /* KHz uV */ + 996000 1075000 + 792000 975000 + >; + clock-latency = <61036>; /* two CLK32 periods */ + clocks = <&clks IMX7D_CLK_ARM>; + }; + + cpu1: cpu@1 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <1>; + }; + }; + + intc: interrupt-controller@31001000 { + compatible = "arm,cortex-a7-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x31001000 0x1000>, + <0x31002000 0x1000>, + <0x31004000 0x2000>, + <0x31006000 0x2000>; + }; + + ckil: clock-cki { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "ckil"; + }; + + osc: clock-osc { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "osc"; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = , + , + , + ; + interrupt-parent = <&intc>; + }; + + etr@30086000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0x30086000 0x1000>; + clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; + clock-names = "apb_pclk"; + + port { + etr_in_port: endpoint { + slave-mode; + remote-endpoint = <&replicator_out_port1>; + }; + }; + }; + + tpiu@30087000 { + compatible = "arm,coresight-tpiu", "arm,primecell"; + reg = <0x30087000 0x1000>; + clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; + clock-names = "apb_pclk"; + + port { + tpiu_in_port: endpoint { + slave-mode; + remote-endpoint = <&replicator_out_port1>; + }; + }; + }; + + replicator { + /* + * non-configurable replicators don't show up on the + * AMBA bus. As such no need to add "arm,primecell" + */ + compatible = "arm,coresight-replicator"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + /* replicator output ports */ + port@0 { + reg = <0>; + replicator_out_port0: endpoint { + remote-endpoint = <&tpiu_in_port>; + }; + }; + + port@1 { + reg = <1>; + replicator_out_port1: endpoint { + remote-endpoint = <&etr_in_port>; + }; + }; + + /* replicator input port */ + port@2 { + reg = <0>; + replicator_in_port0: endpoint { + slave-mode; + remote-endpoint = <&etf_out_port>; + }; + }; + }; + }; + + etf@30084000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0x30084000 0x1000>; + clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + etf_in_port: endpoint { + slave-mode; + remote-endpoint = <&hugo_funnel_out_port0>; + }; + }; + + port@1 { + reg = <0>; + etf_out_port: endpoint { + remote-endpoint = <&replicator_in_port0>; + }; + }; + }; + }; + + funnel@30083000 { + compatible = "arm,coresight-funnel", "arm,primecell"; + reg = <0x30083000 0x1000>; + clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + /* funnel input ports */ + port@0 { + reg = <0>; + hugo_funnel_in_port0: endpoint { + slave-mode; + remote-endpoint = <&ca_funnel_out_port0>; + }; + }; + + port@1 { + reg = <1>; + hugo_funnel_in_port1: endpoint { + slave-mode; /* M4 input */ + }; + }; + + port@2 { + reg = <0>; + hugo_funnel_out_port0: endpoint { + remote-endpoint = <&etf_in_port>; + }; + }; + + /* the other input ports are not connect to anything */ + }; + }; + + funnel@30041000 { + compatible = "arm,coresight-funnel", "arm,primecell"; + reg = <0x30041000 0x1000>; + clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + /* funnel input ports */ + port@0 { + reg = <0>; + ca_funnel_in_port0: endpoint { + slave-mode; + remote-endpoint = <&etm0_out_port>; + }; + }; + + port@1 { + reg = <1>; + ca_funnel_in_port1: endpoint { + slave-mode; + remote-endpoint = <&etm1_out_port>; + }; + }; + + /* funnel output port */ + port@2 { + reg = <0>; + ca_funnel_out_port0: endpoint { + remote-endpoint = <&hugo_funnel_in_port0>; + }; + }; + + /* the other input ports are not connect to anything */ + }; + }; + + etm@3007c000 { + compatible = "arm,coresight-etm3x", "arm,primecell"; + reg = <0x3007c000 0x1000>; + cpu = <&cpu0>; + clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; + clock-names = "apb_pclk"; + + port { + etm0_out_port: endpoint { + remote-endpoint = <&ca_funnel_in_port0>; + }; + }; + }; + + etm@3007d000 { + compatible = "arm,coresight-etm3x", "arm,primecell"; + reg = <0x3007d000 0x1000>; + + /* + * System will hang if added nosmp in kernel command line + * without arm,primecell-periphid because amba bus try to + * read id and core1 power off at this time. + */ + arm,primecell-periphid = <0xbb956>; + cpu = <&cpu1>; + clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; + clock-names = "apb_pclk"; + + port { + etm1_out_port: endpoint { + remote-endpoint = <&ca_funnel_in_port1>; + }; + }; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + interrupt-parent = <&intc>; + ranges; + + aips1: aips-bus@30000000 { + compatible = "fsl,aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x30000000 0x400000>; + ranges; + + gpio1: gpio@30200000 { + compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; + reg = <0x30200000 0x10000>; + interrupts = , /* GPIO1_INT15_0 */ + ; /* GPIO1_INT31_16 */ + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio@30210000 { + compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; + reg = <0x30210000 0x10000>; + interrupts = , + ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio@30220000 { + compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; + reg = <0x30220000 0x10000>; + interrupts = , + ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio4: gpio@30230000 { + compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; + reg = <0x30230000 0x10000>; + interrupts = , + ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio5: gpio@30240000 { + compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; + reg = <0x30240000 0x10000>; + interrupts = , + ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio6: gpio@30250000 { + compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; + reg = <0x30250000 0x10000>; + interrupts = , + ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio7: gpio@30260000 { + compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; + reg = <0x30260000 0x10000>; + interrupts = , + ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + wdog1: wdog@30280000 { + compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt"; + reg = <0x30280000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_WDOG1_ROOT_CLK>; + }; + + wdog2: wdog@30290000 { + compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt"; + reg = <0x30290000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_WDOG2_ROOT_CLK>; + status = "disabled"; + }; + + wdog3: wdog@302a0000 { + compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt"; + reg = <0x302a0000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_WDOG3_ROOT_CLK>; + status = "disabled"; + }; + + wdog4: wdog@302b0000 { + compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt"; + reg = <0x302b0000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_WDOG4_ROOT_CLK>; + status = "disabled"; + }; + + iomuxc_lpsr: iomuxc-lpsr@302c0000 { + compatible = "fsl,imx7d-iomuxc-lpsr"; + reg = <0x302c0000 0x10000>; + fsl,input-sel = <&iomuxc>; + }; + + gpt1: gpt@302d0000 { + compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt"; + reg = <0x302d0000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_CLK_DUMMY>, + <&clks IMX7D_GPT1_ROOT_CLK>; + clock-names = "ipg", "per"; + }; + + gpt2: gpt@302e0000 { + compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt"; + reg = <0x302e0000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_CLK_DUMMY>, + <&clks IMX7D_GPT2_ROOT_CLK>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + gpt3: gpt@302f0000 { + compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt"; + reg = <0x302f0000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_CLK_DUMMY>, + <&clks IMX7D_GPT3_ROOT_CLK>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + gpt4: gpt@30300000 { + compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt"; + reg = <0x30300000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_CLK_DUMMY>, + <&clks IMX7D_GPT4_ROOT_CLK>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + iomuxc: iomuxc@30330000 { + compatible = "fsl,imx7d-iomuxc"; + reg = <0x30330000 0x10000>; + }; + + gpr: iomuxc-gpr@30340000 { + compatible = "fsl,imx7d-iomuxc-gpr", "syscon"; + reg = <0x30340000 0x10000>; + }; + + ocotp: ocotp-ctrl@30350000 { + compatible = "syscon"; + reg = <0x30350000 0x10000>; + clocks = <&clks IMX7D_CLK_DUMMY>; + status = "disabled"; + }; + + anatop: anatop@30360000 { + compatible = "fsl,imx7d-anatop", "fsl,imx6q-anatop", + "syscon", "simple-bus"; + reg = <0x30360000 0x10000>; + interrupts = , + ; + + reg_1p0d: regulator-vdd1p0d { + compatible = "fsl,anatop-regulator"; + regulator-name = "vdd1p0d"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1200000>; + anatop-reg-offset = <0x210>; + anatop-vol-bit-shift = <8>; + anatop-vol-bit-width = <5>; + anatop-min-bit-val = <8>; + anatop-min-voltage = <800000>; + anatop-max-voltage = <1200000>; + anatop-enable-bit = <31>; + }; + }; + + snvs: snvs@30370000 { + compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; + reg = <0x30370000 0x10000>; + + snvs_rtc: snvs-rtc-lp { + compatible = "fsl,sec-v4.0-mon-rtc-lp"; + regmap = <&snvs>; + offset = <0x34>; + interrupts = , + ; + }; + + snvs_poweroff: snvs-poweroff { + compatible = "syscon-poweroff"; + regmap = <&snvs>; + offset = <0x38>; + mask = <0x60>; + }; + + snvs_pwrkey: snvs-powerkey { + compatible = "fsl,sec-v4.0-pwrkey"; + regmap = <&snvs>; + interrupts = ; + linux,keycode = ; + wakeup-source; + }; + }; + + clks: ccm@30380000 { + compatible = "fsl,imx7d-ccm"; + reg = <0x30380000 0x10000>; + interrupts = , + ; + #clock-cells = <1>; + clocks = <&ckil>, <&osc>; + clock-names = "ckil", "osc"; + }; + + src: src@30390000 { + compatible = "fsl,imx7d-src", "fsl,imx51-src", "syscon"; + reg = <0x30390000 0x10000>; + interrupts = ; + #reset-cells = <1>; + }; + }; + + aips2: aips-bus@30400000 { + compatible = "fsl,aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x30400000 0x400000>; + ranges; + + adc1: adc@30610000 { + compatible = "fsl,imx7d-adc"; + reg = <0x30610000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_ADC_ROOT_CLK>; + clock-names = "adc"; + status = "disabled"; + }; + + adc2: adc@30620000 { + compatible = "fsl,imx7d-adc"; + reg = <0x30620000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_ADC_ROOT_CLK>; + clock-names = "adc"; + status = "disabled"; + }; + + ecspi4: ecspi@30630000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi"; + reg = <0x30630000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_ECSPI4_ROOT_CLK>, + <&clks IMX7D_ECSPI4_ROOT_CLK>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + pwm1: pwm@30660000 { + compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm"; + reg = <0x30660000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_PWM1_ROOT_CLK>, + <&clks IMX7D_PWM1_ROOT_CLK>; + clock-names = "ipg", "per"; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm2: pwm@30670000 { + compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm"; + reg = <0x30670000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_PWM2_ROOT_CLK>, + <&clks IMX7D_PWM2_ROOT_CLK>; + clock-names = "ipg", "per"; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm3: pwm@30680000 { + compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm"; + reg = <0x30680000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_PWM3_ROOT_CLK>, + <&clks IMX7D_PWM3_ROOT_CLK>; + clock-names = "ipg", "per"; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm4: pwm@30690000 { + compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm"; + reg = <0x30690000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_PWM4_ROOT_CLK>, + <&clks IMX7D_PWM4_ROOT_CLK>; + clock-names = "ipg", "per"; + #pwm-cells = <2>; + status = "disabled"; + }; + + lcdif: lcdif@30730000 { + compatible = "fsl,imx7d-lcdif", "fsl,imx28-lcdif"; + reg = <0x30730000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>, + <&clks IMX7D_CLK_DUMMY>, + <&clks IMX7D_CLK_DUMMY>; + clock-names = "pix", "axi", "disp_axi"; + status = "disabled"; + }; + }; + + aips3: aips-bus@30800000 { + compatible = "fsl,aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x30800000 0x400000>; + ranges; + + ecspi1: ecspi@30820000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi"; + reg = <0x30820000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_ECSPI1_ROOT_CLK>, + <&clks IMX7D_ECSPI1_ROOT_CLK>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + ecspi2: ecspi@30830000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi"; + reg = <0x30830000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_ECSPI2_ROOT_CLK>, + <&clks IMX7D_ECSPI2_ROOT_CLK>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + ecspi3: ecspi@30840000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi"; + reg = <0x30840000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_ECSPI3_ROOT_CLK>, + <&clks IMX7D_ECSPI3_ROOT_CLK>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + uart1: serial@30860000 { + compatible = "fsl,imx7d-uart", + "fsl,imx6q-uart"; + reg = <0x30860000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_UART1_ROOT_CLK>, + <&clks IMX7D_UART1_ROOT_CLK>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + uart2: serial@30890000 { + compatible = "fsl,imx7d-uart", + "fsl,imx6q-uart"; + reg = <0x30890000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_UART2_ROOT_CLK>, + <&clks IMX7D_UART2_ROOT_CLK>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + uart3: serial@30880000 { + compatible = "fsl,imx7d-uart", + "fsl,imx6q-uart"; + reg = <0x30880000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_UART3_ROOT_CLK>, + <&clks IMX7D_UART3_ROOT_CLK>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + flexcan1: can@30a00000 { + compatible = "fsl,imx7d-flexcan", "fsl,imx6q-flexcan"; + reg = <0x30a00000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_CLK_DUMMY>, + <&clks IMX7D_CAN1_ROOT_CLK>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + flexcan2: can@30a10000 { + compatible = "fsl,imx7d-flexcan", "fsl,imx6q-flexcan"; + reg = <0x30a10000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_CLK_DUMMY>, + <&clks IMX7D_CAN2_ROOT_CLK>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + i2c1: i2c@30a20000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; + reg = <0x30a20000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_I2C1_ROOT_CLK>; + status = "disabled"; + }; + + i2c2: i2c@30a30000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; + reg = <0x30a30000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_I2C2_ROOT_CLK>; + status = "disabled"; + }; + + i2c3: i2c@30a40000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; + reg = <0x30a40000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_I2C3_ROOT_CLK>; + status = "disabled"; + }; + + i2c4: i2c@30a50000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; + reg = <0x30a50000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_I2C4_ROOT_CLK>; + status = "disabled"; + }; + + uart4: serial@30a60000 { + compatible = "fsl,imx7d-uart", + "fsl,imx6q-uart"; + reg = <0x30a60000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_UART4_ROOT_CLK>, + <&clks IMX7D_UART4_ROOT_CLK>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + uart5: serial@30a70000 { + compatible = "fsl,imx7d-uart", + "fsl,imx6q-uart"; + reg = <0x30a70000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_UART5_ROOT_CLK>, + <&clks IMX7D_UART5_ROOT_CLK>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + uart6: serial@30a80000 { + compatible = "fsl,imx7d-uart", + "fsl,imx6q-uart"; + reg = <0x30a80000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_UART6_ROOT_CLK>, + <&clks IMX7D_UART6_ROOT_CLK>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + uart7: serial@30a90000 { + compatible = "fsl,imx7d-uart", + "fsl,imx6q-uart"; + reg = <0x30a90000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_UART7_ROOT_CLK>, + <&clks IMX7D_UART7_ROOT_CLK>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + usbotg1: usb@30b10000 { + compatible = "fsl,imx7d-usb", "fsl,imx27-usb"; + reg = <0x30b10000 0x200>; + interrupts = ; + clocks = <&clks IMX7D_USB_CTRL_CLK>; + fsl,usbphy = <&usbphynop1>; + fsl,usbmisc = <&usbmisc1 0>; + phy-clkgate-delay-us = <400>; + status = "disabled"; + }; + + usbotg2: usb@30b20000 { + compatible = "fsl,imx7d-usb", "fsl,imx27-usb"; + reg = <0x30b20000 0x200>; + interrupts = ; + clocks = <&clks IMX7D_USB_CTRL_CLK>; + fsl,usbphy = <&usbphynop2>; + fsl,usbmisc = <&usbmisc2 0>; + phy-clkgate-delay-us = <400>; + status = "disabled"; + }; + + usbh: usb@30b30000 { + compatible = "fsl,imx7d-usb", "fsl,imx27-usb"; + reg = <0x30b30000 0x200>; + interrupts = ; + clocks = <&clks IMX7D_USB_CTRL_CLK>; + fsl,usbphy = <&usbphynop3>; + fsl,usbmisc = <&usbmisc3 0>; + phy_type = "hsic"; + dr_mode = "host"; + phy-clkgate-delay-us = <400>; + status = "disabled"; + }; + + usbmisc1: usbmisc@30b10200 { + #index-cells = <1>; + compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc"; + reg = <0x30b10200 0x200>; + }; + + usbmisc2: usbmisc@30b20200 { + #index-cells = <1>; + compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc"; + reg = <0x30b20200 0x200>; + }; + + usbmisc3: usbmisc@30b30200 { + #index-cells = <1>; + compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc"; + reg = <0x30b30200 0x200>; + }; + + usbphynop1: usbphynop1 { + compatible = "usb-nop-xceiv"; + clocks = <&clks IMX7D_USB_PHY1_CLK>; + clock-names = "main_clk"; + }; + + usbphynop2: usbphynop2 { + compatible = "usb-nop-xceiv"; + clocks = <&clks IMX7D_USB_PHY2_CLK>; + clock-names = "main_clk"; + }; + + usbphynop3: usbphynop3 { + compatible = "usb-nop-xceiv"; + clocks = <&clks IMX7D_USB_HSIC_ROOT_CLK>; + clock-names = "main_clk"; + }; + + usdhc1: usdhc@30b40000 { + compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc"; + reg = <0x30b40000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_CLK_DUMMY>, + <&clks IMX7D_CLK_DUMMY>, + <&clks IMX7D_USDHC1_ROOT_CLK>; + clock-names = "ipg", "ahb", "per"; + bus-width = <4>; + status = "disabled"; + }; + + usdhc2: usdhc@30b50000 { + compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc"; + reg = <0x30b50000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_CLK_DUMMY>, + <&clks IMX7D_CLK_DUMMY>, + <&clks IMX7D_USDHC2_ROOT_CLK>; + clock-names = "ipg", "ahb", "per"; + bus-width = <4>; + status = "disabled"; + }; + + usdhc3: usdhc@30b60000 { + compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc"; + reg = <0x30b60000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_CLK_DUMMY>, + <&clks IMX7D_CLK_DUMMY>, + <&clks IMX7D_USDHC3_ROOT_CLK>; + clock-names = "ipg", "ahb", "per"; + bus-width = <4>; + status = "disabled"; + }; + + fec1: ethernet@30be0000 { + compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec"; + reg = <0x30be0000 0x10000>; + interrupts = , + , + ; + clocks = <&clks IMX7D_ENET_AXI_ROOT_CLK>, + <&clks IMX7D_ENET_AXI_ROOT_CLK>, + <&clks IMX7D_ENET1_TIME_ROOT_CLK>, + <&clks IMX7D_PLL_ENET_MAIN_125M_CLK>, + <&clks IMX7D_ENET_PHY_REF_ROOT_CLK>; + clock-names = "ipg", "ahb", "ptp", + "enet_clk_ref", "enet_out"; + fsl,num-tx-queues=<3>; + fsl,num-rx-queues=<3>; + status = "disabled"; + }; + + fec2: ethernet@30bf0000 { + compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec"; + reg = <0x30bf0000 0x10000>; + interrupts = , + , + ; + clocks = <&clks IMX7D_ENET_AXI_ROOT_CLK>, + <&clks IMX7D_ENET_AXI_ROOT_CLK>, + <&clks IMX7D_ENET2_TIME_ROOT_CLK>, + <&clks IMX7D_PLL_ENET_MAIN_125M_CLK>, + <&clks IMX7D_ENET_PHY_REF_ROOT_CLK>; + clock-names = "ipg", "ahb", "ptp", + "enet_clk_ref", "enet_out"; + fsl,num-tx-queues=<3>; + fsl,num-rx-queues=<3>; + status = "disabled"; + }; + }; + }; +}; -- cgit v0.10.2 From a67970a22699ad104eac3db627d48c4db502e5ab Mon Sep 17 00:00:00 2001 From: Stefan Agner Date: Sun, 26 Jun 2016 01:47:53 -0700 Subject: ARM: dts: imx7d: recreate imx7d.dtsi with i.MX 7Dual specifics The i.MX 7Solo implements a subset of features available on i.MX 7Dual. Recreate imx7s.dtsi as the base device tree for i.MX 7Dual boards. The i.MX 7Dual's additional features over i.MX 7Solo are: - Second Cortex-A7 core - Second Gigabit Ethernet controller - EPD (Electronc Paper Display, not yet part of the device tree) - PCIe (not yet part of the device tree) - Additional USB2.0 OTG controller Signed-off-by: Stefan Agner Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/imx7d-cl-som-imx7.dts b/arch/arm/boot/dts/imx7d-cl-som-imx7.dts index 3942c7d..4863451 100644 --- a/arch/arm/boot/dts/imx7d-cl-som-imx7.dts +++ b/arch/arm/boot/dts/imx7d-cl-som-imx7.dts @@ -13,7 +13,7 @@ /dts-v1/; #include -#include "imx7s.dtsi" +#include "imx7d.dtsi" / { model = "CompuLab CL-SOM-iMX7"; diff --git a/arch/arm/boot/dts/imx7d-nitrogen7.dts b/arch/arm/boot/dts/imx7d-nitrogen7.dts index 8e993cb..bef394e 100644 --- a/arch/arm/boot/dts/imx7d-nitrogen7.dts +++ b/arch/arm/boot/dts/imx7d-nitrogen7.dts @@ -43,7 +43,7 @@ /dts-v1/; #include -#include "imx7s.dtsi" +#include "imx7d.dtsi" / { model = "Boundary Devices i.MX7 Nitrogen7 Board"; diff --git a/arch/arm/boot/dts/imx7d-sdb.dts b/arch/arm/boot/dts/imx7d-sdb.dts index 8852a84..6bd8203 100644 --- a/arch/arm/boot/dts/imx7d-sdb.dts +++ b/arch/arm/boot/dts/imx7d-sdb.dts @@ -43,7 +43,7 @@ /dts-v1/; #include -#include "imx7s.dtsi" +#include "imx7d.dtsi" / { model = "Freescale i.MX7 SabreSD Board"; diff --git a/arch/arm/boot/dts/imx7d.dtsi b/arch/arm/boot/dts/imx7d.dtsi new file mode 100644 index 0000000..51c13cb --- /dev/null +++ b/arch/arm/boot/dts/imx7d.dtsi @@ -0,0 +1,128 @@ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * Copyright 2016 Toradex AG + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "imx7s.dtsi" + +/ { + cpus { + cpu1: cpu@1 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <1>; + }; + }; + + etm@3007d000 { + compatible = "arm,coresight-etm3x", "arm,primecell"; + reg = <0x3007d000 0x1000>; + + /* + * System will hang if added nosmp in kernel command line + * without arm,primecell-periphid because amba bus try to + * read id and core1 power off at this time. + */ + arm,primecell-periphid = <0xbb956>; + cpu = <&cpu1>; + clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; + clock-names = "apb_pclk"; + + port { + etm1_out_port: endpoint { + remote-endpoint = <&ca_funnel_in_port1>; + }; + }; + }; +}; + +&aips3 { + usbotg2: usb@30b20000 { + compatible = "fsl,imx7d-usb", "fsl,imx27-usb"; + reg = <0x30b20000 0x200>; + interrupts = ; + clocks = <&clks IMX7D_USB_CTRL_CLK>; + fsl,usbphy = <&usbphynop2>; + fsl,usbmisc = <&usbmisc2 0>; + phy-clkgate-delay-us = <400>; + status = "disabled"; + }; + + usbmisc2: usbmisc@30b20200 { + #index-cells = <1>; + compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc"; + reg = <0x30b20200 0x200>; + }; + + usbphynop2: usbphynop2 { + compatible = "usb-nop-xceiv"; + clocks = <&clks IMX7D_USB_PHY2_CLK>; + clock-names = "main_clk"; + }; + + fec2: ethernet@30bf0000 { + compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec"; + reg = <0x30bf0000 0x10000>; + interrupts = , + , + ; + clocks = <&clks IMX7D_ENET_AXI_ROOT_CLK>, + <&clks IMX7D_ENET_AXI_ROOT_CLK>, + <&clks IMX7D_ENET2_TIME_ROOT_CLK>, + <&clks IMX7D_PLL_ENET_MAIN_125M_CLK>, + <&clks IMX7D_ENET_PHY_REF_ROOT_CLK>; + clock-names = "ipg", "ahb", "ptp", + "enet_clk_ref", "enet_out"; + fsl,num-tx-queues=<3>; + fsl,num-rx-queues=<3>; + status = "disabled"; + }; +}; + +&ca_funnel_ports { + port@1 { + reg = <1>; + ca_funnel_in_port1: endpoint { + slave-mode; + remote-endpoint = <&etm1_out_port>; + }; + }; +}; diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi index 9f088a8..7fccb41 100644 --- a/arch/arm/boot/dts/imx7s.dtsi +++ b/arch/arm/boot/dts/imx7s.dtsi @@ -1,5 +1,6 @@ /* * Copyright 2015 Freescale Semiconductor, Inc. + * Copyright 2016 Toradex AG * * This file is dual-licensed: you can use it either under the terms * of the GPL or the X11 license, at your option. Note that this dual @@ -91,12 +92,6 @@ clock-latency = <61036>; /* two CLK32 periods */ clocks = <&clks IMX7D_CLK_ARM>; }; - - cpu1: cpu@1 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - reg = <1>; - }; }; intc: interrupt-controller@31001000 { @@ -267,7 +262,7 @@ clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; clock-names = "apb_pclk"; - ports { + ca_funnel_ports: ports { #address-cells = <1>; #size-cells = <0>; @@ -280,14 +275,6 @@ }; }; - port@1 { - reg = <1>; - ca_funnel_in_port1: endpoint { - slave-mode; - remote-endpoint = <&etm1_out_port>; - }; - }; - /* funnel output port */ port@2 { reg = <0>; @@ -314,27 +301,6 @@ }; }; - etm@3007d000 { - compatible = "arm,coresight-etm3x", "arm,primecell"; - reg = <0x3007d000 0x1000>; - - /* - * System will hang if added nosmp in kernel command line - * without arm,primecell-periphid because amba bus try to - * read id and core1 power off at this time. - */ - arm,primecell-periphid = <0xbb956>; - cpu = <&cpu1>; - clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; - clock-names = "apb_pclk"; - - port { - etm1_out_port: endpoint { - remote-endpoint = <&ca_funnel_in_port1>; - }; - }; - }; - soc { #address-cells = <1>; #size-cells = <1>; @@ -871,17 +837,6 @@ status = "disabled"; }; - usbotg2: usb@30b20000 { - compatible = "fsl,imx7d-usb", "fsl,imx27-usb"; - reg = <0x30b20000 0x200>; - interrupts = ; - clocks = <&clks IMX7D_USB_CTRL_CLK>; - fsl,usbphy = <&usbphynop2>; - fsl,usbmisc = <&usbmisc2 0>; - phy-clkgate-delay-us = <400>; - status = "disabled"; - }; - usbh: usb@30b30000 { compatible = "fsl,imx7d-usb", "fsl,imx27-usb"; reg = <0x30b30000 0x200>; @@ -901,12 +856,6 @@ reg = <0x30b10200 0x200>; }; - usbmisc2: usbmisc@30b20200 { - #index-cells = <1>; - compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc"; - reg = <0x30b20200 0x200>; - }; - usbmisc3: usbmisc@30b30200 { #index-cells = <1>; compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc"; @@ -919,12 +868,6 @@ clock-names = "main_clk"; }; - usbphynop2: usbphynop2 { - compatible = "usb-nop-xceiv"; - clocks = <&clks IMX7D_USB_PHY2_CLK>; - clock-names = "main_clk"; - }; - usbphynop3: usbphynop3 { compatible = "usb-nop-xceiv"; clocks = <&clks IMX7D_USB_HSIC_ROOT_CLK>; @@ -984,24 +927,6 @@ fsl,num-rx-queues=<3>; status = "disabled"; }; - - fec2: ethernet@30bf0000 { - compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec"; - reg = <0x30bf0000 0x10000>; - interrupts = , - , - ; - clocks = <&clks IMX7D_ENET_AXI_ROOT_CLK>, - <&clks IMX7D_ENET_AXI_ROOT_CLK>, - <&clks IMX7D_ENET2_TIME_ROOT_CLK>, - <&clks IMX7D_PLL_ENET_MAIN_125M_CLK>, - <&clks IMX7D_ENET_PHY_REF_ROOT_CLK>; - clock-names = "ipg", "ahb", "ptp", - "enet_clk_ref", "enet_out"; - fsl,num-tx-queues=<3>; - fsl,num-rx-queues=<3>; - status = "disabled"; - }; }; }; }; -- cgit v0.10.2 From 1e886a18e08577f8cbc63a577f2b5da24b3b02f5 Mon Sep 17 00:00:00 2001 From: Stefan Agner Date: Sun, 26 Jun 2016 01:47:54 -0700 Subject: ARM: dts: imx7d: move input header into base device tree The base device tree uses KEY_POWER in the snvs-powerkey node, hence include the input.h header file in the base device tree. Signed-off-by: Stefan Agner Acked-by: Igor Grinberg Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/imx7d-cl-som-imx7.dts b/arch/arm/boot/dts/imx7d-cl-som-imx7.dts index 4863451..58b09bf 100644 --- a/arch/arm/boot/dts/imx7d-cl-som-imx7.dts +++ b/arch/arm/boot/dts/imx7d-cl-som-imx7.dts @@ -12,7 +12,6 @@ /dts-v1/; -#include #include "imx7d.dtsi" / { diff --git a/arch/arm/boot/dts/imx7d-nitrogen7.dts b/arch/arm/boot/dts/imx7d-nitrogen7.dts index bef394e..ce08f18 100644 --- a/arch/arm/boot/dts/imx7d-nitrogen7.dts +++ b/arch/arm/boot/dts/imx7d-nitrogen7.dts @@ -42,7 +42,6 @@ /dts-v1/; -#include #include "imx7d.dtsi" / { diff --git a/arch/arm/boot/dts/imx7d-sdb.dts b/arch/arm/boot/dts/imx7d-sdb.dts index 6bd8203..95ee268 100644 --- a/arch/arm/boot/dts/imx7d-sdb.dts +++ b/arch/arm/boot/dts/imx7d-sdb.dts @@ -42,7 +42,6 @@ /dts-v1/; -#include #include "imx7d.dtsi" / { diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi index 7fccb41..1e90bdb 100644 --- a/arch/arm/boot/dts/imx7s.dtsi +++ b/arch/arm/boot/dts/imx7s.dtsi @@ -43,6 +43,7 @@ #include #include +#include #include #include "imx7d-pinfunc.h" #include "skeleton.dtsi" -- cgit v0.10.2 From b326629f25b7c1a6d1c63a8c5483c8db11689d9c Mon Sep 17 00:00:00 2001 From: Stefan Agner Date: Sun, 26 Jun 2016 01:47:55 -0700 Subject: ARM: dts: imx7: add Toradex Colibri iMX7S/iMX7D support Add support for the Computer on Module Colibri iMX7S/iMX7D along with the development/evaluation carrier board device trees. Follow the usual hierarchic include model, maintaining shared configuration in imx7-colibri.dtsi and imx7-colibri-eval-v3.dtsi respectively. Signed-off-by: Stefan Agner Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 146850b..1e13fcc 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -401,9 +401,11 @@ dtb-$(CONFIG_SOC_IMX6UL) += \ imx6ul-tx6ul-mainboard.dtb dtb-$(CONFIG_SOC_IMX7D) += \ imx7d-cl-som-imx7.dtb \ + imx7d-colibri-eval-v3.dtb \ imx7d-nitrogen7.dtb \ imx7d-sbc-imx7.dtb \ - imx7d-sdb.dtb + imx7d-sdb.dtb \ + imx7s-colibri-eval-v3.dtb dtb-$(CONFIG_SOC_LS1021A) += \ ls1021a-qds.dtb \ ls1021a-twr.dtb diff --git a/arch/arm/boot/dts/imx7-colibri-eval-v3.dtsi b/arch/arm/boot/dts/imx7-colibri-eval-v3.dtsi new file mode 100644 index 0000000..1545661 --- /dev/null +++ b/arch/arm/boot/dts/imx7-colibri-eval-v3.dtsi @@ -0,0 +1,148 @@ +/* + * Copyright 2016 Toradex AG + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/ { + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&bl { + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + status = "okay"; +}; + +&adc1 { + status = "okay"; +}; + +&adc2 { + status = "okay"; +}; + +&fec1 { + status = "okay"; +}; + +&i2c4 { + status = "okay"; + + /* M41T0M6 real time clock on carrier board */ + rtc: m41t0m6@68 { + compatible = "st,m41t00"; + reg = <0x68>; + }; +}; + +&lcdif { + display = <&display0>; + status = "okay"; + + display0: lcd-display { + bits-per-pixel = <16>; + bus-width = <18>; + + display-timings { + native-mode = <&timing_vga>; + + /* Standard VGA timing */ + timing_vga: 640x480 { + clock-frequency = <25175000>; + hactive = <640>; + vactive = <480>; + hback-porch = <40>; + hfront-porch = <24>; + vback-porch = <32>; + vfront-porch = <11>; + hsync-len = <96>; + vsync-len = <2>; + de-active = <1>; + hsync-active = <0>; + vsync-active = <0>; + pixelclk-active = <0>; + }; + }; + }; +}; + +&pwm1 { + status = "okay"; +}; + +&pwm2 { + status = "okay"; +}; + +&pwm3 { + status = "okay"; +}; + +&pwm4 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&uart3 { + status = "okay"; +}; + +&usbotg1 { + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_cd_usdhc1>; + no-1-8-v; + cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; + keep-power-in-suspend; + wakeup-source; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx7-colibri.dtsi b/arch/arm/boot/dts/imx7-colibri.dtsi new file mode 100644 index 0000000..0a9d3a8 --- /dev/null +++ b/arch/arm/boot/dts/imx7-colibri.dtsi @@ -0,0 +1,571 @@ +/* + * Copyright 2016 Toradex AG + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/ { + bl: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 5000000>; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_vref_1v8: regulator-vref-1v8 { + compatible = "regulator-fixed"; + regulator-name = "vref-1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; +}; + +&adc1 { + vref-supply = <®_vref_1v8>; +}; + +&adc2 { + vref-supply = <®_vref_1v8>; +}; + +&cpu0 { + arm-supply = <®_DCDC2>; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>; + clocks = <&clks IMX7D_ENET_AXI_ROOT_CLK>, + <&clks IMX7D_ENET_AXI_ROOT_CLK>, + <&clks IMX7D_ENET1_TIME_ROOT_CLK>, + <&clks IMX7D_PLL_ENET_MAIN_50M_CLK>; + clock-names = "ipg", "ahb", "ptp", "enet_clk_ref"; + assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>, + <&clks IMX7D_ENET1_TIME_ROOT_CLK>; + assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; + assigned-clock-rates = <0>, <100000000>; + phy-mode = "rmii"; + phy-supply = <®_LDO1>; + fsl,magic-packet; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1 &pinctrl_i2c1_int>; + status = "okay"; + + ad7879@2c { + compatible = "adi,ad7879-1"; + reg = <0x2c>; + interrupt-parent = <&gpio1>; + interrupts = <13 IRQ_TYPE_EDGE_FALLING>; + touchscreen-max-pressure = <4096>; + adi,resistance-plate-x = <120>; + adi,first-conversion-delay = /bits/ 8 <3>; + adi,acquisition-time = /bits/ 8 <1>; + adi,median-filter-size = /bits/ 8 <2>; + adi,averaging = /bits/ 8 <1>; + adi,conversion-interval = /bits/ 8 <255>; + }; + + pmic@33 { + compatible = "ricoh,rn5t567"; + reg = <0x33>; + + regulators { + reg_DCDC1: DCDC1 { /* V1.0_SOC */ + regulator-min-microvolt = <975000>; + regulator-max-microvolt = <1125000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_DCDC2: DCDC2 { /* V1.1_ARM */ + regulator-min-microvolt = <975000>; + regulator-max-microvolt = <1125000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_DCDC3: DCDC3 { /* V1.8 */ + regulator-min-microvolt = <1775000>; + regulator-max-microvolt = <1825000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_DCDC4: DCDC4 { /* V1.35_DRAM */ + regulator-min-microvolt = <1325000>; + regulator-max-microvolt = <1375000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_LDO1: LDO1 { /* PWR_EN_+V3.3_ETH */ + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_LDO2: LDO2 { /* +V1.8_SD */ + regulator-min-microvolt = <1775000>; + regulator-max-microvolt = <3325000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_LDO3: LDO3 { /* PWR_EN_+V3.3_LPSR */ + regulator-min-microvolt = <3275000>; + regulator-max-microvolt = <3325000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_LDO4: LDO4 { /* V1.8_LPSR */ + regulator-min-microvolt = <1775000>; + regulator-max-microvolt = <1825000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_LDO5: LDO5 { /* PWR_EN_+V3.3 */ + regulator-min-microvolt = <1775000>; + regulator-max-microvolt = <1825000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; +}; + +&i2c4 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4>; +}; + +&lcdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdif_dat + &pinctrl_lcdif_ctrl>; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; +}; + +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; +}; + +®_1p0d { + vin-supply = <®_DCDC3>; +}; + +&snvs_pwrkey { + status = "disabled"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_ctrl1 &pinctrl_uart1_ctrl2>; + assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; + uart-has-rtscts; + fsl,dte-mode; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + assigned-clocks = <&clks IMX7D_UART2_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; + uart-has-rtscts; + fsl,dte-mode; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; + fsl,dte-mode; +}; + +&usbotg1 { + dr_mode = "host"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio1 &pinctrl_gpio2 &pinctrl_gpio3 &pinctrl_gpio4>; + + pinctrl_gpio1: gpio1-grp { + fsl,pins = < + MX7D_PAD_ENET1_RGMII_RD3__GPIO7_IO3 0x14 /* SODIMM 55 */ + MX7D_PAD_ENET1_RGMII_RD2__GPIO7_IO2 0x14 /* SODIMM 63 */ + MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0X14 /* SODIMM 73 */ + MX7D_PAD_SAI1_RX_SYNC__GPIO6_IO16 0X14 /* SODIMM 77 */ + MX7D_PAD_EPDC_DATA09__GPIO2_IO9 0x14 /* SODIMM 89 */ + MX7D_PAD_EPDC_DATA08__GPIO2_IO8 0x14 /* SODIMM 91 */ + MX7D_PAD_LCD_RESET__GPIO3_IO4 0x14 /* SODIMM 93 */ + MX7D_PAD_EPDC_DATA13__GPIO2_IO13 0x14 /* SODIMM 95 */ + MX7D_PAD_ENET1_RGMII_TXC__GPIO7_IO11 0x14 /* SODIMM 99 */ + MX7D_PAD_EPDC_DATA10__GPIO2_IO10 0x14 /* SODIMM 105 */ + MX7D_PAD_EPDC_DATA15__GPIO2_IO15 0x14 /* SODIMM 107 */ + MX7D_PAD_EPDC_DATA00__GPIO2_IO0 0x14 /* SODIMM 111 */ + MX7D_PAD_EPDC_DATA01__GPIO2_IO1 0x14 /* SODIMM 113 */ + MX7D_PAD_EPDC_DATA02__GPIO2_IO2 0x14 /* SODIMM 115 */ + MX7D_PAD_EPDC_DATA03__GPIO2_IO3 0x14 /* SODIMM 117 */ + MX7D_PAD_EPDC_DATA04__GPIO2_IO4 0x14 /* SODIMM 119 */ + MX7D_PAD_EPDC_DATA05__GPIO2_IO5 0x14 /* SODIMM 121 */ + MX7D_PAD_EPDC_DATA06__GPIO2_IO6 0x14 /* SODIMM 123 */ + MX7D_PAD_EPDC_DATA07__GPIO2_IO7 0x14 /* SODIMM 125 */ + MX7D_PAD_EPDC_SDCE2__GPIO2_IO22 0x14 /* SODIMM 127 */ + MX7D_PAD_UART3_RTS_B__GPIO4_IO6 0x14 /* SODIMM 131 */ + MX7D_PAD_EPDC_GDRL__GPIO2_IO26 0x14 /* SODIMM 133 */ + MX7D_PAD_SAI1_RX_BCLK__GPIO6_IO17 0x14 /* SODIMM 24 */ + MX7D_PAD_SD2_DATA2__GPIO5_IO16 0x14 /* SODIMM 100 */ + MX7D_PAD_SD2_DATA3__GPIO5_IO17 0x14 /* SODIMM 102 */ + MX7D_PAD_EPDC_GDSP__GPIO2_IO27 0x14 /* SODIMM 104 */ + MX7D_PAD_EPDC_BDR0__GPIO2_IO28 0x14 /* SODIMM 106 */ + MX7D_PAD_EPDC_BDR1__GPIO2_IO29 0x14 /* SODIMM 110 */ + MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 0x14 /* SODIMM 112 */ + MX7D_PAD_EPDC_SDCLK__GPIO2_IO16 0x14 /* SODIMM 114 */ + MX7D_PAD_EPDC_SDLE__GPIO2_IO17 0x14 /* SODIMM 116 */ + MX7D_PAD_EPDC_SDOE__GPIO2_IO18 0x14 /* SODIMM 118 */ + MX7D_PAD_EPDC_SDSHR__GPIO2_IO19 0x14 /* SODIMM 120 */ + MX7D_PAD_EPDC_SDCE0__GPIO2_IO20 0x14 /* SODIMM 122 */ + MX7D_PAD_EPDC_SDCE1__GPIO2_IO21 0x14 /* SODIMM 124 */ + MX7D_PAD_EPDC_DATA14__GPIO2_IO14 0x14 /* SODIMM 126 */ + MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 0x14 /* SODIMM 128 */ + MX7D_PAD_EPDC_SDCE3__GPIO2_IO23 0x14 /* SODIMM 130 */ + MX7D_PAD_EPDC_GDCLK__GPIO2_IO24 0x14 /* SODIMM 132 */ + MX7D_PAD_EPDC_GDOE__GPIO2_IO25 0x14 /* SODIMM 134 */ + MX7D_PAD_EPDC_DATA12__GPIO2_IO12 0x14 /* SODIMM 150 */ + MX7D_PAD_EPDC_DATA11__GPIO2_IO11 0x14 /* SODIMM 152 */ + MX7D_PAD_SD2_CLK__GPIO5_IO12 0x14 /* SODIMM 184 */ + MX7D_PAD_SD2_CMD__GPIO5_IO13 0x14 /* SODIMM 186 */ + >; + }; + + pinctrl_gpio2: gpio2-grp { /* On X22 Camera interface */ + fsl,pins = < + MX7D_PAD_ECSPI2_SS0__GPIO4_IO23 0x14 /* SODIMM 65 */ + MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x14 /* SODIMM 69 */ + MX7D_PAD_SD1_WP__GPIO5_IO1 0x14 /* SODIMM 71 */ + MX7D_PAD_I2C4_SDA__GPIO4_IO15 0x14 /* SODIMM 75 */ + MX7D_PAD_ECSPI1_MISO__GPIO4_IO18 0x14 /* SODIMM 79 */ + MX7D_PAD_I2C3_SCL__GPIO4_IO12 0x14 /* SODIMM 81 */ + MX7D_PAD_ECSPI2_MISO__GPIO4_IO22 0x14 /* SODIMM 85 */ + MX7D_PAD_ECSPI1_SS0__GPIO4_IO19 0x14 /* SODIMM 97 */ + MX7D_PAD_ECSPI1_SCLK__GPIO4_IO16 0x14 /* SODIMM 101 */ + MX7D_PAD_ECSPI1_MOSI__GPIO4_IO17 0x14 /* SODIMM 103 */ + MX7D_PAD_I2C3_SDA__GPIO4_IO13 0x14 /* SODIMM 94 */ + MX7D_PAD_I2C4_SCL__GPIO4_IO14 0x14 /* SODIMM 96 */ + MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x14 /* SODIMM 98 */ + >; + }; + + pinctrl_gpio3: gpio3-grp { /* LCD 18-23 */ + fsl,pins = < + MX7D_PAD_LCD_DATA18__GPIO3_IO23 0x14 /* SODIMM 136 */ + MX7D_PAD_LCD_DATA19__GPIO3_IO24 0x14 /* SODIMM 138 */ + MX7D_PAD_LCD_DATA20__GPIO3_IO25 0x14 /* SODIMM 140 */ + MX7D_PAD_LCD_DATA21__GPIO3_IO26 0x14 /* SODIMM 142 */ + MX7D_PAD_LCD_DATA22__GPIO3_IO27 0x14 /* SODIMM 146 */ + MX7D_PAD_LCD_DATA23__GPIO3_IO28 0x14 /* SODIMM 148 */ + >; + }; + + pinctrl_gpio4: gpio4-grp { /* Alternatively CAN2 */ + fsl,pins = < + MX7D_PAD_GPIO1_IO15__GPIO1_IO15 0x14 /* SODIMM 178 */ + MX7D_PAD_GPIO1_IO14__GPIO1_IO14 0x14 /* SODIMM 188 */ + >; + }; + + pinctrl_i2c1_int: i2c1-int-grp { /* PMIC / TOUCH */ + fsl,pins = < + MX7D_PAD_GPIO1_IO13__GPIO1_IO13 0x79 + >; + }; + + pinctrl_enet1: enet1grp { + fsl,pins = < + MX7D_PAD_ENET1_CRS__GPIO7_IO14 0x14 + MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x73 + MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x73 + MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x73 + MX7D_PAD_ENET1_RGMII_RXC__ENET1_RX_ER 0x73 + + MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x73 + MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x73 + MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x73 + MX7D_PAD_GPIO1_IO12__CCM_ENET_REF_CLK1 0x73 + MX7D_PAD_SD2_CD_B__ENET1_MDIO 0x3 + MX7D_PAD_SD2_WP__ENET1_MDC 0x3 + >; + }; + + pinctrl_ecspi3_cs: ecspi3-cs-grp { + fsl,pins = < + MX7D_PAD_I2C2_SDA__GPIO4_IO11 0x14 + >; + }; + + pinctrl_ecspi3: ecspi3-grp { + fsl,pins = < + MX7D_PAD_I2C1_SCL__ECSPI3_MISO 0x2 + MX7D_PAD_I2C1_SDA__ECSPI3_MOSI 0x2 + MX7D_PAD_I2C2_SCL__ECSPI3_SCLK 0x2 + >; + }; + + pinctrl_flexcan2: flexcan2-grp { + fsl,pins = < + MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX 0x59 + MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX 0x59 + >; + }; + + pinctrl_gpmi_nand: gpmi-nand-grp { + fsl,pins = < + MX7D_PAD_SD3_CLK__NAND_CLE 0x71 + MX7D_PAD_SD3_CMD__NAND_ALE 0x71 + MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B 0x71 + MX7D_PAD_SAI1_RX_DATA__NAND_CE1_B 0x71 + MX7D_PAD_SAI1_TX_DATA__NAND_READY_B 0x74 + MX7D_PAD_SD3_STROBE__NAND_RE_B 0x71 + MX7D_PAD_SD3_RESET_B__NAND_WE_B 0x71 + MX7D_PAD_SD3_DATA0__NAND_DATA00 0x71 + MX7D_PAD_SD3_DATA1__NAND_DATA01 0x71 + MX7D_PAD_SD3_DATA2__NAND_DATA02 0x71 + MX7D_PAD_SD3_DATA3__NAND_DATA03 0x71 + MX7D_PAD_SD3_DATA4__NAND_DATA04 0x71 + MX7D_PAD_SD3_DATA5__NAND_DATA05 0x71 + MX7D_PAD_SD3_DATA6__NAND_DATA06 0x71 + MX7D_PAD_SD3_DATA7__NAND_DATA07 0x71 + >; + }; + + pinctrl_i2c4: i2c4-grp { + fsl,pins = < + MX7D_PAD_ENET1_RGMII_TD3__I2C4_SDA 0x4000007f + MX7D_PAD_ENET1_RGMII_TD2__I2C4_SCL 0x4000007f + >; + }; + + pinctrl_lcdif_dat: lcdif-dat-grp { + fsl,pins = < + MX7D_PAD_LCD_DATA00__LCD_DATA0 0x79 + MX7D_PAD_LCD_DATA01__LCD_DATA1 0x79 + MX7D_PAD_LCD_DATA02__LCD_DATA2 0x79 + MX7D_PAD_LCD_DATA03__LCD_DATA3 0x79 + MX7D_PAD_LCD_DATA04__LCD_DATA4 0x79 + MX7D_PAD_LCD_DATA05__LCD_DATA5 0x79 + MX7D_PAD_LCD_DATA06__LCD_DATA6 0x79 + MX7D_PAD_LCD_DATA07__LCD_DATA7 0x79 + MX7D_PAD_LCD_DATA08__LCD_DATA8 0x79 + MX7D_PAD_LCD_DATA09__LCD_DATA9 0x79 + MX7D_PAD_LCD_DATA10__LCD_DATA10 0x79 + MX7D_PAD_LCD_DATA11__LCD_DATA11 0x79 + MX7D_PAD_LCD_DATA12__LCD_DATA12 0x79 + MX7D_PAD_LCD_DATA13__LCD_DATA13 0x79 + MX7D_PAD_LCD_DATA14__LCD_DATA14 0x79 + MX7D_PAD_LCD_DATA15__LCD_DATA15 0x79 + MX7D_PAD_LCD_DATA16__LCD_DATA16 0x79 + MX7D_PAD_LCD_DATA17__LCD_DATA17 0x79 + >; + }; + + pinctrl_lcdif_dat_24: lcdif-dat-24-grp { + fsl,pins = < + MX7D_PAD_LCD_DATA18__LCD_DATA18 0x79 + MX7D_PAD_LCD_DATA19__LCD_DATA19 0x79 + MX7D_PAD_LCD_DATA20__LCD_DATA20 0x79 + MX7D_PAD_LCD_DATA21__LCD_DATA21 0x79 + MX7D_PAD_LCD_DATA22__LCD_DATA22 0x79 + MX7D_PAD_LCD_DATA23__LCD_DATA23 0x79 + >; + }; + + pinctrl_lcdif_ctrl: lcdif-ctrl-grp { + fsl,pins = < + MX7D_PAD_LCD_CLK__LCD_CLK 0x79 + MX7D_PAD_LCD_ENABLE__LCD_ENABLE 0x79 + MX7D_PAD_LCD_VSYNC__LCD_VSYNC 0x79 + MX7D_PAD_LCD_HSYNC__LCD_HSYNC 0x79 + >; + }; + + pinctrl_pwm1: pwm1-grp { + fsl,pins = < + MX7D_PAD_GPIO1_IO08__PWM1_OUT 0x79 + >; + }; + + pinctrl_pwm2: pwm2-grp { + fsl,pins = < + MX7D_PAD_GPIO1_IO09__PWM2_OUT 0x79 + >; + }; + + pinctrl_pwm3: pwm3-grp { + fsl,pins = < + MX7D_PAD_GPIO1_IO10__PWM3_OUT 0x79 + >; + }; + + pinctrl_pwm4: pwm4-grp { + fsl,pins = < + MX7D_PAD_GPIO1_IO11__PWM4_OUT 0x79 + >; + }; + + pinctrl_uart1: uart1-grp { + fsl,pins = < + MX7D_PAD_UART1_TX_DATA__UART1_DTE_RX 0x79 + MX7D_PAD_UART1_RX_DATA__UART1_DTE_TX 0x79 + MX7D_PAD_SAI2_TX_BCLK__UART1_DTE_CTS 0x79 + MX7D_PAD_SAI2_TX_SYNC__UART1_DTE_RTS 0x79 + >; + }; + + pinctrl_uart1_ctrl1: uart1-ctrl1-grp { + fsl,pins = < + MX7D_PAD_SD2_DATA1__GPIO5_IO15 0x14 /* DCD */ + MX7D_PAD_SD2_DATA0__GPIO5_IO14 0x14 /* DTR */ + >; + }; + + pinctrl_uart2: uart2-grp { + fsl,pins = < + MX7D_PAD_UART2_TX_DATA__UART2_DTE_RX 0x79 + MX7D_PAD_UART2_RX_DATA__UART2_DTE_TX 0x79 + MX7D_PAD_SAI2_RX_DATA__UART2_DTE_RTS 0x79 + MX7D_PAD_SAI2_TX_DATA__UART2_DTE_CTS 0x79 + >; + }; + pinctrl_uart3: uart3-grp { + fsl,pins = < + MX7D_PAD_UART3_TX_DATA__UART3_DTE_RX 0x79 + MX7D_PAD_UART3_RX_DATA__UART3_DTE_TX 0x79 + >; + }; + + pinctrl_usbotg2_reg: gpio-usbotg2-vbus { + fsl,pins = < + MX7D_PAD_UART3_CTS_B__GPIO4_IO7 0x14 /* SODIMM 129 USBH PEN */ + >; + }; + + pinctrl_usdhc1: usdhc1-grp { + fsl,pins = < + MX7D_PAD_SD1_CMD__SD1_CMD 0x59 + MX7D_PAD_SD1_CLK__SD1_CLK 0x19 + MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59 + MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59 + MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59 + MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59 + >; + }; + + pinctrl_sai1: sai1-grp { + fsl,pins = < + MX7D_PAD_SAI1_MCLK__SAI1_MCLK 0x1f + MX7D_PAD_ENET1_RX_CLK__SAI1_TX_BCLK 0x1f + MX7D_PAD_SAI1_TX_SYNC__SAI1_TX_SYNC 0x1f + MX7D_PAD_ENET1_COL__SAI1_TX_DATA0 0x30 + MX7D_PAD_ENET1_TX_CLK__SAI1_RX_DATA0 0x1f + >; + }; +}; + +&iomuxc_lpsr { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_lpsr>; + + pinctrl_gpio_lpsr: gpio1-grp { + fsl,pins = < + MX7D_PAD_GPIO1_IO01__GPIO1_IO1 0x59 + MX7D_PAD_GPIO1_IO02__GPIO1_IO2 0x59 + MX7D_PAD_GPIO1_IO03__GPIO1_IO3 0x59 + >; + }; + + pinctrl_i2c1: i2c1-grp { + fsl,pins = < + MX7D_PAD_GPIO1_IO05__I2C1_SDA 0x4000007f + MX7D_PAD_GPIO1_IO04__I2C1_SCL 0x4000007f + >; + }; + + pinctrl_cd_usdhc1: usdhc1-cd-grp { + fsl,pins = < + MX7D_PAD_GPIO1_IO00__GPIO1_IO0 0x59 /* CD */ + >; + }; + + pinctrl_uart1_ctrl2: uart1-ctrl2-grp { + fsl,pins = < + MX7D_PAD_GPIO1_IO07__GPIO1_IO7 0x14 /* DSR */ + MX7D_PAD_GPIO1_IO06__GPIO1_IO6 0x14 /* RI */ + >; + }; +}; diff --git a/arch/arm/boot/dts/imx7d-colibri-eval-v3.dts b/arch/arm/boot/dts/imx7d-colibri-eval-v3.dts new file mode 100644 index 0000000..bd01d2c --- /dev/null +++ b/arch/arm/boot/dts/imx7d-colibri-eval-v3.dts @@ -0,0 +1,66 @@ +/* + * Copyright 2016 Toradex AG + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "imx7d-colibri.dtsi" +#include "imx7-colibri-eval-v3.dtsi" + +/ { + model = "Toradex Colibri iMX7D on Colibri Evaluation Board V3"; + compatible = "toradex,colibri-imx7d-eval-v3", "toradex,colibri-imx7d", + "fsl,imx7d"; + + reg_usb_otg2_vbus: regulator-usb-otg2-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg2_reg>; + regulator-name = "VCC_USB[1-4]"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio4 7 GPIO_ACTIVE_LOW>; + }; +}; + +&usbotg2 { + vbus-supply = <®_usb_otg2_vbus>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx7d-colibri.dtsi b/arch/arm/boot/dts/imx7d-colibri.dtsi new file mode 100644 index 0000000..3c2cb50 --- /dev/null +++ b/arch/arm/boot/dts/imx7d-colibri.dtsi @@ -0,0 +1,54 @@ +/* + * Copyright 2016 Toradex AG + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "imx7d.dtsi" +#include "imx7-colibri.dtsi" + +/ { + memory { + reg = <0x80000000 0x20000000>; + }; +}; + +&usbotg2 { + dr_mode = "host"; +}; diff --git a/arch/arm/boot/dts/imx7s-colibri-eval-v3.dts b/arch/arm/boot/dts/imx7s-colibri-eval-v3.dts new file mode 100644 index 0000000..bd2a49c --- /dev/null +++ b/arch/arm/boot/dts/imx7s-colibri-eval-v3.dts @@ -0,0 +1,51 @@ +/* + * Copyright 2016 Toradex AG + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "imx7s-colibri.dtsi" +#include "imx7-colibri-eval-v3.dtsi" + +/ { + model = "Toradex Colibri iMX7S on Colibri Evaluation Board V3"; + compatible = "toradex,colibri-imx7s-eval-v3", "toradex,colibri-imx7s", + "fsl,imx7s"; +}; diff --git a/arch/arm/boot/dts/imx7s-colibri.dtsi b/arch/arm/boot/dts/imx7s-colibri.dtsi new file mode 100644 index 0000000..b810134 --- /dev/null +++ b/arch/arm/boot/dts/imx7s-colibri.dtsi @@ -0,0 +1,50 @@ +/* + * Copyright 2016 Toradex AG + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "imx7s.dtsi" +#include "imx7-colibri.dtsi" + +/ { + memory { + reg = <0x80000000 0x10000000>; + }; +}; -- cgit v0.10.2 From 69b76795e1e262349dc5a8af29eeac25038923ae Mon Sep 17 00:00:00 2001 From: Jiancheng Xue Date: Wed, 15 Jun 2016 10:19:06 +0800 Subject: ARM: dt-bindings: add device tree bindings for Hi3519 sysctrl Add device tree bindings for Hi3519 system controller. Signed-off-by: Jiancheng Xue Acked-by: Rob Herring Signed-off-by: Wei Xu diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hi3519-sysctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/hi3519-sysctrl.txt new file mode 100644 index 0000000..115c5be --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/hi3519-sysctrl.txt @@ -0,0 +1,14 @@ +* Hisilicon Hi3519 System Controller Block + +This bindings use the following binding: +Documentation/devicetree/bindings/mfd/syscon.txt + +Required properties: +- compatible: "hisilicon,hi3519-sysctrl". +- reg: the register region of this block + +Examples: +sysctrl: system-controller@12010000 { + compatible = "hisilicon,hi3519-sysctrl", "syscon"; + reg = <0x12010000 0x1000>; +}; -- cgit v0.10.2 From f8c331bda6a90b239f600020eec1b0defe7249b5 Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Wed, 22 Jun 2016 17:00:35 -0700 Subject: ARM: dts: BCM5301x: Add BCM953012ER board Add support for the Broadcom BCM953012 Enterprise Router reference board, enable the following peripherals: - UART0 (UART1 is not populated) - WPS and restart GPIO buttons - Ethernet switch w/ only two facing ports - NAND flash - SPI-NOR flash Acked-by: Jon Mason Signed-off-by: Florian Fainelli diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 2654eb6..973b0da 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -85,6 +85,7 @@ dtb-$(CONFIG_ARCH_BCM_5301X) += \ bcm47094-dlink-dir-885l.dtb \ bcm94708.dtb \ bcm94709.dtb \ + bcm953012er.dtb \ bcm953012k.dtb dtb-$(CONFIG_ARCH_BCM_63XX) += \ bcm963138dvt.dtb diff --git a/arch/arm/boot/dts/bcm953012er.dts b/arch/arm/boot/dts/bcm953012er.dts new file mode 100644 index 0000000..0a9abec --- /dev/null +++ b/arch/arm/boot/dts/bcm953012er.dts @@ -0,0 +1,104 @@ +/* + * BSD LICENSE + * + * Copyright(c) 2016 Broadcom. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Broadcom Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/dts-v1/; + +#include "bcm4708.dtsi" +#include "bcm5301x-nand-cs0-bch8.dtsi" + +/ { + model = "NorthStar Enterprise Router (BCM953012ER)"; + compatible = "brcm,bcm953012er", "brcm,brcm53012", "brcm,bcm4708"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory { + reg = <0x00000000 0x8000000>; + }; + + gpio-keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + + wps { + label = "WPS"; + linux,code = ; + gpios = <&chipcommon 6 GPIO_ACTIVE_LOW>; + }; + + restart { + label = "Reset"; + linux,code = ; + gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&uart0 { + status = "okay"; +}; + +&spi_nor { + status = "okay"; +}; + +&srab { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "port0"; + }; + + port@1 { + reg = <1>; + label = "port1"; + }; + + port@5 { + reg = <5>; + label = "cpu"; + ethernet = <&gmac0>; + }; + }; +}; -- cgit v0.10.2 From b0062618496a6c5515c04fd04402bbac7686a7bc Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Mon, 27 Jun 2016 15:20:42 -0400 Subject: ARM: dts: omap2: add missing unit name to func_96m_ck This patch fixes the following DTC warnings for omap2430-sdp.dtb: "func_96m_ck has a reg or ranges property, but no unit name" Signed-off-by: Javier Martinez Canillas Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/omap24xx-clocks.dtsi b/arch/arm/boot/dts/omap24xx-clocks.dtsi index ca73722..769a346d 100644 --- a/arch/arm/boot/dts/omap24xx-clocks.dtsi +++ b/arch/arm/boot/dts/omap24xx-clocks.dtsi @@ -164,7 +164,7 @@ clock-div = <1>; }; - func_96m_ck: func_96m_ck { + func_96m_ck: func_96m_ck@540 { #clock-cells = <0>; }; -- cgit v0.10.2 From d5213c0deb27390fe867ca71ce6a603e7b0a8ccc Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Mon, 27 Jun 2016 15:20:43 -0400 Subject: ARM: dts: am3517-craneboard: remove unneeded unit name for fixedregulator This patch fixes the following DTC warnings for am3517-craneboard.dtb: "fixedregulator@0 has a unit name, but no reg property" Signed-off-by: Javier Martinez Canillas Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/am3517-craneboard.dts b/arch/arm/boot/dts/am3517-craneboard.dts index cb7de1d..f9d8f39 100644 --- a/arch/arm/boot/dts/am3517-craneboard.dts +++ b/arch/arm/boot/dts/am3517-craneboard.dts @@ -20,7 +20,7 @@ reg = <0x80000000 0x10000000>; /* 256 MB */ }; - vbat: fixedregulator@0 { + vbat: fixedregulator { compatible = "regulator-fixed"; regulator-name = "vbat"; regulator-min-microvolt = <5000000>; -- cgit v0.10.2 From 5ce86920da06754eebb88642684ff37c52397728 Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Mon, 27 Jun 2016 15:20:44 -0400 Subject: ARM: dts: dm3730-torpedo-devkit: remove unneeded unit names This patch fixes the following DTC warnings: "dmtimer-pwm@10 has a unit name, but no reg property" "display@0 has a unit name, but no reg property" Signed-off-by: Javier Martinez Canillas Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/logicpd-torpedo-37xx-devkit.dts b/arch/arm/boot/dts/logicpd-torpedo-37xx-devkit.dts index 015f795..08cce17 100644 --- a/arch/arm/boot/dts/logicpd-torpedo-37xx-devkit.dts +++ b/arch/arm/boot/dts/logicpd-torpedo-37xx-devkit.dts @@ -72,7 +72,7 @@ }; }; - pwm10: dmtimer-pwm@10 { + pwm10: dmtimer-pwm { compatible = "ti,omap-dmtimer-pwm"; pinctrl-names = "default"; pinctrl-0 = <&pwm_pins>; @@ -147,7 +147,7 @@ gpio = <&gpio5 27 GPIO_ACTIVE_HIGH>; /* gpio155, lcd INI */ }; - lcd0: display@0 { + lcd0: display { compatible = "panel-dpi"; label = "15"; status = "okay"; -- cgit v0.10.2 From cc9a4bdadadbbcd354d1e0172ce55f19f1e41d80 Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Mon, 27 Jun 2016 15:20:45 -0400 Subject: ARM: dts: n900: remove unneeded unit name for dmtimer-pwm This patch fixes the following DTC warnings for omap3-n900.dtb: "dmtimer-pwm@9 has a unit name, but no reg property" Signed-off-by: Javier Martinez Canillas Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/omap3-n900.dts b/arch/arm/boot/dts/omap3-n900.dts index 0ceff5d..cac9a8b 100644 --- a/arch/arm/boot/dts/omap3-n900.dts +++ b/arch/arm/boot/dts/omap3-n900.dts @@ -144,7 +144,7 @@ io-channel-names = "temp", "bsi", "vbat"; }; - pwm9: dmtimer-pwm@9 { + pwm9: dmtimer-pwm { compatible = "ti,omap-dmtimer-pwm"; #pwm-cells = <3>; ti,timers = <&timer9>; -- cgit v0.10.2 From a3c4c7578ab5447095b8fdf1db16d6a5aca38404 Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Mon, 27 Jun 2016 15:20:46 -0400 Subject: ARM: dts: omap3-beagle: remove unneeded unit names This patch fixes the following DTC warnings for omap3-beagle.dtb: "encoder@0 has a unit name, but no reg property" "encoder@0/ports/port@0/endpoint@0 has a unit name, but no reg property" "encoder@0/ports/port@1/endpoint@0 has a unit name, but no reg property" "connector@0 has a unit name, but no reg property" "connector@1 has a unit name, but no reg property" Signed-off-by: Javier Martinez Canillas Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/omap3-beagle.dts b/arch/arm/boot/dts/omap3-beagle.dts index a4deff0..a19d907 100644 --- a/arch/arm/boot/dts/omap3-beagle.dts +++ b/arch/arm/boot/dts/omap3-beagle.dts @@ -85,7 +85,7 @@ }; - tfp410: encoder@0 { + tfp410: encoder0 { compatible = "ti,tfp410"; powerdown-gpios = <&gpio6 10 GPIO_ACTIVE_LOW>; /* gpio_170 */ @@ -99,7 +99,7 @@ port@0 { reg = <0>; - tfp410_in: endpoint@0 { + tfp410_in: endpoint { remote-endpoint = <&dpi_out>; }; }; @@ -107,14 +107,14 @@ port@1 { reg = <1>; - tfp410_out: endpoint@0 { + tfp410_out: endpoint { remote-endpoint = <&dvi_connector_in>; }; }; }; }; - dvi0: connector@0 { + dvi0: connector0 { compatible = "dvi-connector"; label = "dvi"; @@ -129,7 +129,7 @@ }; }; - tv0: connector@1 { + tv0: connector1 { compatible = "svideo-connector"; label = "tv"; -- cgit v0.10.2 From a58280e5b1ac9efe75c2054b1d7896c6654c45d0 Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Mon, 27 Jun 2016 15:20:47 -0400 Subject: ARM: dts: omap3-beagle-xm: remove unneeded unit names This patch fixes the following DTC warnings for omap3-beagle-xm.dtb: "encoder@0 has a unit name, but no reg property" "encoder@0/ports/port@0/endpoint@0 has a unit name, but no reg property" "encoder@0/ports/port@1/endpoint@0 has a unit name, but no reg property" "connector@0 has a unit name, but no reg property" "connector@1 has a unit name, but no reg property" Signed-off-by: Javier Martinez Canillas Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/omap3-beagle-xm.dts b/arch/arm/boot/dts/omap3-beagle-xm.dts index 01e1e2d..8ffde06 100644 --- a/arch/arm/boot/dts/omap3-beagle-xm.dts +++ b/arch/arm/boot/dts/omap3-beagle-xm.dts @@ -91,7 +91,7 @@ vcc-supply = <&hsusb2_power>; }; - tfp410: encoder@0 { + tfp410: encoder0 { compatible = "ti,tfp410"; powerdown-gpios = <&twl_gpio 2 GPIO_ACTIVE_LOW>; @@ -104,7 +104,7 @@ port@0 { reg = <0>; - tfp410_in: endpoint@0 { + tfp410_in: endpoint { remote-endpoint = <&dpi_out>; }; }; @@ -112,14 +112,14 @@ port@1 { reg = <1>; - tfp410_out: endpoint@0 { + tfp410_out: endpoint { remote-endpoint = <&dvi_connector_in>; }; }; }; }; - dvi0: connector@0 { + dvi0: connector0 { compatible = "dvi-connector"; label = "dvi"; @@ -134,7 +134,7 @@ }; }; - tv0: connector@1 { + tv0: connector1 { compatible = "svideo-connector"; label = "tv"; -- cgit v0.10.2 From bc1dcd57d67acd29596fc313603f3e0634c3eacb Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Mon, 27 Jun 2016 15:20:48 -0400 Subject: ARM: dts: cm-t3x: remove unneeded unit name in connector This patch fixes the following DTC warnings for omap3-cm-t3517.dtb, omap3-cm-t3530.dtb and omap3-cm-t3730.dtb: "connector@1 has a unit name, but no reg property" Signed-off-by: Javier Martinez Canillas Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/omap3-cm-t3x.dtsi b/arch/arm/boot/dts/omap3-cm-t3x.dtsi index a8127bc..6a0df13 100644 --- a/arch/arm/boot/dts/omap3-cm-t3x.dtsi +++ b/arch/arm/boot/dts/omap3-cm-t3x.dtsi @@ -57,7 +57,7 @@ regulator-max-microvolt = <3300000>; }; - tv0: connector@1 { + tv0: connector { compatible = "svideo-connector"; label = "tv"; -- cgit v0.10.2 From 80ca8bed603454d2d84f4fa3836604706ec4d525 Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Mon, 27 Jun 2016 15:20:49 -0400 Subject: ARM: dts: omap3-devkit8000: remove unneeded unit names This patch fixes the following DTC warnings for omap3-devkit8000.dtb, omap3-devkit8000-lcd43.dtb and omap3-devkit8000-lcd70.dtb: "encoder@0 has a unit name, but no reg property" "endpoint@0 has a unit name, but no reg property" "connector@0 has a unit name, but no reg property" "connector@1 has a unit name, but no reg property" Signed-off-by: Javier Martinez Canillas Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/omap3-devkit8000-common.dtsi b/arch/arm/boot/dts/omap3-devkit8000-common.dtsi index b1b8ebf..5860101 100644 --- a/arch/arm/boot/dts/omap3-devkit8000-common.dtsi +++ b/arch/arm/boot/dts/omap3-devkit8000-common.dtsi @@ -68,7 +68,7 @@ }; }; - tfp410: encoder@0 { + tfp410: encoder0 { compatible = "ti,tfp410"; powerdown-gpios = <&twl_gpio 7 GPIO_ACTIVE_LOW>; @@ -79,7 +79,7 @@ port@0 { reg = <0>; - tfp410_in: endpoint@0 { + tfp410_in: endpoint { remote-endpoint = <&dpi_dvi_out>; }; }; @@ -87,14 +87,14 @@ port@1 { reg = <1>; - tfp410_out: endpoint@0 { + tfp410_out: endpoint { remote-endpoint = <&dvi_connector_in>; }; }; }; }; - dvi0: connector@0 { + dvi0: connector0 { compatible = "dvi-connector"; label = "dvi"; @@ -109,7 +109,7 @@ }; }; - tv0: connector@1 { + tv0: connector1 { compatible = "svideo-connector"; label = "tv"; @@ -352,7 +352,7 @@ vdda_dac-supply = <&vdac>; port { - dpi_dvi_out: endpoint@0 { + dpi_dvi_out: endpoint { remote-endpoint = <&tfp410_in>; data-lines = <24>; }; -- cgit v0.10.2 From a346cea1af144cbad650c078ee6bf1f7cc788d18 Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Mon, 27 Jun 2016 15:20:50 -0400 Subject: ARM: dts: omap3-devkit8000-lcd-common: remove unneeded unit names This patch fixes the following DTC warnings for omap3-devkit8000-lcd43.dtb and omap3-devkit8000-lcd70.dtb: "display@0 has a unit name, but no reg property" Signed-off-by: Javier Martinez Canillas Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/omap3-devkit8000-lcd-common.dtsi b/arch/arm/boot/dts/omap3-devkit8000-lcd-common.dtsi index 738910d..2d64bcf 100644 --- a/arch/arm/boot/dts/omap3-devkit8000-lcd-common.dtsi +++ b/arch/arm/boot/dts/omap3-devkit8000-lcd-common.dtsi @@ -14,7 +14,7 @@ display2 = &tv0; }; - lcd0: display@0 { + lcd0: display { compatible = "panel-dpi"; label = "lcd"; @@ -30,7 +30,7 @@ &dss { port { - dpi_lcd_out: endpoint@1 { + dpi_lcd_out: endpoint { remote-endpoint = <&lcd_in>; data-lines = <24>; }; diff --git a/arch/arm/boot/dts/omap3-devkit8000-lcd43.dts b/arch/arm/boot/dts/omap3-devkit8000-lcd43.dts index d570535..d8b1639 100644 --- a/arch/arm/boot/dts/omap3-devkit8000-lcd43.dts +++ b/arch/arm/boot/dts/omap3-devkit8000-lcd43.dts @@ -16,7 +16,7 @@ model = "TimLL OMAP3 Devkit8000 with 4.3'' LCD panel"; compatible = "timll,omap3-devkit8000", "ti,omap3"; - lcd0: display@0 { + lcd0: display { panel-timing { clock-frequency = <10164705>; hactive = <480>; diff --git a/arch/arm/boot/dts/omap3-devkit8000-lcd70.dts b/arch/arm/boot/dts/omap3-devkit8000-lcd70.dts index 4afad4b..edb37ba 100644 --- a/arch/arm/boot/dts/omap3-devkit8000-lcd70.dts +++ b/arch/arm/boot/dts/omap3-devkit8000-lcd70.dts @@ -16,7 +16,7 @@ model = "TimLL OMAP3 Devkit8000 with 7.0'' LCD panel"; compatible = "timll,omap3-devkit8000", "ti,omap3"; - lcd0: display@0 { + lcd0: display { panel-timing { clock-frequency = <40000000>; hactive = <800>; -- cgit v0.10.2 From 314fdd5de1123fb355248582b6fc0cf837793f4b Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Mon, 27 Jun 2016 15:20:51 -0400 Subject: ARM: dts: omap3-gta04: remove unneeded unit names This patch fixes the following DTC warnings for omap3-gta04a3.dtb, omap3-gta04a4.dtb and omap3-gta04a5.dtb: "dmtimer-pwm@11 has a unit name, but no reg property" "connector@1 has a unit name, but no reg property" "endpoint@0 has a unit name, but no reg property" Signed-off-by: Javier Martinez Canillas Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/omap3-gta04.dtsi b/arch/arm/boot/dts/omap3-gta04.dtsi index 3eb53bc..c09a057 100644 --- a/arch/arm/boot/dts/omap3-gta04.dtsi +++ b/arch/arm/boot/dts/omap3-gta04.dtsi @@ -110,7 +110,7 @@ pinctrl-0 = <&backlight_pins>; }; - pwm11: dmtimer-pwm@11 { + pwm11: dmtimer-pwm { compatible = "ti,omap-dmtimer-pwm"; ti,timers = <&timer11>; #pwm-cells = <3>; @@ -121,7 +121,7 @@ reset-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>; }; - tv0: connector@1 { + tv0: connector { compatible = "svideo-connector"; label = "tv"; @@ -142,14 +142,14 @@ port@0 { reg = <0>; - opa_in: endpoint@0 { + opa_in: endpoint { remote-endpoint = <&venc_out>; }; }; port@1 { reg = <1>; - opa_out: endpoint@0 { + opa_out: endpoint { remote-endpoint = <&tv_connector_in>; }; }; -- cgit v0.10.2 From f41c1c182308a49d449775557ffeecdb8a68d721 Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Mon, 27 Jun 2016 15:20:52 -0400 Subject: ARM: dts: omap3-ha-lcd: remove unneeded unit name This patch fixes the following DTC warnings for omap3-ha-lcd.dtb: "display@0 has a unit name, but no reg property" Signed-off-by: Javier Martinez Canillas Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/omap3-ha-lcd.dts b/arch/arm/boot/dts/omap3-ha-lcd.dts index 11aa28d..60af7c2 100644 --- a/arch/arm/boot/dts/omap3-ha-lcd.dts +++ b/arch/arm/boot/dts/omap3-ha-lcd.dts @@ -121,7 +121,7 @@ display0 = &lcd0; }; - lcd0: display@0 { + lcd0: display { compatible = "panel-dpi"; label = "lcd"; -- cgit v0.10.2 From b8d368caa8dcc4436e4e64aa1d045b18bbe6c637 Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Mon, 27 Jun 2016 15:20:53 -0400 Subject: ARM: dts: omap3: overo: remove unneded unit names in display nodes This patch fixes the following DTC warnings for omap3-overo-gallop43.dtb, omap3-overo-chestnut43.dtb, omap3-overo-storm-chestnut43.dtb, omap3-overo-palo43.dtb, and omap3-overo-storm-palo43.dtb: "display@0 has a unit name, but no reg property" Signed-off-by: Javier Martinez Canillas Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/omap3-overo-common-lcd35.dtsi b/arch/arm/boot/dts/omap3-overo-common-lcd35.dtsi index 6314da2..ca86da6 100644 --- a/arch/arm/boot/dts/omap3-overo-common-lcd35.dtsi +++ b/arch/arm/boot/dts/omap3-overo-common-lcd35.dtsi @@ -119,7 +119,7 @@ pinctrl-names = "default"; pinctrl-0 = <&mcspi1_pins>; - lcd0: display@0 { + lcd0: display { compatible = "lgphilips,lb035q02"; label = "lcd35"; diff --git a/arch/arm/boot/dts/omap3-overo-common-lcd43.dtsi b/arch/arm/boot/dts/omap3-overo-common-lcd43.dtsi index 7e3fe85..b0753ef 100644 --- a/arch/arm/boot/dts/omap3-overo-common-lcd43.dtsi +++ b/arch/arm/boot/dts/omap3-overo-common-lcd43.dtsi @@ -96,7 +96,7 @@ display0 = &lcd0; }; - lcd0: display@0 { + lcd0: display { compatible = "samsung,lte430wq-f0c", "panel-dpi"; label = "lcd43"; -- cgit v0.10.2 From d0cdbd08606e42104f2fdacc660715c763ea4333 Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Mon, 27 Jun 2016 15:20:54 -0400 Subject: ARM: dts: omap3-igep0020-common: remove unneded unit names This patch fixes the following DTC warnings for omap3-igep0020.dtb and omap3-igep0020-rev-f.dtb: "encoder@0 has a unit name, but no reg property" "endpoint@0 has a unit name, but no reg property" "connector@0 has a unit name, but no reg property" Signed-off-by: Javier Martinez Canillas Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/omap3-igep0020-common.dtsi b/arch/arm/boot/dts/omap3-igep0020-common.dtsi index d6f839c..6af8154 100644 --- a/arch/arm/boot/dts/omap3-igep0020-common.dtsi +++ b/arch/arm/boot/dts/omap3-igep0020-common.dtsi @@ -60,7 +60,7 @@ vcc-supply = <&hsusb1_power>; }; - tfp410: encoder@0 { + tfp410: encoder { compatible = "ti,tfp410"; powerdown-gpios = <&gpio6 10 GPIO_ACTIVE_LOW>; /* gpio_170 */ @@ -71,7 +71,7 @@ port@0 { reg = <0>; - tfp410_in: endpoint@0 { + tfp410_in: endpoint { remote-endpoint = <&dpi_out>; }; }; @@ -79,14 +79,14 @@ port@1 { reg = <1>; - tfp410_out: endpoint@0 { + tfp410_out: endpoint { remote-endpoint = <&dvi_connector_in>; }; }; }; }; - dvi0: connector@0 { + dvi0: connector { compatible = "dvi-connector"; label = "dvi"; -- cgit v0.10.2 From e4fab1f4a3b468fa23ae7d819a18078c14bfa1e0 Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Mon, 27 Jun 2016 15:20:55 -0400 Subject: ARM: dts: omap3-overo-common-dvi: remove unneded unit names This patch fixes the following DTC warnings for omap3-overo-summit.dtb, omap3-overo-storm-tobi.dtb, omap3-overo-storm-summit.dtb and omap3-overo-tobi.dtb: "encoder@0 has a unit name, but no reg property" "endpoint@0 has a unit name, but no reg property" "connector@0 has a unit name, but no reg property" Signed-off-by: Javier Martinez Canillas Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/omap3-overo-common-dvi.dtsi b/arch/arm/boot/dts/omap3-overo-common-dvi.dtsi index 802f704f..ae5564a 100644 --- a/arch/arm/boot/dts/omap3-overo-common-dvi.dtsi +++ b/arch/arm/boot/dts/omap3-overo-common-dvi.dtsi @@ -69,7 +69,7 @@ display0 = &dvi0; }; - tfp410: encoder@0 { + tfp410: encoder { compatible = "ti,tfp410"; ports { @@ -79,7 +79,7 @@ port@0 { reg = <0>; - tfp410_in: endpoint@0 { + tfp410_in: endpoint { remote-endpoint = <&dpi_out>; }; }; @@ -87,14 +87,14 @@ port@1 { reg = <1>; - tfp410_out: endpoint@0 { + tfp410_out: endpoint { remote-endpoint = <&dvi_connector_in>; }; }; }; }; - dvi0: connector@0 { + dvi0: connector { compatible = "dvi-connector"; label = "dvi"; -- cgit v0.10.2 From f82bc163b715e82e924dac88cea7940752df4c97 Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Mon, 27 Jun 2016 15:20:56 -0400 Subject: ARM: dts: omap3-pandora-common: remove unneded unit name This patch fixes the following DTC warnings for omap3-pandora-600mhz.dtb and omap3-pandora-1ghz.dtb: "connector@1 has a unit name, but no reg property" Signed-off-by: Javier Martinez Canillas Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/omap3-pandora-common.dtsi b/arch/arm/boot/dts/omap3-pandora-common.dtsi index bcf39d6..dbc4dc7 100644 --- a/arch/arm/boot/dts/omap3-pandora-common.dtsi +++ b/arch/arm/boot/dts/omap3-pandora-common.dtsi @@ -27,7 +27,7 @@ display0 = &lcd; }; - tv: connector@1 { + tv: connector { compatible = "connector-analog-tv"; label = "tv"; -- cgit v0.10.2 From ece8410a518ccccc5a1ecc8797c3ac2b7f6b81f4 Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Mon, 27 Jun 2016 15:20:57 -0400 Subject: ARM: dts: sbc-t3x30: remove unneded unit names This patch fixes the following DTC warnings for omap3-sbc-t3517.dtb, omap3-sbc-t3530.dtb and omap3-sbc-t3730.dtb: "encoder@0 has a unit name, but no reg property" "endpoint@0 has a unit name, but no reg property" "connector@0 has a unit name, but no reg property" Signed-off-by: Javier Martinez Canillas Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/omap3-sb-t35.dtsi b/arch/arm/boot/dts/omap3-sb-t35.dtsi index 827f614..73643fa 100644 --- a/arch/arm/boot/dts/omap3-sb-t35.dtsi +++ b/arch/arm/boot/dts/omap3-sb-t35.dtsi @@ -3,7 +3,7 @@ */ / { - tfp410: encoder@0 { + tfp410: encoder { compatible = "ti,tfp410"; powerdown-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>; /* gpio_54 */ @@ -18,7 +18,7 @@ port@0 { reg = <0>; - tfp410_in: endpoint@0 { + tfp410_in: endpoint { remote-endpoint = <&dpi_out>; }; }; @@ -26,14 +26,14 @@ port@1 { reg = <1>; - tfp410_out: endpoint@0 { + tfp410_out: endpoint { remote-endpoint = <&dvi_connector_in>; }; }; }; }; - dvi0: connector@0 { + dvi0: connector { compatible = "dvi-connector"; label = "dvi"; -- cgit v0.10.2 From 22a0f93b738d8943751208283feb3e215aa67ef4 Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Mon, 27 Jun 2016 15:20:58 -0400 Subject: ARM: dts: omap3-thunder: remove unneded unit name This patch fixes the following DTC warnings for omap3-thunder.dtb: "display@0 has a unit name, but no reg property" Signed-off-by: Javier Martinez Canillas Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/omap3-thunder.dts b/arch/arm/boot/dts/omap3-thunder.dts index d659515..9736ba7 100644 --- a/arch/arm/boot/dts/omap3-thunder.dts +++ b/arch/arm/boot/dts/omap3-thunder.dts @@ -85,7 +85,7 @@ display0 = &lcd0; }; - lcd0: display@0 { + lcd0: display { compatible = "samsung,lte430wq-f0c", "panel-dpi"; label = "lcd"; -- cgit v0.10.2 From a8339ccebd25c1dc1b7de5f3950197ea37bb55e4 Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Mon, 27 Jun 2016 15:20:59 -0400 Subject: ARM: dts: omap4-duovero-parlor: remove unneded unit name This patch fixes the following DTC warnings for omap4-duovero-parlor.dtb: "connector@0 has a unit name, but no reg property" Signed-off-by: Javier Martinez Canillas Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/omap4-duovero-parlor.dts b/arch/arm/boot/dts/omap4-duovero-parlor.dts index 06c5482..6b39808 100644 --- a/arch/arm/boot/dts/omap4-duovero-parlor.dts +++ b/arch/arm/boot/dts/omap4-duovero-parlor.dts @@ -40,7 +40,7 @@ }; }; - hdmi0: connector@0 { + hdmi0: connector { compatible = "hdmi-connector"; label = "hdmi"; -- cgit v0.10.2 From 9e19d0d1cd2055e5e0fba5e43c676a2f3ebc3a52 Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Mon, 27 Jun 2016 15:21:00 -0400 Subject: ARM: dts: omap4-panda-common: remove unneded unit names This patch fixes the following DTC warnings for omap4-panda.dtb, omap4-panda-a4.dtb and omap4-panda-es.dtb: "encoder@0 has a unit name, but no reg property" "endpoint@0 has a unit name, but no reg property" "connector@0 has a unit name, but no reg property" "encoder@1 has a unit name, but no reg property" "connector@1 has a unit name, but no reg property" Signed-off-by: Javier Martinez Canillas Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi b/arch/arm/boot/dts/omap4-panda-common.dtsi index e1d606f..f8f1395 100644 --- a/arch/arm/boot/dts/omap4-panda-common.dtsi +++ b/arch/arm/boot/dts/omap4-panda-common.dtsi @@ -103,7 +103,7 @@ enable-active-high; }; - tfp410: encoder@0 { + tfp410: encoder0 { compatible = "ti,tfp410"; powerdown-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; /* gpio_0 */ @@ -114,7 +114,7 @@ port@0 { reg = <0>; - tfp410_in: endpoint@0 { + tfp410_in: endpoint { remote-endpoint = <&dpi_out>; }; }; @@ -122,14 +122,14 @@ port@1 { reg = <1>; - tfp410_out: endpoint@0 { + tfp410_out: endpoint { remote-endpoint = <&dvi_connector_in>; }; }; }; }; - dvi0: connector@0 { + dvi0: connector0 { compatible = "dvi-connector"; label = "dvi"; @@ -144,7 +144,7 @@ }; }; - tpd12s015: encoder@1 { + tpd12s015: encoder1 { compatible = "ti,tpd12s015"; gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>, /* 60, CT CP HPD */ @@ -158,7 +158,7 @@ port@0 { reg = <0>; - tpd12s015_in: endpoint@0 { + tpd12s015_in: endpoint { remote-endpoint = <&hdmi_out>; }; }; @@ -166,14 +166,14 @@ port@1 { reg = <1>; - tpd12s015_out: endpoint@0 { + tpd12s015_out: endpoint { remote-endpoint = <&hdmi_connector_in>; }; }; }; }; - hdmi0: connector@1 { + hdmi0: connector1 { compatible = "hdmi-connector"; label = "hdmi"; -- cgit v0.10.2 From f9a1017a9a260518d120be7f45782d90031ecf3a Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Mon, 27 Jun 2016 15:21:01 -0400 Subject: ARM: dts: omap4-sdp: remove unneded unit names This patch fixes the following DTC warnings for omap4-sdp.dtb and omap4-sdp-es23plus.dtb: "encoder@0 has a unit name, but no reg property" "endpoint@0 has a unit name, but no reg property" "connector@0 has a unit name, but no reg property" Signed-off-by: Javier Martinez Canillas Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/omap4-sdp.dts b/arch/arm/boot/dts/omap4-sdp.dts index 7e6cd2d..10d73a7 100644 --- a/arch/arm/boot/dts/omap4-sdp.dts +++ b/arch/arm/boot/dts/omap4-sdp.dts @@ -160,7 +160,7 @@ enable-active-high; }; - tpd12s015: encoder@0 { + tpd12s015: encoder { compatible = "ti,tpd12s015"; gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>, /* 60, CT CP HPD */ @@ -174,7 +174,7 @@ port@0 { reg = <0>; - tpd12s015_in: endpoint@0 { + tpd12s015_in: endpoint { remote-endpoint = <&hdmi_out>; }; }; @@ -182,14 +182,14 @@ port@1 { reg = <1>; - tpd12s015_out: endpoint@0 { + tpd12s015_out: endpoint { remote-endpoint = <&hdmi_connector_in>; }; }; }; }; - hdmi0: connector@0 { + hdmi0: connector { compatible = "hdmi-connector"; label = "hdmi"; -- cgit v0.10.2 From b536ccbfff0f827a726fcecfde6893f71d1a9e87 Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Mon, 27 Jun 2016 15:21:02 -0400 Subject: ARM: dts: omap4-var-om44customboard: remove unneded unit name This patch fixes the following DTC warnings for omap4-var-dvk-om44.dtb and omap4-var-stk-om44.dtb: "connector@0 has a unit name, but no reg property" Signed-off-by: Javier Martinez Canillas Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/omap4-var-om44customboard.dtsi b/arch/arm/boot/dts/omap4-var-om44customboard.dtsi index 6e278d7..74940b6 100644 --- a/arch/arm/boot/dts/omap4-var-om44customboard.dtsi +++ b/arch/arm/boot/dts/omap4-var-om44customboard.dtsi @@ -45,7 +45,7 @@ }; }; - hdmi0: connector@0 { + hdmi0: connector { compatible = "hdmi-connector"; pinctrl-names = "default"; pinctrl-0 = <&hdmi_hpd_pins>; -- cgit v0.10.2 From bc8bffd0475adc4b4971e21764d63af90b4e3a86 Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Mon, 27 Jun 2016 15:21:03 -0400 Subject: ARM: dts: am43xx-epos-evm: remove unneded unit name This patch fixes the following DTC warnings for am43xx-epos-evm.dtb: "endpoint@0 has a unit name, but no reg property" Signed-off-by: Javier Martinez Canillas Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/am43x-epos-evm.dts b/arch/arm/boot/dts/am43x-epos-evm.dts index 3549b8c..ad32e55 100644 --- a/arch/arm/boot/dts/am43x-epos-evm.dts +++ b/arch/arm/boot/dts/am43x-epos-evm.dts @@ -754,7 +754,7 @@ pinctrl-0 = <&dss_pins>; port { - dpi_out: endpoint@0 { + dpi_out: endpoint { remote-endpoint = <&lcd_in>; data-lines = <24>; }; -- cgit v0.10.2 From 7d304f73eff213d53110f34686f9403f20192480 Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Mon, 27 Jun 2016 15:21:04 -0400 Subject: ARM: dts: am437x-gp-evm: remove unneded unit name This patch fixes the following DTC warnings for am437x-gp-evm.dtb: "endpoint@0 has a unit name, but no reg property" Signed-off-by: Javier Martinez Canillas Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/am437x-gp-evm.dts b/arch/arm/boot/dts/am437x-gp-evm.dts index 84832bf..14677d5 100644 --- a/arch/arm/boot/dts/am437x-gp-evm.dts +++ b/arch/arm/boot/dts/am437x-gp-evm.dts @@ -897,7 +897,7 @@ pinctrl-0 = <&dss_pins>; port { - dpi_out: endpoint@0 { + dpi_out: endpoint { remote-endpoint = <&lcd_in>; data-lines = <24>; }; -- cgit v0.10.2 From a264578805469942f0d0206284ad21ce70ca08c6 Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Mon, 27 Jun 2016 15:21:05 -0400 Subject: ARM: dts: am437x: cm-t43: remove unneded unit names This patch fixes the following DTC warnings for am437x-sbc-t43.dtb: "endpoint@0 has a unit name, but no reg property" "connector@0 has a unit name, but no reg property" Signed-off-by: Javier Martinez Canillas Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/am437x-sbc-t43.dts b/arch/arm/boot/dts/am437x-sbc-t43.dts index 5f750c0..d23260d 100644 --- a/arch/arm/boot/dts/am437x-sbc-t43.dts +++ b/arch/arm/boot/dts/am437x-sbc-t43.dts @@ -145,7 +145,7 @@ pinctrl-0 = <&dss_pinctrl_default>; port { - dpi_lcd_out: endpoint@0 { + dpi_lcd_out: endpoint { remote-endpoint = <&lcd_in>; data-lines = <24>; }; diff --git a/arch/arm/boot/dts/compulab-sb-som.dtsi b/arch/arm/boot/dts/compulab-sb-som.dtsi index 93d7e23..4af1adf 100644 --- a/arch/arm/boot/dts/compulab-sb-som.dtsi +++ b/arch/arm/boot/dts/compulab-sb-som.dtsi @@ -40,7 +40,7 @@ }; }; - hdmi_conn: connector@0 { + hdmi_conn: connector { compatible = "hdmi-connector"; label = "hdmi"; -- cgit v0.10.2 From 3a76e98840a18fe1099b2245d0a58ef45ce21ca3 Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Mon, 27 Jun 2016 15:21:06 -0400 Subject: ARM: dts: omap5-cm-t54: remove unneded unit names and add reg properties This patch fixes the following DTC warnings for omap5-cm-t54.dtb: "connector@0 has a unit name, but no reg property" "encoder@0 has a unit name, but no reg property" "endpoint@0 has a unit name, but no reg property" "connector@1 has a unit name, but no reg property" Signed-off-by: Javier Martinez Canillas Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/omap5-cm-t54.dts b/arch/arm/boot/dts/omap5-cm-t54.dts index 93fdfa9..a976560 100644 --- a/arch/arm/boot/dts/omap5-cm-t54.dts +++ b/arch/arm/boot/dts/omap5-cm-t54.dts @@ -112,7 +112,7 @@ }; }; - hdmi0: connector@0 { + hdmi0: connector0 { compatible = "hdmi-connector"; label = "hdmi"; @@ -130,7 +130,7 @@ }; }; - tfp410: encoder@0 { + tfp410: encoder0 { compatible = "ti,tfp410"; ports { @@ -140,7 +140,7 @@ port@0 { reg = <0>; - tfp410_in: endpoint@0 { + tfp410_in: endpoint { remote-endpoint = <&dpi_dvi_out>; }; }; @@ -148,14 +148,14 @@ port@1 { reg = <1>; - tfp410_out: endpoint@0 { + tfp410_out: endpoint { remote-endpoint = <&dvi_connector_in>; }; }; }; }; - dvi0: connector@1 { + dvi0: connector1 { compatible = "dvi-connector"; label = "dvi"; @@ -646,12 +646,17 @@ pinctrl-0 = <&dss_dpi_pins>; port { + #address-cells = <1>; + #size-cells = <0>; + dpi_dvi_out: endpoint@0 { + reg = <0>; remote-endpoint = <&tfp410_in>; data-lines = <24>; }; dpi_lcd_out: endpoint@1 { + reg = <1>; remote-endpoint = <&lcd_in>; data-lines = <24>; }; -- cgit v0.10.2 From e6db7f1ab22dc700858f6cfbb8a0f40dd208e63c Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Mon, 27 Jun 2016 15:21:07 -0400 Subject: ARM: dts: omap5-board-common: remove unneded unit names This patch fixes the following DTC warnings for omap5-igep0050.dtb, omap5-sbc-t54.dtb and omap5-uevm.dtb: "connector@0 has a unit name, but no reg property" "endpoint@0 has a unit name, but no reg property" "encoder@0 has a unit name, but no reg property" Signed-off-by: Javier Martinez Canillas Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/omap5-board-common.dtsi b/arch/arm/boot/dts/omap5-board-common.dtsi index b95b221..f73934e 100644 --- a/arch/arm/boot/dts/omap5-board-common.dtsi +++ b/arch/arm/boot/dts/omap5-board-common.dtsi @@ -64,7 +64,7 @@ }; }; - tpd12s015: encoder@0 { + tpd12s015: encoder { compatible = "ti,tpd12s015"; pinctrl-names = "default"; @@ -79,7 +79,7 @@ port@0 { reg = <0>; - tpd12s015_in: endpoint@0 { + tpd12s015_in: endpoint { remote-endpoint = <&hdmi_out>; }; }; @@ -87,14 +87,14 @@ port@1 { reg = <1>; - tpd12s015_out: endpoint@0 { + tpd12s015_out: endpoint { remote-endpoint = <&hdmi_connector_in>; }; }; }; }; - hdmi0: connector@0 { + hdmi0: connector { compatible = "hdmi-connector"; label = "hdmi"; -- cgit v0.10.2 From 480985b06c8e3999940929bf024042e4181bbdce Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Mon, 27 Jun 2016 15:21:08 -0400 Subject: ARM: dts: am57xx: sbc-am57x: remove unneded unit name This patch fixes the following DTC warnings for am57xx-sbc-am57x.dtb: "endpoint@0 has a unit name, but no reg property" Signed-off-by: Javier Martinez Canillas Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/am57xx-sbc-am57x.dts b/arch/arm/boot/dts/am57xx-sbc-am57x.dts index 988e996..31f9be6 100644 --- a/arch/arm/boot/dts/am57xx-sbc-am57x.dts +++ b/arch/arm/boot/dts/am57xx-sbc-am57x.dts @@ -128,7 +128,7 @@ vdda_video-supply = <&ldoln_reg>; port { - dpi_lcd_out: endpoint@0 { + dpi_lcd_out: endpoint { remote-endpoint = <&lcd_in>; data-lines = <24>; }; -- cgit v0.10.2 From 1403e38b829acdad5679862a5949e408bca2279a Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 14 Jun 2016 16:15:20 +0200 Subject: ARM: dts: armadillo800eva: Update console parameters Change the console alias to "serial0", for consistency with other boards (the first unlabeled serial port is always called "serial0"). This does change the serial console from /dev/ttySC1 to /dev/ttySC0. Add the serial port config to "chosen/stdout-path", which requires referring to the port by alias. Drop the "console=" parameters from the kernel command line, as they're no longer needed for DT-based platforms. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman diff --git a/arch/arm/boot/dts/r8a7740-armadillo800eva.dts b/arch/arm/boot/dts/r8a7740-armadillo800eva.dts index 6866f61..7885075 100644 --- a/arch/arm/boot/dts/r8a7740-armadillo800eva.dts +++ b/arch/arm/boot/dts/r8a7740-armadillo800eva.dts @@ -20,12 +20,12 @@ compatible = "renesas,armadillo800eva", "renesas,r8a7740"; aliases { - serial1 = &scifa1; + serial0 = &scifa1; }; chosen { - bootargs = "console=tty0 console=ttySC1,115200 earlyprintk=sh-sci.1,115200 ignore_loglevel root=/dev/nfs ip=dhcp rw"; - stdout-path = &scifa1; + bootargs = "earlyprintk ignore_loglevel root=/dev/nfs ip=dhcp rw"; + stdout-path = "serial0:115200n8"; }; memory@40000000 { -- cgit v0.10.2 From be6bebae60a354bcc207d1b99077c87f1a344710 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 14 Jun 2016 16:15:21 +0200 Subject: ARM: dts: genmai: Update console parameters Change the console alias to "serial0", for consistency with other boards (the first unlabeled serial port is always called "serial0"). This does change the serial console from /dev/ttySC2 to /dev/ttySC0. Add the serial port config to "chosen/stdout-path", which requires referring to the port by alias. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman diff --git a/arch/arm/boot/dts/r7s72100-genmai.dts b/arch/arm/boot/dts/r7s72100-genmai.dts index 05ba995..118a8e2 100644 --- a/arch/arm/boot/dts/r7s72100-genmai.dts +++ b/arch/arm/boot/dts/r7s72100-genmai.dts @@ -17,12 +17,12 @@ compatible = "renesas,genmai", "renesas,r7s72100"; aliases { - serial2 = &scif2; + serial0 = &scif2; }; chosen { bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp"; - stdout-path = &scif2; + stdout-path = "serial0:115200n8"; }; memory@8000000 { -- cgit v0.10.2 From 822337d7ff422afcceb523d50e08921dfabd77ae Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 14 Jun 2016 16:15:22 +0200 Subject: ARM: dts: marzen: Add serial port config to chosen/stdout-path Add the serial port config to "chosen/stdout-path", which requires referring to the port by alias. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman diff --git a/arch/arm/boot/dts/r8a7779-marzen.dts b/arch/arm/boot/dts/r8a7779-marzen.dts index 013e6f5..541678d 100644 --- a/arch/arm/boot/dts/r8a7779-marzen.dts +++ b/arch/arm/boot/dts/r8a7779-marzen.dts @@ -25,7 +25,7 @@ chosen { bootargs = "ignore_loglevel root=/dev/nfs ip=on"; - stdout-path = &scif2; + stdout-path = "serial0:115200n8"; }; memory@60000000 { -- cgit v0.10.2 From 20fc3188ac35f4afe52d24d02a0750c5e9307c98 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 14 Jun 2016 16:15:23 +0200 Subject: ARM: dts: kzm9d: Update console parameters Add a "serial1" alias for the serial console (it is labeled "uart1"). Add the serial port config to "chosen/stdout-path", which requires referring to the port by alias. Drop the "console=" parameter from the kernel command line, as it's no longer needed for DT-based platforms. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman diff --git a/arch/arm/boot/dts/emev2-kzm9d.dts b/arch/arm/boot/dts/emev2-kzm9d.dts index 9eb86f8..60d0a73 100644 --- a/arch/arm/boot/dts/emev2-kzm9d.dts +++ b/arch/arm/boot/dts/emev2-kzm9d.dts @@ -23,9 +23,13 @@ reg = <0x40000000 0x8000000>; }; + aliases { + serial1 = &uart1; + }; + chosen { - bootargs = "console=ttyS1,115200n81 ignore_loglevel root=/dev/nfs ip=dhcp"; - stdout-path = &uart1; + bootargs = "ignore_loglevel root=/dev/nfs ip=dhcp"; + stdout-path = "serial1:115200n8"; }; gpio_keys { -- cgit v0.10.2 From 54389e981cdfd081de67de083df451b70651f821 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 14 Jun 2016 16:15:24 +0200 Subject: ARM: dts: kzm9g: Update console parameters Change the console alias to "serial0", for consistency with other boards (the first unlabeled serial port is always called "serial0"). This does change the serial console from /dev/ttySC4 to /dev/ttySC0. Add the serial port config to "chosen/stdout-path", which requires referring to the port by alias. Drop the "console=" parameters from the kernel command line, as they're no longer needed for DT-based platforms. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman diff --git a/arch/arm/boot/dts/sh73a0-kzm9g.dts b/arch/arm/boot/dts/sh73a0-kzm9g.dts index 1df68b1..3d65f1f 100644 --- a/arch/arm/boot/dts/sh73a0-kzm9g.dts +++ b/arch/arm/boot/dts/sh73a0-kzm9g.dts @@ -22,7 +22,7 @@ compatible = "renesas,kzm9g", "renesas,sh73a0"; aliases { - serial4 = &scifa4; + serial0 = &scifa4; }; cpus { @@ -39,8 +39,8 @@ }; chosen { - bootargs = "console=tty0 console=ttySC4,115200 root=/dev/nfs ip=dhcp ignore_loglevel rw"; - stdout-path = &scifa4; + bootargs = "root=/dev/nfs ip=dhcp ignore_loglevel rw"; + stdout-path = "serial0:115200n8"; }; memory@40000000 { -- cgit v0.10.2 From e454b359b7a0a6f59e3d83394e6d4e598554cb33 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Tue, 28 Jun 2016 16:10:30 +0200 Subject: devicetree: bindings: Renesas APMU and SMP Enable method Add DT binding documentation for the APMU hardware and add "renesas,apmu" to the list of enable methods for the ARM cpus. Signed-off-by: Magnus Damm Signed-off-by: Geert Uytterhoeven Acked-by: Rob Herring Cc: devicetree@vger.kernel.org Signed-off-by: Simon Horman diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt index 3f0cbbb..fa7520e 100644 --- a/Documentation/devicetree/bindings/arm/cpus.txt +++ b/Documentation/devicetree/bindings/arm/cpus.txt @@ -204,6 +204,7 @@ nodes to be present and contain the properties described below. "qcom,gcc-msm8660" "qcom,kpss-acc-v1" "qcom,kpss-acc-v2" + "renesas,apmu" "rockchip,rk3036-smp" "rockchip,rk3066-smp" "ste,dbx500-smp" diff --git a/Documentation/devicetree/bindings/power/renesas,apmu.txt b/Documentation/devicetree/bindings/power/renesas,apmu.txt new file mode 100644 index 0000000..84404c9 --- /dev/null +++ b/Documentation/devicetree/bindings/power/renesas,apmu.txt @@ -0,0 +1,31 @@ +DT bindings for the Renesas Advanced Power Management Unit + +Renesas R-Car line of SoCs utilize one or more APMU hardware units +for CPU core power domain control including SMP boot and CPU Hotplug. + +Required properties: + +- compatible: Should be "renesas,-apmu", "renesas,apmu" as fallback. + Examples with soctypes are: + - "renesas,r8a7790-apmu" (R-Car H2) + - "renesas,r8a7791-apmu" (R-Car M2-W) + - "renesas,r8a7792-apmu" (R-Car V2H) + - "renesas,r8a7793-apmu" (R-Car M2-N) + - "renesas,r8a7794-apmu" (R-Car E2) + +- reg: Base address and length of the I/O registers used by the APMU. + +- cpus: This node contains a list of CPU cores, which should match the order + of CPU cores used by the WUPCR and PSTR registers in the Advanced Power + Management Unit section of the device's datasheet. + + +Example: + +This shows the r8a7791 APMU that can control CPU0 and CPU1. + + apmu@e6152000 { + compatible = "renesas,r8a7791-apmu", "renesas,apmu"; + reg = <0 0xe6152000 0 0x188>; + cpus = <&cpu0 &cpu1>; + }; -- cgit v0.10.2 From dc378795156d980ca701aab761457089dae84706 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Tue, 28 Jun 2016 16:10:40 +0200 Subject: ARM: dts: r8a7790: Add APMU nodes Add DT nodes for the Advanced Power Management Units (APMU), and use the enable-method to point out that the APMU should be used for SMP support. Signed-off-by: Magnus Damm Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index 9997e7d..d18558f 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -44,6 +44,7 @@ cpus { #address-cells = <1>; #size-cells = <0>; + enable-method = "renesas,apmu"; cpu0: cpu@0 { device_type = "cpu"; @@ -164,6 +165,18 @@ }; }; + apmu@e6151000 { + compatible = "renesas,r8a7790-apmu", "renesas,apmu"; + reg = <0 0xe6151000 0 0x188>; + cpus = <&cpu4 &cpu5 &cpu6 &cpu7>; + }; + + apmu@e6152000 { + compatible = "renesas,r8a7790-apmu", "renesas,apmu"; + reg = <0 0xe6152000 0 0x188>; + cpus = <&cpu0 &cpu1 &cpu2 &cpu3>; + }; + gic: interrupt-controller@f1001000 { compatible = "arm,gic-400"; #interrupt-cells = <3>; -- cgit v0.10.2 From 477cbcbd8f089ab72721a90760bc5d7987d3a713 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Tue, 28 Jun 2016 16:10:41 +0200 Subject: ARM: dts: r8a7791: Add APMU node Add a DT node for the Advanced Power Management Units (APMU), and use the enable-method to point out that the APMU should be used for SMP support. Signed-off-by: Magnus Damm Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi index 1985bd0..8f0086b 100644 --- a/arch/arm/boot/dts/r8a7791.dtsi +++ b/arch/arm/boot/dts/r8a7791.dtsi @@ -43,6 +43,7 @@ cpus { #address-cells = <1>; #size-cells = <0>; + enable-method = "renesas,apmu"; cpu0: cpu@0 { device_type = "cpu"; @@ -101,6 +102,12 @@ }; }; + apmu@e6152000 { + compatible = "renesas,r8a7791-apmu", "renesas,apmu"; + reg = <0 0xe6152000 0 0x188>; + cpus = <&cpu0 &cpu1>; + }; + gic: interrupt-controller@f1001000 { compatible = "arm,gic-400"; #interrupt-cells = <3>; -- cgit v0.10.2 From 65b133cd79cfde9f4e0157deb0e0f88f92811ad3 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Tue, 28 Jun 2016 16:10:42 +0200 Subject: ARM: dts: r8a7793: Add APMU node and second CPU core Add DT nodes for the Advanced Power Management Unit (APMU) and the second CPU core. Use the enable-method to point out that the APMU should be used for SMP support. Signed-off-by: Magnus Damm Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi index 9b55c1c..8d02aac 100644 --- a/arch/arm/boot/dts/r8a7793.dtsi +++ b/arch/arm/boot/dts/r8a7793.dtsi @@ -35,6 +35,7 @@ cpus { #address-cells = <1>; #size-cells = <0>; + enable-method = "renesas,apmu"; cpu0: cpu@0 { device_type = "cpu"; @@ -56,6 +57,14 @@ next-level-cache = <&L2_CA15>; }; + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <1>; + clock-frequency = <1500000000>; + power-domains = <&sysc R8A7793_PD_CA15_CPU1>; + }; + L2_CA15: cache-controller@0 { compatible = "cache"; reg = <0>; @@ -65,6 +74,12 @@ }; }; + apmu@e6152000 { + compatible = "renesas,r8a7793-apmu", "renesas,apmu"; + reg = <0 0xe6152000 0 0x188>; + cpus = <&cpu0 &cpu1>; + }; + thermal-zones { cpu_thermal: cpu-thermal { polling-delay-passive = <0>; -- cgit v0.10.2 From 8fd763c75c3ab8e72e5d7f0d4c53531e6ff76197 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Tue, 21 Jun 2016 01:31:01 +0300 Subject: ARM: dts: r8a7792: add SMP support Add the device tree nodes for the Advanced Power Management Unit (APMU) and the second Cortex-A15 CPU core. Use the "enable-method" prop to point out that the APMU should be used for the SMP support. Signed-off-by: Sergei Shtylyov Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi index ad895f8..75256ef 100644 --- a/arch/arm/boot/dts/r8a7792.dtsi +++ b/arch/arm/boot/dts/r8a7792.dtsi @@ -21,6 +21,7 @@ cpus { #address-cells = <1>; #size-cells = <0>; + enable-method = "renesas,apmu"; cpu0: cpu@0 { device_type = "cpu"; @@ -32,6 +33,15 @@ next-level-cache = <&L2_CA15>; }; + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <1>; + clock-frequency = <1000000000>; + power-domains = <&sysc R8A7792_PD_CA15_CPU1>; + next-level-cache = <&L2_CA15>; + }; + L2_CA15: cache-controller@0 { compatible = "cache"; reg = <0>; @@ -49,6 +59,12 @@ #size-cells = <2>; ranges; + apmu@e6152000 { + compatible = "renesas,r8a7792-apmu", "renesas,apmu"; + reg = <0 0xe6152000 0 0x188>; + cpus = <&cpu0 &cpu1>; + }; + gic: interrupt-controller@f1001000 { compatible = "arm,gic-400"; #interrupt-cells = <3>; -- cgit v0.10.2 From 6a6898f6e9486a908ee4481fdb55983945fdbd92 Mon Sep 17 00:00:00 2001 From: Jon Hunter Date: Wed, 29 Jun 2016 12:07:31 +0100 Subject: dt-bindings: phy: Fix description of Tegra210 PHY nodes The DT bindings document for the Tegra XUSB pad controller states that 'utmi' is one of the valid choices for the Tegra210 PHY node names and has child lanes named, 'utmi-0', 'utmi-1', 'utmi-2' and 'utmi-3'. However, neither the XUSB pad controller PHY driver or the actual Tegra210 bindings for the XUSB pad controller use these names. Instead both the driver and binding use the node name 'usb2' and for the child lanes use the names 'usb2-0', 'usb2-1', 'usb2-2' and 'usb2-3'. Given that the driver and binding are consistent with the naming, update the DT bindings documentation to match. Signed-off-by: Jon Hunter Acked-by: Rob Herring Signed-off-by: Thierry Reding diff --git a/Documentation/devicetree/bindings/phy/nvidia,tegra124-xusb-padctl.txt b/Documentation/devicetree/bindings/phy/nvidia,tegra124-xusb-padctl.txt index 0bf1ae2..3742c15 100644 --- a/Documentation/devicetree/bindings/phy/nvidia,tegra124-xusb-padctl.txt +++ b/Documentation/devicetree/bindings/phy/nvidia,tegra124-xusb-padctl.txt @@ -124,7 +124,7 @@ For Tegra124 and Tegra132, the list of valid PHY nodes is given below: - functions: "usb3-ss", "sata" For Tegra210, the list of valid PHY nodes is given below: -- utmi: utmi-0, utmi-1, utmi-2, utmi-3 +- usb2: usb2-0, usb2-1, usb2-2, usb2-3 - functions: "snps", "xusb", "uart" - hsic: hsic-0, hsic-1 - functions: "snps", "xusb" -- cgit v0.10.2 From b8c5c990a0fc6b00b7f7256864342e3afc24a392 Mon Sep 17 00:00:00 2001 From: Jon Hunter Date: Wed, 29 Jun 2016 12:07:32 +0100 Subject: dt-bindings: usb: Fix Tegra XUSB example The DT bindings example for the Tegra XUSB controller omits the 'lanes' subnode in the XUSB pad controller which is required according to the DT bindings documentation for the Tegra XUSB pad controller[0]. In addition to this the phy-names with the suffix 'utmi' are also not valid and should have the suffix 'usb2'. Correct both the XUSB pad controller pad path and phy-names for the XUSB example. [0]: Documentation/devicetree/bindings/phy/nvidia,tegra124-xusb-padctl.txt Signed-off-by: Jon Hunter Signed-off-by: Thierry Reding diff --git a/Documentation/devicetree/bindings/usb/nvidia,tegra124-xusb.txt b/Documentation/devicetree/bindings/usb/nvidia,tegra124-xusb.txt index d28295a..3eee9e5 100644 --- a/Documentation/devicetree/bindings/usb/nvidia,tegra124-xusb.txt +++ b/Documentation/devicetree/bindings/usb/nvidia,tegra124-xusb.txt @@ -104,10 +104,10 @@ Example: nvidia,xusb-padctl = <&padctl>; - phys = <&{/padctl@0,7009f000/pads/usb2/usb2-1}>, /* mini-PCIe USB */ - <&{/padctl@0,7009f000/pads/usb2/usb2-2}>, /* USB A */ - <&{/padctl@0,7009f000/pads/pcie/pcie-0}>; /* USB A */ - phy-names = "utmi-1", "utmi-2", "usb3-0"; + phys = <&{/padctl@0,7009f000/pads/usb2/lanes/usb2-1}>, /* mini-PCIe USB */ + <&{/padctl@0,7009f000/pads/usb2/lanes/usb2-2}>, /* USB A */ + <&{/padctl@0,7009f000/pads/pcie/lanes/pcie-0}>; /* USB A */ + phy-names = "usb2-1", "usb2-2", "usb3-0"; avddio-pex-supply = <&vdd_1v05_run>; dvddio-pex-supply = <&vdd_1v05_run>; -- cgit v0.10.2 From 71c7a4dccf30c36896d2804a84109466292f1610 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Thu, 30 Jun 2016 00:23:18 +0200 Subject: dt-bindings: tegra: Add Colibri T30 device tree binding documentation Add the device tree binding documentation for Colibri T30 which was missing so far. Signed-off-by: Marcel Ziswiler Acked-by: Rob Herring Signed-off-by: Thierry Reding diff --git a/Documentation/devicetree/bindings/arm/tegra.txt b/Documentation/devicetree/bindings/arm/tegra.txt index 73278c6..428e098 100644 --- a/Documentation/devicetree/bindings/arm/tegra.txt +++ b/Documentation/devicetree/bindings/arm/tegra.txt @@ -33,6 +33,8 @@ board-specific compatible values: toradex,apalis_t30 toradex,apalis_t30-eval toradex,colibri_t20-512 + toradex,colibri_t30 + toradex,colibri_t30-eval-v3 toradex,iris Trusted Foundations -- cgit v0.10.2 From 7eb28ee074bcbf0d6507e896be11280a558dbf17 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Thu, 30 Jun 2016 00:23:19 +0200 Subject: dt-bindings: tegra: Add Apalis TK1 device tree binding documentation Add the device tree binding documentation for Apalis TK1. Note that this is using dashes aka '-' in compatible strings as previously suggested by Rob. Signed-off-by: Marcel Ziswiler Acked-by: Rob Herring Signed-off-by: Thierry Reding diff --git a/Documentation/devicetree/bindings/arm/tegra.txt b/Documentation/devicetree/bindings/arm/tegra.txt index 428e098..b5a4342 100644 --- a/Documentation/devicetree/bindings/arm/tegra.txt +++ b/Documentation/devicetree/bindings/arm/tegra.txt @@ -32,6 +32,8 @@ board-specific compatible values: nvidia,whistler toradex,apalis_t30 toradex,apalis_t30-eval + toradex,apalis-tk1 + toradex,apalis-tk1-eval toradex,colibri_t20-512 toradex,colibri_t30 toradex,colibri_t30-eval-v3 -- cgit v0.10.2 From 1dd6e8631e88e5baebbf29d1fea8f2259c67e2fa Mon Sep 17 00:00:00 2001 From: Nicolas Ferre Date: Thu, 19 May 2016 14:54:22 +0200 Subject: ARM: dts: at91: add at91sam9260ek board DT Add Device Tree source file for at91sam9260ek board. This official Atmel Evaluation Kit is designed around a SoC based on a ARM 926 core the at91sam9260. The board is also added to the dts Makefile. Signed-off-by: Nicolas Ferre Signed-off-by: Alexandre Belloni diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 0ee9e61..fbd7de6 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -17,6 +17,7 @@ dtb-$(CONFIG_SOC_SAM_V4_V5) += \ evk-pro3.dtb \ tny_a9260.dtb \ usb_a9260.dtb \ + at91sam9260ek.dtb \ at91sam9261ek.dtb \ at91sam9263ek.dtb \ at91-sam9_l9260.dtb \ diff --git a/arch/arm/boot/dts/at91sam9260ek.dts b/arch/arm/boot/dts/at91sam9260ek.dts new file mode 100644 index 0000000..0a29bd0 --- /dev/null +++ b/arch/arm/boot/dts/at91sam9260ek.dts @@ -0,0 +1,211 @@ +/* + * Device Tree file for Atmel at91sam9260 Evaluation Kit + * + * Copyright (C) 2016 Atmel, + * 2016 Nicolas Ferre + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +/dts-v1/; +#include "at91sam9260.dtsi" + +/ { + model = "Atmel at91sam9260ek"; + compatible = "atmel,at91sam9260ek", "atmel,at91sam9260", "atmel,at91sam9"; + + chosen { + stdout-path = &dbgu; + }; + + memory { + reg = <0x20000000 0x4000000>; + }; + + clocks { + slow_xtal { + clock-frequency = <32768>; + }; + + main_xtal { + clock-frequency = <18432000>; + }; + }; + + ahb { + apb { + usb1: gadget@fffa4000 { + atmel,vbus-gpio = <&pioC 5 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + mmc0: mmc@fffa8000 { + pinctrl-0 = < + &pinctrl_board_mmc0_slot1 + &pinctrl_mmc0_clk + &pinctrl_mmc0_slot1_cmd_dat0 + &pinctrl_mmc0_slot1_dat1_3>; + status = "okay"; + slot@1 { + reg = <1>; + bus-width = <4>; + cd-gpios = <&pioC 9 GPIO_ACTIVE_HIGH>; + }; + }; + + usart0: serial@fffb0000 { + pinctrl-0 = + <&pinctrl_usart0 + &pinctrl_usart0_rts + &pinctrl_usart0_cts + &pinctrl_usart0_dtr_dsr + &pinctrl_usart0_dcd + &pinctrl_usart0_ri>; + status = "okay"; + }; + + usart1: serial@fffb4000 { + status = "okay"; + }; + + ssc0: ssc@fffbc000 { + status = "okay"; + pinctrl-0 = <&pinctrl_ssc0_tx>; + }; + + macb0: ethernet@fffc4000 { + phy-mode = "rmii"; + status = "okay"; + }; + + spi0: spi@fffc8000 { + cs-gpios = <0>, <&pioC 11 0>, <0>, <0>; + mtd_dataflash@0 { + compatible = "atmel,at45", "atmel,dataflash"; + spi-max-frequency = <50000000>; + reg = <1>; + }; + }; + + dbgu: serial@fffff200 { + status = "okay"; + }; + + pinctrl@fffff400 { + board { + pinctrl_board_mmc0_slot1: mmc0_slot1-board { + atmel,pins = + ; + }; + }; + }; + + shdwc@fffffd10 { + atmel,wakeup-counter = <10>; + atmel,wakeup-rtt-timer; + }; + + rtc@fffffd20 { + atmel,rtt-rtc-time-reg = <&gpbr 0x0>; + status = "okay"; + }; + + watchdog@fffffd40 { + status = "okay"; + }; + + gpbr: syscon@fffffd50 { + status = "okay"; + }; + }; + + usb0: ohci@500000 { + num-ports = <2>; + status = "okay"; + }; + + nand0: nand@40000000 { + nand-bus-width = <8>; + nand-ecc-mode = "soft"; + nand-on-flash-bbt; + status = "okay"; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + + btn3 { + label = "Button 3"; + gpios = <&pioA 30 GPIO_ACTIVE_LOW>; + linux,code = <0x103>; + gpio-key,wakeup; + }; + + btn4 { + label = "Button 4"; + gpios = <&pioA 31 GPIO_ACTIVE_LOW>; + linux,code = <0x104>; + gpio-key,wakeup; + }; + }; + + i2c@0 { + status = "okay"; + + 24c512@50 { + compatible = "24c512"; + reg = <0x50>; + }; + }; + + leds { + compatible = "gpio-leds"; + + ds1 { + label = "ds1"; + gpios = <&pioA 9 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + + ds5 { + label = "ds5"; + gpios = <&pioA 6 GPIO_ACTIVE_LOW>; + }; + }; +}; -- cgit v0.10.2 From ba5c30ac217b2f7b67eddddd60cc68fd060383a2 Mon Sep 17 00:00:00 2001 From: Raashid Muhammed Date: Fri, 24 Jun 2016 19:01:08 +0530 Subject: ARM: dts: at91: sam9_l9260: Add pinctrl information to ethernet node. Add missing pinctrl information to ethernet node. Signed-off-by: Raashid Muhammed Reviewed-by: Vijay Kumar B. Signed-off-by: Alexandre Belloni diff --git a/arch/arm/boot/dts/at91-sam9_l9260.dts b/arch/arm/boot/dts/at91-sam9_l9260.dts index 349a461..be409f2 100644 --- a/arch/arm/boot/dts/at91-sam9_l9260.dts +++ b/arch/arm/boot/dts/at91-sam9_l9260.dts @@ -49,6 +49,7 @@ }; macb0: ethernet@fffc4000 { + pinctrl-0 = <&pinctrl_macb_rmii &pinctrl_macb_rmii_mii_alt>; phy-mode = "mii"; #address-cells = <1>; #size-cells = <0>; -- cgit v0.10.2 From ee7657b0307cb14fdac35d68f8e8edbd9c96d928 Mon Sep 17 00:00:00 2001 From: Raashid Muhammed Date: Fri, 24 Jun 2016 19:01:09 +0530 Subject: ARM: dts: at91: sam9_l9260: Modify information in LED nodes. Add power led node and rename status led node. Signed-off-by: Raashid Muhammed Reviewed-by: Vijay Kumar B. Signed-off-by: Alexandre Belloni diff --git a/arch/arm/boot/dts/at91-sam9_l9260.dts b/arch/arm/boot/dts/at91-sam9_l9260.dts index be409f2..814753a 100644 --- a/arch/arm/boot/dts/at91-sam9_l9260.dts +++ b/arch/arm/boot/dts/at91-sam9_l9260.dts @@ -106,11 +106,16 @@ leds { compatible = "gpio-leds"; - b0 { - label = "b0"; - gpios = <&pioA 6 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; + pwr_led { + label = "sam9-l9260:yellow:pwr"; + gpios = <&pioA 9 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "cpu0"; }; + status_led { + label = "sam9-l9260:green:status"; + gpios = <&pioA 6 GPIO_ACTIVE_LOW>; + linux,default-trigger = "timer"; + }; }; }; -- cgit v0.10.2 From fcac40c94d48f6137b54b91f390bed18fb16274c Mon Sep 17 00:00:00 2001 From: Olivier Schonken Date: Fri, 1 Jul 2016 16:33:39 +0200 Subject: ARM: dts: at91: sama5d2: add PMU node Add node to support SAMA5D2 Performance Monitor Unit. Signed-off-by: Olivier Schonken Signed-off-by: Alexandre Belloni diff --git a/arch/arm/boot/dts/sama5d2.dtsi b/arch/arm/boot/dts/sama5d2.dtsi index 2827e7a..5d63206 100644 --- a/arch/arm/boot/dts/sama5d2.dtsi +++ b/arch/arm/boot/dts/sama5d2.dtsi @@ -72,6 +72,11 @@ }; }; + pmu { + compatible = "arm,cortex-a5-pmu"; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH 0>; + }; + memory { reg = <0x20000000 0x20000000>; }; -- cgit v0.10.2 From b8bca7eaef9eeda4876b8ded1f49862b0b85181c Mon Sep 17 00:00:00 2001 From: Wenyou Yang Date: Fri, 24 Jun 2016 15:32:05 +0800 Subject: ARM: dts: at91: sama5d2_xplained: Update the pmic node Due to introducing the new driver - ACT8945A MFD drive, change the pmic device node to align with the ACT8945A regulator and charger drivers. Signed-off-by: Wenyou Yang Signed-off-by: Alexandre Belloni diff --git a/arch/arm/boot/dts/at91-sama5d2_xplained.dts b/arch/arm/boot/dts/at91-sama5d2_xplained.dts index eb4f1ac..0b9a59d 100644 --- a/arch/arm/boot/dts/at91-sama5d2_xplained.dts +++ b/arch/arm/boot/dts/at91-sama5d2_xplained.dts @@ -158,56 +158,64 @@ i2c-sda-hold-time-ns = <350>; status = "okay"; - pmic: act8865@5b { - compatible = "active-semi,act8865"; + pmic@5b { + compatible = "active-semi,act8945a"; reg = <0x5b>; active-semi,vsel-high; + active-semi,chglev-gpios = <&pioA 12 GPIO_ACTIVE_HIGH>; + active-semi,lbo-gpios = <&pioA 72 GPIO_ACTIVE_LOW>; + active-semi,irq_gpios = <&pioA 45 GPIO_ACTIVE_LOW>; + active-semi,input-voltage-threshold-microvolt = <6600>; + active-semi,precondition-timeout = <40>; + active-semi,total-timeout = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_charger_chglev &pinctrl_charger_lbo &pinctrl_charger_irq>; status = "okay"; regulators { - vdd_1v35_reg: DCDC_REG1 { + vdd_1v35_reg: REG_DCDC1 { regulator-name = "VDD_1V35"; regulator-min-microvolt = <1350000>; regulator-max-microvolt = <1350000>; regulator-always-on; }; - vdd_1v2_reg: DCDC_REG2 { + vdd_1v2_reg: REG_DCDC2 { regulator-name = "VDD_1V2"; regulator-min-microvolt = <1100000>; regulator-max-microvolt = <1300000>; regulator-always-on; }; - vdd_3v3_reg: DCDC_REG3 { + vdd_3v3_reg: REG_DCDC3 { regulator-name = "VDD_3V3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; }; - vdd_fuse_reg: LDO_REG1 { + vdd_fuse_reg: REG_LDO1 { regulator-name = "VDD_FUSE"; regulator-min-microvolt = <2500000>; regulator-max-microvolt = <2500000>; regulator-always-on; }; - vdd_3v3_lp_reg: LDO_REG2 { + vdd_3v3_lp_reg: REG_LDO2 { regulator-name = "VDD_3V3_LP"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; }; - vdd_led_reg: LDO_REG3 { + vdd_led_reg: REG_LDO3 { regulator-name = "VDD_LED"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; }; - vdd_sdhc_1v8_reg: LDO_REG4 { + vdd_sdhc_1v8_reg: REG_LDO4 { regulator-name = "VDD_SDHC_1V8"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; @@ -309,6 +317,21 @@ bias-disable; }; + pinctrl_charger_chglev: charger_chglev { + pinmux = ; + bias-disable; + }; + + pinctrl_charger_irq: charger_irq { + pinmux = ; + bias-disable; + }; + + pinctrl_charger_lbo: charger_lbo { + pinmux = ; + bias-pull-up; + }; + pinctrl_flx0_default: flx0_default { pinmux = , ; -- cgit v0.10.2 From f5e1648ceae4983ff1fb64449f81dab23c183668 Mon Sep 17 00:00:00 2001 From: Priit Laes Date: Tue, 10 May 2016 22:24:06 +0300 Subject: ARM: sun4i: A10: Add display and TCON clocks Enable the display and TCON clocks that are needed to drive the display engine, tcon and TV encoders. Signed-off-by: Priit Laes Signed-off-by: Maxime Ripard diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi index ca58eb2..a9c3190 100644 --- a/arch/arm/boot/dts/sun4i-a10.dtsi +++ b/arch/arm/boot/dts/sun4i-a10.dtsi @@ -65,9 +65,8 @@ compatible = "allwinner,simple-framebuffer", "simple-framebuffer"; allwinner,pipeline = "de_be0-lcd0-hdmi"; - clocks = <&pll3>, <&pll5 1>, <&ahb_gates 36>, - <&ahb_gates 43>, <&ahb_gates 44>, - <&dram_gates 26>; + clocks = <&ahb_gates 36>, <&ahb_gates 43>, <&ahb_gates 44>, + <&de_be0_clk>, <&tcon0_ch0_clk>, <&dram_gates 26>; status = "disabled"; }; @@ -75,9 +74,9 @@ compatible = "allwinner,simple-framebuffer", "simple-framebuffer"; allwinner,pipeline = "de_fe0-de_be0-lcd0-hdmi"; - clocks = <&pll3>, <&pll5 1>, <&ahb_gates 36>, - <&ahb_gates 43>, <&ahb_gates 44>, - <&ahb_gates 46>, + clocks = <&ahb_gates 36>, <&ahb_gates 43>, + <&ahb_gates 44>, <&ahb_gates 46>, + <&de_be0_clk>, <&de_fe0_clk>, <&tcon0_ch0_clk>, <&dram_gates 25>, <&dram_gates 26>; status = "disabled"; }; @@ -86,8 +85,8 @@ compatible = "allwinner,simple-framebuffer", "simple-framebuffer"; allwinner,pipeline = "de_fe0-de_be0-lcd0"; - clocks = <&pll3>, <&pll5 1>, <&ahb_gates 36>, - <&ahb_gates 44>, <&ahb_gates 46>, + clocks = <&ahb_gates 36>, <&ahb_gates 44>, <&ahb_gates 46>, + <&de_be0_clk>, <&de_fe0_clk>, <&tcon0_ch0_clk>, <&dram_gates 25>, <&dram_gates 26>; status = "disabled"; }; @@ -96,9 +95,9 @@ compatible = "allwinner,simple-framebuffer", "simple-framebuffer"; allwinner,pipeline = "de_fe0-de_be0-lcd0-tve0"; - clocks = <&pll3>, <&pll5 1>, <&ahb_gates 34>, - <&ahb_gates 36>, <&ahb_gates 44>, - <&ahb_gates 46>, + clocks = <&ahb_gates 34>, <&ahb_gates 36>, + <&ahb_gates 44>, <&ahb_gates 46>, + <&de_be0_clk>, <&de_fe0_clk>, <&tcon0_ch0_clk>, <&dram_gates 5>, <&dram_gates 25>, <&dram_gates 26>; status = "disabled"; }; @@ -577,6 +576,81 @@ "dram_de_mp", "dram_ace"; }; + de_be0_clk: clk@01c20104 { + #clock-cells = <0>; + #reset-cells = <0>; + compatible = "allwinner,sun4i-a10-display-clk"; + reg = <0x01c20104 0x4>; + clocks = <&pll3>, <&pll7>, <&pll5 1>; + clock-output-names = "de-be0"; + }; + + de_be1_clk: clk@01c20108 { + #clock-cells = <0>; + #reset-cells = <0>; + compatible = "allwinner,sun4i-a10-display-clk"; + reg = <0x01c20108 0x4>; + clocks = <&pll3>, <&pll7>, <&pll5 1>; + clock-output-names = "de-be1"; + }; + + de_fe0_clk: clk@01c2010c { + #clock-cells = <0>; + #reset-cells = <0>; + compatible = "allwinner,sun4i-a10-display-clk"; + reg = <0x01c2010c 0x4>; + clocks = <&pll3>, <&pll7>, <&pll5 1>; + clock-output-names = "de-fe0"; + }; + + de_fe1_clk: clk@01c20110 { + #clock-cells = <0>; + #reset-cells = <0>; + compatible = "allwinner,sun4i-a10-display-clk"; + reg = <0x01c20110 0x4>; + clocks = <&pll3>, <&pll7>, <&pll5 1>; + clock-output-names = "de-fe1"; + }; + + + tcon0_ch0_clk: clk@01c20118 { + #clock-cells = <0>; + #reset-cells = <1>; + compatible = "allwinner,sun4i-a10-tcon-ch0-clk"; + reg = <0x01c20118 0x4>; + clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>; + clock-output-names = "tcon0-ch0-sclk"; + + }; + + tcon1_ch0_clk: clk@01c2011c { + #clock-cells = <0>; + #reset-cells = <1>; + compatible = "allwinner,sun4i-a10-tcon-ch1-clk"; + reg = <0x01c2011c 0x4>; + clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>; + clock-output-names = "tcon1-ch0-sclk"; + + }; + + tcon0_ch1_clk: clk@01c2012c { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-tcon-ch0-clk"; + reg = <0x01c2012c 0x4>; + clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>; + clock-output-names = "tcon0-ch1-sclk"; + + }; + + tcon1_ch1_clk: clk@01c20130 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-tcon-ch1-clk"; + reg = <0x01c20130 0x4>; + clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>; + clock-output-names = "tcon1-ch1-sclk"; + + }; + ve_clk: clk@01c2013c { #clock-cells = <0>; #reset-cells = <0>; -- cgit v0.10.2 From f1afc13792e31f36cfb7d2d0523ef6a02e29732b Mon Sep 17 00:00:00 2001 From: Priit Laes Date: Tue, 10 May 2016 22:24:07 +0300 Subject: ARM: sun7i: A20: Add display and TCON clocks Enable the display and TCON clocks that are needed to drive the display engine, tcon and TV encoders. Signed-off-by: Priit Laes Signed-off-by: Maxime Ripard diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index 2c34bbb..734f07b 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -67,9 +67,8 @@ compatible = "allwinner,simple-framebuffer", "simple-framebuffer"; allwinner,pipeline = "de_be0-lcd0-hdmi"; - clocks = <&pll3>, <&pll5 1>, <&ahb_gates 36>, - <&ahb_gates 43>, <&ahb_gates 44>, - <&dram_gates 26>; + clocks = <&ahb_gates 36>, <&ahb_gates 43>, <&ahb_gates 44>, + <&de_be0_clk>, <&tcon0_ch0_clk>, <&dram_gates 26>; status = "disabled"; }; @@ -77,8 +76,9 @@ compatible = "allwinner,simple-framebuffer", "simple-framebuffer"; allwinner,pipeline = "de_be0-lcd0"; - clocks = <&pll3>, <&pll5 1>, <&ahb_gates 36>, - <&ahb_gates 44>, <&dram_gates 26>; + clocks = <&ahb_gates 36>, <&ahb_gates 44>, + <&de_be0_clk>, <&tcon0_ch0_clk>, + <&dram_gates 26>; status = "disabled"; }; @@ -86,8 +86,8 @@ compatible = "allwinner,simple-framebuffer", "simple-framebuffer"; allwinner,pipeline = "de_be0-lcd0-tve0"; - clocks = <&pll3>, <&pll5 1>, - <&ahb_gates 34>, <&ahb_gates 36>, <&ahb_gates 44>, + clocks = <&ahb_gates 34>, <&ahb_gates 36>, <&ahb_gates 44>, + <&de_be0_clk>, <&tcon0_ch0_clk>, <&dram_gates 5>, <&dram_gates 26>; status = "disabled"; }; @@ -583,6 +583,80 @@ "dram_de_mp", "dram_ace"; }; + de_be0_clk: clk@01c20104 { + #clock-cells = <0>; + #reset-cells = <0>; + compatible = "allwinner,sun4i-a10-display-clk"; + reg = <0x01c20104 0x4>; + clocks = <&pll3>, <&pll7>, <&pll5 1>; + clock-output-names = "de-be0"; + }; + + de_be1_clk: clk@01c20108 { + #clock-cells = <0>; + #reset-cells = <0>; + compatible = "allwinner,sun4i-a10-display-clk"; + reg = <0x01c20108 0x4>; + clocks = <&pll3>, <&pll7>, <&pll5 1>; + clock-output-names = "de-be1"; + }; + + de_fe0_clk: clk@01c2010c { + #clock-cells = <0>; + #reset-cells = <0>; + compatible = "allwinner,sun4i-a10-display-clk"; + reg = <0x01c2010c 0x4>; + clocks = <&pll3>, <&pll7>, <&pll5 1>; + clock-output-names = "de-fe0"; + }; + + de_fe1_clk: clk@01c20110 { + #clock-cells = <0>; + #reset-cells = <0>; + compatible = "allwinner,sun4i-a10-display-clk"; + reg = <0x01c20110 0x4>; + clocks = <&pll3>, <&pll7>, <&pll5 1>; + clock-output-names = "de-fe1"; + }; + + tcon0_ch0_clk: clk@01c20118 { + #clock-cells = <0>; + #reset-cells = <1>; + compatible = "allwinner,sun4i-a10-tcon-ch0-clk"; + reg = <0x01c20118 0x4>; + clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>; + clock-output-names = "tcon0-ch0-sclk"; + + }; + + tcon1_ch0_clk: clk@01c2011c { + #clock-cells = <0>; + #reset-cells = <1>; + compatible = "allwinner,sun4i-a10-tcon-ch1-clk"; + reg = <0x01c2011c 0x4>; + clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>; + clock-output-names = "tcon1-ch0-sclk"; + + }; + + tcon0_ch1_clk: clk@01c2012c { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-tcon-ch0-clk"; + reg = <0x01c2012c 0x4>; + clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>; + clock-output-names = "tcon0-ch1-sclk"; + + }; + + tcon1_ch1_clk: clk@01c20130 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-tcon-ch1-clk"; + reg = <0x01c20130 0x4>; + clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>; + clock-output-names = "tcon1-ch1-sclk"; + + }; + ve_clk: clk@01c2013c { #clock-cells = <0>; #reset-cells = <0>; -- cgit v0.10.2 From 0090dc5f6cccc9bb9fd59469c91762529b7ac465 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Thu, 25 Feb 2016 17:15:30 -0800 Subject: ARM: sun5i: a13: Add LCD pins The RGB bus can be used in several configurations, one of which being the RGB666. Add a pinctrl group for that case. Acked-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi index 263d46d..79b5d51 100644 --- a/arch/arm/boot/dts/sun5i-a13.dtsi +++ b/arch/arm/boot/dts/sun5i-a13.dtsi @@ -237,6 +237,16 @@ &pio { compatible = "allwinner,sun5i-a13-pinctrl"; + lcd_rgb666_pins: lcd_rgb666@0 { + allwinner,pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7", + "PD10", "PD11", "PD12", "PD13", "PD14", "PD15", + "PD18", "PD19", "PD20", "PD21", "PD22", "PD23", + "PD24", "PD25", "PD26", "PD27"; + allwinner,function = "lcd0"; + allwinner,drive = ; + allwinner,pull = ; + }; + uart1_pins_a: uart1@0 { allwinner,pins = "PE10", "PE11"; allwinner,function = "uart1"; -- cgit v0.10.2 From 2cbc7295cd94d4a7bada416084c4a0ba047e0265 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Thu, 12 May 2016 10:22:06 +0200 Subject: ARM: sun5i: Move display blocks to A13 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Most of the display engine is shared between the R8 and the A13. Move the common parts to the Á13 DTSI. Signed-off-by: Maxime Ripard diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi index 79b5d51..e012890 100644 --- a/arch/arm/boot/dts/sun5i-a13.dtsi +++ b/arch/arm/boot/dts/sun5i-a13.dtsi @@ -207,7 +207,50 @@ }; }; + display-engine { + compatible = "allwinner,sun5i-a13-display-engine"; + allwinner,pipelines = <&fe0>; + }; + soc@01c00000 { + tcon0: lcd-controller@01c0c000 { + compatible = "allwinner,sun5i-a13-tcon"; + reg = <0x01c0c000 0x1000>; + interrupts = <44>; + resets = <&tcon_ch0_clk 1>; + reset-names = "lcd"; + clocks = <&ahb_gates 36>, + <&tcon_ch0_clk>, + <&tcon_ch1_clk>; + clock-names = "ahb", + "tcon-ch0", + "tcon-ch1"; + clock-output-names = "tcon-pixel-clock"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + tcon0_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + tcon0_in_be0: endpoint@0 { + reg = <0>; + remote-endpoint = <&be0_out_tcon0>; + }; + }; + + tcon0_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + }; + }; + pwm: pwm@01c20e00 { compatible = "allwinner,sun5i-a13-pwm"; reg = <0x01c20e00 0xc>; @@ -215,6 +258,75 @@ #pwm-cells = <3>; status = "disabled"; }; + + fe0: display-frontend@01e00000 { + compatible = "allwinner,sun5i-a13-display-frontend"; + reg = <0x01e00000 0x20000>; + interrupts = <47>; + clocks = <&ahb_gates 46>, <&de_fe_clk>, + <&dram_gates 25>; + clock-names = "ahb", "mod", + "ram"; + resets = <&de_fe_clk>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + fe0_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + fe0_out_be0: endpoint@0 { + reg = <0>; + remote-endpoint = <&be0_in_fe0>; + }; + }; + }; + }; + + be0: display-backend@01e60000 { + compatible = "allwinner,sun5i-a13-display-backend"; + reg = <0x01e60000 0x10000>; + clocks = <&ahb_gates 44>, <&de_be_clk>, + <&dram_gates 26>; + clock-names = "ahb", "mod", + "ram"; + resets = <&de_be_clk>; + status = "disabled"; + + assigned-clocks = <&de_be_clk>; + assigned-clock-rates = <300000000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + be0_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + be0_in_fe0: endpoint@0 { + reg = <0>; + remote-endpoint = <&fe0_out_be0>; + }; + }; + + be0_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + be0_out_tcon0: endpoint@0 { + reg = <0>; + remote-endpoint = <&tcon0_in_be0>; + }; + }; + }; + }; }; }; diff --git a/arch/arm/boot/dts/sun5i-r8.dtsi b/arch/arm/boot/dts/sun5i-r8.dtsi index c04cf69..8b058f5 100644 --- a/arch/arm/boot/dts/sun5i-r8.dtsi +++ b/arch/arm/boot/dts/sun5i-r8.dtsi @@ -76,122 +76,12 @@ }; }; }; - - tcon0: lcd-controller@01c0c000 { - compatible = "allwinner,sun5i-a13-tcon"; - reg = <0x01c0c000 0x1000>; - interrupts = <44>; - resets = <&tcon_ch0_clk 1>; - reset-names = "lcd"; - clocks = <&ahb_gates 36>, - <&tcon_ch0_clk>, - <&tcon_ch1_clk>; - clock-names = "ahb", - "tcon-ch0", - "tcon-ch1"; - clock-output-names = "tcon-pixel-clock"; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - tcon0_in: port@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - tcon0_in_be0: endpoint@0 { - reg = <0>; - remote-endpoint = <&be0_out_tcon0>; - }; - }; - - tcon0_out: port@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - tcon0_out_tve0: endpoint@1 { - reg = <1>; - remote-endpoint = <&tve0_in_tcon0>; - }; - }; - }; - }; - - fe0: display-frontend@01e00000 { - compatible = "allwinner,sun5i-a13-display-frontend"; - reg = <0x01e00000 0x20000>; - interrupts = <47>; - clocks = <&ahb_gates 46>, <&de_fe_clk>, - <&dram_gates 25>; - clock-names = "ahb", "mod", - "ram"; - resets = <&de_fe_clk>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - fe0_out: port@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - fe0_out_be0: endpoint@0 { - reg = <0>; - remote-endpoint = <&be0_in_fe0>; - }; - }; - }; - }; - - be0: display-backend@01e60000 { - compatible = "allwinner,sun5i-a13-display-backend"; - reg = <0x01e60000 0x10000>; - clocks = <&ahb_gates 44>, <&de_be_clk>, - <&dram_gates 26>; - clock-names = "ahb", "mod", - "ram"; - resets = <&de_be_clk>; - status = "disabled"; - - assigned-clocks = <&de_be_clk>; - assigned-clock-rates = <300000000>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - be0_in: port@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - be0_in_fe0: endpoint@0 { - reg = <0>; - remote-endpoint = <&fe0_out_be0>; - }; - }; - - be0_out: port@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - be0_out_tcon0: endpoint@0 { - reg = <0>; - remote-endpoint = <&tcon0_in_be0>; - }; - }; - }; - }; }; +}; - display-engine { - compatible = "allwinner,sun5i-a13-display-engine"; - allwinner,pipelines = <&fe0>; +&tcon0_out { + tcon0_out_tve0: endpoint@1 { + reg = <1>; + remote-endpoint = <&tve0_in_tcon0>; }; }; -- cgit v0.10.2 From 90041d075863692b993b14b9701480cdf3e549b7 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Tue, 17 May 2016 23:56:07 +0800 Subject: ARM: dts: axp209: Disable ldo5 by default The output pin of LDO is also a GPIO pin, and the on/off settings of the regulator are actually pinmux settings. Disable it by default so it doesn't conflict with GPIO usage. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard diff --git a/arch/arm/boot/dts/axp209.dtsi b/arch/arm/boot/dts/axp209.dtsi index 051ab3b..afbe89c 100644 --- a/arch/arm/boot/dts/axp209.dtsi +++ b/arch/arm/boot/dts/axp209.dtsi @@ -87,6 +87,7 @@ reg_ldo5: ldo5 { regulator-name = "ldo5"; + status = "disabled"; }; }; -- cgit v0.10.2 From 815c1593851e098bdbaabc840cfe5b3dbe6d9553 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Tue, 17 May 2016 23:56:09 +0800 Subject: ARM: dts: sun5i: q8-common: Enable USB power supply On the A13 Q8 tablets, the PMIC's USB power supply (VBUS) is connected to the external OTG port. This can be used to provide power and OTG VBUS sensing. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard diff --git a/arch/arm/boot/dts/sun5i-q8-common.dtsi b/arch/arm/boot/dts/sun5i-q8-common.dtsi index a78e189..0f7ec63 100644 --- a/arch/arm/boot/dts/sun5i-q8-common.dtsi +++ b/arch/arm/boot/dts/sun5i-q8-common.dtsi @@ -170,11 +170,16 @@ status = "okay"; }; +&usb_power_supply { + status = "okay"; +}; + &usbphy { pinctrl-names = "default"; pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>; usb0_id_det-gpio = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */ usb0_vbus_det-gpio = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */ + usb0_vbus_power-supply = <&usb_power_supply>; usb0_vbus-supply = <®_usb0_vbus>; status = "okay"; }; -- cgit v0.10.2 From dddc8e0b4c6b865c259fd012818f2212af8721dc Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Tue, 17 May 2016 23:56:10 +0800 Subject: ARM: dts: sun5i: q8-common: Enable audio codec The Q8 tablets use the audio codec to provide audio output via a headphone jack or a small mono speaker. A GPIO output is used to control speaker amp. The tablets may or may not have an internal microphone. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard diff --git a/arch/arm/boot/dts/sun5i-q8-common.dtsi b/arch/arm/boot/dts/sun5i-q8-common.dtsi index 0f7ec63..471d46d 100644 --- a/arch/arm/boot/dts/sun5i-q8-common.dtsi +++ b/arch/arm/boot/dts/sun5i-q8-common.dtsi @@ -61,6 +61,13 @@ }; }; +&codec { + pinctrl-names = "default"; + pinctrl-0 = <&codec_pa_pin>; + allwinner,pa-gpios = <&pio 6 10 GPIO_ACTIVE_HIGH>; /* PG10 */ + status = "okay"; +}; + &cpu0 { cpu-supply = <®_dcdc2>; }; @@ -100,6 +107,13 @@ }; &pio { + codec_pa_pin: codec_pa_pin@0 { + allwinner,pins = "PG10"; + allwinner,function = "gpio_out"; + allwinner,drive = ; + allwinner,pull = ; + }; + mmc0_cd_pin_q8: mmc0_cd_pin@0 { allwinner,pins = "PG0"; allwinner,function = "gpio_in"; -- cgit v0.10.2 From 5313ab7e3229da2d9e0301cb0208d0f26c2b80c9 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Tue, 17 May 2016 23:56:11 +0800 Subject: ARM: dts: sun5i: q8-common: Enable display pipeline and LCD display Q8 form factor A13 tablets have a 7" LCD panel. Unfortunately we don't know the exact model of the panel. Just pick a panel with display timings close to what we know. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard diff --git a/arch/arm/boot/dts/sun5i-q8-common.dtsi b/arch/arm/boot/dts/sun5i-q8-common.dtsi index 471d46d..b6af9a4 100644 --- a/arch/arm/boot/dts/sun5i-q8-common.dtsi +++ b/arch/arm/boot/dts/sun5i-q8-common.dtsi @@ -59,6 +59,29 @@ chosen { stdout-path = "serial0:115200n8"; }; + + panel: panel { + compatible = "urt,umsh-8596md-t", "simple-panel"; + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + /* TODO: lcd panel uses axp gpio0 as enable pin */ + backlight = <&backlight>; + #address-cells = <1>; + #size-cells = <0>; + + panel_input: endpoint@0 { + reg = <0>; + remote-endpoint = <&tcon0_out_lcd>; + }; + }; + }; +}; + +&be0 { + status = "okay"; }; &codec { @@ -173,6 +196,19 @@ status = "okay"; }; +&tcon0 { + pinctrl-names = "default"; + pinctrl-0 = <&lcd_rgb666_pins>; + status = "okay"; +}; + +&tcon0_out { + tcon0_out_lcd: endpoint@0 { + reg = <0>; + remote-endpoint = <&panel_input>; + }; +}; + &uart1 { pinctrl-names = "default"; pinctrl-0 = <&uart1_pins_b>; -- cgit v0.10.2 From 5c7b74558442707b68e72d5ed9469f7a5b57763e Mon Sep 17 00:00:00 2001 From: Michal Suchanek Date: Thu, 26 May 2016 19:25:22 +0000 Subject: ARM: dts: sun5i: a10s: add spi2 pins Used on A10s Olinuxino. Signed-off-by: Michal Suchanek Signed-off-by: Maxime Ripard diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi index 367f330..c41a2ba 100644 --- a/arch/arm/boot/dts/sun5i-a10s.dtsi +++ b/arch/arm/boot/dts/sun5i-a10s.dtsi @@ -242,6 +242,20 @@ allwinner,drive = ; allwinner,pull = ; }; + + spi2_pins_a: spi2@0 { + allwinner,pins = "PB12", "PB13", "PB14"; + allwinner,function = "spi2"; + allwinner,drive = ; + allwinner,pull = ; + }; + + spi2_cs0_pins_a: spi2_cs0@0 { + allwinner,pins = "PB11"; + allwinner,function = "spi2"; + allwinner,drive = ; + allwinner,pull = ; + }; }; &sram_a { -- cgit v0.10.2 From b976e7be5cedd25deed7187b360496986ab34501 Mon Sep 17 00:00:00 2001 From: Michal Suchanek Date: Thu, 26 May 2016 19:25:23 +0000 Subject: ARM: dts: sun5i: add spi2 on A10s Olinuxino Micro spi2 is available on the UEXT connector Signed-off-by: Michal Suchanek [Maxime: Fixed the node order] Signed-off-by: Maxime Ripard diff --git a/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts b/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts index 86d046a..aef9147 100644 --- a/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts +++ b/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts @@ -248,6 +248,13 @@ status = "okay"; }; +&spi2 { + pinctrl-names = "default"; + pinctrl-0 = <&spi2_pins_a>, + <&spi2_cs0_pins_a>; + status = "okay"; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pins_a>; -- cgit v0.10.2 From 51189d64848ee47623d8380918fe6a5c0a7a6eb6 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Wed, 1 Jun 2016 00:23:20 +0800 Subject: ARM: dts: sunxi: Add dtsi file for AXP809 PMIC The AXP809 PMIC is used with the Allwinner A80 SoC, along with an AXP806 PMIC as a slave. This patch adds a dtsi file for all the common bindings and default values unrelated to board design. Currently this is just listing all the regulator nodes. The regulators are initialized based on their device node names. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard diff --git a/arch/arm/boot/dts/axp809.dtsi b/arch/arm/boot/dts/axp809.dtsi new file mode 100644 index 0000000..ab8e5f2 --- /dev/null +++ b/arch/arm/boot/dts/axp809.dtsi @@ -0,0 +1,53 @@ +/* + * Copyright 2015 Chen-Yu Tsai + * + * Chen-Yu Tsai + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/* + * AXP809 Integrated Power Management Chip + */ + +&axp809 { + compatible = "x-powers,axp809"; + interrupt-controller; + #interrupt-cells = <1>; +}; -- cgit v0.10.2 From aa4a27bc819ebecab2a86e3cb529cbea51db4bfa Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Wed, 1 Jun 2016 00:23:21 +0800 Subject: ARM: dts: sun9i: a80-optimus: Add AXP809 PMIC device node and regulators The AXP809 PMIC is the primary PMIC. It provides various supply voltages for the SoC and other peripherals. The PMIC's interrupt line is connected to NMI pin of the SoC. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard diff --git a/arch/arm/boot/dts/sun9i-a80-optimus.dts b/arch/arm/boot/dts/sun9i-a80-optimus.dts index d7a20d9..6cfc021 100644 --- a/arch/arm/boot/dts/sun9i-a80-optimus.dts +++ b/arch/arm/boot/dts/sun9i-a80-optimus.dts @@ -150,7 +150,7 @@ &mmc0 { pinctrl-names = "default"; pinctrl-0 = <&mmc0_pins>, <&mmc0_cd_pin_optimus>; - vmmc-supply = <®_vcc3v0>; + vmmc-supply = <®_dcdc1>; bus-width = <4>; cd-gpios = <&pio 7 18 GPIO_ACTIVE_HIGH>; /* PH8 */ cd-inverted; @@ -160,7 +160,7 @@ &mmc2 { pinctrl-names = "default"; pinctrl-0 = <&mmc2_8bit_pins>; - vmmc-supply = <®_vcc3v0>; + vmmc-supply = <®_dcdc1>; bus-width = <8>; non-removable; cap-mmc-hw-reset; @@ -193,8 +193,135 @@ &r_rsb { status = "okay"; + + axp809: pmic@3a3 { + reg = <0x3a3>; + interrupt-parent = <&nmi_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + + regulators { + reg_aldo1: aldo1 { + /* + * TODO: This should be handled by the + * USB PHY driver. + */ + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc33-usbh"; + }; + + reg_aldo2: aldo2 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc-pb-io-cam"; + }; + + aldo3 { + /* unused */ + }; + + reg_dc5ldo: dc5ldo { + regulator-always-on; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-cpus-09-usbh"; + }; + + reg_dcdc1: dcdc1 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc-3v"; + }; + + reg_dcdc2: dcdc2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-gpu"; + }; + + reg_dcdc3: dcdc3 { + regulator-always-on; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-cpua"; + }; + + reg_dcdc4: dcdc4 { + regulator-always-on; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-sys-usb0-hdmi"; + }; + + reg_dcdc5: dcdc5 { + regulator-always-on; + regulator-min-microvolt = <1425000>; + regulator-max-microvolt = <1575000>; + regulator-name = "vcc-dram"; + }; + + reg_dldo1: dldo1 { + /* + * The WiFi chip supports a wide range + * (3.0 ~ 4.8V) of voltages, and so does + * this regulator (3.0 ~ 4.2V), but + * Allwinner SDK always sets it to 3.3V. + */ + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-wifi"; + }; + + reg_dldo2: dldo2 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc-pl"; + }; + + reg_eldo1: eldo1 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-name = "vcc-dvdd-cam"; + }; + + reg_eldo2: eldo2 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc-pe"; + }; + + reg_eldo3: eldo3 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc-pm-codec-io1"; + }; + + reg_ldo_io0: ldo_io0 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc-pg"; + }; + + reg_ldo_io1: ldo_io1 { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-name = "vcc-pa-gmac-2v5"; + }; + + reg_rtc_ldo: rtc_ldo { + regulator-name = "vcc-rtc-vdd1v8-io"; + }; + }; + }; }; +#include "axp809.dtsi" + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pins_a>; -- cgit v0.10.2 From 1e1dea72651bff7bad8273d39c909ff8623cee6b Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Wed, 1 Jun 2016 00:23:22 +0800 Subject: ARM: dts: sun9i: cubieboard4: Add AXP809 PMIC device node and regulators The AXP809 PMIC is the primary PMIC. It provides various supply voltages for the SoC and other peripherals. The PMIC's interrupt line is connected to NMI pin of the SoC. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard diff --git a/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts b/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts index eb2ccd0..8d8af11 100644 --- a/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts +++ b/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts @@ -98,7 +98,7 @@ &mmc0 { pinctrl-names = "default"; pinctrl-0 = <&mmc0_pins>, <&mmc0_cd_pin_cubieboard4>; - vmmc-supply = <®_vcc3v0>; + vmmc-supply = <®_dcdc1>; bus-width = <4>; cd-gpios = <&pio 7 18 GPIO_ACTIVE_HIGH>; /* PH18 */ cd-inverted; @@ -108,7 +108,7 @@ &mmc2 { pinctrl-names = "default"; pinctrl-0 = <&mmc2_8bit_pins>; - vmmc-supply = <®_vcc3v0>; + vmmc-supply = <®_dcdc1>; bus-width = <8>; non-removable; cap-mmc-hw-reset; @@ -126,8 +126,135 @@ &r_rsb { status = "okay"; + + axp809: pmic@3a3 { + reg = <0x3a3>; + interrupt-parent = <&nmi_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + + regulators { + reg_aldo1: aldo1 { + /* + * TODO: This should be handled by the + * USB PHY driver. + */ + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc33-usbh"; + }; + + reg_aldo2: aldo2 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc-pb-io-cam"; + }; + + aldo3 { + /* unused */ + }; + + reg_dc5ldo: dc5ldo { + regulator-always-on; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-cpus-09-usbh"; + }; + + reg_dcdc1: dcdc1 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc-3v"; + }; + + reg_dcdc2: dcdc2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-gpu"; + }; + + reg_dcdc3: dcdc3 { + regulator-always-on; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-cpua"; + }; + + reg_dcdc4: dcdc4 { + regulator-always-on; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-sys-usb0-hdmi"; + }; + + reg_dcdc5: dcdc5 { + regulator-always-on; + regulator-min-microvolt = <1425000>; + regulator-max-microvolt = <1575000>; + regulator-name = "vcc-dram"; + }; + + reg_dldo1: dldo1 { + /* + * The WiFi chip supports a wide range + * (3.0 ~ 4.8V) of voltages, and so does + * this regulator (3.0 ~ 4.2V), but + * Allwinner SDK always sets it to 3.3V. + */ + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-wifi"; + }; + + reg_dldo2: dldo2 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc-pl"; + }; + + reg_eldo1: eldo1 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-name = "vcc-dvdd-cam"; + }; + + reg_eldo2: eldo2 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc-pe"; + }; + + reg_eldo3: eldo3 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc-pm-codec-io1"; + }; + + reg_ldo_io0: ldo_io0 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc-pg"; + }; + + reg_ldo_io1: ldo_io1 { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-name = "vcc-pa-gmac-2v5"; + }; + + reg_rtc_ldo: rtc_ldo { + regulator-name = "vcc-rtc-vdd1v8-io"; + }; + }; + }; }; +#include "axp809.dtsi" + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pins_a>; -- cgit v0.10.2 From 2bcb2b1b95e636bf8222470cf9e4461fd4566789 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Thu, 2 Jun 2016 15:50:09 +0800 Subject: ARM: dts: sun8i-h3: move uart0 pins to sort pinmux list in proper order Move uart0 pins to sort the list of pin settings in alphabetical order. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi index 4a4926b..5255804 100644 --- a/arch/arm/boot/dts/sun8i-h3.dtsi +++ b/arch/arm/boot/dts/sun8i-h3.dtsi @@ -501,13 +501,6 @@ interrupt-controller; #interrupt-cells = <3>; - uart0_pins_a: uart0@0 { - allwinner,pins = "PA4", "PA5"; - allwinner,function = "uart0"; - allwinner,drive = ; - allwinner,pull = ; - }; - mmc0_pins_a: mmc0@0 { allwinner,pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5"; @@ -540,6 +533,13 @@ allwinner,drive = ; allwinner,pull = ; }; + + uart0_pins_a: uart0@0 { + allwinner,pins = "PA4", "PA5"; + allwinner,function = "uart0"; + allwinner,drive = ; + allwinner,pull = ; + }; }; ahb_rst: reset@01c202c0 { -- cgit v0.10.2 From 966c11a3b5e47689b7894c4e87548e9f99b1532a Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Thu, 2 Jun 2016 15:50:10 +0800 Subject: ARM: dts: sun8i-h3: Add uart1 pinmux setting Add uart1 pins for 4 pin (RX/TX/RTS/CTS) mode. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi index 5255804..3c37f7e 100644 --- a/arch/arm/boot/dts/sun8i-h3.dtsi +++ b/arch/arm/boot/dts/sun8i-h3.dtsi @@ -540,6 +540,13 @@ allwinner,drive = ; allwinner,pull = ; }; + + uart1_pins_a: uart1@0 { + allwinner,pins = "PG6", "PG7", "PG8", "PG9"; + allwinner,function = "uart1"; + allwinner,drive = ; + allwinner,pull = ; + }; }; ahb_rst: reset@01c202c0 { -- cgit v0.10.2 From 1db9c753f7aac4f80ad635332228a19a13c42759 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Thu, 2 Jun 2016 15:50:11 +0800 Subject: ARM: dts: sun8i-h3: Add dts file for Sinovoip BPI-M2+ The BPI-M2+ is an H3 development board. It is a smaller form factor than the original BPI-M2, with the new H3 SoC. It has 1GB DRAM, 8GB eMMC, a micro SD card slot, HDMI output, 2 USB host connector and 1 USB OTG connector, an IR receiver, WiFi+BT based on Ampak AP6212. The board also has a 3 pin header for (debug) UART, a 40 pin GPIO header based on the Raspberry Pi B+, but the peripheral signals are not the same, and an FPC connector for connecting BPI's camera. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 06b6c2d..970e906 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -765,7 +765,8 @@ dtb-$(CONFIG_MACH_SUN8I) += \ sun8i-h3-orangepi-2.dtb \ sun8i-h3-orangepi-one.dtb \ sun8i-h3-orangepi-pc.dtb \ - sun8i-h3-orangepi-plus.dtb + sun8i-h3-orangepi-plus.dtb \ + sun8i-h3-sinovoip-bpi-m2-plus.dtb dtb-$(CONFIG_MACH_SUN9I) += \ sun9i-a80-optimus.dtb \ sun9i-a80-cubieboard4.dtb diff --git a/arch/arm/boot/dts/sun8i-h3-sinovoip-bpi-m2-plus.dts b/arch/arm/boot/dts/sun8i-h3-sinovoip-bpi-m2-plus.dts new file mode 100644 index 0000000..d21bc57 --- /dev/null +++ b/arch/arm/boot/dts/sun8i-h3-sinovoip-bpi-m2-plus.dts @@ -0,0 +1,195 @@ +/* + * Copyright (C) 2016 Chen-Yu Tsai + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun8i-h3.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include +#include +#include + +/ { + model = "Sinovoip BPI-M2+"; + compatible = "sinovoip,bpi-m2+", "allwinner,sun8i-h3"; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pwr_led_bpi_m2p>; + + pwr_led { + label = "bpi-m2+:red:pwr"; + gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; /* PL10 */ + default-state = "on"; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&sw_r_bpi_m2p>; + + sw4 { + label = "power"; + linux,code = ; + gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; + }; + }; + + wifi_pwrseq: wifi_pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_en_bpi_m2p>; + reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */ + }; +}; + +&ehci1 { + status = "okay"; +}; + +&ehci2 { + status = "okay"; +}; + +&ir { + pinctrl-names = "default"; + pinctrl-0 = <&ir_pins_a>; + status = "okay"; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>; + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */ + cd-inverted; + status = "okay"; +}; + +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins_a>; + vmmc-supply = <®_vcc3v3>; + vqmmc-supply = <®_vcc3v3>; + mmc-pwrseq = <&wifi_pwrseq>; + bus-width = <4>; + non-removable; + status = "okay"; + + brcmf: bcrmf@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + interrupt-parent = <&pio>; + interrupts = <6 10 IRQ_TYPE_LEVEL_LOW>; /* PG10 / EINT10 */ + interrupt-names = "host-wake"; + }; +}; + +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_8bit_pins>; + vmmc-supply = <®_vcc3v3>; + vqmmc-supply = <®_vcc3v3>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&ohci2 { + status = "okay"; +}; + +&r_pio { + pwr_led_bpi_m2p: led_pins@0 { + allwinner,pins = "PL10"; + allwinner,function = "gpio_out"; + allwinner,drive = ; + allwinner,pull = ; + }; + + sw_r_bpi_m2p: key_pins@0 { + allwinner,pins = "PL3"; + allwinner,function = "gpio_in"; + allwinner,drive = ; + allwinner,pull = ; + }; + + wifi_en_bpi_m2p: wifi_en_pin { + allwinner,pins = "PL7"; + allwinner,function = "gpio_out"; + allwinner,drive = ; + allwinner,pull = ; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins_a>; + status = "okay"; +}; + +&usbphy { + /* USB VBUS is on as long as VCC-IO is on */ + status = "okay"; +}; -- cgit v0.10.2 From 2480c018ea2ae53879725b79beba4a9e38ce5e82 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Fri, 3 Jun 2016 20:10:40 +0200 Subject: ARM: dts: sun5i-a10s-wobo-i5: Enable ldo4 too It seems that the wifi chip is powered by both ldo3 and ldo4 tied together and that using only one results in the wifi-chip dropping of the USB bus sometimes. Ideally we would have a proper way of modelling this (this is being worked on), but currently we do not. This is not an issue since we need to keep these regulators always-on anyways, due to these boards crashing when ldo3/4 get turned back on after having been turned off. Signed-off-by: Hans de Goede Signed-off-by: Maxime Ripard diff --git a/arch/arm/boot/dts/sun5i-a10s-wobo-i5.dts b/arch/arm/boot/dts/sun5i-a10s-wobo-i5.dts index 9fea918..52d18ca 100644 --- a/arch/arm/boot/dts/sun5i-a10s-wobo-i5.dts +++ b/arch/arm/boot/dts/sun5i-a10s-wobo-i5.dts @@ -195,7 +195,14 @@ regulator-always-on; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi"; + regulator-name = "vcc-wifi1"; +}; + +®_ldo4 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-wifi2"; }; ®_usb1_vbus { -- cgit v0.10.2 From 5f4d0ebe88b98ee7e878d4fc823e61a172c28060 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Fri, 3 Jun 2016 14:50:50 +0800 Subject: ARM: dts: sun9i: a80-optimus: Drop sunxi-common-regulators.dtsi sunxi-common-regulators.dtsi provided dummy regulators vcc3v0, vcc3v3, vcc5v0. 3.0V/3.3V and 5.0V are commonly used voltages in Allwinner devices. These dummy regulators provide a stand-in when bindings that require one, but the real regulator is not supported yet. Since these are no longer needed, we can drop the include file by copying over reg_usb1_vbus. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard diff --git a/arch/arm/boot/dts/sun9i-a80-optimus.dts b/arch/arm/boot/dts/sun9i-a80-optimus.dts index 6cfc021..78fddd9 100644 --- a/arch/arm/boot/dts/sun9i-a80-optimus.dts +++ b/arch/arm/boot/dts/sun9i-a80-optimus.dts @@ -44,7 +44,6 @@ /dts-v1/; #include "sun9i-a80.dtsi" -#include "sunxi-common-regulators.dtsi" #include #include @@ -85,6 +84,17 @@ }; }; + reg_usb1_vbus: usb1-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&usb1_vbus_pin_optimus>; + regulator-name = "usb1-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ + }; + reg_usb3_vbus: usb3-vbus { compatible = "regulator-fixed"; pinctrl-names = "default"; @@ -172,12 +182,6 @@ allwinner,drive = ; }; -®_usb1_vbus { - pinctrl-0 = <&usb1_vbus_pin_optimus>; - gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ - status = "okay"; -}; - &r_ir { status = "okay"; }; -- cgit v0.10.2 From 1f241993d4cff64e4125e982a3172f846b5d6909 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Fri, 3 Jun 2016 14:50:51 +0800 Subject: ARM: dts: sun9i: cubieboard4: Drop sunxi-common-regulators.dtsi sunxi-common-regulators.dtsi provided dummy regulators vcc3v0, vcc3v3, vcc5v0. 3.0V/3.3V and 5.0V are commonly used voltages in Allwinner devices. These dummy regulators provide a stand-in when bindings that require one, but the real regulator is not supported yet. Since these are no longer needed, we can drop the include file. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard diff --git a/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts b/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts index 8d8af11..db770d0 100644 --- a/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts +++ b/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts @@ -45,7 +45,6 @@ /dts-v1/; #include "sun9i-a80.dtsi" -#include "sunxi-common-regulators.dtsi" #include #include -- cgit v0.10.2 From fc51b632c7b047c25807023b76f3877aed19c770 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Sat, 4 Jun 2016 12:58:39 +0200 Subject: ARM: dts: sunxi: Add a startup delay for fixed regulator enabled phys It seems that recent kernels have a shorter timeout when scanning for ethernet phys causing us to hit a timeout on boards where the phy's regulator gets enabled just before scanning, which leads to non working ethernet. A 10ms startup delay seems to be enough to fix it, this commit adds a 20ms startup delay just to be safe. This has been tested on a sun4i-a10-a1000 and sun5i-a10s-wobo-i5 board, both of which have non-working ethernet on recent kernels without this fix. Cc: stable@vger.kernel.org Signed-off-by: Hans de Goede Signed-off-by: Maxime Ripard diff --git a/arch/arm/boot/dts/sun4i-a10-a1000.dts b/arch/arm/boot/dts/sun4i-a10-a1000.dts index c92a1ae..fa70b8f 100644 --- a/arch/arm/boot/dts/sun4i-a10-a1000.dts +++ b/arch/arm/boot/dts/sun4i-a10-a1000.dts @@ -84,6 +84,7 @@ regulator-name = "emac-3v3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; + startup-delay-us = <20000>; enable-active-high; gpio = <&pio 7 15 GPIO_ACTIVE_HIGH>; }; diff --git a/arch/arm/boot/dts/sun4i-a10-hackberry.dts b/arch/arm/boot/dts/sun4i-a10-hackberry.dts index 2b17c51..6de83a6 100644 --- a/arch/arm/boot/dts/sun4i-a10-hackberry.dts +++ b/arch/arm/boot/dts/sun4i-a10-hackberry.dts @@ -66,6 +66,7 @@ regulator-name = "emac-3v3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; + startup-delay-us = <20000>; enable-active-high; gpio = <&pio 7 19 GPIO_ACTIVE_HIGH>; }; diff --git a/arch/arm/boot/dts/sun4i-a10-jesurun-q5.dts b/arch/arm/boot/dts/sun4i-a10-jesurun-q5.dts index 7afc7a6..e28f080 100644 --- a/arch/arm/boot/dts/sun4i-a10-jesurun-q5.dts +++ b/arch/arm/boot/dts/sun4i-a10-jesurun-q5.dts @@ -80,6 +80,7 @@ regulator-name = "emac-3v3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; + startup-delay-us = <20000>; enable-active-high; gpio = <&pio 7 19 GPIO_ACTIVE_HIGH>; /* PH19 */ }; diff --git a/arch/arm/boot/dts/sun5i-a10s-wobo-i5.dts b/arch/arm/boot/dts/sun5i-a10s-wobo-i5.dts index 52d18ca..b5de75f 100644 --- a/arch/arm/boot/dts/sun5i-a10s-wobo-i5.dts +++ b/arch/arm/boot/dts/sun5i-a10s-wobo-i5.dts @@ -79,6 +79,7 @@ regulator-name = "emac-3v3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; + startup-delay-us = <20000>; enable-active-high; gpio = <&pio 0 2 GPIO_ACTIVE_HIGH>; }; -- cgit v0.10.2 From a8af25e1ea690353d740ffd052b8365ba3df08d4 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Sun, 5 Jun 2016 14:22:47 +0200 Subject: ARM: dts: sun4i: HDMI and the tv-encoder use tcon ch1 not ch0 Update the simplefb nodes for hdmi / tv-encoder out to point to tcon0_ch1 instead of tcon0_ch0 as tcon clock. While at it fix the clocks lines being longer than 80 chars. Signed-off-by: Hans de Goede Acked-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi index a9c3190..616b0f9 100644 --- a/arch/arm/boot/dts/sun4i-a10.dtsi +++ b/arch/arm/boot/dts/sun4i-a10.dtsi @@ -65,8 +65,9 @@ compatible = "allwinner,simple-framebuffer", "simple-framebuffer"; allwinner,pipeline = "de_be0-lcd0-hdmi"; - clocks = <&ahb_gates 36>, <&ahb_gates 43>, <&ahb_gates 44>, - <&de_be0_clk>, <&tcon0_ch0_clk>, <&dram_gates 26>; + clocks = <&ahb_gates 36>, <&ahb_gates 43>, + <&ahb_gates 44>, <&de_be0_clk>, + <&tcon0_ch1_clk>, <&dram_gates 26>; status = "disabled"; }; @@ -76,7 +77,7 @@ allwinner,pipeline = "de_fe0-de_be0-lcd0-hdmi"; clocks = <&ahb_gates 36>, <&ahb_gates 43>, <&ahb_gates 44>, <&ahb_gates 46>, - <&de_be0_clk>, <&de_fe0_clk>, <&tcon0_ch0_clk>, + <&de_be0_clk>, <&de_fe0_clk>, <&tcon0_ch1_clk>, <&dram_gates 25>, <&dram_gates 26>; status = "disabled"; }; @@ -97,8 +98,9 @@ allwinner,pipeline = "de_fe0-de_be0-lcd0-tve0"; clocks = <&ahb_gates 34>, <&ahb_gates 36>, <&ahb_gates 44>, <&ahb_gates 46>, - <&de_be0_clk>, <&de_fe0_clk>, <&tcon0_ch0_clk>, - <&dram_gates 5>, <&dram_gates 25>, <&dram_gates 26>; + <&de_be0_clk>, <&de_fe0_clk>, + <&tcon0_ch1_clk>, <&dram_gates 5>, + <&dram_gates 25>, <&dram_gates 26>; status = "disabled"; }; }; -- cgit v0.10.2 From 0162117056773403988659a56b41152211ad352d Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Sun, 5 Jun 2016 14:22:48 +0200 Subject: ARM: dts: sun7i: HDMI and the tv-encoder use tcon ch1 not ch0 Update the simplefb nodes for hdmi / tv-encoder out to point to tcon0_ch1 instead of tcon0_ch0 as tcon clock. While at it fix the clocks lines being longer than 80 chars. Signed-off-by: Hans de Goede Acked-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index 734f07b..a2666fc 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -67,8 +67,9 @@ compatible = "allwinner,simple-framebuffer", "simple-framebuffer"; allwinner,pipeline = "de_be0-lcd0-hdmi"; - clocks = <&ahb_gates 36>, <&ahb_gates 43>, <&ahb_gates 44>, - <&de_be0_clk>, <&tcon0_ch0_clk>, <&dram_gates 26>; + clocks = <&ahb_gates 36>, <&ahb_gates 43>, + <&ahb_gates 44>, <&de_be0_clk>, + <&tcon0_ch1_clk>, <&dram_gates 26>; status = "disabled"; }; @@ -86,8 +87,9 @@ compatible = "allwinner,simple-framebuffer", "simple-framebuffer"; allwinner,pipeline = "de_be0-lcd0-tve0"; - clocks = <&ahb_gates 34>, <&ahb_gates 36>, <&ahb_gates 44>, - <&de_be0_clk>, <&tcon0_ch0_clk>, + clocks = <&ahb_gates 34>, <&ahb_gates 36>, + <&ahb_gates 44>, + <&de_be0_clk>, <&tcon0_ch1_clk>, <&dram_gates 5>, <&dram_gates 26>; status = "disabled"; }; -- cgit v0.10.2 From 03907ab3db6865768b9b8244fb362a284e912dfd Mon Sep 17 00:00:00 2001 From: Aleksei Mamlin Date: Fri, 10 Jun 2016 11:05:18 +0300 Subject: ARM: dts: sun4i: Re-order pinctrl nodes alphabetically No functional change. Re-order sun4i pinctrl nodes alphabetically. Signed-off-by: Aleksei Mamlin Signed-off-by: Maxime Ripard diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi index 616b0f9..f1b75c8 100644 --- a/arch/arm/boot/dts/sun4i-a10.dtsi +++ b/arch/arm/boot/dts/sun4i-a10.dtsi @@ -960,69 +960,62 @@ #interrupt-cells = <3>; #gpio-cells = <3>; - pwm0_pins_a: pwm0@0 { - allwinner,pins = "PB2"; - allwinner,function = "pwm"; - allwinner,drive = ; - allwinner,pull = ; - }; - - pwm1_pins_a: pwm1@0 { - allwinner,pins = "PI3"; - allwinner,function = "pwm"; + emac_pins_a: emac0@0 { + allwinner,pins = "PA0", "PA1", "PA2", + "PA3", "PA4", "PA5", "PA6", + "PA7", "PA8", "PA9", "PA10", + "PA11", "PA12", "PA13", "PA14", + "PA15", "PA16"; + allwinner,function = "emac"; allwinner,drive = ; allwinner,pull = ; }; - uart0_pins_a: uart0@0 { - allwinner,pins = "PB22", "PB23"; - allwinner,function = "uart0"; + i2c0_pins_a: i2c0@0 { + allwinner,pins = "PB0", "PB1"; + allwinner,function = "i2c0"; allwinner,drive = ; allwinner,pull = ; }; - uart0_pins_b: uart0@1 { - allwinner,pins = "PF2", "PF4"; - allwinner,function = "uart0"; + i2c1_pins_a: i2c1@0 { + allwinner,pins = "PB18", "PB19"; + allwinner,function = "i2c1"; allwinner,drive = ; allwinner,pull = ; }; - uart1_pins_a: uart1@0 { - allwinner,pins = "PA10", "PA11"; - allwinner,function = "uart1"; + i2c2_pins_a: i2c2@0 { + allwinner,pins = "PB20", "PB21"; + allwinner,function = "i2c2"; allwinner,drive = ; allwinner,pull = ; }; - i2c0_pins_a: i2c0@0 { - allwinner,pins = "PB0", "PB1"; - allwinner,function = "i2c0"; + ir0_rx_pins_a: ir0@0 { + allwinner,pins = "PB4"; + allwinner,function = "ir0"; allwinner,drive = ; allwinner,pull = ; }; - i2c1_pins_a: i2c1@0 { - allwinner,pins = "PB18", "PB19"; - allwinner,function = "i2c1"; + ir0_tx_pins_a: ir0@1 { + allwinner,pins = "PB3"; + allwinner,function = "ir0"; allwinner,drive = ; allwinner,pull = ; }; - i2c2_pins_a: i2c2@0 { - allwinner,pins = "PB20", "PB21"; - allwinner,function = "i2c2"; + ir1_rx_pins_a: ir1@0 { + allwinner,pins = "PB23"; + allwinner,function = "ir1"; allwinner,drive = ; allwinner,pull = ; }; - emac_pins_a: emac0@0 { - allwinner,pins = "PA0", "PA1", "PA2", - "PA3", "PA4", "PA5", "PA6", - "PA7", "PA8", "PA9", "PA10", - "PA11", "PA12", "PA13", "PA14", - "PA15", "PA16"; - allwinner,function = "emac"; + ir1_tx_pins_a: ir1@1 { + allwinner,pins = "PB22"; + allwinner,function = "ir1"; allwinner,drive = ; allwinner,pull = ; }; @@ -1042,34 +1035,41 @@ allwinner,pull = ; }; - ir0_rx_pins_a: ir0@0 { - allwinner,pins = "PB4"; - allwinner,function = "ir0"; + ps20_pins_a: ps20@0 { + allwinner,pins = "PI20", "PI21"; + allwinner,function = "ps2"; allwinner,drive = ; allwinner,pull = ; }; - ir0_tx_pins_a: ir0@1 { - allwinner,pins = "PB3"; - allwinner,function = "ir0"; + ps21_pins_a: ps21@0 { + allwinner,pins = "PH12", "PH13"; + allwinner,function = "ps2"; allwinner,drive = ; allwinner,pull = ; }; - ir1_rx_pins_a: ir1@0 { - allwinner,pins = "PB23"; - allwinner,function = "ir1"; + pwm0_pins_a: pwm0@0 { + allwinner,pins = "PB2"; + allwinner,function = "pwm"; allwinner,drive = ; allwinner,pull = ; }; - ir1_tx_pins_a: ir1@1 { - allwinner,pins = "PB22"; - allwinner,function = "ir1"; + pwm1_pins_a: pwm1@0 { + allwinner,pins = "PI3"; + allwinner,function = "pwm"; allwinner,drive = ; allwinner,pull = ; }; + spdif_tx_pins_a: spdif@0 { + allwinner,pins = "PB13"; + allwinner,function = "spdif"; + allwinner,drive = ; + allwinner,pull = ; + }; + spi0_pins_a: spi0@0 { allwinner,pins = "PI11", "PI12", "PI13"; allwinner,function = "spi0"; @@ -1126,25 +1126,25 @@ allwinner,pull = ; }; - ps20_pins_a: ps20@0 { - allwinner,pins = "PI20", "PI21"; - allwinner,function = "ps2"; + uart0_pins_a: uart0@0 { + allwinner,pins = "PB22", "PB23"; + allwinner,function = "uart0"; allwinner,drive = ; allwinner,pull = ; }; - ps21_pins_a: ps21@0 { - allwinner,pins = "PH12", "PH13"; - allwinner,function = "ps2"; + uart0_pins_b: uart0@1 { + allwinner,pins = "PF2", "PF4"; + allwinner,function = "uart0"; allwinner,drive = ; allwinner,pull = ; }; - spdif_tx_pins_a: spdif@0 { - allwinner,pins = "PB13"; - allwinner,function = "spdif"; + uart1_pins_a: uart1@0 { + allwinner,pins = "PA10", "PA11"; + allwinner,function = "uart1"; allwinner,drive = ; - allwinner,pull = ; + allwinner,pull = ; }; }; -- cgit v0.10.2 From d130f2e7cf24e875271cf33f38c54ef31f34a92e Mon Sep 17 00:00:00 2001 From: Aleksei Mamlin Date: Fri, 10 Jun 2016 11:05:19 +0300 Subject: ARM: dts: sun7i: Re-order pinctrl nodes alphabetically No functional change. Re-order sun7i pinctrl nodes alphabetically. Signed-off-by: Aleksei Mamlin Signed-off-by: Maxime Ripard diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index a2666fc..e1adae7 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -1034,160 +1034,177 @@ #interrupt-cells = <3>; #gpio-cells = <3>; - pwm0_pins_a: pwm0@0 { - allwinner,pins = "PB2"; - allwinner,function = "pwm"; + clk_out_a_pins_a: clk_out_a@0 { + allwinner,pins = "PI12"; + allwinner,function = "clk_out_a"; allwinner,drive = ; allwinner,pull = ; }; - pwm1_pins_a: pwm1@0 { - allwinner,pins = "PI3"; - allwinner,function = "pwm"; + clk_out_b_pins_a: clk_out_b@0 { + allwinner,pins = "PI13"; + allwinner,function = "clk_out_b"; allwinner,drive = ; allwinner,pull = ; }; - uart0_pins_a: uart0@0 { - allwinner,pins = "PB22", "PB23"; - allwinner,function = "uart0"; + emac_pins_a: emac0@0 { + allwinner,pins = "PA0", "PA1", "PA2", + "PA3", "PA4", "PA5", "PA6", + "PA7", "PA8", "PA9", "PA10", + "PA11", "PA12", "PA13", "PA14", + "PA15", "PA16"; + allwinner,function = "emac"; allwinner,drive = ; allwinner,pull = ; }; - uart2_pins_a: uart2@0 { - allwinner,pins = "PI16", "PI17", "PI18", "PI19"; - allwinner,function = "uart2"; + gmac_pins_mii_a: gmac_mii@0 { + allwinner,pins = "PA0", "PA1", "PA2", + "PA3", "PA4", "PA5", "PA6", + "PA7", "PA8", "PA9", "PA10", + "PA11", "PA12", "PA13", "PA14", + "PA15", "PA16"; + allwinner,function = "gmac"; allwinner,drive = ; allwinner,pull = ; }; - uart3_pins_a: uart3@0 { - allwinner,pins = "PG6", "PG7", "PG8", "PG9"; - allwinner,function = "uart3"; - allwinner,drive = ; + gmac_pins_rgmii_a: gmac_rgmii@0 { + allwinner,pins = "PA0", "PA1", "PA2", + "PA3", "PA4", "PA5", "PA6", + "PA7", "PA8", "PA10", + "PA11", "PA12", "PA13", + "PA15", "PA16"; + allwinner,function = "gmac"; + /* + * data lines in RGMII mode use DDR mode + * and need a higher signal drive strength + */ + allwinner,drive = ; allwinner,pull = ; }; - uart3_pins_b: uart3@1 { - allwinner,pins = "PH0", "PH1"; - allwinner,function = "uart3"; + i2c0_pins_a: i2c0@0 { + allwinner,pins = "PB0", "PB1"; + allwinner,function = "i2c0"; allwinner,drive = ; allwinner,pull = ; }; - uart4_pins_a: uart4@0 { - allwinner,pins = "PG10", "PG11"; - allwinner,function = "uart4"; + i2c1_pins_a: i2c1@0 { + allwinner,pins = "PB18", "PB19"; + allwinner,function = "i2c1"; allwinner,drive = ; allwinner,pull = ; }; - uart4_pins_b: uart4@1 { - allwinner,pins = "PH4", "PH5"; - allwinner,function = "uart4"; + i2c2_pins_a: i2c2@0 { + allwinner,pins = "PB20", "PB21"; + allwinner,function = "i2c2"; allwinner,drive = ; allwinner,pull = ; }; - uart5_pins_a: uart5@0 { - allwinner,pins = "PI10", "PI11"; - allwinner,function = "uart5"; + i2c3_pins_a: i2c3@0 { + allwinner,pins = "PI0", "PI1"; + allwinner,function = "i2c3"; allwinner,drive = ; allwinner,pull = ; }; - uart6_pins_a: uart6@0 { - allwinner,pins = "PI12", "PI13"; - allwinner,function = "uart6"; - allwinner,drive = ; - allwinner,pull = ; + ir0_rx_pins_a: ir0@0 { + allwinner,pins = "PB4"; + allwinner,function = "ir0"; + allwinner,drive = ; + allwinner,pull = ; }; - uart7_pins_a: uart7@0 { - allwinner,pins = "PI20", "PI21"; - allwinner,function = "uart7"; - allwinner,drive = ; - allwinner,pull = ; + ir0_tx_pins_a: ir0@1 { + allwinner,pins = "PB3"; + allwinner,function = "ir0"; + allwinner,drive = ; + allwinner,pull = ; }; - i2c0_pins_a: i2c0@0 { - allwinner,pins = "PB0", "PB1"; - allwinner,function = "i2c0"; - allwinner,drive = ; - allwinner,pull = ; + ir1_rx_pins_a: ir1@0 { + allwinner,pins = "PB23"; + allwinner,function = "ir1"; + allwinner,drive = ; + allwinner,pull = ; }; - i2c1_pins_a: i2c1@0 { - allwinner,pins = "PB18", "PB19"; - allwinner,function = "i2c1"; - allwinner,drive = ; - allwinner,pull = ; + ir1_tx_pins_a: ir1@1 { + allwinner,pins = "PB22"; + allwinner,function = "ir1"; + allwinner,drive = ; + allwinner,pull = ; }; - i2c2_pins_a: i2c2@0 { - allwinner,pins = "PB20", "PB21"; - allwinner,function = "i2c2"; - allwinner,drive = ; + mmc0_pins_a: mmc0@0 { + allwinner,pins = "PF0", "PF1", "PF2", + "PF3", "PF4", "PF5"; + allwinner,function = "mmc0"; + allwinner,drive = ; allwinner,pull = ; }; - i2c3_pins_a: i2c3@0 { - allwinner,pins = "PI0", "PI1"; - allwinner,function = "i2c3"; + mmc0_cd_pin_reference_design: mmc0_cd_pin@0 { + allwinner,pins = "PH1"; + allwinner,function = "gpio_in"; allwinner,drive = ; + allwinner,pull = ; + }; + + mmc2_pins_a: mmc2@0 { + allwinner,pins = "PC6", "PC7", "PC8", + "PC9", "PC10", "PC11"; + allwinner,function = "mmc2"; + allwinner,drive = ; + allwinner,pull = ; + }; + + mmc3_pins_a: mmc3@0 { + allwinner,pins = "PI4", "PI5", "PI6", + "PI7", "PI8", "PI9"; + allwinner,function = "mmc3"; + allwinner,drive = ; allwinner,pull = ; }; - emac_pins_a: emac0@0 { - allwinner,pins = "PA0", "PA1", "PA2", - "PA3", "PA4", "PA5", "PA6", - "PA7", "PA8", "PA9", "PA10", - "PA11", "PA12", "PA13", "PA14", - "PA15", "PA16"; - allwinner,function = "emac"; + ps20_pins_a: ps20@0 { + allwinner,pins = "PI20", "PI21"; + allwinner,function = "ps2"; allwinner,drive = ; allwinner,pull = ; }; - clk_out_a_pins_a: clk_out_a@0 { - allwinner,pins = "PI12"; - allwinner,function = "clk_out_a"; + ps21_pins_a: ps21@0 { + allwinner,pins = "PH12", "PH13"; + allwinner,function = "ps2"; allwinner,drive = ; allwinner,pull = ; }; - clk_out_b_pins_a: clk_out_b@0 { - allwinner,pins = "PI13"; - allwinner,function = "clk_out_b"; + pwm0_pins_a: pwm0@0 { + allwinner,pins = "PB2"; + allwinner,function = "pwm"; allwinner,drive = ; allwinner,pull = ; }; - gmac_pins_mii_a: gmac_mii@0 { - allwinner,pins = "PA0", "PA1", "PA2", - "PA3", "PA4", "PA5", "PA6", - "PA7", "PA8", "PA9", "PA10", - "PA11", "PA12", "PA13", "PA14", - "PA15", "PA16"; - allwinner,function = "gmac"; + pwm1_pins_a: pwm1@0 { + allwinner,pins = "PI3"; + allwinner,function = "pwm"; allwinner,drive = ; allwinner,pull = ; }; - gmac_pins_rgmii_a: gmac_rgmii@0 { - allwinner,pins = "PA0", "PA1", "PA2", - "PA3", "PA4", "PA5", "PA6", - "PA7", "PA8", "PA10", - "PA11", "PA12", "PA13", - "PA15", "PA16"; - allwinner,function = "gmac"; - /* - * data lines in RGMII mode use DDR mode - * and need a higher signal drive strength - */ - allwinner,drive = ; - allwinner,pull = ; + spdif_tx_pins_a: spdif@0 { + allwinner,pins = "PB13"; + allwinner,function = "spdif"; + allwinner,drive = ; + allwinner,pull = ; }; spi0_pins_a: spi0@0 { @@ -1253,84 +1270,67 @@ allwinner,pull = ; }; - mmc0_pins_a: mmc0@0 { - allwinner,pins = "PF0", "PF1", "PF2", - "PF3", "PF4", "PF5"; - allwinner,function = "mmc0"; - allwinner,drive = ; + uart0_pins_a: uart0@0 { + allwinner,pins = "PB22", "PB23"; + allwinner,function = "uart0"; + allwinner,drive = ; allwinner,pull = ; }; - mmc0_cd_pin_reference_design: mmc0_cd_pin@0 { - allwinner,pins = "PH1"; - allwinner,function = "gpio_in"; + uart2_pins_a: uart2@0 { + allwinner,pins = "PI16", "PI17", "PI18", "PI19"; + allwinner,function = "uart2"; allwinner,drive = ; - allwinner,pull = ; - }; - - mmc2_pins_a: mmc2@0 { - allwinner,pins = "PC6", "PC7", "PC8", - "PC9", "PC10", "PC11"; - allwinner,function = "mmc2"; - allwinner,drive = ; - allwinner,pull = ; - }; - - mmc3_pins_a: mmc3@0 { - allwinner,pins = "PI4", "PI5", "PI6", - "PI7", "PI8", "PI9"; - allwinner,function = "mmc3"; - allwinner,drive = ; allwinner,pull = ; }; - ir0_rx_pins_a: ir0@0 { - allwinner,pins = "PB4"; - allwinner,function = "ir0"; - allwinner,drive = ; - allwinner,pull = ; + uart3_pins_a: uart3@0 { + allwinner,pins = "PG6", "PG7", "PG8", "PG9"; + allwinner,function = "uart3"; + allwinner,drive = ; + allwinner,pull = ; }; - ir0_tx_pins_a: ir0@1 { - allwinner,pins = "PB3"; - allwinner,function = "ir0"; - allwinner,drive = ; - allwinner,pull = ; + uart3_pins_b: uart3@1 { + allwinner,pins = "PH0", "PH1"; + allwinner,function = "uart3"; + allwinner,drive = ; + allwinner,pull = ; }; - ir1_rx_pins_a: ir1@0 { - allwinner,pins = "PB23"; - allwinner,function = "ir1"; - allwinner,drive = ; - allwinner,pull = ; + uart4_pins_a: uart4@0 { + allwinner,pins = "PG10", "PG11"; + allwinner,function = "uart4"; + allwinner,drive = ; + allwinner,pull = ; }; - ir1_tx_pins_a: ir1@1 { - allwinner,pins = "PB22"; - allwinner,function = "ir1"; - allwinner,drive = ; - allwinner,pull = ; + uart4_pins_b: uart4@1 { + allwinner,pins = "PH4", "PH5"; + allwinner,function = "uart4"; + allwinner,drive = ; + allwinner,pull = ; }; - ps20_pins_a: ps20@0 { - allwinner,pins = "PI20", "PI21"; - allwinner,function = "ps2"; + uart5_pins_a: uart5@0 { + allwinner,pins = "PI10", "PI11"; + allwinner,function = "uart5"; allwinner,drive = ; allwinner,pull = ; }; - ps21_pins_a: ps21@0 { - allwinner,pins = "PH12", "PH13"; - allwinner,function = "ps2"; + uart6_pins_a: uart6@0 { + allwinner,pins = "PI12", "PI13"; + allwinner,function = "uart6"; allwinner,drive = ; allwinner,pull = ; }; - spdif_tx_pins_a: spdif@0 { - allwinner,pins = "PB13"; - allwinner,function = "spdif"; + uart7_pins_a: uart7@0 { + allwinner,pins = "PI20", "PI21"; + allwinner,function = "uart7"; allwinner,drive = ; - allwinner,pull = ; + allwinner,pull = ; }; }; -- cgit v0.10.2 From c365df39d95c33274143a67f021521215ffc4b91 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Sat, 11 Jun 2016 15:53:01 +0200 Subject: ARM: dts: axp22x.dtsi: Disable axp22x ldo_io# regulators by default Use of these as regulators conflicts with use of the gpio pins as gpios, so disabled the ldo_io# regulators by default, this avoids the regulator core touching them when the pins are used as gpios. Signed-off-by: Hans de Goede Signed-off-by: Maxime Ripard diff --git a/arch/arm/boot/dts/axp22x.dtsi b/arch/arm/boot/dts/axp22x.dtsi index 76302f5..0cfec50 100644 --- a/arch/arm/boot/dts/axp22x.dtsi +++ b/arch/arm/boot/dts/axp22x.dtsi @@ -126,10 +126,12 @@ reg_ldo_io0: ldo_io0 { regulator-name = "ldo_io0"; + status = "disabled"; }; reg_ldo_io1: ldo_io1 { regulator-name = "ldo_io1"; + status = "disabled"; }; reg_rtc_ldo: rtc_ldo { -- cgit v0.10.2 From 94efd9da3af3f6e03c4304b6cd528e5f94321938 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Sat, 11 Jun 2016 15:53:02 +0200 Subject: ARM: dts: axp22x.dtsi: Add usb_power_supply node Add a node describing the (optional) usbpower-supply of the axp221 / axp223 pmic. Signed-off-by: Hans de Goede Signed-off-by: Maxime Ripard diff --git a/arch/arm/boot/dts/axp22x.dtsi b/arch/arm/boot/dts/axp22x.dtsi index 0cfec50..0401787 100644 --- a/arch/arm/boot/dts/axp22x.dtsi +++ b/arch/arm/boot/dts/axp22x.dtsi @@ -142,4 +142,9 @@ regulator-name = "rtc_ldo"; }; }; + + usb_power_supply: usb_power_supply { + compatible = "x-powers,axp221-usb-power-supply"; + status = "disabled"; + }; }; -- cgit v0.10.2 From 46850c55c64f73238ca3a37b6b8aed0ff664bf78 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Sat, 11 Jun 2016 15:53:03 +0200 Subject: ARM: dts: axp22x.dtsi: Add reg_drivebus node Add a node describing the drivebus regulator which is an (optional) part of the axp221/axp223 pmic. Since this regulator may not be available at all depending on the board, mark it as disabled by default. Signed-off-by: Hans de Goede Signed-off-by: Maxime Ripard diff --git a/arch/arm/boot/dts/axp22x.dtsi b/arch/arm/boot/dts/axp22x.dtsi index 0401787..458b668 100644 --- a/arch/arm/boot/dts/axp22x.dtsi +++ b/arch/arm/boot/dts/axp22x.dtsi @@ -141,6 +141,11 @@ regulator-max-microvolt = <3000000>; regulator-name = "rtc_ldo"; }; + + reg_drivevbus: drivevbus { + regulator-name = "drivevbus"; + status = "disabled"; + }; }; usb_power_supply: usb_power_supply { -- cgit v0.10.2 From 77b1be43da720ac8aadc982675519c677b2d624e Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Sat, 11 Jun 2016 15:53:04 +0200 Subject: ARM: dts: sun8i-a?3-q8-tablet.dts: Add full otg support Now that we've all the necessary bits in place we can enable full otg support on these tablets. Signed-off-by: Hans de Goede Signed-off-by: Maxime Ripard diff --git a/arch/arm/boot/dts/sun8i-a23-q8-tablet.dts b/arch/arm/boot/dts/sun8i-a23-q8-tablet.dts index 6062ea7..956320a 100644 --- a/arch/arm/boot/dts/sun8i-a23-q8-tablet.dts +++ b/arch/arm/boot/dts/sun8i-a23-q8-tablet.dts @@ -48,18 +48,3 @@ model = "Q8 A23 Tablet"; compatible = "allwinner,q8-a23", "allwinner,sun8i-a23"; }; - -/* - * FIXME for now we only support host mode and rely on u-boot to have - * turned on Vbus which is controlled by the axp223 pmic on the board. - * - * Once we have axp223 support we should switch to fully supporting otg. - */ -&usb_otg { - dr_mode = "host"; - status = "okay"; -}; - -&usbphy { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/sun8i-a33-q8-tablet.dts b/arch/arm/boot/dts/sun8i-a33-q8-tablet.dts index 44b3229..b0bc236 100644 --- a/arch/arm/boot/dts/sun8i-a33-q8-tablet.dts +++ b/arch/arm/boot/dts/sun8i-a33-q8-tablet.dts @@ -48,18 +48,3 @@ model = "Q8 A33 Tablet"; compatible = "allwinner,q8-a33", "allwinner,sun8i-a33"; }; - -/* - * FIXME for now we only support host mode and rely on u-boot to have - * turned on Vbus which is controlled by the axp223 pmic on the board. - * - * Once we have axp223 support we should switch to fully supporting otg. - */ -&usb_otg { - dr_mode = "host"; - status = "okay"; -}; - -&usbphy { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/sun8i-q8-common.dtsi b/arch/arm/boot/dts/sun8i-q8-common.dtsi index 346a49d..991087f 100644 --- a/arch/arm/boot/dts/sun8i-q8-common.dtsi +++ b/arch/arm/boot/dts/sun8i-q8-common.dtsi @@ -87,6 +87,13 @@ allwinner,drive = ; allwinner,pull = ; }; + + usb0_id_detect_pin: usb0_id_detect_pin@0 { + allwinner,pins = "PH8"; + allwinner,function = "gpio_in"; + allwinner,drive = ; + allwinner,pull = ; + }; }; &r_rsb { @@ -98,6 +105,7 @@ interrupt-parent = <&nmi_intc>; interrupts = <0 IRQ_TYPE_LEVEL_LOW>; eldoin-supply = <®_dcdc1>; + x-powers,drive-vbus-en; }; }; @@ -163,6 +171,11 @@ regulator-name = "vcc-dram"; }; +®_drivevbus { + regulator-name = "usb0-vbus"; + status = "okay"; +}; + ®_rtc_ldo { regulator-name = "vcc-rtc"; }; @@ -176,3 +189,21 @@ &simplefb_lcd { vcc-lcd-supply = <®_dc1sw>; }; + +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + +&usb_power_supply { + status = "okay"; +}; + +&usbphy { + pinctrl-names = "default"; + pinctrl-0 = <&usb0_id_detect_pin>; + usb0_id_det-gpio = <&pio 7 8 GPIO_ACTIVE_HIGH>; /* PH8 */ + usb0_vbus_power-supply = <&usb_power_supply>; + usb0_vbus-supply = <®_drivevbus>; + status = "okay"; +}; -- cgit v0.10.2 From 4e4cb0df58e376830645f37fa3fedc3dc4f9be17 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Sat, 11 Jun 2016 15:53:05 +0200 Subject: ARM: dts: sun8i-a23-polaroid-mid2809pxe04: Add full otg support Now that we've all the necessary bits in place we can enable full otg support on these tablets. Signed-off-by: Hans de Goede Signed-off-by: Maxime Ripard diff --git a/arch/arm/boot/dts/sun8i-a23-polaroid-mid2809pxe04.dts b/arch/arm/boot/dts/sun8i-a23-polaroid-mid2809pxe04.dts index cb5daaf..bae779f 100644 --- a/arch/arm/boot/dts/sun8i-a23-polaroid-mid2809pxe04.dts +++ b/arch/arm/boot/dts/sun8i-a23-polaroid-mid2809pxe04.dts @@ -131,6 +131,13 @@ allwinner,drive = ; allwinner,pull = ; }; + + usb0_id_detect_pin: usb0_id_detect_pin@0 { + allwinner,pins = "PH8"; + allwinner,function = "gpio_in"; + allwinner,drive = ; + allwinner,pull = ; + }; }; &pwm { @@ -148,6 +155,7 @@ interrupt-parent = <&nmi_intc>; interrupts = <0 IRQ_TYPE_LEVEL_LOW>; eldoin-supply = <®_dcdc1>; + x-powers,drive-vbus-en; }; }; @@ -219,6 +227,11 @@ regulator-name = "vcc-dram"; }; +®_drivevbus { + regulator-name = "usb0-vbus"; + status = "okay"; +}; + ®_rtc_ldo { regulator-name = "vcc-rtc"; }; @@ -227,17 +240,20 @@ vcc-lcd-supply = <®_dc1sw>; }; -/* - * FIXME for now we only support host mode and rely on u-boot to have - * turned on Vbus which is controlled by the axp223 pmic on the board. - * - * Once we have axp223 support we should switch to fully supporting otg. - */ &usb_otg { - dr_mode = "host"; + dr_mode = "otg"; + status = "okay"; +}; + +&usb_power_supply { status = "okay"; }; &usbphy { + pinctrl-names = "default"; + pinctrl-0 = <&usb0_id_detect_pin>; + usb0_id_det-gpio = <&pio 7 8 GPIO_ACTIVE_HIGH>; /* PH8 */ + usb0_vbus_power-supply = <&usb_power_supply>; + usb0_vbus-supply = <®_drivevbus>; status = "okay"; }; -- cgit v0.10.2 From b2face522994e1367ecf2763bd0451f55a4b5ec8 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Sat, 11 Jun 2016 15:53:06 +0200 Subject: ARM: dts: sun8i-a23-polaroid-mid2809pxe04: Disable ehci0 The Polaroid mid2809pxe04 tablet uses an sdio esp8089 wifi chip, so ehci0 is not used and should be disabled. Signed-off-by: Hans de Goede Signed-off-by: Maxime Ripard diff --git a/arch/arm/boot/dts/sun8i-a23-polaroid-mid2809pxe04.dts b/arch/arm/boot/dts/sun8i-a23-polaroid-mid2809pxe04.dts index bae779f..e8c3f21 100644 --- a/arch/arm/boot/dts/sun8i-a23-polaroid-mid2809pxe04.dts +++ b/arch/arm/boot/dts/sun8i-a23-polaroid-mid2809pxe04.dts @@ -72,10 +72,6 @@ }; }; -&ehci0 { - status = "okay"; -}; - &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins_a>; -- cgit v0.10.2 From d22d64a506d279f9706f23d3fe5de401b6725ebe Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Sun, 5 Jun 2016 14:23:11 +0200 Subject: ARM: dts: sun4i: The blue led on the Mele A1000 is a power led The blue led on the Mele A1000 is wired to light up as soon as the board has powered (it will be on while the gpio is still in input / floating mode), also its location on the top-set box clearly signals "power led". Until now we've been treating this as a generic usr function led, which means that when you plug power into the top-set box, the power-led lights and then turns off as soon as the kernel loads, which looks wrong. This renames the led from a1000:blue:usr to a1000:blue:pwr and marks it as default on, fixing this. Signed-off-by: Hans de Goede Signed-off-by: Maxime Ripard Acked-by: Chen-Yu Tsai diff --git a/arch/arm/boot/dts/sun4i-a10-a1000.dts b/arch/arm/boot/dts/sun4i-a10-a1000.dts index fa70b8f..39e368e 100644 --- a/arch/arm/boot/dts/sun4i-a10-a1000.dts +++ b/arch/arm/boot/dts/sun4i-a10-a1000.dts @@ -72,8 +72,9 @@ }; blue { - label = "a1000:blue:usr"; + label = "a1000:blue:pwr"; gpios = <&pio 7 20 GPIO_ACTIVE_HIGH>; + default-state = "on"; }; }; -- cgit v0.10.2 From a46579bfd990ad15d633543b21d650b21a6d200d Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Sun, 5 Jun 2016 14:23:12 +0200 Subject: ARM: dts: sun6i: The blue led on the Mele A1000G quad is a power led The blue led on the Mele A1000 is wired to light up as soon as the board has powered (it will be on while the gpio is still in input / floating mode), also its location on the top-set box clearly signals "power led". Until now we've been treating this as a generic usr function led, which means that when you plug power into the top-set box, the power-led lights and then turns off as soon as the kernel loads, which looks wrong. This renames the led from m9:blue:usr to a1000g:blue:pwr (fixing a copy and paste error in the prefix while at it) and marks it as default on, fixing this. Signed-off-by: Hans de Goede Signed-off-by: Maxime Ripard Acked-by: Chen-Yu Tsai diff --git a/arch/arm/boot/dts/sun6i-a31-mele-a1000g-quad.dts b/arch/arm/boot/dts/sun6i-a31-mele-a1000g-quad.dts index 4dd70cc..e063dab 100644 --- a/arch/arm/boot/dts/sun6i-a31-mele-a1000g-quad.dts +++ b/arch/arm/boot/dts/sun6i-a31-mele-a1000g-quad.dts @@ -65,8 +65,9 @@ pinctrl-0 = <&led_pins_m9>; blue { - label = "m9:blue:usr"; + label = "a1000g:blue:pwr"; gpios = <&pio 7 13 GPIO_ACTIVE_HIGH>; + default-state = "on"; }; }; }; -- cgit v0.10.2 From 3d9e2b66cf9f1b0eda3cb0891a775a625c14bb9f Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Sun, 5 Jun 2016 14:23:13 +0200 Subject: ARM: dts: sun6i: The blue led on the Mele M9 is a power led The blue led on the Mele M9 is wired to light up as soon as the board has powered (it will be on while the gpio is still in input / floating mode), also its location on the top-set box clearly signals "power led". Until now we've been treating this as a generic usr function led, which means that when you plug power into the top-set box, the power-led lights and then turns off as soon as the kernel loads, which looks wrong. This renames the led from m9:blue:usr to m9:blue:pwr and marks it as default on, fixing this. Signed-off-by: Hans de Goede Signed-off-by: Maxime Ripard Acked-by: Chen-Yu Tsai diff --git a/arch/arm/boot/dts/sun6i-a31-m9.dts b/arch/arm/boot/dts/sun6i-a31-m9.dts index 6e0e5687..66d29b8 100644 --- a/arch/arm/boot/dts/sun6i-a31-m9.dts +++ b/arch/arm/boot/dts/sun6i-a31-m9.dts @@ -65,8 +65,9 @@ pinctrl-0 = <&led_pins_m9>; blue { - label = "m9:blue:usr"; + label = "m9:blue:pwr"; gpios = <&pio 7 13 GPIO_ACTIVE_HIGH>; + default-state = "on"; }; }; }; -- cgit v0.10.2 From a4038fd09571a305a365303350678d5096e9f997 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Sun, 12 Jun 2016 13:07:00 +0200 Subject: ARM: dts: sun6i: Add pmic / regulator nodes to Mele A1000G quad dts Add pmic / regulator nodes to Mele A1000G quad dts. Note both reg_usb1_vbus and reg_dldo4 need to be on for the hub attached to usb1 to work, and we can list only one usb1_vbus-supply, so dldo4 is marked as regulator-always-on. Signed-off-by: Hans de Goede Signed-off-by: Maxime Ripard diff --git a/arch/arm/boot/dts/sun6i-a31-mele-a1000g-quad.dts b/arch/arm/boot/dts/sun6i-a31-mele-a1000g-quad.dts index e063dab..5faeae4 100644 --- a/arch/arm/boot/dts/sun6i-a31-mele-a1000g-quad.dts +++ b/arch/arm/boot/dts/sun6i-a31-mele-a1000g-quad.dts @@ -72,6 +72,10 @@ }; }; +&cpu0 { + cpu-supply = <®_dcdc3>; +}; + &ehci0 { status = "okay"; }; @@ -85,6 +89,7 @@ pinctrl-0 = <&gmac_pins_mii_a>; phy = <&phy1>; phy-mode = "mii"; + phy-supply = <®_dldo1>; status = "okay"; phy1: ethernet-phy@1 { @@ -101,13 +106,26 @@ &mmc0 { pinctrl-names = "default"; pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_m9>; - vmmc-supply = <®_vcc3v3>; + vmmc-supply = <®_dcdc1>; bus-width = <4>; cd-gpios = <&pio 7 22 GPIO_ACTIVE_HIGH>; /* PH22 */ cd-inverted; status = "okay"; }; +&p2wi { + status = "okay"; + + axp22x: pmic@68 { + compatible = "x-powers,axp221"; + reg = <0x68>; + interrupt-parent = <&nmi_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +#include "axp22x.dtsi" + &pio { led_pins_m9: led_pins@0 { allwinner,pins = "PH13"; @@ -131,6 +149,78 @@ }; }; +®_aldo1 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-wifi"; +}; + +®_aldo3 { + regulator-always-on; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3300000>; + regulator-name = "avcc"; +}; + +®_dc5ldo { + regulator-always-on; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1320000>; + regulator-name = "vdd-cpus"; /* This is an educated guess */ +}; + +®_dcdc1 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-3v3"; +}; + +®_dcdc2 { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1320000>; + regulator-name = "vdd-gpu"; +}; + +®_dcdc3 { + regulator-always-on; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1320000>; + regulator-name = "vdd-cpu"; +}; + +®_dcdc4 { + regulator-always-on; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1320000>; + regulator-name = "vdd-sys-dll"; +}; + +®_dcdc5 { + regulator-always-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-name = "vcc-dram"; +}; + +®_dldo1 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-ethernet-phy"; +}; + +/* + * Both reg_usb1_vbus and reg_dldo4 need to be on for the hub attached + * to usb1 to work, and we can list only one usb1_vbus-supply, so dldo4 is + * marked as regulator-always-on. + */ +®_dldo4 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-usb-hub"; +}; + ®_usb1_vbus { pinctrl-names = "default"; pinctrl-0 = <&usb1_vbus_pin_m9>; @@ -151,5 +241,6 @@ &usbphy { usb1_vbus-supply = <®_usb1_vbus>; + usb2_vbus-supply = <®_aldo1>; status = "okay"; }; -- cgit v0.10.2 From 11994511865823689c19560f035e462dda2cda96 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Sun, 12 Jun 2016 13:07:01 +0200 Subject: ARM: dts: sun6i: Add pmic / regulator nodes to Mele M9 dts Add pmic / regulator nodes to Mele M9 dts. Note both reg_usb1_vbus and reg_dldo4 need to be on for the hub attached to usb1 to work, and we can list only one usb1_vbus-supply, so dldo4 is marked as regulator-always-on. Signed-off-by: Hans de Goede Signed-off-by: Maxime Ripard diff --git a/arch/arm/boot/dts/sun6i-a31-m9.dts b/arch/arm/boot/dts/sun6i-a31-m9.dts index 66d29b8..29016a1 100644 --- a/arch/arm/boot/dts/sun6i-a31-m9.dts +++ b/arch/arm/boot/dts/sun6i-a31-m9.dts @@ -72,6 +72,10 @@ }; }; +&cpu0 { + cpu-supply = <®_dcdc3>; +}; + &ehci0 { status = "okay"; }; @@ -85,6 +89,7 @@ pinctrl-0 = <&gmac_pins_mii_a>; phy = <&phy1>; phy-mode = "mii"; + phy-supply = <®_dldo1>; status = "okay"; phy1: ethernet-phy@1 { @@ -101,13 +106,26 @@ &mmc0 { pinctrl-names = "default"; pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_m9>; - vmmc-supply = <®_vcc3v3>; + vmmc-supply = <®_dcdc1>; bus-width = <4>; cd-gpios = <&pio 7 22 GPIO_ACTIVE_HIGH>; /* PH22 */ cd-inverted; status = "okay"; }; +&p2wi { + status = "okay"; + + axp22x: pmic@68 { + compatible = "x-powers,axp221"; + reg = <0x68>; + interrupt-parent = <&nmi_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +#include "axp22x.dtsi" + &pio { led_pins_m9: led_pins@0 { allwinner,pins = "PH13"; @@ -131,6 +149,78 @@ }; }; +®_aldo1 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-wifi"; +}; + +®_aldo3 { + regulator-always-on; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3300000>; + regulator-name = "avcc"; +}; + +®_dc5ldo { + regulator-always-on; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1320000>; + regulator-name = "vdd-cpus"; /* This is an educated guess */ +}; + +®_dcdc1 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-3v3"; +}; + +®_dcdc2 { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1320000>; + regulator-name = "vdd-gpu"; +}; + +®_dcdc3 { + regulator-always-on; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1320000>; + regulator-name = "vdd-cpu"; +}; + +®_dcdc4 { + regulator-always-on; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1320000>; + regulator-name = "vdd-sys-dll"; +}; + +®_dcdc5 { + regulator-always-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-name = "vcc-dram"; +}; + +®_dldo1 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-ethernet-phy"; +}; + +/* + * Both reg_usb1_vbus and reg_dldo4 need to be on for the hub attached + * to usb1 to work, and we can list only one usb1_vbus-supply, so dldo4 is + * marked as regulator-always-on. + */ +®_dldo4 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-usb-hub"; +}; + ®_usb1_vbus { pinctrl-names = "default"; pinctrl-0 = <&usb1_vbus_pin_m9>; @@ -146,5 +236,6 @@ &usbphy { usb1_vbus-supply = <®_usb1_vbus>; + usb2_vbus-supply = <®_aldo1>; status = "okay"; }; -- cgit v0.10.2 From cefd486072a0b11cf8ab3577fb99e6ffc93b85fb Mon Sep 17 00:00:00 2001 From: Boris Brezillon Date: Tue, 14 Jun 2016 14:17:36 +0300 Subject: ARM: dts: sun4i: Add NFC node to Allwinner A10 SoC Add NAND Flash controller node definition to the A10 SoC. Signed-off-by: Boris Brezillon Signed-off-by: Aleksei Mamlin Signed-off-by: Maxime Ripard diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi index f1b75c8..7e7dfc2 100644 --- a/arch/arm/boot/dts/sun4i-a10.dtsi +++ b/arch/arm/boot/dts/sun4i-a10.dtsi @@ -721,6 +721,19 @@ #dma-cells = <2>; }; + nfc: nand@01c03000 { + compatible = "allwinner,sun4i-a10-nand"; + reg = <0x01c03000 0x1000>; + interrupts = <37>; + clocks = <&ahb_gates 13>, <&nand_clk>; + clock-names = "ahb", "mod"; + dmas = <&dma SUN4I_DMA_DEDICATED 3>; + dma-names = "rxtx"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + spi0: spi@01c05000 { compatible = "allwinner,sun4i-a10-spi"; reg = <0x01c05000 0x1000>; -- cgit v0.10.2 From b2a83ad217b8ca24e67b5c4e02de2ab3938eb01e Mon Sep 17 00:00:00 2001 From: Boris Brezillon Date: Tue, 14 Jun 2016 14:17:38 +0300 Subject: ARM: dts: sun7i: Add NFC node to Allwinner A20 SoC Add NAND Flash controller node definition to the A20 SoC. Signed-off-by: Boris Brezillon Signed-off-by: Aleksei Mamlin Signed-off-by: Maxime Ripard diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index e1adae7..1146197 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -802,6 +802,19 @@ #dma-cells = <2>; }; + nfc: nand@01c03000 { + compatible = "allwinner,sun4i-a10-nand"; + reg = <0x01c03000 0x1000>; + interrupts = ; + clocks = <&ahb_gates 13>, <&nand_clk>; + clock-names = "ahb", "mod"; + dmas = <&dma SUN4I_DMA_DEDICATED 3>; + dma-names = "rxtx"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + spi0: spi@01c05000 { compatible = "allwinner,sun4i-a10-spi"; reg = <0x01c05000 0x1000>; -- cgit v0.10.2 From 08ff3e4ef0f839994ec10da47819989c01596462 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Wed, 15 Jun 2016 18:27:45 +0800 Subject: ARM: dts: sun9i: cubieboard4: Order nodes by alphabetical order Move the &pio node below the mmc nodes for proper ordering by name. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard diff --git a/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts b/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts index db770d0..1526b41 100644 --- a/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts +++ b/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts @@ -78,22 +78,6 @@ }; }; -&pio { - led_pins_cubieboard4: led-pins@0 { - allwinner,pins = "PH6", "PH17"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; - - mmc0_cd_pin_cubieboard4: mmc0_cd_pin@0 { - allwinner,pins = "PH18"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; -}; - &mmc0 { pinctrl-names = "default"; pinctrl-0 = <&mmc0_pins>, <&mmc0_cd_pin_cubieboard4>; @@ -119,6 +103,22 @@ allwinner,drive = ; }; +&pio { + led_pins_cubieboard4: led-pins@0 { + allwinner,pins = "PH6", "PH17"; + allwinner,function = "gpio_out"; + allwinner,drive = ; + allwinner,pull = ; + }; + + mmc0_cd_pin_cubieboard4: mmc0_cd_pin@0 { + allwinner,pins = "PH18"; + allwinner,function = "gpio_in"; + allwinner,drive = ; + allwinner,pull = ; + }; +}; + &r_ir { status = "okay"; }; -- cgit v0.10.2 From 659757c20d58fb876b8e9ef56c10b9b8b7beba00 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Wed, 15 Jun 2016 18:27:46 +0800 Subject: ARM: dts: sun9i: a80-optimus: Order nodes by alphabetical order Move the mmc nodes above the ohci nodes for proper ordering by name. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard diff --git a/arch/arm/boot/dts/sun9i-a80-optimus.dts b/arch/arm/boot/dts/sun9i-a80-optimus.dts index 78fddd9..7fd22e8 100644 --- a/arch/arm/boot/dts/sun9i-a80-optimus.dts +++ b/arch/arm/boot/dts/sun9i-a80-optimus.dts @@ -119,6 +119,31 @@ status = "okay"; }; +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins>, <&mmc0_cd_pin_optimus>; + vmmc-supply = <®_dcdc1>; + bus-width = <4>; + cd-gpios = <&pio 7 18 GPIO_ACTIVE_HIGH>; /* PH8 */ + cd-inverted; + status = "okay"; +}; + +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_8bit_pins>; + vmmc-supply = <®_dcdc1>; + bus-width = <8>; + non-removable; + cap-mmc-hw-reset; + status = "okay"; +}; + +&mmc2_8bit_pins { + /* Increase drive strength for DDR modes */ + allwinner,drive = ; +}; + &ohci0 { status = "okay"; }; @@ -157,31 +182,6 @@ }; }; -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>, <&mmc0_cd_pin_optimus>; - vmmc-supply = <®_dcdc1>; - bus-width = <4>; - cd-gpios = <&pio 7 18 GPIO_ACTIVE_HIGH>; /* PH8 */ - cd-inverted; - status = "okay"; -}; - -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_8bit_pins>; - vmmc-supply = <®_dcdc1>; - bus-width = <8>; - non-removable; - cap-mmc-hw-reset; - status = "okay"; -}; - -&mmc2_8bit_pins { - /* Increase drive strength for DDR modes */ - allwinner,drive = ; -}; - &r_ir { status = "okay"; }; -- cgit v0.10.2 From 1cdc0aa5aaf995a571550cbf8d57ae9e1454a141 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Wed, 15 Jun 2016 20:23:50 +0200 Subject: ARM: dts: sun8i-q8-common: Add support for USB wifi controllers Some of the sun8i q8 boards have an usb wifi controller, on other variants this will result in an used usb root-hub, but the best way to deal with wifi on this boards is to simply let the kernel auto-detect usb or sdio wifi controllers. This has been tested on an a23 based q8 tablet with a RTL8188ETV wifi controller. Signed-off-by: Hans de Goede Signed-off-by: Maxime Ripard diff --git a/arch/arm/boot/dts/sun8i-q8-common.dtsi b/arch/arm/boot/dts/sun8i-q8-common.dtsi index 991087f..f3f4ce0 100644 --- a/arch/arm/boot/dts/sun8i-q8-common.dtsi +++ b/arch/arm/boot/dts/sun8i-q8-common.dtsi @@ -63,6 +63,10 @@ }; }; +&ehci0 { + status = "okay"; +}; + &mmc0 { pinctrl-names = "default"; pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_q8>; @@ -171,6 +175,12 @@ regulator-name = "vcc-dram"; }; +®_dldo1 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-wifi"; +}; + ®_drivevbus { regulator-name = "usb0-vbus"; status = "okay"; @@ -205,5 +215,6 @@ usb0_id_det-gpio = <&pio 7 8 GPIO_ACTIVE_HIGH>; /* PH8 */ usb0_vbus_power-supply = <&usb_power_supply>; usb0_vbus-supply = <®_drivevbus>; + usb1_vbus-supply = <®_dldo1>; status = "okay"; }; -- cgit v0.10.2 From 04c85ecad32a28c4afde7e088237075ab6aec0be Mon Sep 17 00:00:00 2001 From: Luo Yi Date: Fri, 17 Jun 2016 17:56:02 +0800 Subject: ARM: dts: sun7i: Add dts file for Bananapi M1 Plus board Add support for the Bananapi M1 Plus A20 development board from sinovoip.com.cn . This board is nearly a clone of the Lemaker's Bananapro, but differ with the wlan chipset connection and i2s pinout. And I also enable the integrated audio codec on default. Signed-off-by: Maxime Ripard diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 970e906..3fde2eb 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -728,6 +728,7 @@ dtb-$(CONFIG_MACH_SUN6I) += \ sun6i-a31s-yones-toptech-bs1078-v2.dtb dtb-$(CONFIG_MACH_SUN7I) += \ sun7i-a20-bananapi.dtb \ + sun7i-a20-bananapi-m1-plus.dtb \ sun7i-a20-bananapro.dtb \ sun7i-a20-cubieboard2.dtb \ sun7i-a20-cubietruck.dtb \ diff --git a/arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts b/arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts new file mode 100644 index 0000000..89e38e9 --- /dev/null +++ b/arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts @@ -0,0 +1,230 @@ +/* + * Copyright 2016 Luo Yi + * + * Thanks to the original work by Hans de Goede + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun7i-a20.dtsi" +#include "sunxi-common-regulators.dtsi" +#include +#include + +/ { + model = "Banana Pi BPI-M1-Plus"; + compatible = "sinovoip,bpi-m1-plus", "allwinner,sun7i-a20"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pins_bananapi>; + + green { + label = "bananapi-m1-plus:green:usr"; + gpios = <&pio 7 24 GPIO_ACTIVE_HIGH>; + }; + + red { + label = "bananapi-m1-plus:red:usr"; + gpios = <&pio 7 25 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + }; + + }; + + mmc3_pwrseq: mmc3_pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc3_pwrseq_pin_bananapim1plus>; + reset-gpios = <&pio 7 22 GPIO_ACTIVE_LOW>; /* PH22 WL-PMU-EN */ + }; + + reg_gmac_3v3: gmac-3v3 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&gmac_power_pin_bananapi>; + regulator-name = "gmac-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <100000>; + enable-active-high; + gpio = <&pio 7 23 GPIO_ACTIVE_HIGH>; + }; +}; + +&ahci { + status = "okay"; +}; + +&codec { + status = "okay"; +}; + +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&gmac { + pinctrl-names = "default"; + pinctrl-0 = <&gmac_pins_rgmii_a>; + phy = <&phy1>; + phy-mode = "rgmii"; + phy-supply = <®_gmac_3v3>; + status = "okay"; + + phy1: ethernet-phy@1 { + reg = <1>; + }; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "okay"; + + axp209: pmic@34 { + compatible = "x-powers,axp209"; + reg = <0x34>; + interrupt-parent = <&nmi_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + + interrupt-controller; + #interrupt-cells = <1>; + }; +}; + +&ir0 { + pinctrl-names = "default"; + pinctrl-0 = <&ir0_rx_pins_a>; + status = "okay"; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_bananapi>; + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 7 10 GPIO_ACTIVE_HIGH>; /* PH10 */ + cd-inverted; + status = "okay"; +}; + +&mmc3 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&mmc3_pins_a>; + vmmc-supply = <®_vcc3v3>; + mmc-pwrseq = <&mmc3_pwrseq>; + bus-width = <4>; + non-removable; + enable-sdio-wakeup; + status = "okay"; + + brcmf: bcrmf@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + interrupt-parent = <&pio>; + interrupts = <7 15 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "host-wake"; + }; +}; + +&mmc3_pins_a { + /* AP6210 requires pull-up */ + allwinner,pull = ; +}; + +&ohci0 { + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&pio { + gmac_power_pin_bananapi: gmac_power_pin@0 { + allwinner,pins = "PH23"; + allwinner,function = "gpio_out"; + allwinner,drive = ; + allwinner,pull = ; + }; + + led_pins_bananapi: led_pins@0 { + allwinner,pins = "PH24", "PG2"; + allwinner,function = "gpio_out"; + allwinner,drive = ; + allwinner,pull = ; + }; + + mmc0_cd_pin_bananapi: mmc0_cd_pin@0 { + allwinner,pins = "PH10"; + allwinner,function = "gpio_in"; + allwinner,drive = ; + allwinner,pull = ; + }; + + mmc3_pwrseq_pin_bananapim1plus: mmc3_pwrseq_pin@0 { + allwinner,pins = "PH22"; + allwinner,function = "gpio_out"; + allwinner,drive = ; + allwinner,pull = ; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; +}; -- cgit v0.10.2 From 3463f32f4c5670f2aeb5c05b01b8a466fc3b8836 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Thu, 23 Jun 2016 17:29:15 +0800 Subject: ARM: dts: sun5i: q8-common: Enable USB-based WiFi The early A13 Q8 tablets all use a Realtek WiFi module connected to USB1. The module is powered by AXP209's LDO3 at 3.3V. Move the related settings from sun5i-a13-q8-tablet.dts to sun5i-q8-common.dtsi, for all q8-based tablets. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard diff --git a/arch/arm/boot/dts/sun5i-a13-q8-tablet.dts b/arch/arm/boot/dts/sun5i-a13-q8-tablet.dts index 72e93ac..dce7782 100644 --- a/arch/arm/boot/dts/sun5i-a13-q8-tablet.dts +++ b/arch/arm/boot/dts/sun5i-a13-q8-tablet.dts @@ -48,13 +48,3 @@ model = "Q8 A13 Tablet"; compatible = "allwinner,q8-a13", "allwinner,sun5i-a13"; }; - -®_ldo3 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi"; -}; - -&usbphy { - usb1_vbus-supply = <®_ldo3>; -}; diff --git a/arch/arm/boot/dts/sun5i-q8-common.dtsi b/arch/arm/boot/dts/sun5i-q8-common.dtsi index b6af9a4..a5de28d 100644 --- a/arch/arm/boot/dts/sun5i-q8-common.dtsi +++ b/arch/arm/boot/dts/sun5i-q8-common.dtsi @@ -191,6 +191,12 @@ regulator-name = "avcc"; }; +®_ldo3 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-wifi"; +}; + ®_usb0_vbus { gpio = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */ status = "okay"; @@ -231,5 +237,6 @@ usb0_vbus_det-gpio = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */ usb0_vbus_power-supply = <&usb_power_supply>; usb0_vbus-supply = <®_usb0_vbus>; + usb1_vbus-supply = <®_ldo3>; status = "okay"; }; -- cgit v0.10.2 From 29bc949088a6bdb97bbd112a0d463d00898f2641 Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Fri, 24 Jun 2016 12:10:01 +0200 Subject: ARM: sun8i: Add Parrot Board DTS The Parrot Board is an evaluation board with an Allwinner R16 (assumed to be close to an Allwinner A33), 4GB of eMMC, 512MB of RAM, USB host and OTG, a WiFi/Bluetooth combo chip, a micro SD Card reader, 2 controllable buttons, an LVDS port with separated backlight and capacitive touch panel ports, an audio/microphone jack, a camera CSI port, 2 sets of 22 GPIOs and an accelerometer. Signed-off-by: Quentin Schulz Acked-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 3fde2eb..016611d 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -767,7 +767,8 @@ dtb-$(CONFIG_MACH_SUN8I) += \ sun8i-h3-orangepi-one.dtb \ sun8i-h3-orangepi-pc.dtb \ sun8i-h3-orangepi-plus.dtb \ - sun8i-h3-sinovoip-bpi-m2-plus.dtb + sun8i-h3-sinovoip-bpi-m2-plus.dtb \ + sun8i-r16-parrot.dtb dtb-$(CONFIG_MACH_SUN9I) += \ sun9i-a80-optimus.dtb \ sun9i-a80-cubieboard4.dtb diff --git a/arch/arm/boot/dts/sun8i-r16-parrot.dts b/arch/arm/boot/dts/sun8i-r16-parrot.dts new file mode 100644 index 0000000..47553e5 --- /dev/null +++ b/arch/arm/boot/dts/sun8i-r16-parrot.dts @@ -0,0 +1,351 @@ +/* + * Copyright 2016 Quentin Schulz + * + * Quentin Schulz + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun8i-a33.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include +#include + +/ { + model = "Allwinner R16 EVB (Parrot)"; + compatible = "allwinner,parrot", "allwinner,sun8i-a33"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pins_parrot>; + + led1 { + label = "parrot:led1:usr"; + gpio = <&pio 4 17 GPIO_ACTIVE_HIGH>; /* PE17 */ + }; + + led2 { + label = "parrot:led2:usr"; + gpio = <&pio 4 16 GPIO_ACTIVE_HIGH>; /* PE16 */ + }; + }; + + wifi_pwrseq: wifi_pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&r_pio 0 6 GPIO_ACTIVE_LOW>; /* PL06 */ + }; + +}; + +&ehci0 { + status = "okay"; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins_a>; + status = "okay"; + + /* + * FIXME: An as-yet-unknown accelerometer is connected to this + * i2c bus. + */ +}; + +&lradc { + vref-supply = <®_aldo3>; + status = "okay"; + + button@0 { + label = "V+"; + linux,code = ; + channel = <0>; + voltage = <190000>; + }; + + button@1 { + label = "V-"; + linux,code = ; + channel = <0>; + voltage = <390000>; + }; + +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_parrot>; + vmmc-supply = <®_dcdc1>; + cd-gpios = <&pio 3 14 GPIO_ACTIVE_LOW>; /* PD14 */ + bus-width = <4>; + status = "okay"; +}; + +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins_a>, <&wifi_reset_pin_parrot>; + vmmc-supply = <®_aldo1>; + mmc-pwrseq = <&wifi_pwrseq>; + bus-width = <4>; + non-removable; + status = "okay"; +}; + +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_8bit_pins>; + vmmc-supply = <®_dcdc1>; + bus-width = <8>; + non-removable; + cap-mmc-hw-reset; + status = "okay"; +}; + +&mmc2_8bit_pins { + allwinner,drive = ; + allwinner,pull = ; +}; + +&ohci0 { + status = "okay"; +}; + +&pio { + mmc0_cd_pin_parrot: mmc0_cd_pin@0 { + allwinner,pins = "PD14"; + allwinner,function = "gpio_in"; + allwinner,drive = ; + allwinner,pull = ; + }; + + led_pins_parrot: led_pins@0 { + allwinner,pins = "PE16", "PE17"; + allwinner,function = "gpio_out"; + allwinner,drive = ; + allwinner,pull = ; + }; + + usb0_id_det: usb0_id_detect_pin@0 { + allwinner,pins = "PD10"; + allwinner,function = "gpio_in"; + allwinner,drive = ; + allwinner,pull = ; + }; + + usb1_vbus_pin_parrot: usb1_vbus_pin@0 { + allwinner,pins = "PD12"; + allwinner,function = "gpio_out"; + allwinner,drive = ; + allwinner,pull = ; + }; +}; + +&r_pio { + wifi_reset_pin_parrot: wifi_reset_pin@0 { + allwinner,pins = "PL6"; + allwinner,function = "gpio_out"; + allwinner,drive = ; + allwinner,pull = ; + }; +}; + +&r_rsb { + status = "okay"; + + axp22x: pmic@3a3 { + compatible = "x-powers,axp223"; + reg = <0x3a3>; + interrupt-parent = <&nmi_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + drivevbus-supply = <®_vcc5v0>; + x-powers,drive-vbus-en; + }; +}; + +#include "axp22x.dtsi" + +®_aldo1 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc-io"; +}; + +®_aldo2 { + regulator-always-on; + regulator-min-microvolt = <2350000>; + regulator-max-microvolt = <2650000>; + regulator-name = "vdd-dll"; +}; + +®_aldo3 { + regulator-always-on; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-pll-avcc"; +}; + +®_dc5ldo { + regulator-always-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-cpus"; +}; + +®_dcdc1 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc-3v0"; +}; + +®_dcdc2 { + regulator-always-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-sys"; +}; + +®_dcdc3 { + regulator-always-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-cpu"; +}; + +®_dcdc5 { + regulator-always-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-name = "vcc-dram"; +}; + +®_dldo1 { + /* + * TODO: WiFi chip needs dldo1 AND dldo2 to be on to be powered. + * Remove next line once it is possible to sync two regulators. + */ + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-wifi0"; +}; + +®_dldo2 { + /* + * TODO: WiFi chip needs dldo1 AND dldo2 to be on to be powered. + * Remove next line once it is possible to sync two regulators. + */ + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-wifi1"; +}; + +®_dldo3 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc-3v0-csi"; +}; + +®_drivevbus { + regulator-name = "usb0-vbus"; + status = "okay"; +}; + +®_eldo1 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-name = "vcc-1v2-hsic"; +}; + +®_eldo2 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc-dsp"; +}; + +®_eldo3 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "eldo3"; +}; + +®_usb1_vbus { + pinctrl-names = "default"; + pinctrl-0 = <&usb1_vbus_pin_parrot>; + gpio = <&pio 3 12 GPIO_ACTIVE_HIGH>; /* PD12 */ + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_b>; + status = "okay"; +}; + +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + +&usb_power_supply { + status = "okay"; +}; + +&usbphy { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&usb0_id_det>; + usb0_vbus-supply = <®_drivevbus>; + usb0_id_det-gpios = <&pio 3 10 GPIO_ACTIVE_HIGH>; /* PD10 */ + usb0_vbus_power-supply = <&usb_power_supply>; + usb1_vbus-supply = <®_usb1_vbus>; +}; -- cgit v0.10.2 From d7b9eaff5f0ca00726336b4c0c3c29decf30412a Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Mon, 27 Jun 2016 17:45:56 -0700 Subject: ARM: dts: sun7i: Add BCM53125 switch nodes to the lamobo-r1 board Now that we have a proper binding for Ethernet switches hanging off different buses, and a driver for the BCM53125 switch, add its Device Tree as a child MDIO node, at MDIO address 30 (Broadcom pseudo-PHY address) and describe the ports layout of the Lamobo R1 board. Signed-off-by: Florian Fainelli Acked-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard diff --git a/arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts b/arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts index 5ee43d8..fbca934 100644 --- a/arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts +++ b/arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts @@ -110,13 +110,67 @@ &gmac { pinctrl-names = "default"; pinctrl-0 = <&gmac_pins_rgmii_a>; - phy = <&phy1>; phy-mode = "rgmii"; phy-supply = <®_gmac_3v3>; status = "okay"; - phy1: ethernet-phy@1 { - reg = <1>; + fixed-link { + speed = <1000>; + full-duplex; + }; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + switch: ethernet-switch@1e { + compatible = "brcm,bcm53125"; + reg = <30>; + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port0: port@0 { + reg = <0>; + label = "lan2"; + }; + + port1: port@1 { + reg = <1>; + label = "lan3"; + }; + + port2: port@2 { + reg = <2>; + label = "lan4"; + }; + + port3: port@3 { + reg = <3>; + label = "wan"; + }; + + port4: port@4 { + reg = <4>; + label = "lan1"; + }; + + port8: port@8 { + reg = <8>; + label = "cpu"; + ethernet = <&gmac>; + phy-mode = "rgmii"; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; + }; }; }; -- cgit v0.10.2 From ba40e221de17a45c7f5f91b552e03af72d163e0e Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Wed, 29 Jun 2016 20:47:00 +0200 Subject: ARM: dts: sun5i: Enable otg on the mk802 Enable the otg controller, the id pin is not connected so enable it in peripheral only mode. Signed-off-by: Hans de Goede Signed-off-by: Maxime Ripard diff --git a/arch/arm/boot/dts/sun5i-a10s-mk802.dts b/arch/arm/boot/dts/sun5i-a10s-mk802.dts index 46ff940..0bb5755 100644 --- a/arch/arm/boot/dts/sun5i-a10s-mk802.dts +++ b/arch/arm/boot/dts/sun5i-a10s-mk802.dts @@ -87,6 +87,10 @@ status = "okay"; }; +&otg_sram { + status = "okay"; +}; + &pio { led_pins_mk802: led_pins@0 { allwinner,pins = "PB2"; @@ -122,6 +126,11 @@ status = "okay"; }; +&usb_otg { + dr_mode = "peripheral"; + status = "okay"; +}; + &usbphy { usb1_vbus-supply = <®_usb1_vbus>; status = "okay"; -- cgit v0.10.2 From afdfcf7c815207d11d4e84ab14f0c1c754493da0 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Wed, 29 Jun 2016 20:47:01 +0200 Subject: ARM: dts: sun5i: Add axp152 pmic node to mk802 Add a node describing the axp152 pmic to the mk802 dts, note there are no regulator nodes as we do not yet support the regulators on the axp152. Signed-off-by: Hans de Goede Signed-off-by: Maxime Ripard diff --git a/arch/arm/boot/dts/sun5i-a10s-mk802.dts b/arch/arm/boot/dts/sun5i-a10s-mk802.dts index 0bb5755..04120e1 100644 --- a/arch/arm/boot/dts/sun5i-a10s-mk802.dts +++ b/arch/arm/boot/dts/sun5i-a10s-mk802.dts @@ -73,6 +73,20 @@ status = "okay"; }; +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "okay"; + + axp152: pmic@30 { + compatible = "x-powers,axp152"; + reg = <0x30>; + interrupts = <0>; + interrupt-controller; + #interrupt-cells = <1>; + }; +}; + &mmc0 { pinctrl-names = "default"; pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_mk802>; -- cgit v0.10.2 From e6495c86a3e7aca844d03a6ec369fcf210122d73 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Wed, 29 Jun 2016 20:47:02 +0200 Subject: ARM: dts: sun5i: Add mmc1 / sdio-wifi node to mk802 The a10s mk802 uses a rtl8189es sdio wifi chip, add a node enabling the mmc1 controller, this enables using the wifi chip (together with an out of tree sdio driver for it). Signed-off-by: Hans de Goede Signed-off-by: Maxime Ripard diff --git a/arch/arm/boot/dts/sun5i-a10s-mk802.dts b/arch/arm/boot/dts/sun5i-a10s-mk802.dts index 04120e1..c84ac00 100644 --- a/arch/arm/boot/dts/sun5i-a10s-mk802.dts +++ b/arch/arm/boot/dts/sun5i-a10s-mk802.dts @@ -97,6 +97,15 @@ status = "okay"; }; +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins_a>; + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + non-removable; + status = "okay"; +}; + &ohci0 { status = "okay"; }; -- cgit v0.10.2 From 60ecb1ef1ee70f4190302cefd41262dc34f493d8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Emilio=20L=C3=B3pez?= Date: Fri, 18 Jul 2014 15:26:08 -0300 Subject: ARM: sun7i: Add mod1 clock nodes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This commit adds all the mod1 clocks available on A20 to its device tree. This list was created by looking at the A20 user manual. Signed-off-by: Emilio López Signed-off-by: Maxime Ripard diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index 1146197..7b253e5 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -371,9 +371,9 @@ <5>, <6>, <7>, <8>, <10>; clock-output-names = "apb0_codec", "apb0_spdif", - "apb0_ac97", "apb0_iis0", "apb0_iis1", + "apb0_ac97", "apb0_i2s0", "apb0_i2s1", "apb0_pio", "apb0_ir0", "apb0_ir1", - "apb0_iis2", "apb0_keypad"; + "apb0_i2s2", "apb0_keypad"; }; apb1: clk@01c20058 { @@ -523,6 +523,28 @@ clock-output-names = "ir1"; }; + i2s0_clk: clk@01c200b8 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-mod1-clk"; + reg = <0x01c200b8 0x4>; + clocks = <&pll2 SUN4I_A10_PLL2_8X>, + <&pll2 SUN4I_A10_PLL2_4X>, + <&pll2 SUN4I_A10_PLL2_2X>, + <&pll2 SUN4I_A10_PLL2_1X>; + clock-output-names = "i2s0"; + }; + + ac97_clk: clk@01c200bc { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-mod1-clk"; + reg = <0x01c200bc 0x4>; + clocks = <&pll2 SUN4I_A10_PLL2_8X>, + <&pll2 SUN4I_A10_PLL2_4X>, + <&pll2 SUN4I_A10_PLL2_2X>, + <&pll2 SUN4I_A10_PLL2_1X>; + clock-output-names = "ac97"; + }; + spdif_clk: clk@01c200c0 { #clock-cells = <0>; compatible = "allwinner,sun4i-a10-mod1-clk"; @@ -560,6 +582,28 @@ clock-output-names = "spi3"; }; + i2s1_clk: clk@01c200d8 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-mod1-clk"; + reg = <0x01c200d8 0x4>; + clocks = <&pll2 SUN4I_A10_PLL2_8X>, + <&pll2 SUN4I_A10_PLL2_4X>, + <&pll2 SUN4I_A10_PLL2_2X>, + <&pll2 SUN4I_A10_PLL2_1X>; + clock-output-names = "i2s1"; + }; + + i2s2_clk: clk@01c200dc { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-mod1-clk"; + reg = <0x01c200dc 0x4>; + clocks = <&pll2 SUN4I_A10_PLL2_8X>, + <&pll2 SUN4I_A10_PLL2_4X>, + <&pll2 SUN4I_A10_PLL2_2X>, + <&pll2 SUN4I_A10_PLL2_1X>; + clock-output-names = "i2s2"; + }; + dram_gates: clk@01c20100 { #clock-cells = <1>; compatible = "allwinner,sun4i-a10-dram-gates-clk"; -- cgit v0.10.2 From 6a706356b4456204fd89ef3fbfc6ed4165cebf37 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Sat, 19 Sep 2015 16:48:00 +0200 Subject: ARM: sun7i: Add DAI nodes Add the new DAI blocks to the device tree. Signed-off-by: Maxime Ripard diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index 7b253e5..bd0c476 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -1453,6 +1453,32 @@ status = "disabled"; }; + i2s1: i2s@01c22000 { + #sound-dai-cells = <0>; + compatible = "allwinner,sun4i-a10-i2s"; + reg = <0x01c22000 0x400>; + interrupts = ; + clocks = <&apb0_gates 4>, <&i2s1_clk>; + clock-names = "apb", "mod"; + dmas = <&dma SUN4I_DMA_NORMAL 4>, + <&dma SUN4I_DMA_NORMAL 4>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + i2s0: i2s@01c22400 { + #sound-dai-cells = <0>; + compatible = "allwinner,sun4i-a10-i2s"; + reg = <0x01c22400 0x400>; + interrupts = ; + clocks = <&apb0_gates 3>, <&i2s0_clk>; + clock-names = "apb", "mod"; + dmas = <&dma SUN4I_DMA_NORMAL 3>, + <&dma SUN4I_DMA_NORMAL 3>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + lradc: lradc@01c22800 { compatible = "allwinner,sun4i-a10-lradc-keys"; reg = <0x01c22800 0x100>; @@ -1478,6 +1504,19 @@ reg = <0x01c23800 0x200>; }; + i2s2: i2s@01c24400 { + #sound-dai-cells = <0>; + compatible = "allwinner,sun4i-a10-i2s"; + reg = <0x01c24400 0x400>; + interrupts = ; + clocks = <&apb0_gates 8>, <&i2s2_clk>; + clock-names = "apb", "mod"; + dmas = <&dma SUN4I_DMA_NORMAL 6>, + <&dma SUN4I_DMA_NORMAL 6>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + rtp: rtp@01c25000 { compatible = "allwinner,sun5i-a13-ts"; reg = <0x01c25000 0x100>; -- cgit v0.10.2 From 73ba3a1c64a4c5a1a4b87c773714814eecb84877 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Wed, 22 Jun 2016 11:15:55 +0200 Subject: ARM: sun5i: Allow PLL3 2x fixed factor clock to change PLL3 rate In order to be able to properly generate its pixel clock, the pll3-2x fixed factor needs to be able to change the PLL3 rate too. Add the needed extra compatible so that it behaves that way. Signed-off-by: Maxime Ripard diff --git a/arch/arm/boot/dts/sun5i.dtsi b/arch/arm/boot/dts/sun5i.dtsi index 0840612..e374f4f 100644 --- a/arch/arm/boot/dts/sun5i.dtsi +++ b/arch/arm/boot/dts/sun5i.dtsi @@ -130,7 +130,7 @@ }; pll3x2: pll3x2_clk { - compatible = "fixed-factor-clock"; + compatible = "allwinner,sun4i-a10-pll3-2x-clk", "fixed-factor-clock"; #clock-cells = <0>; clock-div = <1>; clock-mult = <2>; -- cgit v0.10.2 From d509e205d81f074a9b8d93ac80ab56405dede48b Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Wed, 29 Jun 2016 20:46:59 +0200 Subject: ARM: dts: sun5i: Enable otg on the auxtex t004 The auxtek t004 has its otg usb vbus hardwired to 5v (likely in case people use it to power the board instead of the dedicated power micro usb connector), it does have an id pin, so it allows full otg functionality. Signed-off-by: Hans de Goede Signed-off-by: Maxime Ripard diff --git a/arch/arm/boot/dts/sun5i-a10s-auxtek-t004.dts b/arch/arm/boot/dts/sun5i-a10s-auxtek-t004.dts index a790ec8..2150e15 100644 --- a/arch/arm/boot/dts/sun5i-a10s-auxtek-t004.dts +++ b/arch/arm/boot/dts/sun5i-a10s-auxtek-t004.dts @@ -124,7 +124,18 @@ status = "okay"; }; +&otg_sram { + status = "okay"; +}; + &pio { + usb0_id_detect_pin: usb0_id_detect_pin@0 { + allwinner,pins = "PG12"; + allwinner,function = "gpio_in"; + allwinner,drive = ; + allwinner,pull = ; + }; + mmc0_cd_pin_t004: mmc0_cd_pin@0 { allwinner,pins = "PG1"; allwinner,function = "gpio_in"; @@ -158,11 +169,19 @@ status = "okay"; }; +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + &usb1_vbus_pin_a { allwinner,pins = "PG13"; }; &usbphy { + pinctrl-names = "default"; + pinctrl-0 = <&usb0_id_detect_pin>; + usb0_id_det-gpio = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */ usb1_vbus-supply = <®_usb1_vbus>; status = "okay"; }; -- cgit v0.10.2 From fd048c6b34458cd74f17ea269a18d65804692638 Mon Sep 17 00:00:00 2001 From: Raveendra Padasalagi Date: Tue, 28 Jun 2016 13:10:36 +0530 Subject: ARM: dts: Cygnus: Add Broadcom iproc-static-adc DT node This patch adds the DT node for Broadcom's iproc-static-adc controller driver. Signed-off-by: Raveendra Padasalagi Reviewed-by: Ray Jui Reviewed-by: Scott Branden Signed-off-by: Florian Fainelli diff --git a/arch/arm/boot/dts/bcm-cygnus.dtsi b/arch/arm/boot/dts/bcm-cygnus.dtsi index b42fe55..fabc9f3 100644 --- a/arch/arm/boot/dts/bcm-cygnus.dtsi +++ b/arch/arm/boot/dts/bcm-cygnus.dtsi @@ -366,5 +366,16 @@ interrupts = ; status = "disabled"; }; + + adc: adc@180a6000 { + compatible = "brcm,iproc-static-adc"; + #io-channel-cells = <1>; + io-channel-ranges; + adc-syscon = <&ts_adc_syscon>; + clocks = <&asiu_clks BCM_CYGNUS_ASIU_ADC_CLK>; + clock-names = "tsc_clk"; + interrupts = ; + status = "disabled"; + }; }; }; -- cgit v0.10.2 From 747a1af0bb0ed7d1926463d64ee5209206e9e88b Mon Sep 17 00:00:00 2001 From: Jiancheng Xue Date: Wed, 15 Jun 2016 10:19:07 +0800 Subject: ARM: dts: add dts files for Hi3519 and tidy up the makefile entries - add dts files for Hi3519 - shuffle ARCH_HIGHBANK, ARCH_HISI, ARCH_HIX5HD2 and ARCH_HIP0X around to keep the list sorted Signed-off-by: Jiancheng Xue Signed-off-by: Wei Xu diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 06b6c2d..23f1638 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -146,8 +146,6 @@ dtb-$(CONFIG_ARCH_EXYNOS5) += \ exynos5800-peach-pi.dtb dtb-$(CONFIG_ARCH_HI3xxx) += \ hi3620-hi4511.dtb -dtb-$(CONFIG_ARCH_HIX5HD2) += \ - hisi-x5hd2-dkb.dtb dtb-$(CONFIG_ARCH_HIGHBANK) += \ highbank.dtb \ ecx-2000.dtb @@ -155,6 +153,10 @@ dtb-$(CONFIG_ARCH_HIP01) += \ hip01-ca9x2.dtb dtb-$(CONFIG_ARCH_HIP04) += \ hip04-d01.dtb +dtb-$(CONFIG_ARCH_HISI) += \ + hi3519-demb.dtb +dtb-$(CONFIG_ARCH_HIX5HD2) += \ + hisi-x5hd2-dkb.dtb dtb-$(CONFIG_ARCH_INTEGRATOR) += \ integratorap.dtb \ integratorcp.dtb diff --git a/arch/arm/boot/dts/hi3519-demb.dts b/arch/arm/boot/dts/hi3519-demb.dts new file mode 100644 index 0000000..6991ab6 --- /dev/null +++ b/arch/arm/boot/dts/hi3519-demb.dts @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2015 HiSilicon Technologies Co., Ltd. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + * + */ + +/dts-v1/; +#include "hi3519.dtsi" + +/ { + model = "HiSilicon HI3519 DEMO Board"; + compatible = "hisilicon,hi3519"; + + aliases { + serial0 = &uart0; + }; + + memory { + device_type = "memory"; + reg = <0x80000000 0x40000000>; + }; +}; + +&uart0 { + status = "okay"; +}; + +&dual_timer0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/hi3519.dtsi b/arch/arm/boot/dts/hi3519.dtsi new file mode 100644 index 0000000..5729ecf --- /dev/null +++ b/arch/arm/boot/dts/hi3519.dtsi @@ -0,0 +1,187 @@ +/* + * Copyright (c) 2015 HiSilicon Technologies Co., Ltd. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + * + */ + +#include +#include +/ { + #address-cells = <1>; + #size-cells = <1>; + chosen { }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0>; + }; + }; + + gic: interrupt-controller@10300000 { + compatible = "arm,cortex-a7-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x10301000 0x1000>, <0x10302000 0x1000>; + }; + + clk_3m: clk_3m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <3000000>; + }; + + crg: clock-reset-controller@12010000 { + compatible = "hisilicon,hi3519-crg"; + #clock-cells = <1>; + #reset-cells = <2>; + reg = <0x12010000 0x10000>; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + interrupt-parent = <&gic>; + ranges; + + uart0: serial@12100000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x12100000 0x1000>; + interrupts = ; + clocks = <&crg HI3519_UART0_CLK>; + clock-names = "apb_pclk"; + status = "disable"; + }; + + uart1: serial@12101000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x12101000 0x1000>; + interrupts = ; + clocks = <&crg HI3519_UART1_CLK>; + clock-names = "apb_pclk"; + status = "disable"; + }; + + uart2: serial@12102000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x12102000 0x1000>; + interrupts = ; + clocks = <&crg HI3519_UART2_CLK>; + clock-names = "apb_pclk"; + status = "disable"; + }; + + uart3: serial@12103000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x12103000 0x1000>; + interrupts = ; + clocks = <&crg HI3519_UART3_CLK>; + clock-names = "apb_pclk"; + status = "disable"; + }; + + uart4: serial@12104000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x12104000 0x1000>; + interrupts = ; + clocks = <&crg HI3519_UART4_CLK>; + clock-names = "apb_pclk"; + status = "disable"; + }; + + dual_timer0: timer@12000000 { + compatible = "arm,sp804", "arm,primecell"; + interrupts = , + ; + reg = <0x12000000 0x1000>; + clocks = <&clk_3m>; + clock-names = "apb_pclk"; + status = "disable"; + }; + + dual_timer1: timer@12001000 { + compatible = "arm,sp804", "arm,primecell"; + interrupts = , + ; + reg = <0x12001000 0x1000>; + clocks = <&clk_3m>; + clock-names = "apb_pclk"; + status = "disable"; + }; + + dual_timer2: timer@12002000 { + compatible = "arm,sp804", "arm,primecell"; + interrupts = , + ; + reg = <0x12002000 0x1000>; + clocks = <&clk_3m>; + clock-names = "apb_pclk"; + status = "disable"; + }; + + spi_bus0: spi@12120000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x12120000 0x1000>; + interrupts = ; + clocks = <&crg HI3519_SPI0_CLK>; + clock-names = "apb_pclk"; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disable"; + }; + + spi_bus1: spi@12121000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x12121000 0x1000>; + interrupts = ; + clocks = <&crg HI3519_SPI1_CLK>; + clock-names = "apb_pclk"; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disable"; + }; + + spi_bus2: spi@12122000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x12122000 0x1000>; + interrupts = ; + clocks = <&crg HI3519_SPI2_CLK>; + clock-names = "apb_pclk"; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disable"; + }; + + sysctrl: system-controller@12020000 { + compatible = "hisilicon,hi3519-sysctrl", "syscon"; + reg = <0x12020000 0x1000>; + }; + + reboot { + compatible = "syscon-reboot"; + regmap = <&sysctrl>; + offset = <0x4>; + mask = <0xdeadbeef>; + }; + }; +}; -- cgit v0.10.2 From 46e6b3aa65c86bf204deb5ff590e186639009427 Mon Sep 17 00:00:00 2001 From: Alexander Shiyan Date: Sat, 4 Jun 2016 10:10:04 +0300 Subject: ARM: dts: clps711x: Add DT Cirrus Logic EDB7211 Development board This adds the Cirrus Logic EP7209,EP7211 DT templates and support for EDB7211 Development board. Signed-off-by: Alexander Shiyan Signed-off-by: Arnd Bergmann diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 7bbda1e..e8ce0cb 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -109,6 +109,8 @@ dtb-$(CONFIG_ARCH_BERLIN) += \ berlin2q-marvell-dmp.dtb dtb-$(CONFIG_ARCH_BRCMSTB) += \ bcm7445-bcm97445svmb.dtb +dtb-$(CONFIG_ARCH_CLPS711X) += \ + ep7211-edb7211.dtb dtb-$(CONFIG_ARCH_DAVINCI) += \ da850-enbw-cmc.dtb \ da850-evm.dtb diff --git a/arch/arm/boot/dts/ep7209.dtsi b/arch/arm/boot/dts/ep7209.dtsi new file mode 100644 index 0000000..aaf1261 --- /dev/null +++ b/arch/arm/boot/dts/ep7209.dtsi @@ -0,0 +1,191 @@ +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + */ + +/dts-v1/; + +#include "skeleton.dtsi" + +#include + +/ { + model = "Cirrus Logic EP7209"; + compatible = "cirrus,ep7209"; + + aliases { + gpio0 = &porta; + gpio1 = &portb; + gpio3 = &portd; + gpio4 = &porte; + serial0 = &uart1; + serial1 = &uart2; + spi0 = &spi; + timer0 = &timer1; + timer1 = &timer2; + }; + + cpus { + #address-cells = <0>; + #size-cells = <0>; + + cpu { + device_type = "cpu"; + compatible = "arm,arm720t"; + }; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + interrupt-parent = <&intc>; + ranges; + + clks: clks@80000000 { + #clock-cells = <1>; + compatible = "cirrus,ep7209-clk"; + reg = <0x80000000 0xc000>; + startup-frequency = <73728000>; + }; + + intc: intc@80000000 { + compatible = "cirrus,ep7209-intc"; + reg = <0x80000000 0x4000>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + porta: gpio@80000000 { + compatible = "cirrus,ep7209-gpio"; + reg = <0x80000000 0x1 0x80000040 0x1>; + gpio-controller; + #gpio-cells = <2>; + }; + + portb: gpio@80000001 { + compatible = "cirrus,ep7209-gpio"; + reg = <0x80000001 0x1 0x80000041 0x1>; + gpio-controller; + #gpio-cells = <2>; + }; + + portd: gpio@80000003 { + compatible = "cirrus,ep7209-gpio"; + reg = <0x80000003 0x1 0x80000043 0x1>; + gpio-controller; + #gpio-cells = <2>; + }; + + porte: gpio@80000083 { + compatible = "cirrus,ep7209-gpio"; + reg = <0x80000083 0x1 0x800000c3 0x1>; + gpio-controller; + #gpio-cells = <2>; + }; + + syscon1: syscon@80000100 { + compatible = "cirrus,ep7209-syscon1", "syscon"; + reg = <0x80000100 0x80>; + }; + + bus: bus@80000180 { + #address-cells = <2>; + #size-cells = <1>; + compatible = "cirrus,ep7209-bus", "simple-bus"; + clocks = <&clks CLPS711X_CLK_BUS>; + reg = <0x80000180 0x80>; + ranges = < + 0 0 0x00000000 0x10000000 + 1 0 0x10000000 0x10000000 + 2 0 0x20000000 0x10000000 + 3 0 0x30000000 0x10000000 + 4 0 0x40000000 0x10000000 + 5 0 0x50000000 0x10000000 + 6 0 0x60000000 0x0000c000 + 7 0 0x70000000 0x00000080 + >; + }; + + fb: fb@800002c0 { + compatible = "cirrus,ep7209-fb"; + reg = <0x800002c0 0xd44>, <0x60000000 0xc000>; + clocks = <&clks CLPS711X_CLK_BUS>; + status = "disabled"; + }; + + timer1: timer@80000300 { + compatible = "cirrus,ep7209-timer"; + reg = <0x80000300 0x4>; + clocks = <&clks CLPS711X_CLK_TIMER1>; + interrupts = <8>; + }; + + timer2: timer@80000340 { + compatible = "cirrus,ep7209-timer"; + reg = <0x80000340 0x4>; + clocks = <&clks CLPS711X_CLK_TIMER2>; + interrupts = <9>; + }; + + pwm: pwm@80000400 { + compatible = "cirrus,ep7209-pwm"; + reg = <0x80000400 0x4>; + clocks = <&clks CLPS711X_CLK_PWM>; + #pwm-cells = <1>; + }; + + uart1: uart@80000480 { + compatible = "cirrus,ep7209-uart"; + reg = <0x80000480 0x80>; + interrupts = <12 13>; + clocks = <&clks CLPS711X_CLK_UART>; + syscon = <&syscon1>; + }; + + spi: spi@80000500 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "cirrus,ep7209-spi"; + reg = <0x80000500 0x4>; + interrupts = <15>; + clocks = <&clks CLPS711X_CLK_SPI>; + status = "disabled"; + }; + + syscon2: syscon@80001100 { + compatible = "cirrus,ep7209-syscon2", "syscon"; + reg = <0x80001100 0x80>; + }; + + uart2: uart@80001480 { + compatible = "cirrus,ep7209-uart"; + reg = <0x80001480 0x80>; + interrupts = <28 29>; + clocks = <&clks CLPS711X_CLK_UART>; + syscon = <&syscon2>; + }; + + dai: dai@80002000 { + #sound-dai-cells = <0>; + compatible = "cirrus,ep7209-dai"; + reg = <0x80002000 0x604>; + clocks = <&clks CLPS711X_CLK_PLL>; + clock-names = "pll"; + interrupts = <32>; + status = "disabled"; + }; + + syscon3: syscon@80002200 { + compatible = "cirrus,ep7209-syscon3", "syscon"; + reg = <0x80002200 0x40>; + }; + }; + + mctrl: mctrl { + compatible = "cirrus,ep7209-mctrl-gpio"; + gpio-controller; + #gpio-cells = <2>; + }; +}; diff --git a/arch/arm/boot/dts/ep7211-edb7211.dts b/arch/arm/boot/dts/ep7211-edb7211.dts new file mode 100644 index 0000000..9a134ed --- /dev/null +++ b/arch/arm/boot/dts/ep7211-edb7211.dts @@ -0,0 +1,100 @@ +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + */ + +#include "ep7211.dtsi" +#include + +/ { + model = "Cirrus Logic EP7211 Development Board"; + compatible = "cirrus,edb7211", "cirrus,ep7211", "cirrus,ep7209"; + + memory { + reg = <0xc0000000 0x02000000>; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm 0>; + brightness-levels = < + 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 + 0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf + >; + default-brightness-level = <0x0>; + power-supply = <&blen>; + }; + + display: display { + model = "320x240x4"; + native-mode = <&timing0>; + bits-per-pixel = <4>; + ac-prescale = <17>; + + display-timings { + timing0: 320x240 { + hactive = <320>; + hback-porch = <0>; + hfront-porch = <0>; + hsync-len = <0>; + vactive = <240>; + vback-porch = <0>; + vfront-porch = <0>; + vsync-len = <0>; + clock-frequency = <6500000>; + }; + }; + }; + + i2c: i2c { + compatible = "i2c-gpio"; + gpios = <&portd 4 GPIO_ACTIVE_HIGH>, + <&portd 5 GPIO_ACTIVE_HIGH>; + i2c-gpio,delay-us = <2>; + i2c-gpio,scl-output-only; + #address-cells = <1>; + #size-cells = <0>; + }; + + lcddc: lcddc { + compatible = "regulator-fixed"; + regulator-name = "BACKLIGHT ENABLE"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&portd 1 GPIO_ACTIVE_HIGH>; + }; + + blen: blen { + compatible = "regulator-fixed"; + regulator-name = "BACKLIGHT ENABLE"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&portd 3 GPIO_ACTIVE_HIGH>; + }; +}; + +&bus { + flash: nor@00000000 { + compatible = "cfi-flash"; + reg = <0 0x00000000 0x02000000>; + bank-width = <2>; + #address-cells = <1>; + #size-cells = <1>; + }; +}; + +&fb { + display = <&display>; + lcd-supply = <&lcddc>; + status = "okay"; +}; + +&portd { + lcden { + gpio-hog; + gpios = <2 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "LCD ENABLE"; + }; +}; diff --git a/arch/arm/boot/dts/ep7211.dtsi b/arch/arm/boot/dts/ep7211.dtsi new file mode 100644 index 0000000..e438f6d --- /dev/null +++ b/arch/arm/boot/dts/ep7211.dtsi @@ -0,0 +1,12 @@ +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + */ + +#include "ep7209.dtsi" + +/ { + model = "Cirrus Logic EP7211"; + compatible = "cirrus,ep7211", "cirrus,ep7209"; +}; -- cgit v0.10.2 From 8ab5f1fbd39c29125403678a0caf0a71046da361 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= Date: Mon, 6 Jun 2016 09:43:49 +0200 Subject: ARM: BCM5301X: Specify NAND chip select and ECC in separated files MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Using separated file with common chip select parameters will allow us adding other ECC setups without code duplication. Signed-off-by: Rafał Miłecki Signed-off-by: Florian Fainelli diff --git a/arch/arm/boot/dts/bcm5301x-nand-cs0-bch8.dtsi b/arch/arm/boot/dts/bcm5301x-nand-cs0-bch8.dtsi index d10781e..9a9630d 100644 --- a/arch/arm/boot/dts/bcm5301x-nand-cs0-bch8.dtsi +++ b/arch/arm/boot/dts/bcm5301x-nand-cs0-bch8.dtsi @@ -9,16 +9,10 @@ * Licensed under the GNU/GPL. See COPYING for details. */ -/ { - nand@18028000 { - nandcs@0 { - compatible = "brcm,nandcs"; - reg = <0>; - #address-cells = <1>; - #size-cells = <1>; +#include "bcm5301x-nand-cs0.dtsi" - nand-ecc-strength = <8>; - nand-ecc-step-size = <512>; - }; - }; +&nandcs { + nand-ecc-algo = "bch"; + nand-ecc-strength = <8>; + nand-ecc-step-size = <512>; }; diff --git a/arch/arm/boot/dts/bcm5301x-nand-cs0.dtsi b/arch/arm/boot/dts/bcm5301x-nand-cs0.dtsi new file mode 100644 index 0000000..1684951 --- /dev/null +++ b/arch/arm/boot/dts/bcm5301x-nand-cs0.dtsi @@ -0,0 +1,18 @@ +/* + * Broadcom Northstar NAND. + * + * Copyright (C) 2015 Hauke Mehrtens + * + * Licensed under the GNU/GPL. See COPYING for details. + */ + +/ { + nand@18028000 { + nandcs: nandcs@0 { + compatible = "brcm,nandcs"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + }; + }; +}; -- cgit v0.10.2 From 70a0ae1c33572f012b734d4b574f38136c57f1a0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= Date: Mon, 6 Jun 2016 09:43:50 +0200 Subject: ARM: BCM5301X: Fix NAND ECC parameters for D-Link DIR-885L MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This device uses BCH-1 instead of BCH-8. This fixes ECC errors and makes NAND usable with brcmnand. Signed-off-by: Rafał Miłecki Signed-off-by: Florian Fainelli diff --git a/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts b/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts index 50cf804..c8c0b36 100644 --- a/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts +++ b/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts @@ -10,7 +10,7 @@ /dts-v1/; #include "bcm4708.dtsi" -#include "bcm5301x-nand-cs0-bch8.dtsi" +#include "bcm5301x-nand-cs0-bch1.dtsi" / { compatible = "dlink,dir-885l", "brcm,bcm47094", "brcm,bcm4708"; diff --git a/arch/arm/boot/dts/bcm5301x-nand-cs0-bch1.dtsi b/arch/arm/boot/dts/bcm5301x-nand-cs0-bch1.dtsi new file mode 100644 index 0000000..24b099c --- /dev/null +++ b/arch/arm/boot/dts/bcm5301x-nand-cs0-bch1.dtsi @@ -0,0 +1,15 @@ +/* + * Broadcom Northstar NAND. + * + * Copyright (C) 2016 Rafał Miłecki + * + * Licensed under the ISC license. + */ + +#include "bcm5301x-nand-cs0.dtsi" + +&nandcs { + nand-ecc-algo = "bch"; + nand-ecc-strength = <1>; + nand-ecc-step-size = <512>; +}; -- cgit v0.10.2 From 9a4865d42fe50650e37061da93441133786feac2 Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Tue, 28 Jun 2016 18:04:21 -0700 Subject: ARM: dts: NSP: Specify RAM amount for BCM958625HR board Add 512MB of memory starting at physical offset 0x6000_0000. Fixes: 65e9ac208c8e ("ARM: dts: NSP: Add new DT file for bcm958625hr") Signed-off-by: Florian Fainelli diff --git a/arch/arm/boot/dts/bcm958625hr.dts b/arch/arm/boot/dts/bcm958625hr.dts index d82cc96..03b8bbe 100644 --- a/arch/arm/boot/dts/bcm958625hr.dts +++ b/arch/arm/boot/dts/bcm958625hr.dts @@ -45,6 +45,10 @@ chosen { stdout-path = "serial0:115200n8"; }; + + memory { + reg = <0x60000000 0x20000000>; + }; }; &nand { -- cgit v0.10.2 From 83919ef0a5daa5eee163b060f7c682584df97917 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Mon, 4 Jul 2016 15:10:57 +0200 Subject: ARM: dts: Ux500: fix up TVK sensor data - Fix the I2C address and supply line names for the AK8974 - Sets up the interrupt lines to the different components as they actually are connected, I was confused for some time by the fact that several lines were connected with 0 Ohm resistors, which means NOT MOUNTED and is thus not 0 Ohm at all but infinite ohms, i.e. not connected at all. Signed-off-by: Linus Walleij Signed-off-by: Arnd Bergmann diff --git a/arch/arm/boot/dts/ste-href-tvk1281618.dtsi b/arch/arm/boot/dts/ste-href-tvk1281618.dtsi index fc5e8ce..3c9f2f0 100644 --- a/arch/arm/boot/dts/ste-href-tvk1281618.dtsi +++ b/arch/arm/boot/dts/ste-href-tvk1281618.dtsi @@ -99,46 +99,69 @@ vddio-supply = <&db8500_vsmps2_reg>; pinctrl-names = "default"; pinctrl-0 = <&accel_tvk_mode>; - interrupt-parent = <&gpio2>; - interrupts = <18 IRQ_TYPE_EDGE_FALLING>, - <19 IRQ_TYPE_EDGE_FALLING>; - }; - lsm303dlh@1e { /* - * This magnetometer is packaged with - * the accelerometer, and has a DRDY line, - * however it is not connected on this - * board so it can not generate interrupts. + * These interrupts cannot be used: the other component + * ST-Micro L3D4200D gyro that is connected to the same lines + * cannot set its DRDY line to open drain, so it cannot be + * shared with other peripherals. The should be defined for + * the falling edge if they could be wired together. + * + * interrupts-extended = + * <&gpio1 0 IRQ_TYPE_EDGE_FALLING>, + * <&gpio2 19 IRQ_TYPE_EDGE_FALLING>; */ + }; + lsm303dlh@1e { + /* Magnetometer */ compatible = "st,lsm303dlh-magn"; reg = <0x1e>; vdd-supply = <&ab8500_ldo_aux1_reg>; vddio-supply = <&db8500_vsmps2_reg>; + /* + * These interrupts cannot be used: the other component + * ST-Micro L3D4200D gyro that is connected to the same lines + * cannot set its DRDY line to open drain, so it cannot be + * shared with other peripherals. The should be defined for + * the falling edge if they could be wired together. + * + * interrupts-extended = + * <&gpio1 0 IRQ_TYPE_EDGE_FALLING>, + * <&gpio2 19 IRQ_TYPE_EDGE_FALLING>; + */ }; lis331dl@1c { /* Accelerometer */ compatible = "st,lis331dl-accel"; st,drdy-int-pin = <1>; - drive-open-drain; reg = <0x1c>; vdd-supply = <&ab8500_ldo_aux1_reg>; vddio-supply = <&db8500_vsmps2_reg>; pinctrl-names = "default"; pinctrl-0 = <&accel_tvk_mode>; interrupt-parent = <&gpio2>; - interrupts = <18 IRQ_TYPE_EDGE_FALLING>, - <19 IRQ_TYPE_EDGE_FALLING>; + /* INT2 would need to be open drain */ + interrupts = <18 IRQ_TYPE_EDGE_RISING>, + <19 IRQ_TYPE_EDGE_RISING>; }; ak8974@0f { /* Magnetometer */ compatible = "asahi-kasei,ak8974"; reg = <0x0f>; - vdd-supply = <&ab8500_ldo_aux1_reg>; - vddio-supply = <&db8500_vsmps2_reg>; + avdd-supply = <&ab8500_ldo_aux1_reg>; + dvdd-supply = <&db8500_vsmps2_reg>; pinctrl-names = "default"; pinctrl-0 = <&gyro_magn_tvk_mode>; - interrupt-parent = <&gpio1>; - interrupts = <0 IRQ_TYPE_EDGE_RISING>; + /* + * These interrupts cannot be used: the other component + * ST-Micro L3D4200D gyro that is connected to the same lines + * cannot set its DRDY line to open drain, so it cannot be + * shared with other peripherals. The should be defined for + * the falling edge if they could be wired together. + * + * interrupts-extended = + * <&gpio1 0 IRQ_TYPE_EDGE_FALLING>, + * <&gpio0 31 IRQ_TYPE_EDGE_FALLING>; + */ }; l3g4200d@68 { /* Gyroscope */ @@ -149,8 +172,9 @@ vddio-supply = <&db8500_vsmps2_reg>; pinctrl-names = "default"; pinctrl-0 = <&gyro_magn_tvk_mode>; - interrupt-parent = <&gpio1>; - interrupts = <0 IRQ_TYPE_EDGE_RISING>; + interrupts-extended = + <&gpio1 0 IRQ_TYPE_EDGE_RISING>, + <&gpio0 31 IRQ_TYPE_EDGE_RISING>; }; lsp001wm@5c { /* Barometer/pressure sensor */ @@ -218,7 +242,7 @@ /* Accelerometer interrupt lines 1 & 2 */ tvk_cfg { pins = "GPIO82_C1", "GPIO83_D3"; - ste,config = <&gpio_in_pu>; + ste,config = <&gpio_in_pd>; }; }; }; -- cgit v0.10.2 From 377c2b348376a1e937725b70279cabb48d90acaa Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Wed, 6 Jul 2016 17:10:42 +0800 Subject: ARM: dts: sun7i: lamobo-r1: Fix USB-based WiFi module power On the Lamobo R1, USB2 is connected to the RTL8192CU WiFi module. The power enable pin is connected to PH12. Fix the enable pin the reg_usb2_vbus. Also disable ohci1, as the WiFi module is USB 2.0 capable. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard diff --git a/arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts b/arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts index fbca934..2851428 100644 --- a/arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts +++ b/arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts @@ -212,10 +212,6 @@ status = "okay"; }; -&ohci1 { - status = "okay"; -}; - &otg_sram { status = "okay"; }; @@ -291,6 +287,7 @@ }; ®_usb2_vbus { + gpio = <&pio 7 12 GPIO_ACTIVE_HIGH>; /* PH12 */ status = "okay"; }; @@ -329,6 +326,10 @@ status = "okay"; }; +&usb2_vbus_pin_a { + allwinner,pins = "PH12"; +}; + &usbphy { pinctrl-names = "default"; pinctrl-0 = <&usb0_id_detect_pin>; -- cgit v0.10.2 From bec72ca528e2af87f345863b39197434c53f5c92 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Wed, 6 Jul 2016 17:10:43 +0800 Subject: ARM: dts: sun7i: lamobo-r1: Remove usb1 vbus regulator USB1 VBUS is directly tied to the 5V rail on the board. It is not individually controllable. Drop the regulator. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard diff --git a/arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts b/arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts index 2851428..7307f07 100644 --- a/arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts +++ b/arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts @@ -282,10 +282,6 @@ status = "okay"; }; -®_usb1_vbus { - status = "okay"; -}; - ®_usb2_vbus { gpio = <&pio 7 12 GPIO_ACTIVE_HIGH>; /* PH12 */ status = "okay"; @@ -336,7 +332,6 @@ usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ usb0_vbus_power-supply = <&usb_power_supply>; usb0_vbus-supply = <®_usb0_vbus>; - usb1_vbus-supply = <®_usb1_vbus>; usb2_vbus-supply = <®_usb2_vbus>; status = "okay"; }; -- cgit v0.10.2 From 0cd3d11730087da3473837981cadb446cad35cd7 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Fri, 8 Jul 2016 10:40:39 +0800 Subject: ARM: dts: sun8i-h3: Rename sinovoip-bpi-m2-plus to bananapi-m2-plus The Banana Pi series is a well known series of single board computers. The manufacturer, Sinovoip, is less well known. Moreover, the board markings do not mention Sinovoip, but only the Banana Pi logo, and the BPI-M* model name. Rename the dts file to use the more well known name. Also fix up some of the model names and labels to match other Banana Pi boards. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 016611d..3ccc653 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -763,11 +763,11 @@ dtb-$(CONFIG_MACH_SUN8I) += \ sun8i-a33-sinlinx-sina33.dtb \ sun8i-a83t-allwinner-h8homlet-v2.dtb \ sun8i-a83t-cubietruck-plus.dtb \ + sun8i-h3-bananapi-m2-plus.dtb \ sun8i-h3-orangepi-2.dtb \ sun8i-h3-orangepi-one.dtb \ sun8i-h3-orangepi-pc.dtb \ sun8i-h3-orangepi-plus.dtb \ - sun8i-h3-sinovoip-bpi-m2-plus.dtb \ sun8i-r16-parrot.dtb dtb-$(CONFIG_MACH_SUN9I) += \ sun9i-a80-optimus.dtb \ diff --git a/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts b/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts new file mode 100644 index 0000000..f3b1d5f --- /dev/null +++ b/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts @@ -0,0 +1,195 @@ +/* + * Copyright (C) 2016 Chen-Yu Tsai + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun8i-h3.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include +#include +#include + +/ { + model = "Banana Pi BPI-M2-Plus"; + compatible = "sinovoip,bpi-m2-plus", "allwinner,sun8i-h3"; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pwr_led_bpi_m2p>; + + pwr_led { + label = "bananapi-m2-plus:red:pwr"; + gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; /* PL10 */ + default-state = "on"; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&sw_r_bpi_m2p>; + + sw4 { + label = "power"; + linux,code = ; + gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; + }; + }; + + wifi_pwrseq: wifi_pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_en_bpi_m2p>; + reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */ + }; +}; + +&ehci1 { + status = "okay"; +}; + +&ehci2 { + status = "okay"; +}; + +&ir { + pinctrl-names = "default"; + pinctrl-0 = <&ir_pins_a>; + status = "okay"; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>; + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */ + cd-inverted; + status = "okay"; +}; + +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins_a>; + vmmc-supply = <®_vcc3v3>; + vqmmc-supply = <®_vcc3v3>; + mmc-pwrseq = <&wifi_pwrseq>; + bus-width = <4>; + non-removable; + status = "okay"; + + brcmf: bcrmf@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + interrupt-parent = <&pio>; + interrupts = <6 10 IRQ_TYPE_LEVEL_LOW>; /* PG10 / EINT10 */ + interrupt-names = "host-wake"; + }; +}; + +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_8bit_pins>; + vmmc-supply = <®_vcc3v3>; + vqmmc-supply = <®_vcc3v3>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&ohci2 { + status = "okay"; +}; + +&r_pio { + pwr_led_bpi_m2p: led_pins@0 { + allwinner,pins = "PL10"; + allwinner,function = "gpio_out"; + allwinner,drive = ; + allwinner,pull = ; + }; + + sw_r_bpi_m2p: key_pins@0 { + allwinner,pins = "PL3"; + allwinner,function = "gpio_in"; + allwinner,drive = ; + allwinner,pull = ; + }; + + wifi_en_bpi_m2p: wifi_en_pin { + allwinner,pins = "PL7"; + allwinner,function = "gpio_out"; + allwinner,drive = ; + allwinner,pull = ; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins_a>; + status = "okay"; +}; + +&usbphy { + /* USB VBUS is on as long as VCC-IO is on */ + status = "okay"; +}; diff --git a/arch/arm/boot/dts/sun8i-h3-sinovoip-bpi-m2-plus.dts b/arch/arm/boot/dts/sun8i-h3-sinovoip-bpi-m2-plus.dts deleted file mode 100644 index d21bc57..0000000 --- a/arch/arm/boot/dts/sun8i-h3-sinovoip-bpi-m2-plus.dts +++ /dev/null @@ -1,195 +0,0 @@ -/* - * Copyright (C) 2016 Chen-Yu Tsai - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun8i-h3.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include -#include - -/ { - model = "Sinovoip BPI-M2+"; - compatible = "sinovoip,bpi-m2+", "allwinner,sun8i-h3"; - - aliases { - serial0 = &uart0; - serial1 = &uart1; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pwr_led_bpi_m2p>; - - pwr_led { - label = "bpi-m2+:red:pwr"; - gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; /* PL10 */ - default-state = "on"; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&sw_r_bpi_m2p>; - - sw4 { - label = "power"; - linux,code = ; - gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; - }; - }; - - wifi_pwrseq: wifi_pwrseq { - compatible = "mmc-pwrseq-simple"; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_en_bpi_m2p>; - reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */ - }; -}; - -&ehci1 { - status = "okay"; -}; - -&ehci2 { - status = "okay"; -}; - -&ir { - pinctrl-names = "default"; - pinctrl-0 = <&ir_pins_a>; - status = "okay"; -}; - -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>; - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */ - cd-inverted; - status = "okay"; -}; - -&mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins_a>; - vmmc-supply = <®_vcc3v3>; - vqmmc-supply = <®_vcc3v3>; - mmc-pwrseq = <&wifi_pwrseq>; - bus-width = <4>; - non-removable; - status = "okay"; - - brcmf: bcrmf@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - interrupt-parent = <&pio>; - interrupts = <6 10 IRQ_TYPE_LEVEL_LOW>; /* PG10 / EINT10 */ - interrupt-names = "host-wake"; - }; -}; - -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_8bit_pins>; - vmmc-supply = <®_vcc3v3>; - vqmmc-supply = <®_vcc3v3>; - bus-width = <8>; - non-removable; - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&ohci2 { - status = "okay"; -}; - -&r_pio { - pwr_led_bpi_m2p: led_pins@0 { - allwinner,pins = "PL10"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; - - sw_r_bpi_m2p: key_pins@0 { - allwinner,pins = "PL3"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; - - wifi_en_bpi_m2p: wifi_en_pin { - allwinner,pins = "PL7"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins_a>; - status = "okay"; -}; - -&usbphy { - /* USB VBUS is on as long as VCC-IO is on */ - status = "okay"; -}; -- cgit v0.10.2 From f64cb7c724a677396866061a01dc85d38ac0c3b4 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Wed, 6 Jul 2016 17:10:44 +0800 Subject: ARM: dts: sun7i: lamobo-r1: Fix GPIO flags in reg_ahci_5v reg_ahci_5v uses a GPIO in active high mode. Use the proper macro, instead of just 0 for the GPIO flags. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard diff --git a/arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts b/arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts index 7307f07..c5126a9 100644 --- a/arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts +++ b/arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts @@ -249,7 +249,7 @@ #include "axp209.dtsi" ®_ahci_5v { - gpio = <&pio 1 3 0>; /* PB3 */ + gpio = <&pio 1 3 GPIO_ACTIVE_HIGH>; /* PB3 */ status = "okay"; }; -- cgit v0.10.2 From 6be9aa13414c2a799484d7690edebbd21c44e163 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Wed, 6 Jul 2016 17:10:45 +0800 Subject: ARM: dts: sun7i: lamobo-r1: Enable audio codec Lamobo R1 has a headphone jack for audio output, and an onboard microphone. These are tied to the SoC's internal audio codec. Enable the audio codec. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard diff --git a/arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts b/arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts index c5126a9..73c05da 100644 --- a/arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts +++ b/arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts @@ -95,6 +95,10 @@ status = "okay"; }; +&codec { + status = "okay"; +}; + &cpu0 { cpu-supply = <®_dcdc2>; }; -- cgit v0.10.2 From 8b0b593af7525f88f450198bc5d6c142370b2812 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Wed, 6 Jul 2016 17:10:46 +0800 Subject: ARM: dts: sun7i: bananapi-m1-plus: Reindent whole file using tabs The bananapi-m1-plus dts file was indented using 4 spaces, without tabs. This does not match the code style. Reindent the whole file before we do anything else. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard diff --git a/arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts b/arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts index 89e38e9..edfb5b3 100644 --- a/arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts +++ b/arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts @@ -49,182 +49,182 @@ #include / { - model = "Banana Pi BPI-M1-Plus"; - compatible = "sinovoip,bpi-m1-plus", "allwinner,sun7i-a20"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins_bananapi>; - - green { - label = "bananapi-m1-plus:green:usr"; - gpios = <&pio 7 24 GPIO_ACTIVE_HIGH>; - }; - - red { - label = "bananapi-m1-plus:red:usr"; - gpios = <&pio 7 25 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "default-on"; - }; - - }; - - mmc3_pwrseq: mmc3_pwrseq { - compatible = "mmc-pwrseq-simple"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc3_pwrseq_pin_bananapim1plus>; - reset-gpios = <&pio 7 22 GPIO_ACTIVE_LOW>; /* PH22 WL-PMU-EN */ - }; - - reg_gmac_3v3: gmac-3v3 { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&gmac_power_pin_bananapi>; - regulator-name = "gmac-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <100000>; - enable-active-high; - gpio = <&pio 7 23 GPIO_ACTIVE_HIGH>; - }; + model = "Banana Pi BPI-M1-Plus"; + compatible = "sinovoip,bpi-m1-plus", "allwinner,sun7i-a20"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pins_bananapi>; + + green { + label = "bananapi-m1-plus:green:usr"; + gpios = <&pio 7 24 GPIO_ACTIVE_HIGH>; + }; + + red { + label = "bananapi-m1-plus:red:usr"; + gpios = <&pio 7 25 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + }; + + }; + + mmc3_pwrseq: mmc3_pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc3_pwrseq_pin_bananapim1plus>; + reset-gpios = <&pio 7 22 GPIO_ACTIVE_LOW>; /* PH22 WL-PMU-EN */ + }; + + reg_gmac_3v3: gmac-3v3 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&gmac_power_pin_bananapi>; + regulator-name = "gmac-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <100000>; + enable-active-high; + gpio = <&pio 7 23 GPIO_ACTIVE_HIGH>; + }; }; &ahci { - status = "okay"; + status = "okay"; }; &codec { - status = "okay"; + status = "okay"; }; &ehci0 { - status = "okay"; + status = "okay"; }; &ehci1 { - status = "okay"; + status = "okay"; }; &gmac { - pinctrl-names = "default"; - pinctrl-0 = <&gmac_pins_rgmii_a>; - phy = <&phy1>; - phy-mode = "rgmii"; - phy-supply = <®_gmac_3v3>; - status = "okay"; - - phy1: ethernet-phy@1 { - reg = <1>; - }; + pinctrl-names = "default"; + pinctrl-0 = <&gmac_pins_rgmii_a>; + phy = <&phy1>; + phy-mode = "rgmii"; + phy-supply = <®_gmac_3v3>; + status = "okay"; + + phy1: ethernet-phy@1 { + reg = <1>; + }; }; &i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; - - axp209: pmic@34 { - compatible = "x-powers,axp209"; - reg = <0x34>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - - interrupt-controller; - #interrupt-cells = <1>; - }; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "okay"; + + axp209: pmic@34 { + compatible = "x-powers,axp209"; + reg = <0x34>; + interrupt-parent = <&nmi_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + + interrupt-controller; + #interrupt-cells = <1>; + }; }; &ir0 { - pinctrl-names = "default"; - pinctrl-0 = <&ir0_rx_pins_a>; - status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&ir0_rx_pins_a>; + status = "okay"; }; &mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_bananapi>; - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 10 GPIO_ACTIVE_HIGH>; /* PH10 */ - cd-inverted; - status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_bananapi>; + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 7 10 GPIO_ACTIVE_HIGH>; /* PH10 */ + cd-inverted; + status = "okay"; }; &mmc3 { - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&mmc3_pins_a>; - vmmc-supply = <®_vcc3v3>; - mmc-pwrseq = <&mmc3_pwrseq>; - bus-width = <4>; - non-removable; - enable-sdio-wakeup; - status = "okay"; - - brcmf: bcrmf@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - interrupt-parent = <&pio>; - interrupts = <7 15 IRQ_TYPE_LEVEL_LOW>; - interrupt-names = "host-wake"; - }; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&mmc3_pins_a>; + vmmc-supply = <®_vcc3v3>; + mmc-pwrseq = <&mmc3_pwrseq>; + bus-width = <4>; + non-removable; + enable-sdio-wakeup; + status = "okay"; + + brcmf: bcrmf@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + interrupt-parent = <&pio>; + interrupts = <7 15 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "host-wake"; + }; }; &mmc3_pins_a { - /* AP6210 requires pull-up */ - allwinner,pull = ; + /* AP6210 requires pull-up */ + allwinner,pull = ; }; &ohci0 { - status = "okay"; + status = "okay"; }; &ohci1 { - status = "okay"; + status = "okay"; }; &pio { - gmac_power_pin_bananapi: gmac_power_pin@0 { - allwinner,pins = "PH23"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; - - led_pins_bananapi: led_pins@0 { - allwinner,pins = "PH24", "PG2"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; - - mmc0_cd_pin_bananapi: mmc0_cd_pin@0 { - allwinner,pins = "PH10"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; - - mmc3_pwrseq_pin_bananapim1plus: mmc3_pwrseq_pin@0 { - allwinner,pins = "PH22"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; + gmac_power_pin_bananapi: gmac_power_pin@0 { + allwinner,pins = "PH23"; + allwinner,function = "gpio_out"; + allwinner,drive = ; + allwinner,pull = ; + }; + + led_pins_bananapi: led_pins@0 { + allwinner,pins = "PH24", "PG2"; + allwinner,function = "gpio_out"; + allwinner,drive = ; + allwinner,pull = ; + }; + + mmc0_cd_pin_bananapi: mmc0_cd_pin@0 { + allwinner,pins = "PH10"; + allwinner,function = "gpio_in"; + allwinner,drive = ; + allwinner,pull = ; + }; + + mmc3_pwrseq_pin_bananapim1plus: mmc3_pwrseq_pin@0 { + allwinner,pins = "PH22"; + allwinner,function = "gpio_out"; + allwinner,drive = ; + allwinner,pull = ; + }; }; &uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; - status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; }; -- cgit v0.10.2 From 28b725e0a4d9558cddd601942363485685ea4219 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Wed, 6 Jul 2016 17:10:47 +0800 Subject: ARM: dts: sun7i: bananapi-m1-plus: Unify suffix for board specific labels The dts file uses "bananapi" for some labels and "bananapim1plus" for other. Use the shortened "bpi_m1p" suffix for all board specific labels. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard diff --git a/arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts b/arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts index edfb5b3..14fb463 100644 --- a/arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts +++ b/arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts @@ -63,7 +63,7 @@ leds { compatible = "gpio-leds"; pinctrl-names = "default"; - pinctrl-0 = <&led_pins_bananapi>; + pinctrl-0 = <&led_pins_bpi_m1p>; green { label = "bananapi-m1-plus:green:usr"; @@ -81,14 +81,14 @@ mmc3_pwrseq: mmc3_pwrseq { compatible = "mmc-pwrseq-simple"; pinctrl-names = "default"; - pinctrl-0 = <&mmc3_pwrseq_pin_bananapim1plus>; + pinctrl-0 = <&mmc3_pwrseq_pin_bpi_m1p>; reset-gpios = <&pio 7 22 GPIO_ACTIVE_LOW>; /* PH22 WL-PMU-EN */ }; reg_gmac_3v3: gmac-3v3 { compatible = "regulator-fixed"; pinctrl-names = "default"; - pinctrl-0 = <&gmac_power_pin_bananapi>; + pinctrl-0 = <&gmac_power_pin_bpi_m1p>; regulator-name = "gmac-3v3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; @@ -151,7 +151,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_bananapi>; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_bpi_m1p>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 10 GPIO_ACTIVE_HIGH>; /* PH10 */ @@ -194,28 +194,28 @@ }; &pio { - gmac_power_pin_bananapi: gmac_power_pin@0 { + gmac_power_pin_bpi_m1p: gmac_power_pin@0 { allwinner,pins = "PH23"; allwinner,function = "gpio_out"; allwinner,drive = ; allwinner,pull = ; }; - led_pins_bananapi: led_pins@0 { + led_pins_bpi_m1p: led_pins@0 { allwinner,pins = "PH24", "PG2"; allwinner,function = "gpio_out"; allwinner,drive = ; allwinner,pull = ; }; - mmc0_cd_pin_bananapi: mmc0_cd_pin@0 { + mmc0_cd_pin_bpi_m1p: mmc0_cd_pin@0 { allwinner,pins = "PH10"; allwinner,function = "gpio_in"; allwinner,drive = ; allwinner,pull = ; }; - mmc3_pwrseq_pin_bananapim1plus: mmc3_pwrseq_pin@0 { + mmc3_pwrseq_pin_bpi_m1p: mmc3_pwrseq_pin@0 { allwinner,pins = "PH22"; allwinner,function = "gpio_out"; allwinner,drive = ; -- cgit v0.10.2 From 1384a147b11d7377df4009bbefc8706471a12784 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Wed, 6 Jul 2016 17:10:48 +0800 Subject: ARM: dts: sun7i: bananapi-m1-plus: red LED is power LED The red led on the Bananapi M1+ is wired to light up as soon as the board is powered, and continues to be lit while the GPIO is floating. Rename the LED to "pwr", remove the default trigger, and mark it as default on. Also fix the pinmux node that was specifying a different pin for this LED. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard diff --git a/arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts b/arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts index 14fb463..ba5bca0 100644 --- a/arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts +++ b/arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts @@ -70,12 +70,11 @@ gpios = <&pio 7 24 GPIO_ACTIVE_HIGH>; }; - red { - label = "bananapi-m1-plus:red:usr"; + pwr { + label = "bananapi-m1-plus:pwr:usr"; gpios = <&pio 7 25 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "default-on"; + default-state = "on"; }; - }; mmc3_pwrseq: mmc3_pwrseq { @@ -202,7 +201,7 @@ }; led_pins_bpi_m1p: led_pins@0 { - allwinner,pins = "PH24", "PG2"; + allwinner,pins = "PH24", "PH25"; allwinner,function = "gpio_out"; allwinner,drive = ; allwinner,pull = ; -- cgit v0.10.2 From ca3226d389ae9293a7984a9c3e4d691ce7466072 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Mon, 7 Mar 2016 17:37:49 +0100 Subject: ARM: tegra: Fix a couple of DTC warnings Add unit-addresses to nodes that have a reg property to avoid warnings on newer versions of DTC. Signed-off-by: Thierry Reding diff --git a/arch/arm/boot/dts/tegra114-roth.dts b/arch/arm/boot/dts/tegra114-roth.dts index 9d868af..d36271f 100644 --- a/arch/arm/boot/dts/tegra114-roth.dts +++ b/arch/arm/boot/dts/tegra114-roth.dts @@ -1020,7 +1020,7 @@ #address-cells = <1>; #size-cells = <0>; - clk32k_in: clock { + clk32k_in: clock@0 { compatible = "fixed-clock"; reg=<0>; #clock-cells = <0>; diff --git a/arch/arm/boot/dts/tegra114-tn7.dts b/arch/arm/boot/dts/tegra114-tn7.dts index 89047ed..17dd145 100644 --- a/arch/arm/boot/dts/tegra114-tn7.dts +++ b/arch/arm/boot/dts/tegra114-tn7.dts @@ -277,7 +277,7 @@ #address-cells = <1>; #size-cells = <0>; - clk32k_in: clock { + clk32k_in: clock@0 { compatible = "fixed-clock"; reg = <0>; #clock-cells = <0>; diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1.dts b/arch/arm/boot/dts/tegra124-jetson-tk1.dts index 941f362..f6f5d3c 100644 --- a/arch/arm/boot/dts/tegra124-jetson-tk1.dts +++ b/arch/arm/boot/dts/tegra124-jetson-tk1.dts @@ -2049,7 +2049,7 @@ thermal-zones { cpu { trips { - trip@0 { + trip { temperature = <101000>; hysteresis = <0>; type = "critical"; @@ -2063,7 +2063,7 @@ mem { trips { - trip@0 { + trip { temperature = <101000>; hysteresis = <0>; type = "critical"; @@ -2077,7 +2077,7 @@ gpu { trips { - trip@0 { + trip { temperature = <101000>; hysteresis = <0>; type = "critical"; diff --git a/arch/arm/boot/dts/tegra30-apalis.dtsi b/arch/arm/boot/dts/tegra30-apalis.dtsi index bf36127..34d0d54 100644 --- a/arch/arm/boot/dts/tegra30-apalis.dtsi +++ b/arch/arm/boot/dts/tegra30-apalis.dtsi @@ -567,7 +567,7 @@ blocks = <0x5>; irq-trigger = <0x1>; - stmpe_touchscreen { + stmpe_touchscreen@0 { compatible = "st,stmpe-ts"; reg = <0>; /* 3.25 MHz ADC clock speed */ -- cgit v0.10.2 From 4ec2e60186034d54745d8ee45441dc33acef2e9c Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 10 Jun 2016 18:55:24 +0200 Subject: ARM: tegra: Add spaces around = in properties This seems to have been copied and pasted since the beginning of time, though only until Tegra124, likely because that DT was written from scratch or it was fixed along the way. Signed-off-by: Thierry Reding diff --git a/arch/arm/boot/dts/tegra114-dalmore.dts b/arch/arm/boot/dts/tegra114-dalmore.dts index c970bf6..1dfc492 100644 --- a/arch/arm/boot/dts/tegra114-dalmore.dts +++ b/arch/arm/boot/dts/tegra114-dalmore.dts @@ -1149,7 +1149,7 @@ clk32k_in: clock@0 { compatible = "fixed-clock"; - reg=<0>; + reg = <0>; #clock-cells = <0>; clock-frequency = <32768>; }; diff --git a/arch/arm/boot/dts/tegra114-roth.dts b/arch/arm/boot/dts/tegra114-roth.dts index d36271f..70cf409 100644 --- a/arch/arm/boot/dts/tegra114-roth.dts +++ b/arch/arm/boot/dts/tegra114-roth.dts @@ -1022,7 +1022,7 @@ clk32k_in: clock@0 { compatible = "fixed-clock"; - reg=<0>; + reg = <0>; #clock-cells = <0>; clock-frequency = <32768>; }; diff --git a/arch/arm/boot/dts/tegra20-colibri-512.dtsi b/arch/arm/boot/dts/tegra20-colibri-512.dtsi index 8e0066a..1242b84 100644 --- a/arch/arm/boot/dts/tegra20-colibri-512.dtsi +++ b/arch/arm/boot/dts/tegra20-colibri-512.dtsi @@ -478,7 +478,7 @@ clk32k_in: clock@0 { compatible = "fixed-clock"; - reg=<0>; + reg = <0>; #clock-cells = <0>; clock-frequency = <32768>; }; diff --git a/arch/arm/boot/dts/tegra20-harmony.dts b/arch/arm/boot/dts/tegra20-harmony.dts index d2e960c..d4fb4d3 100644 --- a/arch/arm/boot/dts/tegra20-harmony.dts +++ b/arch/arm/boot/dts/tegra20-harmony.dts @@ -646,7 +646,7 @@ clk32k_in: clock@0 { compatible = "fixed-clock"; - reg=<0>; + reg = <0>; #clock-cells = <0>; clock-frequency = <32768>; }; diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts index 33ed2b2..4e361a8 100644 --- a/arch/arm/boot/dts/tegra20-paz00.dts +++ b/arch/arm/boot/dts/tegra20-paz00.dts @@ -512,7 +512,7 @@ clk32k_in: clock@0 { compatible = "fixed-clock"; - reg=<0>; + reg = <0>; #clock-cells = <0>; clock-frequency = <32768>; }; diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts b/arch/arm/boot/dts/tegra20-seaboard.dts index 94b60a7..2017aca 100644 --- a/arch/arm/boot/dts/tegra20-seaboard.dts +++ b/arch/arm/boot/dts/tegra20-seaboard.dts @@ -798,7 +798,7 @@ clk32k_in: clock@0 { compatible = "fixed-clock"; - reg=<0>; + reg = <0>; #clock-cells = <0>; clock-frequency = <32768>; }; diff --git a/arch/arm/boot/dts/tegra20-tamonten.dtsi b/arch/arm/boot/dts/tegra20-tamonten.dtsi index 025e9e8..27d2bbb 100644 --- a/arch/arm/boot/dts/tegra20-tamonten.dtsi +++ b/arch/arm/boot/dts/tegra20-tamonten.dtsi @@ -508,7 +508,7 @@ clk32k_in: clock@0 { compatible = "fixed-clock"; - reg=<0>; + reg = <0>; #clock-cells = <0>; clock-frequency = <32768>; }; diff --git a/arch/arm/boot/dts/tegra20-trimslice.dts b/arch/arm/boot/dts/tegra20-trimslice.dts index 4a035f7..381747f 100644 --- a/arch/arm/boot/dts/tegra20-trimslice.dts +++ b/arch/arm/boot/dts/tegra20-trimslice.dts @@ -383,7 +383,7 @@ clk32k_in: clock@0 { compatible = "fixed-clock"; - reg=<0>; + reg = <0>; #clock-cells = <0>; clock-frequency = <32768>; }; diff --git a/arch/arm/boot/dts/tegra20-ventana.dts b/arch/arm/boot/dts/tegra20-ventana.dts index a28c060..8f0aaab 100644 --- a/arch/arm/boot/dts/tegra20-ventana.dts +++ b/arch/arm/boot/dts/tegra20-ventana.dts @@ -592,7 +592,7 @@ clk32k_in: clock@0 { compatible = "fixed-clock"; - reg=<0>; + reg = <0>; #clock-cells = <0>; clock-frequency = <32768>; }; diff --git a/arch/arm/boot/dts/tegra20-whistler.dts b/arch/arm/boot/dts/tegra20-whistler.dts index 073806d..1e06f85 100644 --- a/arch/arm/boot/dts/tegra20-whistler.dts +++ b/arch/arm/boot/dts/tegra20-whistler.dts @@ -569,7 +569,7 @@ clk32k_in: clock@0 { compatible = "fixed-clock"; - reg=<0>; + reg = <0>; #clock-cells = <0>; clock-frequency = <32768>; }; diff --git a/arch/arm/boot/dts/tegra30-apalis.dtsi b/arch/arm/boot/dts/tegra30-apalis.dtsi index 34d0d54..192b951 100644 --- a/arch/arm/boot/dts/tegra30-apalis.dtsi +++ b/arch/arm/boot/dts/tegra30-apalis.dtsi @@ -674,13 +674,14 @@ clk32k_in: clk@0 { compatible = "fixed-clock"; - reg=<0>; + reg = <0>; #clock-cells = <0>; clock-frequency = <32768>; }; + clk16m: clk@1 { compatible = "fixed-clock"; - reg=<1>; + reg = <1>; #clock-cells = <0>; clock-frequency = <16000000>; clock-output-names = "clk16m"; diff --git a/arch/arm/boot/dts/tegra30-beaver.dts b/arch/arm/boot/dts/tegra30-beaver.dts index 1eca3b2..c6a67a9 100644 --- a/arch/arm/boot/dts/tegra30-beaver.dts +++ b/arch/arm/boot/dts/tegra30-beaver.dts @@ -1951,7 +1951,7 @@ clk32k_in: clock@0 { compatible = "fixed-clock"; - reg=<0>; + reg = <0>; #clock-cells = <0>; clock-frequency = <32768>; }; diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi index 4721c1c..f11012b 100644 --- a/arch/arm/boot/dts/tegra30-cardhu.dtsi +++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi @@ -423,7 +423,7 @@ clk32k_in: clock@0 { compatible = "fixed-clock"; - reg=<0>; + reg = <0>; #clock-cells = <0>; clock-frequency = <32768>; }; diff --git a/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts b/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts index 76875c3..a8c0318 100644 --- a/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts +++ b/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts @@ -131,7 +131,7 @@ clocks { clk16m: clk@1 { compatible = "fixed-clock"; - reg=<1>; + reg = <1>; #clock-cells = <0>; clock-frequency = <16000000>; clock-output-names = "clk16m"; diff --git a/arch/arm/boot/dts/tegra30-colibri.dtsi b/arch/arm/boot/dts/tegra30-colibri.dtsi index 2d8c58f..a265534 100644 --- a/arch/arm/boot/dts/tegra30-colibri.dtsi +++ b/arch/arm/boot/dts/tegra30-colibri.dtsi @@ -420,7 +420,7 @@ clk32k_in: clk@0 { compatible = "fixed-clock"; - reg=<0>; + reg = <0>; #clock-cells = <0>; clock-frequency = <32768>; }; -- cgit v0.10.2 From aee7a747af6cb9631d608e3a3e4db34eaba65b1f Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Tue, 21 Jun 2016 12:51:49 -0600 Subject: ARM: tegra: Import latest Jetson TK1 spreadsheet This imports v11 of "Jetson TK1 Development Platform Pin Mux" from https://developer.nvidia.com/embedded/downloads. The new version defines the mux option for the MIPI pad ctrl selection. The OWR pin no longer has an entry in the configuration table because the only mux option it support is OWR, that feature isn't supported, and hence can't conflict with any other pin. This pin can only usefully be used as a GPIO. Signed-off-by: Stephen Warren Signed-off-by: Thierry Reding diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1.dts b/arch/arm/boot/dts/tegra124-jetson-tk1.dts index f6f5d3c..9ce385e 100644 --- a/arch/arm/boot/dts/tegra124-jetson-tk1.dts +++ b/arch/arm/boot/dts/tegra124-jetson-tk1.dts @@ -1356,14 +1356,6 @@ nvidia,tristate = ; nvidia,enable-input = ; }; - owr { - nvidia,pins = "owr"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,rcv-sel = ; - }; clk_32k_in { nvidia,pins = "clk_32k_in"; nvidia,function = "clk"; @@ -1378,6 +1370,10 @@ nvidia,tristate = ; nvidia,enable-input = ; }; + dsi_b { + nvidia,pins = "mipi_pad_ctrl_dsi_b"; + nvidia,function = "dsi_b"; + }; }; }; -- cgit v0.10.2 From b5896f67ab3cf881a40d4ae9837bb32ec261f4c3 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Thu, 30 Jun 2016 00:21:37 +0200 Subject: ARM: tegra: Remove commas from unit addresses on Tegra124 Remove commas from unit addresses as suggested by Rob Herring upon me posting initial Apalis TK1 support: http://article.gmane.org/gmane.linux.ports.tegra/26608 Please keep the remaining 0, notation on the GPU node in place as a former mainline U-Boot version was looking for that particular notation in order to perform required fix-ups on it. Signed-off-by: Marcel Ziswiler Acked-by: Stephen Warren Tested-by: Alexandre Courbot Signed-off-by: Thierry Reding diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1-emc.dtsi b/arch/arm/boot/dts/tegra124-jetson-tk1-emc.dtsi index 2c5cede..accb705 100644 --- a/arch/arm/boot/dts/tegra124-jetson-tk1-emc.dtsi +++ b/arch/arm/boot/dts/tegra124-jetson-tk1-emc.dtsi @@ -1,5 +1,5 @@ / { - clock@0,60006000 { + clock@60006000 { emc-timings-3 { nvidia,ram-code = <3>; @@ -78,7 +78,7 @@ }; }; - emc@0,7001b000 { + emc@7001b000 { emc-timings-3 { nvidia,ram-code = <3>; @@ -2101,7 +2101,7 @@ }; }; - memory-controller@0,70019000 { + memory-controller@70019000 { emc-timings-3 { nvidia,ram-code = <3>; diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1.dts b/arch/arm/boot/dts/tegra124-jetson-tk1.dts index 9ce385e..e52b824 100644 --- a/arch/arm/boot/dts/tegra124-jetson-tk1.dts +++ b/arch/arm/boot/dts/tegra124-jetson-tk1.dts @@ -10,8 +10,8 @@ compatible = "nvidia,jetson-tk1", "nvidia,tegra124"; aliases { - rtc0 = "/i2c@0,7000d000/pmic@40"; - rtc1 = "/rtc@0,7000e000"; + rtc0 = "/i2c@7000d000/pmic@40"; + rtc1 = "/rtc@7000e000"; /* This order keeps the mapping DB9 connector <-> ttyS0 */ serial0 = &uartd; @@ -27,7 +27,7 @@ reg = <0x0 0x80000000 0x0 0x80000000>; }; - pcie-controller@0,01003000 { + pcie-controller@01003000 { status = "okay"; avddio-pex-supply = <&vdd_1v05_run>; @@ -40,21 +40,21 @@ /* Mini PCIe */ pci@1,0 { - phys = <&{/padctl@0,7009f000/pads/pcie/lanes/pcie-4}>; + phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-4}>; phy-names = "pcie-0"; status = "okay"; }; /* Gigabit Ethernet */ pci@2,0 { - phys = <&{/padctl@0,7009f000/pads/pcie/lanes/pcie-2}>; + phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-2}>; phy-names = "pcie-0"; status = "okay"; }; }; - host1x@0,50000000 { - hdmi@0,54280000 { + host1x@50000000 { + hdmi@54280000 { status = "okay"; hdmi-supply = <&vdd_5v0_hdmi>; @@ -75,7 +75,7 @@ vdd-supply = <&vdd_gpu>; }; - pinmux: pinmux@0,70000868 { + pinmux: pinmux@70000868 { pinctrl-names = "boot"; pinctrl-0 = <&state_boot>; @@ -1400,12 +1400,12 @@ }; /* DB9 serial port */ - serial@0,70006300 { + serial@70006300 { status = "okay"; }; /* Expansion GEN1_I2C_*, mini-PCIe I2C, on-board components */ - i2c@0,7000c000 { + i2c@7000c000 { status = "okay"; clock-frequency = <100000>; @@ -1433,25 +1433,25 @@ }; /* Expansion GEN2_I2C_* */ - i2c@0,7000c400 { + i2c@7000c400 { status = "okay"; clock-frequency = <100000>; }; /* Expansion CAM_I2C_* */ - i2c@0,7000c500 { + i2c@7000c500 { status = "okay"; clock-frequency = <100000>; }; /* HDMI DDC */ - hdmi_ddc: i2c@0,7000c700 { + hdmi_ddc: i2c@7000c700 { status = "okay"; clock-frequency = <100000>; }; /* Expansion PWR_I2C_*, on-board components */ - i2c@0,7000d000 { + i2c@7000d000 { status = "okay"; clock-frequency = <400000>; @@ -1642,12 +1642,12 @@ }; /* Expansion TS_SPI_* */ - spi@0,7000d400 { + spi@7000d400 { status = "okay"; }; /* Internal SPI */ - spi@0,7000da00 { + spi@7000da00 { status = "okay"; spi-max-frequency = <25000000>; spi-flash@0 { @@ -1657,7 +1657,7 @@ }; }; - pmc@0,7000e400 { + pmc@7000e400 { nvidia,invert-interrupt; nvidia,suspend-mode = <1>; nvidia,cpu-pwr-good-time = <500>; @@ -1676,10 +1676,10 @@ }; /* Serial ATA */ - sata@0,70020000 { + sata@70020000 { status = "okay"; - phys = <&{/padctl@0,7009f000/pads/sata/lanes/sata-0}>; + phys = <&{/padctl@7009f000/pads/sata/lanes/sata-0}>; phy-names = "sata-0"; hvdd-supply = <&vdd_3v3_lp0>; @@ -1690,15 +1690,15 @@ target-12v-supply = <&vdd_12v0_sata>; }; - hda@0,70030000 { + hda@70030000 { status = "okay"; }; - usb@0,70090000 { - phys = <&{/padctl@0,7009f000/pads/usb2/lanes/usb2-0}>, /* Micro A/B */ - <&{/padctl@0,7009f000/pads/usb2/lanes/usb2-1}>, /* Mini PCIe */ - <&{/padctl@0,7009f000/pads/usb2/lanes/usb2-2}>, /* USB3 */ - <&{/padctl@0,7009f000/pads/pcie/lanes/pcie-0}>; /* USB3 */ + usb@70090000 { + phys = <&{/padctl@7009f000/pads/usb2/lanes/usb2-0}>, /* Micro A/B */ + <&{/padctl@7009f000/pads/usb2/lanes/usb2-1}>, /* Mini PCIe */ + <&{/padctl@7009f000/pads/usb2/lanes/usb2-2}>, /* USB3 */ + <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>; /* USB3 */ phy-names = "usb2-0", "usb2-1", "usb2-2", "usb3-0"; avddio-pex-supply = <&vdd_1v05_run>; @@ -1713,7 +1713,7 @@ status = "okay"; }; - padctl@0,7009f000 { + padctl@7009f000 { status = "okay"; pads { @@ -1800,7 +1800,7 @@ }; /* SD card */ - sdhci@0,700b0400 { + sdhci@700b0400 { status = "okay"; cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>; @@ -1810,40 +1810,40 @@ }; /* eMMC */ - sdhci@0,700b0600 { + sdhci@700b0600 { status = "okay"; bus-width = <8>; non-removable; }; /* CPU DFLL clock */ - clock@0,70110000 { + clock@70110000 { status = "okay"; vdd-cpu-supply = <&vdd_cpu>; nvidia,i2c-fs-rate = <400000>; }; - ahub@0,70300000 { - i2s@0,70301100 { + ahub@70300000 { + i2s@70301100 { status = "okay"; }; }; /* mini-PCIe USB */ - usb@0,7d004000 { + usb@7d004000 { status = "okay"; }; - usb-phy@0,7d004000 { + usb-phy@7d004000 { status = "okay"; }; /* USB A connector */ - usb@0,7d008000 { + usb@7d008000 { status = "okay"; }; - usb-phy@0,7d008000 { + usb-phy@7d008000 { status = "okay"; vbus-supply = <&vdd_usb3_vbus>; }; diff --git a/arch/arm/boot/dts/tegra124-nyan-big-emc.dtsi b/arch/arm/boot/dts/tegra124-nyan-big-emc.dtsi index 1a5748d..4458e86 100644 --- a/arch/arm/boot/dts/tegra124-nyan-big-emc.dtsi +++ b/arch/arm/boot/dts/tegra124-nyan-big-emc.dtsi @@ -1,5 +1,5 @@ / { - clock@0,60006000 { + clock@60006000 { emc-timings-1 { nvidia,ram-code = <1>; @@ -67,7 +67,7 @@ }; }; - emc@0,7001b000 { + emc@7001b000 { emc-timings-1 { nvidia,ram-code = <1>; @@ -1754,7 +1754,7 @@ }; }; - memory-controller@0,70019000 { + memory-controller@70019000 { emc-timings-1 { nvidia,ram-code = <1>; diff --git a/arch/arm/boot/dts/tegra124-nyan-big.dts b/arch/arm/boot/dts/tegra124-nyan-big.dts index 2d21253..67d7cfb 100644 --- a/arch/arm/boot/dts/tegra124-nyan-big.dts +++ b/arch/arm/boot/dts/tegra124-nyan-big.dts @@ -15,7 +15,7 @@ ddc-i2c-bus = <&dpaux>; }; - sdhci@0,700b0400 { /* SD Card on this bus */ + sdhci@700b0400 { /* SD Card on this bus */ wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>; }; @@ -26,7 +26,7 @@ nvidia,model = "GoogleNyanBig"; }; - pinmux@0,70000868 { + pinmux@70000868 { pinctrl-names = "default"; pinctrl-0 = <&pinmux_default>; diff --git a/arch/arm/boot/dts/tegra124-nyan-blaze-emc.dtsi b/arch/arm/boot/dts/tegra124-nyan-blaze-emc.dtsi index 9ecd108..4e7b59e 100644 --- a/arch/arm/boot/dts/tegra124-nyan-blaze-emc.dtsi +++ b/arch/arm/boot/dts/tegra124-nyan-blaze-emc.dtsi @@ -1,5 +1,5 @@ / { - clock@0,60006000 { + clock@60006000 { emc-timings-1 { nvidia,ram-code = <1>; @@ -67,7 +67,7 @@ }; }; - emc@0,7001b000 { + emc@7001b000 { emc-timings-1 { nvidia,ram-code = <1>; @@ -1754,7 +1754,7 @@ }; }; - memory-controller@0,70019000 { + memory-controller@70019000 { emc-timings-1 { nvidia,ram-code = <1>; diff --git a/arch/arm/boot/dts/tegra124-nyan-blaze.dts b/arch/arm/boot/dts/tegra124-nyan-blaze.dts index 0d30c51..c9582361 100644 --- a/arch/arm/boot/dts/tegra124-nyan-blaze.dts +++ b/arch/arm/boot/dts/tegra124-nyan-blaze.dts @@ -22,7 +22,7 @@ nvidia,model = "GoogleNyanBlaze"; }; - pinmux@0,70000868 { + pinmux@70000868 { pinctrl-names = "default"; pinctrl-0 = <&pinmux_default>; diff --git a/arch/arm/boot/dts/tegra124-nyan.dtsi b/arch/arm/boot/dts/tegra124-nyan.dtsi index 0710a60..271505e 100644 --- a/arch/arm/boot/dts/tegra124-nyan.dtsi +++ b/arch/arm/boot/dts/tegra124-nyan.dtsi @@ -3,8 +3,8 @@ / { aliases { - rtc0 = "/i2c@0,7000d000/pmic@40"; - rtc1 = "/rtc@0,7000e000"; + rtc0 = "/i2c@7000d000/pmic@40"; + rtc1 = "/rtc@7000e000"; serial0 = &uarta; }; @@ -16,8 +16,8 @@ reg = <0x0 0x80000000 0x0 0x80000000>; }; - host1x@0,50000000 { - hdmi@0,54280000 { + host1x@50000000 { + hdmi@54280000 { status = "okay"; vdd-supply = <&vdd_3v3_hdmi>; @@ -29,29 +29,29 @@ <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; }; - sor@0,54540000 { + sor@54540000 { status = "okay"; nvidia,dpaux = <&dpaux>; nvidia,panel = <&panel>; }; - dpaux@0,545c0000 { + dpaux@545c0000 { vdd-supply = <&vdd_3v3_panel>; status = "okay"; }; }; - serial@0,70006000 { + serial@70006000 { /* Debug connector on the bottom of the board near SD card. */ status = "okay"; }; - pwm@0,7000a000 { + pwm@7000a000 { status = "okay"; }; - i2c@0,7000c000 { + i2c@7000c000 { status = "okay"; clock-frequency = <100000>; @@ -72,7 +72,7 @@ }; }; - i2c@0,7000c400 { + i2c@7000c400 { status = "okay"; clock-frequency = <100000>; @@ -85,7 +85,7 @@ }; }; - i2c@0,7000c500 { + i2c@7000c500 { status = "okay"; clock-frequency = <400000>; @@ -95,12 +95,12 @@ }; }; - hdmi_ddc: i2c@0,7000c700 { + hdmi_ddc: i2c@7000c700 { status = "okay"; clock-frequency = <100000>; }; - i2c@0,7000d000 { + i2c@7000d000 { status = "okay"; clock-frequency = <400000>; @@ -301,7 +301,7 @@ }; }; - spi@0,7000d400 { + spi@7000d400 { status = "okay"; cros_ec: cros-ec@0 { @@ -342,7 +342,7 @@ }; }; - spi@0,7000da00 { + spi@7000da00 { status = "okay"; spi-max-frequency = <25000000>; @@ -353,7 +353,7 @@ }; }; - pmc@0,7000e400 { + pmc@7000e400 { nvidia,invert-interrupt; nvidia,suspend-mode = <0>; nvidia,cpu-pwr-good-time = <500>; @@ -364,16 +364,16 @@ nvidia,sys-clock-req-active-high; }; - hda@0,70030000 { + hda@70030000 { status = "okay"; }; - usb@0,70090000 { - phys = <&{/padctl@0,7009f000/pads/usb2/lanes/usb2-0}>, /* 1st USB A */ - <&{/padctl@0,7009f000/pads/usb2/lanes/usb2-1}>, /* Internal USB */ - <&{/padctl@0,7009f000/pads/usb2/lanes/usb2-2}>, /* 2nd USB A */ - <&{/padctl@0,7009f000/pads/pcie/lanes/pcie-0}>, /* 1st USB A */ - <&{/padctl@0,7009f000/pads/pcie/lanes/pcie-1}>; /* 2nd USB A */ + usb@70090000 { + phys = <&{/padctl@7009f000/pads/usb2/lanes/usb2-0}>, /* 1st USB A */ + <&{/padctl@7009f000/pads/usb2/lanes/usb2-1}>, /* Internal USB */ + <&{/padctl@7009f000/pads/usb2/lanes/usb2-2}>, /* 2nd USB A */ + <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>, /* 1st USB A */ + <&{/padctl@7009f000/pads/pcie/lanes/pcie-1}>; /* 2nd USB A */ phy-names = "usb2-0", "usb2-1", "usb2-2", "usb3-0", "usb3-1"; avddio-pex-supply = <&vdd_1v05_run>; @@ -388,7 +388,7 @@ status = "okay"; }; - padctl@0,7009f000 { + padctl@7009f000 { status = "okay"; pads { @@ -467,7 +467,7 @@ reset-gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_LOW>; }; - sdhci@0,700b0000 { /* WiFi/BT on this bus */ + sdhci@700b0000 { /* WiFi/BT on this bus */ status = "okay"; bus-width = <4>; no-1-8-v; @@ -478,7 +478,7 @@ keep-power-in-suspend; }; - sdhci@0,700b0400 { /* SD Card on this bus */ + sdhci@700b0400 { /* SD Card on this bus */ status = "okay"; cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>; @@ -487,7 +487,7 @@ vqmmc-supply = <&vddio_sdmmc3>; }; - sdhci@0,700b0600 { /* eMMC on this bus */ + sdhci@700b0600 { /* eMMC on this bus */ status = "okay"; bus-width = <8>; no-1-8-v; @@ -495,14 +495,14 @@ }; /* CPU DFLL clock */ - clock@0,70110000 { + clock@70110000 { status = "disabled"; vdd-cpu-supply = <&vdd_cpu>; nvidia,i2c-fs-rate = <400000>; }; - ahub@0,70300000 { - i2s@0,70301100 { + ahub@70300000 { + i2s@70301100 { status = "okay"; }; }; diff --git a/arch/arm/boot/dts/tegra124-venice2.dts b/arch/arm/boot/dts/tegra124-venice2.dts index 973446d..6e59cec 100644 --- a/arch/arm/boot/dts/tegra124-venice2.dts +++ b/arch/arm/boot/dts/tegra124-venice2.dts @@ -8,8 +8,8 @@ compatible = "nvidia,venice2", "nvidia,tegra124"; aliases { - rtc0 = "/i2c@0,7000d000/pmic@40"; - rtc1 = "/rtc@0,7000e000"; + rtc0 = "/i2c@7000d000/pmic@40"; + rtc1 = "/rtc@7000e000"; serial0 = &uarta; }; @@ -21,8 +21,8 @@ reg = <0x0 0x80000000 0x0 0x80000000>; }; - host1x@0,50000000 { - hdmi@0,54280000 { + host1x@50000000 { + hdmi@54280000 { status = "okay"; vdd-supply = <&vdd_3v3_hdmi>; @@ -34,14 +34,14 @@ <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; }; - sor@0,54540000 { + sor@54540000 { status = "okay"; nvidia,dpaux = <&dpaux>; nvidia,panel = <&panel>; }; - dpaux@0,545c0000 { + dpaux@545c0000 { vdd-supply = <&vdd_3v3_panel>; status = "okay"; }; @@ -55,7 +55,7 @@ vdd-supply = <&vdd_gpu>; }; - pinmux: pinmux@0,70000868 { + pinmux: pinmux@70000868 { pinctrl-names = "boot"; pinctrl-0 = <&pinmux_boot>; @@ -596,15 +596,15 @@ }; }; - serial@0,70006000 { + serial@70006000 { status = "okay"; }; - pwm@0,7000a000 { + pwm@7000a000 { status = "okay"; }; - i2c@0,7000c000 { + i2c@7000c000 { status = "okay"; clock-frequency = <100000>; @@ -616,7 +616,7 @@ }; }; - i2c@0,7000c400 { + i2c@7000c400 { status = "okay"; clock-frequency = <100000>; @@ -629,17 +629,17 @@ }; }; - i2c@0,7000c500 { + i2c@7000c500 { status = "okay"; clock-frequency = <100000>; }; - hdmi_ddc: i2c@0,7000c700 { + hdmi_ddc: i2c@7000c700 { status = "okay"; clock-frequency = <100000>; }; - i2c@0,7000d000 { + i2c@7000d000 { status = "okay"; clock-frequency = <400000>; @@ -834,7 +834,7 @@ }; }; - spi@0,7000d400 { + spi@7000d400 { status = "okay"; cros_ec: cros-ec@0 { @@ -874,7 +874,7 @@ }; }; - spi@0,7000da00 { + spi@7000da00 { status = "okay"; spi-max-frequency = <25000000>; spi-flash@0 { @@ -884,7 +884,7 @@ }; }; - pmc@0,7000e400 { + pmc@7000e400 { nvidia,invert-interrupt; nvidia,suspend-mode = <1>; nvidia,cpu-pwr-good-time = <500>; @@ -895,16 +895,16 @@ nvidia,sys-clock-req-active-high; }; - hda@0,70030000 { + hda@70030000 { status = "okay"; }; - usb@0,70090000 { - phys = <&{/padctl@0,7009f000/pads/usb2/lanes/usb2-0}>, /* 1st USB A */ - <&{/padctl@0,7009f000/pads/usb2/lanes/usb2-1}>, /* Internal USB */ - <&{/padctl@0,7009f000/pads/usb2/lanes/usb2-2}>, /* 2nd USB A */ - <&{/padctl@0,7009f000/pads/pcie/lanes/pcie-0}>, /* 1st USB A */ - <&{/padctl@0,7009f000/pads/pcie/lanes/pcie-1}>; /* 2nd USB A */ + usb@70090000 { + phys = <&{/padctl@7009f000/pads/usb2/lanes/usb2-0}>, /* 1st USB A */ + <&{/padctl@7009f000/pads/usb2/lanes/usb2-1}>, /* Internal USB */ + <&{/padctl@7009f000/pads/usb2/lanes/usb2-2}>, /* 2nd USB A */ + <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>, /* 1st USB A */ + <&{/padctl@7009f000/pads/pcie/lanes/pcie-1}>; /* 2nd USB A */ phy-names = "usb2-0", "usb2-1", "usb2-2", "usb3-0", "usb3-1"; avddio-pex-supply = <&vdd_1v05_run>; @@ -919,7 +919,7 @@ status = "okay"; }; - padctl@0,7009f000 { + padctl@7009f000 { pads { usb2 { status = "okay"; @@ -998,7 +998,7 @@ }; }; - sdhci@0,700b0400 { + sdhci@700b0400 { cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>; power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>; wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>; @@ -1007,41 +1007,41 @@ vqmmc-supply = <&vddio_sdmmc3>; }; - sdhci@0,700b0600 { + sdhci@700b0600 { status = "okay"; bus-width = <8>; non-removable; }; - ahub@0,70300000 { - i2s@0,70301100 { + ahub@70300000 { + i2s@70301100 { status = "okay"; }; }; - usb@0,7d000000 { + usb@7d000000 { status = "okay"; }; - usb-phy@0,7d000000 { + usb-phy@7d000000 { status = "okay"; vbus-supply = <&vdd_usb1_vbus>; }; - usb@0,7d004000 { + usb@7d004000 { status = "okay"; }; - usb-phy@0,7d004000 { + usb-phy@7d004000 { status = "okay"; vbus-supply = <&vdd_run_cam>; }; - usb@0,7d008000 { + usb@7d008000 { status = "okay"; }; - usb-phy@0,7d008000 { + usb-phy@7d008000 { status = "okay"; vbus-supply = <&vdd_usb3_vbus>; }; diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index ea48118..ea340f9 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -14,7 +14,7 @@ #address-cells = <2>; #size-cells = <2>; - pcie-controller@0,01003000 { + pcie-controller@01003000 { compatible = "nvidia,tegra124-pcie"; device_type = "pci"; reg = <0x0 0x01003000 0x0 0x00000800 /* PADS registers */ @@ -77,7 +77,7 @@ }; }; - host1x@0,50000000 { + host1x@50000000 { compatible = "nvidia,tegra124-host1x", "simple-bus"; reg = <0x0 0x50000000 0x0 0x00034000>; interrupts = , /* syncpt */ @@ -91,7 +91,7 @@ ranges = <0 0x54000000 0 0x54000000 0 0x01000000>; - dc@0,54200000 { + dc@54200000 { compatible = "nvidia,tegra124-dc"; reg = <0x0 0x54200000 0x0 0x00040000>; interrupts = ; @@ -106,7 +106,7 @@ nvidia,head = <0>; }; - dc@0,54240000 { + dc@54240000 { compatible = "nvidia,tegra124-dc"; reg = <0x0 0x54240000 0x0 0x00040000>; interrupts = ; @@ -121,7 +121,7 @@ nvidia,head = <1>; }; - hdmi@0,54280000 { + hdmi@54280000 { compatible = "nvidia,tegra124-hdmi"; reg = <0x0 0x54280000 0x0 0x00040000>; interrupts = ; @@ -133,7 +133,7 @@ status = "disabled"; }; - sor@0,54540000 { + sor@54540000 { compatible = "nvidia,tegra124-sor"; reg = <0x0 0x54540000 0x0 0x00040000>; interrupts = ; @@ -147,7 +147,7 @@ status = "disabled"; }; - dpaux: dpaux@0,545c0000 { + dpaux: dpaux@545c0000 { compatible = "nvidia,tegra124-dpaux"; reg = <0x0 0x545c0000 0x0 0x00040000>; interrupts = ; @@ -160,7 +160,7 @@ }; }; - gic: interrupt-controller@0,50041000 { + gic: interrupt-controller@50041000 { compatible = "arm,cortex-a15-gic"; #interrupt-cells = <3>; interrupt-controller; @@ -173,6 +173,11 @@ interrupt-parent = <&gic>; }; + /* + * Please keep the following 0, notation in place as a former mainline + * U-Boot version was looking for that particular notation in order to + * perform required fix-ups on that GPU node. + */ gpu@0,57000000 { compatible = "nvidia,gk20a"; reg = <0x0 0x57000000 0x0 0x01000000>, @@ -203,7 +208,7 @@ interrupt-parent = <&gic>; }; - timer@0,60005000 { + timer@60005000 { compatible = "nvidia,tegra124-timer", "nvidia,tegra30-timer", "nvidia,tegra20-timer"; reg = <0x0 0x60005000 0x0 0x400>; interrupts = , @@ -215,7 +220,7 @@ clocks = <&tegra_car TEGRA124_CLK_TIMER>; }; - tegra_car: clock@0,60006000 { + tegra_car: clock@60006000 { compatible = "nvidia,tegra124-car"; reg = <0x0 0x60006000 0x0 0x1000>; #clock-cells = <1>; @@ -223,12 +228,12 @@ nvidia,external-memory-controller = <&emc>; }; - flow-controller@0,60007000 { + flow-controller@60007000 { compatible = "nvidia,tegra124-flowctrl"; reg = <0x0 0x60007000 0x0 0x1000>; }; - actmon@0,6000c800 { + actmon@6000c800 { compatible = "nvidia,tegra124-actmon"; reg = <0x0 0x6000c800 0x0 0x400>; interrupts = ; @@ -239,7 +244,7 @@ reset-names = "actmon"; }; - gpio: gpio@0,6000d000 { + gpio: gpio@6000d000 { compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio"; reg = <0x0 0x6000d000 0x0 0x1000>; interrupts = , @@ -259,7 +264,7 @@ */ }; - apbdma: dma@0,60020000 { + apbdma: dma@60020000 { compatible = "nvidia,tegra124-apbdma", "nvidia,tegra148-apbdma"; reg = <0x0 0x60020000 0x0 0x1400>; interrupts = , @@ -300,13 +305,13 @@ #dma-cells = <1>; }; - apbmisc@0,70000800 { + apbmisc@70000800 { compatible = "nvidia,tegra124-apbmisc", "nvidia,tegra20-apbmisc"; reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */ <0x0 0x7000e864 0x0 0x04>; /* Strapping options */ }; - pinmux: pinmux@0,70000868 { + pinmux: pinmux@70000868 { compatible = "nvidia,tegra124-pinmux"; reg = <0x0 0x70000868 0x0 0x164>, /* Pad control registers */ <0x0 0x70003000 0x0 0x434>, /* Mux registers */ @@ -321,7 +326,7 @@ * the APB DMA based serial driver, the compatible is * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart". */ - uarta: serial@0,70006000 { + uarta: serial@70006000 { compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; reg = <0x0 0x70006000 0x0 0x40>; reg-shift = <2>; @@ -334,7 +339,7 @@ status = "disabled"; }; - uartb: serial@0,70006040 { + uartb: serial@70006040 { compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; reg = <0x0 0x70006040 0x0 0x40>; reg-shift = <2>; @@ -347,7 +352,7 @@ status = "disabled"; }; - uartc: serial@0,70006200 { + uartc: serial@70006200 { compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; reg = <0x0 0x70006200 0x0 0x40>; reg-shift = <2>; @@ -360,7 +365,7 @@ status = "disabled"; }; - uartd: serial@0,70006300 { + uartd: serial@70006300 { compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; reg = <0x0 0x70006300 0x0 0x40>; reg-shift = <2>; @@ -373,7 +378,7 @@ status = "disabled"; }; - pwm: pwm@0,7000a000 { + pwm: pwm@7000a000 { compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm"; reg = <0x0 0x7000a000 0x0 0x100>; #pwm-cells = <2>; @@ -383,7 +388,7 @@ status = "disabled"; }; - i2c@0,7000c000 { + i2c@7000c000 { compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; reg = <0x0 0x7000c000 0x0 0x100>; interrupts = ; @@ -398,7 +403,7 @@ status = "disabled"; }; - i2c@0,7000c400 { + i2c@7000c400 { compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; reg = <0x0 0x7000c400 0x0 0x100>; interrupts = ; @@ -413,7 +418,7 @@ status = "disabled"; }; - i2c@0,7000c500 { + i2c@7000c500 { compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; reg = <0x0 0x7000c500 0x0 0x100>; interrupts = ; @@ -428,7 +433,7 @@ status = "disabled"; }; - i2c@0,7000c700 { + i2c@7000c700 { compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; reg = <0x0 0x7000c700 0x0 0x100>; interrupts = ; @@ -443,7 +448,7 @@ status = "disabled"; }; - i2c@0,7000d000 { + i2c@7000d000 { compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; reg = <0x0 0x7000d000 0x0 0x100>; interrupts = ; @@ -458,7 +463,7 @@ status = "disabled"; }; - i2c@0,7000d100 { + i2c@7000d100 { compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; reg = <0x0 0x7000d100 0x0 0x100>; interrupts = ; @@ -473,7 +478,7 @@ status = "disabled"; }; - spi@0,7000d400 { + spi@7000d400 { compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; reg = <0x0 0x7000d400 0x0 0x200>; interrupts = ; @@ -488,7 +493,7 @@ status = "disabled"; }; - spi@0,7000d600 { + spi@7000d600 { compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; reg = <0x0 0x7000d600 0x0 0x200>; interrupts = ; @@ -503,7 +508,7 @@ status = "disabled"; }; - spi@0,7000d800 { + spi@7000d800 { compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; reg = <0x0 0x7000d800 0x0 0x200>; interrupts = ; @@ -518,7 +523,7 @@ status = "disabled"; }; - spi@0,7000da00 { + spi@7000da00 { compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; reg = <0x0 0x7000da00 0x0 0x200>; interrupts = ; @@ -533,7 +538,7 @@ status = "disabled"; }; - spi@0,7000dc00 { + spi@7000dc00 { compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; reg = <0x0 0x7000dc00 0x0 0x200>; interrupts = ; @@ -548,7 +553,7 @@ status = "disabled"; }; - spi@0,7000de00 { + spi@7000de00 { compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; reg = <0x0 0x7000de00 0x0 0x200>; interrupts = ; @@ -563,21 +568,21 @@ status = "disabled"; }; - rtc@0,7000e000 { + rtc@7000e000 { compatible = "nvidia,tegra124-rtc", "nvidia,tegra20-rtc"; reg = <0x0 0x7000e000 0x0 0x100>; interrupts = ; clocks = <&tegra_car TEGRA124_CLK_RTC>; }; - pmc@0,7000e400 { + pmc@7000e400 { compatible = "nvidia,tegra124-pmc"; reg = <0x0 0x7000e400 0x0 0x400>; clocks = <&tegra_car TEGRA124_CLK_PCLK>, <&clk32k_in>; clock-names = "pclk", "clk32k_in"; }; - fuse@0,7000f800 { + fuse@7000f800 { compatible = "nvidia,tegra124-efuse"; reg = <0x0 0x7000f800 0x0 0x400>; clocks = <&tegra_car TEGRA124_CLK_FUSE>; @@ -586,7 +591,7 @@ reset-names = "fuse"; }; - mc: memory-controller@0,70019000 { + mc: memory-controller@70019000 { compatible = "nvidia,tegra124-mc"; reg = <0x0 0x70019000 0x0 0x1000>; clocks = <&tegra_car TEGRA124_CLK_MC>; @@ -597,14 +602,14 @@ #iommu-cells = <1>; }; - emc: emc@0,7001b000 { + emc: emc@7001b000 { compatible = "nvidia,tegra124-emc"; reg = <0x0 0x7001b000 0x0 0x1000>; nvidia,memory-controller = <&mc>; }; - sata@0,70020000 { + sata@70020000 { compatible = "nvidia,tegra124-ahci"; reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */ <0x0 0x70020000 0x0 0x7000>; /* SATA */ @@ -621,7 +626,7 @@ status = "disabled"; }; - hda@0,70030000 { + hda@70030000 { compatible = "nvidia,tegra124-hda", "nvidia,tegra30-hda"; reg = <0x0 0x70030000 0x0 0x10000>; interrupts = ; @@ -636,7 +641,7 @@ status = "disabled"; }; - usb@0,70090000 { + usb@70090000 { compatible = "nvidia,tegra124-xusb"; reg = <0x0 0x70090000 0x0 0x8000>, <0x0 0x70098000 0x0 0x1000>, @@ -671,7 +676,7 @@ status = "disabled"; }; - padctl: padctl@0,7009f000 { + padctl: padctl@7009f000 { compatible = "nvidia,tegra124-xusb-padctl"; reg = <0x0 0x7009f000 0x0 0x1000>; resets = <&tegra_car 142>; @@ -804,7 +809,7 @@ }; }; - sdhci@0,700b0000 { + sdhci@700b0000 { compatible = "nvidia,tegra124-sdhci"; reg = <0x0 0x700b0000 0x0 0x200>; interrupts = ; @@ -814,7 +819,7 @@ status = "disabled"; }; - sdhci@0,700b0200 { + sdhci@700b0200 { compatible = "nvidia,tegra124-sdhci"; reg = <0x0 0x700b0200 0x0 0x200>; interrupts = ; @@ -824,7 +829,7 @@ status = "disabled"; }; - sdhci@0,700b0400 { + sdhci@700b0400 { compatible = "nvidia,tegra124-sdhci"; reg = <0x0 0x700b0400 0x0 0x200>; interrupts = ; @@ -834,7 +839,7 @@ status = "disabled"; }; - sdhci@0,700b0600 { + sdhci@700b0600 { compatible = "nvidia,tegra124-sdhci"; reg = <0x0 0x700b0600 0x0 0x200>; interrupts = ; @@ -844,7 +849,7 @@ status = "disabled"; }; - soctherm: thermal-sensor@0,700e2000 { + soctherm: thermal-sensor@700e2000 { compatible = "nvidia,tegra124-soctherm"; reg = <0x0 0x700e2000 0x0 0x1000>; interrupts = ; @@ -856,7 +861,7 @@ #thermal-sensor-cells = <1>; }; - dfll: clock@0,70110000 { + dfll: clock@70110000 { compatible = "nvidia,tegra124-dfll"; reg = <0 0x70110000 0 0x100>, /* DFLL control */ <0 0x70110000 0 0x100>, /* I2C output control */ @@ -880,7 +885,7 @@ status = "disabled"; }; - ahub@0,70300000 { + ahub@70300000 { compatible = "nvidia,tegra124-ahub"; reg = <0x0 0x70300000 0x0 0x200>, <0x0 0x70300800 0x0 0x800>, @@ -932,7 +937,7 @@ #address-cells = <2>; #size-cells = <2>; - tegra_i2s0: i2s@0,70301000 { + tegra_i2s0: i2s@70301000 { compatible = "nvidia,tegra124-i2s"; reg = <0x0 0x70301000 0x0 0x100>; nvidia,ahub-cif-ids = <4 4>; @@ -942,7 +947,7 @@ status = "disabled"; }; - tegra_i2s1: i2s@0,70301100 { + tegra_i2s1: i2s@70301100 { compatible = "nvidia,tegra124-i2s"; reg = <0x0 0x70301100 0x0 0x100>; nvidia,ahub-cif-ids = <5 5>; @@ -952,7 +957,7 @@ status = "disabled"; }; - tegra_i2s2: i2s@0,70301200 { + tegra_i2s2: i2s@70301200 { compatible = "nvidia,tegra124-i2s"; reg = <0x0 0x70301200 0x0 0x100>; nvidia,ahub-cif-ids = <6 6>; @@ -962,7 +967,7 @@ status = "disabled"; }; - tegra_i2s3: i2s@0,70301300 { + tegra_i2s3: i2s@70301300 { compatible = "nvidia,tegra124-i2s"; reg = <0x0 0x70301300 0x0 0x100>; nvidia,ahub-cif-ids = <7 7>; @@ -972,7 +977,7 @@ status = "disabled"; }; - tegra_i2s4: i2s@0,70301400 { + tegra_i2s4: i2s@70301400 { compatible = "nvidia,tegra124-i2s"; reg = <0x0 0x70301400 0x0 0x100>; nvidia,ahub-cif-ids = <8 8>; @@ -983,7 +988,7 @@ }; }; - usb@0,7d000000 { + usb@7d000000 { compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci"; reg = <0x0 0x7d000000 0x0 0x4000>; interrupts = ; @@ -995,7 +1000,7 @@ status = "disabled"; }; - phy1: usb-phy@0,7d000000 { + phy1: usb-phy@7d000000 { compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; reg = <0x0 0x7d000000 0x0 0x4000>, <0x0 0x7d000000 0x0 0x4000>; @@ -1020,7 +1025,7 @@ status = "disabled"; }; - usb@0,7d004000 { + usb@7d004000 { compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci"; reg = <0x0 0x7d004000 0x0 0x4000>; interrupts = ; @@ -1032,7 +1037,7 @@ status = "disabled"; }; - phy2: usb-phy@0,7d004000 { + phy2: usb-phy@7d004000 { compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; reg = <0x0 0x7d004000 0x0 0x4000>, <0x0 0x7d000000 0x0 0x4000>; @@ -1056,7 +1061,7 @@ status = "disabled"; }; - usb@0,7d008000 { + usb@7d008000 { compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci"; reg = <0x0 0x7d008000 0x0 0x4000>; interrupts = ; @@ -1068,7 +1073,7 @@ status = "disabled"; }; - phy3: usb-phy@0,7d008000 { + phy3: usb-phy@7d008000 { compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; reg = <0x0 0x7d008000 0x0 0x4000>, <0x0 0x7d000000 0x0 0x4000>; -- cgit v0.10.2 From 85afd20e4bccc39f4eae01cb50e435ca45aef912 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Thu, 30 Jun 2016 00:23:17 +0200 Subject: ARM: tegra: Initial support for Apalis TK1 This patch adds the device tree to support Toradex Apalis TK1 a computer on module which can be used on different carrier boards. The module consists of a Tegra TK1 SoC, a PMIC solution, 2 GB of DDR3L RAM, a bunch of level shifters, an eMMC, a TMP451 temperature sensor chip, an I210 gigabit Ethernet controller and a SGTL5000 audio codec. Furthermore, there is a Kinetis MK20DN512 companion micro controller for analogue, CAN and resistive touch functionality which is not yet supported. Anything that is not self contained on the module is disabled by default. The device tree for the Evaluation Board includes the module's device tree and enables the supported peripherals of the carrier board (the Evaluation Board supports almost all of them). Signed-off-by: Marcel Ziswiler Signed-off-by: Thierry Reding diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 06b6c2d..3a13d4f 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -793,6 +793,7 @@ dtb-$(CONFIG_ARCH_TEGRA_114_SOC) += \ tegra114-roth.dtb \ tegra114-tn7.dtb dtb-$(CONFIG_ARCH_TEGRA_124_SOC) += \ + tegra124-apalis-eval.dtb \ tegra124-jetson-tk1.dtb \ tegra124-nyan-big.dtb \ tegra124-nyan-blaze.dtb \ diff --git a/arch/arm/boot/dts/tegra124-apalis-emc.dtsi b/arch/arm/boot/dts/tegra124-apalis-emc.dtsi new file mode 100644 index 0000000..ca2c3a5 --- /dev/null +++ b/arch/arm/boot/dts/tegra124-apalis-emc.dtsi @@ -0,0 +1,1502 @@ +/* + * Copyright 2016 Toradex AG + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/ { + clock@60006000 { + emc-timings-1 { + nvidia,ram-code = <1>; + + timing-12750000 { + clock-frequency = <12750000>; + nvidia,parent-clock-frequency = <408000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_P>; + clock-names = "emc-parent"; + }; + timing-20400000 { + clock-frequency = <20400000>; + nvidia,parent-clock-frequency = <408000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_P>; + clock-names = "emc-parent"; + }; + timing-40800000 { + clock-frequency = <40800000>; + nvidia,parent-clock-frequency = <408000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_P>; + clock-names = "emc-parent"; + }; + timing-68000000 { + clock-frequency = <68000000>; + nvidia,parent-clock-frequency = <408000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_P>; + clock-names = "emc-parent"; + }; + timing-102000000 { + clock-frequency = <102000000>; + nvidia,parent-clock-frequency = <408000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_P>; + clock-names = "emc-parent"; + }; + timing-204000000 { + clock-frequency = <204000000>; + nvidia,parent-clock-frequency = <408000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_P>; + clock-names = "emc-parent"; + }; + timing-300000000 { + clock-frequency = <300000000>; + nvidia,parent-clock-frequency = <600000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_C>; + clock-names = "emc-parent"; + }; + timing-396000000 { + clock-frequency = <396000000>; + nvidia,parent-clock-frequency = <792000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_M>; + clock-names = "emc-parent"; + }; + timing-528000000 { + clock-frequency = <528000000>; + nvidia,parent-clock-frequency = <528000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>; + clock-names = "emc-parent"; + }; + timing-600000000 { + clock-frequency = <600000000>; + nvidia,parent-clock-frequency = <600000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_C_UD>; + clock-names = "emc-parent"; + }; + timing-792000000 { + clock-frequency = <792000000>; + nvidia,parent-clock-frequency = <792000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>; + clock-names = "emc-parent"; + }; + timing-924000000 { + clock-frequency = <924000000>; + nvidia,parent-clock-frequency = <924000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>; + clock-names = "emc-parent"; + }; + }; + }; + + emc@7001b000 { + emc-timings-1 { + nvidia,ram-code = <1>; + + timing-12750000 { + clock-frequency = <12750000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-cfg = <0x73240000>; + nvidia,emc-cfg-2 = <0x000008c5>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-mrs-wait-cnt = <0x000e000e>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00000000>; + + nvidia,emc-configuration = < + 0x00000000 0x00000003 + 0x00000000 0x00000000 + 0x00000000 0x00000004 + 0x0000000a 0x00000005 + 0x0000000b 0x00000000 + 0x00000000 0x00000003 + 0x00000003 0x00000000 + 0x00000006 0x00000006 + 0x00000006 0x00000002 + 0x00000000 0x00000005 + 0x00000005 0x00010000 + 0x00000003 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000004 + 0x0000000c 0x0000000d + 0x0000000f 0x00000060 + 0x00000000 0x00000018 + 0x00000002 0x00000002 + 0x00000001 0x00000000 + 0x00000007 0x0000000f + 0x00000005 0x00000005 + 0x00000004 0x00000005 + 0x00000004 0x00000000 + 0x00000000 0x00000005 + 0x00000005 0x00000064 + 0x00000000 0x00000000 + 0x00000000 0x106aa298 + 0x002c00a0 0x00008000 + 0x00080000 0x00080000 + 0x00080000 0x00080000 + 0x00080000 0x00080000 + 0x00080000 0x00080000 + 0x00080000 0x00080000 + 0x00080000 0x00080000 + 0x00080000 0x00080000 + 0x00080000 0x00080000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 + 0x0000fc00 0x0000fc00 + 0x0000fc00 0x0000fc00 + 0x10000280 0x00000000 + 0x00111111 0x00000000 + 0x00000000 0x77ffc081 + 0x00000e0e 0x81f1f108 + 0x07070004 0x0000003f + 0x016eeeee 0x51451400 + 0x00514514 0x00514514 + 0x51451400 0x0000003f + 0x00000007 0x00000000 + 0x00000042 0x000e000e + 0x00000000 0x00000003 + 0x0000f2f3 0x800001c5 + 0x0000000a + >; + }; + + timing-20400000 { + clock-frequency = <20400000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-cfg = <0x73240000>; + nvidia,emc-cfg-2 = <0x000008c5>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-mrs-wait-cnt = <0x000e000e>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00000000>; + + nvidia,emc-configuration = < + 0x00000000 0x00000005 + 0x00000000 0x00000000 + 0x00000000 0x00000004 + 0x0000000a 0x00000005 + 0x0000000b 0x00000000 + 0x00000000 0x00000003 + 0x00000003 0x00000000 + 0x00000006 0x00000006 + 0x00000006 0x00000002 + 0x00000000 0x00000005 + 0x00000005 0x00010000 + 0x00000003 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000004 + 0x0000000c 0x0000000d + 0x0000000f 0x0000009a + 0x00000000 0x00000026 + 0x00000002 0x00000002 + 0x00000001 0x00000000 + 0x00000007 0x0000000f + 0x00000006 0x00000006 + 0x00000004 0x00000005 + 0x00000004 0x00000000 + 0x00000000 0x00000005 + 0x00000005 0x000000a0 + 0x00000000 0x00000000 + 0x00000000 0x106aa298 + 0x002c00a0 0x00008000 + 0x00080000 0x00080000 + 0x00080000 0x00080000 + 0x00080000 0x00080000 + 0x00080000 0x00080000 + 0x00080000 0x00080000 + 0x00080000 0x00080000 + 0x00080000 0x00080000 + 0x00080000 0x00080000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 + 0x0000fc00 0x0000fc00 + 0x0000fc00 0x0000fc00 + 0x10000280 0x00000000 + 0x00111111 0x00000000 + 0x00000000 0x77ffc081 + 0x00000e0e 0x81f1f108 + 0x07070004 0x0000003f + 0x016eeeee 0x51451400 + 0x00514514 0x00514514 + 0x51451400 0x0000003f + 0x0000000b 0x00000000 + 0x00000042 0x000e000e + 0x00000000 0x00000003 + 0x0000f2f3 0x8000023a + 0x0000000a + >; + }; + + timing-40800000 { + clock-frequency = <40800000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-cfg = <0x73240000>; + nvidia,emc-cfg-2 = <0x000008c5>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-mrs-wait-cnt = <0x000e000e>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00000000>; + + nvidia,emc-configuration = < + 0x00000001 0x0000000a + 0x00000000 0x00000001 + 0x00000000 0x00000004 + 0x0000000a 0x00000005 + 0x0000000b 0x00000000 + 0x00000000 0x00000003 + 0x00000003 0x00000000 + 0x00000006 0x00000006 + 0x00000006 0x00000002 + 0x00000000 0x00000005 + 0x00000005 0x00010000 + 0x00000003 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000004 + 0x0000000c 0x0000000d + 0x0000000f 0x00000134 + 0x00000000 0x0000004d + 0x00000002 0x00000002 + 0x00000001 0x00000000 + 0x00000008 0x0000000f + 0x0000000c 0x0000000c + 0x00000004 0x00000005 + 0x00000004 0x00000000 + 0x00000000 0x00000005 + 0x00000005 0x0000013f + 0x00000000 0x00000000 + 0x00000000 0x106aa298 + 0x002c00a0 0x00008000 + 0x00080000 0x00080000 + 0x00080000 0x00080000 + 0x00080000 0x00080000 + 0x00080000 0x00080000 + 0x00080000 0x00080000 + 0x00080000 0x00080000 + 0x00080000 0x00080000 + 0x00080000 0x00080000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 + 0x0000fc00 0x0000fc00 + 0x0000fc00 0x0000fc00 + 0x10000280 0x00000000 + 0x00111111 0x00000000 + 0x00000000 0x77ffc081 + 0x00000e0e 0x81f1f108 + 0x07070004 0x0000003f + 0x016eeeee 0x51451400 + 0x00514514 0x00514514 + 0x51451400 0x0000003f + 0x00000015 0x00000000 + 0x00000042 0x000e000e + 0x00000000 0x00000003 + 0x0000f2f3 0x80000370 + 0x0000000a + >; + }; + + timing-68000000 { + clock-frequency = <68000000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-cfg = <0x73240000>; + nvidia,emc-cfg-2 = <0x000008c5>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-mrs-wait-cnt = <0x000e000e>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00000000>; + + nvidia,emc-configuration = < + 0x00000003 0x00000011 + 0x00000000 0x00000002 + 0x00000000 0x00000004 + 0x0000000a 0x00000005 + 0x0000000b 0x00000000 + 0x00000000 0x00000003 + 0x00000003 0x00000000 + 0x00000006 0x00000006 + 0x00000006 0x00000002 + 0x00000000 0x00000005 + 0x00000005 0x00010000 + 0x00000003 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000004 + 0x0000000c 0x0000000d + 0x0000000f 0x00000202 + 0x00000000 0x00000080 + 0x00000002 0x00000002 + 0x00000001 0x00000000 + 0x0000000f 0x0000000f + 0x00000013 0x00000013 + 0x00000004 0x00000005 + 0x00000004 0x00000001 + 0x00000000 0x00000005 + 0x00000005 0x00000213 + 0x00000000 0x00000000 + 0x00000000 0x106aa298 + 0x002c00a0 0x00008000 + 0x00080000 0x00080000 + 0x00080000 0x00080000 + 0x00080000 0x00080000 + 0x00080000 0x00080000 + 0x00080000 0x00080000 + 0x00080000 0x00080000 + 0x00080000 0x00080000 + 0x00080000 0x00080000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 + 0x0000fc00 0x0000fc00 + 0x0000fc00 0x0000fc00 + 0x10000280 0x00000000 + 0x00111111 0x00000000 + 0x00000000 0x77ffc081 + 0x00000e0e 0x81f1f108 + 0x07070004 0x0000003f + 0x016eeeee 0x51451400 + 0x00514514 0x00514514 + 0x51451400 0x0000003f + 0x00000022 0x00000000 + 0x00000042 0x000e000e + 0x00000000 0x00000003 + 0x0000f2f3 0x8000050e + 0x0000000a + >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-cfg = <0x73240000>; + nvidia,emc-cfg-2 = <0x000008c5>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-mrs-wait-cnt = <0x000e000e>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00000000>; + + nvidia,emc-configuration = < + 0x00000004 0x0000001a + 0x00000000 0x00000003 + 0x00000001 0x00000004 + 0x0000000a 0x00000005 + 0x0000000b 0x00000001 + 0x00000001 0x00000003 + 0x00000003 0x00000000 + 0x00000006 0x00000006 + 0x00000006 0x00000002 + 0x00000000 0x00000005 + 0x00000005 0x00010000 + 0x00000003 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000004 + 0x0000000c 0x0000000d + 0x0000000f 0x00000304 + 0x00000000 0x000000c1 + 0x00000002 0x00000002 + 0x00000001 0x00000000 + 0x00000018 0x0000000f + 0x0000001c 0x0000001c + 0x00000004 0x00000005 + 0x00000004 0x00000002 + 0x00000000 0x00000005 + 0x00000005 0x0000031c + 0x00000000 0x00000000 + 0x00000000 0x106aa298 + 0x002c00a0 0x00008000 + 0x00080000 0x00080000 + 0x00080000 0x00080000 + 0x00080000 0x00080000 + 0x00080000 0x00080000 + 0x00080000 0x00080000 + 0x00080000 0x00080000 + 0x00080000 0x00080000 + 0x00080000 0x00080000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 + 0x0000fc00 0x0000fc00 + 0x0000fc00 0x0000fc00 + 0x10000280 0x00000000 + 0x00111111 0x00000000 + 0x00000000 0x77ffc081 + 0x00000e0e 0x81f1f108 + 0x07070004 0x0000003f + 0x016eeeee 0x51451400 + 0x00514514 0x00514514 + 0x51451400 0x0000003f + 0x00000033 0x00000000 + 0x00000042 0x000e000e + 0x00000000 0x00000003 + 0x0000f2f3 0x80000713 + 0x0000000a + >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-cfg = <0x73240000>; + nvidia,emc-cfg-2 = <0x000008cd>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-mrs-wait-cnt = <0x000e000e>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00020000>; + + nvidia,emc-configuration = < + 0x00000009 0x00000035 + 0x00000000 0x00000006 + 0x00000002 0x00000005 + 0x0000000a 0x00000005 + 0x0000000b 0x00000002 + 0x00000002 0x00000003 + 0x00000003 0x00000000 + 0x00000005 0x00000005 + 0x00000006 0x00000002 + 0x00000000 0x00000004 + 0x00000006 0x00010000 + 0x00000003 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000003 + 0x0000000d 0x0000000f + 0x00000011 0x00000607 + 0x00000000 0x00000181 + 0x00000002 0x00000002 + 0x00000001 0x00000000 + 0x00000032 0x0000000f + 0x00000038 0x00000038 + 0x00000004 0x00000005 + 0x00000004 0x00000006 + 0x00000000 0x00000005 + 0x00000005 0x00000638 + 0x00000000 0x00000000 + 0x00000000 0x106aa298 + 0x002c00a0 0x00008000 + 0x00080000 0x00080000 + 0x00080000 0x00080000 + 0x00080000 0x00080000 + 0x00080000 0x00080000 + 0x00080000 0x00080000 + 0x00080000 0x00080000 + 0x00080000 0x00080000 + 0x00080000 0x00080000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00008000 0x00000000 + 0x00000000 0x00008000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00090000 0x00090000 + 0x00090000 0x00090000 + 0x00009000 0x00009000 + 0x00009000 0x00009000 + 0x10000280 0x00000000 + 0x00111111 0x00000000 + 0x00000000 0x77ffc081 + 0x00000707 0x81f1f108 + 0x07070004 0x0000003f + 0x016eeeee 0x51451400 + 0x00514514 0x00514514 + 0x51451400 0x0000003f + 0x00000066 0x00000000 + 0x00000100 0x000e000e + 0x00000000 0x00000003 + 0x0000d2b3 0x80000d22 + 0x0000000a + >; + }; + + timing-300000000 { + clock-frequency = <300000000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000000>; + nvidia,emc-cfg = <0x73340000>; + nvidia,emc-cfg-2 = <0x000008d5>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200000>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80000321>; + nvidia,emc-mrs-wait-cnt = <0x0173000e>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-xm2dqspadctrl2 = <0x01231339>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00020000>; + + nvidia,emc-configuration = < + 0x0000000d 0x0000004d + 0x00000000 0x00000009 + 0x00000003 0x00000004 + 0x00000008 0x00000002 + 0x00000009 0x00000003 + 0x00000003 0x00000002 + 0x00000002 0x00000000 + 0x00000003 0x00000003 + 0x00000005 0x00000002 + 0x00000000 0x00000002 + 0x00000007 0x00020000 + 0x00000003 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000001 + 0x0000000e 0x00000010 + 0x00000012 0x000008e4 + 0x00000000 0x00000239 + 0x00000001 0x00000008 + 0x00000001 0x00000000 + 0x0000004b 0x0000000e + 0x00000052 0x00000200 + 0x00000004 0x00000005 + 0x00000004 0x00000008 + 0x00000000 0x00000005 + 0x00000005 0x00000924 + 0x00000000 0x00000000 + 0x00000000 0x104ab098 + 0x002c00a0 0x00008000 + 0x00030000 0x00030000 + 0x00030000 0x00030000 + 0x00030000 0x00030000 + 0x00030000 0x00030000 + 0x00030000 0x00030000 + 0x00030000 0x00030000 + 0x00030000 0x00030000 + 0x00030000 0x00030000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00098000 0x00098000 + 0x00000000 0x00098000 + 0x00098000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00050000 0x00050000 + 0x00050000 0x00050000 + 0x00005000 0x00005000 + 0x00005000 0x00005000 + 0x10000280 0x00000000 + 0x00111111 0x00000000 + 0x00000000 0x77ffc081 + 0x00000505 0x81f1f108 + 0x07070004 0x00000000 + 0x016eeeee 0x51451420 + 0x00514514 0x00514514 + 0x51451400 0x0000003f + 0x00000096 0x00000000 + 0x00000100 0x0173000e + 0x00000000 0x00000003 + 0x000052a3 0x800012d7 + 0x00000009 + >; + }; + + timing-396000000 { + clock-frequency = <396000000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000000>; + nvidia,emc-cfg = <0x73340000>; + nvidia,emc-cfg-2 = <0x00000895>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200000>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80000521>; + nvidia,emc-mrs-wait-cnt = <0x015b000e>; + nvidia,emc-sel-dpd-ctrl = <0x00040008>; + nvidia,emc-xm2dqspadctrl2 = <0x01231339>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00020000>; + + nvidia,emc-configuration = < + 0x00000011 0x00000066 + 0x00000000 0x0000000c + 0x00000004 0x00000004 + 0x00000008 0x00000002 + 0x0000000a 0x00000004 + 0x00000004 0x00000002 + 0x00000002 0x00000000 + 0x00000003 0x00000003 + 0x00000005 0x00000002 + 0x00000000 0x00000001 + 0x00000008 0x00020000 + 0x00000003 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x0000000f 0x00000010 + 0x00000012 0x00000bd1 + 0x00000000 0x000002f4 + 0x00000001 0x00000008 + 0x00000001 0x00000000 + 0x00000063 0x0000000f + 0x0000006c 0x00000200 + 0x00000004 0x00000005 + 0x00000004 0x0000000b + 0x00000000 0x00000005 + 0x00000005 0x00000c11 + 0x00000000 0x00000000 + 0x00000000 0x104ab098 + 0x002c00a0 0x00008000 + 0x00030000 0x00030000 + 0x00030000 0x00030000 + 0x00030000 0x00030000 + 0x00030000 0x00030000 + 0x00030000 0x00030000 + 0x00030000 0x00030000 + 0x00030000 0x00030000 + 0x00030000 0x00030000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00070000 0x00070000 + 0x00000000 0x00070000 + 0x00070000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00038000 0x00038000 + 0x00038000 0x00038000 + 0x00003800 0x00003800 + 0x00003800 0x00003800 + 0x10000280 0x00000000 + 0x00111111 0x00000000 + 0x00000000 0x77ffc081 + 0x00000505 0x81f1f108 + 0x07070004 0x00000000 + 0x016eeeee 0x51451420 + 0x00514514 0x00514514 + 0x51451400 0x0000003f + 0x000000c6 0x00000000 + 0x00000100 0x015b000e + 0x00000000 0x00000003 + 0x000052a3 0x8000188b + 0x00000009 + >; + }; + + timing-528000000 { + clock-frequency = <528000000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000000>; + nvidia,emc-cfg = <0x73300000>; + nvidia,emc-cfg-2 = <0x0000089d>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80000941>; + nvidia,emc-mrs-wait-cnt = <0x0139000e>; + nvidia,emc-sel-dpd-ctrl = <0x00040008>; + nvidia,emc-xm2dqspadctrl2 = <0x0123133d>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00020000>; + + nvidia,emc-configuration = < + 0x00000018 0x00000088 + 0x00000000 0x00000010 + 0x00000006 0x00000006 + 0x00000009 0x00000002 + 0x0000000d 0x00000006 + 0x00000006 0x00000002 + 0x00000002 0x00000000 + 0x00000003 0x00000003 + 0x00000006 0x00000002 + 0x00000000 0x00000001 + 0x00000009 0x00030000 + 0x00000003 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000010 0x00000012 + 0x00000014 0x00000fd6 + 0x00000000 0x000003f5 + 0x00000002 0x0000000b + 0x00000001 0x00000000 + 0x00000085 0x00000012 + 0x00000090 0x00000200 + 0x00000004 0x00000005 + 0x00000004 0x00000010 + 0x00000000 0x00000006 + 0x00000006 0x00001017 + 0x00000000 0x00000000 + 0x00000000 0x104ab098 + 0xe01200b1 0x00008000 + 0x0000000a 0x0000000a + 0x0000000a 0x0000000a + 0x0000000a 0x0000000a + 0x0000000a 0x0000000a + 0x0000000a 0x0000000a + 0x0000000a 0x0000000a + 0x0000000a 0x0000000a + 0x0000000a 0x0000000a + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00054000 0x00054000 + 0x00000000 0x00054000 + 0x00054000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x0000000c 0x0000000c + 0x0000000c 0x0000000c + 0x0000000c 0x0000000c + 0x0000000c 0x0000000c + 0x100002a0 0x00000000 + 0x00111111 0x00000000 + 0x00000000 0x77ffc085 + 0x00000505 0x81f1f108 + 0x07070004 0x00000000 + 0x016eeeee 0x51451420 + 0x00514514 0x00514514 + 0x51451400 0x0606003f + 0x00000000 0x00000000 + 0x00000100 0x0139000e + 0x00000000 0x00000003 + 0x000042a0 0x80002062 + 0x0000000a + >; + }; + + timing-600000000 { + clock-frequency = <600000000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000000>; + nvidia,emc-cfg = <0x73300000>; + nvidia,emc-cfg-2 = <0x0000089d>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200010>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80000b61>; + nvidia,emc-mrs-wait-cnt = <0x0127000e>; + nvidia,emc-sel-dpd-ctrl = <0x00040008>; + nvidia,emc-xm2dqspadctrl2 = <0x0121113d>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00020000>; + + nvidia,emc-configuration = < + 0x0000001b 0x0000009b + 0x00000000 0x00000013 + 0x00000007 0x00000007 + 0x0000000b 0x00000003 + 0x00000010 0x00000007 + 0x00000007 0x00000002 + 0x00000002 0x00000000 + 0x00000005 0x00000005 + 0x0000000a 0x00000002 + 0x00000000 0x00000003 + 0x0000000b 0x00070000 + 0x00000003 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000002 + 0x00000012 0x00000016 + 0x00000018 0x00001208 + 0x00000000 0x00000482 + 0x00000002 0x0000000d + 0x00000001 0x00000000 + 0x00000097 0x00000015 + 0x000000a3 0x00000200 + 0x00000004 0x00000005 + 0x00000004 0x00000013 + 0x00000000 0x00000006 + 0x00000006 0x00001248 + 0x00000000 0x00000000 + 0x00000000 0x104ab098 + 0xe00e00b1 0x00008000 + 0x0000000a 0x0000000a + 0x0000000a 0x0000000a + 0x0000000a 0x0000000a + 0x0000000a 0x0000000a + 0x0000000a 0x0000000a + 0x0000000a 0x0000000a + 0x0000000a 0x0000000a + 0x0000000a 0x0000000a + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00048000 0x00048000 + 0x00000000 0x00048000 + 0x00048000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x0000000d 0x0000000d + 0x0000000d 0x0000000d + 0x0000000d 0x0000000d + 0x0000000d 0x0000000d + 0x100002a0 0x00000000 + 0x00111111 0x00000000 + 0x00000000 0x77ffc085 + 0x00000505 0x81f1f108 + 0x07070004 0x00000000 + 0x016eeeee 0x51451420 + 0x00514514 0x00514514 + 0x51451400 0x0606003f + 0x00000000 0x00000000 + 0x00000100 0x0127000e + 0x00000000 0x00000003 + 0x000040a0 0x800024aa + 0x0000000e + >; + }; + + timing-792000000 { + clock-frequency = <792000000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000000>; + nvidia,emc-cfg = <0x73300000>; + nvidia,emc-cfg-2 = <0x0000089d>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200018>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80000d71>; + nvidia,emc-mrs-wait-cnt = <0x00f7000e>; + nvidia,emc-sel-dpd-ctrl = <0x00040000>; + nvidia,emc-xm2dqspadctrl2 = <0x0120113d>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00020000>; + + nvidia,emc-configuration = < + 0x00000024 0x000000cd + 0x00000000 0x00000019 + 0x0000000a 0x00000008 + 0x0000000d 0x00000004 + 0x00000013 0x0000000a + 0x0000000a 0x00000004 + 0x00000002 0x00000000 + 0x00000006 0x00000006 + 0x0000000b 0x00000002 + 0x00000000 0x00000002 + 0x0000000d 0x00080000 + 0x00000004 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000001 + 0x00000014 0x00000018 + 0x0000001a 0x000017e2 + 0x00000000 0x000005f8 + 0x00000003 0x00000011 + 0x00000001 0x00000000 + 0x000000c7 0x00000018 + 0x000000d7 0x00000200 + 0x00000005 0x00000006 + 0x00000005 0x00000019 + 0x00000000 0x00000008 + 0x00000008 0x00001822 + 0x00000000 0x00000000 + 0x00000000 0x104ab098 + 0xe00700b1 0x00008000 + 0x007fc008 0x007fc008 + 0x007fc008 0x007fc008 + 0x007fc008 0x007fc008 + 0x007fc008 0x007fc008 + 0x007fc008 0x007fc008 + 0x007fc008 0x007fc008 + 0x007fc008 0x007fc008 + 0x007fc008 0x007fc008 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00034000 0x00034000 + 0x00000000 0x00034000 + 0x00034000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000005 0x00000005 + 0x00000005 0x00000005 + 0x00000005 0x00000005 + 0x00000005 0x00000005 + 0x00000005 0x00000005 + 0x00000005 0x00000005 + 0x00000005 0x00000005 + 0x00000005 0x00000005 + 0x0000000a 0x0000000a + 0x0000000a 0x0000000a + 0x0000000a 0x0000000a + 0x0000000a 0x0000000a + 0x100002a0 0x00000000 + 0x00111111 0x00000000 + 0x00000000 0x77ffc085 + 0x00000000 0x81f1f108 + 0x07070004 0x00000000 + 0x016eeeee 0x61861820 + 0x00514514 0x00514514 + 0x61861800 0x0606003f + 0x00000000 0x00000000 + 0x00000100 0x00f7000e + 0x00000000 0x00000004 + 0x00004080 0x80003012 + 0x0000000f + >; + }; + + timing-924000000 { + clock-frequency = <924000000>; + + nvidia,emc-auto-cal-config = <0xa1430303>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000000>; + nvidia,emc-cfg = <0x73300000>; + nvidia,emc-cfg-2 = <0x0000089d>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200020>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80000f15>; + nvidia,emc-mrs-wait-cnt = <0x00cd000e>; + nvidia,emc-sel-dpd-ctrl = <0x00040000>; + nvidia,emc-xm2dqspadctrl2 = <0x0120113d>; + nvidia,emc-zcal-cnt-long = <0x0000004c>; + nvidia,emc-zcal-interval = <0x00020000>; + + nvidia,emc-configuration = < + 0x0000002b 0x000000f0 + 0x00000000 0x0000001e + 0x0000000b 0x00000009 + 0x0000000f 0x00000005 + 0x00000016 0x0000000b + 0x0000000b 0x00000004 + 0x00000002 0x00000000 + 0x00000007 0x00000007 + 0x0000000d 0x00000002 + 0x00000000 0x00000002 + 0x0000000f 0x000a0000 + 0x00000004 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000001 + 0x00000016 0x0000001a + 0x0000001c 0x00001be7 + 0x00000000 0x000006f9 + 0x00000004 0x00000015 + 0x00000001 0x00000000 + 0x000000e7 0x0000001b + 0x000000fb 0x00000200 + 0x00000006 0x00000007 + 0x00000006 0x0000001e + 0x00000000 0x0000000a + 0x0000000a 0x00001c28 + 0x00000000 0x00000000 + 0x00000000 0x104ab898 + 0xe00400b1 0x00008000 + 0x007f800a 0x007f800a + 0x007f800a 0x007f800a + 0x007f800a 0x007f800a + 0x007f800a 0x007f800a + 0x007f800a 0x007f800a + 0x007f800a 0x007f800a + 0x007f800a 0x007f800a + 0x007f800a 0x007f800a + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x0002c000 0x0002c000 + 0x00000000 0x0002c000 + 0x0002c000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000000 0x00000000 + 0x00000004 0x00000004 + 0x00000004 0x00000004 + 0x00000004 0x00000004 + 0x00000004 0x00000004 + 0x00000004 0x00000004 + 0x00000004 0x00000004 + 0x00000004 0x00000004 + 0x00000004 0x00000004 + 0x00000008 0x00000008 + 0x00000008 0x00000008 + 0x00000008 0x00000008 + 0x00000008 0x00000008 + 0x100002a0 0x00000000 + 0x00111111 0x00000000 + 0x00000000 0x77ffc085 + 0x00000000 0x81f1f108 + 0x07070004 0x00000000 + 0x016eeeee 0x5d75d720 + 0x00514514 0x00514514 + 0x5d75d700 0x0606003f + 0x00000000 0x00000000 + 0x00000128 0x00cd000e + 0x00000000 0x00000004 + 0x00004080 0x800037ea + 0x00000011 + >; + }; + + }; + }; + + memory-controller@70019000 { + emc-timings-1 { + nvidia,ram-code = <1>; + + timing-12750000 { + clock-frequency = <12750000>; + + nvidia,emem-configuration = < + 0x40040001 0x8000000a + 0x00000001 0x00000001 + 0x00000002 0x00000000 + 0x00000002 0x00000001 + 0x00000003 0x00000008 + 0x00000003 0x00000002 + 0x00000003 0x00000006 + 0x06030203 0x000a0502 + 0x77e30303 0x70000f03 + 0x001f0000 + >; + }; + + timing-20400000 { + clock-frequency = <20400000>; + + nvidia,emem-configuration = < + 0x40020001 0x80000012 + 0x00000001 0x00000001 + 0x00000002 0x00000000 + 0x00000002 0x00000001 + 0x00000003 0x00000008 + 0x00000003 0x00000002 + 0x00000003 0x00000006 + 0x06030203 0x000a0502 + 0x76230303 0x70000f03 + 0x001f0000 + >; + }; + + timing-40800000 { + clock-frequency = <40800000>; + + nvidia,emem-configuration = < + 0xa0000001 0x80000017 + 0x00000001 0x00000001 + 0x00000002 0x00000000 + 0x00000002 0x00000001 + 0x00000003 0x00000008 + 0x00000003 0x00000002 + 0x00000003 0x00000006 + 0x06030203 0x000a0502 + 0x74a30303 0x70000f03 + 0x001f0000 + >; + }; + + timing-68000000 { + clock-frequency = <68000000>; + + nvidia,emem-configuration = < + 0x00000001 0x8000001e + 0x00000001 0x00000001 + 0x00000002 0x00000000 + 0x00000002 0x00000001 + 0x00000003 0x00000008 + 0x00000003 0x00000002 + 0x00000003 0x00000006 + 0x06030203 0x000a0502 + 0x74230403 0x70000f03 + 0x001f0000 + >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emem-configuration = < + 0x08000001 0x80000026 + 0x00000001 0x00000001 + 0x00000003 0x00000000 + 0x00000002 0x00000001 + 0x00000003 0x00000008 + 0x00000003 0x00000002 + 0x00000003 0x00000006 + 0x06030203 0x000a0503 + 0x73c30504 0x70000f03 + 0x001f0000 + >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emem-configuration = < + 0x01000003 0x80000040 + 0x00000001 0x00000001 + 0x00000004 0x00000002 + 0x00000003 0x00000001 + 0x00000003 0x00000008 + 0x00000003 0x00000002 + 0x00000004 0x00000006 + 0x06040203 0x000a0504 + 0x73840a05 0x70000f03 + 0x001f0000 + >; + }; + + timing-300000000 { + clock-frequency = <300000000>; + + nvidia,emem-configuration = < + 0x08000004 0x80000040 + 0x00000001 0x00000002 + 0x00000007 0x00000004 + 0x00000004 0x00000001 + 0x00000002 0x00000007 + 0x00000002 0x00000002 + 0x00000004 0x00000006 + 0x06040202 0x000b0607 + 0x77450e08 0x70000f03 + 0x001f0000 + >; + }; + + timing-396000000 { + clock-frequency = <396000000>; + + nvidia,emem-configuration = < + 0x0f000005 0x80000040 + 0x00000001 0x00000002 + 0x00000009 0x00000005 + 0x00000006 0x00000001 + 0x00000002 0x00000008 + 0x00000002 0x00000002 + 0x00000004 0x00000006 + 0x06040202 0x000d0709 + 0x7586120a 0x70000f03 + 0x001f0000 + >; + }; + + timing-528000000 { + clock-frequency = <528000000>; + + nvidia,emem-configuration = < + 0x0f000007 0x80000040 + 0x00000002 0x00000003 + 0x0000000c 0x00000007 + 0x00000008 0x00000001 + 0x00000002 0x00000009 + 0x00000002 0x00000002 + 0x00000005 0x00000006 + 0x06050202 0x0010090c + 0x7428180d 0x70000f03 + 0x001f0000 + >; + }; + + timing-600000000 { + clock-frequency = <600000000>; + + nvidia,emem-configuration = < + 0x00000009 0x80000040 + 0x00000003 0x00000004 + 0x0000000e 0x00000009 + 0x0000000a 0x00000001 + 0x00000003 0x0000000b + 0x00000002 0x00000002 + 0x00000005 0x00000007 + 0x07050202 0x00130b0e + 0x73a91b0f 0x70000f03 + 0x001f0000 + >; + }; + + timing-792000000 { + clock-frequency = <792000000>; + + nvidia,emem-configuration = < + 0x0e00000b 0x80000040 + 0x00000004 0x00000005 + 0x00000013 0x0000000c + 0x0000000d 0x00000002 + 0x00000003 0x0000000c + 0x00000002 0x00000002 + 0x00000006 0x00000008 + 0x08060202 0x00170e13 + 0x736c2414 0x70000f02 + 0x001f0000 + >; + }; + + timing-924000000 { + clock-frequency = <924000000>; + + nvidia,emem-configuration = < + 0x0e00000d 0x80000040 + 0x00000005 0x00000006 + 0x00000016 0x0000000e + 0x0000000f 0x00000002 + 0x00000004 0x0000000e + 0x00000002 0x00000002 + 0x00000006 0x00000009 + 0x09060202 0x001a1016 + 0x734e2a17 0x70000f02 + 0x001f0000 + >; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/tegra124-apalis-eval.dts b/arch/arm/boot/dts/tegra124-apalis-eval.dts new file mode 100644 index 0000000..653044a --- /dev/null +++ b/arch/arm/boot/dts/tegra124-apalis-eval.dts @@ -0,0 +1,284 @@ +/* + * Copyright 2016 Toradex AG + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include +#include "tegra124-apalis.dtsi" + +/ { + model = "Toradex Apalis TK1 on Apalis Evaluation Board"; + compatible = "toradex,apalis-tk1-eval", "toradex,apalis-tk1", + "nvidia,tegra124"; + + aliases { + rtc0 = "/i2c@7000c000/rtc@68"; + rtc1 = "/i2c@7000d000/pmic@40"; + rtc2 = "/rtc@7000e000"; + serial0 = &uarta; + serial1 = &uartb; + serial2 = &uartc; + serial3 = &uartd; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + pcie-controller@01003000 { + pci@1,0 { + status = "okay"; + }; + }; + + host1x@50000000 { + hdmi@54280000 { + status = "okay"; + }; + }; + + /* Apalis UART1 */ + serial@70006000 { + status = "okay"; + }; + + /* Apalis UART2 */ + serial@70006040 { + status = "okay"; + }; + + /* Apalis UART3 */ + serial@70006200 { + status = "okay"; + }; + + /* Apalis UART4 */ + serial@70006300 { + status = "okay"; + }; + + pwm@7000a000 { + status = "okay"; + }; + + /* + * GEN1_I2C: I2C1_SDA/SCL on MXM3 pin 209/211 (e.g. RTC on carrier + * board) + */ + i2c@7000c000 { + status = "okay"; + clock-frequency = <100000>; + + pcie-switch@58 { + compatible = "plx,pex8605"; + reg = <0x58>; + }; + + /* M41T0M6 real time clock on carrier board */ + rtc@68 { + compatible = "st,m41t00"; + reg = <0x68>; + }; + }; + + /* + * GEN2_I2C: I2C2_SDA/SCL (DDC) on MXM3 pin 205/207 (e.g. display EDID) + */ + hdmi_ddc: i2c@7000c400 { + status = "okay"; + clock-frequency = <100000>; + }; + + /* + * CAM_I2C: I2C3_SDA/SCL (CAM) on MXM3 pin 201/203 (e.g. camera sensor + * on carrier board) + */ + i2c@7000c500 { + status = "okay"; + clock-frequency = <100000>; + }; + + /* I2C4 (DDC): unused */ + + /* SPI1: Apalis SPI1 */ + spi@7000d400 { + status = "okay"; + spi-max-frequency = <50000000>; + + spidev0: spidev@0 { + compatible = "spidev"; + reg = <0>; + spi-max-frequency = <50000000>; + }; + }; + + /* SPI4: Apalis SPI2 */ + spi@7000da00 { + status = "okay"; + spi-max-frequency = <50000000>; + + spidev1: spidev@0 { + compatible = "spidev"; + reg = <0>; + spi-max-frequency = <50000000>; + }; + }; + + /* Apalis Serial ATA */ + sata@70020000 { + status = "okay"; + }; + + hda@70030000 { + status = "okay"; + }; + + usb@70090000 { + status = "okay"; + }; + + /* Apalis MMC1 */ + sdhci@700b0000 { + status = "okay"; + /* MMC1_CD# */ + cd-gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_LOW>; + bus-width = <4>; + vqmmc-supply = <&vddio_sdmmc1>; + }; + + /* Apalis SD1 */ + sdhci@700b0400 { + status = "okay"; + /* + * Don't use SD1_CD# aka SDMMC3_CLK_LB_OUT for now as it + * features some magic properties even though the external + * loopback is disabled and the internal loopback used as per + * SDMMC_VENDOR_MISC_CNTRL_0 register's SDMMC_SPARE1 bits being + * set to 0xfffd according to the TRM! + * cd-gpios = <&gpio TEGRA_GPIO(EE, 4) GPIO_ACTIVE_LOW>; + */ + bus-width = <4>; + vqmmc-supply = <&vddio_sdmmc3>; + }; + + /* EHCI instance 0: USB1_DP/N -> USBO1_DP/N */ + usb@7d000000 { + status = "okay"; + dr_mode = "otg"; + }; + + usb-phy@7d000000 { + status = "okay"; + vbus-supply = <®_usbo1_vbus>; + }; + + /* EHCI instance 1: USB2_DP/N -> USBH2_DP/N */ + usb@7d004000 { + status = "okay"; + }; + + usb-phy@7d004000 { + status = "okay"; + vbus-supply = <®_usbh_vbus>; + }; + + /* EHCI instance 2: USB3_DP/N -> USBH4_DP/N */ + usb@7d008000 { + status = "okay"; + }; + + usb-phy@7d008000 { + status = "okay"; + vbus-supply = <®_usbh_vbus>; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + + /* BKL1_PWM */ + pwms = <&pwm 3 5000000>; + brightness-levels = <255 231 223 207 191 159 127 0>; + default-brightness-level = <6>; + /* BKL1_ON */ + enable-gpios = <&gpio TEGRA_GPIO(BB, 5) GPIO_ACTIVE_HIGH>; + }; + + gpio-keys { + compatible = "gpio-keys"; + + wakeup { + label = "WAKE1_MICO"; + gpios = <&gpio TEGRA_GPIO(DD, 3) GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <10>; + wakeup-source; + }; + }; + + reg_5v0: regulator-5v0 { + compatible = "regulator-fixed"; + regulator-name = "5V_SW"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + /* USBO1_EN */ + reg_usbo1_vbus: regulator-usbo1-vbus { + compatible = "regulator-fixed"; + regulator-name = "VCC_USBO1"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_5v0>; + }; + + /* USBH_EN */ + reg_usbh_vbus: regulator-usbh-vbus { + compatible = "regulator-fixed"; + regulator-name = "VCC_USBH(2A|2C|2D|3|4)"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_5v0>; + }; +}; diff --git a/arch/arm/boot/dts/tegra124-apalis.dtsi b/arch/arm/boot/dts/tegra124-apalis.dtsi new file mode 100644 index 0000000..e7a73db --- /dev/null +++ b/arch/arm/boot/dts/tegra124-apalis.dtsi @@ -0,0 +1,2100 @@ +/* + * Copyright 2016 Toradex AG + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "tegra124.dtsi" +#include "tegra124-apalis-emc.dtsi" + +/* + * Toradex Apalis TK1 Module Device Tree + * Compatible for Revisions 2GB: V1.0A + */ +/ { + model = "Toradex Apalis TK1"; + compatible = "toradex,apalis-tk1", "nvidia,tegra124"; + + memory { + reg = <0x0 0x80000000 0x0 0x80000000>; + }; + + pcie-controller@01003000 { + status = "okay"; + + avddio-pex-supply = <&vdd_1v05>; + avdd-pex-pll-supply = <&vdd_1v05>; + avdd-pll-erefe-supply = <&avdd_1v05>; + dvddio-pex-supply = <&vdd_1v05>; + hvdd-pex-pll-e-supply = <®_3v3>; + hvdd-pex-supply = <®_3v3>; + vddio-pex-ctl-supply = <®_3v3>; + + /* Apalis PCIe (additional lane Apalis type specific) */ + pci@1,0 { + /* PCIE1_RX/TX and TS_DIFF1/2 */ + phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-4}>, + <&{/padctl@7009f000/pads/pcie/lanes/pcie-3}>; + phy-names = "pcie-0", "pcie-1"; + }; + + /* I210 Gigabit Ethernet Controller (On-module) */ + pci@2,0 { + phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-2}>; + phy-names = "pcie-0"; + status = "okay"; + }; + }; + + host1x@50000000 { + hdmi@54280000 { + pll-supply = <®_1v05_avdd_hdmi_pll>; + vdd-supply = <®_3v3_avdd_hdmi>; + + nvidia,ddc-i2c-bus = <&hdmi_ddc>; + nvidia,hpd-gpio = + <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; + }; + }; + + gpu@0,57000000 { + /* + * Node left disabled on purpose - the bootloader will enable + * it after having set the VPR up + */ + vdd-supply = <&vdd_gpu>; + }; + + pinmux: pinmux@70000868 { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + /* Analogue Audio (On-module) */ + dap3_fs_pp0 { + nvidia,pins = "dap3_fs_pp0"; + nvidia,function = "i2s2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap3_din_pp1 { + nvidia,pins = "dap3_din_pp1"; + nvidia,function = "i2s2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap3_dout_pp2 { + nvidia,pins = "dap3_dout_pp2"; + nvidia,function = "i2s2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap3_sclk_pp3 { + nvidia,pins = "dap3_sclk_pp3"; + nvidia,function = "i2s2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap_mclk1_pw4 { + nvidia,pins = "dap_mclk1_pw4"; + nvidia,function = "extperiph1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Apalis BKL1_ON */ + pbb5 { + nvidia,pins = "pbb5"; + nvidia,function = "vgp5"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Apalis BKL1_PWM */ + pu6 { + nvidia,pins = "pu6"; + nvidia,function = "pwm3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Apalis CAM1_MCLK */ + cam_mclk_pcc0 { + nvidia,pins = "cam_mclk_pcc0"; + nvidia,function = "vi_alt3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Apalis Digital Audio */ + dap2_fs_pa2 { + nvidia,pins = "dap2_fs_pa2"; + nvidia,function = "hda"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap2_sclk_pa3 { + nvidia,pins = "dap2_sclk_pa3"; + nvidia,function = "hda"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap2_din_pa4 { + nvidia,pins = "dap2_din_pa4"; + nvidia,function = "hda"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap2_dout_pa5 { + nvidia,pins = "dap2_dout_pa5"; + nvidia,function = "hda"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pbb3 { /* DAP1_RESET */ + nvidia,pins = "pbb3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + clk3_out_pee0 { + nvidia,pins = "clk3_out_pee0"; + nvidia,function = "extperiph3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Apalis GPIO */ + ddc_scl_pv4 { + nvidia,pins = "ddc_scl_pv4"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ddc_sda_pv5 { + nvidia,pins = "ddc_sda_pv5"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pex_l0_rst_n_pdd1 { + nvidia,pins = "pex_l0_rst_n_pdd1"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pex_l0_clkreq_n_pdd2 { + nvidia,pins = "pex_l0_clkreq_n_pdd2"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pex_l1_rst_n_pdd5 { + nvidia,pins = "pex_l1_rst_n_pdd5"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pex_l1_clkreq_n_pdd6 { + nvidia,pins = "pex_l1_clkreq_n_pdd6"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dp_hpd_pff0 { + nvidia,pins = "dp_hpd_pff0"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pff2 { + nvidia,pins = "pff2"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + owr { /* PEX_L1_CLKREQ_N multiplexed GPIO6 */ + nvidia,pins = "owr"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,rcv-sel = ; + }; + + /* Apalis HDMI1_CEC */ + hdmi_cec_pee3 { + nvidia,pins = "hdmi_cec_pee3"; + nvidia,function = "cec"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + + /* Apalis HDMI1_HPD */ + hdmi_int_pn7 { + nvidia,pins = "hdmi_int_pn7"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,rcv-sel = ; + }; + + /* Apalis I2C1 */ + gen1_i2c_scl_pc4 { + nvidia,pins = "gen1_i2c_scl_pc4"; + nvidia,function = "i2c1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + gen1_i2c_sda_pc5 { + nvidia,pins = "gen1_i2c_sda_pc5"; + nvidia,function = "i2c1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + + /* Apalis I2C2 (DDC) */ + gen2_i2c_scl_pt5 { + nvidia,pins = "gen2_i2c_scl_pt5"; + nvidia,function = "i2c2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + gen2_i2c_sda_pt6 { + nvidia,pins = "gen2_i2c_sda_pt6"; + nvidia,function = "i2c2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + + /* Apalis I2C3 (CAM) */ + cam_i2c_scl_pbb1 { + nvidia,pins = "cam_i2c_scl_pbb1"; + nvidia,function = "i2c3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + cam_i2c_sda_pbb2 { + nvidia,pins = "cam_i2c_sda_pbb2"; + nvidia,function = "i2c3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + + /* Apalis MMC1 */ + sdmmc1_cd_n_pv3 { /* CD# GPIO */ + nvidia,pins = "sdmmc1_wp_n_pv3"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + clk2_out_pw5 { /* D5 GPIO */ + nvidia,pins = "clk2_out_pw5"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc1_dat3_py4 { + nvidia,pins = "sdmmc1_dat3_py4"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc1_dat2_py5 { + nvidia,pins = "sdmmc1_dat2_py5"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc1_dat1_py6 { + nvidia,pins = "sdmmc1_dat1_py6"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc1_dat0_py7 { + nvidia,pins = "sdmmc1_dat0_py7"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc1_clk_pz0 { + nvidia,pins = "sdmmc1_clk_pz0"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc1_cmd_pz1 { + nvidia,pins = "sdmmc1_cmd_pz1"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + clk2_req_pcc5 { /* D4 GPIO */ + nvidia,pins = "clk2_req_pcc5"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + /* + * Don't use MMC1_D6 aka SDMMC3_CLK_LB_IN for now as it + * features some magic properties even though the + * external loopback is disabled and the internal + * loopback used as per SDMMC_VENDOR_MISC_CNTRL_0 + * register's SDMMC_SPARE1 bits being set to 0xfffd + * according to the TRM! + */ + sdmmc3_clk_lb_in_pee5 { /* D6 GPIO */ + nvidia,pins = "sdmmc3_clk_lb_in_pee5"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + usb_vbus_en2_pff1 { /* D7 GPIO */ + nvidia,pins = "usb_vbus_en2_pff1"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Apalis PWM */ + ph0 { + nvidia,pins = "ph0"; + nvidia,function = "pwm0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ph1 { + nvidia,pins = "ph1"; + nvidia,function = "pwm1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ph2 { + nvidia,pins = "ph2"; + nvidia,function = "pwm2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + /* PWM3 active on pu6 being Apalis BKL1_PWM */ + ph3 { + nvidia,pins = "ph3"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Apalis SATA1_ACT# */ + dap1_dout_pn2 { + nvidia,pins = "dap1_dout_pn2"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Apalis SD1 */ + sdmmc3_clk_pa6 { + nvidia,pins = "sdmmc3_clk_pa6"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3_cmd_pa7 { + nvidia,pins = "sdmmc3_cmd_pa7"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3_dat3_pb4 { + nvidia,pins = "sdmmc3_dat3_pb4"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3_dat2_pb5 { + nvidia,pins = "sdmmc3_dat2_pb5"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3_dat1_pb6 { + nvidia,pins = "sdmmc3_dat1_pb6"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3_dat0_pb7 { + nvidia,pins = "sdmmc3_dat0_pb7"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + /* + * Don't use SD1_CD# aka SDMMC3_CLK_LB_OUT for now as it + * features some magic properties even though the + * external loopback is disabled and the internal + * loopback used as per SDMMC_VENDOR_MISC_CNTRL_0 + * register's SDMMC_SPARE1 bits being set to 0xfffd + * according to the TRM! + */ + sdmmc3_clk_lb_out_pee4 { /* CD# GPIO */ + nvidia,pins = "sdmmc3_clk_lb_out_pee4"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Apalis SPDIF */ + spdif_out_pk5 { + nvidia,pins = "spdif_out_pk5"; + nvidia,function = "spdif"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + spdif_in_pk6 { + nvidia,pins = "spdif_in_pk6"; + nvidia,function = "spdif"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Apalis SPI1 */ + ulpi_clk_py0 { + nvidia,pins = "ulpi_clk_py0"; + nvidia,function = "spi1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_dir_py1 { + nvidia,pins = "ulpi_dir_py1"; + nvidia,function = "spi1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_nxt_py2 { + nvidia,pins = "ulpi_nxt_py2"; + nvidia,function = "spi1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_stp_py3 { + nvidia,pins = "ulpi_stp_py3"; + nvidia,function = "spi1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Apalis SPI2 */ + pg5 { + nvidia,pins = "pg5"; + nvidia,function = "spi4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pg6 { + nvidia,pins = "pg6"; + nvidia,function = "spi4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pg7 { + nvidia,pins = "pg7"; + nvidia,function = "spi4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pi3 { + nvidia,pins = "pi3"; + nvidia,function = "spi4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Apalis UART1 */ + pb1 { /* DCD GPIO */ + nvidia,pins = "pb1"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pk7 { /* RI GPIO */ + nvidia,pins = "pk7"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart1_txd_pu0 { + nvidia,pins = "pu0"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart1_rxd_pu1 { + nvidia,pins = "pu1"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart1_cts_n_pu2 { + nvidia,pins = "pu2"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart1_rts_n_pu3 { + nvidia,pins = "pu3"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart3_cts_n_pa1 { /* DSR GPIO */ + nvidia,pins = "uart3_cts_n_pa1"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart3_rts_n_pc0 { /* DTR GPIO */ + nvidia,pins = "uart3_rts_n_pc0"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Apalis UART2 */ + uart2_txd_pc2 { + nvidia,pins = "uart2_txd_pc2"; + nvidia,function = "irda"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart2_rxd_pc3 { + nvidia,pins = "uart2_rxd_pc3"; + nvidia,function = "irda"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart2_cts_n_pj5 { + nvidia,pins = "uart2_cts_n_pj5"; + nvidia,function = "uartb"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart2_rts_n_pj6 { + nvidia,pins = "uart2_rts_n_pj6"; + nvidia,function = "uartb"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Apalis UART3 */ + uart3_txd_pw6 { + nvidia,pins = "uart3_txd_pw6"; + nvidia,function = "uartc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart3_rxd_pw7 { + nvidia,pins = "uart3_rxd_pw7"; + nvidia,function = "uartc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Apalis UART4 */ + uart4_rxd_pb0 { + nvidia,pins = "pb0"; + nvidia,function = "uartd"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart4_txd_pj7 { + nvidia,pins = "pj7"; + nvidia,function = "uartd"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Apalis USBH_EN */ + usb_vbus_en1_pn5 { + nvidia,pins = "usb_vbus_en1_pn5"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + + /* Apalis USBH_OC# */ + pbb0 { + nvidia,pins = "pbb0"; + nvidia,function = "vgp6"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Apalis USBO1_EN */ + usb_vbus_en0_pn4 { + nvidia,pins = "usb_vbus_en0_pn4"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + + /* Apalis USBO1_OC# */ + pbb4 { + nvidia,pins = "pbb4"; + nvidia,function = "vgp4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Apalis WAKE1_MICO */ + pex_wake_n_pdd3 { + nvidia,pins = "pex_wake_n_pdd3"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* CORE_PWR_REQ */ + core_pwr_req { + nvidia,pins = "core_pwr_req"; + nvidia,function = "pwron"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* CPU_PWR_REQ */ + cpu_pwr_req { + nvidia,pins = "cpu_pwr_req"; + nvidia,function = "cpu"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* DVFS */ + dvfs_pwm_px0 { + nvidia,pins = "dvfs_pwm_px0"; + nvidia,function = "cldvfs"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dvfs_clk_px2 { + nvidia,pins = "dvfs_clk_px2"; + nvidia,function = "cldvfs"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* eMMC */ + sdmmc4_dat0_paa0 { + nvidia,pins = "sdmmc4_dat0_paa0"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4_dat1_paa1 { + nvidia,pins = "sdmmc4_dat1_paa1"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4_dat2_paa2 { + nvidia,pins = "sdmmc4_dat2_paa2"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4_dat3_paa3 { + nvidia,pins = "sdmmc4_dat3_paa3"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4_dat4_paa4 { + nvidia,pins = "sdmmc4_dat4_paa4"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4_dat5_paa5 { + nvidia,pins = "sdmmc4_dat5_paa5"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4_dat6_paa6 { + nvidia,pins = "sdmmc4_dat6_paa6"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4_dat7_paa7 { + nvidia,pins = "sdmmc4_dat7_paa7"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4_clk_pcc4 { + nvidia,pins = "sdmmc4_clk_pcc4"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4_cmd_pt7 { + nvidia,pins = "sdmmc4_cmd_pt7"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* JTAG_RTCK */ + jtag_rtck { + nvidia,pins = "jtag_rtck"; + nvidia,function = "rtck"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* LAN_DEV_OFF# */ + ulpi_data5_po6 { + nvidia,pins = "ulpi_data5_po6"; + nvidia,function = "ulpi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* LAN_RESET# */ + kb_row10_ps2 { + nvidia,pins = "kb_row10_ps2"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* LAN_WAKE# */ + ulpi_data4_po5 { + nvidia,pins = "ulpi_data4_po5"; + nvidia,function = "ulpi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* MCU_INT1# */ + pk2 { + nvidia,pins = "pk2"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* MCU_INT2# */ + pj2 { + nvidia,pins = "pj2"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* MCU_INT3# */ + pi5 { + nvidia,pins = "pi5"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* MCU_INT4# */ + pj0 { + nvidia,pins = "pj0"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* MCU_RESET */ + pbb6 { + nvidia,pins = "pbb6"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* MCU SPI */ + gpio_x4_aud_px4 { + nvidia,pins = "gpio_x4_aud_px4"; + nvidia,function = "spi2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gpio_x5_aud_px5 { + nvidia,pins = "gpio_x5_aud_px5"; + nvidia,function = "spi2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gpio_x6_aud_px6 { /* MCU_CS */ + nvidia,pins = "gpio_x6_aud_px6"; + nvidia,function = "spi2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gpio_x7_aud_px7 { + nvidia,pins = "gpio_x7_aud_px7"; + nvidia,function = "spi2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gpio_w2_aud_pw2 { /* MCU_CSEZP */ + nvidia,pins = "gpio_w2_aud_pw2"; + nvidia,function = "spi2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* PMIC_CLK_32K */ + clk_32k_in { + nvidia,pins = "clk_32k_in"; + nvidia,function = "clk"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* PMIC_CPU_OC_INT */ + clk_32k_out_pa0 { + nvidia,pins = "clk_32k_out_pa0"; + nvidia,function = "soc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* PWR_I2C */ + pwr_i2c_scl_pz6 { + nvidia,pins = "pwr_i2c_scl_pz6"; + nvidia,function = "i2cpwr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + pwr_i2c_sda_pz7 { + nvidia,pins = "pwr_i2c_sda_pz7"; + nvidia,function = "i2cpwr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + + /* PWR_INT_N */ + pwr_int_n { + nvidia,pins = "pwr_int_n"; + nvidia,function = "pmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* RESET_MOCI_CTRL */ + pu4 { + nvidia,pins = "pu4"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* RESET_OUT_N */ + reset_out_n { + nvidia,pins = "reset_out_n"; + nvidia,function = "reset_out_n"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* SHIFT_CTRL_DIR_IN */ + kb_row0_pr0 { + nvidia,pins = "kb_row0_pr0"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row1_pr1 { + nvidia,pins = "kb_row1_pr1"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Configure level-shifter as output for HDA */ + kb_row11_ps3 { + nvidia,pins = "kb_row11_ps3"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* SHIFT_CTRL_DIR_OUT */ + kb_col5_pq5 { + nvidia,pins = "kb_col5_pq5"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_col6_pq6 { + nvidia,pins = "kb_col6_pq6"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_col7_pq7 { + nvidia,pins = "kb_col7_pq7"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* SHIFT_CTRL_OE */ + kb_col0_pq0 { + nvidia,pins = "kb_col0_pq0"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_col1_pq1 { + nvidia,pins = "kb_col1_pq1"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_col2_pq2 { + nvidia,pins = "kb_col2_pq2"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_col4_pq4 { + nvidia,pins = "kb_col4_pq4"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row2_pr2 { + nvidia,pins = "kb_row2_pr2"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* GPIO_PI6 aka TEMP_ALERT_L */ + pi6 { + nvidia,pins = "pi6"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* TOUCH_INT */ + gpio_w3_aud_pw3 { + nvidia,pins = "gpio_w3_aud_pw3"; + nvidia,function = "spi6"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pc7 { /* NC */ + nvidia,pins = "pc7"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pg0 { /* NC */ + nvidia,pins = "pg0"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pg1 { /* NC */ + nvidia,pins = "pg1"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pg2 { /* NC */ + nvidia,pins = "pg2"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pg3 { /* NC */ + nvidia,pins = "pg3"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pg4 { /* NC */ + nvidia,pins = "pg4"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ph4 { /* NC */ + nvidia,pins = "ph4"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ph5 { /* NC */ + nvidia,pins = "ph5"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ph6 { /* NC */ + nvidia,pins = "ph6"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ph7 { /* NC */ + nvidia,pins = "ph7"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pi0 { /* NC */ + nvidia,pins = "pi0"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pi1 { /* NC */ + nvidia,pins = "pi1"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pi2 { /* NC */ + nvidia,pins = "pi2"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pi4 { /* NC */ + nvidia,pins = "pi4"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pi7 { /* NC */ + nvidia,pins = "pi7"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pk0 { /* NC */ + nvidia,pins = "pk0"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pk1 { /* NC */ + nvidia,pins = "pk1"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pk3 { /* NC */ + nvidia,pins = "pk3"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pk4 { /* NC */ + nvidia,pins = "pk4"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap1_fs_pn0 { /* NC */ + nvidia,pins = "dap1_fs_pn0"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap1_din_pn1 { /* NC */ + nvidia,pins = "dap1_din_pn1"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap1_sclk_pn3 { /* NC */ + nvidia,pins = "dap1_sclk_pn3"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_data7_po0 { /* NC */ + nvidia,pins = "ulpi_data7_po0"; + nvidia,function = "ulpi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_data0_po1 { /* NC */ + nvidia,pins = "ulpi_data0_po1"; + nvidia,function = "ulpi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_data1_po2 { /* NC */ + nvidia,pins = "ulpi_data1_po2"; + nvidia,function = "ulpi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_data2_po3 { /* NC */ + nvidia,pins = "ulpi_data2_po3"; + nvidia,function = "ulpi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_data3_po4 { /* NC */ + nvidia,pins = "ulpi_data3_po4"; + nvidia,function = "ulpi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_data6_po7 { /* NC */ + nvidia,pins = "ulpi_data6_po7"; + nvidia,function = "ulpi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap4_fs_pp4 { /* NC */ + nvidia,pins = "dap4_fs_pp4"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap4_din_pp5 { /* NC */ + nvidia,pins = "dap4_din_pp5"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap4_dout_pp6 { /* NC */ + nvidia,pins = "dap4_dout_pp6"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap4_sclk_pp7 { /* NC */ + nvidia,pins = "dap4_sclk_pp7"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_col3_pq3 { /* NC */ + nvidia,pins = "kb_col3_pq3"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row3_pr3 { /* NC */ + nvidia,pins = "kb_row3_pr3"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row4_pr4 { /* NC */ + nvidia,pins = "kb_row4_pr4"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row5_pr5 { /* NC */ + nvidia,pins = "kb_row5_pr5"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row6_pr6 { /* NC */ + nvidia,pins = "kb_row6_pr6"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row7_pr7 { /* NC */ + nvidia,pins = "kb_row7_pr7"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row8_ps0 { /* NC */ + nvidia,pins = "kb_row8_ps0"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row9_ps1 { /* NC */ + nvidia,pins = "kb_row9_ps1"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row12_ps4 { /* NC */ + nvidia,pins = "kb_row12_ps4"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row13_ps5 { /* NC */ + nvidia,pins = "kb_row13_ps5"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row14_ps6 { /* NC */ + nvidia,pins = "kb_row14_ps6"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row15_ps7 { /* NC */ + nvidia,pins = "kb_row15_ps7"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row16_pt0 { /* NC */ + nvidia,pins = "kb_row16_pt0"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row17_pt1 { /* NC */ + nvidia,pins = "kb_row17_pt1"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pu5 { /* NC */ + nvidia,pins = "pu5"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pv0 { /* NC */ + nvidia,pins = "pv0"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pv1 { /* NC */ + nvidia,pins = "pv1"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3_cd_n_pv2 { /* NC */ + nvidia,pins = "sdmmc3_cd_n_pv2"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gpio_x1_aud_px1 { /* NC */ + nvidia,pins = "gpio_x1_aud_px1"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gpio_x3_aud_px3 { /* NC */ + nvidia,pins = "gpio_x3_aud_px3"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pbb7 { /* NC */ + nvidia,pins = "pbb7"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pcc1 { /* NC */ + nvidia,pins = "pcc1"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pcc2 { /* NC */ + nvidia,pins = "pcc2"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + clk3_req_pee1 { /* NC */ + nvidia,pins = "clk3_req_pee1"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap_mclk1_req_pee2 { /* NC */ + nvidia,pins = "dap_mclk1_req_pee2"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + }; + }; + + serial@70006040 { + compatible = "nvidia,tegra124-hsuart"; + }; + + serial@70006200 { + compatible = "nvidia,tegra124-hsuart"; + }; + + serial@70006300 { + compatible = "nvidia,tegra124-hsuart"; + }; + + hdmi_ddc: i2c@7000c400 { + clock-frequency = <100000>; + }; + + /* PWR_I2C: power I2C to audio codec, PMIC and temperature sensor */ + i2c@7000d000 { + status = "okay"; + clock-frequency = <400000>; + + /* SGTL5000 audio codec */ + sgtl5000: codec@0a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + VDDA-supply = <®_3v3>; + VDDIO-supply = <&vddio_1v8>; + clocks = <&tegra_car TEGRA124_CLK_EXTERN1>; + }; + + pmic: pmic@40 { + compatible = "ams,as3722"; + reg = <0x40>; + interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; + + ams,system-power-controller; + + #interrupt-cells = <2>; + interrupt-controller; + + gpio-controller; + #gpio-cells = <2>; + + pinctrl-names = "default"; + pinctrl-0 = <&as3722_default>; + + as3722_default: pinmux { + gpio2_7 { + pins = "gpio2", /* PWR_EN_+V3.3 */ + "gpio7"; /* +V1.6_LPO */ + function = "gpio"; + bias-pull-up; + }; + + gpio1_3_4_5_6 { + pins = "gpio1", "gpio3", "gpio4", + "gpio5", "gpio6"; + bias-high-impedance; + }; + }; + + regulators { + vsup-sd2-supply = <®_3v3>; + vsup-sd3-supply = <®_3v3>; + vsup-sd4-supply = <®_3v3>; + vsup-sd5-supply = <®_3v3>; + vin-ldo0-supply = <&vddio_ddr_1v35>; + vin-ldo1-6-supply = <®_3v3>; + vin-ldo2-5-7-supply = <&vddio_1v8>; + vin-ldo3-4-supply = <®_3v3>; + vin-ldo9-10-supply = <®_3v3>; + vin-ldo11-supply = <®_3v3>; + + vdd_cpu: sd0 { + regulator-name = "+VDD_CPU_AP"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1400000>; + regulator-min-microamp = <3500000>; + regulator-max-microamp = <3500000>; + regulator-always-on; + regulator-boot-on; + ams,ext-control = <2>; + }; + + sd1 { + regulator-name = "+VDD_CORE"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1350000>; + regulator-min-microamp = <2500000>; + regulator-max-microamp = <4000000>; + regulator-always-on; + regulator-boot-on; + ams,ext-control = <1>; + }; + + vddio_ddr_1v35: sd2 { + regulator-name = + "+V1.35_VDDIO_DDR(sd2)"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + }; + + sd3 { + regulator-name = + "+V1.35_VDDIO_DDR(sd3)"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_1v05: sd4 { + regulator-name = "+V1.05"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + }; + + vddio_1v8: sd5 { + regulator-name = "+V1.8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + vdd_gpu: sd6 { + regulator-name = "+VDD_GPU_AP"; + regulator-min-microvolt = <650000>; + regulator-max-microvolt = <1200000>; + regulator-min-microamp = <3500000>; + regulator-max-microamp = <3500000>; + regulator-boot-on; + regulator-always-on; + }; + + avdd_1v05: ldo0 { + regulator-name = "+V1.05_AVDD"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + regulator-boot-on; + regulator-always-on; + ams,ext-control = <1>; + }; + + vddio_sdmmc1: ldo1 { + regulator-name = "VDDIO_SDMMC1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + ldo2 { + regulator-name = "+V1.2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3 { + regulator-name = "+V1.05_RTC"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-boot-on; + regulator-always-on; + ams,enable-tracking; + }; + + /* 1.8V for LVDS, 3.3V for eDP */ + ldo4 { + regulator-name = "AVDD_LVDS0_PLL"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + /* LDO5 not used */ + + vddio_sdmmc3: ldo6 { + regulator-name = "VDDIO_SDMMC3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + /* LDO7 not used */ + + ldo9 { + regulator-name = "+V3.3_ETH(ldo9)"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + ldo10 { + regulator-name = "+V3.3_ETH(ldo10)"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + ldo11 { + regulator-name = "+V1.8_VPP_FUSE"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + }; + }; + + /* + * TMP451 temperature sensor + * Note: THERM_N directly connected to AS3722 PMIC THERM + */ + temperature-sensor@4c { + compatible = "ti,tmp451"; + reg = <0x4c>; + interrupt-parent = <&gpio>; + interrupts = ; + + #thermal-sensor-cells = <1>; + }; + }; + + /* SPI2: MCU SPI */ + spi@7000d600 { + status = "okay"; + spi-max-frequency = <25000000>; + }; + + pmc@7000e400 { + nvidia,invert-interrupt; + nvidia,suspend-mode = <1>; + nvidia,cpu-pwr-good-time = <500>; + nvidia,cpu-pwr-off-time = <300>; + nvidia,core-pwr-good-time = <641 3845>; + nvidia,core-pwr-off-time = <61036>; + nvidia,core-power-req-active-high; + nvidia,sys-clock-req-active-high; + + /* Set power_off bit in ResetControl register of AS3722 PMIC */ + i2c-thermtrip { + nvidia,i2c-controller-id = <4>; + nvidia,bus-addr = <0x40>; + nvidia,reg-addr = <0x36>; + nvidia,reg-data = <0x2>; + }; + }; + + sata@70020000 { + phys = <&{/padctl@7009f000/pads/sata/lanes/sata-0}>; + phy-names = "sata-0"; + + avdd-supply = <&vdd_1v05>; + hvdd-supply = <®_3v3>; + vddio-supply = <&vdd_1v05>; + }; + + usb@70090000 { + /* USBO1, USBO1 (SS), USBH2, USBH4 and USBH4 (SS) */ + phys = <&{/padctl@7009f000/pads/usb2/lanes/usb2-0}>, + <&{/padctl@7009f000/pads/pcie/lanes/pcie-1}>, + <&{/padctl@7009f000/pads/usb2/lanes/usb2-1}>, + <&{/padctl@7009f000/pads/usb2/lanes/usb2-2}>, + <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>; + phy-names = "usb2-0", "usb3-1", "usb2-1", "usb2-2", "usb3-0"; + + avddio-pex-supply = <&vdd_1v05>; + avdd-pll-erefe-supply = <&avdd_1v05>; + avdd-pll-utmip-supply = <&vddio_1v8>; + avdd-usb-ss-pll-supply = <&vdd_1v05>; + avdd-usb-supply = <®_3v3>; + dvddio-pex-supply = <&vdd_1v05>; + hvdd-usb-ss-pll-e-supply = <®_3v3>; + hvdd-usb-ss-supply = <®_3v3>; + }; + + padctl@7009f000 { + pads { + usb2 { + status = "okay"; + + lanes { + usb2-0 { + nvidia,function = "xusb"; + status = "okay"; + }; + + usb2-1 { + nvidia,function = "xusb"; + status = "okay"; + }; + + usb2-2 { + nvidia,function = "xusb"; + status = "okay"; + }; + }; + }; + + pcie { + status = "okay"; + + lanes { + pcie-0 { + nvidia,function = "usb3-ss"; + status = "okay"; + }; + + pcie-1 { + nvidia,function = "usb3-ss"; + status = "okay"; + }; + + pcie-2 { + nvidia,function = "pcie"; + status = "okay"; + }; + + pcie-3 { + nvidia,function = "pcie"; + status = "okay"; + }; + + pcie-4 { + nvidia,function = "pcie"; + status = "okay"; + }; + }; + }; + + sata { + status = "okay"; + + lanes { + sata-0 { + nvidia,function = "sata"; + status = "okay"; + }; + }; + }; + }; + + ports { + /* USBO1 */ + usb2-0 { + status = "okay"; + mode = "otg"; + + vbus-supply = <®_usbo1_vbus>; + }; + + /* USBH2 */ + usb2-1 { + status = "okay"; + mode = "host"; + + vbus-supply = <®_usbh_vbus>; + }; + + /* USBH4 */ + usb2-2 { + status = "okay"; + mode = "host"; + + vbus-supply = <®_usbh_vbus>; + }; + + usb3-0 { + nvidia,usb2-companion = <2>; + status = "okay"; + }; + + usb3-1 { + nvidia,usb2-companion = <0>; + status = "okay"; + }; + }; + }; + + /* eMMC */ + sdhci@700b0600 { + status = "okay"; + bus-width = <8>; + non-removable; + }; + + /* CPU DFLL clock */ + clock@70110000 { + status = "okay"; + vdd-cpu-supply = <&vdd_cpu>; + nvidia,i2c-fs-rate = <400000>; + }; + + ahub@70300000 { + i2s@70301200 { + status = "okay"; + }; + }; + + clocks { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + clk32k_in: clock@0 { + compatible = "fixed-clock"; + reg = <0>; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + }; + + cpus { + cpu@0 { + vdd-cpu-supply = <&vdd_cpu>; + }; + }; + + reg_1v05_avdd_hdmi_pll: regulator-1v05-avdd-hdmi-pll { + compatible = "regulator-fixed"; + regulator-name = "+V1.05_AVDD_HDMI_PLL"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>; + vin-supply = <&vdd_1v05>; + }; + + reg_3v3_mxm: regulator-3v3-mxm { + compatible = "regulator-fixed"; + regulator-name = "+V3.3_MXM"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "+V3.3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + /* PWR_EN_+V3.3 */ + gpio = <&pmic 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_3v3_mxm>; + }; + + reg_3v3_avdd_hdmi: regulator-3v3-avdd-hdmi { + compatible = "regulator-fixed"; + regulator-name = "+V3.3_AVDD_HDMI"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vdd_1v05>; + }; + + sound { + compatible = "toradex,tegra-audio-sgtl5000-apalis_tk1", + "nvidia,tegra-audio-sgtl5000"; + nvidia,model = "Toradex Apalis TK1"; + nvidia,audio-routing = + "Headphone Jack", "HP_OUT", + "LINE_IN", "Line In Jack", + "MIC_IN", "Mic Jack"; + nvidia,i2s-controller = <&tegra_i2s2>; + nvidia,audio-codec = <&sgtl5000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_A>, + <&tegra_car TEGRA124_CLK_PLL_A_OUT0>, + <&tegra_car TEGRA124_CLK_EXTERN1>; + clock-names = "pll_a", "pll_a_out0", "mclk"; + }; + + thermal-zones { + cpu { + trips { + trip@0 { + temperature = <101000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + /* + * There are currently no cooling maps because + * there are no cooling devices + */ + }; + }; + + mem { + trips { + trip@0 { + temperature = <101000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + /* + * There are currently no cooling maps because + * there are no cooling devices + */ + }; + }; + + gpu { + trips { + trip@0 { + temperature = <101000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + /* + * There are currently no cooling maps because + * there are no cooling devices + */ + }; + }; + }; +}; -- cgit v0.10.2 From d261861ab52623e34a25fe6ae76714456edda033 Mon Sep 17 00:00:00 2001 From: Russell King Date: Sun, 10 Jul 2016 16:27:38 +0100 Subject: ARM: dts: armada-388-clearfog: remove duplicate mdio entry The clearfog DTS should not be defining the on-board phy, this device is located on the microsom. Remove the duplicated definition. Reported-by: Jon Nettleton Signed-off-by: Russell King Reviewed-by: Andrew Lunn Signed-off-by: Gregory CLEMENT diff --git a/arch/arm/boot/dts/armada-388-clearfog.dts b/arch/arm/boot/dts/armada-388-clearfog.dts index c60206e..2e0556a 100644 --- a/arch/arm/boot/dts/armada-388-clearfog.dts +++ b/arch/arm/boot/dts/armada-388-clearfog.dts @@ -239,22 +239,6 @@ status = "okay"; }; - mdio@72004 { - pinctrl-0 = <&mdio_pins>; - pinctrl-names = "default"; - - phy_dedicated: ethernet-phy@0 { - /* - * Annoyingly, the marvell phy driver - * configures the LED register, rather - * than preserving reset-loaded setting. - * We undo that rubbish here. - */ - marvell,reg-init = <3 16 0 0x101e>; - reg = <0>; - }; - }; - pinctrl@18000 { clearfog_dsa0_clk_pins: clearfog-dsa0-clk-pins { marvell,pins = "mpp46"; -- cgit v0.10.2 From 6cb4f8dd1044849047023b76567231f41eb64c9e Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Tue, 7 Jun 2016 13:19:00 +0200 Subject: ARM: sti: stih407-family: Supply defines for CLOCKGEN A0 There are 2 LMI clocks generated by CLOCKGEN A0. We wish to control them individually and need to use these indexes to do so. Signed-off-by: Lee Jones diff --git a/include/dt-bindings/clock/stih407-clks.h b/include/dt-bindings/clock/stih407-clks.h index 7af2b71..082edd9 100644 --- a/include/dt-bindings/clock/stih407-clks.h +++ b/include/dt-bindings/clock/stih407-clks.h @@ -5,6 +5,10 @@ #ifndef _DT_BINDINGS_CLK_STIH407 #define _DT_BINDINGS_CLK_STIH407 +/* CLOCKGEN A0 */ +#define CLK_IC_LMI0 0 +#define CLK_IC_LMI1 1 + /* CLOCKGEN C0 */ #define CLK_ICN_GPU 0 #define CLK_FDMA 1 -- cgit v0.10.2 From f221d8100e366e8373096ba7ffc36cf42d504e82 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Tue, 7 Jun 2016 13:19:00 +0200 Subject: ARM: sti: stih410-clocks: Identify critical clocks Lots of platforms contain clocks which if turned off would prove fatal. The only way to recover is to restart the board(s). This driver takes references to clocks which are required to be always-on. The Common Clk Framework will then take references to them. This way they will not be turned off during the clk_disabled_unused() procedure. In this patch we are identifying clocks, which if gated would render the STiH410 development board unserviceable. Signed-off-by: Lee Jones diff --git a/arch/arm/boot/dts/stih410-clock.dtsi b/arch/arm/boot/dts/stih410-clock.dtsi index d1f2aca..fd50496 100644 --- a/arch/arm/boot/dts/stih410-clock.dtsi +++ b/arch/arm/boot/dts/stih410-clock.dtsi @@ -103,6 +103,7 @@ clocks = <&clk_sysin>; clock-output-names = "clk-s-a0-pll-ofd-0"; + clock-critical = <0>; /* clk-s-a0-pll-ofd-0 */ }; clk_s_a0_flexgen: clk-s-a0-flexgen { @@ -115,6 +116,7 @@ clock-output-names = "clk-ic-lmi0", "clk-ic-lmi1"; + clock-critical = ; }; }; @@ -129,6 +131,7 @@ "clk-s-c0-fs0-ch1", "clk-s-c0-fs0-ch2", "clk-s-c0-fs0-ch3"; + clock-critical = <0>; /* clk-s-c0-fs0-ch0 */ }; clk_s_c0: clockgen-c@09103000 { @@ -142,6 +145,7 @@ clocks = <&clk_sysin>; clock-output-names = "clk-s-c0-pll0-odf-0"; + clock-critical = <0>; /* clk-s-c0-pll0-odf-0 */ }; clk_s_c0_pll1: clk-s-c0-pll1 { @@ -204,6 +208,11 @@ "clk-clust-hades", "clk-hwpe-hades", "clk-fc-hades"; + clock-critical = , + , + , + , + ; }; }; -- cgit v0.10.2 From cf4b5ceb95b1e8842bc4f061a8ba8c395b5dbc6d Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Tue, 7 Jun 2016 13:19:00 +0200 Subject: spi: st-ssc4: Remove 'no clocking' hack Due to the newly upstreamed 'critical clocks' API we can now safely handle clocking in the SPI and I2C drivers without fear of catastrophically crippling the running platform. Signed-off-by: Lee Jones diff --git a/drivers/spi/spi-st-ssc4.c b/drivers/spi/spi-st-ssc4.c index d5adf9f..a56eca0 100644 --- a/drivers/spi/spi-st-ssc4.c +++ b/drivers/spi/spi-st-ssc4.c @@ -68,32 +68,6 @@ struct spi_st { struct completion done; }; -static int spi_st_clk_enable(struct spi_st *spi_st) -{ - /* - * Current platforms use one of the core clocks for SPI and I2C. - * If we attempt to disable the clock, the system will hang. - * - * TODO: Remove this when platform supports power domains. - */ - return 0; - - return clk_prepare_enable(spi_st->clk); -} - -static void spi_st_clk_disable(struct spi_st *spi_st) -{ - /* - * Current platforms use one of the core clocks for SPI and I2C. - * If we attempt to disable the clock, the system will hang. - * - * TODO: Remove this when platform supports power domains. - */ - return; - - clk_disable_unprepare(spi_st->clk); -} - /* Load the TX FIFO */ static void ssc_write_tx_fifo(struct spi_st *spi_st) { @@ -349,7 +323,7 @@ static int spi_st_probe(struct platform_device *pdev) goto put_master; } - ret = spi_st_clk_enable(spi_st); + ret = clk_prepare_enable(spi_st->clk); if (ret) goto put_master; @@ -408,7 +382,7 @@ static int spi_st_probe(struct platform_device *pdev) return 0; clk_disable: - spi_st_clk_disable(spi_st); + clk_disable_unprepare(spi_st->clk); put_master: spi_master_put(master); return ret; @@ -419,7 +393,7 @@ static int spi_st_remove(struct platform_device *pdev) struct spi_master *master = platform_get_drvdata(pdev); struct spi_st *spi_st = spi_master_get_devdata(master); - spi_st_clk_disable(spi_st); + clk_disable_unprepare(spi_st->clk); pinctrl_pm_select_sleep_state(&pdev->dev); @@ -435,7 +409,7 @@ static int spi_st_runtime_suspend(struct device *dev) writel_relaxed(0, spi_st->base + SSC_IEN); pinctrl_pm_select_sleep_state(dev); - spi_st_clk_disable(spi_st); + clk_disable_unprepare(spi_st->clk); return 0; } @@ -446,7 +420,7 @@ static int spi_st_runtime_resume(struct device *dev) struct spi_st *spi_st = spi_master_get_devdata(master); int ret; - ret = spi_st_clk_enable(spi_st); + ret = clk_prepare_enable(spi_st->clk); pinctrl_pm_select_default_state(dev); return ret; -- cgit v0.10.2 From 4b9b7b3a2c91e1ebf8be9c7efd4839b91d66e87e Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Tue, 12 Jul 2016 00:51:58 +0300 Subject: ARM: dts: r8a7792: add PLL1 divided by 2 clock Despite the fact that QSPI clock has PLL1/VCOx1/4 clock as a parent, the latter hasn't been added to the R8A7792 device tree. This patch corrects that oversight. Signed-off-by: Sergei Shtylyov Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi index 75256ef..d5fd076 100644 --- a/arch/arm/boot/dts/r8a7792.dtsi +++ b/arch/arm/boot/dts/r8a7792.dtsi @@ -284,6 +284,13 @@ }; /* Fixed factor clocks */ + pll1_div2_clk: pll1_div2 { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7792_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <2>; + clock-mult = <1>; + }; zs_clk: zs { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7792_CLK_PLL1>; -- cgit v0.10.2 From e0c3f92a08f3e0a95024d0d032564fdc1ee96f54 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Tue, 12 Jul 2016 00:52:43 +0300 Subject: ARM: dts: r8a7792: remove ADSP clock Simon Horman told me that R8A7792 has ADSP clock based on an incorrect table in the most recent R-Car gen2 manual. But when I received that manual I discovered that this is false: R8A7792 is the only Gen 2 SoC that doesn't have ADSP at all. Accordingly remove the ADSP clock from DT for the r8a7792. Signed-off-by: Sergei Shtylyov Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi index d5fd076..3fd61d7 100644 --- a/arch/arm/boot/dts/r8a7792.dtsi +++ b/arch/arm/boot/dts/r8a7792.dtsi @@ -279,7 +279,7 @@ clocks = <&extal_clk>; #clock-cells = <1>; clock-output-names = "main", "pll0", "pll1", "pll3", - "lb", "qspi", "z", "adsp"; + "lb", "qspi", "z"; #power-domain-cells = <0>; }; diff --git a/include/dt-bindings/clock/r8a7792-clock.h b/include/dt-bindings/clock/r8a7792-clock.h index 89a5155..9a8b392 100644 --- a/include/dt-bindings/clock/r8a7792-clock.h +++ b/include/dt-bindings/clock/r8a7792-clock.h @@ -18,7 +18,6 @@ #define R8A7792_CLK_LB 4 #define R8A7792_CLK_QSPI 5 #define R8A7792_CLK_Z 6 -#define R8A7792_CLK_ADSP 7 /* MSTP0 */ #define R8A7792_CLK_MSIOF0 0 -- cgit v0.10.2 From 3cf265662c4b3902787d5d1235140a942d7ffa5a Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Tue, 12 Jul 2016 22:07:59 +0200 Subject: Documentation: dt: iio: at91_adc: fix trigger node names The trigger doesn't need the reg property. When it is not defined, the node name doesn't need a unit-address. Remove them from the example. Signed-off-by: Alexandre Belloni diff --git a/Documentation/devicetree/bindings/iio/adc/at91_adc.txt b/Documentation/devicetree/bindings/iio/adc/at91_adc.txt index 0f813de..f65b04f 100644 --- a/Documentation/devicetree/bindings/iio/adc/at91_adc.txt +++ b/Documentation/devicetree/bindings/iio/adc/at91_adc.txt @@ -59,28 +59,24 @@ adc0: adc@fffb0000 { atmel,adc-res-names = "lowres", "highres"; atmel,adc-use-res = "lowres"; - trigger@0 { - reg = <0>; + trigger0 { trigger-name = "external-rising"; trigger-value = <0x1>; trigger-external; }; - trigger@1 { - reg = <1>; + trigger1 { trigger-name = "external-falling"; trigger-value = <0x2>; trigger-external; }; - trigger@2 { - reg = <2>; + trigger2 { trigger-name = "external-any"; trigger-value = <0x3>; trigger-external; }; - trigger@3 { - reg = <3>; + trigger3 { trigger-name = "continuous"; trigger-value = <0x6>; }; -- cgit v0.10.2 From c94afa132b6d7f8e412a12da44da6203d2cd23d4 Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Tue, 12 Jul 2016 22:16:38 +0200 Subject: ARM: dts: at91: Fix ADC trigger nodes The triggers don't need a reg property, remove it when prenset. Also remove the unit-address from their name. This solves: Warning (unit_address_vs_reg): Node /ahb/apb/adc@fc034000/trigger@0 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /ahb/apb/adc@fc034000/trigger@1 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /ahb/apb/adc@fc034000/trigger@2 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /ahb/apb/adc@fc034000/trigger@3 has a unit name, but no reg property Signed-off-by: Alexandre Belloni diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi index af5ba31..49a02f5 100644 --- a/arch/arm/boot/dts/at91sam9260.dtsi +++ b/arch/arm/boot/dts/at91sam9260.dtsi @@ -938,25 +938,21 @@ atmel,adc-res-names = "lowres", "highres"; atmel,adc-use-res = "highres"; - trigger@0 { - reg = <0>; + trigger0 { trigger-name = "timer-counter-0"; trigger-value = <0x1>; }; - trigger@1 { - reg = <1>; + trigger1 { trigger-name = "timer-counter-1"; trigger-value = <0x3>; }; - trigger@2 { - reg = <2>; + trigger2 { trigger-name = "timer-counter-2"; trigger-value = <0x5>; }; - trigger@3 { - reg = <3>; + trigger3 { trigger-name = "external"; trigger-value = <0xd>; trigger-external; diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi index 8837b7e..048a981 100644 --- a/arch/arm/boot/dts/at91sam9g45.dtsi +++ b/arch/arm/boot/dts/at91sam9g45.dtsi @@ -1044,28 +1044,24 @@ atmel,adc-res-names = "lowres", "highres"; atmel,adc-use-res = "highres"; - trigger@0 { - reg = <0>; + trigger0 { trigger-name = "external-rising"; trigger-value = <0x1>; trigger-external; }; - trigger@1 { - reg = <1>; + trigger1 { trigger-name = "external-falling"; trigger-value = <0x2>; trigger-external; }; - trigger@2 { - reg = <2>; + trigger2 { trigger-name = "external-any"; trigger-value = <0x3>; trigger-external; }; - trigger@3 { - reg = <3>; + trigger3 { trigger-name = "continuous"; trigger-value = <0x6>; }; diff --git a/arch/arm/boot/dts/at91sam9rl.dtsi b/arch/arm/boot/dts/at91sam9rl.dtsi index 6d829db..201a3ca 100644 --- a/arch/arm/boot/dts/at91sam9rl.dtsi +++ b/arch/arm/boot/dts/at91sam9rl.dtsi @@ -265,25 +265,21 @@ atmel,adc-res-names = "lowres", "highres"; atmel,adc-use-res = "highres"; - trigger@0 { - reg = <0>; + trigger0 { trigger-name = "timer-counter-0"; trigger-value = <0x1>; }; - trigger@1 { - reg = <1>; + trigger1 { trigger-name = "timer-counter-1"; trigger-value = <0x3>; }; - trigger@2 { - reg = <2>; + trigger2 { trigger-name = "timer-counter-2"; trigger-value = <0x5>; }; - trigger@3 { - reg = <3>; + trigger3 { trigger-name = "external"; trigger-value = <0x13>; trigger-external; diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi index cd0cd5f..075d588 100644 --- a/arch/arm/boot/dts/at91sam9x5.dtsi +++ b/arch/arm/boot/dts/at91sam9x5.dtsi @@ -1048,29 +1048,25 @@ atmel,adc-res-names = "lowres", "highres"; atmel,adc-use-res = "highres"; - trigger@0 { - reg = <0>; + trigger0 { trigger-name = "external-rising"; trigger-value = <0x1>; trigger-external; }; - trigger@1 { - reg = <1>; + trigger1 { trigger-name = "external-falling"; trigger-value = <0x2>; trigger-external; }; - trigger@2 { - reg = <2>; + trigger2 { trigger-name = "external-any"; trigger-value = <0x3>; trigger-external; }; - trigger@3 { - reg = <3>; + trigger3 { trigger-name = "continuous"; trigger-value = <0x6>; }; diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi index 36301bd..a7c5cf4 100644 --- a/arch/arm/boot/dts/sama5d3.dtsi +++ b/arch/arm/boot/dts/sama5d3.dtsi @@ -326,26 +326,22 @@ atmel,adc-res-names = "lowres", "highres"; status = "disabled"; - trigger@0 { - reg = <0>; + trigger0 { trigger-name = "external-rising"; trigger-value = <0x1>; trigger-external; }; - trigger@1 { - reg = <1>; + trigger1 { trigger-name = "external-falling"; trigger-value = <0x2>; trigger-external; }; - trigger@2 { - reg = <2>; + trigger2 { trigger-name = "external-any"; trigger-value = <0x3>; trigger-external; }; - trigger@3 { - reg = <3>; + trigger3 { trigger-name = "continuous"; trigger-value = <0x6>; }; diff --git a/arch/arm/boot/dts/sama5d4.dtsi b/arch/arm/boot/dts/sama5d4.dtsi index 4e2cc30..5a9f50fb8 100644 --- a/arch/arm/boot/dts/sama5d4.dtsi +++ b/arch/arm/boot/dts/sama5d4.dtsi @@ -1226,22 +1226,22 @@ atmel,adc-ts-pressure-threshold = <10000>; status = "disabled"; - trigger@0 { + trigger0 { trigger-name = "external-rising"; trigger-value = <0x1>; trigger-external; }; - trigger@1 { + trigger1 { trigger-name = "external-falling"; trigger-value = <0x2>; trigger-external; }; - trigger@2 { + trigger2 { trigger-name = "external-any"; trigger-value = <0x3>; trigger-external; }; - trigger@3 { + trigger3 { trigger-name = "continuous"; trigger-value = <0x6>; }; -- cgit v0.10.2 From 60ec83e339814a22cfc740b377de3f5b9ef64801 Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Tue, 12 Jul 2016 22:45:47 +0200 Subject: Documentation: dt: usb: atmel-usb: add unit-address The endpoint nodes have a reg property, they also need a unit-address. Add them in the example. Signed-off-by: Alexandre Belloni diff --git a/Documentation/devicetree/bindings/usb/atmel-usb.txt b/Documentation/devicetree/bindings/usb/atmel-usb.txt index 5883b73..f4262ed 100644 --- a/Documentation/devicetree/bindings/usb/atmel-usb.txt +++ b/Documentation/devicetree/bindings/usb/atmel-usb.txt @@ -113,13 +113,13 @@ usb2: gadget@fff78000 { clock-names = "hclk", "pclk"; atmel,vbus-gpio = <&pioB 19 0>; - ep0 { + ep@0 { reg = <0>; atmel,fifo-size = <64>; atmel,nb-banks = <1>; }; - ep1 { + ep@1 { reg = <1>; atmel,fifo-size = <1024>; atmel,nb-banks = <2>; @@ -127,7 +127,7 @@ usb2: gadget@fff78000 { atmel,can-isoc; }; - ep2 { + ep@2 { reg = <2>; atmel,fifo-size = <1024>; atmel,nb-banks = <2>; @@ -135,21 +135,21 @@ usb2: gadget@fff78000 { atmel,can-isoc; }; - ep3 { + ep@3 { reg = <3>; atmel,fifo-size = <1024>; atmel,nb-banks = <3>; atmel,can-dma; }; - ep4 { + ep@4 { reg = <4>; atmel,fifo-size = <1024>; atmel,nb-banks = <3>; atmel,can-dma; }; - ep5 { + ep@5 { reg = <5>; atmel,fifo-size = <1024>; atmel,nb-banks = <3>; @@ -157,7 +157,7 @@ usb2: gadget@fff78000 { atmel,can-isoc; }; - ep6 { + ep@6 { reg = <6>; atmel,fifo-size = <1024>; atmel,nb-banks = <3>; -- cgit v0.10.2 From c32b5bcfa3c43a3c9bb59f65b5e76adb7384c4c8 Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Tue, 12 Jul 2016 22:45:59 +0200 Subject: ARM: dts: at91: Fix USB endpoint nodes Endpoint nodes have a reg property. Add their mandatory unit-address. This solves: Warning (unit_address_vs_reg): Node /ahb/gadget@00400000/ep0 has a reg or ranges property, but no unit name Warning (unit_address_vs_reg): Node /ahb/gadget@00400000/ep1 has a reg or ranges property, but no unit name Warning (unit_address_vs_reg): Node /ahb/gadget@00400000/ep2 has a reg or ranges property, but no unit name Warning (unit_address_vs_reg): Node /ahb/gadget@00400000/ep3 has a reg or ranges property, but no unit name Warning (unit_address_vs_reg): Node /ahb/gadget@00400000/ep4 has a reg or ranges property, but no unit name Warning (unit_address_vs_reg): Node /ahb/gadget@00400000/ep5 has a reg or ranges property, but no unit name Warning (unit_address_vs_reg): Node /ahb/gadget@00400000/ep6 has a reg or ranges property, but no unit name Warning (unit_address_vs_reg): Node /ahb/gadget@00400000/ep7 has a reg or ranges property, but no unit name Warning (unit_address_vs_reg): Node /ahb/gadget@00400000/ep8 has a reg or ranges property, but no unit name Warning (unit_address_vs_reg): Node /ahb/gadget@00400000/ep9 has a reg or ranges property, but no unit name Warning (unit_address_vs_reg): Node /ahb/gadget@00400000/ep10 has a reg or ranges property, but no unit name Warning (unit_address_vs_reg): Node /ahb/gadget@00400000/ep11 has a reg or ranges property, but no unit name Warning (unit_address_vs_reg): Node /ahb/gadget@00400000/ep12 has a reg or ranges property, but no unit name Warning (unit_address_vs_reg): Node /ahb/gadget@00400000/ep13 has a reg or ranges property, but no unit name Warning (unit_address_vs_reg): Node /ahb/gadget@00400000/ep14 has a reg or ranges property, but no unit name Warning (unit_address_vs_reg): Node /ahb/gadget@00400000/ep15 has a reg or ranges property, but no unit name Signed-off-by: Alexandre Belloni diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi index 048a981..c8789a8 100644 --- a/arch/arm/boot/dts/at91sam9g45.dtsi +++ b/arch/arm/boot/dts/at91sam9g45.dtsi @@ -1165,13 +1165,13 @@ clock-names = "pclk", "hclk"; status = "disabled"; - ep0 { + ep@0 { reg = <0>; atmel,fifo-size = <64>; atmel,nb-banks = <1>; }; - ep1 { + ep@1 { reg = <1>; atmel,fifo-size = <1024>; atmel,nb-banks = <2>; @@ -1179,7 +1179,7 @@ atmel,can-isoc; }; - ep2 { + ep@2 { reg = <2>; atmel,fifo-size = <1024>; atmel,nb-banks = <2>; @@ -1187,21 +1187,21 @@ atmel,can-isoc; }; - ep3 { + ep@3 { reg = <3>; atmel,fifo-size = <1024>; atmel,nb-banks = <3>; atmel,can-dma; }; - ep4 { + ep@4 { reg = <4>; atmel,fifo-size = <1024>; atmel,nb-banks = <3>; atmel,can-dma; }; - ep5 { + ep@5 { reg = <5>; atmel,fifo-size = <1024>; atmel,nb-banks = <3>; @@ -1209,7 +1209,7 @@ atmel,can-isoc; }; - ep6 { + ep@6 { reg = <6>; atmel,fifo-size = <1024>; atmel,nb-banks = <3>; diff --git a/arch/arm/boot/dts/at91sam9rl.dtsi b/arch/arm/boot/dts/at91sam9rl.dtsi index 201a3ca..cdaae8e 100644 --- a/arch/arm/boot/dts/at91sam9rl.dtsi +++ b/arch/arm/boot/dts/at91sam9rl.dtsi @@ -297,13 +297,13 @@ clock-names = "pclk", "hclk"; status = "disabled"; - ep0 { + ep@0 { reg = <0>; atmel,fifo-size = <64>; atmel,nb-banks = <1>; }; - ep1 { + ep@1 { reg = <1>; atmel,fifo-size = <1024>; atmel,nb-banks = <2>; @@ -311,7 +311,7 @@ atmel,can-isoc; }; - ep2 { + ep@2 { reg = <2>; atmel,fifo-size = <1024>; atmel,nb-banks = <2>; @@ -319,21 +319,21 @@ atmel,can-isoc; }; - ep3 { + ep@3 { reg = <3>; atmel,fifo-size = <1024>; atmel,nb-banks = <3>; atmel,can-dma; }; - ep4 { + ep@4 { reg = <4>; atmel,fifo-size = <1024>; atmel,nb-banks = <3>; atmel,can-dma; }; - ep5 { + ep@5 { reg = <5>; atmel,fifo-size = <1024>; atmel,nb-banks = <3>; @@ -341,7 +341,7 @@ atmel,can-isoc; }; - ep6 { + ep@6 { reg = <6>; atmel,fifo-size = <1024>; atmel,nb-banks = <3>; diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi index 075d588..f14ed90 100644 --- a/arch/arm/boot/dts/at91sam9x5.dtsi +++ b/arch/arm/boot/dts/at91sam9x5.dtsi @@ -1115,13 +1115,13 @@ clock-names = "hclk", "pclk"; status = "disabled"; - ep0 { + ep@0 { reg = <0>; atmel,fifo-size = <64>; atmel,nb-banks = <1>; }; - ep1 { + ep@1 { reg = <1>; atmel,fifo-size = <1024>; atmel,nb-banks = <2>; @@ -1129,7 +1129,7 @@ atmel,can-isoc; }; - ep2 { + ep@2 { reg = <2>; atmel,fifo-size = <1024>; atmel,nb-banks = <2>; @@ -1137,21 +1137,21 @@ atmel,can-isoc; }; - ep3 { + ep@3 { reg = <3>; atmel,fifo-size = <1024>; atmel,nb-banks = <3>; atmel,can-dma; }; - ep4 { + ep@4 { reg = <4>; atmel,fifo-size = <1024>; atmel,nb-banks = <3>; atmel,can-dma; }; - ep5 { + ep@5 { reg = <5>; atmel,fifo-size = <1024>; atmel,nb-banks = <3>; @@ -1159,7 +1159,7 @@ atmel,can-isoc; }; - ep6 { + ep@6 { reg = <6>; atmel,fifo-size = <1024>; atmel,nb-banks = <3>; diff --git a/arch/arm/boot/dts/sama5d2.dtsi b/arch/arm/boot/dts/sama5d2.dtsi index 5d63206..c885d2b 100644 --- a/arch/arm/boot/dts/sama5d2.dtsi +++ b/arch/arm/boot/dts/sama5d2.dtsi @@ -117,13 +117,13 @@ clock-names = "pclk", "hclk"; status = "disabled"; - ep0 { + ep@0 { reg = <0>; atmel,fifo-size = <64>; atmel,nb-banks = <1>; }; - ep1 { + ep@1 { reg = <1>; atmel,fifo-size = <1024>; atmel,nb-banks = <3>; @@ -131,7 +131,7 @@ atmel,can-isoc; }; - ep2 { + ep@2 { reg = <2>; atmel,fifo-size = <1024>; atmel,nb-banks = <3>; @@ -139,7 +139,7 @@ atmel,can-isoc; }; - ep3 { + ep@3 { reg = <3>; atmel,fifo-size = <1024>; atmel,nb-banks = <2>; @@ -147,7 +147,7 @@ atmel,can-isoc; }; - ep4 { + ep@4 { reg = <4>; atmel,fifo-size = <1024>; atmel,nb-banks = <2>; @@ -155,7 +155,7 @@ atmel,can-isoc; }; - ep5 { + ep@5 { reg = <5>; atmel,fifo-size = <1024>; atmel,nb-banks = <2>; @@ -163,7 +163,7 @@ atmel,can-isoc; }; - ep6 { + ep@6 { reg = <6>; atmel,fifo-size = <1024>; atmel,nb-banks = <2>; @@ -171,7 +171,7 @@ atmel,can-isoc; }; - ep7 { + ep@7 { reg = <7>; atmel,fifo-size = <1024>; atmel,nb-banks = <2>; @@ -179,56 +179,56 @@ atmel,can-isoc; }; - ep8 { + ep@8 { reg = <8>; atmel,fifo-size = <1024>; atmel,nb-banks = <2>; atmel,can-isoc; }; - ep9 { + ep@9 { reg = <9>; atmel,fifo-size = <1024>; atmel,nb-banks = <2>; atmel,can-isoc; }; - ep10 { + ep@10 { reg = <10>; atmel,fifo-size = <1024>; atmel,nb-banks = <2>; atmel,can-isoc; }; - ep11 { + ep@11 { reg = <11>; atmel,fifo-size = <1024>; atmel,nb-banks = <2>; atmel,can-isoc; }; - ep12 { + ep@12 { reg = <12>; atmel,fifo-size = <1024>; atmel,nb-banks = <2>; atmel,can-isoc; }; - ep13 { + ep@13 { reg = <13>; atmel,fifo-size = <1024>; atmel,nb-banks = <2>; atmel,can-isoc; }; - ep14 { + ep@14 { reg = <14>; atmel,fifo-size = <1024>; atmel,nb-banks = <2>; atmel,can-isoc; }; - ep15 { + ep@15 { reg = <15>; atmel,fifo-size = <1024>; atmel,nb-banks = <2>; diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi index a7c5cf4..4c84d33 100644 --- a/arch/arm/boot/dts/sama5d3.dtsi +++ b/arch/arm/boot/dts/sama5d3.dtsi @@ -1337,13 +1337,13 @@ clock-names = "pclk", "hclk"; status = "disabled"; - ep0 { + ep@0 { reg = <0>; atmel,fifo-size = <64>; atmel,nb-banks = <1>; }; - ep1 { + ep@1 { reg = <1>; atmel,fifo-size = <1024>; atmel,nb-banks = <3>; @@ -1351,7 +1351,7 @@ atmel,can-isoc; }; - ep2 { + ep@2 { reg = <2>; atmel,fifo-size = <1024>; atmel,nb-banks = <3>; @@ -1359,84 +1359,84 @@ atmel,can-isoc; }; - ep3 { + ep@3 { reg = <3>; atmel,fifo-size = <1024>; atmel,nb-banks = <2>; atmel,can-dma; }; - ep4 { + ep@4 { reg = <4>; atmel,fifo-size = <1024>; atmel,nb-banks = <2>; atmel,can-dma; }; - ep5 { + ep@5 { reg = <5>; atmel,fifo-size = <1024>; atmel,nb-banks = <2>; atmel,can-dma; }; - ep6 { + ep@6 { reg = <6>; atmel,fifo-size = <1024>; atmel,nb-banks = <2>; atmel,can-dma; }; - ep7 { + ep@7 { reg = <7>; atmel,fifo-size = <1024>; atmel,nb-banks = <2>; atmel,can-dma; }; - ep8 { + ep@8 { reg = <8>; atmel,fifo-size = <1024>; atmel,nb-banks = <2>; }; - ep9 { + ep@9 { reg = <9>; atmel,fifo-size = <1024>; atmel,nb-banks = <2>; }; - ep10 { + ep@10 { reg = <10>; atmel,fifo-size = <1024>; atmel,nb-banks = <2>; }; - ep11 { + ep@11 { reg = <11>; atmel,fifo-size = <1024>; atmel,nb-banks = <2>; }; - ep12 { + ep@12 { reg = <12>; atmel,fifo-size = <1024>; atmel,nb-banks = <2>; }; - ep13 { + ep@13 { reg = <13>; atmel,fifo-size = <1024>; atmel,nb-banks = <2>; }; - ep14 { + ep@14 { reg = <14>; atmel,fifo-size = <1024>; atmel,nb-banks = <2>; }; - ep15 { + ep@15 { reg = <15>; atmel,fifo-size = <1024>; atmel,nb-banks = <2>; diff --git a/arch/arm/boot/dts/sama5d4.dtsi b/arch/arm/boot/dts/sama5d4.dtsi index 5a9f50fb8..65e725f 100644 --- a/arch/arm/boot/dts/sama5d4.dtsi +++ b/arch/arm/boot/dts/sama5d4.dtsi @@ -135,13 +135,13 @@ clock-names = "pclk", "hclk"; status = "disabled"; - ep0 { + ep@0 { reg = <0>; atmel,fifo-size = <64>; atmel,nb-banks = <1>; }; - ep1 { + ep@1 { reg = <1>; atmel,fifo-size = <1024>; atmel,nb-banks = <3>; @@ -149,7 +149,7 @@ atmel,can-isoc; }; - ep2 { + ep@2 { reg = <2>; atmel,fifo-size = <1024>; atmel,nb-banks = <3>; @@ -157,7 +157,7 @@ atmel,can-isoc; }; - ep3 { + ep@3 { reg = <3>; atmel,fifo-size = <1024>; atmel,nb-banks = <2>; @@ -165,7 +165,7 @@ atmel,can-isoc; }; - ep4 { + ep@4 { reg = <4>; atmel,fifo-size = <1024>; atmel,nb-banks = <2>; @@ -173,7 +173,7 @@ atmel,can-isoc; }; - ep5 { + ep@5 { reg = <5>; atmel,fifo-size = <1024>; atmel,nb-banks = <2>; @@ -181,7 +181,7 @@ atmel,can-isoc; }; - ep6 { + ep@6 { reg = <6>; atmel,fifo-size = <1024>; atmel,nb-banks = <2>; @@ -189,7 +189,7 @@ atmel,can-isoc; }; - ep7 { + ep@7 { reg = <7>; atmel,fifo-size = <1024>; atmel,nb-banks = <2>; @@ -197,56 +197,56 @@ atmel,can-isoc; }; - ep8 { + ep@8 { reg = <8>; atmel,fifo-size = <1024>; atmel,nb-banks = <2>; atmel,can-isoc; }; - ep9 { + ep@9 { reg = <9>; atmel,fifo-size = <1024>; atmel,nb-banks = <2>; atmel,can-isoc; }; - ep10 { + ep@10 { reg = <10>; atmel,fifo-size = <1024>; atmel,nb-banks = <2>; atmel,can-isoc; }; - ep11 { + ep@11 { reg = <11>; atmel,fifo-size = <1024>; atmel,nb-banks = <2>; atmel,can-isoc; }; - ep12 { + ep@12 { reg = <12>; atmel,fifo-size = <1024>; atmel,nb-banks = <2>; atmel,can-isoc; }; - ep13 { + ep@13 { reg = <13>; atmel,fifo-size = <1024>; atmel,nb-banks = <2>; atmel,can-isoc; }; - ep14 { + ep@14 { reg = <14>; atmel,fifo-size = <1024>; atmel,nb-banks = <2>; atmel,can-isoc; }; - ep15 { + ep@15 { reg = <15>; atmel,fifo-size = <1024>; atmel,nb-banks = <2>; -- cgit v0.10.2 From 8aabe9b9a038a0be5ef6d4cfcf898ec6ad54c88f Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Wed, 13 Jul 2016 20:06:27 +0200 Subject: ARM: dts: at91: sama5d4ek: remove useless lcd_bus lcd_bus has never been mainlined and is replaced by the atmel_hlcdc driver. Remove stale nodes. Signed-off-by: Alexandre Belloni diff --git a/arch/arm/boot/dts/at91-sama5d4ek.dts b/arch/arm/boot/dts/at91-sama5d4ek.dts index 4e98cda..f8b96ce 100644 --- a/arch/arm/boot/dts/at91-sama5d4ek.dts +++ b/arch/arm/boot/dts/at91-sama5d4ek.dts @@ -69,26 +69,6 @@ ahb { apb { - lcd_bus@f0000000 { - status = "okay"; - - lcd@f0000000 { - status = "okay"; - }; - - lcdovl1@f0000140 { - status = "okay"; - }; - - lcdovl2@f0000240 { - status = "okay"; - }; - - lcdheo1@f0000340 { - status = "okay"; - }; - }; - adc0: adc@fc034000 { pinctrl-names = "default"; pinctrl-0 = < -- cgit v0.10.2 From a63f6a64cc1e78366382657cab70772240b6dcc2 Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Wed, 13 Jul 2016 00:08:19 +0200 Subject: ARM: dts: at91: sama5d3_xplained: fix regulator name vcc_mmc0_reg is a fixed regulator and doesn't need a reg property. Remove its unit-address. Solves: Warning (unit_address_vs_reg): Node /fixedregulator@0 has a unit name, but no reg property Signed-off-by: Alexandre Belloni diff --git a/arch/arm/boot/dts/at91-sama5d3_xplained.dts b/arch/arm/boot/dts/at91-sama5d3_xplained.dts index f3e2b96..c51fc65 100644 --- a/arch/arm/boot/dts/at91-sama5d3_xplained.dts +++ b/arch/arm/boot/dts/at91-sama5d3_xplained.dts @@ -297,7 +297,7 @@ }; }; - vcc_mmc0_reg: fixedregulator@0 { + vcc_mmc0_reg: fixedregulator_mmc0 { compatible = "regulator-fixed"; gpio = <&pioE 2 GPIO_ACTIVE_LOW>; regulator-name = "mmc0-card-supply"; -- cgit v0.10.2 From 17995e60f47b2f1345038159088c4d76365f8873 Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Wed, 13 Jul 2016 00:10:13 +0200 Subject: ARM: dts: at91: sama5d4_xplained: fix regulator names vcc_3v3_reg and vcc_mmc1_reg are fixed regulators and don't need a reg property. Remove their unit-address. Solves: Warning (unit_address_vs_reg): Node /fixedregulator@0 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /fixedregulator@1 has a unit name, but no reg property Signed-off-by: Alexandre Belloni diff --git a/arch/arm/boot/dts/at91-sama5d4_xplained.dts b/arch/arm/boot/dts/at91-sama5d4_xplained.dts index da84e65..ed7fce2 100644 --- a/arch/arm/boot/dts/at91-sama5d4_xplained.dts +++ b/arch/arm/boot/dts/at91-sama5d4_xplained.dts @@ -252,7 +252,7 @@ }; }; - vcc_3v3_reg: fixedregulator@0 { + vcc_3v3_reg: fixedregulator_3v3 { compatible = "regulator-fixed"; regulator-name = "VCC 3V3"; regulator-min-microvolt = <3300000>; @@ -261,7 +261,7 @@ regulator-always-on; }; - vcc_mmc1_reg: fixedregulator@1 { + vcc_mmc1_reg: fixedregulator_mmc1 { compatible = "regulator-fixed"; gpio = <&pioE 4 GPIO_ACTIVE_LOW>; regulator-name = "VDD MCI1"; -- cgit v0.10.2 From 33220987e744d60e184d32ebd687d4d9ce867449 Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Wed, 13 Jul 2016 00:16:23 +0200 Subject: ARM: dts: at91: sama5d4_ma5d4: fix regulator names vcc_3v3_reg and vcc_mmc1_reg are fixed regulators and don't need a reg property. Remove their unit-address. Solves: Warning (unit_address_vs_reg): Node /fixedregulator@0 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /fixedregulator@1 has a unit name, but no reg property Reviewed-by: Marek Vasut Signed-off-by: Alexandre Belloni diff --git a/arch/arm/boot/dts/at91-sama5d4_ma5d4.dtsi b/arch/arm/boot/dts/at91-sama5d4_ma5d4.dtsi index 99d5713..a92c6e0 100644 --- a/arch/arm/boot/dts/at91-sama5d4_ma5d4.dtsi +++ b/arch/arm/boot/dts/at91-sama5d4_ma5d4.dtsi @@ -109,7 +109,7 @@ }; }; - vcc_3v3_reg: fixedregulator@0 { + vcc_3v3_reg: fixedregulator_3v3 { compatible = "regulator-fixed"; regulator-name = "VCC 3V3"; regulator-min-microvolt = <3300000>; @@ -118,7 +118,7 @@ regulator-always-on; }; - vcc_mmc0_reg: fixedregulator@1 { + vcc_mmc0_reg: fixedregulator_mmc0 { compatible = "regulator-fixed"; gpio = <&pioE 15 GPIO_ACTIVE_HIGH>; regulator-name = "RST_n MCI0"; -- cgit v0.10.2 From 6fa3c6bf7453e59fdb5f2692ecc300f2968d1175 Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Wed, 13 Jul 2016 00:19:58 +0200 Subject: ARM: dts: at91: sama5d4_ma5d4evk: fix regulator names vcc_mmc1_reg is a fixed regulators and doesn't need a reg property. Remove its unit-address. Solves: Warning (unit_address_vs_reg): Node /fixedregulator@2 has a unit name, but no reg property Reviewed-by: Marek Vasut Signed-off-by: Alexandre Belloni diff --git a/arch/arm/boot/dts/at91-sama5d4_ma5d4evk.dts b/arch/arm/boot/dts/at91-sama5d4_ma5d4evk.dts index abaaba5..eac4ea2 100644 --- a/arch/arm/boot/dts/at91-sama5d4_ma5d4evk.dts +++ b/arch/arm/boot/dts/at91-sama5d4_ma5d4evk.dts @@ -159,7 +159,7 @@ }; }; - vcc_mmc1_reg: fixedregulator@2 { + vcc_mmc1_reg: fixedregulator_mmc1 { compatible = "regulator-fixed"; gpio = <&pioE 17 GPIO_ACTIVE_LOW>; regulator-name = "VDD MCI1"; -- cgit v0.10.2 From 313dcab07236df65443beb52339c042ca2940143 Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Thu, 14 Jul 2016 16:40:17 +0200 Subject: ARM: dts: at91: ariag25 : fix onewire node Remove the unit-address from the oneiwire node as it doesn't have a reg property. Solves: Warning (unit_address_vs_reg): Node /onewire@0 has a unit name, but no reg property Signed-off-by: Alexandre Belloni diff --git a/arch/arm/boot/dts/at91-ariag25.dts b/arch/arm/boot/dts/at91-ariag25.dts index f16a9b8..4da011a 100644 --- a/arch/arm/boot/dts/at91-ariag25.dts +++ b/arch/arm/boot/dts/at91-ariag25.dts @@ -169,7 +169,7 @@ }; - onewire@0 { + onewire { compatible = "w1-gpio"; gpios = <&pioA 21 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; -- cgit v0.10.2 From d3c1c7181f55f3464529decad189f2317a2932da Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Thu, 14 Jul 2016 16:48:00 +0200 Subject: ARM: dts: at91: vinco: fix regulator name vcc_3v3_reg is a fixed regulator and doesn't need a reg property. Remove its unit-address. Solves: Warning (unit_address_vs_reg): Node /fixedregulator@0 has a unit name, but no reg property Signed-off-by: Alexandre Belloni diff --git a/arch/arm/boot/dts/at91-vinco.dts b/arch/arm/boot/dts/at91-vinco.dts index 6a366ee..e0c0b28 100644 --- a/arch/arm/boot/dts/at91-vinco.dts +++ b/arch/arm/boot/dts/at91-vinco.dts @@ -245,7 +245,7 @@ }; - vcc_3v3_reg: fixedregulator@0 { + vcc_3v3_reg: fixedregulator_3v3 { compatible = "regulator-fixed"; regulator-name = "VCC 3V3"; regulator-min-microvolt = <3300000>; -- cgit v0.10.2 From e152e3f7f4b0141d2fbf4f993dadfcc5eadd1645 Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Thu, 14 Jul 2016 16:58:11 +0200 Subject: ARM: dts: at91: fix i2c-gpio node name i2c-gpio doesn't need a reg property. Change the node names to i2c-gpio-x as used in other dts to remove the unit-address. Solves: Warning (unit_address_vs_reg): Node /i2c@0 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /i2c@1 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /i2c@2 has a unit name, but no reg property Signed-off-by: Alexandre Belloni diff --git a/arch/arm/boot/dts/at91-foxg20.dts b/arch/arm/boot/dts/at91-foxg20.dts index 07c9bac..50d5e71 100644 --- a/arch/arm/boot/dts/at91-foxg20.dts +++ b/arch/arm/boot/dts/at91-foxg20.dts @@ -125,7 +125,7 @@ }; }; - i2c@0 { + i2c-gpio-0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c0>; i2c-gpio,delay-us = <5>; /* ~85 kHz */ diff --git a/arch/arm/boot/dts/at91-kizbox.dts b/arch/arm/boot/dts/at91-kizbox.dts index 0e3f34e..b4f147c 100644 --- a/arch/arm/boot/dts/at91-kizbox.dts +++ b/arch/arm/boot/dts/at91-kizbox.dts @@ -96,7 +96,7 @@ }; }; - i2c@0 { + i2c-gpio-0 { status = "okay"; rtc: pcf8563@51 { diff --git a/arch/arm/boot/dts/at91-qil_a9260.dts b/arch/arm/boot/dts/at91-qil_a9260.dts index 5ad3d90..8f01918 100644 --- a/arch/arm/boot/dts/at91-qil_a9260.dts +++ b/arch/arm/boot/dts/at91-qil_a9260.dts @@ -178,7 +178,7 @@ }; }; - i2c@0 { + i2c-gpio-0 { status = "okay"; }; }; diff --git a/arch/arm/boot/dts/at91-sam9_l9260.dts b/arch/arm/boot/dts/at91-sam9_l9260.dts index 814753a..171243c 100644 --- a/arch/arm/boot/dts/at91-sam9_l9260.dts +++ b/arch/arm/boot/dts/at91-sam9_l9260.dts @@ -99,7 +99,7 @@ }; - i2c@0 { + i2c-gpio-0 { status = "okay"; }; diff --git a/arch/arm/boot/dts/at91rm9200.dtsi b/arch/arm/boot/dts/at91rm9200.dtsi index f6cb7a8..4e913c2 100644 --- a/arch/arm/boot/dts/at91rm9200.dtsi +++ b/arch/arm/boot/dts/at91rm9200.dtsi @@ -948,7 +948,7 @@ }; }; - i2c@0 { + i2c-gpio-0 { compatible = "i2c-gpio"; gpios = <&pioA 25 GPIO_ACTIVE_HIGH /* sda */ &pioA 26 GPIO_ACTIVE_HIGH /* scl */ diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi index 49a02f5..a3e363d 100644 --- a/arch/arm/boot/dts/at91sam9260.dtsi +++ b/arch/arm/boot/dts/at91sam9260.dtsi @@ -1013,7 +1013,7 @@ }; }; - i2c@0 { + i2c-gpio-0 { compatible = "i2c-gpio"; gpios = <&pioA 23 GPIO_ACTIVE_HIGH /* sda */ &pioA 24 GPIO_ACTIVE_HIGH /* scl */ diff --git a/arch/arm/boot/dts/at91sam9260ek.dts b/arch/arm/boot/dts/at91sam9260ek.dts index 0a29bd0..2c87f58 100644 --- a/arch/arm/boot/dts/at91sam9260ek.dts +++ b/arch/arm/boot/dts/at91sam9260ek.dts @@ -185,7 +185,7 @@ }; }; - i2c@0 { + i2c-gpio-0 { status = "okay"; 24c512@50 { diff --git a/arch/arm/boot/dts/at91sam9261.dtsi b/arch/arm/boot/dts/at91sam9261.dtsi index 5e09de4..32752d7 100644 --- a/arch/arm/boot/dts/at91sam9261.dtsi +++ b/arch/arm/boot/dts/at91sam9261.dtsi @@ -860,7 +860,7 @@ }; }; - i2c@0 { + i2c-gpio-0 { compatible = "i2c-gpio"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c_bitbang>; diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi index 9344642..aeb1a36 100644 --- a/arch/arm/boot/dts/at91sam9263.dtsi +++ b/arch/arm/boot/dts/at91sam9263.dtsi @@ -1019,7 +1019,7 @@ }; }; - i2c@0 { + i2c-gpio-0 { compatible = "i2c-gpio"; gpios = <&pioB 4 GPIO_ACTIVE_HIGH /* sda */ &pioB 5 GPIO_ACTIVE_HIGH /* scl */ diff --git a/arch/arm/boot/dts/at91sam9263ek.dts b/arch/arm/boot/dts/at91sam9263ek.dts index 59df9d7..127cc42 100644 --- a/arch/arm/boot/dts/at91sam9263ek.dts +++ b/arch/arm/boot/dts/at91sam9263ek.dts @@ -215,7 +215,7 @@ }; }; - i2c@0 { + i2c-gpio-0 { status = "okay"; 24c512@50 { diff --git a/arch/arm/boot/dts/at91sam9g20ek_common.dtsi b/arch/arm/boot/dts/at91sam9g20ek_common.dtsi index 1395b30..27847a4 100644 --- a/arch/arm/boot/dts/at91sam9g20ek_common.dtsi +++ b/arch/arm/boot/dts/at91sam9g20ek_common.dtsi @@ -176,7 +176,7 @@ }; }; - i2c@0 { + i2c-gpio-0 { status = "okay"; 24c512@50 { diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi index c8789a8..b3501ae 100644 --- a/arch/arm/boot/dts/at91sam9g45.dtsi +++ b/arch/arm/boot/dts/at91sam9g45.dtsi @@ -1316,7 +1316,7 @@ }; }; - i2c@0 { + i2c-gpio-0 { compatible = "i2c-gpio"; gpios = <&pioA 20 GPIO_ACTIVE_HIGH /* sda */ &pioA 21 GPIO_ACTIVE_HIGH /* scl */ diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi index 95569a8..3b3eb3e 100644 --- a/arch/arm/boot/dts/at91sam9n12.dtsi +++ b/arch/arm/boot/dts/at91sam9n12.dtsi @@ -1030,7 +1030,7 @@ }; }; - i2c@0 { + i2c-gpio-0 { compatible = "i2c-gpio"; gpios = <&pioA 30 GPIO_ACTIVE_HIGH /* sda */ &pioA 31 GPIO_ACTIVE_HIGH /* scl */ diff --git a/arch/arm/boot/dts/at91sam9rl.dtsi b/arch/arm/boot/dts/at91sam9rl.dtsi index cdaae8e..70adf94 100644 --- a/arch/arm/boot/dts/at91sam9rl.dtsi +++ b/arch/arm/boot/dts/at91sam9rl.dtsi @@ -1089,7 +1089,7 @@ }; }; - i2c@0 { + i2c-gpio-0 { compatible = "i2c-gpio"; gpios = <&pioA 23 GPIO_ACTIVE_HIGH>, /* sda */ <&pioA 24 GPIO_ACTIVE_HIGH>; /* scl */ @@ -1103,7 +1103,7 @@ status = "disabled"; }; - i2c@1 { + i2c-gpio-1 { compatible = "i2c-gpio"; gpios = <&pioD 10 GPIO_ACTIVE_HIGH>, /* sda */ <&pioD 11 GPIO_ACTIVE_HIGH>; /* scl */ diff --git a/arch/arm/boot/dts/at91sam9rlek.dts b/arch/arm/boot/dts/at91sam9rlek.dts index f10566f..2e567d9 100644 --- a/arch/arm/boot/dts/at91sam9rlek.dts +++ b/arch/arm/boot/dts/at91sam9rlek.dts @@ -227,11 +227,11 @@ }; }; - i2c@0 { + i2c-gpio-0 { status = "okay"; }; - i2c@1 { + i2c-gpio-1 { status = "okay"; }; }; diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi index f14ed90..ed4e4bd 100644 --- a/arch/arm/boot/dts/at91sam9x5.dtsi +++ b/arch/arm/boot/dts/at91sam9x5.dtsi @@ -1238,7 +1238,7 @@ }; }; - i2c@0 { + i2c-gpio-0 { compatible = "i2c-gpio"; gpios = <&pioA 30 GPIO_ACTIVE_HIGH /* sda */ &pioA 31 GPIO_ACTIVE_HIGH /* scl */ @@ -1253,7 +1253,7 @@ status = "disabled"; }; - i2c@1 { + i2c-gpio-1 { compatible = "i2c-gpio"; gpios = <&pioC 0 GPIO_ACTIVE_HIGH /* sda */ &pioC 1 GPIO_ACTIVE_HIGH /* scl */ @@ -1268,7 +1268,7 @@ status = "disabled"; }; - i2c@2 { + i2c-gpio-2 { compatible = "i2c-gpio"; gpios = <&pioB 4 GPIO_ACTIVE_HIGH /* sda */ &pioB 5 GPIO_ACTIVE_HIGH /* scl */ diff --git a/arch/arm/boot/dts/ethernut5.dts b/arch/arm/boot/dts/ethernut5.dts index 298ee2f..4687229 100644 --- a/arch/arm/boot/dts/ethernut5.dts +++ b/arch/arm/boot/dts/ethernut5.dts @@ -83,7 +83,7 @@ }; }; - i2c@0 { + i2c-gpio-0 { status = "okay"; pcf8563@50 { diff --git a/arch/arm/boot/dts/evk-pro3.dts b/arch/arm/boot/dts/evk-pro3.dts index 312d3e8..20a4481 100644 --- a/arch/arm/boot/dts/evk-pro3.dts +++ b/arch/arm/boot/dts/evk-pro3.dts @@ -52,7 +52,7 @@ }; }; - i2c@0 { + i2c-gpio-0 { status = "okay"; }; diff --git a/arch/arm/boot/dts/mpa1600.dts b/arch/arm/boot/dts/mpa1600.dts index 30e66e5..116ce78 100644 --- a/arch/arm/boot/dts/mpa1600.dts +++ b/arch/arm/boot/dts/mpa1600.dts @@ -52,7 +52,7 @@ }; }; - i2c@0 { + i2c-gpio-0 { status = "okay"; }; diff --git a/arch/arm/boot/dts/tny_a9263.dts b/arch/arm/boot/dts/tny_a9263.dts index 2f39f85..9161cd98 100644 --- a/arch/arm/boot/dts/tny_a9263.dts +++ b/arch/arm/boot/dts/tny_a9263.dts @@ -90,7 +90,7 @@ }; }; - i2c@0 { + i2c-gpio-0 { status = "okay"; }; }; diff --git a/arch/arm/boot/dts/usb_a9260_common.dtsi b/arch/arm/boot/dts/usb_a9260_common.dtsi index 0f3a02b..7514b34 100644 --- a/arch/arm/boot/dts/usb_a9260_common.dtsi +++ b/arch/arm/boot/dts/usb_a9260_common.dtsi @@ -110,7 +110,7 @@ }; }; - i2c@0 { + i2c-gpio-0 { status = "okay"; }; }; diff --git a/arch/arm/boot/dts/usb_a9263.dts b/arch/arm/boot/dts/usb_a9263.dts index 94c61507..bfc48a2 100644 --- a/arch/arm/boot/dts/usb_a9263.dts +++ b/arch/arm/boot/dts/usb_a9263.dts @@ -138,7 +138,7 @@ }; }; - i2c@0 { + i2c-gpio-0 { status = "okay"; }; }; diff --git a/arch/arm/boot/dts/usb_a9g20_common.dtsi b/arch/arm/boot/dts/usb_a9g20_common.dtsi index 6156ee8..088c2c3 100644 --- a/arch/arm/boot/dts/usb_a9g20_common.dtsi +++ b/arch/arm/boot/dts/usb_a9g20_common.dtsi @@ -19,7 +19,7 @@ reg = <0x20000000 0x4000000>; }; - i2c@0 { + i2c-gpio-0 { rv3029c2@56 { compatible = "rv3029c2"; reg = <0x56>; -- cgit v0.10.2 From efedc4893b0549b83ee678e428e18e4fa505bc4c Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Thu, 14 Jul 2016 16:50:17 +0200 Subject: ARM: dts: at91: move isi definition to at91sam9g25ek The ISI is only present on the at91sam9g25, move the definition to the at91sam9g25ek board dts to avoid warnings. Solves the following warning for other 9x5ek boards: Warning (unit_address_vs_reg): Node /ahb/apb/isi@f8048000 has a unit name, but no reg property Signed-off-by: Alexandre Belloni diff --git a/arch/arm/boot/dts/at91sam9g25ek.dts b/arch/arm/boot/dts/at91sam9g25ek.dts index 707fd4e..30bfd2e 100644 --- a/arch/arm/boot/dts/at91sam9g25ek.dts +++ b/arch/arm/boot/dts/at91sam9g25ek.dts @@ -26,7 +26,24 @@ i2c0: i2c@f8010000 { ov2640: camera@0x30 { + compatible = "ovti,ov2640"; + reg = <0x30>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pck0_as_isi_mck &pinctrl_sensor_power &pinctrl_sensor_reset>; + resetb-gpios = <&pioA 7 GPIO_ACTIVE_LOW>; + pwdn-gpios = <&pioA 13 GPIO_ACTIVE_HIGH>; + clocks = <&pck0>; + clock-names = "xvclk"; + assigned-clocks = <&pck0>; + assigned-clock-rates = <25000000>; status = "okay"; + + port { + ov2640_0: endpoint { + remote-endpoint = <&isi_0>; + bus-width = <8>; + }; + }; }; }; @@ -37,6 +54,14 @@ isi: isi@f8048000 { status = "okay"; + port { + isi_0: endpoint@0 { + remote-endpoint = <&ov2640_0>; + bus-width = <8>; + vsync-active = <1>; + hsync-active = <1>; + }; + }; }; }; }; diff --git a/arch/arm/boot/dts/at91sam9x5ek.dtsi b/arch/arm/boot/dts/at91sam9x5ek.dtsi index 52425a4..696b8ba 100644 --- a/arch/arm/boot/dts/at91sam9x5ek.dtsi +++ b/arch/arm/boot/dts/at91sam9x5ek.dtsi @@ -60,18 +60,6 @@ status = "okay"; }; - isi: isi@f8048000 { - status = "disabled"; - port { - isi_0: endpoint@0 { - remote-endpoint = <&ov2640_0>; - bus-width = <8>; - vsync-active = <1>; - hsync-active = <1>; - }; - }; - }; - i2c0: i2c@f8010000 { status = "okay"; @@ -79,27 +67,6 @@ compatible = "wm8731"; reg = <0x1a>; }; - - ov2640: camera@0x30 { - compatible = "ovti,ov2640"; - reg = <0x30>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pck0_as_isi_mck &pinctrl_sensor_power &pinctrl_sensor_reset>; - resetb-gpios = <&pioA 7 GPIO_ACTIVE_LOW>; - pwdn-gpios = <&pioA 13 GPIO_ACTIVE_HIGH>; - clocks = <&pck0>; - clock-names = "xvclk"; - assigned-clocks = <&pck0>; - assigned-clock-rates = <25000000>; - status = "disabled"; - - port { - ov2640_0: endpoint { - remote-endpoint = <&isi_0>; - bus-width = <8>; - }; - }; - }; }; adc0: adc@f804c000 { -- cgit v0.10.2 From 81c940d9be74e77ce0301a7f8a20214c8888084c Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Thu, 14 Jul 2016 17:04:50 +0200 Subject: ARM: dts: at91: at91sam9g25ek: fix isi endpoint node Add a reg property in the endpoint node as documented in Documentation/devicetree/bindings/media/video-interfaces.txt Solves: Warning (unit_address_vs_reg): Node /ahb/apb/isi@f8048000/port/endpoint@0 has a unit name, but no reg property Signed-off-by: Alexandre Belloni diff --git a/arch/arm/boot/dts/at91sam9g25ek.dts b/arch/arm/boot/dts/at91sam9g25ek.dts index 30bfd2e..91a7177 100644 --- a/arch/arm/boot/dts/at91sam9g25ek.dts +++ b/arch/arm/boot/dts/at91sam9g25ek.dts @@ -56,6 +56,7 @@ status = "okay"; port { isi_0: endpoint@0 { + reg = <0>; remote-endpoint = <&ov2640_0>; bus-width = <8>; vsync-active = <1>; -- cgit v0.10.2 From 94197ad713a6f7f164837ac674726d3af70a7c53 Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Fri, 15 Jul 2016 11:15:16 +0200 Subject: ARM: dts: at91: sama5d3x: separate motherboard gmac and emac definitions Separate the definitions for the emac and the gmac in different files and include them in the final board dts that uses them. Solves: Warning (unit_address_vs_reg): Node /ahb/apb/ethernet@f0028000 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /ahb/apb/ethernet@f802c000 has a unit name, but no reg property Signed-off-by: Alexandre Belloni diff --git a/arch/arm/boot/dts/sama5d31ek.dts b/arch/arm/boot/dts/sama5d31ek.dts index 04eec0d..25e4c0b 100644 --- a/arch/arm/boot/dts/sama5d31ek.dts +++ b/arch/arm/boot/dts/sama5d31ek.dts @@ -9,6 +9,7 @@ /dts-v1/; #include "sama5d31.dtsi" #include "sama5d3xmb.dtsi" +#include "sama5d3xmb_emac.dtsi" #include "sama5d3xdm.dtsi" / { diff --git a/arch/arm/boot/dts/sama5d33ek.dts b/arch/arm/boot/dts/sama5d33ek.dts index cbd6a3f..c517b87 100644 --- a/arch/arm/boot/dts/sama5d33ek.dts +++ b/arch/arm/boot/dts/sama5d33ek.dts @@ -9,6 +9,7 @@ /dts-v1/; #include "sama5d33.dtsi" #include "sama5d3xmb.dtsi" +#include "sama5d3xmb_gmac.dtsi" #include "sama5d3xdm.dtsi" / { diff --git a/arch/arm/boot/dts/sama5d34ek.dts b/arch/arm/boot/dts/sama5d34ek.dts index 878aa16..c8b8449 100644 --- a/arch/arm/boot/dts/sama5d34ek.dts +++ b/arch/arm/boot/dts/sama5d34ek.dts @@ -9,6 +9,7 @@ /dts-v1/; #include "sama5d34.dtsi" #include "sama5d3xmb.dtsi" +#include "sama5d3xmb_gmac.dtsi" #include "sama5d3xdm.dtsi" / { diff --git a/arch/arm/boot/dts/sama5d35ek.dts b/arch/arm/boot/dts/sama5d35ek.dts index e812f5c..6e261fc 100644 --- a/arch/arm/boot/dts/sama5d35ek.dts +++ b/arch/arm/boot/dts/sama5d35ek.dts @@ -9,6 +9,8 @@ /dts-v1/; #include "sama5d35.dtsi" #include "sama5d3xmb.dtsi" +#include "sama5d3xmb_emac.dtsi" +#include "sama5d3xmb_gmac.dtsi" / { model = "Atmel SAMA5D35-EK"; diff --git a/arch/arm/boot/dts/sama5d36ek.dts b/arch/arm/boot/dts/sama5d36ek.dts index 59576c6..cd458b8 100644 --- a/arch/arm/boot/dts/sama5d36ek.dts +++ b/arch/arm/boot/dts/sama5d36ek.dts @@ -10,6 +10,8 @@ #include "sama5d36.dtsi" #include "sama5d3xmb.dtsi" #include "sama5d3xdm.dtsi" +#include "sama5d3xmb_emac.dtsi" +#include "sama5d3xmb_gmac.dtsi" / { model = "Atmel SAMA5D36-EK"; diff --git a/arch/arm/boot/dts/sama5d3xcm.dtsi b/arch/arm/boot/dts/sama5d3xcm.dtsi index 2cf9c36..b5e111b 100644 --- a/arch/arm/boot/dts/sama5d3xcm.dtsi +++ b/arch/arm/boot/dts/sama5d3xcm.dtsi @@ -34,40 +34,6 @@ spi0: spi@f0004000 { cs-gpios = <&pioD 13 0>, <0>, <0>, <0>; }; - - macb0: ethernet@f0028000 { - phy-mode = "rgmii"; - #address-cells = <1>; - #size-cells = <0>; - - ethernet-phy@1 { - reg = <0x1>; - interrupt-parent = <&pioB>; - interrupts = <25 IRQ_TYPE_EDGE_FALLING>; - txen-skew-ps = <800>; - txc-skew-ps = <3000>; - rxdv-skew-ps = <400>; - rxc-skew-ps = <3000>; - rxd0-skew-ps = <400>; - rxd1-skew-ps = <400>; - rxd2-skew-ps = <400>; - rxd3-skew-ps = <400>; - }; - - ethernet-phy@7 { - reg = <0x7>; - interrupt-parent = <&pioB>; - interrupts = <25 IRQ_TYPE_EDGE_FALLING>; - txen-skew-ps = <800>; - txc-skew-ps = <3000>; - rxdv-skew-ps = <400>; - rxc-skew-ps = <3000>; - rxd0-skew-ps = <400>; - rxd1-skew-ps = <400>; - rxd2-skew-ps = <400>; - rxd3-skew-ps = <400>; - }; - }; }; nand0: nand@60000000 { diff --git a/arch/arm/boot/dts/sama5d3xmb.dtsi b/arch/arm/boot/dts/sama5d3xmb.dtsi index 8901042..6d252ad 100644 --- a/arch/arm/boot/dts/sama5d3xmb.dtsi +++ b/arch/arm/boot/dts/sama5d3xmb.dtsi @@ -117,18 +117,6 @@ status = "okay"; }; - macb1: ethernet@f802c000 { - phy-mode = "rmii"; - - #address-cells = <1>; - #size-cells = <0>; - phy0: ethernet-phy@1 { - interrupt-parent = <&pioE>; - interrupts = <30 IRQ_TYPE_EDGE_FALLING>; - reg = <1>; - }; - }; - pinctrl@fffff200 { board { pinctrl_mmc0_cd: mmc0_cd { diff --git a/arch/arm/boot/dts/sama5d3xmb_emac.dtsi b/arch/arm/boot/dts/sama5d3xmb_emac.dtsi new file mode 100644 index 0000000..2fd14f3 --- /dev/null +++ b/arch/arm/boot/dts/sama5d3xmb_emac.dtsi @@ -0,0 +1,26 @@ +/* + * sama5d3xmb_emac.dts - Device Tree Include file for SAMA5D3x mother board + * Ethernet + * + * Copyright (C) 2016 Atmel, + * + * Licensed under GPLv2 or later. + */ + +/ { + ahb { + apb { + macb1: ethernet@f802c000 { + phy-mode = "rmii"; + + #address-cells = <1>; + #size-cells = <0>; + phy0: ethernet-phy@1 { + interrupt-parent = <&pioE>; + interrupts = <30 IRQ_TYPE_EDGE_FALLING>; + reg = <1>; + }; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/sama5d3xmb_gmac.dtsi b/arch/arm/boot/dts/sama5d3xmb_gmac.dtsi new file mode 100644 index 0000000..65aea7a --- /dev/null +++ b/arch/arm/boot/dts/sama5d3xmb_gmac.dtsi @@ -0,0 +1,48 @@ +/* + * sama5d3xmb_gmac.dtsi - Device Tree Include file for SAMA5D3x motherboard + * Gigabit Ethernet + * + * Copyright (C) 2016 Atmel, + * + * Licensed under GPLv2 or later. + */ + +/ { + ahb { + apb { + macb0: ethernet@f0028000 { + phy-mode = "rgmii"; + #address-cells = <1>; + #size-cells = <0>; + + ethernet-phy@1 { + reg = <0x1>; + interrupt-parent = <&pioB>; + interrupts = <25 IRQ_TYPE_EDGE_FALLING>; + txen-skew-ps = <800>; + txc-skew-ps = <3000>; + rxdv-skew-ps = <400>; + rxc-skew-ps = <3000>; + rxd0-skew-ps = <400>; + rxd1-skew-ps = <400>; + rxd2-skew-ps = <400>; + rxd3-skew-ps = <400>; + }; + + ethernet-phy@7 { + reg = <0x7>; + interrupt-parent = <&pioB>; + interrupts = <25 IRQ_TYPE_EDGE_FALLING>; + txen-skew-ps = <800>; + txc-skew-ps = <3000>; + rxdv-skew-ps = <400>; + rxc-skew-ps = <3000>; + rxd0-skew-ps = <400>; + rxd1-skew-ps = <400>; + rxd2-skew-ps = <400>; + rxd3-skew-ps = <400>; + }; + }; + }; + }; +}; -- cgit v0.10.2 From 7aff0f29cdb484a5d9692a4d6c9e4b908a848688 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Fri, 8 Jul 2016 11:45:19 +0200 Subject: ARM: dts: at91: Don't build unnecessary dtbs Building both ARMv4 and ARMv5 dtbs when SOC_SAM_V4_V5 is an issue for kernelci because it will then attempt to boot ARMv4 kernels on at91sam9 which doesn't work. Use CONFIG_SOC_AT91RM9200 and CONFIG_SOC_AT91SAM9 instead. Signed-off-by: Arnd Bergmann Signed-off-by: Alexandre Belloni diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index fbd7de6..e900dad 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -7,9 +7,10 @@ dtb-$(CONFIG_MACH_ARTPEC6) += \ dtb-$(CONFIG_MACH_ASM9260) += \ alphascale-asm9260-devkit.dtb # Keep at91 dtb files sorted alphabetically for each SoC -dtb-$(CONFIG_SOC_SAM_V4_V5) += \ +dtb-$(CONFIG_SOC_AT91RM9200) += \ at91rm9200ek.dtb \ - mpa1600.dtb \ + mpa1600.dtb +dtb-$(CONFIG_SOC_AT91SAM9) += \ animeo_ip.dtb \ at91-qil_a9260.dtb \ aks-cdu.dtb \ -- cgit v0.10.2 From 110af36aa06dfa201b844ac683d35ce18d4d686e Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Fri, 8 Jul 2016 18:05:42 +0200 Subject: ARM: dts: sunxi: Rename sunxi-q8-common.dtsi sunxi-reference-design-tablet.dtsi Rename sunxi-q8-common.dtsi to sunxi-reference-design-tablet.dtsi. This is part of renaming all the sun?i-q8-common.dtsi files to sun?i-reference-design-tablet.dtsi since most of the hw-config in there is shared by all sunxi tablets. Signed-off-by: Hans de Goede Signed-off-by: Maxime Ripard diff --git a/arch/arm/boot/dts/sun5i-q8-common.dtsi b/arch/arm/boot/dts/sun5i-q8-common.dtsi index a5de28d..8977fb2 100644 --- a/arch/arm/boot/dts/sun5i-q8-common.dtsi +++ b/arch/arm/boot/dts/sun5i-q8-common.dtsi @@ -39,7 +39,7 @@ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. */ -#include "sunxi-q8-common.dtsi" +#include "sunxi-reference-design-tablet.dtsi" #include diff --git a/arch/arm/boot/dts/sun8i-q8-common.dtsi b/arch/arm/boot/dts/sun8i-q8-common.dtsi index f3f4ce0..0b85ea4 100644 --- a/arch/arm/boot/dts/sun8i-q8-common.dtsi +++ b/arch/arm/boot/dts/sun8i-q8-common.dtsi @@ -39,7 +39,7 @@ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. */ -#include "sunxi-q8-common.dtsi" +#include "sunxi-reference-design-tablet.dtsi" #include diff --git a/arch/arm/boot/dts/sunxi-q8-common.dtsi b/arch/arm/boot/dts/sunxi-q8-common.dtsi deleted file mode 100644 index b824146..0000000 --- a/arch/arm/boot/dts/sunxi-q8-common.dtsi +++ /dev/null @@ -1,83 +0,0 @@ -/* - * Copyright 2015 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include -#include -#include -#include "sunxi-common-regulators.dtsi" - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; - status = "okay"; -}; - -&lradc { - vref-supply = <®_vcc3v0>; - status = "okay"; - - button@200 { - label = "Volume Up"; - linux,code = ; - channel = <0>; - voltage = <200000>; - }; - - button@400 { - label = "Volume Down"; - linux,code = ; - channel = <0>; - voltage = <400000>; - }; -}; - -&pwm { - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_pins>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/sunxi-reference-design-tablet.dtsi b/arch/arm/boot/dts/sunxi-reference-design-tablet.dtsi new file mode 100644 index 0000000..b824146 --- /dev/null +++ b/arch/arm/boot/dts/sunxi-reference-design-tablet.dtsi @@ -0,0 +1,83 @@ +/* + * Copyright 2015 Hans de Goede + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include +#include +#include +#include "sunxi-common-regulators.dtsi" + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "okay"; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins_a>; + status = "okay"; +}; + +&lradc { + vref-supply = <®_vcc3v0>; + status = "okay"; + + button@200 { + label = "Volume Up"; + linux,code = ; + channel = <0>; + voltage = <200000>; + }; + + button@400 { + label = "Volume Down"; + linux,code = ; + channel = <0>; + voltage = <400000>; + }; +}; + +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_pins>; + status = "okay"; +}; -- cgit v0.10.2 From f4a51e0ff74a496304ea06c4c74cca934c915efa Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Fri, 8 Jul 2016 18:05:43 +0200 Subject: ARM: dts: sun5i: Move q8 display bits to sun5i-a13-q8-tablet.dts This is a preparation patch for renaming sun5i-q8-common.dtsi to sun5i-reference-design-tablet.dtsi and sharing it between all the A13 tablet dts files. Since we only have a panel config for the 18 tablets (for now) move this to the q8 specific dts file. Signed-off-by: Hans de Goede Signed-off-by: Maxime Ripard diff --git a/arch/arm/boot/dts/sun5i-a13-q8-tablet.dts b/arch/arm/boot/dts/sun5i-a13-q8-tablet.dts index dce7782..afe14f7 100644 --- a/arch/arm/boot/dts/sun5i-a13-q8-tablet.dts +++ b/arch/arm/boot/dts/sun5i-a13-q8-tablet.dts @@ -47,4 +47,40 @@ / { model = "Q8 A13 Tablet"; compatible = "allwinner,q8-a13", "allwinner,sun5i-a13"; + + panel: panel { + compatible = "urt,umsh-8596md-t", "simple-panel"; + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + /* TODO: lcd panel uses axp gpio0 as enable pin */ + backlight = <&backlight>; + #address-cells = <1>; + #size-cells = <0>; + + panel_input: endpoint@0 { + reg = <0>; + remote-endpoint = <&tcon0_out_lcd>; + }; + }; + }; +}; + +&be0 { + status = "okay"; +}; + +&tcon0 { + pinctrl-names = "default"; + pinctrl-0 = <&lcd_rgb666_pins>; + status = "okay"; +}; + +&tcon0_out { + tcon0_out_lcd: endpoint@0 { + reg = <0>; + remote-endpoint = <&panel_input>; + }; }; diff --git a/arch/arm/boot/dts/sun5i-q8-common.dtsi b/arch/arm/boot/dts/sun5i-q8-common.dtsi index 8977fb2..ca5d0c4 100644 --- a/arch/arm/boot/dts/sun5i-q8-common.dtsi +++ b/arch/arm/boot/dts/sun5i-q8-common.dtsi @@ -59,29 +59,6 @@ chosen { stdout-path = "serial0:115200n8"; }; - - panel: panel { - compatible = "urt,umsh-8596md-t", "simple-panel"; - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - /* TODO: lcd panel uses axp gpio0 as enable pin */ - backlight = <&backlight>; - #address-cells = <1>; - #size-cells = <0>; - - panel_input: endpoint@0 { - reg = <0>; - remote-endpoint = <&tcon0_out_lcd>; - }; - }; - }; -}; - -&be0 { - status = "okay"; }; &codec { @@ -202,19 +179,6 @@ status = "okay"; }; -&tcon0 { - pinctrl-names = "default"; - pinctrl-0 = <&lcd_rgb666_pins>; - status = "okay"; -}; - -&tcon0_out { - tcon0_out_lcd: endpoint@0 { - reg = <0>; - remote-endpoint = <&panel_input>; - }; -}; - &uart1 { pinctrl-names = "default"; pinctrl-0 = <&uart1_pins_b>; -- cgit v0.10.2 From 875be91de16f3da61a1071df6184d64310a7788e Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Fri, 8 Jul 2016 18:05:44 +0200 Subject: ARM: dts: sun5i: Rename sun5i-q8-common.dtsi sun5i-reference-design-tablet.dtsi Rename sun5i-q8-common.dtsi to sun5i-reference-design-tablet.dtsi. This is part of renaming all the sun?i-q8-common.dtsi files to sun?i-reference-design-tablet.dtsi since most of the hw-config in there is shared by all sunxi tablets. Signed-off-by: Hans de Goede Signed-off-by: Maxime Ripard diff --git a/arch/arm/boot/dts/sun5i-a13-q8-tablet.dts b/arch/arm/boot/dts/sun5i-a13-q8-tablet.dts index afe14f7..a89f29fa 100644 --- a/arch/arm/boot/dts/sun5i-a13-q8-tablet.dts +++ b/arch/arm/boot/dts/sun5i-a13-q8-tablet.dts @@ -42,7 +42,7 @@ /dts-v1/; #include "sun5i-a13.dtsi" -#include "sun5i-q8-common.dtsi" +#include "sun5i-reference-design-tablet.dtsi" / { model = "Q8 A13 Tablet"; diff --git a/arch/arm/boot/dts/sun5i-q8-common.dtsi b/arch/arm/boot/dts/sun5i-q8-common.dtsi deleted file mode 100644 index ca5d0c4..0000000 --- a/arch/arm/boot/dts/sun5i-q8-common.dtsi +++ /dev/null @@ -1,206 +0,0 @@ -/* - * Copyright 2015 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ -#include "sunxi-reference-design-tablet.dtsi" - -#include - -/ { - aliases { - serial0 = &uart1; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>; - brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; - default-brightness-level = <8>; - /* TODO: backlight uses axp gpio1 as enable pin */ - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&codec { - pinctrl-names = "default"; - pinctrl-0 = <&codec_pa_pin>; - allwinner,pa-gpios = <&pio 6 10 GPIO_ACTIVE_HIGH>; /* PG10 */ - status = "okay"; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&ehci0 { - status = "okay"; -}; - -&i2c0 { - axp209: pmic@34 { - reg = <0x34>; - interrupts = <0>; - }; -}; - -&i2c1 { - pcf8563: rtc@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - }; -}; - -#include "axp209.dtsi" - -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_q8>; - vmmc-supply = <®_vcc3v0>; - bus-width = <4>; - cd-gpios = <&pio 6 0 GPIO_ACTIVE_HIGH>; /* PG0 */ - cd-inverted; - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -&pio { - codec_pa_pin: codec_pa_pin@0 { - allwinner,pins = "PG10"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; - - mmc0_cd_pin_q8: mmc0_cd_pin@0 { - allwinner,pins = "PG0"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; - - usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 { - allwinner,pins = "PG1"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; - - usb0_id_detect_pin: usb0_id_detect_pin@0 { - allwinner,pins = "PG2"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; - - usb0_vbus_pin_a: usb0_vbus_pin@0 { - allwinner,pins = "PG12"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; -}; - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1500000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-int-pll"; -}; - -®_ldo1 { - regulator-name = "vdd-rtc"; -}; - -®_ldo2 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "avcc"; -}; - -®_ldo3 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi"; -}; - -®_usb0_vbus { - gpio = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */ - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins_b>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usb_power_supply { - status = "okay"; -}; - -&usbphy { - pinctrl-names = "default"; - pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>; - usb0_id_det-gpio = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */ - usb0_vbus_det-gpio = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */ - usb0_vbus_power-supply = <&usb_power_supply>; - usb0_vbus-supply = <®_usb0_vbus>; - usb1_vbus-supply = <®_ldo3>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/sun5i-reference-design-tablet.dtsi b/arch/arm/boot/dts/sun5i-reference-design-tablet.dtsi new file mode 100644 index 0000000..ca5d0c4 --- /dev/null +++ b/arch/arm/boot/dts/sun5i-reference-design-tablet.dtsi @@ -0,0 +1,206 @@ +/* + * Copyright 2015 Hans de Goede + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +#include "sunxi-reference-design-tablet.dtsi" + +#include + +/ { + aliases { + serial0 = &uart1; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>; + brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; + default-brightness-level = <8>; + /* TODO: backlight uses axp gpio1 as enable pin */ + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&codec { + pinctrl-names = "default"; + pinctrl-0 = <&codec_pa_pin>; + allwinner,pa-gpios = <&pio 6 10 GPIO_ACTIVE_HIGH>; /* PG10 */ + status = "okay"; +}; + +&cpu0 { + cpu-supply = <®_dcdc2>; +}; + +&ehci0 { + status = "okay"; +}; + +&i2c0 { + axp209: pmic@34 { + reg = <0x34>; + interrupts = <0>; + }; +}; + +&i2c1 { + pcf8563: rtc@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; +}; + +#include "axp209.dtsi" + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_q8>; + vmmc-supply = <®_vcc3v0>; + bus-width = <4>; + cd-gpios = <&pio 6 0 GPIO_ACTIVE_HIGH>; /* PG0 */ + cd-inverted; + status = "okay"; +}; + +&otg_sram { + status = "okay"; +}; + +&pio { + codec_pa_pin: codec_pa_pin@0 { + allwinner,pins = "PG10"; + allwinner,function = "gpio_out"; + allwinner,drive = ; + allwinner,pull = ; + }; + + mmc0_cd_pin_q8: mmc0_cd_pin@0 { + allwinner,pins = "PG0"; + allwinner,function = "gpio_in"; + allwinner,drive = ; + allwinner,pull = ; + }; + + usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 { + allwinner,pins = "PG1"; + allwinner,function = "gpio_in"; + allwinner,drive = ; + allwinner,pull = ; + }; + + usb0_id_detect_pin: usb0_id_detect_pin@0 { + allwinner,pins = "PG2"; + allwinner,function = "gpio_in"; + allwinner,drive = ; + allwinner,pull = ; + }; + + usb0_vbus_pin_a: usb0_vbus_pin@0 { + allwinner,pins = "PG12"; + allwinner,function = "gpio_out"; + allwinner,drive = ; + allwinner,pull = ; + }; +}; + +®_dcdc2 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1500000>; + regulator-name = "vdd-cpu"; +}; + +®_dcdc3 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-int-pll"; +}; + +®_ldo1 { + regulator-name = "vdd-rtc"; +}; + +®_ldo2 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "avcc"; +}; + +®_ldo3 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-wifi"; +}; + +®_usb0_vbus { + gpio = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */ + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins_b>; + status = "okay"; +}; + +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + +&usb_power_supply { + status = "okay"; +}; + +&usbphy { + pinctrl-names = "default"; + pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>; + usb0_id_det-gpio = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */ + usb0_vbus_det-gpio = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */ + usb0_vbus_power-supply = <&usb_power_supply>; + usb0_vbus-supply = <®_usb0_vbus>; + usb1_vbus-supply = <®_ldo3>; + status = "okay"; +}; -- cgit v0.10.2 From 83c9942688b0847b21944e43cd769cc675cd890d Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Fri, 8 Jul 2016 18:05:45 +0200 Subject: ARM: dts: sun5i: reference-design-tablet: Set lradc vref to avcc Set lradc vref to the actual avcc ldo, rather then to the fixed 3v0 regulator from common-regulators.dtsi. Signed-off-by: Hans de Goede Signed-off-by: Maxime Ripard diff --git a/arch/arm/boot/dts/sun5i-reference-design-tablet.dtsi b/arch/arm/boot/dts/sun5i-reference-design-tablet.dtsi index ca5d0c4..e78452c 100644 --- a/arch/arm/boot/dts/sun5i-reference-design-tablet.dtsi +++ b/arch/arm/boot/dts/sun5i-reference-design-tablet.dtsi @@ -92,6 +92,10 @@ #include "axp209.dtsi" +&lradc { + vref-supply = <®_ldo2>; +}; + &mmc0 { pinctrl-names = "default"; pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_q8>; -- cgit v0.10.2 From 86ee09743273e1d0926e321f3288059ed3c7ac37 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Fri, 8 Jul 2016 18:05:46 +0200 Subject: ARM: dts: sun5i: reference-design-tablet: Remove mention of q8 Remove all mention of q8 from sun5i-reference-design-tablet.dtsi. Signed-off-by: Hans de Goede Signed-off-by: Maxime Ripard diff --git a/arch/arm/boot/dts/sun5i-reference-design-tablet.dtsi b/arch/arm/boot/dts/sun5i-reference-design-tablet.dtsi index e78452c..20cc940 100644 --- a/arch/arm/boot/dts/sun5i-reference-design-tablet.dtsi +++ b/arch/arm/boot/dts/sun5i-reference-design-tablet.dtsi @@ -98,7 +98,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_q8>; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>; vmmc-supply = <®_vcc3v0>; bus-width = <4>; cd-gpios = <&pio 6 0 GPIO_ACTIVE_HIGH>; /* PG0 */ @@ -118,7 +118,7 @@ allwinner,pull = ; }; - mmc0_cd_pin_q8: mmc0_cd_pin@0 { + mmc0_cd_pin: mmc0_cd_pin@0 { allwinner,pins = "PG0"; allwinner,function = "gpio_in"; allwinner,drive = ; -- cgit v0.10.2 From f51203b253f26d679d52403d4077ec52d2ec2e17 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Fri, 8 Jul 2016 18:05:47 +0200 Subject: ARM: dts: sun5i: Use sun5i-reference-design-tablet.dtsi for dit4350 dts This results in quite a nice cleanup for this dts file. Note as a side-effect this also enables the on board speaker / headphones out. I've tested that this works as advertised. Signed-off-by: Hans de Goede Signed-off-by: Maxime Ripard diff --git a/arch/arm/boot/dts/sun5i-a13-difrnce-dit4350.dts b/arch/arm/boot/dts/sun5i-a13-difrnce-dit4350.dts index 6546fa0..894c4c4 100644 --- a/arch/arm/boot/dts/sun5i-a13-difrnce-dit4350.dts +++ b/arch/arm/boot/dts/sun5i-a13-difrnce-dit4350.dts @@ -42,185 +42,9 @@ /dts-v1/; #include "sun5i-a13.dtsi" -#include "sunxi-common-regulators.dtsi" -#include -#include -#include -#include -#include +#include "sun5i-reference-design-tablet.dtsi" / { model = "Difrnce DIT4350"; compatible = "difrnce,dit4350", "allwinner,sun5i-a13"; - - aliases { - serial0 = &uart1; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>; - brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; - default-brightness-level = <8>; - /* TODO: backlight uses axp gpio1 as enable pin */ - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&ehci0 { - status = "okay"; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; - - axp209: pmic@34 { - reg = <0x34>; - interrupts = <0>; - }; -}; - -#include "axp209.dtsi" - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; - status = "okay"; - - pcf8563: rtc@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - }; -}; - -&lradc { - vref-supply = <®_ldo2>; - status = "okay"; - - button@200 { - label = "Volume Up"; - linux,code = ; - channel = <0>; - voltage = <200000>; - }; - - button@400 { - label = "Volume Down"; - linux,code = ; - channel = <0>; - voltage = <400000>; - }; -}; - -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_d709>; - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 6 0 GPIO_ACTIVE_HIGH>; /* PG0 */ - cd-inverted; - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -&pio { - mmc0_cd_pin_d709: mmc0_cd_pin@0 { - allwinner,pins = "PG0"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; - - usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 { - allwinner,pins = "PG1"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; - - usb0_id_detect_pin: usb0_id_detect_pin@0 { - allwinner,pins = "PG2"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; -}; - -&pwm { - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_pins>; - status = "okay"; -}; - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1250000>; - regulator-max-microvolt = <1250000>; - regulator-name = "vdd-int-pll"; -}; - -®_ldo1 { - regulator-name = "vdd-rtc"; -}; - -®_ldo2 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "avcc"; -}; - -®_ldo3 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi"; -}; - -®_usb0_vbus { - gpio = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */ - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins_b>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usb0_vbus_pin_a { - allwinner,pins = "PG12"; -}; - -&usbphy { - pinctrl-names = "default"; - pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>; - usb0_id_det-gpio = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */ - usb0_vbus_det-gpio = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */ - usb0_vbus-supply = <®_usb0_vbus>; - usb1_vbus-supply = <®_ldo3>; - status = "okay"; }; -- cgit v0.10.2 From 147c6163daaa2bfda117bb662f5206fc2cc97118 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Fri, 8 Jul 2016 18:05:48 +0200 Subject: ARM: dts: sun5i: Use sun5i-reference-design-tablet.dtsi for utoo p66 dts This results in a nice cleanup for this dts file. Signed-off-by: Hans de Goede Signed-off-by: Maxime Ripard diff --git a/arch/arm/boot/dts/sun5i-a13-utoo-p66.dts b/arch/arm/boot/dts/sun5i-a13-utoo-p66.dts index fa9ddfd..a8b0bcc 100644 --- a/arch/arm/boot/dts/sun5i-a13-utoo-p66.dts +++ b/arch/arm/boot/dts/sun5i-a13-utoo-p66.dts @@ -42,24 +42,20 @@ /dts-v1/; #include "sun5i-a13.dtsi" -#include "sunxi-common-regulators.dtsi" -#include -#include +#include "sun5i-reference-design-tablet.dtsi" #include -#include -#include / { model = "Utoo P66"; compatible = "utoo,p66", "allwinner,sun5i-a13"; - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>; - /* Note levels of 10 / 20% result in backlight off */ - brightness-levels = <0 30 40 50 60 70 80 90 100>; - default-brightness-level = <6>; - /* TODO: backlight uses axp gpio1 as enable pin */ + /* The P66 uses the uart pins as gpios */ + aliases { + /delete-property/serial0; + }; + + chosen { + /delete-property/stdout-path; }; i2c_lcd: i2c@0 { @@ -73,39 +69,21 @@ }; }; -&codec { - pinctrl-names = "default"; - pinctrl-0 = <&codec_pa_pin>; - allwinner,pa-gpios = <&pio 6 3 GPIO_ACTIVE_HIGH>; /* PG3 */ - status = "okay"; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; +&backlight { + /* Note levels of 10 / 20% result in backlight off */ + brightness-levels = <0 30 40 50 60 70 80 90 100>; + default-brightness-level = <6>; }; -&ehci0 { - status = "okay"; +&codec { + allwinner,pa-gpios = <&pio 6 3 GPIO_ACTIVE_HIGH>; /* PG3 */ }; -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; - - axp209: pmic@34 { - reg = <0x34>; - interrupts = <0>; - }; +&codec_pa_pin { + allwinner,pins = "PG3"; }; -#include "axp209.dtsi" - &i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; - status = "okay"; - icn8318: touchscreen@40 { compatible = "chipone,icn8318"; reg = <0x40>; @@ -119,40 +97,6 @@ touchscreen-inverted-x; touchscreen-swapped-x-y; }; - - pcf8563: rtc@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - }; -}; - -&lradc { - vref-supply = <®_ldo2>; - status = "okay"; - - button@200 { - label = "Volume Up"; - linux,code = ; - channel = <0>; - voltage = <200000>; - }; - - button@400 { - label = "Volume Down"; - linux,code = ; - channel = <0>; - voltage = <400000>; - }; -}; - -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_p66>; - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 6 0 GPIO_ACTIVE_HIGH>; /* PG0 */ - cd-inverted; - status = "okay"; }; &mmc2 { @@ -170,39 +114,7 @@ }; }; -&otg_sram { - status = "okay"; -}; - &pio { - codec_pa_pin: codec_pa_pin@0 { - allwinner,pins = "PG3"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; - - mmc0_cd_pin_p66: mmc0_cd_pin@0 { - allwinner,pins = "PG0"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; - - usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 { - allwinner,pins = "PG1"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; - - usb0_id_detect_pin: usb0_id_detect_pin@0 { - allwinner,pins = "PG2"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; - i2c_lcd_pins: i2c_lcd_pin@0 { allwinner,pins = "PG10", "PG12"; allwinner,function = "gpio_out"; @@ -217,67 +129,17 @@ allwinner,pull = ; }; - usb0_vbus_pin_a: usb0_vbus_pin@0 { - allwinner,pins = "PB4"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; -}; - -&pwm { - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_pins>; - status = "okay"; -}; - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1500000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-int-pll"; -}; - -®_ldo1 { - regulator-name = "vdd-rtc"; -}; - -®_ldo2 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "avcc"; -}; - -®_ldo3 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi"; }; ®_usb0_vbus { gpio = <&pio 1 4 GPIO_ACTIVE_HIGH>; /* PB4 */ - status = "okay"; }; -&usb_otg { - dr_mode = "otg"; - status = "okay"; +&uart1 { + /* The P66 uses the uart pins as gpios */ + status = "disabled"; }; -&usbphy { - pinctrl-names = "default"; - pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>; - usb0_id_det-gpio = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */ - usb0_vbus_det-gpio = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */ - usb0_vbus-supply = <®_usb0_vbus>; - usb1_vbus-supply = <®_ldo3>; - status = "okay"; +&usb0_vbus_pin_a { + allwinner,pins = "PB4"; }; -- cgit v0.10.2 From edbc6f1f1d3330017903209189816f15fd9ba5cd Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Fri, 8 Jul 2016 18:05:49 +0200 Subject: ARM: dts: Copy sun8i-q8-common.dtsi sun8i-reference-design-tablet.dtsi Copy sun8i-q8-common.dtsi to sun8i-reference-design-tablet.dtsi. This is part of renaming all the sun?i-q8-common.dtsi files to sun?i-reference-design-tablet.dtsi since most of the hw-config in there is shared by all sunxi tablets. Note that in this case we keep sun5i-q8-common.dtsi as it is shared between a23 / a33 q8 tablets. Also we leave the usb-wifi config in there (rather then in sun8i-reference-design-tablet.dtsi) as most sun8i tablets use sdio wifi rather then usb wifi. Signed-off-by: Hans de Goede Signed-off-by: Maxime Ripard diff --git a/arch/arm/boot/dts/sun8i-q8-common.dtsi b/arch/arm/boot/dts/sun8i-q8-common.dtsi index 0b85ea4..60fa958 100644 --- a/arch/arm/boot/dts/sun8i-q8-common.dtsi +++ b/arch/arm/boot/dts/sun8i-q8-common.dtsi @@ -40,181 +40,12 @@ * OTHER DEALINGS IN THE SOFTWARE. */ #include "sunxi-reference-design-tablet.dtsi" - -#include - -/ { - aliases { - serial0 = &r_uart; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pinctrl-names = "default"; - pinctrl-0 = <&bl_en_pin_q8>; - pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>; - brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; - default-brightness-level = <8>; - enable-gpios = <&pio 7 6 GPIO_ACTIVE_HIGH>; /* PH6 */ - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; +#include "sun8i-reference-design-tablet.dtsi" &ehci0 { status = "okay"; }; -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_q8>; - vmmc-supply = <®_dcdc1>; - bus-width = <4>; - cd-gpios = <&pio 1 4 GPIO_ACTIVE_HIGH>; /* PB4 */ - cd-inverted; - status = "okay"; -}; - -&pio { - bl_en_pin_q8: bl_en_pin@0 { - allwinner,pins = "PH6"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; - - mmc0_cd_pin_q8: mmc0_cd_pin@0 { - allwinner,pins = "PB4"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; - - usb0_id_detect_pin: usb0_id_detect_pin@0 { - allwinner,pins = "PH8"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; -}; - -&r_rsb { - status = "okay"; - - axp22x: pmic@3a3 { - compatible = "x-powers,axp223"; - reg = <0x3a3>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - eldoin-supply = <®_dcdc1>; - x-powers,drive-vbus-en; - }; -}; - -#include "axp22x.dtsi" - -®_aldo1 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc-io"; -}; - -®_aldo2 { - regulator-always-on; - regulator-min-microvolt = <2350000>; - regulator-max-microvolt = <2650000>; - regulator-name = "vdd-dll"; -}; - -®_aldo3 { - regulator-always-on; - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-pll-avcc"; -}; - -®_dc1sw { - regulator-name = "vcc-lcd"; -}; - -®_dc5ldo { - regulator-always-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-cpus"; -}; - -®_dcdc1 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc-3v0"; -}; - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-sys"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc5 { - regulator-always-on; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-name = "vcc-dram"; -}; - -®_dldo1 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi"; -}; - -®_drivevbus { - regulator-name = "usb0-vbus"; - status = "okay"; -}; - -®_rtc_ldo { - regulator-name = "vcc-rtc"; -}; - -&r_uart { - pinctrl-names = "default"; - pinctrl-0 = <&r_uart_pins_a>; - status = "okay"; -}; - -&simplefb_lcd { - vcc-lcd-supply = <®_dc1sw>; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usb_power_supply { - status = "okay"; -}; - &usbphy { - pinctrl-names = "default"; - pinctrl-0 = <&usb0_id_detect_pin>; - usb0_id_det-gpio = <&pio 7 8 GPIO_ACTIVE_HIGH>; /* PH8 */ - usb0_vbus_power-supply = <&usb_power_supply>; - usb0_vbus-supply = <®_drivevbus>; usb1_vbus-supply = <®_dldo1>; - status = "okay"; }; diff --git a/arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi b/arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi new file mode 100644 index 0000000..b8546ef --- /dev/null +++ b/arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi @@ -0,0 +1,215 @@ +/* + * Copyright 2015 Hans de Goede + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +#include "sunxi-reference-design-tablet.dtsi" + +#include + +/ { + aliases { + serial0 = &r_uart; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&bl_en_pin>; + pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>; + brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; + default-brightness-level = <8>; + enable-gpios = <&pio 7 6 GPIO_ACTIVE_HIGH>; /* PH6 */ + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>; + vmmc-supply = <®_dcdc1>; + bus-width = <4>; + cd-gpios = <&pio 1 4 GPIO_ACTIVE_HIGH>; /* PB4 */ + cd-inverted; + status = "okay"; +}; + +&pio { + bl_en_pin: bl_en_pin@0 { + allwinner,pins = "PH6"; + allwinner,function = "gpio_in"; + allwinner,drive = ; + allwinner,pull = ; + }; + + mmc0_cd_pin: mmc0_cd_pin@0 { + allwinner,pins = "PB4"; + allwinner,function = "gpio_in"; + allwinner,drive = ; + allwinner,pull = ; + }; + + usb0_id_detect_pin: usb0_id_detect_pin@0 { + allwinner,pins = "PH8"; + allwinner,function = "gpio_in"; + allwinner,drive = ; + allwinner,pull = ; + }; +}; + +&r_rsb { + status = "okay"; + + axp22x: pmic@3a3 { + compatible = "x-powers,axp223"; + reg = <0x3a3>; + interrupt-parent = <&nmi_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + eldoin-supply = <®_dcdc1>; + x-powers,drive-vbus-en; + }; +}; + +#include "axp22x.dtsi" + +®_aldo1 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc-io"; +}; + +®_aldo2 { + regulator-always-on; + regulator-min-microvolt = <2350000>; + regulator-max-microvolt = <2650000>; + regulator-name = "vdd-dll"; +}; + +®_aldo3 { + regulator-always-on; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-pll-avcc"; +}; + +®_dc1sw { + regulator-name = "vcc-lcd"; +}; + +®_dc5ldo { + regulator-always-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-cpus"; +}; + +®_dcdc1 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc-3v0"; +}; + +®_dcdc2 { + regulator-always-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-sys"; +}; + +®_dcdc3 { + regulator-always-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-cpu"; +}; + +®_dcdc5 { + regulator-always-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-name = "vcc-dram"; +}; + +®_dldo1 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-wifi"; +}; + +®_drivevbus { + regulator-name = "usb0-vbus"; + status = "okay"; +}; + +®_rtc_ldo { + regulator-name = "vcc-rtc"; +}; + +&r_uart { + pinctrl-names = "default"; + pinctrl-0 = <&r_uart_pins_a>; + status = "okay"; +}; + +&simplefb_lcd { + vcc-lcd-supply = <®_dc1sw>; +}; + +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + +&usb_power_supply { + status = "okay"; +}; + +&usbphy { + pinctrl-names = "default"; + pinctrl-0 = <&usb0_id_detect_pin>; + usb0_id_det-gpio = <&pio 7 8 GPIO_ACTIVE_HIGH>; /* PH8 */ + usb0_vbus_power-supply = <&usb_power_supply>; + usb0_vbus-supply = <®_drivevbus>; + status = "okay"; +}; -- cgit v0.10.2 From 672244fa72e5ab29b983b82055eb2ee1fdd983fc Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Fri, 8 Jul 2016 18:05:50 +0200 Subject: ARM: dts: sun8i: reference-design-tablet: Add drivevbus-supply Add a drivevbus-supply property so that the drivevbus regulator reports the right voltage value. Signed-off-by: Hans de Goede Signed-off-by: Maxime Ripard diff --git a/arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi b/arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi index b8546ef..9d90361 100644 --- a/arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi +++ b/arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi @@ -105,6 +105,7 @@ interrupt-parent = <&nmi_intc>; interrupts = <0 IRQ_TYPE_LEVEL_LOW>; eldoin-supply = <®_dcdc1>; + drivevbus-supply = <®_vcc5v0>; x-powers,drive-vbus-en; }; }; -- cgit v0.10.2 From a0e4eb4b81b44663f21b289d8126ca6f6dc8a863 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Fri, 8 Jul 2016 18:05:51 +0200 Subject: ARM: dts: sun8i: Use sun8i-reference-design-tablet for polaroid mid2809pxe04 This results in quite a nice cleanup for this dts file. Signed-off-by: Hans de Goede Signed-off-by: Maxime Ripard diff --git a/arch/arm/boot/dts/sun8i-a23-polaroid-mid2809pxe04.dts b/arch/arm/boot/dts/sun8i-a23-polaroid-mid2809pxe04.dts index e8c3f21..6d06e24 100644 --- a/arch/arm/boot/dts/sun8i-a23-polaroid-mid2809pxe04.dts +++ b/arch/arm/boot/dts/sun8i-a23-polaroid-mid2809pxe04.dts @@ -42,214 +42,9 @@ /dts-v1/; #include "sun8i-a23.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include -#include -#include +#include "sun8i-reference-design-tablet.dtsi" / { model = "Polaroid MID2809PXE04 tablet"; compatible = "polaroid,mid2809pxe04", "allwinner,sun8i-a23"; - - aliases { - serial0 = &r_uart; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pinctrl-names = "default"; - pinctrl-0 = <&bl_en_pin_mid2809>; - pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>; - brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; - default-brightness-level = <8>; - enable-gpios = <&pio 7 6 GPIO_ACTIVE_HIGH>; /* PH6 */ - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; - status = "okay"; -}; - -&lradc { - vref-supply = <®_vcc3v0>; - status = "okay"; - - button@200 { - label = "Volume Up"; - linux,code = ; - channel = <0>; - voltage = <200000>; - }; - - button@400 { - label = "Volume Down"; - linux,code = ; - channel = <0>; - voltage = <400000>; - }; -}; - -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_mid2809>; - vmmc-supply = <®_dcdc1>; - bus-width = <4>; - cd-gpios = <&pio 1 4 GPIO_ACTIVE_HIGH>; /* PB4 */ - cd-inverted; - status = "okay"; -}; - -&pio { - bl_en_pin_mid2809: bl_en_pin@0 { - allwinner,pins = "PH6"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; - - mmc0_cd_pin_mid2809: mmc0_cd_pin@0 { - allwinner,pins = "PB4"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; - - usb0_id_detect_pin: usb0_id_detect_pin@0 { - allwinner,pins = "PH8"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; -}; - -&pwm { - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_pins>; - status = "okay"; -}; - -&r_rsb { - status = "okay"; - - axp22x: pmic@3a3 { - compatible = "x-powers,axp223"; - reg = <0x3a3>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - eldoin-supply = <®_dcdc1>; - x-powers,drive-vbus-en; - }; -}; - -&r_uart { - pinctrl-names = "default"; - pinctrl-0 = <&r_uart_pins_a>; - status = "okay"; -}; - -#include "axp22x.dtsi" - -®_aldo1 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc-io"; -}; - -®_aldo2 { - regulator-always-on; - regulator-min-microvolt = <2350000>; - regulator-max-microvolt = <2650000>; - regulator-name = "vdd-dll"; -}; - -®_aldo3 { - regulator-always-on; - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-pll-avcc"; -}; - -®_dc1sw { - regulator-name = "vcc-lcd"; -}; - -®_dc5ldo { - regulator-always-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-cpus"; -}; - -®_dcdc1 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc-3v0"; -}; - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-sys"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc5 { - regulator-always-on; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-name = "vcc-dram"; -}; - -®_drivevbus { - regulator-name = "usb0-vbus"; - status = "okay"; -}; - -®_rtc_ldo { - regulator-name = "vcc-rtc"; -}; - -&simplefb_lcd { - vcc-lcd-supply = <®_dc1sw>; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usb_power_supply { - status = "okay"; -}; - -&usbphy { - pinctrl-names = "default"; - pinctrl-0 = <&usb0_id_detect_pin>; - usb0_id_det-gpio = <&pio 7 8 GPIO_ACTIVE_HIGH>; /* PH8 */ - usb0_vbus_power-supply = <&usb_power_supply>; - usb0_vbus-supply = <®_drivevbus>; - status = "okay"; }; -- cgit v0.10.2 From 8bb55cf157fdb6c5e930b2dcc47bc72a24646f75 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Fri, 8 Jul 2016 18:05:53 +0200 Subject: ARM: dts: sun8i: Use sun8i-reference-design-tablet for ga10h dts This results in quite a nice cleanup for this dts file. As an added bonus this also enables backlight, regulator and full otg support. I've tested that all these works as advertised. Signed-off-by: Hans de Goede Signed-off-by: Maxime Ripard diff --git a/arch/arm/boot/dts/sun8i-a33-ga10h-v1.1.dts b/arch/arm/boot/dts/sun8i-a33-ga10h-v1.1.dts index 1aefc67..6566032 100644 --- a/arch/arm/boot/dts/sun8i-a33-ga10h-v1.1.dts +++ b/arch/arm/boot/dts/sun8i-a33-ga10h-v1.1.dts @@ -42,59 +42,18 @@ /dts-v1/; #include "sun8i-a33.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include -#include +#include "sun8i-reference-design-tablet.dtsi" / { model = "Allwinner GA10H Quad Core Tablet (v1.1)"; compatible = "allwinner,ga10h-v1.1", "allwinner,sun8i-a33"; - - aliases { - serial0 = &r_uart; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; }; &ehci0 { status = "okay"; }; -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; - status = "okay"; -}; - &lradc { - vref-supply = <®_vcc3v0>; - status = "okay"; - - button@200 { - label = "Volume Up"; - linux,code = ; - channel = <0>; - voltage = <200000>; - }; - - button@400 { - label = "Volume Down"; - linux,code = ; - channel = <0>; - voltage = <400000>; - }; - button@600 { label = "Back"; linux,code = ; @@ -103,40 +62,6 @@ }; }; -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_q8h>; - vmmc-supply = <®_vcc3v0>; - bus-width = <4>; - cd-gpios = <&pio 1 4 GPIO_ACTIVE_HIGH>; /* PB4 */ - cd-inverted; - status = "okay"; -}; - &ohci0 { status = "okay"; }; - -&pio { - mmc0_cd_pin_q8h: mmc0_cd_pin@0 { - allwinner,pins = "PB4"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; -}; - -&r_uart { - pinctrl-names = "default"; - pinctrl-0 = <&r_uart_pins_a>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "host"; - status = "okay"; -}; - -&usbphy { - status = "okay"; -}; -- cgit v0.10.2 From 3e48bb211c8753ad1bc1f1aab7ce8d32c8541f27 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Fri, 8 Jul 2016 18:05:55 +0200 Subject: ARM: dts: sun8i: Add dts file for Polaroid MID2407PXE03 tablet The Polaroid MID2407PXE03 is an a23 based 7" tablet based on a M86_MB V2.0 PCB, featuring a 800x480 LCD, 512MB RAM, 4G NAND, esp8089 wifi, gsl1680 touchschreen, micro-sd slot, 3.5mm headphone jack and a micro-usb otg connector which doubles as charging port. Signed-off-by: Hans de Goede Signed-off-by: Maxime Ripard diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 3ccc653..910e578 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -754,6 +754,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \ sun8i-a23-gt90h-v4.dtb \ sun8i-a23-ippo-q8h-v5.dtb \ sun8i-a23-ippo-q8h-v1.2.dtb \ + sun8i-a23-polaroid-mid2407pxe03.dtb \ sun8i-a23-polaroid-mid2809pxe04.dtb \ sun8i-a23-q8-tablet.dtb \ sun8i-a33-et-q8-v1.6.dtb \ diff --git a/arch/arm/boot/dts/sun8i-a23-polaroid-mid2407pxe03.dts b/arch/arm/boot/dts/sun8i-a23-polaroid-mid2407pxe03.dts new file mode 100644 index 0000000..e300442 --- /dev/null +++ b/arch/arm/boot/dts/sun8i-a23-polaroid-mid2407pxe03.dts @@ -0,0 +1,50 @@ +/* + * Copyright 2016 Hans de Goede + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun8i-a23.dtsi" +#include "sun8i-reference-design-tablet.dtsi" + +/ { + model = "Polaroid MID2407PXE03 tablet"; + compatible = "polaroid,mid2407pxe03", "allwinner,sun8i-a23"; +}; -- cgit v0.10.2 From de427ad22327e2d8d6354feeec82796f79d999ea Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Fri, 8 Jul 2016 18:05:56 +0200 Subject: ARM: dts: sun8i: Add dts file for inet86dz board The inet86dz board is a board used in 7" tablets from various oems. These tablets are a23 based 7" tablets featuring a 1024x600 LCD, 512MB RAM, 4G NAND, rtl8188etv usb wifi, gsl1680 touchschreen, micro-sd slot, 3.5mm headphone jack and a micro-usb otg connector which doubles as charging port. Signed-off-by: Hans de Goede Signed-off-by: Maxime Ripard diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 910e578..fd972ec 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -752,6 +752,7 @@ dtb-$(CONFIG_MACH_SUN7I) += \ dtb-$(CONFIG_MACH_SUN8I) += \ sun8i-a23-evb.dtb \ sun8i-a23-gt90h-v4.dtb \ + sun8i-a23-inet86dz.dtb \ sun8i-a23-ippo-q8h-v5.dtb \ sun8i-a23-ippo-q8h-v1.2.dtb \ sun8i-a23-polaroid-mid2407pxe03.dtb \ diff --git a/arch/arm/boot/dts/sun8i-a23-inet86dz.dts b/arch/arm/boot/dts/sun8i-a23-inet86dz.dts new file mode 100644 index 0000000..0f9f71b --- /dev/null +++ b/arch/arm/boot/dts/sun8i-a23-inet86dz.dts @@ -0,0 +1,58 @@ +/* + * Copyright 2016 Hans de Goede + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun8i-a23.dtsi" +#include "sun8i-reference-design-tablet.dtsi" + +/ { + model = "INet-86DZ Rev 01"; + compatible = "primux,inet86dz", "allwinner,sun8i-a23"; +}; + +&ehci0 { + status = "okay"; +}; + +&usbphy { + usb1_vbus-supply = <®_dldo1>; +}; -- cgit v0.10.2