From 9439eb3ab9d1ece6e4ad7baaa4a7f534f9b9dab0 Mon Sep 17 00:00:00 2001 From: Will Deacon Date: Tue, 3 Sep 2013 10:44:00 +0100 Subject: asm-generic: io: implement relaxed accessor macros as conditional wrappers {read,write}{b,w,l,q}_relaxed are implemented by some architectures in order to permit memory-mapped I/O accesses with weaker barrier semantics than the non-relaxed variants. This patch adds wrappers to asm-generic so that drivers can rely on the relaxed accessors being available, even if they don't always provide weaker ordering guarantees. Since some architectures both include asm-generic/io.h and define some relaxed accessors, the definitions here are conditional for the time being. Cc: Arnd Bergmann Signed-off-by: Will Deacon diff --git a/include/asm-generic/io.h b/include/asm-generic/io.h index b8fdc57..fc8dc0e 100644 --- a/include/asm-generic/io.h +++ b/include/asm-generic/io.h @@ -53,18 +53,27 @@ static inline u32 __raw_readl(const volatile void __iomem *addr) #endif #define readb __raw_readb +#ifndef readb_relaxed +#define readb_relaxed readb +#endif #define readw readw static inline u16 readw(const volatile void __iomem *addr) { return __le16_to_cpu(__raw_readw(addr)); } +#ifndef readw_relaxed +#define readw_relaxed readw +#endif #define readl readl static inline u32 readl(const volatile void __iomem *addr) { return __le32_to_cpu(__raw_readl(addr)); } +#ifndef readl_relaxed +#define readl_relaxed readl +#endif #ifndef __raw_writeb static inline void __raw_writeb(u8 b, volatile void __iomem *addr) @@ -88,8 +97,19 @@ static inline void __raw_writel(u32 b, volatile void __iomem *addr) #endif #define writeb __raw_writeb +#ifndef writeb_relaxed +#define writeb_relaxed writeb +#endif + #define writew(b,addr) __raw_writew(__cpu_to_le16(b),addr) +#ifndef writew_relaxed +#define writew_relaxed writew +#endif + #define writel(b,addr) __raw_writel(__cpu_to_le32(b),addr) +#ifndef writel_relaxed +#define writel_relaxed writel +#endif #ifdef CONFIG_64BIT #ifndef __raw_readq @@ -104,6 +124,9 @@ static inline u64 readq(const volatile void __iomem *addr) { return __le64_to_cpu(__raw_readq(addr)); } +#ifndef readq_relaxed +#define readq_relaxed readq +#endif #ifndef __raw_writeq static inline void __raw_writeq(u64 b, volatile void __iomem *addr) @@ -113,6 +136,9 @@ static inline void __raw_writeq(u64 b, volatile void __iomem *addr) #endif #define writeq(b, addr) __raw_writeq(__cpu_to_le64(b), addr) +#ifndef writeq_relaxed +#define writeq_relaxed writeq +#endif #endif /* CONFIG_64BIT */ #ifndef PCI_IOBASE -- cgit v0.10.2 From e3bc1e2421a14dcc273bf945343a6c948e839c8c Mon Sep 17 00:00:00 2001 From: Will Deacon Date: Wed, 4 Sep 2013 11:37:53 +0100 Subject: microblaze: io: remove dummy relaxed accessor macros These are now defined by asm-generic/io.h, so we don't need the private definitions anymore. Acked-by: Michal Simek Signed-off-by: Will Deacon diff --git a/arch/microblaze/include/asm/io.h b/arch/microblaze/include/asm/io.h index 433751b..940f5fc 100644 --- a/arch/microblaze/include/asm/io.h +++ b/arch/microblaze/include/asm/io.h @@ -69,12 +69,4 @@ extern void __iomem *ioremap(phys_addr_t address, unsigned long size); #include -#define readb_relaxed readb -#define readw_relaxed readw -#define readl_relaxed readl - -#define writeb_relaxed writeb -#define writew_relaxed writew -#define writel_relaxed writel - #endif /* _ASM_MICROBLAZE_IO_H */ -- cgit v0.10.2 From 916136b374566181386bb79ed638de8a8d8b426e Mon Sep 17 00:00:00 2001 From: Will Deacon Date: Wed, 4 Sep 2013 11:37:53 +0100 Subject: s390: io: remove dummy relaxed accessor macros for reads These are now defined by asm-generic/io.h, so we don't need the private definitions anymore. Cc: Heiko Carstens Cc: Martin Schwidefsky Signed-off-by: Will Deacon diff --git a/arch/s390/include/asm/io.h b/arch/s390/include/asm/io.h index cd6b9ee..722befd 100644 --- a/arch/s390/include/asm/io.h +++ b/arch/s390/include/asm/io.h @@ -60,11 +60,6 @@ static inline void iounmap(volatile void __iomem *addr) #define __raw_writel zpci_write_u32 #define __raw_writeq zpci_write_u64 -#define readb_relaxed readb -#define readw_relaxed readw -#define readl_relaxed readl -#define readq_relaxed readq - #endif /* CONFIG_PCI */ #include -- cgit v0.10.2 From affd2ae5de035e3edc212985299bd3da2660ce1d Mon Sep 17 00:00:00 2001 From: Will Deacon Date: Wed, 4 Sep 2013 11:37:53 +0100 Subject: xtensa: io: remove dummy relaxed accessor macros for reads These are now defined by asm-generic/io.h, so we don't need the private definitions anymore. Cc: Chris Zankel Acked-by: Max Filippov Signed-off-by: Will Deacon diff --git a/arch/xtensa/include/asm/io.h b/arch/xtensa/include/asm/io.h index 7494420..fe1600a 100644 --- a/arch/xtensa/include/asm/io.h +++ b/arch/xtensa/include/asm/io.h @@ -74,13 +74,6 @@ static inline void iounmap(volatile void __iomem *addr) #endif /* CONFIG_MMU */ -/* - * Generic I/O - */ -#define readb_relaxed readb -#define readw_relaxed readw -#define readl_relaxed readl - #endif /* __KERNEL__ */ #include -- cgit v0.10.2 From 88a681698008515103e9a5afad229e25510c1e43 Mon Sep 17 00:00:00 2001 From: Will Deacon Date: Tue, 3 Sep 2013 18:36:05 +0100 Subject: frv: io: implement dummy relaxed accessor macros for writes write{b,w,l}_relaxed are implemented by some architectures in order to permit memory-mapped I/O accesses with weaker barrier semantics than the non-relaxed variants. This patch adds dummy macros for the write accessors to frv, in the same vein as the dummy definitions for the relaxed read accessors. Cc: David Howells Signed-off-by: Will Deacon diff --git a/arch/frv/include/asm/io.h b/arch/frv/include/asm/io.h index 8cb50a2..99bb7ef 100644 --- a/arch/frv/include/asm/io.h +++ b/arch/frv/include/asm/io.h @@ -243,6 +243,9 @@ static inline void writel(uint32_t datum, volatile void __iomem *addr) __flush_PCI_writes(); } +#define writeb_relaxed writeb +#define writew_relaxed writew +#define writel_relaxed writel /* Values for nocacheflag and cmode */ #define IOMAP_FULL_CACHING 0 -- cgit v0.10.2 From 62e8abf7161b6a0dd32752cd7c60237988f8bff7 Mon Sep 17 00:00:00 2001 From: Will Deacon Date: Tue, 3 Sep 2013 18:56:46 +0100 Subject: cris: io: implement dummy relaxed accessor macros for writes write{b,w,l}_relaxed are implemented by some architectures in order to permit memory-mapped I/O accesses with weaker barrier semantics than the non-relaxed variants. This patch adds dummy macros for the write accessors to Cris, in the same vein as the dummy definitions for the relaxed read accessors. Cc: Mikael Starvik Acked-by: Jesper Nilsson Signed-off-by: Will Deacon diff --git a/arch/cris/include/asm/io.h b/arch/cris/include/asm/io.h index e59dba1..752a3f4 100644 --- a/arch/cris/include/asm/io.h +++ b/arch/cris/include/asm/io.h @@ -112,6 +112,9 @@ static inline void writel(unsigned int b, volatile void __iomem *addr) else *(volatile unsigned int __force *) addr = b; } +#define writeb_relaxed(b, addr) writeb(b, addr) +#define writew_relaxed(b, addr) writew(b, addr) +#define writel_relaxed(b, addr) writel(b, addr) #define __raw_writeb writeb #define __raw_writew writew #define __raw_writel writel -- cgit v0.10.2 From f6b3b7a9fa44ffa01f9c4f5ed13a9c48921e1ff2 Mon Sep 17 00:00:00 2001 From: Will Deacon Date: Tue, 3 Sep 2013 19:10:11 +0100 Subject: ia64: io: implement dummy relaxed accessor macros for writes write{b,w,l,q}_relaxed are implemented by some architectures in order to permit memory-mapped I/O accesses with weaker barrier semantics than the non-relaxed variants. This patch adds dummy macros for the write accessors to ia64, which may be able to be optimised in a similar manner to the relaxed read accessors at a later date. Cc: Tony Luck Signed-off-by: Will Deacon diff --git a/arch/ia64/include/asm/io.h b/arch/ia64/include/asm/io.h index bee0acd..80a7e34 100644 --- a/arch/ia64/include/asm/io.h +++ b/arch/ia64/include/asm/io.h @@ -393,6 +393,10 @@ __writeq (unsigned long val, volatile void __iomem *addr) #define writew(v,a) __writew((v), (a)) #define writel(v,a) __writel((v), (a)) #define writeq(v,a) __writeq((v), (a)) +#define writeb_relaxed(v,a) __writeb((v), (a)) +#define writew_relaxed(v,a) __writew((v), (a)) +#define writel_relaxed(v,a) __writel((v), (a)) +#define writeq_relaxed(v,a) __writeq((v), (a)) #define __raw_writeb writeb #define __raw_writew writew #define __raw_writel writel -- cgit v0.10.2 From cb147c0f0b33f5ba37dfd07014f2973a53bc5d62 Mon Sep 17 00:00:00 2001 From: Will Deacon Date: Tue, 3 Sep 2013 19:11:58 +0100 Subject: m32r: io: implement dummy relaxed accessor macros for writes write{b,w,l}_relaxed are implemented by some architectures in order to permit memory-mapped I/O accesses with weaker barrier semantics than the non-relaxed variants. This patch adds dummy macros for the write accessors to m32r, in the same vein as the dummy definitions for the relaxed read accessors. Cc: Hirokazu Takata Signed-off-by: Will Deacon diff --git a/arch/m32r/include/asm/io.h b/arch/m32r/include/asm/io.h index 4010f1f..6e7787f 100644 --- a/arch/m32r/include/asm/io.h +++ b/arch/m32r/include/asm/io.h @@ -161,6 +161,9 @@ static inline void _writel(unsigned long l, unsigned long addr) #define __raw_writeb writeb #define __raw_writew writew #define __raw_writel writel +#define writeb_relaxed writeb +#define writew_relaxed writew +#define writel_relaxed writel #define ioread8 read #define ioread16 readw -- cgit v0.10.2 From 88a9192e216fef5f198f860d14e84f7e3c840ace Mon Sep 17 00:00:00 2001 From: Will Deacon Date: Tue, 3 Sep 2013 19:15:42 +0100 Subject: m68k: io: implement dummy relaxed accessor macros for writes write{b,w,l}_relaxed are implemented by some architectures in order to permit memory-mapped I/O accesses with weaker barrier semantics than the non-relaxed variants. This patch adds dummy macros for the write accessors to m68k, in the same vein as the dummy definitions for the relaxed read accessors. Additionally, the existing relaxed read accessors are moved into asm/io.h, so that they can be used by m68k targets with an MMU. Acked-by: Geert Uytterhoeven Signed-off-by: Will Deacon diff --git a/arch/m68k/include/asm/io.h b/arch/m68k/include/asm/io.h index c70cc91..bccd5a9 100644 --- a/arch/m68k/include/asm/io.h +++ b/arch/m68k/include/asm/io.h @@ -3,3 +3,11 @@ #else #include #endif + +#define readb_relaxed(addr) readb(addr) +#define readw_relaxed(addr) readw(addr) +#define readl_relaxed(addr) readl(addr) + +#define writeb_relaxed(b, addr) writeb(b, addr) +#define writew_relaxed(b, addr) writew(b, addr) +#define writel_relaxed(b, addr) writel(b, addr) diff --git a/arch/m68k/include/asm/io_no.h b/arch/m68k/include/asm/io_no.h index be4b5a8..a93c8cd 100644 --- a/arch/m68k/include/asm/io_no.h +++ b/arch/m68k/include/asm/io_no.h @@ -40,10 +40,6 @@ static inline unsigned int _swapl(volatile unsigned long v) #define readl(addr) \ ({ unsigned int __v = (*(volatile unsigned int *) (addr)); __v; }) -#define readb_relaxed(addr) readb(addr) -#define readw_relaxed(addr) readw(addr) -#define readl_relaxed(addr) readl(addr) - #define writeb(b,addr) (void)((*(volatile unsigned char *) (addr)) = (b)) #define writew(b,addr) (void)((*(volatile unsigned short *) (addr)) = (b)) #define writel(b,addr) (void)((*(volatile unsigned int *) (addr)) = (b)) -- cgit v0.10.2 From 960a5597c39109ed2e12964cd9dc34857e5afee2 Mon Sep 17 00:00:00 2001 From: Will Deacon Date: Tue, 3 Sep 2013 19:17:02 +0100 Subject: mn10300: io: implement dummy relaxed accessor macros for writes write{b,w,l}_relaxed are implemented by some architectures in order to permit memory-mapped I/O accesses with weaker barrier semantics than the non-relaxed variants. This patch adds dummy macros for the write accessors to mn10300, in the same vein as the dummy definitions for the relaxed read accessors. Cc: David Howells Signed-off-by: Will Deacon diff --git a/arch/mn10300/include/asm/io.h b/arch/mn10300/include/asm/io.h index e6ed0d8..897ba3c 100644 --- a/arch/mn10300/include/asm/io.h +++ b/arch/mn10300/include/asm/io.h @@ -67,6 +67,10 @@ static inline void writel(u32 b, volatile void __iomem *addr) #define __raw_writew writew #define __raw_writel writel +#define writeb_relaxed writeb +#define writew_relaxed writew +#define writel_relaxed writel + /*****************************************************************************/ /* * traditional input/output functions -- cgit v0.10.2 From 2f083481cfd38320ebde0b83d836b967a2419d53 Mon Sep 17 00:00:00 2001 From: Will Deacon Date: Wed, 4 Sep 2013 11:34:08 +0100 Subject: parisc: io: implement dummy relaxed accessor macros for writes write{b,w,l,q}_relaxed are implemented by some architectures in order to permit memory-mapped I/O accesses with weaker barrier semantics than the non-relaxed variants. This patch adds dummy macros for the write accessors to parisc, in the same vein as the dummy definitions for the relaxed read accessors. Cc: Helge Deller Signed-off-by: Will Deacon diff --git a/arch/parisc/include/asm/io.h b/arch/parisc/include/asm/io.h index 1f6d2ae..8cd0abf 100644 --- a/arch/parisc/include/asm/io.h +++ b/arch/parisc/include/asm/io.h @@ -217,10 +217,14 @@ static inline void writeq(unsigned long long q, volatile void __iomem *addr) #define writel writel #define writeq writeq -#define readb_relaxed(addr) readb(addr) -#define readw_relaxed(addr) readw(addr) -#define readl_relaxed(addr) readl(addr) -#define readq_relaxed(addr) readq(addr) +#define readb_relaxed(addr) readb(addr) +#define readw_relaxed(addr) readw(addr) +#define readl_relaxed(addr) readl(addr) +#define readq_relaxed(addr) readq(addr) +#define writeb_relaxed(b, addr) writeb(b, addr) +#define writew_relaxed(w, addr) writew(w, addr) +#define writel_relaxed(l, addr) writel(l, addr) +#define writeq_relaxed(q, addr) writeq(q, addr) #define mmiowb() do { } while (0) -- cgit v0.10.2 From 5da590574cbc39e48d1b71d87b62766c044b9b52 Mon Sep 17 00:00:00 2001 From: Will Deacon Date: Wed, 4 Sep 2013 11:34:08 +0100 Subject: powerpc: io: implement dummy relaxed accessor macros for writes write{b,w,l,q}_relaxed are implemented by some architectures in order to permit memory-mapped I/O accesses with weaker barrier semantics than the non-relaxed variants. This patch adds dummy macros for the write accessors to powerpc, in the same vein as the dummy definitions for the relaxed read accessors. Cc: Benjamin Herrenschmidt Signed-off-by: Will Deacon diff --git a/arch/powerpc/include/asm/io.h b/arch/powerpc/include/asm/io.h index 97d3869..9eaf301 100644 --- a/arch/powerpc/include/asm/io.h +++ b/arch/powerpc/include/asm/io.h @@ -617,10 +617,14 @@ static inline void name at \ /* * We don't do relaxed operations yet, at least not with this semantic */ -#define readb_relaxed(addr) readb(addr) -#define readw_relaxed(addr) readw(addr) -#define readl_relaxed(addr) readl(addr) -#define readq_relaxed(addr) readq(addr) +#define readb_relaxed(addr) readb(addr) +#define readw_relaxed(addr) readw(addr) +#define readl_relaxed(addr) readl(addr) +#define readq_relaxed(addr) readq(addr) +#define writeb_relaxed(v, addr) writeb(v, addr) +#define writew_relaxed(v, addr) writew(v, addr) +#define writel_relaxed(v, addr) writel(v, addr) +#define writeq_relaxed(v, addr) writeq(v, addr) #ifdef CONFIG_PPC32 #define mmiowb() -- cgit v0.10.2 From 1191ccb34cf810a0fefaaf5ca3cfe3c5d7675927 Mon Sep 17 00:00:00 2001 From: Will Deacon Date: Wed, 4 Sep 2013 11:34:08 +0100 Subject: sparc: io: implement dummy relaxed accessor macros for writes write{b,w,l,q}_relaxed are implemented by some architectures in order to permit memory-mapped I/O accesses with weaker barrier semantics than the non-relaxed variants. This patch adds dummy macros for the write accessors to sparc, in the same vein as the dummy definitions for the relaxed read accessors. The existing relaxed read{b,w,l} accessors are moved into asm/io.h, since they are identical between 32-bit and 64-bit machines. Acked-by: "David S. Miller" Acked-by: Sam Ravnborg Signed-off-by: Will Deacon diff --git a/arch/sparc/include/asm/io.h b/arch/sparc/include/asm/io.h index f6902cf..493f22c 100644 --- a/arch/sparc/include/asm/io.h +++ b/arch/sparc/include/asm/io.h @@ -10,6 +10,15 @@ * Defines used for both SPARC32 and SPARC64 */ +/* Relaxed accessors for MMIO */ +#define readb_relaxed(__addr) readb(__addr) +#define readw_relaxed(__addr) readw(__addr) +#define readl_relaxed(__addr) readl(__addr) + +#define writeb_relaxed(__b, __addr) writeb(__b, __addr) +#define writew_relaxed(__w, __addr) writew(__w, __addr) +#define writel_relaxed(__l, __addr) writel(__l, __addr) + /* Big endian versions of memory read/write routines */ #define readb_be(__addr) __raw_readb(__addr) #define readw_be(__addr) __raw_readw(__addr) diff --git a/arch/sparc/include/asm/io_32.h b/arch/sparc/include/asm/io_32.h index 9f53290..407ac14 100644 --- a/arch/sparc/include/asm/io_32.h +++ b/arch/sparc/include/asm/io_32.h @@ -4,10 +4,6 @@ #include #include /* struct resource */ -#define readb_relaxed(__addr) readb(__addr) -#define readw_relaxed(__addr) readw(__addr) -#define readl_relaxed(__addr) readl(__addr) - #define IO_SPACE_LIMIT 0xffffffff #define memset_io(d,c,sz) _memset_io(d,c,sz) diff --git a/arch/sparc/include/asm/io_64.h b/arch/sparc/include/asm/io_64.h index 80b54b3..d50e612 100644 --- a/arch/sparc/include/asm/io_64.h +++ b/arch/sparc/include/asm/io_64.h @@ -136,6 +136,7 @@ static inline u32 readl(const volatile void __iomem *addr) } #define readq readq +#define readq_relaxed readq static inline u64 readq(const volatile void __iomem *addr) { u64 ret; @@ -175,6 +176,7 @@ static inline void writel(u32 l, volatile void __iomem *addr) } #define writeq writeq +#define writeq_relaxed writeq static inline void writeq(u64 q, volatile void __iomem *addr) { __asm__ __volatile__("stxa\t%r0, [%1] %2\t/* pci_writeq */" @@ -183,7 +185,6 @@ static inline void writeq(u64 q, volatile void __iomem *addr) : "memory"); } - #define inb inb static inline u8 inb(unsigned long addr) { @@ -264,11 +265,6 @@ static inline void iowrite32_rep(void __iomem *port, const void *buf, unsigned l outsl((unsigned long __force)port, buf, count); } -#define readb_relaxed(__addr) readb(__addr) -#define readw_relaxed(__addr) readw(__addr) -#define readl_relaxed(__addr) readl(__addr) -#define readq_relaxed(__addr) readq(__addr) - /* Valid I/O Space regions are anywhere, because each PCI bus supported * can live in an arbitrary area of the physical address range. */ -- cgit v0.10.2 From 579cadee96542200b69efa3bda7ec4898c8153f6 Mon Sep 17 00:00:00 2001 From: Will Deacon Date: Wed, 4 Sep 2013 11:34:08 +0100 Subject: tile: io: implement dummy relaxed accessor macros for writes write{b,w,l,q}_relaxed are implemented by some architectures in order to permit memory-mapped I/O accesses with weaker barrier semantics than the non-relaxed variants. This patch adds dummy macros for the write accessors to tile, in the same vein as the dummy definitions for the relaxed read accessors. Acked-by: Chris Metcalf Signed-off-by: Will Deacon diff --git a/arch/tile/include/asm/io.h b/arch/tile/include/asm/io.h index 9fe4349..d372641 100644 --- a/arch/tile/include/asm/io.h +++ b/arch/tile/include/asm/io.h @@ -241,6 +241,10 @@ static inline void writeq(u64 val, unsigned long addr) #define readw_relaxed readw #define readl_relaxed readl #define readq_relaxed readq +#define writeb_relaxed writeb +#define writew_relaxed writew +#define writel_relaxed writel +#define writeq_relaxed writeq #define ioread8 readb #define ioread16 readw -- cgit v0.10.2 From cbc908ef8e6babc40cb929f46ea1b8a26cbdbce0 Mon Sep 17 00:00:00 2001 From: Will Deacon Date: Wed, 4 Sep 2013 11:34:08 +0100 Subject: x86: io: implement dummy relaxed accessor macros for writes write{b,w,l,q}_relaxed are implemented by some architectures in order to permit memory-mapped I/O accesses with weaker barrier semantics than the non-relaxed variants. This patch adds dummy macros for the write accessors to x86, in the same vein as the dummy definitions for the relaxed read accessors. Cc: Thomas Gleixner Cc: Ingo Molnar Cc: "H. Peter Anvin" Signed-off-by: Will Deacon diff --git a/arch/x86/include/asm/io.h b/arch/x86/include/asm/io.h index b8237d8..2ea07f5e 100644 --- a/arch/x86/include/asm/io.h +++ b/arch/x86/include/asm/io.h @@ -74,6 +74,9 @@ build_mmio_write(__writel, "l", unsigned int, "r", ) #define __raw_readw __readw #define __raw_readl __readl +#define writeb_relaxed(v, a) __writeb(v, a) +#define writew_relaxed(v, a) __writew(v, a) +#define writel_relaxed(v, a) __writel(v, a) #define __raw_writeb __writeb #define __raw_writew __writew #define __raw_writel __writel @@ -86,6 +89,7 @@ build_mmio_read(readq, "q", unsigned long, "=r", :"memory") build_mmio_write(writeq, "q", unsigned long, "r", :"memory") #define readq_relaxed(a) readq(a) +#define writeq_relaxed(v, a) writeq(v, a) #define __raw_readq(a) readq(a) #define __raw_writeq(val, addr) writeq(val, addr) -- cgit v0.10.2 From a8e0aead70b4af957e6b27b82fba849c6179b707 Mon Sep 17 00:00:00 2001 From: Will Deacon Date: Wed, 4 Sep 2013 12:30:08 +0100 Subject: documentation: memory-barriers: clarify relaxed io accessor semantics This patch extends the paragraph describing the relaxed read io accessors so that the relaxed accessors are defined to be: - Ordered with respect to each other if accessing the same peripheral - Unordered with respect to normal memory accesses - Unordered with respect to LOCK/UNLOCK operations Whilst many architectures will provide stricter semantics, ARM, Alpha and PPC can achieve significant performance gains by taking advantage of some or all of the above relaxations. Cc: Randy Dunlap Cc: Benjamin Herrenschmidt Cc: Paul E. McKenney Cc: David Howells Signed-off-by: Will Deacon diff --git a/Documentation/memory-barriers.txt b/Documentation/memory-barriers.txt index 22a969c..4af4cea 100644 --- a/Documentation/memory-barriers.txt +++ b/Documentation/memory-barriers.txt @@ -2465,10 +2465,15 @@ functions: Please refer to the PCI specification for more information on interactions between PCI transactions. - (*) readX_relaxed() - - These are similar to readX(), but are not guaranteed to be ordered in any - way. Be aware that there is no I/O read barrier available. + (*) readX_relaxed(), writeX_relaxed() + + These are similar to readX() and writeX(), but provide weaker memory + ordering guarantees. Specifically, they do not guarantee ordering with + respect to normal memory accesses (e.g. DMA buffers) nor do they guarantee + ordering with respect to LOCK or UNLOCK operations. If the latter is + required, an mmiowb() barrier can be used. Note that relaxed accesses to + the same peripheral are guaranteed to be ordered with respect to each + other. (*) ioreadX(), iowriteX() -- cgit v0.10.2