From bc3eb7076b2b808f79abd4bd33b6a7feebb6f5d5 Mon Sep 17 00:00:00 2001 From: Andi Kleen Date: Fri, 18 Sep 2009 07:49:25 +0200 Subject: x86: Remove final bits of CONFIG_X86_OLD_MCE Caught by Linus. Reported-by: Linus Torvalds Signed-off-by: Andi Kleen Cc: Hidetoshi Seto Cc: Huang Ying Cc: Bartlomiej Zolnierkiewicz Cc: Borislav Petkov [ fixed up context conflict manually. ] Signed-off-by: Ingo Molnar diff --git a/arch/x86/power/cpu.c b/arch/x86/power/cpu.c index 417c9f5..8aa85f1 100644 --- a/arch/x86/power/cpu.c +++ b/arch/x86/power/cpu.c @@ -243,10 +243,6 @@ static void __restore_processor_state(struct saved_context *ctxt) do_fpu_end(); mtrr_bp_restore(); - -#ifdef CONFIG_X86_OLD_MCE - mcheck_init(&boot_cpu_data); -#endif } /* Needed by apm.c */ -- cgit v0.10.2 From c2777f98c205148f1a0d4f9ac03b9cb20b39b2da Mon Sep 17 00:00:00 2001 From: Daniel Walker Date: Sat, 12 Sep 2009 10:40:20 -0700 Subject: x86: apic: Convert BUG() to BUG_ON() This was done using Coccinelle's BUG_ON semantic patch. Signed-off-by: Daniel Walker Cc: Julia Lawall LKML-Reference: <1252777220-30796-1-git-send-email-dwalker@fifo99.com> Signed-off-by: Ingo Molnar diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c index 159740d..79e5b92 100644 --- a/arch/x86/kernel/apic/apic.c +++ b/arch/x86/kernel/apic/apic.c @@ -1196,8 +1196,7 @@ void __cpuinit setup_local_APIC(void) * Double-check whether this APIC is really registered. * This is meaningless in clustered apic mode, so we skip it. */ - if (!apic->apic_id_registered()) - BUG(); + BUG_ON(!apic->apic_id_registered()); /* * Intel recommends to set DFR, LDR and TPR before enabling -- cgit v0.10.2 From d2374aecda3f6c9b0d13287027132a37311da300 Mon Sep 17 00:00:00 2001 From: Jack Steiner Date: Wed, 9 Sep 2009 10:41:05 -0500 Subject: x86: SGI UV: Fix IPI macros The UV BIOS has changed the way interrupt remapping is being done. This affects the id used for sending IPIs. The upper id bits no longer need to be masked off. Signed-off-by: Jack Steiner Cc: LKML-Reference: <20090909154104.GA25083@sgi.com> Signed-off-by: Ingo Molnar diff --git a/arch/x86/include/asm/uv/uv_hub.h b/arch/x86/include/asm/uv/uv_hub.h index 77a6850..03a0cbd 100644 --- a/arch/x86/include/asm/uv/uv_hub.h +++ b/arch/x86/include/asm/uv/uv_hub.h @@ -422,7 +422,7 @@ static inline void uv_hub_send_ipi(int pnode, int apicid, int vector) unsigned long val; val = (1UL << UVH_IPI_INT_SEND_SHFT) | - ((apicid & 0x3f) << UVH_IPI_INT_APIC_ID_SHFT) | + ((apicid) << UVH_IPI_INT_APIC_ID_SHFT) | (vector << UVH_IPI_INT_VECTOR_SHFT); uv_write_global_mmr64(pnode, UVH_IPI_INT, val); } -- cgit v0.10.2 From 8dc579e868addafd24c0a015c12f0e536b1084b1 Mon Sep 17 00:00:00 2001 From: Jack Steiner Date: Thu, 10 Sep 2009 09:31:49 -0500 Subject: x86: SGI UV: Add volatile semantics to macros that access chipset registers Add volatile-semantics to the SGI UV read/write macros that are used to access chipset memory mapped registers. No direct references to volatile are made. Instead the readq/writeq macros are used. Signed-off-by: Jack Steiner Cc: linux-mm@kvack.org Cc: dwalker@fifo99.com Cc: cfriesen@nortel.com LKML-Reference: <20090910143149.GA14273@sgi.com> Signed-off-by: Ingo Molnar diff --git a/arch/x86/include/asm/uv/uv_hub.h b/arch/x86/include/asm/uv/uv_hub.h index 03a0cbd..04eb6c9 100644 --- a/arch/x86/include/asm/uv/uv_hub.h +++ b/arch/x86/include/asm/uv/uv_hub.h @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -258,13 +259,13 @@ static inline unsigned long *uv_global_mmr32_address(int pnode, static inline void uv_write_global_mmr32(int pnode, unsigned long offset, unsigned long val) { - *uv_global_mmr32_address(pnode, offset) = val; + writeq(val, uv_global_mmr32_address(pnode, offset)); } static inline unsigned long uv_read_global_mmr32(int pnode, unsigned long offset) { - return *uv_global_mmr32_address(pnode, offset); + return readq(uv_global_mmr32_address(pnode, offset)); } /* @@ -281,13 +282,13 @@ static inline unsigned long *uv_global_mmr64_address(int pnode, static inline void uv_write_global_mmr64(int pnode, unsigned long offset, unsigned long val) { - *uv_global_mmr64_address(pnode, offset) = val; + writeq(val, uv_global_mmr64_address(pnode, offset)); } static inline unsigned long uv_read_global_mmr64(int pnode, unsigned long offset) { - return *uv_global_mmr64_address(pnode, offset); + return readq(uv_global_mmr64_address(pnode, offset)); } /* @@ -301,22 +302,22 @@ static inline unsigned long *uv_local_mmr_address(unsigned long offset) static inline unsigned long uv_read_local_mmr(unsigned long offset) { - return *uv_local_mmr_address(offset); + return readq(uv_local_mmr_address(offset)); } static inline void uv_write_local_mmr(unsigned long offset, unsigned long val) { - *uv_local_mmr_address(offset) = val; + writeq(val, uv_local_mmr_address(offset)); } static inline unsigned char uv_read_local_mmr8(unsigned long offset) { - return *((unsigned char *)uv_local_mmr_address(offset)); + return readb(uv_local_mmr_address(offset)); } static inline void uv_write_local_mmr8(unsigned long offset, unsigned char val) { - *((unsigned char *)uv_local_mmr_address(offset)) = val; + writeb(val, uv_local_mmr_address(offset)); } /* -- cgit v0.10.2 From daf7b9c9216e2b82e4c14b7248a85286dab021c3 Mon Sep 17 00:00:00 2001 From: Jack Steiner Date: Wed, 9 Sep 2009 10:43:39 -0500 Subject: x86: SGI UV: Map MMIO-High memory range UV depends on the MMRHI space being identity mapped. The patch: x86: Make 64-bit efi_ioremap use ioremap on MMIO regions changed this to make efi regions at a different address using ioremap. Add the identity mapping to uv_system_init. ( Note this code was previously present but was deleted when BIOS added the ranges to the EFI map - previous efi code identify mapped the ranges. ) Signed-off-by: Jack Steiner LKML-Reference: <20090909154339.GA7946@sgi.com> Signed-off-by: Ingo Molnar diff --git a/arch/x86/kernel/apic/x2apic_uv_x.c b/arch/x86/kernel/apic/x2apic_uv_x.c index 6011593..f5f5886 100644 --- a/arch/x86/kernel/apic/x2apic_uv_x.c +++ b/arch/x86/kernel/apic/x2apic_uv_x.c @@ -389,6 +389,16 @@ static __init void map_gru_high(int max_pnode) map_high("GRU", gru.s.base, shift, max_pnode, map_wb); } +static __init void map_mmr_high(int max_pnode) +{ + union uvh_rh_gam_mmr_overlay_config_mmr_u mmr; + int shift = UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT; + + mmr.v = uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR); + if (mmr.s.enable) + map_high("MMR", mmr.s.base, shift, max_pnode, map_uc); +} + static __init void map_mmioh_high(int max_pnode) { union uvh_rh_gam_mmioh_overlay_config_mmr_u mmioh; @@ -643,6 +653,7 @@ void __init uv_system_init(void) } map_gru_high(max_pnode); + map_mmr_high(max_pnode); map_mmioh_high(max_pnode); uv_cpu_init(); -- cgit v0.10.2 From 2fbd07a5f5d1295fa9b0c0564ec27da7c276a75a Mon Sep 17 00:00:00 2001 From: Suresh Siddha Date: Fri, 18 Sep 2009 19:29:59 -0700 Subject: x86, apic: Use logical flat on intel with <= 8 logical cpus On Intel platforms, we can use logical flat mode if there are <= 8 logical cpu's (irrespective of physical apic id values). This will enable simplified and efficient IPI and device interrupt routing on such platforms. Fix the relevant comments while we are at it. We can clean up default_setup_apic_routing() by using apic->probe() but that is a different item. Signed-off-by: Suresh Siddha Cc: "yinghai@kernel.org" LKML-Reference: <1253327399.3948.747.camel@sbs-t61.sc.intel.com> Signed-off-by: Ingo Molnar diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c index 79e5b92..072aea6 100644 --- a/arch/x86/kernel/apic/apic.c +++ b/arch/x86/kernel/apic/apic.c @@ -61,7 +61,7 @@ unsigned int boot_cpu_physical_apicid = -1U; /* * The highest APIC ID seen during enumeration. * - * This determines the messaging protocol we can use: if all APIC IDs + * On AMD, this determines the messaging protocol we can use: if all APIC IDs * are in the 0 ... 7 range, then we can use logical addressing which * has some performance advantages (better broadcasting). * @@ -1915,24 +1915,14 @@ void __cpuinit generic_processor_info(int apicid, int version) max_physical_apicid = apicid; #ifdef CONFIG_X86_32 - /* - * Would be preferable to switch to bigsmp when CONFIG_HOTPLUG_CPU=y - * but we need to work other dependencies like SMP_SUSPEND etc - * before this can be done without some confusion. - * if (CPU_HOTPLUG_ENABLED || num_processors > 8) - * - Ashok Raj - */ - if (max_physical_apicid >= 8) { - switch (boot_cpu_data.x86_vendor) { - case X86_VENDOR_INTEL: - if (!APIC_XAPIC(version)) { - def_to_bigsmp = 0; - break; - } - /* If P4 and above fall through */ - case X86_VENDOR_AMD: + switch (boot_cpu_data.x86_vendor) { + case X86_VENDOR_INTEL: + if (num_processors > 8) + def_to_bigsmp = 1; + break; + case X86_VENDOR_AMD: + if (max_physical_apicid >= 8) def_to_bigsmp = 1; - } } #endif diff --git a/arch/x86/kernel/apic/probe_64.c b/arch/x86/kernel/apic/probe_64.c index 65edc18..c4cbd308 100644 --- a/arch/x86/kernel/apic/probe_64.c +++ b/arch/x86/kernel/apic/probe_64.c @@ -64,16 +64,23 @@ void __init default_setup_apic_routing(void) apic = &apic_x2apic_phys; else apic = &apic_x2apic_cluster; - printk(KERN_INFO "Setting APIC routing to %s\n", apic->name); } #endif if (apic == &apic_flat) { - if (max_physical_apicid >= 8) - apic = &apic_physflat; - printk(KERN_INFO "Setting APIC routing to %s\n", apic->name); + switch (boot_cpu_data.x86_vendor) { + case X86_VENDOR_INTEL: + if (num_processors > 8) + apic = &apic_physflat; + break; + case X86_VENDOR_AMD: + if (max_physical_apicid >= 8) + apic = &apic_physflat; + } } + printk(KERN_INFO "Setting APIC routing to %s\n", apic->name); + if (is_vsmp_box()) { /* need to update phys_pkg_id */ apic->phys_pkg_id = apicid_phys_pkg_id; -- cgit v0.10.2 From a017421ddcdf34474f1133b27e33ab2ca6c19b96 Mon Sep 17 00:00:00 2001 From: Andreas Herrmann Date: Tue, 15 Sep 2009 17:17:27 +0200 Subject: x86, mce: Fix compile warning in case of CONFIG_SMP=n Fix following compile warning: arch/x86/kernel/cpu/mcheck/mce_amd.c: In function 'threshold_create_bank': arch/x86/kernel/cpu/mcheck/mce_amd.c:492: warning: unused variable 'c' which shows up when kernel is compiled with CONFIG_SMP=n. Signed-off-by: Andreas Herrmann LKML-Reference: <20090915151727.GB21670@alberich.amd.com> Signed-off-by: Ingo Molnar diff --git a/arch/x86/kernel/cpu/mcheck/mce_amd.c b/arch/x86/kernel/cpu/mcheck/mce_amd.c index 8cd5224..83a3d1f 100644 --- a/arch/x86/kernel/cpu/mcheck/mce_amd.c +++ b/arch/x86/kernel/cpu/mcheck/mce_amd.c @@ -489,8 +489,9 @@ static __cpuinit int threshold_create_bank(unsigned int cpu, unsigned int bank) int i, err = 0; struct threshold_bank *b = NULL; char name[32]; +#ifdef CONFIG_SMP struct cpuinfo_x86 *c = &cpu_data(cpu); - +#endif sprintf(name, "threshold_bank%i", bank); -- cgit v0.10.2 From eda6da9286ad5b35b1eb70f6368958a8ee41a9dd Mon Sep 17 00:00:00 2001 From: Yinghai Lu Date: Sat, 19 Sep 2009 11:07:57 -0700 Subject: Revert 'x86: Fix system crash when loading with "reservetop" parameter' After close looking, commit 8126dec3 will break: 1. some cpu feature in early stage too, like cpu_has_x2apic 2. will break built-in-command line 3. will break other memmap= and mem= 4. early_dbgp and early_console that will use early_ioremap to access mmio (?) So revert it. Reported-by: Hugh Dickins , Cc: Linus Torvalds , Cc: Andrew Morton , LKML-Reference: <4AB51DFD.2000904@kernel.org> Signed-off-by: Ingo Molnar diff --git a/arch/x86/kernel/setup.c b/arch/x86/kernel/setup.c index 19f15c4..f5baa2a 100644 --- a/arch/x86/kernel/setup.c +++ b/arch/x86/kernel/setup.c @@ -712,21 +712,6 @@ void __init setup_arch(char **cmdline_p) printk(KERN_INFO "Command line: %s\n", boot_command_line); #endif - strlcpy(command_line, boot_command_line, COMMAND_LINE_SIZE); - *cmdline_p = command_line; - -#ifdef CONFIG_X86_64 - /* - * Must call this twice: Once just to detect whether hardware doesn't - * support NX (so that the early EHCI debug console setup can safely - * call set_fixmap(), and then again after parsing early parameters to - * honor the respective command line option. - */ - check_efer(); -#endif - - parse_early_param(); - /* VMI may relocate the fixmap; do this before touching ioremap area */ vmi_init(); @@ -809,6 +794,21 @@ void __init setup_arch(char **cmdline_p) #endif #endif + strlcpy(command_line, boot_command_line, COMMAND_LINE_SIZE); + *cmdline_p = command_line; + +#ifdef CONFIG_X86_64 + /* + * Must call this twice: Once just to detect whether hardware doesn't + * support NX (so that the early EHCI debug console setup can safely + * call set_fixmap(), and then again after parsing early parameters to + * honor the respective command line option. + */ + check_efer(); +#endif + + parse_early_param(); + #ifdef CONFIG_X86_64 check_efer(); #endif -- cgit v0.10.2 From 9ff6d8e06fbd9249804d43574167c2acc52886be Mon Sep 17 00:00:00 2001 From: Joe Perches Date: Mon, 14 Sep 2009 09:28:07 -0700 Subject: x86, mtrr: Convert loop to a while based construct, avoid naked semicolon Perhaps this is a more readable/standard form. Signed-off-by: Joe Perches LKML-Reference: <1252945687.3937.14.camel@Joe-Laptop.home> Signed-off-by: Ingo Molnar diff --git a/arch/x86/kernel/cpu/mtrr/if.c b/arch/x86/kernel/cpu/mtrr/if.c index 08b6ea4..f04e725 100644 --- a/arch/x86/kernel/cpu/mtrr/if.c +++ b/arch/x86/kernel/cpu/mtrr/if.c @@ -126,8 +126,8 @@ mtrr_write(struct file *file, const char __user *buf, size_t len, loff_t * ppos) return -EINVAL; base = simple_strtoull(line + 5, &ptr, 0); - for (; isspace(*ptr); ++ptr) - ; + while (isspace(*ptr)) + ptr++; if (strncmp(ptr, "size=", 5)) return -EINVAL; @@ -135,14 +135,14 @@ mtrr_write(struct file *file, const char __user *buf, size_t len, loff_t * ppos) size = simple_strtoull(ptr + 5, &ptr, 0); if ((base & 0xfff) || (size & 0xfff)) return -EINVAL; - for (; isspace(*ptr); ++ptr) - ; + while (isspace(*ptr)) + ptr++; if (strncmp(ptr, "type=", 5)) return -EINVAL; ptr += 5; - for (; isspace(*ptr); ++ptr) - ; + while (isspace(*ptr)) + ptr++; for (i = 0; i < MTRR_NUM_TYPES; ++i) { if (strcmp(ptr, mtrr_strings[i])) -- cgit v0.10.2 From efc8f7419ea0a97c38d0b80785c8c3d9ab8a4872 Mon Sep 17 00:00:00 2001 From: Huang Weiyi Date: Fri, 18 Sep 2009 06:39:15 +0800 Subject: x86/i386: Remove duplicated #include Remove duplicated #include in: arch/x86/kernel/cpu/common.c Signed-off-by: Huang Weiyi Signed-off-by: Ingo Molnar diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index 2055fc2..2fea97e 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -34,7 +34,6 @@ #include #include #include -#include #ifdef CONFIG_X86_LOCAL_APIC #include -- cgit v0.10.2 From 8312136fa8b0a3ec7323bbb1a46be8c0c26e994e Mon Sep 17 00:00:00 2001 From: Cyrill Gorcunov Date: Tue, 15 Sep 2009 11:12:30 +0400 Subject: x86, apic: Fix missed handling of discrete apics In case of discrete (pretty old) apics we may have cpu_has_apic bit not set but have to check if smp_found_config (MP spec) is there and apic was not disabled. Also don't forget to print apic/io-apic for such case as well. Signed-off-by: Cyrill Gorcunov Cc: "Maciej W. Rozycki" Cc: Yinghai Lu LKML-Reference: <20090915071230.GA10604@lenovo> Signed-off-by: Ingo Molnar diff --git a/arch/x86/include/asm/apic.h b/arch/x86/include/asm/apic.h index 586b7ad..9a86fb4 100644 --- a/arch/x86/include/asm/apic.h +++ b/arch/x86/include/asm/apic.h @@ -66,6 +66,19 @@ static inline void default_inquire_remote_apic(int apicid) } /* + * With 82489DX we can't rely on apic feature bit + * retrieved via cpuid but still have to deal with + * such an apic chip so we assume that SMP configuration + * is found from MP table (64bit case uses ACPI mostly + * which set smp presence flag as well so we are safe + * to use this helper too). + */ +static inline bool apic_from_smp_config(void) +{ + return smp_found_config && !disable_apic; +} + +/* * Basic functions accessing APICs. */ #ifdef CONFIG_PARAVIRT diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c index 072aea6..2d59dfa 100644 --- a/arch/x86/kernel/apic/apic.c +++ b/arch/x86/kernel/apic/apic.c @@ -978,7 +978,7 @@ void lapic_shutdown(void) { unsigned long flags; - if (!cpu_has_apic) + if (!cpu_has_apic && !apic_from_smp_config()) return; local_irq_save(flags); diff --git a/arch/x86/kernel/apic/io_apic.c b/arch/x86/kernel/apic/io_apic.c index 3c8f9e7..593c4f8 100644 --- a/arch/x86/kernel/apic/io_apic.c +++ b/arch/x86/kernel/apic/io_apic.c @@ -1863,7 +1863,7 @@ __apicdebuginit(int) print_all_ICs(void) print_PIC(); /* don't print out if apic is not there */ - if (!cpu_has_apic || disable_apic) + if (!cpu_has_apic && !apic_from_smp_config()) return 0; print_all_local_APICs(); @@ -1981,7 +1981,7 @@ void disable_IO_APIC(void) /* * Use virtual wire A mode when interrupt remapping is enabled. */ - if (cpu_has_apic) + if (cpu_has_apic || apic_from_smp_config()) disconnect_bsp_APIC(!intr_remapping_enabled && ioapic_i8259.pin != -1); } -- cgit v0.10.2 From 878f4f533e5b4498215e67e0f886b0fc81417f5e Mon Sep 17 00:00:00 2001 From: Felipe Contreras Date: Thu, 17 Sep 2009 00:38:38 +0300 Subject: x86: Trivial whitespace cleanups Signed-off-by: Felipe Contreras Cc: Vegard Nossum Cc: Pekka Enberg Cc: Andrew Morton Cc: Alok N Kataria Cc: "Tan Wei Chong" Cc: Len Brown Cc: Lin Ming Cc: Bob Moore LKML-Reference: <1253137123-18047-2-git-send-email-felipe.contreras@gmail.com> Signed-off-by: Ingo Molnar diff --git a/arch/x86/include/asm/string_32.h b/arch/x86/include/asm/string_32.h index c86f452..ae907e6 100644 --- a/arch/x86/include/asm/string_32.h +++ b/arch/x86/include/asm/string_32.h @@ -65,7 +65,6 @@ static __always_inline void *__constant_memcpy(void *to, const void *from, case 4: *(int *)to = *(int *)from; return to; - case 3: *(short *)to = *(short *)from; *((char *)to + 2) = *((char *)from + 2); diff --git a/arch/x86/kernel/tsc.c b/arch/x86/kernel/tsc.c index 71f4368..8a2fc11 100644 --- a/arch/x86/kernel/tsc.c +++ b/arch/x86/kernel/tsc.c @@ -670,7 +670,7 @@ static int time_cpufreq_notifier(struct notifier_block *nb, unsigned long val, if ((val == CPUFREQ_PRECHANGE && freq->old < freq->new) || (val == CPUFREQ_POSTCHANGE && freq->old > freq->new) || (val == CPUFREQ_RESUMECHANGE)) { - *lpj = cpufreq_scale(loops_per_jiffy_ref, ref_freq, freq->new); + *lpj = cpufreq_scale(loops_per_jiffy_ref, ref_freq, freq->new); tsc_khz = cpufreq_scale(tsc_khz_ref, ref_freq, freq->new); if (!(freq->flags & CPUFREQ_CONST_LOOPS)) diff --git a/drivers/acpi/acpica/tbfadt.c b/drivers/acpi/acpica/tbfadt.c index 82b02dc..c016335 100644 --- a/drivers/acpi/acpica/tbfadt.c +++ b/drivers/acpi/acpica/tbfadt.c @@ -275,7 +275,6 @@ void acpi_tb_parse_fadt(u32 table_index) void acpi_tb_create_local_fadt(struct acpi_table_header *table, u32 length) { - /* * Check if the FADT is larger than the largest table that we expect * (the ACPI 2.0/3.0 version). If so, truncate the table, and issue -- cgit v0.10.2 From 4fe487828b912ca004b4f4505275ab164ed6ce9f Mon Sep 17 00:00:00 2001 From: Sergey Senozhatsky Date: Thu, 17 Sep 2009 15:54:01 +0300 Subject: x86: Fix uaccess_32.h typo Trivial: correct "that the we don't" typo. Signed-off-by: Sergey Senozhatsky LKML-Reference: <20090917125401.GU3717@localdomain.by> Signed-off-by: Ingo Molnar diff --git a/arch/x86/include/asm/uaccess_32.h b/arch/x86/include/asm/uaccess_32.h index 5e06259..632fb44 100644 --- a/arch/x86/include/asm/uaccess_32.h +++ b/arch/x86/include/asm/uaccess_32.h @@ -33,7 +33,7 @@ unsigned long __must_check __copy_from_user_ll_nocache_nozero * Copy data from kernel space to user space. Caller must check * the specified block with access_ok() before calling this function. * The caller should also make sure he pins the user space address - * so that the we don't result in page fault and sleep. + * so that we don't result in page fault and sleep. * * Here we special-case 1, 2 and 4-byte copy_*_user invocations. On a fault * we return the initial request size (1, 2 or 4), as copy_*_user should do. -- cgit v0.10.2 From 414128bd33fef3242747154dfa444970bc5caf4c Mon Sep 17 00:00:00 2001 From: Jan Beulich Date: Fri, 4 Sep 2009 09:13:49 +0100 Subject: x86: Increase timeout for EHCI debug port reset completion in early printk On one of my systems, several thousand iterations are needed before CMD_RESET can be observed clear after setting it. Using a much higher value here obviously cannot hurt. Signed-off-by: Jan Beulich Cc: Yinghai Lu LKML-Reference: <4AA0E85D02000078000136F9@vpn.id2.novell.com> Signed-off-by: Ingo Molnar diff --git a/arch/x86/kernel/early_printk.c b/arch/x86/kernel/early_printk.c index 335f049..b11cab3 100644 --- a/arch/x86/kernel/early_printk.c +++ b/arch/x86/kernel/early_printk.c @@ -624,7 +624,7 @@ try_next_port: return -1; } - loop = 10; + loop = 100000; /* Reset the EHCI controller */ cmd = readl(&ehci_regs->command); cmd |= CMD_RESET; -- cgit v0.10.2 From 5f68563996e812f9ca35b3939ad2a42e5d254d66 Mon Sep 17 00:00:00 2001 From: Jan Beulich Date: Fri, 4 Sep 2009 09:16:22 +0100 Subject: x86: cpuinit-annotate SMP boot trampolines properly Add missing annotations, and make use of include/linux/init.h's macros. Signed-off-by: Jan Beulich LKML-Reference: <4AA0E8F60200007800013703@vpn.id2.novell.com> Signed-off-by: Ingo Molnar diff --git a/arch/x86/kernel/trampoline.c b/arch/x86/kernel/trampoline.c index 808031a..699f7ee 100644 --- a/arch/x86/kernel/trampoline.c +++ b/arch/x86/kernel/trampoline.c @@ -4,7 +4,7 @@ #include /* ready for x86_64 and x86 */ -unsigned char *trampoline_base = __va(TRAMPOLINE_BASE); +unsigned char *__cpuinitdata trampoline_base = __va(TRAMPOLINE_BASE); void __init reserve_trampoline_memory(void) { @@ -26,7 +26,7 @@ void __init reserve_trampoline_memory(void) * bootstrap into the page concerned. The caller * has made sure it's suitably aligned. */ -unsigned long setup_trampoline(void) +unsigned long __cpuinit setup_trampoline(void) { memcpy(trampoline_base, trampoline_data, TRAMPOLINE_SIZE); return virt_to_phys(trampoline_base); diff --git a/arch/x86/kernel/trampoline_32.S b/arch/x86/kernel/trampoline_32.S index 66d874e..8508237 100644 --- a/arch/x86/kernel/trampoline_32.S +++ b/arch/x86/kernel/trampoline_32.S @@ -28,16 +28,12 @@ */ #include +#include #include #include /* We can free up trampoline after bootup if cpu hotplug is not supported. */ -#ifndef CONFIG_HOTPLUG_CPU -.section ".cpuinit.data","aw",@progbits -#else -.section .rodata,"a",@progbits -#endif - +__CPUINITRODATA .code16 ENTRY(trampoline_data) diff --git a/arch/x86/kernel/trampoline_64.S b/arch/x86/kernel/trampoline_64.S index cddfb8d..596d54c 100644 --- a/arch/x86/kernel/trampoline_64.S +++ b/arch/x86/kernel/trampoline_64.S @@ -25,14 +25,15 @@ */ #include +#include #include #include #include #include #include -.section .rodata, "a", @progbits - +/* We can free up the trampoline after bootup if cpu hotplug is not supported. */ +__CPUINITRODATA .code16 ENTRY(trampoline_data) -- cgit v0.10.2 From 8d0cc631f6dd0a9283ceb7d61d8b85ecbcd355ea Mon Sep 17 00:00:00 2001 From: Jan Beulich Date: Fri, 4 Sep 2009 09:18:07 +0100 Subject: x86: Correct segment permission flags in 64-bit linker script While these don't get actively used (afaict), it still doesn't hurt for them to properly reflect what how respective segments will get mapped/ accessed. Signed-off-by: Jan Beulich LKML-Reference: <4AA0E95F0200007800013707@vpn.id2.novell.com> Signed-off-by: Ingo Molnar diff --git a/arch/x86/kernel/vmlinux.lds.S b/arch/x86/kernel/vmlinux.lds.S index 0ccb57d..a46accc 100644 --- a/arch/x86/kernel/vmlinux.lds.S +++ b/arch/x86/kernel/vmlinux.lds.S @@ -45,9 +45,9 @@ PHDRS { text PT_LOAD FLAGS(5); /* R_E */ data PT_LOAD FLAGS(7); /* RWE */ #ifdef CONFIG_X86_64 - user PT_LOAD FLAGS(7); /* RWE */ + user PT_LOAD FLAGS(5); /* R_E */ #ifdef CONFIG_SMP - percpu PT_LOAD FLAGS(7); /* RWE */ + percpu PT_LOAD FLAGS(6); /* RW_ */ #endif init PT_LOAD FLAGS(7); /* RWE */ #endif -- cgit v0.10.2 From 6399c087458859cddff2d6b46befb95b866df3e0 Mon Sep 17 00:00:00 2001 From: Alok Kataria Date: Fri, 4 Sep 2009 13:13:39 -0700 Subject: x86: Print the hypervisor returned tsc_khz during boot On an AMD-64 system the processor frequency that is printed during system boot, may be different than the tsc frequency that was returned by the hypervisor, due to the value returned from calibrate_cpu. For debugging timekeeping or other related issues it might be better to get the tsc_khz value returned by the hypervisor. The patch below now prints the tsc frequency that the VMware hypervisor returned. Signed-off-by: Alok N Kataria LKML-Reference: <1252095219.12518.13.camel@ank32.eng.vmware.com> Signed-off-by: Ingo Molnar diff --git a/arch/x86/kernel/cpu/vmware.c b/arch/x86/kernel/cpu/vmware.c index 0a46b4d..1cbed97 100644 --- a/arch/x86/kernel/cpu/vmware.c +++ b/arch/x86/kernel/cpu/vmware.c @@ -58,6 +58,9 @@ static unsigned long vmware_get_tsc_khz(void) tsc_hz = eax | (((uint64_t)ebx) << 32); do_div(tsc_hz, 1000); BUG_ON(tsc_hz >> 32); + printk(KERN_INFO "TSC freq read from hypervisor : %lu.%03lu MHz\n", + (unsigned long) tsc_hz / 1000, + (unsigned long) tsc_hz % 1000); return tsc_hz; } @@ -69,6 +72,9 @@ void __init vmware_platform_setup(void) if (ebx != UINT_MAX) x86_platform.calibrate_tsc = vmware_get_tsc_khz; + else + printk(KERN_WARNING + "Failed to get TSC freq from the hypervisor\n"); } /* -- cgit v0.10.2