From 33a93aa490ae256d0b982e2d66cf570cf61f95de Mon Sep 17 00:00:00 2001 From: Anup Patel Date: Fri, 2 Oct 2015 23:24:18 +0530 Subject: arm64: dts: Add L2-cache DT node for NS2 Recent kernels requires cache hierrachy to be defined via DT hence this patch updates NS2 DT accordingly. Signed-off-by: Anup Patel Reviewed-by: Sandeep Tripathy Reviewed-by: Ray Jui Reviewed-by: Scott Branden Signed-off-by: Florian Fainelli diff --git a/arch/arm64/boot/dts/broadcom/ns2.dtsi b/arch/arm64/boot/dts/broadcom/ns2.dtsi index 3c92d92..f759175 100644 --- a/arch/arm64/boot/dts/broadcom/ns2.dtsi +++ b/arch/arm64/boot/dts/broadcom/ns2.dtsi @@ -50,6 +50,7 @@ reg = <0 0>; enable-method = "spin-table"; cpu-release-addr = <0 0x84b00000>; + next-level-cache = <&CLUSTER0_L2>; }; cpu@1 { @@ -58,6 +59,7 @@ reg = <0 1>; enable-method = "spin-table"; cpu-release-addr = <0 0x84b00000>; + next-level-cache = <&CLUSTER0_L2>; }; cpu@2 { @@ -66,6 +68,7 @@ reg = <0 2>; enable-method = "spin-table"; cpu-release-addr = <0 0x84b00000>; + next-level-cache = <&CLUSTER0_L2>; }; cpu@3 { @@ -74,6 +77,11 @@ reg = <0 3>; enable-method = "spin-table"; cpu-release-addr = <0 0x84b00000>; + next-level-cache = <&CLUSTER0_L2>; + }; + + CLUSTER0_L2: l2-cache@000 { + compatible = "cache"; }; }; -- cgit v0.10.2 From 6ec5f3c5264795290f3d7ed67286cca2c1486bfe Mon Sep 17 00:00:00 2001 From: Anup Patel Date: Fri, 2 Oct 2015 23:24:19 +0530 Subject: arm64: dts: Add SMMU DT node for NS2 The SMMU-500 driver is already available in Linux kernel. Let's enable it for NS2 in DT. This patch keeps mmu-masters attribute empty so that driver patches can later extend this attribute when adding device DT nodes. Signed-off-by: Anup Patel Reviewed-by: Ray Jui Reviewed-by: Scott Branden Signed-off-by: Florian Fainelli diff --git a/arch/arm64/boot/dts/broadcom/ns2.dtsi b/arch/arm64/boot/dts/broadcom/ns2.dtsi index f759175..c5d90e4 100644 --- a/arch/arm64/boot/dts/broadcom/ns2.dtsi +++ b/arch/arm64/boot/dts/broadcom/ns2.dtsi @@ -103,6 +103,47 @@ #size-cells = <1>; ranges = <0 0 0 0xffffffff>; + smmu: mmu@64000000 { + compatible = "arm,mmu-500"; + reg = <0x64000000 0x40000>; + #global-interrupts = <2>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + mmu-masters; + }; + gic: interrupt-controller@65210000 { compatible = "arm,gic-400"; #interrupt-cells = <3>; -- cgit v0.10.2 From 5b467c3b2d36b6ed8a6d17923c12f3091d83ce77 Mon Sep 17 00:00:00 2001 From: Anup Patel Date: Fri, 2 Oct 2015 23:24:20 +0530 Subject: arm64: dts: Add syscon based reboot in DT for NS2 To reset NS2, we simply have to write '0' to BIT[1] at offset 0x90 of CRMU space. The above can be easily achieved by writing 0xfffffffd at offset 0x90 using syscon-reboot driver. We don't need to have separate driver for rebooting NS2. This patch enables syscon-reboot driver for NS2 using DT. Signed-off-by: Anup Patel Reviewed-by: Ray Jui Reviewed-by: Scott Branden Signed-off-by: Florian Fainelli diff --git a/arch/arm64/boot/dts/broadcom/ns2.dtsi b/arch/arm64/boot/dts/broadcom/ns2.dtsi index c5d90e4..5d2ac6b 100644 --- a/arch/arm64/boot/dts/broadcom/ns2.dtsi +++ b/arch/arm64/boot/dts/broadcom/ns2.dtsi @@ -144,6 +144,18 @@ mmu-masters; }; + crmu: crmu@65024000 { + compatible = "syscon"; + reg = <0x65024000 0x100>; + }; + + reboot@65024000 { + compatible ="syscon-reboot"; + regmap = <&crmu>; + offset = <0x90>; + mask = <0xfffffffd>; + }; + gic: interrupt-controller@65210000 { compatible = "arm,gic-400"; #interrupt-cells = <3>; -- cgit v0.10.2 From 5b31d8759bcc36ad994e38970b7cca5195d8bc19 Mon Sep 17 00:00:00 2001 From: Anup Patel Date: Fri, 2 Oct 2015 23:24:21 +0530 Subject: arm64: dts: Add ARM PMUv3 DT node in NS2 DT The NS2 SoC has Cortex-A57 CPUs which support ARM PMUv3 so, lets enable ARM PMUv3 in NS2 DT. Signed-off-by: Anup Patel Reviewed-by: Vikram Prakash Reviewed-by: Ray Jui Reviewed-by: Scott Branden Signed-off-by: Florian Fainelli diff --git a/arch/arm64/boot/dts/broadcom/ns2.dtsi b/arch/arm64/boot/dts/broadcom/ns2.dtsi index 5d2ac6b..bc31c0e 100644 --- a/arch/arm64/boot/dts/broadcom/ns2.dtsi +++ b/arch/arm64/boot/dts/broadcom/ns2.dtsi @@ -44,7 +44,7 @@ #address-cells = <2>; #size-cells = <0>; - cpu@0 { + A57_0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a57", "arm,armv8"; reg = <0 0>; @@ -53,7 +53,7 @@ next-level-cache = <&CLUSTER0_L2>; }; - cpu@1 { + A57_1: cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a57", "arm,armv8"; reg = <0 1>; @@ -62,7 +62,7 @@ next-level-cache = <&CLUSTER0_L2>; }; - cpu@2 { + A57_2: cpu@2 { device_type = "cpu"; compatible = "arm,cortex-a57", "arm,armv8"; reg = <0 2>; @@ -71,7 +71,7 @@ next-level-cache = <&CLUSTER0_L2>; }; - cpu@3 { + A57_3: cpu@3 { device_type = "cpu"; compatible = "arm,cortex-a57", "arm,armv8"; reg = <0 3>; @@ -97,6 +97,18 @@ IRQ_TYPE_EDGE_RISING)>; }; + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = , + , + , + ; + interrupt-affinity = <&A57_0>, + <&A57_1>, + <&A57_2>, + <&A57_3>; + }; + soc: soc { compatible = "simple-bus"; #address-cells = <1>; -- cgit v0.10.2 From e8a6e265f595e93ac54bc8238d6afd350df4b793 Mon Sep 17 00:00:00 2001 From: Anup Patel Date: Fri, 2 Oct 2015 23:24:22 +0530 Subject: arm64: dts: Add IPROC RNG200 DT node for NS2 We have IPROC RNG200 hardware random number generation in NS2 SoC, lets enable it for NS2 in NS2 DT. Signed-off-by: Anup Patel Reviewed-by: Ray Jui Reviewed-by: Pramod KUMAR Reviewed-by: Vikram Prakash Reviewed-by: Scott Branden Signed-off-by: Florian Fainelli diff --git a/arch/arm64/boot/dts/broadcom/ns2.dtsi b/arch/arm64/boot/dts/broadcom/ns2.dtsi index bc31c0e..92ecf1c 100644 --- a/arch/arm64/boot/dts/broadcom/ns2.dtsi +++ b/arch/arm64/boot/dts/broadcom/ns2.dtsi @@ -187,5 +187,10 @@ clock-frequency = <23961600>; status = "disabled"; }; + + hwrng: hwrng@66220000 { + compatible = "brcm,iproc-rng200"; + reg = <0x66220000 0x28>; + }; }; }; -- cgit v0.10.2 From 7ac674e8df7aae461b92652026952d5b788c699b Mon Sep 17 00:00:00 2001 From: Ray Jui Date: Fri, 2 Oct 2015 23:24:23 +0530 Subject: arm64: dts: Add I2C nodes for NS2 This patch adds iProc I2C DT nodes for NS2 and enable them for the NS2 SVK board Signed-off-by: Ray Jui Reviewed-by: Vikram Prakash Reviewed-by: Scott Branden Signed-off-by: Florian Fainelli diff --git a/arch/arm64/boot/dts/broadcom/ns2-svk.dts b/arch/arm64/boot/dts/broadcom/ns2-svk.dts index 244baf8..e5950d5 100644 --- a/arch/arm64/boot/dts/broadcom/ns2-svk.dts +++ b/arch/arm64/boot/dts/broadcom/ns2-svk.dts @@ -52,6 +52,14 @@ }; soc: soc { + i2c0: i2c@66080000 { + status = "ok"; + }; + + i2c1: i2c@660b0000 { + status = "ok"; + }; + uart3: serial@66130000 { status = "ok"; }; diff --git a/arch/arm64/boot/dts/broadcom/ns2.dtsi b/arch/arm64/boot/dts/broadcom/ns2.dtsi index 92ecf1c..f603277 100644 --- a/arch/arm64/boot/dts/broadcom/ns2.dtsi +++ b/arch/arm64/boot/dts/broadcom/ns2.dtsi @@ -178,6 +178,26 @@ <0x65260000 0x1000>; }; + i2c0: i2c@66080000 { + compatible = "brcm,iproc-i2c"; + reg = <0x66080000 0x100>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-frequency = <100000>; + status = "disabled"; + }; + + i2c1: i2c@660b0000 { + compatible = "brcm,iproc-i2c"; + reg = <0x660b0000 0x100>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-frequency = <100000>; + status = "disabled"; + }; + uart3: serial@66130000 { compatible = "snps,dw-apb-uart"; reg = <0x66130000 0x100>; -- cgit v0.10.2 From c6fe9a2edf4debba5697a01b5c134b9d515fad84 Mon Sep 17 00:00:00 2001 From: Anup Patel Date: Fri, 30 Oct 2015 12:29:21 +0530 Subject: arm64: dts: Add BRCM IPROC NAND DT node for NS2 The NAND controller on NS2 SoC is compatible with existing BRCM IPROC NAND driver so let's enable it in NS2 DT and NS2 SVK DT. This patch also fixes use of node labels in ns2-svk.dts. Signed-off-by: Anup Patel Reviewed-by: Ray Jui Reviewed-by: Scott Branden Reviewed-by: Brian Norris Signed-off-by: Florian Fainelli diff --git a/arch/arm64/boot/dts/broadcom/ns2-svk.dts b/arch/arm64/boot/dts/broadcom/ns2-svk.dts index e5950d5..6bb3d4d 100644 --- a/arch/arm64/boot/dts/broadcom/ns2-svk.dts +++ b/arch/arm64/boot/dts/broadcom/ns2-svk.dts @@ -50,18 +50,28 @@ device_type = "memory"; reg = <0x000000000 0x80000000 0x00000000 0x40000000>; }; +}; - soc: soc { - i2c0: i2c@66080000 { - status = "ok"; - }; +&i2c0 { + status = "ok"; +}; - i2c1: i2c@660b0000 { - status = "ok"; - }; +&i2c1 { + status = "ok"; +}; + +&uart3 { + status = "ok"; +}; - uart3: serial@66130000 { - status = "ok"; - }; +&nand { + nandcs@0 { + compatible = "brcm,nandcs"; + reg = <0>; + nand-ecc-mode = "hw"; + nand-ecc-strength = <8>; + nand-ecc-step-size = <512>; + #address-cells = <1>; + #size-cells = <1>; }; }; diff --git a/arch/arm64/boot/dts/broadcom/ns2.dtsi b/arch/arm64/boot/dts/broadcom/ns2.dtsi index f603277..9610822 100644 --- a/arch/arm64/boot/dts/broadcom/ns2.dtsi +++ b/arch/arm64/boot/dts/broadcom/ns2.dtsi @@ -212,5 +212,19 @@ compatible = "brcm,iproc-rng200"; reg = <0x66220000 0x28>; }; + + nand: nand@66460000 { + compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1"; + reg = <0x66460000 0x600>, + <0x67015408 0x600>, + <0x66460f00 0x20>; + reg-names = "nand", "iproc-idm", "iproc-ext"; + interrupts = ; + + #address-cells = <1>; + #size-cells = <0>; + + brcm,nand-has-wp; + }; }; }; -- cgit v0.10.2 From d8bd64c1514ed5dca1c864b24a08d3314829eeb8 Mon Sep 17 00:00:00 2001 From: Jon Mason Date: Fri, 20 Nov 2015 10:17:20 -0500 Subject: ARM64: dts: enable clock support for Broadcom NS2 Add device tree entries for clock support for Broadcom Northstar 2 SoC Signed-off-by: Jon Mason Reviewed-by: Ray Jui Signed-off-by: Florian Fainelli diff --git a/arch/arm64/boot/dts/broadcom/ns2.dtsi b/arch/arm64/boot/dts/broadcom/ns2.dtsi index 9610822..a510d3a 100644 --- a/arch/arm64/boot/dts/broadcom/ns2.dtsi +++ b/arch/arm64/boot/dts/broadcom/ns2.dtsi @@ -31,6 +31,7 @@ */ #include +#include /memreserve/ 0x84b00000 0x00000008; @@ -109,6 +110,33 @@ <&A57_3>; }; + clocks { + #address-cells = <1>; + #size-cells = <1>; + + osc: oscillator { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <25000000>; + }; + + iprocmed: iprocmed { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&genpll_scr BCM_NS2_GENPLL_SCR_SCR_CLK>; + clock-div = <2>; + clock-mult = <1>; + }; + + iprocslow: iprocslow { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&genpll_scr BCM_NS2_GENPLL_SCR_SCR_CLK>; + clock-div = <4>; + clock-mult = <1>; + }; + }; + soc: soc { compatible = "simple-bus"; #address-cells = <1>; @@ -156,6 +184,56 @@ mmu-masters; }; + lcpll_ddr: lcpll_ddr@6501d058 { + #clock-cells = <1>; + compatible = "brcm,ns2-lcpll-ddr"; + reg = <0x6501d058 0x20>, + <0x6501c020 0x4>, + <0x6501d04c 0x4>; + clocks = <&osc>; + clock-output-names = "lcpll_ddr", "pcie_sata_usb", + "ddr", "ddr_ch2_unused", + "ddr_ch3_unused", "ddr_ch4_unused", + "ddr_ch5_unused"; + }; + + lcpll_ports: lcpll_ports@6501d078 { + #clock-cells = <1>; + compatible = "brcm,ns2-lcpll-ports"; + reg = <0x6501d078 0x20>, + <0x6501c020 0x4>, + <0x6501d054 0x4>; + clocks = <&osc>; + clock-output-names = "lcpll_ports", "wan", "rgmii", + "ports_ch2_unused", + "ports_ch3_unused", + "ports_ch4_unused", + "ports_ch5_unused"; + }; + + genpll_scr: genpll_scr@6501d098 { + #clock-cells = <1>; + compatible = "brcm,ns2-genpll-scr"; + reg = <0x6501d098 0x32>, + <0x6501c020 0x4>, + <0x6501d044 0x4>; + clocks = <&osc>; + clock-output-names = "genpll_scr", "scr", "fs", + "audio_ref", "scr_ch3_unused", + "scr_ch4_unused", "scr_ch5_unused"; + }; + + genpll_sw: genpll_sw@6501d0c4 { + #clock-cells = <1>; + compatible = "brcm,ns2-genpll-sw"; + reg = <0x6501d0c4 0x32>, + <0x6501c020 0x4>, + <0x6501d044 0x4>; + clocks = <&osc>; + clock-output-names = "genpll_sw", "rpe", "250", "nic", + "chimp", "port", "sdio"; + }; + crmu: crmu@65024000 { compatible = "syscon"; reg = <0x65024000 0x100>; @@ -204,7 +282,7 @@ interrupts = ; reg-shift = <2>; reg-io-width = <4>; - clock-frequency = <23961600>; + clocks = <&osc>; status = "disabled"; }; -- cgit v0.10.2