From bea5af41dd9b5f127c730c00610756972a616ed4 Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Fri, 15 May 2015 15:41:00 +0800 Subject: ARM: imx: move timer driver into drivers/clocksource After the cleanup on imx timer driver, now it's ready to be moved into drivers/clocksource/. Let's do it. Signed-off-by: Shawn Guo Acked-by: Daniel Lezcano diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index 1d87078..f5813f9 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -2,7 +2,7 @@ menuconfig ARCH_MXC bool "Freescale i.MX family" if ARCH_MULTI_V4_V5 || ARCH_MULTI_V6_V7 select ARCH_REQUIRE_GPIOLIB select ARM_CPU_SUSPEND if PM - select CLKSRC_MMIO + select CLKSRC_IMX_GPT select GENERIC_IRQ_CHIP select PINCTRL select PM_OPP if PM diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index 799e65a..f70e184 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -1,4 +1,4 @@ -obj-y := time.o cpu.o system.o irq-common.o +obj-y := cpu.o system.o irq-common.o obj-$(CONFIG_SOC_IMX1) += mm-imx1.o obj-$(CONFIG_SOC_IMX21) += mm-imx21.o diff --git a/arch/arm/mach-imx/time.c b/arch/arm/mach-imx/time.c deleted file mode 100644 index b460928..0000000 --- a/arch/arm/mach-imx/time.c +++ /dev/null @@ -1,542 +0,0 @@ -/* - * linux/arch/arm/plat-mxc/time.c - * - * Copyright (C) 2000-2001 Deep Blue Solutions - * Copyright (C) 2002 Shane Nay (shane@minirl.com) - * Copyright (C) 2006-2007 Pavel Pisa (ppisa@pikron.com) - * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301, USA. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -/* - * There are 4 versions of the timer hardware on Freescale MXC hardware. - * - MX1/MXL - * - MX21, MX27. - * - MX25, MX31, MX35, MX37, MX51, MX6Q(rev1.0) - * - MX6DL, MX6SX, MX6Q(rev1.1+) - */ - -/* defines common for all i.MX */ -#define MXC_TCTL 0x00 -#define MXC_TCTL_TEN (1 << 0) /* Enable module */ -#define MXC_TPRER 0x04 - -/* MX1, MX21, MX27 */ -#define MX1_2_TCTL_CLK_PCLK1 (1 << 1) -#define MX1_2_TCTL_IRQEN (1 << 4) -#define MX1_2_TCTL_FRR (1 << 8) -#define MX1_2_TCMP 0x08 -#define MX1_2_TCN 0x10 -#define MX1_2_TSTAT 0x14 - -/* MX21, MX27 */ -#define MX2_TSTAT_CAPT (1 << 1) -#define MX2_TSTAT_COMP (1 << 0) - -/* MX31, MX35, MX25, MX5, MX6 */ -#define V2_TCTL_WAITEN (1 << 3) /* Wait enable mode */ -#define V2_TCTL_CLK_IPG (1 << 6) -#define V2_TCTL_CLK_PER (2 << 6) -#define V2_TCTL_CLK_OSC_DIV8 (5 << 6) -#define V2_TCTL_FRR (1 << 9) -#define V2_TCTL_24MEN (1 << 10) -#define V2_TPRER_PRE24M 12 -#define V2_IR 0x0c -#define V2_TSTAT 0x08 -#define V2_TSTAT_OF1 (1 << 0) -#define V2_TCN 0x24 -#define V2_TCMP 0x10 - -#define V2_TIMER_RATE_OSC_DIV8 3000000 - -struct imx_timer { - enum imx_gpt_type type; - void __iomem *base; - int irq; - struct clk *clk_per; - struct clk *clk_ipg; - const struct imx_gpt_data *gpt; - struct clock_event_device ced; - enum clock_event_mode cem; - struct irqaction act; -}; - -struct imx_gpt_data { - int reg_tstat; - int reg_tcn; - int reg_tcmp; - void (*gpt_setup_tctl)(struct imx_timer *imxtm); - void (*gpt_irq_enable)(struct imx_timer *imxtm); - void (*gpt_irq_disable)(struct imx_timer *imxtm); - void (*gpt_irq_acknowledge)(struct imx_timer *imxtm); - int (*set_next_event)(unsigned long evt, - struct clock_event_device *ced); -}; - -static inline struct imx_timer *to_imx_timer(struct clock_event_device *ced) -{ - return container_of(ced, struct imx_timer, ced); -} - -static void imx1_gpt_irq_disable(struct imx_timer *imxtm) -{ - unsigned int tmp; - - tmp = readl_relaxed(imxtm->base + MXC_TCTL); - writel_relaxed(tmp & ~MX1_2_TCTL_IRQEN, imxtm->base + MXC_TCTL); -} -#define imx21_gpt_irq_disable imx1_gpt_irq_disable - -static void imx31_gpt_irq_disable(struct imx_timer *imxtm) -{ - writel_relaxed(0, imxtm->base + V2_IR); -} -#define imx6dl_gpt_irq_disable imx31_gpt_irq_disable - -static void imx1_gpt_irq_enable(struct imx_timer *imxtm) -{ - unsigned int tmp; - - tmp = readl_relaxed(imxtm->base + MXC_TCTL); - writel_relaxed(tmp | MX1_2_TCTL_IRQEN, imxtm->base + MXC_TCTL); -} -#define imx21_gpt_irq_enable imx1_gpt_irq_enable - -static void imx31_gpt_irq_enable(struct imx_timer *imxtm) -{ - writel_relaxed(1<<0, imxtm->base + V2_IR); -} -#define imx6dl_gpt_irq_enable imx31_gpt_irq_enable - -static void imx1_gpt_irq_acknowledge(struct imx_timer *imxtm) -{ - writel_relaxed(0, imxtm->base + MX1_2_TSTAT); -} - -static void imx21_gpt_irq_acknowledge(struct imx_timer *imxtm) -{ - writel_relaxed(MX2_TSTAT_CAPT | MX2_TSTAT_COMP, - imxtm->base + MX1_2_TSTAT); -} - -static void imx31_gpt_irq_acknowledge(struct imx_timer *imxtm) -{ - writel_relaxed(V2_TSTAT_OF1, imxtm->base + V2_TSTAT); -} -#define imx6dl_gpt_irq_acknowledge imx31_gpt_irq_acknowledge - -static void __iomem *sched_clock_reg; - -static u64 notrace mxc_read_sched_clock(void) -{ - return sched_clock_reg ? readl_relaxed(sched_clock_reg) : 0; -} - -static struct delay_timer imx_delay_timer; - -static unsigned long imx_read_current_timer(void) -{ - return readl_relaxed(sched_clock_reg); -} - -static int __init mxc_clocksource_init(struct imx_timer *imxtm) -{ - unsigned int c = clk_get_rate(imxtm->clk_per); - void __iomem *reg = imxtm->base + imxtm->gpt->reg_tcn; - - imx_delay_timer.read_current_timer = &imx_read_current_timer; - imx_delay_timer.freq = c; - register_current_timer_delay(&imx_delay_timer); - - sched_clock_reg = reg; - - sched_clock_register(mxc_read_sched_clock, 32, c); - return clocksource_mmio_init(reg, "mxc_timer1", c, 200, 32, - clocksource_mmio_readl_up); -} - -/* clock event */ - -static int mx1_2_set_next_event(unsigned long evt, - struct clock_event_device *ced) -{ - struct imx_timer *imxtm = to_imx_timer(ced); - unsigned long tcmp; - - tcmp = readl_relaxed(imxtm->base + MX1_2_TCN) + evt; - - writel_relaxed(tcmp, imxtm->base + MX1_2_TCMP); - - return (int)(tcmp - readl_relaxed(imxtm->base + MX1_2_TCN)) < 0 ? - -ETIME : 0; -} - -static int v2_set_next_event(unsigned long evt, - struct clock_event_device *ced) -{ - struct imx_timer *imxtm = to_imx_timer(ced); - unsigned long tcmp; - - tcmp = readl_relaxed(imxtm->base + V2_TCN) + evt; - - writel_relaxed(tcmp, imxtm->base + V2_TCMP); - - return evt < 0x7fffffff && - (int)(tcmp - readl_relaxed(imxtm->base + V2_TCN)) < 0 ? - -ETIME : 0; -} - -#ifdef DEBUG -static const char *clock_event_mode_label[] = { - [CLOCK_EVT_MODE_PERIODIC] = "CLOCK_EVT_MODE_PERIODIC", - [CLOCK_EVT_MODE_ONESHOT] = "CLOCK_EVT_MODE_ONESHOT", - [CLOCK_EVT_MODE_SHUTDOWN] = "CLOCK_EVT_MODE_SHUTDOWN", - [CLOCK_EVT_MODE_UNUSED] = "CLOCK_EVT_MODE_UNUSED", - [CLOCK_EVT_MODE_RESUME] = "CLOCK_EVT_MODE_RESUME", -}; -#endif /* DEBUG */ - -static void mxc_set_mode(enum clock_event_mode mode, - struct clock_event_device *ced) -{ - struct imx_timer *imxtm = to_imx_timer(ced); - unsigned long flags; - - /* - * The timer interrupt generation is disabled at least - * for enough time to call mxc_set_next_event() - */ - local_irq_save(flags); - - /* Disable interrupt in GPT module */ - imxtm->gpt->gpt_irq_disable(imxtm); - - if (mode != imxtm->cem) { - u32 tcn = readl_relaxed(imxtm->base + imxtm->gpt->reg_tcn); - /* Set event time into far-far future */ - writel_relaxed(tcn - 3, imxtm->base + imxtm->gpt->reg_tcmp); - - /* Clear pending interrupt */ - imxtm->gpt->gpt_irq_acknowledge(imxtm); - } - -#ifdef DEBUG - printk(KERN_INFO "mxc_set_mode: changing mode from %s to %s\n", - clock_event_mode_label[imxtm->cem], - clock_event_mode_label[mode]); -#endif /* DEBUG */ - - /* Remember timer mode */ - imxtm->cem = mode; - local_irq_restore(flags); - - switch (mode) { - case CLOCK_EVT_MODE_PERIODIC: - printk(KERN_ERR"mxc_set_mode: Periodic mode is not " - "supported for i.MX\n"); - break; - case CLOCK_EVT_MODE_ONESHOT: - /* - * Do not put overhead of interrupt enable/disable into - * mxc_set_next_event(), the core has about 4 minutes - * to call mxc_set_next_event() or shutdown clock after - * mode switching - */ - local_irq_save(flags); - imxtm->gpt->gpt_irq_enable(imxtm); - local_irq_restore(flags); - break; - case CLOCK_EVT_MODE_SHUTDOWN: - case CLOCK_EVT_MODE_UNUSED: - case CLOCK_EVT_MODE_RESUME: - /* Left event sources disabled, no more interrupts appear */ - break; - } -} - -/* - * IRQ handler for the timer - */ -static irqreturn_t mxc_timer_interrupt(int irq, void *dev_id) -{ - struct clock_event_device *ced = dev_id; - struct imx_timer *imxtm = to_imx_timer(ced); - uint32_t tstat; - - tstat = readl_relaxed(imxtm->base + imxtm->gpt->reg_tstat); - - imxtm->gpt->gpt_irq_acknowledge(imxtm); - - ced->event_handler(ced); - - return IRQ_HANDLED; -} - -static int __init mxc_clockevent_init(struct imx_timer *imxtm) -{ - struct clock_event_device *ced = &imxtm->ced; - struct irqaction *act = &imxtm->act; - - imxtm->cem = CLOCK_EVT_MODE_UNUSED; - - ced->name = "mxc_timer1"; - ced->features = CLOCK_EVT_FEAT_ONESHOT; - ced->set_mode = mxc_set_mode; - ced->set_next_event = imxtm->gpt->set_next_event; - ced->rating = 200; - ced->cpumask = cpumask_of(0); - clockevents_config_and_register(ced, clk_get_rate(imxtm->clk_per), - 0xff, 0xfffffffe); - - act->name = "i.MX Timer Tick"; - act->flags = IRQF_TIMER | IRQF_IRQPOLL; - act->handler = mxc_timer_interrupt; - act->dev_id = ced; - - return setup_irq(imxtm->irq, act); -} - -static void imx1_gpt_setup_tctl(struct imx_timer *imxtm) -{ - u32 tctl_val; - - tctl_val = MX1_2_TCTL_FRR | MX1_2_TCTL_CLK_PCLK1 | MXC_TCTL_TEN; - writel_relaxed(tctl_val, imxtm->base + MXC_TCTL); -} -#define imx21_gpt_setup_tctl imx1_gpt_setup_tctl - -static void imx31_gpt_setup_tctl(struct imx_timer *imxtm) -{ - u32 tctl_val; - - tctl_val = V2_TCTL_FRR | V2_TCTL_WAITEN | MXC_TCTL_TEN; - if (clk_get_rate(imxtm->clk_per) == V2_TIMER_RATE_OSC_DIV8) - tctl_val |= V2_TCTL_CLK_OSC_DIV8; - else - tctl_val |= V2_TCTL_CLK_PER; - - writel_relaxed(tctl_val, imxtm->base + MXC_TCTL); -} - -static void imx6dl_gpt_setup_tctl(struct imx_timer *imxtm) -{ - u32 tctl_val; - - tctl_val = V2_TCTL_FRR | V2_TCTL_WAITEN | MXC_TCTL_TEN; - if (clk_get_rate(imxtm->clk_per) == V2_TIMER_RATE_OSC_DIV8) { - tctl_val |= V2_TCTL_CLK_OSC_DIV8; - /* 24 / 8 = 3 MHz */ - writel_relaxed(7 << V2_TPRER_PRE24M, imxtm->base + MXC_TPRER); - tctl_val |= V2_TCTL_24MEN; - } else { - tctl_val |= V2_TCTL_CLK_PER; - } - - writel_relaxed(tctl_val, imxtm->base + MXC_TCTL); -} - -static const struct imx_gpt_data imx1_gpt_data = { - .reg_tstat = MX1_2_TSTAT, - .reg_tcn = MX1_2_TCN, - .reg_tcmp = MX1_2_TCMP, - .gpt_irq_enable = imx1_gpt_irq_enable, - .gpt_irq_disable = imx1_gpt_irq_disable, - .gpt_irq_acknowledge = imx1_gpt_irq_acknowledge, - .gpt_setup_tctl = imx1_gpt_setup_tctl, - .set_next_event = mx1_2_set_next_event, -}; - -static const struct imx_gpt_data imx21_gpt_data = { - .reg_tstat = MX1_2_TSTAT, - .reg_tcn = MX1_2_TCN, - .reg_tcmp = MX1_2_TCMP, - .gpt_irq_enable = imx21_gpt_irq_enable, - .gpt_irq_disable = imx21_gpt_irq_disable, - .gpt_irq_acknowledge = imx21_gpt_irq_acknowledge, - .gpt_setup_tctl = imx21_gpt_setup_tctl, - .set_next_event = mx1_2_set_next_event, -}; - -static const struct imx_gpt_data imx31_gpt_data = { - .reg_tstat = V2_TSTAT, - .reg_tcn = V2_TCN, - .reg_tcmp = V2_TCMP, - .gpt_irq_enable = imx31_gpt_irq_enable, - .gpt_irq_disable = imx31_gpt_irq_disable, - .gpt_irq_acknowledge = imx31_gpt_irq_acknowledge, - .gpt_setup_tctl = imx31_gpt_setup_tctl, - .set_next_event = v2_set_next_event, -}; - -static const struct imx_gpt_data imx6dl_gpt_data = { - .reg_tstat = V2_TSTAT, - .reg_tcn = V2_TCN, - .reg_tcmp = V2_TCMP, - .gpt_irq_enable = imx6dl_gpt_irq_enable, - .gpt_irq_disable = imx6dl_gpt_irq_disable, - .gpt_irq_acknowledge = imx6dl_gpt_irq_acknowledge, - .gpt_setup_tctl = imx6dl_gpt_setup_tctl, - .set_next_event = v2_set_next_event, -}; - -static void __init _mxc_timer_init(struct imx_timer *imxtm) -{ - switch (imxtm->type) { - case GPT_TYPE_IMX1: - imxtm->gpt = &imx1_gpt_data; - break; - case GPT_TYPE_IMX21: - imxtm->gpt = &imx21_gpt_data; - break; - case GPT_TYPE_IMX31: - imxtm->gpt = &imx31_gpt_data; - break; - case GPT_TYPE_IMX6DL: - imxtm->gpt = &imx6dl_gpt_data; - break; - default: - BUG(); - } - - if (IS_ERR(imxtm->clk_per)) { - pr_err("i.MX timer: unable to get clk\n"); - return; - } - - if (!IS_ERR(imxtm->clk_ipg)) - clk_prepare_enable(imxtm->clk_ipg); - - clk_prepare_enable(imxtm->clk_per); - - /* - * Initialise to a known state (all timers off, and timing reset) - */ - - writel_relaxed(0, imxtm->base + MXC_TCTL); - writel_relaxed(0, imxtm->base + MXC_TPRER); /* see datasheet note */ - - imxtm->gpt->gpt_setup_tctl(imxtm); - - /* init and register the timer to the framework */ - mxc_clocksource_init(imxtm); - mxc_clockevent_init(imxtm); -} - -void __init mxc_timer_init(unsigned long pbase, int irq, enum imx_gpt_type type) -{ - struct imx_timer *imxtm; - - imxtm = kzalloc(sizeof(*imxtm), GFP_KERNEL); - BUG_ON(!imxtm); - - imxtm->clk_per = clk_get_sys("imx-gpt.0", "per"); - imxtm->clk_ipg = clk_get_sys("imx-gpt.0", "ipg"); - - imxtm->base = ioremap(pbase, SZ_4K); - BUG_ON(!imxtm->base); - - imxtm->type = type; - - _mxc_timer_init(imxtm); -} - -static void __init mxc_timer_init_dt(struct device_node *np, enum imx_gpt_type type) -{ - struct imx_timer *imxtm; - static int initialized; - - /* Support one instance only */ - if (initialized) - return; - - imxtm = kzalloc(sizeof(*imxtm), GFP_KERNEL); - BUG_ON(!imxtm); - - imxtm->base = of_iomap(np, 0); - WARN_ON(!imxtm->base); - imxtm->irq = irq_of_parse_and_map(np, 0); - - imxtm->clk_ipg = of_clk_get_by_name(np, "ipg"); - - /* Try osc_per first, and fall back to per otherwise */ - imxtm->clk_per = of_clk_get_by_name(np, "osc_per"); - if (IS_ERR(imxtm->clk_per)) - imxtm->clk_per = of_clk_get_by_name(np, "per"); - - imxtm->type = type; - - _mxc_timer_init(imxtm); - - initialized = 1; -} - -static void __init imx1_timer_init_dt(struct device_node *np) -{ - mxc_timer_init_dt(np, GPT_TYPE_IMX1); -} - -static void __init imx21_timer_init_dt(struct device_node *np) -{ - mxc_timer_init_dt(np, GPT_TYPE_IMX21); -} - -static void __init imx31_timer_init_dt(struct device_node *np) -{ - enum imx_gpt_type type = GPT_TYPE_IMX31; - - /* - * We were using the same compatible string for i.MX6Q/D and i.MX6DL/S - * GPT device, while they actually have different programming model. - * This is a workaround to keep the existing i.MX6DL/S DTBs continue - * working with the new kernel. - */ - if (of_machine_is_compatible("fsl,imx6dl")) - type = GPT_TYPE_IMX6DL; - - mxc_timer_init_dt(np, type); -} - -static void __init imx6dl_timer_init_dt(struct device_node *np) -{ - mxc_timer_init_dt(np, GPT_TYPE_IMX6DL); -} - -CLOCKSOURCE_OF_DECLARE(imx1_timer, "fsl,imx1-gpt", imx1_timer_init_dt); -CLOCKSOURCE_OF_DECLARE(imx21_timer, "fsl,imx21-gpt", imx21_timer_init_dt); -CLOCKSOURCE_OF_DECLARE(imx31_timer, "fsl,imx31-gpt", imx31_timer_init_dt); -CLOCKSOURCE_OF_DECLARE(imx25_timer, "fsl,imx25-gpt", imx31_timer_init_dt); -CLOCKSOURCE_OF_DECLARE(imx50_timer, "fsl,imx50-gpt", imx31_timer_init_dt); -CLOCKSOURCE_OF_DECLARE(imx51_timer, "fsl,imx51-gpt", imx31_timer_init_dt); -CLOCKSOURCE_OF_DECLARE(imx53_timer, "fsl,imx53-gpt", imx31_timer_init_dt); -CLOCKSOURCE_OF_DECLARE(imx6q_timer, "fsl,imx6q-gpt", imx31_timer_init_dt); -CLOCKSOURCE_OF_DECLARE(imx6dl_timer, "fsl,imx6dl-gpt", imx6dl_timer_init_dt); -CLOCKSOURCE_OF_DECLARE(imx6sl_timer, "fsl,imx6sl-gpt", imx6dl_timer_init_dt); -CLOCKSOURCE_OF_DECLARE(imx6sx_timer, "fsl,imx6sx-gpt", imx6dl_timer_init_dt); diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index 51d7865f..618102e 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -258,4 +258,10 @@ config CLKSRC_PXA help This enables OST0 support available on PXA and SA-11x0 platforms. + +config CLKSRC_IMX_GPT + bool "Clocksource using i.MX GPT" if COMPILE_TEST + depends on ARM && CLKDEV_LOOKUP + select CLKSRC_MMIO + endmenu diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile index 5b85f6a..fce332c 100644 --- a/drivers/clocksource/Makefile +++ b/drivers/clocksource/Makefile @@ -51,4 +51,5 @@ obj-$(CONFIG_ARCH_KEYSTONE) += timer-keystone.o obj-$(CONFIG_ARCH_INTEGRATOR_AP) += timer-integrator-ap.o obj-$(CONFIG_CLKSRC_VERSATILE) += versatile.o obj-$(CONFIG_CLKSRC_MIPS_GIC) += mips-gic-timer.o +obj-$(CONFIG_CLKSRC_IMX_GPT) += timer-imx-gpt.o obj-$(CONFIG_ASM9260_TIMER) += asm9260_timer.o diff --git a/drivers/clocksource/timer-imx-gpt.c b/drivers/clocksource/timer-imx-gpt.c new file mode 100644 index 0000000..b460928 --- /dev/null +++ b/drivers/clocksource/timer-imx-gpt.c @@ -0,0 +1,542 @@ +/* + * linux/arch/arm/plat-mxc/time.c + * + * Copyright (C) 2000-2001 Deep Blue Solutions + * Copyright (C) 2002 Shane Nay (shane@minirl.com) + * Copyright (C) 2006-2007 Pavel Pisa (ppisa@pikron.com) + * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +/* + * There are 4 versions of the timer hardware on Freescale MXC hardware. + * - MX1/MXL + * - MX21, MX27. + * - MX25, MX31, MX35, MX37, MX51, MX6Q(rev1.0) + * - MX6DL, MX6SX, MX6Q(rev1.1+) + */ + +/* defines common for all i.MX */ +#define MXC_TCTL 0x00 +#define MXC_TCTL_TEN (1 << 0) /* Enable module */ +#define MXC_TPRER 0x04 + +/* MX1, MX21, MX27 */ +#define MX1_2_TCTL_CLK_PCLK1 (1 << 1) +#define MX1_2_TCTL_IRQEN (1 << 4) +#define MX1_2_TCTL_FRR (1 << 8) +#define MX1_2_TCMP 0x08 +#define MX1_2_TCN 0x10 +#define MX1_2_TSTAT 0x14 + +/* MX21, MX27 */ +#define MX2_TSTAT_CAPT (1 << 1) +#define MX2_TSTAT_COMP (1 << 0) + +/* MX31, MX35, MX25, MX5, MX6 */ +#define V2_TCTL_WAITEN (1 << 3) /* Wait enable mode */ +#define V2_TCTL_CLK_IPG (1 << 6) +#define V2_TCTL_CLK_PER (2 << 6) +#define V2_TCTL_CLK_OSC_DIV8 (5 << 6) +#define V2_TCTL_FRR (1 << 9) +#define V2_TCTL_24MEN (1 << 10) +#define V2_TPRER_PRE24M 12 +#define V2_IR 0x0c +#define V2_TSTAT 0x08 +#define V2_TSTAT_OF1 (1 << 0) +#define V2_TCN 0x24 +#define V2_TCMP 0x10 + +#define V2_TIMER_RATE_OSC_DIV8 3000000 + +struct imx_timer { + enum imx_gpt_type type; + void __iomem *base; + int irq; + struct clk *clk_per; + struct clk *clk_ipg; + const struct imx_gpt_data *gpt; + struct clock_event_device ced; + enum clock_event_mode cem; + struct irqaction act; +}; + +struct imx_gpt_data { + int reg_tstat; + int reg_tcn; + int reg_tcmp; + void (*gpt_setup_tctl)(struct imx_timer *imxtm); + void (*gpt_irq_enable)(struct imx_timer *imxtm); + void (*gpt_irq_disable)(struct imx_timer *imxtm); + void (*gpt_irq_acknowledge)(struct imx_timer *imxtm); + int (*set_next_event)(unsigned long evt, + struct clock_event_device *ced); +}; + +static inline struct imx_timer *to_imx_timer(struct clock_event_device *ced) +{ + return container_of(ced, struct imx_timer, ced); +} + +static void imx1_gpt_irq_disable(struct imx_timer *imxtm) +{ + unsigned int tmp; + + tmp = readl_relaxed(imxtm->base + MXC_TCTL); + writel_relaxed(tmp & ~MX1_2_TCTL_IRQEN, imxtm->base + MXC_TCTL); +} +#define imx21_gpt_irq_disable imx1_gpt_irq_disable + +static void imx31_gpt_irq_disable(struct imx_timer *imxtm) +{ + writel_relaxed(0, imxtm->base + V2_IR); +} +#define imx6dl_gpt_irq_disable imx31_gpt_irq_disable + +static void imx1_gpt_irq_enable(struct imx_timer *imxtm) +{ + unsigned int tmp; + + tmp = readl_relaxed(imxtm->base + MXC_TCTL); + writel_relaxed(tmp | MX1_2_TCTL_IRQEN, imxtm->base + MXC_TCTL); +} +#define imx21_gpt_irq_enable imx1_gpt_irq_enable + +static void imx31_gpt_irq_enable(struct imx_timer *imxtm) +{ + writel_relaxed(1<<0, imxtm->base + V2_IR); +} +#define imx6dl_gpt_irq_enable imx31_gpt_irq_enable + +static void imx1_gpt_irq_acknowledge(struct imx_timer *imxtm) +{ + writel_relaxed(0, imxtm->base + MX1_2_TSTAT); +} + +static void imx21_gpt_irq_acknowledge(struct imx_timer *imxtm) +{ + writel_relaxed(MX2_TSTAT_CAPT | MX2_TSTAT_COMP, + imxtm->base + MX1_2_TSTAT); +} + +static void imx31_gpt_irq_acknowledge(struct imx_timer *imxtm) +{ + writel_relaxed(V2_TSTAT_OF1, imxtm->base + V2_TSTAT); +} +#define imx6dl_gpt_irq_acknowledge imx31_gpt_irq_acknowledge + +static void __iomem *sched_clock_reg; + +static u64 notrace mxc_read_sched_clock(void) +{ + return sched_clock_reg ? readl_relaxed(sched_clock_reg) : 0; +} + +static struct delay_timer imx_delay_timer; + +static unsigned long imx_read_current_timer(void) +{ + return readl_relaxed(sched_clock_reg); +} + +static int __init mxc_clocksource_init(struct imx_timer *imxtm) +{ + unsigned int c = clk_get_rate(imxtm->clk_per); + void __iomem *reg = imxtm->base + imxtm->gpt->reg_tcn; + + imx_delay_timer.read_current_timer = &imx_read_current_timer; + imx_delay_timer.freq = c; + register_current_timer_delay(&imx_delay_timer); + + sched_clock_reg = reg; + + sched_clock_register(mxc_read_sched_clock, 32, c); + return clocksource_mmio_init(reg, "mxc_timer1", c, 200, 32, + clocksource_mmio_readl_up); +} + +/* clock event */ + +static int mx1_2_set_next_event(unsigned long evt, + struct clock_event_device *ced) +{ + struct imx_timer *imxtm = to_imx_timer(ced); + unsigned long tcmp; + + tcmp = readl_relaxed(imxtm->base + MX1_2_TCN) + evt; + + writel_relaxed(tcmp, imxtm->base + MX1_2_TCMP); + + return (int)(tcmp - readl_relaxed(imxtm->base + MX1_2_TCN)) < 0 ? + -ETIME : 0; +} + +static int v2_set_next_event(unsigned long evt, + struct clock_event_device *ced) +{ + struct imx_timer *imxtm = to_imx_timer(ced); + unsigned long tcmp; + + tcmp = readl_relaxed(imxtm->base + V2_TCN) + evt; + + writel_relaxed(tcmp, imxtm->base + V2_TCMP); + + return evt < 0x7fffffff && + (int)(tcmp - readl_relaxed(imxtm->base + V2_TCN)) < 0 ? + -ETIME : 0; +} + +#ifdef DEBUG +static const char *clock_event_mode_label[] = { + [CLOCK_EVT_MODE_PERIODIC] = "CLOCK_EVT_MODE_PERIODIC", + [CLOCK_EVT_MODE_ONESHOT] = "CLOCK_EVT_MODE_ONESHOT", + [CLOCK_EVT_MODE_SHUTDOWN] = "CLOCK_EVT_MODE_SHUTDOWN", + [CLOCK_EVT_MODE_UNUSED] = "CLOCK_EVT_MODE_UNUSED", + [CLOCK_EVT_MODE_RESUME] = "CLOCK_EVT_MODE_RESUME", +}; +#endif /* DEBUG */ + +static void mxc_set_mode(enum clock_event_mode mode, + struct clock_event_device *ced) +{ + struct imx_timer *imxtm = to_imx_timer(ced); + unsigned long flags; + + /* + * The timer interrupt generation is disabled at least + * for enough time to call mxc_set_next_event() + */ + local_irq_save(flags); + + /* Disable interrupt in GPT module */ + imxtm->gpt->gpt_irq_disable(imxtm); + + if (mode != imxtm->cem) { + u32 tcn = readl_relaxed(imxtm->base + imxtm->gpt->reg_tcn); + /* Set event time into far-far future */ + writel_relaxed(tcn - 3, imxtm->base + imxtm->gpt->reg_tcmp); + + /* Clear pending interrupt */ + imxtm->gpt->gpt_irq_acknowledge(imxtm); + } + +#ifdef DEBUG + printk(KERN_INFO "mxc_set_mode: changing mode from %s to %s\n", + clock_event_mode_label[imxtm->cem], + clock_event_mode_label[mode]); +#endif /* DEBUG */ + + /* Remember timer mode */ + imxtm->cem = mode; + local_irq_restore(flags); + + switch (mode) { + case CLOCK_EVT_MODE_PERIODIC: + printk(KERN_ERR"mxc_set_mode: Periodic mode is not " + "supported for i.MX\n"); + break; + case CLOCK_EVT_MODE_ONESHOT: + /* + * Do not put overhead of interrupt enable/disable into + * mxc_set_next_event(), the core has about 4 minutes + * to call mxc_set_next_event() or shutdown clock after + * mode switching + */ + local_irq_save(flags); + imxtm->gpt->gpt_irq_enable(imxtm); + local_irq_restore(flags); + break; + case CLOCK_EVT_MODE_SHUTDOWN: + case CLOCK_EVT_MODE_UNUSED: + case CLOCK_EVT_MODE_RESUME: + /* Left event sources disabled, no more interrupts appear */ + break; + } +} + +/* + * IRQ handler for the timer + */ +static irqreturn_t mxc_timer_interrupt(int irq, void *dev_id) +{ + struct clock_event_device *ced = dev_id; + struct imx_timer *imxtm = to_imx_timer(ced); + uint32_t tstat; + + tstat = readl_relaxed(imxtm->base + imxtm->gpt->reg_tstat); + + imxtm->gpt->gpt_irq_acknowledge(imxtm); + + ced->event_handler(ced); + + return IRQ_HANDLED; +} + +static int __init mxc_clockevent_init(struct imx_timer *imxtm) +{ + struct clock_event_device *ced = &imxtm->ced; + struct irqaction *act = &imxtm->act; + + imxtm->cem = CLOCK_EVT_MODE_UNUSED; + + ced->name = "mxc_timer1"; + ced->features = CLOCK_EVT_FEAT_ONESHOT; + ced->set_mode = mxc_set_mode; + ced->set_next_event = imxtm->gpt->set_next_event; + ced->rating = 200; + ced->cpumask = cpumask_of(0); + clockevents_config_and_register(ced, clk_get_rate(imxtm->clk_per), + 0xff, 0xfffffffe); + + act->name = "i.MX Timer Tick"; + act->flags = IRQF_TIMER | IRQF_IRQPOLL; + act->handler = mxc_timer_interrupt; + act->dev_id = ced; + + return setup_irq(imxtm->irq, act); +} + +static void imx1_gpt_setup_tctl(struct imx_timer *imxtm) +{ + u32 tctl_val; + + tctl_val = MX1_2_TCTL_FRR | MX1_2_TCTL_CLK_PCLK1 | MXC_TCTL_TEN; + writel_relaxed(tctl_val, imxtm->base + MXC_TCTL); +} +#define imx21_gpt_setup_tctl imx1_gpt_setup_tctl + +static void imx31_gpt_setup_tctl(struct imx_timer *imxtm) +{ + u32 tctl_val; + + tctl_val = V2_TCTL_FRR | V2_TCTL_WAITEN | MXC_TCTL_TEN; + if (clk_get_rate(imxtm->clk_per) == V2_TIMER_RATE_OSC_DIV8) + tctl_val |= V2_TCTL_CLK_OSC_DIV8; + else + tctl_val |= V2_TCTL_CLK_PER; + + writel_relaxed(tctl_val, imxtm->base + MXC_TCTL); +} + +static void imx6dl_gpt_setup_tctl(struct imx_timer *imxtm) +{ + u32 tctl_val; + + tctl_val = V2_TCTL_FRR | V2_TCTL_WAITEN | MXC_TCTL_TEN; + if (clk_get_rate(imxtm->clk_per) == V2_TIMER_RATE_OSC_DIV8) { + tctl_val |= V2_TCTL_CLK_OSC_DIV8; + /* 24 / 8 = 3 MHz */ + writel_relaxed(7 << V2_TPRER_PRE24M, imxtm->base + MXC_TPRER); + tctl_val |= V2_TCTL_24MEN; + } else { + tctl_val |= V2_TCTL_CLK_PER; + } + + writel_relaxed(tctl_val, imxtm->base + MXC_TCTL); +} + +static const struct imx_gpt_data imx1_gpt_data = { + .reg_tstat = MX1_2_TSTAT, + .reg_tcn = MX1_2_TCN, + .reg_tcmp = MX1_2_TCMP, + .gpt_irq_enable = imx1_gpt_irq_enable, + .gpt_irq_disable = imx1_gpt_irq_disable, + .gpt_irq_acknowledge = imx1_gpt_irq_acknowledge, + .gpt_setup_tctl = imx1_gpt_setup_tctl, + .set_next_event = mx1_2_set_next_event, +}; + +static const struct imx_gpt_data imx21_gpt_data = { + .reg_tstat = MX1_2_TSTAT, + .reg_tcn = MX1_2_TCN, + .reg_tcmp = MX1_2_TCMP, + .gpt_irq_enable = imx21_gpt_irq_enable, + .gpt_irq_disable = imx21_gpt_irq_disable, + .gpt_irq_acknowledge = imx21_gpt_irq_acknowledge, + .gpt_setup_tctl = imx21_gpt_setup_tctl, + .set_next_event = mx1_2_set_next_event, +}; + +static const struct imx_gpt_data imx31_gpt_data = { + .reg_tstat = V2_TSTAT, + .reg_tcn = V2_TCN, + .reg_tcmp = V2_TCMP, + .gpt_irq_enable = imx31_gpt_irq_enable, + .gpt_irq_disable = imx31_gpt_irq_disable, + .gpt_irq_acknowledge = imx31_gpt_irq_acknowledge, + .gpt_setup_tctl = imx31_gpt_setup_tctl, + .set_next_event = v2_set_next_event, +}; + +static const struct imx_gpt_data imx6dl_gpt_data = { + .reg_tstat = V2_TSTAT, + .reg_tcn = V2_TCN, + .reg_tcmp = V2_TCMP, + .gpt_irq_enable = imx6dl_gpt_irq_enable, + .gpt_irq_disable = imx6dl_gpt_irq_disable, + .gpt_irq_acknowledge = imx6dl_gpt_irq_acknowledge, + .gpt_setup_tctl = imx6dl_gpt_setup_tctl, + .set_next_event = v2_set_next_event, +}; + +static void __init _mxc_timer_init(struct imx_timer *imxtm) +{ + switch (imxtm->type) { + case GPT_TYPE_IMX1: + imxtm->gpt = &imx1_gpt_data; + break; + case GPT_TYPE_IMX21: + imxtm->gpt = &imx21_gpt_data; + break; + case GPT_TYPE_IMX31: + imxtm->gpt = &imx31_gpt_data; + break; + case GPT_TYPE_IMX6DL: + imxtm->gpt = &imx6dl_gpt_data; + break; + default: + BUG(); + } + + if (IS_ERR(imxtm->clk_per)) { + pr_err("i.MX timer: unable to get clk\n"); + return; + } + + if (!IS_ERR(imxtm->clk_ipg)) + clk_prepare_enable(imxtm->clk_ipg); + + clk_prepare_enable(imxtm->clk_per); + + /* + * Initialise to a known state (all timers off, and timing reset) + */ + + writel_relaxed(0, imxtm->base + MXC_TCTL); + writel_relaxed(0, imxtm->base + MXC_TPRER); /* see datasheet note */ + + imxtm->gpt->gpt_setup_tctl(imxtm); + + /* init and register the timer to the framework */ + mxc_clocksource_init(imxtm); + mxc_clockevent_init(imxtm); +} + +void __init mxc_timer_init(unsigned long pbase, int irq, enum imx_gpt_type type) +{ + struct imx_timer *imxtm; + + imxtm = kzalloc(sizeof(*imxtm), GFP_KERNEL); + BUG_ON(!imxtm); + + imxtm->clk_per = clk_get_sys("imx-gpt.0", "per"); + imxtm->clk_ipg = clk_get_sys("imx-gpt.0", "ipg"); + + imxtm->base = ioremap(pbase, SZ_4K); + BUG_ON(!imxtm->base); + + imxtm->type = type; + + _mxc_timer_init(imxtm); +} + +static void __init mxc_timer_init_dt(struct device_node *np, enum imx_gpt_type type) +{ + struct imx_timer *imxtm; + static int initialized; + + /* Support one instance only */ + if (initialized) + return; + + imxtm = kzalloc(sizeof(*imxtm), GFP_KERNEL); + BUG_ON(!imxtm); + + imxtm->base = of_iomap(np, 0); + WARN_ON(!imxtm->base); + imxtm->irq = irq_of_parse_and_map(np, 0); + + imxtm->clk_ipg = of_clk_get_by_name(np, "ipg"); + + /* Try osc_per first, and fall back to per otherwise */ + imxtm->clk_per = of_clk_get_by_name(np, "osc_per"); + if (IS_ERR(imxtm->clk_per)) + imxtm->clk_per = of_clk_get_by_name(np, "per"); + + imxtm->type = type; + + _mxc_timer_init(imxtm); + + initialized = 1; +} + +static void __init imx1_timer_init_dt(struct device_node *np) +{ + mxc_timer_init_dt(np, GPT_TYPE_IMX1); +} + +static void __init imx21_timer_init_dt(struct device_node *np) +{ + mxc_timer_init_dt(np, GPT_TYPE_IMX21); +} + +static void __init imx31_timer_init_dt(struct device_node *np) +{ + enum imx_gpt_type type = GPT_TYPE_IMX31; + + /* + * We were using the same compatible string for i.MX6Q/D and i.MX6DL/S + * GPT device, while they actually have different programming model. + * This is a workaround to keep the existing i.MX6DL/S DTBs continue + * working with the new kernel. + */ + if (of_machine_is_compatible("fsl,imx6dl")) + type = GPT_TYPE_IMX6DL; + + mxc_timer_init_dt(np, type); +} + +static void __init imx6dl_timer_init_dt(struct device_node *np) +{ + mxc_timer_init_dt(np, GPT_TYPE_IMX6DL); +} + +CLOCKSOURCE_OF_DECLARE(imx1_timer, "fsl,imx1-gpt", imx1_timer_init_dt); +CLOCKSOURCE_OF_DECLARE(imx21_timer, "fsl,imx21-gpt", imx21_timer_init_dt); +CLOCKSOURCE_OF_DECLARE(imx31_timer, "fsl,imx31-gpt", imx31_timer_init_dt); +CLOCKSOURCE_OF_DECLARE(imx25_timer, "fsl,imx25-gpt", imx31_timer_init_dt); +CLOCKSOURCE_OF_DECLARE(imx50_timer, "fsl,imx50-gpt", imx31_timer_init_dt); +CLOCKSOURCE_OF_DECLARE(imx51_timer, "fsl,imx51-gpt", imx31_timer_init_dt); +CLOCKSOURCE_OF_DECLARE(imx53_timer, "fsl,imx53-gpt", imx31_timer_init_dt); +CLOCKSOURCE_OF_DECLARE(imx6q_timer, "fsl,imx6q-gpt", imx31_timer_init_dt); +CLOCKSOURCE_OF_DECLARE(imx6dl_timer, "fsl,imx6dl-gpt", imx6dl_timer_init_dt); +CLOCKSOURCE_OF_DECLARE(imx6sl_timer, "fsl,imx6sl-gpt", imx6dl_timer_init_dt); +CLOCKSOURCE_OF_DECLARE(imx6sx_timer, "fsl,imx6sx-gpt", imx6dl_timer_init_dt); -- cgit v0.10.2