From f7b98477f613a69b74ba4a715856630cc6508c0d Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Mon, 4 Aug 2014 15:51:48 +0900 Subject: ARM: shmobile: Remove genmai_defconfig from MAINTAINERS The genmai defconfig file has been removed by 3ed27bd90d6d0c8b ("ARM: shmobile: genmai: remove defconfig") so remove its entry in the MAINTAINERS accordingly. Reported-by: Joe Perches Signed-off-by: Simon Horman diff --git a/MAINTAINERS b/MAINTAINERS index aefa948..99b7807 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1355,7 +1355,6 @@ F: arch/arm/boot/dts/sh* F: arch/arm/configs/ape6evm_defconfig F: arch/arm/configs/armadillo800eva_defconfig F: arch/arm/configs/bockw_defconfig -F: arch/arm/configs/genmai_defconfig F: arch/arm/configs/koelsch_defconfig F: arch/arm/configs/kzm9g_defconfig F: arch/arm/configs/lager_defconfig -- cgit v0.10.2 From 79436f870c910bfa296c76e9f43a9aae69f1b46d Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Mon, 28 Jul 2014 14:24:37 +0300 Subject: ARM: davinci: board-da850-evm: Mark dcdc2 of TPS65070 as always_on DCDC2 should not be turned off since it is powering the CPU among other things. Signed-off-by: Peter Ujfalusi Signed-off-by: Sekhar Nori diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c index 234c5bb..77d8968 100644 --- a/arch/arm/mach-davinci/board-da850-evm.c +++ b/arch/arm/mach-davinci/board-da850-evm.c @@ -936,6 +936,7 @@ static struct regulator_init_data tps65070_regulator_data[] = { .valid_ops_mask = (REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS), .boot_on = 1, + .always_on = 1, }, .num_consumer_supplies = ARRAY_SIZE(tps65070_dcdc2_consumers), .consumer_supplies = tps65070_dcdc2_consumers, -- cgit v0.10.2 From 9e9bc235580829e3a06ccd13aa10110478c2e093 Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Mon, 28 Jul 2014 14:24:38 +0300 Subject: ARM: davinci: board-da850-evm: Add needed regulators for tlv320aic3106 codec IOVDD: tps65070's dcdc2 AVDD and DRVDD: fixed regulator derived from 5V via TPS73701DCQ DVDD: fixed regulator derived from 5V via TPS73701DCQ This patch needed to be able to probe the audio codec. Signed-off-by: Peter Ujfalusi Signed-off-by: Sekhar Nori diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c index 77d8968..fa11415 100644 --- a/arch/arm/mach-davinci/board-da850-evm.c +++ b/arch/arm/mach-davinci/board-da850-evm.c @@ -35,6 +35,7 @@ #include #include #include +#include #include #include #include @@ -842,6 +843,16 @@ static int da850_lcd_hw_init(void) return 0; } +/* Fixed regulator support */ +static struct regulator_consumer_supply fixed_supplies[] = { + /* Baseboard 3.3V: 5V -> TPS73701DCQ -> 3.3V */ + REGULATOR_SUPPLY("AVDD", "1-0018"), + REGULATOR_SUPPLY("DRVDD", "1-0018"), + + /* Baseboard 1.8V: 5V -> TPS73701DCQ -> 1.8V */ + REGULATOR_SUPPLY("DVDD", "1-0018"), +}; + /* TPS65070 voltage regulator support */ /* 3.3V */ @@ -865,6 +876,7 @@ static struct regulator_consumer_supply tps65070_dcdc2_consumers[] = { { .supply = "dvdd3318_c", }, + REGULATOR_SUPPLY("IOVDD", "1-0018"), }; /* 1.2V */ @@ -1447,6 +1459,8 @@ static __init void da850_evm_init(void) if (ret) pr_warn("%s: GPIO init failed: %d\n", __func__, ret); + regulator_register_fixed(0, fixed_supplies, ARRAY_SIZE(fixed_supplies)); + ret = pmic_tps65070_init(); if (ret) pr_warn("%s: TPS65070 PMIC init failed: %d\n", __func__, ret); -- cgit v0.10.2 From a1a57abaaf820a3ed2fe72d70bf52f57a7a5ae21 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Thu, 28 Aug 2014 15:45:03 -0500 Subject: ARM: dts: omap4-panda: Fix model and SoC family details Currently we claim that omap4-panda and omap4-panda-es are essentially the same, but they are not since PandaBoard-ES uses OMAP4460 and PandaBoard uses OMAP4430. So, split the common definition and make the model name available. Signed-off-by: Nishanth Menon Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi b/arch/arm/boot/dts/omap4-panda-common.dtsi index 8cfa3c8..1505135 100644 --- a/arch/arm/boot/dts/omap4-panda-common.dtsi +++ b/arch/arm/boot/dts/omap4-panda-common.dtsi @@ -8,9 +8,6 @@ #include "elpida_ecb240abacn.dtsi" / { - model = "TI OMAP4 PandaBoard"; - compatible = "ti,omap4-panda", "ti,omap4430", "ti,omap4"; - memory { device_type = "memory"; reg = <0x80000000 0x40000000>; /* 1 GB */ diff --git a/arch/arm/boot/dts/omap4-panda-es.dts b/arch/arm/boot/dts/omap4-panda-es.dts index 816d1c9..2f1dabc 100644 --- a/arch/arm/boot/dts/omap4-panda-es.dts +++ b/arch/arm/boot/dts/omap4-panda-es.dts @@ -10,6 +10,11 @@ #include "omap4460.dtsi" #include "omap4-panda-common.dtsi" +/ { + model = "TI OMAP4 PandaBoard-ES"; + compatible = "ti,omap4-panda-es", "ti,omap4-panda", "ti,omap4460", "ti,omap4430", "ti,omap4"; +}; + /* Audio routing is differnet between PandaBoard4430 and PandaBoardES */ &sound { ti,model = "PandaBoardES"; diff --git a/arch/arm/boot/dts/omap4-panda.dts b/arch/arm/boot/dts/omap4-panda.dts index 6189a8b..a0e28b2 100644 --- a/arch/arm/boot/dts/omap4-panda.dts +++ b/arch/arm/boot/dts/omap4-panda.dts @@ -9,3 +9,8 @@ #include "omap443x.dtsi" #include "omap4-panda-common.dtsi" + +/ { + model = "TI OMAP4 PandaBoard"; + compatible = "ti,omap4-panda", "ti,omap4430", "ti,omap4"; +}; -- cgit v0.10.2 From 9a15fff05b702c3ea29ae64db0d3ff0355431eab Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Wed, 3 Sep 2014 11:03:10 -0500 Subject: ARM: dts: am335x-bone*: Fix model name and update compatibility information Beaglebone white and beaglebone black differ in tiny little aspects. This is the reason why we maintain seperate dts for these platforms. However, there is no real way to decode from dtb which platform it is since compatible and model name are the same for both platforms. Fix this so that beaglebone black and beaglebone are identifiable, while maintaining compatibility for older zImages which might use old beaglebone compatible flag for black as well. Reported-by: Tom Rini Signed-off-by: Nishanth Menon Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/am335x-bone-common.dtsi b/arch/arm/boot/dts/am335x-bone-common.dtsi index bde1777..d9d9869 100644 --- a/arch/arm/boot/dts/am335x-bone-common.dtsi +++ b/arch/arm/boot/dts/am335x-bone-common.dtsi @@ -7,9 +7,6 @@ */ / { - model = "TI AM335x BeagleBone"; - compatible = "ti,am335x-bone", "ti,am33xx"; - cpus { cpu@0 { cpu0-supply = <&dcdc2_reg>; diff --git a/arch/arm/boot/dts/am335x-bone.dts b/arch/arm/boot/dts/am335x-bone.dts index 94ee427..83d40f7 100644 --- a/arch/arm/boot/dts/am335x-bone.dts +++ b/arch/arm/boot/dts/am335x-bone.dts @@ -10,6 +10,11 @@ #include "am33xx.dtsi" #include "am335x-bone-common.dtsi" +/ { + model = "TI AM335x BeagleBone"; + compatible = "ti,am335x-bone", "ti,am33xx"; +}; + &ldo3_reg { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; diff --git a/arch/arm/boot/dts/am335x-boneblack.dts b/arch/arm/boot/dts/am335x-boneblack.dts index 305975d..901739f 100644 --- a/arch/arm/boot/dts/am335x-boneblack.dts +++ b/arch/arm/boot/dts/am335x-boneblack.dts @@ -10,6 +10,11 @@ #include "am33xx.dtsi" #include "am335x-bone-common.dtsi" +/ { + model = "TI AM335x BeagleBone Black"; + compatible = "ti,am335x-bone-black", "ti,am335x-bone", "ti,am33xx"; +}; + &ldo3_reg { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; -- cgit v0.10.2 From 0a2e912d296201c476fe5d7ba6ac23a66325935f Mon Sep 17 00:00:00 2001 From: Xia Kaixu Date: Wed, 3 Sep 2014 21:18:12 +0800 Subject: ARM: cns3xxx: fix allmodconfig panic in pci driver The kernel panic occurs when running an allmodconfig kernel on OMAP4460. The inicall "cns3xxx_pcie_init" does not check which hardware it's running on and just tries to access to its specific registers. Now call it from .init_late callback from the two machine descriptors. Signed-off-by: Xia Kaixu Signed-off-by: Arnd Bergmann Cc: Anton Vorontsov Cc: Felix Fietkau Cc: Imre Kaloz Cc: linaro-kernel@lists.linaro.org Cc: linux-arm-kernel@lists.infradead.org diff --git a/arch/arm/mach-cns3xxx/cns3420vb.c b/arch/arm/mach-cns3xxx/cns3420vb.c index d863d87..6428bcc7 100644 --- a/arch/arm/mach-cns3xxx/cns3420vb.c +++ b/arch/arm/mach-cns3xxx/cns3420vb.c @@ -250,5 +250,6 @@ MACHINE_START(CNS3420VB, "Cavium Networks CNS3420 Validation Board") .init_irq = cns3xxx_init_irq, .init_time = cns3xxx_timer_init, .init_machine = cns3420_init, + .init_late = cns3xxx_pcie_init_late, .restart = cns3xxx_restart, MACHINE_END diff --git a/arch/arm/mach-cns3xxx/core.c b/arch/arm/mach-cns3xxx/core.c index f85449a..4e9837d 100644 --- a/arch/arm/mach-cns3xxx/core.c +++ b/arch/arm/mach-cns3xxx/core.c @@ -404,5 +404,6 @@ DT_MACHINE_START(CNS3XXX_DT, "Cavium Networks CNS3xxx") .init_irq = cns3xxx_init_irq, .init_time = cns3xxx_timer_init, .init_machine = cns3xxx_init, + .init_late = cns3xxx_pcie_init_late, .restart = cns3xxx_restart, MACHINE_END diff --git a/arch/arm/mach-cns3xxx/core.h b/arch/arm/mach-cns3xxx/core.h index 5218b61..dc5df7f 100644 --- a/arch/arm/mach-cns3xxx/core.h +++ b/arch/arm/mach-cns3xxx/core.h @@ -21,6 +21,12 @@ void __init cns3xxx_l2x0_init(void); static inline void cns3xxx_l2x0_init(void) {} #endif /* CONFIG_CACHE_L2X0 */ +#ifdef CONFIG_PCI +extern void __init cns3xxx_pcie_init_late(void); +#else +static inline void __init cns3xxx_pcie_init_late(void) {} +#endif + void __init cns3xxx_map_io(void); void __init cns3xxx_init_irq(void); void cns3xxx_power_off(void); diff --git a/arch/arm/mach-cns3xxx/pcie.c b/arch/arm/mach-cns3xxx/pcie.c index 413134c..70fd81e 100644 --- a/arch/arm/mach-cns3xxx/pcie.c +++ b/arch/arm/mach-cns3xxx/pcie.c @@ -318,7 +318,7 @@ static int cns3xxx_pcie_abort_handler(unsigned long addr, unsigned int fsr, return 0; } -static int __init cns3xxx_pcie_init(void) +void __init cns3xxx_pcie_init_late(void) { int i; @@ -337,7 +337,4 @@ static int __init cns3xxx_pcie_init(void) } pci_assign_unassigned_resources(); - - return 0; } -device_initcall(cns3xxx_pcie_init); diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm index 7364a53..18ad141 100644 --- a/drivers/cpufreq/Kconfig.arm +++ b/drivers/cpufreq/Kconfig.arm @@ -77,7 +77,7 @@ config ARM_EXYNOS5440_CPUFREQ config ARM_EXYNOS_CPU_FREQ_BOOST_SW bool "EXYNOS Frequency Overclocking - Software" - depends on ARM_EXYNOS_CPUFREQ + depends on ARM_EXYNOS_CPUFREQ && THERMAL select CPU_FREQ_BOOST_SW select EXYNOS_THERMAL help -- cgit v0.10.2 From 3b0b8ec99aadea710f3dece74c95523463c0087a Mon Sep 17 00:00:00 2001 From: Paul Bolle Date: Tue, 15 Apr 2014 10:26:47 +0200 Subject: ARM: spear: Remove references to PLAT_SPEAR_SINGLE The Kconfig symbol PLAT_SPEAR_SINGLE briefly appeared during the v3.10 development cycle. It was removed in a merge commit before v3.10. A few references to it were left in the tree, probably because they didn't generate merge conflicts. Whatever it was, they're useless now and can safely be removed. Reported-by: Martin Walch Signed-off-by: Paul Bolle Reviewed-by: Rajeev Kumar Cc: Rajeev Kumar Acked-by: Viresh Kumar Signed-off-by: Arnd Bergmann diff --git a/arch/arm/mach-spear/Kconfig b/arch/arm/mach-spear/Kconfig index 6fd4dc8..b6f4bda2 100644 --- a/arch/arm/mach-spear/Kconfig +++ b/arch/arm/mach-spear/Kconfig @@ -4,7 +4,6 @@ menuconfig PLAT_SPEAR bool "ST SPEAr Family" if ARCH_MULTI_V7 || ARCH_MULTI_V5 - default PLAT_SPEAR_SINGLE select ARCH_REQUIRE_GPIOLIB select ARM_AMBA select CLKSRC_MMIO @@ -13,7 +12,7 @@ if PLAT_SPEAR config ARCH_SPEAR13XX bool "ST SPEAr13xx" - depends on ARCH_MULTI_V7 || PLAT_SPEAR_SINGLE + depends on ARCH_MULTI_V7 select ARM_GIC select GPIO_SPEAR_SPICS select HAVE_ARM_SCU if SMP @@ -44,7 +43,7 @@ endif #ARCH_SPEAR13XX config ARCH_SPEAR3XX bool "ST SPEAr3xx" - depends on ARCH_MULTI_V5 || PLAT_SPEAR_SINGLE + depends on ARCH_MULTI_V5 depends on !ARCH_SPEAR13XX select ARM_VIC select PINCTRL @@ -75,7 +74,7 @@ endif config ARCH_SPEAR6XX bool "ST SPEAr6XX" - depends on ARCH_MULTI_V5 || PLAT_SPEAR_SINGLE + depends on ARCH_MULTI_V5 depends on !ARCH_SPEAR13XX select ARM_VIC help @@ -88,7 +87,7 @@ config MACH_SPEAR600 Supports ST SPEAr600 boards configured via the device-tree config ARCH_SPEAR_AUTO - def_bool PLAT_SPEAR_SINGLE + bool depends on !ARCH_SPEAR13XX && !ARCH_SPEAR6XX select ARCH_SPEAR3XX -- cgit v0.10.2 From cafc8cb5b9c84426f3aae3179a64e41d3de97c50 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Fri, 6 Jun 2014 01:21:51 -0500 Subject: ARM: OMAP: DRA7: powerdomain data: fix powerdomain powerstate DRA7 supports only CSWR for CPU, MPU power domains. Core power domain supports upto INA. Signed-off-by: Nishanth Menon Reviewed-by: Kevin Hilman Acked-by: Santosh Shilimkar diff --git a/arch/arm/mach-omap2/powerdomain.h b/arch/arm/mach-omap2/powerdomain.h index f472711..a754c82 100644 --- a/arch/arm/mach-omap2/powerdomain.h +++ b/arch/arm/mach-omap2/powerdomain.h @@ -39,6 +39,7 @@ #define PWRSTS_OFF_RET (PWRSTS_OFF | PWRSTS_RET) #define PWRSTS_RET_ON (PWRSTS_RET | PWRSTS_ON) #define PWRSTS_OFF_RET_ON (PWRSTS_OFF_RET | PWRSTS_ON) +#define PWRSTS_INA_ON (PWRSTS_INACTIVE | PWRSTS_ON) /* diff --git a/arch/arm/mach-omap2/powerdomains7xx_data.c b/arch/arm/mach-omap2/powerdomains7xx_data.c index 48151d1..287a203 100644 --- a/arch/arm/mach-omap2/powerdomains7xx_data.c +++ b/arch/arm/mach-omap2/powerdomains7xx_data.c @@ -160,8 +160,8 @@ static struct powerdomain core_7xx_pwrdm = { .name = "core_pwrdm", .prcm_offs = DRA7XX_PRM_CORE_INST, .prcm_partition = DRA7XX_PRM_PARTITION, - .pwrsts = PWRSTS_RET_ON, - .pwrsts_logic_ret = PWRSTS_OFF_RET, + .pwrsts = PWRSTS_INA_ON, + .pwrsts_logic_ret = PWRSTS_RET, .banks = 5, .pwrsts_mem_ret = { [0] = PWRSTS_OFF_RET, /* core_nret_bank */ @@ -193,8 +193,8 @@ static struct powerdomain cpu0_7xx_pwrdm = { .name = "cpu0_pwrdm", .prcm_offs = DRA7XX_MPU_PRCM_PRM_C0_INST, .prcm_partition = DRA7XX_MPU_PRCM_PARTITION, - .pwrsts = PWRSTS_OFF_RET_ON, - .pwrsts_logic_ret = PWRSTS_OFF_RET, + .pwrsts = PWRSTS_RET_ON, + .pwrsts_logic_ret = PWRSTS_RET, .banks = 1, .pwrsts_mem_ret = { [0] = PWRSTS_OFF_RET, /* cpu0_l1 */ @@ -209,8 +209,8 @@ static struct powerdomain cpu1_7xx_pwrdm = { .name = "cpu1_pwrdm", .prcm_offs = DRA7XX_MPU_PRCM_PRM_C1_INST, .prcm_partition = DRA7XX_MPU_PRCM_PARTITION, - .pwrsts = PWRSTS_OFF_RET_ON, - .pwrsts_logic_ret = PWRSTS_OFF_RET, + .pwrsts = PWRSTS_RET_ON, + .pwrsts_logic_ret = PWRSTS_RET, .banks = 1, .pwrsts_mem_ret = { [0] = PWRSTS_OFF_RET, /* cpu1_l1 */ @@ -243,7 +243,7 @@ static struct powerdomain mpu_7xx_pwrdm = { .prcm_offs = DRA7XX_PRM_MPU_INST, .prcm_partition = DRA7XX_PRM_PARTITION, .pwrsts = PWRSTS_RET_ON, - .pwrsts_logic_ret = PWRSTS_OFF_RET, + .pwrsts_logic_ret = PWRSTS_RET, .banks = 2, .pwrsts_mem_ret = { [0] = PWRSTS_OFF_RET, /* mpu_l2 */ -- cgit v0.10.2 From 9f5dc91b691cf296c49aedf0a671fd659a70f737 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Wed, 20 Aug 2014 08:13:16 -0500 Subject: ARM: OMAP5: powerdomain data: fix powerdomain powerstate Update the power domain power states for final production chip capability. OFF mode, OSWR etc have been descoped for various domains. Signed-off-by: Nishanth Menon Reviewed-by: Kevin Hilman Acked-by: Santosh Shilimkar diff --git a/arch/arm/mach-omap2/powerdomains54xx_data.c b/arch/arm/mach-omap2/powerdomains54xx_data.c index ce1d752..60d7ed8 100644 --- a/arch/arm/mach-omap2/powerdomains54xx_data.c +++ b/arch/arm/mach-omap2/powerdomains54xx_data.c @@ -35,7 +35,7 @@ static struct powerdomain core_54xx_pwrdm = { .prcm_offs = OMAP54XX_PRM_CORE_INST, .prcm_partition = OMAP54XX_PRM_PARTITION, .pwrsts = PWRSTS_RET_ON, - .pwrsts_logic_ret = PWRSTS_OFF_RET, + .pwrsts_logic_ret = PWRSTS_RET, .banks = 5, .pwrsts_mem_ret = { [0] = PWRSTS_OFF_RET, /* core_nret_bank */ @@ -107,8 +107,8 @@ static struct powerdomain cpu0_54xx_pwrdm = { .voltdm = { .name = "mpu" }, .prcm_offs = OMAP54XX_PRCM_MPU_PRM_C0_INST, .prcm_partition = OMAP54XX_PRCM_MPU_PARTITION, - .pwrsts = PWRSTS_OFF_RET_ON, - .pwrsts_logic_ret = PWRSTS_OFF_RET, + .pwrsts = PWRSTS_RET_ON, + .pwrsts_logic_ret = PWRSTS_RET, .banks = 1, .pwrsts_mem_ret = { [0] = PWRSTS_OFF_RET, /* cpu0_l1 */ @@ -124,8 +124,8 @@ static struct powerdomain cpu1_54xx_pwrdm = { .voltdm = { .name = "mpu" }, .prcm_offs = OMAP54XX_PRCM_MPU_PRM_C1_INST, .prcm_partition = OMAP54XX_PRCM_MPU_PARTITION, - .pwrsts = PWRSTS_OFF_RET_ON, - .pwrsts_logic_ret = PWRSTS_OFF_RET, + .pwrsts = PWRSTS_RET_ON, + .pwrsts_logic_ret = PWRSTS_RET, .banks = 1, .pwrsts_mem_ret = { [0] = PWRSTS_OFF_RET, /* cpu1_l1 */ @@ -158,7 +158,7 @@ static struct powerdomain mpu_54xx_pwrdm = { .prcm_offs = OMAP54XX_PRM_MPU_INST, .prcm_partition = OMAP54XX_PRM_PARTITION, .pwrsts = PWRSTS_RET_ON, - .pwrsts_logic_ret = PWRSTS_OFF_RET, + .pwrsts_logic_ret = PWRSTS_RET, .banks = 2, .pwrsts_mem_ret = { [0] = PWRSTS_OFF_RET, /* mpu_l2 */ -- cgit v0.10.2 From 13bbffd4ebca57dfae59a3f13ff98dc417f89b23 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Fri, 6 Jun 2014 19:36:41 -0500 Subject: ARM: OMAP2+: powerdomain: pwrdm_for_each_clkdm iterate only valid clkdms No need to invoke callback when the clkdm pointer is NULL. Signed-off-by: Nishanth Menon Reviewed-by: Kevin Hilman Acked-by: Santosh Shilimkar diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c index faebd5f..f391948 100644 --- a/arch/arm/mach-omap2/powerdomain.c +++ b/arch/arm/mach-omap2/powerdomain.c @@ -546,7 +546,8 @@ int pwrdm_for_each_clkdm(struct powerdomain *pwrdm, return -EINVAL; for (i = 0; i < PWRDM_MAX_CLKDMS && !ret; i++) - ret = (*fn)(pwrdm, pwrdm->pwrdm_clkdms[i]); + if (pwrdm->pwrdm_clkdms[i]) + ret = (*fn)(pwrdm, pwrdm->pwrdm_clkdms[i]); return ret; } -- cgit v0.10.2 From bd002d7bdafc695decf7d4aeba285097356938f1 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Fri, 6 Jun 2014 01:04:20 -0500 Subject: ARM: OMAP2+: powerdomain: introduce logic for finding valid power domain powerdomain configuration in OMAP is done using PWRSTCTRL register for each power domain. However, PRCM lets us write any value we'd like to the logic and power domain target states, however the SoC integration tends to actually function only at a few discrete states. These valid states are already in our powerdomains_xxx_data.c file. So, provide a function to easily query valid low power state that the power domain is allowed to go to. Based on work originally done by Jean Pihet https://patchwork.kernel.org/patch/1325091/ . There is no attempt to create a new powerdomain solution here, except fixing issues seen attempting invalid programming attempts. Future consolidation to the generic powerdomain framework should consider this requirement as well. Similar solutions have been done in product kernels in the past such as: https://android.googlesource.com/kernel/omap.git/+blame/android-omap-panda-3.0/arch/arm/mach-omap2/pm44xx.c Signed-off-by: Nishanth Menon Reviewed-by: Kevin Hilman Acked-by: Santosh Shilimkar diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c index f391948..7fb033e 100644 --- a/arch/arm/mach-omap2/powerdomain.c +++ b/arch/arm/mach-omap2/powerdomain.c @@ -1081,6 +1081,82 @@ int pwrdm_post_transition(struct powerdomain *pwrdm) } /** + * pwrdm_get_valid_lp_state() - Find best match deep power state + * @pwrdm: power domain for which we want to find best match + * @is_logic_state: Are we looking for logic state match here? Should + * be one of PWRDM_xxx macro values + * @req_state: requested power state + * + * Returns: closest match for requested power state. default fallback + * is RET for logic state and ON for power state. + * + * This does a search from the power domain data looking for the + * closest valid power domain state that the hardware can achieve. + * PRCM definitions for PWRSTCTRL allows us to program whatever + * configuration we'd like, and PRCM will actually attempt such + * a transition, however if the powerdomain does not actually support it, + * we endup with a hung system. The valid power domain states are already + * available in our powerdomain data files. So this function tries to do + * the following: + * a) find if we have an exact match to the request - no issues. + * b) else find if a deeper power state is possible. + * c) failing which, it tries to find closest higher power state for the + * request. + */ +u8 pwrdm_get_valid_lp_state(struct powerdomain *pwrdm, + bool is_logic_state, u8 req_state) +{ + u8 pwrdm_states = is_logic_state ? pwrdm->pwrsts_logic_ret : + pwrdm->pwrsts; + /* For logic, ret is highest and others, ON is highest */ + u8 default_pwrst = is_logic_state ? PWRDM_POWER_RET : PWRDM_POWER_ON; + u8 new_pwrst; + bool found; + + /* If it is already supported, nothing to search */ + if (pwrdm_states & BIT(req_state)) + return req_state; + + if (!req_state) + goto up_search; + + /* + * So, we dont have a exact match + * Can we get a deeper power state match? + */ + new_pwrst = req_state - 1; + found = true; + while (!(pwrdm_states & BIT(new_pwrst))) { + /* No match even at OFF? Not available */ + if (new_pwrst == PWRDM_POWER_OFF) { + found = false; + break; + } + new_pwrst--; + } + + if (found) + goto done; + +up_search: + /* OK, no deeper ones, can we get a higher match? */ + new_pwrst = req_state + 1; + while (!(pwrdm_states & BIT(new_pwrst))) { + if (new_pwrst > PWRDM_POWER_ON) { + WARN(1, "powerdomain: %s: Fix max powerstate to ON\n", + pwrdm->name); + return PWRDM_POWER_ON; + } + + if (new_pwrst == default_pwrst) + break; + new_pwrst++; + } +done: + return new_pwrst; +} + +/** * omap_set_pwrdm_state - change a powerdomain's current power state * @pwrdm: struct powerdomain * to change the power state of * @pwrst: power state to change to diff --git a/arch/arm/mach-omap2/powerdomain.h b/arch/arm/mach-omap2/powerdomain.h index a754c82..11bd4dd 100644 --- a/arch/arm/mach-omap2/powerdomain.h +++ b/arch/arm/mach-omap2/powerdomain.h @@ -220,6 +220,9 @@ struct voltagedomain *pwrdm_get_voltdm(struct powerdomain *pwrdm); int pwrdm_get_mem_bank_count(struct powerdomain *pwrdm); +u8 pwrdm_get_valid_lp_state(struct powerdomain *pwrdm, + bool is_logic_state, u8 req_state); + int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst); int pwrdm_read_next_pwrst(struct powerdomain *pwrdm); int pwrdm_read_pwrst(struct powerdomain *pwrdm); -- cgit v0.10.2 From 46ba55265254e8f47f8c2af6408841f31bab4870 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Thu, 5 Jun 2014 21:40:39 -0500 Subject: ARM: OMAP4+: PM: Make logic state programmable Move the logic state as different for each power domain. This allows us to customize the deepest power state we should target over all for each powerdomain in the follow on patches. Signed-off-by: Nishanth Menon Reviewed-by: Kevin Hilman Acked-by: Santosh Shilimkar diff --git a/arch/arm/mach-omap2/pm44xx.c b/arch/arm/mach-omap2/pm44xx.c index 0dda6cf..b377b03 100644 --- a/arch/arm/mach-omap2/pm44xx.c +++ b/arch/arm/mach-omap2/pm44xx.c @@ -29,6 +29,7 @@ u16 pm44xx_errata; struct power_state { struct powerdomain *pwrdm; u32 next_state; + u32 next_logic_state; #ifdef CONFIG_SUSPEND u32 saved_state; u32 saved_logic_state; @@ -54,7 +55,7 @@ static int omap4_pm_suspend(void) /* Set targeted power domain states by suspend */ list_for_each_entry(pwrst, &pwrst_list, node) { omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state); - pwrdm_set_logic_retst(pwrst->pwrdm, PWRDM_POWER_OFF); + pwrdm_set_logic_retst(pwrst->pwrdm, pwrst->next_logic_state); } /* @@ -121,6 +122,8 @@ static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused) pwrst->pwrdm = pwrdm; pwrst->next_state = PWRDM_POWER_RET; + pwrst->next_logic_state = PWRDM_POWER_OFF; + list_add(&pwrst->node, &pwrst_list); return omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state); -- cgit v0.10.2 From bd7593c69af8f610567fd6b105c440cfe9da7661 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Fri, 6 Jun 2014 01:17:37 -0500 Subject: ARM: OMAP4+: PM: use only valid low power state for suspend We are using power domain state as RET and logic state as OFF. This state is OSWR. This may not always be supported on ALL power domains. In fact, on certain power domains, this might result in a hang on certain platforms. Instead, depend on powerdomain data to provide accurate information about the supported powerdomain states and use the appropriate function to query and use it as part of suspend path. Signed-off-by: Nishanth Menon Reviewed-by: Kevin Hilman Acked-by: Santosh Shilimkar diff --git a/arch/arm/mach-omap2/pm44xx.c b/arch/arm/mach-omap2/pm44xx.c index b377b03..0bfce38 100644 --- a/arch/arm/mach-omap2/pm44xx.c +++ b/arch/arm/mach-omap2/pm44xx.c @@ -121,8 +121,10 @@ static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused) return -ENOMEM; pwrst->pwrdm = pwrdm; - pwrst->next_state = PWRDM_POWER_RET; - pwrst->next_logic_state = PWRDM_POWER_OFF; + pwrst->next_state = pwrdm_get_valid_lp_state(pwrdm, false, + PWRDM_POWER_RET); + pwrst->next_logic_state = pwrdm_get_valid_lp_state(pwrdm, true, + PWRDM_POWER_OFF); list_add(&pwrst->node, &pwrst_list); -- cgit v0.10.2 From 3e6a1c945950140926dd6e2cc667893de0a7fe3b Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Thu, 24 Jul 2014 10:24:19 -0500 Subject: ARM: OMAP4+: PM: Use only valid low power state for CPU hotplug Not all SoCs support OFF mode - for example DRA74/72. So, use valid power state during CPU hotplug. Signed-off-by: Nishanth Menon Reviewed-by: Kevin Hilman Acked-by: Santosh Shilimkar diff --git a/arch/arm/mach-omap2/omap-mpuss-lowpower.c b/arch/arm/mach-omap2/omap-mpuss-lowpower.c index 4001325..e9cdacf 100644 --- a/arch/arm/mach-omap2/omap-mpuss-lowpower.c +++ b/arch/arm/mach-omap2/omap-mpuss-lowpower.c @@ -298,6 +298,10 @@ int omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state) if (omap_rev() == OMAP4430_REV_ES1_0) return -ENXIO; + /* Use the achievable power state for the domain */ + power_state = pwrdm_get_valid_lp_state(pm_info->pwrdm, + false, power_state); + if (power_state == PWRDM_POWER_OFF) cpu_state = 1; -- cgit v0.10.2 From e9e0da3323c3bb5adad640018445df701156e13e Mon Sep 17 00:00:00 2001 From: Andrew Lunn Date: Sat, 30 Aug 2014 18:46:06 +0200 Subject: cpuidle: kirkwood: Remove ARCH_KIRKWOOD dependency mach-kirkwood has been removed, now that kirkwood lives in mach-mvebu. Use MACH_KIRKWOOD, which is set when kirkwood is built as part of mach-mvebu. Signed-off-by: Andrew Lunn Cc: Daniel Lezcano Cc: Rafael J. Wysocki Cc: linux-pm@vger.kernel.org Acked-by: Daniel Lezcano Acked-by: Rafael J. Wysocki Link: https://lkml.kernel.org/r/1409417172-6846-2-git-send-email-andrew@lunn.ch Signed-off-by: Jason Cooper diff --git a/drivers/cpuidle/Kconfig.arm b/drivers/cpuidle/Kconfig.arm index 38cff69..58bcd0d 100644 --- a/drivers/cpuidle/Kconfig.arm +++ b/drivers/cpuidle/Kconfig.arm @@ -28,7 +28,7 @@ config ARM_HIGHBANK_CPUIDLE config ARM_KIRKWOOD_CPUIDLE bool "CPU Idle Driver for Marvell Kirkwood SoCs" - depends on ARCH_KIRKWOOD || MACH_KIRKWOOD + depends on MACH_KIRKWOOD help This adds the CPU Idle driver for Marvell Kirkwood SoCs. -- cgit v0.10.2 From 4efded056ec03b5b1b2d494588514edab2528757 Mon Sep 17 00:00:00 2001 From: Andrew Lunn Date: Sat, 30 Aug 2014 18:46:07 +0200 Subject: ata: Remove ARCH_KIRKWOOD dependency mach-kirkwood has been removed, now that kirkwood lives in mach-mvebu. ARCH_MVEBU is sufficient. Signed-off-by: Andrew Lunn Cc: Tejun Heo Cc: linux-ide@vger.kernel.org Acked-by: Tejun Heo Link: https://lkml.kernel.org/r/1409417172-6846-3-git-send-email-andrew@lunn.ch Signed-off-by: Jason Cooper diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig index e1b9278..cd4cccb 100644 --- a/drivers/ata/Kconfig +++ b/drivers/ata/Kconfig @@ -299,7 +299,7 @@ config SATA_HIGHBANK config SATA_MV tristate "Marvell SATA support" - depends on PCI || ARCH_DOVE || ARCH_KIRKWOOD || ARCH_MV78XX0 || \ + depends on PCI || ARCH_DOVE || ARCH_MV78XX0 || \ ARCH_MVEBU || ARCH_ORION5X || COMPILE_TEST select GENERIC_PHY help -- cgit v0.10.2 From 575be653f887601d3f656f7e951e34ecf66da5ec Mon Sep 17 00:00:00 2001 From: Andrew Lunn Date: Sat, 30 Aug 2014 18:46:08 +0200 Subject: thermal: Remove ARCH_KIRKWOOD dependency mach-kirkwood has been removed, now that kirkwood lives in mach-mvebu. Depend on MACH_KIRKWOOD, which will be set when kirkwood is built as part of ARCH_MVEBU. Signed-off-by: Andrew Lunn Cc: Zhang Rui Cc: linux-pm@vger.kernel.org Acked-by: Eduardo Valentin Link: https://lkml.kernel.org/r/1409417172-6846-4-git-send-email-andrew@lunn.ch Signed-off-by: Jason Cooper diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig index 693208e..ef5587f 100644 --- a/drivers/thermal/Kconfig +++ b/drivers/thermal/Kconfig @@ -143,7 +143,7 @@ config RCAR_THERMAL config KIRKWOOD_THERMAL tristate "Temperature sensor on Marvell Kirkwood SoCs" - depends on ARCH_KIRKWOOD || MACH_KIRKWOOD + depends on MACH_KIRKWOOD depends on OF help Support for the Kirkwood thermal sensor driver into the Linux thermal -- cgit v0.10.2 From 1093d8cac46f9a40d2b4d6d20657e7970640a59b Mon Sep 17 00:00:00 2001 From: Andrew Lunn Date: Sat, 30 Aug 2014 18:46:09 +0200 Subject: leds: Remove ARCH_KIRKWOOD dependency mach-kirkwood has been removed, now that kirkwood lives in mach-mvebu. Use MACH_KIRKWOOD which will be set when kirkwood is built as part of mach-mvebu. Signed-off-by: Andrew Lunn Acked-by: Bryan Wu Cc: Richard Purdie Cc: linux-leds@vger.kernel.org Link: https://lkml.kernel.org/r/1409417172-6846-5-git-send-email-andrew@lunn.ch Signed-off-by: Jason Cooper diff --git a/drivers/leds/Kconfig b/drivers/leds/Kconfig index 8c96e2d..f6ef7bb 100644 --- a/drivers/leds/Kconfig +++ b/drivers/leds/Kconfig @@ -410,7 +410,7 @@ config LEDS_MC13783 config LEDS_NS2 tristate "LED support for Network Space v2 GPIO LEDs" depends on LEDS_CLASS - depends on ARCH_KIRKWOOD || MACH_KIRKWOOD + depends on MACH_KIRKWOOD default y help This option enable support for the dual-GPIO LED found on the @@ -420,7 +420,7 @@ config LEDS_NS2 config LEDS_NETXBIG tristate "LED support for Big Network series LEDs" depends on LEDS_CLASS - depends on ARCH_KIRKWOOD || MACH_KIRKWOOD + depends on MACH_KIRKWOOD default y help This option enable support for LEDs found on the LaCie 2Big -- cgit v0.10.2 From ace2c0205b1bae2c3d1ea0932a1e45494938005a Mon Sep 17 00:00:00 2001 From: Andrew Lunn Date: Sat, 30 Aug 2014 18:46:10 +0200 Subject: rtc: Remove ARCH_KIRKWOOD dependency mach-kirkwood has been removed, now that kirkwood lives in mach-mvebu. ARCH_MVEBU is sufficient. Signed-off-by: Andrew Lunn Cc: Alessandro Zummo Cc: rtc-linux@googlegroups.com Link: https://lkml.kernel.org/r/1409417172-6846-6-git-send-email-andrew@lunn.ch Signed-off-by: Jason Cooper diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig index a168e96..fae9464 100644 --- a/drivers/rtc/Kconfig +++ b/drivers/rtc/Kconfig @@ -1198,7 +1198,7 @@ config RTC_DRV_TX4939 config RTC_DRV_MV tristate "Marvell SoC RTC" - depends on ARCH_KIRKWOOD || ARCH_DOVE || ARCH_MVEBU + depends on ARCH_DOVE || ARCH_MVEBU help If you say yes here you will get support for the in-chip RTC that can be found in some of Marvell's SoC devices, such as -- cgit v0.10.2 From 6da4161355bb02876f9123857990f049959c8d7b Mon Sep 17 00:00:00 2001 From: Andrew Lunn Date: Sat, 30 Aug 2014 18:46:11 +0200 Subject: watchdog: Remove ARCH_KIRKWOOD dependency mach-kirkwood has been removed, now that kirkwood lives in mach-mvebu. ARCH_MVEBU is sufficient. Signed-off-by: Andrew Lunn Cc: Wim Van Sebroeck Cc: linux-watchdog@vger.kernel.org Link: https://lkml.kernel.org/r/1409417172-6846-7-git-send-email-andrew@lunn.ch Signed-off-by: Jason Cooper diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index f57312f..1d1330a 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -301,7 +301,7 @@ config DAVINCI_WATCHDOG config ORION_WATCHDOG tristate "Orion watchdog" - depends on ARCH_ORION5X || ARCH_KIRKWOOD || ARCH_DOVE || MACH_DOVE || ARCH_MVEBU + depends on ARCH_ORION5X || ARCH_DOVE || MACH_DOVE || ARCH_MVEBU select WATCHDOG_CORE help Say Y here if to include support for the watchdog timer -- cgit v0.10.2 From 6c8df11ddc3af738c4230100d2de89a02a20cb22 Mon Sep 17 00:00:00 2001 From: Andrew Lunn Date: Sat, 30 Aug 2014 18:46:12 +0200 Subject: cpufreq: Remove ARCH_KIRKWOOD dependency mach-kirkwood has been removed, now that kirkwood lives in mach-mvebu. ARCH_MVEBU is sufficient. Signed-off-by: Andrew Lunn Cc: "Rafael J. Wysocki" Cc: Viresh Kumar Acked-by: Viresh Kumar Acked-by: "Rafael J. Wysocki" Link: https://lkml.kernel.org/r/1409417172-6846-8-git-send-email-andrew@lunn.ch Signed-off-by: Jason Cooper diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm index 7364a53..8c5cf4b 100644 --- a/drivers/cpufreq/Kconfig.arm +++ b/drivers/cpufreq/Kconfig.arm @@ -119,7 +119,7 @@ config ARM_INTEGRATOR If in doubt, say Y. config ARM_KIRKWOOD_CPUFREQ - def_bool ARCH_KIRKWOOD || MACH_KIRKWOOD + def_bool MACH_KIRKWOOD help This adds the CPUFreq driver for Marvell Kirkwood SoCs. -- cgit v0.10.2 From 225b94cdf719d0bc522a354bdafc18e5da5ff83b Mon Sep 17 00:00:00 2001 From: Arnaud Ebalard Date: Sat, 6 Sep 2014 22:49:25 +0200 Subject: ARM: mvebu: Netgear RN104: Use Hardware BCH ECC The bootloader on the Netgear ReadyNAS RN104 uses Hardware BCH ECC (strength = 4), while the pxa3xx NAND driver by default uses Hamming ECC (strength = 1). This patch changes the ECC mode on these machines to match that of the bootloader and of the stock firmware. That way, it is now possible to update the kernel from userland (e.g. using standard tools from mtd-utils package); u-boot will happily load and boot it. The issue was initially reported and fixed by Ben Pedell for RN102. The RN104 shares the same Hynix H27U1G8F2BTR NAND flash and setup. This patch is based on Ben's fix for RN102. Fixes: 0373a558bd79 ("ARM: mvebu: Enable NAND controller in ReadyNAS 104 .dts file") Cc: # v3.14+ Signed-off-by: Arnaud Ebalard Link: https://lkml.kernel.org/r/920c7e7169dc6aaaa3eb4bced2336d38e77b8864.1410035142.git.arno@natisbad.org Signed-off-by: Jason Cooper diff --git a/arch/arm/boot/dts/armada-370-netgear-rn104.dts b/arch/arm/boot/dts/armada-370-netgear-rn104.dts index c5fe8b5..4ec1ce5 100644 --- a/arch/arm/boot/dts/armada-370-netgear-rn104.dts +++ b/arch/arm/boot/dts/armada-370-netgear-rn104.dts @@ -145,6 +145,10 @@ marvell,nand-enable-arbiter; nand-on-flash-bbt; + /* Use Hardware BCH ECC */ + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; + partition@0 { label = "u-boot"; reg = <0x0000000 0x180000>; /* 1.5MB */ -- cgit v0.10.2 From 500abb6ccb9e3f8d638a7f422443a8549245ef90 Mon Sep 17 00:00:00 2001 From: Arnaud Ebalard Date: Sat, 6 Sep 2014 22:49:38 +0200 Subject: ARM: mvebu: Netgear RN2120: Use Hardware BCH ECC The bootloader on the Netgear ReadyNAS RN2120 uses Hardware BCH ECC (strength = 4), while the pxa3xx NAND driver by default uses Hamming ECC (strength = 1). This patch changes the ECC mode on these machines to match that of the bootloader and of the stock firmware. That way, it is now possible to update the kernel from userland (e.g. using standard tools from mtd-utils package); u-boot will happily load and boot it. The issue was initially reported and fixed by Ben Pedell for RN102. The RN2120 shares the same Hynix H27U1G8F2BTR NAND flash and setup. This patch is based on Ben's fix for RN102. Fixes: ad51eddd95ad ("ARM: mvebu: Enable NAND controller in ReadyNAS 2120 .dts file") Cc: # v3.14+ Signed-off-by: Arnaud Ebalard Link: https://lkml.kernel.org/r/61f6a1b7ad0adc57a0e201b9680bc2e5f214a317.1410035142.git.arno@natisbad.org Signed-off-by: Jason Cooper diff --git a/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts b/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts index 0cf999a..c5ed85a 100644 --- a/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts +++ b/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts @@ -223,6 +223,10 @@ marvell,nand-enable-arbiter; nand-on-flash-bbt; + /* Use Hardware BCH ECC */ + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; + partition@0 { label = "u-boot"; reg = <0x0000000 0x180000>; /* 1.5MB */ -- cgit v0.10.2 From 01100c022df5d9b8ac56d3705e33e69dc012a6e2 Mon Sep 17 00:00:00 2001 From: Roland Stigge Date: Tue, 9 Sep 2014 15:13:14 +0200 Subject: ARM: LPC32xx: Fix reset function In the recent change to the reset function API (commit 7b6d864b48d95e6ea1df7df64475b9cb9616dcf9), the mode argument changed from a char to an enum. lpc23xx_restart() only handles REBOOT_SOFT and REBOOT_HARD, but the new kernel code emits REBOOT_COLD (0) on reboots now which leads to lpc32xx simply not rebooting (but halting). This patch fixes this by just resetting unconditionally as on other platforms (e.g. mach-bcm2835). Pulling lpc32xx_watchdog_reset() into lpc23xx_restart() since the while() in lpc23xx_restart() is part of the procedure anyway and lpc32xx_watchdog_reset() isn't used anywhere else anymore. Signed-off-by: Roland Stigge diff --git a/arch/arm/mach-lpc32xx/common.c b/arch/arm/mach-lpc32xx/common.c index de03620..716e83e 100644 --- a/arch/arm/mach-lpc32xx/common.c +++ b/arch/arm/mach-lpc32xx/common.c @@ -57,20 +57,6 @@ int clk_is_sysclk_mainosc(void) } /* - * System reset via the watchdog timer - */ -static void lpc32xx_watchdog_reset(void) -{ - /* Make sure WDT clocks are enabled */ - __raw_writel(LPC32XX_CLKPWR_PWMCLK_WDOG_EN, - LPC32XX_CLKPWR_TIMER_CLK_CTRL); - - /* Instant assert of RESETOUT_N with pulse length 1mS */ - __raw_writel(13000, io_p2v(LPC32XX_WDTIM_BASE + 0x18)); - __raw_writel(0x70, io_p2v(LPC32XX_WDTIM_BASE + 0xC)); -} - -/* * Detects and returns IRAM size for the device variation */ #define LPC32XX_IRAM_BANK_SIZE SZ_128K @@ -210,16 +196,13 @@ void __init lpc32xx_map_io(void) void lpc23xx_restart(enum reboot_mode mode, const char *cmd) { - switch (mode) { - case REBOOT_SOFT: - case REBOOT_HARD: - lpc32xx_watchdog_reset(); - break; + /* Make sure WDT clocks are enabled */ + __raw_writel(LPC32XX_CLKPWR_PWMCLK_WDOG_EN, + LPC32XX_CLKPWR_TIMER_CLK_CTRL); - default: - /* Do nothing */ - break; - } + /* Instant assert of RESETOUT_N with pulse length 1mS */ + __raw_writel(13000, io_p2v(LPC32XX_WDTIM_BASE + 0x18)); + __raw_writel(0x70, io_p2v(LPC32XX_WDTIM_BASE + 0xC)); /* Wait for watchdog to reset system */ while (1) -- cgit v0.10.2 From 58cda01ed18945c17ad858dfcf4a9a74ba70157c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Thu, 11 Sep 2014 21:29:01 +0200 Subject: ARM: omap2: make arrays containing machine compatible strings const MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The definition static const char *omap3_boards_compat[] __initconst = { defines a changable array of constant strings. That is you must not do: *omap3_boards_compat[0] = 'f'; but omap3_boards_compat[0] = "another string"; is fine. So the annotation __initconst is wrong and yields a compiler error when other really const variables are added with __initconst. As the struct machine_desc member dt_compat is declared as const char *const *dt_compat; making the arrays const is the better alternative over changing all annotations to __initdata. Signed-off-by: Uwe Kleine-König Signed-off-by: Tony Lindgren diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c index 9480997..04eaccf 100644 --- a/arch/arm/mach-omap2/board-generic.c +++ b/arch/arm/mach-omap2/board-generic.c @@ -43,7 +43,7 @@ static void __init omap_generic_init(void) } #ifdef CONFIG_SOC_OMAP2420 -static const char *omap242x_boards_compat[] __initconst = { +static const char *const omap242x_boards_compat[] __initconst = { "ti,omap2420", NULL, }; @@ -62,7 +62,7 @@ MACHINE_END #endif #ifdef CONFIG_SOC_OMAP2430 -static const char *omap243x_boards_compat[] __initconst = { +static const char *const omap243x_boards_compat[] __initconst = { "ti,omap2430", NULL, }; @@ -81,7 +81,7 @@ MACHINE_END #endif #ifdef CONFIG_ARCH_OMAP3 -static const char *omap3_boards_compat[] __initconst = { +static const char *const omap3_boards_compat[] __initconst = { "ti,omap3430", "ti,omap3", NULL, @@ -100,7 +100,7 @@ DT_MACHINE_START(OMAP3_DT, "Generic OMAP3 (Flattened Device Tree)") .restart = omap3xxx_restart, MACHINE_END -static const char *omap36xx_boards_compat[] __initconst = { +static const char *const omap36xx_boards_compat[] __initconst = { "ti,omap36xx", NULL, }; @@ -118,7 +118,7 @@ DT_MACHINE_START(OMAP36XX_DT, "Generic OMAP36xx (Flattened Device Tree)") .restart = omap3xxx_restart, MACHINE_END -static const char *omap3_gp_boards_compat[] __initconst = { +static const char *const omap3_gp_boards_compat[] __initconst = { "ti,omap3-beagle", "timll,omap3-devkit8000", NULL, @@ -137,7 +137,7 @@ DT_MACHINE_START(OMAP3_GP_DT, "Generic OMAP3-GP (Flattened Device Tree)") .restart = omap3xxx_restart, MACHINE_END -static const char *am3517_boards_compat[] __initconst = { +static const char *const am3517_boards_compat[] __initconst = { "ti,am3517", NULL, }; @@ -157,7 +157,7 @@ MACHINE_END #endif #ifdef CONFIG_SOC_AM33XX -static const char *am33xx_boards_compat[] __initconst = { +static const char *const am33xx_boards_compat[] __initconst = { "ti,am33xx", NULL, }; @@ -177,7 +177,7 @@ MACHINE_END #endif #ifdef CONFIG_ARCH_OMAP4 -static const char *omap4_boards_compat[] __initconst = { +static const char *const omap4_boards_compat[] __initconst = { "ti,omap4460", "ti,omap4430", "ti,omap4", @@ -199,7 +199,7 @@ MACHINE_END #endif #ifdef CONFIG_SOC_OMAP5 -static const char *omap5_boards_compat[] __initconst = { +static const char *const omap5_boards_compat[] __initconst = { "ti,omap5432", "ti,omap5430", "ti,omap5", @@ -221,7 +221,7 @@ MACHINE_END #endif #ifdef CONFIG_SOC_AM43XX -static const char *am43_boards_compat[] __initconst = { +static const char *const am43_boards_compat[] __initconst = { "ti,am4372", "ti,am43", NULL, @@ -240,7 +240,7 @@ MACHINE_END #endif #ifdef CONFIG_SOC_DRA7XX -static const char *dra74x_boards_compat[] __initconst = { +static const char *const dra74x_boards_compat[] __initconst = { "ti,dra742", "ti,dra7", NULL, @@ -259,7 +259,7 @@ DT_MACHINE_START(DRA74X_DT, "Generic DRA74X (Flattened Device Tree)") .restart = omap44xx_restart, MACHINE_END -static const char *dra72x_boards_compat[] __initconst = { +static const char *const dra72x_boards_compat[] __initconst = { "ti,dra722", NULL, }; -- cgit v0.10.2 From 31957609db529d401658adc2e91ef7df7ea42699 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Wed, 10 Sep 2014 10:26:17 +0200 Subject: ARM: OMAP2+: make of_device_ids const MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit of_device_ids (i.e. compatible strings and the respective data) are not supposed to change at runtime. All functions working with of_device_ids provided by work with const of_device_ids. So mark the non-const function parameters and structs for OMAP2+ as const, too. Signed-off-by: Uwe Kleine-König Signed-off-by: Tony Lindgren diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c index 04eaccf..0b311d5 100644 --- a/arch/arm/mach-omap2/board-generic.c +++ b/arch/arm/mach-omap2/board-generic.c @@ -27,7 +27,7 @@ #define gic_of_init NULL #endif -static struct of_device_id omap_dt_match_table[] __initdata = { +static const struct of_device_id omap_dt_match_table[] __initconst = { { .compatible = "simple-bus", }, { .compatible = "ti,omap-infra", }, { } diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h index dc571f1..7966441 100644 --- a/arch/arm/mach-omap2/common.h +++ b/arch/arm/mach-omap2/common.h @@ -307,7 +307,7 @@ static inline void omap4_cpu_resume(void) #endif -void pdata_quirks_init(struct of_device_id *); +void pdata_quirks_init(const struct of_device_id *); void omap_auxdata_legacy_init(struct device *dev); void omap_pcs_legacy_init(int irq, void (*rearm)(void)); diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c index 9f42d54..4b26e5e 100644 --- a/arch/arm/mach-omap2/gpmc.c +++ b/arch/arm/mach-omap2/gpmc.c @@ -1244,7 +1244,7 @@ int gpmc_cs_program_settings(int cs, struct gpmc_settings *p) } #ifdef CONFIG_OF -static struct of_device_id gpmc_dt_ids[] = { +static const struct of_device_id gpmc_dt_ids[] = { { .compatible = "ti,omap2420-gpmc" }, { .compatible = "ti,omap2430-gpmc" }, { .compatible = "ti,omap3430-gpmc" }, /* omap3430 & omap3630 */ diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c index 35b8590..604a976a 100644 --- a/arch/arm/mach-omap2/irq.c +++ b/arch/arm/mach-omap2/irq.c @@ -289,7 +289,7 @@ int __init intc_of_init(struct device_node *node, return 0; } -static struct of_device_id irq_match[] __initdata = { +static const struct of_device_id irq_match[] __initconst = { { .compatible = "ti,omap2-intc", .data = intc_of_init, }, { } }; diff --git a/arch/arm/mach-omap2/pdata-quirks.c b/arch/arm/mach-omap2/pdata-quirks.c index 90c88d4..05a8c8b 100644 --- a/arch/arm/mach-omap2/pdata-quirks.c +++ b/arch/arm/mach-omap2/pdata-quirks.c @@ -405,7 +405,7 @@ static void pdata_quirks_check(struct pdata_init *quirks) } } -void __init pdata_quirks_init(struct of_device_id *omap_dt_match_table) +void __init pdata_quirks_init(const struct of_device_id *omap_dt_match_table) { omap_sdrc_init(NULL, NULL); pdata_quirks_check(auxdata_quirks); diff --git a/arch/arm/mach-omap2/prm_common.c b/arch/arm/mach-omap2/prm_common.c index 76ca320..74054b8 100644 --- a/arch/arm/mach-omap2/prm_common.c +++ b/arch/arm/mach-omap2/prm_common.c @@ -467,7 +467,7 @@ int prm_unregister(struct prm_ll_data *pld) return 0; } -static struct of_device_id omap_prcm_dt_match_table[] = { +static const struct of_device_id omap_prcm_dt_match_table[] = { { .compatible = "ti,am3-prcm" }, { .compatible = "ti,am3-scrm" }, { .compatible = "ti,am4-prcm" }, diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c index 43d03fb..4f61148 100644 --- a/arch/arm/mach-omap2/timer.c +++ b/arch/arm/mach-omap2/timer.c @@ -141,7 +141,7 @@ static struct property device_disabled = { .value = "disabled", }; -static struct of_device_id omap_timer_match[] __initdata = { +static const struct of_device_id omap_timer_match[] __initconst = { { .compatible = "ti,omap2420-timer", }, { .compatible = "ti,omap3430-timer", }, { .compatible = "ti,omap4430-timer", }, @@ -162,7 +162,7 @@ static struct of_device_id omap_timer_match[] __initdata = { * the timer node in device-tree as disabled, to prevent the kernel from * registering this timer as a platform device and so no one else can use it. */ -static struct device_node * __init omap_get_timer_dt(struct of_device_id *match, +static struct device_node * __init omap_get_timer_dt(const struct of_device_id *match, const char *property) { struct device_node *np; @@ -388,7 +388,7 @@ static u64 notrace dmtimer_read_sched_clock(void) return 0; } -static struct of_device_id omap_counter_match[] __initdata = { +static const struct of_device_id omap_counter_match[] __initconst = { { .compatible = "ti,omap-counter32k", }, { } }; -- cgit v0.10.2 From 4f5e01e96d424b54f5f0e89ee1ba9ccca03a3941 Mon Sep 17 00:00:00 2001 From: Andrew Lunn Date: Mon, 1 Sep 2014 19:35:41 +0200 Subject: ARM: Kirkwood: Fix DT based DSA. During the conversion of boards to use DT to instantiate Distributed Switch Architecture, nobody volunteered to test. As to be expected, the conversion was flawed. Testers and access to hardware has now become available, and this patch hopefully fixes the problems. dsa,mii-bus must be a phandle to the top level mdio node, not the port specific subnode of the mdio device. dsa,ethernet must be a phandle to the port subnode within the ethernet DT node, not the ethernet node. Don't pinctrl hog the card detect gpio for mvsdio. Rename the .dts files to make it clearer which file is for the Z0 stepping and which for the A0 or later stepping. Signed-off-by: Andrew Lunn Cc: seugene@marvell.com Tested-by: Eugene Sanivsky Fixes: e2eaa339af44: ("ARM: Kirkwood: convert rd88f6281-setup.c to DT.") Fixes: e7c8f3808be8: ("ARM: kirkwood: Convert mv88f6281gtw_ge switch setup to DT") Cc: #v3.15+ Link: https://lkml.kernel.org/r/1409592941-22244-1-git-send-email-andrew@lunn.ch Signed-off-by: Jason Cooper diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index b8c5cd3..e6aa6e7 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -144,8 +144,8 @@ dtb-$(CONFIG_MACH_KIRKWOOD) += kirkwood-b3.dtb \ kirkwood-openrd-client.dtb \ kirkwood-openrd-ultimate.dtb \ kirkwood-rd88f6192.dtb \ - kirkwood-rd88f6281-a0.dtb \ - kirkwood-rd88f6281-a1.dtb \ + kirkwood-rd88f6281-z0.dtb \ + kirkwood-rd88f6281-a.dtb \ kirkwood-rs212.dtb \ kirkwood-rs409.dtb \ kirkwood-rs411.dtb \ diff --git a/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts b/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts index 8f76d28..f82827d 100644 --- a/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts +++ b/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts @@ -123,11 +123,11 @@ dsa@0 { compatible = "marvell,dsa"; - #address-cells = <2>; + #address-cells = <1>; #size-cells = <0>; - dsa,ethernet = <ð0>; - dsa,mii-bus = <ðphy0>; + dsa,ethernet = <ð0port>; + dsa,mii-bus = <&mdio>; switch@0 { #address-cells = <1>; @@ -169,17 +169,13 @@ &mdio { status = "okay"; - - ethphy0: ethernet-phy@ff { - reg = <0xff>; /* No phy attached */ - speed = <1000>; - duplex = <1>; - }; }; ð0 { status = "okay"; + ethernet0-port@0 { - phy-handle = <ðphy0>; + speed = <1000>; + duplex = <1>; }; }; diff --git a/arch/arm/boot/dts/kirkwood-rd88f6281-a.dts b/arch/arm/boot/dts/kirkwood-rd88f6281-a.dts new file mode 100644 index 0000000..f2e08b3 --- /dev/null +++ b/arch/arm/boot/dts/kirkwood-rd88f6281-a.dts @@ -0,0 +1,43 @@ +/* + * Marvell RD88F6181 A Board descrition + * + * Andrew Lunn + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + * + * This file contains the definitions for the board with the A0 or + * higher stepping of the SoC. The ethernet switch does not have a + * "wan" port. + */ + +/dts-v1/; +#include "kirkwood-rd88f6281.dtsi" + +/ { + model = "Marvell RD88f6281 Reference design, with A0 or higher SoC"; + compatible = "marvell,rd88f6281-a", "marvell,rd88f6281","marvell,kirkwood-88f6281", "marvell,kirkwood"; + + dsa@0 { + switch@0 { + reg = <10 0>; /* MDIO address 10, switch 0 in tree */ + }; + }; +}; + +&mdio { + status = "okay"; + + ethphy1: ethernet-phy@11 { + reg = <11>; + }; +}; + +ð1 { + status = "okay"; + + ethernet1-port@0 { + phy-handle = <ðphy1>; + }; +}; diff --git a/arch/arm/boot/dts/kirkwood-rd88f6281-a0.dts b/arch/arm/boot/dts/kirkwood-rd88f6281-a0.dts deleted file mode 100644 index a803bbb..0000000 --- a/arch/arm/boot/dts/kirkwood-rd88f6281-a0.dts +++ /dev/null @@ -1,26 +0,0 @@ -/* - * Marvell RD88F6181 A0 Board descrition - * - * Andrew Lunn - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - * - * This file contains the definitions for the board with the A0 variant of - * the SoC. The ethernet switch does not have a "wan" port. - */ - -/dts-v1/; -#include "kirkwood-rd88f6281.dtsi" - -/ { - model = "Marvell RD88f6281 Reference design, with A0 SoC"; - compatible = "marvell,rd88f6281-a0", "marvell,rd88f6281","marvell,kirkwood-88f6281", "marvell,kirkwood"; - - dsa@0 { - switch@0 { - reg = <10 0>; /* MDIO address 10, switch 0 in tree */ - }; - }; -}; \ No newline at end of file diff --git a/arch/arm/boot/dts/kirkwood-rd88f6281-a1.dts b/arch/arm/boot/dts/kirkwood-rd88f6281-a1.dts deleted file mode 100644 index baeebbf..0000000 --- a/arch/arm/boot/dts/kirkwood-rd88f6281-a1.dts +++ /dev/null @@ -1,31 +0,0 @@ -/* - * Marvell RD88F6181 A1 Board descrition - * - * Andrew Lunn - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - * - * This file contains the definitions for the board with the A1 variant of - * the SoC. The ethernet switch has a "wan" port. - */ - -/dts-v1/; - -#include "kirkwood-rd88f6281.dtsi" - -/ { - model = "Marvell RD88f6281 Reference design, with A1 SoC"; - compatible = "marvell,rd88f6281-a1", "marvell,rd88f6281","marvell,kirkwood-88f6281", "marvell,kirkwood"; - - dsa@0 { - switch@0 { - reg = <0 0>; /* MDIO address 0, switch 0 in tree */ - port@4 { - reg = <4>; - label = "wan"; - }; - }; - }; -}; \ No newline at end of file diff --git a/arch/arm/boot/dts/kirkwood-rd88f6281-z0.dts b/arch/arm/boot/dts/kirkwood-rd88f6281-z0.dts new file mode 100644 index 0000000..f4272b6 --- /dev/null +++ b/arch/arm/boot/dts/kirkwood-rd88f6281-z0.dts @@ -0,0 +1,35 @@ +/* + * Marvell RD88F6181 Z0 stepping descrition + * + * Andrew Lunn + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + * + * This file contains the definitions for the board using the Z0 + * stepping of the SoC. The ethernet switch has a "wan" port. +*/ + +/dts-v1/; + +#include "kirkwood-rd88f6281.dtsi" + +/ { + model = "Marvell RD88f6281 Reference design, with Z0 SoC"; + compatible = "marvell,rd88f6281-z0", "marvell,rd88f6281","marvell,kirkwood-88f6281", "marvell,kirkwood"; + + dsa@0 { + switch@0 { + reg = <0 0>; /* MDIO address 0, switch 0 in tree */ + port@4 { + reg = <4>; + label = "wan"; + }; + }; + }; +}; + +ð1 { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/kirkwood-rd88f6281.dtsi b/arch/arm/boot/dts/kirkwood-rd88f6281.dtsi index 26cf0e0..d195e88 100644 --- a/arch/arm/boot/dts/kirkwood-rd88f6281.dtsi +++ b/arch/arm/boot/dts/kirkwood-rd88f6281.dtsi @@ -37,7 +37,6 @@ ocp@f1000000 { pinctrl: pin-controller@10000 { - pinctrl-0 = <&pmx_sdio_cd>; pinctrl-names = "default"; pmx_sdio_cd: pmx-sdio-cd { @@ -69,8 +68,8 @@ #address-cells = <2>; #size-cells = <0>; - dsa,ethernet = <ð0>; - dsa,mii-bus = <ðphy1>; + dsa,ethernet = <ð0port>; + dsa,mii-bus = <&mdio>; switch@0 { #address-cells = <1>; @@ -119,35 +118,19 @@ }; partition@300000 { - label = "data"; + label = "rootfs"; reg = <0x0300000 0x500000>; }; }; &mdio { status = "okay"; - - ethphy0: ethernet-phy@0 { - reg = <0>; - }; - - ethphy1: ethernet-phy@ff { - reg = <0xff>; /* No PHY attached */ - speed = <1000>; - duple = <1>; - }; }; ð0 { status = "okay"; ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; - -ð1 { - status = "okay"; - ethernet1-port@0 { - phy-handle = <ðphy1>; + speed = <1000>; + duplex = <1>; }; }; diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi index afc640c..464f09a 100644 --- a/arch/arm/boot/dts/kirkwood.dtsi +++ b/arch/arm/boot/dts/kirkwood.dtsi @@ -309,7 +309,7 @@ marvell,tx-checksum-limit = <1600>; status = "disabled"; - ethernet0-port@0 { + eth0port: ethernet0-port@0 { compatible = "marvell,kirkwood-eth-port"; reg = <0>; interrupts = <11>; @@ -342,7 +342,7 @@ pinctrl-names = "default"; status = "disabled"; - ethernet1-port@0 { + eth1port: ethernet1-port@0 { compatible = "marvell,kirkwood-eth-port"; reg = <0>; interrupts = <15>; -- cgit v0.10.2 From ace8578182dc347b043c0825b9873f62fdaa5b77 Mon Sep 17 00:00:00 2001 From: "klightspeed@killerwolves.net" Date: Wed, 10 Sep 2014 18:55:41 +1000 Subject: ARM: mvebu: Netgear RN102: Use Hardware BCH ECC The bootloader on the Netgear ReadyNAS RN102 uses Hardware BCH ECC (strength = 4), while the pxa3xx NAND driver by default uses Hamming ECC (strength = 1). This patch changes the ECC mode on these machines to match that of the bootloader and of the stock firmware. That way, it is now possible to update the kernel from userland (e.g. using standard tools from mtd-utils package); u-boot will happily load and boot it. Fixes: 92beaccd8b49 ("ARM: mvebu: Enable NAND controller in ReadyNAS 102 .dts file") Cc: #v3.14+ Signed-off-by: Ben Peddell Acked-by: Ezequiel Garcia Tested-by: Arnaud Ebalard Link: https://lkml.kernel.org/r/1410339341-3372-1-git-send-email-klightspeed@killerwolves.net Signed-off-by: Jason Cooper diff --git a/arch/arm/boot/dts/armada-370-netgear-rn102.dts b/arch/arm/boot/dts/armada-370-netgear-rn102.dts index d6d572e..285524f 100644 --- a/arch/arm/boot/dts/armada-370-netgear-rn102.dts +++ b/arch/arm/boot/dts/armada-370-netgear-rn102.dts @@ -143,6 +143,10 @@ marvell,nand-enable-arbiter; nand-on-flash-bbt; + /* Use Hardware BCH ECC */ + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; + partition@0 { label = "u-boot"; reg = <0x0000000 0x180000>; /* 1.5MB */ -- cgit v0.10.2 From b65e0fb3d046cc65d0a3c45d43de351fb363271b Mon Sep 17 00:00:00 2001 From: Andreas Henriksson Date: Tue, 23 Sep 2014 17:12:52 +0200 Subject: ARM: at91: fix at91sam9263ek DT mmc pinmuxing settings As discovered on a custom board similar to at91sam9263ek and basing its devicetree on that one apparently the pin muxing doesn't get set up properly. This was discovered since the custom boards u-boot does funky stuff with the pin muxing and leaved it set to SPI which made the MMC driver not work under Linux. The fix is simply to define the given configuration as the default. This probably worked by pure luck before, but it's better to make the muxing explicitly set. Signed-off-by: Andreas Henriksson Acked-by: Boris Brezillon Signed-off-by: Nicolas Ferre Cc: # 3.11+ diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi index bb23c2d..5e95a80 100644 --- a/arch/arm/boot/dts/at91sam9263.dtsi +++ b/arch/arm/boot/dts/at91sam9263.dtsi @@ -834,6 +834,7 @@ compatible = "atmel,hsmci"; reg = <0xfff80000 0x600>; interrupts = <10 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-names = "default"; #address-cells = <1>; #size-cells = <0>; clocks = <&mci0_clk>; @@ -845,6 +846,7 @@ compatible = "atmel,hsmci"; reg = <0xfff84000 0x600>; interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-names = "default"; #address-cells = <1>; #size-cells = <0>; clocks = <&mci1_clk>; -- cgit v0.10.2 From cfa1950e6c6b72251e80adc736af3c3d2907ab0e Mon Sep 17 00:00:00 2001 From: Ludovic Desroches Date: Mon, 22 Sep 2014 15:51:33 +0200 Subject: ARM: at91/PMC: don't forget to write PMC_PCDR register to disable clocks When introducing support for sama5d3, the write to PMC_PCDR register has been accidentally removed. Reported-by: Nathalie Cyrille Signed-off-by: Ludovic Desroches Signed-off-by: Nicolas Ferre Cc: # 3.10.x and later diff --git a/arch/arm/mach-at91/clock.c b/arch/arm/mach-at91/clock.c index 034529d..d66f102 100644 --- a/arch/arm/mach-at91/clock.c +++ b/arch/arm/mach-at91/clock.c @@ -962,6 +962,7 @@ static int __init at91_clock_reset(void) } at91_pmc_write(AT91_PMC_SCDR, scdr); + at91_pmc_write(AT91_PMC_PCDR, pcdr); if (cpu_is_sama5d3()) at91_pmc_write(AT91_PMC_PCDR1, pcdr1); -- cgit v0.10.2 From 8da5e30289c285025483f14c6923330f224d505c Mon Sep 17 00:00:00 2001 From: Robert Jarzmik Date: Wed, 24 Sep 2014 23:08:00 +0200 Subject: MAINTAINERS: update ARM pxa maintainers Change pxa active maintainers, and remove more busy people. Remove Eric's tree as it is not accessible anymore. Signed-off-by: Robert Jarzmik Acked-by: Daniel Mack Acked-by: Eric Miao Acked-by: Haojian Zhuang Acked-by: Russell King Signed-off-by: Arnd Bergmann diff --git a/MAINTAINERS b/MAINTAINERS index 3a34ec0..210e103 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -7295,12 +7295,12 @@ F: drivers/video/backlight/pwm_bl.c F: include/linux/pwm_backlight.h PXA2xx/PXA3xx SUPPORT -M: Eric Miao -M: Russell King +M: Daniel Mack M: Haojian Zhuang +M: Robert Jarzmik L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) T: git git://github.com/hzhuang1/linux.git -T: git git://git.linaro.org/people/ycmiao/pxa-linux.git +T: git git://github.com/rjarzmik/linux.git S: Maintained F: arch/arm/mach-pxa/ F: drivers/pcmcia/pxa2xx* -- cgit v0.10.2 From 7c1e38769fa448de02ad6b6aa4b499fff4d89842 Mon Sep 17 00:00:00 2001 From: Carlo Caione Date: Fri, 12 Sep 2014 20:18:31 +0200 Subject: MAINTAINERS: Add entry for the Amlogic MesonX SoCs I'm going to maintain the platform. Signed-off-by: Carlo Caione Signed-off-by: Arnd Bergmann diff --git a/MAINTAINERS b/MAINTAINERS index 210e103..63dd79d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -835,6 +835,12 @@ M: Emilio López S: Maintained F: drivers/clk/sunxi/ +ARM/Amlogic MesonX SoC support +M: Carlo Caione +L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) +S: Maintained +N: meson[x68] + ARM/ATMEL AT91RM9200 AND AT91SAM ARM ARCHITECTURES M: Andrew Victor M: Nicolas Ferre -- cgit v0.10.2 From b125170a39ea35fe5ef93c894940feb6cf08ebd3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Krzysztof=20Ha=C5=82asa?= Date: Tue, 16 Sep 2014 12:35:10 +0200 Subject: CNS3xxx: Fix debug UART. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit UARTs on CNS3xxx are 8250-compatible, not AMBA. The base address for UART0 is 0x78000000 (physical) and 0xfb002000 (virtual). Signed-off-by: Krzysztof Hałasa Signed-off-by: Arnd Bergmann diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug index b11ad54..6a5b496 100644 --- a/arch/arm/Kconfig.debug +++ b/arch/arm/Kconfig.debug @@ -147,7 +147,7 @@ choice config DEBUG_CNS3XXX bool "Kernel Kernel low-level debugging on Cavium Networks CNS3xxx" depends on ARCH_CNS3XXX - select DEBUG_UART_PL01X + select DEBUG_UART_8250 help Say Y here if you want the debug print routines to direct their output to the CNS3xxx UART0. @@ -1068,7 +1068,7 @@ config DEBUG_UART_PHYS default 0x02530c00 if DEBUG_KEYSTONE_UART0 default 0x02531000 if DEBUG_KEYSTONE_UART1 default 0x03010fe0 if ARCH_RPC - default 0x10009000 if DEBUG_REALVIEW_STD_PORT || DEBUG_CNS3XXX || \ + default 0x10009000 if DEBUG_REALVIEW_STD_PORT || \ DEBUG_VEXPRESS_UART0_CA9 default 0x1010c000 if DEBUG_REALVIEW_PB1176_PORT default 0x10124000 if DEBUG_RK3X_UART0 @@ -1094,6 +1094,7 @@ config DEBUG_UART_PHYS default 0x50008000 if DEBUG_S3C24XX_UART && (DEBUG_S3C_UART2 || \ DEBUG_S3C2410_UART2) default 0x7c0003f8 if FOOTBRIDGE + default 0x78000000 if DEBUG_CNS3XXX default 0x80070000 if DEBUG_IMX23_UART default 0x80074000 if DEBUG_IMX28_UART default 0x80230000 if DEBUG_PICOXCELL_UART @@ -1133,7 +1134,6 @@ config DEBUG_UART_VIRT default 0xe0010fe0 if ARCH_RPC default 0xe1000000 if DEBUG_MSM_UART default 0xf0000be0 if ARCH_EBSA110 - default 0xf0009000 if DEBUG_CNS3XXX default 0xf01fb000 if DEBUG_NOMADIK_UART default 0xf0201000 if DEBUG_BCM2835 default 0xf1000300 if DEBUG_BCM_5301X @@ -1155,6 +1155,7 @@ config DEBUG_UART_VIRT default 0xf8009000 if DEBUG_VEXPRESS_UART0_CA9 default 0xf8090000 if DEBUG_VEXPRESS_UART0_RS1 default 0xfa71e000 if DEBUG_QCOM_UARTDM + default 0xfb002000 if DEBUG_CNS3XXX default 0xfb009000 if DEBUG_REALVIEW_STD_PORT default 0xfb10c000 if DEBUG_REALVIEW_PB1176_PORT default 0xfd000000 if ARCH_SPEAR3XX || ARCH_SPEAR6XX -- cgit v0.10.2 From defaa4d1dc97320ccc0ea83bc3851443b1c9083a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Krzysztof=20Ha=C5=82asa?= Date: Tue, 16 Sep 2014 12:36:32 +0200 Subject: CNS3xxx: Fix logical PCIe topology. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Without this patch, each root port and the device connected directly to it seem to be located on a shared (virtual) bus #0. It creates problems with enabling devices (the PCI code doesn't know that the root bridge must be enabled in order to access other devices). The PCIe topology shown by lspci doesn't reflect reality, e.g.: 0000:00:00.0 PCI bridge: Cavium Networks Device 3400 0000:00:01.0 PCI bridge: Texas Instruments XIO2001 PCI Express-to-PCI Bridge 0000:02:... 0001:00:00.0 PCI bridge: Cavium Networks Device 3400 (for the second lane/bus) -+-[0001:00]---00.0-[01]-- \-[0000:00]-+-00.0-[01]-- | ^^^^ root bridge \-01.0-[02]----... ^^^^ first external device With this patch, the first external PCIe device is connected to bus #1 (behind the root bridge). -+-[0001:00]---00.0-[01]-- \-[0000:00]---00.0-[01-02]----------00.0-[02]----... ^^^^ root bridge ^^^^ first external device Signed-off-by: Krzysztof Hałasa Signed-off-by: Arnd Bergmann diff --git a/arch/arm/mach-cns3xxx/pcie.c b/arch/arm/mach-cns3xxx/pcie.c index 70fd81e..fbfe852 100644 --- a/arch/arm/mach-cns3xxx/pcie.c +++ b/arch/arm/mach-cns3xxx/pcie.c @@ -60,11 +60,10 @@ static void __iomem *cns3xxx_pci_cfg_base(struct pci_bus *bus, struct cns3xxx_pcie *cnspci = pbus_to_cnspci(bus); int busno = bus->number; int slot = PCI_SLOT(devfn); - int offset; void __iomem *base; /* If there is no link, just show the CNS PCI bridge. */ - if (!cnspci->linked && (busno > 0 || slot > 0)) + if (!cnspci->linked && busno > 0) return NULL; /* @@ -72,22 +71,21 @@ static void __iomem *cns3xxx_pci_cfg_base(struct pci_bus *bus, * we still want to access it. For this to work, we must place * the first device on the same bus as the CNS PCI bridge. */ - if (busno == 0) { /* directly connected PCIe bus */ - switch (slot) { - case 0: /* host bridge device, function 0 only */ + if (busno == 0) { /* internal PCIe bus, host bridge device */ + if (devfn == 0) /* device# and function# are ignored by hw */ base = cnspci->host_regs; - break; - case 1: /* directly connected device */ + else + return NULL; /* no such device */ + + } else if (busno == 1) { /* directly connected PCIe device */ + if (slot == 0) /* device# is ignored by hw */ base = cnspci->cfg0_regs; - break; - default: + else return NULL; /* no such device */ - } } else /* remote PCI bus */ - base = cnspci->cfg1_regs; + base = cnspci->cfg1_regs + ((busno & 0xf) << 20); - offset = ((busno & 0xf) << 20) | (devfn << 12) | (where & 0xffc); - return base + offset; + return base + (where & 0xffc) + (devfn << 12); } static int cns3xxx_pci_read_config(struct pci_bus *bus, unsigned int devfn, @@ -167,7 +165,7 @@ static struct pci_ops cns3xxx_pcie_ops = { static int cns3xxx_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) { struct cns3xxx_pcie *cnspci = pdev_to_cnspci(dev); - int irq = cnspci->irqs[slot]; + int irq = cnspci->irqs[!!dev->bus->number]; pr_info("PCIe map irq: %04d:%02x:%02x.%02x slot %d, pin %d, irq: %d\n", pci_domain_nr(dev->bus), dev->bus->number, PCI_SLOT(dev->devfn), @@ -297,7 +295,8 @@ static void __init cns3xxx_pcie_hw_init(struct cns3xxx_pcie *cnspci) return; /* Set Device Max_Read_Request_Size to 128 byte */ - devfn = PCI_DEVFN(1, 0); + bus.number = 1; /* directly connected PCIe device */ + devfn = PCI_DEVFN(0, 0); pos = pci_bus_find_capability(&bus, devfn, PCI_CAP_ID_EXP); pci_bus_read_config_word(&bus, devfn, pos + PCI_EXP_DEVCTL, &dc); dc &= ~(0x3 << 12); /* Clear Device Control Register [14:12] */ -- cgit v0.10.2 From 367dc4b75f4349d5363bc3ebdc030939db944786 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Krzysztof=20Ha=C5=82asa?= Date: Tue, 16 Sep 2014 12:37:16 +0200 Subject: CNS3xxx: Fix PCIe read size limit. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Max_Read_Request_Size is 3 bits wide, not 2 bits. Also fix the message. Signed-off-by: Krzysztof Hałasa Signed-off-by: Arnd Bergmann diff --git a/arch/arm/mach-cns3xxx/pcie.c b/arch/arm/mach-cns3xxx/pcie.c index fbfe852..45d6bd0 100644 --- a/arch/arm/mach-cns3xxx/pcie.c +++ b/arch/arm/mach-cns3xxx/pcie.c @@ -299,12 +299,15 @@ static void __init cns3xxx_pcie_hw_init(struct cns3xxx_pcie *cnspci) devfn = PCI_DEVFN(0, 0); pos = pci_bus_find_capability(&bus, devfn, PCI_CAP_ID_EXP); pci_bus_read_config_word(&bus, devfn, pos + PCI_EXP_DEVCTL, &dc); - dc &= ~(0x3 << 12); /* Clear Device Control Register [14:12] */ - pci_bus_write_config_word(&bus, devfn, pos + PCI_EXP_DEVCTL, dc); - pci_bus_read_config_word(&bus, devfn, pos + PCI_EXP_DEVCTL, &dc); - if (!(dc & (0x3 << 12))) - pr_info("PCIe: Set Device Max_Read_Request_Size to 128 byte\n"); - + if (dc & PCI_EXP_DEVCTL_READRQ) { + dc &= ~PCI_EXP_DEVCTL_READRQ; + pci_bus_write_config_word(&bus, devfn, pos + PCI_EXP_DEVCTL, dc); + pci_bus_read_config_word(&bus, devfn, pos + PCI_EXP_DEVCTL, &dc); + if (dc & PCI_EXP_DEVCTL_READRQ) + pr_warn("PCIe: Unable to set device Max_Read_Request_Size\n"); + else + pr_info("PCIe: Max_Read_Request_Size set to 128 bytes\n"); + } /* Disable PCIe0 Interrupt Mask INTA to INTD */ __raw_writel(~0x3FFF, MISC_PCIE_INT_MASK(port)); } -- cgit v0.10.2 From f18cf05038729a958732fbcc16730004dc1b84dd Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Fri, 19 Sep 2014 11:17:12 -0700 Subject: MAINTAINERS: add a third maintainer to mach-bcm Add myself as a third maintainer to the mach-bcm code to increase the chances the redundancy in the merging/reviewing process. Signed-off-by: Florian Fainelli Acked-by: Scott Branden Acked-by: Brian Norris Acked-by: Matt Porter Signed-off-by: Arnd Bergmann diff --git a/MAINTAINERS b/MAINTAINERS index 63dd79d..7de4e64 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2009,6 +2009,7 @@ F: drivers/net/ethernet/broadcom/bnx2x/ BROADCOM BCM281XX/BCM11XXX/BCM216XX ARM ARCHITECTURE M: Christian Daudt M: Matt Porter +M: Florian Fainelli L: bcm-kernel-feedback-list@broadcom.com T: git git://github.com/broadcom/mach-bcm S: Maintained -- cgit v0.10.2 From 49dd0dcfd76091989a746968b7403e038a1953bf Mon Sep 17 00:00:00 2001 From: Behan Webster Date: Tue, 23 Sep 2014 20:44:44 -0700 Subject: arm, vt8500, LLVMLlinux: Use mcr instead of mcr% for mach-vt8500 The ASM below does not compile with clang and is not the way that the mcr command is used in other parts of the kernel. arch/arm/mach-vt8500/vt8500.c:72:11: error: invalid % escape in inline assembly string asm("mcr%? p15, 0, %0, c7, c0, 4" : : "r" (0)); ~~~~~^~~~~~~~~~~~~~~~~~~~~~~~ 1 error generated. There are other forms that are supported on different ARM instruction sets but generally the kernel just uses mcr as it is supported in all ARM instruction sets. Signed-off-by: Behan Webster Reviewed-by: Mark Charlebois Acked-by: Will Deacon Acked-by: Tony Prisk Signed-off-by: Arnd Bergmann diff --git a/arch/arm/mach-vt8500/vt8500.c b/arch/arm/mach-vt8500/vt8500.c index 2da7be3..3bc0dc9 100644 --- a/arch/arm/mach-vt8500/vt8500.c +++ b/arch/arm/mach-vt8500/vt8500.c @@ -69,7 +69,7 @@ static void vt8500_power_off(void) { local_irq_disable(); writew(5, pmc_base + VT8500_HCR_REG); - asm("mcr%? p15, 0, %0, c7, c0, 4" : : "r" (0)); + asm("mcr p15, 0, %0, c7, c0, 4" : : "r" (0)); } static void __init vt8500_init(void) -- cgit v0.10.2 From e54951c8585e8e950ac04b15728910cc5a64e612 Mon Sep 17 00:00:00 2001 From: Matthias Brugger Date: Fri, 26 Sep 2014 11:45:55 +0200 Subject: MAINTAINERS: Add maintainers entry for Mediatek SoCs I plan to stay with the Mediatek SoCs for the next future and hope to expand its support along the way with the help of a whole bunch of people. Signed-off-by: Matthias Brugger Signed-off-by: Arnd Bergmann diff --git a/MAINTAINERS b/MAINTAINERS index 7de4e64..4fe9320 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1156,6 +1156,16 @@ W: http://www.digriz.org.uk/ts78xx/kernel S: Maintained F: arch/arm/mach-orion5x/ts78xx-* +ARM/Mediatek SoC support +M: Matthias Brugger +L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) +S: Maintained +F: arch/arm/boot/dts/mt6* +F: arch/arm/boot/dts/mt8* +F: arch/arm/mach-mediatek/ +N: mtk +K: mediatek + ARM/MICREL KS8695 ARCHITECTURE M: Greg Ungerer L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) -- cgit v0.10.2 From 5529c2cdfd87e64c5801bfb9788a89d78de03414 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Krzysztof=20Ha=C5=82asa?= Date: Tue, 30 Sep 2014 10:32:58 +0200 Subject: MAINTAINERS: CNS3xxx and IXP4xx update. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit I'm told Anton Vorontsov can't maintain Cavium Econa CNS3xxx support anymore. Perhaps I can. Also changing my email contact address for IXP4xx. Signed-off-by: Krzysztof Hałasa Signed-off-by: Arnd Bergmann diff --git a/MAINTAINERS b/MAINTAINERS index 4fe9320..f04c8b6 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -867,10 +867,9 @@ S: Maintained F: arch/arm/mach-highbank/ ARM/CAVIUM NETWORKS CNS3XXX MACHINE SUPPORT -M: Anton Vorontsov +M: Krzysztof Halasa S: Maintained F: arch/arm/mach-cns3xxx/ -T: git git://git.infradead.org/users/cbou/linux-cns3xxx.git ARM/CIRRUS LOGIC CLPS711X ARM ARCHITECTURE M: Alexander Shiyan @@ -1059,7 +1058,7 @@ S: Maintained ARM/INTEL IXP4XX ARM ARCHITECTURE M: Imre Kaloz -M: Krzysztof Halasa +M: Krzysztof Halasa L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained F: arch/arm/mach-ixp4xx/ @@ -4787,7 +4786,7 @@ S: Odd fixes F: drivers/dma/iop-adma.c INTEL IXP4XX QMGR, NPE, ETHERNET and HSS SUPPORT -M: Krzysztof Halasa +M: Krzysztof Halasa S: Maintained F: arch/arm/mach-ixp4xx/include/mach/qmgr.h F: arch/arm/mach-ixp4xx/include/mach/npe.h -- cgit v0.10.2 From 554077c54beafc8d5fe46fa42bf36d9322a51855 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Fri, 3 Oct 2014 09:50:32 -0600 Subject: MAINTAINERS: add Alexandre Courbot for Tegra I'd like to propose Alexandre Courbot as an additional Tegra maintainer. He's been working on a variety of Tegra-related code for a while, and is now officially tasked with working on upstream support. Signed-off-by: Stephen Warren Acked-by: Alexandre Courbot Acked-by: Thierry Reding -- v2: * Use Alexandre's full name. * Use a non-NVIDIA email address to avoid Exchange Server patch corruption. Signed-off-by: Arnd Bergmann diff --git a/MAINTAINERS b/MAINTAINERS index f04c8b6..d50de1a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -9010,6 +9010,7 @@ F: drivers/media/rc/ttusbir.c TEGRA ARCHITECTURE SUPPORT M: Stephen Warren M: Thierry Reding +M: Alexandre Courbot L: linux-tegra@vger.kernel.org Q: http://patchwork.ozlabs.org/project/linux-tegra/list/ T: git git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux.git -- cgit v0.10.2 From 356d41422b00fed4bf8622a0721039a18f687fa0 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Fri, 3 Oct 2014 09:50:33 -0600 Subject: MAINTAINERS: condense some Tegra related entries There's little point having specific entries in MAINTAINERS for Tegra drivers that are already covered by the top-level Tegra architecture support entry, and maintained by people listed there. Remove the duplicates. Signed-off-by: Stephen Warren Acked-by: Thierry Reding Signed-off-by: Arnd Bergmann diff --git a/MAINTAINERS b/MAINTAINERS index d50de1a..ed86a56 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -9017,11 +9017,6 @@ T: git git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux.git S: Supported N: [^a-z]tegra -TEGRA ASOC DRIVER -M: Stephen Warren -S: Supported -F: sound/soc/tegra/ - TEGRA CLOCK DRIVER M: Peter De Schrijver M: Prashant Gaikwad @@ -9033,11 +9028,6 @@ M: Laxman Dewangan S: Supported F: drivers/dma/tegra20-apb-dma.c -TEGRA GPIO DRIVER -M: Stephen Warren -S: Supported -F: drivers/gpio/gpio-tegra.c - TEGRA I2C DRIVER M: Laxman Dewangan S: Supported @@ -9054,11 +9044,6 @@ M: Laxman Dewangan S: Supported F: drivers/input/keyboard/tegra-kbc.c -TEGRA PINCTRL DRIVER -M: Stephen Warren -S: Supported -F: drivers/pinctrl/pinctrl-tegra* - TEGRA PWM DRIVER M: Thierry Reding S: Supported -- cgit v0.10.2 From 5df27823b5552e885e02c1ea0d2f52326d7d710c Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Wed, 8 Oct 2014 20:31:29 +0800 Subject: MAINTAINERS: update Shawn's email address My Freescale email address will be gone shortly. Update my email to be the Linaro one. Signed-off-by: Shawn Guo Signed-off-by: Arnd Bergmann diff --git a/MAINTAINERS b/MAINTAINERS index ed86a56..270d4ab 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -969,7 +969,7 @@ F: arch/arm/include/asm/hardware/dec21285.h F: arch/arm/mach-footbridge/ ARM/FREESCALE IMX / MXC ARM ARCHITECTURE -M: Shawn Guo +M: Shawn Guo M: Sascha Hauer L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained -- cgit v0.10.2