From f53e86760e10abbe7ee98a5b3cb270fa6426fcdb Mon Sep 17 00:00:00 2001 From: Robin Getz Date: Sun, 27 Jan 2008 15:38:44 +0800 Subject: [Blackfin] arch: Add a note describing what is going on - no functional changes Signed-off-by: Robin Getz Signed-off-by: Bryan Wu diff --git a/arch/blackfin/mach-common/cplbmgr.S b/arch/blackfin/mach-common/cplbmgr.S index 6f909cb..faca1ab 100644 --- a/arch/blackfin/mach-common/cplbmgr.S +++ b/arch/blackfin/mach-common/cplbmgr.S @@ -75,6 +75,15 @@ ENTRY(_cplb_mgr) * from the configuration table. */ + /* A multi-word instruction can cross a page boundary. This means the + * first part of the instruction can be in a valid page, but the + * second part is not, and hence generates the instruction miss. + * However, the fault address is for the start of the instruction, + * not the part that's in the bad page. Therefore, we have to check + * whether the fault address applies to a page that is already present + * in the table. + */ + P4.L = LO(ICPLB_FAULT_ADDR); P4.H = HI(ICPLB_FAULT_ADDR); @@ -87,7 +96,7 @@ ENTRY(_cplb_mgr) R4 = [P4]; /* Get faulting address*/ R6 = 64; /* Advance past the fault address, which*/ R6 = R6 + R4; /* we'll use if we find a match*/ - R3 = ((16 << 8) | 2); /* Extract mask, bits 16 and 17.*/ + R3 = ((16 << 8) | 2); /* Extract mask, two bits at posn 16 */ R5 = 0; .Lisearch: @@ -125,7 +134,9 @@ ENTRY(_cplb_mgr) P4.L = LO(IMEM_CONTROL); P4.H = HI(IMEM_CONTROL); - /* disable cplbs */ + /* Turn off CPLBs while we work, necessary according to HRM before + * modifying CPLB descriptors + */ R5 = [P4]; /* Control Register*/ BITCLR(R5,ENICPLB_P); CLI R1; -- cgit v0.10.2 From 13fe24f37df20e580a5a364e67ec8cf3219d8f8c Mon Sep 17 00:00:00 2001 From: Robin Getz Date: Sun, 27 Jan 2008 15:38:56 +0800 Subject: [Blackfin] arch: fix bug - trap_tests fails to recover on some tests. http://blackfin.uclinux.org/gf/project/uclinux-dist/tracker/?action=TrackerItemEdit&tracker_item_id=3719 When the CPLBs get a miss, we do: - find a victim in the HW table - remove the victim - find the replacement in the software table - put it into the HW table. If we can't find a replacement in the software table, we accidently leave a duplicate in the HW table. This patch ensures that duplicate is marked as not valid. What we should do is find the replacement in the software table, before we find a victim in the HW table - but its too late in the release cycle to do that much restructuring of this code. Rather that duplicate code, connect Hardware Errors (irq5) into trap_c, so user space processes get killed properly. The rest of irq_panic() can be moved into traps.c (later) There is still a small corner case that causes problems when a pheriperal interrupt goes off a single cycle before a user space hardware error. This causes a kernel panic, rather than the user space process being killed. But, this checkin makes things work in 99.9% of the cases, and is a vast improvement from what is there today (which fails 100% of the time). Signed-off-by: Robin Getz Signed-off-by: Bryan Wu diff --git a/arch/blackfin/kernel/traps.c b/arch/blackfin/kernel/traps.c index 21a55ef..4be5ff0b 100644 --- a/arch/blackfin/kernel/traps.c +++ b/arch/blackfin/kernel/traps.c @@ -433,6 +433,36 @@ asmlinkage void trap_c(struct pt_regs *fp) /* 0x3D - Reserved, Caught by default */ /* 0x3E - Reserved, Caught by default */ /* 0x3F - Reserved, Caught by default */ + case VEC_HWERR: + info.si_code = BUS_ADRALN; + sig = SIGBUS; + switch (fp->seqstat & SEQSTAT_HWERRCAUSE) { + /* System MMR Error */ + case (SEQSTAT_HWERRCAUSE_SYSTEM_MMR): + info.si_code = BUS_ADRALN; + sig = SIGBUS; + printk(KERN_NOTICE HWC_x2(KERN_NOTICE)); + break; + /* External Memory Addressing Error */ + case (SEQSTAT_HWERRCAUSE_EXTERN_ADDR): + info.si_code = BUS_ADRERR; + sig = SIGBUS; + printk(KERN_NOTICE HWC_x3(KERN_NOTICE)); + break; + /* Performance Monitor Overflow */ + case (SEQSTAT_HWERRCAUSE_PERF_FLOW): + printk(KERN_NOTICE HWC_x12(KERN_NOTICE)); + break; + /* RAISE 5 instruction */ + case (SEQSTAT_HWERRCAUSE_RAISE_5): + printk(KERN_NOTICE HWC_x18(KERN_NOTICE)); + break; + default: /* Reserved */ + printk(KERN_NOTICE HWC_default(KERN_NOTICE)); + break; + } + CHK_DEBUGGER_TRAP(); + break; default: info.si_code = TRAP_ILLTRAP; sig = SIGTRAP; @@ -447,7 +477,11 @@ asmlinkage void trap_c(struct pt_regs *fp) if (sig != SIGTRAP) { unsigned long stack; dump_bfin_process(fp); - dump_bfin_mem((void *)fp->retx); + /* Is it an interrupt, or an exception? */ + if (trapnr == VEC_HWERR) + dump_bfin_mem((void *)fp->pc); + else + dump_bfin_mem((void *)fp->retx); show_regs(fp); /* Print out the trace buffer if it makes sense */ @@ -672,12 +706,11 @@ void dump_bfin_mem(void *retaddr) * context, which should mean an oops is happening */ if (oops_in_progress && x >= 0x0040 && x <= 0x0047 && i <= 0) - panic("\n\nWARNING : You should reconfigure" + printk(KERN_EMERG "\n" + KERN_EMERG "WARNING : You should reconfigure" " the kernel to turn on\n" - " 'Hardware error interrupt" - " debugging'\n" - " The rest of this error" - " is meanless\n"); + KERN_EMERG " 'Hardware error interrupt debugging'\n" + KERN_EMERG " The rest of this error is meanless\n"); #endif if (i == (unsigned int)retaddr) printk("[%04x]", x); @@ -698,6 +731,10 @@ void show_regs(struct pt_regs *fp) printk(KERN_NOTICE "\n" KERN_NOTICE "SEQUENCER STATUS:\n"); printk(KERN_NOTICE " SEQSTAT: %08lx IPEND: %04lx SYSCFG: %04lx\n", (long)fp->seqstat, fp->ipend, fp->syscfg); + printk(KERN_NOTICE " HWERRCAUSE: 0x%lx\n", + (fp->seqstat & SEQSTAT_HWERRCAUSE) >> 14); + printk(KERN_NOTICE " EXCAUSE : 0x%lx\n", + fp->seqstat & SEQSTAT_EXCAUSE); decode_address(buf, fp->rete); printk(KERN_NOTICE " RETE: %s\n", buf); @@ -708,9 +745,10 @@ void show_regs(struct pt_regs *fp) decode_address(buf, fp->rets); printk(KERN_NOTICE " RETS: %s\n", buf); decode_address(buf, fp->pc); - printk(KERN_NOTICE " PC: %s\n", buf); + printk(KERN_NOTICE " PC : %s\n", buf); - if ((long)fp->seqstat & SEQSTAT_EXCAUSE) { + if (((long)fp->seqstat & SEQSTAT_EXCAUSE) && + (((long)fp->seqstat & SEQSTAT_EXCAUSE) != VEC_HWERR)) { decode_address(buf, bfin_read_DCPLB_FAULT_ADDR()); printk(KERN_NOTICE "DCPLB_FAULT_ADDR: %s\n", buf); decode_address(buf, bfin_read_ICPLB_FAULT_ADDR()); diff --git a/arch/blackfin/mach-common/cplbmgr.S b/arch/blackfin/mach-common/cplbmgr.S index faca1ab..f5cf3ac 100644 --- a/arch/blackfin/mach-common/cplbmgr.S +++ b/arch/blackfin/mach-common/cplbmgr.S @@ -190,7 +190,14 @@ ENTRY(_cplb_mgr) [P0 - 4] = R0; R0 = [P0 - 0x100]; [P0-0x104] = R0; -.Lie_move:P0+=4; +.Lie_move: + P0+=4; + + /* Clear ICPLB_DATA15, in case we don't find a replacement + * otherwise, we would have a duplicate entry, and will crash + */ + R0 = 0; + [P0 - 4] = R0; /* We've made space in the ICPLB table, so that ICPLB15 * is now free to be overwritten. Next, we have to determine @@ -515,14 +522,23 @@ ENTRY(_cplb_mgr) R0 = [P0++]; /* move data */ [P0 - 8] = R0; R0 = [P0-0x104] /* move address */ -.Lde_move: [P0-0x108] = R0; +.Lde_move: + [P0-0x108] = R0; + +.Lde_moved: + NOP; + + /* Clear DCPLB_DATA15, in case we don't find a replacement + * otherwise, we would have a duplicate entry, and will crash + */ + R0 = 0; + [P0 - 0x4] = R0; /* We've now made space in DCPLB15 for the new CPLB to be * installed. The next stage is to locate a CPLB in the * config table that covers the faulting address. */ -.Lde_moved:NOP; R0 = I0; /* Our faulting address */ P2.L = _dpdt_table; diff --git a/arch/blackfin/mach-common/interrupt.S b/arch/blackfin/mach-common/interrupt.S index 4de3764..f983ac7 100644 --- a/arch/blackfin/mach-common/interrupt.S +++ b/arch/blackfin/mach-common/interrupt.S @@ -34,9 +34,13 @@ #include #include #include +#include +#include #include +.extern _ret_from_exception + #ifdef CONFIG_I_ENTRY_L1 .section .l1.text #else @@ -134,10 +138,11 @@ __common_int_entry: /* interrupt routine for ivhw - 5 */ ENTRY(_evt_ivhw) - SAVE_CONTEXT + SAVE_ALL_SYS #ifdef CONFIG_FRAME_POINTER fp = 0; #endif + #if ANOMALY_05000283 cc = r7 == r7; p5.h = 0xffc0; @@ -147,13 +152,8 @@ ENTRY(_evt_ivhw) 1: #endif - trace_buffer_stop(p0, r0); - - r0 = IRQ_HWERR; - r1 = sp; - #ifdef CONFIG_HARDWARE_PM - r7 = SEQSTAT; + r7 = [sp + PT_SEQSTAT]; r7 = r7 >>> 0xe; r6 = 0x1F; r7 = r7 & r6; @@ -161,11 +161,29 @@ ENTRY(_evt_ivhw) cc = r7 == r5; if cc jump .Lcall_do_ovf; /* deal with performance counter overflow */ #endif - + # We are going to dump something out, so make sure we print IPEND properly + p2.l = lo(IPEND); + p2.h = hi(IPEND); + r0 = [p2]; + [sp + PT_IPEND] = r0; + + /* set the EXCAUSE to HWERR for trap_c */ + r0 = [sp + PT_SEQSTAT]; + R1.L = LO(VEC_HWERR); + R1.H = HI(VEC_HWERR); + R0 = R0 | R1; + [sp + PT_SEQSTAT] = R0; + + r0 = sp; /* stack frame pt_regs pointer argument ==> r0 */ SP += -12; - call _irq_panic; + call _trap_c; SP += 12; + + call _ret_from_exception; +.Lcommon_restore_all_sys: + RESTORE_ALL_SYS rti; + #ifdef CONFIG_HARDWARE_PM .Lcall_do_ovf: @@ -173,9 +191,11 @@ ENTRY(_evt_ivhw) call _pm_overflow; SP += 12; - jump .Lcommon_restore_context; + jump .Lcommon_restore_all_sys; #endif +ENDPROC(_evt_ivhw) + /* Interrupt routine for evt2 (NMI). * We don't actually use this, so just return. * For inner circle type details, please see: diff --git a/arch/blackfin/mach-common/irqpanic.c b/arch/blackfin/mach-common/irqpanic.c index b22959b..606ded9 100644 --- a/arch/blackfin/mach-common/irqpanic.c +++ b/arch/blackfin/mach-common/irqpanic.c @@ -46,9 +46,6 @@ void irq_panic(int reason, struct pt_regs *regs) __attribute__ ((l1_text)); */ asmlinkage void irq_panic(int reason, struct pt_regs *regs) { - int sig = 0; - siginfo_t info; - #ifdef CONFIG_DEBUG_ICACHE_CHECK unsigned int cmd, tag, ca, cache_hi, cache_lo, *pa; unsigned short i, j, die; @@ -136,53 +133,6 @@ asmlinkage void irq_panic(int reason, struct pt_regs *regs) } #endif - printk(KERN_EMERG "\n"); - printk(KERN_EMERG "Exception: IRQ 0x%x entered\n", reason); - printk(KERN_EMERG " code=[0x%08lx], stack frame=0x%08lx, " - " bad PC=0x%08lx\n", - (unsigned long)regs->seqstat, - (unsigned long)regs, - (unsigned long)regs->pc); - if (reason == 0x5) { - printk(KERN_EMERG "----------- HARDWARE ERROR -----------\n"); - - /* There is only need to check for Hardware Errors, since other - * EXCEPTIONS are handled in TRAPS.c (MH) - */ - switch (regs->seqstat & SEQSTAT_HWERRCAUSE) { - case (SEQSTAT_HWERRCAUSE_SYSTEM_MMR): /* System MMR Error */ - info.si_code = BUS_ADRALN; - sig = SIGBUS; - printk(KERN_EMERG HWC_x2(KERN_EMERG)); - break; - case (SEQSTAT_HWERRCAUSE_EXTERN_ADDR): /* External Memory Addressing Error */ - info.si_code = BUS_ADRERR; - sig = SIGBUS; - printk(KERN_EMERG HWC_x3(KERN_EMERG)); - break; - case (SEQSTAT_HWERRCAUSE_PERF_FLOW): /* Performance Monitor Overflow */ - printk(KERN_EMERG HWC_x12(KERN_EMERG)); - break; - case (SEQSTAT_HWERRCAUSE_RAISE_5): /* RAISE 5 instruction */ - printk(KERN_EMERG HWC_x18(KERN_EMERG)); - break; - default: /* Reserved */ - printk(KERN_EMERG HWC_default(KERN_EMERG)); - break; - } - } - - regs->ipend = bfin_read_IPEND(); - dump_bfin_process(regs); - dump_bfin_mem((void *)regs->pc); - show_regs(regs); - if (0 == (info.si_signo = sig) || 0 == user_mode(regs)) /* in kernelspace */ - panic("Unhandled IRQ or exceptions!\n"); - else { /* in userspace */ - info.si_errno = 0; - info.si_addr = (void *)regs->pc; - force_sig_info(sig, &info, current); - } } #ifdef CONFIG_HARDWARE_PM diff --git a/include/asm-blackfin/traps.h b/include/asm-blackfin/traps.h index ee1cbf7..f0e5f94 100644 --- a/include/asm-blackfin/traps.h +++ b/include/asm-blackfin/traps.h @@ -45,6 +45,10 @@ #define VEC_CPLB_I_M (44) #define VEC_CPLB_I_MHIT (45) #define VEC_ILL_RES (46) /* including unvalid supervisor mode insn */ +/* The hardware reserves (63) for future use - we use it to tell our + * normal exception handling code we have a hardware error + */ +#define VEC_HWERR (63) #ifndef __ASSEMBLY__ -- cgit v0.10.2 From d8f66c8c1ea8e948483ee4739ad91120f5f7de51 Mon Sep 17 00:00:00 2001 From: Robin Getz Date: Mon, 24 Dec 2007 15:27:56 +0800 Subject: [Blackfin] arch: fix bug gdb testing on hardware has regression http://blackfin.uclinux.org/gf/project/toolchain/tracker/?action=TrackerItemEdit&tracker_item_id=3651 As Bernd predicted, this was only necessary because of other problems in the kenel - fixing those, and this is not necessary, so remove it. Signed-off-by: Robin Getz Signed-off-by: Bryan Wu diff --git a/arch/blackfin/kernel/traps.c b/arch/blackfin/kernel/traps.c index 4be5ff0b..8bbfef3 100644 --- a/arch/blackfin/kernel/traps.c +++ b/arch/blackfin/kernel/traps.c @@ -36,6 +36,7 @@ #include #include #include +#include #include #include @@ -508,13 +509,6 @@ asmlinkage void trap_c(struct pt_regs *fp) info.si_addr = (void *)fp->pc; force_sig_info(sig, &info, current); - /* Ensure that bad return addresses don't end up in an infinite - * loop, due to speculative loads/reads. This needs to be done after - * the signal has been sent. - */ - if (trapnr == VEC_CPLB_I_M && sig != SIGTRAP) - fp->pc = SAFE_USER_INSTRUCTION; - trace_buffer_restore(j); return; } @@ -727,6 +721,9 @@ void dump_bfin_mem(void *retaddr) void show_regs(struct pt_regs *fp) { char buf [150]; + struct irqaction *action; + unsigned int i; + unsigned long flags; printk(KERN_NOTICE "\n" KERN_NOTICE "SEQUENCER STATUS:\n"); printk(KERN_NOTICE " SEQSTAT: %08lx IPEND: %04lx SYSCFG: %04lx\n", @@ -735,6 +732,32 @@ void show_regs(struct pt_regs *fp) (fp->seqstat & SEQSTAT_HWERRCAUSE) >> 14); printk(KERN_NOTICE " EXCAUSE : 0x%lx\n", fp->seqstat & SEQSTAT_EXCAUSE); + for (i = 6; i <= 15 ; i++) { + if (fp->ipend & (1 << i)) { + decode_address(buf, bfin_read32(EVT0 + 4*i)); + printk(KERN_NOTICE " physical IVG%i asserted : %s\n", i, buf); + } + } + + /* if no interrupts are going off, don't print this out */ + if (fp->ipend & ~0x3F) { + for (i = 0; i < (NR_IRQS - 1); i++) { + spin_lock_irqsave(&irq_desc[i].lock, flags); + action = irq_desc[i].action; + if (!action) + goto unlock; + + decode_address(buf, (unsigned int)action->handler); + printk(KERN_NOTICE " logical irq %3d mapped : %s", i, buf); + for (action = action->next; action; action = action->next) { + decode_address(buf, (unsigned int)action->handler); + printk(", %s", buf); + } + printk("\n"); +unlock: + spin_unlock_irqrestore(&irq_desc[i].lock, flags); + } + } decode_address(buf, fp->rete); printk(KERN_NOTICE " RETE: %s\n", buf); -- cgit v0.10.2 From 0626d79686b4536eac1dc88e2cf52d927a5010c2 Mon Sep 17 00:00:00 2001 From: Robin Getz Date: Fri, 21 Dec 2007 17:46:33 +0800 Subject: [Blackfin] arch: do not use hard coded addresses Signed-off-by: Robin Getz Signed-off-by: Bryan Wu diff --git a/arch/blackfin/mach-common/interrupt.S b/arch/blackfin/mach-common/interrupt.S index f983ac7..7f752c8 100644 --- a/arch/blackfin/mach-common/interrupt.S +++ b/arch/blackfin/mach-common/interrupt.S @@ -121,8 +121,8 @@ __common_int_entry: #if ANOMALY_05000283 || ANOMALY_05000315 cc = r7 == r7; - p5.h = 0xffc0; - p5.l = 0x0014; + p5.h = HI(CHIPID); + p5.l = LO(CHIPID); if cc jump 1f; r7.l = W[p5]; 1: @@ -145,8 +145,8 @@ ENTRY(_evt_ivhw) #if ANOMALY_05000283 cc = r7 == r7; - p5.h = 0xffc0; - p5.l = 0x0014; + p5.h = HI(CHIPID); + p5.l = LO(CHIPID); if cc jump 1f; r7.l = W[p5]; 1: -- cgit v0.10.2 From 6f3ed704b03b2f9997b604690ac43a3514105a6a Mon Sep 17 00:00:00 2001 From: Robin Getz Date: Fri, 21 Dec 2007 17:48:07 +0800 Subject: [Blackfin] arch: do not use fixed numbers to describe offsets - no functional changes Signed-off-by: Robin Getz Signed-off-by: Bryan Wu diff --git a/arch/blackfin/mach-common/entry.S b/arch/blackfin/mach-common/entry.S index dc9d3ee..1b25b57 100644 --- a/arch/blackfin/mach-common/entry.S +++ b/arch/blackfin/mach-common/entry.S @@ -329,7 +329,7 @@ ENTRY(_exception_to_level5) R7 = R7 + R6; P5 = R7; R1 = [P5]; - [SP + 8] = r1; + [SP + PT_SEQSTAT] = r1; r0 = sp; /* stack frame pt_regs pointer argument ==> r0 */ SP += -12; -- cgit v0.10.2 From d5c4b5e3b2682a9aac07a43a8a79d3b692b22567 Mon Sep 17 00:00:00 2001 From: Robin Getz Date: Fri, 21 Dec 2007 17:49:53 +0800 Subject: [Blackfin] arch: Let the pre-processor do the math to save a few cycles - no functional changes Signed-off-by: Robin Getz Signed-off-by: Bryan Wu diff --git a/arch/blackfin/mach-common/entry.S b/arch/blackfin/mach-common/entry.S index 1b25b57..58f7ad6 100644 --- a/arch/blackfin/mach-common/entry.S +++ b/arch/blackfin/mach-common/entry.S @@ -633,9 +633,7 @@ ENTRY(_ret_from_exception) [sp + PT_IPEND] = r0; 1: - r1 = 0x37(Z); - r2 = ~r1; - r2.h = 0; + r2 = LO(~0x37) (Z); r0 = r2 & r0; cc = r0 == 0; if !cc jump 4f; /* if not return to user mode, get out */ -- cgit v0.10.2 From fb96c56de33def1484614c6a3d0fbef76595ce2f Mon Sep 17 00:00:00 2001 From: Javier Herrero Date: Fri, 21 Dec 2007 18:26:44 +0800 Subject: [Blackfin] arch: Added support for 8250-class UARTs in HV Sistemas H8606 board, modification in 8250.c driver for correct compilation with Blackfin Signed-off-by: Javier Herrero Signed-off-by: Bryan Wu diff --git a/arch/blackfin/mach-bf533/boards/H8606.c b/arch/blackfin/mach-bf533/boards/H8606.c index 6bcf404..675fd1c 100644 --- a/arch/blackfin/mach-bf533/boards/H8606.c +++ b/arch/blackfin/mach-bf533/boards/H8606.c @@ -40,6 +40,7 @@ #endif #include #include + #include #include #include @@ -303,7 +304,49 @@ static struct platform_device bfin_uart_device = { }; #endif -static struct platform_device *stamp_devices[] __initdata = { +#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE) + +#include +#include + +/* + * Configuration for two 16550 UARTS in FPGA at addresses 0x20200000 and 0x202000010. + * running at half system clock, both with interrupt output or-ed to PF8. Change to + * suit different FPGA configuration, or to suit real 16550 UARTS connected to the bus + */ + +static struct plat_serial8250_port serial8250_platform_data [] = { + { + .membase = 0x20200000, + .mapbase = 0x20200000, + .irq = IRQ_PF8, + .flags = UPF_BOOT_AUTOCONF | UART_CONFIG_TYPE, + .iotype = UPIO_MEM, + .regshift = 1, + .uartclk = 66666667, + }, { + .membase = 0x20200010, + .mapbase = 0x20200010, + .irq = IRQ_PF8, + .flags = UPF_BOOT_AUTOCONF | UART_CONFIG_TYPE, + .iotype = UPIO_MEM, + .regshift = 1, + .uartclk = 66666667, + }, { + } +}; + +static struct platform_device serial8250_device = { + .id = PLAT8250_DEV_PLATFORM, + .name = "serial8250", + .dev = { + .platform_data = serial8250_platform_data, + }, +}; + +#endif + +static struct platform_device *h8606_devices[] __initdata = { #if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE) &rtc_device, #endif @@ -327,13 +370,17 @@ static struct platform_device *stamp_devices[] __initdata = { #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE) &bfin_uart_device, #endif + +#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE) + &serial8250_device, +#endif }; static int __init H8606_init(void) { printk(KERN_INFO "HV Sistemas H8606 board support by http://www.hvsistemas.com\n"); printk(KERN_INFO "%s(): registering device resources\n", __FUNCTION__); - platform_add_devices(stamp_devices, ARRAY_SIZE(stamp_devices)); + platform_add_devices(h8606_devices, ARRAY_SIZE(h8606_devices)); #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info)); #endif -- cgit v0.10.2 From a5bb85dfffd38714d83cf7798886462d7314b90a Mon Sep 17 00:00:00 2001 From: Cliff Cai Date: Fri, 21 Dec 2007 21:04:40 +0800 Subject: [Blackfin] arch: fix bug SDIO driver fails to build for BF542/BF548 modified CMD_TIMEOUT and DAT_TIMEOUT to CMD_TIME_OUT and DAT_TIME_OUT Signed-off-by: Cliff Cai Signed-off-by: Bryan Wu diff --git a/include/asm-blackfin/mach-bf548/defBF542.h b/include/asm-blackfin/mach-bf548/defBF542.h index 32d0713..a7c809f 100644 --- a/include/asm-blackfin/mach-bf548/defBF542.h +++ b/include/asm-blackfin/mach-bf548/defBF542.h @@ -432,8 +432,8 @@ #define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */ #define DAT_CRC_FAIL 0x2 /* Data CRC Fail */ -#define CMD_TIMEOUT 0x4 /* CMD Time Out */ -#define DAT_TIMEOUT 0x8 /* Data Time Out */ +#define CMD_TIME_OUT 0x4 /* CMD Time Out */ +#define DAT_TIME_OUT 0x8 /* Data Time Out */ #define TX_UNDERRUN 0x10 /* Transmit Underrun */ #define RX_OVERRUN 0x20 /* Receive Overrun */ #define CMD_RESP_END 0x40 /* CMD Response End */ diff --git a/include/asm-blackfin/mach-bf548/defBF548.h b/include/asm-blackfin/mach-bf548/defBF548.h index ecbca95..e46f568 100644 --- a/include/asm-blackfin/mach-bf548/defBF548.h +++ b/include/asm-blackfin/mach-bf548/defBF548.h @@ -1095,8 +1095,8 @@ #define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */ #define DAT_CRC_FAIL 0x2 /* Data CRC Fail */ -#define CMD_TIMEOUT 0x4 /* CMD Time Out */ -#define DAT_TIMEOUT 0x8 /* Data Time Out */ +#define CMD_TIME_OUT 0x4 /* CMD Time Out */ +#define DAT_TIME_OUT 0x8 /* Data Time Out */ #define TX_UNDERRUN 0x10 /* Transmit Underrun */ #define RX_OVERRUN 0x20 /* Receive Overrun */ #define CMD_RESP_END 0x40 /* CMD Response End */ -- cgit v0.10.2 From c50e19f49830fb651b4b702ad2c3abcdf110b576 Mon Sep 17 00:00:00 2001 From: Yi Li Date: Fri, 21 Dec 2007 21:12:21 +0800 Subject: [Blackfin] arch: fix bug - make memcpy return the dest addr. The memcpy() function returns the src pointer instead of the dst pointer. This patch fix this bug. Signed-off-by: Yi Li Signed-off-by: Bryan Wu diff --git a/arch/blackfin/lib/memcpy.S b/arch/blackfin/lib/memcpy.S index 2e63364..e654a18 100644 --- a/arch/blackfin/lib/memcpy.S +++ b/arch/blackfin/lib/memcpy.S @@ -70,8 +70,8 @@ ENTRY(_memcpy) /* Check for aligned data.*/ R3 = R1 | R0; - R0 = 0x3; - R3 = R3 & R0; + R1 = 0x3; + R3 = R3 & R1; CC = R3; /* low bits set on either address? */ IF CC JUMP .Lnot_aligned; @@ -83,7 +83,6 @@ ENTRY(_memcpy) /* less than eight bytes... */ P2 = R2; LSETUP(.Lthree_start, .Lthree_end) LC0=P2; - R0 = R1; /* setup src address for return */ .Lthree_start: R3 = B[P1++] (X); .Lthree_end: @@ -95,7 +94,6 @@ ENTRY(_memcpy) /* There's at least eight bytes to copy. */ P2 += -1; /* because we unroll one iteration */ LSETUP(.Lword_loops, .Lword_loope) LC0=P2; - R0 = R1; I1 = P1; R3 = [I1++]; #if ANOMALY_05000202 @@ -120,7 +118,6 @@ ENTRY(_memcpy) .Lnot_aligned: /* From here, we're copying byte-by-byte. */ LSETUP (.Lbyte_start, .Lbyte_end) LC0=P2; - R0 = R1; /* Save src address for return */ .Lbyte_start: R1 = B[P1++] (X); .Lbyte_end: @@ -135,7 +132,6 @@ ENTRY(_memcpy) * Don't bother to work out alignment for * the reverse case. */ - R0 = R1; /* save src for later. */ P0 = P0 + P2; P0 += -1; P1 = P1 + P2; -- cgit v0.10.2 From fb5f00492a748facc9f069c95621e05c148edf53 Mon Sep 17 00:00:00 2001 From: Sonic Zhang Date: Sun, 23 Dec 2007 23:02:13 +0800 Subject: [Blackfin] arch: Fix bug to Enable kernel to build for bf548 with PM. On BF548-EZKIT, build kernel faills with power management, video and audio enabled. This patch fix this. Signed-off-by: Sonic Zhang Signed-off-by: Bryan Wu diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig index 25232ba..5ebcfd2 100644 --- a/arch/blackfin/Kconfig +++ b/arch/blackfin/Kconfig @@ -951,6 +951,8 @@ config PM_WAKEUP_SIC_IWR depends on PM_WAKEUP_GPIO_BY_SIC_IWR default 0x80000000 if (BF537 || BF536 || BF534) default 0x100000 if (BF533 || BF532 || BF531) + default 0x800000 if (BF549 || BF548 || BF547 || BF542) + default 0x800000 if (BF527 || BF524 || BF522) config PM_WAKEUP_GPIO_NUMBER int "Wakeup GPIO number" diff --git a/arch/blackfin/mach-bf548/head.S b/arch/blackfin/mach-bf548/head.S index 74b34c7..745662e 100644 --- a/arch/blackfin/mach-bf548/head.S +++ b/arch/blackfin/mach-bf548/head.S @@ -298,8 +298,8 @@ ENTRY(_start_dma_code) w[p0] = r0.l; ssync; - p0.h = hi(SIC_IWR); - p0.l = lo(SIC_IWR); + p0.h = hi(SIC_IWR0); + p0.l = lo(SIC_IWR0); r0.l = 0x1; r0.h = 0x0; [p0] = r0; @@ -395,8 +395,8 @@ ENTRY(_start_dma_code) [P2] = R1; SSYNC; - p0.h = hi(SIC_IWR); - p0.l = lo(SIC_IWR); + p0.h = hi(SIC_IWR0); + p0.l = lo(SIC_IWR0); r0.l = lo(IWR_ENABLE_ALL); r0.h = hi(IWR_ENABLE_ALL); [p0] = r0; diff --git a/arch/blackfin/mach-bf548/ints-priority.c b/arch/blackfin/mach-bf548/ints-priority.c index cb0ebac..05e3b3c 100644 --- a/arch/blackfin/mach-bf548/ints-priority.c +++ b/arch/blackfin/mach-bf548/ints-priority.c @@ -58,7 +58,7 @@ void program_IAR(void) ((CONFIG_IRQ_PINT1 - 7) << IRQ_PINT1_POS) | ((CONFIG_IRQ_MDMAS0 - 7) << IRQ_MDMAS0_POS) | ((CONFIG_IRQ_MDMAS1 - 7) << IRQ_MDMAS1_POS) | - ((CONFIG_IRQ_WATCHDOG - 7) << IRQ_WATCHDOG_POS)); + ((CONFIG_IRQ_WATCHDOG - 7) << IRQ_WATCH_POS)); bfin_write_SIC_IAR3(((CONFIG_IRQ_DMAC1_ERR - 7) << IRQ_DMAC1_ERR_POS) | ((CONFIG_IRQ_SPORT2_ERR - 7) << IRQ_SPORT2_ERR_POS) | diff --git a/arch/blackfin/mach-common/dpmc.S b/arch/blackfin/mach-common/dpmc.S index 39fbc28..301ac1b 100644 --- a/arch/blackfin/mach-common/dpmc.S +++ b/arch/blackfin/mach-common/dpmc.S @@ -38,6 +38,9 @@ ENTRY(_unmask_wdog_wakeup_evt) #if defined(CONFIG_BF561) P0.H = hi(SICA_IWR1); P0.L = lo(SICA_IWR1); +#elif defined(CONFIG_BF54x) || defined(CONFIG_BF52x) + P0.h = HI(SIC_IWR0); + P0.l = LO(SIC_IWR0); #else P0.h = HI(SIC_IWR); P0.l = LO(SIC_IWR); @@ -236,7 +239,7 @@ ENTRY(_deep_sleep) call _set_sic_iwr; - call _set_sdram_srfs; + call _set_dram_srfs; /* Clear all the interrupts,bits sticky */ R0 = 0xFFFF (Z); @@ -253,7 +256,7 @@ ENTRY(_deep_sleep) SSYNC; IDLE; - call _unset_sdram_srfs; + call _unset_dram_srfs; call _test_pll_locked; @@ -285,7 +288,7 @@ ENTRY(_sleep_deeper) P3 = R0; R0 = IWR_ENABLE(0); call _set_sic_iwr; - call _set_sdram_srfs; + call _set_dram_srfs; /* Clear all the interrupts,bits sticky */ R0 = 0xFFFF (Z); @@ -360,7 +363,7 @@ ENTRY(_sleep_deeper) IDLE; call _test_pll_locked; - call _unset_sdram_srfs; + call _unset_dram_srfs; STI R4; @@ -368,25 +371,47 @@ ENTRY(_sleep_deeper) ( R7:0, P5:0 ) = [SP++]; RTS; -ENTRY(_set_sdram_srfs) - /* set the sdram to self refresh mode */ +ENTRY(_set_dram_srfs) + /* set the dram to self refresh mode */ +#if defined(CONFIG_BF54x) + P0.H = hi(EBIU_RSTCTL); + P0.L = lo(EBIU_RSTCTL); + R2 = [P0]; + R3.H = hi(SRREQ); + R3.L = lo(SRREQ); +#else P0.H = hi(EBIU_SDGCTL); P0.L = lo(EBIU_SDGCTL); R2 = [P0]; R3.H = hi(SRFS); R3.L = lo(SRFS); +#endif R2 = R2|R3; [P0] = R2; ssync; +#if defined(CONFIG_BF54x) +.LSRR_MODE: + R2 = [P0]; + CC = BITTST(R2, 4); + if !CC JUMP .LSRR_MODE; +#endif RTS; -ENTRY(_unset_sdram_srfs) - /* set the sdram out of self refresh mode */ +ENTRY(_unset_dram_srfs) + /* set the dram out of self refresh mode */ +#if defined(CONFIG_BF54x) + P0.H = hi(EBIU_RSTCTL); + P0.L = lo(EBIU_RSTCTL); + R2 = [P0]; + R3.H = hi(SRREQ); + R3.L = lo(SRREQ); +#else P0.H = hi(EBIU_SDGCTL); P0.L = lo(EBIU_SDGCTL); R2 = [P0]; R3.H = hi(SRFS); R3.L = lo(SRFS); +#endif R3 = ~R3; R2 = R2&R3; [P0] = R2; @@ -394,8 +419,13 @@ ENTRY(_unset_sdram_srfs) RTS; ENTRY(_set_sic_iwr) +#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) + P0.H = hi(SIC_IWR0); + P0.L = lo(SIC_IWR0); +#else P0.H = hi(SIC_IWR); P0.L = lo(SIC_IWR); +#endif [P0] = R0; SSYNC; RTS; diff --git a/arch/blackfin/mach-common/pm.c b/arch/blackfin/mach-common/pm.c index dac51fb..81930f7 100644 --- a/arch/blackfin/mach-common/pm.c +++ b/arch/blackfin/mach-common/pm.c @@ -77,7 +77,15 @@ void bfin_pm_suspend_standby_enter(void) gpio_pm_restore(); +#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) + bfin_write_SIC_IWR0(IWR_ENABLE_ALL); + bfin_write_SIC_IWR1(IWR_ENABLE_ALL); +# ifdef CONFIG_BF54x + bfin_write_SIC_IWR2(IWR_ENABLE_ALL); +# endif +#else bfin_write_SIC_IWR(IWR_ENABLE_ALL); +#endif local_irq_restore(flags); } @@ -85,7 +93,15 @@ void bfin_pm_suspend_standby_enter(void) #if defined(CONFIG_PM_WAKEUP_GPIO_BY_SIC_IWR) sleep_deeper(CONFIG_PM_WAKEUP_SIC_IWR); +# if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) + bfin_write_SIC_IWR0(IWR_ENABLE_ALL); + bfin_write_SIC_IWR1(IWR_ENABLE_ALL); +# ifdef CONFIG_BF54x + bfin_write_SIC_IWR2(IWR_ENABLE_ALL); +# endif +# else bfin_write_SIC_IWR(IWR_ENABLE_ALL); +# endif #endif /* CONFIG_PM_WAKEUP_GPIO_BY_SIC_IWR */ } diff --git a/include/asm-blackfin/mach-bf548/irq.h b/include/asm-blackfin/mach-bf548/irq.h index 9fb7bc5..c34507a 100644 --- a/include/asm-blackfin/mach-bf548/irq.h +++ b/include/asm-blackfin/mach-bf548/irq.h @@ -88,7 +88,7 @@ Events (highest priority) EMU 0 #define IRQ_PINT1 BFIN_IRQ(20) /* PINT1 Interrupt */ #define IRQ_MDMAS0 BFIN_IRQ(21) /* MDMA Stream 0 Interrupt */ #define IRQ_MDMAS1 BFIN_IRQ(22) /* MDMA Stream 1 Interrupt */ -#define IRQ_WATCHDOG BFIN_IRQ(23) /* Watchdog Interrupt */ +#define IRQ_WATCH BFIN_IRQ(23) /* Watchdog Interrupt */ #define IRQ_DMAC1_ERROR BFIN_IRQ(24) /* DMAC1 Status (Error) Interrupt */ #define IRQ_SPORT2_ERROR BFIN_IRQ(25) /* SPORT2 Error Interrupt */ #define IRQ_SPORT3_ERROR BFIN_IRQ(26) /* SPORT3 Error Interrupt */ @@ -406,7 +406,7 @@ Events (highest priority) EMU 0 #define IRQ_PINT1_POS 16 #define IRQ_MDMAS0_POS 20 #define IRQ_MDMAS1_POS 24 -#define IRQ_WATCHDOG_POS 28 +#define IRQ_WATCH_POS 28 /* IAR3 BIT FIELDS */ #define IRQ_DMAC1_ERR_POS 0 diff --git a/include/asm-blackfin/mach-bf548/mem_init.h b/include/asm-blackfin/mach-bf548/mem_init.h index 0cb279e..e792eb7 100644 --- a/include/asm-blackfin/mach-bf548/mem_init.h +++ b/include/asm-blackfin/mach-bf548/mem_init.h @@ -30,6 +30,7 @@ */ #if (CONFIG_MEM_MT46V32M16) +#endif #if defined CONFIG_CLKIN_HALF #define CLKIN_HALF 1 -- cgit v0.10.2 From 0d4a89bb3eb58f39831186fa6b1542893dbfdc9f Mon Sep 17 00:00:00 2001 From: Michael Hennerich Date: Sun, 27 Jan 2008 19:58:46 +0800 Subject: [Blackfin] arch: add Hitachi TX09D70VM1CDA TFT LCD driver resource to Blackfin board Signed-off-by: Michael Hennerich Signed-off-by: Bryan Wu diff --git a/arch/blackfin/mach-bf537/boards/cm_bf537.c b/arch/blackfin/mach-bf537/boards/cm_bf537.c index c0fb06d..a102615 100644 --- a/arch/blackfin/mach-bf537/boards/cm_bf537.c +++ b/arch/blackfin/mach-bf537/boards/cm_bf537.c @@ -216,6 +216,12 @@ static struct platform_device rtc_device = { }; #endif +#if defined(CONFIG_FB_HITACHI_TX09) || defined(CONFIG_FB_HITACHI_TX09_MODULE) +static struct platform_device hitachi_fb_device = { + .name = "hitachi-tx09", +}; +#endif + #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE) static struct resource smc91x_resources[] = { { @@ -374,6 +380,10 @@ static struct platform_device bfin_pata_device = { #endif static struct platform_device *cm_bf537_devices[] __initdata = { +#if defined(CONFIG_FB_HITACHI_TX09) || defined(CONFIG_FB_HITACHI_TX09_MODULE) + &hitachi_fb_device, +#endif + #if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE) &rtc_device, #endif diff --git a/arch/blackfin/mach-bf561/boards/cm_bf561.c b/arch/blackfin/mach-bf561/boards/cm_bf561.c index c19cd29..3a79a90 100644 --- a/arch/blackfin/mach-bf561/boards/cm_bf561.c +++ b/arch/blackfin/mach-bf561/boards/cm_bf561.c @@ -198,6 +198,13 @@ static struct platform_device bfin_spi0_device = { #endif /* spi master and devices */ +#if defined(CONFIG_FB_HITACHI_TX09) || defined(CONFIG_FB_HITACHI_TX09_MODULE) +static struct platform_device hitachi_fb_device = { + .name = "hitachi-tx09", +}; +#endif + + #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE) static struct resource smc91x_resources[] = { @@ -315,6 +322,10 @@ static struct platform_device bfin_pata_device = { static struct platform_device *cm_bf561_devices[] __initdata = { +#if defined(CONFIG_FB_HITACHI_TX09) || defined(CONFIG_FB_HITACHI_TX09_MODULE) + &hitachi_fb_device, +#endif + #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE) &bfin_uart_device, #endif -- cgit v0.10.2 From b03b08ba9c7235861adf4dde712dade0bb756fe0 Mon Sep 17 00:00:00 2001 From: Robin Getz Date: Sun, 23 Dec 2007 22:57:01 +0800 Subject: [Blackfin] arch: Clean up dump_bfin_mem Clean up dump_bfin_mem so that it will display content from the kernel, as well as l1 instruction, when deferred HW errors happen, print out the last frame info if it makes sense. Signed-off-by: Robin Getz Signed-off-by: Bryan Wu diff --git a/arch/blackfin/kernel/early_printk.c b/arch/blackfin/kernel/early_printk.c index 724f4a5..c892777 100644 --- a/arch/blackfin/kernel/early_printk.c +++ b/arch/blackfin/kernel/early_printk.c @@ -205,7 +205,7 @@ asmlinkage void __init early_trap_c(struct pt_regs *fp, void *retaddr) if (likely(early_console == NULL)) setup_early_printk(DEFAULT_EARLY_PORT); - dump_bfin_mem((void *)fp->retx); + dump_bfin_mem(fp); show_regs(fp); dump_bfin_trace_buffer(); diff --git a/arch/blackfin/kernel/process.c b/arch/blackfin/kernel/process.c index 5bf1512..fff3dd9 100644 --- a/arch/blackfin/kernel/process.c +++ b/arch/blackfin/kernel/process.c @@ -327,6 +327,7 @@ void finish_atomic_sections (struct pt_regs *regs) } #if defined(CONFIG_ACCESS_CHECK) +/* Return 1 if access to memory range is OK, 0 otherwise */ int _access_ok(unsigned long addr, unsigned long size) { if (size == 0) diff --git a/arch/blackfin/kernel/traps.c b/arch/blackfin/kernel/traps.c index 8bbfef3..c90f168 100644 --- a/arch/blackfin/kernel/traps.c +++ b/arch/blackfin/kernel/traps.c @@ -39,6 +39,7 @@ #include #include #include +#include #ifdef CONFIG_KGDB # include @@ -171,7 +172,7 @@ asmlinkage void double_fault_c(struct pt_regs *fp) oops_in_progress = 1; printk(KERN_EMERG "\n" KERN_EMERG "Double Fault\n"); dump_bfin_process(fp); - dump_bfin_mem((void *)fp->retx); + dump_bfin_mem(fp); show_regs(fp); panic("Double Fault - unrecoverable event\n"); @@ -196,6 +197,10 @@ asmlinkage void trap_c(struct pt_regs *fp) * we will kernel panic, so the system reboots. * If KGDB is enabled, don't set this for kernel breakpoints */ + + /* TODO: check to see if we are in some sort of deferred HWERR + * that we should be able to recover from, not kernel panic + */ if ((bfin_read_IPEND() & 0xFFC0) #ifdef CONFIG_KGDB && trapnr != VEC_EXCPT02 @@ -478,11 +483,7 @@ asmlinkage void trap_c(struct pt_regs *fp) if (sig != SIGTRAP) { unsigned long stack; dump_bfin_process(fp); - /* Is it an interrupt, or an exception? */ - if (trapnr == VEC_HWERR) - dump_bfin_mem((void *)fp->pc); - else - dump_bfin_mem((void *)fp->retx); + dump_bfin_mem(fp); show_regs(fp); /* Print out the trace buffer if it makes sense */ @@ -644,8 +645,10 @@ void dump_bfin_process(struct pt_regs *fp) if (oops_in_progress) printk(KERN_EMERG "Kernel OOPS in progress\n"); - if (context & 0x0020) - printk(KERN_NOTICE "Deferred excecption or HW Error context\n"); + if (context & 0x0020 && (fp->seqstat & SEQSTAT_EXCAUSE) == VEC_HWERR) + printk(KERN_NOTICE "HW Error context\n"); + else if (context & 0x0020) + printk(KERN_NOTICE "Defered Exception context\n"); else if (context & 0x3FC0) printk(KERN_NOTICE "Interrupt context\n"); else if (context & 0x4000) @@ -673,49 +676,82 @@ void dump_bfin_process(struct pt_regs *fp) "No Valid process in current context\n"); } -void dump_bfin_mem(void *retaddr) +void dump_bfin_mem(struct pt_regs *fp) { + unsigned short *addr, *erraddr, val = 0, err = 0; + char sti = 0, buf[6]; - if (retaddr >= (void *)FIXED_CODE_START && retaddr < (void *)physical_mem_end -#if L1_CODE_LENGTH != 0 - /* FIXME: Copy the code out of L1 Instruction SRAM through dma - memcpy. */ - && !(retaddr >= (void *)L1_CODE_START - && retaddr < (void *)(L1_CODE_START + L1_CODE_LENGTH)) -#endif - ) { - int i = ((unsigned int)retaddr & 0xFFFFFFF0) - 32; - unsigned short x = 0; - printk(KERN_NOTICE "return address: [0x%p]; contents of:", retaddr); - for (; i < ((unsigned int)retaddr & 0xFFFFFFF0) + 32; i += 2) { - if (!(i & 0xF)) - printk("\n" KERN_NOTICE "0x%08x: ", i); - - if (get_user(x, (unsigned short *)i)) - break; + if (unlikely((fp->seqstat & SEQSTAT_EXCAUSE) == VEC_HWERR)) + erraddr = (void *)fp->pc; + else + erraddr = (void *)fp->retx; + + printk(KERN_NOTICE "return address: [0x%p]; contents of:", erraddr); + + for (addr = (unsigned short *)((unsigned long)erraddr & ~0xF) - 0x10; + addr < (unsigned short *)((unsigned long)erraddr & ~0xF) + 0x10; + addr++) { + if (!((unsigned long)addr & 0xF)) + printk("\n" KERN_NOTICE "0x%p: ", addr); + + if (get_user(val, addr)) { + if (addr >= (unsigned short *)L1_CODE_START && + addr < (unsigned short *)(L1_CODE_START + L1_CODE_LENGTH)) { + dma_memcpy(&val, addr, sizeof(val)); + sprintf(buf, "%04x", val); + } else if (addr >= (unsigned short *)FIXED_CODE_START && + addr <= (unsigned short *)memory_start) { + val = bfin_read16(addr); + sprintf(buf, "%04x", val); + } else { + val = 0; + sprintf(buf, "????"); + } + } else + sprintf(buf, "%04x", val); + + if (addr == erraddr) { + printk("[%s]", buf); + err = val; + } else + printk(" %s ", buf); + + /* Do any previous instructions turn on interrupts? */ + if (addr <= erraddr && /* in the past */ + ((val >= 0x0040 && val <= 0x0047) || /* STI instruction */ + val == 0x017b)) /* [SP++] = RETI */ + sti = 1; + } + + printk("\n"); + + /* Hardware error interrupts can be deferred */ + if (unlikely(sti && (fp->seqstat & SEQSTAT_EXCAUSE) == VEC_HWERR && + oops_in_progress)){ + printk(KERN_NOTICE "Looks like this was a deferred error - sorry\n"); #ifndef CONFIG_DEBUG_HWERR - /* If one of the last few instructions was a STI - * it is likely that the error occured awhile ago - * and we just noticed. This only happens in kernel - * context, which should mean an oops is happening - */ - if (oops_in_progress && x >= 0x0040 && x <= 0x0047 && i <= 0) - printk(KERN_EMERG "\n" - KERN_EMERG "WARNING : You should reconfigure" - " the kernel to turn on\n" - KERN_EMERG " 'Hardware error interrupt debugging'\n" - KERN_EMERG " The rest of this error is meanless\n"); -#endif - if (i == (unsigned int)retaddr) - printk("[%04x]", x); - else - printk(" %04x ", x); + printk(KERN_NOTICE "The remaining message may be meaningless\n" + KERN_NOTICE "You should enable CONFIG_DEBUG_HWERR to get a" + " better idea where it came from\n"); +#else + /* If we are handling only one peripheral interrupt + * and current mm and pid are valid, and the last error + * was in that user space process's text area + * print it out - because that is where the problem exists + */ + if ((!(((fp)->ipend & ~0x30) & (((fp)->ipend & ~0x30) - 1))) && + (current->pid && current->mm)) { + /* And the last RETI points to the current userspace context */ + if ((fp + 1)->pc >= current->mm->start_code && + (fp + 1)->pc <= current->mm->end_code) { + printk(KERN_NOTICE "It might be better to look around here : \n"); + printk(KERN_NOTICE "-------------------------------------------\n"); + show_regs(fp + 1); + printk(KERN_NOTICE "-------------------------------------------\n"); + } } - printk("\n"); - } else - printk("\n" KERN_NOTICE - "Cannot look at the [PC] <%p> for it is" - " in unreadable memory - sorry\n", retaddr); +#endif + } } void show_regs(struct pt_regs *fp) @@ -885,7 +921,7 @@ void panic_cplb_error(int cplb_panic, struct pt_regs *fp) printk(KERN_EMERG "DCPLB_FAULT_ADDR=%p\n", (void *)bfin_read_DCPLB_FAULT_ADDR()); printk(KERN_EMERG "ICPLB_FAULT_ADDR=%p\n", (void *)bfin_read_ICPLB_FAULT_ADDR()); dump_bfin_process(fp); - dump_bfin_mem((void *)fp->retx); + dump_bfin_mem(fp); show_regs(fp); dump_stack(); panic("Unrecoverable event\n"); diff --git a/include/asm-blackfin/bfin-global.h b/include/asm-blackfin/bfin-global.h index 39bdd86..6ae0619 100644 --- a/include/asm-blackfin/bfin-global.h +++ b/include/asm-blackfin/bfin-global.h @@ -51,7 +51,7 @@ extern unsigned long sclk_to_usecs(unsigned long sclk); extern unsigned long usecs_to_sclk(unsigned long usecs); extern void dump_bfin_process(struct pt_regs *regs); -extern void dump_bfin_mem(void *retaddr); +extern void dump_bfin_mem(struct pt_regs *regs); extern void dump_bfin_trace_buffer(void); extern int init_arch_irq(void); -- cgit v0.10.2 From 971d5bc4e5c75bfc4466deaff09839cd6f918eca Mon Sep 17 00:00:00 2001 From: Sonic Zhang Date: Sun, 27 Jan 2008 16:32:31 +0800 Subject: [Blackfin] arch: Fix bug to Enable bf548 to Re-program Clocks while Kernel boots. Reprogram DDR EBIU register properly for bf548. Signed-off-by: Sonic Zhang Signed-off-by: Bryan Wu diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig index 5ebcfd2..1364dca 100644 --- a/arch/blackfin/Kconfig +++ b/arch/blackfin/Kconfig @@ -317,7 +317,7 @@ config VCO_MULT range 1 64 default "22" if BFIN533_EZKIT default "45" if BFIN533_STAMP - default "20" if (BFIN537_STAMP || BFIN527_EZKIT) + default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN548_EZKIT) default "22" if BFIN533_BLUETECHNIX_CM default "20" if BFIN537_BLUETECHNIX_CM default "20" if BFIN561_BLUETECHNIX_CM @@ -354,7 +354,7 @@ config SCLK_DIV range 1 15 default 5 if BFIN533_EZKIT default 5 if BFIN533_STAMP - default 4 if (BFIN537_STAMP || BFIN527_EZKIT) + default 4 if (BFIN537_STAMP || BFIN527_EZKIT || BFIN548_EZKIT) default 5 if BFIN533_BLUETECHNIX_CM default 4 if BFIN537_BLUETECHNIX_CM default 4 if BFIN561_BLUETECHNIX_CM @@ -409,6 +409,7 @@ config MEM_SIZE default 32 if BFIN533_EZKIT default 64 if BFIN527_EZKIT default 64 if BFIN537_STAMP + default 64 if BFIN548_EZKIT default 64 if BFIN561_EZKIT default 128 if BFIN533_STAMP default 64 if PNAV10 @@ -416,6 +417,7 @@ config MEM_SIZE config MEM_ADD_WIDTH int "SDRAM Memory Address Width" + depends on (!BF54x) default 9 if BFIN533_EZKIT default 9 if BFIN561_EZKIT default 9 if H8606_HVSISTEMAS @@ -424,6 +426,19 @@ config MEM_ADD_WIDTH default 11 if BFIN533_STAMP default 10 if PNAV10 + +choice + prompt "DDR SDRAM Chip Type" + depends on BFIN548_EZKIT + default MEM_MT46V32M16_5B + +config MEM_MT46V32M16_6T + bool "MT46V32M16_6T" + +config MEM_MT46V32M16_5B + bool "MT46V32M16_5B" +endchoice + config ENET_FLASH_PIN int "PF port/pin used for flash and ethernet sharing" depends on (BFIN533_STAMP) diff --git a/arch/blackfin/mach-bf548/head.S b/arch/blackfin/mach-bf548/head.S index 745662e..74fe258 100644 --- a/arch/blackfin/mach-bf548/head.S +++ b/arch/blackfin/mach-bf548/head.S @@ -324,12 +324,25 @@ ENTRY(_start_dma_code) w[p0] = r0.l; ssync; +#if defined(CONFIG_BF54x) + P2.H = hi(EBIU_RSTCTL); + P2.L = lo(EBIU_RSTCTL); + R0 = [P2]; + BITSET (R0, 3); +#else P2.H = hi(EBIU_SDGCTL); P2.L = lo(EBIU_SDGCTL); R0 = [P2]; BITSET (R0, 24); +#endif [P2] = R0; SSYNC; +#if defined(CONFIG_BF54x) +.LSRR_MODE: + R0 = [P2]; + CC = BITTST(R0, 4); + if !CC JUMP .LSRR_MODE; +#endif r0 = CONFIG_VCO_MULT & 63; /* Load the VCO multiplier */ r0 = r0 << 9; /* Shift it over, */ @@ -361,6 +374,39 @@ ENTRY(_start_dma_code) w[p0] = r0.l; ssync; +#if defined(CONFIG_BF54x) + P2.H = hi(EBIU_RSTCTL); + P2.L = lo(EBIU_RSTCTL); + R0 = [P2]; + CC = BITTST(R0, 0); + if CC jump .Lskipddrrst; + BITSET (R0, 0); +.Lskipddrrst: + BITCLR (R0, 3); + [P2] = R0; + SSYNC; + + p0.l = lo(EBIU_DDRCTL0); + p0.h = hi(EBIU_DDRCTL0); + r0.l = lo(mem_DDRCTL0); + r0.h = hi(mem_DDRCTL0); + [p0] = r0; + ssync; + + p0.l = lo(EBIU_DDRCTL1); + p0.h = hi(EBIU_DDRCTL1); + r0.l = lo(mem_DDRCTL1); + r0.h = hi(mem_DDRCTL1); + [p0] = r0; + ssync; + + p0.l = lo(EBIU_DDRCTL2); + p0.h = hi(EBIU_DDRCTL2); + r0.l = lo(mem_DDRCTL2); + r0.h = hi(mem_DDRCTL2); + [p0] = r0; + ssync; +#else p0.l = lo(EBIU_SDRRC); p0.h = hi(EBIU_SDRRC); r0 = mem_SDRRC; @@ -394,6 +440,7 @@ ENTRY(_start_dma_code) R1 = R1 | R0; [P2] = R1; SSYNC; +#endif p0.h = hi(SIC_IWR0); p0.l = lo(SIC_IWR0); diff --git a/include/asm-blackfin/mach-bf548/defBF54x_base.h b/include/asm-blackfin/mach-bf548/defBF54x_base.h index 319a485..08f90c2 100644 --- a/include/asm-blackfin/mach-bf548/defBF54x_base.h +++ b/include/asm-blackfin/mach-bf548/defBF54x_base.h @@ -1772,17 +1772,36 @@ #define TRP 0x3c0000 /* Pre charge-to-active command period */ #define TRAS 0x3c00000 /* Min Active-to-pre charge time */ #define TRC 0x3c000000 /* Active-to-active time */ +#define DDR_TRAS(x) ((x<<22)&TRAS) /* DDR tRAS = (1~15) cycles */ +#define DDR_TRP(x) ((x<<18)&TRP) /* DDR tRP = (1~15) cycles */ +#define DDR_TRC(x) ((x<<26)&TRC) /* DDR tRC = (1~15) cycles */ +#define DDR_TRFC(x) ((x<<14)&TRFC) /* DDR tRFC = (1~15) cycles */ +#define DDR_TREFI(x) (x&TREFI) /* DDR tRFC = (1~15) cycles */ /* Bit masks for EBIU_DDRCTL1 */ #define TRCD 0xf /* Active-to-Read/write delay */ -#define MRD 0xf0 /* Mode register set to active */ +#define TMRD 0xf0 /* Mode register set to active */ #define TWR 0x300 /* Write Recovery time */ #define DDRDATWIDTH 0x3000 /* DDR data width */ #define EXTBANKS 0xc000 /* External banks */ #define DDRDEVWIDTH 0x30000 /* DDR device width */ #define DDRDEVSIZE 0xc0000 /* DDR device size */ -#define TWWTR 0xf0000000 /* Write-to-read delay */ +#define TWTR 0xf0000000 /* Write-to-read delay */ +#define DDR_TWTR(x) ((x<<28)&TWTR) /* DDR tWTR = (1~15) cycles */ +#define DDR_TMRD(x) ((x<<4)&TMRD) /* DDR tMRD = (1~15) cycles */ +#define DDR_TWR(x) ((x<<8)&TWR) /* DDR tWR = (1~15) cycles */ +#define DDR_TRCD(x) (x&TRCD) /* DDR tRCD = (1~15) cycles */ +#define DDR_DATWIDTH 0x2000 /* DDR data width */ +#define EXTBANK_1 0 /* 1 external bank */ +#define EXTBANK_2 0x4000 /* 2 external banks */ +#define DEVSZ_64 0x40000 /* DDR External Bank Size = 64MB */ +#define DEVSZ_128 0x80000 /* DDR External Bank Size = 128MB */ +#define DEVSZ_256 0xc0000 /* DDR External Bank Size = 256MB */ +#define DEVSZ_512 0 /* DDR External Bank Size = 512MB */ +#define DEVWD_4 0 /* DDR Device Width = 4 Bits */ +#define DEVWD_8 0x10000 /* DDR Device Width = 8 Bits */ +#define DEVWD_16 0x20000 /* DDR Device Width = 16 Bits */ /* Bit masks for EBIU_DDRCTL2 */ @@ -1790,6 +1809,10 @@ #define CASLATENCY 0x70 /* CAS latency */ #define DLLRESET 0x100 /* DLL Reset */ #define REGE 0x1000 /* Register mode enable */ +#define CL_1_5 0x50 /* DDR CAS Latency = 1.5 cycles */ +#define CL_2 0x20 /* DDR CAS Latency = 2 cycles */ +#define CL_2_5 0x60 /* DDR CAS Latency = 2.5 cycles */ +#define CL_3 0x30 /* DDR CAS Latency = 3 cycles */ /* Bit masks for EBIU_DDRCTL3 */ @@ -2257,6 +2280,10 @@ #define CSEL 0x30 /* Core Select */ #define SSEL 0xf /* System Select */ +#define CSEL_DIV1 0x0000 /* CCLK = VCO / 1 */ +#define CSEL_DIV2 0x0010 /* CCLK = VCO / 2 */ +#define CSEL_DIV4 0x0020 /* CCLK = VCO / 4 */ +#define CSEL_DIV8 0x0030 /* CCLK = VCO / 8 */ /* Bit masks for PLL_CTL */ diff --git a/include/asm-blackfin/mach-bf548/mem_init.h b/include/asm-blackfin/mach-bf548/mem_init.h index e792eb7..befc290 100644 --- a/include/asm-blackfin/mach-bf548/mem_init.h +++ b/include/asm-blackfin/mach-bf548/mem_init.h @@ -28,10 +28,69 @@ * If not, write to the Free Software Foundation, * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ +#define MIN_DDR_SCLK(x) (x*(CONFIG_SCLK_HZ/1000/1000)/1000 + 1) -#if (CONFIG_MEM_MT46V32M16) +#if (CONFIG_MEM_MT46V32M16_6T) +#define DDR_SIZE DEVSZ_512 +#define DDR_WIDTH DEVWD_16 + +#define DDR_tRC DDR_TRC(MIN_DDR_SCLK(60)) +#define DDR_tRAS DDR_TRAS(MIN_DDR_SCLK(42)) +#define DDR_tRP DDR_TRP(MIN_DDR_SCLK(15)) +#define DDR_tRFC DDR_TRFC(MIN_DDR_SCLK(72)) +#define DDR_tREFI DDR_TREFI(MIN_DDR_SCLK(7800)) + +#define DDR_tRCD DDR_TRCD(MIN_DDR_SCLK(15)) +#define DDR_tWTR DDR_TWTR(1) +#define DDR_tMRD DDR_TMRD(MIN_DDR_SCLK(12)) +#define DDR_tWR DDR_TWR(MIN_DDR_SCLK(15)) +#endif + +#if (CONFIG_MEM_MT46V32M16_5B) +#define DDR_SIZE DEVSZ_512 +#define DDR_WIDTH DEVWD_16 + +#define DDR_tRC DDR_TRC(MIN_DDR_SCLK(55)) +#define DDR_tRAS DDR_TRAS(MIN_DDR_SCLK(40)) +#define DDR_tRP DDR_TRP(MIN_DDR_SCLK(15)) +#define DDR_tRFC DDR_TRFC(MIN_DDR_SCLK(70)) +#define DDR_tREFI DDR_TREFI(MIN_DDR_SCLK(7800)) + +#define DDR_tRCD DDR_TRCD(MIN_DDR_SCLK(15)) +#define DDR_tWTR DDR_TWTR(2) +#define DDR_tMRD DDR_TMRD(MIN_DDR_SCLK(10)) +#define DDR_tWR DDR_TWR(MIN_DDR_SCLK(15)) +#endif + +#if (CONFIG_MEM_GENERIC_BOARD) +#define DDR_SIZE DEVSZ_512 +#define DDR_WIDTH DEVWD_16 + +#define DDR_tRCD DDR_TRCD(3) +#define DDR_tWTR DDR_TWTR(2) +#define DDR_tWR DDR_TWR(2) +#define DDR_tMRD DDR_TMRD(2) +#define DDR_tRP DDR_TRP(3) +#define DDR_tRAS DDR_TRAS(7) +#define DDR_tRC DDR_TRC(10) +#define DDR_tRFC DDR_TRFC(12) +#define DDR_tREFI DDR_TREFI(1288) #endif +#if (CONFIG_SCLK_HZ <= 133333333) +#define DDR_CL CL_2 +#elif (CONFIG_SCLK_HZ <= 166666666) +#define DDR_CL CL_2_5 +#else +#define DDR_CL CL_3 +#endif + +#define mem_DDRCTL0 (DDR_tRP | DDR_tRAS | DDR_tRC | DDR_tRFC | DDR_tREFI) +#define mem_DDRCTL1 (DDR_DATWIDTH | EXTBANK_1 | DDR_SIZE | DDR_WIDTH | DDR_tWTR \ + | DDR_tMRD | DDR_tWR | DDR_tRCD) +#define mem_DDRCTL2 DDR_CL + + #if defined CONFIG_CLKIN_HALF #define CLKIN_HALF 1 #else -- cgit v0.10.2 From 1089e228737019b9711a6a394eebe25bf46b22d9 Mon Sep 17 00:00:00 2001 From: Michael Hennerich Date: Mon, 24 Dec 2007 11:49:29 +0800 Subject: [Blackfin] arch: Enable peripheral platform resources on the BF527 EZkit Signed-off-by: Michael Hennerich Signed-off-by: Bryan Wu diff --git a/arch/blackfin/mach-bf527/boards/ezkit.c b/arch/blackfin/mach-bf527/boards/ezkit.c index 003e2ac..bc25681 100644 --- a/arch/blackfin/mach-bf527/boards/ezkit.c +++ b/arch/blackfin/mach-bf527/boards/ezkit.c @@ -41,6 +41,7 @@ #include #include #include +#include #include #include #include @@ -105,6 +106,69 @@ void __exit bfin_isp1761_exit(void) arch_initcall(bfin_isp1761_init); #endif +#if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE) +static struct resource musb_resources[] = { + [0] = { + .start = 0xffc03800, + .end = 0xffc03cff, + .flags = IORESOURCE_MEM, + }, + [1] = { /* general IRQ */ + .start = IRQ_USB_INT0, + .end = IRQ_USB_INT0, + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, + }, + [2] = { /* DMA IRQ */ + .start = IRQ_USB_DMA, + .end = IRQ_USB_DMA, + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, + }, +}; + +static struct musb_hdrc_platform_data musb_plat = { +#if defined(CONFIG_USB_MUSB_OTG) + .mode = MUSB_OTG, +#elif defined(CONFIG_USB_MUSB_HDRC_HCD) + .mode = MUSB_HOST, +#elif defined(CONFIG_USB_GADGET_MUSB_HDRC) + .mode = MUSB_PERIPHERAL, +#endif + .multipoint = 0, +}; + +static u64 musb_dmamask = ~(u32)0; + +static struct platform_device musb_device = { + .name = "musb_hdrc", + .id = 0, + .dev = { + .dma_mask = &musb_dmamask, + .coherent_dma_mask = 0xffffffff, + .platform_data = &musb_plat, + }, + .num_resources = ARRAY_SIZE(musb_resources), + .resource = musb_resources, +}; +#endif + +#if defined(CONFIG_FB_BFIN_T350MCQB) || defined(CONFIG_FB_BFIN_T350MCQB_MODULE) + +static struct resource bf52x_t350mcqb_resources[] = { + { + .start = IRQ_PPI_ERROR, + .end = IRQ_PPI_ERROR, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device bf52x_t350mcqb_device = { + .name = "bfin-t350mcqb", + .id = -1, + .num_resources = ARRAY_SIZE(bf52x_t350mcqb_resources), + .resource = bf52x_t350mcqb_resources, +}; +#endif + #if defined(CONFIG_MTD_NAND_BF5XX) || defined(CONFIG_MTD_NAND_BF5XX_MODULE) static struct mtd_partition partition_info[] = { { @@ -718,6 +782,28 @@ static struct platform_device bfin_pata_device = { }; #endif +#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE) +#include +#include + +static struct gpio_keys_button bfin_gpio_keys_table[] = { + {BTN_0, GPIO_PG0, 1, "gpio-keys: BTN0"}, + {BTN_1, GPIO_PG13, 1, "gpio-keys: BTN1"}, +}; + +static struct gpio_keys_platform_data bfin_gpio_keys_data = { + .buttons = bfin_gpio_keys_table, + .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table), +}; + +static struct platform_device bfin_device_gpiokeys = { + .name = "gpio-keys", + .dev = { + .platform_data = &bfin_gpio_keys_data, + }, +}; +#endif + static struct platform_device *stamp_devices[] __initdata = { #if defined(CONFIG_MTD_NAND_BF5XX) || defined(CONFIG_MTD_NAND_BF5XX_MODULE) &bf5xx_nand_device, @@ -739,6 +825,10 @@ static struct platform_device *stamp_devices[] __initdata = { &isp1362_hcd_device, #endif +#if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE) + &musb_device, +#endif + #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE) &smc91x_device, #endif @@ -763,6 +853,10 @@ static struct platform_device *stamp_devices[] __initdata = { &bfin_fb_device, #endif +#if defined(CONFIG_FB_BFIN_T350MCQB) || defined(CONFIG_FB_BFIN_T350MCQB_MODULE) + &bf52x_t350mcqb_device, +#endif + #if defined(CONFIG_FB_BFIN_7393) || defined(CONFIG_FB_BFIN_7393_MODULE) &bfin_fb_adv7393_device, #endif @@ -783,6 +877,10 @@ static struct platform_device *stamp_devices[] __initdata = { #if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE) &bfin_pata_device, #endif + +#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE) + &bfin_device_gpiokeys, +#endif }; static int __init stamp_init(void) -- cgit v0.10.2 From 50657afdd95a595a68d4ef420300638c0880db37 Mon Sep 17 00:00:00 2001 From: Michael Hennerich Date: Mon, 24 Dec 2007 00:16:01 +0800 Subject: [Blackfin] arch: Trash bf54x-hcd driver - we use the musb driver Signed-off-by: Michael Hennerich Signed-off-by: Bryan Wu diff --git a/arch/blackfin/mach-bf548/boards/ezkit.c b/arch/blackfin/mach-bf548/boards/ezkit.c index d37d665..4d966eb 100644 --- a/arch/blackfin/mach-bf548/boards/ezkit.c +++ b/arch/blackfin/mach-bf548/boards/ezkit.c @@ -206,23 +206,6 @@ static struct platform_device smsc911x_device = { }; #endif -#if defined(CONFIG_USB_BF54x_HCD) || defined(CONFIG_USB_BF54x_HCD_MODULE) -static struct resource bf54x_hcd_resources[] = { - { - .start = 0xFFC03C00, - .end = 0xFFC040FF, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device bf54x_hcd = { - .name = "bf54x-hcd", - .id = 0, - .num_resources = ARRAY_SIZE(bf54x_hcd_resources), - .resource = bf54x_hcd_resources, -}; -#endif - #if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE) static struct resource musb_resources[] = { [0] = { @@ -548,10 +531,6 @@ static struct platform_device *ezkit_devices[] __initdata = { &smsc911x_device, #endif -#if defined(CONFIG_USB_BF54x_HCD) || defined(CONFIG_USB_BF54x_HCD_MODULE) - &bf54x_hcd, -#endif - #if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE) &musb_device, #endif -- cgit v0.10.2 From f31db2a8e824de67b3480c1502d70a9c902c7c1b Mon Sep 17 00:00:00 2001 From: Bryan Wu Date: Thu, 24 Jan 2008 16:14:35 +0800 Subject: [Blackfin] arch: update defconfig of boards Signed-off-by: Michael Hennerich Signed-off-by: Bryan Wu diff --git a/arch/blackfin/configs/BF527-EZKIT_defconfig b/arch/blackfin/configs/BF527-EZKIT_defconfig index fa6eb4e..d59ee15 100644 --- a/arch/blackfin/configs/BF527-EZKIT_defconfig +++ b/arch/blackfin/configs/BF527-EZKIT_defconfig @@ -1,6 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.22.12 +# Linux kernel version: 2.6.22.14 +# Thu Nov 29 17:32:47 2007 # # CONFIG_MMU is not set # CONFIG_FPU is not set @@ -153,8 +154,8 @@ CONFIG_BFIN527_EZKIT=y CONFIG_BF527_SPORT0_PORTG=y CONFIG_BF527_SPORT0_TSCLK_PG10=y # CONFIG_BF527_SPORT0_TSCLK_PG14 is not set -# CONFIG_BF527_UART1_PORTF is not set -CONFIG_BF527_UART1_PORTG=y +CONFIG_BF527_UART1_PORTF=y +# CONFIG_BF527_UART1_PORTG is not set # CONFIG_BF527_NAND_D_PORTF is not set CONFIG_BF527_NAND_D_PORTH=y @@ -232,7 +233,7 @@ CONFIG_CLKIN_HZ=25000000 # CONFIG_BFIN_KERNEL_CLOCK is not set CONFIG_MAX_VCO_HZ=600000000 CONFIG_MIN_VCO_HZ=50000000 -CONFIG_MAX_SCLK_HZ=133000000 +CONFIG_MAX_SCLK_HZ=133333333 CONFIG_MIN_SCLK_HZ=27000000 # @@ -626,8 +627,8 @@ CONFIG_BFIN_MAC_RMII=y # CONFIG_SMSC911X is not set # CONFIG_DM9000 is not set CONFIG_NETDEV_1000=y -CONFIG_NETDEV_10000=y # CONFIG_AX88180 is not set +CONFIG_NETDEV_10000=y # # Wireless LAN @@ -1183,7 +1184,7 @@ CONFIG_NLS_DEFAULT="iso8859-1" # # CONFIG_PRINTK_TIME is not set CONFIG_ENABLE_MUST_CHECK=y -CONFIG_MAGIC_SYSRQ=y +# CONFIG_MAGIC_SYSRQ is not set # CONFIG_UNUSED_SYMBOLS is not set CONFIG_DEBUG_FS=y # CONFIG_HEADERS_CHECK is not set @@ -1208,7 +1209,7 @@ CONFIG_ACCESS_CHECK=y # CONFIG_KEYS is not set CONFIG_SECURITY=y # CONFIG_SECURITY_NETWORK is not set -CONFIG_SECURITY_CAPABILITIES=y +CONFIG_SECURITY_CAPABILITIES=m # # Cryptographic options @@ -1219,7 +1220,7 @@ CONFIG_SECURITY_CAPABILITIES=y # Library routines # CONFIG_BITREVERSE=y -# CONFIG_CRC_CCITT is not set +CONFIG_CRC_CCITT=m # CONFIG_CRC16 is not set # CONFIG_CRC_ITU_T is not set CONFIG_CRC32=y diff --git a/arch/blackfin/configs/BF533-EZKIT_defconfig b/arch/blackfin/configs/BF533-EZKIT_defconfig index 4fdb493..811711f 100644 --- a/arch/blackfin/configs/BF533-EZKIT_defconfig +++ b/arch/blackfin/configs/BF533-EZKIT_defconfig @@ -1,6 +1,6 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.22.12 +# Linux kernel version: 2.6.22.16 # # CONFIG_MMU is not set # CONFIG_FPU is not set @@ -115,7 +115,10 @@ CONFIG_PREEMPT_VOLUNTARY=y # Processor and Board Settings # # CONFIG_BF522 is not set +# CONFIG_BF523 is not set +# CONFIG_BF524 is not set # CONFIG_BF525 is not set +# CONFIG_BF526 is not set # CONFIG_BF527 is not set # CONFIG_BF531 is not set # CONFIG_BF532 is not set @@ -194,7 +197,7 @@ CONFIG_CLKIN_HZ=27000000 # CONFIG_BFIN_KERNEL_CLOCK is not set CONFIG_MAX_VCO_HZ=750000000 CONFIG_MIN_VCO_HZ=50000000 -CONFIG_MAX_SCLK_HZ=133000000 +CONFIG_MAX_SCLK_HZ=133333333 CONFIG_MIN_SCLK_HZ=27000000 # @@ -267,6 +270,7 @@ CONFIG_BFIN_DCACHE=y # CONFIG_BFIN_WB is not set CONFIG_BFIN_WT=y CONFIG_L1_MAX_PIECE=16 +# CONFIG_MPU is not set # # Asynchonous Memory Configuration @@ -321,7 +325,7 @@ CONFIG_PM=y CONFIG_PM_WAKEUP_GPIO_BY_SIC_IWR=y # CONFIG_PM_WAKEUP_BY_GPIO is not set # CONFIG_PM_WAKEUP_GPIO_API is not set -CONFIG_PM_WAKEUP_SIC_IWR=0x100000 +CONFIG_PM_WAKEUP_SIC_IWR=0x80 # # CPU Frequency scaling @@ -510,7 +514,6 @@ CONFIG_MTD_CFI_I2=y # CONFIG_MTD_CFI_INTELEXT is not set # CONFIG_MTD_CFI_AMDSTD is not set # CONFIG_MTD_CFI_STAA is not set -CONFIG_MTD_MW320D=m CONFIG_MTD_RAM=y CONFIG_MTD_ROM=m # CONFIG_MTD_ABSENT is not set @@ -520,9 +523,6 @@ CONFIG_MTD_ROM=m # CONFIG_MTD_COMPLEX_MAPPINGS=y # CONFIG_MTD_PHYSMAP is not set -CONFIG_MTD_BF5xx=m -CONFIG_BFIN_FLASH_SIZE=0x400000 -CONFIG_EBIU_FLASH_BASE=0x20000000 # CONFIG_MTD_UCLINUX is not set # CONFIG_MTD_PLATRAM is not set @@ -610,8 +610,8 @@ CONFIG_SMC91X=y # CONFIG_SMSC911X is not set # CONFIG_DM9000 is not set CONFIG_NETDEV_1000=y -CONFIG_NETDEV_10000=y # CONFIG_AX88180 is not set +CONFIG_NETDEV_10000=y # # Wireless LAN @@ -680,7 +680,6 @@ CONFIG_INPUT_EVDEV=m CONFIG_BFIN_SPORT=y # CONFIG_BFIN_TIMER_LATENCY is not set # CONFIG_AD5304 is not set -# CONFIG_BF5xx_FBDMA is not set # CONFIG_VT is not set # CONFIG_SERIAL_NONSTANDARD is not set diff --git a/arch/blackfin/configs/BF533-STAMP_defconfig b/arch/blackfin/configs/BF533-STAMP_defconfig index b04e8e5..9b7123c 100644 --- a/arch/blackfin/configs/BF533-STAMP_defconfig +++ b/arch/blackfin/configs/BF533-STAMP_defconfig @@ -1,6 +1,6 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.22.12 +# Linux kernel version: 2.6.22.16 # # CONFIG_MMU is not set # CONFIG_FPU is not set @@ -115,7 +115,10 @@ CONFIG_PREEMPT_VOLUNTARY=y # Processor and Board Settings # # CONFIG_BF522 is not set +# CONFIG_BF523 is not set +# CONFIG_BF524 is not set # CONFIG_BF525 is not set +# CONFIG_BF526 is not set # CONFIG_BF527 is not set # CONFIG_BF531 is not set # CONFIG_BF532 is not set @@ -140,7 +143,6 @@ CONFIG_BF_REV_0_3=y CONFIG_BF53x=y CONFIG_BFIN_SINGLE_CORE=y CONFIG_MEM_MT48LC64M4A2FB_7E=y -CONFIG_BFIN_SHARED_FLASH_ENET=y # CONFIG_BFIN533_EZKIT is not set CONFIG_BFIN533_STAMP=y # CONFIG_BFIN533_BLUETECHNIX_CM is not set @@ -195,7 +197,7 @@ CONFIG_CLKIN_HZ=11059200 # CONFIG_BFIN_KERNEL_CLOCK is not set CONFIG_MAX_VCO_HZ=750000000 CONFIG_MIN_VCO_HZ=50000000 -CONFIG_MAX_SCLK_HZ=133000000 +CONFIG_MAX_SCLK_HZ=133333333 CONFIG_MIN_SCLK_HZ=27000000 # @@ -215,18 +217,10 @@ CONFIG_MEM_ADD_WIDTH=11 CONFIG_ENET_FLASH_PIN=0 CONFIG_BOOT_LOAD=0x1000 -# -# LED Status Indicators -# -# CONFIG_BFIN_ALIVE_LED is not set -# CONFIG_BFIN_IDLE_LED is not set + CONFIG_BFIN_SCRATCH_REG_RETN=y # CONFIG_BFIN_SCRATCH_REG_RETE is not set # CONFIG_BFIN_SCRATCH_REG_CYCLES is not set -CONFIG_BFIN_ALIVE_LED_PORT=0xFFC00700 -CONFIG_BFIN_ALIVE_LED_DPORT=0xFFC00730 -CONFIG_BFIN_IDLE_LED_PORT=0xFFC00700 -CONFIG_BFIN_IDLE_LED_DPORT=0xFFC00730 # # Blackfin Kernel Optimizations @@ -279,6 +273,7 @@ CONFIG_BFIN_DCACHE=y # CONFIG_BFIN_WB is not set CONFIG_BFIN_WT=y CONFIG_L1_MAX_PIECE=16 +# CONFIG_MPU is not set # # Asynchonous Memory Configuration @@ -333,7 +328,7 @@ CONFIG_PM=y CONFIG_PM_WAKEUP_GPIO_BY_SIC_IWR=y # CONFIG_PM_WAKEUP_BY_GPIO is not set # CONFIG_PM_WAKEUP_GPIO_API is not set -CONFIG_PM_WAKEUP_SIC_IWR=0x100000 +CONFIG_PM_WAKEUP_SIC_IWR=0x80 # # CPU Frequency scaling @@ -522,7 +517,6 @@ CONFIG_MTD_CFI_I2=y # CONFIG_MTD_CFI_INTELEXT is not set # CONFIG_MTD_CFI_AMDSTD is not set # CONFIG_MTD_CFI_STAA is not set -CONFIG_MTD_MW320D=m CONFIG_MTD_RAM=y CONFIG_MTD_ROM=m # CONFIG_MTD_ABSENT is not set @@ -532,17 +526,6 @@ CONFIG_MTD_ROM=m # CONFIG_MTD_COMPLEX_MAPPINGS=y # CONFIG_MTD_PHYSMAP is not set -CONFIG_MTD_BF5xx=m -CONFIG_BFIN_FLASH_SIZE=0x400000 -CONFIG_EBIU_FLASH_BASE=0x20000000 - -# -# FLASH_EBIU_AMBCTL Control -# -CONFIG_BFIN_FLASH_BANK_0=0x7BB0 -CONFIG_BFIN_FLASH_BANK_1=0x7BB0 -CONFIG_BFIN_FLASH_BANK_2=0x7BB0 -CONFIG_BFIN_FLASH_BANK_3=0x7BB0 # CONFIG_MTD_UCLINUX is not set # CONFIG_MTD_PLATRAM is not set @@ -630,8 +613,8 @@ CONFIG_SMC91X=y # CONFIG_SMSC911X is not set # CONFIG_DM9000 is not set CONFIG_NETDEV_1000=y -CONFIG_NETDEV_10000=y # CONFIG_AX88180 is not set +CONFIG_NETDEV_10000=y # # Wireless LAN @@ -687,7 +670,6 @@ CONFIG_INPUT_MISC=y # CONFIG_INPUT_POWERMATE is not set # CONFIG_INPUT_YEALINK is not set # CONFIG_INPUT_UINPUT is not set -# CONFIG_BF53X_PFBUTTONS is not set CONFIG_TWI_KEYPAD=m CONFIG_BFIN_TWIKEYPAD_IRQ_PFX=39 @@ -711,8 +693,6 @@ CONFIG_BFIN_SPORT=y CONFIG_TWI_LCD=m CONFIG_TWI_LCD_SLAVE_ADDR=34 # CONFIG_AD5304 is not set -# CONFIG_BF5xx_TEA5764 is not set -# CONFIG_BF5xx_FBDMA is not set # CONFIG_VT is not set # CONFIG_SERIAL_NONSTANDARD is not set @@ -778,7 +758,6 @@ CONFIG_I2C_ALGOBIT=m # # I2C Hardware Bus support # -# CONFIG_I2C_BLACKFIN_GPIO is not set # CONFIG_I2C_GPIO is not set # CONFIG_I2C_OCORES is not set # CONFIG_I2C_PARPORT_LIGHT is not set diff --git a/arch/blackfin/configs/BF537-STAMP_defconfig b/arch/blackfin/configs/BF537-STAMP_defconfig index f812b66..b37ccc6 100644 --- a/arch/blackfin/configs/BF537-STAMP_defconfig +++ b/arch/blackfin/configs/BF537-STAMP_defconfig @@ -1,6 +1,6 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.22.12 +# Linux kernel version: 2.6.22.16 # # CONFIG_MMU is not set # CONFIG_FPU is not set @@ -115,7 +115,10 @@ CONFIG_PREEMPT_VOLUNTARY=y # Processor and Board Settings # # CONFIG_BF522 is not set +# CONFIG_BF523 is not set +# CONFIG_BF524 is not set # CONFIG_BF525 is not set +# CONFIG_BF526 is not set # CONFIG_BF527 is not set # CONFIG_BF531 is not set # CONFIG_BF532 is not set @@ -170,6 +173,7 @@ CONFIG_IRQ_WATCH=13 CONFIG_BFIN537_STAMP=y # CONFIG_BFIN537_BLUETECHNIX_CM is not set # CONFIG_PNAV10 is not set +# CONFIG_CAMSIG_MINOTAUR is not set # CONFIG_GENERIC_BF537_BOARD is not set # @@ -201,7 +205,7 @@ CONFIG_CLKIN_HZ=25000000 # CONFIG_BFIN_KERNEL_CLOCK is not set CONFIG_MAX_VCO_HZ=600000000 CONFIG_MIN_VCO_HZ=50000000 -CONFIG_MAX_SCLK_HZ=133000000 +CONFIG_MAX_SCLK_HZ=133333333 CONFIG_MIN_SCLK_HZ=27000000 # @@ -274,6 +278,7 @@ CONFIG_BFIN_DCACHE=y # CONFIG_BFIN_WB is not set CONFIG_BFIN_WT=y CONFIG_L1_MAX_PIECE=16 +# CONFIG_MPU is not set # # Asynchonous Memory Configuration @@ -328,7 +333,7 @@ CONFIG_PM=y CONFIG_PM_WAKEUP_GPIO_BY_SIC_IWR=y # CONFIG_PM_WAKEUP_BY_GPIO is not set # CONFIG_PM_WAKEUP_GPIO_API is not set -CONFIG_PM_WAKEUP_SIC_IWR=0x80000000 +CONFIG_PM_WAKEUP_SIC_IWR=0x8 # # CPU Frequency scaling @@ -483,7 +488,7 @@ CONFIG_MTD=y # CONFIG_MTD_CONCAT is not set CONFIG_MTD_PARTITIONS=y # CONFIG_MTD_REDBOOT_PARTS is not set -# CONFIG_MTD_CMDLINE_PARTS is not set +CONFIG_MTD_CMDLINE_PARTS=y # # User Modules And Translation Layers @@ -500,8 +505,8 @@ CONFIG_MTD_BLOCK=y # # RAM/ROM/Flash chip drivers # -# CONFIG_MTD_CFI is not set -CONFIG_MTD_JEDECPROBE=m +CONFIG_MTD_CFI=m +# CONFIG_MTD_JEDECPROBE is not set CONFIG_MTD_GEN_PROBE=m # CONFIG_MTD_CFI_ADV_OPTIONS is not set CONFIG_MTD_MAP_BANK_WIDTH_1=y @@ -515,9 +520,9 @@ CONFIG_MTD_CFI_I2=y # CONFIG_MTD_CFI_I4 is not set # CONFIG_MTD_CFI_I8 is not set # CONFIG_MTD_CFI_INTELEXT is not set -# CONFIG_MTD_CFI_AMDSTD is not set +CONFIG_MTD_CFI_AMDSTD=m # CONFIG_MTD_CFI_STAA is not set -CONFIG_MTD_MW320D=m +CONFIG_MTD_CFI_UTIL=m CONFIG_MTD_RAM=y CONFIG_MTD_ROM=m # CONFIG_MTD_ABSENT is not set @@ -525,11 +530,11 @@ CONFIG_MTD_ROM=m # # Mapping drivers for chip access # -CONFIG_MTD_COMPLEX_MAPPINGS=y -# CONFIG_MTD_PHYSMAP is not set -CONFIG_MTD_BF5xx=m -CONFIG_BFIN_FLASH_SIZE=0x400000 -CONFIG_EBIU_FLASH_BASE=0x20000000 +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +CONFIG_MTD_PHYSMAP=m +CONFIG_MTD_PHYSMAP_START=0x20000000 +CONFIG_MTD_PHYSMAP_LEN=0x0 +CONFIG_MTD_PHYSMAP_BANKWIDTH=2 # CONFIG_MTD_UCLINUX is not set # CONFIG_MTD_PLATRAM is not set @@ -647,8 +652,8 @@ CONFIG_BFIN_RX_DESC_NUM=20 # CONFIG_SMSC911X is not set # CONFIG_DM9000 is not set CONFIG_NETDEV_1000=y -CONFIG_NETDEV_10000=y # CONFIG_AX88180 is not set +CONFIG_NETDEV_10000=y # # Wireless LAN @@ -704,7 +709,6 @@ CONFIG_INPUT_MISC=y # CONFIG_INPUT_POWERMATE is not set # CONFIG_INPUT_YEALINK is not set # CONFIG_INPUT_UINPUT is not set -# CONFIG_BF53X_PFBUTTONS is not set CONFIG_TWI_KEYPAD=m CONFIG_BFIN_TWIKEYPAD_IRQ_PFX=72 @@ -728,8 +732,6 @@ CONFIG_BFIN_SPORT=y CONFIG_TWI_LCD=m CONFIG_TWI_LCD_SLAVE_ADDR=34 # CONFIG_AD5304 is not set -# CONFIG_BF5xx_TEA5764 is not set -# CONFIG_BF5xx_FBDMA is not set # CONFIG_VT is not set # CONFIG_SERIAL_NONSTANDARD is not set @@ -802,7 +804,6 @@ CONFIG_I2C_CHARDEV=m # # I2C Hardware Bus support # -# CONFIG_I2C_BLACKFIN_GPIO is not set CONFIG_I2C_BLACKFIN_TWI=m CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=50 # CONFIG_I2C_GPIO is not set @@ -957,6 +958,7 @@ CONFIG_LQ035_SLAVE_ADDR=0x58 # CONFIG_FB_BFIN_LANDSCAPE is not set # CONFIG_FB_BFIN_BGR is not set # CONFIG_FB_BFIN_T350MCQB is not set +# CONFIG_FB_HITACHI_TX09 is not set # CONFIG_FB_S1D13XXX is not set # CONFIG_FB_VIRTUAL is not set # CONFIG_LOGO is not set @@ -1008,12 +1010,22 @@ CONFIG_SND_BFIN_AD73311_SE=4 # # System on Chip audio support # -# CONFIG_SND_SOC is not set +CONFIG_SND_SOC_AC97_BUS=y +CONFIG_SND_SOC=m +CONFIG_SND_BF5XX_SOC=m +CONFIG_SND_BF5XX_SOC_AC97=m +# CONFIG_SND_BF5XX_SOC_WM8750 is not set +# CONFIG_SND_BF5XX_SOC_WM8731 is not set +CONFIG_SND_BF5XX_SOC_BF5xx=m +CONFIG_SND_BF5XX_SPORT_NUM=0 +# CONFIG_SND_BF5XX_HAVE_COLD_RESET is not set +CONFIG_SND_SOC_AD1980=m # # Open Sound System # # CONFIG_SOUND_PRIME is not set +CONFIG_AC97_BUS=m # # HID Devices diff --git a/arch/blackfin/configs/BF548-EZKIT_defconfig b/arch/blackfin/configs/BF548-EZKIT_defconfig index 48367cc9..fd70216 100644 --- a/arch/blackfin/configs/BF548-EZKIT_defconfig +++ b/arch/blackfin/configs/BF548-EZKIT_defconfig @@ -1,6 +1,6 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.22.12 +# Linux kernel version: 2.6.22.16 # # CONFIG_MMU is not set # CONFIG_FPU is not set @@ -115,7 +115,10 @@ CONFIG_PREEMPT_VOLUNTARY=y # Processor and Board Settings # # CONFIG_BF522 is not set +# CONFIG_BF523 is not set +# CONFIG_BF524 is not set # CONFIG_BF525 is not set +# CONFIG_BF526 is not set # CONFIG_BF527 is not set # CONFIG_BF531 is not set # CONFIG_BF532 is not set @@ -126,8 +129,8 @@ CONFIG_PREEMPT_VOLUNTARY=y # CONFIG_BF542 is not set # CONFIG_BF544 is not set # CONFIG_BF547 is not set -# CONFIG_BF548 is not set -CONFIG_BF549=y +CONFIG_BF548=y +# CONFIG_BF549 is not set # CONFIG_BF561 is not set CONFIG_BF_REV_0_0=y # CONFIG_BF_REV_0_1 is not set @@ -265,9 +268,9 @@ CONFIG_PINT3_ASSIGN=0x02020303 # CONFIG_CLKIN_HZ=25000000 # CONFIG_BFIN_KERNEL_CLOCK is not set -CONFIG_MAX_VCO_HZ=533000000 +CONFIG_MAX_VCO_HZ=600000000 CONFIG_MIN_VCO_HZ=50000000 -CONFIG_MAX_SCLK_HZ=133000000 +CONFIG_MAX_SCLK_HZ=133333333 CONFIG_MIN_SCLK_HZ=27000000 # @@ -283,7 +286,8 @@ CONFIG_HZ=250 # Memory Setup # CONFIG_MEM_SIZE=64 -CONFIG_MEM_ADD_WIDTH=10 +# CONFIG_MEM_MT46V32M16_6T is not set +CONFIG_MEM_MT46V32M16_5B=y CONFIG_BOOT_LOAD=0x1000 CONFIG_BFIN_SCRATCH_REG_RETN=y # CONFIG_BFIN_SCRATCH_REG_RETE is not set @@ -340,6 +344,7 @@ CONFIG_BFIN_DCACHE=y # CONFIG_BFIN_WB is not set CONFIG_BFIN_WT=y CONFIG_L1_MAX_PIECE=16 +# CONFIG_MPU is not set # # Asynchonous Memory Configuration @@ -349,6 +354,7 @@ CONFIG_L1_MAX_PIECE=16 # EBIU_AMGCTL Global Control # CONFIG_C_AMCKEN=y +# CONFIG_C_CDPRIO is not set # CONFIG_C_AMBEN is not set # CONFIG_C_AMBEN_B0 is not set # CONFIG_C_AMBEN_B0_B1 is not set @@ -362,9 +368,9 @@ CONFIG_BANK_0=0x7BB0 CONFIG_BANK_1=0x5554 CONFIG_BANK_2=0x7BB0 CONFIG_BANK_3=0x99B3 -CONFIG_EBUI_MBSCTLVAL=0x0 -CONFIG_EBUI_MODEVAL=0x1 -CONFIG_EBUI_FCTLVAL=0x6 +CONFIG_EBIU_MBSCTLVAL=0x0 +CONFIG_EBIU_MODEVAL=0x1 +CONFIG_EBIU_FCTLVAL=0x6 # # Bus options (PCI, PCMCIA, EISA, MCA, ISA) @@ -537,7 +543,6 @@ CONFIG_MTD_CFI_I2=y CONFIG_MTD_CFI_INTELEXT=y # CONFIG_MTD_CFI_AMDSTD is not set # CONFIG_MTD_CFI_STAA is not set -# CONFIG_MTD_MW320D is not set CONFIG_MTD_CFI_UTIL=y CONFIG_MTD_RAM=y # CONFIG_MTD_ROM is not set @@ -549,9 +554,8 @@ CONFIG_MTD_RAM=y CONFIG_MTD_COMPLEX_MAPPINGS=y CONFIG_MTD_PHYSMAP=y CONFIG_MTD_PHYSMAP_START=0x20000000 -CONFIG_MTD_PHYSMAP_LEN=0x400000 +CONFIG_MTD_PHYSMAP_LEN=0 CONFIG_MTD_PHYSMAP_BANKWIDTH=2 -# CONFIG_MTD_BF5xx is not set # CONFIG_MTD_UCLINUX is not set # CONFIG_MTD_PLATRAM is not set @@ -690,8 +694,8 @@ CONFIG_MII=y CONFIG_SMSC911X=y # CONFIG_DM9000 is not set CONFIG_NETDEV_1000=y -CONFIG_NETDEV_10000=y # CONFIG_AX88180 is not set +CONFIG_NETDEV_10000=y # # Wireless LAN @@ -719,7 +723,7 @@ CONFIG_NETDEV_10000=y # # Input device support # -CONFIG_INPUT=m +CONFIG_INPUT=y # CONFIG_INPUT_FF_MEMLESS is not set # CONFIG_INPUT_POLLDEV is not set @@ -745,7 +749,8 @@ CONFIG_INPUT_KEYBOARD=y # CONFIG_KEYBOARD_NEWTON is not set # CONFIG_KEYBOARD_STOWAWAY is not set # CONFIG_KEYBOARD_GPIO is not set -CONFIG_KEYBOARD_BFIN=m +CONFIG_KEYBOARD_BFIN=y +# CONFIG_KEYBOARD_OPENCORES is not set # CONFIG_INPUT_MOUSE is not set # CONFIG_INPUT_JOYSTICK is not set # CONFIG_INPUT_TABLET is not set @@ -768,7 +773,6 @@ CONFIG_INPUT_MISC=y # CONFIG_INPUT_POWERMATE is not set # CONFIG_INPUT_YEALINK is not set # CONFIG_INPUT_UINPUT is not set -# CONFIG_BF53X_PFBUTTONS is not set # CONFIG_TWI_KEYPAD is not set # @@ -786,13 +790,16 @@ CONFIG_INPUT_MISC=y # CONFIG_BF5xx_PPIFCD is not set # CONFIG_BFIN_SIMPLE_TIMER is not set # CONFIG_BF5xx_PPI is not set +CONFIG_BFIN_OTP=y +# CONFIG_BFIN_OTP_WRITE_ENABLE is not set # CONFIG_BFIN_SPORT is not set # CONFIG_BFIN_TIMER_LATENCY is not set # CONFIG_TWI_LCD is not set # CONFIG_AD5304 is not set -# CONFIG_BF5xx_TEA5764 is not set -# CONFIG_BF5xx_FBDMA is not set -# CONFIG_VT is not set +CONFIG_VT=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set # CONFIG_SERIAL_NONSTANDARD is not set # @@ -858,7 +865,6 @@ CONFIG_I2C_CHARDEV=y # # I2C Hardware Bus support # -# CONFIG_I2C_BLACKFIN_GPIO is not set CONFIG_I2C_BLACKFIN_TWI=y CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=50 # CONFIG_I2C_GPIO is not set @@ -976,12 +982,12 @@ CONFIG_DAB=y # # CONFIG_DISPLAY_SUPPORT is not set # CONFIG_VGASTATE is not set -CONFIG_FB=m +CONFIG_FB=y CONFIG_FIRMWARE_EDID=y # CONFIG_FB_DDC is not set -CONFIG_FB_CFB_FILLRECT=m -CONFIG_FB_CFB_COPYAREA=m -CONFIG_FB_CFB_IMAGEBLIT=m +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_IMAGEBLIT=y # CONFIG_FB_SYS_FILLRECT is not set # CONFIG_FB_SYS_COPYAREA is not set # CONFIG_FB_SYS_IMAGEBLIT is not set @@ -998,11 +1004,34 @@ CONFIG_FB_DEFERRED_IO=y # # CONFIG_FB_BFIN_7171 is not set # CONFIG_FB_BFIN_7393 is not set -CONFIG_FB_BF54X_LQ043=m +CONFIG_FB_BF54X_LQ043=y # CONFIG_FB_BFIN_T350MCQB is not set # CONFIG_FB_S1D13XXX is not set # CONFIG_FB_VIRTUAL is not set -# CONFIG_LOGO is not set + +# +# Console display driver support +# +CONFIG_DUMMY_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE=y +# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set +CONFIG_FONTS=y +# CONFIG_FONT_8x8 is not set +# CONFIG_FONT_8x16 is not set +CONFIG_FONT_6x11=y +# CONFIG_FONT_7x14 is not set +# CONFIG_FONT_PEARL_8x8 is not set +# CONFIG_FONT_ACORN_8x8 is not set +# CONFIG_FONT_MINI_4x6 is not set +# CONFIG_FONT_SUN8x16 is not set +# CONFIG_FONT_SUN12x22 is not set +# CONFIG_FONT_10x18 is not set +CONFIG_LOGO=y +# CONFIG_LOGO_LINUX_MONO is not set +# CONFIG_LOGO_LINUX_VGA16 is not set +# CONFIG_LOGO_LINUX_CLUT224 is not set +# CONFIG_LOGO_BLACKFIN_VGA16 is not set +CONFIG_LOGO_BLACKFIN_CLUT224=y # # Sound @@ -1051,7 +1080,8 @@ CONFIG_SND_BF5XX_SOC_BF548_EZKIT=y # CONFIG_SND_BF5XX_SOC_WM8750 is not set # CONFIG_SND_BF5XX_SOC_WM8731 is not set CONFIG_SND_BF5XX_SPORT_NUM=0 -# CONFIG_SND_BF5XX_HAVE_COLD_RESET is not set +CONFIG_SND_BF5XX_HAVE_COLD_RESET=y +CONFIG_SND_BF5XX_RESET_GPIO_NUM=19 CONFIG_SND_SOC_AD1980=y # @@ -1403,7 +1433,7 @@ CONFIG_NLS_UTF8=m # # CONFIG_PRINTK_TIME is not set CONFIG_ENABLE_MUST_CHECK=y -CONFIG_MAGIC_SYSRQ=y +# CONFIG_MAGIC_SYSRQ is not set # CONFIG_UNUSED_SYMBOLS is not set CONFIG_DEBUG_FS=y # CONFIG_HEADERS_CHECK is not set @@ -1428,7 +1458,7 @@ CONFIG_ACCESS_CHECK=y # CONFIG_KEYS is not set CONFIG_SECURITY=y # CONFIG_SECURITY_NETWORK is not set -CONFIG_SECURITY_CAPABILITIES=y +CONFIG_SECURITY_CAPABILITIES=m # # Cryptographic options @@ -1439,7 +1469,7 @@ CONFIG_SECURITY_CAPABILITIES=y # Library routines # CONFIG_BITREVERSE=y -# CONFIG_CRC_CCITT is not set +CONFIG_CRC_CCITT=m # CONFIG_CRC16 is not set # CONFIG_CRC_ITU_T is not set CONFIG_CRC32=y diff --git a/arch/blackfin/configs/BF561-EZKIT_defconfig b/arch/blackfin/configs/BF561-EZKIT_defconfig index e9f100b..8546994 100644 --- a/arch/blackfin/configs/BF561-EZKIT_defconfig +++ b/arch/blackfin/configs/BF561-EZKIT_defconfig @@ -1,6 +1,6 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.22.12 +# Linux kernel version: 2.6.22.16 # # CONFIG_MMU is not set # CONFIG_FPU is not set @@ -115,7 +115,10 @@ CONFIG_PREEMPT_VOLUNTARY=y # Processor and Board Settings # # CONFIG_BF522 is not set +# CONFIG_BF523 is not set +# CONFIG_BF524 is not set # CONFIG_BF525 is not set +# CONFIG_BF526 is not set # CONFIG_BF527 is not set # CONFIG_BF531 is not set # CONFIG_BF532 is not set @@ -238,7 +241,7 @@ CONFIG_CLKIN_HZ=30000000 # CONFIG_BFIN_KERNEL_CLOCK is not set CONFIG_MAX_VCO_HZ=600000000 CONFIG_MIN_VCO_HZ=50000000 -CONFIG_MAX_SCLK_HZ=133000000 +CONFIG_MAX_SCLK_HZ=133333333 CONFIG_MIN_SCLK_HZ=27000000 # @@ -311,6 +314,7 @@ CONFIG_BFIN_DCACHE=y # CONFIG_BFIN_WB is not set CONFIG_BFIN_WT=y CONFIG_L1_MAX_PIECE=16 +# CONFIG_MPU is not set # # Asynchonous Memory Configuration @@ -512,7 +516,7 @@ CONFIG_MTD=y # CONFIG_MTD_CONCAT is not set CONFIG_MTD_PARTITIONS=y # CONFIG_MTD_REDBOOT_PARTS is not set -# CONFIG_MTD_CMDLINE_PARTS is not set +CONFIG_MTD_CMDLINE_PARTS=y # # User Modules And Translation Layers @@ -529,8 +533,8 @@ CONFIG_MTD_BLOCK=y # # RAM/ROM/Flash chip drivers # -# CONFIG_MTD_CFI is not set -CONFIG_MTD_JEDECPROBE=m +CONFIG_MTD_CFI=m +# CONFIG_MTD_JEDECPROBE is not set CONFIG_MTD_GEN_PROBE=m # CONFIG_MTD_CFI_ADV_OPTIONS is not set CONFIG_MTD_MAP_BANK_WIDTH_1=y @@ -544,9 +548,9 @@ CONFIG_MTD_CFI_I2=y # CONFIG_MTD_CFI_I4 is not set # CONFIG_MTD_CFI_I8 is not set # CONFIG_MTD_CFI_INTELEXT is not set -# CONFIG_MTD_CFI_AMDSTD is not set +CONFIG_MTD_CFI_AMDSTD=m # CONFIG_MTD_CFI_STAA is not set -CONFIG_MTD_MW320D=m +CONFIG_MTD_CFI_UTIL=m CONFIG_MTD_RAM=y CONFIG_MTD_ROM=m # CONFIG_MTD_ABSENT is not set @@ -554,12 +558,11 @@ CONFIG_MTD_ROM=m # # Mapping drivers for chip access # -CONFIG_MTD_COMPLEX_MAPPINGS=y -# CONFIG_MTD_PHYSMAP is not set -# CONFIG_MTD_EZKIT561 is not set -CONFIG_MTD_BF5xx=m -CONFIG_BFIN_FLASH_SIZE=0x0400000 -CONFIG_EBIU_FLASH_BASE=0x20000000 +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +CONFIG_MTD_PHYSMAP=m +CONFIG_MTD_PHYSMAP_START=0x20000000 +CONFIG_MTD_PHYSMAP_LEN=0x0 +CONFIG_MTD_PHYSMAP_BANKWIDTH=2 # CONFIG_MTD_UCLINUX is not set # CONFIG_MTD_PLATRAM is not set @@ -647,8 +650,8 @@ CONFIG_SMC91X=y # CONFIG_SMSC911X is not set # CONFIG_DM9000 is not set CONFIG_NETDEV_1000=y -CONFIG_NETDEV_10000=y # CONFIG_AX88180 is not set +CONFIG_NETDEV_10000=y # # Wireless LAN @@ -717,7 +720,6 @@ CONFIG_INPUT_EVDEV=m # CONFIG_BFIN_SPORT is not set # CONFIG_BFIN_TIMER_LATENCY is not set # CONFIG_AD5304 is not set -# CONFIG_BF5xx_FBDMA is not set # CONFIG_VT is not set # CONFIG_SERIAL_NONSTANDARD is not set -- cgit v0.10.2 From 0e85e3020ebb9a1afdeaa516fe8b8f16087adac1 Mon Sep 17 00:00:00 2001 From: Michael Hennerich Date: Mon, 24 Dec 2007 11:57:47 +0800 Subject: [Blackfin] arch: The BF527 EZkit connects UART1/PORTF Signed-off-by: Michael Hennerich Signed-off-by: Bryan Wu diff --git a/arch/blackfin/mach-bf527/Kconfig b/arch/blackfin/mach-bf527/Kconfig index 5c73683..3cde4be 100644 --- a/arch/blackfin/mach-bf527/Kconfig +++ b/arch/blackfin/mach-bf527/Kconfig @@ -43,7 +43,7 @@ endchoice choice prompt "UART1" - default BF527_UART1_PORTG + default BF527_UART1_PORTF help Select PORT used for UART1. See Hardware Reference Manual -- cgit v0.10.2 From 2935077e06494638a78a02f7b4cf304e4e70eaca Mon Sep 17 00:00:00 2001 From: Bryan Wu Date: Mon, 24 Dec 2007 12:20:19 +0800 Subject: [Blackfin] arch: Fix if/def BUG - and define is multipoint NO Signed-off-by: Michael Hennerich Signed-off-by: Bryan Wu diff --git a/arch/blackfin/mach-bf548/boards/ezkit.c b/arch/blackfin/mach-bf548/boards/ezkit.c index 4d966eb..856b9db 100644 --- a/arch/blackfin/mach-bf548/boards/ezkit.c +++ b/arch/blackfin/mach-bf548/boards/ezkit.c @@ -226,14 +226,14 @@ static struct resource musb_resources[] = { }; static struct musb_hdrc_platform_data musb_plat = { -#ifdef CONFIG_USB_MUSB_OTG +#if defined(CONFIG_USB_MUSB_OTG) .mode = MUSB_OTG, -#elif CONFIG_USB_MUSB_HDRC_HCD +#elif defined(CONFIG_USB_MUSB_HDRC_HCD) .mode = MUSB_HOST, -#elif CONFIG_USB_GADGET_MUSB_HDRC +#elif defined(CONFIG_USB_GADGET_MUSB_HDRC) .mode = MUSB_PERIPHERAL, #endif - .multipoint = 1, + .multipoint = 0, }; static u64 musb_dmamask = ~(u32)0; -- cgit v0.10.2 From 7a5f819187ff827c131721dbba11ad9596ae5e30 Mon Sep 17 00:00:00 2001 From: Javier Herrero Date: Sun, 27 Jan 2008 19:53:08 +0800 Subject: [Blackfin] arch: Added support for OpenCores Keyboard Controller to H8606 board Signed-off-by: Javier Herrero Signed-off-by: Bryan Wu diff --git a/arch/blackfin/mach-bf533/boards/H8606.c b/arch/blackfin/mach-bf533/boards/H8606.c index 675fd1c..a72c7a6 100644 --- a/arch/blackfin/mach-bf533/boards/H8606.c +++ b/arch/blackfin/mach-bf533/boards/H8606.c @@ -346,6 +346,34 @@ static struct platform_device serial8250_device = { #endif +#if defined(CONFIG_KEYBOARD_OPENCORES) || defined(CONFIG_KEYBOARD_OPENCORES_MODULE) + +/* + * Configuration for one OpenCores keyboard controller in FPGA at address 0x20200030, + * interrupt output wired to PF9. Change to suit different FPGA configuration + */ + +static struct resource opencores_kbd_resources[] = { + [0] = { + .start = 0x20200030, + .end = 0x20300030 + 2, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_PF9, + .end = IRQ_PF9, + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE, + }, +}; + +static struct platform_device opencores_kbd_device = { + .id = -1, + .name = "opencores-kbd", + .resource = opencores_kbd_resources, + .num_resources = ARRAY_SIZE(opencores_kbd_resources), +}; +#endif + static struct platform_device *h8606_devices[] __initdata = { #if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE) &rtc_device, @@ -374,6 +402,10 @@ static struct platform_device *h8606_devices[] __initdata = { #if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE) &serial8250_device, #endif + +#if defined(CONFIG_KEYBOARD_OPENCORES) || defined(CONFIG_KEYBOARD_OPENCORES_MODULE) + &opencores_kbd_device, +#endif }; static int __init H8606_init(void) -- cgit v0.10.2 From b8aab6f6dc57ca79661d291af522d2e85156519f Mon Sep 17 00:00:00 2001 From: Cliff Cai Date: Mon, 24 Dec 2007 12:33:20 +0800 Subject: [Blackfin] arch: set default value of DEB_DMA_URGENT to YES to avoid DMA aborting caused by conflict between core and DMA Signed-off-by: Cliff Cai Signed-off-by: Bryan Wu diff --git a/arch/blackfin/mach-bf548/Kconfig b/arch/blackfin/mach-bf548/Kconfig index d8bd3b49..1bfcd8f 100644 --- a/arch/blackfin/mach-bf548/Kconfig +++ b/arch/blackfin/mach-bf548/Kconfig @@ -7,7 +7,7 @@ menu "BF548 Specific Configuration" config DEB_DMA_URGENT bool "DMA has priority over core for ext. accesses" depends on BF54x - default n + default y help Treat any DEB1, DEB2 and DEB3 request as Urgent -- cgit v0.10.2 From 3ca32c1dc62dabe67d7e51f6e8568e3965f52236 Mon Sep 17 00:00:00 2001 From: Bernd Schmidt Date: Mon, 24 Dec 2007 12:40:29 +0800 Subject: [Blackfin] arch: fix up coding style in uaccess.h Signed-off-by: Bernd Schmidt Signed-off-by: Bryan Wu diff --git a/include/asm-blackfin/uaccess.h b/include/asm-blackfin/uaccess.h index 2233f8f..22a410b 100644 --- a/include/asm-blackfin/uaccess.h +++ b/include/asm-blackfin/uaccess.h @@ -31,7 +31,7 @@ static inline void set_fs(mm_segment_t fs) #define VERIFY_READ 0 #define VERIFY_WRITE 1 -#define access_ok(type,addr,size) _access_ok((unsigned long)(addr),(size)) +#define access_ok(type, addr, size) _access_ok((unsigned long)(addr), (size)) static inline int is_in_rom(unsigned long addr) { -- cgit v0.10.2 From 54a1668ce53fe701f1d36651b591ced388e97275 Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Mon, 24 Dec 2007 14:59:03 +0800 Subject: [Blackfin] arch: scrub dead alive/idle LED code if it does get re-added, it needs to be in the boards directory, not common code ... or it needs a re-implementation Signed-off-by: Mike Frysinger Signed-off-by: Bryan Wu diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig index 1364dca..e4ccdcd 100644 --- a/arch/blackfin/Kconfig +++ b/arch/blackfin/Kconfig @@ -463,40 +463,6 @@ config BOOT_LOAD memory region is used to capture NULL pointer references as well as some core kernel functions. -comment "LED Status Indicators" - depends on (BFIN533_STAMP || BFIN533_BLUETECHNIX_CM) - -config BFIN_ALIVE_LED - bool "Enable Board Alive" - depends on (BFIN533_STAMP || BFIN533_BLUETECHNIX_CM) - default n - help - Blink the LEDs you select when the kernel is running. Helps detect - a hung kernel. - -config BFIN_ALIVE_LED_NUM - int "LED" - depends on BFIN_ALIVE_LED - range 1 3 if BFIN533_STAMP - default "3" if BFIN533_STAMP - help - Select the LED (marked on the board) for you to blink. - -config BFIN_IDLE_LED - bool "Enable System Load/Idle LED" - depends on (BFIN533_STAMP || BFIN533_BLUETECHNIX_CM) - default n - help - Blinks the LED you select when to determine kernel load. - -config BFIN_IDLE_LED_NUM - int "LED" - depends on BFIN_IDLE_LED - range 1 3 if BFIN533_STAMP - default "2" if BFIN533_STAMP - help - Select the LED (marked on the board) for you to blink. - choice prompt "Blackfin Exception Scratch Register" default BFIN_SCRATCH_REG_RETN @@ -543,41 +509,6 @@ config BFIN_SCRATCH_REG_CYCLES endchoice -# -# Sorry - but you need to put the hex address here - -# - -# Flag Data register -config BFIN_ALIVE_LED_PORT - hex - default 0xFFC00700 if (BFIN533_STAMP) - -# Peripheral Flag Direction Register -config BFIN_ALIVE_LED_DPORT - hex - default 0xFFC00730 if (BFIN533_STAMP) - -config BFIN_ALIVE_LED_PIN - hex - default 0x04 if (BFIN533_STAMP && BFIN_ALIVE_LED_NUM = 1) - default 0x08 if (BFIN533_STAMP && BFIN_ALIVE_LED_NUM = 2) - default 0x10 if (BFIN533_STAMP && BFIN_ALIVE_LED_NUM = 3) - -config BFIN_IDLE_LED_PORT - hex - default 0xFFC00700 if (BFIN533_STAMP) - -# Peripheral Flag Direction Register -config BFIN_IDLE_LED_DPORT - hex - default 0xFFC00730 if (BFIN533_STAMP) - -config BFIN_IDLE_LED_PIN - hex - default 0x04 if (BFIN533_STAMP && BFIN_IDLE_LED_NUM = 1) - default 0x08 if (BFIN533_STAMP && BFIN_IDLE_LED_NUM = 2) - default 0x10 if (BFIN533_STAMP && BFIN_IDLE_LED_NUM = 3) - endmenu diff --git a/arch/blackfin/kernel/process.c b/arch/blackfin/kernel/process.c index fff3dd9..023dc80 100644 --- a/arch/blackfin/kernel/process.c +++ b/arch/blackfin/kernel/process.c @@ -39,9 +39,6 @@ #include #include -#define LED_ON 0 -#define LED_OFF 1 - asmlinkage void ret_from_fork(void); /* Points to the SDRAM backup memory for the stack that is currently in @@ -70,32 +67,6 @@ void (*pm_power_off)(void) = NULL; EXPORT_SYMBOL(pm_power_off); /* - * We are using a different LED from the one used to indicate timer interrupt. - */ -#if defined(CONFIG_BFIN_IDLE_LED) -static inline void leds_switch(int flag) -{ - unsigned short tmp = 0; - - tmp = bfin_read_CONFIG_BFIN_IDLE_LED_PORT(); - SSYNC(); - - if (flag == LED_ON) - tmp &= ~CONFIG_BFIN_IDLE_LED_PIN; /* light on */ - else - tmp |= CONFIG_BFIN_IDLE_LED_PIN; /* light off */ - - bfin_write_CONFIG_BFIN_IDLE_LED_PORT(tmp); - SSYNC(); - -} -#else -static inline void leds_switch(int flag) -{ -} -#endif - -/* * The idle loop on BFIN */ #ifdef CONFIG_IDLE_L1 @@ -106,12 +77,10 @@ void cpu_idle(void)__attribute__((l1_text)); void default_idle(void) { while (!need_resched()) { - leds_switch(LED_OFF); local_irq_disable(); if (likely(!need_resched())) idle_with_irq_disabled(); local_irq_enable(); - leds_switch(LED_ON); } } diff --git a/arch/blackfin/kernel/setup.c b/arch/blackfin/kernel/setup.c index d282201..a03c2df 100644 --- a/arch/blackfin/kernel/setup.c +++ b/arch/blackfin/kernel/setup.c @@ -315,8 +315,6 @@ void __init setup_arch(char **cmdline_p) init_mm.end_data = (unsigned long)_edata; init_mm.brk = (unsigned long)0; - init_leds(); - _bfin_swrst = bfin_read_SWRST(); if (_bfin_swrst & RESET_DOUBLE) diff --git a/arch/blackfin/kernel/time.c b/arch/blackfin/kernel/time.c index beef057..5bd64e3 100644 --- a/arch/blackfin/kernel/time.c +++ b/arch/blackfin/kernel/time.c @@ -42,75 +42,6 @@ static void time_sched_init(irqreturn_t(*timer_routine) (int, void *)); static unsigned long gettimeoffset(void); -static inline void do_leds(void); - -#if (defined(CONFIG_BFIN_ALIVE_LED) || defined(CONFIG_BFIN_IDLE_LED)) -void __init init_leds(void) -{ - unsigned int tmp = 0; - -#if defined(CONFIG_BFIN_ALIVE_LED) - /* config pins as output. */ - tmp = bfin_read_CONFIG_BFIN_ALIVE_LED_DPORT(); - SSYNC(); - bfin_write_CONFIG_BFIN_ALIVE_LED_DPORT(tmp | CONFIG_BFIN_ALIVE_LED_PIN); - SSYNC(); - - /* First set led be off */ - tmp = bfin_read_CONFIG_BFIN_ALIVE_LED_PORT(); - SSYNC(); - bfin_write_CONFIG_BFIN_ALIVE_LED_PORT(tmp | CONFIG_BFIN_ALIVE_LED_PIN); /* light off */ - SSYNC(); -#endif - -#if defined(CONFIG_BFIN_IDLE_LED) - /* config pins as output. */ - tmp = bfin_read_CONFIG_BFIN_IDLE_LED_DPORT(); - SSYNC(); - bfin_write_CONFIG_BFIN_IDLE_LED_DPORT(tmp | CONFIG_BFIN_IDLE_LED_PIN); - SSYNC(); - - /* First set led be off */ - tmp = bfin_read_CONFIG_BFIN_IDLE_LED_PORT(); - SSYNC(); - bfin_write_CONFIG_BFIN_IDLE_LED_PORT(tmp | CONFIG_BFIN_IDLE_LED_PIN); /* light off */ - SSYNC(); -#endif -} -#else -void __init init_leds(void) -{ -} -#endif - -#if defined(CONFIG_BFIN_ALIVE_LED) -static inline void do_leds(void) -{ - static unsigned int count = 50; - static int flag; - unsigned short tmp = 0; - - if (--count == 0) { - count = 50; - flag = ~flag; - } - tmp = bfin_read_CONFIG_BFIN_ALIVE_LED_PORT(); - SSYNC(); - - if (flag) - tmp &= ~CONFIG_BFIN_ALIVE_LED_PIN; /* light on */ - else - tmp |= CONFIG_BFIN_ALIVE_LED_PIN; /* light off */ - - bfin_write_CONFIG_BFIN_ALIVE_LED_PORT(tmp); - SSYNC(); - -} -#else -static inline void do_leds(void) -{ -} -#endif static struct irqaction bfin_timer_irq = { .name = "BFIN Timer Tick", @@ -205,7 +136,6 @@ irqreturn_t timer_interrupt(int irq, void *dummy) write_seqlock(&xtime_lock); do_timer(1); - do_leds(); #ifndef CONFIG_SMP update_process_times(user_mode(get_irq_regs())); -- cgit v0.10.2 From 1545a1111a02b5aafe6f141e133a6269c5741285 Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Mon, 24 Dec 2007 16:54:48 +0800 Subject: [Blackfin] arch: add support for BF523/BF524/BF526 Signed-off-by: Mike Frysinger Signed-off-by: Bryan Wu diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig index e4ccdcd..a241a0a 100644 --- a/arch/blackfin/Kconfig +++ b/arch/blackfin/Kconfig @@ -85,11 +85,26 @@ config BF522 help BF522 Processor Support. +config BF523 + bool "BF523" + help + BF523 Processor Support. + +config BF524 + bool "BF524" + help + BF524 Processor Support. + config BF525 bool "BF525" help BF525 Processor Support. +config BF526 + bool "BF526" + help + BF526 Processor Support. + config BF527 bool "BF527" help @@ -198,7 +213,7 @@ endchoice config BF52x bool - depends on (BF522 || BF525 || BF527) + depends on (BF522 || BF523 || BF524 || BF525 || BF526 || BF527) default y config BF53x @@ -371,7 +386,10 @@ config SCLK_DIV config MAX_VCO_HZ int default 600000000 if BF522 + default 400000000 if BF523 + default 400000000 if BF524 default 600000000 if BF525 + default 400000000 if BF526 default 600000000 if BF527 default 400000000 if BF531 default 400000000 if BF532 @@ -383,6 +401,8 @@ config MAX_VCO_HZ default 533333333 if BF539 default 600000000 if BF542 default 533333333 if BF544 + default 600000000 if BF547 + default 600000000 if BF548 default 533333333 if BF549 default 600000000 if BF561 @@ -897,8 +917,8 @@ config PM_WAKEUP_SIC_IWR depends on PM_WAKEUP_GPIO_BY_SIC_IWR default 0x80000000 if (BF537 || BF536 || BF534) default 0x100000 if (BF533 || BF532 || BF531) - default 0x800000 if (BF549 || BF548 || BF547 || BF542) - default 0x800000 if (BF527 || BF524 || BF522) + default 0x800000 if (BF54x) + default 0x800000 if (BF52x) config PM_WAKEUP_GPIO_NUMBER int "Wakeup GPIO number" diff --git a/arch/blackfin/Makefile b/arch/blackfin/Makefile index c47e000..0c9680e 100644 --- a/arch/blackfin/Makefile +++ b/arch/blackfin/Makefile @@ -21,7 +21,10 @@ KBUILD_DEFCONFIG := BF537-STAMP_defconfig # setup the machine name and the machine dependent settings machine-$(CONFIG_BF522) := bf527 +machine-$(CONFIG_BF523) := bf527 +machine-$(CONFIG_BF524) := bf527 machine-$(CONFIG_BF525) := bf527 +machine-$(CONFIG_BF526) := bf527 machine-$(CONFIG_BF527) := bf527 machine-$(CONFIG_BF531) := bf533 machine-$(CONFIG_BF532) := bf533 @@ -39,7 +42,10 @@ MACHINE := $(machine-y) export MACHINE cpu-$(CONFIG_BF522) := bf522 +cpu-$(CONFIG_BF523) := bf523 +cpu-$(CONFIG_BF524) := bf524 cpu-$(CONFIG_BF525) := bf525 +cpu-$(CONFIG_BF526) := bf526 cpu-$(CONFIG_BF527) := bf527 cpu-$(CONFIG_BF531) := bf531 cpu-$(CONFIG_BF532) := bf532 diff --git a/arch/blackfin/kernel/bfin_gpio.c b/arch/blackfin/kernel/bfin_gpio.c index ce85d4b..ea13d2a 100644 --- a/arch/blackfin/kernel/bfin_gpio.c +++ b/arch/blackfin/kernel/bfin_gpio.c @@ -83,6 +83,7 @@ #include #include #include +#include #include #include #include @@ -1194,3 +1195,36 @@ void bfin_gpio_reset_spi0_ssel1(void) } #endif /*BF548_FAMILY */ + +#if defined(CONFIG_PROC_FS) +static int gpio_proc_read(char *buf, char **start, off_t offset, + int len, int *unused_i, void *unused_v) +{ + int c, outlen = 0; + + for (c = 0; c < MAX_RESOURCES; c++) { + if (!check_gpio(c) && (reserved_gpio_map[gpio_bank(c)] & gpio_bit(c))) + len = sprintf(buf, "GPIO_%d: %s \tGPIO %s\n", c, + get_label(c), get_gpio_dir(c) ? "OUTPUT" : "INPUT"); + else if (reserved_peri_map[gpio_bank(c)] & gpio_bit(c)) + len = sprintf(buf, "GPIO_%d: %s \tPeripheral\n", c, get_label(c)); + else + continue; + buf += len; + outlen += len; + } + return outlen; +} + +static __init int gpio_register_proc(void) +{ + struct proc_dir_entry *proc_gpio; + + proc_gpio = create_proc_entry("gpio", S_IRUGO, NULL); + if (proc_gpio) + proc_gpio->read_proc = gpio_proc_read; + return proc_gpio != NULL; +} + +__initcall(gpio_register_proc); +#endif -- cgit v0.10.2 From fac3cf432ef9b6bfd64b35b95afe0b7e0079da74 Mon Sep 17 00:00:00 2001 From: Michael Hennerich Date: Mon, 24 Dec 2007 20:07:03 +0800 Subject: [Blackfin] arch: Fix gpio label handling early serial init also utilizes the peripheral request api - however at this point bfin_gpio_init didn't allocate memory for the labels. So we always have two zombies (allocated pin functions without labels) This happens before the initcalls - We now allocate memory statically. Define MAX_RESOURCES individually for each cpu. Signed-off-by: Michael Hennerich Signed-off-by: Bryan Wu diff --git a/arch/blackfin/kernel/bfin_gpio.c b/arch/blackfin/kernel/bfin_gpio.c index ea13d2a..ffee369 100644 --- a/arch/blackfin/kernel/bfin_gpio.c +++ b/arch/blackfin/kernel/bfin_gpio.c @@ -179,15 +179,13 @@ static struct gpio_port_t *gpio_array[gpio_bank(MAX_BLACKFIN_GPIOS)] = { #endif static unsigned short reserved_gpio_map[gpio_bank(MAX_BLACKFIN_GPIOS)]; -static unsigned short reserved_peri_map[gpio_bank(MAX_BLACKFIN_GPIOS + 16)]; +static unsigned short reserved_peri_map[gpio_bank(MAX_RESOURCES)]; -#define MAX_RESOURCES 256 #define RESOURCE_LABEL_SIZE 16 -struct str_ident { +static struct str_ident { char name[RESOURCE_LABEL_SIZE]; -} *str_ident; - +} str_ident[MAX_RESOURCES]; #ifdef CONFIG_PM static unsigned short wakeup_map[gpio_bank(MAX_BLACKFIN_GPIOS)]; @@ -251,6 +249,11 @@ static char *get_label(unsigned short ident) static int cmp_label(unsigned short ident, const char *label) { + if (label == NULL) { + dump_stack(); + printk(KERN_ERR "Please provide none-null label\n"); + } + if (label && str_ident) return strncmp(str_ident[ident].name, label, strlen(label)); @@ -419,12 +422,6 @@ static void default_gpio(unsigned short gpio) static int __init bfin_gpio_init(void) { - str_ident = kcalloc(MAX_RESOURCES, - sizeof(struct str_ident), GFP_KERNEL); - if (str_ident == NULL) - return -ENOMEM; - - memset(str_ident, 0, MAX_RESOURCES * sizeof(struct str_ident)); printk(KERN_INFO "Blackfin GPIO Controller\n"); @@ -785,6 +782,14 @@ void gpio_pm_restore(void) } #endif +#else /* BF548_FAMILY */ + +unsigned short get_gpio_dir(unsigned short gpio) +{ + return (0x01 & (gpio_array[gpio_bank(gpio)]->port_dir_clear >> gpio_sub_n(gpio))); +} +EXPORT_SYMBOL(get_gpio_dir); + #endif /* BF548_FAMILY */ /*********************************************************** @@ -1204,10 +1209,10 @@ static int gpio_proc_read(char *buf, char **start, off_t offset, for (c = 0; c < MAX_RESOURCES; c++) { if (!check_gpio(c) && (reserved_gpio_map[gpio_bank(c)] & gpio_bit(c))) - len = sprintf(buf, "GPIO_%d: %s \tGPIO %s\n", c, + len = sprintf(buf, "GPIO_%d: %s \t\tGPIO %s\n", c, get_label(c), get_gpio_dir(c) ? "OUTPUT" : "INPUT"); else if (reserved_peri_map[gpio_bank(c)] & gpio_bit(c)) - len = sprintf(buf, "GPIO_%d: %s \tPeripheral\n", c, get_label(c)); + len = sprintf(buf, "GPIO_%d: %s \t\tPeripheral\n", c, get_label(c)); else continue; buf += len; diff --git a/include/asm-blackfin/mach-bf527/portmux.h b/include/asm-blackfin/mach-bf527/portmux.h index dcf001a..ae4d205 100644 --- a/include/asm-blackfin/mach-bf527/portmux.h +++ b/include/asm-blackfin/mach-bf527/portmux.h @@ -1,6 +1,8 @@ #ifndef _MACH_PORTMUX_H_ #define _MACH_PORTMUX_H_ +#define MAX_RESOURCES MAX_BLACKFIN_GPIOS + #define P_PPI0_D0 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(0)) #define P_PPI0_D1 (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(0)) #define P_PPI0_D2 (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(0)) diff --git a/include/asm-blackfin/mach-bf533/portmux.h b/include/asm-blackfin/mach-bf533/portmux.h index 137f488..685a265 100644 --- a/include/asm-blackfin/mach-bf533/portmux.h +++ b/include/asm-blackfin/mach-bf533/portmux.h @@ -1,6 +1,8 @@ #ifndef _MACH_PORTMUX_H_ #define _MACH_PORTMUX_H_ +#define MAX_RESOURCES MAX_BLACKFIN_GPIOS + #define P_PPI0_CLK (P_DONTCARE) #define P_PPI0_FS1 (P_DONTCARE) #define P_PPI0_FS2 (P_DONTCARE) diff --git a/include/asm-blackfin/mach-bf537/portmux.h b/include/asm-blackfin/mach-bf537/portmux.h index 5a3f7d3..78fee6e 100644 --- a/include/asm-blackfin/mach-bf537/portmux.h +++ b/include/asm-blackfin/mach-bf537/portmux.h @@ -1,6 +1,8 @@ #ifndef _MACH_PORTMUX_H_ #define _MACH_PORTMUX_H_ +#define MAX_RESOURCES (MAX_BLACKFIN_GPIOS + GPIO_BANKSIZE) /* We additionally handle PORTJ */ + #define P_UART0_TX (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(0)) #define P_UART0_RX (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(0)) #define P_UART1_TX (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(0)) diff --git a/include/asm-blackfin/mach-bf548/portmux.h b/include/asm-blackfin/mach-bf548/portmux.h index 6b48512..8177a56 100644 --- a/include/asm-blackfin/mach-bf548/portmux.h +++ b/include/asm-blackfin/mach-bf548/portmux.h @@ -1,6 +1,8 @@ #ifndef _MACH_PORTMUX_H_ #define _MACH_PORTMUX_H_ +#define MAX_RESOURCES MAX_BLACKFIN_GPIOS + #define P_SPORT2_TFS (P_DEFINED | P_IDENT(GPIO_PA0) | P_FUNCT(0)) #define P_SPORT2_DTSEC (P_DEFINED | P_IDENT(GPIO_PA1) | P_FUNCT(0)) #define P_SPORT2_DTPRI (P_DEFINED | P_IDENT(GPIO_PA2) | P_FUNCT(0)) diff --git a/include/asm-blackfin/mach-bf561/portmux.h b/include/asm-blackfin/mach-bf561/portmux.h index 132ad31..a6ee820 100644 --- a/include/asm-blackfin/mach-bf561/portmux.h +++ b/include/asm-blackfin/mach-bf561/portmux.h @@ -1,6 +1,8 @@ #ifndef _MACH_PORTMUX_H_ #define _MACH_PORTMUX_H_ +#define MAX_RESOURCES MAX_BLACKFIN_GPIOS + #define P_PPI0_CLK (P_DONTCARE) #define P_PPI0_FS1 (P_DONTCARE) #define P_PPI0_FS2 (P_DONTCARE) -- cgit v0.10.2 From 6fce6a8d6940654b48d3d540627c7ee790a03b80 Mon Sep 17 00:00:00 2001 From: Michael Hennerich Date: Mon, 24 Dec 2007 16:56:12 +0800 Subject: [Blackfin] arch: append IRQ Number to label string Signed-off-by: Michael Hennerich Signed-off-by: Bryan Wu diff --git a/arch/blackfin/mach-common/ints-priority-dc.c b/arch/blackfin/mach-common/ints-priority-dc.c index 4882f0e..8d18d6b 100644 --- a/arch/blackfin/mach-common/ints-priority-dc.c +++ b/arch/blackfin/mach-common/ints-priority-dc.c @@ -222,11 +222,12 @@ static void bf561_gpio_unmask_irq(unsigned int irq) static unsigned int bf561_gpio_irq_startup(unsigned int irq) { unsigned int ret; + char buf[8]; u16 gpionr = irq - IRQ_PF0; if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) { - - ret = gpio_request(gpionr, "IRQ"); + snprintf(buf, sizeof buf, "IRQ %d", irq); + ret = gpio_request(gpionr, buf); if (ret) return ret; @@ -250,6 +251,7 @@ static int bf561_gpio_irq_type(unsigned int irq, unsigned int type) { unsigned int ret; + char buf[8]; u16 gpionr = irq - IRQ_PF0; @@ -265,8 +267,8 @@ static int bf561_gpio_irq_type(unsigned int irq, unsigned int type) IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) { if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) { - - ret = gpio_request(gpionr, "IRQ"); + snprintf(buf, sizeof buf, "IRQ %d", irq); + ret = gpio_request(gpionr, buf); if (ret) return ret; diff --git a/arch/blackfin/mach-common/ints-priority-sc.c b/arch/blackfin/mach-common/ints-priority-sc.c index 147f073..36ef4d1 100644 --- a/arch/blackfin/mach-common/ints-priority-sc.c +++ b/arch/blackfin/mach-common/ints-priority-sc.c @@ -313,6 +313,7 @@ static void bfin_demux_error_irq(unsigned int int_err_irq, static unsigned short gpio_enabled[gpio_bank(MAX_BLACKFIN_GPIOS)]; static unsigned short gpio_edge_triggered[gpio_bank(MAX_BLACKFIN_GPIOS)]; + static void bfin_gpio_ack_irq(unsigned int irq) { u16 gpionr = irq - IRQ_PF0; @@ -352,9 +353,11 @@ static unsigned int bfin_gpio_irq_startup(unsigned int irq) { unsigned int ret; u16 gpionr = irq - IRQ_PF0; + char buf[8]; if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) { - ret = gpio_request(gpionr, "IRQ"); + snprintf(buf, sizeof buf, "IRQ %d", irq); + ret = gpio_request(gpionr, buf); if (ret) return ret; } @@ -376,6 +379,7 @@ static int bfin_gpio_irq_type(unsigned int irq, unsigned int type) { unsigned int ret; + char buf[8]; u16 gpionr = irq - IRQ_PF0; if (type == IRQ_TYPE_PROBE) { @@ -388,7 +392,8 @@ static int bfin_gpio_irq_type(unsigned int irq, unsigned int type) if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) { if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) { - ret = gpio_request(gpionr, "IRQ"); + snprintf(buf, sizeof buf, "IRQ %d", irq); + ret = gpio_request(gpionr, buf); if (ret) return ret; } @@ -587,6 +592,7 @@ static void bfin_gpio_unmask_irq(unsigned int irq) static unsigned int bfin_gpio_irq_startup(unsigned int irq) { unsigned int ret; + char buf[8]; u16 gpionr = irq - IRQ_PA0; u8 pint_val = irq2pint_lut[irq - SYS_IRQS]; @@ -598,7 +604,8 @@ static unsigned int bfin_gpio_irq_startup(unsigned int irq) } if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) { - ret = gpio_request(gpionr, "IRQ"); + snprintf(buf, sizeof buf, "IRQ %d", irq); + ret = gpio_request(gpionr, buf); if (ret) return ret; } @@ -620,6 +627,7 @@ static int bfin_gpio_irq_type(unsigned int irq, unsigned int type) { unsigned int ret; + char buf[8]; u16 gpionr = irq - IRQ_PA0; u8 pint_val = irq2pint_lut[irq - SYS_IRQS]; u32 pintbit = PINT_BIT(pint_val); @@ -638,7 +646,8 @@ static int bfin_gpio_irq_type(unsigned int irq, unsigned int type) if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) { if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) { - ret = gpio_request(gpionr, "IRQ"); + snprintf(buf, sizeof buf, "IRQ %d", irq); + ret = gpio_request(gpionr, buf); if (ret) return ret; } -- cgit v0.10.2 From 2463ef22bf8b6e22048bd26f940c014f7e1f0998 Mon Sep 17 00:00:00 2001 From: Michael Hennerich Date: Sun, 27 Jan 2008 16:49:48 +0800 Subject: [Blackfin] arch: replace current blackfin specific pfbutton driver with kernel generic gpio key driver Signed-off-by: Michael Hennerich Signed-off-by: Bryan Wu diff --git a/arch/blackfin/mach-bf533/boards/ezkit.c b/arch/blackfin/mach-bf533/boards/ezkit.c index be85203..ead5c12 100644 --- a/arch/blackfin/mach-bf533/boards/ezkit.c +++ b/arch/blackfin/mach-bf533/boards/ezkit.c @@ -256,6 +256,30 @@ static struct platform_device bfin_pata_device = { }; #endif +#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE) +#include +#include + +static struct gpio_keys_button bfin_gpio_keys_table[] = { + {BTN_0, GPIO_PF7, 1, "gpio-keys: BTN0"}, + {BTN_1, GPIO_PF8, 1, "gpio-keys: BTN1"}, + {BTN_2, GPIO_PF9, 1, "gpio-keys: BTN2"}, + {BTN_3, GPIO_PF10, 1, "gpio-keys: BTN3"}, +}; + +static struct gpio_keys_platform_data bfin_gpio_keys_data = { + .buttons = bfin_gpio_keys_table, + .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table), +}; + +static struct platform_device bfin_device_gpiokeys = { + .name = "gpio-keys", + .dev = { + .platform_data = &bfin_gpio_keys_data, + }, +}; +#endif + static struct platform_device *ezkit_devices[] __initdata = { #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE) &smc91x_device, @@ -280,6 +304,10 @@ static struct platform_device *ezkit_devices[] __initdata = { #if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE) &bfin_pata_device, #endif + +#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE) + &bfin_device_gpiokeys, +#endif }; static int __init ezkit_init(void) diff --git a/arch/blackfin/mach-bf533/boards/stamp.c b/arch/blackfin/mach-bf533/boards/stamp.c index 8fde8d8..6898169 100644 --- a/arch/blackfin/mach-bf533/boards/stamp.c +++ b/arch/blackfin/mach-bf533/boards/stamp.c @@ -373,6 +373,29 @@ static struct platform_device bfin_pata_device = { }; #endif +#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE) +#include +#include + +static struct gpio_keys_button bfin_gpio_keys_table[] = { + {BTN_0, GPIO_PF5, 1, "gpio-keys: BTN0"}, + {BTN_1, GPIO_PF6, 1, "gpio-keys: BTN1"}, + {BTN_2, GPIO_PF8, 1, "gpio-keys: BTN2"}, +}; + +static struct gpio_keys_platform_data bfin_gpio_keys_data = { + .buttons = bfin_gpio_keys_table, + .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table), +}; + +static struct platform_device bfin_device_gpiokeys = { + .name = "gpio-keys", + .dev = { + .platform_data = &bfin_gpio_keys_data, + }, +}; +#endif + static struct platform_device *stamp_devices[] __initdata = { #if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE) &rtc_device, @@ -406,6 +429,10 @@ static struct platform_device *stamp_devices[] __initdata = { #if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE) &bfin_pata_device, #endif + +#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE) + &bfin_device_gpiokeys, +#endif }; static int __init stamp_init(void) diff --git a/arch/blackfin/mach-bf537/boards/stamp.c b/arch/blackfin/mach-bf537/boards/stamp.c index 07b0dc2..3e0ad04 100644 --- a/arch/blackfin/mach-bf537/boards/stamp.c +++ b/arch/blackfin/mach-bf537/boards/stamp.c @@ -103,6 +103,30 @@ void __exit bfin_isp1761_exit(void) arch_initcall(bfin_isp1761_init); #endif +#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE) +#include +#include + +static struct gpio_keys_button bfin_gpio_keys_table[] = { + {BTN_0, GPIO_PF2, 1, "gpio-keys: BTN0"}, + {BTN_1, GPIO_PF3, 1, "gpio-keys: BTN1"}, + {BTN_2, GPIO_PF4, 1, "gpio-keys: BTN2"}, + {BTN_3, GPIO_PF5, 1, "gpio-keys: BTN3"}, +}; + +static struct gpio_keys_platform_data bfin_gpio_keys_data = { + .buttons = bfin_gpio_keys_table, + .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table), +}; + +static struct platform_device bfin_device_gpiokeys = { + .name = "gpio-keys", + .dev = { + .platform_data = &bfin_gpio_keys_data, + }, +}; +#endif + #if defined(CONFIG_BFIN_CFPCMCIA) || defined(CONFIG_BFIN_CFPCMCIA_MODULE) static struct resource bfin_pcmcia_cf_resources[] = { { @@ -738,6 +762,10 @@ static struct platform_device *stamp_devices[] __initdata = { #if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE) &bfin_pata_device, #endif + +#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE) + &bfin_device_gpiokeys, +#endif }; static int __init stamp_init(void) diff --git a/arch/blackfin/mach-bf548/boards/ezkit.c b/arch/blackfin/mach-bf548/boards/ezkit.c index 856b9db..4ca3288 100644 --- a/arch/blackfin/mach-bf548/boards/ezkit.c +++ b/arch/blackfin/mach-bf548/boards/ezkit.c @@ -514,6 +514,29 @@ static struct platform_device i2c_bfin_twi1_device = { #endif #endif +#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE) +#include + +static struct gpio_keys_button bfin_gpio_keys_table[] = { + {BTN_0, GPIO_PB8, 1, "gpio-keys: BTN0"}, + {BTN_1, GPIO_PB9, 1, "gpio-keys: BTN1"}, + {BTN_2, GPIO_PB10, 1, "gpio-keys: BTN2"}, + {BTN_3, GPIO_PB11, 1, "gpio-keys: BTN3"}, +}; + +static struct gpio_keys_platform_data bfin_gpio_keys_data = { + .buttons = bfin_gpio_keys_table, + .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table), +}; + +static struct platform_device bfin_device_gpiokeys = { + .name = "gpio-keys", + .dev = { + .platform_data = &bfin_gpio_keys_data, + }, +}; +#endif + static struct platform_device *ezkit_devices[] __initdata = { #if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE) &rtc_device, @@ -562,6 +585,10 @@ static struct platform_device *ezkit_devices[] __initdata = { &i2c_bfin_twi1_device, #endif #endif + +#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE) + &bfin_device_gpiokeys, +#endif }; static int __init stamp_init(void) diff --git a/arch/blackfin/mach-bf561/boards/ezkit.c b/arch/blackfin/mach-bf561/boards/ezkit.c index 4ff8f6e..edfceb0 100644 --- a/arch/blackfin/mach-bf561/boards/ezkit.c +++ b/arch/blackfin/mach-bf561/boards/ezkit.c @@ -246,6 +246,30 @@ static struct platform_device bfin_pata_device = { }; #endif +#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE) +#include +#include + +static struct gpio_keys_button bfin_gpio_keys_table[] = { + {BTN_0, GPIO_PF5, 1, "gpio-keys: BTN0"}, + {BTN_1, GPIO_PF6, 1, "gpio-keys: BTN1"}, + {BTN_2, GPIO_PF7, 1, "gpio-keys: BTN2"}, + {BTN_3, GPIO_PF8, 1, "gpio-keys: BTN3"}, +}; + +static struct gpio_keys_platform_data bfin_gpio_keys_data = { + .buttons = bfin_gpio_keys_table, + .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table), +}; + +static struct platform_device bfin_device_gpiokeys = { + .name = "gpio-keys", + .dev = { + .platform_data = &bfin_gpio_keys_data, + }, +}; +#endif + static struct platform_device *ezkit_devices[] __initdata = { #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE) &smc91x_device, @@ -258,12 +282,18 @@ static struct platform_device *ezkit_devices[] __initdata = { #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) &bfin_spi0_device, #endif + #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE) &bfin_uart_device, #endif + #if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE) &bfin_pata_device, #endif + +#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE) + &bfin_device_gpiokeys, +#endif }; static int __init ezkit_init(void) -- cgit v0.10.2 From 471b9a6c7304d5f59503d111e71e60a7e19fb9a0 Mon Sep 17 00:00:00 2001 From: Martin Strubel Date: Sun, 27 Jan 2008 19:54:20 +0800 Subject: [Blackfin] arch: added Minotaur BSP Signed-off-by: Martin Strubel Signed-off-by: Bryan Wu diff --git a/arch/blackfin/mach-bf537/boards/Kconfig b/arch/blackfin/mach-bf537/boards/Kconfig index 96a1519..7e789db 100644 --- a/arch/blackfin/mach-bf537/boards/Kconfig +++ b/arch/blackfin/mach-bf537/boards/Kconfig @@ -21,6 +21,12 @@ config PNAV10 help PNAV board support. +config CAMSIG_MINOTAUR + bool "Cambridge Signal Processing LTD Minotaur" + depends on (BF537) + help + Board supply package for CSP Minotaur + config GENERIC_BF537_BOARD bool "Generic" help diff --git a/arch/blackfin/mach-bf537/boards/Makefile b/arch/blackfin/mach-bf537/boards/Makefile index 94a8517..87e450f 100644 --- a/arch/blackfin/mach-bf537/boards/Makefile +++ b/arch/blackfin/mach-bf537/boards/Makefile @@ -6,3 +6,4 @@ obj-$(CONFIG_GENERIC_BF537_BOARD) += generic_board.o obj-$(CONFIG_BFIN537_STAMP) += stamp.o led.o obj-$(CONFIG_BFIN537_BLUETECHNIX_CM) += cm_bf537.o obj-$(CONFIG_PNAV10) += pnav10.o +obj-$(CONFIG_CAMSIG_MINOTAUR) += minotaur.o diff --git a/arch/blackfin/mach-bf537/boards/minotaur.c b/arch/blackfin/mach-bf537/boards/minotaur.c new file mode 100644 index 0000000..b8bbba8 --- /dev/null +++ b/arch/blackfin/mach-bf537/boards/minotaur.c @@ -0,0 +1,317 @@ +/* + */ + +#include +#include +#include +#include +#include +#include +#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE) +#include +#endif +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * Name the Board for the /proc/cpuinfo + */ +char *bfin_board_name = "CamSig Minotaur BF537"; + +#if defined(CONFIG_BFIN_CFPCMCIA) || defined(CONFIG_BFIN_CFPCMCIA_MODULE) +static struct resource bfin_pcmcia_cf_resources[] = { + { + .start = 0x20310000, /* IO PORT */ + .end = 0x20312000, + .flags = IORESOURCE_MEM, + }, { + .start = 0x20311000, /* Attribute Memory */ + .end = 0x20311FFF, + .flags = IORESOURCE_MEM, + }, { + .start = IRQ_PF4, + .end = IRQ_PF4, + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL, + }, { + .start = IRQ_PF6, /* Card Detect PF6 */ + .end = IRQ_PF6, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device bfin_pcmcia_cf_device = { + .name = "bfin_cf_pcmcia", + .id = -1, + .num_resources = ARRAY_SIZE(bfin_pcmcia_cf_resources), + .resource = bfin_pcmcia_cf_resources, +}; +#endif + +#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE) +static struct platform_device rtc_device = { + .name = "rtc-bfin", + .id = -1, +}; +#endif + +#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE) +static struct platform_device bfin_mac_device = { + .name = "bfin_mac", +}; +#endif + +#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE) +static struct resource net2272_bfin_resources[] = { + { + .start = 0x20300000, + .end = 0x20300000 + 0x100, + .flags = IORESOURCE_MEM, + }, { + .start = IRQ_PF7, + .end = IRQ_PF7, + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, + }, +}; + +static struct platform_device net2272_bfin_device = { + .name = "net2272", + .id = -1, + .num_resources = ARRAY_SIZE(net2272_bfin_resources), + .resource = net2272_bfin_resources, +}; +#endif + +#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) +/* all SPI peripherals info goes here */ + +#if defined(CONFIG_MTD_M25P80) \ + || defined(CONFIG_MTD_M25P80_MODULE) + +/* Partition sizes */ +#define FLASH_SIZE 0x00400000 +#define PSIZE_UBOOT 0x00030000 +#define PSIZE_INITRAMFS 0x00240000 + +static struct mtd_partition bfin_spi_flash_partitions[] = { + { + .name = "uboot", + .size = PSIZE_UBOOT, + .offset = 0x000000, + .mask_flags = MTD_CAP_ROM + }, { + .name = "initramfs", + .size = PSIZE_INITRAMFS, + .offset = PSIZE_UBOOT + }, { + .name = "opt", + .size = FLASH_SIZE - (PSIZE_UBOOT + PSIZE_INITRAMFS), + .offset = PSIZE_UBOOT + PSIZE_INITRAMFS, + } +}; + +static struct flash_platform_data bfin_spi_flash_data = { + .name = "m25p80", + .parts = bfin_spi_flash_partitions, + .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions), + .type = "m25p64", +}; + +/* SPI flash chip (m25p64) */ +static struct bfin5xx_spi_chip spi_flash_chip_info = { + .enable_dma = 0, /* use dma transfer with this chip*/ + .bits_per_word = 8, +}; +#endif + +#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE) +static struct bfin5xx_spi_chip spi_mmc_chip_info = { + .enable_dma = 1, + .bits_per_word = 8, +}; +#endif + +static struct spi_board_info bfin_spi_board_info[] __initdata = { +#if defined(CONFIG_MTD_M25P80) \ + || defined(CONFIG_MTD_M25P80_MODULE) + { + /* the modalias must be the same as spi device driver name */ + .modalias = "m25p80", /* Name of spi_driver for this device */ + .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */ + .bus_num = 0, /* Framework bus number */ + .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/ + .platform_data = &bfin_spi_flash_data, + .controller_data = &spi_flash_chip_info, + .mode = SPI_MODE_3, + }, +#endif + +#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE) + { + .modalias = "spi_mmc_dummy", + .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */ + .bus_num = 0, + .chip_select = 0, + .platform_data = NULL, + .controller_data = &spi_mmc_chip_info, + .mode = SPI_MODE_3, + }, + { + .modalias = "spi_mmc", + .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */ + .bus_num = 0, + .chip_select = CONFIG_SPI_MMC_CS_CHAN, + .platform_data = NULL, + .controller_data = &spi_mmc_chip_info, + .mode = SPI_MODE_3, + }, +#endif +}; + +/* SPI controller data */ +static struct bfin5xx_spi_master bfin_spi0_info = { + .num_chipselect = 8, + .enable_dma = 1, /* master has the ability to do dma transfer */ +}; + +/* SPI (0) */ +static struct resource bfin_spi0_resource[] = { + [0] = { + .start = SPI0_REGBASE, + .end = SPI0_REGBASE + 0xFF, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = CH_SPI, + .end = CH_SPI, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device bfin_spi0_device = { + .name = "bfin-spi", + .id = 0, /* Bus number */ + .num_resources = ARRAY_SIZE(bfin_spi0_resource), + .resource = bfin_spi0_resource, + .dev = { + .platform_data = &bfin_spi0_info, /* Passed to driver */ + }, +}; +#endif /* spi master and devices */ + +#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE) +static struct resource bfin_uart_resources[] = { + { + .start = 0xFFC00400, + .end = 0xFFC004FF, + .flags = IORESOURCE_MEM, + }, { + .start = 0xFFC02000, + .end = 0xFFC020FF, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device bfin_uart_device = { + .name = "bfin-uart", + .id = 1, + .num_resources = ARRAY_SIZE(bfin_uart_resources), + .resource = bfin_uart_resources, +}; +#endif + +#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE) +static struct resource bfin_twi0_resource[] = { + [0] = { + .start = TWI0_REGBASE, + .end = TWI0_REGBASE + 0xFF, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_TWI, + .end = IRQ_TWI, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device i2c_bfin_twi_device = { + .name = "i2c-bfin-twi", + .id = 0, + .num_resources = ARRAY_SIZE(bfin_twi0_resource), + .resource = bfin_twi0_resource, +}; +#endif + +#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE) +static struct platform_device bfin_sport0_uart_device = { + .name = "bfin-sport-uart", + .id = 0, +}; + +static struct platform_device bfin_sport1_uart_device = { + .name = "bfin-sport-uart", + .id = 1, +}; +#endif + +static struct platform_device *minotaur_devices[] __initdata = { +#if defined(CONFIG_BFIN_CFPCMCIA) || defined(CONFIG_BFIN_CFPCMCIA_MODULE) + &bfin_pcmcia_cf_device, +#endif + +#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE) + &rtc_device, +#endif + +#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE) + &bfin_mac_device, +#endif + +#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE) + &net2272_bfin_device, +#endif + +#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) + &bfin_spi0_device, +#endif + +#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE) + &bfin_uart_device, +#endif + +#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE) + &i2c_bfin_twi_device, +#endif + +#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE) + &bfin_sport0_uart_device, + &bfin_sport1_uart_device, +#endif + +}; + +static int __init minotaur_init(void) +{ + printk(KERN_INFO "%s(): registering device resources\n", __FUNCTION__); + platform_add_devices(minotaur_devices, ARRAY_SIZE(minotaur_devices)); +#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) + spi_register_board_info(bfin_spi_board_info, + ARRAY_SIZE(bfin_spi_board_info)); +#endif + + return 0; +} + +arch_initcall(minotaur_init); + +void native_machine_restart(char *cmd) +{ + /* workaround reboot hang when booting from SPI */ + if ((bfin_read_SYSCR() & 0x7) == 0x3) + bfin_gpio_reset_spi0_ssel1(); +} -- cgit v0.10.2 From 8baf560b4c901fb554d15e056aaa7f34b2345be5 Mon Sep 17 00:00:00 2001 From: Michael Hennerich Date: Mon, 24 Dec 2007 18:51:34 +0800 Subject: [Blackfin] arch: Enable both edge triggered GPIO IRQs on BF54x and use irq_to_gpio() Signed-off-by: Michael Hennerich Signed-off-by: Bryan Wu diff --git a/arch/blackfin/mach-common/ints-priority-sc.c b/arch/blackfin/mach-common/ints-priority-sc.c index 36ef4d1..dec42ac 100644 --- a/arch/blackfin/mach-common/ints-priority-sc.c +++ b/arch/blackfin/mach-common/ints-priority-sc.c @@ -483,6 +483,10 @@ static void bfin_demux_gpio_irq(unsigned int intb_irq, static unsigned char irq2pint_lut[NR_PINTS]; static unsigned char pint2irq_lut[NR_PINT_SYS_IRQS * NR_PINT_BITS]; +static unsigned int gpio_both_edge_triggered[NR_PINT_SYS_IRQS]; +static unsigned short gpio_enabled[gpio_bank(MAX_BLACKFIN_GPIOS)]; + + struct pin_int_t { unsigned int mask_set; unsigned int mask_clear; @@ -549,13 +553,20 @@ void init_pint_lut(void) } -static unsigned short gpio_enabled[gpio_bank(MAX_BLACKFIN_GPIOS)]; - static void bfin_gpio_ack_irq(unsigned int irq) { u8 pint_val = irq2pint_lut[irq - SYS_IRQS]; + u32 pintbit = PINT_BIT(pint_val); + u8 bank = PINT_2_BANK(pint_val); + + if (unlikely(gpio_both_edge_triggered[bank] & pintbit)) { + if (pint[bank]->invert_set & pintbit) + pint[bank]->invert_clear = pintbit; + else + pint[bank]->invert_set = pintbit; + } + pint[bank]->request = pintbit; - pint[PINT_2_BANK(pint_val)]->request = PINT_BIT(pint_val); SSYNC(); } @@ -565,6 +576,13 @@ static void bfin_gpio_mask_ack_irq(unsigned int irq) u32 pintbit = PINT_BIT(pint_val); u8 bank = PINT_2_BANK(pint_val); + if (unlikely(gpio_both_edge_triggered[bank] & pintbit)) { + if (pint[bank]->invert_set & pintbit) + pint[bank]->invert_clear = pintbit; + else + pint[bank]->invert_set = pintbit; + } + pint[bank]->request = pintbit; pint[bank]->mask_clear = pintbit; SSYNC(); @@ -593,7 +611,7 @@ static unsigned int bfin_gpio_irq_startup(unsigned int irq) { unsigned int ret; char buf[8]; - u16 gpionr = irq - IRQ_PA0; + u16 gpionr = irq_to_gpio(irq); u8 pint_val = irq2pint_lut[irq - SYS_IRQS]; if (pint_val == IRQ_NOT_AVAIL) { @@ -618,9 +636,11 @@ static unsigned int bfin_gpio_irq_startup(unsigned int irq) static void bfin_gpio_irq_shutdown(unsigned int irq) { + u16 gpionr = irq_to_gpio(irq); + bfin_gpio_mask_irq(irq); - gpio_free(irq - IRQ_PA0); - gpio_enabled[gpio_bank(irq - IRQ_PA0)] &= ~gpio_bit(irq - IRQ_PA0); + gpio_free(gpionr); + gpio_enabled[gpio_bank(gpionr)] &= ~gpio_bit(gpionr); } static int bfin_gpio_irq_type(unsigned int irq, unsigned int type) @@ -628,7 +648,7 @@ static int bfin_gpio_irq_type(unsigned int irq, unsigned int type) unsigned int ret; char buf[8]; - u16 gpionr = irq - IRQ_PA0; + u16 gpionr = irq_to_gpio(irq); u8 pint_val = irq2pint_lut[irq - SYS_IRQS]; u32 pintbit = PINT_BIT(pint_val); u8 bank = PINT_2_BANK(pint_val); @@ -660,28 +680,33 @@ static int bfin_gpio_irq_type(unsigned int irq, unsigned int type) gpio_direction_input(gpionr); - if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) { - pint[bank]->edge_set = pintbit; - } else { - pint[bank]->edge_clear = pintbit; - } - if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW))) pint[bank]->invert_set = pintbit; /* low or falling edge denoted by one */ else - pint[bank]->invert_set = pintbit; /* high or rising edge denoted by zero */ + pint[bank]->invert_clear = pintbit; /* high or rising edge denoted by zero */ - if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) - pint[bank]->invert_set = pintbit; - else - pint[bank]->invert_set = pintbit; + if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) + == (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) { - SSYNC(); + gpio_both_edge_triggered[bank] |= pintbit; - if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) + if (gpio_get_value(gpionr)) + pint[bank]->invert_set = pintbit; + else + pint[bank]->invert_clear = pintbit; + } else { + gpio_both_edge_triggered[bank] &= ~pintbit; + } + + if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) { + pint[bank]->edge_set = pintbit; set_irq_handler(irq, handle_edge_irq); - else + } else { + pint[bank]->edge_clear = pintbit; set_irq_handler(irq, handle_level_irq); + } + + SSYNC(); return 0; } -- cgit v0.10.2 From 7285846ff8d09879cacac5c6d40fc8e8443c7cf0 Mon Sep 17 00:00:00 2001 From: Martin Strubel Date: Mon, 24 Dec 2007 19:12:32 +0800 Subject: [Blackfin] arch: disable bfin_get_ether_addr fucntion for boards when do not use MAC driver Signed-off-by: Martin Strubel Signed-off-by: Bryan Wu diff --git a/arch/blackfin/mach-bf537/boards/generic_board.c b/arch/blackfin/mach-bf537/boards/generic_board.c index 09f4bfb..7fd873f 100644 --- a/arch/blackfin/mach-bf537/boards/generic_board.c +++ b/arch/blackfin/mach-bf537/boards/generic_board.c @@ -733,9 +733,11 @@ void native_machine_restart(char *cmd) bfin_gpio_reset_spi0_ssel1(); } +#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE) void bfin_get_ether_addr(char *addr) { random_ether_addr(addr); printk(KERN_WARNING "%s:%s: Setting Ethernet MAC to a random one\n", __FILE__, __func__); } EXPORT_SYMBOL(bfin_get_ether_addr); +#endif -- cgit v0.10.2 From 43f73fef07eb70be7d508b34eeddf5985e300bb1 Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Mon, 24 Dec 2007 19:35:35 +0800 Subject: [Blackfin] arch: pull in linux/etherdevice.h for random_ether_addr() used in bfin_get_ether_addr() Signed-off-by: Mike Frysinger Signed-off-by: Bryan Wu diff --git a/arch/blackfin/mach-bf537/boards/cm_bf537.c b/arch/blackfin/mach-bf537/boards/cm_bf537.c index a102615..8703b67 100644 --- a/arch/blackfin/mach-bf537/boards/cm_bf537.c +++ b/arch/blackfin/mach-bf537/boards/cm_bf537.c @@ -29,6 +29,7 @@ */ #include +#include #include #include #include diff --git a/arch/blackfin/mach-bf537/boards/generic_board.c b/arch/blackfin/mach-bf537/boards/generic_board.c index 7fd873f..1c97219a 100644 --- a/arch/blackfin/mach-bf537/boards/generic_board.c +++ b/arch/blackfin/mach-bf537/boards/generic_board.c @@ -29,6 +29,7 @@ */ #include +#include #include #include #include diff --git a/arch/blackfin/mach-bf537/boards/pnav10.c b/arch/blackfin/mach-bf537/boards/pnav10.c index fd5f4a6..23e10c7 100644 --- a/arch/blackfin/mach-bf537/boards/pnav10.c +++ b/arch/blackfin/mach-bf537/boards/pnav10.c @@ -29,6 +29,7 @@ */ #include +#include #include #include #include -- cgit v0.10.2 From 37931db5bdce35d37a9bdf93082604620ba3341a Mon Sep 17 00:00:00 2001 From: Sonic Zhang Date: Mon, 24 Dec 2007 19:43:39 +0800 Subject: [Blackfin] arch: Restore default DMA priority over core on bf54x. Signed-off-by: Sonic Zhang Signed-off-by: Bryan Wu diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig index a241a0a..ce521a9 100644 --- a/arch/blackfin/Kconfig +++ b/arch/blackfin/Kconfig @@ -774,7 +774,6 @@ config C_AMCKEN config C_CDPRIO bool "DMA has priority over core for ext. accesses" - depends on !BF54x default n config C_B0PEN -- cgit v0.10.2 From 76a7f4049277691b9b800a23dc09009374cdaa21 Mon Sep 17 00:00:00 2001 From: Enrik Berkhan Date: Mon, 24 Dec 2007 19:51:31 +0800 Subject: [Blackfin] arch: fix bug when DMA operation related core B of BF561 - Before DMA'ing data to core B L1 memory, caches have to be flushed. - Before DMA'ing data from core B L1 memory, caches have to be invalidated. - Fix lock/unlock. Signed-off-by: Enrik Berkhan Signed-off-by: Mike Frysinger Signed-off-by: Bryan Wu diff --git a/arch/blackfin/mach-bf561/coreb.c b/arch/blackfin/mach-bf561/coreb.c index 5d1d21b..1b44e9e 100644 --- a/arch/blackfin/mach-bf561/coreb.c +++ b/arch/blackfin/mach-bf561/coreb.c @@ -33,7 +33,9 @@ #include #include #include +#include #include +#include #define MODULE_VER "v0.1" @@ -90,11 +92,12 @@ static ssize_t coreb_write(struct file *file, const char *buf, size_t count, coreb_dma_done = 0; + flush_dcache_range((unsigned long)buf, (unsigned long)(buf+len)); /* Source Channel */ set_dma_start_addr(CH_MEM_STREAM2_SRC, (unsigned long)buf); set_dma_x_count(CH_MEM_STREAM2_SRC, len); set_dma_x_modify(CH_MEM_STREAM2_SRC, sizeof(char)); - set_dma_config(CH_MEM_STREAM2_SRC, RESTART); + set_dma_config(CH_MEM_STREAM2_SRC, 0); /* Destination Channel */ set_dma_start_addr(CH_MEM_STREAM2_DEST, coreb_base + p); set_dma_x_count(CH_MEM_STREAM2_DEST, len); @@ -135,11 +138,12 @@ static ssize_t coreb_read(struct file *file, char *buf, size_t count, coreb_dma_done = 0; + invalidate_dcache_range((unsigned long)buf, (unsigned long)(buf+len)); /* Source Channel */ set_dma_start_addr(CH_MEM_STREAM2_SRC, coreb_base + p); set_dma_x_count(CH_MEM_STREAM2_SRC, len); set_dma_x_modify(CH_MEM_STREAM2_SRC, sizeof(char)); - set_dma_config(CH_MEM_STREAM2_SRC, RESTART); + set_dma_config(CH_MEM_STREAM2_SRC, 0); /* Destination Channel */ set_dma_start_addr(CH_MEM_STREAM2_DEST, (unsigned long)buf); set_dma_x_count(CH_MEM_STREAM2_DEST, len); @@ -266,7 +270,7 @@ static int coreb_ioctl(struct inode *inode, struct file *file, coreb_status |= COREB_IS_RUNNING; bfin_write_SICA_SYSCR(bfin_read_SICA_SYSCR() & ~0x0020); SSYNC(); - spin_lock_irq(&coreb_lock); + spin_unlock_irq(&coreb_lock); break; #if defined(CONFIG_BF561_COREB_RESET) case CMD_COREB_STOP: @@ -275,7 +279,7 @@ static int coreb_ioctl(struct inode *inode, struct file *file, bfin_write_SICA_SYSCR(bfin_read_SICA_SYSCR() | 0x0020); bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | 0x0080); coreb_status &= ~COREB_IS_RUNNING; - spin_lock_irq(&coreb_lock); + spin_unlock_irq(&coreb_lock); break; case CMD_COREB_RESET: printk(KERN_INFO "Resetting Core B\n"); -- cgit v0.10.2 -- cgit v0.10.2 From 79f1ec862ae2e693b85fd7c94654ba1779ff5863 Mon Sep 17 00:00:00 2001 From: Joe Perches Date: Mon, 24 Dec 2007 20:03:51 +0800 Subject: [Blackfin] arch: Spelling fixes Signed-off-by: Joe Perches Signed-off-by: Mike Frysinger Signed-off-by: Bryan Wu diff --git a/arch/blackfin/kernel/early_printk.c b/arch/blackfin/kernel/early_printk.c index c892777..60f67f9 100644 --- a/arch/blackfin/kernel/early_printk.c +++ b/arch/blackfin/kernel/early_printk.c @@ -187,7 +187,7 @@ asmlinkage void __init init_early_exception_vectors(void) bfin_write_EVT15(early_trap); CSYNC(); - /* Set all the return from interupt, exception, NMI to a known place + /* Set all the return from interrupt, exception, NMI to a known place * so if we do a RETI, RETX or RETN by mistake - we go somewhere known * Note - don't change RETS - we are in a subroutine, or * RETE - since it might screw up if emulator is attached diff --git a/arch/blackfin/mach-bf548/ints-priority.c b/arch/blackfin/mach-bf548/ints-priority.c index 05e3b3c..2665653 100644 --- a/arch/blackfin/mach-bf548/ints-priority.c +++ b/arch/blackfin/mach-bf548/ints-priority.c @@ -4,7 +4,7 @@ * Author: Michael Hennerich * * Created: - * Description: Set up the interupt priorities + * Description: Set up the interrupt priorities * * Modified: * Copyright 2004-2006 Analog Devices Inc. -- cgit v0.10.2 From 7cc1c4b2c44d7807f55da6a36f5b2e49977c67b7 Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Mon, 24 Dec 2007 20:05:09 +0800 Subject: [Blackfin] arch: update to latest anomaly sheets Signed-off-by: Mike Frysinger Signed-off-by: Bryan Wu diff --git a/include/asm-blackfin/mach-bf533/anomaly.h b/include/asm-blackfin/mach-bf533/anomaly.h index f36ff5af..98209d4 100644 --- a/include/asm-blackfin/mach-bf533/anomaly.h +++ b/include/asm-blackfin/mach-bf533/anomaly.h @@ -7,9 +7,7 @@ */ /* This file shoule be up to date with: - * - Revision X, March 23, 2007; ADSP-BF533 Blackfin Processor Anomaly List - * - Revision AB, March 23, 2007; ADSP-BF532 Blackfin Processor Anomaly List - * - Revision W, March 23, 2007; ADSP-BF531 Blackfin Processor Anomaly List + * - Revision B, 12/10/2007; ADSP-BF531/BF532/BF533 Blackfin Processor Anomaly List */ #ifndef _MACH_ANOMALY_H_ @@ -17,7 +15,7 @@ /* We do not support 0.1 or 0.2 silicon - sorry */ #if __SILICON_REVISION__ < 3 -# error Kernel will not work on BF533 silicon version 0.0, 0.1, or 0.2 +# error will not work on BF533 silicon version 0.0, 0.1, or 0.2 #endif #if defined(__ADSPBF531__) @@ -251,6 +249,12 @@ #define ANOMALY_05000192 (__SILICON_REVISION__ < 3) /* Internal Voltage Regulator may not start up */ #define ANOMALY_05000206 (__SILICON_REVISION__ < 3) +/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */ +#define ANOMALY_05000357 (1) +/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */ +#define ANOMALY_05000366 (1) +/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */ +#define ANOMALY_05000371 (1) /* Anomalies that don't exist on this proc */ #define ANOMALY_05000266 (0) diff --git a/include/asm-blackfin/mach-bf537/anomaly.h b/include/asm-blackfin/mach-bf537/anomaly.h index 2b66ecf..746a794 100644 --- a/include/asm-blackfin/mach-bf537/anomaly.h +++ b/include/asm-blackfin/mach-bf537/anomaly.h @@ -7,9 +7,7 @@ */ /* This file shoule be up to date with: - * - Revision M, March 13, 2007; ADSP-BF537 Blackfin Processor Anomaly List - * - Revision L, March 13, 2007; ADSP-BF536 Blackfin Processor Anomaly List - * - Revision M, March 13, 2007; ADSP-BF534 Blackfin Processor Anomaly List + * - Revision A, 09/04/2007; ADSP-BF534/ADSP-BF536/ADSP-BF537 Blackfin Processor Anomaly List */ #ifndef _MACH_ANOMALY_H_ @@ -17,7 +15,7 @@ /* We do not support 0.1 silicon - sorry */ #if __SILICON_REVISION__ < 2 -# error Kernel will not work on BF537 silicon version 0.0 or 0.1 +# error will not work on BF537 silicon version 0.0 or 0.1 #endif #if defined(__ADSPBF534__) @@ -44,6 +42,8 @@ #define ANOMALY_05000122 (1) /* Killed 32-bit MMR write leads to next system MMR access thinking it should be 32-bit */ #define ANOMALY_05000157 (__SILICON_REVISION__ < 2) +/* Turning SPORTs on while External Frame Sync Is Active May Corrupt Data */ +#define ANOMALY_05000167 (1) /* PPI_DELAY not functional in PPI modes with 0 frame syncs */ #define ANOMALY_05000180 (1) /* Instruction Cache Is Not Functional */ @@ -130,6 +130,12 @@ #define ANOMALY_05000321 (__SILICON_REVISION__ < 3) /* EMAC RMII mode at 10-Base-T speed: RX frames not received properly */ #define ANOMALY_05000322 (1) +/* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */ +#define ANOMALY_05000341 (__SILICON_REVISION__ >= 3) +/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */ +#define ANOMALY_05000357 (1) +/* DMAs that Go Urgent during Tight Core Writes to External Memory Are Blocked */ +#define ANOMALY_05000359 (1) /* Anomalies that don't exist on this proc */ #define ANOMALY_05000125 (0) diff --git a/include/asm-blackfin/mach-bf548/anomaly.h b/include/asm-blackfin/mach-bf548/anomaly.h index c5b6375..850dc12 100644 --- a/include/asm-blackfin/mach-bf548/anomaly.h +++ b/include/asm-blackfin/mach-bf548/anomaly.h @@ -7,7 +7,7 @@ */ /* This file shoule be up to date with: - * - Revision C, July 16, 2007; ADSP-BF549 Silicon Anomaly List + * - Revision E, 11/28/2007; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List */ #ifndef _MACH_ANOMALY_H_ @@ -26,47 +26,59 @@ /* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */ #define ANOMALY_05000272 (1) /* False Hardware Error Exception when ISR context is not restored */ -#define ANOMALY_05000281 (1) +#define ANOMALY_05000281 (__SILICON_REVISION__ < 1) /* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */ -#define ANOMALY_05000304 (1) +#define ANOMALY_05000304 (__SILICON_REVISION__ < 1) /* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ #define ANOMALY_05000310 (1) /* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ -#define ANOMALY_05000312 (1) +#define ANOMALY_05000312 (__SILICON_REVISION__ < 1) /* TWI Slave Boot Mode Is Not Functional */ -#define ANOMALY_05000324 (1) +#define ANOMALY_05000324 (__SILICON_REVISION__ < 1) /* External FIFO Boot Mode Is Not Functional */ -#define ANOMALY_05000325 (1) +#define ANOMALY_05000325 (__SILICON_REVISION__ < 1) /* Data Lost When Core and DMA Accesses Are Made to the USB FIFO Simultaneously */ -#define ANOMALY_05000327 (1) +#define ANOMALY_05000327 (__SILICON_REVISION__ < 1) /* Incorrect Access of OTP_STATUS During otp_write() Function */ -#define ANOMALY_05000328 (1) +#define ANOMALY_05000328 (__SILICON_REVISION__ < 1) /* Synchronous Burst Flash Boot Mode Is Not Functional */ -#define ANOMALY_05000329 (1) +#define ANOMALY_05000329 (__SILICON_REVISION__ < 1) /* Host DMA Boot Mode Is Not Functional */ -#define ANOMALY_05000330 (1) +#define ANOMALY_05000330 (__SILICON_REVISION__ < 1) /* Inadequate Timing Margins on DDR DQS to DQ and DQM Skew */ -#define ANOMALY_05000334 (1) +#define ANOMALY_05000334 (__SILICON_REVISION__ < 1) /* Inadequate Rotary Debounce Logic Duration */ -#define ANOMALY_05000335 (1) +#define ANOMALY_05000335 (__SILICON_REVISION__ < 1) /* Phantom Interrupt Occurs After First Configuration of Host DMA Port */ -#define ANOMALY_05000336 (1) +#define ANOMALY_05000336 (__SILICON_REVISION__ < 1) /* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */ -#define ANOMALY_05000337 (1) +#define ANOMALY_05000337 (__SILICON_REVISION__ < 1) /* Slave-Mode SPI0 MISO Failure With CPHA = 0 */ -#define ANOMALY_05000338 (1) +#define ANOMALY_05000338 (__SILICON_REVISION__ < 1) /* If Memory Reads Are Enabled on SDH or HOSTDP, Other DMAC1 Peripherals Cannot Read */ -#define ANOMALY_05000340 (1) +#define ANOMALY_05000340 (__SILICON_REVISION__ < 1) /* Boot Host Wait (HWAIT) and Boot Host Wait Alternate (HWAITA) Signals Are Swapped */ -#define ANOMALY_05000344 (1) +#define ANOMALY_05000344 (__SILICON_REVISION__ < 1) /* USB Calibration Value Is Not Intialized */ -#define ANOMALY_05000346 (1) +#define ANOMALY_05000346 (__SILICON_REVISION__ < 1) /* Boot ROM Kernel Incorrectly Alters Reset Value of USB Register */ -#define ANOMALY_05000347 (1) +#define ANOMALY_05000347 (__SILICON_REVISION__ < 1) /* Data Lost when Core Reads SDH Data FIFO */ -#define ANOMALY_05000349 (1) +#define ANOMALY_05000349 (__SILICON_REVISION__ < 1) /* PLL Status Register Is Inaccurate */ -#define ANOMALY_05000351 (1) +#define ANOMALY_05000351 (__SILICON_REVISION__ < 1) +/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */ +#define ANOMALY_05000357 (1) +/* External Memory Read Access Hangs Core With PLL Bypass */ +#define ANOMALY_05000360 (1) +/* DMAs that Go Urgent during Tight Core Writes to External Memory Are Blocked */ +#define ANOMALY_05000365 (1) +/* Addressing Conflict between Boot ROM and Asynchronous Memory */ +#define ANOMALY_05000369 (1) +/* Mobile DDR Operation Not Functional */ +#define ANOMALY_05000377 (1) +/* Security/Authentication Speedpath Causes Authentication To Fail To Initiate */ +#define ANOMALY_05000378 (1) /* Anomalies that don't exist on this proc */ #define ANOMALY_05000125 (0) diff --git a/include/asm-blackfin/mach-bf561/anomaly.h b/include/asm-blackfin/mach-bf561/anomaly.h index bed9564..0c1d461 100644 --- a/include/asm-blackfin/mach-bf561/anomaly.h +++ b/include/asm-blackfin/mach-bf561/anomaly.h @@ -7,7 +7,7 @@ */ /* This file shoule be up to date with: - * - Revision N, March 28, 2007; ADSP-BF561 Silicon Anomaly List + * - Revision O, 11/15/2007; ADSP-BF561 Blackfin Processor Anomaly List */ #ifndef _MACH_ANOMALY_H_ @@ -15,7 +15,7 @@ /* We do not support 0.1, 0.2, or 0.4 silicon - sorry */ #if __SILICON_REVISION__ < 3 || __SILICON_REVISION__ == 4 -# error Kernel will not work on BF561 silicon version 0.0, 0.1, 0.2, or 0.4 +# error will not work on BF561 silicon version 0.0, 0.1, 0.2, or 0.4 #endif /* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot 2 Not Supported */ @@ -208,6 +208,8 @@ #define ANOMALY_05000275 (__SILICON_REVISION__ > 2) /* Timing Requirements Change for External Frame Sync PPI Modes with Non-Zero PPI_DELAY */ #define ANOMALY_05000276 (__SILICON_REVISION__ < 5) +/* Writes to an I/O data register one SCLK cycle after an edge is detected may clear interrupt */ +#define ANOMALY_05000277 (__SILICON_REVISION__ < 3) /* Disabling Peripherals with DMA Running May Cause DMA System Instability */ #define ANOMALY_05000278 (__SILICON_REVISION__ < 5) /* False Hardware Error Exception When ISR Context Is Not Restored */ @@ -246,6 +248,18 @@ #define ANOMALY_05000332 (__SILICON_REVISION__ < 5) /* Flag Data Register Writes One SCLK Cycle After Edge Is Detected May Clear Interrupt Status */ #define ANOMALY_05000333 (__SILICON_REVISION__ < 5) +/* New Feature: Additional PPI Frame Sync Sampling Options (Not Available on Older Silicon) */ +#define ANOMALY_05000339 (__SILICON_REVISION__ < 5) +/* Memory DMA FIFO Causes Throughput Degradation on Writes to External Memory */ +#define ANOMALY_05000343 (__SILICON_REVISION__ < 5) +/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */ +#define ANOMALY_05000357 (1) +/* Conflicting Column Address Widths Causes SDRAM Errors */ +#define ANOMALY_05000362 (1) +/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */ +#define ANOMALY_05000366 (1) +/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */ +#define ANOMALY_05000371 (1) /* Anomalies that don't exist on this proc */ #define ANOMALY_05000158 (0) -- cgit v0.10.2 From a546b0ac5988348446e4fd5987df699b4c9b1f2a Mon Sep 17 00:00:00 2001 From: Michael Hennerich Date: Mon, 24 Dec 2007 20:19:51 +0800 Subject: [Blackfin] arch: Fix BUG - kernel sometimes would stuck with KEYBOARD_GPIO on Make sure the SYSTEM reset completes before we issue the CORE reset Signed-off-by: Michael Hennerich Signed-off-by: Bryan Wu diff --git a/arch/blackfin/kernel/reboot.c b/arch/blackfin/kernel/reboot.c index ae28aac..06501a5 100644 --- a/arch/blackfin/kernel/reboot.c +++ b/arch/blackfin/kernel/reboot.c @@ -34,9 +34,11 @@ void bfin_reset(void) while (1) { /* initiate system soft reset with magic 0x7 */ bfin_write_SWRST(0x7); + bfin_read_SWRST(); asm("ssync;"); /* clear system soft reset */ bfin_write_SWRST(0); + bfin_read_SWRST(); asm("ssync;"); /* issue core reset */ asm("raise 1"); -- cgit v0.10.2 From 6b5eace2f15b53d5a6849078d22e78db77625929 Mon Sep 17 00:00:00 2001 From: Robin Getz Date: Thu, 10 Jan 2008 17:57:56 +0800 Subject: [Blackfin] arch: Don't oops_in_progress if single step is comming from the kernel Don't oops_in_progress if single step is comming from the kernel, which happens if a single step occurs after a exception cause. This fixes up the remaining issues in the toolchain bug. Signed-off-by: Robin Getz Signed-off-by: Bryan Wu diff --git a/arch/blackfin/kernel/traps.c b/arch/blackfin/kernel/traps.c index c90f168..5e84072 100644 --- a/arch/blackfin/kernel/traps.c +++ b/arch/blackfin/kernel/traps.c @@ -201,9 +201,9 @@ asmlinkage void trap_c(struct pt_regs *fp) /* TODO: check to see if we are in some sort of deferred HWERR * that we should be able to recover from, not kernel panic */ - if ((bfin_read_IPEND() & 0xFFC0) + if ((bfin_read_IPEND() & 0xFFC0) && (trapnr != VEC_STEP) #ifdef CONFIG_KGDB - && trapnr != VEC_EXCPT02 + && (trapnr != VEC_EXCPT02) #endif ){ console_verbose(); -- cgit v0.10.2 From e31639540d2b1474766e95c1a7b1b698468ba092 Mon Sep 17 00:00:00 2001 From: Bryan Wu Date: Thu, 24 Jan 2008 16:19:15 +0800 Subject: [Blackfin] arch: enable generic GPIO based I2C driver in STAMP-BF533, EZKIT-BF533 and EZKIT-BF561 boards Signed-off-by: Bryan Wu diff --git a/arch/blackfin/mach-bf533/boards/ezkit.c b/arch/blackfin/mach-bf533/boards/ezkit.c index ead5c12..c37dd45 100644 --- a/arch/blackfin/mach-bf533/boards/ezkit.c +++ b/arch/blackfin/mach-bf533/boards/ezkit.c @@ -280,6 +280,26 @@ static struct platform_device bfin_device_gpiokeys = { }; #endif +#if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE) +#include + +static struct i2c_gpio_platform_data i2c_gpio_data = { + .sda_pin = 1, + .scl_pin = 0, + .sda_is_open_drain = 0, + .scl_is_open_drain = 0, + .udelay = 40, +}; + +static struct platform_device i2c_gpio_device = { + .name = "i2c-gpio", + .id = 0, + .dev = { + .platform_data = &i2c_gpio_data, + }, +}; +#endif + static struct platform_device *ezkit_devices[] __initdata = { #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE) &smc91x_device, @@ -308,6 +328,10 @@ static struct platform_device *ezkit_devices[] __initdata = { #if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE) &bfin_device_gpiokeys, #endif + +#if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE) + &i2c_gpio_device, +#endif }; static int __init ezkit_init(void) diff --git a/arch/blackfin/mach-bf533/boards/stamp.c b/arch/blackfin/mach-bf533/boards/stamp.c index 6898169..cd87df7 100644 --- a/arch/blackfin/mach-bf533/boards/stamp.c +++ b/arch/blackfin/mach-bf533/boards/stamp.c @@ -396,6 +396,26 @@ static struct platform_device bfin_device_gpiokeys = { }; #endif +#if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE) +#include + +static struct i2c_gpio_platform_data i2c_gpio_data = { + .sda_pin = 2, + .scl_pin = 3, + .sda_is_open_drain = 0, + .scl_is_open_drain = 0, + .udelay = 40, +}; + +static struct platform_device i2c_gpio_device = { + .name = "i2c-gpio", + .id = 0, + .dev = { + .platform_data = &i2c_gpio_data, + }, +}; +#endif + static struct platform_device *stamp_devices[] __initdata = { #if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE) &rtc_device, @@ -433,6 +453,10 @@ static struct platform_device *stamp_devices[] __initdata = { #if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE) &bfin_device_gpiokeys, #endif + +#if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE) + &i2c_gpio_device, +#endif }; static int __init stamp_init(void) diff --git a/arch/blackfin/mach-bf561/boards/ezkit.c b/arch/blackfin/mach-bf561/boards/ezkit.c index edfceb0..36114dd 100644 --- a/arch/blackfin/mach-bf561/boards/ezkit.c +++ b/arch/blackfin/mach-bf561/boards/ezkit.c @@ -270,6 +270,26 @@ static struct platform_device bfin_device_gpiokeys = { }; #endif +#if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE) +#include + +static struct i2c_gpio_platform_data i2c_gpio_data = { + .sda_pin = 1, + .scl_pin = 0, + .sda_is_open_drain = 0, + .scl_is_open_drain = 0, + .udelay = 40, +}; + +static struct platform_device i2c_gpio_device = { + .name = "i2c-gpio", + .id = 0, + .dev = { + .platform_data = &i2c_gpio_data, + }, +}; +#endif + static struct platform_device *ezkit_devices[] __initdata = { #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE) &smc91x_device, @@ -294,6 +314,10 @@ static struct platform_device *ezkit_devices[] __initdata = { #if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE) &bfin_device_gpiokeys, #endif + +#if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE) + &i2c_gpio_device, +#endif }; static int __init ezkit_init(void) -- cgit v0.10.2 From aee3a29240ad167ad7875d859506d8bb90431c70 Mon Sep 17 00:00:00 2001 From: Robin Getz Date: Fri, 11 Jan 2008 16:53:00 +0800 Subject: [Blackfin] arch: print out list of modules if kernel is crashing and tell people if the kernel is tainted Signed-off-by: Robin Getz Signed-off-by: Bryan Wu diff --git a/arch/blackfin/kernel/traps.c b/arch/blackfin/kernel/traps.c index 5e84072..66b5f3e 100644 --- a/arch/blackfin/kernel/traps.c +++ b/arch/blackfin/kernel/traps.c @@ -497,6 +497,7 @@ asmlinkage void trap_c(struct pt_regs *fp) dump_bfin_trace_buffer(); show_stack(current, &stack); if (oops_in_progress) { + print_modules(); #ifndef CONFIG_ACCESS_CHECK printk(KERN_EMERG "Please turn on " "CONFIG_ACCESS_CHECK\n"); @@ -761,7 +762,7 @@ void show_regs(struct pt_regs *fp) unsigned int i; unsigned long flags; - printk(KERN_NOTICE "\n" KERN_NOTICE "SEQUENCER STATUS:\n"); + printk(KERN_NOTICE "\n" KERN_NOTICE "SEQUENCER STATUS:\t\t%s\n", print_tainted()); printk(KERN_NOTICE " SEQSTAT: %08lx IPEND: %04lx SYSCFG: %04lx\n", (long)fp->seqstat, fp->ipend, fp->syscfg); printk(KERN_NOTICE " HWERRCAUSE: 0x%lx\n", -- cgit v0.10.2 From 7a1a6d00618bce53ae88e501ff5d4b82522db926 Mon Sep 17 00:00:00 2001 From: Bernd Schmidt Date: Fri, 11 Jan 2008 16:58:44 +0800 Subject: [Blackfin] arch: move all code related to CPLB handling into a new subdirectory under kernel/ Signed-off-by: Bernd Schmidt Signed-off-by: Bryan Wu diff --git a/arch/blackfin/Makefile b/arch/blackfin/Makefile index 0c9680e..2fc899c 100644 --- a/arch/blackfin/Makefile +++ b/arch/blackfin/Makefile @@ -82,6 +82,8 @@ core-y += arch/$(ARCH)/mach-$(MACHINE)/ core-y += arch/$(ARCH)/mach-$(MACHINE)/boards/ endif +core-y += arch/$(ARCH)/kernel/cplb-nompu/ + libs-y += arch/$(ARCH)/lib/ drivers-$(CONFIG_OPROFILE) += arch/$(ARCH)/oprofile/ diff --git a/arch/blackfin/kernel/Makefile b/arch/blackfin/kernel/Makefile index 8a4cfb2..318b9b6 100644 --- a/arch/blackfin/kernel/Makefile +++ b/arch/blackfin/kernel/Makefile @@ -7,7 +7,7 @@ extra-y := init_task.o vmlinux.lds obj-y := \ entry.o process.o bfin_ksyms.o ptrace.o setup.o signal.o \ sys_bfin.o time.o traps.o irqchip.o dma-mapping.o flat.o \ - fixed_code.o cplbinit.o cacheinit.o reboot.o bfin_gpio.o + fixed_code.o reboot.o bfin_gpio.o obj-$(CONFIG_BFIN_GPTIMERS) += gptimers.o obj-$(CONFIG_MODULES) += module.o diff --git a/arch/blackfin/kernel/cacheinit.c b/arch/blackfin/kernel/cacheinit.c deleted file mode 100644 index 62cbba7..0000000 --- a/arch/blackfin/kernel/cacheinit.c +++ /dev/null @@ -1,67 +0,0 @@ -/* - * Copyright 2004-2007 Analog Devices Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, see the file COPYING, or write - * to the Free Software Foundation, Inc., - * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include - -#include -#include -#include -#include - -#if defined(CONFIG_BFIN_ICACHE) -void bfin_icache_init(void) -{ - unsigned long *table = icplb_table; - unsigned long ctrl; - int i; - - for (i = 0; i < MAX_CPLBS; i++) { - unsigned long addr = *table++; - unsigned long data = *table++; - if (addr == (unsigned long)-1) - break; - bfin_write32(ICPLB_ADDR0 + i * 4, addr); - bfin_write32(ICPLB_DATA0 + i * 4, data); - } - ctrl = bfin_read_IMEM_CONTROL(); - ctrl |= IMC | ENICPLB; - bfin_write_IMEM_CONTROL(ctrl); -} -#endif - -#if defined(CONFIG_BFIN_DCACHE) -void bfin_dcache_init(void) -{ - unsigned long *table = dcplb_table; - unsigned long ctrl; - int i; - - for (i = 0; i < MAX_CPLBS; i++) { - unsigned long addr = *table++; - unsigned long data = *table++; - if (addr == (unsigned long)-1) - break; - bfin_write32(DCPLB_ADDR0 + i * 4, addr); - bfin_write32(DCPLB_DATA0 + i * 4, data); - } - ctrl = bfin_read_DMEM_CONTROL(); - ctrl |= DMEM_CNTR; - bfin_write_DMEM_CONTROL(ctrl); -} -#endif diff --git a/arch/blackfin/kernel/cplb-nompu/Makefile b/arch/blackfin/kernel/cplb-nompu/Makefile new file mode 100644 index 0000000..d36ea9b --- /dev/null +++ b/arch/blackfin/kernel/cplb-nompu/Makefile @@ -0,0 +1,8 @@ +# +# arch/blackfin/kernel/cplb-nompu/Makefile +# + +obj-y := cplbinit.o cacheinit.o cplbhdlr.o cplbmgr.o + +obj-$(CONFIG_CPLB_INFO) += cplbinfo.o + diff --git a/arch/blackfin/kernel/cplb-nompu/cacheinit.c b/arch/blackfin/kernel/cplb-nompu/cacheinit.c new file mode 100644 index 0000000..62cbba7 --- /dev/null +++ b/arch/blackfin/kernel/cplb-nompu/cacheinit.c @@ -0,0 +1,67 @@ +/* + * Copyright 2004-2007 Analog Devices Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see the file COPYING, or write + * to the Free Software Foundation, Inc., + * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include + +#include +#include +#include +#include + +#if defined(CONFIG_BFIN_ICACHE) +void bfin_icache_init(void) +{ + unsigned long *table = icplb_table; + unsigned long ctrl; + int i; + + for (i = 0; i < MAX_CPLBS; i++) { + unsigned long addr = *table++; + unsigned long data = *table++; + if (addr == (unsigned long)-1) + break; + bfin_write32(ICPLB_ADDR0 + i * 4, addr); + bfin_write32(ICPLB_DATA0 + i * 4, data); + } + ctrl = bfin_read_IMEM_CONTROL(); + ctrl |= IMC | ENICPLB; + bfin_write_IMEM_CONTROL(ctrl); +} +#endif + +#if defined(CONFIG_BFIN_DCACHE) +void bfin_dcache_init(void) +{ + unsigned long *table = dcplb_table; + unsigned long ctrl; + int i; + + for (i = 0; i < MAX_CPLBS; i++) { + unsigned long addr = *table++; + unsigned long data = *table++; + if (addr == (unsigned long)-1) + break; + bfin_write32(DCPLB_ADDR0 + i * 4, addr); + bfin_write32(DCPLB_DATA0 + i * 4, data); + } + ctrl = bfin_read_DMEM_CONTROL(); + ctrl |= DMEM_CNTR; + bfin_write_DMEM_CONTROL(ctrl); +} +#endif diff --git a/arch/blackfin/kernel/cplb-nompu/cplbhdlr.S b/arch/blackfin/kernel/cplb-nompu/cplbhdlr.S new file mode 100644 index 0000000..2788532 --- /dev/null +++ b/arch/blackfin/kernel/cplb-nompu/cplbhdlr.S @@ -0,0 +1,130 @@ +/* + * File: arch/blackfin/mach-common/cplbhdlr.S + * Based on: + * Author: LG Soft India + * + * Created: ? + * Description: CPLB exception handler + * + * Modified: + * Copyright 2004-2006 Analog Devices Inc. + * + * Bugs: Enter bugs at http://blackfin.uclinux.org/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see the file COPYING, or write + * to the Free Software Foundation, Inc., + * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include + +#ifdef CONFIG_EXCPT_IRQ_SYSC_L1 +.section .l1.text +#else +.text +#endif + +.type _cplb_mgr, STT_FUNC; +.type _panic_cplb_error, STT_FUNC; + +.align 2 + +ENTRY(__cplb_hdr) + R2 = SEQSTAT; + + /* Mask the contents of SEQSTAT and leave only EXCAUSE in R2 */ + R2 <<= 26; + R2 >>= 26; + + R1 = 0x23; /* Data access CPLB protection violation */ + CC = R2 == R1; + IF !CC JUMP .Lnot_data_write; + R0 = 2; /* is a write to data space*/ + JUMP .Lis_icplb_miss; + +.Lnot_data_write: + R1 = 0x2C; /* CPLB miss on an instruction fetch */ + CC = R2 == R1; + R0 = 0; /* is_data_miss == False*/ + IF CC JUMP .Lis_icplb_miss; + + R1 = 0x26; + CC = R2 == R1; + IF !CC JUMP .Lunknown; + + R0 = 1; /* is_data_miss == True*/ + +.Lis_icplb_miss: + +#if defined(CONFIG_BFIN_ICACHE) || defined(CONFIG_BFIN_DCACHE) +# if defined(CONFIG_BFIN_ICACHE) && !defined(CONFIG_BFIN_DCACHE) + R1 = CPLB_ENABLE_ICACHE; +# endif +# if !defined(CONFIG_BFIN_ICACHE) && defined(CONFIG_BFIN_DCACHE) + R1 = CPLB_ENABLE_DCACHE; +# endif +# if defined(CONFIG_BFIN_ICACHE) && defined(CONFIG_BFIN_DCACHE) + R1 = CPLB_ENABLE_DCACHE | CPLB_ENABLE_ICACHE; +# endif +#else + R1 = 0; +#endif + + [--SP] = RETS; + CALL _cplb_mgr; + RETS = [SP++]; + CC = R0 == 0; + IF !CC JUMP .Lnot_replaced; + RTS; + +/* + * Diagnostic exception handlers + */ +.Lunknown: + R0 = CPLB_UNKNOWN_ERR; + JUMP .Lcplb_error; + +.Lnot_replaced: + CC = R0 == CPLB_NO_UNLOCKED; + IF !CC JUMP .Lnext_check; + R0 = CPLB_NO_UNLOCKED; + JUMP .Lcplb_error; + +.Lnext_check: + CC = R0 == CPLB_NO_ADDR_MATCH; + IF !CC JUMP .Lnext_check2; + R0 = CPLB_NO_ADDR_MATCH; + JUMP .Lcplb_error; + +.Lnext_check2: + CC = R0 == CPLB_PROT_VIOL; + IF !CC JUMP .Lstrange_return_from_cplb_mgr; + R0 = CPLB_PROT_VIOL; + JUMP .Lcplb_error; + +.Lstrange_return_from_cplb_mgr: + IDLE; + CSYNC; + JUMP .Lstrange_return_from_cplb_mgr; + +.Lcplb_error: + R1 = sp; + SP += -12; + call _panic_cplb_error; + SP += 12; + JUMP _handle_bad_cplb; + +ENDPROC(__cplb_hdr) diff --git a/arch/blackfin/kernel/cplb-nompu/cplbinfo.c b/arch/blackfin/kernel/cplb-nompu/cplbinfo.c new file mode 100644 index 0000000..a4f0b42 --- /dev/null +++ b/arch/blackfin/kernel/cplb-nompu/cplbinfo.c @@ -0,0 +1,208 @@ +/* + * File: arch/blackfin/mach-common/cplbinfo.c + * Based on: + * Author: Sonic Zhang + * + * Created: Jan. 2005 + * Description: Display CPLB status + * + * Modified: + * Copyright 2004-2006 Analog Devices Inc. + * + * Bugs: Enter bugs at http://blackfin.uclinux.org/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see the file COPYING, or write + * to the Free Software Foundation, Inc., + * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#define CPLB_I 1 +#define CPLB_D 2 + +#define SYNC_SYS SSYNC() +#define SYNC_CORE CSYNC() + +#define CPLB_BIT_PAGESIZE 0x30000 + +static int page_size_table[4] = { + 0x00000400, /* 1K */ + 0x00001000, /* 4K */ + 0x00100000, /* 1M */ + 0x00400000 /* 4M */ +}; + +static char page_size_string_table[][4] = { "1K", "4K", "1M", "4M" }; + +static int cplb_find_entry(unsigned long *cplb_addr, + unsigned long *cplb_data, unsigned long addr, + unsigned long data) +{ + int ii; + + for (ii = 0; ii < 16; ii++) + if (addr >= cplb_addr[ii] && addr < cplb_addr[ii] + + page_size_table[(cplb_data[ii] & CPLB_BIT_PAGESIZE) >> 16] + && (cplb_data[ii] == data)) + return ii; + + return -1; +} + +static char *cplb_print_entry(char *buf, int type) +{ + unsigned long *p_addr = dpdt_table; + unsigned long *p_data = dpdt_table + 1; + unsigned long *p_icount = dpdt_swapcount_table; + unsigned long *p_ocount = dpdt_swapcount_table + 1; + unsigned long *cplb_addr = (unsigned long *)DCPLB_ADDR0; + unsigned long *cplb_data = (unsigned long *)DCPLB_DATA0; + int entry = 0, used_cplb = 0; + + if (type == CPLB_I) { + buf += sprintf(buf, "Instruction CPLB entry:\n"); + p_addr = ipdt_table; + p_data = ipdt_table + 1; + p_icount = ipdt_swapcount_table; + p_ocount = ipdt_swapcount_table + 1; + cplb_addr = (unsigned long *)ICPLB_ADDR0; + cplb_data = (unsigned long *)ICPLB_DATA0; + } else + buf += sprintf(buf, "Data CPLB entry:\n"); + + buf += sprintf(buf, "Address\t\tData\tSize\tValid\tLocked\tSwapin\tiCount\toCount\n"); + + while (*p_addr != 0xffffffff) { + entry = cplb_find_entry(cplb_addr, cplb_data, *p_addr, *p_data); + if (entry >= 0) + used_cplb |= 1 << entry; + + buf += + sprintf(buf, + "0x%08lx\t0x%05lx\t%s\t%c\t%c\t%2d\t%ld\t%ld\n", + *p_addr, *p_data, + page_size_string_table[(*p_data & 0x30000) >> 16], + (*p_data & CPLB_VALID) ? 'Y' : 'N', + (*p_data & CPLB_LOCK) ? 'Y' : 'N', entry, *p_icount, + *p_ocount); + + p_addr += 2; + p_data += 2; + p_icount += 2; + p_ocount += 2; + } + + if (used_cplb != 0xffff) { + buf += sprintf(buf, "Unused/mismatched CPLBs:\n"); + + for (entry = 0; entry < 16; entry++) + if (0 == ((1 << entry) & used_cplb)) { + int flags = cplb_data[entry]; + buf += + sprintf(buf, + "%2d: 0x%08lx\t0x%05x\t%s\t%c\t%c\n", + entry, cplb_addr[entry], flags, + page_size_string_table[(flags & + 0x30000) >> + 16], + (flags & CPLB_VALID) ? 'Y' : 'N', + (flags & CPLB_LOCK) ? 'Y' : 'N'); + } + } + + buf += sprintf(buf, "\n"); + + return buf; +} + +static int cplbinfo_proc_output(char *buf) +{ + char *p; + + p = buf; + + p += sprintf(p, "------------------ CPLB Information ------------------\n\n"); + + if (bfin_read_IMEM_CONTROL() & ENICPLB) + p = cplb_print_entry(p, CPLB_I); + else + p += sprintf(p, "Instruction CPLB is disabled.\n\n"); + + if (bfin_read_DMEM_CONTROL() & ENDCPLB) + p = cplb_print_entry(p, CPLB_D); + else + p += sprintf(p, "Data CPLB is disabled.\n"); + + return p - buf; +} + +static int cplbinfo_read_proc(char *page, char **start, off_t off, + int count, int *eof, void *data) +{ + int len; + + len = cplbinfo_proc_output(page); + if (len <= off + count) + *eof = 1; + *start = page + off; + len -= off; + if (len > count) + len = count; + if (len < 0) + len = 0; + return len; +} + +static int cplbinfo_write_proc(struct file *file, const char __user *buffer, + unsigned long count, void *data) +{ + printk(KERN_INFO "Reset the CPLB swap in/out counts.\n"); + memset(ipdt_swapcount_table, 0, MAX_SWITCH_I_CPLBS * sizeof(unsigned long)); + memset(dpdt_swapcount_table, 0, MAX_SWITCH_D_CPLBS * sizeof(unsigned long)); + + return count; +} + +static int __init cplbinfo_init(void) +{ + struct proc_dir_entry *entry; + + entry = create_proc_entry("cplbinfo", 0, NULL); + if (!entry) + return -ENOMEM; + + entry->read_proc = cplbinfo_read_proc; + entry->write_proc = cplbinfo_write_proc; + entry->data = NULL; + + return 0; +} + +static void __exit cplbinfo_exit(void) +{ + remove_proc_entry("cplbinfo", NULL); +} + +module_init(cplbinfo_init); +module_exit(cplbinfo_exit); diff --git a/arch/blackfin/kernel/cplb-nompu/cplbinit.c b/arch/blackfin/kernel/cplb-nompu/cplbinit.c new file mode 100644 index 0000000..6320bc4 --- /dev/null +++ b/arch/blackfin/kernel/cplb-nompu/cplbinit.c @@ -0,0 +1,437 @@ +/* + * Blackfin CPLB initialization + * + * Copyright 2004-2007 Analog Devices Inc. + * + * Bugs: Enter bugs at http://blackfin.uclinux.org/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see the file COPYING, or write + * to the Free Software Foundation, Inc., + * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include + +#include +#include +#include + +u_long icplb_table[MAX_CPLBS + 1]; +u_long dcplb_table[MAX_CPLBS + 1]; + +#ifdef CONFIG_CPLB_SWITCH_TAB_L1 +# define PDT_ATTR __attribute__((l1_data)) +#else +# define PDT_ATTR +#endif + +u_long ipdt_table[MAX_SWITCH_I_CPLBS + 1] PDT_ATTR; +u_long dpdt_table[MAX_SWITCH_D_CPLBS + 1] PDT_ATTR; + +#ifdef CONFIG_CPLB_INFO +u_long ipdt_swapcount_table[MAX_SWITCH_I_CPLBS] PDT_ATTR; +u_long dpdt_swapcount_table[MAX_SWITCH_D_CPLBS] PDT_ATTR; +#endif + +struct s_cplb { + struct cplb_tab init_i; + struct cplb_tab init_d; + struct cplb_tab switch_i; + struct cplb_tab switch_d; +}; + +#if defined(CONFIG_BFIN_DCACHE) || defined(CONFIG_BFIN_ICACHE) +static struct cplb_desc cplb_data[] = { + { + .start = 0, + .end = SIZE_1K, + .psize = SIZE_1K, + .attr = INITIAL_T | SWITCH_T | I_CPLB | D_CPLB, + .i_conf = SDRAM_OOPS, + .d_conf = SDRAM_OOPS, +#if defined(CONFIG_DEBUG_HUNT_FOR_ZERO) + .valid = 1, +#else + .valid = 0, +#endif + .name = "Zero Pointer Guard Page", + }, + { + .start = L1_CODE_START, + .end = L1_CODE_START + L1_CODE_LENGTH, + .psize = SIZE_4M, + .attr = INITIAL_T | SWITCH_T | I_CPLB, + .i_conf = L1_IMEMORY, + .d_conf = 0, + .valid = 1, + .name = "L1 I-Memory", + }, + { + .start = L1_DATA_A_START, + .end = L1_DATA_B_START + L1_DATA_B_LENGTH, + .psize = SIZE_4M, + .attr = INITIAL_T | SWITCH_T | D_CPLB, + .i_conf = 0, + .d_conf = L1_DMEMORY, +#if ((L1_DATA_A_LENGTH > 0) || (L1_DATA_B_LENGTH > 0)) + .valid = 1, +#else + .valid = 0, +#endif + .name = "L1 D-Memory", + }, + { + .start = 0, + .end = 0, /* dynamic */ + .psize = 0, + .attr = INITIAL_T | SWITCH_T | I_CPLB | D_CPLB, + .i_conf = SDRAM_IGENERIC, + .d_conf = SDRAM_DGENERIC, + .valid = 1, + .name = "Kernel Memory", + }, + { + .start = 0, /* dynamic */ + .end = 0, /* dynamic */ + .psize = 0, + .attr = INITIAL_T | SWITCH_T | D_CPLB, + .i_conf = SDRAM_IGENERIC, + .d_conf = SDRAM_DNON_CHBL, + .valid = 1, + .name = "uClinux MTD Memory", + }, + { + .start = 0, /* dynamic */ + .end = 0, /* dynamic */ + .psize = SIZE_1M, + .attr = INITIAL_T | SWITCH_T | D_CPLB, + .d_conf = SDRAM_DNON_CHBL, + .valid = 1, + .name = "Uncached DMA Zone", + }, + { + .start = 0, /* dynamic */ + .end = 0, /* dynamic */ + .psize = 0, + .attr = SWITCH_T | D_CPLB, + .i_conf = 0, /* dynamic */ + .d_conf = 0, /* dynamic */ + .valid = 1, + .name = "Reserved Memory", + }, + { + .start = ASYNC_BANK0_BASE, + .end = ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE, + .psize = 0, + .attr = SWITCH_T | D_CPLB, + .d_conf = SDRAM_EBIU, + .valid = 1, + .name = "Asynchronous Memory Banks", + }, + { +#ifdef L2_START + .start = L2_START, + .end = L2_START + L2_LENGTH, + .psize = SIZE_1M, + .attr = SWITCH_T | I_CPLB | D_CPLB, + .i_conf = L2_MEMORY, + .d_conf = L2_MEMORY, + .valid = 1, +#else + .valid = 0, +#endif + .name = "L2 Memory", + }, + { + .start = BOOT_ROM_START, + .end = BOOT_ROM_START + BOOT_ROM_LENGTH, + .psize = SIZE_1M, + .attr = SWITCH_T | I_CPLB | D_CPLB, + .i_conf = SDRAM_IGENERIC, + .d_conf = SDRAM_DGENERIC, + .valid = 1, + .name = "On-Chip BootROM", + }, +}; + +static u16 __init lock_kernel_check(u32 start, u32 end) +{ + if ((end <= (u32) _end && end >= (u32)_stext) || + (start <= (u32) _end && start >= (u32)_stext)) + return IN_KERNEL; + return 0; +} + +static unsigned short __init +fill_cplbtab(struct cplb_tab *table, + unsigned long start, unsigned long end, + unsigned long block_size, unsigned long cplb_data) +{ + int i; + + switch (block_size) { + case SIZE_4M: + i = 3; + break; + case SIZE_1M: + i = 2; + break; + case SIZE_4K: + i = 1; + break; + case SIZE_1K: + default: + i = 0; + break; + } + + cplb_data = (cplb_data & ~(3 << 16)) | (i << 16); + + while ((start < end) && (table->pos < table->size)) { + + table->tab[table->pos++] = start; + + if (lock_kernel_check(start, start + block_size) == IN_KERNEL) + table->tab[table->pos++] = + cplb_data | CPLB_LOCK | CPLB_DIRTY; + else + table->tab[table->pos++] = cplb_data; + + start += block_size; + } + return 0; +} + +static unsigned short __init +close_cplbtab(struct cplb_tab *table) +{ + + while (table->pos < table->size) { + + table->tab[table->pos++] = 0; + table->tab[table->pos++] = 0; /* !CPLB_VALID */ + } + return 0; +} + +/* helper function */ +static void __fill_code_cplbtab(struct cplb_tab *t, int i, u32 a_start, u32 a_end) +{ + if (cplb_data[i].psize) { + fill_cplbtab(t, + cplb_data[i].start, + cplb_data[i].end, + cplb_data[i].psize, + cplb_data[i].i_conf); + } else { +#if defined(CONFIG_BFIN_ICACHE) + if (ANOMALY_05000263 && i == SDRAM_KERN) { + fill_cplbtab(t, + cplb_data[i].start, + cplb_data[i].end, + SIZE_4M, + cplb_data[i].i_conf); + } else +#endif + { + fill_cplbtab(t, + cplb_data[i].start, + a_start, + SIZE_1M, + cplb_data[i].i_conf); + fill_cplbtab(t, + a_start, + a_end, + SIZE_4M, + cplb_data[i].i_conf); + fill_cplbtab(t, a_end, + cplb_data[i].end, + SIZE_1M, + cplb_data[i].i_conf); + } + } +} + +static void __fill_data_cplbtab(struct cplb_tab *t, int i, u32 a_start, u32 a_end) +{ + if (cplb_data[i].psize) { + fill_cplbtab(t, + cplb_data[i].start, + cplb_data[i].end, + cplb_data[i].psize, + cplb_data[i].d_conf); + } else { + fill_cplbtab(t, + cplb_data[i].start, + a_start, SIZE_1M, + cplb_data[i].d_conf); + fill_cplbtab(t, a_start, + a_end, SIZE_4M, + cplb_data[i].d_conf); + fill_cplbtab(t, a_end, + cplb_data[i].end, + SIZE_1M, + cplb_data[i].d_conf); + } +} + +void __init generate_cpl_tables(void) +{ + + u16 i, j, process; + u32 a_start, a_end, as, ae, as_1m; + + struct cplb_tab *t_i = NULL; + struct cplb_tab *t_d = NULL; + struct s_cplb cplb; + + cplb.init_i.size = MAX_CPLBS; + cplb.init_d.size = MAX_CPLBS; + cplb.switch_i.size = MAX_SWITCH_I_CPLBS; + cplb.switch_d.size = MAX_SWITCH_D_CPLBS; + + cplb.init_i.pos = 0; + cplb.init_d.pos = 0; + cplb.switch_i.pos = 0; + cplb.switch_d.pos = 0; + + cplb.init_i.tab = icplb_table; + cplb.init_d.tab = dcplb_table; + cplb.switch_i.tab = ipdt_table; + cplb.switch_d.tab = dpdt_table; + + cplb_data[SDRAM_KERN].end = memory_end; + +#ifdef CONFIG_MTD_UCLINUX + cplb_data[SDRAM_RAM_MTD].start = memory_mtd_start; + cplb_data[SDRAM_RAM_MTD].end = memory_mtd_start + mtd_size; + cplb_data[SDRAM_RAM_MTD].valid = mtd_size > 0; +# if defined(CONFIG_ROMFS_FS) + cplb_data[SDRAM_RAM_MTD].attr |= I_CPLB; + + /* + * The ROMFS_FS size is often not multiple of 1MB. + * This can cause multiple CPLB sets covering the same memory area. + * This will then cause multiple CPLB hit exceptions. + * Workaround: We ensure a contiguous memory area by extending the kernel + * memory section over the mtd section. + * For ROMFS_FS memory must be covered with ICPLBs anyways. + * So there is no difference between kernel and mtd memory setup. + */ + + cplb_data[SDRAM_KERN].end = memory_mtd_start + mtd_size;; + cplb_data[SDRAM_RAM_MTD].valid = 0; + +# endif +#else + cplb_data[SDRAM_RAM_MTD].valid = 0; +#endif + + cplb_data[SDRAM_DMAZ].start = _ramend - DMA_UNCACHED_REGION; + cplb_data[SDRAM_DMAZ].end = _ramend; + + cplb_data[RES_MEM].start = _ramend; + cplb_data[RES_MEM].end = physical_mem_end; + + if (reserved_mem_dcache_on) + cplb_data[RES_MEM].d_conf = SDRAM_DGENERIC; + else + cplb_data[RES_MEM].d_conf = SDRAM_DNON_CHBL; + + if (reserved_mem_icache_on) + cplb_data[RES_MEM].i_conf = SDRAM_IGENERIC; + else + cplb_data[RES_MEM].i_conf = SDRAM_INON_CHBL; + + for (i = ZERO_P; i < ARRAY_SIZE(cplb_data); ++i) { + if (!cplb_data[i].valid) + continue; + + as_1m = cplb_data[i].start % SIZE_1M; + + /* We need to make sure all sections are properly 1M aligned + * However between Kernel Memory and the Kernel mtd section, depending on the + * rootfs size, there can be overlapping memory areas. + */ + + if (as_1m && i != L1I_MEM && i != L1D_MEM) { +#ifdef CONFIG_MTD_UCLINUX + if (i == SDRAM_RAM_MTD) { + if ((cplb_data[SDRAM_KERN].end + 1) > cplb_data[SDRAM_RAM_MTD].start) + cplb_data[SDRAM_RAM_MTD].start = (cplb_data[i].start & (-2*SIZE_1M)) + SIZE_1M; + else + cplb_data[SDRAM_RAM_MTD].start = (cplb_data[i].start & (-2*SIZE_1M)); + } else +#endif + printk(KERN_WARNING "Unaligned Start of %s at 0x%X\n", + cplb_data[i].name, cplb_data[i].start); + } + + as = cplb_data[i].start % SIZE_4M; + ae = cplb_data[i].end % SIZE_4M; + + if (as) + a_start = cplb_data[i].start + (SIZE_4M - (as)); + else + a_start = cplb_data[i].start; + + a_end = cplb_data[i].end - ae; + + for (j = INITIAL_T; j <= SWITCH_T; j++) { + + switch (j) { + case INITIAL_T: + if (cplb_data[i].attr & INITIAL_T) { + t_i = &cplb.init_i; + t_d = &cplb.init_d; + process = 1; + } else + process = 0; + break; + case SWITCH_T: + if (cplb_data[i].attr & SWITCH_T) { + t_i = &cplb.switch_i; + t_d = &cplb.switch_d; + process = 1; + } else + process = 0; + break; + default: + process = 0; + break; + } + + if (!process) + continue; + if (cplb_data[i].attr & I_CPLB) + __fill_code_cplbtab(t_i, i, a_start, a_end); + + if (cplb_data[i].attr & D_CPLB) + __fill_data_cplbtab(t_d, i, a_start, a_end); + } + } + +/* close tables */ + + close_cplbtab(&cplb.init_i); + close_cplbtab(&cplb.init_d); + + cplb.init_i.tab[cplb.init_i.pos] = -1; + cplb.init_d.tab[cplb.init_d.pos] = -1; + cplb.switch_i.tab[cplb.switch_i.pos] = -1; + cplb.switch_d.tab[cplb.switch_d.pos] = -1; + +} + +#endif + diff --git a/arch/blackfin/kernel/cplb-nompu/cplbmgr.S b/arch/blackfin/kernel/cplb-nompu/cplbmgr.S new file mode 100644 index 0000000..f5cf3ac --- /dev/null +++ b/arch/blackfin/kernel/cplb-nompu/cplbmgr.S @@ -0,0 +1,646 @@ +/* + * File: arch/blackfin/mach-common/cplbmgtr.S + * Based on: + * Author: LG Soft India + * + * Created: ? + * Description: CPLB replacement routine for CPLB mismatch + * + * Modified: + * Copyright 2004-2006 Analog Devices Inc. + * + * Bugs: Enter bugs at http://blackfin.uclinux.org/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see the file COPYING, or write + * to the Free Software Foundation, Inc., + * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* Usage: int _cplb_mgr(is_data_miss,int enable_cache) + * is_data_miss==2 => Mark as Dirty, write to the clean data page + * is_data_miss==1 => Replace a data CPLB. + * is_data_miss==0 => Replace an instruction CPLB. + * + * Returns: + * CPLB_RELOADED => Successfully updated CPLB table. + * CPLB_NO_UNLOCKED => All CPLBs are locked, so cannot be evicted. + * This indicates that the CPLBs in the configuration + * tablei are badly configured, as this should never + * occur. + * CPLB_NO_ADDR_MATCH => The address being accessed, that triggered the + * exception, is not covered by any of the CPLBs in + * the configuration table. The application is + * presumably misbehaving. + * CPLB_PROT_VIOL => The address being accessed, that triggered the + * exception, was not a first-write to a clean Write + * Back Data page, and so presumably is a genuine + * violation of the page's protection attributes. + * The application is misbehaving. + */ + +#include +#include +#include + +#ifdef CONFIG_EXCPT_IRQ_SYSC_L1 +.section .l1.text +#else +.text +#endif + +.align 2; +ENTRY(_cplb_mgr) + + [--SP]=( R7:4,P5:3 ); + + CC = R0 == 2; + IF CC JUMP .Ldcplb_write; + + CC = R0 == 0; + IF !CC JUMP .Ldcplb_miss_compare; + + /* ICPLB Miss Exception. We need to choose one of the + * currently-installed CPLBs, and replace it with one + * from the configuration table. + */ + + /* A multi-word instruction can cross a page boundary. This means the + * first part of the instruction can be in a valid page, but the + * second part is not, and hence generates the instruction miss. + * However, the fault address is for the start of the instruction, + * not the part that's in the bad page. Therefore, we have to check + * whether the fault address applies to a page that is already present + * in the table. + */ + + P4.L = LO(ICPLB_FAULT_ADDR); + P4.H = HI(ICPLB_FAULT_ADDR); + + P1 = 16; + P5.L = _page_size_table; + P5.H = _page_size_table; + + P0.L = LO(ICPLB_DATA0); + P0.H = HI(ICPLB_DATA0); + R4 = [P4]; /* Get faulting address*/ + R6 = 64; /* Advance past the fault address, which*/ + R6 = R6 + R4; /* we'll use if we find a match*/ + R3 = ((16 << 8) | 2); /* Extract mask, two bits at posn 16 */ + + R5 = 0; +.Lisearch: + + R1 = [P0-0x100]; /* Address for this CPLB */ + + R0 = [P0++]; /* Info for this CPLB*/ + CC = BITTST(R0,0); /* Is the CPLB valid?*/ + IF !CC JUMP .Lnomatch; /* Skip it, if not.*/ + CC = R4 < R1(IU); /* If fault address less than page start*/ + IF CC JUMP .Lnomatch; /* then skip this one.*/ + R2 = EXTRACT(R0,R3.L) (Z); /* Get page size*/ + P1 = R2; + P1 = P5 + (P1<<2); /* index into page-size table*/ + R2 = [P1]; /* Get the page size*/ + R1 = R1 + R2; /* and add to page start, to get page end*/ + CC = R4 < R1(IU); /* and see whether fault addr is in page.*/ + IF !CC R4 = R6; /* If so, advance the address and finish loop.*/ + IF !CC JUMP .Lisearch_done; +.Lnomatch: + /* Go around again*/ + R5 += 1; + CC = BITTST(R5, 4); /* i.e CC = R5 >= 16*/ + IF !CC JUMP .Lisearch; + +.Lisearch_done: + I0 = R4; /* Fault address we'll search for*/ + + /* set up pointers */ + P0.L = LO(ICPLB_DATA0); + P0.H = HI(ICPLB_DATA0); + + /* The replacement procedure for ICPLBs */ + + P4.L = LO(IMEM_CONTROL); + P4.H = HI(IMEM_CONTROL); + + /* Turn off CPLBs while we work, necessary according to HRM before + * modifying CPLB descriptors + */ + R5 = [P4]; /* Control Register*/ + BITCLR(R5,ENICPLB_P); + CLI R1; + SSYNC; /* SSYNC required before writing to IMEM_CONTROL. */ + .align 8; + [P4] = R5; + SSYNC; + STI R1; + + R1 = -1; /* end point comparison */ + R3 = 16; /* counter */ + + /* Search through CPLBs for first non-locked entry */ + /* Overwrite it by moving everyone else up by 1 */ +.Licheck_lock: + R0 = [P0++]; + R3 = R3 + R1; + CC = R3 == R1; + IF CC JUMP .Lall_locked; + CC = BITTST(R0, 0); /* an invalid entry is good */ + IF !CC JUMP .Lifound_victim; + CC = BITTST(R0,1); /* but a locked entry isn't */ + IF CC JUMP .Licheck_lock; + +.Lifound_victim: +#ifdef CONFIG_CPLB_INFO + R7 = [P0 - 0x104]; + P2.L = _ipdt_table; + P2.H = _ipdt_table; + P3.L = _ipdt_swapcount_table; + P3.H = _ipdt_swapcount_table; + P3 += -4; +.Licount: + R2 = [P2]; /* address from config table */ + P2 += 8; + P3 += 8; + CC = R2==-1; + IF CC JUMP .Licount_done; + CC = R7==R2; + IF !CC JUMP .Licount; + R7 = [P3]; + R7 += 1; + [P3] = R7; + CSYNC; +.Licount_done: +#endif + LC0=R3; + LSETUP(.Lis_move,.Lie_move) LC0; +.Lis_move: + R0 = [P0]; + [P0 - 4] = R0; + R0 = [P0 - 0x100]; + [P0-0x104] = R0; +.Lie_move: + P0+=4; + + /* Clear ICPLB_DATA15, in case we don't find a replacement + * otherwise, we would have a duplicate entry, and will crash + */ + R0 = 0; + [P0 - 4] = R0; + + /* We've made space in the ICPLB table, so that ICPLB15 + * is now free to be overwritten. Next, we have to determine + * which CPLB we need to install, from the configuration + * table. This is a matter of getting the start-of-page + * addresses and page-lengths from the config table, and + * determining whether the fault address falls within that + * range. + */ + + P2.L = _ipdt_table; + P2.H = _ipdt_table; +#ifdef CONFIG_CPLB_INFO + P3.L = _ipdt_swapcount_table; + P3.H = _ipdt_swapcount_table; + P3 += -8; +#endif + P0.L = _page_size_table; + P0.H = _page_size_table; + + /* Retrieve our fault address (which may have been advanced + * because the faulting instruction crossed a page boundary). + */ + + R0 = I0; + + /* An extraction pattern, to get the page-size bits from + * the CPLB data entry. Bits 16-17, so two bits at posn 16. + */ + + R1 = ((16<<8)|2); +.Linext: R4 = [P2++]; /* address from config table */ + R2 = [P2++]; /* data from config table */ +#ifdef CONFIG_CPLB_INFO + P3 += 8; +#endif + + CC = R4 == -1; /* End of config table*/ + IF CC JUMP .Lno_page_in_table; + + /* See if failed address > start address */ + CC = R4 <= R0(IU); + IF !CC JUMP .Linext; + + /* extract page size (17:16)*/ + R3 = EXTRACT(R2, R1.L) (Z); + + /* add page size to addr to get range */ + + P5 = R3; + P5 = P0 + (P5 << 2); /* scaled, for int access*/ + R3 = [P5]; + R3 = R3 + R4; + + /* See if failed address < (start address + page size) */ + CC = R0 < R3(IU); + IF !CC JUMP .Linext; + + /* We've found a CPLB in the config table that covers + * the faulting address, so install this CPLB into the + * last entry of the table. + */ + + P1.L = LO(ICPLB_DATA15); /* ICPLB_DATA15 */ + P1.H = HI(ICPLB_DATA15); + [P1] = R2; + [P1-0x100] = R4; +#ifdef CONFIG_CPLB_INFO + R3 = [P3]; + R3 += 1; + [P3] = R3; +#endif + + /* P4 points to IMEM_CONTROL, and R5 contains its old + * value, after we disabled ICPLBS. Re-enable them. + */ + + BITSET(R5,ENICPLB_P); + CLI R2; + SSYNC; /* SSYNC required before writing to IMEM_CONTROL. */ + .align 8; + [P4] = R5; + SSYNC; + STI R2; + + ( R7:4,P5:3 ) = [SP++]; + R0 = CPLB_RELOADED; + RTS; + +/* FAILED CASES*/ +.Lno_page_in_table: + R0 = CPLB_NO_ADDR_MATCH; + JUMP .Lfail_ret; + +.Lall_locked: + R0 = CPLB_NO_UNLOCKED; + JUMP .Lfail_ret; + +.Lprot_violation: + R0 = CPLB_PROT_VIOL; + +.Lfail_ret: + /* Make sure we turn protection/cache back on, even in the failing case */ + BITSET(R5,ENICPLB_P); + CLI R2; + SSYNC; /* SSYNC required before writing to IMEM_CONTROL. */ + .align 8; + [P4] = R5; + SSYNC; + STI R2; + + ( R7:4,P5:3 ) = [SP++]; + RTS; + +.Ldcplb_write: + + /* if a DCPLB is marked as write-back (CPLB_WT==0), and + * it is clean (CPLB_DIRTY==0), then a write to the + * CPLB's page triggers a protection violation. We have to + * mark the CPLB as dirty, to indicate that there are + * pending writes associated with the CPLB. + */ + + P4.L = LO(DCPLB_STATUS); + P4.H = HI(DCPLB_STATUS); + P3.L = LO(DCPLB_DATA0); + P3.H = HI(DCPLB_DATA0); + R5 = [P4]; + + /* A protection violation can be caused by more than just writes + * to a clean WB page, so we have to ensure that: + * - It's a write + * - to a clean WB page + * - and is allowed in the mode the access occurred. + */ + + CC = BITTST(R5, 16); /* ensure it was a write*/ + IF !CC JUMP .Lprot_violation; + + /* to check the rest, we have to retrieve the DCPLB.*/ + + /* The low half of DCPLB_STATUS is a bit mask*/ + + R2 = R5.L (Z); /* indicating which CPLB triggered the event.*/ + R3 = 30; /* so we can use this to determine the offset*/ + R2.L = SIGNBITS R2; + R2 = R2.L (Z); /* into the DCPLB table.*/ + R3 = R3 - R2; + P4 = R3; + P3 = P3 + (P4<<2); + R3 = [P3]; /* Retrieve the CPLB*/ + + /* Now we can check whether it's a clean WB page*/ + + CC = BITTST(R3, 14); /* 0==WB, 1==WT*/ + IF CC JUMP .Lprot_violation; + CC = BITTST(R3, 7); /* 0 == clean, 1 == dirty*/ + IF CC JUMP .Lprot_violation; + + /* Check whether the write is allowed in the mode that was active.*/ + + R2 = 1<<3; /* checking write in user mode*/ + CC = BITTST(R5, 17); /* 0==was user, 1==was super*/ + R5 = CC; + R2 <<= R5; /* if was super, check write in super mode*/ + R2 = R3 & R2; + CC = R2 == 0; + IF CC JUMP .Lprot_violation; + + /* It's a genuine write-to-clean-page.*/ + + BITSET(R3, 7); /* mark as dirty*/ + [P3] = R3; /* and write back.*/ + NOP; + CSYNC; + ( R7:4,P5:3 ) = [SP++]; + R0 = CPLB_RELOADED; + RTS; + +.Ldcplb_miss_compare: + + /* Data CPLB Miss event. We need to choose a CPLB to + * evict, and then locate a new CPLB to install from the + * config table, that covers the faulting address. + */ + + P1.L = LO(DCPLB_DATA15); + P1.H = HI(DCPLB_DATA15); + + P4.L = LO(DCPLB_FAULT_ADDR); + P4.H = HI(DCPLB_FAULT_ADDR); + R4 = [P4]; + I0 = R4; + + /* The replacement procedure for DCPLBs*/ + + R6 = R1; /* Save for later*/ + + /* Turn off CPLBs while we work.*/ + P4.L = LO(DMEM_CONTROL); + P4.H = HI(DMEM_CONTROL); + R5 = [P4]; + BITCLR(R5,ENDCPLB_P); + CLI R0; + SSYNC; /* SSYNC required before writing to DMEM_CONTROL. */ + .align 8; + [P4] = R5; + SSYNC; + STI R0; + + /* Start looking for a CPLB to evict. Our order of preference + * is: invalid CPLBs, clean CPLBs, dirty CPLBs. Locked CPLBs + * are no good. + */ + + I1.L = LO(DCPLB_DATA0); + I1.H = HI(DCPLB_DATA0); + P1 = 2; + P2 = 16; + I2.L = _dcplb_preference; + I2.H = _dcplb_preference; + LSETUP(.Lsdsearch1, .Ledsearch1) LC0 = P1; +.Lsdsearch1: + R0 = [I2++]; /* Get the bits we're interested in*/ + P0 = I1; /* Go back to start of table*/ + LSETUP (.Lsdsearch2, .Ledsearch2) LC1 = P2; +.Lsdsearch2: + R1 = [P0++]; /* Fetch each installed CPLB in turn*/ + R2 = R1 & R0; /* and test for interesting bits.*/ + CC = R2 == 0; /* If none are set, it'll do.*/ + IF !CC JUMP .Lskip_stack_check; + + R2 = [P0 - 0x104]; /* R2 - PageStart */ + P3.L = _page_size_table; /* retrieve end address */ + P3.H = _page_size_table; /* retrieve end address */ + R3 = 0x1002; /* 16th - position, 2 bits -length */ +#if ANOMALY_05000209 + nop; /* Anomaly 05000209 */ +#endif + R7 = EXTRACT(R1,R3.l); + R7 = R7 << 2; /* Page size index offset */ + P5 = R7; + P3 = P3 + P5; + R7 = [P3]; /* page size in bytes */ + + R7 = R2 + R7; /* R7 - PageEnd */ + R4 = SP; /* Test SP is in range */ + + CC = R7 < R4; /* if PageEnd < SP */ + IF CC JUMP .Ldfound_victim; + R3 = 0x284; /* stack length from start of trap till + * the point. + * 20 stack locations for future modifications + */ + R4 = R4 + R3; + CC = R4 < R2; /* if SP + stacklen < PageStart */ + IF CC JUMP .Ldfound_victim; +.Lskip_stack_check: + +.Ledsearch2: NOP; +.Ledsearch1: NOP; + + /* If we got here, we didn't find a DCPLB we considered + * replacable, which means all of them were locked. + */ + + JUMP .Lall_locked; +.Ldfound_victim: + +#ifdef CONFIG_CPLB_INFO + R7 = [P0 - 0x104]; + P2.L = _dpdt_table; + P2.H = _dpdt_table; + P3.L = _dpdt_swapcount_table; + P3.H = _dpdt_swapcount_table; + P3 += -4; +.Ldicount: + R2 = [P2]; + P2 += 8; + P3 += 8; + CC = R2==-1; + IF CC JUMP .Ldicount_done; + CC = R7==R2; + IF !CC JUMP .Ldicount; + R7 = [P3]; + R7 += 1; + [P3] = R7; +.Ldicount_done: +#endif + + /* Clean down the hardware loops*/ + R2 = 0; + LC1 = R2; + LC0 = R2; + + /* There's a suitable victim in [P0-4] (because we've + * advanced already). + */ + +.LDdoverwrite: + + /* [P0-4] is a suitable victim CPLB, so we want to + * overwrite it by moving all the following CPLBs + * one space closer to the start. + */ + + R1.L = LO(DCPLB_DATA16); /* DCPLB_DATA15 + 4 */ + R1.H = HI(DCPLB_DATA16); + R0 = P0; + + /* If the victim happens to be in DCPLB15, + * we don't need to move anything. + */ + + CC = R1 == R0; + IF CC JUMP .Lde_moved; + R1 = R1 - R0; + R1 >>= 2; + P1 = R1; + LSETUP(.Lds_move, .Lde_move) LC0=P1; +.Lds_move: + R0 = [P0++]; /* move data */ + [P0 - 8] = R0; + R0 = [P0-0x104] /* move address */ +.Lde_move: + [P0-0x108] = R0; + +.Lde_moved: + NOP; + + /* Clear DCPLB_DATA15, in case we don't find a replacement + * otherwise, we would have a duplicate entry, and will crash + */ + R0 = 0; + [P0 - 0x4] = R0; + + /* We've now made space in DCPLB15 for the new CPLB to be + * installed. The next stage is to locate a CPLB in the + * config table that covers the faulting address. + */ + + R0 = I0; /* Our faulting address */ + + P2.L = _dpdt_table; + P2.H = _dpdt_table; +#ifdef CONFIG_CPLB_INFO + P3.L = _dpdt_swapcount_table; + P3.H = _dpdt_swapcount_table; + P3 += -8; +#endif + + P1.L = _page_size_table; + P1.H = _page_size_table; + + /* An extraction pattern, to retrieve bits 17:16.*/ + + R1 = (16<<8)|2; +.Ldnext: R4 = [P2++]; /* address */ + R2 = [P2++]; /* data */ +#ifdef CONFIG_CPLB_INFO + P3 += 8; +#endif + + CC = R4 == -1; + IF CC JUMP .Lno_page_in_table; + + /* See if failed address > start address */ + CC = R4 <= R0(IU); + IF !CC JUMP .Ldnext; + + /* extract page size (17:16)*/ + R3 = EXTRACT(R2, R1.L) (Z); + + /* add page size to addr to get range */ + + P5 = R3; + P5 = P1 + (P5 << 2); + R3 = [P5]; + R3 = R3 + R4; + + /* See if failed address < (start address + page size) */ + CC = R0 < R3(IU); + IF !CC JUMP .Ldnext; + + /* We've found the CPLB that should be installed, so + * write it into CPLB15, masking off any caching bits + * if necessary. + */ + + P1.L = LO(DCPLB_DATA15); + P1.H = HI(DCPLB_DATA15); + + /* If the DCPLB has cache bits set, but caching hasn't + * been enabled, then we want to mask off the cache-in-L1 + * bit before installing. Moreover, if caching is off, we + * also want to ensure that the DCPLB has WT mode set, rather + * than WB, since WB pages still trigger first-write exceptions + * even when not caching is off, and the page isn't marked as + * cachable. Finally, we could mark the page as clean, not dirty, + * but we choose to leave that decision to the user; if the user + * chooses to have a CPLB pre-defined as dirty, then they always + * pay the cost of flushing during eviction, but don't pay the + * cost of first-write exceptions to mark the page as dirty. + */ + +#ifdef CONFIG_BFIN_WT + BITSET(R6, 14); /* Set WT*/ +#endif + + [P1] = R2; + [P1-0x100] = R4; +#ifdef CONFIG_CPLB_INFO + R3 = [P3]; + R3 += 1; + [P3] = R3; +#endif + + /* We've installed the CPLB, so re-enable CPLBs. P4 + * points to DMEM_CONTROL, and R5 is the value we + * last wrote to it, when we were disabling CPLBs. + */ + + BITSET(R5,ENDCPLB_P); + CLI R2; + .align 8; + [P4] = R5; + SSYNC; + STI R2; + + ( R7:4,P5:3 ) = [SP++]; + R0 = CPLB_RELOADED; + RTS; +ENDPROC(_cplb_mgr) + +.data +.align 4; +_page_size_table: +.byte4 0x00000400; /* 1K */ +.byte4 0x00001000; /* 4K */ +.byte4 0x00100000; /* 1M */ +.byte4 0x00400000; /* 4M */ + +.align 4; +_dcplb_preference: +.byte4 0x00000001; /* valid bit */ +.byte4 0x00000002; /* lock bit */ diff --git a/arch/blackfin/kernel/cplbinit.c b/arch/blackfin/kernel/cplbinit.c deleted file mode 100644 index 6320bc4..0000000 --- a/arch/blackfin/kernel/cplbinit.c +++ /dev/null @@ -1,437 +0,0 @@ -/* - * Blackfin CPLB initialization - * - * Copyright 2004-2007 Analog Devices Inc. - * - * Bugs: Enter bugs at http://blackfin.uclinux.org/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, see the file COPYING, or write - * to the Free Software Foundation, Inc., - * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ -#include - -#include -#include -#include - -u_long icplb_table[MAX_CPLBS + 1]; -u_long dcplb_table[MAX_CPLBS + 1]; - -#ifdef CONFIG_CPLB_SWITCH_TAB_L1 -# define PDT_ATTR __attribute__((l1_data)) -#else -# define PDT_ATTR -#endif - -u_long ipdt_table[MAX_SWITCH_I_CPLBS + 1] PDT_ATTR; -u_long dpdt_table[MAX_SWITCH_D_CPLBS + 1] PDT_ATTR; - -#ifdef CONFIG_CPLB_INFO -u_long ipdt_swapcount_table[MAX_SWITCH_I_CPLBS] PDT_ATTR; -u_long dpdt_swapcount_table[MAX_SWITCH_D_CPLBS] PDT_ATTR; -#endif - -struct s_cplb { - struct cplb_tab init_i; - struct cplb_tab init_d; - struct cplb_tab switch_i; - struct cplb_tab switch_d; -}; - -#if defined(CONFIG_BFIN_DCACHE) || defined(CONFIG_BFIN_ICACHE) -static struct cplb_desc cplb_data[] = { - { - .start = 0, - .end = SIZE_1K, - .psize = SIZE_1K, - .attr = INITIAL_T | SWITCH_T | I_CPLB | D_CPLB, - .i_conf = SDRAM_OOPS, - .d_conf = SDRAM_OOPS, -#if defined(CONFIG_DEBUG_HUNT_FOR_ZERO) - .valid = 1, -#else - .valid = 0, -#endif - .name = "Zero Pointer Guard Page", - }, - { - .start = L1_CODE_START, - .end = L1_CODE_START + L1_CODE_LENGTH, - .psize = SIZE_4M, - .attr = INITIAL_T | SWITCH_T | I_CPLB, - .i_conf = L1_IMEMORY, - .d_conf = 0, - .valid = 1, - .name = "L1 I-Memory", - }, - { - .start = L1_DATA_A_START, - .end = L1_DATA_B_START + L1_DATA_B_LENGTH, - .psize = SIZE_4M, - .attr = INITIAL_T | SWITCH_T | D_CPLB, - .i_conf = 0, - .d_conf = L1_DMEMORY, -#if ((L1_DATA_A_LENGTH > 0) || (L1_DATA_B_LENGTH > 0)) - .valid = 1, -#else - .valid = 0, -#endif - .name = "L1 D-Memory", - }, - { - .start = 0, - .end = 0, /* dynamic */ - .psize = 0, - .attr = INITIAL_T | SWITCH_T | I_CPLB | D_CPLB, - .i_conf = SDRAM_IGENERIC, - .d_conf = SDRAM_DGENERIC, - .valid = 1, - .name = "Kernel Memory", - }, - { - .start = 0, /* dynamic */ - .end = 0, /* dynamic */ - .psize = 0, - .attr = INITIAL_T | SWITCH_T | D_CPLB, - .i_conf = SDRAM_IGENERIC, - .d_conf = SDRAM_DNON_CHBL, - .valid = 1, - .name = "uClinux MTD Memory", - }, - { - .start = 0, /* dynamic */ - .end = 0, /* dynamic */ - .psize = SIZE_1M, - .attr = INITIAL_T | SWITCH_T | D_CPLB, - .d_conf = SDRAM_DNON_CHBL, - .valid = 1, - .name = "Uncached DMA Zone", - }, - { - .start = 0, /* dynamic */ - .end = 0, /* dynamic */ - .psize = 0, - .attr = SWITCH_T | D_CPLB, - .i_conf = 0, /* dynamic */ - .d_conf = 0, /* dynamic */ - .valid = 1, - .name = "Reserved Memory", - }, - { - .start = ASYNC_BANK0_BASE, - .end = ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE, - .psize = 0, - .attr = SWITCH_T | D_CPLB, - .d_conf = SDRAM_EBIU, - .valid = 1, - .name = "Asynchronous Memory Banks", - }, - { -#ifdef L2_START - .start = L2_START, - .end = L2_START + L2_LENGTH, - .psize = SIZE_1M, - .attr = SWITCH_T | I_CPLB | D_CPLB, - .i_conf = L2_MEMORY, - .d_conf = L2_MEMORY, - .valid = 1, -#else - .valid = 0, -#endif - .name = "L2 Memory", - }, - { - .start = BOOT_ROM_START, - .end = BOOT_ROM_START + BOOT_ROM_LENGTH, - .psize = SIZE_1M, - .attr = SWITCH_T | I_CPLB | D_CPLB, - .i_conf = SDRAM_IGENERIC, - .d_conf = SDRAM_DGENERIC, - .valid = 1, - .name = "On-Chip BootROM", - }, -}; - -static u16 __init lock_kernel_check(u32 start, u32 end) -{ - if ((end <= (u32) _end && end >= (u32)_stext) || - (start <= (u32) _end && start >= (u32)_stext)) - return IN_KERNEL; - return 0; -} - -static unsigned short __init -fill_cplbtab(struct cplb_tab *table, - unsigned long start, unsigned long end, - unsigned long block_size, unsigned long cplb_data) -{ - int i; - - switch (block_size) { - case SIZE_4M: - i = 3; - break; - case SIZE_1M: - i = 2; - break; - case SIZE_4K: - i = 1; - break; - case SIZE_1K: - default: - i = 0; - break; - } - - cplb_data = (cplb_data & ~(3 << 16)) | (i << 16); - - while ((start < end) && (table->pos < table->size)) { - - table->tab[table->pos++] = start; - - if (lock_kernel_check(start, start + block_size) == IN_KERNEL) - table->tab[table->pos++] = - cplb_data | CPLB_LOCK | CPLB_DIRTY; - else - table->tab[table->pos++] = cplb_data; - - start += block_size; - } - return 0; -} - -static unsigned short __init -close_cplbtab(struct cplb_tab *table) -{ - - while (table->pos < table->size) { - - table->tab[table->pos++] = 0; - table->tab[table->pos++] = 0; /* !CPLB_VALID */ - } - return 0; -} - -/* helper function */ -static void __fill_code_cplbtab(struct cplb_tab *t, int i, u32 a_start, u32 a_end) -{ - if (cplb_data[i].psize) { - fill_cplbtab(t, - cplb_data[i].start, - cplb_data[i].end, - cplb_data[i].psize, - cplb_data[i].i_conf); - } else { -#if defined(CONFIG_BFIN_ICACHE) - if (ANOMALY_05000263 && i == SDRAM_KERN) { - fill_cplbtab(t, - cplb_data[i].start, - cplb_data[i].end, - SIZE_4M, - cplb_data[i].i_conf); - } else -#endif - { - fill_cplbtab(t, - cplb_data[i].start, - a_start, - SIZE_1M, - cplb_data[i].i_conf); - fill_cplbtab(t, - a_start, - a_end, - SIZE_4M, - cplb_data[i].i_conf); - fill_cplbtab(t, a_end, - cplb_data[i].end, - SIZE_1M, - cplb_data[i].i_conf); - } - } -} - -static void __fill_data_cplbtab(struct cplb_tab *t, int i, u32 a_start, u32 a_end) -{ - if (cplb_data[i].psize) { - fill_cplbtab(t, - cplb_data[i].start, - cplb_data[i].end, - cplb_data[i].psize, - cplb_data[i].d_conf); - } else { - fill_cplbtab(t, - cplb_data[i].start, - a_start, SIZE_1M, - cplb_data[i].d_conf); - fill_cplbtab(t, a_start, - a_end, SIZE_4M, - cplb_data[i].d_conf); - fill_cplbtab(t, a_end, - cplb_data[i].end, - SIZE_1M, - cplb_data[i].d_conf); - } -} - -void __init generate_cpl_tables(void) -{ - - u16 i, j, process; - u32 a_start, a_end, as, ae, as_1m; - - struct cplb_tab *t_i = NULL; - struct cplb_tab *t_d = NULL; - struct s_cplb cplb; - - cplb.init_i.size = MAX_CPLBS; - cplb.init_d.size = MAX_CPLBS; - cplb.switch_i.size = MAX_SWITCH_I_CPLBS; - cplb.switch_d.size = MAX_SWITCH_D_CPLBS; - - cplb.init_i.pos = 0; - cplb.init_d.pos = 0; - cplb.switch_i.pos = 0; - cplb.switch_d.pos = 0; - - cplb.init_i.tab = icplb_table; - cplb.init_d.tab = dcplb_table; - cplb.switch_i.tab = ipdt_table; - cplb.switch_d.tab = dpdt_table; - - cplb_data[SDRAM_KERN].end = memory_end; - -#ifdef CONFIG_MTD_UCLINUX - cplb_data[SDRAM_RAM_MTD].start = memory_mtd_start; - cplb_data[SDRAM_RAM_MTD].end = memory_mtd_start + mtd_size; - cplb_data[SDRAM_RAM_MTD].valid = mtd_size > 0; -# if defined(CONFIG_ROMFS_FS) - cplb_data[SDRAM_RAM_MTD].attr |= I_CPLB; - - /* - * The ROMFS_FS size is often not multiple of 1MB. - * This can cause multiple CPLB sets covering the same memory area. - * This will then cause multiple CPLB hit exceptions. - * Workaround: We ensure a contiguous memory area by extending the kernel - * memory section over the mtd section. - * For ROMFS_FS memory must be covered with ICPLBs anyways. - * So there is no difference between kernel and mtd memory setup. - */ - - cplb_data[SDRAM_KERN].end = memory_mtd_start + mtd_size;; - cplb_data[SDRAM_RAM_MTD].valid = 0; - -# endif -#else - cplb_data[SDRAM_RAM_MTD].valid = 0; -#endif - - cplb_data[SDRAM_DMAZ].start = _ramend - DMA_UNCACHED_REGION; - cplb_data[SDRAM_DMAZ].end = _ramend; - - cplb_data[RES_MEM].start = _ramend; - cplb_data[RES_MEM].end = physical_mem_end; - - if (reserved_mem_dcache_on) - cplb_data[RES_MEM].d_conf = SDRAM_DGENERIC; - else - cplb_data[RES_MEM].d_conf = SDRAM_DNON_CHBL; - - if (reserved_mem_icache_on) - cplb_data[RES_MEM].i_conf = SDRAM_IGENERIC; - else - cplb_data[RES_MEM].i_conf = SDRAM_INON_CHBL; - - for (i = ZERO_P; i < ARRAY_SIZE(cplb_data); ++i) { - if (!cplb_data[i].valid) - continue; - - as_1m = cplb_data[i].start % SIZE_1M; - - /* We need to make sure all sections are properly 1M aligned - * However between Kernel Memory and the Kernel mtd section, depending on the - * rootfs size, there can be overlapping memory areas. - */ - - if (as_1m && i != L1I_MEM && i != L1D_MEM) { -#ifdef CONFIG_MTD_UCLINUX - if (i == SDRAM_RAM_MTD) { - if ((cplb_data[SDRAM_KERN].end + 1) > cplb_data[SDRAM_RAM_MTD].start) - cplb_data[SDRAM_RAM_MTD].start = (cplb_data[i].start & (-2*SIZE_1M)) + SIZE_1M; - else - cplb_data[SDRAM_RAM_MTD].start = (cplb_data[i].start & (-2*SIZE_1M)); - } else -#endif - printk(KERN_WARNING "Unaligned Start of %s at 0x%X\n", - cplb_data[i].name, cplb_data[i].start); - } - - as = cplb_data[i].start % SIZE_4M; - ae = cplb_data[i].end % SIZE_4M; - - if (as) - a_start = cplb_data[i].start + (SIZE_4M - (as)); - else - a_start = cplb_data[i].start; - - a_end = cplb_data[i].end - ae; - - for (j = INITIAL_T; j <= SWITCH_T; j++) { - - switch (j) { - case INITIAL_T: - if (cplb_data[i].attr & INITIAL_T) { - t_i = &cplb.init_i; - t_d = &cplb.init_d; - process = 1; - } else - process = 0; - break; - case SWITCH_T: - if (cplb_data[i].attr & SWITCH_T) { - t_i = &cplb.switch_i; - t_d = &cplb.switch_d; - process = 1; - } else - process = 0; - break; - default: - process = 0; - break; - } - - if (!process) - continue; - if (cplb_data[i].attr & I_CPLB) - __fill_code_cplbtab(t_i, i, a_start, a_end); - - if (cplb_data[i].attr & D_CPLB) - __fill_data_cplbtab(t_d, i, a_start, a_end); - } - } - -/* close tables */ - - close_cplbtab(&cplb.init_i); - close_cplbtab(&cplb.init_d); - - cplb.init_i.tab[cplb.init_i.pos] = -1; - cplb.init_d.tab[cplb.init_d.pos] = -1; - cplb.switch_i.tab[cplb.switch_i.pos] = -1; - cplb.switch_d.tab[cplb.switch_d.pos] = -1; - -} - -#endif - diff --git a/arch/blackfin/mach-common/Makefile b/arch/blackfin/mach-common/Makefile index 4d7733d..8636d42 100644 --- a/arch/blackfin/mach-common/Makefile +++ b/arch/blackfin/mach-common/Makefile @@ -3,10 +3,9 @@ # obj-y := \ - cache.o cacheinit.o cplbhdlr.o cplbmgr.o entry.o \ + cache.o cacheinit.o entry.o \ interrupt.o lock.o irqpanic.o arch_checks.o -obj-$(CONFIG_CPLB_INFO) += cplbinfo.o obj-$(CONFIG_BFIN_SINGLE_CORE) += ints-priority-sc.o obj-$(CONFIG_BFIN_DUAL_CORE) += ints-priority-dc.o obj-$(CONFIG_PM) += pm.o dpmc.o diff --git a/arch/blackfin/mach-common/cplbhdlr.S b/arch/blackfin/mach-common/cplbhdlr.S deleted file mode 100644 index 2788532..0000000 --- a/arch/blackfin/mach-common/cplbhdlr.S +++ /dev/null @@ -1,130 +0,0 @@ -/* - * File: arch/blackfin/mach-common/cplbhdlr.S - * Based on: - * Author: LG Soft India - * - * Created: ? - * Description: CPLB exception handler - * - * Modified: - * Copyright 2004-2006 Analog Devices Inc. - * - * Bugs: Enter bugs at http://blackfin.uclinux.org/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, see the file COPYING, or write - * to the Free Software Foundation, Inc., - * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include -#include - -#ifdef CONFIG_EXCPT_IRQ_SYSC_L1 -.section .l1.text -#else -.text -#endif - -.type _cplb_mgr, STT_FUNC; -.type _panic_cplb_error, STT_FUNC; - -.align 2 - -ENTRY(__cplb_hdr) - R2 = SEQSTAT; - - /* Mask the contents of SEQSTAT and leave only EXCAUSE in R2 */ - R2 <<= 26; - R2 >>= 26; - - R1 = 0x23; /* Data access CPLB protection violation */ - CC = R2 == R1; - IF !CC JUMP .Lnot_data_write; - R0 = 2; /* is a write to data space*/ - JUMP .Lis_icplb_miss; - -.Lnot_data_write: - R1 = 0x2C; /* CPLB miss on an instruction fetch */ - CC = R2 == R1; - R0 = 0; /* is_data_miss == False*/ - IF CC JUMP .Lis_icplb_miss; - - R1 = 0x26; - CC = R2 == R1; - IF !CC JUMP .Lunknown; - - R0 = 1; /* is_data_miss == True*/ - -.Lis_icplb_miss: - -#if defined(CONFIG_BFIN_ICACHE) || defined(CONFIG_BFIN_DCACHE) -# if defined(CONFIG_BFIN_ICACHE) && !defined(CONFIG_BFIN_DCACHE) - R1 = CPLB_ENABLE_ICACHE; -# endif -# if !defined(CONFIG_BFIN_ICACHE) && defined(CONFIG_BFIN_DCACHE) - R1 = CPLB_ENABLE_DCACHE; -# endif -# if defined(CONFIG_BFIN_ICACHE) && defined(CONFIG_BFIN_DCACHE) - R1 = CPLB_ENABLE_DCACHE | CPLB_ENABLE_ICACHE; -# endif -#else - R1 = 0; -#endif - - [--SP] = RETS; - CALL _cplb_mgr; - RETS = [SP++]; - CC = R0 == 0; - IF !CC JUMP .Lnot_replaced; - RTS; - -/* - * Diagnostic exception handlers - */ -.Lunknown: - R0 = CPLB_UNKNOWN_ERR; - JUMP .Lcplb_error; - -.Lnot_replaced: - CC = R0 == CPLB_NO_UNLOCKED; - IF !CC JUMP .Lnext_check; - R0 = CPLB_NO_UNLOCKED; - JUMP .Lcplb_error; - -.Lnext_check: - CC = R0 == CPLB_NO_ADDR_MATCH; - IF !CC JUMP .Lnext_check2; - R0 = CPLB_NO_ADDR_MATCH; - JUMP .Lcplb_error; - -.Lnext_check2: - CC = R0 == CPLB_PROT_VIOL; - IF !CC JUMP .Lstrange_return_from_cplb_mgr; - R0 = CPLB_PROT_VIOL; - JUMP .Lcplb_error; - -.Lstrange_return_from_cplb_mgr: - IDLE; - CSYNC; - JUMP .Lstrange_return_from_cplb_mgr; - -.Lcplb_error: - R1 = sp; - SP += -12; - call _panic_cplb_error; - SP += 12; - JUMP _handle_bad_cplb; - -ENDPROC(__cplb_hdr) diff --git a/arch/blackfin/mach-common/cplbinfo.c b/arch/blackfin/mach-common/cplbinfo.c deleted file mode 100644 index a4f0b42..0000000 --- a/arch/blackfin/mach-common/cplbinfo.c +++ /dev/null @@ -1,208 +0,0 @@ -/* - * File: arch/blackfin/mach-common/cplbinfo.c - * Based on: - * Author: Sonic Zhang - * - * Created: Jan. 2005 - * Description: Display CPLB status - * - * Modified: - * Copyright 2004-2006 Analog Devices Inc. - * - * Bugs: Enter bugs at http://blackfin.uclinux.org/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, see the file COPYING, or write - * to the Free Software Foundation, Inc., - * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#define CPLB_I 1 -#define CPLB_D 2 - -#define SYNC_SYS SSYNC() -#define SYNC_CORE CSYNC() - -#define CPLB_BIT_PAGESIZE 0x30000 - -static int page_size_table[4] = { - 0x00000400, /* 1K */ - 0x00001000, /* 4K */ - 0x00100000, /* 1M */ - 0x00400000 /* 4M */ -}; - -static char page_size_string_table[][4] = { "1K", "4K", "1M", "4M" }; - -static int cplb_find_entry(unsigned long *cplb_addr, - unsigned long *cplb_data, unsigned long addr, - unsigned long data) -{ - int ii; - - for (ii = 0; ii < 16; ii++) - if (addr >= cplb_addr[ii] && addr < cplb_addr[ii] + - page_size_table[(cplb_data[ii] & CPLB_BIT_PAGESIZE) >> 16] - && (cplb_data[ii] == data)) - return ii; - - return -1; -} - -static char *cplb_print_entry(char *buf, int type) -{ - unsigned long *p_addr = dpdt_table; - unsigned long *p_data = dpdt_table + 1; - unsigned long *p_icount = dpdt_swapcount_table; - unsigned long *p_ocount = dpdt_swapcount_table + 1; - unsigned long *cplb_addr = (unsigned long *)DCPLB_ADDR0; - unsigned long *cplb_data = (unsigned long *)DCPLB_DATA0; - int entry = 0, used_cplb = 0; - - if (type == CPLB_I) { - buf += sprintf(buf, "Instruction CPLB entry:\n"); - p_addr = ipdt_table; - p_data = ipdt_table + 1; - p_icount = ipdt_swapcount_table; - p_ocount = ipdt_swapcount_table + 1; - cplb_addr = (unsigned long *)ICPLB_ADDR0; - cplb_data = (unsigned long *)ICPLB_DATA0; - } else - buf += sprintf(buf, "Data CPLB entry:\n"); - - buf += sprintf(buf, "Address\t\tData\tSize\tValid\tLocked\tSwapin\tiCount\toCount\n"); - - while (*p_addr != 0xffffffff) { - entry = cplb_find_entry(cplb_addr, cplb_data, *p_addr, *p_data); - if (entry >= 0) - used_cplb |= 1 << entry; - - buf += - sprintf(buf, - "0x%08lx\t0x%05lx\t%s\t%c\t%c\t%2d\t%ld\t%ld\n", - *p_addr, *p_data, - page_size_string_table[(*p_data & 0x30000) >> 16], - (*p_data & CPLB_VALID) ? 'Y' : 'N', - (*p_data & CPLB_LOCK) ? 'Y' : 'N', entry, *p_icount, - *p_ocount); - - p_addr += 2; - p_data += 2; - p_icount += 2; - p_ocount += 2; - } - - if (used_cplb != 0xffff) { - buf += sprintf(buf, "Unused/mismatched CPLBs:\n"); - - for (entry = 0; entry < 16; entry++) - if (0 == ((1 << entry) & used_cplb)) { - int flags = cplb_data[entry]; - buf += - sprintf(buf, - "%2d: 0x%08lx\t0x%05x\t%s\t%c\t%c\n", - entry, cplb_addr[entry], flags, - page_size_string_table[(flags & - 0x30000) >> - 16], - (flags & CPLB_VALID) ? 'Y' : 'N', - (flags & CPLB_LOCK) ? 'Y' : 'N'); - } - } - - buf += sprintf(buf, "\n"); - - return buf; -} - -static int cplbinfo_proc_output(char *buf) -{ - char *p; - - p = buf; - - p += sprintf(p, "------------------ CPLB Information ------------------\n\n"); - - if (bfin_read_IMEM_CONTROL() & ENICPLB) - p = cplb_print_entry(p, CPLB_I); - else - p += sprintf(p, "Instruction CPLB is disabled.\n\n"); - - if (bfin_read_DMEM_CONTROL() & ENDCPLB) - p = cplb_print_entry(p, CPLB_D); - else - p += sprintf(p, "Data CPLB is disabled.\n"); - - return p - buf; -} - -static int cplbinfo_read_proc(char *page, char **start, off_t off, - int count, int *eof, void *data) -{ - int len; - - len = cplbinfo_proc_output(page); - if (len <= off + count) - *eof = 1; - *start = page + off; - len -= off; - if (len > count) - len = count; - if (len < 0) - len = 0; - return len; -} - -static int cplbinfo_write_proc(struct file *file, const char __user *buffer, - unsigned long count, void *data) -{ - printk(KERN_INFO "Reset the CPLB swap in/out counts.\n"); - memset(ipdt_swapcount_table, 0, MAX_SWITCH_I_CPLBS * sizeof(unsigned long)); - memset(dpdt_swapcount_table, 0, MAX_SWITCH_D_CPLBS * sizeof(unsigned long)); - - return count; -} - -static int __init cplbinfo_init(void) -{ - struct proc_dir_entry *entry; - - entry = create_proc_entry("cplbinfo", 0, NULL); - if (!entry) - return -ENOMEM; - - entry->read_proc = cplbinfo_read_proc; - entry->write_proc = cplbinfo_write_proc; - entry->data = NULL; - - return 0; -} - -static void __exit cplbinfo_exit(void) -{ - remove_proc_entry("cplbinfo", NULL); -} - -module_init(cplbinfo_init); -module_exit(cplbinfo_exit); diff --git a/arch/blackfin/mach-common/cplbmgr.S b/arch/blackfin/mach-common/cplbmgr.S deleted file mode 100644 index f5cf3ac..0000000 --- a/arch/blackfin/mach-common/cplbmgr.S +++ /dev/null @@ -1,646 +0,0 @@ -/* - * File: arch/blackfin/mach-common/cplbmgtr.S - * Based on: - * Author: LG Soft India - * - * Created: ? - * Description: CPLB replacement routine for CPLB mismatch - * - * Modified: - * Copyright 2004-2006 Analog Devices Inc. - * - * Bugs: Enter bugs at http://blackfin.uclinux.org/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, see the file COPYING, or write - * to the Free Software Foundation, Inc., - * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* Usage: int _cplb_mgr(is_data_miss,int enable_cache) - * is_data_miss==2 => Mark as Dirty, write to the clean data page - * is_data_miss==1 => Replace a data CPLB. - * is_data_miss==0 => Replace an instruction CPLB. - * - * Returns: - * CPLB_RELOADED => Successfully updated CPLB table. - * CPLB_NO_UNLOCKED => All CPLBs are locked, so cannot be evicted. - * This indicates that the CPLBs in the configuration - * tablei are badly configured, as this should never - * occur. - * CPLB_NO_ADDR_MATCH => The address being accessed, that triggered the - * exception, is not covered by any of the CPLBs in - * the configuration table. The application is - * presumably misbehaving. - * CPLB_PROT_VIOL => The address being accessed, that triggered the - * exception, was not a first-write to a clean Write - * Back Data page, and so presumably is a genuine - * violation of the page's protection attributes. - * The application is misbehaving. - */ - -#include -#include -#include - -#ifdef CONFIG_EXCPT_IRQ_SYSC_L1 -.section .l1.text -#else -.text -#endif - -.align 2; -ENTRY(_cplb_mgr) - - [--SP]=( R7:4,P5:3 ); - - CC = R0 == 2; - IF CC JUMP .Ldcplb_write; - - CC = R0 == 0; - IF !CC JUMP .Ldcplb_miss_compare; - - /* ICPLB Miss Exception. We need to choose one of the - * currently-installed CPLBs, and replace it with one - * from the configuration table. - */ - - /* A multi-word instruction can cross a page boundary. This means the - * first part of the instruction can be in a valid page, but the - * second part is not, and hence generates the instruction miss. - * However, the fault address is for the start of the instruction, - * not the part that's in the bad page. Therefore, we have to check - * whether the fault address applies to a page that is already present - * in the table. - */ - - P4.L = LO(ICPLB_FAULT_ADDR); - P4.H = HI(ICPLB_FAULT_ADDR); - - P1 = 16; - P5.L = _page_size_table; - P5.H = _page_size_table; - - P0.L = LO(ICPLB_DATA0); - P0.H = HI(ICPLB_DATA0); - R4 = [P4]; /* Get faulting address*/ - R6 = 64; /* Advance past the fault address, which*/ - R6 = R6 + R4; /* we'll use if we find a match*/ - R3 = ((16 << 8) | 2); /* Extract mask, two bits at posn 16 */ - - R5 = 0; -.Lisearch: - - R1 = [P0-0x100]; /* Address for this CPLB */ - - R0 = [P0++]; /* Info for this CPLB*/ - CC = BITTST(R0,0); /* Is the CPLB valid?*/ - IF !CC JUMP .Lnomatch; /* Skip it, if not.*/ - CC = R4 < R1(IU); /* If fault address less than page start*/ - IF CC JUMP .Lnomatch; /* then skip this one.*/ - R2 = EXTRACT(R0,R3.L) (Z); /* Get page size*/ - P1 = R2; - P1 = P5 + (P1<<2); /* index into page-size table*/ - R2 = [P1]; /* Get the page size*/ - R1 = R1 + R2; /* and add to page start, to get page end*/ - CC = R4 < R1(IU); /* and see whether fault addr is in page.*/ - IF !CC R4 = R6; /* If so, advance the address and finish loop.*/ - IF !CC JUMP .Lisearch_done; -.Lnomatch: - /* Go around again*/ - R5 += 1; - CC = BITTST(R5, 4); /* i.e CC = R5 >= 16*/ - IF !CC JUMP .Lisearch; - -.Lisearch_done: - I0 = R4; /* Fault address we'll search for*/ - - /* set up pointers */ - P0.L = LO(ICPLB_DATA0); - P0.H = HI(ICPLB_DATA0); - - /* The replacement procedure for ICPLBs */ - - P4.L = LO(IMEM_CONTROL); - P4.H = HI(IMEM_CONTROL); - - /* Turn off CPLBs while we work, necessary according to HRM before - * modifying CPLB descriptors - */ - R5 = [P4]; /* Control Register*/ - BITCLR(R5,ENICPLB_P); - CLI R1; - SSYNC; /* SSYNC required before writing to IMEM_CONTROL. */ - .align 8; - [P4] = R5; - SSYNC; - STI R1; - - R1 = -1; /* end point comparison */ - R3 = 16; /* counter */ - - /* Search through CPLBs for first non-locked entry */ - /* Overwrite it by moving everyone else up by 1 */ -.Licheck_lock: - R0 = [P0++]; - R3 = R3 + R1; - CC = R3 == R1; - IF CC JUMP .Lall_locked; - CC = BITTST(R0, 0); /* an invalid entry is good */ - IF !CC JUMP .Lifound_victim; - CC = BITTST(R0,1); /* but a locked entry isn't */ - IF CC JUMP .Licheck_lock; - -.Lifound_victim: -#ifdef CONFIG_CPLB_INFO - R7 = [P0 - 0x104]; - P2.L = _ipdt_table; - P2.H = _ipdt_table; - P3.L = _ipdt_swapcount_table; - P3.H = _ipdt_swapcount_table; - P3 += -4; -.Licount: - R2 = [P2]; /* address from config table */ - P2 += 8; - P3 += 8; - CC = R2==-1; - IF CC JUMP .Licount_done; - CC = R7==R2; - IF !CC JUMP .Licount; - R7 = [P3]; - R7 += 1; - [P3] = R7; - CSYNC; -.Licount_done: -#endif - LC0=R3; - LSETUP(.Lis_move,.Lie_move) LC0; -.Lis_move: - R0 = [P0]; - [P0 - 4] = R0; - R0 = [P0 - 0x100]; - [P0-0x104] = R0; -.Lie_move: - P0+=4; - - /* Clear ICPLB_DATA15, in case we don't find a replacement - * otherwise, we would have a duplicate entry, and will crash - */ - R0 = 0; - [P0 - 4] = R0; - - /* We've made space in the ICPLB table, so that ICPLB15 - * is now free to be overwritten. Next, we have to determine - * which CPLB we need to install, from the configuration - * table. This is a matter of getting the start-of-page - * addresses and page-lengths from the config table, and - * determining whether the fault address falls within that - * range. - */ - - P2.L = _ipdt_table; - P2.H = _ipdt_table; -#ifdef CONFIG_CPLB_INFO - P3.L = _ipdt_swapcount_table; - P3.H = _ipdt_swapcount_table; - P3 += -8; -#endif - P0.L = _page_size_table; - P0.H = _page_size_table; - - /* Retrieve our fault address (which may have been advanced - * because the faulting instruction crossed a page boundary). - */ - - R0 = I0; - - /* An extraction pattern, to get the page-size bits from - * the CPLB data entry. Bits 16-17, so two bits at posn 16. - */ - - R1 = ((16<<8)|2); -.Linext: R4 = [P2++]; /* address from config table */ - R2 = [P2++]; /* data from config table */ -#ifdef CONFIG_CPLB_INFO - P3 += 8; -#endif - - CC = R4 == -1; /* End of config table*/ - IF CC JUMP .Lno_page_in_table; - - /* See if failed address > start address */ - CC = R4 <= R0(IU); - IF !CC JUMP .Linext; - - /* extract page size (17:16)*/ - R3 = EXTRACT(R2, R1.L) (Z); - - /* add page size to addr to get range */ - - P5 = R3; - P5 = P0 + (P5 << 2); /* scaled, for int access*/ - R3 = [P5]; - R3 = R3 + R4; - - /* See if failed address < (start address + page size) */ - CC = R0 < R3(IU); - IF !CC JUMP .Linext; - - /* We've found a CPLB in the config table that covers - * the faulting address, so install this CPLB into the - * last entry of the table. - */ - - P1.L = LO(ICPLB_DATA15); /* ICPLB_DATA15 */ - P1.H = HI(ICPLB_DATA15); - [P1] = R2; - [P1-0x100] = R4; -#ifdef CONFIG_CPLB_INFO - R3 = [P3]; - R3 += 1; - [P3] = R3; -#endif - - /* P4 points to IMEM_CONTROL, and R5 contains its old - * value, after we disabled ICPLBS. Re-enable them. - */ - - BITSET(R5,ENICPLB_P); - CLI R2; - SSYNC; /* SSYNC required before writing to IMEM_CONTROL. */ - .align 8; - [P4] = R5; - SSYNC; - STI R2; - - ( R7:4,P5:3 ) = [SP++]; - R0 = CPLB_RELOADED; - RTS; - -/* FAILED CASES*/ -.Lno_page_in_table: - R0 = CPLB_NO_ADDR_MATCH; - JUMP .Lfail_ret; - -.Lall_locked: - R0 = CPLB_NO_UNLOCKED; - JUMP .Lfail_ret; - -.Lprot_violation: - R0 = CPLB_PROT_VIOL; - -.Lfail_ret: - /* Make sure we turn protection/cache back on, even in the failing case */ - BITSET(R5,ENICPLB_P); - CLI R2; - SSYNC; /* SSYNC required before writing to IMEM_CONTROL. */ - .align 8; - [P4] = R5; - SSYNC; - STI R2; - - ( R7:4,P5:3 ) = [SP++]; - RTS; - -.Ldcplb_write: - - /* if a DCPLB is marked as write-back (CPLB_WT==0), and - * it is clean (CPLB_DIRTY==0), then a write to the - * CPLB's page triggers a protection violation. We have to - * mark the CPLB as dirty, to indicate that there are - * pending writes associated with the CPLB. - */ - - P4.L = LO(DCPLB_STATUS); - P4.H = HI(DCPLB_STATUS); - P3.L = LO(DCPLB_DATA0); - P3.H = HI(DCPLB_DATA0); - R5 = [P4]; - - /* A protection violation can be caused by more than just writes - * to a clean WB page, so we have to ensure that: - * - It's a write - * - to a clean WB page - * - and is allowed in the mode the access occurred. - */ - - CC = BITTST(R5, 16); /* ensure it was a write*/ - IF !CC JUMP .Lprot_violation; - - /* to check the rest, we have to retrieve the DCPLB.*/ - - /* The low half of DCPLB_STATUS is a bit mask*/ - - R2 = R5.L (Z); /* indicating which CPLB triggered the event.*/ - R3 = 30; /* so we can use this to determine the offset*/ - R2.L = SIGNBITS R2; - R2 = R2.L (Z); /* into the DCPLB table.*/ - R3 = R3 - R2; - P4 = R3; - P3 = P3 + (P4<<2); - R3 = [P3]; /* Retrieve the CPLB*/ - - /* Now we can check whether it's a clean WB page*/ - - CC = BITTST(R3, 14); /* 0==WB, 1==WT*/ - IF CC JUMP .Lprot_violation; - CC = BITTST(R3, 7); /* 0 == clean, 1 == dirty*/ - IF CC JUMP .Lprot_violation; - - /* Check whether the write is allowed in the mode that was active.*/ - - R2 = 1<<3; /* checking write in user mode*/ - CC = BITTST(R5, 17); /* 0==was user, 1==was super*/ - R5 = CC; - R2 <<= R5; /* if was super, check write in super mode*/ - R2 = R3 & R2; - CC = R2 == 0; - IF CC JUMP .Lprot_violation; - - /* It's a genuine write-to-clean-page.*/ - - BITSET(R3, 7); /* mark as dirty*/ - [P3] = R3; /* and write back.*/ - NOP; - CSYNC; - ( R7:4,P5:3 ) = [SP++]; - R0 = CPLB_RELOADED; - RTS; - -.Ldcplb_miss_compare: - - /* Data CPLB Miss event. We need to choose a CPLB to - * evict, and then locate a new CPLB to install from the - * config table, that covers the faulting address. - */ - - P1.L = LO(DCPLB_DATA15); - P1.H = HI(DCPLB_DATA15); - - P4.L = LO(DCPLB_FAULT_ADDR); - P4.H = HI(DCPLB_FAULT_ADDR); - R4 = [P4]; - I0 = R4; - - /* The replacement procedure for DCPLBs*/ - - R6 = R1; /* Save for later*/ - - /* Turn off CPLBs while we work.*/ - P4.L = LO(DMEM_CONTROL); - P4.H = HI(DMEM_CONTROL); - R5 = [P4]; - BITCLR(R5,ENDCPLB_P); - CLI R0; - SSYNC; /* SSYNC required before writing to DMEM_CONTROL. */ - .align 8; - [P4] = R5; - SSYNC; - STI R0; - - /* Start looking for a CPLB to evict. Our order of preference - * is: invalid CPLBs, clean CPLBs, dirty CPLBs. Locked CPLBs - * are no good. - */ - - I1.L = LO(DCPLB_DATA0); - I1.H = HI(DCPLB_DATA0); - P1 = 2; - P2 = 16; - I2.L = _dcplb_preference; - I2.H = _dcplb_preference; - LSETUP(.Lsdsearch1, .Ledsearch1) LC0 = P1; -.Lsdsearch1: - R0 = [I2++]; /* Get the bits we're interested in*/ - P0 = I1; /* Go back to start of table*/ - LSETUP (.Lsdsearch2, .Ledsearch2) LC1 = P2; -.Lsdsearch2: - R1 = [P0++]; /* Fetch each installed CPLB in turn*/ - R2 = R1 & R0; /* and test for interesting bits.*/ - CC = R2 == 0; /* If none are set, it'll do.*/ - IF !CC JUMP .Lskip_stack_check; - - R2 = [P0 - 0x104]; /* R2 - PageStart */ - P3.L = _page_size_table; /* retrieve end address */ - P3.H = _page_size_table; /* retrieve end address */ - R3 = 0x1002; /* 16th - position, 2 bits -length */ -#if ANOMALY_05000209 - nop; /* Anomaly 05000209 */ -#endif - R7 = EXTRACT(R1,R3.l); - R7 = R7 << 2; /* Page size index offset */ - P5 = R7; - P3 = P3 + P5; - R7 = [P3]; /* page size in bytes */ - - R7 = R2 + R7; /* R7 - PageEnd */ - R4 = SP; /* Test SP is in range */ - - CC = R7 < R4; /* if PageEnd < SP */ - IF CC JUMP .Ldfound_victim; - R3 = 0x284; /* stack length from start of trap till - * the point. - * 20 stack locations for future modifications - */ - R4 = R4 + R3; - CC = R4 < R2; /* if SP + stacklen < PageStart */ - IF CC JUMP .Ldfound_victim; -.Lskip_stack_check: - -.Ledsearch2: NOP; -.Ledsearch1: NOP; - - /* If we got here, we didn't find a DCPLB we considered - * replacable, which means all of them were locked. - */ - - JUMP .Lall_locked; -.Ldfound_victim: - -#ifdef CONFIG_CPLB_INFO - R7 = [P0 - 0x104]; - P2.L = _dpdt_table; - P2.H = _dpdt_table; - P3.L = _dpdt_swapcount_table; - P3.H = _dpdt_swapcount_table; - P3 += -4; -.Ldicount: - R2 = [P2]; - P2 += 8; - P3 += 8; - CC = R2==-1; - IF CC JUMP .Ldicount_done; - CC = R7==R2; - IF !CC JUMP .Ldicount; - R7 = [P3]; - R7 += 1; - [P3] = R7; -.Ldicount_done: -#endif - - /* Clean down the hardware loops*/ - R2 = 0; - LC1 = R2; - LC0 = R2; - - /* There's a suitable victim in [P0-4] (because we've - * advanced already). - */ - -.LDdoverwrite: - - /* [P0-4] is a suitable victim CPLB, so we want to - * overwrite it by moving all the following CPLBs - * one space closer to the start. - */ - - R1.L = LO(DCPLB_DATA16); /* DCPLB_DATA15 + 4 */ - R1.H = HI(DCPLB_DATA16); - R0 = P0; - - /* If the victim happens to be in DCPLB15, - * we don't need to move anything. - */ - - CC = R1 == R0; - IF CC JUMP .Lde_moved; - R1 = R1 - R0; - R1 >>= 2; - P1 = R1; - LSETUP(.Lds_move, .Lde_move) LC0=P1; -.Lds_move: - R0 = [P0++]; /* move data */ - [P0 - 8] = R0; - R0 = [P0-0x104] /* move address */ -.Lde_move: - [P0-0x108] = R0; - -.Lde_moved: - NOP; - - /* Clear DCPLB_DATA15, in case we don't find a replacement - * otherwise, we would have a duplicate entry, and will crash - */ - R0 = 0; - [P0 - 0x4] = R0; - - /* We've now made space in DCPLB15 for the new CPLB to be - * installed. The next stage is to locate a CPLB in the - * config table that covers the faulting address. - */ - - R0 = I0; /* Our faulting address */ - - P2.L = _dpdt_table; - P2.H = _dpdt_table; -#ifdef CONFIG_CPLB_INFO - P3.L = _dpdt_swapcount_table; - P3.H = _dpdt_swapcount_table; - P3 += -8; -#endif - - P1.L = _page_size_table; - P1.H = _page_size_table; - - /* An extraction pattern, to retrieve bits 17:16.*/ - - R1 = (16<<8)|2; -.Ldnext: R4 = [P2++]; /* address */ - R2 = [P2++]; /* data */ -#ifdef CONFIG_CPLB_INFO - P3 += 8; -#endif - - CC = R4 == -1; - IF CC JUMP .Lno_page_in_table; - - /* See if failed address > start address */ - CC = R4 <= R0(IU); - IF !CC JUMP .Ldnext; - - /* extract page size (17:16)*/ - R3 = EXTRACT(R2, R1.L) (Z); - - /* add page size to addr to get range */ - - P5 = R3; - P5 = P1 + (P5 << 2); - R3 = [P5]; - R3 = R3 + R4; - - /* See if failed address < (start address + page size) */ - CC = R0 < R3(IU); - IF !CC JUMP .Ldnext; - - /* We've found the CPLB that should be installed, so - * write it into CPLB15, masking off any caching bits - * if necessary. - */ - - P1.L = LO(DCPLB_DATA15); - P1.H = HI(DCPLB_DATA15); - - /* If the DCPLB has cache bits set, but caching hasn't - * been enabled, then we want to mask off the cache-in-L1 - * bit before installing. Moreover, if caching is off, we - * also want to ensure that the DCPLB has WT mode set, rather - * than WB, since WB pages still trigger first-write exceptions - * even when not caching is off, and the page isn't marked as - * cachable. Finally, we could mark the page as clean, not dirty, - * but we choose to leave that decision to the user; if the user - * chooses to have a CPLB pre-defined as dirty, then they always - * pay the cost of flushing during eviction, but don't pay the - * cost of first-write exceptions to mark the page as dirty. - */ - -#ifdef CONFIG_BFIN_WT - BITSET(R6, 14); /* Set WT*/ -#endif - - [P1] = R2; - [P1-0x100] = R4; -#ifdef CONFIG_CPLB_INFO - R3 = [P3]; - R3 += 1; - [P3] = R3; -#endif - - /* We've installed the CPLB, so re-enable CPLBs. P4 - * points to DMEM_CONTROL, and R5 is the value we - * last wrote to it, when we were disabling CPLBs. - */ - - BITSET(R5,ENDCPLB_P); - CLI R2; - .align 8; - [P4] = R5; - SSYNC; - STI R2; - - ( R7:4,P5:3 ) = [SP++]; - R0 = CPLB_RELOADED; - RTS; -ENDPROC(_cplb_mgr) - -.data -.align 4; -_page_size_table: -.byte4 0x00000400; /* 1K */ -.byte4 0x00001000; /* 4K */ -.byte4 0x00100000; /* 1M */ -.byte4 0x00400000; /* 4M */ - -.align 4; -_dcplb_preference: -.byte4 0x00000001; /* valid bit */ -.byte4 0x00000002; /* lock bit */ -- cgit v0.10.2 From 4521ef42de8dbaa9bce3f60bbb5868564f752e98 Mon Sep 17 00:00:00 2001 From: Michael Hennerich Date: Fri, 11 Jan 2008 17:21:41 +0800 Subject: [Blackfin] arch: Add some comments - fix semicolons Signed-off-by: Michael Hennerich Signed-off-by: Bryan Wu diff --git a/arch/blackfin/mach-common/dpmc.S b/arch/blackfin/mach-common/dpmc.S index 301ac1b..b82c096e 100644 --- a/arch/blackfin/mach-common/dpmc.S +++ b/arch/blackfin/mach-common/dpmc.S @@ -175,7 +175,7 @@ ENTRY(_sleep_mode) call _set_sic_iwr; R0 = 0xFFFF (Z); - call _set_rtc_istat + call _set_rtc_istat; P0.H = hi(PLL_CTL); P0.L = lo(PLL_CTL); @@ -213,7 +213,7 @@ ENTRY(_hibernate_mode) call _set_sic_iwr; R0 = 0xFFFF (Z); - call _set_rtc_istat + call _set_rtc_istat; P0.H = hi(VR_CTL); P0.L = lo(VR_CTL); @@ -288,23 +288,22 @@ ENTRY(_sleep_deeper) P3 = R0; R0 = IWR_ENABLE(0); call _set_sic_iwr; - call _set_dram_srfs; + call _set_dram_srfs; /* Set SDRAM Self Refresh */ /* Clear all the interrupts,bits sticky */ R0 = 0xFFFF (Z); - call _set_rtc_istat - + call _set_rtc_istat; P0.H = hi(PLL_DIV); P0.L = lo(PLL_DIV); R6 = W[P0](z); R0.L = 0xF; - W[P0] = R0.l; + W[P0] = R0.l; /* Set Max VCO to SCLK divider */ P0.H = hi(PLL_CTL); P0.L = lo(PLL_CTL); R5 = W[P0](z); R0.L = (CONFIG_MIN_VCO_HZ/CONFIG_CLKIN_HZ) << 9; - W[P0] = R0.l; + W[P0] = R0.l; /* Set Min CLKIN to VCO multiplier */ SSYNC; IDLE; @@ -320,29 +319,28 @@ ENTRY(_sleep_deeper) R1 = R1|R2; R2 = DEPOSIT(R7, R1); - W[P0] = R2; + W[P0] = R2; /* Set Min Core Voltage */ SSYNC; IDLE; call _test_pll_locked; + R0 = P3; + call _set_sic_iwr; /* Set Awake from IDLE */ + P0.H = hi(PLL_CTL); P0.L = lo(PLL_CTL); R0 = W[P0](z); BITSET (R0, 3); - W[P0] = R0.L; - - R0 = P3; - call _set_sic_iwr; - + W[P0] = R0.L; /* Turn CCLK OFF */ SSYNC; IDLE; call _test_pll_locked; R0 = IWR_ENABLE(0); - call _set_sic_iwr; + call _set_sic_iwr; /* Set Awake from IDLE PLL */ P0.H = hi(VR_CTL); P0.L = lo(VR_CTL); @@ -355,15 +353,15 @@ ENTRY(_sleep_deeper) P0.H = hi(PLL_DIV); P0.L = lo(PLL_DIV); - W[P0]= R6; + W[P0]= R6; /* Restore CCLK and SCLK divider */ P0.H = hi(PLL_CTL); P0.L = lo(PLL_CTL); - w[p0] = R5; + w[p0] = R5; /* Restore VCO multiplier */ IDLE; call _test_pll_locked; - call _unset_dram_srfs; + call _unset_dram_srfs; /* SDRAM Self Refresh Off */ STI R4; -- cgit v0.10.2 From 2047e40d724d42928c0b5994a1568c1b738efdb7 Mon Sep 17 00:00:00 2001 From: Michael Hennerich Date: Tue, 22 Jan 2008 15:29:18 +0800 Subject: [Blackfin] arch: set_bfin_dma_config shouldnt set SYNC or RESTART by default - add argument or option Signed-off-by: Michael Hennerich Signed-off-by: Bryan Wu diff --git a/arch/blackfin/kernel/bfin_dma_5xx.c b/arch/blackfin/kernel/bfin_dma_5xx.c index b544460..fa9debe8 100644 --- a/arch/blackfin/kernel/bfin_dma_5xx.c +++ b/arch/blackfin/kernel/bfin_dma_5xx.c @@ -339,13 +339,13 @@ EXPORT_SYMBOL(set_dma_config); unsigned short set_bfin_dma_config(char direction, char flow_mode, - char intr_mode, char dma_mode, char width) + char intr_mode, char dma_mode, char width, char syncmode) { unsigned short config; config = ((direction << 1) | (width << 2) | (dma_mode << 4) | - (intr_mode << 6) | (flow_mode << 12) | RESTART); + (intr_mode << 6) | (flow_mode << 12) | (syncmode << 5)); return config; } EXPORT_SYMBOL(set_bfin_dma_config); diff --git a/drivers/serial/bfin_5xx.c b/drivers/serial/bfin_5xx.c index 6f475b6..ac2a3ef 100644 --- a/drivers/serial/bfin_5xx.c +++ b/drivers/serial/bfin_5xx.c @@ -442,7 +442,8 @@ static void bfin_serial_dma_tx_chars(struct bfin_serial_port *uart) set_bfin_dma_config(DIR_READ, DMA_FLOW_STOP, INTR_ON_BUF, DIMENSION_LINEAR, - DATA_SIZE_8)); + DATA_SIZE_8, + DMA_SYNC_RESTART)); set_dma_start_addr(uart->tx_dma_channel, (unsigned long)(xmit->buf+xmit->tail)); set_dma_x_count(uart->tx_dma_channel, uart->tx_count); set_dma_x_modify(uart->tx_dma_channel, 1); @@ -689,7 +690,8 @@ static int bfin_serial_startup(struct uart_port *port) set_dma_config(uart->rx_dma_channel, set_bfin_dma_config(DIR_WRITE, DMA_FLOW_AUTO, INTR_ON_ROW, DIMENSION_2D, - DATA_SIZE_8)); + DATA_SIZE_8, + DMA_SYNC_RESTART)); set_dma_x_count(uart->rx_dma_channel, DMA_RX_XCOUNT); set_dma_x_modify(uart->rx_dma_channel, 1); set_dma_y_count(uart->rx_dma_channel, DMA_RX_YCOUNT); diff --git a/drivers/video/bf54x-lq043fb.c b/drivers/video/bf54x-lq043fb.c index 74d11c3..1b7e54de 100644 --- a/drivers/video/bf54x-lq043fb.c +++ b/drivers/video/bf54x-lq043fb.c @@ -224,7 +224,8 @@ static int config_dma(struct bfin_bf54xfb_info *fbi) set_dma_config(CH_EPPI0, set_bfin_dma_config(DIR_READ, DMA_FLOW_AUTO, INTR_DISABLE, DIMENSION_2D, - DATA_SIZE_32)); + DATA_SIZE_32, + DMA_NOSYNC_KEEP_DMA_BUF)); set_dma_x_count(CH_EPPI0, (LCD_X_RES * LCD_BPP) / DMA_BUS_SIZE); set_dma_x_modify(CH_EPPI0, DMA_BUS_SIZE / 8); set_dma_y_count(CH_EPPI0, LCD_Y_RES); diff --git a/include/asm-blackfin/dma.h b/include/asm-blackfin/dma.h index b469505..5abaa2c 100644 --- a/include/asm-blackfin/dma.h +++ b/include/asm-blackfin/dma.h @@ -76,6 +76,9 @@ enum dma_chan_status { #define INTR_ON_BUF 2 #define INTR_ON_ROW 3 +#define DMA_NOSYNC_KEEP_DMA_BUF 0 +#define DMA_SYNC_RESTART 1 + struct dmasg { unsigned long next_desc_addr; unsigned long start_addr; @@ -157,7 +160,8 @@ void set_dma_y_count(unsigned int channel, unsigned short y_count); void set_dma_y_modify(unsigned int channel, short y_modify); void set_dma_config(unsigned int channel, unsigned short config); unsigned short set_bfin_dma_config(char direction, char flow_mode, - char intr_mode, char dma_mode, char width); + char intr_mode, char dma_mode, char width, + char syncmode); void set_dma_curr_addr(unsigned int channel, unsigned long addr); /* get curr status for polling */ -- cgit v0.10.2 From b97b8a998397e8c64699559099fa9febffae2b4d Mon Sep 17 00:00:00 2001 From: Bernd Schmidt Date: Sun, 27 Jan 2008 18:39:16 +0800 Subject: [Blackfin] arch: Initial checkin of the memory protection support. Enable it with CONFIG_MPU. Signed-off-by: Bernd Schmidt Signed-off-by: Bryan Wu diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig index ce521a9..6b96d7d 100644 --- a/arch/blackfin/Kconfig +++ b/arch/blackfin/Kconfig @@ -765,6 +765,15 @@ config L1_MAX_PIECE Set the max memory pieces for the L1 SRAM allocation algorithm. Min value is 16. Max value is 1024. + +config MPU + bool "Enable the memory protection unit (EXPERIMENTAL)" + default n + help + Use the processor's MPU to protect applications from accessing + memory they do not own. This comes at a performance penalty + and is recommended only for debugging. + comment "Asynchonous Memory Configuration" menu "EBIU_AMGCTL Global Control" diff --git a/arch/blackfin/Makefile b/arch/blackfin/Makefile index 2fc899c..0edc402 100644 --- a/arch/blackfin/Makefile +++ b/arch/blackfin/Makefile @@ -82,7 +82,11 @@ core-y += arch/$(ARCH)/mach-$(MACHINE)/ core-y += arch/$(ARCH)/mach-$(MACHINE)/boards/ endif -core-y += arch/$(ARCH)/kernel/cplb-nompu/ +ifeq ($(CONFIG_MPU),y) +core-y += arch/$(ARCH)/kernel/cplb-mpu/ +else +core-y += arch/$(ARCH)/kernel/cplb-nompu/ +endif libs-y += arch/$(ARCH)/lib/ diff --git a/arch/blackfin/kernel/cplb-mpu/Makefile b/arch/blackfin/kernel/cplb-mpu/Makefile new file mode 100644 index 0000000..286b693 --- /dev/null +++ b/arch/blackfin/kernel/cplb-mpu/Makefile @@ -0,0 +1,8 @@ +# +# arch/blackfin/kernel/cplb-nompu/Makefile +# + +obj-y := cplbinit.o cacheinit.o cplbmgr.o + +obj-$(CONFIG_CPLB_INFO) += cplbinfo.o + diff --git a/arch/blackfin/kernel/cplb-mpu/cacheinit.c b/arch/blackfin/kernel/cplb-mpu/cacheinit.c new file mode 100644 index 0000000..9eecfa4 --- /dev/null +++ b/arch/blackfin/kernel/cplb-mpu/cacheinit.c @@ -0,0 +1,62 @@ +/* + * Copyright 2004-2007 Analog Devices Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see the file COPYING, or write + * to the Free Software Foundation, Inc., + * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include + +#include +#include +#include +#include + +#if defined(CONFIG_BFIN_ICACHE) +void bfin_icache_init(void) +{ + unsigned long ctrl; + int i; + + SSYNC(); + for (i = 0; i < MAX_CPLBS; i++) { + bfin_write32(ICPLB_ADDR0 + i * 4, icplb_tbl[i].addr); + bfin_write32(ICPLB_DATA0 + i * 4, icplb_tbl[i].data); + } + ctrl = bfin_read_IMEM_CONTROL(); + ctrl |= IMC | ENICPLB; + bfin_write_IMEM_CONTROL(ctrl); + SSYNC(); +} +#endif + +#if defined(CONFIG_BFIN_DCACHE) +void bfin_dcache_init(void) +{ + unsigned long ctrl; + int i; + + SSYNC(); + for (i = 0; i < MAX_CPLBS; i++) { + bfin_write32(DCPLB_ADDR0 + i * 4, dcplb_tbl[i].addr); + bfin_write32(DCPLB_DATA0 + i * 4, dcplb_tbl[i].data); + } + + ctrl = bfin_read_DMEM_CONTROL(); + ctrl |= DMEM_CNTR; + bfin_write_DMEM_CONTROL(ctrl); + SSYNC(); +} +#endif diff --git a/arch/blackfin/kernel/cplb-mpu/cplbinfo.c b/arch/blackfin/kernel/cplb-mpu/cplbinfo.c new file mode 100644 index 0000000..bd07229 --- /dev/null +++ b/arch/blackfin/kernel/cplb-mpu/cplbinfo.c @@ -0,0 +1,144 @@ +/* + * File: arch/blackfin/mach-common/cplbinfo.c + * Based on: + * Author: Sonic Zhang + * + * Created: Jan. 2005 + * Description: Display CPLB status + * + * Modified: + * Copyright 2004-2006 Analog Devices Inc. + * + * Bugs: Enter bugs at http://blackfin.uclinux.org/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see the file COPYING, or write + * to the Free Software Foundation, Inc., + * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#define CPLB_I 1 +#define CPLB_D 2 + +#define SYNC_SYS SSYNC() +#define SYNC_CORE CSYNC() + +#define CPLB_BIT_PAGESIZE 0x30000 + +static char page_size_string_table[][4] = { "1K", "4K", "1M", "4M" }; + +static char *cplb_print_entry(char *buf, struct cplb_entry *tbl, int switched) +{ + int i; + buf += sprintf(buf, "Index\tAddress\t\tData\tSize\tU/RD\tU/WR\tS/WR\tSwitch\n"); + for (i = 0; i < MAX_CPLBS; i++) { + unsigned long data = tbl[i].data; + unsigned long addr = tbl[i].addr; + if (!(data & CPLB_VALID)) + continue; + + buf += + sprintf(buf, + "%d\t0x%08lx\t%06lx\t%s\t%c\t%c\t%c\t%c\n", + i, addr, data, + page_size_string_table[(data & 0x30000) >> 16], + (data & CPLB_USER_RD) ? 'Y' : 'N', + (data & CPLB_USER_WR) ? 'Y' : 'N', + (data & CPLB_SUPV_WR) ? 'Y' : 'N', + i < switched ? 'N' : 'Y'); + } + buf += sprintf(buf, "\n"); + + return buf; +} + +int cplbinfo_proc_output(char *buf) +{ + char *p; + + p = buf; + + p += sprintf(p, "------------------ CPLB Information ------------------\n\n"); + + if (bfin_read_IMEM_CONTROL() & ENICPLB) { + p += sprintf(p, "Instruction CPLB entry:\n"); + p = cplb_print_entry(p, icplb_tbl, first_switched_icplb); + } else + p += sprintf(p, "Instruction CPLB is disabled.\n\n"); + + if (1 || bfin_read_DMEM_CONTROL() & ENDCPLB) { + p += sprintf(p, "Data CPLB entry:\n"); + p = cplb_print_entry(p, dcplb_tbl, first_switched_dcplb); + } else + p += sprintf(p, "Data CPLB is disabled.\n"); + + p += sprintf(p, "ICPLB miss: %d\nICPLB supervisor miss: %d\n", + nr_icplb_miss, nr_icplb_supv_miss); + p += sprintf(p, "DCPLB miss: %d\nDCPLB protection fault:%d\n", + nr_dcplb_miss, nr_dcplb_prot); + p += sprintf(p, "CPLB flushes: %d\n", + nr_cplb_flush); + + return p - buf; +} + +static int cplbinfo_read_proc(char *page, char **start, off_t off, + int count, int *eof, void *data) +{ + int len; + + len = cplbinfo_proc_output(page); + if (len <= off + count) + *eof = 1; + *start = page + off; + len -= off; + if (len > count) + len = count; + if (len < 0) + len = 0; + return len; +} + +static int __init cplbinfo_init(void) +{ + struct proc_dir_entry *entry; + + entry = create_proc_entry("cplbinfo", 0, NULL); + if (!entry) + return -ENOMEM; + + entry->read_proc = cplbinfo_read_proc; + entry->data = NULL; + + return 0; +} + +static void __exit cplbinfo_exit(void) +{ + remove_proc_entry("cplbinfo", NULL); +} + +module_init(cplbinfo_init); +module_exit(cplbinfo_exit); diff --git a/arch/blackfin/kernel/cplb-mpu/cplbinit.c b/arch/blackfin/kernel/cplb-mpu/cplbinit.c new file mode 100644 index 0000000..e2e2b50 --- /dev/null +++ b/arch/blackfin/kernel/cplb-mpu/cplbinit.c @@ -0,0 +1,91 @@ +/* + * Blackfin CPLB initialization + * + * Copyright 2004-2007 Analog Devices Inc. + * + * Bugs: Enter bugs at http://blackfin.uclinux.org/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see the file COPYING, or write + * to the Free Software Foundation, Inc., + * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include + +#include +#include +#include + +struct cplb_entry icplb_tbl[MAX_CPLBS]; +struct cplb_entry dcplb_tbl[MAX_CPLBS]; + +int first_switched_icplb, first_switched_dcplb; +int first_mask_dcplb; + +void __init generate_cpl_tables(void) +{ + int i_d, i_i; + unsigned long addr; + unsigned long d_data, i_data; + unsigned long d_cache = 0, i_cache = 0; + +#ifdef CONFIG_BFIN_ICACHE + i_cache = CPLB_L1_CHBL | ANOMALY_05000158_WORKAROUND; +#endif + +#ifdef CONFIG_BFIN_DCACHE + d_cache = CPLB_L1_CHBL; +#ifdef CONFIG_BLKFIN_WT + d_cache |= CPLB_L1_AOW | CPLB_WT; +#endif +#endif + i_d = i_i = 0; + + /* Set up the zero page. */ + dcplb_tbl[i_d].addr = 0; + dcplb_tbl[i_d++].data = SDRAM_OOPS | PAGE_SIZE_1KB; + +#if 0 + icplb_tbl[i_i].addr = 0; + icplb_tbl[i_i++].data = i_cache | CPLB_USER_RD | PAGE_SIZE_4KB; +#endif + + /* Cover kernel memory with 4M pages. */ + addr = 0; + d_data = d_cache | CPLB_SUPV_WR | CPLB_VALID | PAGE_SIZE_4MB | CPLB_DIRTY; + i_data = i_cache | CPLB_VALID | CPLB_PORTPRIO | PAGE_SIZE_4MB; + + for (; addr < memory_start; addr += 4 * 1024 * 1024) { + dcplb_tbl[i_d].addr = addr; + dcplb_tbl[i_d++].data = d_data; + icplb_tbl[i_i].addr = addr; + icplb_tbl[i_i++].data = i_data | (addr == 0 ? CPLB_USER_RD : 0); + } + + /* Cover L1 memory. One 4M area for code and data each is enough. */ +#if L1_DATA_A_LENGTH > 0 || L1_DATA_B_LENGTH > 0 + dcplb_tbl[i_d].addr = L1_DATA_A_START; + dcplb_tbl[i_d++].data = L1_DMEMORY | PAGE_SIZE_4MB; +#endif + icplb_tbl[i_i].addr = L1_CODE_START; + icplb_tbl[i_i++].data = L1_IMEMORY | PAGE_SIZE_4MB; + + first_mask_dcplb = i_d; + first_switched_dcplb = i_d + (1 << page_mask_order); + first_switched_icplb = i_i; + + while (i_d < MAX_CPLBS) + dcplb_tbl[i_d++].data = 0; + while (i_i < MAX_CPLBS) + icplb_tbl[i_i++].data = 0; +} diff --git a/arch/blackfin/kernel/cplb-mpu/cplbmgr.c b/arch/blackfin/kernel/cplb-mpu/cplbmgr.c new file mode 100644 index 0000000..c426a22 --- /dev/null +++ b/arch/blackfin/kernel/cplb-mpu/cplbmgr.c @@ -0,0 +1,338 @@ +/* + * Blackfin CPLB exception handling. + * Copyright 2004-2007 Analog Devices Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see the file COPYING, or write + * to the Free Software Foundation, Inc., + * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include +#include + +#include +#include +#include + +#ifdef CONFIG_BFIN_ICACHE + +#define FAULT_RW (1 << 16) +#define FAULT_USERSUPV (1 << 17) + +int page_mask_nelts; +int page_mask_order; +unsigned long *current_rwx_mask; + +int nr_dcplb_miss, nr_icplb_miss, nr_icplb_supv_miss, nr_dcplb_prot; +int nr_cplb_flush; + +static inline void disable_dcplb(void) +{ + unsigned long ctrl; + SSYNC(); + ctrl = bfin_read_DMEM_CONTROL(); + ctrl &= ~ENDCPLB; + bfin_write_DMEM_CONTROL(ctrl); + SSYNC(); +} + +static inline void enable_dcplb(void) +{ + unsigned long ctrl; + SSYNC(); + ctrl = bfin_read_DMEM_CONTROL(); + ctrl |= ENDCPLB; + bfin_write_DMEM_CONTROL(ctrl); + SSYNC(); +} + +static inline void disable_icplb(void) +{ + unsigned long ctrl; + SSYNC(); + ctrl = bfin_read_IMEM_CONTROL(); + ctrl &= ~ENICPLB; + bfin_write_IMEM_CONTROL(ctrl); + SSYNC(); +} + +static inline void enable_icplb(void) +{ + unsigned long ctrl; + SSYNC(); + ctrl = bfin_read_IMEM_CONTROL(); + ctrl |= ENICPLB; + bfin_write_IMEM_CONTROL(ctrl); + SSYNC(); +} + +/* + * Given the contents of the status register, return the index of the + * CPLB that caused the fault. + */ +static inline int faulting_cplb_index(int status) +{ + int signbits = __builtin_bfin_norm_fr1x32(status & 0xFFFF); + return 30 - signbits; +} + +/* + * Given the contents of the status register and the DCPLB_DATA contents, + * return true if a write access should be permitted. + */ +static inline int write_permitted(int status, unsigned long data) +{ + if (status & FAULT_USERSUPV) + return !!(data & CPLB_SUPV_WR); + else + return !!(data & CPLB_USER_WR); +} + +/* Counters to implement round-robin replacement. */ +static int icplb_rr_index, dcplb_rr_index; + +/* + * Find an ICPLB entry to be evicted and return its index. + */ +static int evict_one_icplb(void) +{ + int i; + for (i = first_switched_icplb; i < MAX_CPLBS; i++) + if ((icplb_tbl[i].data & CPLB_VALID) == 0) + return i; + i = first_switched_icplb + icplb_rr_index; + if (i >= MAX_CPLBS) { + i -= MAX_CPLBS - first_switched_icplb; + icplb_rr_index -= MAX_CPLBS - first_switched_icplb; + } + icplb_rr_index++; + return i; +} + +static int evict_one_dcplb(void) +{ + int i; + for (i = first_switched_dcplb; i < MAX_CPLBS; i++) + if ((dcplb_tbl[i].data & CPLB_VALID) == 0) + return i; + i = first_switched_dcplb + dcplb_rr_index; + if (i >= MAX_CPLBS) { + i -= MAX_CPLBS - first_switched_dcplb; + dcplb_rr_index -= MAX_CPLBS - first_switched_dcplb; + } + dcplb_rr_index++; + return i; +} + +static noinline int dcplb_miss(void) +{ + unsigned long addr = bfin_read_DCPLB_FAULT_ADDR(); + int status = bfin_read_DCPLB_STATUS(); + unsigned long *mask; + int idx; + unsigned long d_data; + + nr_dcplb_miss++; + if (addr >= _ramend) + return CPLB_PROT_VIOL; + + d_data = CPLB_SUPV_WR | CPLB_VALID | CPLB_DIRTY | PAGE_SIZE_4KB; +#ifdef CONFIG_BFIN_DCACHE + d_data |= CPLB_L1_CHBL | ANOMALY_05000158_WORKAROUND; +#ifdef CONFIG_BLKFIN_WT + d_data |= CPLB_L1_AOW | CPLB_WT; +#endif +#endif + mask = current_rwx_mask; + if (mask) { + int page = addr >> PAGE_SHIFT; + int offs = page >> 5; + int bit = 1 << (page & 31); + + if (mask[offs] & bit) + d_data |= CPLB_USER_RD; + + mask += page_mask_nelts; + if (mask[offs] & bit) + d_data |= CPLB_USER_WR; + } + + idx = evict_one_dcplb(); + + addr &= PAGE_MASK; + dcplb_tbl[idx].addr = addr; + dcplb_tbl[idx].data = d_data; + + disable_dcplb(); + bfin_write32(DCPLB_DATA0 + idx * 4, d_data); + bfin_write32(DCPLB_ADDR0 + idx * 4, addr); + enable_dcplb(); + + return 0; +} + +static noinline int icplb_miss(void) +{ + unsigned long addr = bfin_read_ICPLB_FAULT_ADDR(); + int status = bfin_read_ICPLB_STATUS(); + int idx; + unsigned long i_data; + + nr_icplb_miss++; + if (status & FAULT_USERSUPV) + nr_icplb_supv_miss++; + + if (addr >= _ramend) + return CPLB_PROT_VIOL; + + /* + * First, try to find a CPLB that matches this address. If we + * find one, then the fact that we're in the miss handler means + * that the instruction crosses a page boundary. + */ + for (idx = first_switched_icplb; idx < MAX_CPLBS; idx++) { + if (icplb_tbl[idx].data & CPLB_VALID) { + unsigned long this_addr = icplb_tbl[idx].addr; + if (this_addr <= addr && this_addr + PAGE_SIZE > addr) { + addr += PAGE_SIZE; + break; + } + } + } + + i_data = CPLB_VALID | CPLB_PORTPRIO | PAGE_SIZE_4KB; +#ifdef CONFIG_BFIN_ICACHE + i_data |= CPLB_L1_CHBL | ANOMALY_05000158_WORKAROUND; +#endif + + /* + * Two cases to distinguish - a supervisor access must necessarily + * be for a module page; we grant it unconditionally (could do better + * here in the future). Otherwise, check the x bitmap of the current + * process. + */ + if (!(status & FAULT_USERSUPV)) { + unsigned long *mask = current_rwx_mask; + + if (mask) { + int page = addr >> PAGE_SHIFT; + int offs = page >> 5; + int bit = 1 << (page & 31); + + mask += 2 * page_mask_nelts; + if (mask[offs] & bit) + i_data |= CPLB_USER_RD; + } + } + + idx = evict_one_icplb(); + addr &= PAGE_MASK; + icplb_tbl[idx].addr = addr; + icplb_tbl[idx].data = i_data; + + disable_icplb(); + bfin_write32(ICPLB_DATA0 + idx * 4, i_data); + bfin_write32(ICPLB_ADDR0 + idx * 4, addr); + enable_icplb(); + + return 0; +} + +static noinline int dcplb_protection_fault(void) +{ + unsigned long addr = bfin_read_DCPLB_FAULT_ADDR(); + int status = bfin_read_DCPLB_STATUS(); + + nr_dcplb_prot++; + + if (status & FAULT_RW) { + int idx = faulting_cplb_index(status); + unsigned long data = dcplb_tbl[idx].data; + if (!(data & CPLB_WT) && !(data & CPLB_DIRTY) && + write_permitted(status, data)) { + data |= CPLB_DIRTY; + dcplb_tbl[idx].data = data; + bfin_write32(DCPLB_DATA0 + idx * 4, data); + return 0; + } + } + return CPLB_PROT_VIOL; +} + +int cplb_hdr(int seqstat, struct pt_regs *regs) +{ + int cause = seqstat & 0x3f; + switch (cause) { + case 0x23: + return dcplb_protection_fault(); + case 0x2C: + return icplb_miss(); + case 0x26: + return dcplb_miss(); + default: + return 1; + panic_cplb_error(seqstat, regs); + } +} + +void flush_switched_cplbs(void) +{ + int i; + + nr_cplb_flush++; + + disable_icplb(); + for (i = first_switched_icplb; i < MAX_CPLBS; i++) { + icplb_tbl[i].data = 0; + bfin_write32(ICPLB_DATA0 + i * 4, 0); + } + enable_icplb(); + + disable_dcplb(); + for (i = first_mask_dcplb; i < MAX_CPLBS; i++) { + dcplb_tbl[i].data = 0; + bfin_write32(DCPLB_DATA0 + i * 4, 0); + } + enable_dcplb(); +} + +void set_mask_dcplbs(unsigned long *masks) +{ + int i; + unsigned long addr = (unsigned long)masks; + unsigned long d_data; + current_rwx_mask = masks; + + if (!masks) + return; + + d_data = CPLB_SUPV_WR | CPLB_VALID | CPLB_DIRTY | PAGE_SIZE_4KB; +#ifdef CONFIG_BFIN_DCACHE + d_data |= CPLB_L1_CHBL; +#ifdef CONFIG_BLKFIN_WT + d_data |= CPLB_L1_AOW | CPLB_WT; +#endif +#endif + + disable_dcplb(); + for (i = first_mask_dcplb; i < first_switched_dcplb; i++) { + dcplb_tbl[i].addr = addr; + dcplb_tbl[i].data = d_data; + bfin_write32(DCPLB_DATA0 + i * 4, d_data); + bfin_write32(DCPLB_ADDR0 + i * 4, addr); + addr += PAGE_SIZE; + } + enable_dcplb(); +} + +#endif diff --git a/arch/blackfin/kernel/setup.c b/arch/blackfin/kernel/setup.c index a03c2df..1a942a7 100644 --- a/arch/blackfin/kernel/setup.c +++ b/arch/blackfin/kernel/setup.c @@ -238,7 +238,12 @@ void __init setup_arch(char **cmdline_p) memory_end = _ramend - DMA_UNCACHED_REGION; _ramstart = (unsigned long)__bss_stop; +#ifdef CONFIG_MPU + /* Round up to multiple of 4MB. */ + memory_start = (_ramstart + 0x3fffff) & ~0x3fffff; +#else memory_start = PAGE_ALIGN(_ramstart); +#endif #if defined(CONFIG_MTD_UCLINUX) /* generic memory mapped MTD driver */ @@ -307,6 +312,11 @@ void __init setup_arch(char **cmdline_p) printk(KERN_NOTICE "Warning: limiting memory to %liMB due to hardware anomaly 05000263\n", memory_end >> 20); #endif /* ANOMALY_05000263 */ +#ifdef CONFIG_MPU + page_mask_nelts = ((_ramend >> PAGE_SHIFT) + 31) / 32; + page_mask_order = get_order(3 * page_mask_nelts * sizeof(long)); +#endif + #if !defined(CONFIG_MTD_UCLINUX) memory_end -= SIZE_4K; /*In case there is no valid CPLB behind memory_end make sure we don't get to close*/ #endif diff --git a/arch/blackfin/mach-common/entry.S b/arch/blackfin/mach-common/entry.S index 58f7ad6..c2e81a1 100644 --- a/arch/blackfin/mach-common/entry.S +++ b/arch/blackfin/mach-common/entry.S @@ -95,6 +95,9 @@ ENTRY(_ex_workaround_261) R6 = 0x26; /* Data CPLB Miss */ cc = R6 == R7; if cc jump _ex_dcplb_miss (BP); + R6 = 0x23; /* Data CPLB Miss */ + cc = R6 == R7; + if cc jump _ex_dcplb_viol (BP); /* Handle 0x23 Data CPLB Protection Violation * and Data CPLB Multiple Hits - Linux Trap Zero */ @@ -102,17 +105,33 @@ ENTRY(_ex_workaround_261) ENDPROC(_ex_workaround_261) #else +#ifdef CONFIG_MPU +#define _ex_dviol _ex_dcplb_viol +#else #define _ex_dviol _ex_trap_c +#endif #define _ex_dmiss _ex_dcplb_miss #define _ex_dmult _ex_trap_c #endif + +ENTRY(_ex_dcplb_viol) ENTRY(_ex_dcplb_miss) ENTRY(_ex_icplb_miss) (R7:6,P5:4) = [sp++]; ASTAT = [sp++]; SAVE_ALL_SYS +#ifdef CONFIG_MPU + R0 = SEQSTAT; + R1 = SP; + sp += -12; + call _cplb_hdr; + sp += 12; + CC = R0 == 0; + IF !CC JUMP _handle_bad_cplb; +#else call __cplb_hdr; +#endif DEBUG_START_HWTRACE(p5, r7) RESTORE_ALL_SYS SP = EX_SCRATCH_REG; diff --git a/arch/blackfin/mm/init.c b/arch/blackfin/mm/init.c index e97ea8f..9f007ca 100644 --- a/arch/blackfin/mm/init.c +++ b/arch/blackfin/mm/init.c @@ -184,13 +184,15 @@ static __init void free_init_pages(const char *what, unsigned long begin, unsign #ifdef CONFIG_BLK_DEV_INITRD void __init free_initrd_mem(unsigned long start, unsigned long end) { +#ifndef CONFIG_MPU free_init_pages("initrd memory", start, end); +#endif } #endif void __init free_initmem(void) { -#ifdef CONFIG_RAMKERNEL +#if defined CONFIG_RAMKERNEL && !defined CONFIG_MPU free_init_pages("unused kernel memory", (unsigned long)(&__init_begin), (unsigned long)(&__init_end)); diff --git a/include/asm-blackfin/cplb-mpu.h b/include/asm-blackfin/cplb-mpu.h new file mode 100644 index 0000000..75c67b9 --- /dev/null +++ b/include/asm-blackfin/cplb-mpu.h @@ -0,0 +1,61 @@ +/* + * File: include/asm-blackfin/cplbinit.h + * Based on: + * Author: + * + * Created: + * Description: + * + * Modified: + * Copyright 2004-2006 Analog Devices Inc. + * + * Bugs: Enter bugs at http://blackfin.uclinux.org/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see the file COPYING, or write + * to the Free Software Foundation, Inc., + * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#ifndef __ASM_BFIN_CPLB_MPU_H +#define __ASM_BFIN_CPLB_MPU_H + +struct cplb_entry { + unsigned long data, addr; +}; + +struct mem_region { + unsigned long start, end; + unsigned long dcplb_data; + unsigned long icplb_data; +}; + +extern struct cplb_entry dcplb_tbl[MAX_CPLBS]; +extern struct cplb_entry icplb_tbl[MAX_CPLBS]; +extern int first_switched_icplb; +extern int first_mask_dcplb; +extern int first_switched_dcplb; + +extern int nr_dcplb_miss, nr_icplb_miss, nr_icplb_supv_miss, nr_dcplb_prot; +extern int nr_cplb_flush; + +extern int page_mask_order; +extern int page_mask_nelts; + +extern unsigned long *current_rwx_mask; + +extern void flush_switched_cplbs(void); +extern void set_mask_dcplbs(unsigned long *); + +extern void __noreturn panic_cplb_error(int seqstat, struct pt_regs *); + +#endif /* __ASM_BFIN_CPLB_MPU_H */ diff --git a/include/asm-blackfin/cplb.h b/include/asm-blackfin/cplb.h index 06828d7..654375c 100644 --- a/include/asm-blackfin/cplb.h +++ b/include/asm-blackfin/cplb.h @@ -65,7 +65,11 @@ #define SIZE_1M 0x00100000 /* 1M */ #define SIZE_4M 0x00400000 /* 4M */ +#ifdef CONFIG_MPU +#define MAX_CPLBS 16 +#else #define MAX_CPLBS (16 * 2) +#endif #define ASYNC_MEMORY_CPLB_COVERAGE ((ASYNC_BANK0_SIZE + ASYNC_BANK1_SIZE + \ ASYNC_BANK2_SIZE + ASYNC_BANK3_SIZE) / SIZE_4M) diff --git a/include/asm-blackfin/cplbinit.h b/include/asm-blackfin/cplbinit.h index c4d0596..0eb1c1b 100644 --- a/include/asm-blackfin/cplbinit.h +++ b/include/asm-blackfin/cplbinit.h @@ -33,6 +33,12 @@ #include #include +#ifdef CONFIG_MPU + +#include + +#else + #define INITIAL_T 0x1 #define SWITCH_T 0x2 #define I_CPLB 0x4 @@ -79,6 +85,8 @@ extern u_long ipdt_swapcount_table[]; extern u_long dpdt_swapcount_table[]; #endif +#endif /* CONFIG_MPU */ + extern unsigned long reserved_mem_dcache_on; extern unsigned long reserved_mem_icache_on; diff --git a/include/asm-blackfin/mmu.h b/include/asm-blackfin/mmu.h index 11d52f1..757e439 100644 --- a/include/asm-blackfin/mmu.h +++ b/include/asm-blackfin/mmu.h @@ -24,7 +24,9 @@ typedef struct { unsigned long exec_fdpic_loadmap; unsigned long interp_fdpic_loadmap; #endif - +#ifdef CONFIG_MPU + unsigned long *page_rwx_mask; +#endif } mm_context_t; #endif diff --git a/include/asm-blackfin/mmu_context.h b/include/asm-blackfin/mmu_context.h index c5c71a6..b5eb675 100644 --- a/include/asm-blackfin/mmu_context.h +++ b/include/asm-blackfin/mmu_context.h @@ -30,9 +30,12 @@ #ifndef __BLACKFIN_MMU_CONTEXT_H__ #define __BLACKFIN_MMU_CONTEXT_H__ +#include +#include #include #include #include +#include extern void *current_l1_stack_save; extern int nr_l1stack_tasks; @@ -50,6 +53,12 @@ static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk) static inline int init_new_context(struct task_struct *tsk, struct mm_struct *mm) { +#ifdef CONFIG_MPU + unsigned long p = __get_free_pages(GFP_KERNEL, page_mask_order); + mm->context.page_rwx_mask = (unsigned long *)p; + memset(mm->context.page_rwx_mask, 0, + page_mask_nelts * 3 * sizeof(long)); +#endif return 0; } @@ -73,6 +82,11 @@ static inline void destroy_context(struct mm_struct *mm) sram_free(tmp->addr); kfree(tmp); } +#ifdef CONFIG_MPU + if (current_rwx_mask == mm->context.page_rwx_mask) + current_rwx_mask = NULL; + free_pages((unsigned long)mm->context.page_rwx_mask, page_mask_order); +#endif } static inline unsigned long @@ -106,9 +120,21 @@ activate_l1stack(struct mm_struct *mm, unsigned long sp_base) #define deactivate_mm(tsk,mm) do { } while (0) -static inline void activate_mm(struct mm_struct *prev_mm, - struct mm_struct *next_mm) +#define activate_mm(prev, next) switch_mm(prev, next, NULL) + +static inline void switch_mm(struct mm_struct *prev_mm, struct mm_struct *next_mm, + struct task_struct *tsk) { + if (prev_mm == next_mm) + return; +#ifdef CONFIG_MPU + if (prev_mm->context.page_rwx_mask == current_rwx_mask) { + flush_switched_cplbs(); + set_mask_dcplbs(next_mm->context.page_rwx_mask); + } +#endif + + /* L1 stack switching. */ if (!next_mm->context.l1_stack_save) return; if (next_mm->context.l1_stack_save == current_l1_stack_save) @@ -120,10 +146,36 @@ static inline void activate_mm(struct mm_struct *prev_mm, memcpy(l1_stack_base, current_l1_stack_save, l1_stack_len); } -static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next, - struct task_struct *tsk) +#ifdef CONFIG_MPU +static inline void protect_page(struct mm_struct *mm, unsigned long addr, + unsigned long flags) +{ + unsigned long *mask = mm->context.page_rwx_mask; + unsigned long page = addr >> 12; + unsigned long idx = page >> 5; + unsigned long bit = 1 << (page & 31); + + if (flags & VM_MAYREAD) + mask[idx] |= bit; + else + mask[idx] &= ~bit; + mask += page_mask_nelts; + if (flags & VM_MAYWRITE) + mask[idx] |= bit; + else + mask[idx] &= ~bit; + mask += page_mask_nelts; + if (flags & VM_MAYEXEC) + mask[idx] |= bit; + else + mask[idx] &= ~bit; +} + +static inline void update_protections(struct mm_struct *mm) { - activate_mm(prev, next); + flush_switched_cplbs(); + set_mask_dcplbs(mm->context.page_rwx_mask); } +#endif #endif -- cgit v0.10.2 From acbcd2631975cf6f0be5cd294cbfd12226cd9958 Mon Sep 17 00:00:00 2001 From: Michael Hennerich Date: Tue, 22 Jan 2008 18:36:20 +0800 Subject: [Blackfin] arch: Fix BUG gpio_direction_output API is not compatitable with GENERIC_GPIO API interface signef-off-by: Michael Hennerich Signed-off-by: Bryan Wu diff --git a/arch/blackfin/kernel/bfin_gpio.c b/arch/blackfin/kernel/bfin_gpio.c index ffee369..7312011 100644 --- a/arch/blackfin/kernel/bfin_gpio.c +++ b/arch/blackfin/kernel/bfin_gpio.c @@ -229,6 +229,11 @@ inline int check_gpio(unsigned short gpio) } #endif +void gpio_error(unsigned gpio) +{ + printk(KERN_ERR "bfin-gpio: GPIO %d wasn't requested!\n", gpio); +} + static void set_label(unsigned short ident, const char *label) { @@ -1034,7 +1039,7 @@ EXPORT_SYMBOL(peripheral_free_list); * MODIFICATION HISTORY : **************************************************************/ -int gpio_request(unsigned short gpio, const char *label) +int gpio_request(unsigned gpio, const char *label) { unsigned long flags; @@ -1081,7 +1086,7 @@ int gpio_request(unsigned short gpio, const char *label) } EXPORT_SYMBOL(gpio_request); -void gpio_free(unsigned short gpio) +void gpio_free(unsigned gpio) { unsigned long flags; @@ -1091,7 +1096,7 @@ void gpio_free(unsigned short gpio) local_irq_save(flags); if (unlikely(!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio)))) { - printk(KERN_ERR "bfin-gpio: GPIO %d wasn't reserved!\n", gpio); + gpio_error(gpio); dump_stack(); local_irq_restore(flags); return; @@ -1107,34 +1112,47 @@ void gpio_free(unsigned short gpio) } EXPORT_SYMBOL(gpio_free); + #ifdef BF548_FAMILY -void gpio_direction_input(unsigned short gpio) +int gpio_direction_input(unsigned gpio) { unsigned long flags; - BUG_ON(!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio))); + if (!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio))) { + gpio_error(gpio); + return -EINVAL; + } + local_irq_save(flags); gpio_array[gpio_bank(gpio)]->port_dir_clear = gpio_bit(gpio); gpio_array[gpio_bank(gpio)]->port_inen |= gpio_bit(gpio); local_irq_restore(flags); + + return 0; } EXPORT_SYMBOL(gpio_direction_input); -void gpio_direction_output(unsigned short gpio) +int gpio_direction_output(unsigned gpio, int value) { unsigned long flags; - BUG_ON(!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio))); + if (!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio))) { + gpio_error(gpio); + return -EINVAL; + } local_irq_save(flags); gpio_array[gpio_bank(gpio)]->port_inen &= ~gpio_bit(gpio); + gpio_set_value(gpio, value); gpio_array[gpio_bank(gpio)]->port_dir_set = gpio_bit(gpio); local_irq_restore(flags); + + return 0; } EXPORT_SYMBOL(gpio_direction_output); -void gpio_set_value(unsigned short gpio, unsigned short arg) +void gpio_set_value(unsigned gpio, int arg) { if (arg) gpio_array[gpio_bank(gpio)]->port_set = gpio_bit(gpio); @@ -1144,7 +1162,7 @@ void gpio_set_value(unsigned short gpio, unsigned short arg) } EXPORT_SYMBOL(gpio_set_value); -unsigned short gpio_get_value(unsigned short gpio) +int gpio_get_value(unsigned gpio) { return (1 & (gpio_array[gpio_bank(gpio)]->port_data >> gpio_sub_n(gpio))); } @@ -1152,31 +1170,42 @@ EXPORT_SYMBOL(gpio_get_value); #else -void gpio_direction_input(unsigned short gpio) +int gpio_direction_input(unsigned gpio) { unsigned long flags; - BUG_ON(!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio))); + if (!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio))) { + gpio_error(gpio); + return -EINVAL; + } local_irq_save(flags); gpio_bankb[gpio_bank(gpio)]->dir &= ~gpio_bit(gpio); gpio_bankb[gpio_bank(gpio)]->inen |= gpio_bit(gpio); AWA_DUMMY_READ(inen); local_irq_restore(flags); + + return 0; } EXPORT_SYMBOL(gpio_direction_input); -void gpio_direction_output(unsigned short gpio) +int gpio_direction_output(unsigned gpio, int value) { unsigned long flags; - BUG_ON(!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio))); + if (!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio))) { + gpio_error(gpio); + return -EINVAL; + } local_irq_save(flags); gpio_bankb[gpio_bank(gpio)]->inen &= ~gpio_bit(gpio); + gpio_set_value(gpio, value); gpio_bankb[gpio_bank(gpio)]->dir |= gpio_bit(gpio); AWA_DUMMY_READ(dir); local_irq_restore(flags); + + return 0; } EXPORT_SYMBOL(gpio_direction_output); diff --git a/arch/blackfin/mach-bf527/boards/ezkit.c b/arch/blackfin/mach-bf527/boards/ezkit.c index bc25681..6d70aae 100644 --- a/arch/blackfin/mach-bf527/boards/ezkit.c +++ b/arch/blackfin/mach-bf527/boards/ezkit.c @@ -317,12 +317,7 @@ static struct resource sl811_hcd_resources[] = { void sl811_port_power(struct device *dev, int is_on) { gpio_request(CONFIG_USB_SL811_BFIN_GPIO_VBUS, "usb:SL811_VBUS"); - gpio_direction_output(CONFIG_USB_SL811_BFIN_GPIO_VBUS); - - if (is_on) - gpio_set_value(CONFIG_USB_SL811_BFIN_GPIO_VBUS, 1); - else - gpio_set_value(CONFIG_USB_SL811_BFIN_GPIO_VBUS, 0); + gpio_direction_output(CONFIG_USB_SL811_BFIN_GPIO_VBUS, is_on); } #endif diff --git a/arch/blackfin/mach-bf537/boards/generic_board.c b/arch/blackfin/mach-bf537/boards/generic_board.c index 1c97219a..3225b15 100644 --- a/arch/blackfin/mach-bf537/boards/generic_board.c +++ b/arch/blackfin/mach-bf537/boards/generic_board.c @@ -205,12 +205,8 @@ static struct resource sl811_hcd_resources[] = { void sl811_port_power(struct device *dev, int is_on) { gpio_request(CONFIG_USB_SL811_BFIN_GPIO_VBUS, "usb:SL811_VBUS"); - gpio_direction_output(CONFIG_USB_SL811_BFIN_GPIO_VBUS); + gpio_direction_output(CONFIG_USB_SL811_BFIN_GPIO_VBUS, is_on); - if (is_on) - gpio_set_value(CONFIG_USB_SL811_BFIN_GPIO_VBUS, 1); - else - gpio_set_value(CONFIG_USB_SL811_BFIN_GPIO_VBUS, 0); } #endif diff --git a/arch/blackfin/mach-bf537/boards/pnav10.c b/arch/blackfin/mach-bf537/boards/pnav10.c index 23e10c7..4c48705 100644 --- a/arch/blackfin/mach-bf537/boards/pnav10.c +++ b/arch/blackfin/mach-bf537/boards/pnav10.c @@ -134,12 +134,8 @@ static struct resource sl811_hcd_resources[] = { void sl811_port_power(struct device *dev, int is_on) { gpio_request(CONFIG_USB_SL811_BFIN_GPIO_VBUS, "usb:SL811_VBUS"); - gpio_direction_output(CONFIG_USB_SL811_BFIN_GPIO_VBUS); + gpio_direction_output(CONFIG_USB_SL811_BFIN_GPIO_VBUS, is_on); - if (is_on) - gpio_set_value(CONFIG_USB_SL811_BFIN_GPIO_VBUS, 1); - else - gpio_set_value(CONFIG_USB_SL811_BFIN_GPIO_VBUS, 0); } #endif diff --git a/arch/blackfin/mach-bf537/boards/stamp.c b/arch/blackfin/mach-bf537/boards/stamp.c index 3e0ad04..37759ac 100644 --- a/arch/blackfin/mach-bf537/boards/stamp.c +++ b/arch/blackfin/mach-bf537/boards/stamp.c @@ -250,12 +250,7 @@ static struct resource sl811_hcd_resources[] = { void sl811_port_power(struct device *dev, int is_on) { gpio_request(CONFIG_USB_SL811_BFIN_GPIO_VBUS, "usb:SL811_VBUS"); - gpio_direction_output(CONFIG_USB_SL811_BFIN_GPIO_VBUS); - - if (is_on) - gpio_set_value(CONFIG_USB_SL811_BFIN_GPIO_VBUS, 1); - else - gpio_set_value(CONFIG_USB_SL811_BFIN_GPIO_VBUS, 0); + gpio_direction_output(CONFIG_USB_SL811_BFIN_GPIO_VBUS, is_on); } #endif diff --git a/drivers/video/bf54x-lq043fb.c b/drivers/video/bf54x-lq043fb.c index 1b7e54de..c8e7427 100644 --- a/drivers/video/bf54x-lq043fb.c +++ b/drivers/video/bf54x-lq043fb.c @@ -264,8 +264,7 @@ static int request_ports(struct bfin_bf54xfb_info *fbi) } } - gpio_direction_output(disp); - gpio_set_value(disp, 1); + gpio_direction_output(disp, 1); return 0; } diff --git a/include/asm-blackfin/gpio.h b/include/asm-blackfin/gpio.h index 33ce98e..7bba9b1 100644 --- a/include/asm-blackfin/gpio.h +++ b/include/asm-blackfin/gpio.h @@ -426,19 +426,19 @@ struct gpio_port_s { * MODIFICATION HISTORY : **************************************************************/ -int gpio_request(unsigned short, const char *); -void gpio_free(unsigned short); +int gpio_request(unsigned, const char *); +void gpio_free(unsigned); -void gpio_set_value(unsigned short gpio, unsigned short arg); -unsigned short gpio_get_value(unsigned short gpio); +void gpio_set_value(unsigned gpio, int arg); +int gpio_get_value(unsigned gpio); #ifndef BF548_FAMILY #define gpio_get_value(gpio) get_gpio_data(gpio) #define gpio_set_value(gpio, value) set_gpio_data(gpio, value) #endif -void gpio_direction_input(unsigned short gpio); -void gpio_direction_output(unsigned short gpio); +int gpio_direction_input(unsigned gpio); +int gpio_direction_output(unsigned gpio, int value); #include /* cansleep wrappers */ #include diff --git a/include/asm-blackfin/mach-bf527/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf527/bfin_serial_5xx.h index 0b867e6..15dbc21 100644 --- a/include/asm-blackfin/mach-bf527/bfin_serial_5xx.h +++ b/include/asm-blackfin/mach-bf527/bfin_serial_5xx.h @@ -146,7 +146,7 @@ static void bfin_serial_hw_init(struct bfin_serial_port *uart) if (uart->rts_pin >= 0) { gpio_request(uart->rts_pin, DRIVER_NAME); - gpio_direction_output(uart->rts_pin); + gpio_direction_output(uart->rts_pin, 0); } #endif } diff --git a/include/asm-blackfin/mach-bf533/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf533/bfin_serial_5xx.h index 69b9f8e..7871d43 100644 --- a/include/asm-blackfin/mach-bf533/bfin_serial_5xx.h +++ b/include/asm-blackfin/mach-bf533/bfin_serial_5xx.h @@ -111,7 +111,7 @@ static void bfin_serial_hw_init(struct bfin_serial_port *uart) } if (uart->rts_pin >= 0) { gpio_request(uart->rts_pin, DRIVER_NAME); - gpio_direction_input(uart->rts_pin); + gpio_direction_input(uart->rts_pin, 0); } #endif } diff --git a/include/asm-blackfin/mach-bf537/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf537/bfin_serial_5xx.h index 6fb328f..86e45c3 100644 --- a/include/asm-blackfin/mach-bf537/bfin_serial_5xx.h +++ b/include/asm-blackfin/mach-bf537/bfin_serial_5xx.h @@ -146,7 +146,7 @@ static void bfin_serial_hw_init(struct bfin_serial_port *uart) if (uart->rts_pin >= 0) { gpio_request(uart->rts_pin, DRIVER_NAME); - gpio_direction_output(uart->rts_pin); + gpio_direction_output(uart->rts_pin, 0); } #endif } diff --git a/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h index f21a162..3770aa3 100644 --- a/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h +++ b/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h @@ -186,7 +186,7 @@ static void bfin_serial_hw_init(struct bfin_serial_port *uart) if (uart->rts_pin >= 0) { gpio_request(uart->rts_pin, DRIVER_NAME); - gpio_direction_output(uart->rts_pin); + gpio_direction_output(uart->rts_pin, 0); } #endif } diff --git a/include/asm-blackfin/mach-bf561/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf561/bfin_serial_5xx.h index 69b9f8e..7871d43 100644 --- a/include/asm-blackfin/mach-bf561/bfin_serial_5xx.h +++ b/include/asm-blackfin/mach-bf561/bfin_serial_5xx.h @@ -111,7 +111,7 @@ static void bfin_serial_hw_init(struct bfin_serial_port *uart) } if (uart->rts_pin >= 0) { gpio_request(uart->rts_pin, DRIVER_NAME); - gpio_direction_input(uart->rts_pin); + gpio_direction_input(uart->rts_pin, 0); } #endif } -- cgit v0.10.2 From a2c8cfef6abb33ee49d80c58391ebfc4f94221ef Mon Sep 17 00:00:00 2001 From: Michael Hennerich Date: Tue, 22 Jan 2008 17:20:10 +0800 Subject: [Blackfin] arch: GPIO API cleanup and anomaly update - Add anomaly workaround for bfin_gpio_reset_spi0_ssel1 - Fix style - Update copyright - Remove BUG_ON checks for functions intended to be used only by arch support. GPIO users should only access using the generic GPIO API - Make all GPIO identifier unsigned int Signed-off-by: Michael Hennerich Signed-off-by: Bryan Wu diff --git a/arch/blackfin/kernel/bfin_gpio.c b/arch/blackfin/kernel/bfin_gpio.c index 7312011..6bbe0a2 100644 --- a/arch/blackfin/kernel/bfin_gpio.c +++ b/arch/blackfin/kernel/bfin_gpio.c @@ -7,7 +7,7 @@ * Description: GPIO Abstraction Layer * * Modified: - * Copyright 2007 Analog Devices Inc. + * Copyright 2008 Analog Devices Inc. * * Bugs: Enter bugs at http://blackfin.uclinux.org/ * @@ -137,7 +137,6 @@ static unsigned short *port_fer[gpio_bank(MAX_BLACKFIN_GPIOS)] = { (unsigned short *) PORTG_FER, (unsigned short *) PORTH_FER, }; - #endif #ifdef BF527_FAMILY @@ -211,7 +210,7 @@ static unsigned int sic_iwr_irqs[gpio_bank(MAX_BLACKFIN_GPIOS)] = {IRQ_PROG0_INT #endif /* CONFIG_PM */ #if defined(BF548_FAMILY) -inline int check_gpio(unsigned short gpio) +inline int check_gpio(unsigned gpio) { if (gpio == GPIO_PB15 || gpio == GPIO_PC14 || gpio == GPIO_PC15 || gpio == GPIO_PH14 || gpio == GPIO_PH15 @@ -221,7 +220,7 @@ inline int check_gpio(unsigned short gpio) return 0; } #else -inline int check_gpio(unsigned short gpio) +inline int check_gpio(unsigned gpio) { if (gpio >= MAX_BLACKFIN_GPIOS) return -EINVAL; @@ -236,7 +235,6 @@ void gpio_error(unsigned gpio) static void set_label(unsigned short ident, const char *label) { - if (label && str_ident) { strncpy(str_ident[ident].name, label, RESOURCE_LABEL_SIZE); @@ -267,7 +265,7 @@ static int cmp_label(unsigned short ident, const char *label) } #if defined(BF527_FAMILY) || defined(BF537_FAMILY) -static void port_setup(unsigned short gpio, unsigned short usage) +static void port_setup(unsigned gpio, unsigned short usage) { if (!check_gpio(gpio)) { if (usage == GPIO_USAGE) @@ -278,7 +276,7 @@ static void port_setup(unsigned short gpio, unsigned short usage) } } #elif defined(BF548_FAMILY) -static void port_setup(unsigned short gpio, unsigned short usage) +static void port_setup(unsigned gpio, unsigned short usage) { if (usage == GPIO_USAGE) gpio_array[gpio_bank(gpio)]->port_fer &= ~gpio_bit(gpio); @@ -399,7 +397,7 @@ inline void portmux_setup(unsigned short portno, unsigned short function) #endif #ifndef BF548_FAMILY -static void default_gpio(unsigned short gpio) +static void default_gpio(unsigned gpio) { unsigned short bank, bitmask; unsigned long flags; @@ -419,7 +417,6 @@ static void default_gpio(unsigned short gpio) gpio_bankb[bank]->edge &= ~bitmask; AWA_DUMMY_READ(edge); local_irq_restore(flags); - } #else # define default_gpio(...) do { } while (0) @@ -457,10 +454,9 @@ arch_initcall(bfin_gpio_init); /* Set a specific bit */ #define SET_GPIO(name) \ -void set_gpio_ ## name(unsigned short gpio, unsigned short arg) \ +void set_gpio_ ## name(unsigned gpio, unsigned short arg) \ { \ unsigned long flags; \ - BUG_ON(!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio))); \ local_irq_save(flags); \ if (arg) \ gpio_bankb[gpio_bank(gpio)]->name |= gpio_bit(gpio); \ @@ -480,10 +476,9 @@ SET_GPIO(both) #if ANOMALY_05000311 || ANOMALY_05000323 #define SET_GPIO_SC(name) \ -void set_gpio_ ## name(unsigned short gpio, unsigned short arg) \ +void set_gpio_ ## name(unsigned gpio, unsigned short arg) \ { \ unsigned long flags; \ - BUG_ON(!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio))); \ local_irq_save(flags); \ if (arg) \ gpio_bankb[gpio_bank(gpio)]->name ## _set = gpio_bit(gpio); \ @@ -495,9 +490,8 @@ void set_gpio_ ## name(unsigned short gpio, unsigned short arg) \ EXPORT_SYMBOL(set_gpio_ ## name); #else #define SET_GPIO_SC(name) \ -void set_gpio_ ## name(unsigned short gpio, unsigned short arg) \ +void set_gpio_ ## name(unsigned gpio, unsigned short arg) \ { \ - BUG_ON(!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio))); \ if (arg) \ gpio_bankb[gpio_bank(gpio)]->name ## _set = gpio_bit(gpio); \ else \ @@ -511,19 +505,17 @@ SET_GPIO_SC(maskb) SET_GPIO_SC(data) #if ANOMALY_05000311 || ANOMALY_05000323 -void set_gpio_toggle(unsigned short gpio) +void set_gpio_toggle(unsigned gpio) { unsigned long flags; - BUG_ON(!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio))); local_irq_save(flags); gpio_bankb[gpio_bank(gpio)]->toggle = gpio_bit(gpio); AWA_DUMMY_READ(toggle); local_irq_restore(flags); } #else -void set_gpio_toggle(unsigned short gpio) +void set_gpio_toggle(unsigned gpio) { - BUG_ON(!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio))); gpio_bankb[gpio_bank(gpio)]->toggle = gpio_bit(gpio); } #endif @@ -534,7 +526,7 @@ EXPORT_SYMBOL(set_gpio_toggle); #if ANOMALY_05000311 || ANOMALY_05000323 #define SET_GPIO_P(name) \ -void set_gpiop_ ## name(unsigned short gpio, unsigned short arg) \ +void set_gpiop_ ## name(unsigned gpio, unsigned short arg) \ { \ unsigned long flags; \ local_irq_save(flags); \ @@ -545,7 +537,7 @@ void set_gpiop_ ## name(unsigned short gpio, unsigned short arg) \ EXPORT_SYMBOL(set_gpiop_ ## name); #else #define SET_GPIO_P(name) \ -void set_gpiop_ ## name(unsigned short gpio, unsigned short arg) \ +void set_gpiop_ ## name(unsigned gpio, unsigned short arg) \ { \ gpio_bankb[gpio_bank(gpio)]->name = arg; \ } \ @@ -561,11 +553,10 @@ SET_GPIO_P(both) SET_GPIO_P(maska) SET_GPIO_P(maskb) - /* Get a specific bit */ #if ANOMALY_05000311 || ANOMALY_05000323 #define GET_GPIO(name) \ -unsigned short get_gpio_ ## name(unsigned short gpio) \ +unsigned short get_gpio_ ## name(unsigned gpio) \ { \ unsigned long flags; \ unsigned short ret; \ @@ -578,7 +569,7 @@ unsigned short get_gpio_ ## name(unsigned short gpio) \ EXPORT_SYMBOL(get_gpio_ ## name); #else #define GET_GPIO(name) \ -unsigned short get_gpio_ ## name(unsigned short gpio) \ +unsigned short get_gpio_ ## name(unsigned gpio) \ { \ return (0x01 & (gpio_bankb[gpio_bank(gpio)]->name >> gpio_sub_n(gpio))); \ } \ @@ -598,7 +589,7 @@ GET_GPIO(maskb) #if ANOMALY_05000311 || ANOMALY_05000323 #define GET_GPIO_P(name) \ -unsigned short get_gpiop_ ## name(unsigned short gpio) \ +unsigned short get_gpiop_ ## name(unsigned gpio) \ { \ unsigned long flags; \ unsigned short ret; \ @@ -611,7 +602,7 @@ unsigned short get_gpiop_ ## name(unsigned short gpio) \ EXPORT_SYMBOL(get_gpiop_ ## name); #else #define GET_GPIO_P(name) \ -unsigned short get_gpiop_ ## name(unsigned short gpio) \ +unsigned short get_gpiop_ ## name(unsigned gpio) \ { \ return (gpio_bankb[gpio_bank(gpio)]->name);\ } \ @@ -648,7 +639,7 @@ GET_GPIO_P(maskb) ************************************************************* * MODIFICATION HISTORY : **************************************************************/ -int gpio_pm_wakeup_request(unsigned short gpio, unsigned char type) +int gpio_pm_wakeup_request(unsigned gpio, unsigned char type) { unsigned long flags; @@ -656,7 +647,6 @@ int gpio_pm_wakeup_request(unsigned short gpio, unsigned char type) return -EINVAL; local_irq_save(flags); - wakeup_map[gpio_bank(gpio)] |= gpio_bit(gpio); wakeup_flags_map[gpio] = type; local_irq_restore(flags); @@ -665,7 +655,7 @@ int gpio_pm_wakeup_request(unsigned short gpio, unsigned char type) } EXPORT_SYMBOL(gpio_pm_wakeup_request); -void gpio_pm_wakeup_free(unsigned short gpio) +void gpio_pm_wakeup_free(unsigned gpio) { unsigned long flags; @@ -680,7 +670,7 @@ void gpio_pm_wakeup_free(unsigned short gpio) } EXPORT_SYMBOL(gpio_pm_wakeup_free); -static int bfin_gpio_wakeup_type(unsigned short gpio, unsigned char type) +static int bfin_gpio_wakeup_type(unsigned gpio, unsigned char type) { port_setup(gpio, GPIO_USAGE); set_gpio_dir(gpio, 0); @@ -789,7 +779,7 @@ void gpio_pm_restore(void) #endif #else /* BF548_FAMILY */ -unsigned short get_gpio_dir(unsigned short gpio) +unsigned short get_gpio_dir(unsigned gpio) { return (0x01 & (gpio_array[gpio_bank(gpio)]->port_dir_clear >> gpio_sub_n(gpio))); } @@ -1123,7 +1113,6 @@ int gpio_direction_input(unsigned gpio) return -EINVAL; } - local_irq_save(flags); gpio_array[gpio_bank(gpio)]->port_dir_clear = gpio_bit(gpio); gpio_array[gpio_bank(gpio)]->port_inen |= gpio_bit(gpio); @@ -1158,7 +1147,6 @@ void gpio_set_value(unsigned gpio, int arg) gpio_array[gpio_bank(gpio)]->port_set = gpio_bit(gpio); else gpio_array[gpio_bank(gpio)]->port_clear = gpio_bit(gpio); - } EXPORT_SYMBOL(gpio_set_value); @@ -1200,7 +1188,12 @@ int gpio_direction_output(unsigned gpio, int value) local_irq_save(flags); gpio_bankb[gpio_bank(gpio)]->inen &= ~gpio_bit(gpio); - gpio_set_value(gpio, value); + + if (value) + gpio_bankb[gpio_bank(gpio)]->data_set = gpio_bit(gpio); + else + gpio_bankb[gpio_bank(gpio)]->data_clear = gpio_bit(gpio); + gpio_bankb[gpio_bank(gpio)]->dir |= gpio_bit(gpio); AWA_DUMMY_READ(dir); local_irq_restore(flags); @@ -1225,6 +1218,7 @@ void bfin_gpio_reset_spi0_ssel1(void) port_setup(gpio, GPIO_USAGE); gpio_bankb[gpio_bank(gpio)]->data_set = gpio_bit(gpio); + AWA_DUMMY_READ(data_set); udelay(1); } @@ -1259,6 +1253,5 @@ static __init int gpio_register_proc(void) proc_gpio->read_proc = gpio_proc_read; return proc_gpio != NULL; } - __initcall(gpio_register_proc); #endif diff --git a/include/asm-blackfin/gpio.h b/include/asm-blackfin/gpio.h index 7bba9b1..d0426c1 100644 --- a/include/asm-blackfin/gpio.h +++ b/include/asm-blackfin/gpio.h @@ -7,7 +7,7 @@ * Description: * * Modified: - * Copyright 2004-2006 Analog Devices Inc. + * Copyright 2004-2008 Analog Devices Inc. * * Bugs: Enter bugs at http://blackfin.uclinux.org/ * @@ -304,39 +304,39 @@ **************************************************************/ #ifndef BF548_FAMILY -void set_gpio_dir(unsigned short, unsigned short); -void set_gpio_inen(unsigned short, unsigned short); -void set_gpio_polar(unsigned short, unsigned short); -void set_gpio_edge(unsigned short, unsigned short); -void set_gpio_both(unsigned short, unsigned short); -void set_gpio_data(unsigned short, unsigned short); -void set_gpio_maska(unsigned short, unsigned short); -void set_gpio_maskb(unsigned short, unsigned short); -void set_gpio_toggle(unsigned short); -void set_gpiop_dir(unsigned short, unsigned short); -void set_gpiop_inen(unsigned short, unsigned short); -void set_gpiop_polar(unsigned short, unsigned short); -void set_gpiop_edge(unsigned short, unsigned short); -void set_gpiop_both(unsigned short, unsigned short); -void set_gpiop_data(unsigned short, unsigned short); -void set_gpiop_maska(unsigned short, unsigned short); -void set_gpiop_maskb(unsigned short, unsigned short); -unsigned short get_gpio_dir(unsigned short); -unsigned short get_gpio_inen(unsigned short); -unsigned short get_gpio_polar(unsigned short); -unsigned short get_gpio_edge(unsigned short); -unsigned short get_gpio_both(unsigned short); -unsigned short get_gpio_maska(unsigned short); -unsigned short get_gpio_maskb(unsigned short); -unsigned short get_gpio_data(unsigned short); -unsigned short get_gpiop_dir(unsigned short); -unsigned short get_gpiop_inen(unsigned short); -unsigned short get_gpiop_polar(unsigned short); -unsigned short get_gpiop_edge(unsigned short); -unsigned short get_gpiop_both(unsigned short); -unsigned short get_gpiop_maska(unsigned short); -unsigned short get_gpiop_maskb(unsigned short); -unsigned short get_gpiop_data(unsigned short); +void set_gpio_dir(unsigned, unsigned short); +void set_gpio_inen(unsigned, unsigned short); +void set_gpio_polar(unsigned, unsigned short); +void set_gpio_edge(unsigned, unsigned short); +void set_gpio_both(unsigned, unsigned short); +void set_gpio_data(unsigned, unsigned short); +void set_gpio_maska(unsigned, unsigned short); +void set_gpio_maskb(unsigned, unsigned short); +void set_gpio_toggle(unsigned); +void set_gpiop_dir(unsigned, unsigned short); +void set_gpiop_inen(unsigned, unsigned short); +void set_gpiop_polar(unsigned, unsigned short); +void set_gpiop_edge(unsigned, unsigned short); +void set_gpiop_both(unsigned, unsigned short); +void set_gpiop_data(unsigned, unsigned short); +void set_gpiop_maska(unsigned, unsigned short); +void set_gpiop_maskb(unsigned, unsigned short); +unsigned short get_gpio_dir(unsigned); +unsigned short get_gpio_inen(unsigned); +unsigned short get_gpio_polar(unsigned); +unsigned short get_gpio_edge(unsigned); +unsigned short get_gpio_both(unsigned); +unsigned short get_gpio_maska(unsigned); +unsigned short get_gpio_maskb(unsigned); +unsigned short get_gpio_data(unsigned); +unsigned short get_gpiop_dir(unsigned); +unsigned short get_gpiop_inen(unsigned); +unsigned short get_gpiop_polar(unsigned); +unsigned short get_gpiop_edge(unsigned); +unsigned short get_gpiop_both(unsigned); +unsigned short get_gpiop_maska(unsigned); +unsigned short get_gpiop_maskb(unsigned); +unsigned short get_gpiop_data(unsigned); struct gpio_port_t { unsigned short data; @@ -382,8 +382,8 @@ struct gpio_port_t { #define PM_WAKE_LOW 0x8 #define PM_WAKE_BOTH_EDGES (PM_WAKE_RISING | PM_WAKE_FALLING) -int gpio_pm_wakeup_request(unsigned short gpio, unsigned char type); -void gpio_pm_wakeup_free(unsigned short gpio); +int gpio_pm_wakeup_request(unsigned gpio, unsigned char type); +void gpio_pm_wakeup_free(unsigned gpio); unsigned int gpio_pm_setup(void); void gpio_pm_restore(void); -- cgit v0.10.2 From a628a8bcd8a6daea6096fe781fc36cae4ac1ed48 Mon Sep 17 00:00:00 2001 From: Michael Hennerich Date: Tue, 22 Jan 2008 17:29:16 +0800 Subject: [Blackfin] arch: Update copyright date Signed-off-by: Michael Hennerich Signed-off-by: Bryan Wu diff --git a/arch/blackfin/mach-bf527/boards/ezkit.c b/arch/blackfin/mach-bf527/boards/ezkit.c index 6d70aae..f8c411a 100644 --- a/arch/blackfin/mach-bf527/boards/ezkit.c +++ b/arch/blackfin/mach-bf527/boards/ezkit.c @@ -8,7 +8,7 @@ * * Modified: * Copyright 2005 National ICT Australia (NICTA) - * Copyright 2004-2007 Analog Devices Inc. + * Copyright 2004-2008 Analog Devices Inc. * * Bugs: Enter bugs at http://blackfin.uclinux.org/ * diff --git a/arch/blackfin/mach-bf537/boards/generic_board.c b/arch/blackfin/mach-bf537/boards/generic_board.c index 3225b15..3e52f3f 100644 --- a/arch/blackfin/mach-bf537/boards/generic_board.c +++ b/arch/blackfin/mach-bf537/boards/generic_board.c @@ -8,7 +8,7 @@ * * Modified: * Copyright 2005 National ICT Australia (NICTA) - * Copyright 2004-2007 Analog Devices Inc. + * Copyright 2004-2008 Analog Devices Inc. * * Bugs: Enter bugs at http://blackfin.uclinux.org/ * diff --git a/arch/blackfin/mach-bf537/boards/pnav10.c b/arch/blackfin/mach-bf537/boards/pnav10.c index 4c48705..509a8a2 100644 --- a/arch/blackfin/mach-bf537/boards/pnav10.c +++ b/arch/blackfin/mach-bf537/boards/pnav10.c @@ -8,7 +8,7 @@ * * Modified: * Copyright 2005 National ICT Australia (NICTA) - * Copyright 2004-2006 Analog Devices Inc. + * Copyright 2004-2008 Analog Devices Inc. * * Bugs: Enter bugs at http://blackfin.uclinux.org/ * -- cgit v0.10.2 From 444ad82bc3eaa554be40d22dc248e58aeefd54d9 Mon Sep 17 00:00:00 2001 From: Michael Hennerich Date: Tue, 22 Jan 2008 18:38:02 +0800 Subject: [Blackfin] arch: Add proper SW System Reset delay sequence Signed-off-by: Michael Hennerich Signed-off-by: Bryan Wu diff --git a/arch/blackfin/kernel/reboot.c b/arch/blackfin/kernel/reboot.c index 06501a5..483f93d 100644 --- a/arch/blackfin/kernel/reboot.c +++ b/arch/blackfin/kernel/reboot.c @@ -19,6 +19,11 @@ #define SYSCR_VAL 0x10 #endif +/* + * Delay min 5 SCLK cycles using worst case CCLK/SCLK ratio (15) + */ +#define SWRST_DELAY (5 * 15) + /* A system soft reset makes external memory unusable * so force this function into L1. */ @@ -34,11 +39,15 @@ void bfin_reset(void) while (1) { /* initiate system soft reset with magic 0x7 */ bfin_write_SWRST(0x7); - bfin_read_SWRST(); - asm("ssync;"); + + /* Wait for System reset to actually reset, needs to be 5 SCLKs, */ + /* Assume CCLK / SCLK ratio is worst case (15), and use 5*15 */ + + asm("LSETUP(.Lfoo,.Lfoo) LC0 = %0\n .Lfoo: NOP;\n" + : : "a" (SWRST_DELAY) : "LC0", "LT0", "LB0"); + /* clear system soft reset */ bfin_write_SWRST(0); - bfin_read_SWRST(); asm("ssync;"); /* issue core reset */ asm("raise 1"); -- cgit v0.10.2 From 03c5732855300f05aac718ca770c2bb05e1fd48b Mon Sep 17 00:00:00 2001 From: Sonic Zhang Date: Tue, 22 Jan 2008 18:45:10 +0800 Subject: [Blackfin] arch: Fix bug Only RTC interrupt can wake up deeper sleep core. Signed-off-by: Sonic Zhang Signed-off-by: Bryan Wu diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig index 6b96d7d..ecb356e 100644 --- a/arch/blackfin/Kconfig +++ b/arch/blackfin/Kconfig @@ -923,10 +923,10 @@ endchoice config PM_WAKEUP_SIC_IWR hex "Wakeup Events (SIC_IWR)" depends on PM_WAKEUP_GPIO_BY_SIC_IWR - default 0x80000000 if (BF537 || BF536 || BF534) - default 0x100000 if (BF533 || BF532 || BF531) - default 0x800000 if (BF54x) - default 0x800000 if (BF52x) + default 0x8 if (BF537 || BF536 || BF534) + default 0x80 if (BF533 || BF532 || BF531) + default 0x80 if (BF54x) + default 0x80 if (BF52x) config PM_WAKEUP_GPIO_NUMBER int "Wakeup GPIO number" -- cgit v0.10.2 From 96a5c6f9bef027e1187b2f168bb3e08ef21d0b6f Mon Sep 17 00:00:00 2001 From: Michael Hennerich Date: Tue, 22 Jan 2008 19:23:50 +0800 Subject: [Blackfin] arch: Fix bug - kernel build with Debug option enabled fails to boot up writes to I/DMEM_CONTROL must be followed by SSYNC Signed-off-by: Michael Hennerich Signed-off-by: Bryan Wu diff --git a/arch/blackfin/kernel/cplb-nompu/cacheinit.c b/arch/blackfin/kernel/cplb-nompu/cacheinit.c index 62cbba7..8a18399 100644 --- a/arch/blackfin/kernel/cplb-nompu/cacheinit.c +++ b/arch/blackfin/kernel/cplb-nompu/cacheinit.c @@ -42,6 +42,7 @@ void bfin_icache_init(void) ctrl = bfin_read_IMEM_CONTROL(); ctrl |= IMC | ENICPLB; bfin_write_IMEM_CONTROL(ctrl); + SSYNC(); } #endif @@ -63,5 +64,6 @@ void bfin_dcache_init(void) ctrl = bfin_read_DMEM_CONTROL(); ctrl |= DMEM_CNTR; bfin_write_DMEM_CONTROL(ctrl); + SSYNC(); } #endif -- cgit v0.10.2 From de8c43f2fca9bb06f3ee87b38a61d5d9966ce221 Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Thu, 24 Jan 2008 17:14:04 +0800 Subject: [Blackfin] arch: use common flash driver to setup partitions rather than the bf5xx-flash driver Signed-off-by: Mike Frysinger Signed-off-by: Bryan Wu diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig index ecb356e..fc7ca86 100644 --- a/arch/blackfin/Kconfig +++ b/arch/blackfin/Kconfig @@ -268,11 +268,6 @@ config MEM_MT48LC32M16A2TG_75 depends on (BFIN527_EZKIT) default y -config BFIN_SHARED_FLASH_ENET - bool - depends on (BFIN533_STAMP) - default y - source "arch/blackfin/mach-bf527/Kconfig" source "arch/blackfin/mach-bf533/Kconfig" source "arch/blackfin/mach-bf561/Kconfig" diff --git a/arch/blackfin/mach-bf533/boards/stamp.c b/arch/blackfin/mach-bf533/boards/stamp.c index cd87df7..ac52b04 100644 --- a/arch/blackfin/mach-bf533/boards/stamp.c +++ b/arch/blackfin/mach-bf533/boards/stamp.c @@ -32,6 +32,7 @@ #include #include #include +#include #include #include #if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE) @@ -108,6 +109,50 @@ static struct platform_device net2272_bfin_device = { }; #endif +static struct mtd_partition stamp_partitions[] = { + { + .name = "Bootloader", + .size = 0x20000, + .offset = 0, + }, { + .name = "Kernel", + .size = 0xE0000, + .offset = MTDPART_OFS_APPEND, + }, { + .name = "RootFS", + .size = MTDPART_SIZ_FULL, + .offset = MTDPART_OFS_APPEND, + } +}; + +static struct physmap_flash_data stamp_flash_data = { + .width = 2, + .parts = stamp_partitions, + .nr_parts = ARRAY_SIZE(stamp_partitions), +}; + +static struct resource stamp_flash_resource[] = { + { + .name = "cfi_probe", + .start = 0x20000000, + .end = 0x203fffff, + .flags = IORESOURCE_MEM, + }, { + .start = CONFIG_ENET_FLASH_PIN, + .flags = IORESOURCE_IRQ, + } +}; + +static struct platform_device stamp_flash_device = { + .name = "BF5xx-Flash", + .id = 0, + .dev = { + .platform_data = &stamp_flash_data, + }, + .num_resources = ARRAY_SIZE(stamp_flash_resource), + .resource = stamp_flash_resource, +}; + #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) /* all SPI peripherals info goes here */ @@ -457,6 +502,7 @@ static struct platform_device *stamp_devices[] __initdata = { #if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE) &i2c_gpio_device, #endif + &stamp_flash_device, }; static int __init stamp_init(void) @@ -469,12 +515,10 @@ static int __init stamp_init(void) return ret; #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE) -# if defined(CONFIG_BFIN_SHARED_FLASH_ENET) /* setup BF533_STAMP CPLD to route AMS3 to Ethernet MAC */ bfin_write_FIO_DIR(bfin_read_FIO_DIR() | (1 << CONFIG_ENET_FLASH_PIN)); bfin_write_FIO_FLAG_S(1 << CONFIG_ENET_FLASH_PIN); SSYNC(); -# endif #endif #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) @@ -491,10 +535,8 @@ arch_initcall(stamp_init); void native_machine_restart(char *cmd) { -#if defined(CONFIG_BFIN_SHARED_FLASH_ENET) -# define BIT_TO_SET (1 << CONFIG_ENET_FLASH_PIN) +#define BIT_TO_SET (1 << CONFIG_ENET_FLASH_PIN) bfin_write_FIO_INEN(~BIT_TO_SET); bfin_write_FIO_DIR(BIT_TO_SET); bfin_write_FIO_FLAG_C(BIT_TO_SET); -#endif } diff --git a/arch/blackfin/mach-bf537/boards/stamp.c b/arch/blackfin/mach-bf537/boards/stamp.c index 37759ac..7725415 100644 --- a/arch/blackfin/mach-bf537/boards/stamp.c +++ b/arch/blackfin/mach-bf537/boards/stamp.c @@ -32,6 +32,7 @@ #include #include #include +#include #include #include #if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE) @@ -339,6 +340,49 @@ static struct platform_device net2272_bfin_device = { }; #endif +static struct mtd_partition stamp_partitions[] = { + { + .name = "Bootloader", + .size = 0x20000, + .offset = 0, + }, { + .name = "Kernel", + .size = 0xE0000, + .offset = MTDPART_OFS_APPEND, + }, { + .name = "RootFS", + .size = 0x400000 - 0x20000 - 0xE0000 - 0x10000, + .offset = MTDPART_OFS_APPEND, + }, { + .name = "MAC Address", + .size = MTDPART_SIZ_FULL, + .offset = 0x3F0000, + .mask_flags = MTD_WRITEABLE, + } +}; + +static struct physmap_flash_data stamp_flash_data = { + .width = 2, + .parts = stamp_partitions, + .nr_parts = ARRAY_SIZE(stamp_partitions), +}; + +static struct resource stamp_flash_resource = { + .start = 0x20000000, + .end = 0x203fffff, + .flags = IORESOURCE_MEM, +}; + +static struct platform_device stamp_flash_device = { + .name = "physmap-flash", + .id = 0, + .dev = { + .platform_data = &stamp_flash_data, + }, + .num_resources = 1, + .resource = &stamp_flash_resource, +}; + #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) /* all SPI peripherals info goes here */ @@ -761,6 +805,7 @@ static struct platform_device *stamp_devices[] __initdata = { #if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE) &bfin_device_gpiokeys, #endif + &stamp_flash_device, }; static int __init stamp_init(void) diff --git a/arch/blackfin/mach-bf548/boards/ezkit.c b/arch/blackfin/mach-bf548/boards/ezkit.c index 4ca3288..14860f0 100644 --- a/arch/blackfin/mach-bf548/boards/ezkit.c +++ b/arch/blackfin/mach-bf548/boards/ezkit.c @@ -32,6 +32,7 @@ #include #include #include +#include #include #include #include @@ -327,6 +328,44 @@ static struct platform_device bf54x_sdh_device = { }; #endif +static struct mtd_partition ezkit_partitions[] = { + { + .name = "Bootloader", + .size = 0x20000, + .offset = 0, + }, { + .name = "Kernel", + .size = 0xE0000, + .offset = MTDPART_OFS_APPEND, + }, { + .name = "RootFS", + .size = MTDPART_SIZ_FULL, + .offset = MTDPART_OFS_APPEND, + } +}; + +static struct physmap_flash_data ezkit_flash_data = { + .width = 2, + .parts = ezkit_partitions, + .nr_parts = ARRAY_SIZE(ezkit_partitions), +}; + +static struct resource ezkit_flash_resource = { + .start = 0x20000000, + .end = 0x20ffffff, + .flags = IORESOURCE_MEM, +}; + +static struct platform_device ezkit_flash_device = { + .name = "physmap-flash", + .id = 0, + .dev = { + .platform_data = &ezkit_flash_data, + }, + .num_resources = 1, + .resource = &ezkit_flash_resource, +}; + #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) /* all SPI peripherals info goes here */ #if defined(CONFIG_MTD_M25P80) \ @@ -589,6 +628,7 @@ static struct platform_device *ezkit_devices[] __initdata = { #if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE) &bfin_device_gpiokeys, #endif + &ezkit_flash_device, }; static int __init stamp_init(void) diff --git a/arch/blackfin/mach-bf561/boards/ezkit.c b/arch/blackfin/mach-bf561/boards/ezkit.c index 36114dd..7601c3b 100644 --- a/arch/blackfin/mach-bf561/boards/ezkit.c +++ b/arch/blackfin/mach-bf561/boards/ezkit.c @@ -29,6 +29,9 @@ #include #include +#include +#include +#include #include #include #include @@ -155,6 +158,44 @@ static struct platform_device bfin_uart_device = { }; #endif +static struct mtd_partition ezkit_partitions[] = { + { + .name = "Bootloader", + .size = 0x20000, + .offset = 0, + }, { + .name = "Kernel", + .size = 0xE0000, + .offset = MTDPART_OFS_APPEND, + }, { + .name = "RootFS", + .size = MTDPART_SIZ_FULL, + .offset = MTDPART_OFS_APPEND, + } +}; + +static struct physmap_flash_data ezkit_flash_data = { + .width = 2, + .parts = ezkit_partitions, + .nr_parts = ARRAY_SIZE(ezkit_partitions), +}; + +static struct resource ezkit_flash_resource = { + .start = 0x20000000, + .end = 0x207fffff, + .flags = IORESOURCE_MEM, +}; + +static struct platform_device ezkit_flash_device = { + .name = "physmap-flash", + .id = 0, + .dev = { + .platform_data = &ezkit_flash_data, + }, + .num_resources = 1, + .resource = &ezkit_flash_resource, +}; + #ifdef CONFIG_SPI_BFIN #if defined(CONFIG_SND_BLACKFIN_AD1836) \ || defined(CONFIG_SND_BLACKFIN_AD1836_MODULE) @@ -318,6 +359,7 @@ static struct platform_device *ezkit_devices[] __initdata = { #if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE) &i2c_gpio_device, #endif + &ezkit_flash_device, }; static int __init ezkit_init(void) -- cgit v0.10.2 From ee7883b7466e721a72edacbcba2fe9cf449d82b2 Mon Sep 17 00:00:00 2001 From: Yi Li Date: Sun, 27 Jan 2008 19:56:17 +0800 Subject: [Blackfin] arch: fix bug kernel boot message: memory information is not reasonable Some of the information in kernel boot message is not reasonable. http://blackfin.uclinux.org/gf/project/uclinux-dist/tracker/?action=TrackerItemEdit&tracker_item_id=3846 - use _rambase as the start of kernel image. kernel is in the region [_rambase, _ramstart] - count in pages in per-cpu-page list as available memory - reserved memory now include: [0 - 4K] for bad pointer catching, memory reserved for abnormaly 05000263, memory reserved by kernel itself. Signed-off-by: Yi Li Signed-off-by: Bryan Wu diff --git a/arch/blackfin/kernel/setup.c b/arch/blackfin/kernel/setup.c index 1a942a7..462cae8 100644 --- a/arch/blackfin/kernel/setup.c +++ b/arch/blackfin/kernel/setup.c @@ -238,6 +238,7 @@ void __init setup_arch(char **cmdline_p) memory_end = _ramend - DMA_UNCACHED_REGION; _ramstart = (unsigned long)__bss_stop; + _rambase = (unsigned long)_stext; #ifdef CONFIG_MPU /* Round up to multiple of 4MB. */ memory_start = (_ramstart + 0x3fffff) & ~0x3fffff; diff --git a/arch/blackfin/mm/init.c b/arch/blackfin/mm/init.c index 9f007ca..eb1a12a 100644 --- a/arch/blackfin/mm/init.c +++ b/arch/blackfin/mm/init.c @@ -128,8 +128,8 @@ void __init paging_init(void) void __init mem_init(void) { unsigned int codek = 0, datak = 0, initk = 0; + unsigned int reservedpages = 0, freepages = 0; unsigned long tmp; - unsigned int len = _ramend - _rambase; unsigned long start_mem = memory_start; unsigned long end_mem = memory_end; @@ -138,19 +138,36 @@ void __init mem_init(void) start_mem = PAGE_ALIGN(start_mem); max_mapnr = num_physpages = MAP_NR(high_memory); - printk(KERN_INFO "Physical pages: %lx\n", num_physpages); + printk(KERN_INFO "Kernel managed physical pages: %lu\n", + num_physpages); /* This will put all memory onto the freelists. */ totalram_pages = free_all_bootmem(); + reservedpages = 0; + for (tmp = 0; tmp < max_mapnr; tmp++) + if (PageReserved(pfn_to_page(tmp))) + reservedpages++; + freepages = max_mapnr - reservedpages; + + /* do not count in kernel image between _rambase and _ramstart */ + reservedpages -= (_ramstart - _rambase) >> PAGE_SHIFT; +#if (defined(CONFIG_BFIN_ICACHE) && ANOMALY_05000263) + reservedpages += (_ramend - memory_end - DMA_UNCACHED_REGION) >> + PAGE_SHIFT; +#endif + codek = (_etext - _stext) >> 10; - datak = (__bss_stop - __bss_start) >> 10; initk = (__init_end - __init_begin) >> 10; + datak = ((_ramstart - _rambase) >> 10) - codek - initk; - tmp = nr_free_pages() << PAGE_SHIFT; printk(KERN_INFO - "Memory available: %luk/%uk RAM, (%uk init code, %uk kernel code, %uk data, %uk dma)\n", - tmp >> 10, len >> 10, initk, codek, datak, DMA_UNCACHED_REGION >> 10); + "Memory available: %luk/%luk RAM, " + "(%uk init code, %uk kernel code, " + "%uk data, %uk dma, %uk reserved)\n", + (unsigned long) freepages << (PAGE_SHIFT-10), _ramend >> 10, + initk, codek, datak, DMA_UNCACHED_REGION >> 10, + (reservedpages << (PAGE_SHIFT-10))); /* Initialize the blackfin L1 Memory. */ l1sram_init(); -- cgit v0.10.2 From fc97551db9e4e9402ff2b5c94be8267b2e5f32f4 Mon Sep 17 00:00:00 2001 From: Bernd Schmidt Date: Sun, 27 Jan 2008 19:56:43 +0800 Subject: [Blackfin] arch: Add the semtimedop syscall. Upstream uClibc doesn't compile without it. Signed-off-by: Bernd Schmidt Signed-off-by: Bryan Wu diff --git a/arch/blackfin/mach-common/entry.S b/arch/blackfin/mach-common/entry.S index c2e81a1..56ff51b 100644 --- a/arch/blackfin/mach-common/entry.S +++ b/arch/blackfin/mach-common/entry.S @@ -1381,6 +1381,7 @@ ENTRY(_sys_call_table) .long _sys_set_robust_list .long _sys_get_robust_list /* 355 */ .long _sys_fallocate + .long _sys_semtimedop .rept NR_syscalls-(.-_sys_call_table)/4 .long _sys_ni_syscall .endr diff --git a/include/asm-blackfin/unistd.h b/include/asm-blackfin/unistd.h index 07ffe8b..e981673 100644 --- a/include/asm-blackfin/unistd.h +++ b/include/asm-blackfin/unistd.h @@ -369,8 +369,9 @@ #define __NR_set_robust_list 354 #define __NR_get_robust_list 355 #define __NR_fallocate 356 +#define __NR_semtimedop 357 -#define __NR_syscall 357 +#define __NR_syscall 358 #define NR_syscalls __NR_syscall /* Old optional stuff no one actually uses */ -- cgit v0.10.2 From 408dbc0da29913f99e56001db892eb653b47c13b Mon Sep 17 00:00:00 2001 From: Bryan Wu Date: Sun, 27 Jan 2008 18:38:12 +0800 Subject: [Blackfin] arch: remove old I2C BF54x porting. Signed-off-by: Bryan Wu diff --git a/include/asm-blackfin/mach-bf548/cdefBF54x_base.h b/include/asm-blackfin/mach-bf548/cdefBF54x_base.h index aefab3f..19ddcd8 100644 --- a/include/asm-blackfin/mach-bf548/cdefBF54x_base.h +++ b/include/asm-blackfin/mach-bf548/cdefBF54x_base.h @@ -244,39 +244,6 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) #define bfin_read_TWI0_RCV_DATA16() bfin_read16(TWI0_RCV_DATA16) #define bfin_write_TWI0_RCV_DATA16(val) bfin_write16(TWI0_RCV_DATA16, val) -#define bfin_read_TWI_CLKDIV() bfin_read16(TWI0_CLKDIV) -#define bfin_write_TWI_CLKDIV(val) bfin_write16(TWI0_CLKDIV, val) -#define bfin_read_TWI_CONTROL() bfin_read16(TWI0_CONTROL) -#define bfin_write_TWI_CONTROL(val) bfin_write16(TWI0_CONTROL, val) -#define bfin_read_TWI_SLAVE_CTRL() bfin_read16(TWI0_SLAVE_CTRL) -#define bfin_write_TWI_SLAVE_CTRL(val) bfin_write16(TWI0_SLAVE_CTRL, val) -#define bfin_read_TWI_SLAVE_STAT() bfin_read16(TWI0_SLAVE_STAT) -#define bfin_write_TWI_SLAVE_STAT(val) bfin_write16(TWI0_SLAVE_STAT, val) -#define bfin_read_TWI_SLAVE_ADDR() bfin_read16(TWI0_SLAVE_ADDR) -#define bfin_write_TWI_SLAVE_ADDR(val) bfin_write16(TWI0_SLAVE_ADDR, val) -#define bfin_read_TWI_MASTER_CTL() bfin_read16(TWI0_MASTER_CTRL) -#define bfin_write_TWI_MASTER_CTL(val) bfin_write16(TWI0_MASTER_CTRL, val) -#define bfin_read_TWI_MASTER_STAT() bfin_read16(TWI0_MASTER_STAT) -#define bfin_write_TWI_MASTER_STAT(val) bfin_write16(TWI0_MASTER_STAT, val) -#define bfin_read_TWI_MASTER_ADDR() bfin_read16(TWI0_MASTER_ADDR) -#define bfin_write_TWI_MASTER_ADDR(val) bfin_write16(TWI0_MASTER_ADDR, val) -#define bfin_read_TWI_INT_STAT() bfin_read16(TWI0_INT_STAT) -#define bfin_write_TWI_INT_STAT(val) bfin_write16(TWI0_INT_STAT, val) -#define bfin_read_TWI_INT_MASK() bfin_read16(TWI0_INT_MASK) -#define bfin_write_TWI_INT_MASK(val) bfin_write16(TWI0_INT_MASK, val) -#define bfin_read_TWI_FIFO_CTL() bfin_read16(TWI0_FIFO_CTRL) -#define bfin_write_TWI_FIFO_CTL(val) bfin_write16(TWI0_FIFO_CTRL, val) -#define bfin_read_TWI_FIFO_STAT() bfin_read16(TWI0_FIFO_STAT) -#define bfin_write_TWI_FIFO_STAT(val) bfin_write16(TWI0_FIFO_STAT, val) -#define bfin_read_TWI_XMT_DATA8() bfin_read16(TWI0_XMT_DATA8) -#define bfin_write_TWI_XMT_DATA8(val) bfin_write16(TWI0_XMT_DATA8, val) -#define bfin_read_TWI_XMT_DATA16() bfin_read16(TWI0_XMT_DATA16) -#define bfin_write_TWI_XMT_DATA16(val) bfin_write16(TWI0_XMT_DATA16, val) -#define bfin_read_TWI_RCV_DATA8() bfin_read16(TWI0_RCV_DATA8) -#define bfin_write_TWI_RCV_DATA8(val) bfin_write16(TWI0_RCV_DATA8, val) -#define bfin_read_TWI_RCV_DATA16() bfin_read16(TWI0_RCV_DATA16) -#define bfin_write_TWI_RCV_DATA16(val) bfin_write16(TWI0_RCV_DATA16, val) - /* SPORT0 is not defined in the shared file because it is not available on the ADSP-BF542 and ADSP-BF544 bfin_read_()rocessors */ /* SPORT1 Registers */ -- cgit v0.10.2 From 9c5e710bc1431f41ccdd0c294fa355aa0d45d2d7 Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Sat, 17 Nov 2007 23:19:44 +0800 Subject: MAINTIANERS: just use Mike gmail e-mail for contact and pawn the serial driver off onto Sonic Signed-off-by: Mike Frysinger Signed-off-by: Bryan Wu diff --git a/MAINTAINERS b/MAINTAINERS index 59db481..2937122 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -758,22 +758,20 @@ S: Supported BLACKFIN RTC DRIVER P: Mike Frysinger -M: michael.frysinger@analog.com M: vapier.adi@gmail.com L: uclinux-dist-devel@blackfin.uclinux.org (subscribers-only) W: http://blackfin.uclinux.org S: Supported BLACKFIN SERIAL DRIVER -P: Aubrey Li -M: aubrey.li@analog.com +P: Sonic Zhang +M: sonic.zhang@analog.com L: uclinux-dist-devel@blackfin.uclinux.org (subscribers-only) W: http://blackfin.uclinux.org S: Supported BLACKFIN WATCHDOG DRIVER P: Mike Frysinger -M: michael.frysinger@analog.com M: vapier.adi@gmail.com L: uclinux-dist-devel@blackfin.uclinux.org (subscribers-only) W: http://blackfin.uclinux.org -- cgit v0.10.2