From ce95d709449a757effc08b5a0da3edc311340ede Mon Sep 17 00:00:00 2001 From: "Arnaud Patard (Rtp)" Date: Sat, 27 Aug 2011 15:21:12 +0200 Subject: MX5: fix clock usage While suspending, we're enabling a clock in ->suspend() but we're in atomic context, leading to this : [30803.667305] PM: late suspend of devices complete after 1.237 msecs [30803.667449] BUG: sleeping function called from invalid context at kernel/mutex.c:271 [30803.667464] in_atomic(): 0, irqs_disabled(): 128, pid: 4941, name: pm-suspend [30803.667474] INFO: lockdep is turned off. [30803.667483] irq event stamp: 0 [30803.667489] hardirqs last enabled at (0): [< (null)>] (null) [30803.667503] hardirqs last disabled at (0): [] copy_process.part.48+0x1e0/0xa7c [30803.667543] softirqs last enabled at (0): [] copy_process.part.48+0x1e0/0xa7c [30803.667562] softirqs last disabled at (0): [< (null)>] (null) [30803.667574] Backtrace: [30803.667611] [] (dump_backtrace+0x0/0x110) from [] (dump_stack+0x18/0x1c) [30803.667624] r6:00000000 r5:00000000 r4:d9648000 r3:d9648000 [30803.667652] [] (dump_stack+0x0/0x1c) from [] (__might_sleep.part.101+0x90/0xa8) [30803.667673] [] (__might_sleep.part.101+0x0/0xa8) from [] (__might_sleep+0x80/0x94) [30803.667686] r4:c05d58c0 [30803.667705] [] (__might_sleep+0x0/0x94) from [] (mutex_lock_nested+0x2c/0x30c) [30803.667735] [] (mutex_lock_nested+0x0/0x30c) from [] (clk_enable+0x28/0x50) [30803.667747] r8:c0438464 r7:00000003 r6:00000000 r5:00000000 r4:c05d2e98 [30803.667780] [] (clk_enable+0x0/0x50) from [] (mx5_suspend_enter+0x1c/0x98) [30803.667792] r4:00000003 r3:c060dfe0 [30803.667821] [] (mx5_suspend_enter+0x0/0x98) from [] (suspend_enter+0xec/0x15c) [30803.667833] r4:00000003 r3:c0017244 [30803.667856] [] (suspend_enter+0x0/0x15c) from [] (suspend_devices_and_enter+0x94/0x130) [30803.667868] r6:00000000 r5:00000003 r4:c0c0af00 r3:00002710 [30803.667897] [] (suspend_devices_and_enter+0x0/0x130) from [] (enter_state+0xc8/0x130) [30803.667909] r6:00000000 r5:00000003 r4:c05286e4 [30803.667934] [] (enter_state+0x0/0x130) from [] (state_store+0xac/0xc0) [30803.667945] r6:00000003 r5:00000003 r4:df39d000 r3:00000003 [30803.667978] [] (state_store+0x0/0xc0) from [] (kobj_attr_store+0x1c/0x28) [30803.668009] [] (kobj_attr_store+0x0/0x28) from [] (sysfs_write_file+0x88/0xbc) [30803.668032] [] (sysfs_write_file+0x0/0xbc) from [] (vfs_write+0xbc/0x138) [30803.668051] [] (vfs_write+0x0/0x138) from [] (sys_write+0x44/0x70) [30803.668062] r8:00000000 r7:00000004 r6:00000003 r5:002694d0 r4:d966acc0 [30803.668094] [] (sys_write+0x0/0x70) from [] (ret_fast_syscall+0x0/0x3c) [30803.668106] r9:d9648000 r8:c000dcc4 r6:00000001 r5:002694d0 r4:00000003 [30803.669927] PM: early resume of devices complete after 0.972 msecs Just move the clk_enable/disable in ->prepare() and ->finish() Signed-off-by: Arnaud Patard Signed-off-by: Sascha Hauer diff --git a/arch/arm/mach-mx5/pm-imx5.c b/arch/arm/mach-mx5/pm-imx5.c index e4529af..be19e9c 100644 --- a/arch/arm/mach-mx5/pm-imx5.c +++ b/arch/arm/mach-mx5/pm-imx5.c @@ -19,9 +19,13 @@ static struct clk *gpc_dvfs_clk; +static int mx5_suspend_prepare(void) +{ + return clk_enable(gpc_dvfs_clk); +} + static int mx5_suspend_enter(suspend_state_t state) { - clk_enable(gpc_dvfs_clk); switch (state) { case PM_SUSPEND_MEM: mx5_cpu_lp_set(STOP_POWER_OFF); @@ -42,11 +46,14 @@ static int mx5_suspend_enter(suspend_state_t state) __raw_writel(0, MXC_SRPG_EMPGC1_SRPGCR); } cpu_do_idle(); - clk_disable(gpc_dvfs_clk); - return 0; } +static void mx5_suspend_finish(void) +{ + clk_disable(gpc_dvfs_clk); +} + static int mx5_pm_valid(suspend_state_t state) { return (state > PM_SUSPEND_ON && state <= PM_SUSPEND_MAX); @@ -54,7 +61,9 @@ static int mx5_pm_valid(suspend_state_t state) static const struct platform_suspend_ops mx5_suspend_ops = { .valid = mx5_pm_valid, + .prepare = mx5_suspend_prepare, .enter = mx5_suspend_enter, + .finish = mx5_suspend_finish, }; static int __init mx5_pm_init(void) -- cgit v0.10.2 From d093d5bbdb255b64d9dd6478d1d534e2101f9a70 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 14 Sep 2011 14:04:38 -0300 Subject: ARM: mx31pdk: Fix build by passing IMX_HAVE_PLATFORM_MXC_MMC mx31pdk target fails to build: CC init/version.o LD init/built-in.o LD .tmp_vmlinux1 arch/arm/mach-imx/built-in.o: In function `mx31_3ds_init': mach-mx31_3ds.c:(.init.text+0x548): undefined reference to `imx_add_mxc_mmc' mach-mx31_3ds.c:(.init.text+0x69c): undefined reference to `imx31_mxc_mmc_data' make: *** [.tmp_vmlinux1] Error Fix this by passsing IMX_HAVE_PLATFORM_MXC_MMC option. Signed-off-by: Fabio Estevam Signed-off-by: Sascha Hauer diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index 0519dd7..e9c2968 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -449,6 +449,7 @@ config MACH_MX31_3DS select IMX_HAVE_PLATFORM_IMX_UART select IMX_HAVE_PLATFORM_IPU_CORE select IMX_HAVE_PLATFORM_MXC_EHCI + select IMX_HAVE_PLATFORM_MXC_MMC select IMX_HAVE_PLATFORM_MXC_NAND select IMX_HAVE_PLATFORM_SPI_IMX select MXC_ULPI if USB_ULPI -- cgit v0.10.2 From e0628d25ce9cea371e07cba5ee470af63e602a41 Mon Sep 17 00:00:00 2001 From: srinidhi kasagar Date: Tue, 20 Sep 2011 11:15:46 +0530 Subject: ARM: mach-ux500: enable fix for ARM errata 754322 This applies ARM errata fix 754322 for all ux500 platforms. Cc: stable@kernel.org Signed-off-by: srinidhi kasagar Signed-off-by: Linus Walleij diff --git a/arch/arm/mach-ux500/Kconfig b/arch/arm/mach-ux500/Kconfig index 4210cb4..a3e0c86 100644 --- a/arch/arm/mach-ux500/Kconfig +++ b/arch/arm/mach-ux500/Kconfig @@ -6,6 +6,7 @@ config UX500_SOC_COMMON select ARM_GIC select HAS_MTU select ARM_ERRATA_753970 + select ARM_ERRATA_754322 menu "Ux500 SoC" -- cgit v0.10.2 From 1bf6d2c1bb23533af6930581cc39b74685bc29de Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Fri, 12 Aug 2011 13:54:42 +0200 Subject: ARM: mach-ux500: unlock I&D l2x0 caches before init Apparently U8500 U-Boot versions may leave the l2x0 locked down before executing the kernel. Make sure we unlock it before we initialize the l2x0. This fixes a performance problem reported by Jan Rinze. The l2x0 core has been modified to unlock the l2x0 by default, but it will not touch the locking registers if the l2x0 was already enabled, as on the ux500, so we need this quirk to make sure it is properly turned off. Cc: stable@kernel.org Cc: Srinidhi Kasagar Cc: Rabin Vincent Cc: Adrian Bunk Reported-by: Jan Rinze Tested-by: Robert Marklund Signed-off-by: Linus Walleij diff --git a/arch/arm/mach-ux500/cpu.c b/arch/arm/mach-ux500/cpu.c index 1da23bb..8aa104a 100644 --- a/arch/arm/mach-ux500/cpu.c +++ b/arch/arm/mach-ux500/cpu.c @@ -99,7 +99,27 @@ static void ux500_l2x0_inv_all(void) ux500_cache_sync(); } -static int ux500_l2x0_init(void) +static int __init ux500_l2x0_unlock(void) +{ + int i; + + /* + * Unlock Data and Instruction Lock if locked. Ux500 U-Boot versions + * apparently locks both caches before jumping to the kernel. The + * l2x0 core will not touch the unlock registers if the l2x0 is + * already enabled, so we do it right here instead. The PL310 has + * 8 sets of registers, one per possible CPU. + */ + for (i = 0; i < 8; i++) { + writel_relaxed(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_D_BASE + + i * L2X0_LOCKDOWN_STRIDE); + writel_relaxed(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_I_BASE + + i * L2X0_LOCKDOWN_STRIDE); + } + return 0; +} + +static int __init ux500_l2x0_init(void) { if (cpu_is_u5500()) l2x0_base = __io_address(U5500_L2CC_BASE); @@ -108,6 +128,9 @@ static int ux500_l2x0_init(void) else ux500_unknown_soc(); + /* Unlock before init */ + ux500_l2x0_unlock(); + /* 64KB way size, 8 way associativity, force WA */ l2x0_init(l2x0_base, 0x3e060000, 0xc0000fff); -- cgit v0.10.2 From 6111d50c5885f6ba00dc935e44bcbbcd63b3915d Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Tue, 20 Sep 2011 10:46:26 -0600 Subject: arm/dt: Tegra: Add support-8bit to SDHCI nodes For Seaboard's internal eMMC, this makes the difference between a 5.5MB/s and 10.2MB/s transfer rate. On Harmony, there wasn't any measurable difference on my cheap/slow ~2MB/s card. Signed-off-by: Stephen Warren Signed-off-by: Arnd Bergmann diff --git a/arch/arm/boot/dts/tegra-harmony.dts b/arch/arm/boot/dts/tegra-harmony.dts index e581866..0e225b8 100644 --- a/arch/arm/boot/dts/tegra-harmony.dts +++ b/arch/arm/boot/dts/tegra-harmony.dts @@ -66,5 +66,6 @@ cd-gpios = <&gpio 58 0>; /* gpio PH2 */ wp-gpios = <&gpio 59 0>; /* gpio PH3 */ power-gpios = <&gpio 70 0>; /* gpio PI6 */ + support-8bit; }; }; diff --git a/arch/arm/boot/dts/tegra-seaboard.dts b/arch/arm/boot/dts/tegra-seaboard.dts index 64cedca..a72299b 100644 --- a/arch/arm/boot/dts/tegra-seaboard.dts +++ b/arch/arm/boot/dts/tegra-seaboard.dts @@ -25,4 +25,8 @@ wp-gpios = <&gpio 57 0>; /* gpio PH1 */ power-gpios = <&gpio 70 0>; /* gpio PI6 */ }; + + sdhci@c8000600 { + support-8bit; + }; }; -- cgit v0.10.2 From a368f7764491a0116baff9963d22247d4d8f6f51 Mon Sep 17 00:00:00 2001 From: Bjarne Steinsbo Date: Fri, 30 Sep 2011 11:05:56 -0700 Subject: ARM: OMAP4: Keyboard: Fix section mismatch in the board file `keypad_pads' is referred to by `keypad_data' which is not __initdata, so `keypad_pads' should not be __initdata either. Signed-off-by: Bjarne Steinsbo Reviewed-by: Felipe Balbi Signed-off-by: Tony Lindgren diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c index c7cef44..9e423ac 100644 --- a/arch/arm/mach-omap2/board-4430sdp.c +++ b/arch/arm/mach-omap2/board-4430sdp.c @@ -129,7 +129,7 @@ static const int sdp4430_keymap[] = { KEY(7, 6, KEY_OK), KEY(7, 7, KEY_DOWN), }; -static struct omap_device_pad keypad_pads[] __initdata = { +static struct omap_device_pad keypad_pads[] = { { .name = "kpd_col1.kpd_col1", .enable = OMAP_WAKEUP_EN | OMAP_MUX_MODE1, }, -- cgit v0.10.2 From 5c30cdfa41821dd89792600118cab5c02a5c322b Mon Sep 17 00:00:00 2001 From: Tapani Utriainen Date: Fri, 30 Sep 2011 11:05:56 -0700 Subject: ARM: OMAP: irq: loop counter fix in omap_init_irq() Fixes bug where variable i was redundantly used for counting two nested loops. Signed-off-by: Tapani Utriainen Signed-off-by: Tony Lindgren diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c index 3a12f75..65f1be6 100644 --- a/arch/arm/mach-omap2/irq.c +++ b/arch/arm/mach-omap2/irq.c @@ -165,8 +165,8 @@ static void __init omap_init_irq(u32 base, int nr_irqs) omap_irq_bank_init_one(bank); - for (i = 0, j = 0; i < bank->nr_irqs; i += 32, j += 0x20) - omap_alloc_gc(bank->base_reg + j, i, 32); + for (j = 0; j < bank->nr_irqs; j += 32) + omap_alloc_gc(bank->base_reg + j, j, 32); nr_of_irqs += bank->nr_irqs; nr_banks++; -- cgit v0.10.2 From e227e88ae46e921f608b056e27e1d8704b7d12fa Mon Sep 17 00:00:00 2001 From: Eric Miao Date: Sun, 11 Sep 2011 16:56:58 +0800 Subject: ARM: pxa: fix building error by palm27x_lcd_init() when FB_PXA not defined Cc: Marek Vasut Signed-off-by: Eric Miao diff --git a/arch/arm/mach-pxa/include/mach/palm27x.h b/arch/arm/mach-pxa/include/mach/palm27x.h index 0a5e5ea..f80bbe2 100644 --- a/arch/arm/mach-pxa/include/mach/palm27x.h +++ b/arch/arm/mach-pxa/include/mach/palm27x.h @@ -34,7 +34,7 @@ extern struct pxafb_mode_info palm_320x320_new_lcd_mode; extern void __init palm27x_lcd_init(int power, struct pxafb_mode_info *mode); #else -static inline void palm27x_lcd_init(int power, struct pxafb_mode_info *mode) {} +#define palm27x_lcd_init(power, mode) do {} while (0) #endif #if defined(CONFIG_USB_GADGET_PXA27X) || \ -- cgit v0.10.2 From 2d60cd15d4b0566d371373ca8433358af27dbf5f Mon Sep 17 00:00:00 2001 From: Nicolas Ferre Date: Thu, 22 Sep 2011 18:49:44 +0200 Subject: ARM: at91: remove dependency for Atmel PWM driver selector in Kconfig Remove dependency line which was not including the SAM9G45. [arnd: added dependency on HAVE_CLK to avoid breaking other machines] Signed-off-by: Nicolas Ferre Signed-off-by: Arnd Bergmann diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index 2d6423c..166d149 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -63,7 +63,7 @@ config AD525X_DPOT_SPI config ATMEL_PWM tristate "Atmel AT32/AT91 PWM support" - depends on AVR32 || ARCH_AT91SAM9263 || ARCH_AT91SAM9RL || ARCH_AT91CAP9 + depends on HAVE_CLK help This option enables device driver support for the PWM channels on certain Atmel processors. Pulse Width Modulation is used for -- cgit v0.10.2 From 1d354b820407b978226da182e06279c4aa90f9af Mon Sep 17 00:00:00 2001 From: Nicolas Ferre Date: Thu, 22 Sep 2011 18:50:57 +0200 Subject: ARM: at91: add defconfig for at91sam9g45 family Defconfig file for at91sam9g45 SoC family: at91sam9g45, at91sam9g46, at91sam9m10, at91sam9m11. The Atmel Evaluation Kit for this family is the at91sam9m10g45ek. It is so useful for automatic compile tests... Signed-off-by: Nicolas Ferre Acked-by: Jean-Christophe PLAGNIOL-VILLARD diff --git a/arch/arm/configs/at91sam9g45_defconfig b/arch/arm/configs/at91sam9g45_defconfig new file mode 100644 index 0000000..c5876d2 --- /dev/null +++ b/arch/arm/configs/at91sam9g45_defconfig @@ -0,0 +1,214 @@ +CONFIG_EXPERIMENTAL=y +# CONFIG_LOCALVERSION_AUTO is not set +# CONFIG_SWAP is not set +CONFIG_SYSVIPC=y +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_SYSFS_DEPRECATED=y +CONFIG_SYSFS_DEPRECATED_V2=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_EMBEDDED=y +CONFIG_SLAB=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_LBDAF is not set +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_IOSCHED_DEADLINE is not set +# CONFIG_IOSCHED_CFQ is not set +CONFIG_ARCH_AT91=y +CONFIG_ARCH_AT91SAM9G45=y +CONFIG_MACH_AT91SAM9M10G45EK=y +CONFIG_AT91_PROGRAMMABLE_CLOCKS=y +CONFIG_AT91_SLOW_CLOCK=y +CONFIG_AEABI=y +# CONFIG_OABI_COMPAT is not set +CONFIG_LEDS=y +CONFIG_LEDS_CPU=y +CONFIG_UACCESS_WITH_MEMCPY=y +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_CMDLINE="mem=128M console=ttyS0,115200 initrd=0x71100000,25165824 root=/dev/ram0 rw" +CONFIG_AUTO_ZRELADDR=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_DIAG is not set +CONFIG_IPV6=y +# CONFIG_INET6_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET6_XFRM_MODE_TUNNEL is not set +# CONFIG_INET6_XFRM_MODE_BEET is not set +CONFIG_IPV6_SIT_6RD=y +CONFIG_CFG80211=y +CONFIG_LIB80211=y +CONFIG_MAC80211=y +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +# CONFIG_STANDALONE is not set +# CONFIG_PREVENT_FIRMWARE_BUILD is not set +CONFIG_MTD=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_DATAFLASH=y +CONFIG_MTD_NAND=y +CONFIG_MTD_NAND_ATMEL=y +CONFIG_MTD_UBI=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=4 +CONFIG_BLK_DEV_RAM_SIZE=8192 +CONFIG_MISC_DEVICES=y +CONFIG_ATMEL_PWM=y +CONFIG_ATMEL_TCLIB=y +CONFIG_SCSI=y +CONFIG_BLK_DEV_SD=y +CONFIG_SCSI_MULTI_LUN=y +# CONFIG_SCSI_LOWLEVEL is not set +CONFIG_NETDEVICES=y +CONFIG_MII=y +CONFIG_DAVICOM_PHY=y +CONFIG_NET_ETHERNET=y +CONFIG_MACB=y +# CONFIG_NETDEV_1000 is not set +# CONFIG_NETDEV_10000 is not set +CONFIG_LIBERTAS_THINFIRM=m +CONFIG_LIBERTAS_THINFIRM_USB=m +CONFIG_AT76C50X_USB=m +CONFIG_USB_ZD1201=m +CONFIG_RTL8187=m +CONFIG_ATH_COMMON=m +CONFIG_ATH9K=m +CONFIG_CARL9170=m +CONFIG_B43=m +CONFIG_B43_PHY_N=y +CONFIG_LIBERTAS=m +CONFIG_LIBERTAS_USB=m +CONFIG_LIBERTAS_SDIO=m +CONFIG_LIBERTAS_SPI=m +CONFIG_RT2X00=m +CONFIG_RT2500USB=m +CONFIG_RT73USB=m +CONFIG_RT2800USB=m +CONFIG_RT2800USB_RT53XX=y +CONFIG_RT2800USB_UNKNOWN=y +CONFIG_RTL8192CU=m +CONFIG_WL1251=m +CONFIG_WL1251_SDIO=m +CONFIG_WL12XX_MENU=m +CONFIG_WL12XX=m +CONFIG_WL12XX_SDIO=m +CONFIG_ZD1211RW=m +CONFIG_MWIFIEX=m +CONFIG_MWIFIEX_SDIO=m +CONFIG_INPUT_POLLDEV=m +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set +CONFIG_INPUT_MOUSEDEV_SCREEN_X=480 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=272 +CONFIG_INPUT_JOYDEV=y +CONFIG_INPUT_EVDEV=y +# CONFIG_KEYBOARD_ATKBD is not set +CONFIG_KEYBOARD_QT1070=m +CONFIG_KEYBOARD_QT2160=m +CONFIG_KEYBOARD_GPIO=y +# CONFIG_INPUT_MOUSE is not set +CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_TOUCHSCREEN_ATMEL_MXT=m +CONFIG_TOUCHSCREEN_ATMEL_TSADCC=y +# CONFIG_SERIO is not set +CONFIG_LEGACY_PTY_COUNT=4 +CONFIG_SERIAL_ATMEL=y +CONFIG_SERIAL_ATMEL_CONSOLE=y +CONFIG_HW_RANDOM=y +CONFIG_I2C=y +CONFIG_I2C_GPIO=y +CONFIG_SPI=y +CONFIG_SPI_ATMEL=y +# CONFIG_HWMON is not set +# CONFIG_MFD_SUPPORT is not set +CONFIG_FB=y +CONFIG_FB_ATMEL=y +CONFIG_FB_UDL=m +CONFIG_BACKLIGHT_LCD_SUPPORT=y +# CONFIG_LCD_CLASS_DEVICE is not set +CONFIG_BACKLIGHT_CLASS_DEVICE=y +CONFIG_BACKLIGHT_ATMEL_LCDC=y +# CONFIG_BACKLIGHT_GENERIC is not set +CONFIG_SOUND=y +CONFIG_SND=y +CONFIG_SND_SEQUENCER=y +CONFIG_SND_MIXER_OSS=y +CONFIG_SND_PCM_OSS=y +# CONFIG_SND_SUPPORT_OLD_API is not set +# CONFIG_SND_VERBOSE_PROCFS is not set +# CONFIG_SND_DRIVERS is not set +# CONFIG_SND_ARM is not set +CONFIG_SND_ATMEL_AC97C=y +# CONFIG_SND_SPI is not set +CONFIG_SND_USB_AUDIO=m +# CONFIG_USB_HID is not set +CONFIG_USB=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y +CONFIG_USB_DEVICEFS=y +# CONFIG_USB_DEVICE_CLASS is not set +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_ACM=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_ATMEL_USBA=m +CONFIG_USB_ZERO=m +CONFIG_USB_AUDIO=m +CONFIG_USB_ETH=m +CONFIG_USB_ETH_EEM=y +CONFIG_USB_MASS_STORAGE=m +CONFIG_USB_G_SERIAL=m +CONFIG_USB_CDC_COMPOSITE=m +CONFIG_USB_G_MULTI=m +CONFIG_USB_G_MULTI_CDC=y +CONFIG_MMC=y +# CONFIG_MMC_BLOCK_BOUNCE is not set +CONFIG_SDIO_UART=m +CONFIG_MMC_ATMELMCI=y +CONFIG_MMC_ATMELMCI_DMA=y +CONFIG_LEDS_ATMEL_PWM=y +CONFIG_LEDS_GPIO=y +CONFIG_LEDS_TRIGGER_TIMER=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +CONFIG_LEDS_TRIGGER_GPIO=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_AT91RM9200=y +CONFIG_DMADEVICES=y +CONFIG_AT_HDMAC=y +CONFIG_DMATEST=m +# CONFIG_IOMMU_SUPPORT is not set +CONFIG_EXT2_FS=y +CONFIG_FANOTIFY=y +CONFIG_VFAT_FS=y +CONFIG_TMPFS=y +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_SUMMARY=y +CONFIG_CRAMFS=m +CONFIG_SQUASHFS=m +CONFIG_SQUASHFS_EMBEDDED=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_CODEPAGE_850=y +CONFIG_NLS_ISO8859_1=y +CONFIG_STRIP_ASM_SYMS=y +# CONFIG_SCHED_DEBUG is not set +CONFIG_DEBUG_MEMORY_INIT=y +# CONFIG_FTRACE is not set +CONFIG_DEBUG_USER=y +CONFIG_CRYPTO_ECB=y +# CONFIG_CRYPTO_ANSI_CPRNG is not set +CONFIG_CRYPTO_USER_API_HASH=m +CONFIG_CRYPTO_USER_API_SKCIPHER=m +# CONFIG_CRYPTO_HW is not set -- cgit v0.10.2 From ba4a90a6d86a428c295775b46e653ab8f8e459b8 Mon Sep 17 00:00:00 2001 From: Eric Miao Date: Sun, 11 Sep 2011 17:19:11 +0800 Subject: ARM: pxa/z2: fix building error of pxa27x_cpu_suspend() no longer available Cc: Vasily Khoruzhick Acked-by: Arnd Bergmann Signed-off-by: Eric Miao diff --git a/arch/arm/mach-pxa/include/mach/pxa27x.h b/arch/arm/mach-pxa/include/mach/pxa27x.h index b9b1bdc..7cff640 100644 --- a/arch/arm/mach-pxa/include/mach/pxa27x.h +++ b/arch/arm/mach-pxa/include/mach/pxa27x.h @@ -1,6 +1,7 @@ #ifndef __MACH_PXA27x_H #define __MACH_PXA27x_H +#include #include #include #include @@ -21,6 +22,7 @@ extern void __init pxa27x_map_io(void); extern void __init pxa27x_init_irq(void); extern int __init pxa27x_set_pwrmode(unsigned int mode); +extern void pxa27x_cpu_pm_enter(suspend_state_t state); #define pxa27x_handle_irq ichp_handle_irq diff --git a/arch/arm/mach-pxa/z2.c b/arch/arm/mach-pxa/z2.c index 6c9275a..a82d420 100644 --- a/arch/arm/mach-pxa/z2.c +++ b/arch/arm/mach-pxa/z2.c @@ -686,7 +686,8 @@ static void z2_power_off(void) */ PSPR = 0x0; local_irq_disable(); - pxa27x_cpu_suspend(PWRMODE_DEEPSLEEP, PLAT_PHYS_OFFSET - PAGE_OFFSET); + pxa27x_set_pwrmode(PWRMODE_DEEPSLEEP); + pxa27x_cpu_pm_enter(PM_SUSPEND_MEM); } #else #define z2_power_off NULL -- cgit v0.10.2 From ec13592060ed809c5d6af50f2fcc0b4cc18e3f77 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Sat, 1 Oct 2011 22:03:37 +0200 Subject: ARM: pxa: make zylonite_pxa*_init declaration match code When support for zylonite is disabled, the zylonite_pxa300_init and zylonite_pxa320_init functions are not there, but the declaration is still kept around if any other boards for the same soc are enabled. This changes the declaration to be conditional on the same symbol as the code. Signed-off-by: Arnd Bergmann Signed-off-by: Eric Miao diff --git a/arch/arm/mach-pxa/include/mach/zylonite.h b/arch/arm/mach-pxa/include/mach/zylonite.h index ea24998..ecca976 100644 --- a/arch/arm/mach-pxa/include/mach/zylonite.h +++ b/arch/arm/mach-pxa/include/mach/zylonite.h @@ -19,7 +19,7 @@ extern int wm9713_irq; extern int lcd_id; extern int lcd_orientation; -#ifdef CONFIG_CPU_PXA300 +#ifdef CONFIG_MACH_ZYLONITE300 extern void zylonite_pxa300_init(void); #else static inline void zylonite_pxa300_init(void) @@ -29,7 +29,7 @@ static inline void zylonite_pxa300_init(void) } #endif -#ifdef CONFIG_CPU_PXA320 +#ifdef CONFIG_MACH_ZYLONITE320 extern void zylonite_pxa320_init(void); #else static inline void zylonite_pxa320_init(void) -- cgit v0.10.2 From 145580388b43b4ad549d0621f42bed4e3960537e Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Sat, 1 Oct 2011 22:03:41 +0200 Subject: ARM: pxa: export symbols from pxa3xx-ulpi The pxa3xx_u2d_start_hc/pxa3xx_u2d_stop_hc symbols are used by the ohci-pxa27x driver, which can be a module. Signed-off-by: Arnd Bergmann Cc: Igor Grinberg Signed-off-by: Eric Miao diff --git a/arch/arm/mach-pxa/pxa3xx-ulpi.c b/arch/arm/mach-pxa/pxa3xx-ulpi.c index ce7168b..e28dfb8 100644 --- a/arch/arm/mach-pxa/pxa3xx-ulpi.c +++ b/arch/arm/mach-pxa/pxa3xx-ulpi.c @@ -265,6 +265,7 @@ int pxa3xx_u2d_start_hc(struct usb_bus *host) return err; } +EXPORT_SYMBOL_GPL(pxa3xx_u2d_start_hc); void pxa3xx_u2d_stop_hc(struct usb_bus *host) { @@ -277,6 +278,7 @@ void pxa3xx_u2d_stop_hc(struct usb_bus *host) clk_disable(u2d->clk); } +EXPORT_SYMBOL_GPL(pxa3xx_u2d_stop_hc); static int pxa3xx_u2d_probe(struct platform_device *pdev) { -- cgit v0.10.2 From 0c82cc5d726a9d0a96220dc77a073927086e3852 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Sat, 1 Oct 2011 22:03:42 +0200 Subject: ARM: pxa: allow selecting just one of TREO680/CENTRO There are two variants of the palmtreo machine, the 680 and the centro, and Kconfig allows selecting one or both of them. This changes the board file so that it's actually possible to build all configurations that are allowed. Signed-off-by: Arnd Bergmann Cc: Marek Vasut Signed-off-by: Eric Miao diff --git a/arch/arm/mach-pxa/palmtreo.c b/arch/arm/mach-pxa/palmtreo.c index bb27d4b..30364b0 100644 --- a/arch/arm/mach-pxa/palmtreo.c +++ b/arch/arm/mach-pxa/palmtreo.c @@ -423,6 +423,7 @@ static void __init palmphone_common_init(void) palmtreo_leds_init(); } +#ifdef CONFIG_MACH_TREO680 static void __init treo680_init(void) { pxa2xx_mfp_config(ARRAY_AND_SIZE(treo680_pin_config)); @@ -430,7 +431,9 @@ static void __init treo680_init(void) palm27x_mmc_init(GPIO_NR_TREO_SD_DETECT_N, GPIO_NR_TREO680_SD_READONLY, GPIO_NR_TREO680_SD_POWER, 0); } +#endif +#ifdef CONFIG_MACH_CENTRO static void __init centro_init(void) { pxa2xx_mfp_config(ARRAY_AND_SIZE(centro685_pin_config)); @@ -438,7 +441,9 @@ static void __init centro_init(void) palm27x_mmc_init(GPIO_NR_TREO_SD_DETECT_N, -1, GPIO_NR_CENTRO_SD_POWER, 1); } +#endif +#ifdef CONFIG_MACH_TREO680 MACHINE_START(TREO680, "Palm Treo 680") .boot_params = 0xa0000100, .map_io = pxa27x_map_io, @@ -448,7 +453,9 @@ MACHINE_START(TREO680, "Palm Treo 680") .timer = &pxa_timer, .init_machine = treo680_init, MACHINE_END +#endif +#ifdef CONFIG_MACH_CENTRO MACHINE_START(CENTRO, "Palm Centro 685") .boot_params = 0xa0000100, .map_io = pxa27x_map_io, @@ -458,3 +465,4 @@ MACHINE_START(CENTRO, "Palm Centro 685") .timer = &pxa_timer, .init_machine = centro_init, MACHINE_END +#endif -- cgit v0.10.2 From 654a60e0b4ae8a89f96513d2f02b136e1a6bc509 Mon Sep 17 00:00:00 2001 From: Eric Miao Date: Fri, 7 Oct 2011 15:28:29 +0800 Subject: ARM: pxa: pxa95x/saarb depends on pxa3xx code saarb uses pxa3xx_map_io and pxa3xx_handle_irq, which are part of the pxa3xx code. This makes sure the necessary header and implementation is used when building the board file. Signed-off-by: Arnd Bergmann Signed-off-by: Eric Miao diff --git a/arch/arm/mach-pxa/Makefile b/arch/arm/mach-pxa/Makefile index cc39d17..be0f7df 100644 --- a/arch/arm/mach-pxa/Makefile +++ b/arch/arm/mach-pxa/Makefile @@ -19,7 +19,7 @@ endif obj-$(CONFIG_PXA25x) += mfp-pxa2xx.o clock-pxa2xx.o pxa2xx.o pxa25x.o obj-$(CONFIG_PXA27x) += mfp-pxa2xx.o clock-pxa2xx.o pxa2xx.o pxa27x.o obj-$(CONFIG_PXA3xx) += mfp-pxa3xx.o clock-pxa3xx.o pxa3xx.o smemc.o pxa3xx-ulpi.o -obj-$(CONFIG_PXA95x) += mfp-pxa3xx.o clock-pxa3xx.o pxa95x.o smemc.o +obj-$(CONFIG_PXA95x) += mfp-pxa3xx.o clock-pxa3xx.o pxa3xx.o pxa95x.o smemc.o obj-$(CONFIG_CPU_PXA300) += pxa300.o obj-$(CONFIG_CPU_PXA320) += pxa320.o obj-$(CONFIG_CPU_PXA930) += pxa930.o diff --git a/arch/arm/mach-pxa/include/mach/pxa95x.h b/arch/arm/mach-pxa/include/mach/pxa95x.h new file mode 100644 index 0000000..cbb097c --- /dev/null +++ b/arch/arm/mach-pxa/include/mach/pxa95x.h @@ -0,0 +1,7 @@ +#ifndef __MACH_PXA95X_H +#define __MACH_PXA95X_H + +#include +#include + +#endif /* __MACH_PXA95X_H */ diff --git a/arch/arm/mach-pxa/saarb.c b/arch/arm/mach-pxa/saarb.c index ebd6379..aebd5d9 100644 --- a/arch/arm/mach-pxa/saarb.c +++ b/arch/arm/mach-pxa/saarb.c @@ -21,9 +21,8 @@ #include #include -#include -#include #include +#include #include "generic.h" -- cgit v0.10.2 From ca7d156e30766d7ad3d92a31a672c72c29a19825 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Sat, 1 Oct 2011 22:03:51 +0200 Subject: ARM: pxa: CPU_FREQ_TABLE is needed for CPU_FREQ The pxa specific cpufreq code is based on the cpu_freq_table module, so we have to select that. Signed-off-by: Arnd Bergmann Signed-off-by: Eric Miao diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 3146ed3..e1050a7 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1953,6 +1953,7 @@ config CPU_FREQ_PXA bool depends on CPU_FREQ && ARCH_PXA && PXA25x default y + select CPU_FREQ_TABLE select CPU_FREQ_DEFAULT_GOV_USERSPACE config CPU_FREQ_S3C -- cgit v0.10.2 From 59efd93f64c516dcf959c2c5c53bde6bc48f5f38 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Sat, 1 Oct 2011 22:03:49 +0200 Subject: ARM: pxa: pxa95x is incompatible with earlier pxa We cannot support ARMv5 and ARMv7 based boards in a single kernel, so introduce a new option in mach-pxa to select between the two. The PJ4 (ARMv7) based boards are now only visible when CONFIG_ARCH_PXA_V7 is set, the other boards are only visible when it's not set. Signed-off-by: Arnd Bergmann Signed-off-by: Eric Miao diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig index cd19309..bb310d0 100644 --- a/arch/arm/mach-pxa/Kconfig +++ b/arch/arm/mach-pxa/Kconfig @@ -2,6 +2,27 @@ if ARCH_PXA menu "Intel PXA2xx/PXA3xx Implementations" +config ARCH_PXA_V7 + bool "ARMv7 (PXA95x) based systems" + +if ARCH_PXA_V7 +comment "Marvell Dev Platforms (sorted by hardware release time)" +config MACH_TAVOREVB3 + bool "PXA95x Development Platform (aka TavorEVB III)" + select CPU_PXA955 + +config MACH_SAARB + bool "PXA955 Handheld Platform (aka SAARB)" + select CPU_PXA955 +endif + +config PXA_V7_MACH_AUTO + def_bool y + depends on ARCH_PXA_V7 + depends on !MACH_SAARB + select MACH_TAVOREVB3 + +if !ARCH_PXA_V7 comment "Intel/Marvell Dev Platforms (sorted by hardware release time)" config ARCH_LUBBOCK @@ -41,19 +62,11 @@ config MACH_TAVOREVB select PXA3xx select CPU_PXA930 -config MACH_TAVOREVB3 - bool "PXA95x Development Platform (aka TavorEVB III)" - select CPU_PXA950 - config MACH_SAAR bool "PXA930 Handheld Platform (aka SAAR)" select PXA3xx select CPU_PXA930 -config MACH_SAARB - bool "PXA955 Handheld Platform (aka SAARB)" - select CPU_PXA955 - comment "Third Party Dev Platforms (sorted by vendor name)" config ARCH_PXA_IDP @@ -598,7 +611,7 @@ config MACH_ZIPIT2 bool "Zipit Z2 Handheld" select PXA27x select HAVE_PWM - +endif endmenu config PXA25x -- cgit v0.10.2 From 8582643a4b2fb9582eb30e1128a509198afe3c74 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Sat, 1 Oct 2011 22:03:53 +0200 Subject: ARM: pxa: select POWER_SUPPLY on raumfeld The raumfeld platform code calls power_supply_set_battery_charged which is part of the power supply layer, so that always has to be enabled. Signed-off-by: Arnd Bergmann Signed-off-by: Eric Miao diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig index bb310d0..ee963e0 100644 --- a/arch/arm/mach-pxa/Kconfig +++ b/arch/arm/mach-pxa/Kconfig @@ -449,15 +449,18 @@ config MACH_RAUMFELD_RC bool "Raumfeld Controller" select PXA3xx select CPU_PXA300 + select POWER_SUPPLY select HAVE_PWM config MACH_RAUMFELD_CONNECTOR bool "Raumfeld Connector" + select POWER_SUPPLY select PXA3xx select CPU_PXA300 config MACH_RAUMFELD_SPEAKER bool "Raumfeld Speaker" + select POWER_SUPPLY select PXA3xx select CPU_PXA300 -- cgit v0.10.2 From c9d1917c63274e70958a7e2e8c874c1bca15af0a Mon Sep 17 00:00:00 2001 From: Eric Miao Date: Sat, 8 Oct 2011 18:19:23 +0800 Subject: ARM: pxa: make pxafb_smart_*() empty when not enabled Reported-by: Arnd Bergmann Signed-off-by: Eric Miao diff --git a/arch/arm/mach-pxa/include/mach/pxafb.h b/arch/arm/mach-pxa/include/mach/pxafb.h index 01a45ac4..486b4c5 100644 --- a/arch/arm/mach-pxa/include/mach/pxafb.h +++ b/arch/arm/mach-pxa/include/mach/pxafb.h @@ -158,5 +158,18 @@ struct pxafb_mach_info { void pxa_set_fb_info(struct device *, struct pxafb_mach_info *); unsigned long pxafb_get_hsync_time(struct device *dev); +#ifdef CONFIG_FB_PXA_SMARTPANEL extern int pxafb_smart_queue(struct fb_info *info, uint16_t *cmds, int); extern int pxafb_smart_flush(struct fb_info *info); +#else +static inline int pxafb_smart_queue(struct fb_info *info, + uint16_t *cmds, int n) +{ + return 0; +} + +static inline int pxafb_smart_flush(struct fb_info *info) +{ + return 0; +} +#endif diff --git a/drivers/video/pxafb.c b/drivers/video/pxafb.c index 0f4e8c9..389530b 100644 --- a/drivers/video/pxafb.c +++ b/drivers/video/pxafb.c @@ -1309,16 +1309,6 @@ static int pxafb_smart_init(struct pxafb_info *fbi) return 0; } #else -int pxafb_smart_queue(struct fb_info *info, uint16_t *cmds, int n_cmds) -{ - return 0; -} - -int pxafb_smart_flush(struct fb_info *info) -{ - return 0; -} - static inline int pxafb_smart_init(struct pxafb_info *fbi) { return 0; } #endif /* CONFIG_FB_PXA_SMARTPANEL */ -- cgit v0.10.2 From 41f91d90ec6d12d7f3edee2b86ecd7c2c2b0e063 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Sat, 1 Oct 2011 22:03:56 +0200 Subject: ARM: pxa: centro and treo680 need palm27x The two platforms are part of the palm27x family and use the same code. Select the palm27x symbol to make sure they can be built standalone. Signed-off-by: Arnd Bergmann Signed-off-by: Eric Miao diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig index ee963e0..e435b25 100644 --- a/arch/arm/mach-pxa/Kconfig +++ b/arch/arm/mach-pxa/Kconfig @@ -427,6 +427,7 @@ config MACH_CENTRO bool "Palm Centro 685 (GSM)" default y depends on ARCH_PXA_PALM + select MACH_PALM27X select PXA27x select IWMMXT select PALM_TREO @@ -438,6 +439,7 @@ config MACH_TREO680 bool "Palm Treo 680" default y depends on ARCH_PXA_PALM + select MACH_PALM27X select PXA27x select IWMMXT select PALM_TREO -- cgit v0.10.2 From 7272889d3f40ed6aa2ade32bed5834789b3299cc Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Sat, 1 Oct 2011 22:03:58 +0200 Subject: ARM: pxa: sharpsl pm needs SPI The sharpsl code selects the max1111 spi driver, so it must also ensure that SPI itself is enabled. The platform does not work without max1111. Signed-off-by: Arnd Bergmann Signed-off-by: Eric Miao diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig index e435b25..61d3c72 100644 --- a/arch/arm/mach-pxa/Kconfig +++ b/arch/arm/mach-pxa/Kconfig @@ -706,6 +706,8 @@ config SHARPSL_PM config SHARPSL_PM_MAX1111 bool select HWMON + select SPI + select SPI_MASTER select SENSORS_MAX1111 config PXA_HAVE_ISA_IRQS -- cgit v0.10.2 From 97b09da4ee36ec4bd0f6e16b84b4bb6fa05db110 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Sat, 1 Oct 2011 22:03:45 +0200 Subject: ARM: pxa: use correct __iomem annotations This tries to clear up the confusion between integers and iomem pointers in the marvell pxa platform. MMIO addresses are supposed to be __iomem* values, in order to let the Linux type checking work correctly. This patch moves the cast to __iomem as far back as possible, to the place where the MMIO virtual address windows are defined. Signed-off-by: Arnd Bergmann Signed-off-by: Eric Miao diff --git a/arch/arm/include/asm/hardware/it8152.h b/arch/arm/include/asm/hardware/it8152.h index b3fea38..43cab49 100644 --- a/arch/arm/include/asm/hardware/it8152.h +++ b/arch/arm/include/asm/hardware/it8152.h @@ -9,7 +9,7 @@ #ifndef __ASM_HARDWARE_IT8152_H #define __ASM_HARDWARE_IT8152_H -extern unsigned long it8152_base_address; +extern void __iomem *it8152_base_address; #define IT8152_IO_BASE (it8152_base_address + 0x03e00000) #define IT8152_CFGREG_BASE (it8152_base_address + 0x03f00000) diff --git a/arch/arm/mach-mmp/clock.h b/arch/arm/mach-mmp/clock.h index 3143e99..149b30c 100644 --- a/arch/arm/mach-mmp/clock.h +++ b/arch/arm/mach-mmp/clock.h @@ -30,7 +30,7 @@ extern struct clkops apmu_clk_ops; #define APBC_CLK(_name, _reg, _fnclksel, _rate) \ struct clk clk_##_name = { \ - .clk_rst = (void __iomem *)APBC_##_reg, \ + .clk_rst = APBC_##_reg, \ .fnclksel = _fnclksel, \ .rate = _rate, \ .ops = &apbc_clk_ops, \ @@ -38,7 +38,7 @@ struct clk clk_##_name = { \ #define APBC_CLK_OPS(_name, _reg, _fnclksel, _rate, _ops) \ struct clk clk_##_name = { \ - .clk_rst = (void __iomem *)APBC_##_reg, \ + .clk_rst = APBC_##_reg, \ .fnclksel = _fnclksel, \ .rate = _rate, \ .ops = _ops, \ @@ -46,7 +46,7 @@ struct clk clk_##_name = { \ #define APMU_CLK(_name, _reg, _eval, _rate) \ struct clk clk_##_name = { \ - .clk_rst = (void __iomem *)APMU_##_reg, \ + .clk_rst = APMU_##_reg, \ .enable_val = _eval, \ .rate = _rate, \ .ops = &apmu_clk_ops, \ @@ -54,7 +54,7 @@ struct clk clk_##_name = { \ #define APMU_CLK_OPS(_name, _reg, _eval, _rate, _ops) \ struct clk clk_##_name = { \ - .clk_rst = (void __iomem *)APMU_##_reg, \ + .clk_rst = APMU_##_reg, \ .enable_val = _eval, \ .rate = _rate, \ .ops = _ops, \ diff --git a/arch/arm/mach-mmp/common.c b/arch/arm/mach-mmp/common.c index 0ec0ca8..5720674 100644 --- a/arch/arm/mach-mmp/common.c +++ b/arch/arm/mach-mmp/common.c @@ -27,12 +27,12 @@ EXPORT_SYMBOL(mmp_chip_id); static struct map_desc standard_io_desc[] __initdata = { { .pfn = __phys_to_pfn(APB_PHYS_BASE), - .virtual = APB_VIRT_BASE, + .virtual = (unsigned long)APB_VIRT_BASE, .length = APB_PHYS_SIZE, .type = MT_DEVICE, }, { .pfn = __phys_to_pfn(AXI_PHYS_BASE), - .virtual = AXI_VIRT_BASE, + .virtual = (unsigned long)AXI_VIRT_BASE, .length = AXI_PHYS_SIZE, .type = MT_DEVICE, }, diff --git a/arch/arm/mach-mmp/include/mach/addr-map.h b/arch/arm/mach-mmp/include/mach/addr-map.h index 3254089..3e404ac 100644 --- a/arch/arm/mach-mmp/include/mach/addr-map.h +++ b/arch/arm/mach-mmp/include/mach/addr-map.h @@ -11,6 +11,12 @@ #ifndef __ASM_MACH_ADDR_MAP_H #define __ASM_MACH_ADDR_MAP_H +#ifndef __ASSEMBLER__ +#define IOMEM(x) ((void __iomem *)(x)) +#else +#define IOMEM(x) (x) +#endif + /* APB - Application Subsystem Peripheral Bus * * NOTE: the DMA controller registers are actually on the AXI fabric #1 @@ -18,11 +24,11 @@ * peripherals on APB, let's count it into the ABP mapping area. */ #define APB_PHYS_BASE 0xd4000000 -#define APB_VIRT_BASE 0xfe000000 +#define APB_VIRT_BASE IOMEM(0xfe000000) #define APB_PHYS_SIZE 0x00200000 #define AXI_PHYS_BASE 0xd4200000 -#define AXI_VIRT_BASE 0xfe200000 +#define AXI_VIRT_BASE IOMEM(0xfe200000) #define AXI_PHYS_SIZE 0x00200000 /* Static Memory Controller - Chip Select 0 and 1 */ diff --git a/arch/arm/mach-mmp/mmp2.c b/arch/arm/mach-mmp/mmp2.c index 079c188..a80cbea 100644 --- a/arch/arm/mach-mmp/mmp2.c +++ b/arch/arm/mach-mmp/mmp2.c @@ -87,7 +87,8 @@ static struct mfp_addr_map mmp2_addr_map[] __initdata = { void mmp2_clear_pmic_int(void) { - unsigned long mfpr_pmic, data; + void __iomem *mfpr_pmic; + unsigned long data; mfpr_pmic = APB_VIRT_BASE + 0x1e000 + 0x2c4; data = __raw_readl(mfpr_pmic); diff --git a/arch/arm/mach-pxa/balloon3.c b/arch/arm/mach-pxa/balloon3.c index ef3e8b1..d0f1411 100644 --- a/arch/arm/mach-pxa/balloon3.c +++ b/arch/arm/mach-pxa/balloon3.c @@ -591,7 +591,7 @@ static void balloon3_nand_cmd_ctl(struct mtd_info *mtd, int cmd, unsigned int ct BALLOON3_NAND_CONTROL_REG); if (balloon3_ctl_set) __raw_writel(balloon3_ctl_set, - BALLOON3_NAND_CONTROL_REG | + BALLOON3_NAND_CONTROL_REG + BALLOON3_FPGA_SETnCLR); } @@ -608,7 +608,7 @@ static void balloon3_nand_select_chip(struct mtd_info *mtd, int chip) __raw_writew( BALLOON3_NAND_CONTROL_FLCE0 | BALLOON3_NAND_CONTROL_FLCE1 | BALLOON3_NAND_CONTROL_FLCE2 | BALLOON3_NAND_CONTROL_FLCE3, - BALLOON3_NAND_CONTROL_REG | BALLOON3_FPGA_SETnCLR); + BALLOON3_NAND_CONTROL_REG + BALLOON3_FPGA_SETnCLR); /* Deassert correct nCE line */ __raw_writew(BALLOON3_NAND_CONTROL_FLCE0 << chip, @@ -626,7 +626,7 @@ static int balloon3_nand_probe(struct platform_device *pdev) int ret; __raw_writew(BALLOON3_NAND_CONTROL2_16BIT, - BALLOON3_NAND_CONTROL2_REG | BALLOON3_FPGA_SETnCLR); + BALLOON3_NAND_CONTROL2_REG + BALLOON3_FPGA_SETnCLR); ver = __raw_readw(BALLOON3_FPGA_VER); if (ver < 0x4f08) @@ -649,7 +649,7 @@ static int balloon3_nand_probe(struct platform_device *pdev) BALLOON3_NAND_CONTROL_FLCE0 | BALLOON3_NAND_CONTROL_FLCE1 | BALLOON3_NAND_CONTROL_FLCE2 | BALLOON3_NAND_CONTROL_FLCE3 | BALLOON3_NAND_CONTROL_FLWP, - BALLOON3_NAND_CONTROL_REG | BALLOON3_FPGA_SETnCLR); + BALLOON3_NAND_CONTROL_REG + BALLOON3_FPGA_SETnCLR); return 0; err2: @@ -807,7 +807,7 @@ static void __init balloon3_init(void) static struct map_desc balloon3_io_desc[] __initdata = { { /* CPLD/FPGA */ - .virtual = BALLOON3_FPGA_VIRT, + .virtual = (unsigned long)BALLOON3_FPGA_VIRT, .pfn = __phys_to_pfn(BALLOON3_FPGA_PHYS), .length = BALLOON3_FPGA_LENGTH, .type = MT_DEVICE, diff --git a/arch/arm/mach-pxa/cm-x2xx-pci.c b/arch/arm/mach-pxa/cm-x2xx-pci.c index 6bf479d..ebd9259 100644 --- a/arch/arm/mach-pxa/cm-x2xx-pci.c +++ b/arch/arm/mach-pxa/cm-x2xx-pci.c @@ -26,7 +26,7 @@ #include -unsigned long it8152_base_address; +void __iomem *it8152_base_address; static int cmx2xx_it8152_irq_gpio; static void cmx2xx_it8152_irq_demux(unsigned int irq, struct irq_desc *desc) diff --git a/arch/arm/mach-pxa/cm-x2xx.c b/arch/arm/mach-pxa/cm-x2xx.c index 13cf518..4f07e16 100644 --- a/arch/arm/mach-pxa/cm-x2xx.c +++ b/arch/arm/mach-pxa/cm-x2xx.c @@ -39,7 +39,7 @@ extern void cmx270_init(void); #define CMX2XX_NR_IRQS (IRQ_BOARD_START + 40) /* virtual addresses for statically mapped regions */ -#define CMX2XX_VIRT_BASE (0xe8000000) +#define CMX2XX_VIRT_BASE (void __iomem *)(0xe8000000) #define CMX2XX_IT8152_VIRT (CMX2XX_VIRT_BASE) /* physical address if local-bus attached devices */ @@ -482,7 +482,7 @@ static void __init cmx2xx_init_irq(void) /* Map PCI companion statically */ static struct map_desc cmx2xx_io_desc[] __initdata = { [0] = { /* PCI bridge */ - .virtual = CMX2XX_IT8152_VIRT, + .virtual = (unsigned long)CMX2XX_IT8152_VIRT, .pfn = __phys_to_pfn(PXA_CS4_PHYS), .length = SZ_64M, .type = MT_DEVICE diff --git a/arch/arm/mach-pxa/include/mach/addr-map.h b/arch/arm/mach-pxa/include/mach/addr-map.h index f4c0365..bbf9df3 100644 --- a/arch/arm/mach-pxa/include/mach/addr-map.h +++ b/arch/arm/mach-pxa/include/mach/addr-map.h @@ -20,7 +20,7 @@ * Peripheral Bus */ #define PERIPH_PHYS 0x40000000 -#define PERIPH_VIRT 0xf2000000 +#define PERIPH_VIRT IOMEM(0xf2000000) #define PERIPH_SIZE 0x02000000 /* @@ -28,21 +28,21 @@ */ #define PXA2XX_SMEMC_PHYS 0x48000000 #define PXA3XX_SMEMC_PHYS 0x4a000000 -#define SMEMC_VIRT 0xf6000000 +#define SMEMC_VIRT IOMEM(0xf6000000) #define SMEMC_SIZE 0x00100000 /* * Dynamic Memory Controller (only on PXA3xx) */ #define DMEMC_PHYS 0x48100000 -#define DMEMC_VIRT 0xf6100000 +#define DMEMC_VIRT IOMEM(0xf6100000) #define DMEMC_SIZE 0x00100000 /* * Internal Memory Controller (PXA27x and later) */ #define IMEMC_PHYS 0x58000000 -#define IMEMC_VIRT 0xfe000000 +#define IMEMC_VIRT IOMEM(0xfe000000) #define IMEMC_SIZE 0x00100000 #endif /* __ASM_MACH_ADDR_MAP_H */ diff --git a/arch/arm/mach-pxa/include/mach/balloon3.h b/arch/arm/mach-pxa/include/mach/balloon3.h index 7074e76..6d7eab3 100644 --- a/arch/arm/mach-pxa/include/mach/balloon3.h +++ b/arch/arm/mach-pxa/include/mach/balloon3.h @@ -23,7 +23,7 @@ enum balloon3_features { }; #define BALLOON3_FPGA_PHYS PXA_CS4_PHYS -#define BALLOON3_FPGA_VIRT (0xf1000000) /* as per balloon2 */ +#define BALLOON3_FPGA_VIRT IOMEM(0xf1000000) /* as per balloon2 */ #define BALLOON3_FPGA_LENGTH 0x01000000 #define BALLOON3_FPGA_SETnCLR (0x1000) diff --git a/arch/arm/mach-pxa/include/mach/hardware.h b/arch/arm/mach-pxa/include/mach/hardware.h index de63ca3..8184669 100644 --- a/arch/arm/mach-pxa/include/mach/hardware.h +++ b/arch/arm/mach-pxa/include/mach/hardware.h @@ -36,22 +36,23 @@ * Note that not all PXA2xx chips implement all those addresses, and the * kernel only maps the minimum needed range of this mapping. */ -#define io_p2v(x) (0xf2000000 + ((x) & 0x01ffffff) + (((x) & 0x1c000000) >> 1)) #define io_v2p(x) (0x3c000000 + ((x) & 0x01ffffff) + (((x) & 0x0e000000) << 1)) +#define io_p2v(x) IOMEM(0xf2000000 + ((x) & 0x01ffffff) + (((x) & 0x1c000000) >> 1)) #ifndef __ASSEMBLY__ - -# define __REG(x) (*((volatile u32 *)io_p2v(x))) +# define IOMEM(x) ((void __iomem *)(x)) +# define __REG(x) (*((volatile u32 __iomem *)io_p2v(x))) /* With indexed regs we don't want to feed the index through io_p2v() especially if it is a variable, otherwise horrible code will result. */ # define __REG2(x,y) \ - (*(volatile u32 *)((u32)&__REG(x) + (y))) + (*(volatile u32 __iomem*)((u32)&__REG(x) + (y))) # define __PREG(x) (io_v2p((u32)&(x))) #else +# define IOMEM(x) x # define __REG(x) io_p2v(x) # define __PREG(x) io_v2p(x) diff --git a/arch/arm/mach-pxa/include/mach/lpd270.h b/arch/arm/mach-pxa/include/mach/lpd270.h index cd07009..4edc712 100644 --- a/arch/arm/mach-pxa/include/mach/lpd270.h +++ b/arch/arm/mach-pxa/include/mach/lpd270.h @@ -13,13 +13,13 @@ #define __ASM_ARCH_LPD270_H #define LPD270_CPLD_PHYS PXA_CS2_PHYS -#define LPD270_CPLD_VIRT 0xf0000000 +#define LPD270_CPLD_VIRT IOMEM(0xf0000000) #define LPD270_CPLD_SIZE 0x00100000 #define LPD270_ETH_PHYS (PXA_CS2_PHYS + 0x01000000) /* CPLD registers */ -#define LPD270_CPLD_REG(x) ((unsigned long)(LPD270_CPLD_VIRT + (x))) +#define LPD270_CPLD_REG(x) (LPD270_CPLD_VIRT + (x)) #define LPD270_CONTROL LPD270_CPLD_REG(0x00) #define LPD270_PERIPHERAL0 LPD270_CPLD_REG(0x04) #define LPD270_PERIPHERAL1 LPD270_CPLD_REG(0x08) diff --git a/arch/arm/mach-pxa/include/mach/mtd-xip.h b/arch/arm/mach-pxa/include/mach/mtd-xip.h index 297387e..990d2bf 100644 --- a/arch/arm/mach-pxa/include/mach/mtd-xip.h +++ b/arch/arm/mach-pxa/include/mach/mtd-xip.h @@ -16,7 +16,6 @@ #define __ARCH_PXA_MTD_XIP_H__ #include -#include #define xip_irqpending() (ICIP & ICMR) diff --git a/arch/arm/mach-pxa/include/mach/palmtx.h b/arch/arm/mach-pxa/include/mach/palmtx.h index 10abc4f..7074a6e 100644 --- a/arch/arm/mach-pxa/include/mach/palmtx.h +++ b/arch/arm/mach-pxa/include/mach/palmtx.h @@ -71,7 +71,7 @@ /* Various addresses */ #define PALMTX_PCMCIA_PHYS 0x28000000 -#define PALMTX_PCMCIA_VIRT 0xf0000000 +#define PALMTX_PCMCIA_VIRT IOMEM(0xf0000000) #define PALMTX_PCMCIA_SIZE 0x100000 #define PALMTX_PHYS_RAM_START 0xa0000000 @@ -84,8 +84,8 @@ #define PALMTX_NAND_ALE_PHYS (PALMTX_PHYS_NAND_START | (1 << 24)) #define PALMTX_NAND_CLE_PHYS (PALMTX_PHYS_NAND_START | (1 << 25)) -#define PALMTX_NAND_ALE_VIRT 0xff100000 -#define PALMTX_NAND_CLE_VIRT 0xff200000 +#define PALMTX_NAND_ALE_VIRT IOMEM(0xff100000) +#define PALMTX_NAND_CLE_VIRT IOMEM(0xff200000) /* TOUCHSCREEN */ #define AC97_LINK_FRAME 21 diff --git a/arch/arm/mach-pxa/include/mach/smemc.h b/arch/arm/mach-pxa/include/mach/smemc.h index 654adc9..b7de471 100644 --- a/arch/arm/mach-pxa/include/mach/smemc.h +++ b/arch/arm/mach-pxa/include/mach/smemc.h @@ -13,7 +13,7 @@ #define PXA2XX_SMEMC_BASE 0x48000000 #define PXA3XX_SMEMC_BASE 0x4a000000 -#define SMEMC_VIRT 0xf6000000 +#define SMEMC_VIRT IOMEM(0xf6000000) #define MDCNFG (SMEMC_VIRT + 0x00) /* SDRAM Configuration Register 0 */ #define MDREFR (SMEMC_VIRT + 0x04) /* SDRAM Refresh Control Register */ diff --git a/arch/arm/mach-pxa/include/mach/zeus.h b/arch/arm/mach-pxa/include/mach/zeus.h index 0641f31..56024f8 100644 --- a/arch/arm/mach-pxa/include/mach/zeus.h +++ b/arch/arm/mach-pxa/include/mach/zeus.h @@ -68,7 +68,7 @@ * Be gentle, and remap that over 32kB... */ -#define ZEUS_CPLD (0xf0000000) +#define ZEUS_CPLD IOMEM(0xf0000000) #define ZEUS_CPLD_VERSION (ZEUS_CPLD + 0x0000) #define ZEUS_CPLD_ISA_IRQ (ZEUS_CPLD + 0x1000) #define ZEUS_CPLD_CONTROL (ZEUS_CPLD + 0x2000) @@ -76,7 +76,7 @@ /* CPLD register bits */ #define ZEUS_CPLD_CONTROL_CF_RST 0x01 -#define ZEUS_PC104IO (0xf1000000) +#define ZEUS_PC104IO IOMEM(0xf1000000) #define ZEUS_SRAM_SIZE (256 * 1024) diff --git a/arch/arm/mach-pxa/irq.c b/arch/arm/mach-pxa/irq.c index b09e848..fead5c7 100644 --- a/arch/arm/mach-pxa/irq.c +++ b/arch/arm/mach-pxa/irq.c @@ -25,7 +25,7 @@ #include "generic.h" -#define IRQ_BASE (void __iomem *)io_p2v(0x40d00000) +#define IRQ_BASE io_p2v(0x40d00000) #define ICIP (0x000) #define ICMR (0x004) @@ -63,7 +63,7 @@ static inline void __iomem *irq_base(int i) 0x40d00130, }; - return (void __iomem *)io_p2v(phys_base[i]); + return io_p2v(phys_base[i]); } void pxa_mask_irq(struct irq_data *d) diff --git a/arch/arm/mach-pxa/lpd270.c b/arch/arm/mach-pxa/lpd270.c index c171d6e..e30cdc8 100644 --- a/arch/arm/mach-pxa/lpd270.c +++ b/arch/arm/mach-pxa/lpd270.c @@ -480,7 +480,7 @@ static void __init lpd270_init(void) static struct map_desc lpd270_io_desc[] __initdata = { { - .virtual = LPD270_CPLD_VIRT, + .virtual = (unsigned long)LPD270_CPLD_VIRT, .pfn = __phys_to_pfn(LPD270_CPLD_PHYS), .length = LPD270_CPLD_SIZE, .type = MT_DEVICE, diff --git a/arch/arm/mach-pxa/palmtx.c b/arch/arm/mach-pxa/palmtx.c index fc428558..00c318f 100644 --- a/arch/arm/mach-pxa/palmtx.c +++ b/arch/arm/mach-pxa/palmtx.c @@ -247,7 +247,7 @@ static void palmtx_nand_cmd_ctl(struct mtd_info *mtd, int cmd, unsigned int ctrl) { struct nand_chip *this = mtd->priv; - unsigned long nandaddr = (unsigned long)this->IO_ADDR_W; + char __iomem *nandaddr = this->IO_ADDR_W; if (cmd == NAND_CMD_NONE) return; @@ -315,17 +315,17 @@ static inline void palmtx_nand_init(void) {} ******************************************************************************/ static struct map_desc palmtx_io_desc[] __initdata = { { - .virtual = PALMTX_PCMCIA_VIRT, + .virtual = (unsigned long)PALMTX_PCMCIA_VIRT, .pfn = __phys_to_pfn(PALMTX_PCMCIA_PHYS), .length = PALMTX_PCMCIA_SIZE, .type = MT_DEVICE, }, { - .virtual = PALMTX_NAND_ALE_VIRT, + .virtual = (unsigned long)PALMTX_NAND_ALE_VIRT, .pfn = __phys_to_pfn(PALMTX_NAND_ALE_PHYS), .length = SZ_1M, .type = MT_DEVICE, }, { - .virtual = PALMTX_NAND_CLE_VIRT, + .virtual = (unsigned long)PALMTX_NAND_CLE_VIRT, .pfn = __phys_to_pfn(PALMTX_NAND_CLE_PHYS), .length = SZ_1M, .type = MT_DEVICE, diff --git a/arch/arm/mach-pxa/pxa25x.c b/arch/arm/mach-pxa/pxa25x.c index 9c434d2..6c49c7c 100644 --- a/arch/arm/mach-pxa/pxa25x.c +++ b/arch/arm/mach-pxa/pxa25x.c @@ -324,7 +324,7 @@ void __init pxa26x_init_irq(void) static struct map_desc pxa25x_io_desc[] __initdata = { { /* Mem Ctl */ - .virtual = SMEMC_VIRT, + .virtual = (unsigned long)SMEMC_VIRT, .pfn = __phys_to_pfn(PXA2XX_SMEMC_BASE), .length = 0x00200000, .type = MT_DEVICE diff --git a/arch/arm/mach-pxa/pxa27x.c b/arch/arm/mach-pxa/pxa27x.c index 9d2400b..729af54 100644 --- a/arch/arm/mach-pxa/pxa27x.c +++ b/arch/arm/mach-pxa/pxa27x.c @@ -390,7 +390,7 @@ void __init pxa27x_init_irq(void) static struct map_desc pxa27x_io_desc[] __initdata = { { /* Mem Ctl */ - .virtual = SMEMC_VIRT, + .virtual = (unsigned long)SMEMC_VIRT, .pfn = __phys_to_pfn(PXA2XX_SMEMC_BASE), .length = 0x00200000, .type = MT_DEVICE diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c index b5cd9e5..b2479cb 100644 --- a/arch/arm/mach-pxa/pxa3xx.c +++ b/arch/arm/mach-pxa/pxa3xx.c @@ -394,7 +394,7 @@ void __init pxa3xx_init_irq(void) static struct map_desc pxa3xx_io_desc[] __initdata = { { /* Mem Ctl */ - .virtual = SMEMC_VIRT, + .virtual = (unsigned long)SMEMC_VIRT, .pfn = __phys_to_pfn(PXA3XX_SMEMC_BASE), .length = 0x00200000, .type = MT_DEVICE diff --git a/arch/arm/mach-pxa/zeus.c b/arch/arm/mach-pxa/zeus.c index 99c49bc..9188492 100644 --- a/arch/arm/mach-pxa/zeus.c +++ b/arch/arm/mach-pxa/zeus.c @@ -860,25 +860,25 @@ static void __init zeus_init(void) static struct map_desc zeus_io_desc[] __initdata = { { - .virtual = ZEUS_CPLD_VERSION, + .virtual = (unsigned long)ZEUS_CPLD_VERSION, .pfn = __phys_to_pfn(ZEUS_CPLD_VERSION_PHYS), .length = 0x1000, .type = MT_DEVICE, }, { - .virtual = ZEUS_CPLD_ISA_IRQ, + .virtual = (unsigned long)ZEUS_CPLD_ISA_IRQ, .pfn = __phys_to_pfn(ZEUS_CPLD_ISA_IRQ_PHYS), .length = 0x1000, .type = MT_DEVICE, }, { - .virtual = ZEUS_CPLD_CONTROL, + .virtual = (unsigned long)ZEUS_CPLD_CONTROL, .pfn = __phys_to_pfn(ZEUS_CPLD_CONTROL_PHYS), .length = 0x1000, .type = MT_DEVICE, }, { - .virtual = ZEUS_PC104IO, + .virtual = (unsigned long)ZEUS_PC104IO, .pfn = __phys_to_pfn(ZEUS_PC104IO_PHYS), .length = 0x00800000, .type = MT_DEVICE, diff --git a/arch/arm/plat-pxa/gpio.c b/arch/arm/plat-pxa/gpio.c index a11dc36..0db7615 100644 --- a/arch/arm/plat-pxa/gpio.c +++ b/arch/arm/plat-pxa/gpio.c @@ -122,7 +122,7 @@ static int __init pxa_init_gpio_chip(int gpio_end) struct gpio_chip *c = &chips[i].chip; sprintf(chips[i].label, "gpio-%d", i); - chips[i].regbase = (void __iomem *)GPIO_BANK(i); + chips[i].regbase = GPIO_BANK(i); c->base = gpio; c->label = chips[i].label; diff --git a/arch/arm/plat-pxa/include/plat/mfp.h b/arch/arm/plat-pxa/include/plat/mfp.h index 89e68e0..5c79c29 100644 --- a/arch/arm/plat-pxa/include/plat/mfp.h +++ b/arch/arm/plat-pxa/include/plat/mfp.h @@ -456,7 +456,7 @@ struct mfp_addr_map { #define MFP_ADDR_END { MFP_PIN_INVALID, 0 } -void __init mfp_init_base(unsigned long mfpr_base); +void __init mfp_init_base(void __iomem *mfpr_base); void __init mfp_init_addr(struct mfp_addr_map *map); /* diff --git a/arch/arm/plat-pxa/mfp.c b/arch/arm/plat-pxa/mfp.c index be12ead..2c4dbb1 100644 --- a/arch/arm/plat-pxa/mfp.c +++ b/arch/arm/plat-pxa/mfp.c @@ -229,7 +229,7 @@ void mfp_write(int mfp, unsigned long val) spin_unlock_irqrestore(&mfp_spin_lock, flags); } -void __init mfp_init_base(unsigned long mfpr_base) +void __init mfp_init_base(void __iomem *mfpr_base) { int i; @@ -237,7 +237,7 @@ void __init mfp_init_base(unsigned long mfpr_base) for (i = 0; i < ARRAY_SIZE(mfp_table); i++) mfp_table[i].config = -1; - mfpr_mmio_base = (void __iomem *)mfpr_base; + mfpr_mmio_base = mfpr_base; } void __init mfp_init_addr(struct mfp_addr_map *map) diff --git a/drivers/pcmcia/pxa2xx_balloon3.c b/drivers/pcmcia/pxa2xx_balloon3.c index f56d7de..22a75e6 100644 --- a/drivers/pcmcia/pxa2xx_balloon3.c +++ b/drivers/pcmcia/pxa2xx_balloon3.c @@ -97,7 +97,7 @@ static void balloon3_pcmcia_socket_state(struct soc_pcmcia_socket *skt, static int balloon3_pcmcia_configure_socket(struct soc_pcmcia_socket *skt, const socket_state_t *state) { - __raw_writew(BALLOON3_CF_RESET, BALLOON3_CF_CONTROL_REG | + __raw_writew(BALLOON3_CF_RESET, BALLOON3_CF_CONTROL_REG + ((state->flags & SS_RESET) ? BALLOON3_FPGA_SETnCLR : 0)); return 0; diff --git a/drivers/video/mbx/mbxfb.c b/drivers/video/mbx/mbxfb.c index afea9ab..6ce3416 100644 --- a/drivers/video/mbx/mbxfb.c +++ b/drivers/video/mbx/mbxfb.c @@ -34,7 +34,7 @@ #include "regs.h" #include "reg_bits.h" -static unsigned long virt_base_2700; +static void __iomem *virt_base_2700; #define write_reg(val, reg) do { writel((val), (reg)); } while(0) @@ -850,7 +850,7 @@ static int mbxfb_suspend(struct platform_device *dev, pm_message_t state) { /* make frame buffer memory enter self-refresh mode */ write_reg_dly(LMPWR_MC_PWR_SRM, LMPWR); - while (LMPWRSTAT != LMPWRSTAT_MC_PWR_SRM) + while (readl(LMPWRSTAT) != LMPWRSTAT_MC_PWR_SRM) ; /* empty statement */ /* reset the device, since it's initial state is 'mostly sleeping' */ @@ -946,7 +946,7 @@ static int __devinit mbxfb_probe(struct platform_device *dev) ret = -EINVAL; goto err3; } - virt_base_2700 = (unsigned long)mfbi->reg_virt_addr; + virt_base_2700 = mfbi->reg_virt_addr; mfbi->fb_virt_addr = ioremap_nocache(mfbi->fb_phys_addr, res_size(mfbi->fb_req)); -- cgit v0.10.2 From 100aafc992039794d0facb0e7bbd02f8a11fd1d6 Mon Sep 17 00:00:00 2001 From: "Arnaud Patard (Rtp)" Date: Sat, 27 Aug 2011 15:21:12 +0200 Subject: ARM: mx5: fix clock usage for suspend MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit While suspending, we're enabling a clock in ->suspend() but we're in atomic context, leading to this : [30803.667305] PM: late suspend of devices complete after 1.237 msecs [30803.667449] BUG: sleeping function called from invalid context at kernel/mutex.c:271 [30803.667464] in_atomic(): 0, irqs_disabled(): 128, pid: 4941, name: pm-suspend [30803.667474] INFO: lockdep is turned off. [30803.667483] irq event stamp: 0 [30803.667489] hardirqs last enabled at (0): [< (null)>] (null) [30803.667503] hardirqs last disabled at (0): [] copy_process.part.48+0x1e0/0xa7c [30803.667543] softirqs last enabled at (0): [] copy_process.part.48+0x1e0/0xa7c [30803.667562] softirqs last disabled at (0): [< (null)>] (null) [30803.667574] Backtrace: [30803.667611] [] (dump_backtrace+0x0/0x110) from [] (dump_stack+0x18/0x1c) [30803.667624] r6:00000000 r5:00000000 r4:d9648000 r3:d9648000 [30803.667652] [] (dump_stack+0x0/0x1c) from [] (__might_sleep.part.101+0x90/0xa8) [30803.667673] [] (__might_sleep.part.101+0x0/0xa8) from [] (__might_sleep+0x80/0x94) [30803.667686] r4:c05d58c0 [30803.667705] [] (__might_sleep+0x0/0x94) from [] (mutex_lock_nested+0x2c/0x30c) [30803.667735] [] (mutex_lock_nested+0x0/0x30c) from [] (clk_enable+0x28/0x50) [30803.667747] r8:c0438464 r7:00000003 r6:00000000 r5:00000000 r4:c05d2e98 [30803.667780] [] (clk_enable+0x0/0x50) from [] (mx5_suspend_enter+0x1c/0x98) [30803.667792] r4:00000003 r3:c060dfe0 [30803.667821] [] (mx5_suspend_enter+0x0/0x98) from [] (suspend_enter+0xec/0x15c) [30803.667833] r4:00000003 r3:c0017244 [30803.667856] [] (suspend_enter+0x0/0x15c) from [] (suspend_devices_and_enter+0x94/0x130) [30803.667868] r6:00000000 r5:00000003 r4:c0c0af00 r3:00002710 [30803.667897] [] (suspend_devices_and_enter+0x0/0x130) from [] (enter_state+0xc8/0x130) [30803.667909] r6:00000000 r5:00000003 r4:c05286e4 [30803.667934] [] (enter_state+0x0/0x130) from [] (state_store+0xac/0xc0) [30803.667945] r6:00000003 r5:00000003 r4:df39d000 r3:00000003 [30803.667978] [] (state_store+0x0/0xc0) from [] (kobj_attr_store+0x1c/0x28) [30803.668009] [] (kobj_attr_store+0x0/0x28) from [] (sysfs_write_file+0x88/0xbc) [30803.668032] [] (sysfs_write_file+0x0/0xbc) from [] (vfs_write+0xbc/0x138) [30803.668051] [] (vfs_write+0x0/0x138) from [] (sys_write+0x44/0x70) [30803.668062] r8:00000000 r7:00000004 r6:00000003 r5:002694d0 r4:d966acc0 [30803.668094] [] (sys_write+0x0/0x70) from [] (ret_fast_syscall+0x0/0x3c) [30803.668106] r9:d9648000 r8:c000dcc4 r6:00000001 r5:002694d0 r4:00000003 [30803.669927] PM: early resume of devices complete after 0.972 msecs Just move the clk_enable/disable in ->prepare() and ->finish() Signed-off-by: Arnaud Patard Signed-off-by: Sascha Hauer Signed-off-by: Uwe Kleine-König diff --git a/arch/arm/mach-mx5/pm-imx5.c b/arch/arm/mach-mx5/pm-imx5.c index e4529af..be19e9c 100644 --- a/arch/arm/mach-mx5/pm-imx5.c +++ b/arch/arm/mach-mx5/pm-imx5.c @@ -19,9 +19,13 @@ static struct clk *gpc_dvfs_clk; +static int mx5_suspend_prepare(void) +{ + return clk_enable(gpc_dvfs_clk); +} + static int mx5_suspend_enter(suspend_state_t state) { - clk_enable(gpc_dvfs_clk); switch (state) { case PM_SUSPEND_MEM: mx5_cpu_lp_set(STOP_POWER_OFF); @@ -42,11 +46,14 @@ static int mx5_suspend_enter(suspend_state_t state) __raw_writel(0, MXC_SRPG_EMPGC1_SRPGCR); } cpu_do_idle(); - clk_disable(gpc_dvfs_clk); - return 0; } +static void mx5_suspend_finish(void) +{ + clk_disable(gpc_dvfs_clk); +} + static int mx5_pm_valid(suspend_state_t state) { return (state > PM_SUSPEND_ON && state <= PM_SUSPEND_MAX); @@ -54,7 +61,9 @@ static int mx5_pm_valid(suspend_state_t state) static const struct platform_suspend_ops mx5_suspend_ops = { .valid = mx5_pm_valid, + .prepare = mx5_suspend_prepare, .enter = mx5_suspend_enter, + .finish = mx5_suspend_finish, }; static int __init mx5_pm_init(void) -- cgit v0.10.2 From 6571534b600b8ca1936ff5630b9e0947f21faf16 Mon Sep 17 00:00:00 2001 From: Paul Fertser Date: Mon, 10 Oct 2011 11:19:23 +0400 Subject: plat-mxc: iomux-v3.h: implicitly enable pull-up/down when that's desired To configure pads during the initialisation a set of special constants is used, e.g. #define MX25_PAD_FEC_MDIO__FEC_MDIO IOMUX_PAD(0x3c4, 0x1cc, 0x10, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_22K_UP) The problem is that no pull-up/down is getting activated unless both PAD_CTL_PUE (pull-up enable) and PAD_CTL_PKE (pull/keeper module enable) set. This is clearly stated in the i.MX25 datasheet and is confirmed by the measurements on hardware. This leads to some rather hard to understand bugs such as misdetecting an absent ethernet PHY (a real bug i had), unstable data transfer etc. This might affect mx25, mx35, mx50, mx51 and mx53 SoCs. It's reasonable to expect that if the pullup value is specified, the intention was to have it actually active, so we implicitly add the needed bits. Cc: stable@kernel.org Signed-off-by: Paul Fertser Signed-off-by: Sascha Hauer diff --git a/arch/arm/plat-mxc/include/mach/iomux-v3.h b/arch/arm/plat-mxc/include/mach/iomux-v3.h index ebbce33..4509956 100644 --- a/arch/arm/plat-mxc/include/mach/iomux-v3.h +++ b/arch/arm/plat-mxc/include/mach/iomux-v3.h @@ -89,11 +89,11 @@ typedef u64 iomux_v3_cfg_t; #define PAD_CTL_HYS (1 << 8) #define PAD_CTL_PKE (1 << 7) -#define PAD_CTL_PUE (1 << 6) -#define PAD_CTL_PUS_100K_DOWN (0 << 4) -#define PAD_CTL_PUS_47K_UP (1 << 4) -#define PAD_CTL_PUS_100K_UP (2 << 4) -#define PAD_CTL_PUS_22K_UP (3 << 4) +#define PAD_CTL_PUE (1 << 6 | PAD_CTL_PKE) +#define PAD_CTL_PUS_100K_DOWN (0 << 4 | PAD_CTL_PUE) +#define PAD_CTL_PUS_47K_UP (1 << 4 | PAD_CTL_PUE) +#define PAD_CTL_PUS_100K_UP (2 << 4 | PAD_CTL_PUE) +#define PAD_CTL_PUS_22K_UP (3 << 4 | PAD_CTL_PUE) #define PAD_CTL_ODE (1 << 3) -- cgit v0.10.2 From 590842f90984f96a3da6d8b59447dfa1d186d01e Mon Sep 17 00:00:00 2001 From: Matt Burtch Date: Mon, 17 Oct 2011 09:25:45 -0700 Subject: ARM: i.MX28: shift frac value in _CLK_SET_RATE Noticed when setting SSP0 in clk_set_rate, _CLK_SET_RATE attempts to reset the clock divider for the SSP0 parent clock, in this case IO0FRAC. Bits 24-29 of HW_CLKCTRL_FRAC0 are cleared correctly, but when the new frac value is written the value isn't shifted up to write the correct bit-field. This results in IO0FRAC being set to 0 and CPUFRAC being corrupted. This should occur when writing IO1FRAC, EMIFRAC in HW_CLKCTRL_FRAC0 and GPMIFRAC, HSADCFRAC in HW_CLKCTRL_FRAC1. Tested on custom i.MX28 board with SSP0 SPI driver. Signed-off-by: Matt Burtch Signed-off-by: Sascha Hauer diff --git a/arch/arm/mach-mxs/clock-mx28.c b/arch/arm/mach-mxs/clock-mx28.c index 5dcc59d..ba53227 100644 --- a/arch/arm/mach-mxs/clock-mx28.c +++ b/arch/arm/mach-mxs/clock-mx28.c @@ -349,7 +349,7 @@ static int name##_set_rate(struct clk *clk, unsigned long rate) \ \ reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##fr); \ reg &= ~BM_CLKCTRL_##fr##_##fs##FRAC; \ - reg |= frac; \ + reg |= frac << BP_CLKCTRL_##fr##_##fs##FRAC; \ __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_##fr); \ } \ \ -- cgit v0.10.2 From 5328ecbb516f4b1aca1233ac2ee690368da1bc82 Mon Sep 17 00:00:00 2001 From: Paul Bolle Date: Wed, 12 Oct 2011 14:04:22 +0200 Subject: ARM: imx: Fix typo 'MACH_MX31_3DS_MXC_NAND_USE_BBT' Signed-off-by: Paul Bolle Signed-off-by: Sascha Hauer diff --git a/arch/arm/mach-imx/mach-mx31_3ds.c b/arch/arm/mach-imx/mach-mx31_3ds.c index c20be75..5750ca5 100644 --- a/arch/arm/mach-imx/mach-mx31_3ds.c +++ b/arch/arm/mach-imx/mach-mx31_3ds.c @@ -542,7 +542,7 @@ static const struct mxc_nand_platform_data mx31_3ds_nand_board_info __initconst = { .width = 1, .hw_ecc = 1, -#ifdef MACH_MX31_3DS_MXC_NAND_USE_BBT +#ifdef CONFIG_MACH_MX31_3DS_MXC_NAND_USE_BBT .flash_bbt = 1, #endif }; -- cgit v0.10.2 From c149f6c8ae47c35821d93e2bffd5a3a7ca54ad9e Mon Sep 17 00:00:00 2001 From: Eric Miao Date: Tue, 16 Aug 2011 12:28:57 +0800 Subject: ARM: mmp: rename SHEEVAD to GPLUGD GuruPlugD was initially named to be SHEEVAD, and it's causing naming confusion in the mach-types database. Make it consistent by renaming to GPLUGD. Reported-and-Acked-by: Linus Walleij Acked-by: Tanmay Upadhyay Signed-off-by: Eric Miao diff --git a/arch/arm/mach-mmp/Kconfig b/arch/arm/mach-mmp/Kconfig index 56ef5f6..323d4c9 100644 --- a/arch/arm/mach-mmp/Kconfig +++ b/arch/arm/mach-mmp/Kconfig @@ -77,7 +77,7 @@ config MACH_TETON_BGA Say 'Y' here if you want to support the Marvell PXA168-based Teton BGA Development Board. -config MACH_SHEEVAD +config MACH_GPLUGD bool "Marvell's PXA168 GuruPlug Display (gplugD) Board" select CPU_PXA168 help diff --git a/arch/arm/mach-mmp/Makefile b/arch/arm/mach-mmp/Makefile index b0ac942..8f948f9 100644 --- a/arch/arm/mach-mmp/Makefile +++ b/arch/arm/mach-mmp/Makefile @@ -19,4 +19,4 @@ obj-$(CONFIG_MACH_BROWNSTONE) += brownstone.o obj-$(CONFIG_MACH_FLINT) += flint.o obj-$(CONFIG_MACH_MARVELL_JASPER) += jasper.o obj-$(CONFIG_MACH_TETON_BGA) += teton_bga.o -obj-$(CONFIG_MACH_SHEEVAD) += gplugd.o +obj-$(CONFIG_MACH_GPLUGD) += gplugd.o diff --git a/arch/arm/mach-mmp/gplugd.c b/arch/arm/mach-mmp/gplugd.c index 98e25d9..2d2c0ad 100644 --- a/arch/arm/mach-mmp/gplugd.c +++ b/arch/arm/mach-mmp/gplugd.c @@ -188,7 +188,7 @@ static void __init gplugd_init(void) pxa168_add_eth(&gplugd_eth_platform_data); } -MACHINE_START(SHEEVAD, "PXA168-based GuruPlug Display (gplugD) Platform") +MACHINE_START(GPLUGD, "PXA168-based GuruPlug Display (gplugD) Platform") .map_io = mmp_map_io, .nr_irqs = IRQ_BOARD_START, .init_irq = pxa168_init_irq, -- cgit v0.10.2 From 1a64200ec5e93be03e27c3b2fc332e04ae443eb2 Mon Sep 17 00:00:00 2001 From: Axel Lin Date: Sat, 17 Sep 2011 22:15:34 +0800 Subject: ARM: pxa/cm-x300: properly set bt_reset pin Fix below build warning and properly set bt_reset pin. CC arch/arm/mach-pxa/cm-x300.o arch/arm/mach-pxa/cm-x300.c: In function 'cm_x300_init_wi2wi': arch/arm/mach-pxa/cm-x300.c:779: warning: unused variable 'wlan_en' arch/arm/mach-pxa/cm-x300.c:795: warning: 'bt_reset' may be used uninitialized in this function Signed-off-by: Axel Lin Cc: Acked-by: Igor Grinberg Signed-off-by: Eric Miao diff --git a/arch/arm/mach-pxa/cm-x300.c b/arch/arm/mach-pxa/cm-x300.c index b6a5134..3814e12 100644 --- a/arch/arm/mach-pxa/cm-x300.c +++ b/arch/arm/mach-pxa/cm-x300.c @@ -775,7 +775,6 @@ static struct gpio cm_x300_wi2wi_gpios[] __initdata = { static void __init cm_x300_init_wi2wi(void) { - int bt_reset, wlan_en; int err; if (system_rev < 130) { @@ -791,12 +790,11 @@ static void __init cm_x300_init_wi2wi(void) } udelay(10); - gpio_set_value(bt_reset, 0); + gpio_set_value(cm_x300_wi2wi_gpios[1].gpio, 0); udelay(10); - gpio_set_value(bt_reset, 1); + gpio_set_value(cm_x300_wi2wi_gpios[1].gpio, 1); - gpio_free(wlan_en); - gpio_free(bt_reset); + gpio_free_array(ARRAY_AND_SIZE(cm_x300_wi2wi_gpios)); } /* MFP */ -- cgit v0.10.2