From 1893b2cfad0829f8d93f6d88bd396d353ec024c3 Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Thu, 2 Apr 2015 11:55:49 +0200 Subject: pinctrl: at91: Add set_multiple GPIO chip feature This adds the callback for set_multiple. As this controller has a separate set and clear register, we can't write directly to PIO_ODSR as this would required a cached variable and would race with at91_gpio_set. So build masks for the PIO_SODR and PIO_CODR registers and write them together. Signed-off-by: Alexander Stein Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c index 2f797cb..d80ade2 100644 --- a/drivers/pinctrl/pinctrl-at91.c +++ b/drivers/pinctrl/pinctrl-at91.c @@ -1326,6 +1326,21 @@ static void at91_gpio_set(struct gpio_chip *chip, unsigned offset, writel_relaxed(mask, pio + (val ? PIO_SODR : PIO_CODR)); } +static void at91_gpio_set_multiple(struct gpio_chip *chip, + unsigned long *mask, unsigned long *bits) +{ + struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip); + void __iomem *pio = at91_gpio->regbase; + +#define BITS_MASK(bits) (((bits) == 32) ? ~0U : (BIT(bits) - 1)) + /* Mask additionally to ngpio as not all GPIO controllers have 32 pins */ + uint32_t set_mask = (*mask & *bits) & BITS_MASK(chip->ngpio); + uint32_t clear_mask = (*mask & ~(*bits)) & BITS_MASK(chip->ngpio); + + writel_relaxed(set_mask, pio + PIO_SODR); + writel_relaxed(clear_mask, pio + PIO_CODR); +} + static int at91_gpio_direction_output(struct gpio_chip *chip, unsigned offset, int val) { @@ -1685,6 +1700,7 @@ static struct gpio_chip at91_gpio_template = { .get = at91_gpio_get, .direction_output = at91_gpio_direction_output, .set = at91_gpio_set, + .set_multiple = at91_gpio_set_multiple, .dbg_show = at91_gpio_dbg_show, .can_sleep = false, .ngpio = MAX_NB_GPIO_PER_BANK, -- cgit v0.10.2 From 2f77ac93a947f19301a18250845e4be776c71afd Mon Sep 17 00:00:00 2001 From: Joachim Eastwood Date: Tue, 28 Apr 2015 00:14:08 +0200 Subject: pinctrl: add lpc18xx pinctrl driver Pinctrl driver for the System Control Unit (SCU) found on NXP LPC18xx/43xx devices. Driver uses the generic pinctrl DT bindings for multiplexing and property settings. Signed-off-by: Joachim Eastwood Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index aeb5729..53ae816 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -88,6 +88,15 @@ config PINCTRL_LANTIQ select PINMUX select PINCONF +config PINCTRL_LPC18XX + bool "NXP LPC18XX/43XX SCU pinctrl driver" + depends on OF && (ARCH_LPC18XX || COMPILE_TEST) + default ARCH_LPC18XX + select PINMUX + select GENERIC_PINCONF + help + Pinctrl driver for NXP LPC18xx/43xx System Control Unit (SCU). + config PINCTRL_FALCON bool depends on SOC_FALCON diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index 6eadf04..6a7b4ba 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -34,6 +34,7 @@ obj-$(CONFIG_PINCTRL_U300) += pinctrl-u300.o obj-$(CONFIG_PINCTRL_COH901) += pinctrl-coh901.o obj-$(CONFIG_PINCTRL_XWAY) += pinctrl-xway.o obj-$(CONFIG_PINCTRL_LANTIQ) += pinctrl-lantiq.o +obj-$(CONFIG_PINCTRL_LPC18XX) += pinctrl-lpc18xx.o obj-$(CONFIG_PINCTRL_TB10X) += pinctrl-tb10x.o obj-$(CONFIG_PINCTRL_ST) += pinctrl-st.o obj-$(CONFIG_PINCTRL_ZYNQ) += pinctrl-zynq.o diff --git a/drivers/pinctrl/pinctrl-lpc18xx.c b/drivers/pinctrl/pinctrl-lpc18xx.c new file mode 100644 index 0000000..15fe1e2 --- /dev/null +++ b/drivers/pinctrl/pinctrl-lpc18xx.c @@ -0,0 +1,1144 @@ +/* + * Pinctrl driver for NXP LPC18xx/LPC43xx System Control Unit (SCU) + * + * Copyright (C) 2015 Joachim Eastwood + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "core.h" +#include "pinctrl-utils.h" + +/* LPC18XX SCU analog function registers */ +#define LPC18XX_SCU_REG_ENAIO0 0xc88 +#define LPC18XX_SCU_REG_ENAIO1 0xc8c +#define LPC18XX_SCU_REG_ENAIO2 0xc90 +#define LPC18XX_SCU_REG_ENAIO2_DAC BIT(0) + +/* LPC18XX SCU pin register definitions */ +#define LPC18XX_SCU_PIN_MODE_MASK 0x7 +#define LPC18XX_SCU_PIN_EPD BIT(3) +#define LPC18XX_SCU_PIN_EPUN BIT(4) +#define LPC18XX_SCU_PIN_EHS BIT(5) +#define LPC18XX_SCU_PIN_EZI BIT(6) +#define LPC18XX_SCU_PIN_ZIF BIT(7) +#define LPC18XX_SCU_PIN_EHD_MASK 0x300 +#define LPC18XX_SCU_PIN_EHD_POS 8 + +#define LPC18XX_SCU_I2C0_EFP BIT(0) +#define LPC18XX_SCU_I2C0_EHD BIT(2) +#define LPC18XX_SCU_I2C0_EZI BIT(3) +#define LPC18XX_SCU_I2C0_ZIF BIT(7) +#define LPC18XX_SCU_I2C0_SCL_SHIFT 0 +#define LPC18XX_SCU_I2C0_SDA_SHIFT 8 + +#define LPC18XX_SCU_FUNC_PER_PIN 8 + +struct lpc18xx_scu_data { + struct pinctrl_dev *pctl; + void __iomem *base; + struct clk *clk; +}; + +/* LPC18xx pin types */ +enum { + TYPE_ND, /* Normal-drive */ + TYPE_HD, /* High-drive */ + TYPE_HS, /* High-speed */ + TYPE_I2C0, + TYPE_USB1, +}; + +/* LPC18xx pin functions */ +enum { + FUNC_R, /* Reserved */ + FUNC_ADC, + FUNC_ADCTRIG, + FUNC_CAN0, + FUNC_CAN1, + FUNC_CGU_OUT, + FUNC_CLKIN, + FUNC_CLKOUT, + FUNC_CTIN, + FUNC_CTOUT, + FUNC_DAC, + FUNC_EMC, + FUNC_EMC_ALT, + FUNC_ENET, + FUNC_ENET_ALT, + FUNC_GPIO, + FUNC_I2C0, + FUNC_I2C1, + FUNC_I2S0_RX_MCLK, + FUNC_I2S0_RX_SCK, + FUNC_I2S0_RX_SDA, + FUNC_I2S0_RX_WS, + FUNC_I2S0_TX_MCLK, + FUNC_I2S0_TX_SCK, + FUNC_I2S0_TX_SDA, + FUNC_I2S0_TX_WS, + FUNC_I2S1, + FUNC_LCD, + FUNC_LCD_ALT, + FUNC_MCTRL, + FUNC_NMI, + FUNC_QEI, + FUNC_SDMMC, + FUNC_SGPIO, + FUNC_SPI, + FUNC_SPIFI, + FUNC_SSP0, + FUNC_SSP0_ALT, + FUNC_SSP1, + FUNC_TIMER0, + FUNC_TIMER1, + FUNC_TIMER2, + FUNC_TIMER3, + FUNC_TRACE, + FUNC_UART0, + FUNC_UART1, + FUNC_UART2, + FUNC_UART3, + FUNC_USB0, + FUNC_USB1, +}; + +static const char *const lpc18xx_function_names[] = { + [FUNC_R] = "", + [FUNC_ADC] = "adc", + [FUNC_ADCTRIG] = "adctrig", + [FUNC_CAN0] = "can0", + [FUNC_CAN1] = "can1", + [FUNC_CGU_OUT] = "cgu_out", + [FUNC_CLKIN] = "clkin", + [FUNC_CLKOUT] = "clkout", + [FUNC_CTIN] = "ctin", + [FUNC_CTOUT] = "ctout", + [FUNC_DAC] = "dac", + [FUNC_EMC] = "emc", + [FUNC_EMC_ALT] = "emc_alt", + [FUNC_ENET] = "enet", + [FUNC_ENET_ALT] = "enet_alt", + [FUNC_GPIO] = "gpio", + [FUNC_I2C0] = "i2c0", + [FUNC_I2C1] = "i2c1", + [FUNC_I2S0_RX_MCLK] = "i2s0_rx_mclk", + [FUNC_I2S0_RX_SCK] = "i2s0_rx_sck", + [FUNC_I2S0_RX_SDA] = "i2s0_rx_sda", + [FUNC_I2S0_RX_WS] = "i2s0_rx_ws", + [FUNC_I2S0_TX_MCLK] = "i2s0_tx_mclk", + [FUNC_I2S0_TX_SCK] = "i2s0_tx_sck", + [FUNC_I2S0_TX_SDA] = "i2s0_tx_sda", + [FUNC_I2S0_TX_WS] = "i2s0_tx_ws", + [FUNC_I2S1] = "i2s1", + [FUNC_LCD] = "lcd", + [FUNC_LCD_ALT] = "lcd_alt", + [FUNC_MCTRL] = "mctrl", + [FUNC_NMI] = "nmi", + [FUNC_QEI] = "qei", + [FUNC_SDMMC] = "sdmmc", + [FUNC_SGPIO] = "sgpio", + [FUNC_SPI] = "spi", + [FUNC_SPIFI] = "spifi", + [FUNC_SSP0] = "ssp0", + [FUNC_SSP0_ALT] = "ssp0_alt", + [FUNC_SSP1] = "ssp1", + [FUNC_TIMER0] = "timer0", + [FUNC_TIMER1] = "timer1", + [FUNC_TIMER2] = "timer2", + [FUNC_TIMER3] = "timer3", + [FUNC_TRACE] = "trace", + [FUNC_UART0] = "uart0", + [FUNC_UART1] = "uart1", + [FUNC_UART2] = "uart2", + [FUNC_UART3] = "uart3", + [FUNC_USB0] = "usb0", + [FUNC_USB1] = "usb1", +}; + +struct lpc18xx_pin_caps { + unsigned int offset; + unsigned char functions[LPC18XX_SCU_FUNC_PER_PIN]; + unsigned char analog; + unsigned char type; +}; + +/* Analog pins are required to have both bias and input disabled */ +#define LPC18XX_SCU_ANALOG_PIN_CFG 0x10 + +/* Macros to maniupluate analog member in lpc18xx_pin_caps */ +#define LPC18XX_ANALOG_PIN BIT(7) +#define LPC18XX_ANALOG_ADC(a) ((a >> 5) & 0x3) +#define LPC18XX_ANALOG_BIT_MASK 0x1f +#define ADC0 (LPC18XX_ANALOG_PIN | (0x00 << 5)) +#define ADC1 (LPC18XX_ANALOG_PIN | (0x01 << 5)) +#define DAC LPC18XX_ANALOG_PIN + +#define LPC_P(port, pin, f0, f1, f2, f3, f4, f5, f6, f7, a, t) \ +static struct lpc18xx_pin_caps lpc18xx_pin_p##port##_##pin = { \ + .offset = 0x##port * 32 * 4 + pin * 4, \ + .functions = { \ + FUNC_##f0, FUNC_##f1, FUNC_##f2, \ + FUNC_##f3, FUNC_##f4, FUNC_##f5, \ + FUNC_##f6, FUNC_##f7, \ + }, \ + .analog = a, \ + .type = TYPE_##t, \ +} + +#define LPC_N(pname, off, f0, f1, f2, f3, f4, f5, f6, f7, a, t) \ +static struct lpc18xx_pin_caps lpc18xx_pin_##pname = { \ + .offset = off, \ + .functions = { \ + FUNC_##f0, FUNC_##f1, FUNC_##f2, \ + FUNC_##f3, FUNC_##f4, FUNC_##f5, \ + FUNC_##f6, FUNC_##f7, \ + }, \ + .analog = a, \ + .type = TYPE_##t, \ +} + + +/* Pinmuxing table taken from data sheet */ +/* Pin FUNC0 FUNC1 FUNC2 FUNC3 FUNC4 FUNC5 FUNC6 FUNC7 ANALOG TYPE */ +LPC_P(0,0, GPIO, SSP1, ENET, SGPIO, R, R, I2S0_TX_WS,I2S1, 0, ND); +LPC_P(0,1, GPIO, SSP1,ENET_ALT,SGPIO, R, R, ENET, I2S1, 0, ND); +LPC_P(1,0, GPIO, CTIN, EMC, R, R, SSP0, SGPIO, R, 0, ND); +LPC_P(1,1, GPIO, CTOUT, EMC, SGPIO, R, SSP0, R, R, 0, ND); +LPC_P(1,2, GPIO, CTOUT, EMC, SGPIO, R, SSP0, R, R, 0, ND); +LPC_P(1,3, GPIO, CTOUT, SGPIO, EMC, USB0, SSP1, R, SDMMC, 0, ND); +LPC_P(1,4, GPIO, CTOUT, SGPIO, EMC, USB0, SSP1, R, SDMMC, 0, ND); +LPC_P(1,5, GPIO, CTOUT, R, EMC, USB0, SSP1, SGPIO, SDMMC, 0, ND); +LPC_P(1,6, GPIO, CTIN, R, EMC, R, R, SGPIO, SDMMC, 0, ND); +LPC_P(1,7, GPIO, UART1, CTOUT, EMC, USB0, R, R, R, 0, ND); +LPC_P(1,8, GPIO, UART1, CTOUT, EMC, R, R, R, SDMMC, 0, ND); +LPC_P(1,9, GPIO, UART1, CTOUT, EMC, R, R, R, SDMMC, 0, ND); +LPC_P(1,10, GPIO, UART1, CTOUT, EMC, R, R, R, SDMMC, 0, ND); +LPC_P(1,11, GPIO, UART1, CTOUT, EMC, R, R, R, SDMMC, 0, ND); +LPC_P(1,12, GPIO, UART1, R, EMC, TIMER0, R, SGPIO, SDMMC, 0, ND); +LPC_P(1,13, GPIO, UART1, R, EMC, TIMER0, R, SGPIO, SDMMC, 0, ND); +LPC_P(1,14, GPIO, UART1, R, EMC, TIMER0, R, SGPIO, R, 0, ND); +LPC_P(1,15, GPIO, UART2, SGPIO, ENET, TIMER0, R, R, R, 0, ND); +LPC_P(1,16, GPIO, UART2, SGPIO,ENET_ALT,TIMER0, R, R, ENET, 0, ND); +LPC_P(1,17, GPIO, UART2, R, ENET, TIMER0, CAN1, SGPIO, R, 0, HD); +LPC_P(1,18, GPIO, UART2, R, ENET, TIMER0, CAN1, SGPIO, R, 0, ND); +LPC_P(1,19, ENET, SSP1, R, R, CLKOUT, R, I2S0_RX_MCLK,I2S1, 0, ND); +LPC_P(1,20, GPIO, SSP1, R, ENET, TIMER0, R, SGPIO, R, 0, ND); +LPC_P(2,0, SGPIO, UART0, EMC, USB0, GPIO, R, TIMER3, ENET, 0, ND); +LPC_P(2,1, SGPIO, UART0, EMC, USB0, GPIO, R, TIMER3, R, 0, ND); +LPC_P(2,2, SGPIO, UART0, EMC, USB0, GPIO, CTIN, TIMER3, R, 0, ND); +LPC_P(2,3, SGPIO, I2C1, UART3, CTIN, GPIO, R, TIMER3, USB0, 0, HD); +LPC_P(2,4, SGPIO, I2C1, UART3, CTIN, GPIO, R, TIMER3, USB0, 0, HD); +LPC_P(2,5, SGPIO, CTIN, USB1, ADCTRIG, GPIO, R, TIMER3, USB0, 0, HD); +LPC_P(2,6, SGPIO, UART0, EMC, USB0, GPIO, CTIN, TIMER3, R, 0, ND); +LPC_P(2,7, GPIO, CTOUT, UART3, EMC, R, R, TIMER3, R, 0, ND); +LPC_P(2,8, SGPIO, CTOUT, UART3, EMC, GPIO, R, R, R, 0, ND); +LPC_P(2,9, GPIO, CTOUT, UART3, EMC, R, R, R, R, 0, ND); +LPC_P(2,10, GPIO, CTOUT, UART2, EMC, R, R, R, R, 0, ND); +LPC_P(2,11, GPIO, CTOUT, UART2, EMC, R, R, R, R, 0, ND); +LPC_P(2,12, GPIO, CTOUT, R, EMC, R, R, R, UART2, 0, ND); +LPC_P(2,13, GPIO, CTIN, R, EMC, R, R, R, UART2, 0, ND); +LPC_P(3,0, I2S0_RX_SCK, I2S0_RX_MCLK, I2S0_TX_SCK, I2S0_TX_MCLK,SSP0,R,R,R, 0, ND); +LPC_P(3,1, I2S0_TX_WS, I2S0_RX_WS,CAN0,USB1,GPIO, R, LCD, R, 0, ND); +LPC_P(3,2, I2S0_TX_SDA, I2S0_RX_SDA,CAN0,USB1,GPIO, R, LCD, R, 0, ND); +LPC_P(3,3, R, SPI, SSP0, SPIFI, CGU_OUT,R, I2S0_TX_MCLK, I2S1, 0, HS); +LPC_P(3,4, GPIO, R, R, SPIFI, UART1, I2S0_TX_WS, I2S1, LCD, 0, ND); +LPC_P(3,5, GPIO, R, R, SPIFI, UART1, I2S0_TX_SDA,I2S1, LCD, 0, ND); +LPC_P(3,6, GPIO, SPI, SSP0, SPIFI, R, SSP0_ALT, R, R, 0, ND); +LPC_P(3,7, R, SPI, SSP0, SPIFI, GPIO, SSP0_ALT, R, R, 0, ND); +LPC_P(3,8, R, SPI, SSP0, SPIFI, GPIO, SSP0_ALT, R, R, 0, ND); +LPC_P(4,0, GPIO, MCTRL, NMI, R, R, LCD, UART3, R, 0, ND); +LPC_P(4,1, GPIO, CTOUT, LCD, R, R, LCD_ALT, UART3, ENET, ADC0|1, ND); +LPC_P(4,2, GPIO, CTOUT, LCD, R, R, LCD_ALT, UART3, SGPIO, 0, ND); +LPC_P(4,3, GPIO, CTOUT, LCD, R, R, LCD_ALT, UART3, SGPIO, ADC0|0, ND); +LPC_P(4,4, GPIO, CTOUT, LCD, R, R, LCD_ALT, UART3, SGPIO, DAC, ND); +LPC_P(4,5, GPIO, CTOUT, LCD, R, R, R, R, SGPIO, 0, ND); +LPC_P(4,6, GPIO, CTOUT, LCD, R, R, R, R, SGPIO, 0, ND); +LPC_P(4,7, LCD, CLKIN, R, R, R, R, I2S1,I2S0_TX_SCK, 0, ND); +LPC_P(4,8, R, CTIN, LCD, R, GPIO, LCD_ALT, CAN1, SGPIO, 0, ND); +LPC_P(4,9, R, CTIN, LCD, R, GPIO, LCD_ALT, CAN1, SGPIO, 0, ND); +LPC_P(4,10, R, CTIN, LCD, R, GPIO, LCD_ALT, R, SGPIO, 0, ND); +LPC_P(5,0, GPIO, MCTRL, EMC, R, UART1, TIMER1, R, R, 0, ND); +LPC_P(5,1, GPIO, MCTRL, EMC, R, UART1, TIMER1, R, R, 0, ND); +LPC_P(5,2, GPIO, MCTRL, EMC, R, UART1, TIMER1, R, R, 0, ND); +LPC_P(5,3, GPIO, MCTRL, EMC, R, UART1, TIMER1, R, R, 0, ND); +LPC_P(5,4, GPIO, MCTRL, EMC, R, UART1, TIMER1, R, R, 0, ND); +LPC_P(5,5, GPIO, MCTRL, EMC, R, UART1, TIMER1, R, R, 0, ND); +LPC_P(5,6, GPIO, MCTRL, EMC, R, UART1, TIMER1, R, R, 0, ND); +LPC_P(5,7, GPIO, MCTRL, EMC, R, UART1, TIMER1, R, R, 0, ND); +LPC_P(6,0, R, I2S0_RX_MCLK,R, R, I2S0_RX_SCK, R, R, R, 0, ND); +LPC_P(6,1, GPIO, EMC, UART0, I2S0_RX_WS, R, TIMER2, R, R, 0, ND); +LPC_P(6,2, GPIO, EMC, UART0, I2S0_RX_SDA, R, TIMER2, R, R, 0, ND); +LPC_P(6,3, GPIO, USB0, SGPIO, EMC, R, TIMER2, R, R, 0, ND); +LPC_P(6,4, GPIO, CTIN, UART0, EMC, R, R, R, R, 0, ND); +LPC_P(6,5, GPIO, CTOUT, UART0, EMC, R, R, R, R, 0, ND); +LPC_P(6,6, GPIO, EMC, SGPIO, USB0, R, TIMER2, R, R, 0, ND); +LPC_P(6,7, R, EMC, SGPIO, USB0, GPIO, TIMER2, R, R, 0, ND); +LPC_P(6,8, R, EMC, SGPIO, USB0, GPIO, TIMER2, R, R, 0, ND); +LPC_P(6,9, GPIO, R, R, EMC, R, TIMER2, R, R, 0, ND); +LPC_P(6,10, GPIO, MCTRL, R, EMC, R, R, R, R, 0, ND); +LPC_P(6,11, GPIO, R, R, EMC, R, TIMER2, R, R, 0, ND); +LPC_P(6,12, GPIO, CTOUT, R, EMC, R, R, R, R, 0, ND); +LPC_P(7,0, GPIO, CTOUT, R, LCD, R, R, R, SGPIO, 0, ND); +LPC_P(7,1, GPIO, CTOUT,I2S0_TX_WS,LCD,LCD_ALT, R, UART2, SGPIO, 0, ND); +LPC_P(7,2, GPIO, CTIN,I2S0_TX_SDA,LCD,LCD_ALT, R, UART2, SGPIO, 0, ND); +LPC_P(7,3, GPIO, CTIN, R, LCD,LCD_ALT, R, R, R, 0, ND); +LPC_P(7,4, GPIO, CTOUT, R, LCD,LCD_ALT, TRACE, R, R, ADC0|4, ND); +LPC_P(7,5, GPIO, CTOUT, R, LCD,LCD_ALT, TRACE, R, R, ADC0|3, ND); +LPC_P(7,6, GPIO, CTOUT, R, LCD, R, TRACE, R, R, 0, ND); +LPC_P(7,7, GPIO, CTOUT, R, LCD, R, TRACE, ENET, SGPIO, ADC1|6, ND); +LPC_P(8,0, GPIO, USB0, R, MCTRL, SGPIO, R, R, TIMER0, 0, HD); +LPC_P(8,1, GPIO, USB0, R, MCTRL, SGPIO, R, R, TIMER0, 0, HD); +LPC_P(8,2, GPIO, USB0, R, MCTRL, SGPIO, R, R, TIMER0, 0, HD); +LPC_P(8,3, GPIO, USB1, R, LCD, LCD_ALT, R, R, TIMER0, 0, ND); +LPC_P(8,4, GPIO, USB1, R, LCD, LCD_ALT, R, R, TIMER0, 0, ND); +LPC_P(8,5, GPIO, USB1, R, LCD, LCD_ALT, R, R, TIMER0, 0, ND); +LPC_P(8,6, GPIO, USB1, R, LCD, LCD_ALT, R, R, TIMER0, 0, ND); +LPC_P(8,7, GPIO, USB1, R, LCD, LCD_ALT, R, R, TIMER0, 0, ND); +LPC_P(8,8, R, USB1, R, R, R, R,CGU_OUT, I2S1, 0, ND); +LPC_P(9,0, GPIO, MCTRL, R, R, R, ENET, SGPIO, SSP0, 0, ND); +LPC_P(9,1, GPIO, MCTRL, R, R, I2S0_TX_WS,ENET, SGPIO, SSP0, 0, ND); +LPC_P(9,2, GPIO, MCTRL, R, R, I2S0_TX_SDA,ENET,SGPIO, SSP0, 0, ND); +LPC_P(9,3, GPIO, MCTRL, USB1, R, R, ENET, SGPIO, UART3, 0, ND); +LPC_P(9,4, R, MCTRL, USB1, R, GPIO, ENET, SGPIO, UART3, 0, ND); +LPC_P(9,5, R, MCTRL, USB1, R, GPIO, ENET, SGPIO, UART0, 0, ND); +LPC_P(9,6, GPIO, MCTRL, USB1, R, R, ENET, SGPIO, UART0, 0, ND); +LPC_P(a,0, R, R, R, R, R, I2S1, CGU_OUT, R, 0, ND); +LPC_P(a,1, GPIO, QEI, R, UART2, R, R, R, R, 0, HD); +LPC_P(a,2, GPIO, QEI, R, UART2, R, R, R, R, 0, HD); +LPC_P(a,3, GPIO, QEI, R, R, R, R, R, R, 0, HD); +LPC_P(a,4, R, CTOUT, R, EMC, GPIO, R, R, R, 0, ND); +LPC_P(b,0, R, CTOUT, LCD, R, GPIO, R, R, R, 0, ND); +LPC_P(b,1, R, USB1, LCD, R, GPIO, CTOUT, R, R, 0, ND); +LPC_P(b,2, R, USB1, LCD, R, GPIO, CTOUT, R, R, 0, ND); +LPC_P(b,3, R, USB1, LCD, R, GPIO, CTOUT, R, R, 0, ND); +LPC_P(b,4, R, USB1, LCD, R, GPIO, CTIN, R, R, 0, ND); +LPC_P(b,5, R, USB1, LCD, R, GPIO, CTIN, LCD_ALT, R, 0, ND); +LPC_P(b,6, R, USB1, LCD, R, GPIO, CTIN, LCD_ALT, R, ADC0|6, ND); +LPC_P(c,0, R, USB1, R, ENET, LCD, R, R, SDMMC, ADC1|1, ND); +LPC_P(c,1, USB1, R, UART1, ENET, GPIO, R, TIMER3, SDMMC, 0, ND); +LPC_P(c,2, USB1, R, UART1, ENET, GPIO, R, R, SDMMC, 0, ND); +LPC_P(c,3, USB1, R, UART1, ENET, GPIO, R, R, SDMMC, ADC1|0, ND); +LPC_P(c,4, R, USB1, R, ENET, GPIO, R, TIMER3, SDMMC, 0, ND); +LPC_P(c,5, R, USB1, R, ENET, GPIO, R, TIMER3, SDMMC, 0, ND); +LPC_P(c,6, R, USB1, R, ENET, GPIO, R, TIMER3, SDMMC, 0, ND); +LPC_P(c,7, R, USB1, R, ENET, GPIO, R, TIMER3, SDMMC, 0, ND); +LPC_P(c,8, R, USB1, R, ENET, GPIO, R, TIMER3, SDMMC, 0, ND); +LPC_P(c,9, R, USB1, R, ENET, GPIO, R, TIMER3, SDMMC, 0, ND); +LPC_P(c,10, R, USB1, UART1, R, GPIO, R, TIMER3, SDMMC, 0, ND); +LPC_P(c,11, R, USB1, UART1, R, GPIO, R, R, SDMMC, 0, ND); +LPC_P(c,12, R, R, UART1, R, GPIO, SGPIO, I2S0_TX_SDA,SDMMC, 0, ND); +LPC_P(c,13, R, R, UART1, R, GPIO, SGPIO, I2S0_TX_WS, SDMMC, 0, ND); +LPC_P(c,14, R, R, UART1, R, GPIO, SGPIO, ENET, SDMMC, 0, ND); +LPC_P(d,0, R, CTOUT, EMC, R, GPIO, R, R, SGPIO, 0, ND); +LPC_P(d,1, R, R, EMC, R, GPIO, SDMMC, R, SGPIO, 0, ND); +LPC_P(d,2, R, CTOUT, EMC, R, GPIO, R, R, SGPIO, 0, ND); +LPC_P(d,3, R, CTOUT, EMC, R, GPIO, R, R, SGPIO, 0, ND); +LPC_P(d,4, R, CTOUT, EMC, R, GPIO, R, R, SGPIO, 0, ND); +LPC_P(d,5, R, CTOUT, EMC, R, GPIO, R, R, SGPIO, 0, ND); +LPC_P(d,6, R, CTOUT, EMC, R, GPIO, R, R, SGPIO, 0, ND); +LPC_P(d,7, R, CTIN, EMC, R, GPIO, R, R, SGPIO, 0, ND); +LPC_P(d,8, R, CTIN, EMC, R, GPIO, R, R, SGPIO, 0, ND); +LPC_P(d,9, R, CTOUT, EMC, R, GPIO, R, R, SGPIO, 0, ND); +LPC_P(d,10, R, CTIN, EMC, R, GPIO, R, R, R, 0, ND); +LPC_P(d,11, R, R, EMC, R, GPIO, USB1, CTOUT, R, 0, ND); +LPC_P(d,12, R, R, EMC, R, GPIO, R, CTOUT, R, 0, ND); +LPC_P(d,13, R, CTIN, EMC, R, GPIO, R, CTOUT, R, 0, ND); +LPC_P(d,14, R, R, EMC, R, GPIO, R, CTOUT, R, 0, ND); +LPC_P(d,15, R, R, EMC, R, GPIO, SDMMC, CTOUT, R, 0, ND); +LPC_P(d,16, R, R, EMC, R, GPIO, SDMMC, CTOUT, R, 0, ND); +LPC_P(e,0, R, R, R, EMC, GPIO, CAN1, R, R, 0, ND); +LPC_P(e,1, R, R, R, EMC, GPIO, CAN1, R, R, 0, ND); +LPC_P(e,2,ADCTRIG, CAN0, R, EMC, GPIO, R, R, R, 0, ND); +LPC_P(e,3, R, CAN0,ADCTRIG, EMC, GPIO, R, R, R, 0, ND); +LPC_P(e,4, R, NMI, R, EMC, GPIO, R, R, R, 0, ND); +LPC_P(e,5, R, CTOUT, UART1, EMC, GPIO, R, R, R, 0, ND); +LPC_P(e,6, R, CTOUT, UART1, EMC, GPIO, R, R, R, 0, ND); +LPC_P(e,7, R, CTOUT, UART1, EMC, GPIO, R, R, R, 0, ND); +LPC_P(e,8, R, CTOUT, UART1, EMC, GPIO, R, R, R, 0, ND); +LPC_P(e,9, R, CTIN, UART1, EMC, GPIO, R, R, R, 0, ND); +LPC_P(e,10, R, CTIN, UART1, EMC, GPIO, R, R, R, 0, ND); +LPC_P(e,11, R, CTOUT, UART1, EMC, GPIO, R, R, R, 0, ND); +LPC_P(e,12, R, CTOUT, UART1, EMC, GPIO, R, R, R, 0, ND); +LPC_P(e,13, R, CTOUT, I2C1, EMC, GPIO, R, R, R, 0, ND); +LPC_P(e,14, R, R, R, EMC, GPIO, R, R, R, 0, ND); +LPC_P(e,15, R, CTOUT, I2C1, EMC, GPIO, R, R, R, 0, ND); +LPC_P(f,0, SSP0, CLKIN, R, R, R, R, R, I2S1, 0, ND); +LPC_P(f,1, R, R, SSP0, R, GPIO, R, SGPIO, R, 0, ND); +LPC_P(f,2, R, UART3, SSP0, R, GPIO, R, SGPIO, R, 0, ND); +LPC_P(f,3, R, UART3, SSP0, R, GPIO, R, SGPIO, R, 0, ND); +LPC_P(f,4, SSP1, CLKIN, TRACE, R, R, R, I2S0_TX_MCLK,I2S0_RX_SCK, 0, ND); +LPC_P(f,5, R, UART3, SSP1, TRACE, GPIO, R, SGPIO, R, ADC1|4, ND); +LPC_P(f,6, R, UART3, SSP1, TRACE, GPIO, R, SGPIO, I2S1, ADC1|3, ND); +LPC_P(f,7, R, UART3, SSP1, TRACE, GPIO, R, SGPIO, I2S1, ADC1|7, ND); +LPC_P(f,8, R, UART0, CTIN, TRACE, GPIO, R, SGPIO, R, ADC0|2, ND); +LPC_P(f,9, R, UART0, CTOUT, R, GPIO, R, SGPIO, R, ADC1|2, ND); +LPC_P(f,10, R, UART0, R, R, GPIO, R, SDMMC, R, ADC0|5, ND); +LPC_P(f,11, R, UART0, R, R, GPIO, R, SDMMC, R, ADC1|5, ND); + +/* Pin Offset FUNC0 FUNC1 FUNC2 FUNC3 FUNC4 FUNC5 FUNC6 FUNC7 ANALOG TYPE */ +LPC_N(clk0, 0xc00, EMC, CLKOUT, R, R, SDMMC, EMC_ALT, SSP1, ENET, 0, HS); +LPC_N(clk1, 0xc04, EMC, CLKOUT, R, R, R, CGU_OUT, R, I2S1, 0, HS); +LPC_N(clk2, 0xc08, EMC, CLKOUT, R, R, SDMMC, EMC_ALT,I2S0_TX_MCLK,I2S1, 0, HS); +LPC_N(clk3, 0xc0c, EMC, CLKOUT, R, R, R, CGU_OUT, R, I2S1, 0, HS); +LPC_N(usb1_dm, 0xc80, R, R, R, R, R, R, R, R, 0, USB1); +LPC_N(usb1_dp, 0xc80, R, R, R, R, R, R, R, R, 0, USB1); +LPC_N(i2c0_scl, 0xc84, R, R, R, R, R, R, R, R, 0, I2C0); +LPC_N(i2c0_sda, 0xc84, R, R, R, R, R, R, R, R, 0, I2C0); + +#define LPC18XX_PIN_P(port, pin) { \ + .number = 0x##port * 32 + pin, \ + .name = "p"#port"_"#pin, \ + .drv_data = &lpc18xx_pin_p##port##_##pin \ +} + +/* Pin numbers for special pins */ +enum { + PIN_CLK0 = 600, + PIN_CLK1, + PIN_CLK2, + PIN_CLK3, + PIN_USB1_DM, + PIN_USB1_DP, + PIN_I2C0_SCL, + PIN_I2C0_SDA, +}; + +#define LPC18XX_PIN(pname, n) { \ + .number = n, \ + .name = #pname, \ + .drv_data = &lpc18xx_pin_##pname \ +} + +static const struct pinctrl_pin_desc lpc18xx_pins[] = { + LPC18XX_PIN_P(0,0), + LPC18XX_PIN_P(0,1), + LPC18XX_PIN_P(1,0), + LPC18XX_PIN_P(1,1), + LPC18XX_PIN_P(1,2), + LPC18XX_PIN_P(1,3), + LPC18XX_PIN_P(1,4), + LPC18XX_PIN_P(1,5), + LPC18XX_PIN_P(1,6), + LPC18XX_PIN_P(1,7), + LPC18XX_PIN_P(1,8), + LPC18XX_PIN_P(1,9), + LPC18XX_PIN_P(1,10), + LPC18XX_PIN_P(1,11), + LPC18XX_PIN_P(1,12), + LPC18XX_PIN_P(1,13), + LPC18XX_PIN_P(1,14), + LPC18XX_PIN_P(1,15), + LPC18XX_PIN_P(1,16), + LPC18XX_PIN_P(1,17), + LPC18XX_PIN_P(1,18), + LPC18XX_PIN_P(1,19), + LPC18XX_PIN_P(1,20), + LPC18XX_PIN_P(2,0), + LPC18XX_PIN_P(2,1), + LPC18XX_PIN_P(2,2), + LPC18XX_PIN_P(2,3), + LPC18XX_PIN_P(2,4), + LPC18XX_PIN_P(2,5), + LPC18XX_PIN_P(2,6), + LPC18XX_PIN_P(2,7), + LPC18XX_PIN_P(2,8), + LPC18XX_PIN_P(2,9), + LPC18XX_PIN_P(2,10), + LPC18XX_PIN_P(2,11), + LPC18XX_PIN_P(2,12), + LPC18XX_PIN_P(2,13), + LPC18XX_PIN_P(3,0), + LPC18XX_PIN_P(3,1), + LPC18XX_PIN_P(3,2), + LPC18XX_PIN_P(3,3), + LPC18XX_PIN_P(3,4), + LPC18XX_PIN_P(3,5), + LPC18XX_PIN_P(3,6), + LPC18XX_PIN_P(3,7), + LPC18XX_PIN_P(3,8), + LPC18XX_PIN_P(4,0), + LPC18XX_PIN_P(4,1), + LPC18XX_PIN_P(4,2), + LPC18XX_PIN_P(4,3), + LPC18XX_PIN_P(4,4), + LPC18XX_PIN_P(4,5), + LPC18XX_PIN_P(4,6), + LPC18XX_PIN_P(4,7), + LPC18XX_PIN_P(4,8), + LPC18XX_PIN_P(4,9), + LPC18XX_PIN_P(4,10), + LPC18XX_PIN_P(5,0), + LPC18XX_PIN_P(5,1), + LPC18XX_PIN_P(5,2), + LPC18XX_PIN_P(5,3), + LPC18XX_PIN_P(5,4), + LPC18XX_PIN_P(5,5), + LPC18XX_PIN_P(5,6), + LPC18XX_PIN_P(5,7), + LPC18XX_PIN_P(6,0), + LPC18XX_PIN_P(6,1), + LPC18XX_PIN_P(6,2), + LPC18XX_PIN_P(6,3), + LPC18XX_PIN_P(6,4), + LPC18XX_PIN_P(6,5), + LPC18XX_PIN_P(6,6), + LPC18XX_PIN_P(6,7), + LPC18XX_PIN_P(6,8), + LPC18XX_PIN_P(6,9), + LPC18XX_PIN_P(6,10), + LPC18XX_PIN_P(6,11), + LPC18XX_PIN_P(6,12), + LPC18XX_PIN_P(7,0), + LPC18XX_PIN_P(7,1), + LPC18XX_PIN_P(7,2), + LPC18XX_PIN_P(7,3), + LPC18XX_PIN_P(7,4), + LPC18XX_PIN_P(7,5), + LPC18XX_PIN_P(7,6), + LPC18XX_PIN_P(7,7), + LPC18XX_PIN_P(8,0), + LPC18XX_PIN_P(8,1), + LPC18XX_PIN_P(8,2), + LPC18XX_PIN_P(8,3), + LPC18XX_PIN_P(8,4), + LPC18XX_PIN_P(8,5), + LPC18XX_PIN_P(8,6), + LPC18XX_PIN_P(8,7), + LPC18XX_PIN_P(8,8), + LPC18XX_PIN_P(9,0), + LPC18XX_PIN_P(9,1), + LPC18XX_PIN_P(9,2), + LPC18XX_PIN_P(9,3), + LPC18XX_PIN_P(9,4), + LPC18XX_PIN_P(9,5), + LPC18XX_PIN_P(9,6), + LPC18XX_PIN_P(a,0), + LPC18XX_PIN_P(a,1), + LPC18XX_PIN_P(a,2), + LPC18XX_PIN_P(a,3), + LPC18XX_PIN_P(a,4), + LPC18XX_PIN_P(b,0), + LPC18XX_PIN_P(b,1), + LPC18XX_PIN_P(b,2), + LPC18XX_PIN_P(b,3), + LPC18XX_PIN_P(b,4), + LPC18XX_PIN_P(b,5), + LPC18XX_PIN_P(b,6), + LPC18XX_PIN_P(c,0), + LPC18XX_PIN_P(c,1), + LPC18XX_PIN_P(c,2), + LPC18XX_PIN_P(c,3), + LPC18XX_PIN_P(c,4), + LPC18XX_PIN_P(c,5), + LPC18XX_PIN_P(c,6), + LPC18XX_PIN_P(c,7), + LPC18XX_PIN_P(c,8), + LPC18XX_PIN_P(c,9), + LPC18XX_PIN_P(c,10), + LPC18XX_PIN_P(c,11), + LPC18XX_PIN_P(c,12), + LPC18XX_PIN_P(c,13), + LPC18XX_PIN_P(c,14), + LPC18XX_PIN_P(d,0), + LPC18XX_PIN_P(d,1), + LPC18XX_PIN_P(d,2), + LPC18XX_PIN_P(d,3), + LPC18XX_PIN_P(d,4), + LPC18XX_PIN_P(d,5), + LPC18XX_PIN_P(d,6), + LPC18XX_PIN_P(d,7), + LPC18XX_PIN_P(d,8), + LPC18XX_PIN_P(d,9), + LPC18XX_PIN_P(d,10), + LPC18XX_PIN_P(d,11), + LPC18XX_PIN_P(d,12), + LPC18XX_PIN_P(d,13), + LPC18XX_PIN_P(d,14), + LPC18XX_PIN_P(d,15), + LPC18XX_PIN_P(d,16), + LPC18XX_PIN_P(e,0), + LPC18XX_PIN_P(e,1), + LPC18XX_PIN_P(e,2), + LPC18XX_PIN_P(e,3), + LPC18XX_PIN_P(e,4), + LPC18XX_PIN_P(e,5), + LPC18XX_PIN_P(e,6), + LPC18XX_PIN_P(e,7), + LPC18XX_PIN_P(e,8), + LPC18XX_PIN_P(e,9), + LPC18XX_PIN_P(e,10), + LPC18XX_PIN_P(e,11), + LPC18XX_PIN_P(e,12), + LPC18XX_PIN_P(e,13), + LPC18XX_PIN_P(e,14), + LPC18XX_PIN_P(e,15), + LPC18XX_PIN_P(f,0), + LPC18XX_PIN_P(f,1), + LPC18XX_PIN_P(f,2), + LPC18XX_PIN_P(f,3), + LPC18XX_PIN_P(f,4), + LPC18XX_PIN_P(f,5), + LPC18XX_PIN_P(f,6), + LPC18XX_PIN_P(f,7), + LPC18XX_PIN_P(f,8), + LPC18XX_PIN_P(f,9), + LPC18XX_PIN_P(f,10), + LPC18XX_PIN_P(f,11), + + LPC18XX_PIN(clk0, PIN_CLK0), + LPC18XX_PIN(clk1, PIN_CLK1), + LPC18XX_PIN(clk2, PIN_CLK2), + LPC18XX_PIN(clk3, PIN_CLK3), + LPC18XX_PIN(usb1_dm, PIN_USB1_DM), + LPC18XX_PIN(usb1_dp, PIN_USB1_DP), + LPC18XX_PIN(i2c0_scl, PIN_I2C0_SCL), + LPC18XX_PIN(i2c0_sda, PIN_I2C0_SDA), +}; + +static int lpc18xx_pconf_get_usb1(enum pin_config_param param, int *arg, u32 reg) +{ + /* TODO */ + return -ENOTSUPP; +} + +static int lpc18xx_pconf_get_i2c0(enum pin_config_param param, int *arg, u32 reg, + unsigned pin) +{ + u8 shift; + + if (pin == PIN_I2C0_SCL) + shift = LPC18XX_SCU_I2C0_SCL_SHIFT; + else + shift = LPC18XX_SCU_I2C0_SDA_SHIFT; + + switch (param) { + case PIN_CONFIG_INPUT_ENABLE: + if (reg & (LPC18XX_SCU_I2C0_EZI << shift)) + *arg = 1; + else + return -EINVAL; + break; + + case PIN_CONFIG_SLEW_RATE: + if (reg & (LPC18XX_SCU_I2C0_EHD << shift)) + *arg = 1; + else + *arg = 0; + break; + + case PIN_CONFIG_INPUT_SCHMITT: + if (reg & (LPC18XX_SCU_I2C0_EFP << shift)) + *arg = 3; + else + *arg = 50; + break; + + case PIN_CONFIG_INPUT_SCHMITT_ENABLE: + if (reg & (LPC18XX_SCU_I2C0_ZIF << shift)) + return -EINVAL; + else + *arg = 1; + break; + + default: + return -ENOTSUPP; + } + + return 0; +} + +static int lpc18xx_pconf_get_pin(enum pin_config_param param, int *arg, u32 reg, + struct lpc18xx_pin_caps *pin_cap) +{ + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + if ((!(reg & LPC18XX_SCU_PIN_EPD)) && (reg & LPC18XX_SCU_PIN_EPUN)) + ; + else + return -EINVAL; + break; + + case PIN_CONFIG_BIAS_PULL_UP: + if (reg & LPC18XX_SCU_PIN_EPUN) + return -EINVAL; + else + *arg = 1; + break; + + case PIN_CONFIG_BIAS_PULL_DOWN: + if (reg & LPC18XX_SCU_PIN_EPD) + *arg = 1; + else + return -EINVAL; + break; + + case PIN_CONFIG_INPUT_ENABLE: + if (reg & LPC18XX_SCU_PIN_EZI) + *arg = 1; + else + return -EINVAL; + break; + + case PIN_CONFIG_SLEW_RATE: + if (pin_cap->type == TYPE_HD) + return -ENOTSUPP; + + if (reg & LPC18XX_SCU_PIN_EHS) + *arg = 1; + else + *arg = 0; + break; + + case PIN_CONFIG_INPUT_SCHMITT_ENABLE: + if (reg & LPC18XX_SCU_PIN_ZIF) + return -EINVAL; + else + *arg = 1; + break; + + case PIN_CONFIG_DRIVE_STRENGTH: + if (pin_cap->type != TYPE_HD) + return -ENOTSUPP; + + *arg = (reg & LPC18XX_SCU_PIN_EHD_MASK) >> LPC18XX_SCU_PIN_EHD_POS; + switch (*arg) { + case 3: *arg += 5; + case 2: *arg += 5; + case 1: *arg += 3; + case 0: *arg += 4; + } + break; + + default: + return -ENOTSUPP; + } + + return 0; +} + +static int lpc18xx_pconf_get(struct pinctrl_dev *pctldev, unsigned pin, + unsigned long *config) +{ + struct lpc18xx_scu_data *scu = pinctrl_dev_get_drvdata(pctldev); + enum pin_config_param param = pinconf_to_config_param(*config); + struct lpc18xx_pin_caps *pin_cap; + int ret, arg = 0; + u32 reg; + int i; + + for (i = 0; i < ARRAY_SIZE(lpc18xx_pins); i++) { + if (lpc18xx_pins[i].number == pin) + pin = i; + } + + pin_cap = lpc18xx_pins[pin].drv_data; + reg = readl(scu->base + pin_cap->offset); + + if (pin_cap->type == TYPE_I2C0) + ret = lpc18xx_pconf_get_i2c0(param, &arg, reg, pin); + else if (pin_cap->type == TYPE_USB1) + ret = lpc18xx_pconf_get_usb1(param, &arg, reg); + else + ret = lpc18xx_pconf_get_pin(param, &arg, reg, pin_cap); + + if (ret < 0) + return ret; + + *config = pinconf_to_config_packed(param, (u16)arg); + + return 0; +} + +static int lpc18xx_pconf_set_usb1(struct pinctrl_dev *pctldev, + enum pin_config_param param, + u16 param_val, u32 *reg) +{ + /* TODO */ + return -ENOTSUPP; +} + +static int lpc18xx_pconf_set_i2c0(struct pinctrl_dev *pctldev, + enum pin_config_param param, + u16 param_val, u32 *reg, + unsigned pin) +{ + u8 shift; + + if (pin == PIN_I2C0_SCL) + shift = LPC18XX_SCU_I2C0_SCL_SHIFT; + else + shift = LPC18XX_SCU_I2C0_SDA_SHIFT; + + switch (param) { + case PIN_CONFIG_INPUT_ENABLE: + if (param_val) + *reg |= (LPC18XX_SCU_I2C0_EZI << shift); + else + *reg &= ~(LPC18XX_SCU_I2C0_EZI << shift); + break; + + case PIN_CONFIG_SLEW_RATE: + if (param_val) + *reg |= (LPC18XX_SCU_I2C0_EHD << shift); + else + *reg &= ~(LPC18XX_SCU_I2C0_EHD << shift); + break; + + case PIN_CONFIG_INPUT_SCHMITT: + if (param_val == 3) + *reg |= (LPC18XX_SCU_I2C0_EFP << shift); + else if (param_val == 50) + *reg &= ~(LPC18XX_SCU_I2C0_EFP << shift); + else + return -ENOTSUPP; + break; + + case PIN_CONFIG_INPUT_SCHMITT_ENABLE: + if (param) + *reg &= ~(LPC18XX_SCU_I2C0_ZIF << shift); + else + *reg |= (LPC18XX_SCU_I2C0_ZIF << shift); + break; + + default: + dev_err(pctldev->dev, "Property not supported\n"); + return -ENOTSUPP; + } + + return 0; +} + +static int lpc18xx_pconf_set_pin(struct pinctrl_dev *pctldev, + enum pin_config_param param, + u16 param_val, u32 *reg, + struct lpc18xx_pin_caps *pin_cap) +{ + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + *reg &= ~LPC18XX_SCU_PIN_EPD; + *reg |= LPC18XX_SCU_PIN_EPUN; + break; + + case PIN_CONFIG_BIAS_PULL_UP: + *reg &= ~LPC18XX_SCU_PIN_EPUN; + break; + + case PIN_CONFIG_BIAS_PULL_DOWN: + *reg |= LPC18XX_SCU_PIN_EPD; + break; + + case PIN_CONFIG_INPUT_ENABLE: + if (param_val) + *reg |= LPC18XX_SCU_PIN_EZI; + else + *reg &= ~LPC18XX_SCU_PIN_EZI; + break; + + case PIN_CONFIG_SLEW_RATE: + if (pin_cap->type == TYPE_HD) { + dev_err(pctldev->dev, "Slew rate unsupported on high-drive pins\n"); + return -ENOTSUPP; + } + + if (param_val == 0) + *reg &= ~LPC18XX_SCU_PIN_EHS; + else + *reg |= LPC18XX_SCU_PIN_EHS; + break; + + case PIN_CONFIG_INPUT_SCHMITT_ENABLE: + if (param) + *reg &= ~LPC18XX_SCU_PIN_ZIF; + else + *reg |= LPC18XX_SCU_PIN_ZIF; + break; + + case PIN_CONFIG_DRIVE_STRENGTH: + if (pin_cap->type != TYPE_HD) { + dev_err(pctldev->dev, "Drive strength available only on high-drive pins\n"); + return -ENOTSUPP; + } + *reg &= ~LPC18XX_SCU_PIN_EHD_MASK; + + switch (param_val) { + case 20: param_val -= 5; + case 14: param_val -= 5; + case 8: param_val -= 3; + case 4: param_val -= 4; + break; + default: + dev_err(pctldev->dev, "Drive strength %u unsupported\n", param_val); + return -ENOTSUPP; + } + *reg |= param_val << LPC18XX_SCU_PIN_EHD_POS; + break; + + default: + dev_err(pctldev->dev, "Property not supported\n"); + return -ENOTSUPP; + } + + return 0; +} + +static int lpc18xx_pconf_set(struct pinctrl_dev *pctldev, unsigned pin, + unsigned long *configs, unsigned num_configs) +{ + struct lpc18xx_scu_data *scu = pinctrl_dev_get_drvdata(pctldev); + struct lpc18xx_pin_caps *pin_cap; + enum pin_config_param param; + u16 param_val; + u32 reg; + int ret; + int i; + + for (i = 0; i < ARRAY_SIZE(lpc18xx_pins); i++) { + if (lpc18xx_pins[i].number == pin) + break; + } + + pin_cap = lpc18xx_pins[i].drv_data; + reg = readl(scu->base + pin_cap->offset); + + for (i = 0; i < num_configs; i++) { + param = pinconf_to_config_param(configs[i]); + param_val = pinconf_to_config_argument(configs[i]); + + if (pin_cap->type == TYPE_I2C0) + ret = lpc18xx_pconf_set_i2c0(pctldev, param, param_val, ®, pin); + else if (pin_cap->type == TYPE_USB1) + ret = lpc18xx_pconf_set_usb1(pctldev, param, param_val, ®); + else + ret = lpc18xx_pconf_set_pin(pctldev, param, param_val, ®, pin_cap); + + if (ret) + return ret; + } + + writel(reg, scu->base + pin_cap->offset); + + return 0; +} + +static const struct pinconf_ops lpc18xx_pconf_ops = { + .is_generic = true, + .pin_config_get = lpc18xx_pconf_get, + .pin_config_set = lpc18xx_pconf_set, +}; + +static int lpc18xx_pmx_get_funcs_count(struct pinctrl_dev *pctldev) +{ + return ARRAY_SIZE(lpc18xx_function_names); +} + +static const char *lpc18xx_pmx_get_func_name(struct pinctrl_dev *pctldev, + unsigned function) +{ + return lpc18xx_function_names[function]; +} + +static int lpc18xx_pmx_get_func_groups(struct pinctrl_dev *pctldev, + unsigned function, + const char *const **groups, + unsigned *const num_groups) +{ + return 0; +} + +static int lpc18xx_pmx_set(struct pinctrl_dev *pctldev, unsigned function, + unsigned group) +{ + struct lpc18xx_scu_data *scu = pinctrl_dev_get_drvdata(pctldev); + struct lpc18xx_pin_caps *pin = lpc18xx_pins[group].drv_data; + int func; + u32 reg; + + /* Dedicated USB1 and I2C0 pins doesn't support muxing */ + if (pin->type == TYPE_USB1) { + if (function == FUNC_USB1) + return 0; + + goto fail; + } + + if (pin->type == TYPE_I2C0) { + if (function == FUNC_I2C0) + return 0; + + goto fail; + } + + if (function == FUNC_ADC && (pin->analog & LPC18XX_ANALOG_PIN)) { + u32 offset; + + writel(LPC18XX_SCU_ANALOG_PIN_CFG, scu->base + pin->offset); + + if (LPC18XX_ANALOG_ADC(pin->analog) == 0) + offset = LPC18XX_SCU_REG_ENAIO0; + else + offset = LPC18XX_SCU_REG_ENAIO1; + + reg = readl(scu->base + offset); + reg |= pin->analog & LPC18XX_ANALOG_BIT_MASK; + writel(reg, scu->base + offset); + + return 0; + } + + if (function == FUNC_DAC && (pin->analog & LPC18XX_ANALOG_PIN)) { + writel(LPC18XX_SCU_ANALOG_PIN_CFG, scu->base + pin->offset); + + reg = readl(scu->base + LPC18XX_SCU_REG_ENAIO2); + reg |= LPC18XX_SCU_REG_ENAIO2_DAC; + writel(reg, scu->base + LPC18XX_SCU_REG_ENAIO2); + + return 0; + } + + for (func = 0; func < LPC18XX_SCU_FUNC_PER_PIN; func++) { + if (function == pin->functions[func]) + break; + } + + if (func >= LPC18XX_SCU_FUNC_PER_PIN) + goto fail; + + reg = readl(scu->base + pin->offset); + reg &= ~LPC18XX_SCU_PIN_MODE_MASK; + writel(reg | func, scu->base + pin->offset); + + return 0; +fail: + dev_err(pctldev->dev, "Pin %s can't be %s\n", lpc18xx_pins[group].name, + lpc18xx_function_names[function]); + return -EINVAL; +} + +static const struct pinmux_ops lpc18xx_pmx_ops = { + .get_functions_count = lpc18xx_pmx_get_funcs_count, + .get_function_name = lpc18xx_pmx_get_func_name, + .get_function_groups = lpc18xx_pmx_get_func_groups, + .set_mux = lpc18xx_pmx_set, +}; + +static int lpc18xx_pctl_get_groups_count(struct pinctrl_dev *pctldev) +{ + return ARRAY_SIZE(lpc18xx_pins); +} + +static const char *lpc18xx_pctl_get_group_name(struct pinctrl_dev *pctldev, + unsigned group) +{ + return lpc18xx_pins[group].name; +} + +static int lpc18xx_pctl_get_group_pins(struct pinctrl_dev *pctldev, + unsigned group, + const unsigned **pins, + unsigned *num_pins) +{ + *pins = &lpc18xx_pins[group].number; + *num_pins = 1; + + return 0; +} + +static const struct pinctrl_ops lpc18xx_pctl_ops = { + .get_groups_count = lpc18xx_pctl_get_groups_count, + .get_group_name = lpc18xx_pctl_get_group_name, + .get_group_pins = lpc18xx_pctl_get_group_pins, + .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, + .dt_free_map = pinctrl_utils_dt_free_map, +}; + +static struct pinctrl_desc lpc18xx_scu_desc = { + .name = "lpc18xx/43xx-scu", + .pins = lpc18xx_pins, + .npins = ARRAY_SIZE(lpc18xx_pins), + .pctlops = &lpc18xx_pctl_ops, + .pmxops = &lpc18xx_pmx_ops, + .confops = &lpc18xx_pconf_ops, + .owner = THIS_MODULE, +}; + +static int lpc18xx_scu_probe(struct platform_device *pdev) +{ + struct lpc18xx_scu_data *scu; + struct resource *res; + int ret; + + scu = devm_kzalloc(&pdev->dev, sizeof(*scu), GFP_KERNEL); + if (!scu) + return -ENOMEM; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + scu->base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(scu->base)) + return PTR_ERR(scu->base); + + scu->clk = devm_clk_get(&pdev->dev, NULL); + if (IS_ERR(scu->clk)) { + dev_err(&pdev->dev, "Input clock not found.\n"); + return PTR_ERR(scu->clk); + } + + ret = clk_prepare_enable(scu->clk); + if (ret) { + dev_err(&pdev->dev, "Unable to enable clock.\n"); + return ret; + } + + platform_set_drvdata(pdev, scu); + + scu->pctl = pinctrl_register(&lpc18xx_scu_desc, &pdev->dev, scu); + if (!scu->pctl) { + dev_err(&pdev->dev, "Could not register pinctrl driver\n"); + clk_disable_unprepare(scu->clk); + return -EINVAL; + } + + return 0; +} + +static int lpc18xx_scu_remove(struct platform_device *pdev) +{ + struct lpc18xx_scu_data *scu = platform_get_drvdata(pdev); + + pinctrl_unregister(scu->pctl); + clk_disable_unprepare(scu->clk); + + return 0; +} + +static const struct of_device_id lpc18xx_scu_match[] = { + { .compatible = "nxp,lpc1850-scu" }, + {}, +}; +MODULE_DEVICE_TABLE(of, lpc18xx_scu_match); + +static struct platform_driver lpc18xx_scu_driver = { + .probe = lpc18xx_scu_probe, + .remove = lpc18xx_scu_remove, + .driver = { + .name = "lpc18xx-scu", + .of_match_table = lpc18xx_scu_match, + }, +}; +module_platform_driver(lpc18xx_scu_driver); + +MODULE_AUTHOR("Joachim Eastwood "); +MODULE_DESCRIPTION("Pinctrl driver for NXP LPC18xx/43xx SCU"); +MODULE_LICENSE("GPL v2"); -- cgit v0.10.2 From a9ed9eb6345806917bae87b689a906e97415fd01 Mon Sep 17 00:00:00 2001 From: Joachim Eastwood Date: Tue, 28 Apr 2015 00:14:09 +0200 Subject: pinctrl: add DT bindings for lpc1850-scu pinctrl driver Signed-off-by: Joachim Eastwood Signed-off-by: Linus Walleij diff --git a/Documentation/devicetree/bindings/pinctrl/nxp,lpc1850-scu.txt b/Documentation/devicetree/bindings/pinctrl/nxp,lpc1850-scu.txt new file mode 100644 index 0000000..df0309c --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/nxp,lpc1850-scu.txt @@ -0,0 +1,57 @@ +NXP LPC18xx/43xx SCU pin controller Device Tree Bindings +-------------------------------------------------------- + +Required properties: +- compatible : Should be "nxp,lpc1850-scu" +- reg : Address and length of the register set for the device +- clocks : Clock specifier (see clock bindings for details) + +The lpc1850-scu driver uses the generic pin multiplexing and generic pin +configuration documented in pinctrl-bindings.txt. + +The following generic nodes are supported: + - function + - pins + - bias-disable + - bias-pull-up + - bias-pull-down + - drive-strength + - input-enable + - input-disable + - input-schmitt-enable + - input-schmitt-disable + - slew-rate + +Not all pins support all properties so either refer to the NXP 1850/4350 +user manual or the pin table in the pinctrl-lpc18xx driver for supported +pin properties. + +Example: +pinctrl: pinctrl@40086000 { + compatible = "nxp,lpc1850-scu"; + reg = <0x40086000 0x1000>; + clocks = <&ccu1 CLK_CPU_SCU>; + + i2c0_pins: i2c0-pins { + i2c0_pins_cfg { + pins = "i2c0_scl", "i2c0_sda"; + function = "i2c0"; + input-enable; + }; + }; + + uart0_pins: uart0-pins { + uart0_rx_cfg { + pins = "pf_11"; + function = "uart0"; + bias-disable; + input-enable; + }; + + uart0_tx_cfg { + pins = "pf_10"; + function = "uart0"; + bias-disable; + }; + }; +}; -- cgit v0.10.2 From abbc48e1c2a246d3d10393dec070e02ee150d0ae Mon Sep 17 00:00:00 2001 From: Andrew Bresticker Date: Tue, 28 Apr 2015 18:13:01 -0700 Subject: pinctrl: Add Pistachio SoC pin control binding document Add a device-tree binding document for the pin controller present on the IMG Pistachio SoC. Signed-off-by: Damien Horsley Signed-off-by: Ezequiel Garcia Signed-off-by: Andrew Bresticker Cc: Rob Herring Cc: Pawel Moll Cc: Mark Rutland Cc: Ian Campbell Cc: Kumar Gala Signed-off-by: Linus Walleij diff --git a/Documentation/devicetree/bindings/pinctrl/img,pistachio-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/img,pistachio-pinctrl.txt new file mode 100644 index 0000000..08a4a32 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/img,pistachio-pinctrl.txt @@ -0,0 +1,217 @@ +Imagination Technologies Pistachio SoC pin controllers +====================================================== + +The pin controllers on Pistachio are a combined GPIO controller, (GPIO) +interrupt controller, and pinmux + pinconf device. The system ("east") pin +controller on Pistachio has 99 pins, 90 of which are MFIOs which can be +configured as GPIOs. The 90 GPIOs are divided into 6 banks of up to 16 GPIOs +each. The GPIO banks are represented as sub-nodes of the pad controller node. + +Please refer to pinctrl-bindings.txt, ../gpio/gpio.txt, and +../interrupt-controller/interrupts.txt for generic information regarding +pin controller, GPIO, and interrupt bindings. + +Required properties for pin controller node: +-------------------------------------------- + - compatible: "img,pistachio-system-pinctrl". + - reg: Address range of the pinctrl registers. + +Required properties for GPIO bank sub-nodes: +-------------------------------------------- + - interrupts: Interrupt line for the GPIO bank. + - gpio-controller: Indicates the device is a GPIO controller. + - #gpio-cells: Must be two. The first cell is the GPIO pin number and the + second cell indicates the polarity. See for + a list of possible values. + - interrupt-controller: Indicates the device is an interrupt controller. + - #interrupt-cells: Must be two. The first cell is the GPIO pin number and + the second cell encodes the interrupt flags. See + for a list of valid flags. + +Note that the N GPIO bank sub-nodes *must* be named gpio0, gpio1, ... gpioN-1. + +Required properties for pin configuration sub-nodes: +---------------------------------------------------- + - pins: List of pins to which the configuration applies. See below for a + list of possible pins. + +Optional properties for pin configuration sub-nodes: +---------------------------------------------------- + - function: Mux function for the specified pins. This is not applicable for + non-MFIO pins. See below for a list of valid functions for each pin. + - bias-high-impedance: Enable high-impedance mode. + - bias-pull-up: Enable weak pull-up. + - bias-pull-down: Enable weak pull-down. + - bias-bus-hold: Enable bus-keeper mode. + - drive-strength: Drive strength in mA. Supported values: 2, 4, 8, 12. + - input-schmitt-enable: Enable Schmitt trigger. + - input-schmitt-disable: Disable Schmitt trigger. + - slew-rate: Slew rate control. 0 for slow, 1 for fast. + +Pin Functions +--- --------- +mfio0 spim1 +mfio1 spim1, spim0, uart1 +mfio2 spim1, spim0, uart1 +mfio3 spim1 +mfio4 spim1 +mfio5 spim1 +mfio6 spim1 +mfio7 spim1 +mfio8 spim0 +mfio9 spim0 +mfio10 spim0 +mfio11 spis +mfio12 spis +mfio13 spis +mfio14 spis +mfio15 sdhost, mips_trace_clk, mips_trace_data +mfio16 sdhost, mips_trace_dint, mips_trace_data +mfio17 sdhost, mips_trace_trigout, mips_trace_data +mfio18 sdhost, mips_trace_trigin, mips_trace_data +mfio19 sdhost, mips_trace_dm, mips_trace_data +mfio20 sdhost, mips_trace_probe_n, mips_trace_data +mfio21 sdhost, mips_trace_data +mfio22 sdhost, mips_trace_data +mfio23 sdhost +mfio24 sdhost +mfio25 sdhost +mfio26 sdhost +mfio27 sdhost +mfio28 i2c0, spim0 +mfio29 i2c0, spim0 +mfio30 i2c1, spim0 +mfio31 i2c1, spim1 +mfio32 i2c2 +mfio33 i2c2 +mfio34 i2c3 +mfio35 i2c3 +mfio36 i2s_out, audio_clk_in +mfio37 i2s_out, debug_raw_cca_ind +mfio38 i2s_out, debug_ed_sec20_cca_ind +mfio39 i2s_out, debug_ed_sec40_cca_ind +mfio40 i2s_out, debug_agc_done_0 +mfio41 i2s_out, debug_agc_done_1 +mfio42 i2s_out, debug_ed_cca_ind +mfio43 i2s_out, debug_s2l_done +mfio44 i2s_out +mfio45 i2s_dac_clk, audio_sync +mfio46 audio_trigger +mfio47 i2s_in +mfio48 i2s_in +mfio49 i2s_in +mfio50 i2s_in +mfio51 i2s_in +mfio52 i2s_in +mfio53 i2s_in +mfio54 i2s_in, spdif_in +mfio55 uart0, spim0, spim1 +mfio56 uart0, spim0, spim1 +mfio57 uart0, spim0, spim1 +mfio58 uart0, spim1 +mfio59 uart1 +mfio60 uart1 +mfio61 spdif_out +mfio62 spdif_in +mfio63 eth, mips_trace_clk, mips_trace_data +mfio64 eth, mips_trace_dint, mips_trace_data +mfio65 eth, mips_trace_trigout, mips_trace_data +mfio66 eth, mips_trace_trigin, mips_trace_data +mfio67 eth, mips_trace_dm, mips_trace_data +mfio68 eth, mips_trace_probe_n, mips_trace_data +mfio69 eth, mips_trace_data +mfio70 eth, mips_trace_data +mfio71 eth +mfio72 ir +mfio73 pwmpdm, mips_trace_clk, sram_debug +mfio74 pwmpdm, mips_trace_dint, sram_debug +mfio75 pwmpdm, mips_trace_trigout, rom_debug +mfio76 pwmpdm, mips_trace_trigin, rom_debug +mfio77 mdc_debug, mips_trace_dm, rpu_debug +mfio78 mdc_debug, mips_trace_probe_n, rpu_debug +mfio79 ddr_debug, mips_trace_data, mips_debug +mfio80 ddr_debug, mips_trace_data, mips_debug +mfio81 dreq0, mips_trace_data, eth_debug +mfio82 dreq1, mips_trace_data, eth_debug +mfio83 mips_pll_lock, mips_trace_data, usb_debug +mfio84 sys_pll_lock, mips_trace_data, usb_debug +mfio85 wifi_pll_lock, mips_trace_data, sdhost_debug +mfio86 bt_pll_lock, mips_trace_data, sdhost_debug +mfio87 rpu_v_pll_lock, dreq2, socif_debug +mfio88 rpu_l_pll_lock, dreq3, socif_debug +mfio89 audio_pll_lock, dreq4, dreq5 +tck +trstn +tdi +tms +tdo +jtag_comply +safe_mode +por_disable +resetn + +Example: +-------- +pinctrl@18101C00 { + compatible = "img,pistachio-system-pinctrl"; + reg = <0x18101C00 0x400>; + + gpio0: gpio0 { + interrupts = ; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + ... + + gpio5: gpio5 { + interrupts = ; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + ... + + uart0_xfer: uart0-xfer { + uart0-rxd { + pins = "mfio55"; + function = "uart0"; + }; + uart0-txd { + pins = "mfio56"; + function = "uart0"; + }; + }; + + uart0_rts_cts: uart0-rts-cts { + uart0-rts { + pins = "mfio57"; + function = "uart0"; + }; + uart0-cts { + pins = "mfio58"; + function = "uart0"; + }; + }; +}; + +uart@... { + ... + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer>, <&uart0_rts_cts>; + ... +}; + +usb_vbus: fixed-regulator { + ... + gpio = <&gpio5 6 GPIO_ACTIVE_HIGH>; + ... +}; -- cgit v0.10.2 From c30024a6449070d6fde51a8bddf4c97f884db2cc Mon Sep 17 00:00:00 2001 From: Frank Li Date: Wed, 29 Apr 2015 22:20:05 +0800 Subject: pinctrl: add imx7d support Add i.MX7D pinctrl driver support Signed-off-by: Frank Li Signed-off-by: Anson Huang Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/freescale/Kconfig b/drivers/pinctrl/freescale/Kconfig index 16aac38..12ef544 100644 --- a/drivers/pinctrl/freescale/Kconfig +++ b/drivers/pinctrl/freescale/Kconfig @@ -87,6 +87,13 @@ config PINCTRL_IMX6SX help Say Y here to enable the imx6sx pinctrl driver +config PINCTRL_IMX7D + bool "IMX7D pinctrl driver" + depends on SOC_IMX7D + select PINCTRL_IMX + help + Say Y here to enable the imx7d pinctrl driver + config PINCTRL_VF610 bool "Freescale Vybrid VF610 pinctrl driver" depends on SOC_VF610 diff --git a/drivers/pinctrl/freescale/Makefile b/drivers/pinctrl/freescale/Makefile index bba73c2..343cb43 100644 --- a/drivers/pinctrl/freescale/Makefile +++ b/drivers/pinctrl/freescale/Makefile @@ -12,6 +12,7 @@ obj-$(CONFIG_PINCTRL_IMX6Q) += pinctrl-imx6q.o obj-$(CONFIG_PINCTRL_IMX6Q) += pinctrl-imx6dl.o obj-$(CONFIG_PINCTRL_IMX6SL) += pinctrl-imx6sl.o obj-$(CONFIG_PINCTRL_IMX6SX) += pinctrl-imx6sx.o +obj-$(CONFIG_PINCTRL_IMX7D) += pinctrl-imx7d.o obj-$(CONFIG_PINCTRL_VF610) += pinctrl-vf610.o obj-$(CONFIG_PINCTRL_MXS) += pinctrl-mxs.o obj-$(CONFIG_PINCTRL_IMX23) += pinctrl-imx23.o diff --git a/drivers/pinctrl/freescale/pinctrl-imx7d.c b/drivers/pinctrl/freescale/pinctrl-imx7d.c new file mode 100644 index 0000000..d8ab17e --- /dev/null +++ b/drivers/pinctrl/freescale/pinctrl-imx7d.c @@ -0,0 +1,385 @@ +/* + * Copyright (C) 2014-2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "pinctrl-imx.h" + +enum imx7d_pads { + MX7D_PAD_RESERVE0 = 0, + MX7D_PAD_RESERVE1 = 1, + MX7D_PAD_RESERVE2 = 2, + MX7D_PAD_RESERVE3 = 3, + MX7D_PAD_RESERVE4 = 4, + MX7D_PAD_GPIO1_IO08 = 5, + MX7D_PAD_GPIO1_IO09 = 6, + MX7D_PAD_GPIO1_IO10 = 7, + MX7D_PAD_GPIO1_IO11 = 8, + MX7D_PAD_GPIO1_IO12 = 9, + MX7D_PAD_GPIO1_IO13 = 10, + MX7D_PAD_GPIO1_IO14 = 11, + MX7D_PAD_GPIO1_IO15 = 12, + MX7D_PAD_EPDC_DATA00 = 13, + MX7D_PAD_EPDC_DATA01 = 14, + MX7D_PAD_EPDC_DATA02 = 15, + MX7D_PAD_EPDC_DATA03 = 16, + MX7D_PAD_EPDC_DATA04 = 17, + MX7D_PAD_EPDC_DATA05 = 18, + MX7D_PAD_EPDC_DATA06 = 19, + MX7D_PAD_EPDC_DATA07 = 20, + MX7D_PAD_EPDC_DATA08 = 21, + MX7D_PAD_EPDC_DATA09 = 22, + MX7D_PAD_EPDC_DATA10 = 23, + MX7D_PAD_EPDC_DATA11 = 24, + MX7D_PAD_EPDC_DATA12 = 25, + MX7D_PAD_EPDC_DATA13 = 26, + MX7D_PAD_EPDC_DATA14 = 27, + MX7D_PAD_EPDC_DATA15 = 28, + MX7D_PAD_EPDC_SDCLK = 29, + MX7D_PAD_EPDC_SDLE = 30, + MX7D_PAD_EPDC_SDOE = 31, + MX7D_PAD_EPDC_SDSHR = 32, + MX7D_PAD_EPDC_SDCE0 = 33, + MX7D_PAD_EPDC_SDCE1 = 34, + MX7D_PAD_EPDC_SDCE2 = 35, + MX7D_PAD_EPDC_SDCE3 = 36, + MX7D_PAD_EPDC_GDCLK = 37, + MX7D_PAD_EPDC_GDOE = 38, + MX7D_PAD_EPDC_GDRL = 39, + MX7D_PAD_EPDC_GDSP = 40, + MX7D_PAD_EPDC_BDR0 = 41, + MX7D_PAD_EPDC_BDR1 = 42, + MX7D_PAD_EPDC_PWR_COM = 43, + MX7D_PAD_EPDC_PWR_STAT = 44, + MX7D_PAD_LCD_CLK = 45, + MX7D_PAD_LCD_ENABLE = 46, + MX7D_PAD_LCD_HSYNC = 47, + MX7D_PAD_LCD_VSYNC = 48, + MX7D_PAD_LCD_RESET = 49, + MX7D_PAD_LCD_DATA00 = 50, + MX7D_PAD_LCD_DATA01 = 51, + MX7D_PAD_LCD_DATA02 = 52, + MX7D_PAD_LCD_DATA03 = 53, + MX7D_PAD_LCD_DATA04 = 54, + MX7D_PAD_LCD_DATA05 = 55, + MX7D_PAD_LCD_DATA06 = 56, + MX7D_PAD_LCD_DATA07 = 57, + MX7D_PAD_LCD_DATA08 = 58, + MX7D_PAD_LCD_DATA09 = 59, + MX7D_PAD_LCD_DATA10 = 60, + MX7D_PAD_LCD_DATA11 = 61, + MX7D_PAD_LCD_DATA12 = 62, + MX7D_PAD_LCD_DATA13 = 63, + MX7D_PAD_LCD_DATA14 = 64, + MX7D_PAD_LCD_DATA15 = 65, + MX7D_PAD_LCD_DATA16 = 66, + MX7D_PAD_LCD_DATA17 = 67, + MX7D_PAD_LCD_DATA18 = 68, + MX7D_PAD_LCD_DATA19 = 69, + MX7D_PAD_LCD_DATA20 = 70, + MX7D_PAD_LCD_DATA21 = 71, + MX7D_PAD_LCD_DATA22 = 72, + MX7D_PAD_LCD_DATA23 = 73, + MX7D_PAD_UART1_RX_DATA = 74, + MX7D_PAD_UART1_TX_DATA = 75, + MX7D_PAD_UART2_RX_DATA = 76, + MX7D_PAD_UART2_TX_DATA = 77, + MX7D_PAD_UART3_RX_DATA = 78, + MX7D_PAD_UART3_TX_DATA = 79, + MX7D_PAD_UART3_RTS_B = 80, + MX7D_PAD_UART3_CTS_B = 81, + MX7D_PAD_I2C1_SCL = 82, + MX7D_PAD_I2C1_SDA = 83, + MX7D_PAD_I2C2_SCL = 84, + MX7D_PAD_I2C2_SDA = 85, + MX7D_PAD_I2C3_SCL = 86, + MX7D_PAD_I2C3_SDA = 87, + MX7D_PAD_I2C4_SCL = 88, + MX7D_PAD_I2C4_SDA = 89, + MX7D_PAD_ECSPI1_SCLK = 90, + MX7D_PAD_ECSPI1_MOSI = 91, + MX7D_PAD_ECSPI1_MISO = 92, + MX7D_PAD_ECSPI1_SS0 = 93, + MX7D_PAD_ECSPI2_SCLK = 94, + MX7D_PAD_ECSPI2_MOSI = 95, + MX7D_PAD_ECSPI2_MISO = 96, + MX7D_PAD_ECSPI2_SS0 = 97, + MX7D_PAD_SD1_CD_B = 98, + MX7D_PAD_SD1_WP = 99, + MX7D_PAD_SD1_RESET_B = 100, + MX7D_PAD_SD1_CLK = 101, + MX7D_PAD_SD1_CMD = 102, + MX7D_PAD_SD1_DATA0 = 103, + MX7D_PAD_SD1_DATA1 = 104, + MX7D_PAD_SD1_DATA2 = 105, + MX7D_PAD_SD1_DATA3 = 106, + MX7D_PAD_SD2_CD_B = 107, + MX7D_PAD_SD2_WP = 108, + MX7D_PAD_SD2_RESET_B = 109, + MX7D_PAD_SD2_CLK = 110, + MX7D_PAD_SD2_CMD = 111, + MX7D_PAD_SD2_DATA0 = 112, + MX7D_PAD_SD2_DATA1 = 113, + MX7D_PAD_SD2_DATA2 = 114, + MX7D_PAD_SD2_DATA3 = 115, + MX7D_PAD_SD3_CLK = 116, + MX7D_PAD_SD3_CMD = 117, + MX7D_PAD_SD3_DATA0 = 118, + MX7D_PAD_SD3_DATA1 = 119, + MX7D_PAD_SD3_DATA2 = 120, + MX7D_PAD_SD3_DATA3 = 121, + MX7D_PAD_SD3_DATA4 = 122, + MX7D_PAD_SD3_DATA5 = 123, + MX7D_PAD_SD3_DATA6 = 124, + MX7D_PAD_SD3_DATA7 = 125, + MX7D_PAD_SD3_STROBE = 126, + MX7D_PAD_SD3_RESET_B = 127, + MX7D_PAD_SAI1_RX_DATA = 128, + MX7D_PAD_SAI1_TX_BCLK = 129, + MX7D_PAD_SAI1_TX_SYNC = 130, + MX7D_PAD_SAI1_TX_DATA = 131, + MX7D_PAD_SAI1_RX_SYNC = 132, + MX7D_PAD_SAI1_RX_BCLK = 133, + MX7D_PAD_SAI1_MCLK = 134, + MX7D_PAD_SAI2_TX_SYNC = 135, + MX7D_PAD_SAI2_TX_BCLK = 136, + MX7D_PAD_SAI2_RX_DATA = 137, + MX7D_PAD_SAI2_TX_DATA = 138, + MX7D_PAD_ENET1_RGMII_RD0 = 139, + MX7D_PAD_ENET1_RGMII_RD1 = 140, + MX7D_PAD_ENET1_RGMII_RD2 = 141, + MX7D_PAD_ENET1_RGMII_RD3 = 142, + MX7D_PAD_ENET1_RGMII_RX_CTL = 143, + MX7D_PAD_ENET1_RGMII_RXC = 144, + MX7D_PAD_ENET1_RGMII_TD0 = 145, + MX7D_PAD_ENET1_RGMII_TD1 = 146, + MX7D_PAD_ENET1_RGMII_TD2 = 147, + MX7D_PAD_ENET1_RGMII_TD3 = 148, + MX7D_PAD_ENET1_RGMII_TX_CTL = 149, + MX7D_PAD_ENET1_RGMII_TXC = 150, + MX7D_PAD_ENET1_TX_CLK = 151, + MX7D_PAD_ENET1_RX_CLK = 152, + MX7D_PAD_ENET1_CRS = 153, + MX7D_PAD_ENET1_COL = 154, +}; + +/* Pad names for the pinmux subsystem */ +static const struct pinctrl_pin_desc imx7d_pinctrl_pads[] = { + IMX_PINCTRL_PIN(MX7D_PAD_RESERVE0), + IMX_PINCTRL_PIN(MX7D_PAD_RESERVE1), + IMX_PINCTRL_PIN(MX7D_PAD_RESERVE2), + IMX_PINCTRL_PIN(MX7D_PAD_RESERVE3), + IMX_PINCTRL_PIN(MX7D_PAD_RESERVE4), + IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO08), + IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO09), + IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO10), + IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO11), + IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO12), + IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO13), + IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO14), + IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO15), + IMX_PINCTRL_PIN(MX7D_PAD_EPDC_DATA00), + IMX_PINCTRL_PIN(MX7D_PAD_EPDC_DATA01), + IMX_PINCTRL_PIN(MX7D_PAD_EPDC_DATA02), + IMX_PINCTRL_PIN(MX7D_PAD_EPDC_DATA03), + IMX_PINCTRL_PIN(MX7D_PAD_EPDC_DATA04), + IMX_PINCTRL_PIN(MX7D_PAD_EPDC_DATA05), + IMX_PINCTRL_PIN(MX7D_PAD_EPDC_DATA06), + IMX_PINCTRL_PIN(MX7D_PAD_EPDC_DATA07), + IMX_PINCTRL_PIN(MX7D_PAD_EPDC_DATA08), + IMX_PINCTRL_PIN(MX7D_PAD_EPDC_DATA09), + IMX_PINCTRL_PIN(MX7D_PAD_EPDC_DATA10), + IMX_PINCTRL_PIN(MX7D_PAD_EPDC_DATA11), + IMX_PINCTRL_PIN(MX7D_PAD_EPDC_DATA12), + IMX_PINCTRL_PIN(MX7D_PAD_EPDC_DATA13), + IMX_PINCTRL_PIN(MX7D_PAD_EPDC_DATA14), + IMX_PINCTRL_PIN(MX7D_PAD_EPDC_DATA15), + IMX_PINCTRL_PIN(MX7D_PAD_EPDC_SDCLK), + IMX_PINCTRL_PIN(MX7D_PAD_EPDC_SDLE), + IMX_PINCTRL_PIN(MX7D_PAD_EPDC_SDOE), + IMX_PINCTRL_PIN(MX7D_PAD_EPDC_SDSHR), + IMX_PINCTRL_PIN(MX7D_PAD_EPDC_SDCE0), + IMX_PINCTRL_PIN(MX7D_PAD_EPDC_SDCE1), + IMX_PINCTRL_PIN(MX7D_PAD_EPDC_SDCE2), + IMX_PINCTRL_PIN(MX7D_PAD_EPDC_SDCE3), + IMX_PINCTRL_PIN(MX7D_PAD_EPDC_GDCLK), + IMX_PINCTRL_PIN(MX7D_PAD_EPDC_GDOE), + IMX_PINCTRL_PIN(MX7D_PAD_EPDC_GDRL), + IMX_PINCTRL_PIN(MX7D_PAD_EPDC_GDSP), + IMX_PINCTRL_PIN(MX7D_PAD_EPDC_BDR0), + IMX_PINCTRL_PIN(MX7D_PAD_EPDC_BDR1), + IMX_PINCTRL_PIN(MX7D_PAD_EPDC_PWR_COM), + IMX_PINCTRL_PIN(MX7D_PAD_EPDC_PWR_STAT), + IMX_PINCTRL_PIN(MX7D_PAD_LCD_CLK), + IMX_PINCTRL_PIN(MX7D_PAD_LCD_ENABLE), + IMX_PINCTRL_PIN(MX7D_PAD_LCD_HSYNC), + IMX_PINCTRL_PIN(MX7D_PAD_LCD_VSYNC), + IMX_PINCTRL_PIN(MX7D_PAD_LCD_RESET), + IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA00), + IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA01), + IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA02), + IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA03), + IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA04), + IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA05), + IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA06), + IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA07), + IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA08), + IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA09), + IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA10), + IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA11), + IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA12), + IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA13), + IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA14), + IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA15), + IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA16), + IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA17), + IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA18), + IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA19), + IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA20), + IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA21), + IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA22), + IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA23), + IMX_PINCTRL_PIN(MX7D_PAD_UART1_RX_DATA), + IMX_PINCTRL_PIN(MX7D_PAD_UART1_TX_DATA), + IMX_PINCTRL_PIN(MX7D_PAD_UART2_RX_DATA), + IMX_PINCTRL_PIN(MX7D_PAD_UART2_TX_DATA), + IMX_PINCTRL_PIN(MX7D_PAD_UART3_RX_DATA), + IMX_PINCTRL_PIN(MX7D_PAD_UART3_TX_DATA), + IMX_PINCTRL_PIN(MX7D_PAD_UART3_RTS_B), + IMX_PINCTRL_PIN(MX7D_PAD_UART3_CTS_B), + IMX_PINCTRL_PIN(MX7D_PAD_I2C1_SCL), + IMX_PINCTRL_PIN(MX7D_PAD_I2C1_SDA), + IMX_PINCTRL_PIN(MX7D_PAD_I2C2_SCL), + IMX_PINCTRL_PIN(MX7D_PAD_I2C2_SDA), + IMX_PINCTRL_PIN(MX7D_PAD_I2C3_SCL), + IMX_PINCTRL_PIN(MX7D_PAD_I2C3_SDA), + IMX_PINCTRL_PIN(MX7D_PAD_I2C4_SCL), + IMX_PINCTRL_PIN(MX7D_PAD_I2C4_SDA), + IMX_PINCTRL_PIN(MX7D_PAD_ECSPI1_SCLK), + IMX_PINCTRL_PIN(MX7D_PAD_ECSPI1_MOSI), + IMX_PINCTRL_PIN(MX7D_PAD_ECSPI1_MISO), + IMX_PINCTRL_PIN(MX7D_PAD_ECSPI1_SS0), + IMX_PINCTRL_PIN(MX7D_PAD_ECSPI2_SCLK), + IMX_PINCTRL_PIN(MX7D_PAD_ECSPI2_MOSI), + IMX_PINCTRL_PIN(MX7D_PAD_ECSPI2_MISO), + IMX_PINCTRL_PIN(MX7D_PAD_ECSPI2_SS0), + IMX_PINCTRL_PIN(MX7D_PAD_SD1_CD_B), + IMX_PINCTRL_PIN(MX7D_PAD_SD1_WP), + IMX_PINCTRL_PIN(MX7D_PAD_SD1_RESET_B), + IMX_PINCTRL_PIN(MX7D_PAD_SD1_CLK), + IMX_PINCTRL_PIN(MX7D_PAD_SD1_CMD), + IMX_PINCTRL_PIN(MX7D_PAD_SD1_DATA0), + IMX_PINCTRL_PIN(MX7D_PAD_SD1_DATA1), + IMX_PINCTRL_PIN(MX7D_PAD_SD1_DATA2), + IMX_PINCTRL_PIN(MX7D_PAD_SD1_DATA3), + IMX_PINCTRL_PIN(MX7D_PAD_SD2_CD_B), + IMX_PINCTRL_PIN(MX7D_PAD_SD2_WP), + IMX_PINCTRL_PIN(MX7D_PAD_SD2_RESET_B), + IMX_PINCTRL_PIN(MX7D_PAD_SD2_CLK), + IMX_PINCTRL_PIN(MX7D_PAD_SD2_CMD), + IMX_PINCTRL_PIN(MX7D_PAD_SD2_DATA0), + IMX_PINCTRL_PIN(MX7D_PAD_SD2_DATA1), + IMX_PINCTRL_PIN(MX7D_PAD_SD2_DATA2), + IMX_PINCTRL_PIN(MX7D_PAD_SD2_DATA3), + IMX_PINCTRL_PIN(MX7D_PAD_SD3_CLK), + IMX_PINCTRL_PIN(MX7D_PAD_SD3_CMD), + IMX_PINCTRL_PIN(MX7D_PAD_SD3_DATA0), + IMX_PINCTRL_PIN(MX7D_PAD_SD3_DATA1), + IMX_PINCTRL_PIN(MX7D_PAD_SD3_DATA2), + IMX_PINCTRL_PIN(MX7D_PAD_SD3_DATA3), + IMX_PINCTRL_PIN(MX7D_PAD_SD3_DATA4), + IMX_PINCTRL_PIN(MX7D_PAD_SD3_DATA5), + IMX_PINCTRL_PIN(MX7D_PAD_SD3_DATA6), + IMX_PINCTRL_PIN(MX7D_PAD_SD3_DATA7), + IMX_PINCTRL_PIN(MX7D_PAD_SD3_STROBE), + IMX_PINCTRL_PIN(MX7D_PAD_SD3_RESET_B), + IMX_PINCTRL_PIN(MX7D_PAD_SAI1_RX_DATA), + IMX_PINCTRL_PIN(MX7D_PAD_SAI1_TX_BCLK), + IMX_PINCTRL_PIN(MX7D_PAD_SAI1_TX_SYNC), + IMX_PINCTRL_PIN(MX7D_PAD_SAI1_TX_DATA), + IMX_PINCTRL_PIN(MX7D_PAD_SAI1_RX_SYNC), + IMX_PINCTRL_PIN(MX7D_PAD_SAI1_RX_BCLK), + IMX_PINCTRL_PIN(MX7D_PAD_SAI1_MCLK), + IMX_PINCTRL_PIN(MX7D_PAD_SAI2_TX_SYNC), + IMX_PINCTRL_PIN(MX7D_PAD_SAI2_TX_BCLK), + IMX_PINCTRL_PIN(MX7D_PAD_SAI2_RX_DATA), + IMX_PINCTRL_PIN(MX7D_PAD_SAI2_TX_DATA), + IMX_PINCTRL_PIN(MX7D_PAD_ENET1_RGMII_RD0), + IMX_PINCTRL_PIN(MX7D_PAD_ENET1_RGMII_RD1), + IMX_PINCTRL_PIN(MX7D_PAD_ENET1_RGMII_RD2), + IMX_PINCTRL_PIN(MX7D_PAD_ENET1_RGMII_RD3), + IMX_PINCTRL_PIN(MX7D_PAD_ENET1_RGMII_RX_CTL), + IMX_PINCTRL_PIN(MX7D_PAD_ENET1_RGMII_RXC), + IMX_PINCTRL_PIN(MX7D_PAD_ENET1_RGMII_TD0), + IMX_PINCTRL_PIN(MX7D_PAD_ENET1_RGMII_TD1), + IMX_PINCTRL_PIN(MX7D_PAD_ENET1_RGMII_TD2), + IMX_PINCTRL_PIN(MX7D_PAD_ENET1_RGMII_TD3), + IMX_PINCTRL_PIN(MX7D_PAD_ENET1_RGMII_TX_CTL), + IMX_PINCTRL_PIN(MX7D_PAD_ENET1_RGMII_TXC), + IMX_PINCTRL_PIN(MX7D_PAD_ENET1_TX_CLK), + IMX_PINCTRL_PIN(MX7D_PAD_ENET1_RX_CLK), + IMX_PINCTRL_PIN(MX7D_PAD_ENET1_CRS), + IMX_PINCTRL_PIN(MX7D_PAD_ENET1_COL), +}; + +static struct imx_pinctrl_soc_info imx7d_pinctrl_info = { + .pins = imx7d_pinctrl_pads, + .npins = ARRAY_SIZE(imx7d_pinctrl_pads), +}; + +static struct of_device_id imx7d_pinctrl_of_match[] = { + { .compatible = "fsl,imx7d-iomuxc", .data = &imx7d_pinctrl_info, }, + { /* sentinel */ } +}; + +static int imx7d_pinctrl_probe(struct platform_device *pdev) +{ + const struct of_device_id *match; + struct imx_pinctrl_soc_info *pinctrl_info; + + match = of_match_device(imx7d_pinctrl_of_match, &pdev->dev); + + if (!match) + return -ENODEV; + + pinctrl_info = (struct imx_pinctrl_soc_info *) match->data; + + return imx_pinctrl_probe(pdev, pinctrl_info); +} + +static struct platform_driver imx7d_pinctrl_driver = { + .driver = { + .name = "imx7d-pinctrl", + .owner = THIS_MODULE, + .of_match_table = of_match_ptr(imx7d_pinctrl_of_match), + }, + .probe = imx7d_pinctrl_probe, + .remove = imx_pinctrl_remove, +}; + +static int __init imx7d_pinctrl_init(void) +{ + return platform_driver_register(&imx7d_pinctrl_driver); +} +arch_initcall(imx7d_pinctrl_init); + +static void __exit imx7d_pinctrl_exit(void) +{ + platform_driver_unregister(&imx7d_pinctrl_driver); +} +module_exit(imx7d_pinctrl_exit); + +MODULE_AUTHOR("Anson Huang "); +MODULE_DESCRIPTION("Freescale imx7d pinctrl driver"); +MODULE_LICENSE("GPL v2"); -- cgit v0.10.2 From fa76a3db7093a527333c380df82a0f158d9b8299 Mon Sep 17 00:00:00 2001 From: Sonic Zhang Date: Thu, 9 Apr 2015 11:13:07 +0800 Subject: pinctrl: allow exlusive GPIO/mux pin allocation Disallow simultaneous use of the the GPIO and peripheral mux functions by setting a flag "strict" in struct pinctrl_desc. The blackfin pinmux and gpio controller doesn't allow user to set up a pin for both GPIO and peripheral function. So, add flag strict in struct pinctrl_desc to check both gpio_owner and mux_owner before approving the pin request. v2-changes: - if strict flag is set, check gpio_owner and mux_onwer in if and else clause v3-changes: - add kerneldoc for this struct - augment Documentation/pinctrl.txt Signed-off-by: Sonic Zhang Signed-off-by: Linus Walleij diff --git a/Documentation/pinctrl.txt b/Documentation/pinctrl.txt index a9b4716..d6b2bed 100644 --- a/Documentation/pinctrl.txt +++ b/Documentation/pinctrl.txt @@ -73,6 +73,7 @@ static struct pinctrl_desc foo_desc = { .pins = foo_pins, .npins = ARRAY_SIZE(foo_pins), .owner = THIS_MODULE, + .strict = true, }; int __init foo_probe(void) @@ -830,6 +831,11 @@ separate memory range only intended for GPIO driving, and the register range dealing with pin config and pin multiplexing get placed into a different memory range and a separate section of the data sheet. +A flag "strict" in struct pinctrl_desc is available to check and deny +simultaneous access to the same pin from GPIO and pin multiplexing +consumers on hardware of this type. The pinctrl driver should set this flag +accordingly. + (B) pin config @@ -850,6 +856,11 @@ possible that the GPIO, pin config and pin multiplex registers are placed into the same memory range and the same section of the data sheet, although that need not be the case. +In some pin controllers, although the physical pins are designed in the same +way as (B), the GPIO function still can't be enabled at the same time as the +peripheral functions. So again the "strict" flag should be set, denying +simultaneous activation by GPIO and other muxed in devices. + From a kernel point of view, however, these are different aspects of the hardware and shall be put into different subsystems: diff --git a/drivers/pinctrl/pinctrl-adi2.c b/drivers/pinctrl/pinctrl-adi2.c index 8434439..fbd4926 100644 --- a/drivers/pinctrl/pinctrl-adi2.c +++ b/drivers/pinctrl/pinctrl-adi2.c @@ -710,6 +710,7 @@ static struct pinctrl_desc adi_pinmux_desc = { .name = DRIVER_NAME, .pctlops = &adi_pctrl_ops, .pmxops = &adi_pinmux_ops, + .strict = true, .owner = THIS_MODULE, }; diff --git a/drivers/pinctrl/pinmux.c b/drivers/pinctrl/pinmux.c index b874458..2546fa7 100644 --- a/drivers/pinctrl/pinmux.c +++ b/drivers/pinctrl/pinmux.c @@ -107,6 +107,13 @@ static int pin_request(struct pinctrl_dev *pctldev, desc->name, desc->gpio_owner, owner); goto out; } + if (pctldev->desc->strict && desc->mux_usecount && + strcmp(desc->mux_owner, owner)) { + dev_err(pctldev->dev, + "pin %s already requested by %s; cannot claim for %s\n", + desc->name, desc->mux_owner, owner); + goto out; + } desc->gpio_owner = owner; } else { @@ -116,6 +123,12 @@ static int pin_request(struct pinctrl_dev *pctldev, desc->name, desc->mux_owner, owner); goto out; } + if (pctldev->desc->strict && desc->gpio_owner) { + dev_err(pctldev->dev, + "pin %s already requested by %s; cannot claim for %s\n", + desc->name, desc->gpio_owner, owner); + goto out; + } desc->mux_usecount++; if (desc->mux_usecount > 1) diff --git a/include/linux/pinctrl/pinctrl.h b/include/linux/pinctrl/pinctrl.h index 66e4697..fc6b034 100644 --- a/include/linux/pinctrl/pinctrl.h +++ b/include/linux/pinctrl/pinctrl.h @@ -114,6 +114,8 @@ struct pinctrl_ops { * of the pins field above * @pctlops: pin control operation vtable, to support global concepts like * grouping of pins, this is optional. + * @strict: check both gpio_owner and mux_owner strictly before approving + the pin request * @pmxops: pinmux operations vtable, if you support pinmuxing in your driver * @confops: pin config operations vtable, if you support pin configuration in * your driver @@ -132,6 +134,7 @@ struct pinctrl_desc { const struct pinctrl_ops *pctlops; const struct pinmux_ops *pmxops; const struct pinconf_ops *confops; + bool strict; struct module *owner; #ifdef CONFIG_GENERIC_PINCONF unsigned int num_custom_params; -- cgit v0.10.2 From 8c4c2016345feefcd289ce2479eb70286d30825a Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Wed, 6 May 2015 14:19:13 +0200 Subject: pinctrl: move strict option to pinmux_ops While the pinmux_ops are ideally just a vtable for pin mux calls, the "strict" setting belongs so intuitively with the pin multiplexing that we should move it here anyway. Putting it in the top pinctrl_desc makes no sense. Cc: Sonic Zhang Signed-off-by: Linus Walleij diff --git a/Documentation/pinctrl.txt b/Documentation/pinctrl.txt index d6b2bed..4976389e 100644 --- a/Documentation/pinctrl.txt +++ b/Documentation/pinctrl.txt @@ -73,7 +73,6 @@ static struct pinctrl_desc foo_desc = { .pins = foo_pins, .npins = ARRAY_SIZE(foo_pins), .owner = THIS_MODULE, - .strict = true, }; int __init foo_probe(void) @@ -715,6 +714,7 @@ static struct pinmux_ops foo_pmxops = { .get_function_name = foo_get_fname, .get_function_groups = foo_get_groups, .set_mux = foo_set_mux, + .strict = true, }; /* Pinmux operations are handled by some pin controller */ diff --git a/drivers/pinctrl/pinctrl-adi2.c b/drivers/pinctrl/pinctrl-adi2.c index fbd4926..49df903 100644 --- a/drivers/pinctrl/pinctrl-adi2.c +++ b/drivers/pinctrl/pinctrl-adi2.c @@ -703,6 +703,7 @@ static struct pinmux_ops adi_pinmux_ops = { .get_function_name = adi_pinmux_get_func_name, .get_function_groups = adi_pinmux_get_groups, .gpio_request_enable = adi_pinmux_request_gpio, + .strict = true, }; @@ -710,7 +711,6 @@ static struct pinctrl_desc adi_pinmux_desc = { .name = DRIVER_NAME, .pctlops = &adi_pctrl_ops, .pmxops = &adi_pinmux_ops, - .strict = true, .owner = THIS_MODULE, }; diff --git a/drivers/pinctrl/pinmux.c b/drivers/pinctrl/pinmux.c index 2546fa7..c58c168 100644 --- a/drivers/pinctrl/pinmux.c +++ b/drivers/pinctrl/pinmux.c @@ -107,7 +107,7 @@ static int pin_request(struct pinctrl_dev *pctldev, desc->name, desc->gpio_owner, owner); goto out; } - if (pctldev->desc->strict && desc->mux_usecount && + if (ops->strict && desc->mux_usecount && strcmp(desc->mux_owner, owner)) { dev_err(pctldev->dev, "pin %s already requested by %s; cannot claim for %s\n", @@ -123,7 +123,7 @@ static int pin_request(struct pinctrl_dev *pctldev, desc->name, desc->mux_owner, owner); goto out; } - if (pctldev->desc->strict && desc->gpio_owner) { + if (ops->strict && desc->gpio_owner) { dev_err(pctldev->dev, "pin %s already requested by %s; cannot claim for %s\n", desc->name, desc->gpio_owner, owner); diff --git a/include/linux/pinctrl/pinctrl.h b/include/linux/pinctrl/pinctrl.h index fc6b034..66e4697 100644 --- a/include/linux/pinctrl/pinctrl.h +++ b/include/linux/pinctrl/pinctrl.h @@ -114,8 +114,6 @@ struct pinctrl_ops { * of the pins field above * @pctlops: pin control operation vtable, to support global concepts like * grouping of pins, this is optional. - * @strict: check both gpio_owner and mux_owner strictly before approving - the pin request * @pmxops: pinmux operations vtable, if you support pinmuxing in your driver * @confops: pin config operations vtable, if you support pin configuration in * your driver @@ -134,7 +132,6 @@ struct pinctrl_desc { const struct pinctrl_ops *pctlops; const struct pinmux_ops *pmxops; const struct pinconf_ops *confops; - bool strict; struct module *owner; #ifdef CONFIG_GENERIC_PINCONF unsigned int num_custom_params; diff --git a/include/linux/pinctrl/pinmux.h b/include/linux/pinctrl/pinmux.h index 511bda9..d3740fa 100644 --- a/include/linux/pinctrl/pinmux.h +++ b/include/linux/pinctrl/pinmux.h @@ -56,6 +56,9 @@ struct pinctrl_dev; * depending on whether the GPIO is configured as input or output, * a direction selector function may be implemented as a backing * to the GPIO controllers that need pin muxing. + * @strict: do not allow simultaneous use of the same pin for GPIO and another + * function. Check both gpio_owner and mux_owner strictly before approving + * the pin request. */ struct pinmux_ops { int (*request) (struct pinctrl_dev *pctldev, unsigned offset); @@ -79,6 +82,7 @@ struct pinmux_ops { struct pinctrl_gpio_range *range, unsigned offset, bool input); + bool strict; }; #endif /* CONFIG_PINMUX */ -- cgit v0.10.2 From a21763a0b1e5a5ab8310f581886d04beadc16616 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Wed, 6 May 2015 14:43:45 +0200 Subject: pinctrl: nomadik: activate strict mux mode This activates strict mode muxing for the Nomadik pin controllers, as these do not allow GPIO and functions to use the same pin simultaneously. Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/nomadik/pinctrl-abx500.c b/drivers/pinctrl/nomadik/pinctrl-abx500.c index 23db4c9..15ccafd 100644 --- a/drivers/pinctrl/nomadik/pinctrl-abx500.c +++ b/drivers/pinctrl/nomadik/pinctrl-abx500.c @@ -787,6 +787,7 @@ static const struct pinmux_ops abx500_pinmux_ops = { .set_mux = abx500_pmx_set, .gpio_request_enable = abx500_gpio_request_enable, .gpio_disable_free = abx500_gpio_disable_free, + .strict = true, }; static int abx500_get_groups_cnt(struct pinctrl_dev *pctldev) diff --git a/drivers/pinctrl/nomadik/pinctrl-nomadik.c b/drivers/pinctrl/nomadik/pinctrl-nomadik.c index a6a2205..0c57edb 100644 --- a/drivers/pinctrl/nomadik/pinctrl-nomadik.c +++ b/drivers/pinctrl/nomadik/pinctrl-nomadik.c @@ -1803,6 +1803,7 @@ static const struct pinmux_ops nmk_pinmux_ops = { .set_mux = nmk_pmx_set, .gpio_request_enable = nmk_gpio_request_enable, .gpio_disable_free = nmk_gpio_disable_free, + .strict = true, }; static int nmk_pin_config_get(struct pinctrl_dev *pctldev, unsigned pin, -- cgit v0.10.2 From 3007d941bef84f78b6cf19cdfd5da80319cd28ae Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Wed, 6 May 2015 14:46:40 +0200 Subject: pinctrl: nomadik: assign chips dynamically Assign GPIO chip and irqchip to the GPIO container dynamically, so we can set a unique name for each GPIO irqchip and see what chip the hwirq offset actually relates to. Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/nomadik/pinctrl-nomadik.c b/drivers/pinctrl/nomadik/pinctrl-nomadik.c index 0c57edb..2589304 100644 --- a/drivers/pinctrl/nomadik/pinctrl-nomadik.c +++ b/drivers/pinctrl/nomadik/pinctrl-nomadik.c @@ -246,6 +246,7 @@ enum nmk_gpio_slpm { struct nmk_gpio_chip { struct gpio_chip chip; + struct irq_chip irqchip; void __iomem *addr; struct clk *clk; unsigned int bank; @@ -842,18 +843,6 @@ static void nmk_gpio_irq_shutdown(struct irq_data *d) clk_disable(nmk_chip->clk); } -static struct irq_chip nmk_gpio_irq_chip = { - .name = "Nomadik-GPIO", - .irq_ack = nmk_gpio_irq_ack, - .irq_mask = nmk_gpio_irq_mask, - .irq_unmask = nmk_gpio_irq_unmask, - .irq_set_type = nmk_gpio_irq_set_type, - .irq_set_wake = nmk_gpio_irq_set_wake, - .irq_startup = nmk_gpio_irq_startup, - .irq_shutdown = nmk_gpio_irq_shutdown, - .flags = IRQCHIP_MASK_ON_SUSPEND, -}; - static void __nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc, u32 status) { @@ -1077,18 +1066,6 @@ static inline void nmk_gpio_dbg_show_one(struct seq_file *s, #define nmk_gpio_dbg_show NULL #endif -/* This structure is replicated for each GPIO block allocated at probe time */ -static struct gpio_chip nmk_gpio_template = { - .request = nmk_gpio_request, - .free = nmk_gpio_free, - .direction_input = nmk_gpio_make_input, - .get = nmk_gpio_get_input, - .direction_output = nmk_gpio_make_output, - .set = nmk_gpio_set_output, - .dbg_show = nmk_gpio_dbg_show, - .can_sleep = false, -}; - void nmk_gpio_clocks_enable(void) { int i; @@ -1190,6 +1167,7 @@ static int nmk_gpio_probe(struct platform_device *dev) struct device_node *np = dev->dev.of_node; struct nmk_gpio_chip *nmk_chip; struct gpio_chip *chip; + struct irq_chip *irqchip; struct resource *res; struct clk *clk; int latent_irq; @@ -1236,19 +1214,40 @@ static int nmk_gpio_probe(struct platform_device *dev) nmk_chip->bank = dev->id; nmk_chip->clk = clk; nmk_chip->addr = base; - nmk_chip->chip = nmk_gpio_template; nmk_chip->parent_irq = irq; nmk_chip->latent_parent_irq = latent_irq; nmk_chip->sleepmode = supports_sleepmode; spin_lock_init(&nmk_chip->lock); chip = &nmk_chip->chip; + chip->request = nmk_gpio_request; + chip->free = nmk_gpio_free; + chip->direction_input = nmk_gpio_make_input; + chip->get = nmk_gpio_get_input; + chip->direction_output = nmk_gpio_make_output; + chip->set = nmk_gpio_set_output; + chip->dbg_show = nmk_gpio_dbg_show; + chip->can_sleep = false; chip->base = dev->id * NMK_GPIO_PER_CHIP; chip->ngpio = NMK_GPIO_PER_CHIP; chip->label = dev_name(&dev->dev); chip->dev = &dev->dev; chip->owner = THIS_MODULE; + irqchip = &nmk_chip->irqchip; + irqchip->irq_ack = nmk_gpio_irq_ack; + irqchip->irq_mask = nmk_gpio_irq_mask; + irqchip->irq_unmask = nmk_gpio_irq_unmask; + irqchip->irq_set_type = nmk_gpio_irq_set_type; + irqchip->irq_set_wake = nmk_gpio_irq_set_wake; + irqchip->irq_startup = nmk_gpio_irq_startup; + irqchip->irq_shutdown = nmk_gpio_irq_shutdown; + irqchip->flags = IRQCHIP_MASK_ON_SUSPEND; + irqchip->name = kasprintf(GFP_KERNEL, "nmk%u-%u-%u", + dev->id, + chip->base, + chip->base + chip->ngpio - 1); + clk_enable(nmk_chip->clk); nmk_chip->lowemi = readl_relaxed(nmk_chip->addr + NMK_GPIO_LOWEMI); clk_disable(nmk_chip->clk); @@ -1269,8 +1268,8 @@ static int nmk_gpio_probe(struct platform_device *dev) * handler will perform the actual work of handling the parent * interrupt. */ - ret = gpiochip_irqchip_add(&nmk_chip->chip, - &nmk_gpio_irq_chip, + ret = gpiochip_irqchip_add(chip, + irqchip, 0, handle_edge_irq, IRQ_TYPE_EDGE_FALLING); @@ -1280,13 +1279,13 @@ static int nmk_gpio_probe(struct platform_device *dev) return -ENODEV; } /* Then register the chain on the parent IRQ */ - gpiochip_set_chained_irqchip(&nmk_chip->chip, - &nmk_gpio_irq_chip, + gpiochip_set_chained_irqchip(chip, + irqchip, nmk_chip->parent_irq, nmk_gpio_irq_handler); if (nmk_chip->latent_parent_irq > 0) - gpiochip_set_chained_irqchip(&nmk_chip->chip, - &nmk_gpio_irq_chip, + gpiochip_set_chained_irqchip(chip, + irqchip, nmk_chip->latent_parent_irq, nmk_gpio_latent_irq_handler); -- cgit v0.10.2 From 83a21727c3fb23844de38f85fb4250bd21961c25 Mon Sep 17 00:00:00 2001 From: Helmut Buchsbaum Date: Sun, 26 Apr 2015 11:32:47 +0200 Subject: pinctrl: zynq: configure SPI SSx pins separately MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Since SCLK, MISO and MOSI are the only mandatory signals at Zynq's SPI interfaces, SS0, SS1 and SS2 have to be configured separately as they may be used as simple GPIO lines. This, of course, has to be considered in the devicetree, so pin controller configuration for e.g. an SPI0 using SS0 and SS1 only might look like the following snippet (derived from the example of chapter "17.5.3 MIO/EMIO" Routing of Zynq-7000 TRM UG585). So MIO20 can now be used as GPIO instead of being occupied by SPI0 SS2 function. Note the separate pinmux function for the slave select signals: pinctrl_spi0_default: spi0-default { mux_spi { function = "spi0"; groups = "spi0_0_grp"; }; mux_ss { function = "spi0_ss"; groups = "spi0_0_ss0_grp", "spi0_0_ss1_grp"; } conf-output { pins = "MIO16", "MIO21"; slew-rate = <0>; bias-disable; low-power-disable; io-standard = <1>; }; conf-input { pins = "MIO17"; slew-rate = <0>; bias-high-impedance; low-power-disable; io-standard = <1>; }; conf-select { pins = "MIO18", "MIO19"; slew-rate = <0>; bias-pull-up; low-power-disable; io-standard = <1>; }; }; pinctrl_gpio0_default { mux { function = "gpio0"; groups = "gpio0_20_grp" }; conf { pins = "MIO20"; slew-rate = <0>; bias-pull-up; low-power-disable; io-standard = <1>; }; }; Signed-off-by: Helmut Buchsbaum Acked-by: Sören Brinkmann Signed-off-by: Linus Walleij diff --git a/Documentation/devicetree/bindings/pinctrl/xlnx,zynq-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/xlnx,zynq-pinctrl.txt index b7b55a9..f488b0f 100644 --- a/Documentation/devicetree/bindings/pinctrl/xlnx,zynq-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/xlnx,zynq-pinctrl.txt @@ -45,8 +45,9 @@ to specify in a pinconf subnode: Valid values for groups are: ethernet0_0_grp, ethernet1_0_grp, mdio0_0_grp, mdio1_0_grp, - qspi0_0_grp, qspi1_0_grp, qspi_fbclk, qspi_cs1_grp, spi0_0_grp, - spi0_1_grp - spi0_2_grp, spi1_0_grp - spi1_3_grp, sdio0_0_grp - sdio0_2_grp, + qspi0_0_grp, qspi1_0_grp, qspi_fbclk, qspi_cs1_grp, spi0_0_grp - spi0_2_grp, + spi0_X_ssY (X=0..2, Y=0..2), spi1_0_grp - spi1_3_grp, + spi1_X_ssY (X=0..3, Y=0..2), sdio0_0_grp - sdio0_2_grp, sdio1_0_grp - sdio1_3_grp, sdio0_emio_wp, sdio0_emio_cd, sdio1_emio_wp, sdio1_emio_cd, smc0_nor, smc0_nor_cs1_grp, smc0_nor_addr25_grp, smc0_nand, can0_0_grp - can0_10_grp, can1_0_grp - can1_11_grp, uart0_0_grp - uart0_10_grp, @@ -59,7 +60,7 @@ to specify in a pinconf subnode: Valid values for function are: ethernet0, ethernet1, mdio0, mdio1, qspi0, qspi1, qspi_fbclk, qspi_cs1, - spi0, spi1, sdio0, sdio0_pc, sdio0_cd, sdio0_wp, + spi0, spi0_ss, spi1, spi1_ss, sdio0, sdio0_pc, sdio0_cd, sdio0_wp, sdio1, sdio1_pc, sdio1_cd, sdio1_wp, smc0_nor, smc0_nor_cs1, smc0_nor_addr25, smc0_nand, can0, can1, uart0, uart1, i2c0, i2c1, ttc0, ttc1, swdt0, gpio0, usb0, usb1 diff --git a/drivers/pinctrl/pinctrl-zynq.c b/drivers/pinctrl/pinctrl-zynq.c index 22280bd..af726b9 100644 --- a/drivers/pinctrl/pinctrl-zynq.c +++ b/drivers/pinctrl/pinctrl-zynq.c @@ -101,6 +101,8 @@ enum zynq_pinmux_functions { ZYNQ_PMUX_qspi_cs1, ZYNQ_PMUX_spi0, ZYNQ_PMUX_spi1, + ZYNQ_PMUX_spi0_ss, + ZYNQ_PMUX_spi1_ss, ZYNQ_PMUX_sdio0, ZYNQ_PMUX_sdio0_pc, ZYNQ_PMUX_sdio0_cd, @@ -196,13 +198,35 @@ static const unsigned int qspi0_0_pins[] = {1, 2, 3, 4, 5, 6}; static const unsigned int qspi1_0_pins[] = {9, 10, 11, 12, 13}; static const unsigned int qspi_cs1_pins[] = {0}; static const unsigned int qspi_fbclk_pins[] = {8}; -static const unsigned int spi0_0_pins[] = {16, 17, 18, 19, 20, 21}; -static const unsigned int spi0_1_pins[] = {28, 29, 30, 31, 32, 33}; -static const unsigned int spi0_2_pins[] = {40, 41, 42, 43, 44, 45}; -static const unsigned int spi1_0_pins[] = {10, 11, 12, 13, 14, 15}; -static const unsigned int spi1_1_pins[] = {22, 23, 24, 25, 26, 27}; -static const unsigned int spi1_2_pins[] = {34, 35, 36, 37, 38, 39}; -static const unsigned int spi1_3_pins[] = {46, 47, 48, 49, 40, 51}; +static const unsigned int spi0_0_pins[] = {16, 17, 21}; +static const unsigned int spi0_0_ss0_pins[] = {18}; +static const unsigned int spi0_0_ss1_pins[] = {19}; +static const unsigned int spi0_0_ss2_pins[] = {20,}; +static const unsigned int spi0_1_pins[] = {28, 29, 33}; +static const unsigned int spi0_1_ss0_pins[] = {30}; +static const unsigned int spi0_1_ss1_pins[] = {31}; +static const unsigned int spi0_1_ss2_pins[] = {32}; +static const unsigned int spi0_2_pins[] = {40, 41, 45}; +static const unsigned int spi0_2_ss0_pins[] = {42}; +static const unsigned int spi0_2_ss1_pins[] = {43}; +static const unsigned int spi0_2_ss2_pins[] = {44}; +static const unsigned int spi1_0_pins[] = {10, 11, 12}; +static const unsigned int spi1_0_ss0_pins[] = {13}; +static const unsigned int spi1_0_ss1_pins[] = {14}; +static const unsigned int spi1_0_ss2_pins[] = {15}; +static const unsigned int spi1_1_pins[] = {22, 23, 24}; +static const unsigned int spi1_1_ss0_pins[] = {25}; +static const unsigned int spi1_1_ss1_pins[] = {26}; +static const unsigned int spi1_1_ss2_pins[] = {27}; +static const unsigned int spi1_2_pins[] = {34, 35, 36}; +static const unsigned int spi1_2_ss0_pins[] = {37}; +static const unsigned int spi1_2_ss1_pins[] = {38}; +static const unsigned int spi1_2_ss2_pins[] = {39}; +static const unsigned int spi1_3_pins[] = {46, 47, 48, 49}; +static const unsigned int spi1_3_ss0_pins[] = {49}; +static const unsigned int spi1_3_ss1_pins[] = {50}; +static const unsigned int spi1_3_ss2_pins[] = {51}; + static const unsigned int sdio0_0_pins[] = {16, 17, 18, 19, 20, 21}; static const unsigned int sdio0_1_pins[] = {28, 29, 30, 31, 32, 33}; static const unsigned int sdio0_2_pins[] = {40, 41, 42, 43, 44, 45}; @@ -379,12 +403,33 @@ struct zynq_pctrl_group zynq_pctrl_groups[] = { DEFINE_ZYNQ_PINCTRL_GRP(qspi_fbclk), DEFINE_ZYNQ_PINCTRL_GRP(qspi_cs1), DEFINE_ZYNQ_PINCTRL_GRP(spi0_0), + DEFINE_ZYNQ_PINCTRL_GRP(spi0_0_ss0), + DEFINE_ZYNQ_PINCTRL_GRP(spi0_0_ss1), + DEFINE_ZYNQ_PINCTRL_GRP(spi0_0_ss2), DEFINE_ZYNQ_PINCTRL_GRP(spi0_1), + DEFINE_ZYNQ_PINCTRL_GRP(spi0_1_ss0), + DEFINE_ZYNQ_PINCTRL_GRP(spi0_1_ss1), + DEFINE_ZYNQ_PINCTRL_GRP(spi0_1_ss2), DEFINE_ZYNQ_PINCTRL_GRP(spi0_2), + DEFINE_ZYNQ_PINCTRL_GRP(spi0_2_ss0), + DEFINE_ZYNQ_PINCTRL_GRP(spi0_2_ss1), + DEFINE_ZYNQ_PINCTRL_GRP(spi0_2_ss2), DEFINE_ZYNQ_PINCTRL_GRP(spi1_0), + DEFINE_ZYNQ_PINCTRL_GRP(spi1_0_ss0), + DEFINE_ZYNQ_PINCTRL_GRP(spi1_0_ss1), + DEFINE_ZYNQ_PINCTRL_GRP(spi1_0_ss2), DEFINE_ZYNQ_PINCTRL_GRP(spi1_1), + DEFINE_ZYNQ_PINCTRL_GRP(spi1_1_ss0), + DEFINE_ZYNQ_PINCTRL_GRP(spi1_1_ss1), + DEFINE_ZYNQ_PINCTRL_GRP(spi1_1_ss2), DEFINE_ZYNQ_PINCTRL_GRP(spi1_2), + DEFINE_ZYNQ_PINCTRL_GRP(spi1_2_ss0), + DEFINE_ZYNQ_PINCTRL_GRP(spi1_2_ss1), + DEFINE_ZYNQ_PINCTRL_GRP(spi1_2_ss2), DEFINE_ZYNQ_PINCTRL_GRP(spi1_3), + DEFINE_ZYNQ_PINCTRL_GRP(spi1_3_ss0), + DEFINE_ZYNQ_PINCTRL_GRP(spi1_3_ss1), + DEFINE_ZYNQ_PINCTRL_GRP(spi1_3_ss2), DEFINE_ZYNQ_PINCTRL_GRP(sdio0_0), DEFINE_ZYNQ_PINCTRL_GRP(sdio0_1), DEFINE_ZYNQ_PINCTRL_GRP(sdio0_2), @@ -552,6 +597,15 @@ static const char * const spi0_groups[] = {"spi0_0_grp", "spi0_1_grp", "spi0_2_grp"}; static const char * const spi1_groups[] = {"spi1_0_grp", "spi1_1_grp", "spi1_2_grp", "spi1_3_grp"}; +static const char * const spi0_ss_groups[] = {"spi0_0_ss0_grp", + "spi0_0_ss1_grp", "spi0_0_ss2_grp", "spi0_1_ss0_grp", + "spi0_1_ss1_grp", "spi0_1_ss2_grp", "spi0_2_ss0_grp", + "spi0_2_ss1_grp", "spi0_2_ss2_grp"}; +static const char * const spi1_ss_groups[] = {"spi1_0_ss0_grp", + "spi1_0_ss1_grp", "spi1_0_ss2_grp", "spi1_1_ss0_grp", + "spi1_1_ss1_grp", "spi1_1_ss2_grp", "spi1_2_ss0_grp", + "spi1_2_ss1_grp", "spi1_2_ss2_grp", "spi1_3_ss0_grp", + "spi1_3_ss1_grp", "spi1_3_ss2_grp"}; static const char * const sdio0_groups[] = {"sdio0_0_grp", "sdio0_1_grp", "sdio0_2_grp"}; static const char * const sdio1_groups[] = {"sdio1_0_grp", "sdio1_1_grp", @@ -742,6 +796,8 @@ static const struct zynq_pinmux_function zynq_pmux_functions[] = { DEFINE_ZYNQ_PINMUX_FUNCTION(qspi_cs1, 1), DEFINE_ZYNQ_PINMUX_FUNCTION(spi0, 0x50), DEFINE_ZYNQ_PINMUX_FUNCTION(spi1, 0x50), + DEFINE_ZYNQ_PINMUX_FUNCTION(spi0_ss, 0x50), + DEFINE_ZYNQ_PINMUX_FUNCTION(spi1_ss, 0x50), DEFINE_ZYNQ_PINMUX_FUNCTION(sdio0, 0x40), DEFINE_ZYNQ_PINMUX_FUNCTION(sdio0_pc, 0xc), DEFINE_ZYNQ_PINMUX_FUNCTION_MUX(sdio0_wp, 0, 130, ZYNQ_SDIO_WP_MASK, -- cgit v0.10.2 From 5fcdf6a7ed95ef3feef2678c39c906cfc5572cfa Mon Sep 17 00:00:00 2001 From: Markus Pargmann Date: Fri, 10 Apr 2015 16:22:38 +0200 Subject: pinctrl: imx: Allow parsing DT without function nodes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The old format to define pinctrl settings for imx in DT has two hierarchy levels. The first level are function device nodes. The second level are pingroups which contain a property fsl,pins. The original intention was to define all pin functions in a single dtsi file and just reference the correct ones in the board files. This idea was rejected some time ago leading to the current design to have all the pinfunctions defined in the board files. So we don't need the function device nodes anymore. This patch changes the pinctrl driver to accept devicetrees which do not have the first hierarchy level, function device nodes. For example karo-tx25 already has such a devicetree. Old devicetrees are still parsed and supported. Signed-off-by: Markus Pargmann Acked-by: Uwe Kleine-König Acked-by: Shawn Guo Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/freescale/pinctrl-imx.c b/drivers/pinctrl/freescale/pinctrl-imx.c index e261f1c..e73e1ed 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx.c +++ b/drivers/pinctrl/freescale/pinctrl-imx.c @@ -606,6 +606,29 @@ static int imx_pinctrl_parse_functions(struct device_node *np, return 0; } +/* + * Check if the DT contains pins in the direct child nodes. This indicates the + * newer DT format to store pins. This function returns true if the first found + * fsl,pins property is in a child of np. Otherwise false is returned. + */ +static bool imx_pinctrl_dt_is_flat_functions(struct device_node *np) +{ + struct device_node *function_np; + struct device_node *pinctrl_np; + + for_each_child_of_node(np, function_np) { + if (of_property_read_bool(function_np, "fsl,pins")) + return true; + + for_each_child_of_node(function_np, pinctrl_np) { + if (of_property_read_bool(pinctrl_np, "fsl,pins")) + return false; + } + } + + return true; +} + static int imx_pinctrl_probe_dt(struct platform_device *pdev, struct imx_pinctrl_soc_info *info) { @@ -613,14 +636,20 @@ static int imx_pinctrl_probe_dt(struct platform_device *pdev, struct device_node *child; u32 nfuncs = 0; u32 i = 0; + bool flat_funcs; if (!np) return -ENODEV; - nfuncs = of_get_child_count(np); - if (nfuncs <= 0) { - dev_err(&pdev->dev, "no functions defined\n"); - return -EINVAL; + flat_funcs = imx_pinctrl_dt_is_flat_functions(np); + if (flat_funcs) { + nfuncs = 1; + } else { + nfuncs = of_get_child_count(np); + if (nfuncs <= 0) { + dev_err(&pdev->dev, "no functions defined\n"); + return -EINVAL; + } } info->nfunctions = nfuncs; @@ -629,16 +658,24 @@ static int imx_pinctrl_probe_dt(struct platform_device *pdev, if (!info->functions) return -ENOMEM; - info->ngroups = 0; - for_each_child_of_node(np, child) - info->ngroups += of_get_child_count(child); + if (flat_funcs) { + info->ngroups = of_get_child_count(np); + } else { + info->ngroups = 0; + for_each_child_of_node(np, child) + info->ngroups += of_get_child_count(child); + } info->groups = devm_kzalloc(&pdev->dev, info->ngroups * sizeof(struct imx_pin_group), GFP_KERNEL); if (!info->groups) return -ENOMEM; - for_each_child_of_node(np, child) - imx_pinctrl_parse_functions(child, info, i++); + if (flat_funcs) { + imx_pinctrl_parse_functions(np, info, 0); + } else { + for_each_child_of_node(np, child) + imx_pinctrl_parse_functions(child, info, i++); + } return 0; } -- cgit v0.10.2 From e5b609537616aae7effb6345c78f7a4f00201fd6 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 27 Apr 2015 21:54:06 +0900 Subject: pinctrl: single: Constify irq_domain_ops The irq_domain_ops are not modified by the driver and the irqdomain core code accepts pointer to a const data. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c index 13b45f2..968e352 100644 --- a/drivers/pinctrl/pinctrl-single.c +++ b/drivers/pinctrl/pinctrl-single.c @@ -1726,7 +1726,7 @@ static int pcs_irqdomain_map(struct irq_domain *d, unsigned int irq, return 0; } -static struct irq_domain_ops pcs_irqdomain_ops = { +static const struct irq_domain_ops pcs_irqdomain_ops = { .map = pcs_irqdomain_map, .xlate = irq_domain_xlate_onecell, }; -- cgit v0.10.2 From 0b354dc4335b230c05d8de3648404943553ca54f Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 27 Apr 2015 21:54:07 +0900 Subject: gpio: Constify irq_domain_ops The irq_domain_ops are not modified by the driver and the irqdomain core code accepts pointer to a const data. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Linus Walleij diff --git a/drivers/gpio/gpio-bcm-kona.c b/drivers/gpio/gpio-bcm-kona.c index b164ce8..cb89f37 100644 --- a/drivers/gpio/gpio-bcm-kona.c +++ b/drivers/gpio/gpio-bcm-kona.c @@ -534,7 +534,7 @@ static void bcm_kona_gpio_irq_unmap(struct irq_domain *d, unsigned int irq) irq_set_chip_data(irq, NULL); } -static struct irq_domain_ops bcm_kona_irq_ops = { +static const struct irq_domain_ops bcm_kona_irq_ops = { .map = bcm_kona_gpio_irq_map, .unmap = bcm_kona_gpio_irq_unmap, .xlate = irq_domain_xlate_twocell, diff --git a/drivers/gpio/gpio-em.c b/drivers/gpio/gpio-em.c index 3cfcfc6..fbf2873 100644 --- a/drivers/gpio/gpio-em.c +++ b/drivers/gpio/gpio-em.c @@ -266,7 +266,7 @@ static int em_gio_irq_domain_map(struct irq_domain *h, unsigned int irq, return 0; } -static struct irq_domain_ops em_gio_irq_domain_ops = { +static const struct irq_domain_ops em_gio_irq_domain_ops = { .map = em_gio_irq_domain_map, .xlate = irq_domain_xlate_twocell, }; diff --git a/drivers/gpio/gpio-grgpio.c b/drivers/gpio/gpio-grgpio.c index 35a0277..0a8f761 100644 --- a/drivers/gpio/gpio-grgpio.c +++ b/drivers/gpio/gpio-grgpio.c @@ -332,7 +332,7 @@ static void grgpio_irq_unmap(struct irq_domain *d, unsigned int irq) spin_unlock_irqrestore(&priv->bgc.lock, flags); } -static struct irq_domain_ops grgpio_irq_domain_ops = { +static const struct irq_domain_ops grgpio_irq_domain_ops = { .map = grgpio_irq_map, .unmap = grgpio_irq_unmap, }; diff --git a/drivers/gpio/gpio-mpc8xxx.c b/drivers/gpio/gpio-mpc8xxx.c index a65b751..20aa66f 100644 --- a/drivers/gpio/gpio-mpc8xxx.c +++ b/drivers/gpio/gpio-mpc8xxx.c @@ -329,7 +329,7 @@ static int mpc8xxx_gpio_irq_map(struct irq_domain *h, unsigned int irq, return 0; } -static struct irq_domain_ops mpc8xxx_gpio_irq_ops = { +static const struct irq_domain_ops mpc8xxx_gpio_irq_ops = { .map = mpc8xxx_gpio_irq_map, .xlate = irq_domain_xlate_twocell, }; diff --git a/drivers/gpio/gpio-sa1100.c b/drivers/gpio/gpio-sa1100.c index bec397a..3fa22da 100644 --- a/drivers/gpio/gpio-sa1100.c +++ b/drivers/gpio/gpio-sa1100.c @@ -160,7 +160,7 @@ static int sa1100_gpio_irqdomain_map(struct irq_domain *d, return 0; } -static struct irq_domain_ops sa1100_gpio_irqdomain_ops = { +static const struct irq_domain_ops sa1100_gpio_irqdomain_ops = { .map = sa1100_gpio_irqdomain_map, .xlate = irq_domain_xlate_onetwocell, }; diff --git a/drivers/gpio/gpio-sodaville.c b/drivers/gpio/gpio-sodaville.c index d8da36c..65bc9f4 100644 --- a/drivers/gpio/gpio-sodaville.c +++ b/drivers/gpio/gpio-sodaville.c @@ -125,7 +125,7 @@ static int sdv_xlate(struct irq_domain *h, struct device_node *node, return 0; } -static struct irq_domain_ops irq_domain_sdv_ops = { +static const struct irq_domain_ops irq_domain_sdv_ops = { .xlate = sdv_xlate, }; -- cgit v0.10.2 From 66eb3bd857f5311f72c7c371f78ddc9c472befba Mon Sep 17 00:00:00 2001 From: Fabian Frederick Date: Mon, 27 Apr 2015 18:04:05 +0200 Subject: pinctrl: use ERR_CAST instead of ERR_PTR/PTR_ERR Inspired by scripts/coccinelle/api/err_cast.cocci Signed-off-by: Fabian Frederick Signed-off-by: Linus Walleij diff --git a/include/linux/pinctrl/consumer.h b/include/linux/pinctrl/consumer.h index 18eccef..d7e5d60 100644 --- a/include/linux/pinctrl/consumer.h +++ b/include/linux/pinctrl/consumer.h @@ -142,7 +142,7 @@ static inline struct pinctrl * __must_check pinctrl_get_select( s = pinctrl_lookup_state(p, name); if (IS_ERR(s)) { pinctrl_put(p); - return ERR_PTR(PTR_ERR(s)); + return ERR_CAST(s); } ret = pinctrl_select_state(p, s); -- cgit v0.10.2 From 592be8d3c1110ae12082399c39eef18ec15c0d1d Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 28 Apr 2015 12:15:07 +0200 Subject: pinctrl: sh-pfc: Remove r8a73a4 platform_device_id entry As of commit 9d07d414d4c33d86 ("ARM: shmobile: r8a73a4: ape6evm: Remove legacy platform"), r8a73a4 is only supported in generic DT-only ARM multi-platform builds. The driver doesn't need to match platform devices by name anymore, hence remove the corresponding platform_device_id entry. Signed-off-by: Geert Uytterhoeven Acked-by: Laurent Pinchart Acked-by: Simon Horman Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c index 7b2c949..287a3d0 100644 --- a/drivers/pinctrl/sh-pfc/core.c +++ b/drivers/pinctrl/sh-pfc/core.c @@ -579,9 +579,6 @@ static int sh_pfc_remove(struct platform_device *pdev) } static const struct platform_device_id sh_pfc_id_table[] = { -#ifdef CONFIG_PINCTRL_PFC_R8A73A4 - { "pfc-r8a73a4", (kernel_ulong_t)&r8a73a4_pinmux_info }, -#endif #ifdef CONFIG_PINCTRL_PFC_R8A7740 { "pfc-r8a7740", (kernel_ulong_t)&r8a7740_pinmux_info }, #endif -- cgit v0.10.2 From b217e4385d7ae59d1628b0ecb4cffa10f16d5864 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 4 May 2015 19:46:57 +0200 Subject: pinctrl: Grammar s/used in as/used as/ Signed-off-by: Geert Uytterhoeven Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/core.c b/drivers/pinctrl/core.c index 89dca77..291099d 100644 --- a/drivers/pinctrl/core.c +++ b/drivers/pinctrl/core.c @@ -558,7 +558,7 @@ int pinctrl_get_group_selector(struct pinctrl_dev *pctldev, } /** - * pinctrl_request_gpio() - request a single pin to be used in as GPIO + * pinctrl_request_gpio() - request a single pin to be used as GPIO * @gpio: the GPIO pin number from the GPIO subsystem number space * * This function should *ONLY* be used from gpiolib-based GPIO drivers, -- cgit v0.10.2 From 551fa5801ef10298aa1f43e5e95355e2dd5cb3bb Mon Sep 17 00:00:00 2001 From: Mika Westerberg Date: Thu, 7 May 2015 12:54:59 +0300 Subject: pinctrl: intel: sunrisepoint: Add Intel Sunrisepoint-H support Intel Sunrisepoint-H is a desktop version of the PCH (Platform Controller Hub). It has slightly different pin configuration compared to the LP version. This patch adds support for Sunrisepoint-H to the existing pinctrl-sunrisepoint.c driver. Signed-off-by: Mika Westerberg Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/intel/pinctrl-sunrisepoint.c b/drivers/pinctrl/intel/pinctrl-sunrisepoint.c index 55d025d..1de9ae5 100644 --- a/drivers/pinctrl/intel/pinctrl-sunrisepoint.c +++ b/drivers/pinctrl/intel/pinctrl-sunrisepoint.c @@ -284,8 +284,271 @@ static const struct intel_pinctrl_soc_data sptlp_soc_data = { .ncommunities = ARRAY_SIZE(sptlp_communities), }; +/* Sunrisepoint-H */ +static const struct pinctrl_pin_desc spth_pins[] = { + /* GPP_A */ + PINCTRL_PIN(0, "RCINB"), + PINCTRL_PIN(1, "LAD_0"), + PINCTRL_PIN(2, "LAD_1"), + PINCTRL_PIN(3, "LAD_2"), + PINCTRL_PIN(4, "LAD_3"), + PINCTRL_PIN(5, "LFRAMEB"), + PINCTRL_PIN(6, "SERIQ"), + PINCTRL_PIN(7, "PIRQAB"), + PINCTRL_PIN(8, "CLKRUNB"), + PINCTRL_PIN(9, "CLKOUT_LPC_0"), + PINCTRL_PIN(10, "CLKOUT_LPC_1"), + PINCTRL_PIN(11, "PMEB"), + PINCTRL_PIN(12, "BM_BUSYB"), + PINCTRL_PIN(13, "SUSWARNB_SUS_PWRDNACK"), + PINCTRL_PIN(14, "SUS_STATB"), + PINCTRL_PIN(15, "SUSACKB"), + PINCTRL_PIN(16, "CLKOUT_48"), + PINCTRL_PIN(17, "ISH_GP_7"), + PINCTRL_PIN(18, "ISH_GP_0"), + PINCTRL_PIN(19, "ISH_GP_1"), + PINCTRL_PIN(20, "ISH_GP_2"), + PINCTRL_PIN(21, "ISH_GP_3"), + PINCTRL_PIN(22, "ISH_GP_4"), + PINCTRL_PIN(23, "ISH_GP_5"), + /* GPP_B */ + PINCTRL_PIN(24, "CORE_VID_0"), + PINCTRL_PIN(25, "CORE_VID_1"), + PINCTRL_PIN(26, "VRALERTB"), + PINCTRL_PIN(27, "CPU_GP_2"), + PINCTRL_PIN(28, "CPU_GP_3"), + PINCTRL_PIN(29, "SRCCLKREQB_0"), + PINCTRL_PIN(30, "SRCCLKREQB_1"), + PINCTRL_PIN(31, "SRCCLKREQB_2"), + PINCTRL_PIN(32, "SRCCLKREQB_3"), + PINCTRL_PIN(33, "SRCCLKREQB_4"), + PINCTRL_PIN(34, "SRCCLKREQB_5"), + PINCTRL_PIN(35, "EXT_PWR_GATEB"), + PINCTRL_PIN(36, "SLP_S0B"), + PINCTRL_PIN(37, "PLTRSTB"), + PINCTRL_PIN(38, "SPKR"), + PINCTRL_PIN(39, "GSPI0_CSB"), + PINCTRL_PIN(40, "GSPI0_CLK"), + PINCTRL_PIN(41, "GSPI0_MISO"), + PINCTRL_PIN(42, "GSPI0_MOSI"), + PINCTRL_PIN(43, "GSPI1_CSB"), + PINCTRL_PIN(44, "GSPI1_CLK"), + PINCTRL_PIN(45, "GSPI1_MISO"), + PINCTRL_PIN(46, "GSPI1_MOSI"), + PINCTRL_PIN(47, "SML1ALERTB"), + /* GPP_C */ + PINCTRL_PIN(48, "SMBCLK"), + PINCTRL_PIN(49, "SMBDATA"), + PINCTRL_PIN(50, "SMBALERTB"), + PINCTRL_PIN(51, "SML0CLK"), + PINCTRL_PIN(52, "SML0DATA"), + PINCTRL_PIN(53, "SML0ALERTB"), + PINCTRL_PIN(54, "SML1CLK"), + PINCTRL_PIN(55, "SML1DATA"), + PINCTRL_PIN(56, "UART0_RXD"), + PINCTRL_PIN(57, "UART0_TXD"), + PINCTRL_PIN(58, "UART0_RTSB"), + PINCTRL_PIN(59, "UART0_CTSB"), + PINCTRL_PIN(60, "UART1_RXD"), + PINCTRL_PIN(61, "UART1_TXD"), + PINCTRL_PIN(62, "UART1_RTSB"), + PINCTRL_PIN(63, "UART1_CTSB"), + PINCTRL_PIN(64, "I2C0_SDA"), + PINCTRL_PIN(65, "I2C0_SCL"), + PINCTRL_PIN(66, "I2C1_SDA"), + PINCTRL_PIN(67, "I2C1_SCL"), + PINCTRL_PIN(68, "UART2_RXD"), + PINCTRL_PIN(69, "UART2_TXD"), + PINCTRL_PIN(70, "UART2_RTSB"), + PINCTRL_PIN(71, "UART2_CTSB"), + /* GPP_D */ + PINCTRL_PIN(72, "SPI1_CSB"), + PINCTRL_PIN(73, "SPI1_CLK"), + PINCTRL_PIN(74, "SPI1_MISO_IO_1"), + PINCTRL_PIN(75, "SPI1_MOSI_IO_0"), + PINCTRL_PIN(76, "ISH_I2C2_SDA"), + PINCTRL_PIN(77, "SSP0_SFRM"), + PINCTRL_PIN(78, "SSP0_TXD"), + PINCTRL_PIN(79, "SSP0_RXD"), + PINCTRL_PIN(80, "SSP0_SCLK"), + PINCTRL_PIN(81, "ISH_SPI_CSB"), + PINCTRL_PIN(82, "ISH_SPI_CLK"), + PINCTRL_PIN(83, "ISH_SPI_MISO"), + PINCTRL_PIN(84, "ISH_SPI_MOSI"), + PINCTRL_PIN(85, "ISH_UART0_RXD"), + PINCTRL_PIN(86, "ISH_UART0_TXD"), + PINCTRL_PIN(87, "ISH_UART0_RTSB"), + PINCTRL_PIN(88, "ISH_UART0_CTSB"), + PINCTRL_PIN(89, "DMIC_CLK_1"), + PINCTRL_PIN(90, "DMIC_DATA_1"), + PINCTRL_PIN(91, "DMIC_CLK_0"), + PINCTRL_PIN(92, "DMIC_DATA_0"), + PINCTRL_PIN(93, "SPI1_IO_2"), + PINCTRL_PIN(94, "SPI1_IO_3"), + PINCTRL_PIN(95, "ISH_I2C2_SCL"), + /* GPP_E */ + PINCTRL_PIN(96, "SATAXPCIE_0"), + PINCTRL_PIN(97, "SATAXPCIE_1"), + PINCTRL_PIN(98, "SATAXPCIE_2"), + PINCTRL_PIN(99, "CPU_GP_0"), + PINCTRL_PIN(100, "SATA_DEVSLP_0"), + PINCTRL_PIN(101, "SATA_DEVSLP_1"), + PINCTRL_PIN(102, "SATA_DEVSLP_2"), + PINCTRL_PIN(103, "CPU_GP_1"), + PINCTRL_PIN(104, "SATA_LEDB"), + PINCTRL_PIN(105, "USB2_OCB_0"), + PINCTRL_PIN(106, "USB2_OCB_1"), + PINCTRL_PIN(107, "USB2_OCB_2"), + PINCTRL_PIN(108, "USB2_OCB_3"), + /* GPP_F */ + PINCTRL_PIN(109, "SATAXPCIE_3"), + PINCTRL_PIN(110, "SATAXPCIE_4"), + PINCTRL_PIN(111, "SATAXPCIE_5"), + PINCTRL_PIN(112, "SATAXPCIE_6"), + PINCTRL_PIN(113, "SATAXPCIE_7"), + PINCTRL_PIN(114, "SATA_DEVSLP_3"), + PINCTRL_PIN(115, "SATA_DEVSLP_4"), + PINCTRL_PIN(116, "SATA_DEVSLP_5"), + PINCTRL_PIN(117, "SATA_DEVSLP_6"), + PINCTRL_PIN(118, "SATA_DEVSLP_7"), + PINCTRL_PIN(119, "SATA_SCLOCK"), + PINCTRL_PIN(120, "SATA_SLOAD"), + PINCTRL_PIN(121, "SATA_SDATAOUT1"), + PINCTRL_PIN(122, "SATA_SDATAOUT0"), + PINCTRL_PIN(123, "GPP_F_14"), + PINCTRL_PIN(124, "USB_OCB_4"), + PINCTRL_PIN(125, "USB_OCB_5"), + PINCTRL_PIN(126, "USB_OCB_6"), + PINCTRL_PIN(127, "USB_OCB_7"), + PINCTRL_PIN(128, "L_VDDEN"), + PINCTRL_PIN(129, "L_BKLTEN"), + PINCTRL_PIN(130, "L_BKLTCTL"), + PINCTRL_PIN(131, "GPP_F_22"), + PINCTRL_PIN(132, "GPP_F_23"), + /* GPP_G */ + PINCTRL_PIN(133, "FAN_TACH_0"), + PINCTRL_PIN(134, "FAN_TACH_1"), + PINCTRL_PIN(135, "FAN_TACH_2"), + PINCTRL_PIN(136, "FAN_TACH_3"), + PINCTRL_PIN(137, "FAN_TACH_4"), + PINCTRL_PIN(138, "FAN_TACH_5"), + PINCTRL_PIN(139, "FAN_TACH_6"), + PINCTRL_PIN(140, "FAN_TACH_7"), + PINCTRL_PIN(141, "FAN_PWM_0"), + PINCTRL_PIN(142, "FAN_PWM_1"), + PINCTRL_PIN(143, "FAN_PWM_2"), + PINCTRL_PIN(144, "FAN_PWM_3"), + PINCTRL_PIN(145, "GSXDOUT"), + PINCTRL_PIN(146, "GSXSLOAD"), + PINCTRL_PIN(147, "GSXDIN"), + PINCTRL_PIN(148, "GSXRESETB"), + PINCTRL_PIN(149, "GSXCLK"), + PINCTRL_PIN(150, "ADR_COMPLETE"), + PINCTRL_PIN(151, "NMIB"), + PINCTRL_PIN(152, "SMIB"), + PINCTRL_PIN(153, "GPP_G_20"), + PINCTRL_PIN(154, "GPP_G_21"), + PINCTRL_PIN(155, "GPP_G_22"), + PINCTRL_PIN(156, "GPP_G_23"), + /* GPP_H */ + PINCTRL_PIN(157, "SRCCLKREQB_6"), + PINCTRL_PIN(158, "SRCCLKREQB_7"), + PINCTRL_PIN(159, "SRCCLKREQB_8"), + PINCTRL_PIN(160, "SRCCLKREQB_9"), + PINCTRL_PIN(161, "SRCCLKREQB_10"), + PINCTRL_PIN(162, "SRCCLKREQB_11"), + PINCTRL_PIN(163, "SRCCLKREQB_12"), + PINCTRL_PIN(164, "SRCCLKREQB_13"), + PINCTRL_PIN(165, "SRCCLKREQB_14"), + PINCTRL_PIN(166, "SRCCLKREQB_15"), + PINCTRL_PIN(167, "SML2CLK"), + PINCTRL_PIN(168, "SML2DATA"), + PINCTRL_PIN(169, "SML2ALERTB"), + PINCTRL_PIN(170, "SML3CLK"), + PINCTRL_PIN(171, "SML3DATA"), + PINCTRL_PIN(172, "SML3ALERTB"), + PINCTRL_PIN(173, "SML4CLK"), + PINCTRL_PIN(174, "SML4DATA"), + PINCTRL_PIN(175, "SML4ALERTB"), + PINCTRL_PIN(176, "ISH_I2C0_SDA"), + PINCTRL_PIN(177, "ISH_I2C0_SCL"), + PINCTRL_PIN(178, "ISH_I2C1_SDA"), + PINCTRL_PIN(179, "ISH_I2C1_SCL"), + PINCTRL_PIN(180, "GPP_H_23"), + /* GPP_I */ + PINCTRL_PIN(181, "DDSP_HDP_0"), + PINCTRL_PIN(182, "DDSP_HDP_1"), + PINCTRL_PIN(183, "DDSP_HDP_2"), + PINCTRL_PIN(184, "DDSP_HDP_3"), + PINCTRL_PIN(185, "EDP_HPD"), + PINCTRL_PIN(186, "DDPB_CTRLCLK"), + PINCTRL_PIN(187, "DDPB_CTRLDATA"), + PINCTRL_PIN(188, "DDPC_CTRLCLK"), + PINCTRL_PIN(189, "DDPC_CTRLDATA"), + PINCTRL_PIN(190, "DDPD_CTRLCLK"), + PINCTRL_PIN(191, "DDPD_CTRLDATA"), +}; + +static const unsigned spth_spi0_pins[] = { 39, 40, 41, 42 }; +static const unsigned spth_spi1_pins[] = { 43, 44, 45, 46 }; +static const unsigned spth_uart0_pins[] = { 56, 57, 58, 59 }; +static const unsigned spth_uart1_pins[] = { 60, 61, 62, 63 }; +static const unsigned spth_uart2_pins[] = { 68, 69, 71, 71 }; +static const unsigned spth_i2c0_pins[] = { 64, 65 }; +static const unsigned spth_i2c1_pins[] = { 66, 67 }; +static const unsigned spth_i2c2_pins[] = { 76, 95 }; + +static const struct intel_pingroup spth_groups[] = { + PIN_GROUP("spi0_grp", spth_spi0_pins, 1), + PIN_GROUP("spi1_grp", spth_spi1_pins, 1), + PIN_GROUP("uart0_grp", spth_uart0_pins, 1), + PIN_GROUP("uart1_grp", spth_uart1_pins, 1), + PIN_GROUP("uart2_grp", spth_uart2_pins, 1), + PIN_GROUP("i2c0_grp", spth_i2c0_pins, 1), + PIN_GROUP("i2c1_grp", spth_i2c1_pins, 1), + PIN_GROUP("i2c2_grp", spth_i2c2_pins, 2), +}; + +static const char * const spth_spi0_groups[] = { "spi0_grp" }; +static const char * const spth_spi1_groups[] = { "spi0_grp" }; +static const char * const spth_uart0_groups[] = { "uart0_grp" }; +static const char * const spth_uart1_groups[] = { "uart1_grp" }; +static const char * const spth_uart2_groups[] = { "uart2_grp" }; +static const char * const spth_i2c0_groups[] = { "i2c0_grp" }; +static const char * const spth_i2c1_groups[] = { "i2c1_grp" }; +static const char * const spth_i2c2_groups[] = { "i2c2_grp" }; + +static const struct intel_function spth_functions[] = { + FUNCTION("spi0", spth_spi0_groups), + FUNCTION("spi1", spth_spi1_groups), + FUNCTION("uart0", spth_uart0_groups), + FUNCTION("uart1", spth_uart1_groups), + FUNCTION("uart2", spth_uart2_groups), + FUNCTION("i2c0", spth_i2c0_groups), + FUNCTION("i2c1", spth_i2c1_groups), + FUNCTION("i2c2", spth_i2c2_groups), +}; + +static const struct intel_community spth_communities[] = { + SPT_COMMUNITY(0, 0, 47), + SPT_COMMUNITY(1, 48, 180), + SPT_COMMUNITY(2, 181, 191), +}; + +static const struct intel_pinctrl_soc_data spth_soc_data = { + .pins = spth_pins, + .npins = ARRAY_SIZE(spth_pins), + .groups = spth_groups, + .ngroups = ARRAY_SIZE(spth_groups), + .functions = spth_functions, + .nfunctions = ARRAY_SIZE(spth_functions), + .communities = spth_communities, + .ncommunities = ARRAY_SIZE(spth_communities), +}; + static const struct acpi_device_id spt_pinctrl_acpi_match[] = { { "INT344B", (kernel_ulong_t)&sptlp_soc_data }, + { "INT345D", (kernel_ulong_t)&spth_soc_data }, { } }; MODULE_DEVICE_TABLE(acpi, spt_pinctrl_acpi_match); -- cgit v0.10.2 From 992161965f60c4f19176026045f82749f30dafa2 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 4 May 2015 16:40:46 +0200 Subject: pinctrl: sh-pfc: r8a7740: Fix typo SCIFAB in comment The last serial port is called "SCIFB", not "SCIFAB". Signed-off-by: Geert Uytterhoeven Acked-by: Laurent Pinchart Reviewed-by: Simon Horman Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c index b486e9d..d0bb145 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c @@ -258,7 +258,7 @@ enum { /* SCIFA7 */ SCIFA7_TXD_MARK, SCIFA7_RXD_MARK, - /* SCIFAB */ + /* SCIFB */ SCIFB_SCK_PORT190_MARK, /* MSEL5CR_17_0 */ SCIFB_RXD_PORT191_MARK, SCIFB_TXD_PORT192_MARK, -- cgit v0.10.2 From 19e1e98fbf68d398bab944244f883ae14535b196 Mon Sep 17 00:00:00 2001 From: Ulrich Hecht Date: Tue, 12 May 2015 11:13:19 +0200 Subject: pinctrl: sh-pfc: Add r8a7793 support Regarding pin control, r8a7791 and r8a7793 are identical, so it is sufficient to add an sh_pfc_soc_info structure to enable r8a7793 support. Signed-off-by: Ulrich Hecht Acked-by: Geert Uytterhoeven Acked-by: Laurent Pinchart Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c index 287a3d0..9655636 100644 --- a/drivers/pinctrl/sh-pfc/core.c +++ b/drivers/pinctrl/sh-pfc/core.c @@ -481,6 +481,12 @@ static const struct of_device_id sh_pfc_of_table[] = { .data = &r8a7791_pinmux_info, }, #endif +#ifdef CONFIG_PINCTRL_PFC_R8A7793 + { + .compatible = "renesas,pfc-r8a7793", + .data = &r8a7793_pinmux_info, + }, +#endif #ifdef CONFIG_PINCTRL_PFC_SH73A0 { .compatible = "renesas,pfc-sh73a0", diff --git a/drivers/pinctrl/sh-pfc/core.h b/drivers/pinctrl/sh-pfc/core.h index 6dc8a6f..b151b77 100644 --- a/drivers/pinctrl/sh-pfc/core.h +++ b/drivers/pinctrl/sh-pfc/core.h @@ -71,6 +71,7 @@ extern const struct sh_pfc_soc_info r8a7778_pinmux_info; extern const struct sh_pfc_soc_info r8a7779_pinmux_info; extern const struct sh_pfc_soc_info r8a7790_pinmux_info; extern const struct sh_pfc_soc_info r8a7791_pinmux_info; +extern const struct sh_pfc_soc_info r8a7793_pinmux_info; extern const struct sh_pfc_soc_info sh7203_pinmux_info; extern const struct sh_pfc_soc_info sh7264_pinmux_info; extern const struct sh_pfc_soc_info sh7269_pinmux_info; diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c index fdd2c87..cbf8ec3 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c @@ -6181,6 +6181,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { { }, }; +#ifdef CONFIG_PINCTRL_PFC_R8A7791 const struct sh_pfc_soc_info r8a7791_pinmux_info = { .name = "r8a77910_pfc", .unlock_reg = 0xe6060000, /* PMMR */ @@ -6199,3 +6200,25 @@ const struct sh_pfc_soc_info r8a7791_pinmux_info = { .gpio_data = pinmux_data, .gpio_data_size = ARRAY_SIZE(pinmux_data), }; +#endif + +#ifdef CONFIG_PINCTRL_PFC_R8A7793 +const struct sh_pfc_soc_info r8a7793_pinmux_info = { + .name = "r8a77930_pfc", + .unlock_reg = 0xe6060000, /* PMMR */ + + .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, + + .pins = pinmux_pins, + .nr_pins = ARRAY_SIZE(pinmux_pins), + .groups = pinmux_groups, + .nr_groups = ARRAY_SIZE(pinmux_groups), + .functions = pinmux_functions, + .nr_functions = ARRAY_SIZE(pinmux_functions), + + .cfg_regs = pinmux_config_regs, + + .gpio_data = pinmux_data, + .gpio_data_size = ARRAY_SIZE(pinmux_data), +}; +#endif -- cgit v0.10.2 From cb0ba73d09a0deb03b292c39b1c39e1d622e66df Mon Sep 17 00:00:00 2001 From: Ulrich Hecht Date: Tue, 12 May 2015 11:13:20 +0200 Subject: pinctrl: sh-pfc: Enable building of r8a7793 PFC support Signed-off-by: Ulrich Hecht Acked-by: Geert Uytterhoeven Acked-by: Laurent Pinchart Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/sh-pfc/Kconfig b/drivers/pinctrl/sh-pfc/Kconfig index 8c4b3d3..5d570fd 100644 --- a/drivers/pinctrl/sh-pfc/Kconfig +++ b/drivers/pinctrl/sh-pfc/Kconfig @@ -55,6 +55,11 @@ config PINCTRL_PFC_R8A7791 depends on ARCH_R8A7791 select PINCTRL_SH_PFC +config PINCTRL_PFC_R8A7793 + def_bool y + depends on ARCH_R8A7793 + select PINCTRL_SH_PFC + config PINCTRL_PFC_SH7203 def_bool y depends on CPU_SUBTYPE_SH7203 diff --git a/drivers/pinctrl/sh-pfc/Makefile b/drivers/pinctrl/sh-pfc/Makefile index f4074e1..11eefcb 100644 --- a/drivers/pinctrl/sh-pfc/Makefile +++ b/drivers/pinctrl/sh-pfc/Makefile @@ -10,6 +10,7 @@ obj-$(CONFIG_PINCTRL_PFC_R8A7778) += pfc-r8a7778.o obj-$(CONFIG_PINCTRL_PFC_R8A7779) += pfc-r8a7779.o obj-$(CONFIG_PINCTRL_PFC_R8A7790) += pfc-r8a7790.o obj-$(CONFIG_PINCTRL_PFC_R8A7791) += pfc-r8a7791.o +obj-$(CONFIG_PINCTRL_PFC_R8A7793) += pfc-r8a7791.o obj-$(CONFIG_PINCTRL_PFC_SH7203) += pfc-sh7203.o obj-$(CONFIG_PINCTRL_PFC_SH7264) += pfc-sh7264.o obj-$(CONFIG_PINCTRL_PFC_SH7269) += pfc-sh7269.o -- cgit v0.10.2 From 7e15a967a2d686bc959a268fd12c50e39d705416 Mon Sep 17 00:00:00 2001 From: Ulrich Hecht Date: Tue, 12 May 2015 11:13:21 +0200 Subject: pinctrl: sh-pfc: Add renesas,pfc-r8a7793 to binding documentation Also renames "R-Car M2" to "R-Car M2-W" to avoid confusion. Signed-off-by: Ulrich Hecht Acked-by: Simon Horman Acked-by: Geert Uytterhoeven Acked-by: Laurent Pinchart Cc: devicetree@vger.kernel.org Signed-off-by: Linus Walleij diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt index bfe72ec..6bcf851 100644 --- a/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt @@ -16,7 +16,8 @@ Required Properties: - "renesas,pfc-r8a7778": for R8A7778 (R-Mobile M1) compatible pin-controller. - "renesas,pfc-r8a7779": for R8A7779 (R-Car H1) compatible pin-controller. - "renesas,pfc-r8a7790": for R8A7790 (R-Car H2) compatible pin-controller. - - "renesas,pfc-r8a7791": for R8A7791 (R-Car M2) compatible pin-controller. + - "renesas,pfc-r8a7791": for R8A7791 (R-Car M2-W) compatible pin-controller. + - "renesas,pfc-r8a7793": for R8A7793 (R-Car M2-N) compatible pin-controller. - "renesas,pfc-sh73a0": for SH73A0 (SH-Mobile AG5) compatible pin-controller. - reg: Base address and length of each memory resource used by the pin -- cgit v0.10.2 From e8e36d2f1873218a2fdaf0b7cd335b84e8be6112 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 28 Apr 2015 12:15:06 +0200 Subject: pinctrl: sh-pfc: r8a73a4: Remove obsolete multi-platform check As of commit 9d07d414d4c33d86 ("ARM: shmobile: r8a73a4: ape6evm: Remove legacy platform"), r8a73a4 is only supported in generic ARM multi-platform builds. Hence CONFIG_ARCH_MULTIPLATFORM is always set, and the check can be removed. Signed-off-by: Geert Uytterhoeven Acked-by: Laurent Pinchart Acked-by: Simon Horman Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c b/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c index 280a56f..ba18d2e 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c @@ -21,10 +21,6 @@ #include #include -#ifndef CONFIG_ARCH_MULTIPLATFORM -#include -#endif - #include "core.h" #include "sh_pfc.h" -- cgit v0.10.2 From 403fbdee4728afc4e5c4b0a24b8eac3b52595b39 Mon Sep 17 00:00:00 2001 From: Joachim Eastwood Date: Wed, 6 May 2015 19:11:21 +0200 Subject: pinctrl: lpc18xx: create pin cap lookup helper Both pconf_get_pin and pconf_set_pin needs to lookup pin cap based on the pin number. Create a common helper function that both functions can use that also handles the case where no pin number is found in the pins array. This also fixes a small bug in pconf_get_pin where pconf_get_i2c0 would use the pins array index rather than the pin number. Signed-off-by: Joachim Eastwood Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/pinctrl-lpc18xx.c b/drivers/pinctrl/pinctrl-lpc18xx.c index 15fe1e2..0facb7e 100644 --- a/drivers/pinctrl/pinctrl-lpc18xx.c +++ b/drivers/pinctrl/pinctrl-lpc18xx.c @@ -729,6 +729,18 @@ static int lpc18xx_pconf_get_pin(enum pin_config_param param, int *arg, u32 reg, return 0; } +static struct lpc18xx_pin_caps *lpc18xx_get_pin_caps(unsigned pin) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(lpc18xx_pins); i++) { + if (lpc18xx_pins[i].number == pin) + return lpc18xx_pins[i].drv_data; + } + + return NULL; +} + static int lpc18xx_pconf_get(struct pinctrl_dev *pctldev, unsigned pin, unsigned long *config) { @@ -737,14 +749,11 @@ static int lpc18xx_pconf_get(struct pinctrl_dev *pctldev, unsigned pin, struct lpc18xx_pin_caps *pin_cap; int ret, arg = 0; u32 reg; - int i; - for (i = 0; i < ARRAY_SIZE(lpc18xx_pins); i++) { - if (lpc18xx_pins[i].number == pin) - pin = i; - } + pin_cap = lpc18xx_get_pin_caps(pin); + if (!pin_cap) + return -EINVAL; - pin_cap = lpc18xx_pins[pin].drv_data; reg = readl(scu->base + pin_cap->offset); if (pin_cap->type == TYPE_I2C0) @@ -905,12 +914,10 @@ static int lpc18xx_pconf_set(struct pinctrl_dev *pctldev, unsigned pin, int ret; int i; - for (i = 0; i < ARRAY_SIZE(lpc18xx_pins); i++) { - if (lpc18xx_pins[i].number == pin) - break; - } + pin_cap = lpc18xx_get_pin_caps(pin); + if (!pin_cap) + return -EINVAL; - pin_cap = lpc18xx_pins[i].drv_data; reg = readl(scu->base + pin_cap->offset); for (i = 0; i < num_configs; i++) { -- cgit v0.10.2 From cefc03e5995e82082b1e4cda4ef565ccdaff1f45 Mon Sep 17 00:00:00 2001 From: Andrew Bresticker Date: Wed, 6 May 2015 12:59:03 -0700 Subject: pinctrl: Add Pistachio SoC pin control driver Add a driver for the pin controller present on the IMG Pistachio SoC. This driver provides pinmux and pinconfig operations as well as GPIO and IRQ chips for the GPIO banks. Changes from v4: - Switched to using gpiochip_add_pin_range(). - Fixed up Kconfig entry. Changes from v3: - Addressed review comments from Ezequiel. Changes from v2: - Removed module stuff which would be compiled out. Changes from v1: - Addressed review comments from Linus. - Changed compatible string to "img,pistachio-system-pinctrl". - Look for GPIO sub-nodes by name. - A couple of bug fixes. Signed-off-by: Damien Horsley Signed-off-by: Govindraj Raja Signed-off-by: Ezequiel Garcia Signed-off-by: Kevin Cernekee Signed-off-by: Andrew Bresticker Cc: James Hartley Cc: James Hogan Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 53ae816..542a12a 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -134,6 +134,14 @@ config PINCTRL_SIRF select PINMUX select GPIOLIB_IRQCHIP +config PINCTRL_PISTACHIO + def_bool y if MACH_PISTACHIO + depends on GPIOLIB + select PINMUX + select GENERIC_PINCONF + select GPIOLIB_IRQCHIP + select OF_GPIO + config PINCTRL_ST bool depends on OF diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index 6a7b4ba..f4216d9 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -18,6 +18,7 @@ obj-$(CONFIG_PINCTRL_AMD) += pinctrl-amd.o obj-$(CONFIG_PINCTRL_FALCON) += pinctrl-falcon.o obj-$(CONFIG_PINCTRL_MESON) += meson/ obj-$(CONFIG_PINCTRL_PALMAS) += pinctrl-palmas.o +obj-$(CONFIG_PINCTRL_PISTACHIO) += pinctrl-pistachio.o obj-$(CONFIG_PINCTRL_ROCKCHIP) += pinctrl-rockchip.o obj-$(CONFIG_PINCTRL_SINGLE) += pinctrl-single.o obj-$(CONFIG_PINCTRL_SIRF) += sirf/ diff --git a/drivers/pinctrl/pinctrl-pistachio.c b/drivers/pinctrl/pinctrl-pistachio.c new file mode 100644 index 0000000..079ce8b --- /dev/null +++ b/drivers/pinctrl/pinctrl-pistachio.c @@ -0,0 +1,1504 @@ +/* + * Pistachio SoC pinctrl driver + * + * Copyright (C) 2014 Imagination Technologies Ltd. + * Copyright (C) 2014 Google, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "pinctrl-utils.h" + +#define PADS_SCHMITT_EN0 0x000 +#define PADS_SCHMITT_EN_REG(pin) (PADS_SCHMITT_EN0 + 0x4 * ((pin) / 32)) +#define PADS_SCHMITT_EN_BIT(pin) BIT((pin) % 32) + +#define PADS_PU_PD0 0x040 +#define PADS_PU_PD_REG(pin) (PADS_PU_PD0 + 0x4 * ((pin) / 16)) +#define PADS_PU_PD_SHIFT(pin) (2 * ((pin) % 16)) +#define PADS_PU_PD_MASK 0x3 +#define PADS_PU_PD_HIGHZ 0x0 +#define PADS_PU_PD_UP 0x1 +#define PADS_PU_PD_DOWN 0x2 +#define PADS_PU_PD_BUS 0x3 + +#define PADS_FUNCTION_SELECT0 0x0c0 +#define PADS_FUNCTION_SELECT1 0x0c4 +#define PADS_FUNCTION_SELECT2 0x0c8 +#define PADS_SCENARIO_SELECT 0x0f8 + +#define PADS_SLEW_RATE0 0x100 +#define PADS_SLEW_RATE_REG(pin) (PADS_SLEW_RATE0 + 0x4 * ((pin) / 32)) +#define PADS_SLEW_RATE_BIT(pin) BIT((pin) % 32) + +#define PADS_DRIVE_STRENGTH0 0x120 +#define PADS_DRIVE_STRENGTH_REG(pin) \ + (PADS_DRIVE_STRENGTH0 + 0x4 * ((pin) / 16)) +#define PADS_DRIVE_STRENGTH_SHIFT(pin) (2 * ((pin) % 16)) +#define PADS_DRIVE_STRENGTH_MASK 0x3 +#define PADS_DRIVE_STRENGTH_2MA 0x0 +#define PADS_DRIVE_STRENGTH_4MA 0x1 +#define PADS_DRIVE_STRENGTH_8MA 0x2 +#define PADS_DRIVE_STRENGTH_12MA 0x3 + +#define GPIO_BANK_BASE(bank) (0x200 + 0x24 * (bank)) + +#define GPIO_BIT_EN 0x00 +#define GPIO_OUTPUT_EN 0x04 +#define GPIO_OUTPUT 0x08 +#define GPIO_INPUT 0x0c +#define GPIO_INPUT_POLARITY 0x10 +#define GPIO_INTERRUPT_TYPE 0x14 +#define GPIO_INTERRUPT_TYPE_LEVEL 0x0 +#define GPIO_INTERRUPT_TYPE_EDGE 0x1 +#define GPIO_INTERRUPT_EDGE 0x18 +#define GPIO_INTERRUPT_EDGE_SINGLE 0x0 +#define GPIO_INTERRUPT_EDGE_DUAL 0x1 +#define GPIO_INTERRUPT_EN 0x1c +#define GPIO_INTERRUPT_STATUS 0x20 + +struct pistachio_function { + const char *name; + const char * const *groups; + unsigned int ngroups; + const int *scenarios; + unsigned int nscenarios; + unsigned int scenario_reg; + unsigned int scenario_shift; + unsigned int scenario_mask; +}; + +struct pistachio_pin_group { + const char *name; + unsigned int pin; + int mux_option[3]; + int mux_reg; + int mux_shift; + int mux_mask; +}; + +struct pistachio_gpio_bank { + struct pistachio_pinctrl *pctl; + void __iomem *base; + unsigned int pin_base; + unsigned int npins; + struct gpio_chip gpio_chip; + struct irq_chip irq_chip; +}; + +struct pistachio_pinctrl { + struct device *dev; + void __iomem *base; + struct pinctrl_dev *pctldev; + const struct pinctrl_pin_desc *pins; + unsigned int npins; + const struct pistachio_function *functions; + unsigned int nfunctions; + const struct pistachio_pin_group *groups; + unsigned int ngroups; + struct pistachio_gpio_bank *gpio_banks; + unsigned int nbanks; +}; + +#define PISTACHIO_PIN_MFIO(p) (p) +#define PISTACHIO_PIN_TCK 90 +#define PISTACHIO_PIN_TRSTN 91 +#define PISTACHIO_PIN_TDI 92 +#define PISTACHIO_PIN_TMS 93 +#define PISTACHIO_PIN_TDO 94 +#define PISTACHIO_PIN_JTAG_COMPLY 95 +#define PISTACHIO_PIN_SAFE_MODE 96 +#define PISTACHIO_PIN_POR_DISABLE 97 +#define PISTACHIO_PIN_RESETN 98 + +#define MFIO_PIN_DESC(p) PINCTRL_PIN(PISTACHIO_PIN_MFIO(p), "mfio" #p) + +static const struct pinctrl_pin_desc pistachio_pins[] = { + MFIO_PIN_DESC(0), + MFIO_PIN_DESC(1), + MFIO_PIN_DESC(2), + MFIO_PIN_DESC(3), + MFIO_PIN_DESC(4), + MFIO_PIN_DESC(5), + MFIO_PIN_DESC(6), + MFIO_PIN_DESC(7), + MFIO_PIN_DESC(8), + MFIO_PIN_DESC(9), + MFIO_PIN_DESC(10), + MFIO_PIN_DESC(11), + MFIO_PIN_DESC(12), + MFIO_PIN_DESC(13), + MFIO_PIN_DESC(14), + MFIO_PIN_DESC(15), + MFIO_PIN_DESC(16), + MFIO_PIN_DESC(17), + MFIO_PIN_DESC(18), + MFIO_PIN_DESC(19), + MFIO_PIN_DESC(20), + MFIO_PIN_DESC(21), + MFIO_PIN_DESC(22), + MFIO_PIN_DESC(23), + MFIO_PIN_DESC(24), + MFIO_PIN_DESC(25), + MFIO_PIN_DESC(26), + MFIO_PIN_DESC(27), + MFIO_PIN_DESC(28), + MFIO_PIN_DESC(29), + MFIO_PIN_DESC(30), + MFIO_PIN_DESC(31), + MFIO_PIN_DESC(32), + MFIO_PIN_DESC(33), + MFIO_PIN_DESC(34), + MFIO_PIN_DESC(35), + MFIO_PIN_DESC(36), + MFIO_PIN_DESC(37), + MFIO_PIN_DESC(38), + MFIO_PIN_DESC(39), + MFIO_PIN_DESC(40), + MFIO_PIN_DESC(41), + MFIO_PIN_DESC(42), + MFIO_PIN_DESC(43), + MFIO_PIN_DESC(44), + MFIO_PIN_DESC(45), + MFIO_PIN_DESC(46), + MFIO_PIN_DESC(47), + MFIO_PIN_DESC(48), + MFIO_PIN_DESC(49), + MFIO_PIN_DESC(50), + MFIO_PIN_DESC(51), + MFIO_PIN_DESC(52), + MFIO_PIN_DESC(53), + MFIO_PIN_DESC(54), + MFIO_PIN_DESC(55), + MFIO_PIN_DESC(56), + MFIO_PIN_DESC(57), + MFIO_PIN_DESC(58), + MFIO_PIN_DESC(59), + MFIO_PIN_DESC(60), + MFIO_PIN_DESC(61), + MFIO_PIN_DESC(62), + MFIO_PIN_DESC(63), + MFIO_PIN_DESC(64), + MFIO_PIN_DESC(65), + MFIO_PIN_DESC(66), + MFIO_PIN_DESC(67), + MFIO_PIN_DESC(68), + MFIO_PIN_DESC(69), + MFIO_PIN_DESC(70), + MFIO_PIN_DESC(71), + MFIO_PIN_DESC(72), + MFIO_PIN_DESC(73), + MFIO_PIN_DESC(74), + MFIO_PIN_DESC(75), + MFIO_PIN_DESC(76), + MFIO_PIN_DESC(77), + MFIO_PIN_DESC(78), + MFIO_PIN_DESC(79), + MFIO_PIN_DESC(80), + MFIO_PIN_DESC(81), + MFIO_PIN_DESC(82), + MFIO_PIN_DESC(83), + MFIO_PIN_DESC(84), + MFIO_PIN_DESC(85), + MFIO_PIN_DESC(86), + MFIO_PIN_DESC(87), + MFIO_PIN_DESC(88), + MFIO_PIN_DESC(89), + PINCTRL_PIN(PISTACHIO_PIN_TCK, "tck"), + PINCTRL_PIN(PISTACHIO_PIN_TRSTN, "trstn"), + PINCTRL_PIN(PISTACHIO_PIN_TDI, "tdi"), + PINCTRL_PIN(PISTACHIO_PIN_TMS, "tms"), + PINCTRL_PIN(PISTACHIO_PIN_TDO, "tdo"), + PINCTRL_PIN(PISTACHIO_PIN_JTAG_COMPLY, "jtag_comply"), + PINCTRL_PIN(PISTACHIO_PIN_SAFE_MODE, "safe_mode"), + PINCTRL_PIN(PISTACHIO_PIN_POR_DISABLE, "por_disable"), + PINCTRL_PIN(PISTACHIO_PIN_RESETN, "resetn"), +}; + +static const char * const pistachio_spim0_groups[] = { + "mfio1", "mfio2", "mfio8", "mfio9", "mfio10", "mfio28", "mfio29", + "mfio30", "mfio55", "mfio56", "mfio57", +}; + +static const char * const pistachio_spim1_groups[] = { + "mfio0", "mfio1", "mfio2", "mfio3", "mfio4", "mfio5", "mfio6", + "mfio7", "mfio31", "mfio55", "mfio56", "mfio57", "mfio58", +}; + +static const char * const pistachio_spis_groups[] = { + "mfio11", "mfio12", "mfio13", "mfio14", +}; + +static const char *const pistachio_sdhost_groups[] = { + "mfio15", "mfio16", "mfio17", "mfio18", "mfio19", "mfio20", + "mfio21", "mfio22", "mfio23", "mfio24", "mfio25", "mfio26", + "mfio27", +}; + +static const char * const pistachio_i2c0_groups[] = { + "mfio28", "mfio29", +}; + +static const char * const pistachio_i2c1_groups[] = { + "mfio30", "mfio31", +}; + +static const char * const pistachio_i2c2_groups[] = { + "mfio32", "mfio33", +}; + +static const char * const pistachio_i2c3_groups[] = { + "mfio34", "mfio35", +}; + +static const char * const pistachio_audio_clk_in_groups[] = { + "mfio36", +}; + +static const char * const pistachio_i2s_out_groups[] = { + "mfio36", "mfio37", "mfio38", "mfio39", "mfio40", "mfio41", + "mfio42", "mfio43", "mfio44", +}; + +static const char * const pistachio_debug_raw_cca_ind_groups[] = { + "mfio37", +}; + +static const char * const pistachio_debug_ed_sec20_cca_ind_groups[] = { + "mfio38", +}; + +static const char * const pistachio_debug_ed_sec40_cca_ind_groups[] = { + "mfio39", +}; + +static const char * const pistachio_debug_agc_done_0_groups[] = { + "mfio40", +}; + +static const char * const pistachio_debug_agc_done_1_groups[] = { + "mfio41", +}; + +static const char * const pistachio_debug_ed_cca_ind_groups[] = { + "mfio42", +}; + +static const char * const pistachio_debug_s2l_done_groups[] = { + "mfio43", +}; + +static const char * const pistachio_i2s_dac_clk_groups[] = { + "mfio45", +}; + +static const char * const pistachio_audio_sync_groups[] = { + "mfio45", +}; + +static const char * const pistachio_audio_trigger_groups[] = { + "mfio46", +}; + +static const char * const pistachio_i2s_in_groups[] = { + "mfio47", "mfio48", "mfio49", "mfio50", "mfio51", "mfio52", + "mfio53", "mfio54", +}; + +static const char * const pistachio_uart0_groups[] = { + "mfio55", "mfio56", "mfio57", "mfio58", +}; + +static const char * const pistachio_uart1_groups[] = { + "mfio59", "mfio60", "mfio1", "mfio2", +}; + +static const char * const pistachio_spdif_out_groups[] = { + "mfio61", +}; + +static const char * const pistachio_spdif_in_groups[] = { + "mfio62", "mfio54", +}; +static const int pistachio_spdif_in_scenarios[] = { + PISTACHIO_PIN_MFIO(62), + PISTACHIO_PIN_MFIO(54), +}; + +static const char * const pistachio_eth_groups[] = { + "mfio63", "mfio64", "mfio65", "mfio66", "mfio67", "mfio68", + "mfio69", "mfio70", "mfio71", +}; + +static const char * const pistachio_ir_groups[] = { + "mfio72", +}; + +static const char * const pistachio_pwmpdm_groups[] = { + "mfio73", "mfio74", "mfio75", "mfio76", +}; + +static const char * const pistachio_mips_trace_clk_groups[] = { + "mfio15", "mfio63", "mfio73", +}; + +static const char * const pistachio_mips_trace_dint_groups[] = { + "mfio16", "mfio64", "mfio74", +}; +static const int pistachio_mips_trace_dint_scenarios[] = { + PISTACHIO_PIN_MFIO(16), + PISTACHIO_PIN_MFIO(64), + PISTACHIO_PIN_MFIO(74), +}; + +static const char * const pistachio_mips_trace_trigout_groups[] = { + "mfio17", "mfio65", "mfio75", +}; + +static const char * const pistachio_mips_trace_trigin_groups[] = { + "mfio18", "mfio66", "mfio76", +}; +static const int pistachio_mips_trace_trigin_scenarios[] = { + PISTACHIO_PIN_MFIO(18), + PISTACHIO_PIN_MFIO(66), + PISTACHIO_PIN_MFIO(76), +}; + +static const char * const pistachio_mips_trace_dm_groups[] = { + "mfio19", "mfio67", "mfio77", +}; + +static const char * const pistachio_mips_probe_n_groups[] = { + "mfio20", "mfio68", "mfio78", +}; +static const int pistachio_mips_probe_n_scenarios[] = { + PISTACHIO_PIN_MFIO(20), + PISTACHIO_PIN_MFIO(68), + PISTACHIO_PIN_MFIO(78), +}; + +static const char * const pistachio_mips_trace_data_groups[] = { + "mfio15", "mfio16", "mfio17", "mfio18", "mfio19", "mfio20", + "mfio21", "mfio22", "mfio63", "mfio64", "mfio65", "mfio66", + "mfio67", "mfio68", "mfio69", "mfio70", "mfio79", "mfio80", + "mfio81", "mfio82", "mfio83", "mfio84", "mfio85", "mfio86", +}; + +static const char * const pistachio_sram_debug_groups[] = { + "mfio73", "mfio74", +}; + +static const char * const pistachio_rom_debug_groups[] = { + "mfio75", "mfio76", +}; + +static const char * const pistachio_rpu_debug_groups[] = { + "mfio77", "mfio78", +}; + +static const char * const pistachio_mips_debug_groups[] = { + "mfio79", "mfio80", +}; + +static const char * const pistachio_eth_debug_groups[] = { + "mfio81", "mfio82", +}; + +static const char * const pistachio_usb_debug_groups[] = { + "mfio83", "mfio84", +}; + +static const char * const pistachio_sdhost_debug_groups[] = { + "mfio85", "mfio86", +}; + +static const char * const pistachio_socif_debug_groups[] = { + "mfio87", "mfio88", +}; + +static const char * const pistachio_mdc_debug_groups[] = { + "mfio77", "mfio78", +}; + +static const char * const pistachio_ddr_debug_groups[] = { + "mfio79", "mfio80", +}; + +static const char * const pistachio_dreq0_groups[] = { + "mfio81", +}; + +static const char * const pistachio_dreq1_groups[] = { + "mfio82", +}; + +static const char * const pistachio_dreq2_groups[] = { + "mfio87", +}; + +static const char * const pistachio_dreq3_groups[] = { + "mfio88", +}; + +static const char * const pistachio_dreq4_groups[] = { + "mfio89", +}; + +static const char * const pistachio_dreq5_groups[] = { + "mfio89", +}; + +static const char * const pistachio_mips_pll_lock_groups[] = { + "mfio83", +}; + +static const char * const pistachio_sys_pll_lock_groups[] = { + "mfio84", +}; + +static const char * const pistachio_wifi_pll_lock_groups[] = { + "mfio85", +}; + +static const char * const pistachio_bt_pll_lock_groups[] = { + "mfio86", +}; + +static const char * const pistachio_rpu_v_pll_lock_groups[] = { + "mfio87", +}; + +static const char * const pistachio_rpu_l_pll_lock_groups[] = { + "mfio88", +}; + +static const char * const pistachio_audio_pll_lock_groups[] = { + "mfio89", +}; + +#define FUNCTION(_name) \ + { \ + .name = #_name, \ + .groups = pistachio_##_name##_groups, \ + .ngroups = ARRAY_SIZE(pistachio_##_name##_groups), \ + } + +#define FUNCTION_SCENARIO(_name, _reg, _shift, _mask) \ + { \ + .name = #_name, \ + .groups = pistachio_##_name##_groups, \ + .ngroups = ARRAY_SIZE(pistachio_##_name##_groups), \ + .scenarios = pistachio_##_name##_scenarios, \ + .nscenarios = ARRAY_SIZE(pistachio_##_name##_scenarios),\ + .scenario_reg = _reg, \ + .scenario_shift = _shift, \ + .scenario_mask = _mask, \ + } + +enum pistachio_mux_option { + PISTACHIO_FUNCTION_NONE = -1, + PISTACHIO_FUNCTION_SPIM0, + PISTACHIO_FUNCTION_SPIM1, + PISTACHIO_FUNCTION_SPIS, + PISTACHIO_FUNCTION_SDHOST, + PISTACHIO_FUNCTION_I2C0, + PISTACHIO_FUNCTION_I2C1, + PISTACHIO_FUNCTION_I2C2, + PISTACHIO_FUNCTION_I2C3, + PISTACHIO_FUNCTION_AUDIO_CLK_IN, + PISTACHIO_FUNCTION_I2S_OUT, + PISTACHIO_FUNCTION_I2S_DAC_CLK, + PISTACHIO_FUNCTION_AUDIO_SYNC, + PISTACHIO_FUNCTION_AUDIO_TRIGGER, + PISTACHIO_FUNCTION_I2S_IN, + PISTACHIO_FUNCTION_UART0, + PISTACHIO_FUNCTION_UART1, + PISTACHIO_FUNCTION_SPDIF_OUT, + PISTACHIO_FUNCTION_SPDIF_IN, + PISTACHIO_FUNCTION_ETH, + PISTACHIO_FUNCTION_IR, + PISTACHIO_FUNCTION_PWMPDM, + PISTACHIO_FUNCTION_MIPS_TRACE_CLK, + PISTACHIO_FUNCTION_MIPS_TRACE_DINT, + PISTACHIO_FUNCTION_MIPS_TRACE_TRIGOUT, + PISTACHIO_FUNCTION_MIPS_TRACE_TRIGIN, + PISTACHIO_FUNCTION_MIPS_TRACE_DM, + PISTACHIO_FUNCTION_MIPS_TRACE_PROBE_N, + PISTACHIO_FUNCTION_MIPS_TRACE_DATA, + PISTACHIO_FUNCTION_SRAM_DEBUG, + PISTACHIO_FUNCTION_ROM_DEBUG, + PISTACHIO_FUNCTION_RPU_DEBUG, + PISTACHIO_FUNCTION_MIPS_DEBUG, + PISTACHIO_FUNCTION_ETH_DEBUG, + PISTACHIO_FUNCTION_USB_DEBUG, + PISTACHIO_FUNCTION_SDHOST_DEBUG, + PISTACHIO_FUNCTION_SOCIF_DEBUG, + PISTACHIO_FUNCTION_MDC_DEBUG, + PISTACHIO_FUNCTION_DDR_DEBUG, + PISTACHIO_FUNCTION_DREQ0, + PISTACHIO_FUNCTION_DREQ1, + PISTACHIO_FUNCTION_DREQ2, + PISTACHIO_FUNCTION_DREQ3, + PISTACHIO_FUNCTION_DREQ4, + PISTACHIO_FUNCTION_DREQ5, + PISTACHIO_FUNCTION_MIPS_PLL_LOCK, + PISTACHIO_FUNCTION_SYS_PLL_LOCK, + PISTACHIO_FUNCTION_WIFI_PLL_LOCK, + PISTACHIO_FUNCTION_BT_PLL_LOCK, + PISTACHIO_FUNCTION_RPU_V_PLL_LOCK, + PISTACHIO_FUNCTION_RPU_L_PLL_LOCK, + PISTACHIO_FUNCTION_AUDIO_PLL_LOCK, + PISTACHIO_FUNCTION_DEBUG_RAW_CCA_IND, + PISTACHIO_FUNCTION_DEBUG_ED_SEC20_CCA_IND, + PISTACHIO_FUNCTION_DEBUG_ED_SEC40_CCA_IND, + PISTACHIO_FUNCTION_DEBUG_AGC_DONE_0, + PISTACHIO_FUNCTION_DEBUG_AGC_DONE_1, + PISTACHIO_FUNCTION_DEBUG_ED_CCA_IND, + PISTACHIO_FUNCTION_DEBUG_S2L_DONE, +}; + +static const struct pistachio_function pistachio_functions[] = { + FUNCTION(spim0), + FUNCTION(spim1), + FUNCTION(spis), + FUNCTION(sdhost), + FUNCTION(i2c0), + FUNCTION(i2c1), + FUNCTION(i2c2), + FUNCTION(i2c3), + FUNCTION(audio_clk_in), + FUNCTION(i2s_out), + FUNCTION(i2s_dac_clk), + FUNCTION(audio_sync), + FUNCTION(audio_trigger), + FUNCTION(i2s_in), + FUNCTION(uart0), + FUNCTION(uart1), + FUNCTION(spdif_out), + FUNCTION_SCENARIO(spdif_in, PADS_SCENARIO_SELECT, 0, 0x1), + FUNCTION(eth), + FUNCTION(ir), + FUNCTION(pwmpdm), + FUNCTION(mips_trace_clk), + FUNCTION_SCENARIO(mips_trace_dint, PADS_SCENARIO_SELECT, 1, 0x3), + FUNCTION(mips_trace_trigout), + FUNCTION_SCENARIO(mips_trace_trigin, PADS_SCENARIO_SELECT, 3, 0x3), + FUNCTION(mips_trace_dm), + FUNCTION_SCENARIO(mips_probe_n, PADS_SCENARIO_SELECT, 5, 0x3), + FUNCTION(mips_trace_data), + FUNCTION(sram_debug), + FUNCTION(rom_debug), + FUNCTION(rpu_debug), + FUNCTION(mips_debug), + FUNCTION(eth_debug), + FUNCTION(usb_debug), + FUNCTION(sdhost_debug), + FUNCTION(socif_debug), + FUNCTION(mdc_debug), + FUNCTION(ddr_debug), + FUNCTION(dreq0), + FUNCTION(dreq1), + FUNCTION(dreq2), + FUNCTION(dreq3), + FUNCTION(dreq4), + FUNCTION(dreq5), + FUNCTION(mips_pll_lock), + FUNCTION(sys_pll_lock), + FUNCTION(wifi_pll_lock), + FUNCTION(bt_pll_lock), + FUNCTION(rpu_v_pll_lock), + FUNCTION(rpu_l_pll_lock), + FUNCTION(audio_pll_lock), + FUNCTION(debug_raw_cca_ind), + FUNCTION(debug_ed_sec20_cca_ind), + FUNCTION(debug_ed_sec40_cca_ind), + FUNCTION(debug_agc_done_0), + FUNCTION(debug_agc_done_1), + FUNCTION(debug_ed_cca_ind), + FUNCTION(debug_s2l_done), +}; + +#define PIN_GROUP(_pin, _name) \ + { \ + .name = #_name, \ + .pin = PISTACHIO_PIN_##_pin, \ + .mux_option = { \ + PISTACHIO_FUNCTION_NONE, \ + PISTACHIO_FUNCTION_NONE, \ + PISTACHIO_FUNCTION_NONE, \ + }, \ + .mux_reg = -1, \ + .mux_shift = -1, \ + .mux_mask = -1, \ + } + +#define MFIO_PIN_GROUP(_pin, _func) \ + { \ + .name = "mfio" #_pin, \ + .pin = PISTACHIO_PIN_MFIO(_pin), \ + .mux_option = { \ + PISTACHIO_FUNCTION_##_func, \ + PISTACHIO_FUNCTION_NONE, \ + PISTACHIO_FUNCTION_NONE, \ + }, \ + .mux_reg = -1, \ + .mux_shift = -1, \ + .mux_mask = -1, \ + } + +#define MFIO_MUX_PIN_GROUP(_pin, _f0, _f1, _f2, _reg, _shift, _mask) \ + { \ + .name = "mfio" #_pin, \ + .pin = PISTACHIO_PIN_MFIO(_pin), \ + .mux_option = { \ + PISTACHIO_FUNCTION_##_f0, \ + PISTACHIO_FUNCTION_##_f1, \ + PISTACHIO_FUNCTION_##_f2, \ + }, \ + .mux_reg = _reg, \ + .mux_shift = _shift, \ + .mux_mask = _mask, \ + } + +static const struct pistachio_pin_group pistachio_groups[] = { + MFIO_PIN_GROUP(0, SPIM1), + MFIO_MUX_PIN_GROUP(1, SPIM1, SPIM0, UART1, + PADS_FUNCTION_SELECT0, 0, 0x3), + MFIO_MUX_PIN_GROUP(2, SPIM1, SPIM0, UART1, + PADS_FUNCTION_SELECT0, 2, 0x3), + MFIO_PIN_GROUP(3, SPIM1), + MFIO_PIN_GROUP(4, SPIM1), + MFIO_PIN_GROUP(5, SPIM1), + MFIO_PIN_GROUP(6, SPIM1), + MFIO_PIN_GROUP(7, SPIM1), + MFIO_PIN_GROUP(8, SPIM0), + MFIO_PIN_GROUP(9, SPIM0), + MFIO_PIN_GROUP(10, SPIM0), + MFIO_PIN_GROUP(11, SPIS), + MFIO_PIN_GROUP(12, SPIS), + MFIO_PIN_GROUP(13, SPIS), + MFIO_PIN_GROUP(14, SPIS), + MFIO_MUX_PIN_GROUP(15, SDHOST, MIPS_TRACE_CLK, MIPS_TRACE_DATA, + PADS_FUNCTION_SELECT0, 4, 0x3), + MFIO_MUX_PIN_GROUP(16, SDHOST, MIPS_TRACE_DINT, MIPS_TRACE_DATA, + PADS_FUNCTION_SELECT0, 6, 0x3), + MFIO_MUX_PIN_GROUP(17, SDHOST, MIPS_TRACE_TRIGOUT, MIPS_TRACE_DATA, + PADS_FUNCTION_SELECT0, 8, 0x3), + MFIO_MUX_PIN_GROUP(18, SDHOST, MIPS_TRACE_TRIGIN, MIPS_TRACE_DATA, + PADS_FUNCTION_SELECT0, 10, 0x3), + MFIO_MUX_PIN_GROUP(19, SDHOST, MIPS_TRACE_DM, MIPS_TRACE_DATA, + PADS_FUNCTION_SELECT0, 12, 0x3), + MFIO_MUX_PIN_GROUP(20, SDHOST, MIPS_TRACE_PROBE_N, MIPS_TRACE_DATA, + PADS_FUNCTION_SELECT0, 14, 0x3), + MFIO_MUX_PIN_GROUP(21, SDHOST, NONE, MIPS_TRACE_DATA, + PADS_FUNCTION_SELECT0, 16, 0x3), + MFIO_MUX_PIN_GROUP(22, SDHOST, NONE, MIPS_TRACE_DATA, + PADS_FUNCTION_SELECT0, 18, 0x3), + MFIO_PIN_GROUP(23, SDHOST), + MFIO_PIN_GROUP(24, SDHOST), + MFIO_PIN_GROUP(25, SDHOST), + MFIO_PIN_GROUP(26, SDHOST), + MFIO_PIN_GROUP(27, SDHOST), + MFIO_MUX_PIN_GROUP(28, I2C0, SPIM0, NONE, + PADS_FUNCTION_SELECT0, 20, 0x1), + MFIO_MUX_PIN_GROUP(29, I2C0, SPIM0, NONE, + PADS_FUNCTION_SELECT0, 21, 0x1), + MFIO_MUX_PIN_GROUP(30, I2C1, SPIM0, NONE, + PADS_FUNCTION_SELECT0, 22, 0x1), + MFIO_MUX_PIN_GROUP(31, I2C1, SPIM1, NONE, + PADS_FUNCTION_SELECT0, 23, 0x1), + MFIO_PIN_GROUP(32, I2C2), + MFIO_PIN_GROUP(33, I2C2), + MFIO_PIN_GROUP(34, I2C3), + MFIO_PIN_GROUP(35, I2C3), + MFIO_MUX_PIN_GROUP(36, I2S_OUT, AUDIO_CLK_IN, NONE, + PADS_FUNCTION_SELECT0, 24, 0x1), + MFIO_MUX_PIN_GROUP(37, I2S_OUT, DEBUG_RAW_CCA_IND, NONE, + PADS_FUNCTION_SELECT0, 25, 0x1), + MFIO_MUX_PIN_GROUP(38, I2S_OUT, DEBUG_ED_SEC20_CCA_IND, NONE, + PADS_FUNCTION_SELECT0, 26, 0x1), + MFIO_MUX_PIN_GROUP(39, I2S_OUT, DEBUG_ED_SEC40_CCA_IND, NONE, + PADS_FUNCTION_SELECT0, 27, 0x1), + MFIO_MUX_PIN_GROUP(40, I2S_OUT, DEBUG_AGC_DONE_0, NONE, + PADS_FUNCTION_SELECT0, 28, 0x1), + MFIO_MUX_PIN_GROUP(41, I2S_OUT, DEBUG_AGC_DONE_1, NONE, + PADS_FUNCTION_SELECT0, 29, 0x1), + MFIO_MUX_PIN_GROUP(42, I2S_OUT, DEBUG_ED_CCA_IND, NONE, + PADS_FUNCTION_SELECT0, 30, 0x1), + MFIO_MUX_PIN_GROUP(43, I2S_OUT, DEBUG_S2L_DONE, NONE, + PADS_FUNCTION_SELECT0, 31, 0x1), + MFIO_PIN_GROUP(44, I2S_OUT), + MFIO_MUX_PIN_GROUP(45, I2S_DAC_CLK, AUDIO_SYNC, NONE, + PADS_FUNCTION_SELECT1, 0, 0x1), + MFIO_PIN_GROUP(46, AUDIO_TRIGGER), + MFIO_PIN_GROUP(47, I2S_IN), + MFIO_PIN_GROUP(48, I2S_IN), + MFIO_PIN_GROUP(49, I2S_IN), + MFIO_PIN_GROUP(50, I2S_IN), + MFIO_PIN_GROUP(51, I2S_IN), + MFIO_PIN_GROUP(52, I2S_IN), + MFIO_PIN_GROUP(53, I2S_IN), + MFIO_MUX_PIN_GROUP(54, I2S_IN, NONE, SPDIF_IN, + PADS_FUNCTION_SELECT1, 1, 0x3), + MFIO_MUX_PIN_GROUP(55, UART0, SPIM0, SPIM1, + PADS_FUNCTION_SELECT1, 3, 0x3), + MFIO_MUX_PIN_GROUP(56, UART0, SPIM0, SPIM1, + PADS_FUNCTION_SELECT1, 5, 0x3), + MFIO_MUX_PIN_GROUP(57, UART0, SPIM0, SPIM1, + PADS_FUNCTION_SELECT1, 7, 0x3), + MFIO_MUX_PIN_GROUP(58, UART0, SPIM1, NONE, + PADS_FUNCTION_SELECT1, 9, 0x1), + MFIO_PIN_GROUP(59, UART1), + MFIO_PIN_GROUP(60, UART1), + MFIO_PIN_GROUP(61, SPDIF_OUT), + MFIO_PIN_GROUP(62, SPDIF_IN), + MFIO_MUX_PIN_GROUP(63, ETH, MIPS_TRACE_CLK, MIPS_TRACE_DATA, + PADS_FUNCTION_SELECT1, 10, 0x3), + MFIO_MUX_PIN_GROUP(64, ETH, MIPS_TRACE_DINT, MIPS_TRACE_DATA, + PADS_FUNCTION_SELECT1, 12, 0x3), + MFIO_MUX_PIN_GROUP(65, ETH, MIPS_TRACE_TRIGOUT, MIPS_TRACE_DATA, + PADS_FUNCTION_SELECT1, 14, 0x3), + MFIO_MUX_PIN_GROUP(66, ETH, MIPS_TRACE_TRIGIN, MIPS_TRACE_DATA, + PADS_FUNCTION_SELECT1, 16, 0x3), + MFIO_MUX_PIN_GROUP(67, ETH, MIPS_TRACE_DM, MIPS_TRACE_DATA, + PADS_FUNCTION_SELECT1, 18, 0x3), + MFIO_MUX_PIN_GROUP(68, ETH, MIPS_TRACE_PROBE_N, MIPS_TRACE_DATA, + PADS_FUNCTION_SELECT1, 20, 0x3), + MFIO_MUX_PIN_GROUP(69, ETH, NONE, MIPS_TRACE_DATA, + PADS_FUNCTION_SELECT1, 22, 0x3), + MFIO_MUX_PIN_GROUP(70, ETH, NONE, MIPS_TRACE_DATA, + PADS_FUNCTION_SELECT1, 24, 0x3), + MFIO_PIN_GROUP(71, ETH), + MFIO_PIN_GROUP(72, IR), + MFIO_MUX_PIN_GROUP(73, PWMPDM, MIPS_TRACE_CLK, SRAM_DEBUG, + PADS_FUNCTION_SELECT1, 26, 0x3), + MFIO_MUX_PIN_GROUP(74, PWMPDM, MIPS_TRACE_DINT, SRAM_DEBUG, + PADS_FUNCTION_SELECT1, 28, 0x3), + MFIO_MUX_PIN_GROUP(75, PWMPDM, MIPS_TRACE_TRIGOUT, ROM_DEBUG, + PADS_FUNCTION_SELECT1, 30, 0x3), + MFIO_MUX_PIN_GROUP(76, PWMPDM, MIPS_TRACE_TRIGIN, ROM_DEBUG, + PADS_FUNCTION_SELECT2, 0, 0x3), + MFIO_MUX_PIN_GROUP(77, MDC_DEBUG, MIPS_TRACE_DM, RPU_DEBUG, + PADS_FUNCTION_SELECT2, 2, 0x3), + MFIO_MUX_PIN_GROUP(78, MDC_DEBUG, MIPS_TRACE_PROBE_N, RPU_DEBUG, + PADS_FUNCTION_SELECT2, 4, 0x3), + MFIO_MUX_PIN_GROUP(79, DDR_DEBUG, MIPS_TRACE_DATA, MIPS_DEBUG, + PADS_FUNCTION_SELECT2, 6, 0x3), + MFIO_MUX_PIN_GROUP(80, DDR_DEBUG, MIPS_TRACE_DATA, MIPS_DEBUG, + PADS_FUNCTION_SELECT2, 8, 0x3), + MFIO_MUX_PIN_GROUP(81, DREQ0, MIPS_TRACE_DATA, ETH_DEBUG, + PADS_FUNCTION_SELECT2, 10, 0x3), + MFIO_MUX_PIN_GROUP(82, DREQ1, MIPS_TRACE_DATA, ETH_DEBUG, + PADS_FUNCTION_SELECT2, 12, 0x3), + MFIO_MUX_PIN_GROUP(83, MIPS_PLL_LOCK, MIPS_TRACE_DATA, USB_DEBUG, + PADS_FUNCTION_SELECT2, 14, 0x3), + MFIO_MUX_PIN_GROUP(84, SYS_PLL_LOCK, MIPS_TRACE_DATA, USB_DEBUG, + PADS_FUNCTION_SELECT2, 16, 0x3), + MFIO_MUX_PIN_GROUP(85, WIFI_PLL_LOCK, MIPS_TRACE_DATA, SDHOST_DEBUG, + PADS_FUNCTION_SELECT2, 18, 0x3), + MFIO_MUX_PIN_GROUP(86, BT_PLL_LOCK, MIPS_TRACE_DATA, SDHOST_DEBUG, + PADS_FUNCTION_SELECT2, 20, 0x3), + MFIO_MUX_PIN_GROUP(87, RPU_V_PLL_LOCK, DREQ2, SOCIF_DEBUG, + PADS_FUNCTION_SELECT2, 22, 0x3), + MFIO_MUX_PIN_GROUP(88, RPU_L_PLL_LOCK, DREQ3, SOCIF_DEBUG, + PADS_FUNCTION_SELECT2, 24, 0x3), + MFIO_MUX_PIN_GROUP(89, AUDIO_PLL_LOCK, DREQ4, DREQ5, + PADS_FUNCTION_SELECT2, 26, 0x3), + PIN_GROUP(TCK, "tck"), + PIN_GROUP(TRSTN, "trstn"), + PIN_GROUP(TDI, "tdi"), + PIN_GROUP(TMS, "tms"), + PIN_GROUP(TDO, "tdo"), + PIN_GROUP(JTAG_COMPLY, "jtag_comply"), + PIN_GROUP(SAFE_MODE, "safe_mode"), + PIN_GROUP(POR_DISABLE, "por_disable"), + PIN_GROUP(RESETN, "resetn"), +}; + +static inline u32 pctl_readl(struct pistachio_pinctrl *pctl, u32 reg) +{ + return readl(pctl->base + reg); +} + +static inline void pctl_writel(struct pistachio_pinctrl *pctl, u32 val, u32 reg) +{ + writel(val, pctl->base + reg); +} + +static inline struct pistachio_gpio_bank *gc_to_bank(struct gpio_chip *gc) +{ + return container_of(gc, struct pistachio_gpio_bank, gpio_chip); +} + +static inline struct pistachio_gpio_bank *irqd_to_bank(struct irq_data *d) +{ + return gc_to_bank(irq_data_get_irq_chip_data(d)); +} + +static inline u32 gpio_readl(struct pistachio_gpio_bank *bank, u32 reg) +{ + return readl(bank->base + reg); +} + +static inline void gpio_writel(struct pistachio_gpio_bank *bank, u32 val, + u32 reg) +{ + writel(val, bank->base + reg); +} + +static inline void gpio_mask_writel(struct pistachio_gpio_bank *bank, + u32 reg, unsigned int bit, u32 val) +{ + /* + * For most of the GPIO registers, bit 16 + X must be set in order to + * write bit X. + */ + gpio_writel(bank, (0x10000 | val) << bit, reg); +} + +static inline void gpio_enable(struct pistachio_gpio_bank *bank, + unsigned offset) +{ + gpio_mask_writel(bank, GPIO_BIT_EN, offset, 1); +} + +static inline void gpio_disable(struct pistachio_gpio_bank *bank, + unsigned offset) +{ + gpio_mask_writel(bank, GPIO_BIT_EN, offset, 0); +} + +static int pistachio_pinctrl_get_groups_count(struct pinctrl_dev *pctldev) +{ + struct pistachio_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); + + return pctl->ngroups; +} + +static const char *pistachio_pinctrl_get_group_name(struct pinctrl_dev *pctldev, + unsigned group) +{ + struct pistachio_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); + + return pctl->groups[group].name; +} + +static int pistachio_pinctrl_get_group_pins(struct pinctrl_dev *pctldev, + unsigned group, + const unsigned **pins, + unsigned *num_pins) +{ + struct pistachio_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); + + *pins = &pctl->groups[group].pin; + *num_pins = 1; + + return 0; +} + +static const struct pinctrl_ops pistachio_pinctrl_ops = { + .get_groups_count = pistachio_pinctrl_get_groups_count, + .get_group_name = pistachio_pinctrl_get_group_name, + .get_group_pins = pistachio_pinctrl_get_group_pins, + .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, + .dt_free_map = pinctrl_utils_dt_free_map, +}; + +static int pistachio_pinmux_get_functions_count(struct pinctrl_dev *pctldev) +{ + struct pistachio_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); + + return pctl->nfunctions; +} + +static const char * +pistachio_pinmux_get_function_name(struct pinctrl_dev *pctldev, unsigned func) +{ + struct pistachio_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); + + return pctl->functions[func].name; +} + +static int pistachio_pinmux_get_function_groups(struct pinctrl_dev *pctldev, + unsigned func, + const char * const **groups, + unsigned * const num_groups) +{ + struct pistachio_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); + + *groups = pctl->functions[func].groups; + *num_groups = pctl->functions[func].ngroups; + + return 0; +} + +static int pistachio_pinmux_enable(struct pinctrl_dev *pctldev, + unsigned func, unsigned group) +{ + struct pistachio_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); + const struct pistachio_pin_group *pg = &pctl->groups[group]; + const struct pistachio_function *pf = &pctl->functions[func]; + struct pinctrl_gpio_range *range; + unsigned int i; + u32 val; + + if (pg->mux_reg > 0) { + for (i = 0; i < ARRAY_SIZE(pg->mux_option); i++) { + if (pg->mux_option[i] == func) + break; + } + if (i == ARRAY_SIZE(pg->mux_option)) { + dev_err(pctl->dev, "Cannot mux pin %u to function %u\n", + group, func); + return -EINVAL; + } + + val = pctl_readl(pctl, pg->mux_reg); + val &= ~(pg->mux_mask << pg->mux_shift); + val |= i << pg->mux_shift; + pctl_writel(pctl, val, pg->mux_reg); + + if (pf->scenarios) { + for (i = 0; i < pf->nscenarios; i++) { + if (pf->scenarios[i] == group) + break; + } + if (WARN_ON(i == pf->nscenarios)) + return -EINVAL; + + val = pctl_readl(pctl, pf->scenario_reg); + val &= ~(pf->scenario_mask << pf->scenario_shift); + val |= i << pf->scenario_shift; + pctl_writel(pctl, val, pf->scenario_reg); + } + } + + range = pinctrl_find_gpio_range_from_pin(pctl->pctldev, pg->pin); + if (range) + gpio_disable(gc_to_bank(range->gc), pg->pin - range->pin_base); + + return 0; +} + +static const struct pinmux_ops pistachio_pinmux_ops = { + .get_functions_count = pistachio_pinmux_get_functions_count, + .get_function_name = pistachio_pinmux_get_function_name, + .get_function_groups = pistachio_pinmux_get_function_groups, + .set_mux = pistachio_pinmux_enable, +}; + +static int pistachio_pinconf_get(struct pinctrl_dev *pctldev, unsigned pin, + unsigned long *config) +{ + struct pistachio_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); + enum pin_config_param param = pinconf_to_config_param(*config); + u32 val, arg; + + switch (param) { + case PIN_CONFIG_INPUT_SCHMITT_ENABLE: + val = pctl_readl(pctl, PADS_SCHMITT_EN_REG(pin)); + arg = !!(val & PADS_SCHMITT_EN_BIT(pin)); + break; + case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: + val = pctl_readl(pctl, PADS_PU_PD_REG(pin)) >> + PADS_PU_PD_SHIFT(pin); + arg = (val & PADS_PU_PD_MASK) == PADS_PU_PD_HIGHZ; + break; + case PIN_CONFIG_BIAS_PULL_UP: + val = pctl_readl(pctl, PADS_PU_PD_REG(pin)) >> + PADS_PU_PD_SHIFT(pin); + arg = (val & PADS_PU_PD_MASK) == PADS_PU_PD_UP; + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + val = pctl_readl(pctl, PADS_PU_PD_REG(pin)) >> + PADS_PU_PD_SHIFT(pin); + arg = (val & PADS_PU_PD_MASK) == PADS_PU_PD_DOWN; + break; + case PIN_CONFIG_BIAS_BUS_HOLD: + val = pctl_readl(pctl, PADS_PU_PD_REG(pin)) >> + PADS_PU_PD_SHIFT(pin); + arg = (val & PADS_PU_PD_MASK) == PADS_PU_PD_BUS; + break; + case PIN_CONFIG_SLEW_RATE: + val = pctl_readl(pctl, PADS_SLEW_RATE_REG(pin)); + arg = !!(val & PADS_SLEW_RATE_BIT(pin)); + break; + case PIN_CONFIG_DRIVE_STRENGTH: + val = pctl_readl(pctl, PADS_DRIVE_STRENGTH_REG(pin)) >> + PADS_DRIVE_STRENGTH_SHIFT(pin); + switch (val & PADS_DRIVE_STRENGTH_MASK) { + case PADS_DRIVE_STRENGTH_2MA: + arg = 2; + break; + case PADS_DRIVE_STRENGTH_4MA: + arg = 4; + break; + case PADS_DRIVE_STRENGTH_8MA: + arg = 8; + break; + case PADS_DRIVE_STRENGTH_12MA: + default: + arg = 12; + break; + } + break; + default: + dev_dbg(pctl->dev, "Property %u not supported\n", param); + return -ENOTSUPP; + } + + *config = pinconf_to_config_packed(param, arg); + + return 0; +} + +static int pistachio_pinconf_set(struct pinctrl_dev *pctldev, unsigned pin, + unsigned long *configs, unsigned num_configs) +{ + struct pistachio_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); + enum pin_config_param param; + u32 drv, val, arg; + unsigned int i; + + for (i = 0; i < num_configs; i++) { + param = pinconf_to_config_param(configs[i]); + arg = pinconf_to_config_argument(configs[i]); + + switch (param) { + case PIN_CONFIG_INPUT_SCHMITT_ENABLE: + val = pctl_readl(pctl, PADS_SCHMITT_EN_REG(pin)); + if (arg) + val |= PADS_SCHMITT_EN_BIT(pin); + else + val &= ~PADS_SCHMITT_EN_BIT(pin); + pctl_writel(pctl, val, PADS_SCHMITT_EN_REG(pin)); + break; + case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: + val = pctl_readl(pctl, PADS_PU_PD_REG(pin)); + val &= ~(PADS_PU_PD_MASK << PADS_PU_PD_SHIFT(pin)); + val |= PADS_PU_PD_HIGHZ << PADS_PU_PD_SHIFT(pin); + pctl_writel(pctl, val, PADS_PU_PD_REG(pin)); + break; + case PIN_CONFIG_BIAS_PULL_UP: + val = pctl_readl(pctl, PADS_PU_PD_REG(pin)); + val &= ~(PADS_PU_PD_MASK << PADS_PU_PD_SHIFT(pin)); + val |= PADS_PU_PD_UP << PADS_PU_PD_SHIFT(pin); + pctl_writel(pctl, val, PADS_PU_PD_REG(pin)); + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + val = pctl_readl(pctl, PADS_PU_PD_REG(pin)); + val &= ~(PADS_PU_PD_MASK << PADS_PU_PD_SHIFT(pin)); + val |= PADS_PU_PD_DOWN << PADS_PU_PD_SHIFT(pin); + pctl_writel(pctl, val, PADS_PU_PD_REG(pin)); + break; + case PIN_CONFIG_BIAS_BUS_HOLD: + val = pctl_readl(pctl, PADS_PU_PD_REG(pin)); + val &= ~(PADS_PU_PD_MASK << PADS_PU_PD_SHIFT(pin)); + val |= PADS_PU_PD_BUS << PADS_PU_PD_SHIFT(pin); + pctl_writel(pctl, val, PADS_PU_PD_REG(pin)); + break; + case PIN_CONFIG_SLEW_RATE: + val = pctl_readl(pctl, PADS_SLEW_RATE_REG(pin)); + if (arg) + val |= PADS_SLEW_RATE_BIT(pin); + else + val &= ~PADS_SLEW_RATE_BIT(pin); + pctl_writel(pctl, val, PADS_SLEW_RATE_REG(pin)); + break; + case PIN_CONFIG_DRIVE_STRENGTH: + val = pctl_readl(pctl, PADS_DRIVE_STRENGTH_REG(pin)); + val &= ~(PADS_DRIVE_STRENGTH_MASK << + PADS_DRIVE_STRENGTH_SHIFT(pin)); + switch (arg) { + case 2: + drv = PADS_DRIVE_STRENGTH_2MA; + break; + case 4: + drv = PADS_DRIVE_STRENGTH_4MA; + break; + case 8: + drv = PADS_DRIVE_STRENGTH_8MA; + break; + case 12: + drv = PADS_DRIVE_STRENGTH_12MA; + break; + default: + dev_err(pctl->dev, + "Drive strength %umA not supported\n", + arg); + return -EINVAL; + } + val |= drv << PADS_DRIVE_STRENGTH_SHIFT(pin); + pctl_writel(pctl, val, PADS_DRIVE_STRENGTH_REG(pin)); + break; + default: + dev_err(pctl->dev, "Property %u not supported\n", + param); + return -ENOTSUPP; + } + } + + return 0; +} + +static const struct pinconf_ops pistachio_pinconf_ops = { + .pin_config_get = pistachio_pinconf_get, + .pin_config_set = pistachio_pinconf_set, + .is_generic = true, +}; + +static struct pinctrl_desc pistachio_pinctrl_desc = { + .name = "pistachio-pinctrl", + .pctlops = &pistachio_pinctrl_ops, + .pmxops = &pistachio_pinmux_ops, + .confops = &pistachio_pinconf_ops, +}; + +static int pistachio_gpio_request(struct gpio_chip *chip, unsigned offset) +{ + return pinctrl_request_gpio(chip->base + offset); +} + +static void pistachio_gpio_free(struct gpio_chip *chip, unsigned offset) +{ + pinctrl_free_gpio(chip->base + offset); +} + +static int pistachio_gpio_get_direction(struct gpio_chip *chip, unsigned offset) +{ + struct pistachio_gpio_bank *bank = gc_to_bank(chip); + + return !(gpio_readl(bank, GPIO_OUTPUT_EN) & BIT(offset)); +} + +static int pistachio_gpio_get(struct gpio_chip *chip, unsigned offset) +{ + struct pistachio_gpio_bank *bank = gc_to_bank(chip); + u32 reg; + + if (gpio_readl(bank, GPIO_OUTPUT_EN) & BIT(offset)) + reg = GPIO_OUTPUT; + else + reg = GPIO_INPUT; + + return !!(gpio_readl(bank, reg) & BIT(offset)); +} + +static void pistachio_gpio_set(struct gpio_chip *chip, unsigned offset, + int value) +{ + struct pistachio_gpio_bank *bank = gc_to_bank(chip); + + gpio_mask_writel(bank, GPIO_OUTPUT, offset, !!value); +} + +static int pistachio_gpio_direction_input(struct gpio_chip *chip, + unsigned offset) +{ + struct pistachio_gpio_bank *bank = gc_to_bank(chip); + + gpio_mask_writel(bank, GPIO_OUTPUT_EN, offset, 0); + gpio_enable(bank, offset); + + return 0; +} + +static int pistachio_gpio_direction_output(struct gpio_chip *chip, + unsigned offset, int value) +{ + struct pistachio_gpio_bank *bank = gc_to_bank(chip); + + pistachio_gpio_set(chip, offset, value); + gpio_mask_writel(bank, GPIO_OUTPUT_EN, offset, 1); + gpio_enable(bank, offset); + + return 0; +} + +static void pistachio_gpio_irq_ack(struct irq_data *data) +{ + struct pistachio_gpio_bank *bank = irqd_to_bank(data); + + gpio_mask_writel(bank, GPIO_INTERRUPT_STATUS, data->hwirq, 0); +} + +static void pistachio_gpio_irq_mask(struct irq_data *data) +{ + struct pistachio_gpio_bank *bank = irqd_to_bank(data); + + gpio_mask_writel(bank, GPIO_INTERRUPT_EN, data->hwirq, 0); +} + +static void pistachio_gpio_irq_unmask(struct irq_data *data) +{ + struct pistachio_gpio_bank *bank = irqd_to_bank(data); + + gpio_mask_writel(bank, GPIO_INTERRUPT_EN, data->hwirq, 1); +} + +static unsigned int pistachio_gpio_irq_startup(struct irq_data *data) +{ + struct gpio_chip *chip = irq_data_get_irq_chip_data(data); + + pistachio_gpio_direction_input(chip, data->hwirq); + pistachio_gpio_irq_unmask(data); + + return 0; +} + +static int pistachio_gpio_irq_set_type(struct irq_data *data, unsigned int type) +{ + struct pistachio_gpio_bank *bank = irqd_to_bank(data); + + switch (type & IRQ_TYPE_SENSE_MASK) { + case IRQ_TYPE_EDGE_RISING: + gpio_mask_writel(bank, GPIO_INPUT_POLARITY, data->hwirq, 1); + gpio_mask_writel(bank, GPIO_INTERRUPT_TYPE, data->hwirq, + GPIO_INTERRUPT_TYPE_EDGE); + gpio_mask_writel(bank, GPIO_INTERRUPT_EDGE, data->hwirq, + GPIO_INTERRUPT_EDGE_SINGLE); + break; + case IRQ_TYPE_EDGE_FALLING: + gpio_mask_writel(bank, GPIO_INPUT_POLARITY, data->hwirq, 0); + gpio_mask_writel(bank, GPIO_INTERRUPT_TYPE, data->hwirq, + GPIO_INTERRUPT_TYPE_EDGE); + gpio_mask_writel(bank, GPIO_INTERRUPT_EDGE, data->hwirq, + GPIO_INTERRUPT_EDGE_SINGLE); + break; + case IRQ_TYPE_EDGE_BOTH: + gpio_mask_writel(bank, GPIO_INTERRUPT_TYPE, data->hwirq, + GPIO_INTERRUPT_TYPE_EDGE); + gpio_mask_writel(bank, GPIO_INTERRUPT_EDGE, data->hwirq, + GPIO_INTERRUPT_EDGE_DUAL); + break; + case IRQ_TYPE_LEVEL_HIGH: + gpio_mask_writel(bank, GPIO_INPUT_POLARITY, data->hwirq, 1); + gpio_mask_writel(bank, GPIO_INTERRUPT_TYPE, data->hwirq, + GPIO_INTERRUPT_TYPE_LEVEL); + break; + case IRQ_TYPE_LEVEL_LOW: + gpio_mask_writel(bank, GPIO_INPUT_POLARITY, data->hwirq, 0); + gpio_mask_writel(bank, GPIO_INTERRUPT_TYPE, data->hwirq, + GPIO_INTERRUPT_TYPE_LEVEL); + break; + default: + return -EINVAL; + } + + if (type & IRQ_TYPE_LEVEL_MASK) + __irq_set_handler_locked(data->irq, handle_level_irq); + else + __irq_set_handler_locked(data->irq, handle_edge_irq); + + return 0; +} + +static void pistachio_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) +{ + struct gpio_chip *gc = irq_get_handler_data(irq); + struct pistachio_gpio_bank *bank = gc_to_bank(gc); + struct irq_chip *chip = irq_get_chip(irq); + unsigned long pending; + unsigned int pin; + + chained_irq_enter(chip, desc); + pending = gpio_readl(bank, GPIO_INTERRUPT_STATUS) & + gpio_readl(bank, GPIO_INTERRUPT_EN); + for_each_set_bit(pin, &pending, 16) + generic_handle_irq(irq_linear_revmap(gc->irqdomain, pin)); + chained_irq_exit(chip, desc); +} + +#define GPIO_BANK(_bank, _pin_base, _npins) \ + { \ + .pin_base = _pin_base, \ + .npins = _npins, \ + .gpio_chip = { \ + .label = "GPIO" #_bank, \ + .request = pistachio_gpio_request, \ + .free = pistachio_gpio_free, \ + .get_direction = pistachio_gpio_get_direction, \ + .direction_input = pistachio_gpio_direction_input, \ + .direction_output = pistachio_gpio_direction_output, \ + .get = pistachio_gpio_get, \ + .set = pistachio_gpio_set, \ + .base = _pin_base, \ + .ngpio = _npins, \ + }, \ + .irq_chip = { \ + .name = "GPIO" #_bank, \ + .irq_startup = pistachio_gpio_irq_startup, \ + .irq_ack = pistachio_gpio_irq_ack, \ + .irq_mask = pistachio_gpio_irq_mask, \ + .irq_unmask = pistachio_gpio_irq_unmask, \ + .irq_set_type = pistachio_gpio_irq_set_type, \ + }, \ + } + +static struct pistachio_gpio_bank pistachio_gpio_banks[] = { + GPIO_BANK(0, PISTACHIO_PIN_MFIO(0), 16), + GPIO_BANK(1, PISTACHIO_PIN_MFIO(16), 16), + GPIO_BANK(2, PISTACHIO_PIN_MFIO(32), 16), + GPIO_BANK(3, PISTACHIO_PIN_MFIO(48), 16), + GPIO_BANK(4, PISTACHIO_PIN_MFIO(64), 16), + GPIO_BANK(5, PISTACHIO_PIN_MFIO(80), 10), +}; + +static int pistachio_gpio_register(struct pistachio_pinctrl *pctl) +{ + struct device_node *node = pctl->dev->of_node; + struct pistachio_gpio_bank *bank; + unsigned int i; + int irq, ret = 0; + + for (i = 0; i < pctl->nbanks; i++) { + char child_name[sizeof("gpioXX")]; + struct device_node *child; + + snprintf(child_name, sizeof(child_name), "gpio%d", i); + child = of_get_child_by_name(node, child_name); + if (!child) { + dev_err(pctl->dev, "No node for bank %u\n", i); + ret = -ENODEV; + goto err; + } + + if (!of_find_property(child, "gpio-controller", NULL)) { + dev_err(pctl->dev, + "No gpio-controller property for bank %u\n", i); + ret = -ENODEV; + goto err; + } + + irq = irq_of_parse_and_map(child, 0); + if (irq < 0) { + dev_err(pctl->dev, "No IRQ for bank %u: %d\n", i, irq); + ret = irq; + goto err; + } + + bank = &pctl->gpio_banks[i]; + bank->pctl = pctl; + bank->base = pctl->base + GPIO_BANK_BASE(i); + + bank->gpio_chip.dev = pctl->dev; + bank->gpio_chip.of_node = child; + ret = gpiochip_add(&bank->gpio_chip); + if (ret < 0) { + dev_err(pctl->dev, "Failed to add GPIO chip %u: %d\n", + i, ret); + goto err; + } + + ret = gpiochip_irqchip_add(&bank->gpio_chip, &bank->irq_chip, + 0, handle_level_irq, IRQ_TYPE_NONE); + if (ret < 0) { + dev_err(pctl->dev, "Failed to add IRQ chip %u: %d\n", + i, ret); + gpiochip_remove(&bank->gpio_chip); + goto err; + } + gpiochip_set_chained_irqchip(&bank->gpio_chip, &bank->irq_chip, + irq, pistachio_gpio_irq_handler); + + ret = gpiochip_add_pin_range(&bank->gpio_chip, + dev_name(pctl->dev), 0, + bank->pin_base, bank->npins); + if (ret < 0) { + dev_err(pctl->dev, "Failed to add GPIO range %u: %d\n", + i, ret); + gpiochip_remove(&bank->gpio_chip); + goto err; + } + } + + return 0; +err: + for (; i > 0; i--) { + bank = &pctl->gpio_banks[i - 1]; + gpiochip_remove(&bank->gpio_chip); + } + return ret; +} + +static const struct of_device_id pistachio_pinctrl_of_match[] = { + { .compatible = "img,pistachio-system-pinctrl", }, + { }, +}; + +static int pistachio_pinctrl_probe(struct platform_device *pdev) +{ + struct pistachio_pinctrl *pctl; + struct resource *res; + int ret; + + pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL); + if (!pctl) + return -ENOMEM; + pctl->dev = &pdev->dev; + dev_set_drvdata(&pdev->dev, pctl); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + pctl->base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(pctl->base)) + return PTR_ERR(pctl->base); + + pctl->pins = pistachio_pins; + pctl->npins = ARRAY_SIZE(pistachio_pins); + pctl->functions = pistachio_functions; + pctl->nfunctions = ARRAY_SIZE(pistachio_functions); + pctl->groups = pistachio_groups; + pctl->ngroups = ARRAY_SIZE(pistachio_groups); + pctl->gpio_banks = pistachio_gpio_banks; + pctl->nbanks = ARRAY_SIZE(pistachio_gpio_banks); + + pistachio_pinctrl_desc.pins = pctl->pins; + pistachio_pinctrl_desc.npins = pctl->npins; + + pctl->pctldev = pinctrl_register(&pistachio_pinctrl_desc, &pdev->dev, + pctl); + if (!pctl->pctldev) { + dev_err(&pdev->dev, "Failed to register pinctrl device\n"); + return -EINVAL; + } + + ret = pistachio_gpio_register(pctl); + if (ret < 0) { + pinctrl_unregister(pctl->pctldev); + return ret; + } + + return 0; +} + +static struct platform_driver pistachio_pinctrl_driver = { + .driver = { + .name = "pistachio-pinctrl", + .of_match_table = pistachio_pinctrl_of_match, + .suppress_bind_attrs = true, + }, + .probe = pistachio_pinctrl_probe, +}; + +static int __init pistachio_pinctrl_register(void) +{ + return platform_driver_register(&pistachio_pinctrl_driver); +} +arch_initcall(pistachio_pinctrl_register); -- cgit v0.10.2 From 6dce6d24956c57e5e6aeeaab87849d1856cc1620 Mon Sep 17 00:00:00 2001 From: Ray Jui Date: Wed, 13 May 2015 17:06:22 -0700 Subject: pinctrl: cygnus: fixed typo in the gpio driver Fixed a small typo in the Cygnus GPIO driver Signed-off-by: Jason Uy Signed-off-by: Ray Jui Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/bcm/pinctrl-cygnus-gpio.c b/drivers/pinctrl/bcm/pinctrl-cygnus-gpio.c index 4ad5c1a..bde45ba 100644 --- a/drivers/pinctrl/bcm/pinctrl-cygnus-gpio.c +++ b/drivers/pinctrl/bcm/pinctrl-cygnus-gpio.c @@ -38,7 +38,7 @@ #define CYGNUS_GPIO_DATA_IN_OFFSET 0x00 #define CYGNUS_GPIO_DATA_OUT_OFFSET 0x04 #define CYGNUS_GPIO_OUT_EN_OFFSET 0x08 -#define CYGNUS_GPIO_IN_TYPE_OFFSET 0x0c +#define CYGNUS_GPIO_INT_TYPE_OFFSET 0x0c #define CYGNUS_GPIO_INT_DE_OFFSET 0x10 #define CYGNUS_GPIO_INT_EDGE_OFFSET 0x14 #define CYGNUS_GPIO_INT_MSK_OFFSET 0x18 @@ -264,7 +264,7 @@ static int cygnus_gpio_irq_set_type(struct irq_data *d, unsigned int type) } spin_lock_irqsave(&chip->lock, flags); - cygnus_set_bit(chip, CYGNUS_GPIO_IN_TYPE_OFFSET, gpio, + cygnus_set_bit(chip, CYGNUS_GPIO_INT_TYPE_OFFSET, gpio, level_triggered); cygnus_set_bit(chip, CYGNUS_GPIO_INT_DE_OFFSET, gpio, dual_edge); cygnus_set_bit(chip, CYGNUS_GPIO_INT_EDGE_OFFSET, gpio, -- cgit v0.10.2 From 16a4851d8c0c508f0e75a2b4b5e9195524dae600 Mon Sep 17 00:00:00 2001 From: Joachim Eastwood Date: Thu, 14 May 2015 14:45:58 +0200 Subject: pinctrl: lpc18xx: add the missing group function map Add the required group function map and fill it at probe using the pin capabilities information already present in the driver. Signed-off-by: Joachim Eastwood Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/pinctrl-lpc18xx.c b/drivers/pinctrl/pinctrl-lpc18xx.c index 0facb7e..a8bc1ad 100644 --- a/drivers/pinctrl/pinctrl-lpc18xx.c +++ b/drivers/pinctrl/pinctrl-lpc18xx.c @@ -46,12 +46,6 @@ #define LPC18XX_SCU_FUNC_PER_PIN 8 -struct lpc18xx_scu_data { - struct pinctrl_dev *pctl; - void __iomem *base; - struct clk *clk; -}; - /* LPC18xx pin types */ enum { TYPE_ND, /* Normal-drive */ @@ -113,10 +107,11 @@ enum { FUNC_UART3, FUNC_USB0, FUNC_USB1, + FUNC_MAX }; static const char *const lpc18xx_function_names[] = { - [FUNC_R] = "", + [FUNC_R] = "reserved", [FUNC_ADC] = "adc", [FUNC_ADCTRIG] = "adctrig", [FUNC_CAN0] = "can0", @@ -168,6 +163,18 @@ static const char *const lpc18xx_function_names[] = { [FUNC_USB1] = "usb1", }; +struct lpc18xx_pmx_func { + const char **groups; + unsigned ngroups; +}; + +struct lpc18xx_scu_data { + struct pinctrl_dev *pctl; + void __iomem *base; + struct clk *clk; + struct lpc18xx_pmx_func func[FUNC_MAX]; +}; + struct lpc18xx_pin_caps { unsigned int offset; unsigned char functions[LPC18XX_SCU_FUNC_PER_PIN]; @@ -962,6 +969,11 @@ static int lpc18xx_pmx_get_func_groups(struct pinctrl_dev *pctldev, const char *const **groups, unsigned *const num_groups) { + struct lpc18xx_scu_data *scu = pinctrl_dev_get_drvdata(pctldev); + + *groups = scu->func[function].groups; + *num_groups = scu->func[function].ngroups; + return 0; } @@ -1081,6 +1093,57 @@ static struct pinctrl_desc lpc18xx_scu_desc = { .owner = THIS_MODULE, }; +static bool lpc18xx_valid_pin_function(unsigned pin, unsigned function) +{ + struct lpc18xx_pin_caps *p = lpc18xx_pins[pin].drv_data; + int i; + + if (function == FUNC_DAC && p->analog == DAC) + return true; + + if (function == FUNC_ADC && p->analog) + return true; + + if (function == FUNC_I2C0 && p->type == TYPE_I2C0) + return true; + + if (function == FUNC_USB1 && p->type == TYPE_USB1) + return true; + + for (i = 0; i < LPC18XX_SCU_FUNC_PER_PIN; i++) { + if (function == p->functions[i]) + return true; + } + + return false; +} + +static int lpc18xx_create_group_func_map(struct device *dev, + struct lpc18xx_scu_data *scu) +{ + u16 pins[ARRAY_SIZE(lpc18xx_pins)]; + int func, ngroups, i; + + for (func = 0; func < FUNC_MAX; ngroups = 0, func++) { + + for (i = 0; i < ARRAY_SIZE(lpc18xx_pins); i++) { + if (lpc18xx_valid_pin_function(i, func)) + pins[ngroups++] = i; + } + + scu->func[func].ngroups = ngroups; + scu->func[func].groups = devm_kzalloc(dev, ngroups * + sizeof(char *), GFP_KERNEL); + if (!scu->func[func].groups) + return -ENOMEM; + + for (i = 0; i < ngroups; i++) + scu->func[func].groups[i] = lpc18xx_pins[pins[i]].name; + } + + return 0; +} + static int lpc18xx_scu_probe(struct platform_device *pdev) { struct lpc18xx_scu_data *scu; @@ -1102,6 +1165,12 @@ static int lpc18xx_scu_probe(struct platform_device *pdev) return PTR_ERR(scu->clk); } + ret = lpc18xx_create_group_func_map(&pdev->dev, scu); + if (ret) { + dev_err(&pdev->dev, "Unable to create group func map.\n"); + return ret; + } + ret = clk_prepare_enable(scu->clk); if (ret) { dev_err(&pdev->dev, "Unable to enable clock.\n"); -- cgit v0.10.2 From 8a88375c3866901753adc4f957f25540cbe11521 Mon Sep 17 00:00:00 2001 From: Hongzhou Yang Date: Mon, 18 May 2015 23:11:12 -0700 Subject: pinctrl: mediatek: Modify pinctrl bindings for mt6397. Since 6397 is no need to support interrupt controller, moving interrupt controller relate property to optional list. Also adding mt8173 and mt8127 to bindings. Signed-off-by: Hongzhou Yang Signed-off-by: Linus Walleij diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt index 5868a0f..0480bc3 100644 --- a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt @@ -3,9 +3,11 @@ The Mediatek's Pin controller is used to control SoC pins. Required properties: -- compatible: value should be either of the following. +- compatible: value should be one of the following. (a) "mediatek,mt8135-pinctrl", compatible with mt8135 pinctrl. -- mediatek,pctl-regmap: Should be a phandle of the syscfg node. + (b) "mediatek,mt8173-pinctrl", compatible with mt8173 pinctrl. + (c) "mediatek,mt6397-pinctrl", compatible with mt6397 pinctrl. + (d) "mediatek,mt8127-pinctrl", compatible with mt8127 pinctrl. - pins-are-numbered: Specify the subnodes are using numbered pinmux to specify pins. - gpio-controller : Marks the device node as a gpio controller. @@ -24,6 +26,9 @@ Required properties: Only the following flags are supported: 0 - GPIO_ACTIVE_HIGH 1 - GPIO_ACTIVE_LOW + +Optional properties: +- mediatek,pctl-regmap: Should be a phandle of the syscfg node. - reg: physicall address base for EINT registers - interrupt-controller: Marks the device node as an interrupt controller - #interrupt-cells: Should be two. -- cgit v0.10.2 From 0dcdbd2b66704509a1e20b1545c936d8d4390aa7 Mon Sep 17 00:00:00 2001 From: Hongzhou Yang Date: Mon, 18 May 2015 20:01:27 -0700 Subject: pinctrl: mt6397: Add pinfunc header file for mt6397. Add pinfunc header file, mt8135/mt8173 relate dts will include it. Signed-off-by: Hongzhou Yang Signed-off-by: Linus Walleij diff --git a/include/dt-bindings/pinctrl/mt6397-pinfunc.h b/include/dt-bindings/pinctrl/mt6397-pinfunc.h new file mode 100644 index 0000000..85739b3 --- /dev/null +++ b/include/dt-bindings/pinctrl/mt6397-pinfunc.h @@ -0,0 +1,256 @@ +#ifndef __DTS_MT6397_PINFUNC_H +#define __DTS_MT6397_PINFUNC_H + +#include + +#define MT6397_PIN_0_INT__FUNC_GPIO0 (MTK_PIN_NO(0) | 0) +#define MT6397_PIN_0_INT__FUNC_INT (MTK_PIN_NO(0) | 1) + +#define MT6397_PIN_1_SRCVOLTEN__FUNC_GPIO1 (MTK_PIN_NO(1) | 0) +#define MT6397_PIN_1_SRCVOLTEN__FUNC_SRCVOLTEN (MTK_PIN_NO(1) | 1) +#define MT6397_PIN_1_SRCVOLTEN__FUNC_TEST_CK1 (MTK_PIN_NO(1) | 6) + +#define MT6397_PIN_2_SRCLKEN_PERI__FUNC_GPIO2 (MTK_PIN_NO(2) | 0) +#define MT6397_PIN_2_SRCLKEN_PERI__FUNC_SRCLKEN_PERI (MTK_PIN_NO(2) | 1) +#define MT6397_PIN_2_SRCLKEN_PERI__FUNC_TEST_CK2 (MTK_PIN_NO(2) | 6) + +#define MT6397_PIN_3_RTC_32K1V8__FUNC_GPIO3 (MTK_PIN_NO(3) | 0) +#define MT6397_PIN_3_RTC_32K1V8__FUNC_RTC_32K1V8 (MTK_PIN_NO(3) | 1) +#define MT6397_PIN_3_RTC_32K1V8__FUNC_TEST_CK3 (MTK_PIN_NO(3) | 6) + +#define MT6397_PIN_4_WRAP_EVENT__FUNC_GPIO4 (MTK_PIN_NO(4) | 0) +#define MT6397_PIN_4_WRAP_EVENT__FUNC_WRAP_EVENT (MTK_PIN_NO(4) | 1) + +#define MT6397_PIN_5_SPI_CLK__FUNC_GPIO5 (MTK_PIN_NO(5) | 0) +#define MT6397_PIN_5_SPI_CLK__FUNC_SPI_CLK (MTK_PIN_NO(5) | 1) + +#define MT6397_PIN_6_SPI_CSN__FUNC_GPIO6 (MTK_PIN_NO(6) | 0) +#define MT6397_PIN_6_SPI_CSN__FUNC_SPI_CSN (MTK_PIN_NO(6) | 1) + +#define MT6397_PIN_7_SPI_MOSI__FUNC_GPIO7 (MTK_PIN_NO(7) | 0) +#define MT6397_PIN_7_SPI_MOSI__FUNC_SPI_MOSI (MTK_PIN_NO(7) | 1) + +#define MT6397_PIN_8_SPI_MISO__FUNC_GPIO8 (MTK_PIN_NO(8) | 0) +#define MT6397_PIN_8_SPI_MISO__FUNC_SPI_MISO (MTK_PIN_NO(8) | 1) + +#define MT6397_PIN_9_AUD_CLK_MOSI__FUNC_GPIO9 (MTK_PIN_NO(9) | 0) +#define MT6397_PIN_9_AUD_CLK_MOSI__FUNC_AUD_CLK (MTK_PIN_NO(9) | 1) +#define MT6397_PIN_9_AUD_CLK_MOSI__FUNC_TEST_IN0 (MTK_PIN_NO(9) | 6) +#define MT6397_PIN_9_AUD_CLK_MOSI__FUNC_TEST_OUT0 (MTK_PIN_NO(9) | 7) + +#define MT6397_PIN_10_AUD_DAT_MISO__FUNC_GPIO10 (MTK_PIN_NO(10) | 0) +#define MT6397_PIN_10_AUD_DAT_MISO__FUNC_AUD_MISO (MTK_PIN_NO(10) | 1) +#define MT6397_PIN_10_AUD_DAT_MISO__FUNC_TEST_IN1 (MTK_PIN_NO(10) | 6) +#define MT6397_PIN_10_AUD_DAT_MISO__FUNC_TEST_OUT1 (MTK_PIN_NO(10) | 7) + +#define MT6397_PIN_11_AUD_DAT_MOSI__FUNC_GPIO11 (MTK_PIN_NO(11) | 0) +#define MT6397_PIN_11_AUD_DAT_MOSI__FUNC_AUD_MOSI (MTK_PIN_NO(11) | 1) +#define MT6397_PIN_11_AUD_DAT_MOSI__FUNC_TEST_IN2 (MTK_PIN_NO(11) | 6) +#define MT6397_PIN_11_AUD_DAT_MOSI__FUNC_TEST_OUT2 (MTK_PIN_NO(11) | 7) + +#define MT6397_PIN_12_COL0__FUNC_GPIO12 (MTK_PIN_NO(12) | 0) +#define MT6397_PIN_12_COL0__FUNC_COL0_USBDL (MTK_PIN_NO(12) | 1) +#define MT6397_PIN_12_COL0__FUNC_EINT10_1X (MTK_PIN_NO(12) | 2) +#define MT6397_PIN_12_COL0__FUNC_PWM1_3X (MTK_PIN_NO(12) | 3) +#define MT6397_PIN_12_COL0__FUNC_TEST_IN3 (MTK_PIN_NO(12) | 6) +#define MT6397_PIN_12_COL0__FUNC_TEST_OUT3 (MTK_PIN_NO(12) | 7) + +#define MT6397_PIN_13_COL1__FUNC_GPIO13 (MTK_PIN_NO(13) | 0) +#define MT6397_PIN_13_COL1__FUNC_COL1 (MTK_PIN_NO(13) | 1) +#define MT6397_PIN_13_COL1__FUNC_EINT11_1X (MTK_PIN_NO(13) | 2) +#define MT6397_PIN_13_COL1__FUNC_SCL0_2X (MTK_PIN_NO(13) | 3) +#define MT6397_PIN_13_COL1__FUNC_TEST_IN4 (MTK_PIN_NO(13) | 6) +#define MT6397_PIN_13_COL1__FUNC_TEST_OUT4 (MTK_PIN_NO(13) | 7) + +#define MT6397_PIN_14_COL2__FUNC_GPIO14 (MTK_PIN_NO(14) | 0) +#define MT6397_PIN_14_COL2__FUNC_COL2 (MTK_PIN_NO(14) | 1) +#define MT6397_PIN_14_COL2__FUNC_EINT12_1X (MTK_PIN_NO(14) | 2) +#define MT6397_PIN_14_COL2__FUNC_SDA0_2X (MTK_PIN_NO(14) | 3) +#define MT6397_PIN_14_COL2__FUNC_TEST_IN5 (MTK_PIN_NO(14) | 6) +#define MT6397_PIN_14_COL2__FUNC_TEST_OUT5 (MTK_PIN_NO(14) | 7) + +#define MT6397_PIN_15_COL3__FUNC_GPIO15 (MTK_PIN_NO(15) | 0) +#define MT6397_PIN_15_COL3__FUNC_COL3 (MTK_PIN_NO(15) | 1) +#define MT6397_PIN_15_COL3__FUNC_EINT13_1X (MTK_PIN_NO(15) | 2) +#define MT6397_PIN_15_COL3__FUNC_SCL1_2X (MTK_PIN_NO(15) | 3) +#define MT6397_PIN_15_COL3__FUNC_TEST_IN6 (MTK_PIN_NO(15) | 6) +#define MT6397_PIN_15_COL3__FUNC_TEST_OUT6 (MTK_PIN_NO(15) | 7) + +#define MT6397_PIN_16_COL4__FUNC_GPIO16 (MTK_PIN_NO(16) | 0) +#define MT6397_PIN_16_COL4__FUNC_COL4 (MTK_PIN_NO(16) | 1) +#define MT6397_PIN_16_COL4__FUNC_EINT14_1X (MTK_PIN_NO(16) | 2) +#define MT6397_PIN_16_COL4__FUNC_SDA1_2X (MTK_PIN_NO(16) | 3) +#define MT6397_PIN_16_COL4__FUNC_TEST_IN7 (MTK_PIN_NO(16) | 6) +#define MT6397_PIN_16_COL4__FUNC_TEST_OUT7 (MTK_PIN_NO(16) | 7) + +#define MT6397_PIN_17_COL5__FUNC_GPIO17 (MTK_PIN_NO(17) | 0) +#define MT6397_PIN_17_COL5__FUNC_COL5 (MTK_PIN_NO(17) | 1) +#define MT6397_PIN_17_COL5__FUNC_EINT15_1X (MTK_PIN_NO(17) | 2) +#define MT6397_PIN_17_COL5__FUNC_SCL2_2X (MTK_PIN_NO(17) | 3) +#define MT6397_PIN_17_COL5__FUNC_TEST_IN8 (MTK_PIN_NO(17) | 6) +#define MT6397_PIN_17_COL5__FUNC_TEST_OUT8 (MTK_PIN_NO(17) | 7) + +#define MT6397_PIN_18_COL6__FUNC_GPIO18 (MTK_PIN_NO(18) | 0) +#define MT6397_PIN_18_COL6__FUNC_COL6 (MTK_PIN_NO(18) | 1) +#define MT6397_PIN_18_COL6__FUNC_EINT16_1X (MTK_PIN_NO(18) | 2) +#define MT6397_PIN_18_COL6__FUNC_SDA2_2X (MTK_PIN_NO(18) | 3) +#define MT6397_PIN_18_COL6__FUNC_GPIO32K_0 (MTK_PIN_NO(18) | 4) +#define MT6397_PIN_18_COL6__FUNC_GPIO26M_0 (MTK_PIN_NO(18) | 5) +#define MT6397_PIN_18_COL6__FUNC_TEST_IN9 (MTK_PIN_NO(18) | 6) +#define MT6397_PIN_18_COL6__FUNC_TEST_OUT9 (MTK_PIN_NO(18) | 7) + +#define MT6397_PIN_19_COL7__FUNC_GPIO19 (MTK_PIN_NO(19) | 0) +#define MT6397_PIN_19_COL7__FUNC_COL7 (MTK_PIN_NO(19) | 1) +#define MT6397_PIN_19_COL7__FUNC_EINT17_1X (MTK_PIN_NO(19) | 2) +#define MT6397_PIN_19_COL7__FUNC_PWM2_3X (MTK_PIN_NO(19) | 3) +#define MT6397_PIN_19_COL7__FUNC_GPIO32K_1 (MTK_PIN_NO(19) | 4) +#define MT6397_PIN_19_COL7__FUNC_GPIO26M_1 (MTK_PIN_NO(19) | 5) +#define MT6397_PIN_19_COL7__FUNC_TEST_IN10 (MTK_PIN_NO(19) | 6) +#define MT6397_PIN_19_COL7__FUNC_TEST_OUT10 (MTK_PIN_NO(19) | 7) + +#define MT6397_PIN_20_ROW0__FUNC_GPIO20 (MTK_PIN_NO(20) | 0) +#define MT6397_PIN_20_ROW0__FUNC_ROW0 (MTK_PIN_NO(20) | 1) +#define MT6397_PIN_20_ROW0__FUNC_EINT18_1X (MTK_PIN_NO(20) | 2) +#define MT6397_PIN_20_ROW0__FUNC_SCL0_3X (MTK_PIN_NO(20) | 3) +#define MT6397_PIN_20_ROW0__FUNC_TEST_IN11 (MTK_PIN_NO(20) | 6) +#define MT6397_PIN_20_ROW0__FUNC_TEST_OUT11 (MTK_PIN_NO(20) | 7) + +#define MT6397_PIN_21_ROW1__FUNC_GPIO21 (MTK_PIN_NO(21) | 0) +#define MT6397_PIN_21_ROW1__FUNC_ROW1 (MTK_PIN_NO(21) | 1) +#define MT6397_PIN_21_ROW1__FUNC_EINT19_1X (MTK_PIN_NO(21) | 2) +#define MT6397_PIN_21_ROW1__FUNC_SDA0_3X (MTK_PIN_NO(21) | 3) +#define MT6397_PIN_21_ROW1__FUNC_AUD_TSTCK (MTK_PIN_NO(21) | 4) +#define MT6397_PIN_21_ROW1__FUNC_TEST_IN12 (MTK_PIN_NO(21) | 6) +#define MT6397_PIN_21_ROW1__FUNC_TEST_OUT12 (MTK_PIN_NO(21) | 7) + +#define MT6397_PIN_22_ROW2__FUNC_GPIO22 (MTK_PIN_NO(22) | 0) +#define MT6397_PIN_22_ROW2__FUNC_ROW2 (MTK_PIN_NO(22) | 1) +#define MT6397_PIN_22_ROW2__FUNC_EINT20_1X (MTK_PIN_NO(22) | 2) +#define MT6397_PIN_22_ROW2__FUNC_SCL1_3X (MTK_PIN_NO(22) | 3) +#define MT6397_PIN_22_ROW2__FUNC_TEST_IN13 (MTK_PIN_NO(22) | 6) +#define MT6397_PIN_22_ROW2__FUNC_TEST_OUT13 (MTK_PIN_NO(22) | 7) + +#define MT6397_PIN_23_ROW3__FUNC_GPIO23 (MTK_PIN_NO(23) | 0) +#define MT6397_PIN_23_ROW3__FUNC_ROW3 (MTK_PIN_NO(23) | 1) +#define MT6397_PIN_23_ROW3__FUNC_EINT21_1X (MTK_PIN_NO(23) | 2) +#define MT6397_PIN_23_ROW3__FUNC_SDA1_3X (MTK_PIN_NO(23) | 3) +#define MT6397_PIN_23_ROW3__FUNC_TEST_IN14 (MTK_PIN_NO(23) | 6) +#define MT6397_PIN_23_ROW3__FUNC_TEST_OUT14 (MTK_PIN_NO(23) | 7) + +#define MT6397_PIN_24_ROW4__FUNC_GPIO24 (MTK_PIN_NO(24) | 0) +#define MT6397_PIN_24_ROW4__FUNC_ROW4 (MTK_PIN_NO(24) | 1) +#define MT6397_PIN_24_ROW4__FUNC_EINT22_1X (MTK_PIN_NO(24) | 2) +#define MT6397_PIN_24_ROW4__FUNC_SCL2_3X (MTK_PIN_NO(24) | 3) +#define MT6397_PIN_24_ROW4__FUNC_TEST_IN15 (MTK_PIN_NO(24) | 6) +#define MT6397_PIN_24_ROW4__FUNC_TEST_OUT15 (MTK_PIN_NO(24) | 7) + +#define MT6397_PIN_25_ROW5__FUNC_GPIO25 (MTK_PIN_NO(25) | 0) +#define MT6397_PIN_25_ROW5__FUNC_ROW5 (MTK_PIN_NO(25) | 1) +#define MT6397_PIN_25_ROW5__FUNC_EINT23_1X (MTK_PIN_NO(25) | 2) +#define MT6397_PIN_25_ROW5__FUNC_SDA2_3X (MTK_PIN_NO(25) | 3) +#define MT6397_PIN_25_ROW5__FUNC_TEST_IN16 (MTK_PIN_NO(25) | 6) +#define MT6397_PIN_25_ROW5__FUNC_TEST_OUT16 (MTK_PIN_NO(25) | 7) + +#define MT6397_PIN_26_ROW6__FUNC_GPIO26 (MTK_PIN_NO(26) | 0) +#define MT6397_PIN_26_ROW6__FUNC_ROW6 (MTK_PIN_NO(26) | 1) +#define MT6397_PIN_26_ROW6__FUNC_EINT24_1X (MTK_PIN_NO(26) | 2) +#define MT6397_PIN_26_ROW6__FUNC_PWM3_3X (MTK_PIN_NO(26) | 3) +#define MT6397_PIN_26_ROW6__FUNC_GPIO32K_2 (MTK_PIN_NO(26) | 4) +#define MT6397_PIN_26_ROW6__FUNC_GPIO26M_2 (MTK_PIN_NO(26) | 5) +#define MT6397_PIN_26_ROW6__FUNC_TEST_IN17 (MTK_PIN_NO(26) | 6) +#define MT6397_PIN_26_ROW6__FUNC_TEST_OUT17 (MTK_PIN_NO(26) | 7) + +#define MT6397_PIN_27_ROW7__FUNC_GPIO27 (MTK_PIN_NO(27) | 0) +#define MT6397_PIN_27_ROW7__FUNC_ROW7 (MTK_PIN_NO(27) | 1) +#define MT6397_PIN_27_ROW7__FUNC_EINT3_1X (MTK_PIN_NO(27) | 2) +#define MT6397_PIN_27_ROW7__FUNC_CBUS (MTK_PIN_NO(27) | 3) +#define MT6397_PIN_27_ROW7__FUNC_GPIO32K_3 (MTK_PIN_NO(27) | 4) +#define MT6397_PIN_27_ROW7__FUNC_GPIO26M_3 (MTK_PIN_NO(27) | 5) +#define MT6397_PIN_27_ROW7__FUNC_TEST_IN18 (MTK_PIN_NO(27) | 6) +#define MT6397_PIN_27_ROW7__FUNC_TEST_OUT18 (MTK_PIN_NO(27) | 7) + +#define MT6397_PIN_28_PWM1__FUNC_GPIO28 (MTK_PIN_NO(28) | 0) +#define MT6397_PIN_28_PWM1__FUNC_PWM1 (MTK_PIN_NO(28) | 1) +#define MT6397_PIN_28_PWM1__FUNC_EINT4_1X (MTK_PIN_NO(28) | 2) +#define MT6397_PIN_28_PWM1__FUNC_GPIO32K_4 (MTK_PIN_NO(28) | 4) +#define MT6397_PIN_28_PWM1__FUNC_GPIO26M_4 (MTK_PIN_NO(28) | 5) +#define MT6397_PIN_28_PWM1__FUNC_TEST_IN19 (MTK_PIN_NO(28) | 6) +#define MT6397_PIN_28_PWM1__FUNC_TEST_OUT19 (MTK_PIN_NO(28) | 7) + +#define MT6397_PIN_29_PWM2__FUNC_GPIO29 (MTK_PIN_NO(29) | 0) +#define MT6397_PIN_29_PWM2__FUNC_PWM2 (MTK_PIN_NO(29) | 1) +#define MT6397_PIN_29_PWM2__FUNC_EINT5_1X (MTK_PIN_NO(29) | 2) +#define MT6397_PIN_29_PWM2__FUNC_GPIO32K_5 (MTK_PIN_NO(29) | 4) +#define MT6397_PIN_29_PWM2__FUNC_GPIO26M_5 (MTK_PIN_NO(29) | 5) +#define MT6397_PIN_29_PWM2__FUNC_TEST_IN20 (MTK_PIN_NO(29) | 6) +#define MT6397_PIN_29_PWM2__FUNC_TEST_OUT20 (MTK_PIN_NO(29) | 7) + +#define MT6397_PIN_30_PWM3__FUNC_GPIO30 (MTK_PIN_NO(30) | 0) +#define MT6397_PIN_30_PWM3__FUNC_PWM3 (MTK_PIN_NO(30) | 1) +#define MT6397_PIN_30_PWM3__FUNC_EINT6_1X (MTK_PIN_NO(30) | 2) +#define MT6397_PIN_30_PWM3__FUNC_COL0 (MTK_PIN_NO(30) | 3) +#define MT6397_PIN_30_PWM3__FUNC_GPIO32K_6 (MTK_PIN_NO(30) | 4) +#define MT6397_PIN_30_PWM3__FUNC_GPIO26M_6 (MTK_PIN_NO(30) | 5) +#define MT6397_PIN_30_PWM3__FUNC_TEST_IN21 (MTK_PIN_NO(30) | 6) +#define MT6397_PIN_30_PWM3__FUNC_TEST_OUT21 (MTK_PIN_NO(30) | 7) + +#define MT6397_PIN_31_SCL0__FUNC_GPIO31 (MTK_PIN_NO(31) | 0) +#define MT6397_PIN_31_SCL0__FUNC_SCL0 (MTK_PIN_NO(31) | 1) +#define MT6397_PIN_31_SCL0__FUNC_EINT7_1X (MTK_PIN_NO(31) | 2) +#define MT6397_PIN_31_SCL0__FUNC_PWM1_2X (MTK_PIN_NO(31) | 3) +#define MT6397_PIN_31_SCL0__FUNC_TEST_IN22 (MTK_PIN_NO(31) | 6) +#define MT6397_PIN_31_SCL0__FUNC_TEST_OUT22 (MTK_PIN_NO(31) | 7) + +#define MT6397_PIN_32_SDA0__FUNC_GPIO32 (MTK_PIN_NO(32) | 0) +#define MT6397_PIN_32_SDA0__FUNC_SDA0 (MTK_PIN_NO(32) | 1) +#define MT6397_PIN_32_SDA0__FUNC_EINT8_1X (MTK_PIN_NO(32) | 2) +#define MT6397_PIN_32_SDA0__FUNC_TEST_IN23 (MTK_PIN_NO(32) | 6) +#define MT6397_PIN_32_SDA0__FUNC_TEST_OUT23 (MTK_PIN_NO(32) | 7) + +#define MT6397_PIN_33_SCL1__FUNC_GPIO33 (MTK_PIN_NO(33) | 0) +#define MT6397_PIN_33_SCL1__FUNC_SCL1 (MTK_PIN_NO(33) | 1) +#define MT6397_PIN_33_SCL1__FUNC_EINT9_1X (MTK_PIN_NO(33) | 2) +#define MT6397_PIN_33_SCL1__FUNC_PWM2_2X (MTK_PIN_NO(33) | 3) +#define MT6397_PIN_33_SCL1__FUNC_TEST_IN24 (MTK_PIN_NO(33) | 6) +#define MT6397_PIN_33_SCL1__FUNC_TEST_OUT24 (MTK_PIN_NO(33) | 7) + +#define MT6397_PIN_34_SDA1__FUNC_GPIO34 (MTK_PIN_NO(34) | 0) +#define MT6397_PIN_34_SDA1__FUNC_SDA1 (MTK_PIN_NO(34) | 1) +#define MT6397_PIN_34_SDA1__FUNC_EINT0_1X (MTK_PIN_NO(34) | 2) +#define MT6397_PIN_34_SDA1__FUNC_TEST_IN25 (MTK_PIN_NO(34) | 6) +#define MT6397_PIN_34_SDA1__FUNC_TEST_OUT25 (MTK_PIN_NO(34) | 7) + +#define MT6397_PIN_35_SCL2__FUNC_GPIO35 (MTK_PIN_NO(35) | 0) +#define MT6397_PIN_35_SCL2__FUNC_SCL2 (MTK_PIN_NO(35) | 1) +#define MT6397_PIN_35_SCL2__FUNC_EINT1_1X (MTK_PIN_NO(35) | 2) +#define MT6397_PIN_35_SCL2__FUNC_PWM3_2X (MTK_PIN_NO(35) | 3) +#define MT6397_PIN_35_SCL2__FUNC_TEST_IN26 (MTK_PIN_NO(35) | 6) +#define MT6397_PIN_35_SCL2__FUNC_TEST_OUT26 (MTK_PIN_NO(35) | 7) + +#define MT6397_PIN_36_SDA2__FUNC_GPIO36 (MTK_PIN_NO(36) | 0) +#define MT6397_PIN_36_SDA2__FUNC_SDA2 (MTK_PIN_NO(36) | 1) +#define MT6397_PIN_36_SDA2__FUNC_EINT2_1X (MTK_PIN_NO(36) | 2) +#define MT6397_PIN_36_SDA2__FUNC_TEST_IN27 (MTK_PIN_NO(36) | 6) +#define MT6397_PIN_36_SDA2__FUNC_TEST_OUT27 (MTK_PIN_NO(36) | 7) + +#define MT6397_PIN_37_HDMISD__FUNC_GPIO37 (MTK_PIN_NO(37) | 0) +#define MT6397_PIN_37_HDMISD__FUNC_HDMISD (MTK_PIN_NO(37) | 1) +#define MT6397_PIN_37_HDMISD__FUNC_TEST_IN28 (MTK_PIN_NO(37) | 6) +#define MT6397_PIN_37_HDMISD__FUNC_TEST_OUT28 (MTK_PIN_NO(37) | 7) + +#define MT6397_PIN_38_HDMISCK__FUNC_GPIO38 (MTK_PIN_NO(38) | 0) +#define MT6397_PIN_38_HDMISCK__FUNC_HDMISCK (MTK_PIN_NO(38) | 1) +#define MT6397_PIN_38_HDMISCK__FUNC_TEST_IN29 (MTK_PIN_NO(38) | 6) +#define MT6397_PIN_38_HDMISCK__FUNC_TEST_OUT29 (MTK_PIN_NO(38) | 7) + +#define MT6397_PIN_39_HTPLG__FUNC_GPIO39 (MTK_PIN_NO(39) | 0) +#define MT6397_PIN_39_HTPLG__FUNC_HTPLG (MTK_PIN_NO(39) | 1) +#define MT6397_PIN_39_HTPLG__FUNC_TEST_IN30 (MTK_PIN_NO(39) | 6) +#define MT6397_PIN_39_HTPLG__FUNC_TEST_OUT30 (MTK_PIN_NO(39) | 7) + +#define MT6397_PIN_40_CEC__FUNC_GPIO40 (MTK_PIN_NO(40) | 0) +#define MT6397_PIN_40_CEC__FUNC_CEC (MTK_PIN_NO(40) | 1) +#define MT6397_PIN_40_CEC__FUNC_TEST_IN31 (MTK_PIN_NO(40) | 6) +#define MT6397_PIN_40_CEC__FUNC_TEST_OUT31 (MTK_PIN_NO(40) | 7) + +#endif /* __DTS_MT6397_PINFUNC_H */ -- cgit v0.10.2 From 4b9b5268460cbc85270b309559b8f3f48295709a Mon Sep 17 00:00:00 2001 From: Yingjoe Chen Date: Mon, 18 May 2015 23:11:14 -0700 Subject: pinctrl: mediatek: data struct optimize and remove unused member struct mtk_desc_pin.chip, mtk_pinctrl_devdata.invser_offset and mtk_pinctrl_devdata.chip_type are never used in code. Remove them. Some per-pin data are using int for pin number and offsets. Change to short and rearrange to reduce const data size. Signed-off-by: Yingjoe Chen Signed-off-by: Hongzhou Yang Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8135.c b/drivers/pinctrl/mediatek/pinctrl-mt8135.c index f1e1e18..8e6abd5 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8135.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8135.c @@ -32,12 +32,12 @@ #define R1_BASE2 0x250 struct mtk_spec_pull_set { - unsigned int pin; - unsigned int pupd_offset; + unsigned char pin; unsigned char pupd_bit; - unsigned int r0_offset; + unsigned short pupd_offset; + unsigned short r0_offset; + unsigned short r1_offset; unsigned char r0_bit; - unsigned int r1_offset; unsigned char r1_bit; }; @@ -305,7 +305,6 @@ static const struct mtk_pinctrl_devdata mt8135_pinctrl_data = { .pullen_offset = 0x0200, .smt_offset = 0x0300, .pullsel_offset = 0x0400, - .invser_offset = 0x0600, .dout_offset = 0x0800, .din_offset = 0x0A00, .pinmux_offset = 0x0C00, @@ -314,7 +313,6 @@ static const struct mtk_pinctrl_devdata mt8135_pinctrl_data = { .port_shf = 4, .port_mask = 0xf, .port_align = 4, - .chip_type = MTK_CHIP_TYPE_BASE, .eint_offsets = { .name = "mt8135_eint", .stat = 0x000, diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.h b/drivers/pinctrl/mediatek/pinctrl-mtk-common.h index 375771d..1508849 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.h +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.h @@ -19,8 +19,6 @@ #include #define NO_EINT_SUPPORT 255 -#define MTK_CHIP_TYPE_BASE 0 -#define MTK_CHIP_TYPE_PMIC 1 #define MT_EDGE_SENSITIVE 0 #define MT_LEVEL_SENSITIVE 1 #define EINT_DBNC_SET_DBNC_BITS 4 @@ -39,7 +37,6 @@ struct mtk_desc_eint { struct mtk_desc_pin { struct pinctrl_pin_desc pin; - const char *chip; const struct mtk_desc_eint eint; const struct mtk_desc_function *functions; }; @@ -47,7 +44,6 @@ struct mtk_desc_pin { #define MTK_PIN(_pin, _pad, _chip, _eint, ...) \ { \ .pin = _pin, \ - .chip = _chip, \ .eint = _eint, \ .functions = (struct mtk_desc_function[]){ \ __VA_ARGS__, { } }, \ @@ -107,8 +103,8 @@ struct mtk_drv_group_desc { * @grp: The group for this pin belongs to. */ struct mtk_pin_drv_grp { - unsigned int pin; - unsigned int offset; + unsigned short pin; + unsigned short offset; unsigned char bit; unsigned char grp; }; @@ -193,7 +189,6 @@ struct mtk_pinctrl_devdata { unsigned int pullen_offset; unsigned int pullsel_offset; unsigned int drv_offset; - unsigned int invser_offset; unsigned int dout_offset; unsigned int din_offset; unsigned int pinmux_offset; @@ -202,7 +197,6 @@ struct mtk_pinctrl_devdata { unsigned char port_shf; unsigned char port_mask; unsigned char port_align; - unsigned char chip_type; struct mtk_eint_offsets eint_offsets; unsigned int ap_num; unsigned int db_cnt; -- cgit v0.10.2 From e73fe2713fc9e8ab8d2d039abc48f7684b60f5ac Mon Sep 17 00:00:00 2001 From: Yingjoe Chen Date: Mon, 18 May 2015 23:11:15 -0700 Subject: pinctrl: mediatek: add mtk_pctrl_spec_pull_set_samereg common code Several mediatek soc use similar pull setting procedure as mt8173, the pupd enable and resistance setting are in the same register. Add common code mtk_pctrl_spec_pull_set_samereg out of spec_pull_set in mt8173 to handle this case, so future soc driver can use it. Signed-off-by: Yingjoe Chen Signed-off-by: Hongzhou Yang Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8173.c b/drivers/pinctrl/mediatek/pinctrl-mt8173.c index 412ea84..cc44b27 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8173.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8173.c @@ -47,130 +47,54 @@ struct mtk_pin_ies_smt_set { .offset = _offset, \ } -/** - * struct mtk_pin_spec_pupd_set - For special pins' pull up/down setting. - * @pin: The pin number. - * @offset: The offset of special pull up/down setting register. - * @pupd_bit: The pull up/down bit in this register. - * @r0_bit: The r0 bit of pull resistor. - * @r1_bit: The r1 bit of pull resistor. - */ -struct mtk_pin_spec_pupd_set { - unsigned int pin; - unsigned int offset; - unsigned char pupd_bit; - unsigned char r1_bit; - unsigned char r0_bit; -}; - -#define MTK_PIN_PUPD_SPEC(_pin, _offset, _pupd, _r1, _r0) \ - { \ - .pin = _pin, \ - .offset = _offset, \ - .pupd_bit = _pupd, \ - .r1_bit = _r1, \ - .r0_bit = _r0, \ - } - -static const struct mtk_pin_spec_pupd_set mt8173_spec_pupd[] = { - MTK_PIN_PUPD_SPEC(119, 0xe00, 2, 1, 0), /* KROW0 */ - MTK_PIN_PUPD_SPEC(120, 0xe00, 6, 5, 4), /* KROW1 */ - MTK_PIN_PUPD_SPEC(121, 0xe00, 10, 9, 8), /* KROW2 */ - MTK_PIN_PUPD_SPEC(122, 0xe10, 2, 1, 0), /* KCOL0 */ - MTK_PIN_PUPD_SPEC(123, 0xe10, 6, 5, 4), /* KCOL1 */ - MTK_PIN_PUPD_SPEC(124, 0xe10, 10, 9, 8), /* KCOL2 */ - - MTK_PIN_PUPD_SPEC(67, 0xd10, 2, 1, 0), /* ms0 DS */ - MTK_PIN_PUPD_SPEC(68, 0xd00, 2, 1, 0), /* ms0 RST */ - MTK_PIN_PUPD_SPEC(66, 0xc10, 2, 1, 0), /* ms0 cmd */ - MTK_PIN_PUPD_SPEC(65, 0xc00, 2, 1, 0), /* ms0 clk */ - MTK_PIN_PUPD_SPEC(57, 0xc20, 2, 1, 0), /* ms0 data0 */ - MTK_PIN_PUPD_SPEC(58, 0xc20, 2, 1, 0), /* ms0 data1 */ - MTK_PIN_PUPD_SPEC(59, 0xc20, 2, 1, 0), /* ms0 data2 */ - MTK_PIN_PUPD_SPEC(60, 0xc20, 2, 1, 0), /* ms0 data3 */ - MTK_PIN_PUPD_SPEC(61, 0xc20, 2, 1, 0), /* ms0 data4 */ - MTK_PIN_PUPD_SPEC(62, 0xc20, 2, 1, 0), /* ms0 data5 */ - MTK_PIN_PUPD_SPEC(63, 0xc20, 2, 1, 0), /* ms0 data6 */ - MTK_PIN_PUPD_SPEC(64, 0xc20, 2, 1, 0), /* ms0 data7 */ - - MTK_PIN_PUPD_SPEC(78, 0xc50, 2, 1, 0), /* ms1 cmd */ - MTK_PIN_PUPD_SPEC(73, 0xd20, 2, 1, 0), /* ms1 dat0 */ - MTK_PIN_PUPD_SPEC(74, 0xd20, 6, 5, 4), /* ms1 dat1 */ - MTK_PIN_PUPD_SPEC(75, 0xd20, 10, 9, 8), /* ms1 dat2 */ - MTK_PIN_PUPD_SPEC(76, 0xd20, 14, 13, 12), /* ms1 dat3 */ - MTK_PIN_PUPD_SPEC(77, 0xc40, 2, 1, 0), /* ms1 clk */ - - MTK_PIN_PUPD_SPEC(100, 0xd40, 2, 1, 0), /* ms2 dat0 */ - MTK_PIN_PUPD_SPEC(101, 0xd40, 6, 5, 4), /* ms2 dat1 */ - MTK_PIN_PUPD_SPEC(102, 0xd40, 10, 9, 8), /* ms2 dat2 */ - MTK_PIN_PUPD_SPEC(103, 0xd40, 14, 13, 12), /* ms2 dat3 */ - MTK_PIN_PUPD_SPEC(104, 0xc80, 2, 1, 0), /* ms2 clk */ - MTK_PIN_PUPD_SPEC(105, 0xc90, 2, 1, 0), /* ms2 cmd */ - - MTK_PIN_PUPD_SPEC(22, 0xd60, 2, 1, 0), /* ms3 dat0 */ - MTK_PIN_PUPD_SPEC(23, 0xd60, 6, 5, 4), /* ms3 dat1 */ - MTK_PIN_PUPD_SPEC(24, 0xd60, 10, 9, 8), /* ms3 dat2 */ - MTK_PIN_PUPD_SPEC(25, 0xd60, 14, 13, 12), /* ms3 dat3 */ - MTK_PIN_PUPD_SPEC(26, 0xcc0, 2, 1, 0), /* ms3 clk */ - MTK_PIN_PUPD_SPEC(27, 0xcd0, 2, 1, 0) /* ms3 cmd */ +static const struct mtk_pin_spec_pupd_set_samereg mt8173_spec_pupd[] = { + MTK_PIN_PUPD_SPEC_SR(119, 0xe00, 2, 1, 0), /* KROW0 */ + MTK_PIN_PUPD_SPEC_SR(120, 0xe00, 6, 5, 4), /* KROW1 */ + MTK_PIN_PUPD_SPEC_SR(121, 0xe00, 10, 9, 8), /* KROW2 */ + MTK_PIN_PUPD_SPEC_SR(122, 0xe10, 2, 1, 0), /* KCOL0 */ + MTK_PIN_PUPD_SPEC_SR(123, 0xe10, 6, 5, 4), /* KCOL1 */ + MTK_PIN_PUPD_SPEC_SR(124, 0xe10, 10, 9, 8), /* KCOL2 */ + + MTK_PIN_PUPD_SPEC_SR(67, 0xd10, 2, 1, 0), /* ms0 DS */ + MTK_PIN_PUPD_SPEC_SR(68, 0xd00, 2, 1, 0), /* ms0 RST */ + MTK_PIN_PUPD_SPEC_SR(66, 0xc10, 2, 1, 0), /* ms0 cmd */ + MTK_PIN_PUPD_SPEC_SR(65, 0xc00, 2, 1, 0), /* ms0 clk */ + MTK_PIN_PUPD_SPEC_SR(57, 0xc20, 2, 1, 0), /* ms0 data0 */ + MTK_PIN_PUPD_SPEC_SR(58, 0xc20, 2, 1, 0), /* ms0 data1 */ + MTK_PIN_PUPD_SPEC_SR(59, 0xc20, 2, 1, 0), /* ms0 data2 */ + MTK_PIN_PUPD_SPEC_SR(60, 0xc20, 2, 1, 0), /* ms0 data3 */ + MTK_PIN_PUPD_SPEC_SR(61, 0xc20, 2, 1, 0), /* ms0 data4 */ + MTK_PIN_PUPD_SPEC_SR(62, 0xc20, 2, 1, 0), /* ms0 data5 */ + MTK_PIN_PUPD_SPEC_SR(63, 0xc20, 2, 1, 0), /* ms0 data6 */ + MTK_PIN_PUPD_SPEC_SR(64, 0xc20, 2, 1, 0), /* ms0 data7 */ + + MTK_PIN_PUPD_SPEC_SR(78, 0xc50, 2, 1, 0), /* ms1 cmd */ + MTK_PIN_PUPD_SPEC_SR(73, 0xd20, 2, 1, 0), /* ms1 dat0 */ + MTK_PIN_PUPD_SPEC_SR(74, 0xd20, 6, 5, 4), /* ms1 dat1 */ + MTK_PIN_PUPD_SPEC_SR(75, 0xd20, 10, 9, 8), /* ms1 dat2 */ + MTK_PIN_PUPD_SPEC_SR(76, 0xd20, 14, 13, 12), /* ms1 dat3 */ + MTK_PIN_PUPD_SPEC_SR(77, 0xc40, 2, 1, 0), /* ms1 clk */ + + MTK_PIN_PUPD_SPEC_SR(100, 0xd40, 2, 1, 0), /* ms2 dat0 */ + MTK_PIN_PUPD_SPEC_SR(101, 0xd40, 6, 5, 4), /* ms2 dat1 */ + MTK_PIN_PUPD_SPEC_SR(102, 0xd40, 10, 9, 8), /* ms2 dat2 */ + MTK_PIN_PUPD_SPEC_SR(103, 0xd40, 14, 13, 12), /* ms2 dat3 */ + MTK_PIN_PUPD_SPEC_SR(104, 0xc80, 2, 1, 0), /* ms2 clk */ + MTK_PIN_PUPD_SPEC_SR(105, 0xc90, 2, 1, 0), /* ms2 cmd */ + + MTK_PIN_PUPD_SPEC_SR(22, 0xd60, 2, 1, 0), /* ms3 dat0 */ + MTK_PIN_PUPD_SPEC_SR(23, 0xd60, 6, 5, 4), /* ms3 dat1 */ + MTK_PIN_PUPD_SPEC_SR(24, 0xd60, 10, 9, 8), /* ms3 dat2 */ + MTK_PIN_PUPD_SPEC_SR(25, 0xd60, 14, 13, 12), /* ms3 dat3 */ + MTK_PIN_PUPD_SPEC_SR(26, 0xcc0, 2, 1, 0), /* ms3 clk */ + MTK_PIN_PUPD_SPEC_SR(27, 0xcd0, 2, 1, 0) /* ms3 cmd */ }; -static int spec_pull_set(struct regmap *regmap, unsigned int pin, +static int mt8173_spec_pull_set(struct regmap *regmap, unsigned int pin, unsigned char align, bool isup, unsigned int r1r0) { - unsigned int i; - unsigned int reg_pupd, reg_set, reg_rst; - unsigned int bit_pupd, bit_r0, bit_r1; - const struct mtk_pin_spec_pupd_set *spec_pupd_pin; - bool find = false; - - for (i = 0; i < ARRAY_SIZE(mt8173_spec_pupd); i++) { - if (pin == mt8173_spec_pupd[i].pin) { - find = true; - break; - } - } - - if (!find) - return -EINVAL; - - spec_pupd_pin = mt8173_spec_pupd + i; - reg_set = spec_pupd_pin->offset + align; - reg_rst = spec_pupd_pin->offset + (align << 1); - - if (isup) - reg_pupd = reg_rst; - else - reg_pupd = reg_set; - - bit_pupd = BIT(spec_pupd_pin->pupd_bit); - regmap_write(regmap, reg_pupd, bit_pupd); - - bit_r0 = BIT(spec_pupd_pin->r0_bit); - bit_r1 = BIT(spec_pupd_pin->r1_bit); - - switch (r1r0) { - case MTK_PUPD_SET_R1R0_00: - regmap_write(regmap, reg_rst, bit_r0); - regmap_write(regmap, reg_rst, bit_r1); - break; - case MTK_PUPD_SET_R1R0_01: - regmap_write(regmap, reg_set, bit_r0); - regmap_write(regmap, reg_rst, bit_r1); - break; - case MTK_PUPD_SET_R1R0_10: - regmap_write(regmap, reg_rst, bit_r0); - regmap_write(regmap, reg_set, bit_r1); - break; - case MTK_PUPD_SET_R1R0_11: - regmap_write(regmap, reg_set, bit_r0); - regmap_write(regmap, reg_set, bit_r1); - break; - default: - return -EINVAL; - } - - return 0; + return mtk_pctrl_spec_pull_set_samereg(regmap, mt8173_spec_pupd, + ARRAY_SIZE(mt8173_spec_pupd), pin, align, isup, r1r0); } static const struct mtk_pin_ies_smt_set mt8173_ies_smt_set[] = { @@ -382,7 +306,7 @@ static const struct mtk_pinctrl_devdata mt8173_pinctrl_data = { .n_grp_cls = ARRAY_SIZE(mt8173_drv_grp), .pin_drv_grp = mt8173_pin_drv, .n_pin_drv_grps = ARRAY_SIZE(mt8173_pin_drv), - .spec_pull_set = spec_pull_set, + .spec_pull_set = mt8173_spec_pull_set, .spec_ies_smt_set = spec_ies_smt_set, .dir_offset = 0x0000, .pullen_offset = 0x0100, diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c index 493294c..0aee6bc 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c @@ -186,6 +186,66 @@ static int mtk_pconf_set_driving(struct mtk_pinctrl *pctl, return -EINVAL; } +int mtk_pctrl_spec_pull_set_samereg(struct regmap *regmap, + const struct mtk_pin_spec_pupd_set_samereg *pupd_infos, + unsigned int info_num, unsigned int pin, + unsigned char align, bool isup, unsigned int r1r0) +{ + unsigned int i; + unsigned int reg_pupd, reg_set, reg_rst; + unsigned int bit_pupd, bit_r0, bit_r1; + const struct mtk_pin_spec_pupd_set_samereg *spec_pupd_pin; + bool find = false; + + for (i = 0; i < info_num; i++) { + if (pin == pupd_infos[i].pin) { + find = true; + break; + } + } + + if (!find) + return -EINVAL; + + spec_pupd_pin = pupd_infos + i; + reg_set = spec_pupd_pin->offset + align; + reg_rst = spec_pupd_pin->offset + (align << 1); + + if (isup) + reg_pupd = reg_rst; + else + reg_pupd = reg_set; + + bit_pupd = BIT(spec_pupd_pin->pupd_bit); + regmap_write(regmap, reg_pupd, bit_pupd); + + bit_r0 = BIT(spec_pupd_pin->r0_bit); + bit_r1 = BIT(spec_pupd_pin->r1_bit); + + switch (r1r0) { + case MTK_PUPD_SET_R1R0_00: + regmap_write(regmap, reg_rst, bit_r0); + regmap_write(regmap, reg_rst, bit_r1); + break; + case MTK_PUPD_SET_R1R0_01: + regmap_write(regmap, reg_set, bit_r0); + regmap_write(regmap, reg_rst, bit_r1); + break; + case MTK_PUPD_SET_R1R0_10: + regmap_write(regmap, reg_rst, bit_r0); + regmap_write(regmap, reg_set, bit_r1); + break; + case MTK_PUPD_SET_R1R0_11: + regmap_write(regmap, reg_set, bit_r0); + regmap_write(regmap, reg_set, bit_r1); + break; + default: + return -EINVAL; + } + + return 0; +} + static int mtk_pconf_set_pull_select(struct mtk_pinctrl *pctl, unsigned int pin, bool enable, bool isup, unsigned int arg) { diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.h b/drivers/pinctrl/mediatek/pinctrl-mtk-common.h index 1508849..2a4b7be 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.h +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.h @@ -117,6 +117,32 @@ struct mtk_pin_drv_grp { .grp = _grp, \ } +/** + * struct mtk_pin_spec_pupd_set_samereg + * - For special pins' pull up/down setting which resides in same register + * @pin: The pin number. + * @offset: The offset of special pull up/down setting register. + * @pupd_bit: The pull up/down bit in this register. + * @r0_bit: The r0 bit of pull resistor. + * @r1_bit: The r1 bit of pull resistor. + */ +struct mtk_pin_spec_pupd_set_samereg { + unsigned short pin; + unsigned short offset; + unsigned char pupd_bit; + unsigned char r1_bit; + unsigned char r0_bit; +}; + +#define MTK_PIN_PUPD_SPEC_SR(_pin, _offset, _pupd, _r1, _r0) \ + { \ + .pin = _pin, \ + .offset = _offset, \ + .pupd_bit = _pupd, \ + .r1_bit = _r1, \ + .r0_bit = _r0, \ + } + struct mtk_eint_offsets { const char *name; unsigned int stat; @@ -220,4 +246,9 @@ struct mtk_pinctrl { int mtk_pctrl_init(struct platform_device *pdev, const struct mtk_pinctrl_devdata *data); +int mtk_pctrl_spec_pull_set_samereg(struct regmap *regmap, + const struct mtk_pin_spec_pupd_set_samereg *pupd_infos, + unsigned int info_num, unsigned int pin, + unsigned char align, bool isup, unsigned int r1r0); + #endif /* __PINCTRL_MTK_COMMON_H */ -- cgit v0.10.2 From 25d76b21b1b959b37520931fb6c4b8319a021705 Mon Sep 17 00:00:00 2001 From: Hongzhou Yang Date: Mon, 18 May 2015 23:11:16 -0700 Subject: pinctrl: mediatek: add ies/smt control to common code. Input enable and smt setting have different register, modify code to fix it. Several mediatek soc use similar input enable/smt setting procedure as mt8173, some soc use generic input enable/smt setting, some soc has no input enable/smt setting. Adding common code to handle all those cases, so future soc driver can use it. Signed-off-by: Hongzhou Yang Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8173.c b/drivers/pinctrl/mediatek/pinctrl-mt8173.c index cc44b27..a7e5b24 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8173.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8173.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include "pinctrl-mtk-common.h" @@ -25,28 +26,6 @@ #define DRV_BASE 0xb00 -/** - * struct mtk_pin_ies_smt_set - For special pins' ies and smt setting. - * @start: The start pin number of those special pins. - * @end: The end pin number of those special pins. - * @offset: The offset of special setting register. - * @bit: The bit of special setting register. - */ -struct mtk_pin_ies_smt_set { - unsigned int start; - unsigned int end; - unsigned int offset; - unsigned char bit; -}; - -#define MTK_PIN_IES_SMT_SET(_start, _end, _offset, _bit) \ - { \ - .start = _start, \ - .end = _end, \ - .bit = _bit, \ - .offset = _offset, \ - } - static const struct mtk_pin_spec_pupd_set_samereg mt8173_spec_pupd[] = { MTK_PIN_PUPD_SPEC_SR(119, 0xe00, 2, 1, 0), /* KROW0 */ MTK_PIN_PUPD_SPEC_SR(120, 0xe00, 6, 5, 4), /* KROW1 */ @@ -97,80 +76,114 @@ static int mt8173_spec_pull_set(struct regmap *regmap, unsigned int pin, ARRAY_SIZE(mt8173_spec_pupd), pin, align, isup, r1r0); } -static const struct mtk_pin_ies_smt_set mt8173_ies_smt_set[] = { - MTK_PIN_IES_SMT_SET(0, 4, 0x930, 1), - MTK_PIN_IES_SMT_SET(5, 9, 0x930, 2), - MTK_PIN_IES_SMT_SET(10, 13, 0x930, 10), - MTK_PIN_IES_SMT_SET(14, 15, 0x940, 10), - MTK_PIN_IES_SMT_SET(16, 16, 0x930, 0), - MTK_PIN_IES_SMT_SET(17, 17, 0x950, 2), - MTK_PIN_IES_SMT_SET(18, 21, 0x940, 3), - MTK_PIN_IES_SMT_SET(29, 32, 0x930, 3), - MTK_PIN_IES_SMT_SET(33, 33, 0x930, 4), - MTK_PIN_IES_SMT_SET(34, 36, 0x930, 5), - MTK_PIN_IES_SMT_SET(37, 38, 0x930, 6), - MTK_PIN_IES_SMT_SET(39, 39, 0x930, 7), - MTK_PIN_IES_SMT_SET(40, 41, 0x930, 9), - MTK_PIN_IES_SMT_SET(42, 42, 0x940, 0), - MTK_PIN_IES_SMT_SET(43, 44, 0x930, 11), - MTK_PIN_IES_SMT_SET(45, 46, 0x930, 12), - MTK_PIN_IES_SMT_SET(57, 64, 0xc20, 13), - MTK_PIN_IES_SMT_SET(65, 65, 0xc10, 13), - MTK_PIN_IES_SMT_SET(66, 66, 0xc00, 13), - MTK_PIN_IES_SMT_SET(67, 67, 0xd10, 13), - MTK_PIN_IES_SMT_SET(68, 68, 0xd00, 13), - MTK_PIN_IES_SMT_SET(69, 72, 0x940, 14), - MTK_PIN_IES_SMT_SET(73, 76, 0xc60, 13), - MTK_PIN_IES_SMT_SET(77, 77, 0xc40, 13), - MTK_PIN_IES_SMT_SET(78, 78, 0xc50, 13), - MTK_PIN_IES_SMT_SET(79, 82, 0x940, 15), - MTK_PIN_IES_SMT_SET(83, 83, 0x950, 0), - MTK_PIN_IES_SMT_SET(84, 85, 0x950, 1), - MTK_PIN_IES_SMT_SET(86, 91, 0x950, 2), - MTK_PIN_IES_SMT_SET(92, 92, 0x930, 13), - MTK_PIN_IES_SMT_SET(93, 95, 0x930, 14), - MTK_PIN_IES_SMT_SET(96, 99, 0x930, 15), - MTK_PIN_IES_SMT_SET(100, 103, 0xca0, 13), - MTK_PIN_IES_SMT_SET(104, 104, 0xc80, 13), - MTK_PIN_IES_SMT_SET(105, 105, 0xc90, 13), - MTK_PIN_IES_SMT_SET(106, 107, 0x940, 4), - MTK_PIN_IES_SMT_SET(108, 112, 0x940, 1), - MTK_PIN_IES_SMT_SET(113, 116, 0x940, 2), - MTK_PIN_IES_SMT_SET(117, 118, 0x940, 5), - MTK_PIN_IES_SMT_SET(119, 124, 0x940, 6), - MTK_PIN_IES_SMT_SET(125, 126, 0x940, 7), - MTK_PIN_IES_SMT_SET(127, 127, 0x940, 0), - MTK_PIN_IES_SMT_SET(128, 128, 0x950, 8), - MTK_PIN_IES_SMT_SET(129, 130, 0x950, 9), - MTK_PIN_IES_SMT_SET(131, 132, 0x950, 8), - MTK_PIN_IES_SMT_SET(133, 134, 0x910, 8) +static const struct mtk_pin_ies_smt_set mt8173_smt_set[] = { + MTK_PIN_IES_SMT_SPEC(0, 4, 0x930, 1), + MTK_PIN_IES_SMT_SPEC(5, 9, 0x930, 2), + MTK_PIN_IES_SMT_SPEC(10, 13, 0x930, 10), + MTK_PIN_IES_SMT_SPEC(14, 15, 0x940, 10), + MTK_PIN_IES_SMT_SPEC(16, 16, 0x930, 0), + MTK_PIN_IES_SMT_SPEC(17, 17, 0x950, 2), + MTK_PIN_IES_SMT_SPEC(18, 21, 0x940, 3), + MTK_PIN_IES_SMT_SPEC(29, 32, 0x930, 3), + MTK_PIN_IES_SMT_SPEC(33, 33, 0x930, 4), + MTK_PIN_IES_SMT_SPEC(34, 36, 0x930, 5), + MTK_PIN_IES_SMT_SPEC(37, 38, 0x930, 6), + MTK_PIN_IES_SMT_SPEC(39, 39, 0x930, 7), + MTK_PIN_IES_SMT_SPEC(40, 41, 0x930, 9), + MTK_PIN_IES_SMT_SPEC(42, 42, 0x940, 0), + MTK_PIN_IES_SMT_SPEC(43, 44, 0x930, 11), + MTK_PIN_IES_SMT_SPEC(45, 46, 0x930, 12), + MTK_PIN_IES_SMT_SPEC(57, 64, 0xc20, 13), + MTK_PIN_IES_SMT_SPEC(65, 65, 0xc10, 13), + MTK_PIN_IES_SMT_SPEC(66, 66, 0xc00, 13), + MTK_PIN_IES_SMT_SPEC(67, 67, 0xd10, 13), + MTK_PIN_IES_SMT_SPEC(68, 68, 0xd00, 13), + MTK_PIN_IES_SMT_SPEC(69, 72, 0x940, 14), + MTK_PIN_IES_SMT_SPEC(73, 76, 0xc60, 13), + MTK_PIN_IES_SMT_SPEC(77, 77, 0xc40, 13), + MTK_PIN_IES_SMT_SPEC(78, 78, 0xc50, 13), + MTK_PIN_IES_SMT_SPEC(79, 82, 0x940, 15), + MTK_PIN_IES_SMT_SPEC(83, 83, 0x950, 0), + MTK_PIN_IES_SMT_SPEC(84, 85, 0x950, 1), + MTK_PIN_IES_SMT_SPEC(86, 91, 0x950, 2), + MTK_PIN_IES_SMT_SPEC(92, 92, 0x930, 13), + MTK_PIN_IES_SMT_SPEC(93, 95, 0x930, 14), + MTK_PIN_IES_SMT_SPEC(96, 99, 0x930, 15), + MTK_PIN_IES_SMT_SPEC(100, 103, 0xca0, 13), + MTK_PIN_IES_SMT_SPEC(104, 104, 0xc80, 13), + MTK_PIN_IES_SMT_SPEC(105, 105, 0xc90, 13), + MTK_PIN_IES_SMT_SPEC(106, 107, 0x940, 4), + MTK_PIN_IES_SMT_SPEC(108, 112, 0x940, 1), + MTK_PIN_IES_SMT_SPEC(113, 116, 0x940, 2), + MTK_PIN_IES_SMT_SPEC(117, 118, 0x940, 5), + MTK_PIN_IES_SMT_SPEC(119, 124, 0x940, 6), + MTK_PIN_IES_SMT_SPEC(125, 126, 0x940, 7), + MTK_PIN_IES_SMT_SPEC(127, 127, 0x940, 0), + MTK_PIN_IES_SMT_SPEC(128, 128, 0x950, 8), + MTK_PIN_IES_SMT_SPEC(129, 130, 0x950, 9), + MTK_PIN_IES_SMT_SPEC(131, 132, 0x950, 8), + MTK_PIN_IES_SMT_SPEC(133, 134, 0x910, 8) }; -static int spec_ies_smt_set(struct regmap *regmap, unsigned int pin, - unsigned char align, int value) -{ - unsigned int i, reg_addr, bit; - bool find = false; - - for (i = 0; i < ARRAY_SIZE(mt8173_ies_smt_set); i++) { - if (pin >= mt8173_ies_smt_set[i].start && - pin <= mt8173_ies_smt_set[i].end) { - find = true; - break; - } - } - - if (!find) - return -EINVAL; - - if (value) - reg_addr = mt8173_ies_smt_set[i].offset + align; - else - reg_addr = mt8173_ies_smt_set[i].offset + (align << 1); +static const struct mtk_pin_ies_smt_set mt8173_ies_set[] = { + MTK_PIN_IES_SMT_SPEC(0, 4, 0x900, 1), + MTK_PIN_IES_SMT_SPEC(5, 9, 0x900, 2), + MTK_PIN_IES_SMT_SPEC(10, 13, 0x900, 10), + MTK_PIN_IES_SMT_SPEC(14, 15, 0x910, 10), + MTK_PIN_IES_SMT_SPEC(16, 16, 0x900, 0), + MTK_PIN_IES_SMT_SPEC(17, 17, 0x920, 2), + MTK_PIN_IES_SMT_SPEC(18, 21, 0x910, 3), + MTK_PIN_IES_SMT_SPEC(29, 32, 0x900, 3), + MTK_PIN_IES_SMT_SPEC(33, 33, 0x900, 4), + MTK_PIN_IES_SMT_SPEC(34, 36, 0x900, 5), + MTK_PIN_IES_SMT_SPEC(37, 38, 0x900, 6), + MTK_PIN_IES_SMT_SPEC(39, 39, 0x900, 7), + MTK_PIN_IES_SMT_SPEC(40, 41, 0x900, 9), + MTK_PIN_IES_SMT_SPEC(42, 42, 0x910, 0), + MTK_PIN_IES_SMT_SPEC(43, 44, 0x900, 11), + MTK_PIN_IES_SMT_SPEC(45, 46, 0x900, 12), + MTK_PIN_IES_SMT_SPEC(57, 64, 0xc20, 14), + MTK_PIN_IES_SMT_SPEC(65, 65, 0xc10, 14), + MTK_PIN_IES_SMT_SPEC(66, 66, 0xc00, 14), + MTK_PIN_IES_SMT_SPEC(67, 67, 0xd10, 14), + MTK_PIN_IES_SMT_SPEC(68, 68, 0xd00, 14), + MTK_PIN_IES_SMT_SPEC(69, 72, 0x910, 14), + MTK_PIN_IES_SMT_SPEC(73, 76, 0xc60, 14), + MTK_PIN_IES_SMT_SPEC(77, 77, 0xc40, 14), + MTK_PIN_IES_SMT_SPEC(78, 78, 0xc50, 14), + MTK_PIN_IES_SMT_SPEC(79, 82, 0x910, 15), + MTK_PIN_IES_SMT_SPEC(83, 83, 0x920, 0), + MTK_PIN_IES_SMT_SPEC(84, 85, 0x920, 1), + MTK_PIN_IES_SMT_SPEC(86, 91, 0x920, 2), + MTK_PIN_IES_SMT_SPEC(92, 92, 0x900, 13), + MTK_PIN_IES_SMT_SPEC(93, 95, 0x900, 14), + MTK_PIN_IES_SMT_SPEC(96, 99, 0x900, 15), + MTK_PIN_IES_SMT_SPEC(100, 103, 0xca0, 14), + MTK_PIN_IES_SMT_SPEC(104, 104, 0xc80, 14), + MTK_PIN_IES_SMT_SPEC(105, 105, 0xc90, 14), + MTK_PIN_IES_SMT_SPEC(106, 107, 0x91, 4), + MTK_PIN_IES_SMT_SPEC(108, 112, 0x910, 1), + MTK_PIN_IES_SMT_SPEC(113, 116, 0x910, 2), + MTK_PIN_IES_SMT_SPEC(117, 118, 0x910, 5), + MTK_PIN_IES_SMT_SPEC(119, 124, 0x910, 6), + MTK_PIN_IES_SMT_SPEC(125, 126, 0x910, 7), + MTK_PIN_IES_SMT_SPEC(127, 127, 0x910, 0), + MTK_PIN_IES_SMT_SPEC(128, 128, 0x920, 8), + MTK_PIN_IES_SMT_SPEC(129, 130, 0x920, 9), + MTK_PIN_IES_SMT_SPEC(131, 132, 0x920, 8), + MTK_PIN_IES_SMT_SPEC(133, 134, 0x910, 8) +}; - bit = BIT(mt8173_ies_smt_set[i].bit); - regmap_write(regmap, reg_addr, bit); - return 0; +static int mt8173_ies_smt_set(struct regmap *regmap, unsigned int pin, + unsigned char align, int value, enum pin_config_param arg) +{ + if (arg == PIN_CONFIG_INPUT_ENABLE) + return mtk_pconf_spec_set_ies_smt_range(regmap, mt8173_ies_set, + ARRAY_SIZE(mt8173_ies_set), pin, align, value); + else if (arg == PIN_CONFIG_INPUT_SCHMITT_ENABLE) + return mtk_pconf_spec_set_ies_smt_range(regmap, mt8173_smt_set, + ARRAY_SIZE(mt8173_smt_set), pin, align, value); + return -EINVAL; } static const struct mtk_drv_group_desc mt8173_drv_grp[] = { @@ -307,7 +320,7 @@ static const struct mtk_pinctrl_devdata mt8173_pinctrl_data = { .pin_drv_grp = mt8173_pin_drv, .n_pin_drv_grps = ARRAY_SIZE(mt8173_pin_drv), .spec_pull_set = mt8173_spec_pull_set, - .spec_ies_smt_set = spec_ies_smt_set, + .spec_ies_smt_set = mt8173_ies_smt_set, .dir_offset = 0x0000, .pullen_offset = 0x0100, .pullsel_offset = 0x0200, diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c index 0aee6bc..36f8920 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c @@ -107,28 +107,38 @@ static void mtk_gpio_set(struct gpio_chip *chip, unsigned offset, int value) regmap_write(mtk_get_regmap(pctl, offset), reg_addr, bit); } -static void mtk_pconf_set_ies_smt(struct mtk_pinctrl *pctl, unsigned pin, - int value, enum pin_config_param param) +static int mtk_pconf_set_ies_smt(struct mtk_pinctrl *pctl, unsigned pin, + int value, enum pin_config_param arg) { unsigned int reg_addr, offset; unsigned int bit; - int ret; + + /** + * Due to some soc are not support ies/smt config, add this special + * control to handle it. + */ + if (!pctl->devdata->spec_ies_smt_set && + pctl->devdata->ies_offset == MTK_PINCTRL_NOT_SUPPORT && + arg == PIN_CONFIG_INPUT_ENABLE) + return -EINVAL; + + if (!pctl->devdata->spec_ies_smt_set && + pctl->devdata->smt_offset == MTK_PINCTRL_NOT_SUPPORT && + arg == PIN_CONFIG_INPUT_SCHMITT_ENABLE) + return -EINVAL; /* * Due to some pins are irregular, their input enable and smt - * control register are discontinuous, but they are mapping together. - * So we need this special handle. + * control register are discontinuous, so we need this special handle. */ if (pctl->devdata->spec_ies_smt_set) { - ret = pctl->devdata->spec_ies_smt_set(mtk_get_regmap(pctl, pin), - pin, pctl->devdata->port_align, value); - if (!ret) - return; + return pctl->devdata->spec_ies_smt_set(mtk_get_regmap(pctl, pin), + pin, pctl->devdata->port_align, value, arg); } bit = BIT(pin & 0xf); - if (param == PIN_CONFIG_INPUT_ENABLE) + if (arg == PIN_CONFIG_INPUT_ENABLE) offset = pctl->devdata->ies_offset; else offset = pctl->devdata->smt_offset; @@ -139,6 +149,33 @@ static void mtk_pconf_set_ies_smt(struct mtk_pinctrl *pctl, unsigned pin, reg_addr = CLR_ADDR(mtk_get_port(pctl, pin) + offset, pctl); regmap_write(mtk_get_regmap(pctl, pin), reg_addr, bit); + return 0; +} + +int mtk_pconf_spec_set_ies_smt_range(struct regmap *regmap, + const struct mtk_pin_ies_smt_set *ies_smt_infos, unsigned int info_num, + unsigned int pin, unsigned char align, int value) +{ + unsigned int i, reg_addr, bit; + + for (i = 0; i < info_num; i++) { + if (pin >= ies_smt_infos[i].start && + pin <= ies_smt_infos[i].end) { + break; + } + } + + if (i == info_num) + return -EINVAL; + + if (value) + reg_addr = ies_smt_infos[i].offset + align; + else + reg_addr = ies_smt_infos[i].offset + (align << 1); + + bit = BIT(ies_smt_infos[i].bit); + regmap_write(regmap, reg_addr, bit); + return 0; } static const struct mtk_pin_drv_grp *mtk_find_pin_drv_grp_by_pin( @@ -295,36 +332,37 @@ static int mtk_pconf_parse_conf(struct pinctrl_dev *pctldev, unsigned int pin, enum pin_config_param param, enum pin_config_param arg) { + int ret = 0; struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); switch (param) { case PIN_CONFIG_BIAS_DISABLE: - mtk_pconf_set_pull_select(pctl, pin, false, false, arg); + ret = mtk_pconf_set_pull_select(pctl, pin, false, false, arg); break; case PIN_CONFIG_BIAS_PULL_UP: - mtk_pconf_set_pull_select(pctl, pin, true, true, arg); + ret = mtk_pconf_set_pull_select(pctl, pin, true, true, arg); break; case PIN_CONFIG_BIAS_PULL_DOWN: - mtk_pconf_set_pull_select(pctl, pin, true, false, arg); + ret = mtk_pconf_set_pull_select(pctl, pin, true, false, arg); break; case PIN_CONFIG_INPUT_ENABLE: - mtk_pconf_set_ies_smt(pctl, pin, arg, param); + ret = mtk_pconf_set_ies_smt(pctl, pin, arg, param); break; case PIN_CONFIG_OUTPUT: mtk_gpio_set(pctl->chip, pin, arg); - mtk_pmx_gpio_set_direction(pctldev, NULL, pin, false); + ret = mtk_pmx_gpio_set_direction(pctldev, NULL, pin, false); break; case PIN_CONFIG_INPUT_SCHMITT_ENABLE: - mtk_pconf_set_ies_smt(pctl, pin, arg, param); + ret = mtk_pconf_set_ies_smt(pctl, pin, arg, param); break; case PIN_CONFIG_DRIVE_STRENGTH: - mtk_pconf_set_driving(pctl, pin, arg); + ret = mtk_pconf_set_driving(pctl, pin, arg); break; default: - return -EINVAL; + ret = -EINVAL; } - return 0; + return ret; } static int mtk_pconf_group_get(struct pinctrl_dev *pctldev, @@ -343,12 +381,14 @@ static int mtk_pconf_group_set(struct pinctrl_dev *pctldev, unsigned group, { struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); struct mtk_pinctrl_group *g = &pctl->groups[group]; - int i; + int i, ret; for (i = 0; i < num_configs; i++) { - mtk_pconf_parse_conf(pctldev, g->pin, + ret = mtk_pconf_parse_conf(pctldev, g->pin, pinconf_to_config_param(configs[i]), pinconf_to_config_argument(configs[i])); + if (ret < 0) + return ret; g->config = configs[i]; } diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.h b/drivers/pinctrl/mediatek/pinctrl-mtk-common.h index 2a4b7be..c703e7d 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.h +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.h @@ -17,6 +17,7 @@ #include #include +#include #define NO_EINT_SUPPORT 255 #define MT_EDGE_SENSITIVE 0 @@ -25,6 +26,8 @@ #define EINT_DBNC_RST_BIT (0x1 << 1) #define EINT_DBNC_SET_EN (0x1 << 0) +#define MTK_PINCTRL_NOT_SUPPORT (0xffff) + struct mtk_desc_function { const char *name; unsigned char muxval; @@ -143,6 +146,28 @@ struct mtk_pin_spec_pupd_set_samereg { .r0_bit = _r0, \ } +/** + * struct mtk_pin_ies_set - For special pins' ies and smt setting. + * @start: The start pin number of those special pins. + * @end: The end pin number of those special pins. + * @offset: The offset of special setting register. + * @bit: The bit of special setting register. + */ +struct mtk_pin_ies_smt_set { + unsigned short start; + unsigned short end; + unsigned short offset; + unsigned char bit; +}; + +#define MTK_PIN_IES_SMT_SPEC(_start, _end, _offset, _bit) \ + { \ + .start = _start, \ + .end = _end, \ + .bit = _bit, \ + .offset = _offset, \ + } + struct mtk_eint_offsets { const char *name; unsigned int stat; @@ -208,7 +233,7 @@ struct mtk_pinctrl_devdata { int (*spec_pull_set)(struct regmap *reg, unsigned int pin, unsigned char align, bool isup, unsigned int arg); int (*spec_ies_smt_set)(struct regmap *reg, unsigned int pin, - unsigned char align, int value); + unsigned char align, int value, enum pin_config_param arg); unsigned int dir_offset; unsigned int ies_offset; unsigned int smt_offset; @@ -251,4 +276,8 @@ int mtk_pctrl_spec_pull_set_samereg(struct regmap *regmap, unsigned int info_num, unsigned int pin, unsigned char align, bool isup, unsigned int r1r0); +int mtk_pconf_spec_set_ies_smt_range(struct regmap *regmap, + const struct mtk_pin_ies_smt_set *ies_smt_infos, unsigned int info_num, + unsigned int pin, unsigned char align, int value); + #endif /* __PINCTRL_MTK_COMMON_H */ -- cgit v0.10.2 From fc59e66c4284a420f9a1b3a0f99f784847bf3ef8 Mon Sep 17 00:00:00 2001 From: Hongzhou Yang Date: Mon, 18 May 2015 23:11:17 -0700 Subject: pinctrl: mediatek: Add Pinctrl/GPIO driver for mt6397. Add mt6397 support using mediatek common pinctrl driver. mt6397 is a PMIC, and pinctrl/GPIO is part of 6397 chip. Pinctrl/GPIO driver should obtain regmap from PMIC, so adding this support to common code. Also, mt6397 is no need to support interrupt controller, so changing common code to skip it. Signed-off-by: Hongzhou Yang Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig index 6b3551c..ddae479 100644 --- a/drivers/pinctrl/mediatek/Kconfig +++ b/drivers/pinctrl/mediatek/Kconfig @@ -23,4 +23,10 @@ config PINCTRL_MT8173 default ARM64 && ARCH_MEDIATEK select PINCTRL_MTK_COMMON +# For PMIC +config PINCTRL_MT6397 + bool "Mediatek MT6397 pin control" if COMPILE_TEST && !MFD_MT6397 + default MFD_MT6397 + select PINCTRL_MTK_COMMON + endif diff --git a/drivers/pinctrl/mediatek/Makefile b/drivers/pinctrl/mediatek/Makefile index d8606a2..ad0180c 100644 --- a/drivers/pinctrl/mediatek/Makefile +++ b/drivers/pinctrl/mediatek/Makefile @@ -4,3 +4,4 @@ obj-$(CONFIG_PINCTRL_MTK_COMMON) += pinctrl-mtk-common.o # SoC Drivers obj-$(CONFIG_PINCTRL_MT8135) += pinctrl-mt8135.o obj-$(CONFIG_PINCTRL_MT8173) += pinctrl-mt8173.o +obj-$(CONFIG_PINCTRL_MT6397) += pinctrl-mt6397.o diff --git a/drivers/pinctrl/mediatek/pinctrl-mt6397.c b/drivers/pinctrl/mediatek/pinctrl-mt6397.c new file mode 100644 index 0000000..767bbdf --- /dev/null +++ b/drivers/pinctrl/mediatek/pinctrl-mt6397.c @@ -0,0 +1,78 @@ +/* + * Copyright (c) 2015 MediaTek Inc. + * Author: Hongzhou.Yang + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "pinctrl-mtk-common.h" +#include "pinctrl-mtk-mt6397.h" + +#define MT6397_PIN_REG_BASE 0xc000 + +static const struct mtk_pinctrl_devdata mt6397_pinctrl_data = { + .pins = mtk_pins_mt6397, + .npins = ARRAY_SIZE(mtk_pins_mt6397), + .dir_offset = (MT6397_PIN_REG_BASE + 0x000), + .ies_offset = MTK_PINCTRL_NOT_SUPPORT, + .smt_offset = MTK_PINCTRL_NOT_SUPPORT, + .pullen_offset = (MT6397_PIN_REG_BASE + 0x020), + .pullsel_offset = (MT6397_PIN_REG_BASE + 0x040), + .dout_offset = (MT6397_PIN_REG_BASE + 0x080), + .din_offset = (MT6397_PIN_REG_BASE + 0x0a0), + .pinmux_offset = (MT6397_PIN_REG_BASE + 0x0c0), + .type1_start = 41, + .type1_end = 41, + .port_shf = 3, + .port_mask = 0x3, + .port_align = 2, +}; + +static int mt6397_pinctrl_probe(struct platform_device *pdev) +{ + struct mt6397_chip *mt6397; + + mt6397 = dev_get_drvdata(pdev->dev.parent); + return mtk_pctrl_init(pdev, &mt6397_pinctrl_data, mt6397->regmap); +} + +static const struct of_device_id mt6397_pctrl_match[] = { + { .compatible = "mediatek,mt6397-pinctrl", }, + { } +}; +MODULE_DEVICE_TABLE(of, mt6397_pctrl_match); + +static struct platform_driver mtk_pinctrl_driver = { + .probe = mt6397_pinctrl_probe, + .driver = { + .name = "mediatek-mt6397-pinctrl", + .owner = THIS_MODULE, + .of_match_table = mt6397_pctrl_match, + }, +}; + +static int __init mtk_pinctrl_init(void) +{ + return platform_driver_register(&mtk_pinctrl_driver); +} + +module_init(mtk_pinctrl_init); + +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("MediaTek MT6397 Pinctrl Driver"); +MODULE_AUTHOR("Hongzhou Yang "); diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8135.c b/drivers/pinctrl/mediatek/pinctrl-mt8135.c index 8e6abd5..203bd2a 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8135.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8135.c @@ -342,7 +342,7 @@ static const struct mtk_pinctrl_devdata mt8135_pinctrl_data = { static int mt8135_pinctrl_probe(struct platform_device *pdev) { - return mtk_pctrl_init(pdev, &mt8135_pinctrl_data); + return mtk_pctrl_init(pdev, &mt8135_pinctrl_data, NULL); } static const struct of_device_id mt8135_pctrl_match[] = { diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8173.c b/drivers/pinctrl/mediatek/pinctrl-mt8173.c index a7e5b24..cf4ed6e 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8173.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8173.c @@ -361,7 +361,7 @@ static const struct mtk_pinctrl_devdata mt8173_pinctrl_data = { static int mt8173_pinctrl_probe(struct platform_device *pdev) { - return mtk_pctrl_init(pdev, &mt8173_pinctrl_data); + return mtk_pctrl_init(pdev, &mt8173_pinctrl_data, NULL); } static const struct of_device_id mt8173_pctrl_match[] = { diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c index 36f8920..cd22729 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c @@ -1207,7 +1207,8 @@ static struct pinctrl_desc mtk_pctrl_desc = { }; int mtk_pctrl_init(struct platform_device *pdev, - const struct mtk_pinctrl_devdata *data) + const struct mtk_pinctrl_devdata *data, + struct regmap *regmap) { struct pinctrl_pin_desc *pins; struct mtk_pinctrl *pctl; @@ -1233,6 +1234,11 @@ int mtk_pctrl_init(struct platform_device *pdev, pctl->regmap1 = syscon_node_to_regmap(node); if (IS_ERR(pctl->regmap1)) return PTR_ERR(pctl->regmap1); + } else if (regmap) { + pctl->regmap1 = regmap; + } else { + dev_err(&pdev->dev, "Pinctrl node has not register regmap.\n"); + return -EINVAL; } /* Only 8135 has two base addr, other SoCs have only one. */ @@ -1278,7 +1284,7 @@ int mtk_pctrl_init(struct platform_device *pdev, pctl->chip->ngpio = pctl->devdata->npins; pctl->chip->label = dev_name(&pdev->dev); pctl->chip->dev = &pdev->dev; - pctl->chip->base = 0; + pctl->chip->base = -1; ret = gpiochip_add(pctl->chip); if (ret) { @@ -1294,6 +1300,9 @@ int mtk_pctrl_init(struct platform_device *pdev, goto chip_error; } + if (of_find_property(np, "interrupt-controller", NULL)) + return 0; + /* Get EINT register base from dts. */ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); if (!res) { diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.h b/drivers/pinctrl/mediatek/pinctrl-mtk-common.h index c703e7d..30213e5 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.h +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.h @@ -269,7 +269,8 @@ struct mtk_pinctrl { }; int mtk_pctrl_init(struct platform_device *pdev, - const struct mtk_pinctrl_devdata *data); + const struct mtk_pinctrl_devdata *data, + struct regmap *regmap); int mtk_pctrl_spec_pull_set_samereg(struct regmap *regmap, const struct mtk_pin_spec_pupd_set_samereg *pupd_infos, diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-mt6397.h b/drivers/pinctrl/mediatek/pinctrl-mtk-mt6397.h new file mode 100644 index 0000000..4eb98dd --- /dev/null +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-mt6397.h @@ -0,0 +1,424 @@ +#ifndef __PINCTRL_MTK_MT6397_H +#define __PINCTRL_MTK_MT6397_H + +#include +#include "pinctrl-mtk-common.h" + +static const struct mtk_desc_pin mtk_pins_mt6397[] = { + MTK_PIN( + PINCTRL_PIN(0, "INT"), + "N2", "mt6397", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + MTK_FUNCTION(0, "GPIO0"), + MTK_FUNCTION(1, "INT") + ), + MTK_PIN( + PINCTRL_PIN(1, "SRCVOLTEN"), + "M4", "mt6397", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + MTK_FUNCTION(0, "GPIO1"), + MTK_FUNCTION(1, "SRCVOLTEN"), + MTK_FUNCTION(6, "TEST_CK1") + ), + MTK_PIN( + PINCTRL_PIN(2, "SRCLKEN_PERI"), + "M2", "mt6397", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + MTK_FUNCTION(0, "GPIO2"), + MTK_FUNCTION(1, "SRCLKEN_PERI"), + MTK_FUNCTION(6, "TEST_CK2") + ), + MTK_PIN( + PINCTRL_PIN(3, "RTC_32K1V8"), + "K3", "mt6397", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + MTK_FUNCTION(0, "GPIO3"), + MTK_FUNCTION(1, "RTC_32K1V8"), + MTK_FUNCTION(6, "TEST_CK3") + ), + MTK_PIN( + PINCTRL_PIN(4, "WRAP_EVENT"), + "J2", "mt6397", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + MTK_FUNCTION(0, "GPIO4"), + MTK_FUNCTION(1, "WRAP_EVENT") + ), + MTK_PIN( + PINCTRL_PIN(5, "SPI_CLK"), + "L4", "mt6397", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + MTK_FUNCTION(0, "GPIO5"), + MTK_FUNCTION(1, "SPI_CLK") + ), + MTK_PIN( + PINCTRL_PIN(6, "SPI_CSN"), + "J3", "mt6397", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + MTK_FUNCTION(0, "GPIO6"), + MTK_FUNCTION(1, "SPI_CSN") + ), + MTK_PIN( + PINCTRL_PIN(7, "SPI_MOSI"), + "J1", "mt6397", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + MTK_FUNCTION(0, "GPIO7"), + MTK_FUNCTION(1, "SPI_MOSI") + ), + MTK_PIN( + PINCTRL_PIN(8, "SPI_MISO"), + "L3", "mt6397", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + MTK_FUNCTION(0, "GPIO8"), + MTK_FUNCTION(1, "SPI_MISO") + ), + MTK_PIN( + PINCTRL_PIN(9, "AUD_CLK_MOSI"), + "H2", "mt6397", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + MTK_FUNCTION(0, "GPIO9"), + MTK_FUNCTION(1, "AUD_CLK"), + MTK_FUNCTION(6, "TEST_IN0"), + MTK_FUNCTION(7, "TEST_OUT0") + ), + MTK_PIN( + PINCTRL_PIN(10, "AUD_DAT_MISO"), + "H3", "mt6397", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + MTK_FUNCTION(0, "GPIO10"), + MTK_FUNCTION(1, "AUD_MISO"), + MTK_FUNCTION(6, "TEST_IN1"), + MTK_FUNCTION(7, "TEST_OUT1") + ), + MTK_PIN( + PINCTRL_PIN(11, "AUD_DAT_MOSI"), + "H1", "mt6397", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + MTK_FUNCTION(0, "GPIO11"), + MTK_FUNCTION(1, "AUD_MOSI"), + MTK_FUNCTION(6, "TEST_IN2"), + MTK_FUNCTION(7, "TEST_OUT2") + ), + MTK_PIN( + PINCTRL_PIN(12, "COL0"), + "F3", "mt6397", + MTK_EINT_FUNCTION(2, 10), + MTK_FUNCTION(0, "GPIO12"), + MTK_FUNCTION(1, "COL0_USBDL"), + MTK_FUNCTION(2, "EINT10_1X"), + MTK_FUNCTION(3, "PWM1_3X"), + MTK_FUNCTION(6, "TEST_IN3"), + MTK_FUNCTION(7, "TEST_OUT3") + ), + MTK_PIN( + PINCTRL_PIN(13, "COL1"), + "G8", "mt6397", + MTK_EINT_FUNCTION(2, 11), + MTK_FUNCTION(0, "GPIO13"), + MTK_FUNCTION(1, "COL1"), + MTK_FUNCTION(2, "EINT11_1X"), + MTK_FUNCTION(3, "SCL0_2X"), + MTK_FUNCTION(6, "TEST_IN4"), + MTK_FUNCTION(7, "TEST_OUT4") + ), + MTK_PIN( + PINCTRL_PIN(14, "COL2"), + "H4", "mt6397", + MTK_EINT_FUNCTION(2, 12), + MTK_FUNCTION(0, "GPIO14"), + MTK_FUNCTION(1, "COL2"), + MTK_FUNCTION(2, "EINT12_1X"), + MTK_FUNCTION(3, "SDA0_2X"), + MTK_FUNCTION(6, "TEST_IN5"), + MTK_FUNCTION(7, "TEST_OUT5") + ), + MTK_PIN( + PINCTRL_PIN(15, "COL3"), + "G2", "mt6397", + MTK_EINT_FUNCTION(2, 13), + MTK_FUNCTION(0, "GPIO15"), + MTK_FUNCTION(1, "COL3"), + MTK_FUNCTION(2, "EINT13_1X"), + MTK_FUNCTION(3, "SCL1_2X"), + MTK_FUNCTION(6, "TEST_IN6"), + MTK_FUNCTION(7, "TEST_OUT6") + ), + MTK_PIN( + PINCTRL_PIN(16, "COL4"), + "F2", "mt6397", + MTK_EINT_FUNCTION(2, 14), + MTK_FUNCTION(0, "GPIO16"), + MTK_FUNCTION(1, "COL4"), + MTK_FUNCTION(2, "EINT14_1X"), + MTK_FUNCTION(3, "SDA1_2X"), + MTK_FUNCTION(6, "TEST_IN7"), + MTK_FUNCTION(7, "TEST_OUT7") + ), + MTK_PIN( + PINCTRL_PIN(17, "COL5"), + "G7", "mt6397", + MTK_EINT_FUNCTION(2, 15), + MTK_FUNCTION(0, "GPIO17"), + MTK_FUNCTION(1, "COL5"), + MTK_FUNCTION(2, "EINT15_1X"), + MTK_FUNCTION(3, "SCL2_2X"), + MTK_FUNCTION(6, "TEST_IN8"), + MTK_FUNCTION(7, "TEST_OUT8") + ), + MTK_PIN( + PINCTRL_PIN(18, "COL6"), + "J6", "mt6397", + MTK_EINT_FUNCTION(2, 16), + MTK_FUNCTION(0, "GPIO18"), + MTK_FUNCTION(1, "COL6"), + MTK_FUNCTION(2, "EINT16_1X"), + MTK_FUNCTION(3, "SDA2_2X"), + MTK_FUNCTION(4, "GPIO32K_0"), + MTK_FUNCTION(5, "GPIO26M_0"), + MTK_FUNCTION(6, "TEST_IN9"), + MTK_FUNCTION(7, "TEST_OUT9") + ), + MTK_PIN( + PINCTRL_PIN(19, "COL7"), + "J5", "mt6397", + MTK_EINT_FUNCTION(2, 17), + MTK_FUNCTION(0, "GPIO19"), + MTK_FUNCTION(1, "COL7"), + MTK_FUNCTION(2, "EINT17_1X"), + MTK_FUNCTION(3, "PWM2_3X"), + MTK_FUNCTION(4, "GPIO32K_1"), + MTK_FUNCTION(5, "GPIO26M_1"), + MTK_FUNCTION(6, "TEST_IN10"), + MTK_FUNCTION(7, "TEST_OUT10") + ), + MTK_PIN( + PINCTRL_PIN(20, "ROW0"), + "L7", "mt6397", + MTK_EINT_FUNCTION(2, 18), + MTK_FUNCTION(0, "GPIO20"), + MTK_FUNCTION(1, "ROW0"), + MTK_FUNCTION(2, "EINT18_1X"), + MTK_FUNCTION(3, "SCL0_3X"), + MTK_FUNCTION(6, "TEST_IN11"), + MTK_FUNCTION(7, "TEST_OUT11") + ), + MTK_PIN( + PINCTRL_PIN(21, "ROW1"), + "P1", "mt6397", + MTK_EINT_FUNCTION(2, 19), + MTK_FUNCTION(0, "GPIO21"), + MTK_FUNCTION(1, "ROW1"), + MTK_FUNCTION(2, "EINT19_1X"), + MTK_FUNCTION(3, "SDA0_3X"), + MTK_FUNCTION(4, "AUD_TSTCK"), + MTK_FUNCTION(6, "TEST_IN12"), + MTK_FUNCTION(7, "TEST_OUT12") + ), + MTK_PIN( + PINCTRL_PIN(22, "ROW2"), + "J8", "mt6397", + MTK_EINT_FUNCTION(2, 20), + MTK_FUNCTION(0, "GPIO22"), + MTK_FUNCTION(1, "ROW2"), + MTK_FUNCTION(2, "EINT20_1X"), + MTK_FUNCTION(3, "SCL1_3X"), + MTK_FUNCTION(6, "TEST_IN13"), + MTK_FUNCTION(7, "TEST_OUT13") + ), + MTK_PIN( + PINCTRL_PIN(23, "ROW3"), + "J7", "mt6397", + MTK_EINT_FUNCTION(2, 21), + MTK_FUNCTION(0, "GPIO23"), + MTK_FUNCTION(1, "ROW3"), + MTK_FUNCTION(2, "EINT21_1X"), + MTK_FUNCTION(3, "SDA1_3X"), + MTK_FUNCTION(6, "TEST_IN14"), + MTK_FUNCTION(7, "TEST_OUT14") + ), + MTK_PIN( + PINCTRL_PIN(24, "ROW4"), + "L5", "mt6397", + MTK_EINT_FUNCTION(2, 22), + MTK_FUNCTION(0, "GPIO24"), + MTK_FUNCTION(1, "ROW4"), + MTK_FUNCTION(2, "EINT22_1X"), + MTK_FUNCTION(3, "SCL2_3X"), + MTK_FUNCTION(6, "TEST_IN15"), + MTK_FUNCTION(7, "TEST_OUT15") + ), + MTK_PIN( + PINCTRL_PIN(25, "ROW5"), + "N6", "mt6397", + MTK_EINT_FUNCTION(2, 23), + MTK_FUNCTION(0, "GPIO25"), + MTK_FUNCTION(1, "ROW5"), + MTK_FUNCTION(2, "EINT23_1X"), + MTK_FUNCTION(3, "SDA2_3X"), + MTK_FUNCTION(6, "TEST_IN16"), + MTK_FUNCTION(7, "TEST_OUT16") + ), + MTK_PIN( + PINCTRL_PIN(26, "ROW6"), + "L6", "mt6397", + MTK_EINT_FUNCTION(2, 24), + MTK_FUNCTION(0, "GPIO26"), + MTK_FUNCTION(1, "ROW6"), + MTK_FUNCTION(2, "EINT24_1X"), + MTK_FUNCTION(3, "PWM3_3X"), + MTK_FUNCTION(4, "GPIO32K_2"), + MTK_FUNCTION(5, "GPIO26M_2"), + MTK_FUNCTION(6, "TEST_IN17"), + MTK_FUNCTION(7, "TEST_OUT17") + ), + MTK_PIN( + PINCTRL_PIN(27, "ROW7"), + "P2", "mt6397", + MTK_EINT_FUNCTION(2, 3), + MTK_FUNCTION(0, "GPIO27"), + MTK_FUNCTION(1, "ROW7"), + MTK_FUNCTION(2, "EINT3_1X"), + MTK_FUNCTION(3, "CBUS"), + MTK_FUNCTION(4, "GPIO32K_3"), + MTK_FUNCTION(5, "GPIO26M_3"), + MTK_FUNCTION(6, "TEST_IN18"), + MTK_FUNCTION(7, "TEST_OUT18") + ), + MTK_PIN( + PINCTRL_PIN(28, "PWM1(VMSEL1)"), + "J4", "mt6397", + MTK_EINT_FUNCTION(2, 4), + MTK_FUNCTION(0, "GPIO28"), + MTK_FUNCTION(1, "PWM1"), + MTK_FUNCTION(2, "EINT4_1X"), + MTK_FUNCTION(4, "GPIO32K_4"), + MTK_FUNCTION(5, "GPIO26M_4"), + MTK_FUNCTION(6, "TEST_IN19"), + MTK_FUNCTION(7, "TEST_OUT19") + ), + MTK_PIN( + PINCTRL_PIN(29, "PWM2(VMSEL2)"), + "N5", "mt6397", + MTK_EINT_FUNCTION(2, 5), + MTK_FUNCTION(0, "GPIO29"), + MTK_FUNCTION(1, "PWM2"), + MTK_FUNCTION(2, "EINT5_1X"), + MTK_FUNCTION(4, "GPIO32K_5"), + MTK_FUNCTION(5, "GPIO26M_5"), + MTK_FUNCTION(6, "TEST_IN20"), + MTK_FUNCTION(7, "TEST_OUT20") + ), + MTK_PIN( + PINCTRL_PIN(30, "PWM3(PWM)"), + "R3", "mt6397", + MTK_EINT_FUNCTION(2, 6), + MTK_FUNCTION(0, "GPIO30"), + MTK_FUNCTION(1, "PWM3"), + MTK_FUNCTION(2, "EINT6_1X"), + MTK_FUNCTION(3, "COL0"), + MTK_FUNCTION(4, "GPIO32K_6"), + MTK_FUNCTION(5, "GPIO26M_6"), + MTK_FUNCTION(6, "TEST_IN21"), + MTK_FUNCTION(7, "TEST_OUT21") + ), + MTK_PIN( + PINCTRL_PIN(31, "SCL0"), + "N1", "mt6397", + MTK_EINT_FUNCTION(2, 7), + MTK_FUNCTION(0, "GPIO31"), + MTK_FUNCTION(1, "SCL0"), + MTK_FUNCTION(2, "EINT7_1X"), + MTK_FUNCTION(3, "PWM1_2X"), + MTK_FUNCTION(6, "TEST_IN22"), + MTK_FUNCTION(7, "TEST_OUT22") + ), + MTK_PIN( + PINCTRL_PIN(32, "SDA0"), + "N3", "mt6397", + MTK_EINT_FUNCTION(2, 8), + MTK_FUNCTION(0, "GPIO32"), + MTK_FUNCTION(1, "SDA0"), + MTK_FUNCTION(2, "EINT8_1X"), + MTK_FUNCTION(6, "TEST_IN23"), + MTK_FUNCTION(7, "TEST_OUT23") + ), + MTK_PIN( + PINCTRL_PIN(33, "SCL1"), + "T1", "mt6397", + MTK_EINT_FUNCTION(2, 9), + MTK_FUNCTION(0, "GPIO33"), + MTK_FUNCTION(1, "SCL1"), + MTK_FUNCTION(2, "EINT9_1X"), + MTK_FUNCTION(3, "PWM2_2X"), + MTK_FUNCTION(6, "TEST_IN24"), + MTK_FUNCTION(7, "TEST_OUT24") + ), + MTK_PIN( + PINCTRL_PIN(34, "SDA1"), + "T2", "mt6397", + MTK_EINT_FUNCTION(2, 0), + MTK_FUNCTION(0, "GPIO34"), + MTK_FUNCTION(1, "SDA1"), + MTK_FUNCTION(2, "EINT0_1X"), + MTK_FUNCTION(6, "TEST_IN25"), + MTK_FUNCTION(7, "TEST_OUT25") + ), + MTK_PIN( + PINCTRL_PIN(35, "SCL2"), + "T3", "mt6397", + MTK_EINT_FUNCTION(2, 1), + MTK_FUNCTION(0, "GPIO35"), + MTK_FUNCTION(1, "SCL2"), + MTK_FUNCTION(2, "EINT1_1X"), + MTK_FUNCTION(3, "PWM3_2X"), + MTK_FUNCTION(6, "TEST_IN26"), + MTK_FUNCTION(7, "TEST_OUT26") + ), + MTK_PIN( + PINCTRL_PIN(36, "SDA2"), + "U2", "mt6397", + MTK_EINT_FUNCTION(2, 2), + MTK_FUNCTION(0, "GPIO36"), + MTK_FUNCTION(1, "SDA2"), + MTK_FUNCTION(2, "EINT2_1X"), + MTK_FUNCTION(6, "TEST_IN27"), + MTK_FUNCTION(7, "TEST_OUT27") + ), + MTK_PIN( + PINCTRL_PIN(37, "HDMISD"), + "H6", "mt6397", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + MTK_FUNCTION(0, "GPIO37"), + MTK_FUNCTION(1, "HDMISD"), + MTK_FUNCTION(6, "TEST_IN28"), + MTK_FUNCTION(7, "TEST_OUT28") + ), + MTK_PIN( + PINCTRL_PIN(38, "HDMISCK"), + "H5", "mt6397", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + MTK_FUNCTION(0, "GPIO38"), + MTK_FUNCTION(1, "HDMISCK"), + MTK_FUNCTION(6, "TEST_IN29"), + MTK_FUNCTION(7, "TEST_OUT29") + ), + MTK_PIN( + PINCTRL_PIN(39, "HTPLG"), + "H7", "mt6397", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + MTK_FUNCTION(0, "GPIO39"), + MTK_FUNCTION(1, "HTPLG"), + MTK_FUNCTION(6, "TEST_IN30"), + MTK_FUNCTION(7, "TEST_OUT30") + ), + MTK_PIN( + PINCTRL_PIN(40, "CEC"), + "J9", "mt6397", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + MTK_FUNCTION(0, "GPIO40"), + MTK_FUNCTION(1, "CEC"), + MTK_FUNCTION(6, "TEST_IN31"), + MTK_FUNCTION(7, "TEST_OUT31") + ), +}; + +#endif /* __PINCTRL_MTK_MT6397_H */ -- cgit v0.10.2 From 6acdee8c1325ce3b02006f7ed6047f42273c9d44 Mon Sep 17 00:00:00 2001 From: Yingjoe Chen Date: Mon, 18 May 2015 20:01:32 -0700 Subject: pinctrl: mediatek: add pinctrl/GPIO/EINT driver for mt8127 MT8127 pinctrl/eint are similar to mt8135 and mt8173, add support for mt8127 using mediatek common pinctrl driver. Signed-off-by: Yingjoe Chen Signed-off-by: Hongzhou Yang Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig index ddae479..0bc84fb 100644 --- a/drivers/pinctrl/mediatek/Kconfig +++ b/drivers/pinctrl/mediatek/Kconfig @@ -15,6 +15,12 @@ config PINCTRL_MT8135 default MACH_MT8135 select PINCTRL_MTK_COMMON +config PINCTRL_MT8127 + bool "Mediatek MT8127 pin control" if COMPILE_TEST && !MACH_MT8127 + depends on OF + default MACH_MT8127 + select PINCTRL_MTK_COMMON + # For ARMv8 SoCs config PINCTRL_MT8173 bool "Mediatek MT8173 pin control" diff --git a/drivers/pinctrl/mediatek/Makefile b/drivers/pinctrl/mediatek/Makefile index ad0180c..eb923d6 100644 --- a/drivers/pinctrl/mediatek/Makefile +++ b/drivers/pinctrl/mediatek/Makefile @@ -3,5 +3,6 @@ obj-$(CONFIG_PINCTRL_MTK_COMMON) += pinctrl-mtk-common.o # SoC Drivers obj-$(CONFIG_PINCTRL_MT8135) += pinctrl-mt8135.o +obj-$(CONFIG_PINCTRL_MT8127) += pinctrl-mt8127.o obj-$(CONFIG_PINCTRL_MT8173) += pinctrl-mt8173.o obj-$(CONFIG_PINCTRL_MT6397) += pinctrl-mt6397.o diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8127.c b/drivers/pinctrl/mediatek/pinctrl-mt8127.c new file mode 100644 index 0000000..6a26cfa --- /dev/null +++ b/drivers/pinctrl/mediatek/pinctrl-mt8127.c @@ -0,0 +1,359 @@ +/* + * Copyright (c) 2015 MediaTek Inc. + * Author: Hongzhou.Yang + * Yingjoe Chen + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "pinctrl-mtk-common.h" +#include "pinctrl-mtk-mt8127.h" + +static const struct mtk_drv_group_desc mt8127_drv_grp[] = { + /* 0E4E8SR 4/8/12/16 */ + MTK_DRV_GRP(4, 16, 1, 2, 4), + /* 0E2E4SR 2/4/6/8 */ + MTK_DRV_GRP(2, 8, 1, 2, 2), + /* E8E4E2 2/4/6/8/10/12/14/16 */ + MTK_DRV_GRP(2, 16, 0, 2, 2) +}; + +static const struct mtk_pin_drv_grp mt8127_pin_drv[] = { + MTK_PIN_DRV_GRP(0, 0xb00, 0, 1), + MTK_PIN_DRV_GRP(1, 0xb00, 0, 1), + MTK_PIN_DRV_GRP(2, 0xb00, 0, 1), + MTK_PIN_DRV_GRP(3, 0xb00, 0, 1), + MTK_PIN_DRV_GRP(4, 0xb00, 0, 1), + MTK_PIN_DRV_GRP(5, 0xb00, 0, 1), + MTK_PIN_DRV_GRP(6, 0xb00, 0, 1), + MTK_PIN_DRV_GRP(7, 0xb00, 12, 1), + MTK_PIN_DRV_GRP(8, 0xb00, 12, 1), + MTK_PIN_DRV_GRP(9, 0xb00, 12, 1), + MTK_PIN_DRV_GRP(10, 0xb00, 8, 1), + MTK_PIN_DRV_GRP(11, 0xb00, 8, 1), + MTK_PIN_DRV_GRP(12, 0xb00, 8, 1), + MTK_PIN_DRV_GRP(13, 0xb00, 8, 1), + MTK_PIN_DRV_GRP(14, 0xb10, 4, 0), + MTK_PIN_DRV_GRP(15, 0xb10, 4, 0), + MTK_PIN_DRV_GRP(16, 0xb10, 4, 0), + MTK_PIN_DRV_GRP(17, 0xb10, 4, 0), + MTK_PIN_DRV_GRP(18, 0xb10, 8, 0), + MTK_PIN_DRV_GRP(19, 0xb10, 8, 0), + MTK_PIN_DRV_GRP(20, 0xb10, 8, 0), + MTK_PIN_DRV_GRP(21, 0xb10, 8, 0), + MTK_PIN_DRV_GRP(22, 0xb20, 0, 0), + MTK_PIN_DRV_GRP(23, 0xb20, 0, 0), + MTK_PIN_DRV_GRP(24, 0xb20, 0, 0), + MTK_PIN_DRV_GRP(25, 0xb20, 0, 0), + MTK_PIN_DRV_GRP(26, 0xb20, 0, 0), + MTK_PIN_DRV_GRP(27, 0xb20, 4, 0), + MTK_PIN_DRV_GRP(28, 0xb20, 4, 0), + MTK_PIN_DRV_GRP(29, 0xb20, 4, 0), + MTK_PIN_DRV_GRP(30, 0xb20, 4, 0), + MTK_PIN_DRV_GRP(31, 0xb20, 4, 0), + MTK_PIN_DRV_GRP(32, 0xb20, 4, 0), + MTK_PIN_DRV_GRP(33, 0xb30, 4, 1), + MTK_PIN_DRV_GRP(34, 0xb30, 8, 1), + MTK_PIN_DRV_GRP(35, 0xb30, 8, 1), + MTK_PIN_DRV_GRP(36, 0xb30, 8, 1), + MTK_PIN_DRV_GRP(37, 0xb30, 8, 1), + MTK_PIN_DRV_GRP(38, 0xb30, 8, 1), + MTK_PIN_DRV_GRP(39, 0xb30, 12, 1), + MTK_PIN_DRV_GRP(40, 0xb30, 12, 1), + MTK_PIN_DRV_GRP(41, 0xb30, 12, 1), + MTK_PIN_DRV_GRP(42, 0xb30, 12, 1), + MTK_PIN_DRV_GRP(43, 0xb40, 12, 0), + MTK_PIN_DRV_GRP(44, 0xb40, 12, 0), + MTK_PIN_DRV_GRP(45, 0xb40, 12, 0), + MTK_PIN_DRV_GRP(46, 0xb50, 0, 2), + MTK_PIN_DRV_GRP(47, 0xb50, 0, 2), + MTK_PIN_DRV_GRP(48, 0xb50, 0, 2), + MTK_PIN_DRV_GRP(49, 0xb50, 0, 2), + MTK_PIN_DRV_GRP(50, 0xb70, 0, 1), + MTK_PIN_DRV_GRP(51, 0xb70, 0, 1), + MTK_PIN_DRV_GRP(52, 0xb70, 0, 1), + MTK_PIN_DRV_GRP(53, 0xb50, 12, 1), + MTK_PIN_DRV_GRP(54, 0xb50, 12, 1), + MTK_PIN_DRV_GRP(55, 0xb50, 12, 1), + MTK_PIN_DRV_GRP(56, 0xb50, 12, 1), + MTK_PIN_DRV_GRP(59, 0xb40, 4, 1), + MTK_PIN_DRV_GRP(60, 0xb40, 0, 1), + MTK_PIN_DRV_GRP(61, 0xb40, 0, 1), + MTK_PIN_DRV_GRP(62, 0xb40, 0, 1), + MTK_PIN_DRV_GRP(63, 0xb40, 4, 1), + MTK_PIN_DRV_GRP(64, 0xb40, 4, 1), + MTK_PIN_DRV_GRP(65, 0xb40, 4, 1), + MTK_PIN_DRV_GRP(66, 0xb40, 8, 1), + MTK_PIN_DRV_GRP(67, 0xb40, 8, 1), + MTK_PIN_DRV_GRP(68, 0xb40, 8, 1), + MTK_PIN_DRV_GRP(69, 0xb40, 8, 1), + MTK_PIN_DRV_GRP(70, 0xb40, 8, 1), + MTK_PIN_DRV_GRP(71, 0xb40, 8, 1), + MTK_PIN_DRV_GRP(72, 0xb50, 4, 1), + MTK_PIN_DRV_GRP(73, 0xb50, 4, 1), + MTK_PIN_DRV_GRP(74, 0xb50, 4, 1), + MTK_PIN_DRV_GRP(79, 0xb50, 8, 1), + MTK_PIN_DRV_GRP(80, 0xb50, 8, 1), + MTK_PIN_DRV_GRP(81, 0xb50, 8, 1), + MTK_PIN_DRV_GRP(82, 0xb50, 8, 1), + MTK_PIN_DRV_GRP(83, 0xb50, 8, 1), + MTK_PIN_DRV_GRP(84, 0xb50, 8, 1), + MTK_PIN_DRV_GRP(85, 0xce0, 0, 2), + MTK_PIN_DRV_GRP(86, 0xcd0, 0, 2), + MTK_PIN_DRV_GRP(87, 0xcf0, 0, 2), + MTK_PIN_DRV_GRP(88, 0xcf0, 0, 2), + MTK_PIN_DRV_GRP(89, 0xcf0, 0, 2), + MTK_PIN_DRV_GRP(90, 0xcf0, 0, 2), + MTK_PIN_DRV_GRP(117, 0xb60, 12, 1), + MTK_PIN_DRV_GRP(118, 0xb60, 12, 1), + MTK_PIN_DRV_GRP(119, 0xb60, 12, 1), + MTK_PIN_DRV_GRP(120, 0xb60, 12, 1), + MTK_PIN_DRV_GRP(121, 0xc80, 0, 2), + MTK_PIN_DRV_GRP(122, 0xc70, 0, 2), + MTK_PIN_DRV_GRP(123, 0xc90, 0, 2), + MTK_PIN_DRV_GRP(124, 0xc90, 0, 2), + MTK_PIN_DRV_GRP(125, 0xc90, 0, 2), + MTK_PIN_DRV_GRP(126, 0xc90, 0, 2), + MTK_PIN_DRV_GRP(127, 0xc20, 0, 2), + MTK_PIN_DRV_GRP(128, 0xc20, 0, 2), + MTK_PIN_DRV_GRP(129, 0xc20, 0, 2), + MTK_PIN_DRV_GRP(130, 0xc20, 0, 2), + MTK_PIN_DRV_GRP(131, 0xc20, 0, 2), + MTK_PIN_DRV_GRP(132, 0xc10, 0, 2), + MTK_PIN_DRV_GRP(133, 0xc00, 0, 2), + MTK_PIN_DRV_GRP(134, 0xc20, 0, 2), + MTK_PIN_DRV_GRP(135, 0xc20, 0, 2), + MTK_PIN_DRV_GRP(136, 0xc20, 0, 2), + MTK_PIN_DRV_GRP(137, 0xc20, 0, 2), + MTK_PIN_DRV_GRP(142, 0xb50, 0, 2), +}; + +static const struct mtk_pin_spec_pupd_set_samereg mt8127_spec_pupd[] = { + MTK_PIN_PUPD_SPEC_SR(33, 0xd90, 2, 0, 1), /* KPROW0 */ + MTK_PIN_PUPD_SPEC_SR(34, 0xd90, 6, 4, 5), /* KPROW1 */ + MTK_PIN_PUPD_SPEC_SR(35, 0xd90, 10, 8, 9), /* KPROW2 */ + MTK_PIN_PUPD_SPEC_SR(36, 0xda0, 2, 0, 1), /* KPCOL0 */ + MTK_PIN_PUPD_SPEC_SR(37, 0xda0, 6, 4, 5), /* KPCOL1 */ + MTK_PIN_PUPD_SPEC_SR(38, 0xda0, 10, 8, 9), /* KPCOL2 */ + MTK_PIN_PUPD_SPEC_SR(46, 0xdb0, 2, 0, 1), /* EINT14 */ + MTK_PIN_PUPD_SPEC_SR(47, 0xdb0, 6, 4, 5), /* EINT15 */ + MTK_PIN_PUPD_SPEC_SR(48, 0xdb0, 10, 8, 9), /* EINT16 */ + MTK_PIN_PUPD_SPEC_SR(49, 0xdb0, 14, 12, 13), /* EINT17 */ + MTK_PIN_PUPD_SPEC_SR(85, 0xce0, 8, 10, 9), /* MSDC2_CMD */ + MTK_PIN_PUPD_SPEC_SR(86, 0xcd0, 8, 10, 9), /* MSDC2_CLK */ + MTK_PIN_PUPD_SPEC_SR(87, 0xd00, 0, 2, 1), /* MSDC2_DAT0 */ + MTK_PIN_PUPD_SPEC_SR(88, 0xd00, 4, 6, 5), /* MSDC2_DAT1 */ + MTK_PIN_PUPD_SPEC_SR(89, 0xd00, 8, 10, 9), /* MSDC2_DAT2 */ + MTK_PIN_PUPD_SPEC_SR(90, 0xd00, 12, 14, 13), /* MSDC2_DAT3 */ + MTK_PIN_PUPD_SPEC_SR(121, 0xc80, 8, 10, 9), /* MSDC1_CMD */ + MTK_PIN_PUPD_SPEC_SR(122, 0xc70, 8, 10, 9), /* MSDC1_CLK */ + MTK_PIN_PUPD_SPEC_SR(123, 0xca0, 0, 2, 1), /* MSDC1_DAT0 */ + MTK_PIN_PUPD_SPEC_SR(124, 0xca0, 4, 6, 5), /* MSDC1_DAT1 */ + MTK_PIN_PUPD_SPEC_SR(125, 0xca0, 8, 10, 9), /* MSDC1_DAT2 */ + MTK_PIN_PUPD_SPEC_SR(126, 0xca0, 12, 14, 13), /* MSDC1_DAT3 */ + MTK_PIN_PUPD_SPEC_SR(127, 0xc40, 12, 14, 13), /* MSDC0_DAT7 */ + MTK_PIN_PUPD_SPEC_SR(128, 0xc40, 8, 10, 9), /* MSDC0_DAT6 */ + MTK_PIN_PUPD_SPEC_SR(129, 0xc40, 4, 6, 5), /* MSDC0_DAT5 */ + MTK_PIN_PUPD_SPEC_SR(130, 0xc40, 0, 2, 1), /* MSDC0_DAT4 */ + MTK_PIN_PUPD_SPEC_SR(131, 0xc50, 0, 2, 1), /* MSDC0_RSTB */ + MTK_PIN_PUPD_SPEC_SR(132, 0xc10, 8, 10, 9), /* MSDC0_CMD */ + MTK_PIN_PUPD_SPEC_SR(133, 0xc00, 8, 10, 9), /* MSDC0_CLK */ + MTK_PIN_PUPD_SPEC_SR(134, 0xc30, 12, 14, 13), /* MSDC0_DAT3 */ + MTK_PIN_PUPD_SPEC_SR(135, 0xc30, 8, 10, 9), /* MSDC0_DAT2 */ + MTK_PIN_PUPD_SPEC_SR(136, 0xc30, 4, 6, 5), /* MSDC0_DAT1 */ + MTK_PIN_PUPD_SPEC_SR(137, 0xc30, 0, 2, 1), /* MSDC0_DAT0 */ + MTK_PIN_PUPD_SPEC_SR(142, 0xdc0, 2, 0, 1), /* EINT21 */ +}; + +static int mt8127_spec_pull_set(struct regmap *regmap, unsigned int pin, + unsigned char align, bool isup, unsigned int r1r0) +{ + return mtk_pctrl_spec_pull_set_samereg(regmap, mt8127_spec_pupd, + ARRAY_SIZE(mt8127_spec_pupd), pin, align, isup, r1r0); +} + +static const struct mtk_pin_ies_smt_set mt8127_ies_set[] = { + MTK_PIN_IES_SMT_SPEC(0, 9, 0x900, 0), + MTK_PIN_IES_SMT_SPEC(10, 13, 0x900, 1), + MTK_PIN_IES_SMT_SPEC(14, 28, 0x900, 2), + MTK_PIN_IES_SMT_SPEC(29, 32, 0x900, 3), + MTK_PIN_IES_SMT_SPEC(33, 33, 0x910, 11), + MTK_PIN_IES_SMT_SPEC(34, 38, 0x900, 10), + MTK_PIN_IES_SMT_SPEC(39, 42, 0x900, 11), + MTK_PIN_IES_SMT_SPEC(43, 45, 0x900, 12), + MTK_PIN_IES_SMT_SPEC(46, 49, 0x900, 13), + MTK_PIN_IES_SMT_SPEC(50, 52, 0x910, 10), + MTK_PIN_IES_SMT_SPEC(53, 56, 0x900, 14), + MTK_PIN_IES_SMT_SPEC(57, 58, 0x910, 0), + MTK_PIN_IES_SMT_SPEC(59, 65, 0x910, 2), + MTK_PIN_IES_SMT_SPEC(66, 71, 0x910, 3), + MTK_PIN_IES_SMT_SPEC(72, 74, 0x910, 4), + MTK_PIN_IES_SMT_SPEC(75, 76, 0x900, 15), + MTK_PIN_IES_SMT_SPEC(77, 78, 0x910, 1), + MTK_PIN_IES_SMT_SPEC(79, 82, 0x910, 5), + MTK_PIN_IES_SMT_SPEC(83, 84, 0x910, 6), + MTK_PIN_IES_SMT_SPEC(117, 120, 0x910, 7), + MTK_PIN_IES_SMT_SPEC(121, 121, 0xc80, 4), + MTK_PIN_IES_SMT_SPEC(122, 122, 0xc70, 4), + MTK_PIN_IES_SMT_SPEC(123, 126, 0xc90, 4), + MTK_PIN_IES_SMT_SPEC(127, 131, 0xc20, 4), + MTK_PIN_IES_SMT_SPEC(132, 132, 0xc10, 4), + MTK_PIN_IES_SMT_SPEC(133, 133, 0xc00, 4), + MTK_PIN_IES_SMT_SPEC(134, 137, 0xc20, 4), + MTK_PIN_IES_SMT_SPEC(138, 141, 0x910, 9), + MTK_PIN_IES_SMT_SPEC(142, 142, 0x900, 13), +}; + +static const struct mtk_pin_ies_smt_set mt8127_smt_set[] = { + MTK_PIN_IES_SMT_SPEC(0, 9, 0x920, 0), + MTK_PIN_IES_SMT_SPEC(10, 13, 0x920, 1), + MTK_PIN_IES_SMT_SPEC(14, 28, 0x920, 2), + MTK_PIN_IES_SMT_SPEC(29, 32, 0x920, 3), + MTK_PIN_IES_SMT_SPEC(33, 33, 0x930, 11), + MTK_PIN_IES_SMT_SPEC(34, 38, 0x920, 10), + MTK_PIN_IES_SMT_SPEC(39, 42, 0x920, 11), + MTK_PIN_IES_SMT_SPEC(43, 45, 0x920, 12), + MTK_PIN_IES_SMT_SPEC(46, 49, 0x920, 13), + MTK_PIN_IES_SMT_SPEC(50, 52, 0x930, 10), + MTK_PIN_IES_SMT_SPEC(53, 56, 0x920, 14), + MTK_PIN_IES_SMT_SPEC(57, 58, 0x930, 0), + MTK_PIN_IES_SMT_SPEC(59, 65, 0x930, 2), + MTK_PIN_IES_SMT_SPEC(66, 71, 0x930, 3), + MTK_PIN_IES_SMT_SPEC(72, 74, 0x930, 4), + MTK_PIN_IES_SMT_SPEC(75, 76, 0x920, 15), + MTK_PIN_IES_SMT_SPEC(77, 78, 0x930, 1), + MTK_PIN_IES_SMT_SPEC(79, 82, 0x930, 5), + MTK_PIN_IES_SMT_SPEC(83, 84, 0x930, 6), + MTK_PIN_IES_SMT_SPEC(85, 85, 0xce0, 11), + MTK_PIN_IES_SMT_SPEC(86, 86, 0xcd0, 11), + MTK_PIN_IES_SMT_SPEC(87, 87, 0xd00, 3), + MTK_PIN_IES_SMT_SPEC(88, 88, 0xd00, 7), + MTK_PIN_IES_SMT_SPEC(89, 89, 0xd00, 11), + MTK_PIN_IES_SMT_SPEC(90, 90, 0xd00, 15), + MTK_PIN_IES_SMT_SPEC(117, 120, 0x930, 7), + MTK_PIN_IES_SMT_SPEC(121, 121, 0xc80, 11), + MTK_PIN_IES_SMT_SPEC(122, 122, 0xc70, 11), + MTK_PIN_IES_SMT_SPEC(123, 123, 0xca0, 3), + MTK_PIN_IES_SMT_SPEC(124, 124, 0xca0, 7), + MTK_PIN_IES_SMT_SPEC(125, 125, 0xca0, 11), + MTK_PIN_IES_SMT_SPEC(126, 126, 0xca0, 15), + MTK_PIN_IES_SMT_SPEC(127, 127, 0xc40, 15), + MTK_PIN_IES_SMT_SPEC(128, 128, 0xc40, 11), + MTK_PIN_IES_SMT_SPEC(129, 129, 0xc40, 7), + MTK_PIN_IES_SMT_SPEC(130, 130, 0xc40, 3), + MTK_PIN_IES_SMT_SPEC(131, 131, 0xc50, 3), + MTK_PIN_IES_SMT_SPEC(132, 132, 0xc10, 11), + MTK_PIN_IES_SMT_SPEC(133, 133, 0xc00, 11), + MTK_PIN_IES_SMT_SPEC(134, 134, 0xc30, 15), + MTK_PIN_IES_SMT_SPEC(135, 135, 0xc30, 11), + MTK_PIN_IES_SMT_SPEC(136, 136, 0xc30, 7), + MTK_PIN_IES_SMT_SPEC(137, 137, 0xc30, 3), + MTK_PIN_IES_SMT_SPEC(138, 141, 0x930, 9), + MTK_PIN_IES_SMT_SPEC(142, 142, 0x920, 13), +}; + +static int mt8127_ies_smt_set(struct regmap *regmap, unsigned int pin, + unsigned char align, int value, enum pin_config_param arg) +{ + if (arg == PIN_CONFIG_INPUT_ENABLE) + return mtk_pconf_spec_set_ies_smt_range(regmap, mt8127_ies_set, + ARRAY_SIZE(mt8127_ies_set), pin, align, value); + else if (arg == PIN_CONFIG_INPUT_SCHMITT_ENABLE) + return mtk_pconf_spec_set_ies_smt_range(regmap, mt8127_smt_set, + ARRAY_SIZE(mt8127_smt_set), pin, align, value); + return -EINVAL; +} + + +static const struct mtk_pinctrl_devdata mt8127_pinctrl_data = { + .pins = mtk_pins_mt8127, + .npins = ARRAY_SIZE(mtk_pins_mt8127), + .grp_desc = mt8127_drv_grp, + .n_grp_cls = ARRAY_SIZE(mt8127_drv_grp), + .pin_drv_grp = mt8127_pin_drv, + .n_pin_drv_grps = ARRAY_SIZE(mt8127_pin_drv), + .spec_pull_set = mt8127_spec_pull_set, + .spec_ies_smt_set = mt8127_ies_smt_set, + .dir_offset = 0x0000, + .pullen_offset = 0x0100, + .pullsel_offset = 0x0200, + .dout_offset = 0x0400, + .din_offset = 0x0500, + .pinmux_offset = 0x0600, + .type1_start = 143, + .type1_end = 143, + .port_shf = 4, + .port_mask = 0xf, + .port_align = 4, + .eint_offsets = { + .name = "mt8127_eint", + .stat = 0x000, + .ack = 0x040, + .mask = 0x080, + .mask_set = 0x0c0, + .mask_clr = 0x100, + .sens = 0x140, + .sens_set = 0x180, + .sens_clr = 0x1c0, + .soft = 0x200, + .soft_set = 0x240, + .soft_clr = 0x280, + .pol = 0x300, + .pol_set = 0x340, + .pol_clr = 0x380, + .dom_en = 0x400, + .dbnc_ctrl = 0x500, + .dbnc_set = 0x600, + .dbnc_clr = 0x700, + .port_mask = 7, + .ports = 6, + }, + .ap_num = 143, + .db_cnt = 16, +}; + +static int mt8127_pinctrl_probe(struct platform_device *pdev) +{ + return mtk_pctrl_init(pdev, &mt8127_pinctrl_data, NULL); +} + +static const struct of_device_id mt8127_pctrl_match[] = { + { .compatible = "mediatek,mt8127-pinctrl", }, + { } +}; +MODULE_DEVICE_TABLE(of, mt8127_pctrl_match); + +static struct platform_driver mtk_pinctrl_driver = { + .probe = mt8127_pinctrl_probe, + .driver = { + .name = "mediatek-mt8127-pinctrl", + .owner = THIS_MODULE, + .of_match_table = mt8127_pctrl_match, + }, +}; + +static int __init mtk_pinctrl_init(void) +{ + return platform_driver_register(&mtk_pinctrl_driver); +} + +module_init(mtk_pinctrl_init); + +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("MediaTek MT8127 Pinctrl Driver"); +MODULE_AUTHOR("Yingjoe Chen "); diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-mt8127.h b/drivers/pinctrl/mediatek/pinctrl-mtk-mt8127.h new file mode 100644 index 0000000..212559c --- /dev/null +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-mt8127.h @@ -0,0 +1,1318 @@ +#ifndef __PINCTRL_MTK_MT8127_H +#define __PINCTRL_MTK_MT8127_H + +#include +#include "pinctrl-mtk-common.h" + +static const struct mtk_desc_pin mtk_pins_mt8127[] = { + MTK_PIN( + PINCTRL_PIN(0, "PWRAP_SPI0_MI"), + "P22", "mt8127", + MTK_EINT_FUNCTION(0, 22), + MTK_FUNCTION(0, "GPIO0"), + MTK_FUNCTION(1, "PWRAP_SPIDO"), + MTK_FUNCTION(2, "PWRAP_SPIDI") + ), + MTK_PIN( + PINCTRL_PIN(1, "PWRAP_SPI0_MO"), + "M22", "mt8127", + MTK_EINT_FUNCTION(0, 23), + MTK_FUNCTION(0, "GPIO1"), + MTK_FUNCTION(1, "PWRAP_SPIDI"), + MTK_FUNCTION(2, "PWRAP_SPIDO") + ), + MTK_PIN( + PINCTRL_PIN(2, "PWRAP_INT"), + "L23", "mt8127", + MTK_EINT_FUNCTION(0, 24), + MTK_FUNCTION(0, "GPIO2") + ), + MTK_PIN( + PINCTRL_PIN(3, "PWRAP_SPI0_CK"), + "N23", "mt8127", + MTK_EINT_FUNCTION(0, 25), + MTK_FUNCTION(0, "GPIO3"), + MTK_FUNCTION(1, "PWRAP_SPICK_I") + ), + MTK_PIN( + PINCTRL_PIN(4, "PWRAP_SPI0_CSN"), + "N22", "mt8127", + MTK_EINT_FUNCTION(0, 26), + MTK_FUNCTION(0, "GPIO4"), + MTK_FUNCTION(1, "PWRAP_SPICS_B_I") + ), + MTK_PIN( + PINCTRL_PIN(5, "PWRAP_SPI0_CK2"), + "L19", "mt8127", + MTK_EINT_FUNCTION(0, 27), + MTK_FUNCTION(0, "GPIO5"), + MTK_FUNCTION(1, "PWRAP_SPICK2_I"), + MTK_FUNCTION(2, "ANT_SEL1"), + MTK_FUNCTION(3, "VDEC_TEST_CK"), + MTK_FUNCTION(7, "DBG_MON_B[0]") + ), + MTK_PIN( + PINCTRL_PIN(6, "PWRAP_SPI0_CSN2"), + "M23", "mt8127", + MTK_EINT_FUNCTION(0, 28), + MTK_FUNCTION(0, "GPIO6"), + MTK_FUNCTION(1, "PWRAP_SPICS2_B_I"), + MTK_FUNCTION(2, "ANT_SEL0"), + MTK_FUNCTION(3, "MM_TEST_CK"), + MTK_FUNCTION(7, "DBG_MON_B[1]") + ), + MTK_PIN( + PINCTRL_PIN(7, "AUD_CLK_MOSI"), + "K23", "mt8127", + MTK_EINT_FUNCTION(0, 29), + MTK_FUNCTION(0, "GPIO7"), + MTK_FUNCTION(1, "AUD_CLK"), + MTK_FUNCTION(2, "ADC_CK") + ), + MTK_PIN( + PINCTRL_PIN(8, "AUD_DAT_MISO"), + "K24", "mt8127", + MTK_EINT_FUNCTION(0, 30), + MTK_FUNCTION(0, "GPIO8"), + MTK_FUNCTION(1, "AUD_MISO"), + MTK_FUNCTION(2, "ADC_DAT_IN"), + MTK_FUNCTION(3, "AUD_MOSI") + ), + MTK_PIN( + PINCTRL_PIN(9, "AUD_DAT_MOSI"), + "K22", "mt8127", + MTK_EINT_FUNCTION(0, 31), + MTK_FUNCTION(0, "GPIO9"), + MTK_FUNCTION(1, "AUD_MOSI"), + MTK_FUNCTION(2, "ADC_WS"), + MTK_FUNCTION(3, "AUD_MISO") + ), + MTK_PIN( + PINCTRL_PIN(10, "RTC32K_CK"), + "R21", "mt8127", + MTK_EINT_FUNCTION(0, 32), + MTK_FUNCTION(0, "GPIO10"), + MTK_FUNCTION(1, "RTC32K_CK") + ), + MTK_PIN( + PINCTRL_PIN(11, "WATCHDOG"), + "P24", "mt8127", + MTK_EINT_FUNCTION(0, 33), + MTK_FUNCTION(0, "GPIO11"), + MTK_FUNCTION(1, "WATCHDOG") + ), + MTK_PIN( + PINCTRL_PIN(12, "SRCLKENA"), + "R22", "mt8127", + MTK_EINT_FUNCTION(0, 34), + MTK_FUNCTION(0, "GPIO12"), + MTK_FUNCTION(1, "SRCLKENA") + ), + MTK_PIN( + PINCTRL_PIN(13, "SRCLKENAI"), + "P23", "mt8127", + MTK_EINT_FUNCTION(0, 35), + MTK_FUNCTION(0, "GPIO13"), + MTK_FUNCTION(1, "SRCLKENAI") + ), + MTK_PIN( + PINCTRL_PIN(14, "URXD2"), + "U19", "mt8127", + MTK_EINT_FUNCTION(0, 36), + MTK_FUNCTION(0, "GPIO14"), + MTK_FUNCTION(1, "URXD2"), + MTK_FUNCTION(2, "DPI_D5"), + MTK_FUNCTION(3, "UTXD2"), + MTK_FUNCTION(5, "SRCCLKENAI2"), + MTK_FUNCTION(6, "KROW4") + ), + MTK_PIN( + PINCTRL_PIN(15, "UTXD2"), + "U20", "mt8127", + MTK_EINT_FUNCTION(0, 37), + MTK_FUNCTION(0, "GPIO15"), + MTK_FUNCTION(1, "UTXD2"), + MTK_FUNCTION(2, "DPI_HSYNC"), + MTK_FUNCTION(3, "URXD2"), + MTK_FUNCTION(6, "KROW5") + ), + MTK_PIN( + PINCTRL_PIN(16, "URXD3"), + "U18", "mt8127", + MTK_EINT_FUNCTION(0, 38), + MTK_FUNCTION(0, "GPIO16"), + MTK_FUNCTION(1, "URXD3"), + MTK_FUNCTION(2, "DPI_DE"), + MTK_FUNCTION(3, "UTXD3"), + MTK_FUNCTION(4, "UCTS2"), + MTK_FUNCTION(5, "PWM3"), + MTK_FUNCTION(6, "KROW6") + ), + MTK_PIN( + PINCTRL_PIN(17, "UTXD3"), + "R18", "mt8127", + MTK_EINT_FUNCTION(0, 39), + MTK_FUNCTION(0, "GPIO17"), + MTK_FUNCTION(1, "UTXD3"), + MTK_FUNCTION(2, "DPI_VSYNC"), + MTK_FUNCTION(3, "URXD3"), + MTK_FUNCTION(4, "URTS2"), + MTK_FUNCTION(5, "PWM4"), + MTK_FUNCTION(6, "KROW7") + ), + MTK_PIN( + PINCTRL_PIN(18, "PCM_CLK"), + "U22", "mt8127", + MTK_EINT_FUNCTION(0, 40), + MTK_FUNCTION(0, "GPIO18"), + MTK_FUNCTION(1, "PCM_CLK0"), + MTK_FUNCTION(2, "DPI_D4"), + MTK_FUNCTION(3, "I2SIN1_BCK0"), + MTK_FUNCTION(4, "I2SOUT_BCK"), + MTK_FUNCTION(5, "CONN_DSP_JCK"), + MTK_FUNCTION(6, "IR"), + MTK_FUNCTION(7, "DBG_MON_A[0]") + ), + MTK_PIN( + PINCTRL_PIN(19, "PCM_SYNC"), + "U23", "mt8127", + MTK_EINT_FUNCTION(0, 41), + MTK_FUNCTION(0, "GPIO19"), + MTK_FUNCTION(1, "PCM_SYNC"), + MTK_FUNCTION(2, "DPI_D3"), + MTK_FUNCTION(3, "I2SIN1_LRCK"), + MTK_FUNCTION(4, "I2SOUT_LRCK"), + MTK_FUNCTION(5, "CONN_DSP_JINTP"), + MTK_FUNCTION(6, "EXT_COL"), + MTK_FUNCTION(7, "DBG_MON_A[1]") + ), + MTK_PIN( + PINCTRL_PIN(20, "PCM_RX"), + "V22", "mt8127", + MTK_EINT_FUNCTION(0, 42), + MTK_FUNCTION(0, "GPIO20"), + MTK_FUNCTION(1, "PCM_RX"), + MTK_FUNCTION(2, "DPI_D1"), + MTK_FUNCTION(3, "I2SIN1_DATA_IN"), + MTK_FUNCTION(4, "PCM_TX"), + MTK_FUNCTION(5, "CONN_DSP_JDI"), + MTK_FUNCTION(6, "EXT_MDIO"), + MTK_FUNCTION(7, "DBG_MON_A[2]") + ), + MTK_PIN( + PINCTRL_PIN(21, "PCM_TX"), + "U21", "mt8127", + MTK_EINT_FUNCTION(0, 43), + MTK_FUNCTION(0, "GPIO21"), + MTK_FUNCTION(1, "PCM_TX"), + MTK_FUNCTION(2, "DPI_D2"), + MTK_FUNCTION(3, "I2SOUT_DATA_OUT"), + MTK_FUNCTION(4, "PCM_RX"), + MTK_FUNCTION(5, "CONN_DSP_JMS"), + MTK_FUNCTION(6, "EXT_MDC"), + MTK_FUNCTION(7, "DBG_MON_A[3]") + ), + MTK_PIN( + PINCTRL_PIN(22, "EINT0"), + "AB19", "mt8127", + MTK_EINT_FUNCTION(0, 0), + MTK_FUNCTION(0, "GPIO22"), + MTK_FUNCTION(1, "PWM1"), + MTK_FUNCTION(2, "DPI_CK"), + MTK_FUNCTION(4, "EXT_TXD0"), + MTK_FUNCTION(5, "CONN_DSP_JDO"), + MTK_FUNCTION(7, "DBG_MON_A[4]") + ), + MTK_PIN( + PINCTRL_PIN(23, "EINT1"), + "AA21", "mt8127", + MTK_EINT_FUNCTION(0, 1), + MTK_FUNCTION(0, "GPIO23"), + MTK_FUNCTION(1, "PWM2"), + MTK_FUNCTION(2, "DPI_D12"), + MTK_FUNCTION(4, "EXT_TXD1"), + MTK_FUNCTION(5, "CONN_MCU_TDO"), + MTK_FUNCTION(7, "DBG_MON_A[5]") + ), + MTK_PIN( + PINCTRL_PIN(24, "EINT2"), + "AA19", "mt8127", + MTK_EINT_FUNCTION(0, 2), + MTK_FUNCTION(0, "GPIO24"), + MTK_FUNCTION(1, "CLKM0"), + MTK_FUNCTION(2, "DPI_D13"), + MTK_FUNCTION(4, "EXT_TXD2"), + MTK_FUNCTION(5, "CONN_MCU_DBGACK_N"), + MTK_FUNCTION(6, "KCOL4"), + MTK_FUNCTION(7, "DBG_MON_A[6]") + ), + MTK_PIN( + PINCTRL_PIN(25, "EINT3"), + "Y19", "mt8127", + MTK_EINT_FUNCTION(0, 3), + MTK_FUNCTION(0, "GPIO25"), + MTK_FUNCTION(1, "CLKM1"), + MTK_FUNCTION(2, "DPI_D14"), + MTK_FUNCTION(3, "SPI_MI"), + MTK_FUNCTION(4, "EXT_TXD3"), + MTK_FUNCTION(5, "CONN_MCU_DBGI_N"), + MTK_FUNCTION(6, "KCOL5"), + MTK_FUNCTION(7, "DBG_MON_A[7]") + ), + MTK_PIN( + PINCTRL_PIN(26, "EINT4"), + "V21", "mt8127", + MTK_EINT_FUNCTION(0, 4), + MTK_FUNCTION(0, "GPIO26"), + MTK_FUNCTION(1, "CLKM2"), + MTK_FUNCTION(2, "DPI_D15"), + MTK_FUNCTION(3, "SPI_MO"), + MTK_FUNCTION(4, "EXT_TXC"), + MTK_FUNCTION(5, "CONN_MCU_TCK0"), + MTK_FUNCTION(6, "CONN_MCU_AICE_JCKC"), + MTK_FUNCTION(7, "DBG_MON_A[8]") + ), + MTK_PIN( + PINCTRL_PIN(27, "EINT5"), + "AB22", "mt8127", + MTK_EINT_FUNCTION(0, 5), + MTK_FUNCTION(0, "GPIO27"), + MTK_FUNCTION(1, "UCTS2"), + MTK_FUNCTION(2, "DPI_D16"), + MTK_FUNCTION(3, "SPI_CS"), + MTK_FUNCTION(4, "EXT_RXER"), + MTK_FUNCTION(5, "CONN_MCU_TDI"), + MTK_FUNCTION(6, "KCOL6"), + MTK_FUNCTION(7, "DBG_MON_A[9]") + ), + MTK_PIN( + PINCTRL_PIN(28, "EINT6"), + "AA23", "mt8127", + MTK_EINT_FUNCTION(0, 6), + MTK_FUNCTION(0, "GPIO28"), + MTK_FUNCTION(1, "URTS2"), + MTK_FUNCTION(2, "DPI_D17"), + MTK_FUNCTION(3, "SPI_CK"), + MTK_FUNCTION(4, "EXT_RXC"), + MTK_FUNCTION(5, "CONN_MCU_TRST_B"), + MTK_FUNCTION(6, "KCOL7"), + MTK_FUNCTION(7, "DBG_MON_A[10]") + ), + MTK_PIN( + PINCTRL_PIN(29, "EINT7"), + "Y23", "mt8127", + MTK_EINT_FUNCTION(0, 7), + MTK_FUNCTION(0, "GPIO29"), + MTK_FUNCTION(1, "UCTS3"), + MTK_FUNCTION(2, "DPI_D6"), + MTK_FUNCTION(3, "SDA1"), + MTK_FUNCTION(4, "EXT_RXDV"), + MTK_FUNCTION(5, "CONN_MCU_TMS"), + MTK_FUNCTION(6, "CONN_MCU_AICE_JMSC"), + MTK_FUNCTION(7, "DBG_MON_A[11]") + ), + MTK_PIN( + PINCTRL_PIN(30, "EINT8"), + "Y24", "mt8127", + MTK_EINT_FUNCTION(0, 8), + MTK_FUNCTION(0, "GPIO30"), + MTK_FUNCTION(1, "URTS3"), + MTK_FUNCTION(2, "CLKM3"), + MTK_FUNCTION(3, "SCL1"), + MTK_FUNCTION(4, "EXT_RXD0"), + MTK_FUNCTION(5, "ANT_SEL0"), + MTK_FUNCTION(6, "DPI_D7"), + MTK_FUNCTION(7, "DBG_MON_B[2]") + ), + MTK_PIN( + PINCTRL_PIN(31, "EINT9"), + "W23", "mt8127", + MTK_EINT_FUNCTION(0, 9), + MTK_FUNCTION(0, "GPIO31"), + MTK_FUNCTION(1, "CLKM4"), + MTK_FUNCTION(2, "SDA2"), + MTK_FUNCTION(3, "EXT_FRAME_SYNC"), + MTK_FUNCTION(4, "EXT_RXD1"), + MTK_FUNCTION(5, "ANT_SEL1"), + MTK_FUNCTION(6, "DPI_D8"), + MTK_FUNCTION(7, "DBG_MON_B[3]") + ), + MTK_PIN( + PINCTRL_PIN(32, "EINT10"), + "W24", "mt8127", + MTK_EINT_FUNCTION(0, 10), + MTK_FUNCTION(0, "GPIO32"), + MTK_FUNCTION(1, "CLKM5"), + MTK_FUNCTION(2, "SCL2"), + MTK_FUNCTION(3, "EXT_FRAME_SYNC"), + MTK_FUNCTION(4, "EXT_RXD2"), + MTK_FUNCTION(5, "ANT_SEL2"), + MTK_FUNCTION(6, "DPI_D9"), + MTK_FUNCTION(7, "DBG_MON_B[4]") + ), + MTK_PIN( + PINCTRL_PIN(33, "KPROW0"), + "AB24", "mt8127", + MTK_EINT_FUNCTION(0, 44), + MTK_FUNCTION(0, "GPIO33"), + MTK_FUNCTION(1, "KROW0"), + MTK_FUNCTION(4, "IMG_TEST_CK"), + MTK_FUNCTION(7, "DBG_MON_A[12]") + ), + MTK_PIN( + PINCTRL_PIN(34, "KPROW1"), + "AC24", "mt8127", + MTK_EINT_FUNCTION(0, 45), + MTK_FUNCTION(0, "GPIO34"), + MTK_FUNCTION(1, "KROW1"), + MTK_FUNCTION(2, "IDDIG"), + MTK_FUNCTION(3, "EXT_FRAME_SYNC"), + MTK_FUNCTION(4, "MFG_TEST_CK"), + MTK_FUNCTION(7, "DBG_MON_B[5]") + ), + MTK_PIN( + PINCTRL_PIN(35, "KPROW2"), + "AD24", "mt8127", + MTK_EINT_FUNCTION(0, 46), + MTK_FUNCTION(0, "GPIO35"), + MTK_FUNCTION(1, "KROW2"), + MTK_FUNCTION(2, "DRV_VBUS"), + MTK_FUNCTION(3, "EXT_FRAME_SYNC"), + MTK_FUNCTION(4, "CONN_TEST_CK"), + MTK_FUNCTION(7, "DBG_MON_B[6]") + ), + MTK_PIN( + PINCTRL_PIN(36, "KPCOL0"), + "AB23", "mt8127", + MTK_EINT_FUNCTION(0, 47), + MTK_FUNCTION(0, "GPIO36"), + MTK_FUNCTION(1, "KCOL0"), + MTK_FUNCTION(7, "DBG_MON_A[13]") + ), + MTK_PIN( + PINCTRL_PIN(37, "KPCOL1"), + "AC22", "mt8127", + MTK_EINT_FUNCTION(0, 48), + MTK_FUNCTION(0, "GPIO37"), + MTK_FUNCTION(1, "KCOL1"), + MTK_FUNCTION(7, "DBG_MON_B[7]") + ), + MTK_PIN( + PINCTRL_PIN(38, "KPCOL2"), + "AC23", "mt8127", + MTK_EINT_FUNCTION(0, 49), + MTK_FUNCTION(0, "GPIO38"), + MTK_FUNCTION(1, "KCOL2"), + MTK_FUNCTION(2, "IDDIG"), + MTK_FUNCTION(3, "EXT_FRAME_SYNC"), + MTK_FUNCTION(7, "DBG_MON_B[8]") + ), + MTK_PIN( + PINCTRL_PIN(39, "JTMS"), + "V18", "mt8127", + MTK_EINT_FUNCTION(0, 50), + MTK_FUNCTION(0, "GPIO39"), + MTK_FUNCTION(1, "JTMS"), + MTK_FUNCTION(2, "CONN_MCU_TMS"), + MTK_FUNCTION(3, "CONN_MCU_AICE_JMSC") + ), + MTK_PIN( + PINCTRL_PIN(40, "JTCK"), + "AA18", "mt8127", + MTK_EINT_FUNCTION(0, 51), + MTK_FUNCTION(0, "GPIO40"), + MTK_FUNCTION(1, "JTCK"), + MTK_FUNCTION(2, "CONN_MCU_TCK1"), + MTK_FUNCTION(3, "CONN_MCU_AICE_JCKC") + ), + MTK_PIN( + PINCTRL_PIN(41, "JTDI"), + "W18", "mt8127", + MTK_EINT_FUNCTION(0, 52), + MTK_FUNCTION(0, "GPIO41"), + MTK_FUNCTION(1, "JTDI"), + MTK_FUNCTION(2, "CONN_MCU_TDI") + ), + MTK_PIN( + PINCTRL_PIN(42, "JTDO"), + "Y18", "mt8127", + MTK_EINT_FUNCTION(0, 53), + MTK_FUNCTION(0, "GPIO42"), + MTK_FUNCTION(1, "JTDO"), + MTK_FUNCTION(2, "CONN_MCU_TDO") + ), + MTK_PIN( + PINCTRL_PIN(43, "EINT11"), + "W22", "mt8127", + MTK_EINT_FUNCTION(0, 11), + MTK_FUNCTION(0, "GPIO43"), + MTK_FUNCTION(1, "CLKM4"), + MTK_FUNCTION(2, "PWM2"), + MTK_FUNCTION(3, "KROW3"), + MTK_FUNCTION(4, "ANT_SEL3"), + MTK_FUNCTION(5, "DPI_D10"), + MTK_FUNCTION(6, "EXT_RXD3"), + MTK_FUNCTION(7, "DBG_MON_B[9]") + ), + MTK_PIN( + PINCTRL_PIN(44, "EINT12"), + "V23", "mt8127", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + MTK_FUNCTION(0, "GPIO44"), + MTK_FUNCTION(1, "CLKM5"), + MTK_FUNCTION(2, "PWM0"), + MTK_FUNCTION(3, "KCOL3"), + MTK_FUNCTION(4, "ANT_SEL4"), + MTK_FUNCTION(5, "DPI_D11"), + MTK_FUNCTION(6, "EXT_TXEN"), + MTK_FUNCTION(7, "DBG_MON_B[10]") + ), + MTK_PIN( + PINCTRL_PIN(45, "EINT13"), + "Y21", "mt8127", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + MTK_FUNCTION(0, "GPIO45"), + MTK_FUNCTION(4, "ANT_SEL5"), + MTK_FUNCTION(5, "DPI_D0"), + MTK_FUNCTION(6, "SPDIF"), + MTK_FUNCTION(7, "DBG_MON_B[11]") + ), + MTK_PIN( + PINCTRL_PIN(46, "EINT14"), + "F23", "mt8127", + MTK_EINT_FUNCTION(0, 14), + MTK_FUNCTION(0, "GPIO46"), + MTK_FUNCTION(2, "DAC_DAT_OUT"), + MTK_FUNCTION(4, "ANT_SEL1"), + MTK_FUNCTION(5, "CONN_MCU_DBGACK_N"), + MTK_FUNCTION(6, "NCLE"), + MTK_FUNCTION(7, "DBG_MON_A[14]") + ), + MTK_PIN( + PINCTRL_PIN(47, "EINT15"), + "G23", "mt8127", + MTK_EINT_FUNCTION(0, 15), + MTK_FUNCTION(0, "GPIO47"), + MTK_FUNCTION(2, "DAC_WS"), + MTK_FUNCTION(4, "ANT_SEL2"), + MTK_FUNCTION(5, "CONN_MCU_DBGI_N"), + MTK_FUNCTION(6, "NCEB1"), + MTK_FUNCTION(7, "DBG_MON_A[15]") + ), + MTK_PIN( + PINCTRL_PIN(48, "EINT16"), + "H23", "mt8127", + MTK_EINT_FUNCTION(0, 16), + MTK_FUNCTION(0, "GPIO48"), + MTK_FUNCTION(2, "DAC_CK"), + MTK_FUNCTION(4, "ANT_SEL3"), + MTK_FUNCTION(5, "CONN_MCU_TRST_B"), + MTK_FUNCTION(6, "NCEB0"), + MTK_FUNCTION(7, "DBG_MON_A[16]") + ), + MTK_PIN( + PINCTRL_PIN(49, "EINT17"), + "J22", "mt8127", + MTK_EINT_FUNCTION(0, 17), + MTK_FUNCTION(0, "GPIO49"), + MTK_FUNCTION(1, "UCTS0"), + MTK_FUNCTION(3, "CLKM0"), + MTK_FUNCTION(4, "IDDIG"), + MTK_FUNCTION(5, "ANT_SEL4"), + MTK_FUNCTION(6, "NREB"), + MTK_FUNCTION(7, "DBG_MON_A[17]") + ), + MTK_PIN( + PINCTRL_PIN(50, "EINT18"), + "AD20", "mt8127", + MTK_EINT_FUNCTION(0, 18), + MTK_FUNCTION(0, "GPIO50"), + MTK_FUNCTION(1, "URTS0"), + MTK_FUNCTION(2, "CLKM3"), + MTK_FUNCTION(3, "I2SOUT_LRCK"), + MTK_FUNCTION(4, "DRV_VBUS"), + MTK_FUNCTION(5, "ANT_SEL3"), + MTK_FUNCTION(6, "ADC_CK"), + MTK_FUNCTION(7, "DBG_MON_B[12]") + ), + MTK_PIN( + PINCTRL_PIN(51, "EINT19"), + "AC21", "mt8127", + MTK_EINT_FUNCTION(0, 19), + MTK_FUNCTION(0, "GPIO51"), + MTK_FUNCTION(1, "UCTS1"), + MTK_FUNCTION(3, "I2SOUT_BCK"), + MTK_FUNCTION(4, "CLKM1"), + MTK_FUNCTION(5, "ANT_SEL4"), + MTK_FUNCTION(6, "ADC_DAT_IN"), + MTK_FUNCTION(7, "DBG_MON_B[13]") + ), + MTK_PIN( + PINCTRL_PIN(52, "EINT20"), + "V20", "mt8127", + MTK_EINT_FUNCTION(0, 20), + MTK_FUNCTION(0, "GPIO52"), + MTK_FUNCTION(1, "URTS1"), + MTK_FUNCTION(2, "PCM_TX"), + MTK_FUNCTION(3, "I2SOUT_DATA_OUT"), + MTK_FUNCTION(4, "CLKM2"), + MTK_FUNCTION(5, "ANT_SEL5"), + MTK_FUNCTION(6, "ADC_WS"), + MTK_FUNCTION(7, "DBG_MON_B[14]") + ), + MTK_PIN( + PINCTRL_PIN(53, "SPI_CS"), + "AD19", "mt8127", + MTK_EINT_FUNCTION(0, 54), + MTK_FUNCTION(0, "GPIO53"), + MTK_FUNCTION(1, "SPI_CS"), + MTK_FUNCTION(3, "I2SIN1_DATA_IN"), + MTK_FUNCTION(4, "ADC_CK"), + MTK_FUNCTION(7, "DBG_MON_B[15]") + ), + MTK_PIN( + PINCTRL_PIN(54, "SPI_CK"), + "AC18", "mt8127", + MTK_EINT_FUNCTION(0, 55), + MTK_FUNCTION(0, "GPIO54"), + MTK_FUNCTION(1, "SPI_CK"), + MTK_FUNCTION(3, "I2SIN1_LRCK"), + MTK_FUNCTION(4, "ADC_DAT_IN"), + MTK_FUNCTION(7, "DBG_MON_B[16]") + ), + MTK_PIN( + PINCTRL_PIN(55, "SPI_MI"), + "AC19", "mt8127", + MTK_EINT_FUNCTION(0, 56), + MTK_FUNCTION(0, "GPIO55"), + MTK_FUNCTION(1, "SPI_MI"), + MTK_FUNCTION(2, "SPI_MO"), + MTK_FUNCTION(3, "I2SIN1_BCK1"), + MTK_FUNCTION(4, "ADC_WS"), + MTK_FUNCTION(7, "DBG_MON_B[17]") + ), + MTK_PIN( + PINCTRL_PIN(56, "SPI_MO"), + "AD18", "mt8127", + MTK_EINT_FUNCTION(0, 57), + MTK_FUNCTION(0, "GPIO56"), + MTK_FUNCTION(1, "SPI_MO"), + MTK_FUNCTION(2, "SPI_MI"), + MTK_FUNCTION(7, "DBG_MON_B[18]") + ), + MTK_PIN( + PINCTRL_PIN(57, "SDA1"), + "AE23", "mt8127", + MTK_EINT_FUNCTION(0, 58), + MTK_FUNCTION(0, "GPIO57"), + MTK_FUNCTION(1, "SDA1") + ), + MTK_PIN( + PINCTRL_PIN(58, "SCL1"), + "AD23", "mt8127", + MTK_EINT_FUNCTION(0, 59), + MTK_FUNCTION(0, "GPIO58"), + MTK_FUNCTION(1, "SCL1") + ), + MTK_PIN( + PINCTRL_PIN(59, "DISP_PWM"), + "AC20", "mt8127", + MTK_EINT_FUNCTION(0, 60), + MTK_FUNCTION(0, "GPIO59"), + MTK_FUNCTION(1, "DISP_PWM"), + MTK_FUNCTION(2, "PWM1"), + MTK_FUNCTION(7, "DBG_MON_A[18]") + ), + MTK_PIN( + PINCTRL_PIN(60, "WB_RSTB"), + "AD7", "mt8127", + MTK_EINT_FUNCTION(0, 61), + MTK_FUNCTION(0, "GPIO60"), + MTK_FUNCTION(1, "WB_RSTB"), + MTK_FUNCTION(7, "DBG_MON_A[19]") + ), + MTK_PIN( + PINCTRL_PIN(61, "F2W_DATA"), + "Y10", "mt8127", + MTK_EINT_FUNCTION(0, 62), + MTK_FUNCTION(0, "GPIO61"), + MTK_FUNCTION(1, "F2W_DATA"), + MTK_FUNCTION(7, "DBG_MON_A[20]") + ), + MTK_PIN( + PINCTRL_PIN(62, "F2W_CLK"), + "W10", "mt8127", + MTK_EINT_FUNCTION(0, 63), + MTK_FUNCTION(0, "GPIO62"), + MTK_FUNCTION(1, "F2W_CK"), + MTK_FUNCTION(7, "DBG_MON_A[21]") + ), + MTK_PIN( + PINCTRL_PIN(63, "WB_SCLK"), + "AB7", "mt8127", + MTK_EINT_FUNCTION(0, 64), + MTK_FUNCTION(0, "GPIO63"), + MTK_FUNCTION(1, "WB_SCLK"), + MTK_FUNCTION(7, "DBG_MON_A[22]") + ), + MTK_PIN( + PINCTRL_PIN(64, "WB_SDATA"), + "AA7", "mt8127", + MTK_EINT_FUNCTION(0, 65), + MTK_FUNCTION(0, "GPIO64"), + MTK_FUNCTION(1, "WB_SDATA"), + MTK_FUNCTION(7, "DBG_MON_A[23]") + ), + MTK_PIN( + PINCTRL_PIN(65, "WB_SEN"), + "Y7", "mt8127", + MTK_EINT_FUNCTION(0, 66), + MTK_FUNCTION(0, "GPIO65"), + MTK_FUNCTION(1, "WB_SEN"), + MTK_FUNCTION(7, "DBG_MON_A[24]") + ), + MTK_PIN( + PINCTRL_PIN(66, "WB_CRTL0"), + "AA1", "mt8127", + MTK_EINT_FUNCTION(0, 67), + MTK_FUNCTION(0, "GPIO66"), + MTK_FUNCTION(1, "WB_CRTL0"), + MTK_FUNCTION(2, "DFD_NTRST_XI"), + MTK_FUNCTION(7, "DBG_MON_A[25]") + ), + MTK_PIN( + PINCTRL_PIN(67, "WB_CRTL1"), + "AA2", "mt8127", + MTK_EINT_FUNCTION(0, 68), + MTK_FUNCTION(0, "GPIO67"), + MTK_FUNCTION(1, "WB_CRTL1"), + MTK_FUNCTION(2, "DFD_TMS_XI"), + MTK_FUNCTION(7, "DBG_MON_A[26]") + ), + MTK_PIN( + PINCTRL_PIN(68, "WB_CRTL2"), + "Y1", "mt8127", + MTK_EINT_FUNCTION(0, 69), + MTK_FUNCTION(0, "GPIO68"), + MTK_FUNCTION(1, "WB_CRTL2"), + MTK_FUNCTION(2, "DFD_TCK_XI"), + MTK_FUNCTION(7, "DBG_MON_A[27]") + ), + MTK_PIN( + PINCTRL_PIN(69, "WB_CRTL3"), + "Y2", "mt8127", + MTK_EINT_FUNCTION(0, 70), + MTK_FUNCTION(0, "GPIO69"), + MTK_FUNCTION(1, "WB_CRTL3"), + MTK_FUNCTION(2, "DFD_TDI_XI"), + MTK_FUNCTION(7, "DBG_MON_A[28]") + ), + MTK_PIN( + PINCTRL_PIN(70, "WB_CRTL4"), + "Y3", "mt8127", + MTK_EINT_FUNCTION(0, 71), + MTK_FUNCTION(0, "GPIO70"), + MTK_FUNCTION(1, "WB_CRTL4"), + MTK_FUNCTION(2, "DFD_TDO"), + MTK_FUNCTION(7, "DBG_MON_A[29]") + ), + MTK_PIN( + PINCTRL_PIN(71, "WB_CRTL5"), + "Y4", "mt8127", + MTK_EINT_FUNCTION(0, 72), + MTK_FUNCTION(0, "GPIO71"), + MTK_FUNCTION(1, "WB_CRTL5"), + MTK_FUNCTION(7, "DBG_MON_A[30]") + ), + MTK_PIN( + PINCTRL_PIN(72, "I2S_DATA_IN"), + "K21", "mt8127", + MTK_EINT_FUNCTION(0, 73), + MTK_FUNCTION(0, "GPIO72"), + MTK_FUNCTION(1, "I2SIN1_DATA_IN"), + MTK_FUNCTION(2, "PCM_RX"), + MTK_FUNCTION(3, "I2SOUT_DATA_OUT"), + MTK_FUNCTION(4, "DAC_DAT_OUT"), + MTK_FUNCTION(5, "PWM0"), + MTK_FUNCTION(6, "ADC_CK"), + MTK_FUNCTION(7, "DBG_MON_B[19]") + ), + MTK_PIN( + PINCTRL_PIN(73, "I2S_LRCK"), + "L21", "mt8127", + MTK_EINT_FUNCTION(0, 74), + MTK_FUNCTION(0, "GPIO73"), + MTK_FUNCTION(1, "I2SIN1_LRCK"), + MTK_FUNCTION(2, "PCM_SYNC"), + MTK_FUNCTION(3, "I2SOUT_LRCK"), + MTK_FUNCTION(4, "DAC_WS"), + MTK_FUNCTION(5, "PWM3"), + MTK_FUNCTION(6, "ADC_DAT_IN"), + MTK_FUNCTION(7, "DBG_MON_B[20]") + ), + MTK_PIN( + PINCTRL_PIN(74, "I2S_BCK"), + "L20", "mt8127", + MTK_EINT_FUNCTION(0, 75), + MTK_FUNCTION(0, "GPIO74"), + MTK_FUNCTION(1, "I2SIN1_BCK2"), + MTK_FUNCTION(2, "PCM_CLK1"), + MTK_FUNCTION(3, "I2SOUT_BCK"), + MTK_FUNCTION(4, "DAC_CK"), + MTK_FUNCTION(5, "PWM4"), + MTK_FUNCTION(6, "ADC_WS"), + MTK_FUNCTION(7, "DBG_MON_B[21]") + ), + MTK_PIN( + PINCTRL_PIN(75, "SDA0"), + "W3", "mt8127", + MTK_EINT_FUNCTION(0, 76), + MTK_FUNCTION(0, "GPIO75"), + MTK_FUNCTION(1, "SDA0") + ), + MTK_PIN( + PINCTRL_PIN(76, "SCL0"), + "W4", "mt8127", + MTK_EINT_FUNCTION(0, 77), + MTK_FUNCTION(0, "GPIO76"), + MTK_FUNCTION(1, "SCL0") + ), + MTK_PIN( + PINCTRL_PIN(77, "SDA2"), + "K19", "mt8127", + MTK_EINT_FUNCTION(0, 78), + MTK_FUNCTION(0, "GPIO77"), + MTK_FUNCTION(1, "SDA2"), + MTK_FUNCTION(2, "PWM1") + ), + MTK_PIN( + PINCTRL_PIN(78, "SCL2"), + "K20", "mt8127", + MTK_EINT_FUNCTION(0, 79), + MTK_FUNCTION(0, "GPIO78"), + MTK_FUNCTION(1, "SCL2"), + MTK_FUNCTION(2, "PWM2") + ), + MTK_PIN( + PINCTRL_PIN(79, "URXD0"), + "K18", "mt8127", + MTK_EINT_FUNCTION(0, 80), + MTK_FUNCTION(0, "GPIO79"), + MTK_FUNCTION(1, "URXD0"), + MTK_FUNCTION(2, "UTXD0") + ), + MTK_PIN( + PINCTRL_PIN(80, "UTXD0"), + "K17", "mt8127", + MTK_EINT_FUNCTION(0, 81), + MTK_FUNCTION(0, "GPIO80"), + MTK_FUNCTION(1, "UTXD0"), + MTK_FUNCTION(2, "URXD0") + ), + MTK_PIN( + PINCTRL_PIN(81, "URXD1"), + "L17", "mt8127", + MTK_EINT_FUNCTION(0, 82), + MTK_FUNCTION(0, "GPIO81"), + MTK_FUNCTION(1, "URXD1"), + MTK_FUNCTION(2, "UTXD1") + ), + MTK_PIN( + PINCTRL_PIN(82, "UTXD1"), + "L18", "mt8127", + MTK_EINT_FUNCTION(0, 83), + MTK_FUNCTION(0, "GPIO82"), + MTK_FUNCTION(1, "UTXD1"), + MTK_FUNCTION(2, "URXD1") + ), + MTK_PIN( + PINCTRL_PIN(83, "LCM_RST"), + "W5", "mt8127", + MTK_EINT_FUNCTION(0, 84), + MTK_FUNCTION(0, "GPIO83"), + MTK_FUNCTION(1, "LCM_RST"), + MTK_FUNCTION(2, "VDAC_CK_XI"), + MTK_FUNCTION(7, "DBG_MON_A[31]") + ), + MTK_PIN( + PINCTRL_PIN(84, "DSI_TE"), + "W6", "mt8127", + MTK_EINT_FUNCTION(0, 85), + MTK_FUNCTION(0, "GPIO84"), + MTK_FUNCTION(1, "DSI_TE"), + MTK_FUNCTION(7, "DBG_MON_A[32]") + ), + MTK_PIN( + PINCTRL_PIN(85, "MSDC2_CMD"), + "U7", "mt8127", + MTK_EINT_FUNCTION(0, 86), + MTK_FUNCTION(0, "GPIO85"), + MTK_FUNCTION(1, "MSDC2_CMD"), + MTK_FUNCTION(2, "ANT_SEL0"), + MTK_FUNCTION(3, "SDA1"), + MTK_FUNCTION(6, "I2SOUT_BCK"), + MTK_FUNCTION(7, "DBG_MON_B[22]") + ), + MTK_PIN( + PINCTRL_PIN(86, "MSDC2_CLK"), + "T8", "mt8127", + MTK_EINT_FUNCTION(0, 87), + MTK_FUNCTION(0, "GPIO86"), + MTK_FUNCTION(1, "MSDC2_CLK"), + MTK_FUNCTION(2, "ANT_SEL1"), + MTK_FUNCTION(3, "SCL1"), + MTK_FUNCTION(6, "I2SOUT_LRCK"), + MTK_FUNCTION(7, "DBG_MON_B[23]") + ), + MTK_PIN( + PINCTRL_PIN(87, "MSDC2_DAT0"), + "V3", "mt8127", + MTK_EINT_FUNCTION(0, 88), + MTK_FUNCTION(0, "GPIO87"), + MTK_FUNCTION(1, "MSDC2_DAT0"), + MTK_FUNCTION(2, "ANT_SEL2"), + MTK_FUNCTION(5, "UTXD0"), + MTK_FUNCTION(6, "I2SOUT_DATA_OUT"), + MTK_FUNCTION(7, "DBG_MON_B[24]") + ), + MTK_PIN( + PINCTRL_PIN(88, "MSDC2_DAT1"), + "V4", "mt8127", + MTK_EINT_FUNCTION(0, 89), + MTK_FUNCTION(0, "GPIO88"), + MTK_FUNCTION(1, "MSDC2_DAT1"), + MTK_FUNCTION(2, "ANT_SEL3"), + MTK_FUNCTION(3, "PWM0"), + MTK_FUNCTION(5, "URXD0"), + MTK_FUNCTION(6, "PWM1"), + MTK_FUNCTION(7, "DBG_MON_B[25]") + ), + MTK_PIN( + PINCTRL_PIN(89, "MSDC2_DAT2"), + "U5", "mt8127", + MTK_EINT_FUNCTION(0, 90), + MTK_FUNCTION(0, "GPIO89"), + MTK_FUNCTION(1, "MSDC2_DAT2"), + MTK_FUNCTION(2, "ANT_SEL4"), + MTK_FUNCTION(3, "SDA2"), + MTK_FUNCTION(5, "UTXD1"), + MTK_FUNCTION(6, "PWM2"), + MTK_FUNCTION(7, "DBG_MON_B[26]") + ), + MTK_PIN( + PINCTRL_PIN(90, "MSDC2_DAT3"), + "U6", "mt8127", + MTK_EINT_FUNCTION(0, 91), + MTK_FUNCTION(0, "GPIO90"), + MTK_FUNCTION(1, "MSDC2_DAT3"), + MTK_FUNCTION(2, "ANT_SEL5"), + MTK_FUNCTION(3, "SCL2"), + MTK_FUNCTION(4, "EXT_FRAME_SYNC"), + MTK_FUNCTION(5, "URXD1"), + MTK_FUNCTION(6, "PWM3"), + MTK_FUNCTION(7, "DBG_MON_B[27]") + ), + MTK_PIN( + PINCTRL_PIN(91, "TDN3"), + "U2", "mt8127", + MTK_EINT_FUNCTION(0, 92), + MTK_FUNCTION(0, "GPI91"), + MTK_FUNCTION(1, "TDN3") + ), + MTK_PIN( + PINCTRL_PIN(92, "TDP3"), + "U1", "mt8127", + MTK_EINT_FUNCTION(0, 93), + MTK_FUNCTION(0, "GPI92"), + MTK_FUNCTION(1, "TDP3") + ), + MTK_PIN( + PINCTRL_PIN(93, "TDN2"), + "T2", "mt8127", + MTK_EINT_FUNCTION(0, 94), + MTK_FUNCTION(0, "GPI93"), + MTK_FUNCTION(1, "TDN2") + ), + MTK_PIN( + PINCTRL_PIN(94, "TDP2"), + "T1", "mt8127", + MTK_EINT_FUNCTION(0, 95), + MTK_FUNCTION(0, "GPI94"), + MTK_FUNCTION(1, "TDP2") + ), + MTK_PIN( + PINCTRL_PIN(95, "TCN"), + "R5", "mt8127", + MTK_EINT_FUNCTION(0, 96), + MTK_FUNCTION(0, "GPI95"), + MTK_FUNCTION(1, "TCN") + ), + MTK_PIN( + PINCTRL_PIN(96, "TCP"), + "R4", "mt8127", + MTK_EINT_FUNCTION(0, 97), + MTK_FUNCTION(0, "GPI96"), + MTK_FUNCTION(1, "TCP") + ), + MTK_PIN( + PINCTRL_PIN(97, "TDN1"), + "R3", "mt8127", + MTK_EINT_FUNCTION(0, 98), + MTK_FUNCTION(0, "GPI97"), + MTK_FUNCTION(1, "TDN1") + ), + MTK_PIN( + PINCTRL_PIN(98, "TDP1"), + "R2", "mt8127", + MTK_EINT_FUNCTION(0, 99), + MTK_FUNCTION(0, "GPI98"), + MTK_FUNCTION(1, "TDP1") + ), + MTK_PIN( + PINCTRL_PIN(99, "TDN0"), + "P3", "mt8127", + MTK_EINT_FUNCTION(0, 100), + MTK_FUNCTION(0, "GPI99"), + MTK_FUNCTION(1, "TDN0") + ), + MTK_PIN( + PINCTRL_PIN(100, "TDP0"), + "P2", "mt8127", + MTK_EINT_FUNCTION(0, 101), + MTK_FUNCTION(0, "GPI100"), + MTK_FUNCTION(1, "TDP0") + ), + MTK_PIN( + PINCTRL_PIN(101, "RDN0"), + "K1", "mt8127", + MTK_EINT_FUNCTION(0, 102), + MTK_FUNCTION(0, "GPI101"), + MTK_FUNCTION(1, "RDN0") + ), + MTK_PIN( + PINCTRL_PIN(102, "RDP0"), + "K2", "mt8127", + MTK_EINT_FUNCTION(0, 103), + MTK_FUNCTION(0, "GPI102"), + MTK_FUNCTION(1, "RDP0") + ), + MTK_PIN( + PINCTRL_PIN(103, "RDN1"), + "L2", "mt8127", + MTK_EINT_FUNCTION(0, 104), + MTK_FUNCTION(0, "GPI103"), + MTK_FUNCTION(1, "RDN1") + ), + MTK_PIN( + PINCTRL_PIN(104, "RDP1"), + "L3", "mt8127", + MTK_EINT_FUNCTION(0, 105), + MTK_FUNCTION(0, "GPI104"), + MTK_FUNCTION(1, "RDP1") + ), + MTK_PIN( + PINCTRL_PIN(105, "RCN"), + "M4", "mt8127", + MTK_EINT_FUNCTION(0, 106), + MTK_FUNCTION(0, "GPI105"), + MTK_FUNCTION(1, "RCN") + ), + MTK_PIN( + PINCTRL_PIN(106, "RCP"), + "M5", "mt8127", + MTK_EINT_FUNCTION(0, 107), + MTK_FUNCTION(0, "GPI106"), + MTK_FUNCTION(1, "RCP") + ), + MTK_PIN( + PINCTRL_PIN(107, "RDN2"), + "M2", "mt8127", + MTK_EINT_FUNCTION(0, 108), + MTK_FUNCTION(0, "GPI107"), + MTK_FUNCTION(1, "RDN2"), + MTK_FUNCTION(2, "CMDAT8") + ), + MTK_PIN( + PINCTRL_PIN(108, "RDP2"), + "M3", "mt8127", + MTK_EINT_FUNCTION(0, 109), + MTK_FUNCTION(0, "GPI108"), + MTK_FUNCTION(1, "RDP2"), + MTK_FUNCTION(2, "CMDAT9") + ), + MTK_PIN( + PINCTRL_PIN(109, "RDN3"), + "N2", "mt8127", + MTK_EINT_FUNCTION(0, 110), + MTK_FUNCTION(0, "GPI109"), + MTK_FUNCTION(1, "RDN3"), + MTK_FUNCTION(2, "CMDAT4") + ), + MTK_PIN( + PINCTRL_PIN(110, "RDP3"), + "N3", "mt8127", + MTK_EINT_FUNCTION(0, 111), + MTK_FUNCTION(0, "GPI110"), + MTK_FUNCTION(1, "RDP3"), + MTK_FUNCTION(2, "CMDAT5") + ), + MTK_PIN( + PINCTRL_PIN(111, "RCN_A"), + "J5", "mt8127", + MTK_EINT_FUNCTION(0, 112), + MTK_FUNCTION(0, "GPI111"), + MTK_FUNCTION(1, "RCN_A"), + MTK_FUNCTION(2, "CMDAT6") + ), + MTK_PIN( + PINCTRL_PIN(112, "RCP_A"), + "J4", "mt8127", + MTK_EINT_FUNCTION(0, 113), + MTK_FUNCTION(0, "GPI112"), + MTK_FUNCTION(1, "RCP_A"), + MTK_FUNCTION(2, "CMDAT7") + ), + MTK_PIN( + PINCTRL_PIN(113, "RDN1_A"), + "J2", "mt8127", + MTK_EINT_FUNCTION(0, 114), + MTK_FUNCTION(0, "GPI113"), + MTK_FUNCTION(1, "RDN1_A"), + MTK_FUNCTION(2, "CMDAT2"), + MTK_FUNCTION(3, "CMCSD2") + ), + MTK_PIN( + PINCTRL_PIN(114, "RDP1_A"), + "J3", "mt8127", + MTK_EINT_FUNCTION(0, 115), + MTK_FUNCTION(0, "GPI114"), + MTK_FUNCTION(1, "RDP1_A"), + MTK_FUNCTION(2, "CMDAT3"), + MTK_FUNCTION(3, "CMCSD3") + ), + MTK_PIN( + PINCTRL_PIN(115, "RDN0_A"), + "H2", "mt8127", + MTK_EINT_FUNCTION(0, 116), + MTK_FUNCTION(0, "GPI115"), + MTK_FUNCTION(1, "RDN0_A"), + MTK_FUNCTION(2, "CMHSYNC") + ), + MTK_PIN( + PINCTRL_PIN(116, "RDP0_A"), + "H3", "mt8127", + MTK_EINT_FUNCTION(0, 117), + MTK_FUNCTION(0, "GPI116"), + MTK_FUNCTION(1, "RDP0_A"), + MTK_FUNCTION(2, "CMVSYNC") + ), + MTK_PIN( + PINCTRL_PIN(117, "CMDAT0"), + "G5", "mt8127", + MTK_EINT_FUNCTION(0, 118), + MTK_FUNCTION(0, "GPIO117"), + MTK_FUNCTION(1, "CMDAT0"), + MTK_FUNCTION(2, "CMCSD0"), + MTK_FUNCTION(3, "ANT_SEL2"), + MTK_FUNCTION(7, "DBG_MON_B[28]") + ), + MTK_PIN( + PINCTRL_PIN(118, "CMDAT1"), + "G4", "mt8127", + MTK_EINT_FUNCTION(0, 119), + MTK_FUNCTION(0, "GPIO118"), + MTK_FUNCTION(1, "CMDAT1"), + MTK_FUNCTION(2, "CMCSD1"), + MTK_FUNCTION(3, "ANT_SEL3"), + MTK_FUNCTION(7, "DBG_MON_B[29]") + ), + MTK_PIN( + PINCTRL_PIN(119, "CMMCLK"), + "F3", "mt8127", + MTK_EINT_FUNCTION(0, 120), + MTK_FUNCTION(0, "GPIO119"), + MTK_FUNCTION(1, "CMMCLK"), + MTK_FUNCTION(3, "ANT_SEL4"), + MTK_FUNCTION(7, "DBG_MON_B[30]") + ), + MTK_PIN( + PINCTRL_PIN(120, "CMPCLK"), + "G6", "mt8127", + MTK_EINT_FUNCTION(0, 121), + MTK_FUNCTION(0, "GPIO120"), + MTK_FUNCTION(1, "CMPCLK"), + MTK_FUNCTION(2, "CMCSK"), + MTK_FUNCTION(3, "ANT_SEL5"), + MTK_FUNCTION(7, "DBG_MON_B[31]") + ), + MTK_PIN( + PINCTRL_PIN(121, "MSDC1_CMD"), + "E3", "mt8127", + MTK_EINT_FUNCTION(0, 122), + MTK_FUNCTION(0, "GPIO121"), + MTK_FUNCTION(1, "MSDC1_CMD") + ), + MTK_PIN( + PINCTRL_PIN(122, "MSDC1_CLK"), + "D1", "mt8127", + MTK_EINT_FUNCTION(0, 123), + MTK_FUNCTION(0, "GPIO122"), + MTK_FUNCTION(1, "MSDC1_CLK") + ), + MTK_PIN( + PINCTRL_PIN(123, "MSDC1_DAT0"), + "D2", "mt8127", + MTK_EINT_FUNCTION(0, 124), + MTK_FUNCTION(0, "GPIO123"), + MTK_FUNCTION(1, "MSDC1_DAT0") + ), + MTK_PIN( + PINCTRL_PIN(124, "MSDC1_DAT1"), + "D3", "mt8127", + MTK_EINT_FUNCTION(0, 125), + MTK_FUNCTION(0, "GPIO124"), + MTK_FUNCTION(1, "MSDC1_DAT1") + ), + MTK_PIN( + PINCTRL_PIN(125, "MSDC1_DAT2"), + "F2", "mt8127", + MTK_EINT_FUNCTION(0, 126), + MTK_FUNCTION(0, "GPIO125"), + MTK_FUNCTION(1, "MSDC1_DAT2") + ), + MTK_PIN( + PINCTRL_PIN(126, "MSDC1_DAT3"), + "E2", "mt8127", + MTK_EINT_FUNCTION(0, 127), + MTK_FUNCTION(0, "GPIO126"), + MTK_FUNCTION(1, "MSDC1_DAT3") + ), + MTK_PIN( + PINCTRL_PIN(127, "MSDC0_DAT7"), + "C23", "mt8127", + MTK_EINT_FUNCTION(0, 128), + MTK_FUNCTION(0, "GPIO127"), + MTK_FUNCTION(1, "MSDC0_DAT7"), + MTK_FUNCTION(4, "NLD7") + ), + MTK_PIN( + PINCTRL_PIN(128, "MSDC0_DAT6"), + "C24", "mt8127", + MTK_EINT_FUNCTION(0, 129), + MTK_FUNCTION(0, "GPIO128"), + MTK_FUNCTION(1, "MSDC0_DAT6"), + MTK_FUNCTION(4, "NLD6") + ), + MTK_PIN( + PINCTRL_PIN(129, "MSDC0_DAT5"), + "D22", "mt8127", + MTK_EINT_FUNCTION(0, 130), + MTK_FUNCTION(0, "GPIO129"), + MTK_FUNCTION(1, "MSDC0_DAT5"), + MTK_FUNCTION(4, "NLD4") + ), + MTK_PIN( + PINCTRL_PIN(130, "MSDC0_DAT4"), + "D24", "mt8127", + MTK_EINT_FUNCTION(0, 131), + MTK_FUNCTION(0, "GPIO130"), + MTK_FUNCTION(1, "MSDC0_DAT4"), + MTK_FUNCTION(4, "NLD3") + ), + MTK_PIN( + PINCTRL_PIN(131, "MSDC0_RSTB"), + "F24", "mt8127", + MTK_EINT_FUNCTION(0, 132), + MTK_FUNCTION(0, "GPIO131"), + MTK_FUNCTION(1, "MSDC0_RSTB"), + MTK_FUNCTION(4, "NLD0") + ), + MTK_PIN( + PINCTRL_PIN(132, "MSDC0_CMD"), + "G20", "mt8127", + MTK_EINT_FUNCTION(0, 133), + MTK_FUNCTION(0, "GPIO132"), + MTK_FUNCTION(1, "MSDC0_CMD"), + MTK_FUNCTION(4, "NALE") + ), + MTK_PIN( + PINCTRL_PIN(133, "MSDC0_CLK"), + "G21", "mt8127", + MTK_EINT_FUNCTION(0, 134), + MTK_FUNCTION(0, "GPIO133"), + MTK_FUNCTION(1, "MSDC0_CLK"), + MTK_FUNCTION(4, "NWEB") + ), + MTK_PIN( + PINCTRL_PIN(134, "MSDC0_DAT3"), + "D23", "mt8127", + MTK_EINT_FUNCTION(0, 135), + MTK_FUNCTION(0, "GPIO134"), + MTK_FUNCTION(1, "MSDC0_DAT3"), + MTK_FUNCTION(4, "NLD1") + ), + MTK_PIN( + PINCTRL_PIN(135, "MSDC0_DAT2"), + "E22", "mt8127", + MTK_EINT_FUNCTION(0, 136), + MTK_FUNCTION(0, "GPIO135"), + MTK_FUNCTION(1, "MSDC0_DAT2"), + MTK_FUNCTION(4, "NLD5") + ), + MTK_PIN( + PINCTRL_PIN(136, "MSDC0_DAT1"), + "E23", "mt8127", + MTK_EINT_FUNCTION(0, 137), + MTK_FUNCTION(0, "GPIO136"), + MTK_FUNCTION(1, "MSDC0_DAT1"), + MTK_FUNCTION(4, "NLD8") + ), + MTK_PIN( + PINCTRL_PIN(137, "MSDC0_DAT0"), + "F22", "mt8127", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + MTK_FUNCTION(0, "GPIO137"), + MTK_FUNCTION(1, "MSDC0_DAT0"), + MTK_FUNCTION(4, "WATCHDOG"), + MTK_FUNCTION(5, "NLD2") + ), + MTK_PIN( + PINCTRL_PIN(138, "CEC"), + "AE21", "mt8127", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + MTK_FUNCTION(0, "GPIO138"), + MTK_FUNCTION(1, "CEC") + ), + MTK_PIN( + PINCTRL_PIN(139, "HTPLG"), + "AD21", "mt8127", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + MTK_FUNCTION(0, "GPIO139"), + MTK_FUNCTION(1, "HTPLG") + ), + MTK_PIN( + PINCTRL_PIN(140, "HDMISCK"), + "AE22", "mt8127", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + MTK_FUNCTION(0, "GPIO140"), + MTK_FUNCTION(1, "HDMISCK") + ), + MTK_PIN( + PINCTRL_PIN(141, "HDMISD"), + "AD22", "mt8127", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + MTK_FUNCTION(0, "GPIO141"), + MTK_FUNCTION(1, "HDMISD") + ), + MTK_PIN( + PINCTRL_PIN(142, "EINT21"), + "J23", "mt8127", + MTK_EINT_FUNCTION(0, 21), + MTK_FUNCTION(0, "GPIO142"), + MTK_FUNCTION(1, "NRNB"), + MTK_FUNCTION(2, "ANT_SEL0"), + MTK_FUNCTION(7, "DBG_MON_B[32]") + ), +}; + +#endif /* __PINCTRL_MTK_MT8127_H */ -- cgit v0.10.2 From 5c89c15b748c011332d855d13f4159d3e06378d9 Mon Sep 17 00:00:00 2001 From: Yoshihiro Shimoda Date: Thu, 14 May 2015 19:48:54 +0900 Subject: pinctrl: sh-pfc: r8a7790: Add PWM pin groups and functions Signed-off-by: Yoshihiro Shimoda Reviewed-by: Geert Uytterhoeven Acked-by: Laurent Pinchart Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c index 22a5470..baab81e 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c @@ -2664,6 +2664,61 @@ static const unsigned int msiof3_tx_b_pins[] = { static const unsigned int msiof3_tx_b_mux[] = { MSIOF3_TXD_B_MARK, }; +/* - PWM -------------------------------------------------------------------- */ +static const unsigned int pwm0_pins[] = { + RCAR_GP_PIN(5, 29), +}; +static const unsigned int pwm0_mux[] = { + PWM0_MARK, +}; +static const unsigned int pwm0_b_pins[] = { + RCAR_GP_PIN(4, 30), +}; +static const unsigned int pwm0_b_mux[] = { + PWM0_B_MARK, +}; +static const unsigned int pwm1_pins[] = { + RCAR_GP_PIN(5, 30), +}; +static const unsigned int pwm1_mux[] = { + PWM1_MARK, +}; +static const unsigned int pwm1_b_pins[] = { + RCAR_GP_PIN(4, 31), +}; +static const unsigned int pwm1_b_mux[] = { + PWM1_B_MARK, +}; +static const unsigned int pwm2_pins[] = { + RCAR_GP_PIN(5, 31), +}; +static const unsigned int pwm2_mux[] = { + PWM2_MARK, +}; +static const unsigned int pwm3_pins[] = { + RCAR_GP_PIN(0, 16), +}; +static const unsigned int pwm3_mux[] = { + PWM3_MARK, +}; +static const unsigned int pwm4_pins[] = { + RCAR_GP_PIN(0, 17), +}; +static const unsigned int pwm4_mux[] = { + PWM4_MARK, +}; +static const unsigned int pwm5_pins[] = { + RCAR_GP_PIN(0, 18), +}; +static const unsigned int pwm5_mux[] = { + PWM5_MARK, +}; +static const unsigned int pwm6_pins[] = { + RCAR_GP_PIN(0, 19), +}; +static const unsigned int pwm6_mux[] = { + PWM6_MARK, +}; /* - QSPI ------------------------------------------------------------------- */ static const unsigned int qspi_ctrl_pins[] = { /* SPCLK, SSL */ @@ -4008,6 +4063,15 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(msiof3_sync_b), SH_PFC_PIN_GROUP(msiof3_rx_b), SH_PFC_PIN_GROUP(msiof3_tx_b), + SH_PFC_PIN_GROUP(pwm0), + SH_PFC_PIN_GROUP(pwm0_b), + SH_PFC_PIN_GROUP(pwm1), + SH_PFC_PIN_GROUP(pwm1_b), + SH_PFC_PIN_GROUP(pwm2), + SH_PFC_PIN_GROUP(pwm3), + SH_PFC_PIN_GROUP(pwm4), + SH_PFC_PIN_GROUP(pwm5), + SH_PFC_PIN_GROUP(pwm6), SH_PFC_PIN_GROUP(qspi_ctrl), SH_PFC_PIN_GROUP(qspi_data2), SH_PFC_PIN_GROUP(qspi_data4), @@ -4364,6 +4428,36 @@ static const char * const msiof3_groups[] = { "msiof3_tx_b", }; +static const char * const pwm0_groups[] = { + "pwm0", + "pwm0_b", +}; + +static const char * const pwm1_groups[] = { + "pwm1", + "pwm1_b", +}; + +static const char * const pwm2_groups[] = { + "pwm2", +}; + +static const char * const pwm3_groups[] = { + "pwm3", +}; + +static const char * const pwm4_groups[] = { + "pwm4", +}; + +static const char * const pwm5_groups[] = { + "pwm5", +}; + +static const char * const pwm6_groups[] = { + "pwm6", +}; + static const char * const qspi_groups[] = { "qspi_ctrl", "qspi_data2", @@ -4621,6 +4715,13 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(msiof1), SH_PFC_FUNCTION(msiof2), SH_PFC_FUNCTION(msiof3), + SH_PFC_FUNCTION(pwm0), + SH_PFC_FUNCTION(pwm1), + SH_PFC_FUNCTION(pwm2), + SH_PFC_FUNCTION(pwm3), + SH_PFC_FUNCTION(pwm4), + SH_PFC_FUNCTION(pwm5), + SH_PFC_FUNCTION(pwm6), SH_PFC_FUNCTION(qspi), SH_PFC_FUNCTION(scif0), SH_PFC_FUNCTION(scif1), -- cgit v0.10.2 From 5ceb41ad1d7521f6fefe2f2f86aeda6727d9736f Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Fri, 15 May 2015 12:31:38 +0900 Subject: pinctrl: zynq: add static to platform_driver remove callback MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This function is only referenced in this file. Signed-off-by: Masahiro Yamada Reviewed-by: Sören Brinkmann Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/pinctrl-zynq.c b/drivers/pinctrl/pinctrl-zynq.c index af726b9..d66f64c 100644 --- a/drivers/pinctrl/pinctrl-zynq.c +++ b/drivers/pinctrl/pinctrl-zynq.c @@ -1205,7 +1205,7 @@ static int zynq_pinctrl_probe(struct platform_device *pdev) return 0; } -int zynq_pinctrl_remove(struct platform_device *pdev) +static int zynq_pinctrl_remove(struct platform_device *pdev) { struct zynq_pinctrl *pctrl = platform_get_drvdata(pdev); -- cgit v0.10.2 From f9367793293d2262460942b0a4904c21857a1a8b Mon Sep 17 00:00:00 2001 From: Wei Chen Date: Mon, 18 May 2015 07:28:32 +0000 Subject: pinctrl: sirf: add sirf atlas7 pinctrl and gpio support The Pinctrl module (ioc) controls the Pad's function select (each pad can have 8 functions), Pad's Drive Strength, Pad's Pull Select and Pad's Input Disable status. The ioc has two modules, ioc_top & ioc_rtc. Both of these two modules have function select/clear, Pull select and Drive Strength registers. But only ioc_rtc has input-disable registers. The Pads on ioc_top have to access ioc_rtc to set their input-disable status and intpu-disable-value. So have to use one ioc driver instance to drive these two ioc modules at the same time, and each ioc module will be treat as one bank on the "IOC Device". The GPIO Controller controls the GPIO status if the Pad has been config as GPIO by Pinctrl already. Includes the GPIO Input/output, Interrupt type, Interrupt Status, and Set/Get Values. The GPIO pull up/down are controlled by Pinctrl. There are 7 GPIO Groups and splited into 3 MACROs in atlas7. The GPIO Groups in one MACRO share one GPIO controllers, each GPIO Group are treated as one GPIO bank. For example: In VDIFM macro, there is one GPIO Controller, it has 3 banks to control 3 gpio groups. Its gpio name space is from 0 to 95. The Device Tree can be written as following: gpio-ranges = <&pinctrl 0 0 0>, <&pinctrl 32 0 0>, <&pinctrl 64 0 0>; gpio-ranges-group-names = "gnss_gpio_grp", "lcd_vip_gpio_grp", "sdio_i2s_gpio_grp"; bank#0 is from 0~31, the pins are from pinctrl's "gnss_gpio_grp". bank#2 is from 32~63, the pins are from pinctrl's "lcd_vip_gpio_grp". bank#3 is from 64~95, the pins are from pinctrl's "sdio_i2s_gpio_grp". Signed-off-by: Wei Chen Signed-off-by: Barry Song Signed-off-by: Linus Walleij diff --git a/Documentation/devicetree/bindings/gpio/gpio-atlas7.txt b/Documentation/devicetree/bindings/gpio/gpio-atlas7.txt new file mode 100644 index 0000000..d7e123f --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/gpio-atlas7.txt @@ -0,0 +1,50 @@ +CSR SiRFatlas7 GPIO controller bindings + +Required properties: +- compatible : "sirf,atlas7-gpio" +- reg : Address range of the pinctrl registers +- interrupts : Interrupts used by every GPIO group +- gpio-banks : How many gpio banks on this controller +- gpio-controller : Indicates this device is a GPIO controller +- interrupt-controller : Marks the device node as an interrupt controller + +The GPIO controller also acts as an interrupt controller. It uses the default +two cells specifier as described in Documentation/devicetree/bindings/ +interrupt-controller/interrupts.txt. + +Example: + + gpio_0: gpio_mediam@17040000 { + compatible = "sirf,atlas7-gpio"; + reg = <0x17040000 0x1000>; + interrupts = <0 13 0>, <0 14 0>; + + #gpio-cells = <2>; + #interrupt-cells = <2>; + + gpio-controller; + interrupt-controller; + + gpio-banks = <2>; + gpio-ranges = <&pinctrl 0 0 0>, + <&pinctrl 32 0 0>; + gpio-ranges-group-names = "lvds_gpio_grp", + "uart_nand_gpio_grp"; + }; + + leds { + compatible = "gpio-leds"; + + led1 { + gpios = <&gpio_1 15 0>; + ... + }; + + led2 { + gpios = <&gpio_2 34 0>; + ... + }; + }; + +Please refer to gpio.txt in this directory for details of the common +gpio properties used by devices. diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-atlas7.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-atlas7.txt new file mode 100644 index 0000000..eecf028 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-atlas7.txt @@ -0,0 +1,109 @@ +CSR SiRFatlas7 pinmux controller + +Required properties: +- compatible : "sirf,atlas7-ioc" +- reg : Address range of the pinctrl registers + +For example, pinctrl might have properties like the following: + pinctrl: ioc@18880000 { + compatible = "sirf,atlas7-ioc"; + reg = <0x18880000 0x1000>; + + a_ac97_pmx: ac97@0 { + ac97 { + groups = "audio_ac97_grp"; + function = "audio_ac97"; + }; + }; + + ... + + sd2_pmx: sd2@0 { + sd2 { + groups = "sd2_grp0"; + function = "sd2"; + }; + }; + + ... + + + sample0_cfg: sample0@0 { + sample0 { + pins = "ldd_0", "ldd_1"; + bias-pull-up; + }; + }; + + sample1_cfg: sample1@0 { + sample1 { + pins = "ldd_2", "ldd_3"; + input-schmitt-enable; + }; + }; + + sample2_cfg: sample2@0 { + sample2 { + groups = "uart4_nopause_grp"; + bias-pull-down; + }; + }; + + sample3_cfg: sample3@0 { + sample3 { + pins = "ldd_4", "ldd_5"; + drive-strength = <2>; + }; + }; + }; + +Please refer to pinctrl-bindings.txt in this directory for details of the common +pinctrl bindings used by client devices. + +SiRFatlas7's pinmux nodes act as a container for an abitrary number of subnodes. +Each of these subnodes represents some desired configuration for a group of pins. + +Required subnode-properties: +- groups : An array of strings. Each string contains the name of a group. +- function: A string containing the name of the function to mux to the + group. + + Valid values for group and function names can be found from looking at the + group and function arrays in driver files: + drivers/pinctrl/pinctrl-sirf.c + +For example, pinctrl might have subnodes like the following: + sd0_pmx: sd0@0 { + sd0 { + groups = "sd0_grp"; + function = "sd0"; + }; + }; + + sd1_pmx0: sd1@0 { + sd1 { + groups = "sd1_grp0"; + function = "sd1_m0"; + }; + }; + + sd1_pmx1: sd1@1 { + sd1 { + groups = "sd1_grp1"; + function = "sd1_m1"; + }; + }; + +For a specific board, if it wants to use sd1, +it can add the following to its board-specific .dts file. +sd1: sd@0x12340000 { + pinctrl-names = "default"; + pinctrl-0 = <&sd1_pmx0>; +} + +or + +sd1: sd@0x12340000 { + pinctrl-names = "default"; + pinctrl-0 = <&sd1_pmx1>; +} diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 542a12a..100d9ac 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -132,6 +132,8 @@ config PINCTRL_SIRF bool "CSR SiRFprimaII pin controller driver" depends on ARCH_SIRF select PINMUX + select PINCONF + select GENERIC_PINCONF select GPIOLIB_IRQCHIP config PINCTRL_PISTACHIO diff --git a/drivers/pinctrl/sirf/Makefile b/drivers/pinctrl/sirf/Makefile index 3ffc475..fd58e0b 100644 --- a/drivers/pinctrl/sirf/Makefile +++ b/drivers/pinctrl/sirf/Makefile @@ -3,3 +3,4 @@ obj-y += pinctrl-sirf.o obj-y += pinctrl-prima2.o obj-y += pinctrl-atlas6.o +obj-y += pinctrl-atlas7.o diff --git a/drivers/pinctrl/sirf/pinctrl-atlas7.c b/drivers/pinctrl/sirf/pinctrl-atlas7.c new file mode 100644 index 0000000..046251a --- /dev/null +++ b/drivers/pinctrl/sirf/pinctrl-atlas7.c @@ -0,0 +1,4639 @@ +/* + * pinctrl pads, groups, functions for CSR SiRFatlasVII + * + * Copyright (c) 2011 - 2014 Cambridge Silicon Radio Limited, a CSR plc group + * company. + * + * Licensed under GPLv2 or later. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Definition of Pad&Mux Properties */ +#define N 0 + +/* The Bank contains input-disable regisgers */ +#define BANK_DS 0 + +/* Clear Register offset */ +#define CLR_REG(r) ((r) + 0x04) + +/* Definition of multiple function select register */ +#define FUNC_CLEAR_MASK 0x7 +#define FUNC_GPIO 0 +#define FUNC_ANALOGUE 0x8 +#define ANA_CLEAR_MASK 0x1 + +/* The Atlas7's Pad Type List */ +enum altas7_pad_type { + PAD_T_4WE_PD = 0, /* ZIO_PAD3V_4WE_PD */ + PAD_T_4WE_PU, /* ZIO_PAD3V_4WE_PD */ + PAD_T_16ST, /* ZIO_PAD3V_SDCLK_PD */ + PAD_T_M31_0204_PD, /* PRDW0204SDGZ_M311311_PD */ + PAD_T_M31_0204_PU, /* PRDW0204SDGZ_M311311_PU */ + PAD_T_M31_0610_PD, /* PRUW0610SDGZ_M311311_PD */ + PAD_T_M31_0610_PU, /* PRUW0610SDGZ_M311311_PU */ + PAD_T_AD, /* PRDWUWHW08SCDG_HZ */ +}; + +/* Raw value of Driver-Strength Bits */ +#define DS3 BIT(3) +#define DS2 BIT(2) +#define DS1 BIT(1) +#define DS0 BIT(0) +#define DSZ 0 + +/* Drive-Strength Intermediate Values */ +#define DS_NULL -1 +#define DS_1BIT_IM_VAL DS0 +#define DS_1BIT_MASK 0x1 +#define DS_2BIT_IM_VAL (DS1 | DS0) +#define DS_2BIT_MASK 0x3 +#define DS_4BIT_IM_VAL (DS3 | DS2 | DS1 | DS0) +#define DS_4BIT_MASK 0xf + +/* The Drive-Strength of 4WE Pad DS1 0 CO */ +#define DS_4WE_3 (DS1 | DS0) /* 1 1 3 */ +#define DS_4WE_2 (DS1) /* 1 0 2 */ +#define DS_4WE_1 (DS0) /* 0 1 1 */ +#define DS_4WE_0 (DSZ) /* 0 0 0 */ + +/* The Drive-Strength of 16st Pad DS3 2 1 0 CO */ +#define DS_16ST_15 (DS3 | DS2 | DS1 | DS0) /* 1 1 1 1 15 */ +#define DS_16ST_14 (DS3 | DS2 | DS0) /* 1 1 0 1 13 */ +#define DS_16ST_13 (DS3 | DS2 | DS1) /* 1 1 1 0 14 */ +#define DS_16ST_12 (DS2 | DS1 | DS0) /* 0 1 1 1 7 */ +#define DS_16ST_11 (DS2 | DS0) /* 0 1 0 1 5 */ +#define DS_16ST_10 (DS3 | DS1 | DS0) /* 1 0 1 1 11 */ +#define DS_16ST_9 (DS3 | DS0) /* 1 0 0 1 9 */ +#define DS_16ST_8 (DS1 | DS0) /* 0 0 1 1 3 */ +#define DS_16ST_7 (DS2 | DS1) /* 0 1 1 0 6 */ +#define DS_16ST_6 (DS3 | DS2) /* 1 1 0 0 12 */ +#define DS_16ST_5 (DS2) /* 0 1 0 0 4 */ +#define DS_16ST_4 (DS3 | DS1) /* 1 0 1 0 10 */ +#define DS_16ST_3 (DS1) /* 0 0 1 0 2 */ +#define DS_16ST_2 (DS0) /* 0 0 0 1 1 */ +#define DS_16ST_1 (DSZ) /* 0 0 0 0 0 */ +#define DS_16ST_0 (DS3) /* 1 0 0 0 8 */ + +/* The Drive-Strength of M31 Pad DS0 CO */ +#define DS_M31_0 (DSZ) /* 0 0 */ +#define DS_M31_1 (DS0) /* 1 1 */ + +/* Raw values of Pull Option Bits */ +#define PUN BIT(1) +#define PD BIT(0) +#define PE BIT(0) +#define PZ 0 + +/* Definition of Pull Types */ +#define PULL_UP 0 +#define HIGH_HYSTERESIS 1 +#define HIGH_Z 2 +#define PULL_DOWN 3 +#define PULL_DISABLE 4 +#define PULL_ENABLE 5 +#define PULL_UNKNOWN -1 + +/* Pull Options for 4WE Pad PUN PD CO */ +#define P4WE_PULL_MASK 0x3 +#define P4WE_PULL_DOWN (PUN | PD) /* 1 1 3 */ +#define P4WE_HIGH_Z (PUN) /* 1 0 2 */ +#define P4WE_HIGH_HYSTERESIS (PD) /* 0 1 1 */ +#define P4WE_PULL_UP (PZ) /* 0 0 0 */ + +/* Pull Options for 16ST Pad PUN PD CO */ +#define P16ST_PULL_MASK 0x3 +#define P16ST_PULL_DOWN (PUN | PD) /* 1 1 3 */ +#define P16ST_HIGH_Z (PUN) /* 1 0 2 */ +#define P16ST_PULL_UP (PZ) /* 0 0 0 */ + +/* Pull Options for M31 Pad PE */ +#define PM31_PULL_MASK 0x1 +#define PM31_PULL_ENABLED (PE) /* 1 */ +#define PM31_PULL_DISABLED (PZ) /* 0 */ + +/* Pull Options for A/D Pad PUN PD CO */ +#define PANGD_PULL_MASK 0x3 +#define PANGD_PULL_DOWN (PUN | PD) /* 1 1 3 */ +#define PANGD_HIGH_Z (PUN) /* 1 0 2 */ +#define PANGD_PULL_UP (PZ) /* 0 0 0 */ + +/* Definition of Input Disable */ +#define DI_MASK 0x1 +#define DI_DISABLE 0x1 +#define DI_ENABLE 0x0 + +/* Definition of Input Disable Value */ +#define DIV_MASK 0x1 +#define DIV_DISABLE 0x1 +#define DIV_ENABLE 0x0 + +struct dt_params { + const char *property; + int value; +}; + +/** + * struct atlas7_pad_conf - Atlas7 Pad Configuration + * @id The ID of this Pad. + * @type: The type of this Pad. + * @mux_reg: The mux register offset. + * This register contains the mux. + * @pupd_reg: The pull-up/down register offset. + * @drvstr_reg: The drive-strength register offset. + * @ad_ctrl_reg: The Analogue/Digital Control register. + * + * @mux_bit: The start bit of mux register. + * @pupd_bit: The start bit of pull-up/down register. + * @drvstr_bit: The start bit of drive-strength register. + * @ad_ctrl_bit: The start bit of analogue/digital register. + */ +struct atlas7_pad_config { + const u32 id; + u32 type; + u32 mux_reg; + u32 pupd_reg; + u32 drvstr_reg; + u32 ad_ctrl_reg; + /* bits in register */ + u8 mux_bit; + u8 pupd_bit; + u8 drvstr_bit; + u8 ad_ctrl_bit; +}; + +#define PADCONF(pad, t, mr, pr, dsr, adr, mb, pb, dsb, adb) \ + { \ + .id = pad, \ + .type = t, \ + .mux_reg = mr, \ + .pupd_reg = pr, \ + .drvstr_reg = dsr, \ + .ad_ctrl_reg = adr, \ + .mux_bit = mb, \ + .pupd_bit = pb, \ + .drvstr_bit = dsb, \ + .ad_ctrl_bit = adb, \ + } + +/** + * struct atlas7_pad_mux - Atlas7 mux + * @bank: The bank of this pad's registers on. + * @pin : The ID of this Pad. + * @func: The mux func on this Pad. + * @dinput_reg: The Input-Disable register offset. + * @dinput_bit: The start bit of Input-Disable register. + * @dinput_val_reg: The Input-Disable-value register offset. + * This register is used to set the value of this pad + * if this pad was disabled. + * @dinput_val_bit: The start bit of Input-Disable Value register. + */ +struct atlas7_pad_mux { + u32 bank; + u32 pin; + u32 func; + u32 dinput_reg; + u32 dinput_bit; + u32 dinput_val_reg; + u32 dinput_val_bit; +}; + +#define MUX(b, pad, f, dr, db, dvr, dvb) \ + { \ + .bank = b, \ + .pin = pad, \ + .func = f, \ + .dinput_reg = dr, \ + .dinput_bit = db, \ + .dinput_val_reg = dvr, \ + .dinput_val_bit = dvb, \ + } + +struct atlas7_grp_mux { + unsigned int group; + unsigned int pad_mux_count; + const struct atlas7_pad_mux *pad_mux_list; +}; + + /** + * struct sirfsoc_pin_group - describes a SiRFprimaII pin group + * @name: the name of this specific pin group + * @pins: an array of discrete physical pins used in this group, taken + * from the driver-local pin enumeration space + * @num_pins: the number of pins in this group array, i.e. the number of + * elements in .pins so we can iterate over that array + */ +struct atlas7_pin_group { + const char *name; + const unsigned int *pins; + const unsigned num_pins; +}; + +#define GROUP(n, p) \ + { \ + .name = n, \ + .pins = p, \ + .num_pins = ARRAY_SIZE(p), \ + } + +struct atlas7_pmx_func { + const char *name; + const char * const *groups; + const unsigned num_groups; + const struct atlas7_grp_mux *grpmux; +}; + +#define FUNCTION(n, g, m) \ + { \ + .name = n, \ + .groups = g, \ + .num_groups = ARRAY_SIZE(g), \ + .grpmux = m, \ + } + +struct atlas7_pinctrl_data { + struct pinctrl_pin_desc *pads; + int pads_cnt; + struct atlas7_pin_group *grps; + int grps_cnt; + struct atlas7_pmx_func *funcs; + int funcs_cnt; + struct atlas7_pad_config *confs; + int confs_cnt; +}; + +/* Platform info of atlas7 pinctrl */ +#define ATLAS7_PINCTRL_REG_BANKS 2 +#define ATLAS7_PINCTRL_BANK_0_PINS 18 + +/** + * Atlas7 GPIO Chip + */ + +#define NGPIO_OF_BANK 32 +#define GPIO_TO_BANK(gpio) ((gpio) / NGPIO_OF_BANK) + +/* Registers of GPIO Controllers */ +#define ATLAS7_GPIO_BASE(g, b) ((g)->reg + 0x100 * (b)) +#define ATLAS7_GPIO_CTRL(b, i) ((b)->base + 4 * (i)) +#define ATLAS7_GPIO_INT_STATUS(b) ((b)->base + 0x8C) + +/* Definition bits of GPIO Control Registers */ +#define ATLAS7_GPIO_CTL_INTR_LOW_MASK BIT(0) +#define ATLAS7_GPIO_CTL_INTR_HIGH_MASK BIT(1) +#define ATLAS7_GPIO_CTL_INTR_TYPE_MASK BIT(2) +#define ATLAS7_GPIO_CTL_INTR_EN_MASK BIT(3) +#define ATLAS7_GPIO_CTL_INTR_STATUS_MASK BIT(4) +#define ATLAS7_GPIO_CTL_OUT_EN_MASK BIT(5) +#define ATLAS7_GPIO_CTL_DATAOUT_MASK BIT(6) +#define ATLAS7_GPIO_CTL_DATAIN_MASK BIT(7) + +struct atlas7_gpio_bank { + struct pinctrl_dev *pctldev; + int id; + int irq; + void __iomem *base; + unsigned int gpio_offset; + unsigned int ngpio; + const unsigned int *gpio_pins; +}; + +struct atlas7_gpio_chip { + const char *name; + void __iomem *reg; + struct clk *clk; + int nbank; + spinlock_t lock; + struct gpio_chip chip; + struct atlas7_gpio_bank banks[0]; +}; + +static inline struct atlas7_gpio_chip *to_atlas7_gpio(struct gpio_chip *gc) +{ + return container_of(gc, struct atlas7_gpio_chip, chip); +} + +/** + * @dev: a pointer back to containing device + * @virtbase: the offset to the controller in virtual memory + */ +struct atlas7_pmx { + struct device *dev; + struct pinctrl_dev *pctl; + struct pinctrl_desc pctl_desc; + struct atlas7_pinctrl_data *pctl_data; + void __iomem *regs[ATLAS7_PINCTRL_REG_BANKS]; +}; + +/* + * Pad list for the pinmux subsystem + * refer to A7DA IO Summary - CS-314158-DD-4E.xls + */ + +/*Pads in IOC RTC & TOP */ +static const struct pinctrl_pin_desc atlas7_ioc_pads[] = { + /* RTC PADs */ + PINCTRL_PIN(0, "rtc_gpio_0"), + PINCTRL_PIN(1, "rtc_gpio_1"), + PINCTRL_PIN(2, "rtc_gpio_2"), + PINCTRL_PIN(3, "rtc_gpio_3"), + PINCTRL_PIN(4, "low_bat_ind_b"), + PINCTRL_PIN(5, "on_key_b"), + PINCTRL_PIN(6, "ext_on"), + PINCTRL_PIN(7, "mem_on"), + PINCTRL_PIN(8, "core_on"), + PINCTRL_PIN(9, "io_on"), + PINCTRL_PIN(10, "can0_tx"), + PINCTRL_PIN(11, "can0_rx"), + PINCTRL_PIN(12, "spi0_clk"), + PINCTRL_PIN(13, "spi0_cs_b"), + PINCTRL_PIN(14, "spi0_io_0"), + PINCTRL_PIN(15, "spi0_io_1"), + PINCTRL_PIN(16, "spi0_io_2"), + PINCTRL_PIN(17, "spi0_io_3"), + + /* TOP PADs */ + PINCTRL_PIN(18, "spi1_en"), + PINCTRL_PIN(19, "spi1_clk"), + PINCTRL_PIN(20, "spi1_din"), + PINCTRL_PIN(21, "spi1_dout"), + PINCTRL_PIN(22, "trg_spi_clk"), + PINCTRL_PIN(23, "trg_spi_di"), + PINCTRL_PIN(24, "trg_spi_do"), + PINCTRL_PIN(25, "trg_spi_cs_b"), + PINCTRL_PIN(26, "trg_acq_d1"), + PINCTRL_PIN(27, "trg_irq_b"), + PINCTRL_PIN(28, "trg_acq_d0"), + PINCTRL_PIN(29, "trg_acq_clk"), + PINCTRL_PIN(30, "trg_shutdown_b_out"), + PINCTRL_PIN(31, "sdio2_clk"), + PINCTRL_PIN(32, "sdio2_cmd"), + PINCTRL_PIN(33, "sdio2_dat_0"), + PINCTRL_PIN(34, "sdio2_dat_1"), + PINCTRL_PIN(35, "sdio2_dat_2"), + PINCTRL_PIN(36, "sdio2_dat_3"), + PINCTRL_PIN(37, "df_ad_7"), + PINCTRL_PIN(38, "df_ad_6"), + PINCTRL_PIN(39, "df_ad_5"), + PINCTRL_PIN(40, "df_ad_4"), + PINCTRL_PIN(41, "df_ad_3"), + PINCTRL_PIN(42, "df_ad_2"), + PINCTRL_PIN(43, "df_ad_1"), + PINCTRL_PIN(44, "df_ad_0"), + PINCTRL_PIN(45, "df_dqs"), + PINCTRL_PIN(46, "df_cle"), + PINCTRL_PIN(47, "df_ale"), + PINCTRL_PIN(48, "df_we_b"), + PINCTRL_PIN(49, "df_re_b"), + PINCTRL_PIN(50, "df_ry_by"), + PINCTRL_PIN(51, "df_cs_b_1"), + PINCTRL_PIN(52, "df_cs_b_0"), + PINCTRL_PIN(53, "l_pclk"), + PINCTRL_PIN(54, "l_lck"), + PINCTRL_PIN(55, "l_fck"), + PINCTRL_PIN(56, "l_de"), + PINCTRL_PIN(57, "ldd_0"), + PINCTRL_PIN(58, "ldd_1"), + PINCTRL_PIN(59, "ldd_2"), + PINCTRL_PIN(60, "ldd_3"), + PINCTRL_PIN(61, "ldd_4"), + PINCTRL_PIN(62, "ldd_5"), + PINCTRL_PIN(63, "ldd_6"), + PINCTRL_PIN(64, "ldd_7"), + PINCTRL_PIN(65, "ldd_8"), + PINCTRL_PIN(66, "ldd_9"), + PINCTRL_PIN(67, "ldd_10"), + PINCTRL_PIN(68, "ldd_11"), + PINCTRL_PIN(69, "ldd_12"), + PINCTRL_PIN(70, "ldd_13"), + PINCTRL_PIN(71, "ldd_14"), + PINCTRL_PIN(72, "ldd_15"), + PINCTRL_PIN(73, "lcd_gpio_20"), + PINCTRL_PIN(74, "vip_0"), + PINCTRL_PIN(75, "vip_1"), + PINCTRL_PIN(76, "vip_2"), + PINCTRL_PIN(77, "vip_3"), + PINCTRL_PIN(78, "vip_4"), + PINCTRL_PIN(79, "vip_5"), + PINCTRL_PIN(80, "vip_6"), + PINCTRL_PIN(81, "vip_7"), + PINCTRL_PIN(82, "vip_pxclk"), + PINCTRL_PIN(83, "vip_hsync"), + PINCTRL_PIN(84, "vip_vsync"), + PINCTRL_PIN(85, "sdio3_clk"), + PINCTRL_PIN(86, "sdio3_cmd"), + PINCTRL_PIN(87, "sdio3_dat_0"), + PINCTRL_PIN(88, "sdio3_dat_1"), + PINCTRL_PIN(89, "sdio3_dat_2"), + PINCTRL_PIN(90, "sdio3_dat_3"), + PINCTRL_PIN(91, "sdio5_clk"), + PINCTRL_PIN(92, "sdio5_cmd"), + PINCTRL_PIN(93, "sdio5_dat_0"), + PINCTRL_PIN(94, "sdio5_dat_1"), + PINCTRL_PIN(95, "sdio5_dat_2"), + PINCTRL_PIN(96, "sdio5_dat_3"), + PINCTRL_PIN(97, "rgmii_txd_0"), + PINCTRL_PIN(98, "rgmii_txd_1"), + PINCTRL_PIN(99, "rgmii_txd_2"), + PINCTRL_PIN(100, "rgmii_txd_3"), + PINCTRL_PIN(101, "rgmii_txclk"), + PINCTRL_PIN(102, "rgmii_tx_ctl"), + PINCTRL_PIN(103, "rgmii_rxd_0"), + PINCTRL_PIN(104, "rgmii_rxd_1"), + PINCTRL_PIN(105, "rgmii_rxd_2"), + PINCTRL_PIN(106, "rgmii_rxd_3"), + PINCTRL_PIN(107, "rgmii_rx_clk"), + PINCTRL_PIN(108, "rgmii_rxc_ctl"), + PINCTRL_PIN(109, "rgmii_mdio"), + PINCTRL_PIN(110, "rgmii_mdc"), + PINCTRL_PIN(111, "rgmii_intr_n"), + PINCTRL_PIN(112, "i2s_mclk"), + PINCTRL_PIN(113, "i2s_bclk"), + PINCTRL_PIN(114, "i2s_ws"), + PINCTRL_PIN(115, "i2s_dout0"), + PINCTRL_PIN(116, "i2s_dout1"), + PINCTRL_PIN(117, "i2s_dout2"), + PINCTRL_PIN(118, "i2s_din"), + PINCTRL_PIN(119, "gpio_0"), + PINCTRL_PIN(120, "gpio_1"), + PINCTRL_PIN(121, "gpio_2"), + PINCTRL_PIN(122, "gpio_3"), + PINCTRL_PIN(123, "gpio_4"), + PINCTRL_PIN(124, "gpio_5"), + PINCTRL_PIN(125, "gpio_6"), + PINCTRL_PIN(126, "gpio_7"), + PINCTRL_PIN(127, "sda_0"), + PINCTRL_PIN(128, "scl_0"), + PINCTRL_PIN(129, "coex_pio_0"), + PINCTRL_PIN(130, "coex_pio_1"), + PINCTRL_PIN(131, "coex_pio_2"), + PINCTRL_PIN(132, "coex_pio_3"), + PINCTRL_PIN(133, "uart0_tx"), + PINCTRL_PIN(134, "uart0_rx"), + PINCTRL_PIN(135, "uart1_tx"), + PINCTRL_PIN(136, "uart1_rx"), + PINCTRL_PIN(137, "uart3_tx"), + PINCTRL_PIN(138, "uart3_rx"), + PINCTRL_PIN(139, "uart4_tx"), + PINCTRL_PIN(140, "uart4_rx"), + PINCTRL_PIN(141, "usp0_clk"), + PINCTRL_PIN(142, "usp0_tx"), + PINCTRL_PIN(143, "usp0_rx"), + PINCTRL_PIN(144, "usp0_fs"), + PINCTRL_PIN(145, "usp1_clk"), + PINCTRL_PIN(146, "usp1_tx"), + PINCTRL_PIN(147, "usp1_rx"), + PINCTRL_PIN(148, "usp1_fs"), + PINCTRL_PIN(149, "lvds_tx0d4p"), + PINCTRL_PIN(150, "lvds_tx0d4n"), + PINCTRL_PIN(151, "lvds_tx0d3p"), + PINCTRL_PIN(152, "lvds_tx0d3n"), + PINCTRL_PIN(153, "lvds_tx0d2p"), + PINCTRL_PIN(154, "lvds_tx0d2n"), + PINCTRL_PIN(155, "lvds_tx0d1p"), + PINCTRL_PIN(156, "lvds_tx0d1n"), + PINCTRL_PIN(157, "lvds_tx0d0p"), + PINCTRL_PIN(158, "lvds_tx0d0n"), +}; + +struct atlas7_pad_config atlas7_ioc_pad_confs[] = { + /* The Configuration of IOC_RTC Pads */ + PADCONF(0, 3, 0x0, 0x100, 0x200, -1, 0, 0, 0, 0), + PADCONF(1, 3, 0x0, 0x100, 0x200, -1, 4, 2, 2, 0), + PADCONF(2, 3, 0x0, 0x100, 0x200, -1, 8, 4, 4, 0), + PADCONF(3, 5, 0x0, 0x100, 0x200, -1, 12, 6, 6, 0), + PADCONF(4, 4, 0x0, 0x100, 0x200, -1, 16, 8, 8, 0), + PADCONF(5, 4, 0x0, 0x100, 0x200, -1, 20, 10, 10, 0), + PADCONF(6, 3, 0x0, 0x100, 0x200, -1, 24, 12, 12, 0), + PADCONF(7, 3, 0x0, 0x100, 0x200, -1, 28, 14, 14, 0), + PADCONF(8, 3, 0x8, 0x100, 0x200, -1, 0, 16, 16, 0), + PADCONF(9, 3, 0x8, 0x100, 0x200, -1, 4, 18, 18, 0), + PADCONF(10, 4, 0x8, 0x100, 0x200, -1, 8, 20, 20, 0), + PADCONF(11, 4, 0x8, 0x100, 0x200, -1, 12, 22, 22, 0), + PADCONF(12, 5, 0x8, 0x100, 0x200, -1, 16, 24, 24, 0), + PADCONF(13, 6, 0x8, 0x100, 0x200, -1, 20, 26, 26, 0), + PADCONF(14, 5, 0x8, 0x100, 0x200, -1, 24, 28, 28, 0), + PADCONF(15, 5, 0x8, 0x100, 0x200, -1, 28, 30, 30, 0), + PADCONF(16, 5, 0x10, 0x108, 0x208, -1, 0, 0, 0, 0), + PADCONF(17, 5, 0x10, 0x108, 0x208, -1, 4, 2, 2, 0), + /* The Configuration of IOC_TOP Pads */ + PADCONF(18, 5, 0x80, 0x180, 0x300, -1, 0, 0, 0, 0), + PADCONF(19, 5, 0x80, 0x180, 0x300, -1, 4, 2, 2, 0), + PADCONF(20, 5, 0x80, 0x180, 0x300, -1, 8, 4, 4, 0), + PADCONF(21, 5, 0x80, 0x180, 0x300, -1, 12, 6, 6, 0), + PADCONF(22, 5, 0x88, 0x188, 0x308, -1, 0, 0, 0, 0), + PADCONF(23, 5, 0x88, 0x188, 0x308, -1, 4, 2, 2, 0), + PADCONF(24, 5, 0x88, 0x188, 0x308, -1, 8, 4, 4, 0), + PADCONF(25, 6, 0x88, 0x188, 0x308, -1, 12, 6, 6, 0), + PADCONF(26, 5, 0x88, 0x188, 0x308, -1, 16, 8, 8, 0), + PADCONF(27, 6, 0x88, 0x188, 0x308, -1, 20, 10, 10, 0), + PADCONF(28, 5, 0x88, 0x188, 0x308, -1, 24, 12, 12, 0), + PADCONF(29, 5, 0x88, 0x188, 0x308, -1, 28, 14, 14, 0), + PADCONF(30, 5, 0x90, 0x188, 0x308, -1, 0, 16, 16, 0), + PADCONF(31, 2, 0x98, 0x190, 0x310, -1, 0, 0, 0, 0), + PADCONF(32, 1, 0x98, 0x190, 0x310, -1, 4, 2, 4, 0), + PADCONF(33, 1, 0x98, 0x190, 0x310, -1, 8, 4, 6, 0), + PADCONF(34, 1, 0x98, 0x190, 0x310, -1, 12, 6, 8, 0), + PADCONF(35, 1, 0x98, 0x190, 0x310, -1, 16, 8, 10, 0), + PADCONF(36, 1, 0x98, 0x190, 0x310, -1, 20, 10, 12, 0), + PADCONF(37, 1, 0xa0, 0x198, 0x318, -1, 0, 0, 0, 0), + PADCONF(38, 1, 0xa0, 0x198, 0x318, -1, 4, 2, 2, 0), + PADCONF(39, 1, 0xa0, 0x198, 0x318, -1, 8, 4, 4, 0), + PADCONF(40, 1, 0xa0, 0x198, 0x318, -1, 12, 6, 6, 0), + PADCONF(41, 1, 0xa0, 0x198, 0x318, -1, 16, 8, 8, 0), + PADCONF(42, 1, 0xa0, 0x198, 0x318, -1, 20, 10, 10, 0), + PADCONF(43, 1, 0xa0, 0x198, 0x318, -1, 24, 12, 12, 0), + PADCONF(44, 1, 0xa0, 0x198, 0x318, -1, 28, 14, 14, 0), + PADCONF(45, 0, 0xa8, 0x198, 0x318, -1, 0, 16, 16, 0), + PADCONF(46, 0, 0xa8, 0x198, 0x318, -1, 4, 18, 18, 0), + PADCONF(47, 1, 0xa8, 0x198, 0x318, -1, 8, 20, 20, 0), + PADCONF(48, 1, 0xa8, 0x198, 0x318, -1, 12, 22, 22, 0), + PADCONF(49, 1, 0xa8, 0x198, 0x318, -1, 16, 24, 24, 0), + PADCONF(50, 1, 0xa8, 0x198, 0x318, -1, 20, 26, 26, 0), + PADCONF(51, 1, 0xa8, 0x198, 0x318, -1, 24, 28, 28, 0), + PADCONF(52, 1, 0xa8, 0x198, 0x318, -1, 28, 30, 30, 0), + PADCONF(53, 0, 0xb0, 0x1a0, 0x320, -1, 0, 0, 0, 0), + PADCONF(54, 0, 0xb0, 0x1a0, 0x320, -1, 4, 2, 2, 0), + PADCONF(55, 0, 0xb0, 0x1a0, 0x320, -1, 8, 4, 4, 0), + PADCONF(56, 0, 0xb0, 0x1a0, 0x320, -1, 12, 6, 6, 0), + PADCONF(57, 0, 0xb0, 0x1a0, 0x320, -1, 16, 8, 8, 0), + PADCONF(58, 0, 0xb0, 0x1a0, 0x320, -1, 20, 10, 10, 0), + PADCONF(59, 0, 0xb0, 0x1a0, 0x320, -1, 24, 12, 12, 0), + PADCONF(60, 0, 0xb0, 0x1a0, 0x320, -1, 28, 14, 14, 0), + PADCONF(61, 0, 0xb8, 0x1a0, 0x320, -1, 0, 16, 16, 0), + PADCONF(62, 0, 0xb8, 0x1a0, 0x320, -1, 4, 18, 18, 0), + PADCONF(63, 0, 0xb8, 0x1a0, 0x320, -1, 8, 20, 20, 0), + PADCONF(64, 0, 0xb8, 0x1a0, 0x320, -1, 12, 22, 22, 0), + PADCONF(65, 0, 0xb8, 0x1a0, 0x320, -1, 16, 24, 24, 0), + PADCONF(66, 0, 0xb8, 0x1a0, 0x320, -1, 20, 26, 26, 0), + PADCONF(67, 0, 0xb8, 0x1a0, 0x320, -1, 24, 28, 28, 0), + PADCONF(68, 0, 0xb8, 0x1a0, 0x320, -1, 28, 30, 30, 0), + PADCONF(69, 0, 0xc0, 0x1a8, 0x328, -1, 0, 0, 0, 0), + PADCONF(70, 0, 0xc0, 0x1a8, 0x328, -1, 4, 2, 2, 0), + PADCONF(71, 0, 0xc0, 0x1a8, 0x328, -1, 8, 4, 4, 0), + PADCONF(72, 0, 0xc0, 0x1a8, 0x328, -1, 12, 6, 6, 0), + PADCONF(73, 0, 0xc0, 0x1a8, 0x328, -1, 16, 8, 8, 0), + PADCONF(74, 0, 0xc8, 0x1b0, 0x330, -1, 0, 0, 0, 0), + PADCONF(75, 0, 0xc8, 0x1b0, 0x330, -1, 4, 2, 2, 0), + PADCONF(76, 0, 0xc8, 0x1b0, 0x330, -1, 8, 4, 4, 0), + PADCONF(77, 0, 0xc8, 0x1b0, 0x330, -1, 12, 6, 6, 0), + PADCONF(78, 0, 0xc8, 0x1b0, 0x330, -1, 16, 8, 8, 0), + PADCONF(79, 0, 0xc8, 0x1b0, 0x330, -1, 20, 10, 10, 0), + PADCONF(80, 0, 0xc8, 0x1b0, 0x330, -1, 24, 12, 12, 0), + PADCONF(81, 0, 0xc8, 0x1b0, 0x330, -1, 28, 14, 14, 0), + PADCONF(82, 0, 0xd0, 0x1b0, 0x330, -1, 0, 16, 16, 0), + PADCONF(83, 0, 0xd0, 0x1b0, 0x330, -1, 4, 18, 18, 0), + PADCONF(84, 0, 0xd0, 0x1b0, 0x330, -1, 8, 20, 20, 0), + PADCONF(85, 2, 0xd8, 0x1b8, 0x338, -1, 0, 0, 0, 0), + PADCONF(86, 1, 0xd8, 0x1b8, 0x338, -1, 4, 4, 4, 0), + PADCONF(87, 1, 0xd8, 0x1b8, 0x338, -1, 8, 6, 6, 0), + PADCONF(88, 1, 0xd8, 0x1b8, 0x338, -1, 12, 8, 8, 0), + PADCONF(89, 1, 0xd8, 0x1b8, 0x338, -1, 16, 10, 10, 0), + PADCONF(90, 1, 0xd8, 0x1b8, 0x338, -1, 20, 12, 12, 0), + PADCONF(91, 2, 0xe0, 0x1c0, 0x340, -1, 0, 0, 0, 0), + PADCONF(92, 1, 0xe0, 0x1c0, 0x340, -1, 4, 4, 4, 0), + PADCONF(93, 1, 0xe0, 0x1c0, 0x340, -1, 8, 6, 6, 0), + PADCONF(94, 1, 0xe0, 0x1c0, 0x340, -1, 12, 8, 8, 0), + PADCONF(95, 1, 0xe0, 0x1c0, 0x340, -1, 16, 10, 10, 0), + PADCONF(96, 1, 0xe0, 0x1c0, 0x340, -1, 20, 12, 12, 0), + PADCONF(97, 0, 0xe8, 0x1c8, 0x348, -1, 0, 0, 0, 0), + PADCONF(98, 0, 0xe8, 0x1c8, 0x348, -1, 4, 2, 2, 0), + PADCONF(99, 0, 0xe8, 0x1c8, 0x348, -1, 8, 4, 4, 0), + PADCONF(100, 0, 0xe8, 0x1c8, 0x348, -1, 12, 6, 6, 0), + PADCONF(101, 2, 0xe8, 0x1c8, 0x348, -1, 16, 8, 8, 0), + PADCONF(102, 0, 0xe8, 0x1c8, 0x348, -1, 20, 12, 12, 0), + PADCONF(103, 0, 0xe8, 0x1c8, 0x348, -1, 24, 14, 14, 0), + PADCONF(104, 0, 0xe8, 0x1c8, 0x348, -1, 28, 16, 16, 0), + PADCONF(105, 0, 0xf0, 0x1c8, 0x348, -1, 0, 18, 18, 0), + PADCONF(106, 0, 0xf0, 0x1c8, 0x348, -1, 4, 20, 20, 0), + PADCONF(107, 0, 0xf0, 0x1c8, 0x348, -1, 8, 22, 22, 0), + PADCONF(108, 0, 0xf0, 0x1c8, 0x348, -1, 12, 24, 24, 0), + PADCONF(109, 1, 0xf0, 0x1c8, 0x348, -1, 16, 26, 26, 0), + PADCONF(110, 0, 0xf0, 0x1c8, 0x348, -1, 20, 28, 28, 0), + PADCONF(111, 1, 0xf0, 0x1c8, 0x348, -1, 24, 30, 30, 0), + PADCONF(112, 5, 0xf8, 0x200, 0x350, -1, 0, 0, 0, 0), + PADCONF(113, 5, 0xf8, 0x200, 0x350, -1, 4, 2, 2, 0), + PADCONF(114, 5, 0xf8, 0x200, 0x350, -1, 8, 4, 4, 0), + PADCONF(115, 5, 0xf8, 0x200, 0x350, -1, 12, 6, 6, 0), + PADCONF(116, 5, 0xf8, 0x200, 0x350, -1, 16, 8, 8, 0), + PADCONF(117, 5, 0xf8, 0x200, 0x350, -1, 20, 10, 10, 0), + PADCONF(118, 5, 0xf8, 0x200, 0x350, -1, 24, 12, 12, 0), + PADCONF(119, 5, 0x100, 0x250, 0x358, -1, 0, 0, 0, 0), + PADCONF(120, 5, 0x100, 0x250, 0x358, -1, 4, 2, 2, 0), + PADCONF(121, 5, 0x100, 0x250, 0x358, -1, 8, 4, 4, 0), + PADCONF(122, 5, 0x100, 0x250, 0x358, -1, 12, 6, 6, 0), + PADCONF(123, 6, 0x100, 0x250, 0x358, -1, 16, 8, 8, 0), + PADCONF(124, 6, 0x100, 0x250, 0x358, -1, 20, 10, 10, 0), + PADCONF(125, 6, 0x100, 0x250, 0x358, -1, 24, 12, 12, 0), + PADCONF(126, 6, 0x100, 0x250, 0x358, -1, 28, 14, 14, 0), + PADCONF(127, 6, 0x108, 0x250, 0x358, -1, 16, 24, 24, 0), + PADCONF(128, 6, 0x108, 0x250, 0x358, -1, 20, 26, 26, 0), + PADCONF(129, 0, 0x110, 0x258, 0x360, -1, 0, 0, 0, 0), + PADCONF(130, 0, 0x110, 0x258, 0x360, -1, 4, 2, 2, 0), + PADCONF(131, 0, 0x110, 0x258, 0x360, -1, 8, 4, 4, 0), + PADCONF(132, 0, 0x110, 0x258, 0x360, -1, 12, 6, 6, 0), + PADCONF(133, 6, 0x118, 0x260, 0x368, -1, 0, 0, 0, 0), + PADCONF(134, 6, 0x118, 0x260, 0x368, -1, 4, 2, 2, 0), + PADCONF(135, 6, 0x118, 0x260, 0x368, -1, 16, 8, 8, 0), + PADCONF(136, 6, 0x118, 0x260, 0x368, -1, 20, 10, 10, 0), + PADCONF(137, 6, 0x118, 0x260, 0x368, -1, 24, 12, 12, 0), + PADCONF(138, 6, 0x118, 0x260, 0x368, -1, 28, 14, 14, 0), + PADCONF(139, 6, 0x120, 0x260, 0x368, -1, 0, 16, 16, 0), + PADCONF(140, 6, 0x120, 0x260, 0x368, -1, 4, 18, 18, 0), + PADCONF(141, 5, 0x128, 0x268, 0x378, -1, 0, 0, 0, 0), + PADCONF(142, 5, 0x128, 0x268, 0x378, -1, 4, 2, 2, 0), + PADCONF(143, 5, 0x128, 0x268, 0x378, -1, 8, 4, 4, 0), + PADCONF(144, 5, 0x128, 0x268, 0x378, -1, 12, 6, 6, 0), + PADCONF(145, 5, 0x128, 0x268, 0x378, -1, 16, 8, 8, 0), + PADCONF(146, 5, 0x128, 0x268, 0x378, -1, 20, 10, 10, 0), + PADCONF(147, 5, 0x128, 0x268, 0x378, -1, 24, 12, 12, 0), + PADCONF(148, 5, 0x128, 0x268, 0x378, -1, 28, 14, 14, 0), + PADCONF(149, 7, 0x130, 0x270, -1, 0x480, 0, 0, 0, 0), + PADCONF(150, 7, 0x130, 0x270, -1, 0x480, 4, 2, 0, 1), + PADCONF(151, 7, 0x130, 0x270, -1, 0x480, 8, 4, 0, 2), + PADCONF(152, 7, 0x130, 0x270, -1, 0x480, 12, 6, 0, 3), + PADCONF(153, 7, 0x130, 0x270, -1, 0x480, 16, 8, 0, 4), + PADCONF(154, 7, 0x130, 0x270, -1, 0x480, 20, 10, 0, 5), + PADCONF(155, 7, 0x130, 0x270, -1, 0x480, 24, 12, 0, 6), + PADCONF(156, 7, 0x130, 0x270, -1, 0x480, 28, 14, 0, 7), + PADCONF(157, 7, 0x138, 0x278, -1, 0x480, 0, 0, 0, 8), + PADCONF(158, 7, 0x138, 0x278, -1, 0x480, 4, 2, 0, 9), +}; + +/* pin list of each pin group */ +static const unsigned int gnss_gpio_pins[] = { 119, 120, 121, 122, 123, 124, + 125, 126, 127, 128, 22, 23, 24, 25, 26, 27, 28, 29, 30, }; +static const unsigned int lcd_vip_gpio_pins[] = { 74, 75, 76, 77, 78, 79, 80, + 81, 82, 83, 84, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, + 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, }; +static const unsigned int sdio_i2s_gpio_pins[] = { 31, 32, 33, 34, 35, 36, + 85, 86, 87, 88, 89, 90, 129, 130, 131, 132, 91, 92, 93, 94, + 95, 96, 112, 113, 114, 115, 116, 117, 118, }; +static const unsigned int sp_rgmii_gpio_pins[] = { 97, 98, 99, 100, 101, 102, + 103, 104, 105, 106, 107, 108, 109, 110, 111, 18, 19, 20, 21, + 141, 142, 143, 144, 145, 146, 147, 148, }; +static const unsigned int lvds_gpio_pins[] = { 157, 158, 155, 156, 153, 154, + 151, 152, 149, 150, }; +static const unsigned int uart_nand_gpio_pins[] = { 44, 43, 42, 41, 40, 39, + 38, 37, 46, 47, 48, 49, 50, 52, 51, 45, 133, 134, 135, 136, + 137, 138, 139, 140, }; +static const unsigned int rtc_gpio_pins[] = { 0, 1, 2, 3, 4, 10, 11, 12, 13, + 14, 15, 16, 17, }; +static const unsigned int audio_ac97_pins[] = { 113, 118, 115, 114, }; +static const unsigned int audio_func_dbg_pins[] = { 141, 144, 44, 43, 42, 41, + 40, 39, 38, 37, 74, 75, 76, 77, 78, 79, 81, 113, 114, 118, + 115, 49, 50, 142, 143, 80, }; +static const unsigned int audio_i2s_pins[] = { 118, 115, 116, 117, 112, 113, + 114, }; +static const unsigned int audio_i2s_2ch_pins[] = { 118, 115, 112, 113, 114, }; +static const unsigned int audio_i2s_extclk_pins[] = { 112, }; +static const unsigned int audio_uart0_pins[] = { 143, 142, 141, 144, }; +static const unsigned int audio_uart1_pins[] = { 147, 146, 145, 148, }; +static const unsigned int audio_uart2_pins0[] = { 20, 21, 19, 18, }; +static const unsigned int audio_uart2_pins1[] = { 109, 110, 101, 111, }; +static const unsigned int c_can_trnsvr_pins[] = { 1, }; +static const unsigned int c0_can_pins0[] = { 11, 10, }; +static const unsigned int c0_can_pins1[] = { 2, 3, }; +static const unsigned int c1_can_pins0[] = { 138, 137, }; +static const unsigned int c1_can_pins1[] = { 147, 146, }; +static const unsigned int c1_can_pins2[] = { 2, 3, }; +static const unsigned int ca_audio_lpc_pins[] = { 62, 63, 64, 65, 66, 67, 68, + 69, 70, 71, }; +static const unsigned int ca_bt_lpc_pins[] = { 85, 86, 87, 88, 89, 90, }; +static const unsigned int ca_coex_pins[] = { 129, 130, 131, 132, }; +static const unsigned int ca_curator_lpc_pins[] = { 57, 58, 59, 60, }; +static const unsigned int ca_pcm_debug_pins[] = { 91, 93, 94, 92, }; +static const unsigned int ca_pio_pins[] = { 121, 122, 125, 126, 38, 37, 47, + 49, 50, 54, 55, 56, }; +static const unsigned int ca_sdio_debug_pins[] = { 40, 39, 44, 43, 42, 41, }; +static const unsigned int ca_spi_pins[] = { 82, 79, 80, 81, }; +static const unsigned int ca_trb_pins[] = { 91, 93, 94, 95, 96, 78, 74, 75, + 76, 77, }; +static const unsigned int ca_uart_debug_pins[] = { 136, 135, 134, 133, }; +static const unsigned int clkc_pins0[] = { 30, 47, }; +static const unsigned int clkc_pins1[] = { 78, 54, }; +static const unsigned int gn_gnss_i2c_pins[] = { 128, 127, }; +static const unsigned int gn_gnss_uart_nopause_pins[] = { 134, 133, }; +static const unsigned int gn_gnss_uart_pins[] = { 134, 133, 136, 135, }; +static const unsigned int gn_trg_spi_pins0[] = { 22, 25, 23, 24, }; +static const unsigned int gn_trg_spi_pins1[] = { 82, 79, 80, 81, }; +static const unsigned int cvbs_dbg_pins[] = { 54, 53, 82, 74, 75, 76, 77, 78, + 79, 80, 81, 83, 84, 73, 55, 56, }; +static const unsigned int cvbs_dbg_test_pins0[] = { 57, }; +static const unsigned int cvbs_dbg_test_pins1[] = { 58, }; +static const unsigned int cvbs_dbg_test_pins2[] = { 59, }; +static const unsigned int cvbs_dbg_test_pins3[] = { 60, }; +static const unsigned int cvbs_dbg_test_pins4[] = { 61, }; +static const unsigned int cvbs_dbg_test_pins5[] = { 62, }; +static const unsigned int cvbs_dbg_test_pins6[] = { 63, }; +static const unsigned int cvbs_dbg_test_pins7[] = { 64, }; +static const unsigned int cvbs_dbg_test_pins8[] = { 65, }; +static const unsigned int cvbs_dbg_test_pins9[] = { 66, }; +static const unsigned int cvbs_dbg_test_pins10[] = { 67, }; +static const unsigned int cvbs_dbg_test_pins11[] = { 68, }; +static const unsigned int cvbs_dbg_test_pins12[] = { 69, }; +static const unsigned int cvbs_dbg_test_pins13[] = { 70, }; +static const unsigned int cvbs_dbg_test_pins14[] = { 71, }; +static const unsigned int cvbs_dbg_test_pins15[] = { 72, }; +static const unsigned int gn_gnss_power_pins[] = { 123, 124, 121, 122, 125, + 120, }; +static const unsigned int gn_gnss_sw_status_pins[] = { 57, 58, 59, 60, 61, + 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 53, 55, 56, 54, }; +static const unsigned int gn_gnss_eclk_pins[] = { 113, }; +static const unsigned int gn_gnss_irq1_pins0[] = { 112, }; +static const unsigned int gn_gnss_irq2_pins0[] = { 118, }; +static const unsigned int gn_gnss_tm_pins[] = { 115, }; +static const unsigned int gn_gnss_tsync_pins[] = { 114, }; +static const unsigned int gn_io_gnsssys_sw_cfg_pins[] = { 44, 43, 42, 41, 40, + 39, 38, 37, 49, 50, 91, 92, 93, 94, 95, 96, }; +static const unsigned int gn_trg_pins0[] = { 29, 28, 26, 27, }; +static const unsigned int gn_trg_pins1[] = { 77, 76, 74, 75, }; +static const unsigned int gn_trg_shutdown_pins0[] = { 30, }; +static const unsigned int gn_trg_shutdown_pins1[] = { 83, }; +static const unsigned int gn_trg_shutdown_pins2[] = { 117, }; +static const unsigned int gn_trg_shutdown_pins3[] = { 123, }; +static const unsigned int i2c0_pins[] = { 128, 127, }; +static const unsigned int i2c1_pins[] = { 126, 125, }; +static const unsigned int jtag_pins0[] = { 125, 4, 2, 0, 1, 3, }; +static const unsigned int ks_kas_spi_pins0[] = { 141, 144, 143, 142, }; +static const unsigned int ld_ldd_pins[] = { 57, 58, 59, 60, 61, 62, 63, 64, + 65, 66, 67, 68, 69, 70, 71, 72, 74, 75, 76, 77, 78, 79, 80, + 81, 56, 53, }; +static const unsigned int ld_ldd_16bit_pins[] = { 57, 58, 59, 60, 61, 62, 63, + 64, 65, 66, 67, 68, 69, 70, 71, 72, 56, 53, }; +static const unsigned int ld_ldd_fck_pins[] = { 55, }; +static const unsigned int ld_ldd_lck_pins[] = { 54, }; +static const unsigned int lr_lcdrom_pins[] = { 73, 54, 57, 58, 59, 60, 61, + 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 56, 53, 55, }; +static const unsigned int lvds_analog_pins[] = { 149, 150, 151, 152, 153, 154, + 155, 156, 157, 158, }; +static const unsigned int nd_df_pins[] = { 44, 43, 42, 41, 40, 39, 38, 37, + 47, 46, 52, 51, 45, 49, 50, 48, 124, }; +static const unsigned int nd_df_nowp_pins[] = { 44, 43, 42, 41, 40, 39, 38, + 37, 47, 46, 52, 51, 45, 49, 50, 48, }; +static const unsigned int ps_pins[] = { 120, 119, }; +static const unsigned int pwc_core_on_pins[] = { 8, }; +static const unsigned int pwc_ext_on_pins[] = { 6, }; +static const unsigned int pwc_gpio3_clk_pins[] = { 3, }; +static const unsigned int pwc_io_on_pins[] = { 9, }; +static const unsigned int pwc_lowbatt_b_pins0[] = { 4, }; +static const unsigned int pwc_mem_on_pins[] = { 7, }; +static const unsigned int pwc_on_key_b_pins0[] = { 5, }; +static const unsigned int pwc_wakeup_src0_pins[] = { 0, }; +static const unsigned int pwc_wakeup_src1_pins[] = { 1, }; +static const unsigned int pwc_wakeup_src2_pins[] = { 2, }; +static const unsigned int pwc_wakeup_src3_pins[] = { 3, }; +static const unsigned int pw_cko0_pins0[] = { 123, }; +static const unsigned int pw_cko0_pins1[] = { 101, }; +static const unsigned int pw_cko0_pins2[] = { 82, }; +static const unsigned int pw_cko1_pins0[] = { 124, }; +static const unsigned int pw_cko1_pins1[] = { 110, }; +static const unsigned int pw_i2s01_clk_pins0[] = { 125, }; +static const unsigned int pw_i2s01_clk_pins1[] = { 117, }; +static const unsigned int pw_pwm0_pins[] = { 119, }; +static const unsigned int pw_pwm1_pins[] = { 120, }; +static const unsigned int pw_pwm2_pins0[] = { 121, }; +static const unsigned int pw_pwm2_pins1[] = { 98, }; +static const unsigned int pw_pwm3_pins0[] = { 122, }; +static const unsigned int pw_pwm3_pins1[] = { 73, }; +static const unsigned int pw_pwm_cpu_vol_pins0[] = { 121, }; +static const unsigned int pw_pwm_cpu_vol_pins1[] = { 98, }; +static const unsigned int pw_backlight_pins0[] = { 122, }; +static const unsigned int pw_backlight_pins1[] = { 73, }; +static const unsigned int rg_eth_mac_pins[] = { 108, 103, 104, 105, 106, 107, + 102, 97, 98, 99, 100, 101, }; +static const unsigned int rg_gmac_phy_intr_n_pins[] = { 111, }; +static const unsigned int rg_rgmii_mac_pins[] = { 109, 110, }; +static const unsigned int rg_rgmii_phy_ref_clk_pins0[] = { 111, }; +static const unsigned int rg_rgmii_phy_ref_clk_pins1[] = { 53, }; +static const unsigned int sd0_pins[] = { 46, 47, 44, 43, 42, 41, 40, 39, 38, + 37, }; +static const unsigned int sd0_4bit_pins[] = { 46, 47, 44, 43, 42, 41, }; +static const unsigned int sd1_pins[] = { 48, 49, 44, 43, 42, 41, 40, 39, 38, + 37, }; +static const unsigned int sd1_4bit_pins0[] = { 48, 49, 44, 43, 42, 41, }; +static const unsigned int sd1_4bit_pins1[] = { 48, 49, 40, 39, 38, 37, }; +static const unsigned int sd2_pins0[] = { 124, 31, 32, 33, 34, 35, 36, 123, }; +static const unsigned int sd2_no_cdb_pins0[] = { 31, 32, 33, 34, 35, 36, 123, }; +static const unsigned int sd3_pins[] = { 85, 86, 87, 88, 89, 90, }; +static const unsigned int sd5_pins[] = { 91, 92, 93, 94, 95, 96, }; +static const unsigned int sd6_pins0[] = { 79, 78, 74, 75, 76, 77, }; +static const unsigned int sd6_pins1[] = { 101, 99, 100, 110, 109, 111, }; +static const unsigned int sp0_ext_ldo_on_pins[] = { 4, }; +static const unsigned int sp0_qspi_pins[] = { 12, 13, 14, 15, 16, 17, }; +static const unsigned int sp1_spi_pins[] = { 19, 20, 21, 18, }; +static const unsigned int tpiu_trace_pins[] = { 53, 56, 57, 58, 59, 60, 61, + 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, }; +static const unsigned int uart0_pins[] = { 121, 120, 134, 133, }; +static const unsigned int uart0_nopause_pins[] = { 134, 133, }; +static const unsigned int uart1_pins[] = { 136, 135, }; +static const unsigned int uart2_pins[] = { 11, 10, }; +static const unsigned int uart3_pins0[] = { 125, 126, 138, 137, }; +static const unsigned int uart3_pins1[] = { 111, 109, 84, 83, }; +static const unsigned int uart3_pins2[] = { 140, 139, 138, 137, }; +static const unsigned int uart3_pins3[] = { 139, 140, 84, 83, }; +static const unsigned int uart3_nopause_pins0[] = { 138, 137, }; +static const unsigned int uart3_nopause_pins1[] = { 84, 83, }; +static const unsigned int uart4_pins0[] = { 122, 123, 140, 139, }; +static const unsigned int uart4_pins1[] = { 100, 99, 140, 139, }; +static const unsigned int uart4_pins2[] = { 117, 116, 140, 139, }; +static const unsigned int uart4_nopause_pins[] = { 140, 139, }; +static const unsigned int usb0_drvvbus_pins[] = { 51, }; +static const unsigned int usb1_drvvbus_pins[] = { 134, }; +static const unsigned int visbus_dout_pins[] = { 57, 58, 59, 60, 61, 62, 63, + 64, 65, 66, 67, 68, 69, 70, 71, 72, 53, 54, 55, 56, 85, 86, + 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, }; +static const unsigned int vi_vip1_pins[] = { 74, 75, 76, 77, 78, 79, 80, 81, + 82, 83, 84, 103, 104, 105, 106, 107, 102, 97, 98, }; +static const unsigned int vi_vip1_ext_pins[] = { 74, 75, 76, 77, 78, 79, 80, + 81, 82, 83, 84, 108, 103, 104, 105, 106, 107, 102, 97, 98, + 99, 100, }; +static const unsigned int vi_vip1_low8bit_pins[] = { 74, 75, 76, 77, 78, 79, + 80, 81, }; +static const unsigned int vi_vip1_high8bit_pins[] = { 82, 83, 84, 108, 103, + 104, 105, 106, }; + +/* definition of pin group table */ +struct atlas7_pin_group altas7_pin_groups[] = { + GROUP("gnss_gpio_grp", gnss_gpio_pins), + GROUP("lcd_vip_gpio_grp", lcd_vip_gpio_pins), + GROUP("sdio_i2s_gpio_grp", sdio_i2s_gpio_pins), + GROUP("sp_rgmii_gpio_grp", sp_rgmii_gpio_pins), + GROUP("lvds_gpio_grp", lvds_gpio_pins), + GROUP("uart_nand_gpio_grp", uart_nand_gpio_pins), + GROUP("rtc_gpio_grp", rtc_gpio_pins), + GROUP("audio_ac97_grp", audio_ac97_pins), + GROUP("audio_func_dbg_grp", audio_func_dbg_pins), + GROUP("audio_i2s_grp", audio_i2s_pins), + GROUP("audio_i2s_2ch_grp", audio_i2s_2ch_pins), + GROUP("audio_i2s_extclk_grp", audio_i2s_extclk_pins), + GROUP("audio_uart0_grp", audio_uart0_pins), + GROUP("audio_uart1_grp", audio_uart1_pins), + GROUP("audio_uart2_grp0", audio_uart2_pins0), + GROUP("audio_uart2_grp1", audio_uart2_pins1), + GROUP("c_can_trnsvr_grp", c_can_trnsvr_pins), + GROUP("c0_can_grp0", c0_can_pins0), + GROUP("c0_can_grp1", c0_can_pins1), + GROUP("c1_can_grp0", c1_can_pins0), + GROUP("c1_can_grp1", c1_can_pins1), + GROUP("c1_can_grp2", c1_can_pins2), + GROUP("ca_audio_lpc_grp", ca_audio_lpc_pins), + GROUP("ca_bt_lpc_grp", ca_bt_lpc_pins), + GROUP("ca_coex_grp", ca_coex_pins), + GROUP("ca_curator_lpc_grp", ca_curator_lpc_pins), + GROUP("ca_pcm_debug_grp", ca_pcm_debug_pins), + GROUP("ca_pio_grp", ca_pio_pins), + GROUP("ca_sdio_debug_grp", ca_sdio_debug_pins), + GROUP("ca_spi_grp", ca_spi_pins), + GROUP("ca_trb_grp", ca_trb_pins), + GROUP("ca_uart_debug_grp", ca_uart_debug_pins), + GROUP("clkc_grp0", clkc_pins0), + GROUP("clkc_grp1", clkc_pins1), + GROUP("gn_gnss_i2c_grp", gn_gnss_i2c_pins), + GROUP("gn_gnss_uart_nopause_grp", gn_gnss_uart_nopause_pins), + GROUP("gn_gnss_uart_grp", gn_gnss_uart_pins), + GROUP("gn_trg_spi_grp0", gn_trg_spi_pins0), + GROUP("gn_trg_spi_grp1", gn_trg_spi_pins1), + GROUP("cvbs_dbg_grp", cvbs_dbg_pins), + GROUP("cvbs_dbg_test_grp0", cvbs_dbg_test_pins0), + GROUP("cvbs_dbg_test_grp1", cvbs_dbg_test_pins1), + GROUP("cvbs_dbg_test_grp2", cvbs_dbg_test_pins2), + GROUP("cvbs_dbg_test_grp3", cvbs_dbg_test_pins3), + GROUP("cvbs_dbg_test_grp4", cvbs_dbg_test_pins4), + GROUP("cvbs_dbg_test_grp5", cvbs_dbg_test_pins5), + GROUP("cvbs_dbg_test_grp6", cvbs_dbg_test_pins6), + GROUP("cvbs_dbg_test_grp7", cvbs_dbg_test_pins7), + GROUP("cvbs_dbg_test_grp8", cvbs_dbg_test_pins8), + GROUP("cvbs_dbg_test_grp9", cvbs_dbg_test_pins9), + GROUP("cvbs_dbg_test_grp10", cvbs_dbg_test_pins10), + GROUP("cvbs_dbg_test_grp11", cvbs_dbg_test_pins11), + GROUP("cvbs_dbg_test_grp12", cvbs_dbg_test_pins12), + GROUP("cvbs_dbg_test_grp13", cvbs_dbg_test_pins13), + GROUP("cvbs_dbg_test_grp14", cvbs_dbg_test_pins14), + GROUP("cvbs_dbg_test_grp15", cvbs_dbg_test_pins15), + GROUP("gn_gnss_power_grp", gn_gnss_power_pins), + GROUP("gn_gnss_sw_status_grp", gn_gnss_sw_status_pins), + GROUP("gn_gnss_eclk_grp", gn_gnss_eclk_pins), + GROUP("gn_gnss_irq1_grp0", gn_gnss_irq1_pins0), + GROUP("gn_gnss_irq2_grp0", gn_gnss_irq2_pins0), + GROUP("gn_gnss_tm_grp", gn_gnss_tm_pins), + GROUP("gn_gnss_tsync_grp", gn_gnss_tsync_pins), + GROUP("gn_io_gnsssys_sw_cfg_grp", gn_io_gnsssys_sw_cfg_pins), + GROUP("gn_trg_grp0", gn_trg_pins0), + GROUP("gn_trg_grp1", gn_trg_pins1), + GROUP("gn_trg_shutdown_grp0", gn_trg_shutdown_pins0), + GROUP("gn_trg_shutdown_grp1", gn_trg_shutdown_pins1), + GROUP("gn_trg_shutdown_grp2", gn_trg_shutdown_pins2), + GROUP("gn_trg_shutdown_grp3", gn_trg_shutdown_pins3), + GROUP("i2c0_grp", i2c0_pins), + GROUP("i2c1_grp", i2c1_pins), + GROUP("jtag_grp0", jtag_pins0), + GROUP("ks_kas_spi_grp0", ks_kas_spi_pins0), + GROUP("ld_ldd_grp", ld_ldd_pins), + GROUP("ld_ldd_16bit_grp", ld_ldd_16bit_pins), + GROUP("ld_ldd_fck_grp", ld_ldd_fck_pins), + GROUP("ld_ldd_lck_grp", ld_ldd_lck_pins), + GROUP("lr_lcdrom_grp", lr_lcdrom_pins), + GROUP("lvds_analog_grp", lvds_analog_pins), + GROUP("nd_df_grp", nd_df_pins), + GROUP("nd_df_nowp_grp", nd_df_nowp_pins), + GROUP("ps_grp", ps_pins), + GROUP("pwc_core_on_grp", pwc_core_on_pins), + GROUP("pwc_ext_on_grp", pwc_ext_on_pins), + GROUP("pwc_gpio3_clk_grp", pwc_gpio3_clk_pins), + GROUP("pwc_io_on_grp", pwc_io_on_pins), + GROUP("pwc_lowbatt_b_grp0", pwc_lowbatt_b_pins0), + GROUP("pwc_mem_on_grp", pwc_mem_on_pins), + GROUP("pwc_on_key_b_grp0", pwc_on_key_b_pins0), + GROUP("pwc_wakeup_src0_grp", pwc_wakeup_src0_pins), + GROUP("pwc_wakeup_src1_grp", pwc_wakeup_src1_pins), + GROUP("pwc_wakeup_src2_grp", pwc_wakeup_src2_pins), + GROUP("pwc_wakeup_src3_grp", pwc_wakeup_src3_pins), + GROUP("pw_cko0_grp0", pw_cko0_pins0), + GROUP("pw_cko0_grp1", pw_cko0_pins1), + GROUP("pw_cko0_grp2", pw_cko0_pins2), + GROUP("pw_cko1_grp0", pw_cko1_pins0), + GROUP("pw_cko1_grp1", pw_cko1_pins1), + GROUP("pw_i2s01_clk_grp0", pw_i2s01_clk_pins0), + GROUP("pw_i2s01_clk_grp1", pw_i2s01_clk_pins1), + GROUP("pw_pwm0_grp", pw_pwm0_pins), + GROUP("pw_pwm1_grp", pw_pwm1_pins), + GROUP("pw_pwm2_grp0", pw_pwm2_pins0), + GROUP("pw_pwm2_grp1", pw_pwm2_pins1), + GROUP("pw_pwm3_grp0", pw_pwm3_pins0), + GROUP("pw_pwm3_grp1", pw_pwm3_pins1), + GROUP("pw_pwm_cpu_vol_grp0", pw_pwm_cpu_vol_pins0), + GROUP("pw_pwm_cpu_vol_grp1", pw_pwm_cpu_vol_pins1), + GROUP("pw_backlight_grp0", pw_backlight_pins0), + GROUP("pw_backlight_grp1", pw_backlight_pins1), + GROUP("rg_eth_mac_grp", rg_eth_mac_pins), + GROUP("rg_gmac_phy_intr_n_grp", rg_gmac_phy_intr_n_pins), + GROUP("rg_rgmii_mac_grp", rg_rgmii_mac_pins), + GROUP("rg_rgmii_phy_ref_clk_grp0", rg_rgmii_phy_ref_clk_pins0), + GROUP("rg_rgmii_phy_ref_clk_grp1", rg_rgmii_phy_ref_clk_pins1), + GROUP("sd0_grp", sd0_pins), + GROUP("sd0_4bit_grp", sd0_4bit_pins), + GROUP("sd1_grp", sd1_pins), + GROUP("sd1_4bit_grp0", sd1_4bit_pins0), + GROUP("sd1_4bit_grp1", sd1_4bit_pins1), + GROUP("sd2_grp0", sd2_pins0), + GROUP("sd2_no_cdb_grp0", sd2_no_cdb_pins0), + GROUP("sd3_grp", sd3_pins), + GROUP("sd5_grp", sd5_pins), + GROUP("sd6_grp0", sd6_pins0), + GROUP("sd6_grp1", sd6_pins1), + GROUP("sp0_ext_ldo_on_grp", sp0_ext_ldo_on_pins), + GROUP("sp0_qspi_grp", sp0_qspi_pins), + GROUP("sp1_spi_grp", sp1_spi_pins), + GROUP("tpiu_trace_grp", tpiu_trace_pins), + GROUP("uart0_grp", uart0_pins), + GROUP("uart0_nopause_grp", uart0_nopause_pins), + GROUP("uart1_grp", uart1_pins), + GROUP("uart2_grp", uart2_pins), + GROUP("uart3_grp0", uart3_pins0), + GROUP("uart3_grp1", uart3_pins1), + GROUP("uart3_grp2", uart3_pins2), + GROUP("uart3_grp3", uart3_pins3), + GROUP("uart3_nopause_grp0", uart3_nopause_pins0), + GROUP("uart3_nopause_grp1", uart3_nopause_pins1), + GROUP("uart4_grp0", uart4_pins0), + GROUP("uart4_grp1", uart4_pins1), + GROUP("uart4_grp2", uart4_pins2), + GROUP("uart4_nopause_grp", uart4_nopause_pins), + GROUP("usb0_drvvbus_grp", usb0_drvvbus_pins), + GROUP("usb1_drvvbus_grp", usb1_drvvbus_pins), + GROUP("visbus_dout_grp", visbus_dout_pins), + GROUP("vi_vip1_grp", vi_vip1_pins), + GROUP("vi_vip1_ext_grp", vi_vip1_ext_pins), + GROUP("vi_vip1_low8bit_grp", vi_vip1_low8bit_pins), + GROUP("vi_vip1_high8bit_grp", vi_vip1_high8bit_pins), +}; + +/* How many groups that a function can use */ +static const char * const gnss_gpio_grp[] = { "gnss_gpio_grp", }; +static const char * const lcd_vip_gpio_grp[] = { "lcd_vip_gpio_grp", }; +static const char * const sdio_i2s_gpio_grp[] = { "sdio_i2s_gpio_grp", }; +static const char * const sp_rgmii_gpio_grp[] = { "sp_rgmii_gpio_grp", }; +static const char * const lvds_gpio_grp[] = { "lvds_gpio_grp", }; +static const char * const uart_nand_gpio_grp[] = { "uart_nand_gpio_grp", }; +static const char * const rtc_gpio_grp[] = { "rtc_gpio_grp", }; +static const char * const audio_ac97_grp[] = { "audio_ac97_grp", }; +static const char * const audio_func_dbg_grp[] = { "audio_func_dbg_grp", }; +static const char * const audio_i2s_grp[] = { "audio_i2s_grp", }; +static const char * const audio_i2s_2ch_grp[] = { "audio_i2s_2ch_grp", }; +static const char * const audio_i2s_extclk_grp[] = { "audio_i2s_extclk_grp", }; +static const char * const audio_uart0_grp[] = { "audio_uart0_grp", }; +static const char * const audio_uart1_grp[] = { "audio_uart1_grp", }; +static const char * const audio_uart2_grp0[] = { "audio_uart2_grp0", }; +static const char * const audio_uart2_grp1[] = { "audio_uart2_grp1", }; +static const char * const c_can_trnsvr_grp[] = { "c_can_trnsvr_grp", }; +static const char * const c0_can_grp0[] = { "c0_can_grp0", }; +static const char * const c0_can_grp1[] = { "c0_can_grp1", }; +static const char * const c1_can_grp0[] = { "c1_can_grp0", }; +static const char * const c1_can_grp1[] = { "c1_can_grp1", }; +static const char * const c1_can_grp2[] = { "c1_can_grp2", }; +static const char * const ca_audio_lpc_grp[] = { "ca_audio_lpc_grp", }; +static const char * const ca_bt_lpc_grp[] = { "ca_bt_lpc_grp", }; +static const char * const ca_coex_grp[] = { "ca_coex_grp", }; +static const char * const ca_curator_lpc_grp[] = { "ca_curator_lpc_grp", }; +static const char * const ca_pcm_debug_grp[] = { "ca_pcm_debug_grp", }; +static const char * const ca_pio_grp[] = { "ca_pio_grp", }; +static const char * const ca_sdio_debug_grp[] = { "ca_sdio_debug_grp", }; +static const char * const ca_spi_grp[] = { "ca_spi_grp", }; +static const char * const ca_trb_grp[] = { "ca_trb_grp", }; +static const char * const ca_uart_debug_grp[] = { "ca_uart_debug_grp", }; +static const char * const clkc_grp0[] = { "clkc_grp0", }; +static const char * const clkc_grp1[] = { "clkc_grp1", }; +static const char * const gn_gnss_i2c_grp[] = { "gn_gnss_i2c_grp", }; +static const char * const gn_gnss_uart_nopause_grp[] = { + "gn_gnss_uart_nopause_grp", }; +static const char * const gn_gnss_uart_grp[] = { "gn_gnss_uart_grp", }; +static const char * const gn_trg_spi_grp0[] = { "gn_trg_spi_grp0", }; +static const char * const gn_trg_spi_grp1[] = { "gn_trg_spi_grp1", }; +static const char * const cvbs_dbg_grp[] = { "cvbs_dbg_grp", }; +static const char * const cvbs_dbg_test_grp0[] = { "cvbs_dbg_test_grp0", }; +static const char * const cvbs_dbg_test_grp1[] = { "cvbs_dbg_test_grp1", }; +static const char * const cvbs_dbg_test_grp2[] = { "cvbs_dbg_test_grp2", }; +static const char * const cvbs_dbg_test_grp3[] = { "cvbs_dbg_test_grp3", }; +static const char * const cvbs_dbg_test_grp4[] = { "cvbs_dbg_test_grp4", }; +static const char * const cvbs_dbg_test_grp5[] = { "cvbs_dbg_test_grp5", }; +static const char * const cvbs_dbg_test_grp6[] = { "cvbs_dbg_test_grp6", }; +static const char * const cvbs_dbg_test_grp7[] = { "cvbs_dbg_test_grp7", }; +static const char * const cvbs_dbg_test_grp8[] = { "cvbs_dbg_test_grp8", }; +static const char * const cvbs_dbg_test_grp9[] = { "cvbs_dbg_test_grp9", }; +static const char * const cvbs_dbg_test_grp10[] = { "cvbs_dbg_test_grp10", }; +static const char * const cvbs_dbg_test_grp11[] = { "cvbs_dbg_test_grp11", }; +static const char * const cvbs_dbg_test_grp12[] = { "cvbs_dbg_test_grp12", }; +static const char * const cvbs_dbg_test_grp13[] = { "cvbs_dbg_test_grp13", }; +static const char * const cvbs_dbg_test_grp14[] = { "cvbs_dbg_test_grp14", }; +static const char * const cvbs_dbg_test_grp15[] = { "cvbs_dbg_test_grp15", }; +static const char * const gn_gnss_power_grp[] = { "gn_gnss_power_grp", }; +static const char * const gn_gnss_sw_status_grp[] = { + "gn_gnss_sw_status_grp", }; +static const char * const gn_gnss_eclk_grp[] = { "gn_gnss_eclk_grp", }; +static const char * const gn_gnss_irq1_grp0[] = { "gn_gnss_irq1_grp0", }; +static const char * const gn_gnss_irq2_grp0[] = { "gn_gnss_irq2_grp0", }; +static const char * const gn_gnss_tm_grp[] = { "gn_gnss_tm_grp", }; +static const char * const gn_gnss_tsync_grp[] = { "gn_gnss_tsync_grp", }; +static const char * const gn_io_gnsssys_sw_cfg_grp[] = { + "gn_io_gnsssys_sw_cfg_grp", }; +static const char * const gn_trg_grp0[] = { "gn_trg_grp0", }; +static const char * const gn_trg_grp1[] = { "gn_trg_grp1", }; +static const char * const gn_trg_shutdown_grp0[] = { "gn_trg_shutdown_grp0", }; +static const char * const gn_trg_shutdown_grp1[] = { "gn_trg_shutdown_grp1", }; +static const char * const gn_trg_shutdown_grp2[] = { "gn_trg_shutdown_grp2", }; +static const char * const gn_trg_shutdown_grp3[] = { "gn_trg_shutdown_grp3", }; +static const char * const i2c0_grp[] = { "i2c0_grp", }; +static const char * const i2c1_grp[] = { "i2c1_grp", }; +static const char * const jtag_grp0[] = { "jtag_grp0", }; +static const char * const ks_kas_spi_grp0[] = { "ks_kas_spi_grp0", }; +static const char * const ld_ldd_grp[] = { "ld_ldd_grp", }; +static const char * const ld_ldd_16bit_grp[] = { "ld_ldd_16bit_grp", }; +static const char * const ld_ldd_fck_grp[] = { "ld_ldd_fck_grp", }; +static const char * const ld_ldd_lck_grp[] = { "ld_ldd_lck_grp", }; +static const char * const lr_lcdrom_grp[] = { "lr_lcdrom_grp", }; +static const char * const lvds_analog_grp[] = { "lvds_analog_grp", }; +static const char * const nd_df_grp[] = { "nd_df_grp", }; +static const char * const nd_df_nowp_grp[] = { "nd_df_nowp_grp", }; +static const char * const ps_grp[] = { "ps_grp", }; +static const char * const pwc_core_on_grp[] = { "pwc_core_on_grp", }; +static const char * const pwc_ext_on_grp[] = { "pwc_ext_on_grp", }; +static const char * const pwc_gpio3_clk_grp[] = { "pwc_gpio3_clk_grp", }; +static const char * const pwc_io_on_grp[] = { "pwc_io_on_grp", }; +static const char * const pwc_lowbatt_b_grp0[] = { "pwc_lowbatt_b_grp0", }; +static const char * const pwc_mem_on_grp[] = { "pwc_mem_on_grp", }; +static const char * const pwc_on_key_b_grp0[] = { "pwc_on_key_b_grp0", }; +static const char * const pwc_wakeup_src0_grp[] = { "pwc_wakeup_src0_grp", }; +static const char * const pwc_wakeup_src1_grp[] = { "pwc_wakeup_src1_grp", }; +static const char * const pwc_wakeup_src2_grp[] = { "pwc_wakeup_src2_grp", }; +static const char * const pwc_wakeup_src3_grp[] = { "pwc_wakeup_src3_grp", }; +static const char * const pw_cko0_grp0[] = { "pw_cko0_grp0", }; +static const char * const pw_cko0_grp1[] = { "pw_cko0_grp1", }; +static const char * const pw_cko0_grp2[] = { "pw_cko0_grp2", }; +static const char * const pw_cko1_grp0[] = { "pw_cko1_grp0", }; +static const char * const pw_cko1_grp1[] = { "pw_cko1_grp1", }; +static const char * const pw_i2s01_clk_grp0[] = { "pw_i2s01_clk_grp0", }; +static const char * const pw_i2s01_clk_grp1[] = { "pw_i2s01_clk_grp1", }; +static const char * const pw_pwm0_grp[] = { "pw_pwm0_grp", }; +static const char * const pw_pwm1_grp[] = { "pw_pwm1_grp", }; +static const char * const pw_pwm2_grp0[] = { "pw_pwm2_grp0", }; +static const char * const pw_pwm2_grp1[] = { "pw_pwm2_grp1", }; +static const char * const pw_pwm3_grp0[] = { "pw_pwm3_grp0", }; +static const char * const pw_pwm3_grp1[] = { "pw_pwm3_grp1", }; +static const char * const pw_pwm_cpu_vol_grp0[] = { "pw_pwm_cpu_vol_grp0", }; +static const char * const pw_pwm_cpu_vol_grp1[] = { "pw_pwm_cpu_vol_grp1", }; +static const char * const pw_backlight_grp0[] = { "pw_backlight_grp0", }; +static const char * const pw_backlight_grp1[] = { "pw_backlight_grp1", }; +static const char * const rg_eth_mac_grp[] = { "rg_eth_mac_grp", }; +static const char * const rg_gmac_phy_intr_n_grp[] = { + "rg_gmac_phy_intr_n_grp", }; +static const char * const rg_rgmii_mac_grp[] = { "rg_rgmii_mac_grp", }; +static const char * const rg_rgmii_phy_ref_clk_grp0[] = { + "rg_rgmii_phy_ref_clk_grp0", }; +static const char * const rg_rgmii_phy_ref_clk_grp1[] = { + "rg_rgmii_phy_ref_clk_grp1", }; +static const char * const sd0_grp[] = { "sd0_grp", }; +static const char * const sd0_4bit_grp[] = { "sd0_4bit_grp", }; +static const char * const sd1_grp[] = { "sd1_grp", }; +static const char * const sd1_4bit_grp0[] = { "sd1_4bit_grp0", }; +static const char * const sd1_4bit_grp1[] = { "sd1_4bit_grp1", }; +static const char * const sd2_grp0[] = { "sd2_grp0", }; +static const char * const sd2_no_cdb_grp0[] = { "sd2_no_cdb_grp0", }; +static const char * const sd3_grp[] = { "sd3_grp", }; +static const char * const sd5_grp[] = { "sd5_grp", }; +static const char * const sd6_grp0[] = { "sd6_grp0", }; +static const char * const sd6_grp1[] = { "sd6_grp1", }; +static const char * const sp0_ext_ldo_on_grp[] = { "sp0_ext_ldo_on_grp", }; +static const char * const sp0_qspi_grp[] = { "sp0_qspi_grp", }; +static const char * const sp1_spi_grp[] = { "sp1_spi_grp", }; +static const char * const tpiu_trace_grp[] = { "tpiu_trace_grp", }; +static const char * const uart0_grp[] = { "uart0_grp", }; +static const char * const uart0_nopause_grp[] = { "uart0_nopause_grp", }; +static const char * const uart1_grp[] = { "uart1_grp", }; +static const char * const uart2_grp[] = { "uart2_grp", }; +static const char * const uart3_grp0[] = { "uart3_grp0", }; +static const char * const uart3_grp1[] = { "uart3_grp1", }; +static const char * const uart3_grp2[] = { "uart3_grp2", }; +static const char * const uart3_grp3[] = { "uart3_grp3", }; +static const char * const uart3_nopause_grp0[] = { "uart3_nopause_grp0", }; +static const char * const uart3_nopause_grp1[] = { "uart3_nopause_grp1", }; +static const char * const uart4_grp0[] = { "uart4_grp0", }; +static const char * const uart4_grp1[] = { "uart4_grp1", }; +static const char * const uart4_grp2[] = { "uart4_grp2", }; +static const char * const uart4_nopause_grp[] = { "uart4_nopause_grp", }; +static const char * const usb0_drvvbus_grp[] = { "usb0_drvvbus_grp", }; +static const char * const usb1_drvvbus_grp[] = { "usb1_drvvbus_grp", }; +static const char * const visbus_dout_grp[] = { "visbus_dout_grp", }; +static const char * const vi_vip1_grp[] = { "vi_vip1_grp", }; +static const char * const vi_vip1_ext_grp[] = { "vi_vip1_ext_grp", }; +static const char * const vi_vip1_low8bit_grp[] = { "vi_vip1_low8bit_grp", }; +static const char * const vi_vip1_high8bit_grp[] = { "vi_vip1_high8bit_grp", }; + +static struct atlas7_pad_mux gnss_gpio_grp_pad_mux[] = { + MUX(1, 119, 0, N, N, N, N), + MUX(1, 120, 0, N, N, N, N), + MUX(1, 121, 0, N, N, N, N), + MUX(1, 122, 0, N, N, N, N), + MUX(1, 123, 0, N, N, N, N), + MUX(1, 124, 0, N, N, N, N), + MUX(1, 125, 0, N, N, N, N), + MUX(1, 126, 0, N, N, N, N), + MUX(1, 127, 0, N, N, N, N), + MUX(1, 128, 0, N, N, N, N), + MUX(1, 22, 0, N, N, N, N), + MUX(1, 23, 0, N, N, N, N), + MUX(1, 24, 0, N, N, N, N), + MUX(1, 25, 0, N, N, N, N), + MUX(1, 26, 0, N, N, N, N), + MUX(1, 27, 0, N, N, N, N), + MUX(1, 28, 0, N, N, N, N), + MUX(1, 29, 0, N, N, N, N), + MUX(1, 30, 0, N, N, N, N), +}; + +static struct atlas7_grp_mux gnss_gpio_grp_mux = { + .pad_mux_count = ARRAY_SIZE(gnss_gpio_grp_pad_mux), + .pad_mux_list = gnss_gpio_grp_pad_mux, +}; + +static struct atlas7_pad_mux lcd_vip_gpio_grp_pad_mux[] = { + MUX(1, 74, 0, N, N, N, N), + MUX(1, 75, 0, N, N, N, N), + MUX(1, 76, 0, N, N, N, N), + MUX(1, 77, 0, N, N, N, N), + MUX(1, 78, 0, N, N, N, N), + MUX(1, 79, 0, N, N, N, N), + MUX(1, 80, 0, N, N, N, N), + MUX(1, 81, 0, N, N, N, N), + MUX(1, 82, 0, N, N, N, N), + MUX(1, 83, 0, N, N, N, N), + MUX(1, 84, 0, N, N, N, N), + MUX(1, 53, 0, N, N, N, N), + MUX(1, 54, 0, N, N, N, N), + MUX(1, 55, 0, N, N, N, N), + MUX(1, 56, 0, N, N, N, N), + MUX(1, 57, 0, N, N, N, N), + MUX(1, 58, 0, N, N, N, N), + MUX(1, 59, 0, N, N, N, N), + MUX(1, 60, 0, N, N, N, N), + MUX(1, 61, 0, N, N, N, N), + MUX(1, 62, 0, N, N, N, N), + MUX(1, 63, 0, N, N, N, N), + MUX(1, 64, 0, N, N, N, N), + MUX(1, 65, 0, N, N, N, N), + MUX(1, 66, 0, N, N, N, N), + MUX(1, 67, 0, N, N, N, N), + MUX(1, 68, 0, N, N, N, N), + MUX(1, 69, 0, N, N, N, N), + MUX(1, 70, 0, N, N, N, N), + MUX(1, 71, 0, N, N, N, N), + MUX(1, 72, 0, N, N, N, N), + MUX(1, 73, 0, N, N, N, N), +}; + +static struct atlas7_grp_mux lcd_vip_gpio_grp_mux = { + .pad_mux_count = ARRAY_SIZE(lcd_vip_gpio_grp_pad_mux), + .pad_mux_list = lcd_vip_gpio_grp_pad_mux, +}; + +static struct atlas7_pad_mux sdio_i2s_gpio_grp_pad_mux[] = { + MUX(1, 31, 0, N, N, N, N), + MUX(1, 32, 0, N, N, N, N), + MUX(1, 33, 0, N, N, N, N), + MUX(1, 34, 0, N, N, N, N), + MUX(1, 35, 0, N, N, N, N), + MUX(1, 36, 0, N, N, N, N), + MUX(1, 85, 0, N, N, N, N), + MUX(1, 86, 0, N, N, N, N), + MUX(1, 87, 0, N, N, N, N), + MUX(1, 88, 0, N, N, N, N), + MUX(1, 89, 0, N, N, N, N), + MUX(1, 90, 0, N, N, N, N), + MUX(1, 129, 0, N, N, N, N), + MUX(1, 130, 0, N, N, N, N), + MUX(1, 131, 0, N, N, N, N), + MUX(1, 132, 0, N, N, N, N), + MUX(1, 91, 0, N, N, N, N), + MUX(1, 92, 0, N, N, N, N), + MUX(1, 93, 0, N, N, N, N), + MUX(1, 94, 0, N, N, N, N), + MUX(1, 95, 0, N, N, N, N), + MUX(1, 96, 0, N, N, N, N), + MUX(1, 112, 0, N, N, N, N), + MUX(1, 113, 0, N, N, N, N), + MUX(1, 114, 0, N, N, N, N), + MUX(1, 115, 0, N, N, N, N), + MUX(1, 116, 0, N, N, N, N), + MUX(1, 117, 0, N, N, N, N), + MUX(1, 118, 0, N, N, N, N), +}; + +static struct atlas7_grp_mux sdio_i2s_gpio_grp_mux = { + .pad_mux_count = ARRAY_SIZE(sdio_i2s_gpio_grp_pad_mux), + .pad_mux_list = sdio_i2s_gpio_grp_pad_mux, +}; + +static struct atlas7_pad_mux sp_rgmii_gpio_grp_pad_mux[] = { + MUX(1, 97, 0, N, N, N, N), + MUX(1, 98, 0, N, N, N, N), + MUX(1, 99, 0, N, N, N, N), + MUX(1, 100, 0, N, N, N, N), + MUX(1, 101, 0, N, N, N, N), + MUX(1, 102, 0, N, N, N, N), + MUX(1, 103, 0, N, N, N, N), + MUX(1, 104, 0, N, N, N, N), + MUX(1, 105, 0, N, N, N, N), + MUX(1, 106, 0, N, N, N, N), + MUX(1, 107, 0, N, N, N, N), + MUX(1, 108, 0, N, N, N, N), + MUX(1, 109, 0, N, N, N, N), + MUX(1, 110, 0, N, N, N, N), + MUX(1, 111, 0, N, N, N, N), + MUX(1, 18, 0, N, N, N, N), + MUX(1, 19, 0, N, N, N, N), + MUX(1, 20, 0, N, N, N, N), + MUX(1, 21, 0, N, N, N, N), + MUX(1, 141, 0, N, N, N, N), + MUX(1, 142, 0, N, N, N, N), + MUX(1, 143, 0, N, N, N, N), + MUX(1, 144, 0, N, N, N, N), + MUX(1, 145, 0, N, N, N, N), + MUX(1, 146, 0, N, N, N, N), + MUX(1, 147, 0, N, N, N, N), + MUX(1, 148, 0, N, N, N, N), +}; + +static struct atlas7_grp_mux sp_rgmii_gpio_grp_mux = { + .pad_mux_count = ARRAY_SIZE(sp_rgmii_gpio_grp_pad_mux), + .pad_mux_list = sp_rgmii_gpio_grp_pad_mux, +}; + +static struct atlas7_pad_mux lvds_gpio_grp_pad_mux[] = { + MUX(1, 157, 0, N, N, N, N), + MUX(1, 158, 0, N, N, N, N), + MUX(1, 155, 0, N, N, N, N), + MUX(1, 156, 0, N, N, N, N), + MUX(1, 153, 0, N, N, N, N), + MUX(1, 154, 0, N, N, N, N), + MUX(1, 151, 0, N, N, N, N), + MUX(1, 152, 0, N, N, N, N), + MUX(1, 149, 0, N, N, N, N), + MUX(1, 150, 0, N, N, N, N), +}; + +static struct atlas7_grp_mux lvds_gpio_grp_mux = { + .pad_mux_count = ARRAY_SIZE(lvds_gpio_grp_pad_mux), + .pad_mux_list = lvds_gpio_grp_pad_mux, +}; + +static struct atlas7_pad_mux uart_nand_gpio_grp_pad_mux[] = { + MUX(1, 44, 0, N, N, N, N), + MUX(1, 43, 0, N, N, N, N), + MUX(1, 42, 0, N, N, N, N), + MUX(1, 41, 0, N, N, N, N), + MUX(1, 40, 0, N, N, N, N), + MUX(1, 39, 0, N, N, N, N), + MUX(1, 38, 0, N, N, N, N), + MUX(1, 37, 0, N, N, N, N), + MUX(1, 46, 0, N, N, N, N), + MUX(1, 47, 0, N, N, N, N), + MUX(1, 48, 0, N, N, N, N), + MUX(1, 49, 0, N, N, N, N), + MUX(1, 50, 0, N, N, N, N), + MUX(1, 52, 0, N, N, N, N), + MUX(1, 51, 0, N, N, N, N), + MUX(1, 45, 0, N, N, N, N), + MUX(1, 133, 0, N, N, N, N), + MUX(1, 134, 0, N, N, N, N), + MUX(1, 135, 0, N, N, N, N), + MUX(1, 136, 0, N, N, N, N), + MUX(1, 137, 0, N, N, N, N), + MUX(1, 138, 0, N, N, N, N), + MUX(1, 139, 0, N, N, N, N), + MUX(1, 140, 0, N, N, N, N), +}; + +static struct atlas7_grp_mux uart_nand_gpio_grp_mux = { + .pad_mux_count = ARRAY_SIZE(uart_nand_gpio_grp_pad_mux), + .pad_mux_list = uart_nand_gpio_grp_pad_mux, +}; + +static struct atlas7_pad_mux rtc_gpio_grp_pad_mux[] = { + MUX(0, 0, 0, N, N, N, N), + MUX(0, 1, 0, N, N, N, N), + MUX(0, 2, 0, N, N, N, N), + MUX(0, 3, 0, N, N, N, N), + MUX(0, 4, 0, N, N, N, N), + MUX(0, 10, 0, N, N, N, N), + MUX(0, 11, 0, N, N, N, N), + MUX(0, 12, 0, N, N, N, N), + MUX(0, 13, 0, N, N, N, N), + MUX(0, 14, 0, N, N, N, N), + MUX(0, 15, 0, N, N, N, N), + MUX(0, 16, 0, N, N, N, N), + MUX(0, 17, 0, N, N, N, N), +}; + +static struct atlas7_grp_mux rtc_gpio_grp_mux = { + .pad_mux_count = ARRAY_SIZE(rtc_gpio_grp_pad_mux), + .pad_mux_list = rtc_gpio_grp_pad_mux, +}; + +static struct atlas7_pad_mux audio_ac97_grp_pad_mux[] = { + MUX(1, 113, 2, N, N, N, N), + MUX(1, 118, 2, N, N, N, N), + MUX(1, 115, 2, N, N, N, N), + MUX(1, 114, 2, N, N, N, N), +}; + +static struct atlas7_grp_mux audio_ac97_grp_mux = { + .pad_mux_count = ARRAY_SIZE(audio_ac97_grp_pad_mux), + .pad_mux_list = audio_ac97_grp_pad_mux, +}; + +static struct atlas7_pad_mux audio_func_dbg_grp_pad_mux[] = { + MUX(1, 141, 4, N, N, N, N), + MUX(1, 144, 4, N, N, N, N), + MUX(1, 44, 6, N, N, N, N), + MUX(1, 43, 6, N, N, N, N), + MUX(1, 42, 6, N, N, N, N), + MUX(1, 41, 6, N, N, N, N), + MUX(1, 40, 6, N, N, N, N), + MUX(1, 39, 6, N, N, N, N), + MUX(1, 38, 6, N, N, N, N), + MUX(1, 37, 6, N, N, N, N), + MUX(1, 74, 6, N, N, N, N), + MUX(1, 75, 6, N, N, N, N), + MUX(1, 76, 6, N, N, N, N), + MUX(1, 77, 6, N, N, N, N), + MUX(1, 78, 6, N, N, N, N), + MUX(1, 79, 6, N, N, N, N), + MUX(1, 81, 6, N, N, N, N), + MUX(1, 113, 6, N, N, N, N), + MUX(1, 114, 6, N, N, N, N), + MUX(1, 118, 6, N, N, N, N), + MUX(1, 115, 6, N, N, N, N), + MUX(1, 49, 6, N, N, N, N), + MUX(1, 50, 6, N, N, N, N), + MUX(1, 142, 4, N, N, N, N), + MUX(1, 143, 4, N, N, N, N), + MUX(1, 80, 6, N, N, N, N), +}; + +static struct atlas7_grp_mux audio_func_dbg_grp_mux = { + .pad_mux_count = ARRAY_SIZE(audio_func_dbg_grp_pad_mux), + .pad_mux_list = audio_func_dbg_grp_pad_mux, +}; + +static struct atlas7_pad_mux audio_i2s_grp_pad_mux[] = { + MUX(1, 118, 1, N, N, N, N), + MUX(1, 115, 1, N, N, N, N), + MUX(1, 116, 1, N, N, N, N), + MUX(1, 117, 1, N, N, N, N), + MUX(1, 112, 1, N, N, N, N), + MUX(1, 113, 1, N, N, N, N), + MUX(1, 114, 1, N, N, N, N), +}; + +static struct atlas7_grp_mux audio_i2s_grp_mux = { + .pad_mux_count = ARRAY_SIZE(audio_i2s_grp_pad_mux), + .pad_mux_list = audio_i2s_grp_pad_mux, +}; + +static struct atlas7_pad_mux audio_i2s_2ch_grp_pad_mux[] = { + MUX(1, 118, 1, N, N, N, N), + MUX(1, 115, 1, N, N, N, N), + MUX(1, 112, 1, N, N, N, N), + MUX(1, 113, 1, N, N, N, N), + MUX(1, 114, 1, N, N, N, N), +}; + +static struct atlas7_grp_mux audio_i2s_2ch_grp_mux = { + .pad_mux_count = ARRAY_SIZE(audio_i2s_2ch_grp_pad_mux), + .pad_mux_list = audio_i2s_2ch_grp_pad_mux, +}; + +static struct atlas7_pad_mux audio_i2s_extclk_grp_pad_mux[] = { + MUX(1, 112, 2, N, N, N, N), +}; + +static struct atlas7_grp_mux audio_i2s_extclk_grp_mux = { + .pad_mux_count = ARRAY_SIZE(audio_i2s_extclk_grp_pad_mux), + .pad_mux_list = audio_i2s_extclk_grp_pad_mux, +}; + +static struct atlas7_pad_mux audio_uart0_grp_pad_mux[] = { + MUX(1, 143, 1, N, N, N, N), + MUX(1, 142, 1, N, N, N, N), + MUX(1, 141, 1, N, N, N, N), + MUX(1, 144, 1, N, N, N, N), +}; + +static struct atlas7_grp_mux audio_uart0_grp_mux = { + .pad_mux_count = ARRAY_SIZE(audio_uart0_grp_pad_mux), + .pad_mux_list = audio_uart0_grp_pad_mux, +}; + +static struct atlas7_pad_mux audio_uart1_grp_pad_mux[] = { + MUX(1, 147, 1, N, N, N, N), + MUX(1, 146, 1, N, N, N, N), + MUX(1, 145, 1, N, N, N, N), + MUX(1, 148, 1, N, N, N, N), +}; + +static struct atlas7_grp_mux audio_uart1_grp_mux = { + .pad_mux_count = ARRAY_SIZE(audio_uart1_grp_pad_mux), + .pad_mux_list = audio_uart1_grp_pad_mux, +}; + +static struct atlas7_pad_mux audio_uart2_grp0_pad_mux[] = { + MUX(1, 20, 2, 0xa00, 24, 0xa80, 24), + MUX(1, 21, 2, 0xa00, 25, 0xa80, 25), + MUX(1, 19, 2, 0xa00, 23, 0xa80, 23), + MUX(1, 18, 2, 0xa00, 22, 0xa80, 22), +}; + +static struct atlas7_grp_mux audio_uart2_grp0_mux = { + .pad_mux_count = ARRAY_SIZE(audio_uart2_grp0_pad_mux), + .pad_mux_list = audio_uart2_grp0_pad_mux, +}; + +static struct atlas7_pad_mux audio_uart2_grp1_pad_mux[] = { + MUX(1, 109, 2, 0xa00, 24, 0xa80, 24), + MUX(1, 110, 2, 0xa00, 25, 0xa80, 25), + MUX(1, 101, 2, 0xa00, 23, 0xa80, 23), + MUX(1, 111, 2, 0xa00, 22, 0xa80, 22), +}; + +static struct atlas7_grp_mux audio_uart2_grp1_mux = { + .pad_mux_count = ARRAY_SIZE(audio_uart2_grp1_pad_mux), + .pad_mux_list = audio_uart2_grp1_pad_mux, +}; + +static struct atlas7_pad_mux c_can_trnsvr_grp_pad_mux[] = { + MUX(0, 1, 2, N, N, N, N), +}; + +static struct atlas7_grp_mux c_can_trnsvr_grp_mux = { + .pad_mux_count = ARRAY_SIZE(c_can_trnsvr_grp_pad_mux), + .pad_mux_list = c_can_trnsvr_grp_pad_mux, +}; + +static struct atlas7_pad_mux c0_can_grp0_pad_mux[] = { + MUX(0, 11, 1, 0xa08, 9, 0xa88, 9), + MUX(0, 10, 1, N, N, N, N), +}; + +static struct atlas7_grp_mux c0_can_grp0_mux = { + .pad_mux_count = ARRAY_SIZE(c0_can_grp0_pad_mux), + .pad_mux_list = c0_can_grp0_pad_mux, +}; + +static struct atlas7_pad_mux c0_can_grp1_pad_mux[] = { + MUX(0, 2, 5, 0xa08, 9, 0xa88, 9), + MUX(0, 3, 5, N, N, N, N), +}; + +static struct atlas7_grp_mux c0_can_grp1_mux = { + .pad_mux_count = ARRAY_SIZE(c0_can_grp1_pad_mux), + .pad_mux_list = c0_can_grp1_pad_mux, +}; + +static struct atlas7_pad_mux c1_can_grp0_pad_mux[] = { + MUX(1, 138, 2, 0xa00, 4, 0xa80, 4), + MUX(1, 137, 2, N, N, N, N), +}; + +static struct atlas7_grp_mux c1_can_grp0_mux = { + .pad_mux_count = ARRAY_SIZE(c1_can_grp0_pad_mux), + .pad_mux_list = c1_can_grp0_pad_mux, +}; + +static struct atlas7_pad_mux c1_can_grp1_pad_mux[] = { + MUX(1, 147, 2, 0xa00, 4, 0xa80, 4), + MUX(1, 146, 2, N, N, N, N), +}; + +static struct atlas7_grp_mux c1_can_grp1_mux = { + .pad_mux_count = ARRAY_SIZE(c1_can_grp1_pad_mux), + .pad_mux_list = c1_can_grp1_pad_mux, +}; + +static struct atlas7_pad_mux c1_can_grp2_pad_mux[] = { + MUX(0, 2, 2, 0xa00, 4, 0xa80, 4), + MUX(0, 3, 2, N, N, N, N), +}; + +static struct atlas7_grp_mux c1_can_grp2_mux = { + .pad_mux_count = ARRAY_SIZE(c1_can_grp2_pad_mux), + .pad_mux_list = c1_can_grp2_pad_mux, +}; + +static struct atlas7_pad_mux ca_audio_lpc_grp_pad_mux[] = { + MUX(1, 62, 4, N, N, N, N), + MUX(1, 63, 4, N, N, N, N), + MUX(1, 64, 4, N, N, N, N), + MUX(1, 65, 4, N, N, N, N), + MUX(1, 66, 4, N, N, N, N), + MUX(1, 67, 4, N, N, N, N), + MUX(1, 68, 4, N, N, N, N), + MUX(1, 69, 4, N, N, N, N), + MUX(1, 70, 4, N, N, N, N), + MUX(1, 71, 4, N, N, N, N), +}; + +static struct atlas7_grp_mux ca_audio_lpc_grp_mux = { + .pad_mux_count = ARRAY_SIZE(ca_audio_lpc_grp_pad_mux), + .pad_mux_list = ca_audio_lpc_grp_pad_mux, +}; + +static struct atlas7_pad_mux ca_bt_lpc_grp_pad_mux[] = { + MUX(1, 85, 5, N, N, N, N), + MUX(1, 86, 5, N, N, N, N), + MUX(1, 87, 5, N, N, N, N), + MUX(1, 88, 5, N, N, N, N), + MUX(1, 89, 5, N, N, N, N), + MUX(1, 90, 5, N, N, N, N), +}; + +static struct atlas7_grp_mux ca_bt_lpc_grp_mux = { + .pad_mux_count = ARRAY_SIZE(ca_bt_lpc_grp_pad_mux), + .pad_mux_list = ca_bt_lpc_grp_pad_mux, +}; + +static struct atlas7_pad_mux ca_coex_grp_pad_mux[] = { + MUX(1, 129, 1, N, N, N, N), + MUX(1, 130, 1, N, N, N, N), + MUX(1, 131, 1, N, N, N, N), + MUX(1, 132, 1, N, N, N, N), +}; + +static struct atlas7_grp_mux ca_coex_grp_mux = { + .pad_mux_count = ARRAY_SIZE(ca_coex_grp_pad_mux), + .pad_mux_list = ca_coex_grp_pad_mux, +}; + +static struct atlas7_pad_mux ca_curator_lpc_grp_pad_mux[] = { + MUX(1, 57, 4, N, N, N, N), + MUX(1, 58, 4, N, N, N, N), + MUX(1, 59, 4, N, N, N, N), + MUX(1, 60, 4, N, N, N, N), +}; + +static struct atlas7_grp_mux ca_curator_lpc_grp_mux = { + .pad_mux_count = ARRAY_SIZE(ca_curator_lpc_grp_pad_mux), + .pad_mux_list = ca_curator_lpc_grp_pad_mux, +}; + +static struct atlas7_pad_mux ca_pcm_debug_grp_pad_mux[] = { + MUX(1, 91, 5, N, N, N, N), + MUX(1, 93, 5, N, N, N, N), + MUX(1, 94, 5, N, N, N, N), + MUX(1, 92, 5, N, N, N, N), +}; + +static struct atlas7_grp_mux ca_pcm_debug_grp_mux = { + .pad_mux_count = ARRAY_SIZE(ca_pcm_debug_grp_pad_mux), + .pad_mux_list = ca_pcm_debug_grp_pad_mux, +}; + +static struct atlas7_pad_mux ca_pio_grp_pad_mux[] = { + MUX(1, 121, 2, N, N, N, N), + MUX(1, 122, 2, N, N, N, N), + MUX(1, 125, 6, N, N, N, N), + MUX(1, 126, 6, N, N, N, N), + MUX(1, 38, 5, N, N, N, N), + MUX(1, 37, 5, N, N, N, N), + MUX(1, 47, 5, N, N, N, N), + MUX(1, 49, 5, N, N, N, N), + MUX(1, 50, 5, N, N, N, N), + MUX(1, 54, 4, N, N, N, N), + MUX(1, 55, 4, N, N, N, N), + MUX(1, 56, 4, N, N, N, N), +}; + +static struct atlas7_grp_mux ca_pio_grp_mux = { + .pad_mux_count = ARRAY_SIZE(ca_pio_grp_pad_mux), + .pad_mux_list = ca_pio_grp_pad_mux, +}; + +static struct atlas7_pad_mux ca_sdio_debug_grp_pad_mux[] = { + MUX(1, 40, 5, N, N, N, N), + MUX(1, 39, 5, N, N, N, N), + MUX(1, 44, 5, N, N, N, N), + MUX(1, 43, 5, N, N, N, N), + MUX(1, 42, 5, N, N, N, N), + MUX(1, 41, 5, N, N, N, N), +}; + +static struct atlas7_grp_mux ca_sdio_debug_grp_mux = { + .pad_mux_count = ARRAY_SIZE(ca_sdio_debug_grp_pad_mux), + .pad_mux_list = ca_sdio_debug_grp_pad_mux, +}; + +static struct atlas7_pad_mux ca_spi_grp_pad_mux[] = { + MUX(1, 82, 5, N, N, N, N), + MUX(1, 79, 5, 0xa08, 6, 0xa88, 6), + MUX(1, 80, 5, N, N, N, N), + MUX(1, 81, 5, N, N, N, N), +}; + +static struct atlas7_grp_mux ca_spi_grp_mux = { + .pad_mux_count = ARRAY_SIZE(ca_spi_grp_pad_mux), + .pad_mux_list = ca_spi_grp_pad_mux, +}; + +static struct atlas7_pad_mux ca_trb_grp_pad_mux[] = { + MUX(1, 91, 4, N, N, N, N), + MUX(1, 93, 4, N, N, N, N), + MUX(1, 94, 4, N, N, N, N), + MUX(1, 95, 4, N, N, N, N), + MUX(1, 96, 4, N, N, N, N), + MUX(1, 78, 5, N, N, N, N), + MUX(1, 74, 5, N, N, N, N), + MUX(1, 75, 5, N, N, N, N), + MUX(1, 76, 5, N, N, N, N), + MUX(1, 77, 5, N, N, N, N), +}; + +static struct atlas7_grp_mux ca_trb_grp_mux = { + .pad_mux_count = ARRAY_SIZE(ca_trb_grp_pad_mux), + .pad_mux_list = ca_trb_grp_pad_mux, +}; + +static struct atlas7_pad_mux ca_uart_debug_grp_pad_mux[] = { + MUX(1, 136, 3, N, N, N, N), + MUX(1, 135, 3, N, N, N, N), + MUX(1, 134, 3, N, N, N, N), + MUX(1, 133, 3, N, N, N, N), +}; + +static struct atlas7_grp_mux ca_uart_debug_grp_mux = { + .pad_mux_count = ARRAY_SIZE(ca_uart_debug_grp_pad_mux), + .pad_mux_list = ca_uart_debug_grp_pad_mux, +}; + +static struct atlas7_pad_mux clkc_grp0_pad_mux[] = { + MUX(1, 30, 2, 0xa08, 14, 0xa88, 14), + MUX(1, 47, 6, N, N, N, N), +}; + +static struct atlas7_grp_mux clkc_grp0_mux = { + .pad_mux_count = ARRAY_SIZE(clkc_grp0_pad_mux), + .pad_mux_list = clkc_grp0_pad_mux, +}; + +static struct atlas7_pad_mux clkc_grp1_pad_mux[] = { + MUX(1, 78, 3, 0xa08, 14, 0xa88, 14), + MUX(1, 54, 5, N, N, N, N), +}; + +static struct atlas7_grp_mux clkc_grp1_mux = { + .pad_mux_count = ARRAY_SIZE(clkc_grp1_pad_mux), + .pad_mux_list = clkc_grp1_pad_mux, +}; + +static struct atlas7_pad_mux gn_gnss_i2c_grp_pad_mux[] = { + MUX(1, 128, 2, N, N, N, N), + MUX(1, 127, 2, N, N, N, N), +}; + +static struct atlas7_grp_mux gn_gnss_i2c_grp_mux = { + .pad_mux_count = ARRAY_SIZE(gn_gnss_i2c_grp_pad_mux), + .pad_mux_list = gn_gnss_i2c_grp_pad_mux, +}; + +static struct atlas7_pad_mux gn_gnss_uart_nopause_grp_pad_mux[] = { + MUX(1, 134, 4, N, N, N, N), + MUX(1, 133, 4, N, N, N, N), +}; + +static struct atlas7_grp_mux gn_gnss_uart_nopause_grp_mux = { + .pad_mux_count = ARRAY_SIZE(gn_gnss_uart_nopause_grp_pad_mux), + .pad_mux_list = gn_gnss_uart_nopause_grp_pad_mux, +}; + +static struct atlas7_pad_mux gn_gnss_uart_grp_pad_mux[] = { + MUX(1, 134, 4, N, N, N, N), + MUX(1, 133, 4, N, N, N, N), + MUX(1, 136, 4, N, N, N, N), + MUX(1, 135, 4, N, N, N, N), +}; + +static struct atlas7_grp_mux gn_gnss_uart_grp_mux = { + .pad_mux_count = ARRAY_SIZE(gn_gnss_uart_grp_pad_mux), + .pad_mux_list = gn_gnss_uart_grp_pad_mux, +}; + +static struct atlas7_pad_mux gn_trg_spi_grp0_pad_mux[] = { + MUX(1, 22, 1, N, N, N, N), + MUX(1, 25, 1, N, N, N, N), + MUX(1, 23, 1, 0xa00, 10, 0xa80, 10), + MUX(1, 24, 1, N, N, N, N), +}; + +static struct atlas7_grp_mux gn_trg_spi_grp0_mux = { + .pad_mux_count = ARRAY_SIZE(gn_trg_spi_grp0_pad_mux), + .pad_mux_list = gn_trg_spi_grp0_pad_mux, +}; + +static struct atlas7_pad_mux gn_trg_spi_grp1_pad_mux[] = { + MUX(1, 82, 3, N, N, N, N), + MUX(1, 79, 3, N, N, N, N), + MUX(1, 80, 3, 0xa00, 10, 0xa80, 10), + MUX(1, 81, 3, N, N, N, N), +}; + +static struct atlas7_grp_mux gn_trg_spi_grp1_mux = { + .pad_mux_count = ARRAY_SIZE(gn_trg_spi_grp1_pad_mux), + .pad_mux_list = gn_trg_spi_grp1_pad_mux, +}; + +static struct atlas7_pad_mux cvbs_dbg_grp_pad_mux[] = { + MUX(1, 54, 3, N, N, N, N), + MUX(1, 53, 3, N, N, N, N), + MUX(1, 82, 7, N, N, N, N), + MUX(1, 74, 7, N, N, N, N), + MUX(1, 75, 7, N, N, N, N), + MUX(1, 76, 7, N, N, N, N), + MUX(1, 77, 7, N, N, N, N), + MUX(1, 78, 7, N, N, N, N), + MUX(1, 79, 7, N, N, N, N), + MUX(1, 80, 7, N, N, N, N), + MUX(1, 81, 7, N, N, N, N), + MUX(1, 83, 7, N, N, N, N), + MUX(1, 84, 7, N, N, N, N), + MUX(1, 73, 3, N, N, N, N), + MUX(1, 55, 3, N, N, N, N), + MUX(1, 56, 3, N, N, N, N), +}; + +static struct atlas7_grp_mux cvbs_dbg_grp_mux = { + .pad_mux_count = ARRAY_SIZE(cvbs_dbg_grp_pad_mux), + .pad_mux_list = cvbs_dbg_grp_pad_mux, +}; + +static struct atlas7_pad_mux cvbs_dbg_test_grp0_pad_mux[] = { + MUX(1, 57, 3, N, N, N, N), +}; + +static struct atlas7_grp_mux cvbs_dbg_test_grp0_mux = { + .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp0_pad_mux), + .pad_mux_list = cvbs_dbg_test_grp0_pad_mux, +}; + +static struct atlas7_pad_mux cvbs_dbg_test_grp1_pad_mux[] = { + MUX(1, 58, 3, N, N, N, N), +}; + +static struct atlas7_grp_mux cvbs_dbg_test_grp1_mux = { + .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp1_pad_mux), + .pad_mux_list = cvbs_dbg_test_grp1_pad_mux, +}; + +static struct atlas7_pad_mux cvbs_dbg_test_grp2_pad_mux[] = { + MUX(1, 59, 3, N, N, N, N), +}; + +static struct atlas7_grp_mux cvbs_dbg_test_grp2_mux = { + .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp2_pad_mux), + .pad_mux_list = cvbs_dbg_test_grp2_pad_mux, +}; + +static struct atlas7_pad_mux cvbs_dbg_test_grp3_pad_mux[] = { + MUX(1, 60, 3, N, N, N, N), +}; + +static struct atlas7_grp_mux cvbs_dbg_test_grp3_mux = { + .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp3_pad_mux), + .pad_mux_list = cvbs_dbg_test_grp3_pad_mux, +}; + +static struct atlas7_pad_mux cvbs_dbg_test_grp4_pad_mux[] = { + MUX(1, 61, 3, N, N, N, N), +}; + +static struct atlas7_grp_mux cvbs_dbg_test_grp4_mux = { + .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp4_pad_mux), + .pad_mux_list = cvbs_dbg_test_grp4_pad_mux, +}; + +static struct atlas7_pad_mux cvbs_dbg_test_grp5_pad_mux[] = { + MUX(1, 62, 3, N, N, N, N), +}; + +static struct atlas7_grp_mux cvbs_dbg_test_grp5_mux = { + .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp5_pad_mux), + .pad_mux_list = cvbs_dbg_test_grp5_pad_mux, +}; + +static struct atlas7_pad_mux cvbs_dbg_test_grp6_pad_mux[] = { + MUX(1, 63, 3, N, N, N, N), +}; + +static struct atlas7_grp_mux cvbs_dbg_test_grp6_mux = { + .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp6_pad_mux), + .pad_mux_list = cvbs_dbg_test_grp6_pad_mux, +}; + +static struct atlas7_pad_mux cvbs_dbg_test_grp7_pad_mux[] = { + MUX(1, 64, 3, N, N, N, N), +}; + +static struct atlas7_grp_mux cvbs_dbg_test_grp7_mux = { + .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp7_pad_mux), + .pad_mux_list = cvbs_dbg_test_grp7_pad_mux, +}; + +static struct atlas7_pad_mux cvbs_dbg_test_grp8_pad_mux[] = { + MUX(1, 65, 3, N, N, N, N), +}; + +static struct atlas7_grp_mux cvbs_dbg_test_grp8_mux = { + .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp8_pad_mux), + .pad_mux_list = cvbs_dbg_test_grp8_pad_mux, +}; + +static struct atlas7_pad_mux cvbs_dbg_test_grp9_pad_mux[] = { + MUX(1, 66, 3, N, N, N, N), +}; + +static struct atlas7_grp_mux cvbs_dbg_test_grp9_mux = { + .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp9_pad_mux), + .pad_mux_list = cvbs_dbg_test_grp9_pad_mux, +}; + +static struct atlas7_pad_mux cvbs_dbg_test_grp10_pad_mux[] = { + MUX(1, 67, 3, N, N, N, N), +}; + +static struct atlas7_grp_mux cvbs_dbg_test_grp10_mux = { + .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp10_pad_mux), + .pad_mux_list = cvbs_dbg_test_grp10_pad_mux, +}; + +static struct atlas7_pad_mux cvbs_dbg_test_grp11_pad_mux[] = { + MUX(1, 68, 3, N, N, N, N), +}; + +static struct atlas7_grp_mux cvbs_dbg_test_grp11_mux = { + .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp11_pad_mux), + .pad_mux_list = cvbs_dbg_test_grp11_pad_mux, +}; + +static struct atlas7_pad_mux cvbs_dbg_test_grp12_pad_mux[] = { + MUX(1, 69, 3, N, N, N, N), +}; + +static struct atlas7_grp_mux cvbs_dbg_test_grp12_mux = { + .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp12_pad_mux), + .pad_mux_list = cvbs_dbg_test_grp12_pad_mux, +}; + +static struct atlas7_pad_mux cvbs_dbg_test_grp13_pad_mux[] = { + MUX(1, 70, 3, N, N, N, N), +}; + +static struct atlas7_grp_mux cvbs_dbg_test_grp13_mux = { + .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp13_pad_mux), + .pad_mux_list = cvbs_dbg_test_grp13_pad_mux, +}; + +static struct atlas7_pad_mux cvbs_dbg_test_grp14_pad_mux[] = { + MUX(1, 71, 3, N, N, N, N), +}; + +static struct atlas7_grp_mux cvbs_dbg_test_grp14_mux = { + .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp14_pad_mux), + .pad_mux_list = cvbs_dbg_test_grp14_pad_mux, +}; + +static struct atlas7_pad_mux cvbs_dbg_test_grp15_pad_mux[] = { + MUX(1, 72, 3, N, N, N, N), +}; + +static struct atlas7_grp_mux cvbs_dbg_test_grp15_mux = { + .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp15_pad_mux), + .pad_mux_list = cvbs_dbg_test_grp15_pad_mux, +}; + +static struct atlas7_pad_mux gn_gnss_power_grp_pad_mux[] = { + MUX(1, 123, 7, N, N, N, N), + MUX(1, 124, 7, N, N, N, N), + MUX(1, 121, 7, N, N, N, N), + MUX(1, 122, 7, N, N, N, N), + MUX(1, 125, 7, N, N, N, N), + MUX(1, 120, 7, N, N, N, N), +}; + +static struct atlas7_grp_mux gn_gnss_power_grp_mux = { + .pad_mux_count = ARRAY_SIZE(gn_gnss_power_grp_pad_mux), + .pad_mux_list = gn_gnss_power_grp_pad_mux, +}; + +static struct atlas7_pad_mux gn_gnss_sw_status_grp_pad_mux[] = { + MUX(1, 57, 7, N, N, N, N), + MUX(1, 58, 7, N, N, N, N), + MUX(1, 59, 7, N, N, N, N), + MUX(1, 60, 7, N, N, N, N), + MUX(1, 61, 7, N, N, N, N), + MUX(1, 62, 7, N, N, N, N), + MUX(1, 63, 7, N, N, N, N), + MUX(1, 64, 7, N, N, N, N), + MUX(1, 65, 7, N, N, N, N), + MUX(1, 66, 7, N, N, N, N), + MUX(1, 67, 7, N, N, N, N), + MUX(1, 68, 7, N, N, N, N), + MUX(1, 69, 7, N, N, N, N), + MUX(1, 70, 7, N, N, N, N), + MUX(1, 71, 7, N, N, N, N), + MUX(1, 72, 7, N, N, N, N), + MUX(1, 53, 7, N, N, N, N), + MUX(1, 55, 7, N, N, N, N), + MUX(1, 56, 7, 0xa08, 12, 0xa88, 12), + MUX(1, 54, 7, N, N, N, N), +}; + +static struct atlas7_grp_mux gn_gnss_sw_status_grp_mux = { + .pad_mux_count = ARRAY_SIZE(gn_gnss_sw_status_grp_pad_mux), + .pad_mux_list = gn_gnss_sw_status_grp_pad_mux, +}; + +static struct atlas7_pad_mux gn_gnss_eclk_grp_pad_mux[] = { + MUX(1, 113, 4, N, N, N, N), +}; + +static struct atlas7_grp_mux gn_gnss_eclk_grp_mux = { + .pad_mux_count = ARRAY_SIZE(gn_gnss_eclk_grp_pad_mux), + .pad_mux_list = gn_gnss_eclk_grp_pad_mux, +}; + +static struct atlas7_pad_mux gn_gnss_irq1_grp0_pad_mux[] = { + MUX(1, 112, 4, 0xa08, 10, 0xa88, 10), +}; + +static struct atlas7_grp_mux gn_gnss_irq1_grp0_mux = { + .pad_mux_count = ARRAY_SIZE(gn_gnss_irq1_grp0_pad_mux), + .pad_mux_list = gn_gnss_irq1_grp0_pad_mux, +}; + +static struct atlas7_pad_mux gn_gnss_irq2_grp0_pad_mux[] = { + MUX(1, 118, 4, 0xa08, 11, 0xa88, 11), +}; + +static struct atlas7_grp_mux gn_gnss_irq2_grp0_mux = { + .pad_mux_count = ARRAY_SIZE(gn_gnss_irq2_grp0_pad_mux), + .pad_mux_list = gn_gnss_irq2_grp0_pad_mux, +}; + +static struct atlas7_pad_mux gn_gnss_tm_grp_pad_mux[] = { + MUX(1, 115, 4, N, N, N, N), +}; + +static struct atlas7_grp_mux gn_gnss_tm_grp_mux = { + .pad_mux_count = ARRAY_SIZE(gn_gnss_tm_grp_pad_mux), + .pad_mux_list = gn_gnss_tm_grp_pad_mux, +}; + +static struct atlas7_pad_mux gn_gnss_tsync_grp_pad_mux[] = { + MUX(1, 114, 4, N, N, N, N), +}; + +static struct atlas7_grp_mux gn_gnss_tsync_grp_mux = { + .pad_mux_count = ARRAY_SIZE(gn_gnss_tsync_grp_pad_mux), + .pad_mux_list = gn_gnss_tsync_grp_pad_mux, +}; + +static struct atlas7_pad_mux gn_io_gnsssys_sw_cfg_grp_pad_mux[] = { + MUX(1, 44, 7, N, N, N, N), + MUX(1, 43, 7, N, N, N, N), + MUX(1, 42, 7, N, N, N, N), + MUX(1, 41, 7, N, N, N, N), + MUX(1, 40, 7, N, N, N, N), + MUX(1, 39, 7, N, N, N, N), + MUX(1, 38, 7, N, N, N, N), + MUX(1, 37, 7, N, N, N, N), + MUX(1, 49, 7, N, N, N, N), + MUX(1, 50, 7, N, N, N, N), + MUX(1, 91, 7, N, N, N, N), + MUX(1, 92, 7, N, N, N, N), + MUX(1, 93, 7, N, N, N, N), + MUX(1, 94, 7, N, N, N, N), + MUX(1, 95, 7, N, N, N, N), + MUX(1, 96, 7, N, N, N, N), +}; + +static struct atlas7_grp_mux gn_io_gnsssys_sw_cfg_grp_mux = { + .pad_mux_count = ARRAY_SIZE(gn_io_gnsssys_sw_cfg_grp_pad_mux), + .pad_mux_list = gn_io_gnsssys_sw_cfg_grp_pad_mux, +}; + +static struct atlas7_pad_mux gn_trg_grp0_pad_mux[] = { + MUX(1, 29, 1, 0xa00, 6, 0xa80, 6), + MUX(1, 28, 1, 0xa00, 7, 0xa80, 7), + MUX(1, 26, 1, 0xa00, 8, 0xa80, 8), + MUX(1, 27, 1, 0xa00, 9, 0xa80, 9), +}; + +static struct atlas7_grp_mux gn_trg_grp0_mux = { + .pad_mux_count = ARRAY_SIZE(gn_trg_grp0_pad_mux), + .pad_mux_list = gn_trg_grp0_pad_mux, +}; + +static struct atlas7_pad_mux gn_trg_grp1_pad_mux[] = { + MUX(1, 77, 3, 0xa00, 6, 0xa80, 6), + MUX(1, 76, 3, 0xa00, 7, 0xa80, 7), + MUX(1, 74, 3, 0xa00, 8, 0xa80, 8), + MUX(1, 75, 3, 0xa00, 9, 0xa80, 9), +}; + +static struct atlas7_grp_mux gn_trg_grp1_mux = { + .pad_mux_count = ARRAY_SIZE(gn_trg_grp1_pad_mux), + .pad_mux_list = gn_trg_grp1_pad_mux, +}; + +static struct atlas7_pad_mux gn_trg_shutdown_grp0_pad_mux[] = { + MUX(1, 30, 1, N, N, N, N), +}; + +static struct atlas7_grp_mux gn_trg_shutdown_grp0_mux = { + .pad_mux_count = ARRAY_SIZE(gn_trg_shutdown_grp0_pad_mux), + .pad_mux_list = gn_trg_shutdown_grp0_pad_mux, +}; + +static struct atlas7_pad_mux gn_trg_shutdown_grp1_pad_mux[] = { + MUX(1, 83, 3, N, N, N, N), +}; + +static struct atlas7_grp_mux gn_trg_shutdown_grp1_mux = { + .pad_mux_count = ARRAY_SIZE(gn_trg_shutdown_grp1_pad_mux), + .pad_mux_list = gn_trg_shutdown_grp1_pad_mux, +}; + +static struct atlas7_pad_mux gn_trg_shutdown_grp2_pad_mux[] = { + MUX(1, 117, 4, N, N, N, N), +}; + +static struct atlas7_grp_mux gn_trg_shutdown_grp2_mux = { + .pad_mux_count = ARRAY_SIZE(gn_trg_shutdown_grp2_pad_mux), + .pad_mux_list = gn_trg_shutdown_grp2_pad_mux, +}; + +static struct atlas7_pad_mux gn_trg_shutdown_grp3_pad_mux[] = { + MUX(1, 123, 5, N, N, N, N), +}; + +static struct atlas7_grp_mux gn_trg_shutdown_grp3_mux = { + .pad_mux_count = ARRAY_SIZE(gn_trg_shutdown_grp3_pad_mux), + .pad_mux_list = gn_trg_shutdown_grp3_pad_mux, +}; + +static struct atlas7_pad_mux i2c0_grp_pad_mux[] = { + MUX(1, 128, 1, N, N, N, N), + MUX(1, 127, 1, N, N, N, N), +}; + +static struct atlas7_grp_mux i2c0_grp_mux = { + .pad_mux_count = ARRAY_SIZE(i2c0_grp_pad_mux), + .pad_mux_list = i2c0_grp_pad_mux, +}; + +static struct atlas7_pad_mux i2c1_grp_pad_mux[] = { + MUX(1, 126, 4, N, N, N, N), + MUX(1, 125, 4, N, N, N, N), +}; + +static struct atlas7_grp_mux i2c1_grp_mux = { + .pad_mux_count = ARRAY_SIZE(i2c1_grp_pad_mux), + .pad_mux_list = i2c1_grp_pad_mux, +}; + +static struct atlas7_pad_mux jtag_grp0_pad_mux[] = { + MUX(1, 125, 5, 0xa08, 2, 0xa88, 2), + MUX(0, 4, 3, 0xa08, 3, 0xa88, 3), + MUX(0, 2, 3, N, N, N, N), + MUX(0, 0, 3, N, N, N, N), + MUX(0, 1, 3, N, N, N, N), + MUX(0, 3, 3, N, N, N, N), +}; + +static struct atlas7_grp_mux jtag_grp0_mux = { + .pad_mux_count = ARRAY_SIZE(jtag_grp0_pad_mux), + .pad_mux_list = jtag_grp0_pad_mux, +}; + +static struct atlas7_pad_mux ks_kas_spi_grp0_pad_mux[] = { + MUX(1, 141, 2, N, N, N, N), + MUX(1, 144, 2, 0xa08, 8, 0xa88, 8), + MUX(1, 143, 2, N, N, N, N), + MUX(1, 142, 2, N, N, N, N), +}; + +static struct atlas7_grp_mux ks_kas_spi_grp0_mux = { + .pad_mux_count = ARRAY_SIZE(ks_kas_spi_grp0_pad_mux), + .pad_mux_list = ks_kas_spi_grp0_pad_mux, +}; + +static struct atlas7_pad_mux ld_ldd_grp_pad_mux[] = { + MUX(1, 57, 1, N, N, N, N), + MUX(1, 58, 1, N, N, N, N), + MUX(1, 59, 1, N, N, N, N), + MUX(1, 60, 1, N, N, N, N), + MUX(1, 61, 1, N, N, N, N), + MUX(1, 62, 1, N, N, N, N), + MUX(1, 63, 1, N, N, N, N), + MUX(1, 64, 1, N, N, N, N), + MUX(1, 65, 1, N, N, N, N), + MUX(1, 66, 1, N, N, N, N), + MUX(1, 67, 1, N, N, N, N), + MUX(1, 68, 1, N, N, N, N), + MUX(1, 69, 1, N, N, N, N), + MUX(1, 70, 1, N, N, N, N), + MUX(1, 71, 1, N, N, N, N), + MUX(1, 72, 1, N, N, N, N), + MUX(1, 74, 2, N, N, N, N), + MUX(1, 75, 2, N, N, N, N), + MUX(1, 76, 2, N, N, N, N), + MUX(1, 77, 2, N, N, N, N), + MUX(1, 78, 2, N, N, N, N), + MUX(1, 79, 2, N, N, N, N), + MUX(1, 80, 2, N, N, N, N), + MUX(1, 81, 2, N, N, N, N), + MUX(1, 56, 1, N, N, N, N), + MUX(1, 53, 1, N, N, N, N), +}; + +static struct atlas7_grp_mux ld_ldd_grp_mux = { + .pad_mux_count = ARRAY_SIZE(ld_ldd_grp_pad_mux), + .pad_mux_list = ld_ldd_grp_pad_mux, +}; + +static struct atlas7_pad_mux ld_ldd_16bit_grp_pad_mux[] = { + MUX(1, 57, 1, N, N, N, N), + MUX(1, 58, 1, N, N, N, N), + MUX(1, 59, 1, N, N, N, N), + MUX(1, 60, 1, N, N, N, N), + MUX(1, 61, 1, N, N, N, N), + MUX(1, 62, 1, N, N, N, N), + MUX(1, 63, 1, N, N, N, N), + MUX(1, 64, 1, N, N, N, N), + MUX(1, 65, 1, N, N, N, N), + MUX(1, 66, 1, N, N, N, N), + MUX(1, 67, 1, N, N, N, N), + MUX(1, 68, 1, N, N, N, N), + MUX(1, 69, 1, N, N, N, N), + MUX(1, 70, 1, N, N, N, N), + MUX(1, 71, 1, N, N, N, N), + MUX(1, 72, 1, N, N, N, N), + MUX(1, 56, 1, N, N, N, N), + MUX(1, 53, 1, N, N, N, N), +}; + +static struct atlas7_grp_mux ld_ldd_16bit_grp_mux = { + .pad_mux_count = ARRAY_SIZE(ld_ldd_16bit_grp_pad_mux), + .pad_mux_list = ld_ldd_16bit_grp_pad_mux, +}; + +static struct atlas7_pad_mux ld_ldd_fck_grp_pad_mux[] = { + MUX(1, 55, 1, N, N, N, N), +}; + +static struct atlas7_grp_mux ld_ldd_fck_grp_mux = { + .pad_mux_count = ARRAY_SIZE(ld_ldd_fck_grp_pad_mux), + .pad_mux_list = ld_ldd_fck_grp_pad_mux, +}; + +static struct atlas7_pad_mux ld_ldd_lck_grp_pad_mux[] = { + MUX(1, 54, 1, N, N, N, N), +}; + +static struct atlas7_grp_mux ld_ldd_lck_grp_mux = { + .pad_mux_count = ARRAY_SIZE(ld_ldd_lck_grp_pad_mux), + .pad_mux_list = ld_ldd_lck_grp_pad_mux, +}; + +static struct atlas7_pad_mux lr_lcdrom_grp_pad_mux[] = { + MUX(1, 73, 2, N, N, N, N), + MUX(1, 54, 2, N, N, N, N), + MUX(1, 57, 2, N, N, N, N), + MUX(1, 58, 2, N, N, N, N), + MUX(1, 59, 2, N, N, N, N), + MUX(1, 60, 2, N, N, N, N), + MUX(1, 61, 2, N, N, N, N), + MUX(1, 62, 2, N, N, N, N), + MUX(1, 63, 2, N, N, N, N), + MUX(1, 64, 2, N, N, N, N), + MUX(1, 65, 2, N, N, N, N), + MUX(1, 66, 2, N, N, N, N), + MUX(1, 67, 2, N, N, N, N), + MUX(1, 68, 2, N, N, N, N), + MUX(1, 69, 2, N, N, N, N), + MUX(1, 70, 2, N, N, N, N), + MUX(1, 71, 2, N, N, N, N), + MUX(1, 72, 2, N, N, N, N), + MUX(1, 56, 2, N, N, N, N), + MUX(1, 53, 2, N, N, N, N), + MUX(1, 55, 2, N, N, N, N), +}; + +static struct atlas7_grp_mux lr_lcdrom_grp_mux = { + .pad_mux_count = ARRAY_SIZE(lr_lcdrom_grp_pad_mux), + .pad_mux_list = lr_lcdrom_grp_pad_mux, +}; + +static struct atlas7_pad_mux lvds_analog_grp_pad_mux[] = { + MUX(1, 149, 8, N, N, N, N), + MUX(1, 150, 8, N, N, N, N), + MUX(1, 151, 8, N, N, N, N), + MUX(1, 152, 8, N, N, N, N), + MUX(1, 153, 8, N, N, N, N), + MUX(1, 154, 8, N, N, N, N), + MUX(1, 155, 8, N, N, N, N), + MUX(1, 156, 8, N, N, N, N), + MUX(1, 157, 8, N, N, N, N), + MUX(1, 158, 8, N, N, N, N), +}; + +static struct atlas7_grp_mux lvds_analog_grp_mux = { + .pad_mux_count = ARRAY_SIZE(lvds_analog_grp_pad_mux), + .pad_mux_list = lvds_analog_grp_pad_mux, +}; + +static struct atlas7_pad_mux nd_df_grp_pad_mux[] = { + MUX(1, 44, 1, N, N, N, N), + MUX(1, 43, 1, N, N, N, N), + MUX(1, 42, 1, N, N, N, N), + MUX(1, 41, 1, N, N, N, N), + MUX(1, 40, 1, N, N, N, N), + MUX(1, 39, 1, N, N, N, N), + MUX(1, 38, 1, N, N, N, N), + MUX(1, 37, 1, N, N, N, N), + MUX(1, 47, 1, N, N, N, N), + MUX(1, 46, 1, N, N, N, N), + MUX(1, 52, 1, N, N, N, N), + MUX(1, 51, 1, N, N, N, N), + MUX(1, 45, 1, N, N, N, N), + MUX(1, 49, 1, N, N, N, N), + MUX(1, 50, 1, N, N, N, N), + MUX(1, 48, 1, N, N, N, N), + MUX(1, 124, 4, N, N, N, N), +}; + +static struct atlas7_grp_mux nd_df_grp_mux = { + .pad_mux_count = ARRAY_SIZE(nd_df_grp_pad_mux), + .pad_mux_list = nd_df_grp_pad_mux, +}; + +static struct atlas7_pad_mux nd_df_nowp_grp_pad_mux[] = { + MUX(1, 44, 1, N, N, N, N), + MUX(1, 43, 1, N, N, N, N), + MUX(1, 42, 1, N, N, N, N), + MUX(1, 41, 1, N, N, N, N), + MUX(1, 40, 1, N, N, N, N), + MUX(1, 39, 1, N, N, N, N), + MUX(1, 38, 1, N, N, N, N), + MUX(1, 37, 1, N, N, N, N), + MUX(1, 47, 1, N, N, N, N), + MUX(1, 46, 1, N, N, N, N), + MUX(1, 52, 1, N, N, N, N), + MUX(1, 51, 1, N, N, N, N), + MUX(1, 45, 1, N, N, N, N), + MUX(1, 49, 1, N, N, N, N), + MUX(1, 50, 1, N, N, N, N), + MUX(1, 48, 1, N, N, N, N), +}; + +static struct atlas7_grp_mux nd_df_nowp_grp_mux = { + .pad_mux_count = ARRAY_SIZE(nd_df_nowp_grp_pad_mux), + .pad_mux_list = nd_df_nowp_grp_pad_mux, +}; + +static struct atlas7_pad_mux ps_grp_pad_mux[] = { + MUX(1, 120, 2, N, N, N, N), + MUX(1, 119, 2, N, N, N, N), +}; + +static struct atlas7_grp_mux ps_grp_mux = { + .pad_mux_count = ARRAY_SIZE(ps_grp_pad_mux), + .pad_mux_list = ps_grp_pad_mux, +}; + +static struct atlas7_pad_mux pwc_core_on_grp_pad_mux[] = { + MUX(0, 8, 1, N, N, N, N), +}; + +static struct atlas7_grp_mux pwc_core_on_grp_mux = { + .pad_mux_count = ARRAY_SIZE(pwc_core_on_grp_pad_mux), + .pad_mux_list = pwc_core_on_grp_pad_mux, +}; + +static struct atlas7_pad_mux pwc_ext_on_grp_pad_mux[] = { + MUX(0, 6, 1, N, N, N, N), +}; + +static struct atlas7_grp_mux pwc_ext_on_grp_mux = { + .pad_mux_count = ARRAY_SIZE(pwc_ext_on_grp_pad_mux), + .pad_mux_list = pwc_ext_on_grp_pad_mux, +}; + +static struct atlas7_pad_mux pwc_gpio3_clk_grp_pad_mux[] = { + MUX(0, 3, 4, N, N, N, N), +}; + +static struct atlas7_grp_mux pwc_gpio3_clk_grp_mux = { + .pad_mux_count = ARRAY_SIZE(pwc_gpio3_clk_grp_pad_mux), + .pad_mux_list = pwc_gpio3_clk_grp_pad_mux, +}; + +static struct atlas7_pad_mux pwc_io_on_grp_pad_mux[] = { + MUX(0, 9, 1, N, N, N, N), +}; + +static struct atlas7_grp_mux pwc_io_on_grp_mux = { + .pad_mux_count = ARRAY_SIZE(pwc_io_on_grp_pad_mux), + .pad_mux_list = pwc_io_on_grp_pad_mux, +}; + +static struct atlas7_pad_mux pwc_lowbatt_b_grp0_pad_mux[] = { + MUX(0, 4, 1, 0xa08, 4, 0xa88, 4), +}; + +static struct atlas7_grp_mux pwc_lowbatt_b_grp0_mux = { + .pad_mux_count = ARRAY_SIZE(pwc_lowbatt_b_grp0_pad_mux), + .pad_mux_list = pwc_lowbatt_b_grp0_pad_mux, +}; + +static struct atlas7_pad_mux pwc_mem_on_grp_pad_mux[] = { + MUX(0, 7, 1, N, N, N, N), +}; + +static struct atlas7_grp_mux pwc_mem_on_grp_mux = { + .pad_mux_count = ARRAY_SIZE(pwc_mem_on_grp_pad_mux), + .pad_mux_list = pwc_mem_on_grp_pad_mux, +}; + +static struct atlas7_pad_mux pwc_on_key_b_grp0_pad_mux[] = { + MUX(0, 5, 1, 0xa08, 5, 0xa88, 5), +}; + +static struct atlas7_grp_mux pwc_on_key_b_grp0_mux = { + .pad_mux_count = ARRAY_SIZE(pwc_on_key_b_grp0_pad_mux), + .pad_mux_list = pwc_on_key_b_grp0_pad_mux, +}; + +static struct atlas7_pad_mux pwc_wakeup_src0_grp_pad_mux[] = { + MUX(0, 0, 1, N, N, N, N), +}; + +static struct atlas7_grp_mux pwc_wakeup_src0_grp_mux = { + .pad_mux_count = ARRAY_SIZE(pwc_wakeup_src0_grp_pad_mux), + .pad_mux_list = pwc_wakeup_src0_grp_pad_mux, +}; + +static struct atlas7_pad_mux pwc_wakeup_src1_grp_pad_mux[] = { + MUX(0, 1, 1, N, N, N, N), +}; + +static struct atlas7_grp_mux pwc_wakeup_src1_grp_mux = { + .pad_mux_count = ARRAY_SIZE(pwc_wakeup_src1_grp_pad_mux), + .pad_mux_list = pwc_wakeup_src1_grp_pad_mux, +}; + +static struct atlas7_pad_mux pwc_wakeup_src2_grp_pad_mux[] = { + MUX(0, 2, 1, N, N, N, N), +}; + +static struct atlas7_grp_mux pwc_wakeup_src2_grp_mux = { + .pad_mux_count = ARRAY_SIZE(pwc_wakeup_src2_grp_pad_mux), + .pad_mux_list = pwc_wakeup_src2_grp_pad_mux, +}; + +static struct atlas7_pad_mux pwc_wakeup_src3_grp_pad_mux[] = { + MUX(0, 3, 1, N, N, N, N), +}; + +static struct atlas7_grp_mux pwc_wakeup_src3_grp_mux = { + .pad_mux_count = ARRAY_SIZE(pwc_wakeup_src3_grp_pad_mux), + .pad_mux_list = pwc_wakeup_src3_grp_pad_mux, +}; + +static struct atlas7_pad_mux pw_cko0_grp0_pad_mux[] = { + MUX(1, 123, 3, N, N, N, N), +}; + +static struct atlas7_grp_mux pw_cko0_grp0_mux = { + .pad_mux_count = ARRAY_SIZE(pw_cko0_grp0_pad_mux), + .pad_mux_list = pw_cko0_grp0_pad_mux, +}; + +static struct atlas7_pad_mux pw_cko0_grp1_pad_mux[] = { + MUX(1, 101, 4, N, N, N, N), +}; + +static struct atlas7_grp_mux pw_cko0_grp1_mux = { + .pad_mux_count = ARRAY_SIZE(pw_cko0_grp1_pad_mux), + .pad_mux_list = pw_cko0_grp1_pad_mux, +}; + +static struct atlas7_pad_mux pw_cko0_grp2_pad_mux[] = { + MUX(1, 82, 2, N, N, N, N), +}; + +static struct atlas7_grp_mux pw_cko0_grp2_mux = { + .pad_mux_count = ARRAY_SIZE(pw_cko0_grp2_pad_mux), + .pad_mux_list = pw_cko0_grp2_pad_mux, +}; + +static struct atlas7_pad_mux pw_cko1_grp0_pad_mux[] = { + MUX(1, 124, 3, N, N, N, N), +}; + +static struct atlas7_grp_mux pw_cko1_grp0_mux = { + .pad_mux_count = ARRAY_SIZE(pw_cko1_grp0_pad_mux), + .pad_mux_list = pw_cko1_grp0_pad_mux, +}; + +static struct atlas7_pad_mux pw_cko1_grp1_pad_mux[] = { + MUX(1, 110, 4, N, N, N, N), +}; + +static struct atlas7_grp_mux pw_cko1_grp1_mux = { + .pad_mux_count = ARRAY_SIZE(pw_cko1_grp1_pad_mux), + .pad_mux_list = pw_cko1_grp1_pad_mux, +}; + +static struct atlas7_pad_mux pw_i2s01_clk_grp0_pad_mux[] = { + MUX(1, 125, 3, N, N, N, N), +}; + +static struct atlas7_grp_mux pw_i2s01_clk_grp0_mux = { + .pad_mux_count = ARRAY_SIZE(pw_i2s01_clk_grp0_pad_mux), + .pad_mux_list = pw_i2s01_clk_grp0_pad_mux, +}; + +static struct atlas7_pad_mux pw_i2s01_clk_grp1_pad_mux[] = { + MUX(1, 117, 3, N, N, N, N), +}; + +static struct atlas7_grp_mux pw_i2s01_clk_grp1_mux = { + .pad_mux_count = ARRAY_SIZE(pw_i2s01_clk_grp1_pad_mux), + .pad_mux_list = pw_i2s01_clk_grp1_pad_mux, +}; + +static struct atlas7_pad_mux pw_pwm0_grp_pad_mux[] = { + MUX(1, 119, 3, N, N, N, N), +}; + +static struct atlas7_grp_mux pw_pwm0_grp_mux = { + .pad_mux_count = ARRAY_SIZE(pw_pwm0_grp_pad_mux), + .pad_mux_list = pw_pwm0_grp_pad_mux, +}; + +static struct atlas7_pad_mux pw_pwm1_grp_pad_mux[] = { + MUX(1, 120, 3, N, N, N, N), +}; + +static struct atlas7_grp_mux pw_pwm1_grp_mux = { + .pad_mux_count = ARRAY_SIZE(pw_pwm1_grp_pad_mux), + .pad_mux_list = pw_pwm1_grp_pad_mux, +}; + +static struct atlas7_pad_mux pw_pwm2_grp0_pad_mux[] = { + MUX(1, 121, 3, N, N, N, N), +}; + +static struct atlas7_grp_mux pw_pwm2_grp0_mux = { + .pad_mux_count = ARRAY_SIZE(pw_pwm2_grp0_pad_mux), + .pad_mux_list = pw_pwm2_grp0_pad_mux, +}; + +static struct atlas7_pad_mux pw_pwm2_grp1_pad_mux[] = { + MUX(1, 98, 3, N, N, N, N), +}; + +static struct atlas7_grp_mux pw_pwm2_grp1_mux = { + .pad_mux_count = ARRAY_SIZE(pw_pwm2_grp1_pad_mux), + .pad_mux_list = pw_pwm2_grp1_pad_mux, +}; + +static struct atlas7_pad_mux pw_pwm3_grp0_pad_mux[] = { + MUX(1, 122, 3, N, N, N, N), +}; + +static struct atlas7_grp_mux pw_pwm3_grp0_mux = { + .pad_mux_count = ARRAY_SIZE(pw_pwm3_grp0_pad_mux), + .pad_mux_list = pw_pwm3_grp0_pad_mux, +}; + +static struct atlas7_pad_mux pw_pwm3_grp1_pad_mux[] = { + MUX(1, 73, 4, N, N, N, N), +}; + +static struct atlas7_grp_mux pw_pwm3_grp1_mux = { + .pad_mux_count = ARRAY_SIZE(pw_pwm3_grp1_pad_mux), + .pad_mux_list = pw_pwm3_grp1_pad_mux, +}; + +static struct atlas7_pad_mux pw_pwm_cpu_vol_grp0_pad_mux[] = { + MUX(1, 121, 3, N, N, N, N), +}; + +static struct atlas7_grp_mux pw_pwm_cpu_vol_grp0_mux = { + .pad_mux_count = ARRAY_SIZE(pw_pwm_cpu_vol_grp0_pad_mux), + .pad_mux_list = pw_pwm_cpu_vol_grp0_pad_mux, +}; + +static struct atlas7_pad_mux pw_pwm_cpu_vol_grp1_pad_mux[] = { + MUX(1, 98, 3, N, N, N, N), +}; + +static struct atlas7_grp_mux pw_pwm_cpu_vol_grp1_mux = { + .pad_mux_count = ARRAY_SIZE(pw_pwm_cpu_vol_grp1_pad_mux), + .pad_mux_list = pw_pwm_cpu_vol_grp1_pad_mux, +}; + +static struct atlas7_pad_mux pw_backlight_grp0_pad_mux[] = { + MUX(1, 122, 3, N, N, N, N), +}; + +static struct atlas7_grp_mux pw_backlight_grp0_mux = { + .pad_mux_count = ARRAY_SIZE(pw_backlight_grp0_pad_mux), + .pad_mux_list = pw_backlight_grp0_pad_mux, +}; + +static struct atlas7_pad_mux pw_backlight_grp1_pad_mux[] = { + MUX(1, 73, 4, N, N, N, N), +}; + +static struct atlas7_grp_mux pw_backlight_grp1_mux = { + .pad_mux_count = ARRAY_SIZE(pw_backlight_grp1_pad_mux), + .pad_mux_list = pw_backlight_grp1_pad_mux, +}; + +static struct atlas7_pad_mux rg_eth_mac_grp_pad_mux[] = { + MUX(1, 108, 1, N, N, N, N), + MUX(1, 103, 1, N, N, N, N), + MUX(1, 104, 1, N, N, N, N), + MUX(1, 105, 1, N, N, N, N), + MUX(1, 106, 1, N, N, N, N), + MUX(1, 107, 1, N, N, N, N), + MUX(1, 102, 1, N, N, N, N), + MUX(1, 97, 1, N, N, N, N), + MUX(1, 98, 1, N, N, N, N), + MUX(1, 99, 1, N, N, N, N), + MUX(1, 100, 1, N, N, N, N), + MUX(1, 101, 1, N, N, N, N), +}; + +static struct atlas7_grp_mux rg_eth_mac_grp_mux = { + .pad_mux_count = ARRAY_SIZE(rg_eth_mac_grp_pad_mux), + .pad_mux_list = rg_eth_mac_grp_pad_mux, +}; + +static struct atlas7_pad_mux rg_gmac_phy_intr_n_grp_pad_mux[] = { + MUX(1, 111, 1, 0xa08, 13, 0xa88, 13), +}; + +static struct atlas7_grp_mux rg_gmac_phy_intr_n_grp_mux = { + .pad_mux_count = ARRAY_SIZE(rg_gmac_phy_intr_n_grp_pad_mux), + .pad_mux_list = rg_gmac_phy_intr_n_grp_pad_mux, +}; + +static struct atlas7_pad_mux rg_rgmii_mac_grp_pad_mux[] = { + MUX(1, 109, 1, N, N, N, N), + MUX(1, 110, 1, N, N, N, N), +}; + +static struct atlas7_grp_mux rg_rgmii_mac_grp_mux = { + .pad_mux_count = ARRAY_SIZE(rg_rgmii_mac_grp_pad_mux), + .pad_mux_list = rg_rgmii_mac_grp_pad_mux, +}; + +static struct atlas7_pad_mux rg_rgmii_phy_ref_clk_grp0_pad_mux[] = { + MUX(1, 111, 5, N, N, N, N), +}; + +static struct atlas7_grp_mux rg_rgmii_phy_ref_clk_grp0_mux = { + .pad_mux_count = ARRAY_SIZE(rg_rgmii_phy_ref_clk_grp0_pad_mux), + .pad_mux_list = rg_rgmii_phy_ref_clk_grp0_pad_mux, +}; + +static struct atlas7_pad_mux rg_rgmii_phy_ref_clk_grp1_pad_mux[] = { + MUX(1, 53, 4, N, N, N, N), +}; + +static struct atlas7_grp_mux rg_rgmii_phy_ref_clk_grp1_mux = { + .pad_mux_count = ARRAY_SIZE(rg_rgmii_phy_ref_clk_grp1_pad_mux), + .pad_mux_list = rg_rgmii_phy_ref_clk_grp1_pad_mux, +}; + +static struct atlas7_pad_mux sd0_grp_pad_mux[] = { + MUX(1, 46, 2, N, N, N, N), + MUX(1, 47, 2, N, N, N, N), + MUX(1, 44, 2, N, N, N, N), + MUX(1, 43, 2, N, N, N, N), + MUX(1, 42, 2, N, N, N, N), + MUX(1, 41, 2, N, N, N, N), + MUX(1, 40, 2, N, N, N, N), + MUX(1, 39, 2, N, N, N, N), + MUX(1, 38, 2, N, N, N, N), + MUX(1, 37, 2, N, N, N, N), +}; + +static struct atlas7_grp_mux sd0_grp_mux = { + .pad_mux_count = ARRAY_SIZE(sd0_grp_pad_mux), + .pad_mux_list = sd0_grp_pad_mux, +}; + +static struct atlas7_pad_mux sd0_4bit_grp_pad_mux[] = { + MUX(1, 46, 2, N, N, N, N), + MUX(1, 47, 2, N, N, N, N), + MUX(1, 44, 2, N, N, N, N), + MUX(1, 43, 2, N, N, N, N), + MUX(1, 42, 2, N, N, N, N), + MUX(1, 41, 2, N, N, N, N), +}; + +static struct atlas7_grp_mux sd0_4bit_grp_mux = { + .pad_mux_count = ARRAY_SIZE(sd0_4bit_grp_pad_mux), + .pad_mux_list = sd0_4bit_grp_pad_mux, +}; + +static struct atlas7_pad_mux sd1_grp_pad_mux[] = { + MUX(1, 48, 3, N, N, N, N), + MUX(1, 49, 3, N, N, N, N), + MUX(1, 44, 3, 0xa00, 0, 0xa80, 0), + MUX(1, 43, 3, 0xa00, 1, 0xa80, 1), + MUX(1, 42, 3, 0xa00, 2, 0xa80, 2), + MUX(1, 41, 3, 0xa00, 3, 0xa80, 3), + MUX(1, 40, 3, N, N, N, N), + MUX(1, 39, 3, N, N, N, N), + MUX(1, 38, 3, N, N, N, N), + MUX(1, 37, 3, N, N, N, N), +}; + +static struct atlas7_grp_mux sd1_grp_mux = { + .pad_mux_count = ARRAY_SIZE(sd1_grp_pad_mux), + .pad_mux_list = sd1_grp_pad_mux, +}; + +static struct atlas7_pad_mux sd1_4bit_grp0_pad_mux[] = { + MUX(1, 48, 3, N, N, N, N), + MUX(1, 49, 3, N, N, N, N), + MUX(1, 44, 3, 0xa00, 0, 0xa80, 0), + MUX(1, 43, 3, 0xa00, 1, 0xa80, 1), + MUX(1, 42, 3, 0xa00, 2, 0xa80, 2), + MUX(1, 41, 3, 0xa00, 3, 0xa80, 3), +}; + +static struct atlas7_grp_mux sd1_4bit_grp0_mux = { + .pad_mux_count = ARRAY_SIZE(sd1_4bit_grp0_pad_mux), + .pad_mux_list = sd1_4bit_grp0_pad_mux, +}; + +static struct atlas7_pad_mux sd1_4bit_grp1_pad_mux[] = { + MUX(1, 48, 3, N, N, N, N), + MUX(1, 49, 3, N, N, N, N), + MUX(1, 40, 4, 0xa00, 0, 0xa80, 0), + MUX(1, 39, 4, 0xa00, 1, 0xa80, 1), + MUX(1, 38, 4, 0xa00, 2, 0xa80, 2), + MUX(1, 37, 4, 0xa00, 3, 0xa80, 3), +}; + +static struct atlas7_grp_mux sd1_4bit_grp1_mux = { + .pad_mux_count = ARRAY_SIZE(sd1_4bit_grp1_pad_mux), + .pad_mux_list = sd1_4bit_grp1_pad_mux, +}; + +static struct atlas7_pad_mux sd2_grp0_pad_mux[] = { + MUX(1, 124, 2, 0xa08, 7, 0xa88, 7), + MUX(1, 31, 1, N, N, N, N), + MUX(1, 32, 1, N, N, N, N), + MUX(1, 33, 1, N, N, N, N), + MUX(1, 34, 1, N, N, N, N), + MUX(1, 35, 1, N, N, N, N), + MUX(1, 36, 1, N, N, N, N), + MUX(1, 123, 2, N, N, N, N), +}; + +static struct atlas7_grp_mux sd2_grp0_mux = { + .pad_mux_count = ARRAY_SIZE(sd2_grp0_pad_mux), + .pad_mux_list = sd2_grp0_pad_mux, +}; + +static struct atlas7_pad_mux sd2_no_cdb_grp0_pad_mux[] = { + MUX(1, 31, 1, N, N, N, N), + MUX(1, 32, 1, N, N, N, N), + MUX(1, 33, 1, N, N, N, N), + MUX(1, 34, 1, N, N, N, N), + MUX(1, 35, 1, N, N, N, N), + MUX(1, 36, 1, N, N, N, N), + MUX(1, 123, 2, N, N, N, N), +}; + +static struct atlas7_grp_mux sd2_no_cdb_grp0_mux = { + .pad_mux_count = ARRAY_SIZE(sd2_no_cdb_grp0_pad_mux), + .pad_mux_list = sd2_no_cdb_grp0_pad_mux, +}; + +static struct atlas7_pad_mux sd3_grp_pad_mux[] = { + MUX(1, 85, 1, N, N, N, N), + MUX(1, 86, 1, N, N, N, N), + MUX(1, 87, 1, N, N, N, N), + MUX(1, 88, 1, N, N, N, N), + MUX(1, 89, 1, N, N, N, N), + MUX(1, 90, 1, N, N, N, N), +}; + +static struct atlas7_grp_mux sd3_grp_mux = { + .pad_mux_count = ARRAY_SIZE(sd3_grp_pad_mux), + .pad_mux_list = sd3_grp_pad_mux, +}; + +static struct atlas7_pad_mux sd5_grp_pad_mux[] = { + MUX(1, 91, 1, N, N, N, N), + MUX(1, 92, 1, N, N, N, N), + MUX(1, 93, 1, N, N, N, N), + MUX(1, 94, 1, N, N, N, N), + MUX(1, 95, 1, N, N, N, N), + MUX(1, 96, 1, N, N, N, N), +}; + +static struct atlas7_grp_mux sd5_grp_mux = { + .pad_mux_count = ARRAY_SIZE(sd5_grp_pad_mux), + .pad_mux_list = sd5_grp_pad_mux, +}; + +static struct atlas7_pad_mux sd6_grp0_pad_mux[] = { + MUX(1, 79, 4, 0xa00, 27, 0xa80, 27), + MUX(1, 78, 4, 0xa00, 26, 0xa80, 26), + MUX(1, 74, 4, 0xa00, 28, 0xa80, 28), + MUX(1, 75, 4, 0xa00, 29, 0xa80, 29), + MUX(1, 76, 4, 0xa00, 30, 0xa80, 30), + MUX(1, 77, 4, 0xa00, 31, 0xa80, 31), +}; + +static struct atlas7_grp_mux sd6_grp0_mux = { + .pad_mux_count = ARRAY_SIZE(sd6_grp0_pad_mux), + .pad_mux_list = sd6_grp0_pad_mux, +}; + +static struct atlas7_pad_mux sd6_grp1_pad_mux[] = { + MUX(1, 101, 3, 0xa00, 27, 0xa80, 27), + MUX(1, 99, 3, 0xa00, 26, 0xa80, 26), + MUX(1, 100, 3, 0xa00, 28, 0xa80, 28), + MUX(1, 110, 3, 0xa00, 29, 0xa80, 29), + MUX(1, 109, 3, 0xa00, 30, 0xa80, 30), + MUX(1, 111, 3, 0xa00, 31, 0xa80, 31), +}; + +static struct atlas7_grp_mux sd6_grp1_mux = { + .pad_mux_count = ARRAY_SIZE(sd6_grp1_pad_mux), + .pad_mux_list = sd6_grp1_pad_mux, +}; + +static struct atlas7_pad_mux sp0_ext_ldo_on_grp_pad_mux[] = { + MUX(0, 4, 2, N, N, N, N), +}; + +static struct atlas7_grp_mux sp0_ext_ldo_on_grp_mux = { + .pad_mux_count = ARRAY_SIZE(sp0_ext_ldo_on_grp_pad_mux), + .pad_mux_list = sp0_ext_ldo_on_grp_pad_mux, +}; + +static struct atlas7_pad_mux sp0_qspi_grp_pad_mux[] = { + MUX(0, 12, 1, N, N, N, N), + MUX(0, 13, 1, N, N, N, N), + MUX(0, 14, 1, N, N, N, N), + MUX(0, 15, 1, N, N, N, N), + MUX(0, 16, 1, N, N, N, N), + MUX(0, 17, 1, N, N, N, N), +}; + +static struct atlas7_grp_mux sp0_qspi_grp_mux = { + .pad_mux_count = ARRAY_SIZE(sp0_qspi_grp_pad_mux), + .pad_mux_list = sp0_qspi_grp_pad_mux, +}; + +static struct atlas7_pad_mux sp1_spi_grp_pad_mux[] = { + MUX(1, 19, 1, N, N, N, N), + MUX(1, 20, 1, N, N, N, N), + MUX(1, 21, 1, N, N, N, N), + MUX(1, 18, 1, N, N, N, N), +}; + +static struct atlas7_grp_mux sp1_spi_grp_mux = { + .pad_mux_count = ARRAY_SIZE(sp1_spi_grp_pad_mux), + .pad_mux_list = sp1_spi_grp_pad_mux, +}; + +static struct atlas7_pad_mux tpiu_trace_grp_pad_mux[] = { + MUX(1, 53, 5, N, N, N, N), + MUX(1, 56, 5, N, N, N, N), + MUX(1, 57, 5, N, N, N, N), + MUX(1, 58, 5, N, N, N, N), + MUX(1, 59, 5, N, N, N, N), + MUX(1, 60, 5, N, N, N, N), + MUX(1, 61, 5, N, N, N, N), + MUX(1, 62, 5, N, N, N, N), + MUX(1, 63, 5, N, N, N, N), + MUX(1, 64, 5, N, N, N, N), + MUX(1, 65, 5, N, N, N, N), + MUX(1, 66, 5, N, N, N, N), + MUX(1, 67, 5, N, N, N, N), + MUX(1, 68, 5, N, N, N, N), + MUX(1, 69, 5, N, N, N, N), + MUX(1, 70, 5, N, N, N, N), + MUX(1, 71, 5, N, N, N, N), + MUX(1, 72, 5, N, N, N, N), +}; + +static struct atlas7_grp_mux tpiu_trace_grp_mux = { + .pad_mux_count = ARRAY_SIZE(tpiu_trace_grp_pad_mux), + .pad_mux_list = tpiu_trace_grp_pad_mux, +}; + +static struct atlas7_pad_mux uart0_grp_pad_mux[] = { + MUX(1, 121, 4, N, N, N, N), + MUX(1, 120, 4, N, N, N, N), + MUX(1, 134, 1, N, N, N, N), + MUX(1, 133, 1, N, N, N, N), +}; + +static struct atlas7_grp_mux uart0_grp_mux = { + .pad_mux_count = ARRAY_SIZE(uart0_grp_pad_mux), + .pad_mux_list = uart0_grp_pad_mux, +}; + +static struct atlas7_pad_mux uart0_nopause_grp_pad_mux[] = { + MUX(1, 134, 1, N, N, N, N), + MUX(1, 133, 1, N, N, N, N), +}; + +static struct atlas7_grp_mux uart0_nopause_grp_mux = { + .pad_mux_count = ARRAY_SIZE(uart0_nopause_grp_pad_mux), + .pad_mux_list = uart0_nopause_grp_pad_mux, +}; + +static struct atlas7_pad_mux uart1_grp_pad_mux[] = { + MUX(1, 136, 1, N, N, N, N), + MUX(1, 135, 1, N, N, N, N), +}; + +static struct atlas7_grp_mux uart1_grp_mux = { + .pad_mux_count = ARRAY_SIZE(uart1_grp_pad_mux), + .pad_mux_list = uart1_grp_pad_mux, +}; + +static struct atlas7_pad_mux uart2_grp_pad_mux[] = { + MUX(0, 11, 2, N, N, N, N), + MUX(0, 10, 2, N, N, N, N), +}; + +static struct atlas7_grp_mux uart2_grp_mux = { + .pad_mux_count = ARRAY_SIZE(uart2_grp_pad_mux), + .pad_mux_list = uart2_grp_pad_mux, +}; + +static struct atlas7_pad_mux uart3_grp0_pad_mux[] = { + MUX(1, 125, 2, 0xa08, 0, 0xa88, 0), + MUX(1, 126, 2, N, N, N, N), + MUX(1, 138, 1, 0xa00, 5, 0xa80, 5), + MUX(1, 137, 1, N, N, N, N), +}; + +static struct atlas7_grp_mux uart3_grp0_mux = { + .pad_mux_count = ARRAY_SIZE(uart3_grp0_pad_mux), + .pad_mux_list = uart3_grp0_pad_mux, +}; + +static struct atlas7_pad_mux uart3_grp1_pad_mux[] = { + MUX(1, 111, 4, 0xa08, 0, 0xa88, 0), + MUX(1, 109, 4, N, N, N, N), + MUX(1, 84, 2, 0xa00, 5, 0xa80, 5), + MUX(1, 83, 2, N, N, N, N), +}; + +static struct atlas7_grp_mux uart3_grp1_mux = { + .pad_mux_count = ARRAY_SIZE(uart3_grp1_pad_mux), + .pad_mux_list = uart3_grp1_pad_mux, +}; + +static struct atlas7_pad_mux uart3_grp2_pad_mux[] = { + MUX(1, 140, 2, 0xa08, 0, 0xa88, 0), + MUX(1, 139, 2, N, N, N, N), + MUX(1, 138, 1, 0xa00, 5, 0xa80, 5), + MUX(1, 137, 1, N, N, N, N), +}; + +static struct atlas7_grp_mux uart3_grp2_mux = { + .pad_mux_count = ARRAY_SIZE(uart3_grp2_pad_mux), + .pad_mux_list = uart3_grp2_pad_mux, +}; + +static struct atlas7_pad_mux uart3_grp3_pad_mux[] = { + MUX(1, 139, 2, N, N, N, N), + MUX(1, 140, 2, 0xa08, 0, 0xa88, 0), + MUX(1, 84, 2, 0xa00, 5, 0xa80, 5), + MUX(1, 83, 2, N, N, N, N), +}; + +static struct atlas7_grp_mux uart3_grp3_mux = { + .pad_mux_count = ARRAY_SIZE(uart3_grp3_pad_mux), + .pad_mux_list = uart3_grp3_pad_mux, +}; + +static struct atlas7_pad_mux uart3_nopause_grp0_pad_mux[] = { + MUX(1, 138, 1, 0xa00, 5, 0xa80, 5), + MUX(1, 137, 1, N, N, N, N), +}; + +static struct atlas7_grp_mux uart3_nopause_grp0_mux = { + .pad_mux_count = ARRAY_SIZE(uart3_nopause_grp0_pad_mux), + .pad_mux_list = uart3_nopause_grp0_pad_mux, +}; + +static struct atlas7_pad_mux uart3_nopause_grp1_pad_mux[] = { + MUX(1, 84, 2, 0xa00, 5, 0xa80, 5), + MUX(1, 83, 2, N, N, N, N), +}; + +static struct atlas7_grp_mux uart3_nopause_grp1_mux = { + .pad_mux_count = ARRAY_SIZE(uart3_nopause_grp1_pad_mux), + .pad_mux_list = uart3_nopause_grp1_pad_mux, +}; + +static struct atlas7_pad_mux uart4_grp0_pad_mux[] = { + MUX(1, 122, 4, 0xa08, 1, 0xa88, 1), + MUX(1, 123, 4, N, N, N, N), + MUX(1, 140, 1, N, N, N, N), + MUX(1, 139, 1, N, N, N, N), +}; + +static struct atlas7_grp_mux uart4_grp0_mux = { + .pad_mux_count = ARRAY_SIZE(uart4_grp0_pad_mux), + .pad_mux_list = uart4_grp0_pad_mux, +}; + +static struct atlas7_pad_mux uart4_grp1_pad_mux[] = { + MUX(1, 100, 4, 0xa08, 1, 0xa88, 1), + MUX(1, 99, 4, N, N, N, N), + MUX(1, 140, 1, N, N, N, N), + MUX(1, 139, 1, N, N, N, N), +}; + +static struct atlas7_grp_mux uart4_grp1_mux = { + .pad_mux_count = ARRAY_SIZE(uart4_grp1_pad_mux), + .pad_mux_list = uart4_grp1_pad_mux, +}; + +static struct atlas7_pad_mux uart4_grp2_pad_mux[] = { + MUX(1, 117, 2, 0xa08, 1, 0xa88, 1), + MUX(1, 116, 2, N, N, N, N), + MUX(1, 140, 1, N, N, N, N), + MUX(1, 139, 1, N, N, N, N), +}; + +static struct atlas7_grp_mux uart4_grp2_mux = { + .pad_mux_count = ARRAY_SIZE(uart4_grp2_pad_mux), + .pad_mux_list = uart4_grp2_pad_mux, +}; + +static struct atlas7_pad_mux uart4_nopause_grp_pad_mux[] = { + MUX(1, 140, 1, N, N, N, N), + MUX(1, 139, 1, N, N, N, N), +}; + +static struct atlas7_grp_mux uart4_nopause_grp_mux = { + .pad_mux_count = ARRAY_SIZE(uart4_nopause_grp_pad_mux), + .pad_mux_list = uart4_nopause_grp_pad_mux, +}; + +static struct atlas7_pad_mux usb0_drvvbus_grp_pad_mux[] = { + MUX(1, 51, 2, N, N, N, N), +}; + +static struct atlas7_grp_mux usb0_drvvbus_grp_mux = { + .pad_mux_count = ARRAY_SIZE(usb0_drvvbus_grp_pad_mux), + .pad_mux_list = usb0_drvvbus_grp_pad_mux, +}; + +static struct atlas7_pad_mux usb1_drvvbus_grp_pad_mux[] = { + MUX(1, 134, 2, N, N, N, N), +}; + +static struct atlas7_grp_mux usb1_drvvbus_grp_mux = { + .pad_mux_count = ARRAY_SIZE(usb1_drvvbus_grp_pad_mux), + .pad_mux_list = usb1_drvvbus_grp_pad_mux, +}; + +static struct atlas7_pad_mux visbus_dout_grp_pad_mux[] = { + MUX(1, 57, 6, N, N, N, N), + MUX(1, 58, 6, N, N, N, N), + MUX(1, 59, 6, N, N, N, N), + MUX(1, 60, 6, N, N, N, N), + MUX(1, 61, 6, N, N, N, N), + MUX(1, 62, 6, N, N, N, N), + MUX(1, 63, 6, N, N, N, N), + MUX(1, 64, 6, N, N, N, N), + MUX(1, 65, 6, N, N, N, N), + MUX(1, 66, 6, N, N, N, N), + MUX(1, 67, 6, N, N, N, N), + MUX(1, 68, 6, N, N, N, N), + MUX(1, 69, 6, N, N, N, N), + MUX(1, 70, 6, N, N, N, N), + MUX(1, 71, 6, N, N, N, N), + MUX(1, 72, 6, N, N, N, N), + MUX(1, 53, 6, N, N, N, N), + MUX(1, 54, 6, N, N, N, N), + MUX(1, 55, 6, N, N, N, N), + MUX(1, 56, 6, N, N, N, N), + MUX(1, 85, 6, N, N, N, N), + MUX(1, 86, 6, N, N, N, N), + MUX(1, 87, 6, N, N, N, N), + MUX(1, 88, 6, N, N, N, N), + MUX(1, 89, 6, N, N, N, N), + MUX(1, 90, 6, N, N, N, N), + MUX(1, 91, 6, N, N, N, N), + MUX(1, 92, 6, N, N, N, N), + MUX(1, 93, 6, N, N, N, N), + MUX(1, 94, 6, N, N, N, N), + MUX(1, 95, 6, N, N, N, N), + MUX(1, 96, 6, N, N, N, N), +}; + +static struct atlas7_grp_mux visbus_dout_grp_mux = { + .pad_mux_count = ARRAY_SIZE(visbus_dout_grp_pad_mux), + .pad_mux_list = visbus_dout_grp_pad_mux, +}; + +static struct atlas7_pad_mux vi_vip1_grp_pad_mux[] = { + MUX(1, 74, 1, N, N, N, N), + MUX(1, 75, 1, N, N, N, N), + MUX(1, 76, 1, N, N, N, N), + MUX(1, 77, 1, N, N, N, N), + MUX(1, 78, 1, N, N, N, N), + MUX(1, 79, 1, N, N, N, N), + MUX(1, 80, 1, N, N, N, N), + MUX(1, 81, 1, N, N, N, N), + MUX(1, 82, 1, N, N, N, N), + MUX(1, 83, 1, N, N, N, N), + MUX(1, 84, 1, N, N, N, N), + MUX(1, 103, 2, N, N, N, N), + MUX(1, 104, 2, N, N, N, N), + MUX(1, 105, 2, N, N, N, N), + MUX(1, 106, 2, N, N, N, N), + MUX(1, 107, 2, N, N, N, N), + MUX(1, 102, 2, N, N, N, N), + MUX(1, 97, 2, N, N, N, N), + MUX(1, 98, 2, N, N, N, N), +}; + +static struct atlas7_grp_mux vi_vip1_grp_mux = { + .pad_mux_count = ARRAY_SIZE(vi_vip1_grp_pad_mux), + .pad_mux_list = vi_vip1_grp_pad_mux, +}; + +static struct atlas7_pad_mux vi_vip1_ext_grp_pad_mux[] = { + MUX(1, 74, 1, N, N, N, N), + MUX(1, 75, 1, N, N, N, N), + MUX(1, 76, 1, N, N, N, N), + MUX(1, 77, 1, N, N, N, N), + MUX(1, 78, 1, N, N, N, N), + MUX(1, 79, 1, N, N, N, N), + MUX(1, 80, 1, N, N, N, N), + MUX(1, 81, 1, N, N, N, N), + MUX(1, 82, 1, N, N, N, N), + MUX(1, 83, 1, N, N, N, N), + MUX(1, 84, 1, N, N, N, N), + MUX(1, 108, 2, N, N, N, N), + MUX(1, 103, 2, N, N, N, N), + MUX(1, 104, 2, N, N, N, N), + MUX(1, 105, 2, N, N, N, N), + MUX(1, 106, 2, N, N, N, N), + MUX(1, 107, 2, N, N, N, N), + MUX(1, 102, 2, N, N, N, N), + MUX(1, 97, 2, N, N, N, N), + MUX(1, 98, 2, N, N, N, N), + MUX(1, 99, 2, N, N, N, N), + MUX(1, 100, 2, N, N, N, N), +}; + +static struct atlas7_grp_mux vi_vip1_ext_grp_mux = { + .pad_mux_count = ARRAY_SIZE(vi_vip1_ext_grp_pad_mux), + .pad_mux_list = vi_vip1_ext_grp_pad_mux, +}; + +static struct atlas7_pad_mux vi_vip1_low8bit_grp_pad_mux[] = { + MUX(1, 74, 1, N, N, N, N), + MUX(1, 75, 1, N, N, N, N), + MUX(1, 76, 1, N, N, N, N), + MUX(1, 77, 1, N, N, N, N), + MUX(1, 78, 1, N, N, N, N), + MUX(1, 79, 1, N, N, N, N), + MUX(1, 80, 1, N, N, N, N), + MUX(1, 81, 1, N, N, N, N), +}; + +static struct atlas7_grp_mux vi_vip1_low8bit_grp_mux = { + .pad_mux_count = ARRAY_SIZE(vi_vip1_low8bit_grp_pad_mux), + .pad_mux_list = vi_vip1_low8bit_grp_pad_mux, +}; + +static struct atlas7_pad_mux vi_vip1_high8bit_grp_pad_mux[] = { + MUX(1, 82, 1, N, N, N, N), + MUX(1, 83, 1, N, N, N, N), + MUX(1, 84, 1, N, N, N, N), + MUX(1, 108, 2, N, N, N, N), + MUX(1, 103, 2, N, N, N, N), + MUX(1, 104, 2, N, N, N, N), + MUX(1, 105, 2, N, N, N, N), + MUX(1, 106, 2, N, N, N, N), +}; + +static struct atlas7_grp_mux vi_vip1_high8bit_grp_mux = { + .pad_mux_count = ARRAY_SIZE(vi_vip1_high8bit_grp_pad_mux), + .pad_mux_list = vi_vip1_high8bit_grp_pad_mux, +}; + +static struct atlas7_pmx_func atlas7_pmx_functions[] = { + FUNCTION("gnss_gpio", gnss_gpio_grp, &gnss_gpio_grp_mux), + FUNCTION("lcd_vip_gpio", lcd_vip_gpio_grp, &lcd_vip_gpio_grp_mux), + FUNCTION("sdio_i2s_gpio", sdio_i2s_gpio_grp, &sdio_i2s_gpio_grp_mux), + FUNCTION("sp_rgmii_gpio", sp_rgmii_gpio_grp, &sp_rgmii_gpio_grp_mux), + FUNCTION("lvds_gpio", lvds_gpio_grp, &lvds_gpio_grp_mux), + FUNCTION("uart_nand_gpio", + uart_nand_gpio_grp, + &uart_nand_gpio_grp_mux), + FUNCTION("rtc_gpio", rtc_gpio_grp, &rtc_gpio_grp_mux), + FUNCTION("audio_ac97", audio_ac97_grp, &audio_ac97_grp_mux), + FUNCTION("audio_func_dbg", + audio_func_dbg_grp, + &audio_func_dbg_grp_mux), + FUNCTION("audio_i2s", audio_i2s_grp, &audio_i2s_grp_mux), + FUNCTION("audio_i2s_2ch", audio_i2s_2ch_grp, &audio_i2s_2ch_grp_mux), + FUNCTION("audio_i2s_extclk", + audio_i2s_extclk_grp, + &audio_i2s_extclk_grp_mux), + FUNCTION("audio_uart0", audio_uart0_grp, &audio_uart0_grp_mux), + FUNCTION("audio_uart1", audio_uart1_grp, &audio_uart1_grp_mux), + FUNCTION("audio_uart2_m0", audio_uart2_grp0, &audio_uart2_grp0_mux), + FUNCTION("audio_uart2_m1", audio_uart2_grp1, &audio_uart2_grp1_mux), + FUNCTION("c_can_trnsvr", c_can_trnsvr_grp, &c_can_trnsvr_grp_mux), + FUNCTION("c0_can_m0", c0_can_grp0, &c0_can_grp0_mux), + FUNCTION("c0_can_m1", c0_can_grp1, &c0_can_grp1_mux), + FUNCTION("c1_can_m0", c1_can_grp0, &c1_can_grp0_mux), + FUNCTION("c1_can_m1", c1_can_grp1, &c1_can_grp1_mux), + FUNCTION("c1_can_m2", c1_can_grp2, &c1_can_grp2_mux), + FUNCTION("ca_audio_lpc", ca_audio_lpc_grp, &ca_audio_lpc_grp_mux), + FUNCTION("ca_bt_lpc", ca_bt_lpc_grp, &ca_bt_lpc_grp_mux), + FUNCTION("ca_coex", ca_coex_grp, &ca_coex_grp_mux), + FUNCTION("ca_curator_lpc", + ca_curator_lpc_grp, + &ca_curator_lpc_grp_mux), + FUNCTION("ca_pcm_debug", ca_pcm_debug_grp, &ca_pcm_debug_grp_mux), + FUNCTION("ca_pio", ca_pio_grp, &ca_pio_grp_mux), + FUNCTION("ca_sdio_debug", ca_sdio_debug_grp, &ca_sdio_debug_grp_mux), + FUNCTION("ca_spi", ca_spi_grp, &ca_spi_grp_mux), + FUNCTION("ca_trb", ca_trb_grp, &ca_trb_grp_mux), + FUNCTION("ca_uart_debug", ca_uart_debug_grp, &ca_uart_debug_grp_mux), + FUNCTION("clkc_m0", clkc_grp0, &clkc_grp0_mux), + FUNCTION("clkc_m1", clkc_grp1, &clkc_grp1_mux), + FUNCTION("gn_gnss_i2c", gn_gnss_i2c_grp, &gn_gnss_i2c_grp_mux), + FUNCTION("gn_gnss_uart_nopause", + gn_gnss_uart_nopause_grp, + &gn_gnss_uart_nopause_grp_mux), + FUNCTION("gn_gnss_uart", gn_gnss_uart_grp, &gn_gnss_uart_grp_mux), + FUNCTION("gn_trg_spi_m0", gn_trg_spi_grp0, &gn_trg_spi_grp0_mux), + FUNCTION("gn_trg_spi_m1", gn_trg_spi_grp1, &gn_trg_spi_grp1_mux), + FUNCTION("cvbs_dbg", cvbs_dbg_grp, &cvbs_dbg_grp_mux), + FUNCTION("cvbs_dbg_test_m0", + cvbs_dbg_test_grp0, + &cvbs_dbg_test_grp0_mux), + FUNCTION("cvbs_dbg_test_m1", + cvbs_dbg_test_grp1, + &cvbs_dbg_test_grp1_mux), + FUNCTION("cvbs_dbg_test_m2", + cvbs_dbg_test_grp2, + &cvbs_dbg_test_grp2_mux), + FUNCTION("cvbs_dbg_test_m3", + cvbs_dbg_test_grp3, + &cvbs_dbg_test_grp3_mux), + FUNCTION("cvbs_dbg_test_m4", + cvbs_dbg_test_grp4, + &cvbs_dbg_test_grp4_mux), + FUNCTION("cvbs_dbg_test_m5", + cvbs_dbg_test_grp5, + &cvbs_dbg_test_grp5_mux), + FUNCTION("cvbs_dbg_test_m6", + cvbs_dbg_test_grp6, + &cvbs_dbg_test_grp6_mux), + FUNCTION("cvbs_dbg_test_m7", + cvbs_dbg_test_grp7, + &cvbs_dbg_test_grp7_mux), + FUNCTION("cvbs_dbg_test_m8", + cvbs_dbg_test_grp8, + &cvbs_dbg_test_grp8_mux), + FUNCTION("cvbs_dbg_test_m9", + cvbs_dbg_test_grp9, + &cvbs_dbg_test_grp9_mux), + FUNCTION("cvbs_dbg_test_m10", + cvbs_dbg_test_grp10, + &cvbs_dbg_test_grp10_mux), + FUNCTION("cvbs_dbg_test_m11", + cvbs_dbg_test_grp11, + &cvbs_dbg_test_grp11_mux), + FUNCTION("cvbs_dbg_test_m12", + cvbs_dbg_test_grp12, + &cvbs_dbg_test_grp12_mux), + FUNCTION("cvbs_dbg_test_m13", + cvbs_dbg_test_grp13, + &cvbs_dbg_test_grp13_mux), + FUNCTION("cvbs_dbg_test_m14", + cvbs_dbg_test_grp14, + &cvbs_dbg_test_grp14_mux), + FUNCTION("cvbs_dbg_test_m15", + cvbs_dbg_test_grp15, + &cvbs_dbg_test_grp15_mux), + FUNCTION("gn_gnss_power", gn_gnss_power_grp, &gn_gnss_power_grp_mux), + FUNCTION("gn_gnss_sw_status", + gn_gnss_sw_status_grp, + &gn_gnss_sw_status_grp_mux), + FUNCTION("gn_gnss_eclk", gn_gnss_eclk_grp, &gn_gnss_eclk_grp_mux), + FUNCTION("gn_gnss_irq1_m0", + gn_gnss_irq1_grp0, + &gn_gnss_irq1_grp0_mux), + FUNCTION("gn_gnss_irq2_m0", + gn_gnss_irq2_grp0, + &gn_gnss_irq2_grp0_mux), + FUNCTION("gn_gnss_tm", gn_gnss_tm_grp, &gn_gnss_tm_grp_mux), + FUNCTION("gn_gnss_tsync", gn_gnss_tsync_grp, &gn_gnss_tsync_grp_mux), + FUNCTION("gn_io_gnsssys_sw_cfg", + gn_io_gnsssys_sw_cfg_grp, + &gn_io_gnsssys_sw_cfg_grp_mux), + FUNCTION("gn_trg_m0", gn_trg_grp0, &gn_trg_grp0_mux), + FUNCTION("gn_trg_m1", gn_trg_grp1, &gn_trg_grp1_mux), + FUNCTION("gn_trg_shutdown_m0", + gn_trg_shutdown_grp0, + &gn_trg_shutdown_grp0_mux), + FUNCTION("gn_trg_shutdown_m1", + gn_trg_shutdown_grp1, + &gn_trg_shutdown_grp1_mux), + FUNCTION("gn_trg_shutdown_m2", + gn_trg_shutdown_grp2, + &gn_trg_shutdown_grp2_mux), + FUNCTION("gn_trg_shutdown_m3", + gn_trg_shutdown_grp3, + &gn_trg_shutdown_grp3_mux), + FUNCTION("i2c0", i2c0_grp, &i2c0_grp_mux), + FUNCTION("i2c1", i2c1_grp, &i2c1_grp_mux), + FUNCTION("jtag_m0", jtag_grp0, &jtag_grp0_mux), + FUNCTION("ks_kas_spi_m0", ks_kas_spi_grp0, &ks_kas_spi_grp0_mux), + FUNCTION("ld_ldd", ld_ldd_grp, &ld_ldd_grp_mux), + FUNCTION("ld_ldd_16bit", ld_ldd_16bit_grp, &ld_ldd_16bit_grp_mux), + FUNCTION("ld_ldd_fck", ld_ldd_fck_grp, &ld_ldd_fck_grp_mux), + FUNCTION("ld_ldd_lck", ld_ldd_lck_grp, &ld_ldd_lck_grp_mux), + FUNCTION("lr_lcdrom", lr_lcdrom_grp, &lr_lcdrom_grp_mux), + FUNCTION("lvds_analog", lvds_analog_grp, &lvds_analog_grp_mux), + FUNCTION("nd_df", nd_df_grp, &nd_df_grp_mux), + FUNCTION("nd_df_nowp", nd_df_nowp_grp, &nd_df_nowp_grp_mux), + FUNCTION("ps", ps_grp, &ps_grp_mux), + FUNCTION("pwc_core_on", pwc_core_on_grp, &pwc_core_on_grp_mux), + FUNCTION("pwc_ext_on", pwc_ext_on_grp, &pwc_ext_on_grp_mux), + FUNCTION("pwc_gpio3_clk", pwc_gpio3_clk_grp, &pwc_gpio3_clk_grp_mux), + FUNCTION("pwc_io_on", pwc_io_on_grp, &pwc_io_on_grp_mux), + FUNCTION("pwc_lowbatt_b_m0", + pwc_lowbatt_b_grp0, + &pwc_lowbatt_b_grp0_mux), + FUNCTION("pwc_mem_on", pwc_mem_on_grp, &pwc_mem_on_grp_mux), + FUNCTION("pwc_on_key_b_m0", + pwc_on_key_b_grp0, + &pwc_on_key_b_grp0_mux), + FUNCTION("pwc_wakeup_src0", + pwc_wakeup_src0_grp, + &pwc_wakeup_src0_grp_mux), + FUNCTION("pwc_wakeup_src1", + pwc_wakeup_src1_grp, + &pwc_wakeup_src1_grp_mux), + FUNCTION("pwc_wakeup_src2", + pwc_wakeup_src2_grp, + &pwc_wakeup_src2_grp_mux), + FUNCTION("pwc_wakeup_src3", + pwc_wakeup_src3_grp, + &pwc_wakeup_src3_grp_mux), + FUNCTION("pw_cko0_m0", pw_cko0_grp0, &pw_cko0_grp0_mux), + FUNCTION("pw_cko0_m1", pw_cko0_grp1, &pw_cko0_grp1_mux), + FUNCTION("pw_cko0_m2", pw_cko0_grp2, &pw_cko0_grp2_mux), + FUNCTION("pw_cko1_m0", pw_cko1_grp0, &pw_cko1_grp0_mux), + FUNCTION("pw_cko1_m1", pw_cko1_grp1, &pw_cko1_grp1_mux), + FUNCTION("pw_i2s01_clk_m0", + pw_i2s01_clk_grp0, + &pw_i2s01_clk_grp0_mux), + FUNCTION("pw_i2s01_clk_m1", + pw_i2s01_clk_grp1, + &pw_i2s01_clk_grp1_mux), + FUNCTION("pw_pwm0", pw_pwm0_grp, &pw_pwm0_grp_mux), + FUNCTION("pw_pwm1", pw_pwm1_grp, &pw_pwm1_grp_mux), + FUNCTION("pw_pwm2_m0", pw_pwm2_grp0, &pw_pwm2_grp0_mux), + FUNCTION("pw_pwm2_m1", pw_pwm2_grp1, &pw_pwm2_grp1_mux), + FUNCTION("pw_pwm3_m0", pw_pwm3_grp0, &pw_pwm3_grp0_mux), + FUNCTION("pw_pwm3_m1", pw_pwm3_grp1, &pw_pwm3_grp1_mux), + FUNCTION("pw_pwm_cpu_vol_m0", + pw_pwm_cpu_vol_grp0, + &pw_pwm_cpu_vol_grp0_mux), + FUNCTION("pw_pwm_cpu_vol_m1", + pw_pwm_cpu_vol_grp1, + &pw_pwm_cpu_vol_grp1_mux), + FUNCTION("pw_backlight_m0", + pw_backlight_grp0, + &pw_backlight_grp0_mux), + FUNCTION("pw_backlight_m1", + pw_backlight_grp1, + &pw_backlight_grp1_mux), + FUNCTION("rg_eth_mac", rg_eth_mac_grp, &rg_eth_mac_grp_mux), + FUNCTION("rg_gmac_phy_intr_n", + rg_gmac_phy_intr_n_grp, + &rg_gmac_phy_intr_n_grp_mux), + FUNCTION("rg_rgmii_mac", rg_rgmii_mac_grp, &rg_rgmii_mac_grp_mux), + FUNCTION("rg_rgmii_phy_ref_clk_m0", + rg_rgmii_phy_ref_clk_grp0, + &rg_rgmii_phy_ref_clk_grp0_mux), + FUNCTION("rg_rgmii_phy_ref_clk_m1", + rg_rgmii_phy_ref_clk_grp1, + &rg_rgmii_phy_ref_clk_grp1_mux), + FUNCTION("sd0", sd0_grp, &sd0_grp_mux), + FUNCTION("sd0_4bit", sd0_4bit_grp, &sd0_4bit_grp_mux), + FUNCTION("sd1", sd1_grp, &sd1_grp_mux), + FUNCTION("sd1_4bit_m0", sd1_4bit_grp0, &sd1_4bit_grp0_mux), + FUNCTION("sd1_4bit_m1", sd1_4bit_grp1, &sd1_4bit_grp1_mux), + FUNCTION("sd2_m0", sd2_grp0, &sd2_grp0_mux), + FUNCTION("sd2_no_cdb_m0", sd2_no_cdb_grp0, &sd2_no_cdb_grp0_mux), + FUNCTION("sd3", sd3_grp, &sd3_grp_mux), + FUNCTION("sd5", sd5_grp, &sd5_grp_mux), + FUNCTION("sd6_m0", sd6_grp0, &sd6_grp0_mux), + FUNCTION("sd6_m1", sd6_grp1, &sd6_grp1_mux), + FUNCTION("sp0_ext_ldo_on", + sp0_ext_ldo_on_grp, + &sp0_ext_ldo_on_grp_mux), + FUNCTION("sp0_qspi", sp0_qspi_grp, &sp0_qspi_grp_mux), + FUNCTION("sp1_spi", sp1_spi_grp, &sp1_spi_grp_mux), + FUNCTION("tpiu_trace", tpiu_trace_grp, &tpiu_trace_grp_mux), + FUNCTION("uart0", uart0_grp, &uart0_grp_mux), + FUNCTION("uart0_nopause", uart0_nopause_grp, &uart0_nopause_grp_mux), + FUNCTION("uart1", uart1_grp, &uart1_grp_mux), + FUNCTION("uart2", uart2_grp, &uart2_grp_mux), + FUNCTION("uart3_m0", uart3_grp0, &uart3_grp0_mux), + FUNCTION("uart3_m1", uart3_grp1, &uart3_grp1_mux), + FUNCTION("uart3_m2", uart3_grp2, &uart3_grp2_mux), + FUNCTION("uart3_m3", uart3_grp3, &uart3_grp3_mux), + FUNCTION("uart3_nopause_m0", + uart3_nopause_grp0, + &uart3_nopause_grp0_mux), + FUNCTION("uart3_nopause_m1", + uart3_nopause_grp1, + &uart3_nopause_grp1_mux), + FUNCTION("uart4_m0", uart4_grp0, &uart4_grp0_mux), + FUNCTION("uart4_m1", uart4_grp1, &uart4_grp1_mux), + FUNCTION("uart4_m2", uart4_grp2, &uart4_grp2_mux), + FUNCTION("uart4_nopause", uart4_nopause_grp, &uart4_nopause_grp_mux), + FUNCTION("usb0_drvvbus", usb0_drvvbus_grp, &usb0_drvvbus_grp_mux), + FUNCTION("usb1_drvvbus", usb1_drvvbus_grp, &usb1_drvvbus_grp_mux), + FUNCTION("visbus_dout", visbus_dout_grp, &visbus_dout_grp_mux), + FUNCTION("vi_vip1", vi_vip1_grp, &vi_vip1_grp_mux), + FUNCTION("vi_vip1_ext", vi_vip1_ext_grp, &vi_vip1_ext_grp_mux), + FUNCTION("vi_vip1_low8bit", + vi_vip1_low8bit_grp, + &vi_vip1_low8bit_grp_mux), + FUNCTION("vi_vip1_high8bit", + vi_vip1_high8bit_grp, + &vi_vip1_high8bit_grp_mux), +}; + +struct atlas7_pinctrl_data atlas7_ioc_data = { + .pads = (struct pinctrl_pin_desc *)atlas7_ioc_pads, + .pads_cnt = ARRAY_SIZE(atlas7_ioc_pads), + .grps = (struct atlas7_pin_group *)altas7_pin_groups, + .grps_cnt = ARRAY_SIZE(altas7_pin_groups), + .funcs = (struct atlas7_pmx_func *)atlas7_pmx_functions, + .funcs_cnt = ARRAY_SIZE(atlas7_pmx_functions), + .confs = (struct atlas7_pad_config *)atlas7_ioc_pad_confs, + .confs_cnt = ARRAY_SIZE(atlas7_ioc_pad_confs), +}; + +static inline u32 atlas7_pin_to_bank(u32 pin) +{ + return (pin >= ATLAS7_PINCTRL_BANK_0_PINS) ? 1 : 0; +} + +static int atlas7_pmx_get_funcs_count(struct pinctrl_dev *pctldev) +{ + struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); + + return pmx->pctl_data->funcs_cnt; +} + +static const char *atlas7_pmx_get_func_name(struct pinctrl_dev *pctldev, + u32 selector) +{ + struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); + + return pmx->pctl_data->funcs[selector].name; +} + +static int atlas7_pmx_get_func_groups(struct pinctrl_dev *pctldev, + u32 selector, const char * const **groups, + u32 * const num_groups) +{ + struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); + + *groups = pmx->pctl_data->funcs[selector].groups; + *num_groups = pmx->pctl_data->funcs[selector].num_groups; + + return 0; +} + +static void __atlas7_pmx_pin_input_disable_set(struct atlas7_pmx *pmx, + const struct atlas7_pad_mux *mux) +{ + /* Set Input Disable to avoid input glitches + * + * All Input-Disable Control registers are located on IOCRTC. + * So the regs bank is always 0. + * + */ + if (mux->dinput_reg && mux->dinput_val_reg) { + writel(DI_MASK << mux->dinput_bit, + pmx->regs[BANK_DS] + CLR_REG(mux->dinput_reg)); + writel(DI_DISABLE << mux->dinput_bit, + pmx->regs[BANK_DS] + mux->dinput_reg); + + + writel(DIV_MASK << mux->dinput_val_bit, + pmx->regs[BANK_DS] + CLR_REG(mux->dinput_val_reg)); + writel(DIV_DISABLE << mux->dinput_val_bit, + pmx->regs[BANK_DS] + mux->dinput_val_reg); + } +} + +static void __atlas7_pmx_pin_input_disable_clr(struct atlas7_pmx *pmx, + const struct atlas7_pad_mux *mux) +{ + /* Clear Input Disable to avoid input glitches */ + if (mux->dinput_reg && mux->dinput_val_reg) { + writel(DI_MASK << mux->dinput_bit, + pmx->regs[BANK_DS] + CLR_REG(mux->dinput_reg)); + writel(DI_ENABLE << mux->dinput_bit, + pmx->regs[BANK_DS] + mux->dinput_reg); + + writel(DIV_MASK << mux->dinput_val_bit, + pmx->regs[BANK_DS] + CLR_REG(mux->dinput_val_reg)); + writel(DIV_ENABLE << mux->dinput_val_bit, + pmx->regs[BANK_DS] + mux->dinput_val_reg); + } +} + +static int __atlas7_pmx_pin_ad_sel(struct atlas7_pmx *pmx, + struct atlas7_pad_config *conf, + u32 bank, u32 ad_sel) +{ + unsigned long regv; + + /* Write to clear register to clear A/D selector */ + writel(ANA_CLEAR_MASK << conf->ad_ctrl_bit, + pmx->regs[bank] + CLR_REG(conf->ad_ctrl_reg)); + + /* Set target pad A/D selector */ + regv = readl(pmx->regs[bank] + conf->ad_ctrl_reg); + regv &= ~(ANA_CLEAR_MASK << conf->ad_ctrl_bit); + writel(regv | (ad_sel << conf->ad_ctrl_bit), + pmx->regs[bank] + conf->ad_ctrl_reg); + + regv = readl(pmx->regs[bank] + conf->ad_ctrl_reg); + pr_debug("bank:%d reg:0x%04x val:0x%08lx\n", + bank, conf->ad_ctrl_reg, regv); + return 0; +} + +static int __atlas7_pmx_pin_analog_enable(struct atlas7_pmx *pmx, + struct atlas7_pad_config *conf, u32 bank) +{ + /* Only PAD_T_AD pins can change between Analogue&Digital */ + if (conf->type != PAD_T_AD) + return -EINVAL; + + return __atlas7_pmx_pin_ad_sel(pmx, conf, bank, 0); +} + +static int __atlas7_pmx_pin_digital_enable(struct atlas7_pmx *pmx, + struct atlas7_pad_config *conf, u32 bank) +{ + /* Other type pads are always digital */ + if (conf->type != PAD_T_AD) + return 0; + + return __atlas7_pmx_pin_ad_sel(pmx, conf, bank, 1); +} + +static int __atlas7_pmx_pin_enable(struct atlas7_pmx *pmx, + u32 pin, u32 func) +{ + struct atlas7_pad_config *conf; + u32 bank; + int ret; + unsigned long regv; + + pr_debug("PMX DUMP ### pin#%d func:%d #### START >>>\n", + pin, func); + + /* Get this Pad's descriptor from PINCTRL */ + conf = &pmx->pctl_data->confs[pin]; + bank = atlas7_pin_to_bank(pin); + + /* Just enable the analog function of this pad */ + if (FUNC_ANALOGUE == func) { + ret = __atlas7_pmx_pin_analog_enable(pmx, conf, bank); + if (ret) + dev_err(pmx->dev, + "Convert pad#%d to analog failed, ret=%d\n", + pin, ret); + return ret; + } + + /* Set Pads from analog to digital */ + ret = __atlas7_pmx_pin_digital_enable(pmx, conf, bank); + if (ret) { + dev_err(pmx->dev, + "Convert pad#%d to digital failed, ret=%d\n", + pin, ret); + return ret; + } + + /* Write to clear register to clear current function */ + writel(FUNC_CLEAR_MASK << conf->mux_bit, + pmx->regs[bank] + CLR_REG(conf->mux_reg)); + + /* Set target pad mux function */ + regv = readl(pmx->regs[bank] + conf->mux_reg); + regv &= ~(FUNC_CLEAR_MASK << conf->mux_bit); + writel(regv | (func << conf->mux_bit), + pmx->regs[bank] + conf->mux_reg); + + regv = readl(pmx->regs[bank] + conf->mux_reg); + pr_debug("bank:%d reg:0x%04x val:0x%08lx\n", + bank, conf->mux_reg, regv); + + return 0; +} + +static int atlas7_pmx_set_mux(struct pinctrl_dev *pctldev, + u32 func_selector, u32 group_selector) +{ + int idx, ret; + struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); + struct atlas7_pmx_func *pmx_func; + struct atlas7_pin_group *pin_grp; + const struct atlas7_grp_mux *grp_mux; + const struct atlas7_pad_mux *mux; + + pmx_func = &pmx->pctl_data->funcs[func_selector]; + pin_grp = &pmx->pctl_data->grps[group_selector]; + + pr_debug("PMX DUMP ### Function:[%s] Group:[%s] #### START >>>\n", + pmx_func->name, pin_grp->name); + + grp_mux = pmx_func->grpmux; + + for (idx = 0; idx < grp_mux->pad_mux_count; idx++) { + mux = &grp_mux->pad_mux_list[idx]; + __atlas7_pmx_pin_input_disable_set(pmx, mux); + ret = __atlas7_pmx_pin_enable(pmx, mux->pin, mux->func); + if (ret) { + dev_err(pmx->dev, + "FUNC:%s GRP:%s PIN#%d.%d failed, ret=%d\n", + pmx_func->name, pin_grp->name, + mux->pin, mux->func, ret); + BUG_ON(1); + } + __atlas7_pmx_pin_input_disable_clr(pmx, mux); + } + pr_debug("PMX DUMP ### Function:[%s] Group:[%s] #### END <<<\n", + pmx_func->name, pin_grp->name); + + return 0; +} + +struct atlas7_ds_info { + u32 ma; + u32 ds_16st; + u32 ds_4we; + u32 ds_0204m31; + u32 ds_0610m31; +}; + +const struct atlas7_ds_info atlas7_ds_map[] = { + { 2, DS_16ST_0, DS_4WE_0, DS_M31_0, DS_NULL}, + { 4, DS_16ST_1, DS_NULL, DS_M31_1, DS_NULL}, + { 6, DS_16ST_2, DS_NULL, DS_NULL, DS_M31_0}, + { 8, DS_16ST_3, DS_4WE_1, DS_NULL, DS_NULL}, + { 10, DS_16ST_4, DS_NULL, DS_NULL, DS_M31_1}, + { 12, DS_16ST_5, DS_NULL, DS_NULL, DS_NULL}, + { 14, DS_16ST_6, DS_NULL, DS_NULL, DS_NULL}, + { 16, DS_16ST_7, DS_4WE_2, DS_NULL, DS_NULL}, + { 18, DS_16ST_8, DS_NULL, DS_NULL, DS_NULL}, + { 20, DS_16ST_9, DS_NULL, DS_NULL, DS_NULL}, + { 22, DS_16ST_10, DS_NULL, DS_NULL, DS_NULL}, + { 24, DS_16ST_11, DS_NULL, DS_NULL, DS_NULL}, + { 26, DS_16ST_12, DS_NULL, DS_NULL, DS_NULL}, + { 28, DS_16ST_13, DS_4WE_3, DS_NULL, DS_NULL}, + { 30, DS_16ST_14, DS_NULL, DS_NULL, DS_NULL}, + { 32, DS_16ST_15, DS_NULL, DS_NULL, DS_NULL}, +}; + +static u32 convert_current_to_drive_strength(u32 type, u32 ma) +{ + int idx; + + for (idx = 0; idx < ARRAY_SIZE(atlas7_ds_map); idx++) { + if (atlas7_ds_map[idx].ma != ma) + continue; + + if (type == PAD_T_4WE_PD || type == PAD_T_4WE_PU) + return atlas7_ds_map[idx].ds_4we; + else if (type == PAD_T_16ST) + return atlas7_ds_map[idx].ds_16st; + else if (type == PAD_T_M31_0204_PD || type == PAD_T_M31_0204_PU) + return atlas7_ds_map[idx].ds_0204m31; + else if (type == PAD_T_M31_0610_PD || type == PAD_T_M31_0610_PU) + return atlas7_ds_map[idx].ds_0610m31; + } + + return DS_NULL; +} + +static int altas7_pinctrl_set_pull_sel(struct pinctrl_dev *pctldev, + u32 pin, u32 sel) +{ + struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); + struct atlas7_pad_config *conf = &pmx->pctl_data->confs[pin]; + u32 type = conf->type; + u32 shift = conf->pupd_bit; + u32 bank = atlas7_pin_to_bank(pin); + void __iomem *pull_sel_reg, *pull_clr_reg; + + pull_sel_reg = pmx->regs[bank] + conf->pupd_reg; + pull_clr_reg = CLR_REG(pull_sel_reg); + + if (type == PAD_T_4WE_PD || type == PAD_T_4WE_PU) { + writel(P4WE_PULL_MASK << shift, pull_clr_reg); + + if (sel == PULL_UP) + writel(P4WE_PULL_UP << shift, pull_sel_reg); + else if (sel == HIGH_HYSTERESIS) + writel(P4WE_HIGH_HYSTERESIS << shift, pull_sel_reg); + else if (sel == HIGH_Z) + writel(P4WE_HIGH_Z << shift, pull_sel_reg); + else if (sel == PULL_DOWN) + writel(P4WE_PULL_DOWN << shift, pull_sel_reg); + else { + pr_err("Unknown Pull select type for 4WEPAD#%d\n", + pin); + return -ENOTSUPP; + } + } else if (type == PAD_T_16ST) { + writel(P16ST_PULL_MASK << shift, pull_clr_reg); + + if (sel == PULL_UP) + writel(P16ST_PULL_UP << shift, pull_sel_reg); + else if (sel == HIGH_Z) + writel(P16ST_HIGH_Z << shift, pull_sel_reg); + else if (sel == PULL_DOWN) + writel(P16ST_PULL_DOWN << shift, pull_sel_reg); + else { + pr_err("Unknown Pull select type for 16STPAD#%d\n", + pin); + return -ENOTSUPP; + } + } else if (type == PAD_T_M31_0204_PD || + type == PAD_T_M31_0204_PU || + type == PAD_T_M31_0610_PD || + type == PAD_T_M31_0610_PU) { + writel(PM31_PULL_MASK << shift, pull_clr_reg); + + if (sel == PULL_UP) + writel(PM31_PULL_ENABLED << shift, pull_sel_reg); + else if (sel == PULL_DOWN) + writel(PM31_PULL_DISABLED << shift, pull_sel_reg); + else { + pr_err("Unknown Pull select type for M31PAD#%d\n", + pin); + return -ENOTSUPP; + } + } else if (type == PAD_T_AD) { + writel(PANGD_PULL_MASK << shift, pull_clr_reg); + + if (sel == PULL_UP) + writel(PANGD_PULL_UP << shift, pull_sel_reg); + else if (sel == HIGH_Z) + writel(PANGD_HIGH_Z << shift, pull_sel_reg); + else if (sel == PULL_DOWN) + writel(PANGD_PULL_DOWN << shift, pull_sel_reg); + else { + pr_err("Unknown Pull select type for A/D PAD#%d\n", + pin); + return -ENOTSUPP; + } + } else { + pr_err("Unknown Pad type[%d] for pull select PAD#%d\n", + type, pin); + return -ENOTSUPP; + } + + pr_debug("PIN_CFG ### SET PIN#%d PULL SELECTOR:%d == OK ####\n", + pin, sel); + return 0; +} + +static int __altas7_pinctrl_set_drive_strength_sel(struct pinctrl_dev *pctldev, + u32 pin, u32 sel) +{ + struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); + struct atlas7_pad_config *conf = &pmx->pctl_data->confs[pin]; + u32 type = conf->type; + u32 shift = conf->drvstr_bit; + u32 bank = atlas7_pin_to_bank(pin); + void __iomem *ds_sel_reg, *ds_clr_reg; + + ds_sel_reg = pmx->regs[bank] + conf->drvstr_reg; + ds_clr_reg = CLR_REG(ds_sel_reg); + if (type == PAD_T_4WE_PD || type == PAD_T_4WE_PU) { + if (sel & (~DS_2BIT_MASK)) + goto unsupport; + + writel(DS_2BIT_IM_VAL << shift, ds_clr_reg); + writel(sel << shift, ds_sel_reg); + + return 0; + } else if (type == PAD_T_16ST) { + if (sel & (~DS_4BIT_MASK)) + goto unsupport; + + writel(DS_4BIT_IM_VAL << shift, ds_clr_reg); + writel(sel << shift, ds_sel_reg); + + return 0; + } else if (type == PAD_T_M31_0204_PD || type == PAD_T_M31_0204_PU || + type == PAD_T_M31_0610_PD || type == PAD_T_M31_0610_PU) { + if (sel & (~DS_1BIT_MASK)) + goto unsupport; + + writel(DS_1BIT_IM_VAL << shift, ds_clr_reg); + writel(sel << shift, ds_sel_reg); + + return 0; + } + +unsupport: + pr_err("Pad#%d type[%d] doesn't support ds code[%d]!\n", + pin, type, sel); + return -ENOTSUPP; +} + +static int altas7_pinctrl_set_drive_strength_sel(struct pinctrl_dev *pctldev, + u32 pin, u32 ma) +{ + struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); + struct atlas7_pad_config *conf = &pmx->pctl_data->confs[pin]; + u32 type = conf->type; + u32 sel; + int ret; + + sel = convert_current_to_drive_strength(conf->type, ma); + if (DS_NULL == sel) { + pr_err("Pad#%d type[%d] doesn't support ds current[%d]!\n", + pin, type, ma); + return -ENOTSUPP; + } + + ret = __altas7_pinctrl_set_drive_strength_sel(pctldev, + pin, sel); + pr_debug("PIN_CFG ### SET PIN#%d DS:%d MA:%d == %s ####\n", + pin, sel, ma, ret?"FAILED":"OK"); + return ret; +} + +static int atlas7_pmx_gpio_request_enable(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, u32 pin) +{ + struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); + u32 idx; + + dev_dbg(pmx->dev, + "atlas7_pmx_gpio_request_enable: pin=%d\n", pin); + for (idx = 0; idx < range->npins; idx++) { + if (pin == range->pins[idx]) + break; + } + + if (idx >= range->npins) { + dev_err(pmx->dev, + "The pin#%d could not be requested as GPIO!!\n", + pin); + return -EPERM; + } + + __atlas7_pmx_pin_enable(pmx, pin, FUNC_GPIO); + + return 0; +} + +static struct pinmux_ops atlas7_pinmux_ops = { + .get_functions_count = atlas7_pmx_get_funcs_count, + .get_function_name = atlas7_pmx_get_func_name, + .get_function_groups = atlas7_pmx_get_func_groups, + .set_mux = atlas7_pmx_set_mux, + .gpio_request_enable = atlas7_pmx_gpio_request_enable, +}; + +static int atlas7_pinctrl_get_groups_count(struct pinctrl_dev *pctldev) +{ + struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); + + return pmx->pctl_data->grps_cnt; +} + +static const char *atlas7_pinctrl_get_group_name(struct pinctrl_dev *pctldev, + u32 group) +{ + struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); + + return pmx->pctl_data->grps[group].name; +} + +static int atlas7_pinctrl_get_group_pins(struct pinctrl_dev *pctldev, + u32 group, const u32 **pins, u32 *num_pins) +{ + struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); + + *num_pins = pmx->pctl_data->grps[group].num_pins; + *pins = pmx->pctl_data->grps[group].pins; + + return 0; +} + +static int atlas7_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev, + struct device_node *np_config, + struct pinctrl_map **map, + u32 *num_maps) +{ + return pinconf_generic_dt_node_to_map(pctldev, np_config, map, + num_maps, PIN_MAP_TYPE_INVALID); +} + +static void atlas7_pinctrl_dt_free_map(struct pinctrl_dev *pctldev, + struct pinctrl_map *map, u32 num_maps) +{ + kfree(map); +} + +static const struct pinctrl_ops atlas7_pinctrl_ops = { + .get_groups_count = atlas7_pinctrl_get_groups_count, + .get_group_name = atlas7_pinctrl_get_group_name, + .get_group_pins = atlas7_pinctrl_get_group_pins, + .dt_node_to_map = atlas7_pinctrl_dt_node_to_map, + .dt_free_map = atlas7_pinctrl_dt_free_map, +}; + +static int atlas7_pin_config_set(struct pinctrl_dev *pctldev, + unsigned pin, unsigned long *configs, + unsigned num_configs) +{ + u16 param, arg; + int idx, err; + + for (idx = 0; idx < num_configs; idx++) { + param = pinconf_to_config_param(configs[idx]); + arg = pinconf_to_config_argument(configs[idx]); + + pr_debug("PMX CFG###### ATLAS7 PIN#%d [%s] CONFIG PARAM:%d ARG:%d >>>>>\n", + pin, atlas7_ioc_pads[pin].name, param, arg); + switch (param) { + case PIN_CONFIG_BIAS_PULL_UP: + err = altas7_pinctrl_set_pull_sel(pctldev, + pin, PULL_UP); + if (err) + return err; + break; + + case PIN_CONFIG_BIAS_PULL_DOWN: + err = altas7_pinctrl_set_pull_sel(pctldev, + pin, PULL_DOWN); + if (err) + return err; + break; + + case PIN_CONFIG_INPUT_SCHMITT_ENABLE: + err = altas7_pinctrl_set_pull_sel(pctldev, + pin, HIGH_HYSTERESIS); + if (err) + return err; + break; + case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: + err = altas7_pinctrl_set_pull_sel(pctldev, + pin, HIGH_Z); + if (err) + return err; + break; + + case PIN_CONFIG_DRIVE_STRENGTH: + err = altas7_pinctrl_set_drive_strength_sel(pctldev, + pin, arg); + if (err) + return err; + break; + default: + return -ENOTSUPP; + } + pr_debug("PMX CFG###### ATLAS7 PIN#%d [%s] CONFIG PARAM:%d ARG:%d <<<<\n", + pin, atlas7_ioc_pads[pin].name, param, arg); + } + + return 0; +} + +static int atlas7_pin_config_group_set(struct pinctrl_dev *pctldev, + unsigned group, unsigned long *configs, + unsigned num_configs) +{ + const unsigned *pins; + unsigned npins; + int i, ret; + + ret = atlas7_pinctrl_get_group_pins(pctldev, group, &pins, &npins); + if (ret) + return ret; + for (i = 0; i < npins; i++) { + if (atlas7_pin_config_set(pctldev, pins[i], + configs, num_configs)) + return -ENOTSUPP; + } + return 0; +} + +static const struct pinconf_ops atlas7_pinconf_ops = { + .pin_config_set = atlas7_pin_config_set, + .pin_config_group_set = atlas7_pin_config_group_set, + .is_generic = true, +}; + +static int atlas7_pinmux_probe(struct platform_device *pdev) +{ + int ret, idx; + struct atlas7_pmx *pmx; + struct device_node *np = pdev->dev.of_node; + u32 banks = ATLAS7_PINCTRL_REG_BANKS; + + /* Create state holders etc for this driver */ + pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL); + if (!pmx) + return -ENOMEM; + + pmx->dev = &pdev->dev; + + pmx->pctl_data = &atlas7_ioc_data; + pmx->pctl_desc.name = "pinctrl-atlas7"; + pmx->pctl_desc.pins = pmx->pctl_data->pads; + pmx->pctl_desc.npins = pmx->pctl_data->pads_cnt; + pmx->pctl_desc.pctlops = &atlas7_pinctrl_ops; + pmx->pctl_desc.pmxops = &atlas7_pinmux_ops; + pmx->pctl_desc.confops = &atlas7_pinconf_ops; + pmx->pctl_desc.owner = THIS_MODULE; + + for (idx = 0; idx < banks; idx++) { + pmx->regs[idx] = of_iomap(np, idx); + if (!pmx->regs[idx]) { + dev_err(&pdev->dev, + "can't map ioc bank#%d registers\n", idx); + ret = -ENOMEM; + goto unmap_io; + } + } + + /* Now register the pin controller and all pins it handles */ + pmx->pctl = pinctrl_register(&pmx->pctl_desc, &pdev->dev, pmx); + if (!pmx->pctl) { + dev_err(&pdev->dev, "could not register atlas7 pinmux driver\n"); + ret = -EINVAL; + goto unmap_io; + } + + platform_set_drvdata(pdev, pmx); + + dev_info(&pdev->dev, "initialized atlas7 pinmux driver\n"); + + return 0; + +unmap_io: + for (idx = 0; idx < banks; idx++) { + if (!pmx->regs[idx]) + break; + iounmap(pmx->regs[idx]); + } + + return ret; +} + +static const struct of_device_id atlas7_pinmux_ids[] = { + { .compatible = "sirf,atlas7-ioc",}, +}; + +static struct platform_driver atlas7_pinmux_driver = { + .driver = { + .name = "atlas7-ioc", + .owner = THIS_MODULE, + .of_match_table = atlas7_pinmux_ids, + }, + .probe = atlas7_pinmux_probe, +}; + +static int __init atlas7_pinmux_init(void) +{ + return platform_driver_register(&atlas7_pinmux_driver); +} +arch_initcall(atlas7_pinmux_init); + + +/** + * The Following is GPIO Code + */ +static inline struct +atlas7_gpio_bank *atlas7_gpio_to_bank(struct atlas7_gpio_chip *a7gc, u32 gpio) +{ + return &a7gc->banks[GPIO_TO_BANK(gpio)]; +} + +static int __atlas7_gpio_to_pin(struct atlas7_gpio_chip *a7gc, u32 gpio) +{ + struct atlas7_gpio_bank *bank; + u32 ofs; + + bank = atlas7_gpio_to_bank(a7gc, gpio); + ofs = gpio - bank->gpio_offset; + if (ofs >= bank->ngpio) + return -ENODEV; + + return bank->gpio_pins[ofs]; +} + +static void atlas7_gpio_irq_ack(struct irq_data *d) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct atlas7_gpio_chip *a7gc = to_atlas7_gpio(gc); + struct atlas7_gpio_bank *bank; + void __iomem *ctrl_reg; + u32 val, pin_in_bank; + unsigned long flags; + + bank = atlas7_gpio_to_bank(a7gc, d->hwirq); + pin_in_bank = d->hwirq - bank->gpio_offset; + ctrl_reg = ATLAS7_GPIO_CTRL(bank, pin_in_bank); + + spin_lock_irqsave(&a7gc->lock, flags); + + val = readl(ctrl_reg); + /* clear interrupt status */ + writel(val, ctrl_reg); + + spin_unlock_irqrestore(&a7gc->lock, flags); +} + +static void __atlas7_gpio_irq_mask(struct atlas7_gpio_chip *a7gc, int idx) +{ + struct atlas7_gpio_bank *bank; + void __iomem *ctrl_reg; + u32 val, pin_in_bank; + + bank = atlas7_gpio_to_bank(a7gc, idx); + pin_in_bank = idx - bank->gpio_offset; + ctrl_reg = ATLAS7_GPIO_CTRL(bank, pin_in_bank); + + val = readl(ctrl_reg); + val &= ~(ATLAS7_GPIO_CTL_INTR_EN_MASK | + ATLAS7_GPIO_CTL_INTR_STATUS_MASK); + writel(val, ctrl_reg); +} + +static void atlas7_gpio_irq_mask(struct irq_data *d) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct atlas7_gpio_chip *a7gc = to_atlas7_gpio(gc); + unsigned long flags; + + spin_lock_irqsave(&a7gc->lock, flags); + + __atlas7_gpio_irq_mask(a7gc, d->hwirq); + + spin_unlock_irqrestore(&a7gc->lock, flags); +} + +static void atlas7_gpio_irq_unmask(struct irq_data *d) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct atlas7_gpio_chip *a7gc = to_atlas7_gpio(gc); + struct atlas7_gpio_bank *bank; + void __iomem *ctrl_reg; + u32 val, pin_in_bank; + unsigned long flags; + + bank = atlas7_gpio_to_bank(a7gc, d->hwirq); + pin_in_bank = d->hwirq - bank->gpio_offset; + ctrl_reg = ATLAS7_GPIO_CTRL(bank, pin_in_bank); + + spin_lock_irqsave(&a7gc->lock, flags); + + val = readl(ctrl_reg); + val &= ~ATLAS7_GPIO_CTL_INTR_STATUS_MASK; + val |= ATLAS7_GPIO_CTL_INTR_EN_MASK; + writel(val, ctrl_reg); + + spin_unlock_irqrestore(&a7gc->lock, flags); +} + +static int atlas7_gpio_irq_type(struct irq_data *d, + unsigned int type) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct atlas7_gpio_chip *a7gc = to_atlas7_gpio(gc); + struct atlas7_gpio_bank *bank; + void __iomem *ctrl_reg; + u32 val, pin_in_bank; + unsigned long flags; + + bank = atlas7_gpio_to_bank(a7gc, d->hwirq); + pin_in_bank = d->hwirq - bank->gpio_offset; + ctrl_reg = ATLAS7_GPIO_CTRL(bank, pin_in_bank); + + spin_lock_irqsave(&a7gc->lock, flags); + + val = readl(ctrl_reg); + val &= ~(ATLAS7_GPIO_CTL_INTR_STATUS_MASK | + ATLAS7_GPIO_CTL_INTR_EN_MASK); + + switch (type) { + case IRQ_TYPE_NONE: + break; + + case IRQ_TYPE_EDGE_RISING: + val |= ATLAS7_GPIO_CTL_INTR_HIGH_MASK | + ATLAS7_GPIO_CTL_INTR_TYPE_MASK; + val &= ~ATLAS7_GPIO_CTL_INTR_LOW_MASK; + break; + + case IRQ_TYPE_EDGE_FALLING: + val &= ~ATLAS7_GPIO_CTL_INTR_HIGH_MASK; + val |= ATLAS7_GPIO_CTL_INTR_LOW_MASK | + ATLAS7_GPIO_CTL_INTR_TYPE_MASK; + break; + + case IRQ_TYPE_EDGE_BOTH: + val |= ATLAS7_GPIO_CTL_INTR_HIGH_MASK | + ATLAS7_GPIO_CTL_INTR_LOW_MASK | + ATLAS7_GPIO_CTL_INTR_TYPE_MASK; + break; + + case IRQ_TYPE_LEVEL_LOW: + val &= ~(ATLAS7_GPIO_CTL_INTR_HIGH_MASK | + ATLAS7_GPIO_CTL_INTR_TYPE_MASK); + val |= ATLAS7_GPIO_CTL_INTR_LOW_MASK; + break; + + case IRQ_TYPE_LEVEL_HIGH: + val |= ATLAS7_GPIO_CTL_INTR_HIGH_MASK; + val &= ~(ATLAS7_GPIO_CTL_INTR_LOW_MASK | + ATLAS7_GPIO_CTL_INTR_TYPE_MASK); + break; + } + + writel(val, ctrl_reg); + + spin_unlock_irqrestore(&a7gc->lock, flags); + + return 0; +} + +static struct irq_chip atlas7_gpio_irq_chip = { + .name = "atlas7-gpio-irq", + .irq_ack = atlas7_gpio_irq_ack, + .irq_mask = atlas7_gpio_irq_mask, + .irq_unmask = atlas7_gpio_irq_unmask, + .irq_set_type = atlas7_gpio_irq_type, +}; + +static void atlas7_gpio_handle_irq(unsigned int irq, struct irq_desc *desc) +{ + struct gpio_chip *gc = irq_desc_get_handler_data(desc); + struct atlas7_gpio_chip *a7gc = to_atlas7_gpio(gc); + struct atlas7_gpio_bank *bank = NULL; + u32 status, ctrl; + int pin_in_bank = 0, idx; + struct irq_chip *chip = irq_get_chip(irq); + + for (idx = 0; idx < a7gc->nbank; idx++) { + bank = &a7gc->banks[idx]; + if (bank->irq == irq) + break; + } + BUG_ON(idx == a7gc->nbank); + + chained_irq_enter(chip, desc); + + status = readl(ATLAS7_GPIO_INT_STATUS(bank)); + if (!status) { + pr_warn("%s: gpio [%s] status %#x no interrupt is flaged\n", + __func__, gc->label, status); + handle_bad_irq(irq, desc); + return; + } + + while (status) { + ctrl = readl(ATLAS7_GPIO_CTRL(bank, pin_in_bank)); + + /* + * Here we must check whether the corresponding GPIO's + * interrupt has been enabled, otherwise just skip it + */ + if ((status & 0x1) && (ctrl & ATLAS7_GPIO_CTL_INTR_EN_MASK)) { + pr_debug("%s: chip[%s] gpio:%d happens\n", + __func__, gc->label, + bank->gpio_offset + pin_in_bank); + generic_handle_irq( + irq_find_mapping(gc->irqdomain, + bank->gpio_offset + pin_in_bank)); + } + + if (++pin_in_bank >= bank->ngpio) + break; + + status = status >> 1; + } + + chained_irq_exit(chip, desc); +} + +static void __atlas7_gpio_set_input(struct atlas7_gpio_chip *a7gc, + unsigned int gpio) +{ + struct atlas7_gpio_bank *bank; + void __iomem *ctrl_reg; + u32 val, pin_in_bank; + + bank = atlas7_gpio_to_bank(a7gc, gpio); + pin_in_bank = gpio - bank->gpio_offset; + ctrl_reg = ATLAS7_GPIO_CTRL(bank, pin_in_bank); + + val = readl(ctrl_reg); + val &= ~ATLAS7_GPIO_CTL_OUT_EN_MASK; + writel(val, ctrl_reg); +} + +static int atlas7_gpio_request(struct gpio_chip *chip, + unsigned int gpio) +{ + struct atlas7_gpio_chip *a7gc = to_atlas7_gpio(chip); + int ret; + unsigned long flags; + + ret = __atlas7_gpio_to_pin(a7gc, gpio); + if (ret < 0) + return ret; + + if (pinctrl_request_gpio(chip->base + gpio)) + return -ENODEV; + + spin_lock_irqsave(&a7gc->lock, flags); + + /* + * default status: + * set direction as input and mask irq + */ + __atlas7_gpio_set_input(a7gc, gpio); + __atlas7_gpio_irq_mask(a7gc, gpio); + + spin_unlock_irqrestore(&a7gc->lock, flags); + + return 0; +} + +static void atlas7_gpio_free(struct gpio_chip *chip, + unsigned int gpio) +{ + struct atlas7_gpio_chip *a7gc = to_atlas7_gpio(chip); + unsigned long flags; + + spin_lock_irqsave(&a7gc->lock, flags); + + __atlas7_gpio_irq_mask(a7gc, gpio); + __atlas7_gpio_set_input(a7gc, gpio); + + spin_unlock_irqrestore(&a7gc->lock, flags); + + pinctrl_free_gpio(chip->base + gpio); +} + +static int atlas7_gpio_direction_input(struct gpio_chip *chip, + unsigned int gpio) +{ + struct atlas7_gpio_chip *a7gc = to_atlas7_gpio(chip); + unsigned long flags; + + spin_lock_irqsave(&a7gc->lock, flags); + + __atlas7_gpio_set_input(a7gc, gpio); + + spin_unlock_irqrestore(&a7gc->lock, flags); + + return 0; +} + +static void __atlas7_gpio_set_output(struct atlas7_gpio_chip *a7gc, + unsigned int gpio, int value) +{ + struct atlas7_gpio_bank *bank; + void __iomem *ctrl_reg; + u32 out_ctrl, pin_in_bank; + + bank = atlas7_gpio_to_bank(a7gc, gpio); + pin_in_bank = gpio - bank->gpio_offset; + ctrl_reg = ATLAS7_GPIO_CTRL(bank, pin_in_bank); + + out_ctrl = readl(ctrl_reg); + if (value) + out_ctrl |= ATLAS7_GPIO_CTL_DATAOUT_MASK; + else + out_ctrl &= ~ATLAS7_GPIO_CTL_DATAOUT_MASK; + + out_ctrl &= ~ATLAS7_GPIO_CTL_INTR_EN_MASK; + out_ctrl |= ATLAS7_GPIO_CTL_OUT_EN_MASK; + writel(out_ctrl, ctrl_reg); +} + +static int atlas7_gpio_direction_output(struct gpio_chip *chip, + unsigned int gpio, int value) +{ + struct atlas7_gpio_chip *a7gc = to_atlas7_gpio(chip); + unsigned long flags; + + spin_lock_irqsave(&a7gc->lock, flags); + + __atlas7_gpio_set_output(a7gc, gpio, value); + + spin_unlock_irqrestore(&a7gc->lock, flags); + + return 0; +} + +static int atlas7_gpio_get_value(struct gpio_chip *chip, + unsigned int gpio) +{ + struct atlas7_gpio_chip *a7gc = to_atlas7_gpio(chip); + struct atlas7_gpio_bank *bank; + u32 val, pin_in_bank; + unsigned long flags; + + bank = atlas7_gpio_to_bank(a7gc, gpio); + pin_in_bank = gpio - bank->gpio_offset; + + spin_lock_irqsave(&a7gc->lock, flags); + + val = readl(ATLAS7_GPIO_CTRL(bank, pin_in_bank)); + + spin_unlock_irqrestore(&a7gc->lock, flags); + + return !!(val & ATLAS7_GPIO_CTL_DATAIN_MASK); +} + +static void atlas7_gpio_set_value(struct gpio_chip *chip, + unsigned int gpio, int value) +{ + struct atlas7_gpio_chip *a7gc = to_atlas7_gpio(chip); + struct atlas7_gpio_bank *bank; + void __iomem *ctrl_reg; + u32 ctrl, pin_in_bank; + unsigned long flags; + + bank = atlas7_gpio_to_bank(a7gc, gpio); + pin_in_bank = gpio - bank->gpio_offset; + ctrl_reg = ATLAS7_GPIO_CTRL(bank, pin_in_bank); + + spin_lock_irqsave(&a7gc->lock, flags); + + ctrl = readl(ctrl_reg); + if (value) + ctrl |= ATLAS7_GPIO_CTL_DATAOUT_MASK; + else + ctrl &= ~ATLAS7_GPIO_CTL_DATAOUT_MASK; + writel(ctrl, ctrl_reg); + + spin_unlock_irqrestore(&a7gc->lock, flags); +} + +static const struct of_device_id atlas7_gpio_ids[] = { + { .compatible = "sirf,atlas7-gpio", }, +}; + +static int atlas7_gpio_probe(struct platform_device *pdev) +{ + struct device_node *np = pdev->dev.of_node; + struct atlas7_gpio_chip *a7gc; + struct gpio_chip *chip; + u32 nbank; + int ret, idx; + + ret = of_property_read_u32(np, "gpio-banks", &nbank); + if (ret) { + dev_err(&pdev->dev, + "Could not find GPIO bank info,ret=%d!\n", + ret); + return ret; + } + + /* retrieve gpio descriptor data */ + a7gc = devm_kzalloc(&pdev->dev, sizeof(*a7gc) + + sizeof(struct atlas7_gpio_bank) * nbank, GFP_KERNEL); + if (!a7gc) + return -ENOMEM; + + /* Get Gpio clk */ + a7gc->clk = of_clk_get(np, 0); + if (!IS_ERR(a7gc->clk)) { + ret = clk_prepare_enable(a7gc->clk); + if (ret) { + dev_err(&pdev->dev, + "Could not enable clock!\n"); + return ret; + } + } + + /* Get Gpio Registers */ + a7gc->reg = of_iomap(np, 0); + if (!a7gc->reg) { + dev_err(&pdev->dev, "Could not map GPIO Registers!\n"); + return -ENOMEM; + } + + a7gc->nbank = nbank; + spin_lock_init(&a7gc->lock); + + /* Setup GPIO Chip */ + chip = &a7gc->chip; + chip->request = atlas7_gpio_request; + chip->free = atlas7_gpio_free; + chip->direction_input = atlas7_gpio_direction_input; + chip->get = atlas7_gpio_get_value; + chip->direction_output = atlas7_gpio_direction_output; + chip->set = atlas7_gpio_set_value; + chip->base = -1; + /* Each chip can support 32 pins at one bank */ + chip->ngpio = NGPIO_OF_BANK * nbank; + chip->label = kstrdup(np->name, GFP_KERNEL); + chip->of_node = np; + chip->of_gpio_n_cells = 2; + chip->dev = &pdev->dev; + + /* Add gpio chip to system */ + ret = gpiochip_add(chip); + if (ret) { + dev_err(&pdev->dev, + "%s: error in probe function with status %d\n", + np->name, ret); + goto failed; + } + + /* Add gpio chip to irq subsystem */ + ret = gpiochip_irqchip_add(chip, &atlas7_gpio_irq_chip, + 0, handle_level_irq, IRQ_TYPE_NONE); + if (ret) { + dev_err(&pdev->dev, + "could not connect irqchip to gpiochip\n"); + goto failed; + } + + for (idx = 0; idx < nbank; idx++) { + struct gpio_pin_range *pin_range; + struct atlas7_gpio_bank *bank; + + bank = &a7gc->banks[idx]; + /* Set ctrl registers' base of this bank */ + bank->base = ATLAS7_GPIO_BASE(a7gc, idx); + + /* Get interrupt number from DTS */ + ret = of_irq_get(np, idx); + if (ret == -EPROBE_DEFER) { + dev_err(&pdev->dev, + "Unable to find IRQ number. ret=%d\n", ret); + goto failed; + } + bank->irq = ret; + + gpiochip_set_chained_irqchip(chip, &atlas7_gpio_irq_chip, + bank->irq, atlas7_gpio_handle_irq); + + /* Records gpio_pin_range to a7gc */ + list_for_each_entry(pin_range, &chip->pin_ranges, node) { + struct pinctrl_gpio_range *range; + + range = &pin_range->range; + if (range->id == NGPIO_OF_BANK * idx) { + bank->gpio_offset = range->id; + bank->ngpio = range->npins; + bank->gpio_pins = range->pins; + bank->pctldev = pin_range->pctldev; + break; + } + } + + BUG_ON(!bank->pctldev); + } + + dev_info(&pdev->dev, "add to system.\n"); + return 0; +failed: + return ret; +} + +static struct platform_driver atlas7_gpio_driver = { + .driver = { + .name = "atlas7-gpio", + .owner = THIS_MODULE, + .of_match_table = atlas7_gpio_ids, + }, + .probe = atlas7_gpio_probe, +}; + +static int __init atlas7_gpio_init(void) +{ + return platform_driver_register(&atlas7_gpio_driver); +} +subsys_initcall(atlas7_gpio_init); + +MODULE_DESCRIPTION("SIRFSOC Atlas7 pin control driver"); +MODULE_LICENSE("GPL"); -- cgit v0.10.2 From f9784298e2b4a95be3bd7200075a2fdc61fd9f3b Mon Sep 17 00:00:00 2001 From: Yoshihiro Shimoda Date: Mon, 18 May 2015 10:41:05 +0900 Subject: pinctrl: sh-pfc: r8a7791: Add PWM pin groups and functions Signed-off-by: Yoshihiro Shimoda Acked-by: Geert Uytterhoeven Acked-by: Laurent Pinchart Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c index cbf8ec3..6e9ed6f 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c @@ -2928,6 +2928,79 @@ static const unsigned int msiof2_tx_e_pins[] = { static const unsigned int msiof2_tx_e_mux[] = { MSIOF2_TXD_E_MARK, }; +/* - PWM -------------------------------------------------------------------- */ +static const unsigned int pwm0_pins[] = { + RCAR_GP_PIN(6, 14), +}; +static const unsigned int pwm0_mux[] = { + PWM0_MARK, +}; +static const unsigned int pwm0_b_pins[] = { + RCAR_GP_PIN(5, 30), +}; +static const unsigned int pwm0_b_mux[] = { + PWM0_B_MARK, +}; +static const unsigned int pwm1_pins[] = { + RCAR_GP_PIN(1, 17), +}; +static const unsigned int pwm1_mux[] = { + PWM1_MARK, +}; +static const unsigned int pwm1_b_pins[] = { + RCAR_GP_PIN(6, 15), +}; +static const unsigned int pwm1_b_mux[] = { + PWM1_B_MARK, +}; +static const unsigned int pwm2_pins[] = { + RCAR_GP_PIN(1, 18), +}; +static const unsigned int pwm2_mux[] = { + PWM2_MARK, +}; +static const unsigned int pwm2_b_pins[] = { + RCAR_GP_PIN(0, 16), +}; +static const unsigned int pwm2_b_mux[] = { + PWM2_B_MARK, +}; +static const unsigned int pwm3_pins[] = { + RCAR_GP_PIN(1, 24), +}; +static const unsigned int pwm3_mux[] = { + PWM3_MARK, +}; +static const unsigned int pwm4_pins[] = { + RCAR_GP_PIN(3, 26), +}; +static const unsigned int pwm4_mux[] = { + PWM4_MARK, +}; +static const unsigned int pwm4_b_pins[] = { + RCAR_GP_PIN(3, 31), +}; +static const unsigned int pwm4_b_mux[] = { + PWM4_B_MARK, +}; +static const unsigned int pwm5_pins[] = { + RCAR_GP_PIN(7, 21), +}; +static const unsigned int pwm5_mux[] = { + PWM5_MARK, +}; +static const unsigned int pwm5_b_pins[] = { + RCAR_GP_PIN(7, 20), +}; +static const unsigned int pwm5_b_mux[] = { + PWM5_B_MARK, +}; +static const unsigned int pwm6_pins[] = { + RCAR_GP_PIN(7, 22), +}; +static const unsigned int pwm6_mux[] = { + PWM6_MARK, +}; /* - QSPI ------------------------------------------------------------------- */ static const unsigned int qspi_ctrl_pins[] = { /* SPCLK, SSL */ @@ -4348,6 +4421,18 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(msiof2_sync_e), SH_PFC_PIN_GROUP(msiof2_rx_e), SH_PFC_PIN_GROUP(msiof2_tx_e), + SH_PFC_PIN_GROUP(pwm0), + SH_PFC_PIN_GROUP(pwm0_b), + SH_PFC_PIN_GROUP(pwm1), + SH_PFC_PIN_GROUP(pwm1_b), + SH_PFC_PIN_GROUP(pwm2), + SH_PFC_PIN_GROUP(pwm2_b), + SH_PFC_PIN_GROUP(pwm3), + SH_PFC_PIN_GROUP(pwm4), + SH_PFC_PIN_GROUP(pwm4_b), + SH_PFC_PIN_GROUP(pwm5), + SH_PFC_PIN_GROUP(pwm5_b), + SH_PFC_PIN_GROUP(pwm6), SH_PFC_PIN_GROUP(qspi_ctrl), SH_PFC_PIN_GROUP(qspi_data2), SH_PFC_PIN_GROUP(qspi_data4), @@ -4745,6 +4830,39 @@ static const char * const msiof2_groups[] = { "msiof2_tx_e", }; +static const char * const pwm0_groups[] = { + "pwm0", + "pwm0_b", +}; + +static const char * const pwm1_groups[] = { + "pwm1", + "pwm1_b", +}; + +static const char * const pwm2_groups[] = { + "pwm2", + "pwm2_b", +}; + +static const char * const pwm3_groups[] = { + "pwm3", +}; + +static const char * const pwm4_groups[] = { + "pwm4", + "pwm4_b", +}; + +static const char * const pwm5_groups[] = { + "pwm5", + "pwm5_b", +}; + +static const char * const pwm6_groups[] = { + "pwm6", +}; + static const char * const qspi_groups[] = { "qspi_ctrl", "qspi_data2", @@ -4989,6 +5107,13 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(msiof0), SH_PFC_FUNCTION(msiof1), SH_PFC_FUNCTION(msiof2), + SH_PFC_FUNCTION(pwm0), + SH_PFC_FUNCTION(pwm1), + SH_PFC_FUNCTION(pwm2), + SH_PFC_FUNCTION(pwm3), + SH_PFC_FUNCTION(pwm4), + SH_PFC_FUNCTION(pwm5), + SH_PFC_FUNCTION(pwm6), SH_PFC_FUNCTION(qspi), SH_PFC_FUNCTION(scif0), SH_PFC_FUNCTION(scif1), -- cgit v0.10.2 From a2202a4c762bedb56bcaafd3200deceac1c2e7b5 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Wed, 20 May 2015 09:11:23 +0200 Subject: pinctrl: mediatek: add OF dependency to MT6397 X86_64 allmodconfig screams like so: warning: (PINCTRL_MT6397) selects PINCTRL_MTK_COMMON which has unmet direct dependencies (PINCTRL && (ARCH_MEDIATEK || COMPILE_TEST) && OF) So add OF to dependencies to shut up this warning. Cc: Hongzhou Yang Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig index 0bc84fb..02f6f92 100644 --- a/drivers/pinctrl/mediatek/Kconfig +++ b/drivers/pinctrl/mediatek/Kconfig @@ -32,6 +32,7 @@ config PINCTRL_MT8173 # For PMIC config PINCTRL_MT6397 bool "Mediatek MT6397 pin control" if COMPILE_TEST && !MFD_MT6397 + depends on OF default MFD_MT6397 select PINCTRL_MTK_COMMON -- cgit v0.10.2 From 815088550342904acd68f43436e1b4d1d78b77c1 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Thu, 28 May 2015 10:11:19 +0200 Subject: pinctrl: improve debugfs for strict controllers If we know we are using a strict pin controller (one that cannot mix device functions+group use and GPIO) we can be a bit more specific in debugfs, just print either device-function-group or GPIO consumer for the pin. Let's do that to be helpful. Cc: Sonic Zhang Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/pinmux.c b/drivers/pinctrl/pinmux.c index c58c168..77f82b2 100644 --- a/drivers/pinctrl/pinmux.c +++ b/drivers/pinctrl/pinmux.c @@ -585,7 +585,12 @@ static int pinmux_pins_show(struct seq_file *s, void *what) return 0; seq_puts(s, "Pinmux settings per pin\n"); - seq_puts(s, "Format: pin (name): mux_owner gpio_owner hog?\n"); + if (pmxops->strict) + seq_puts(s, + "Format: pin (name): mux_owner|gpio_owner (strict) hog?\n"); + else + seq_puts(s, + "Format: pin (name): mux_owner gpio_owner hog?\n"); mutex_lock(&pctldev->mutex); @@ -604,14 +609,34 @@ static int pinmux_pins_show(struct seq_file *s, void *what) !strcmp(desc->mux_owner, pinctrl_dev_get_name(pctldev))) is_hog = true; - seq_printf(s, "pin %d (%s): %s %s%s", pin, - desc->name ? desc->name : "unnamed", - desc->mux_owner ? desc->mux_owner - : "(MUX UNCLAIMED)", - desc->gpio_owner ? desc->gpio_owner - : "(GPIO UNCLAIMED)", - is_hog ? " (HOG)" : ""); + if (pmxops->strict) { + if (desc->mux_owner) + seq_printf(s, "pin %d (%s): device %s%s", + pin, + desc->name ? desc->name : "unnamed", + desc->mux_owner, + is_hog ? " (HOG)" : ""); + else if (desc->gpio_owner) + seq_printf(s, "pin %d (%s): GPIO %s", + pin, + desc->name ? desc->name : "unnamed", + desc->gpio_owner); + else + seq_printf(s, "pin %d (%s): UNCLAIMED", + pin, + desc->name ? desc->name : "unnamed"); + } else { + /* For non-strict controllers */ + seq_printf(s, "pin %d (%s): %s %s%s", pin, + desc->name ? desc->name : "unnamed", + desc->mux_owner ? desc->mux_owner + : "(MUX UNCLAIMED)", + desc->gpio_owner ? desc->gpio_owner + : "(GPIO UNCLAIMED)", + is_hog ? " (HOG)" : ""); + } + /* If mux: print function+group claiming the pin */ if (desc->mux_setting) seq_printf(s, " function %s group %s\n", pmxops->get_function_name(pctldev, -- cgit v0.10.2 From 1133c6379c8a2af9d0825db621ce2f16c694a8fe Mon Sep 17 00:00:00 2001 From: Jon Hunter Date: Wed, 27 May 2015 14:11:53 +0100 Subject: pinctrl: tegra-xusb: Remove unused structure The structure tegra_xusb_padctl_group is defined but never used and so remove this. Signed-off-by: Jon Hunter Acked-by: Thierry Reding Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/pinctrl-tegra-xusb.c b/drivers/pinctrl/pinctrl-tegra-xusb.c index 753d747..3e8e4a9 100644 --- a/drivers/pinctrl/pinctrl-tegra-xusb.c +++ b/drivers/pinctrl/pinctrl-tegra-xusb.c @@ -59,11 +59,6 @@ struct tegra_xusb_padctl_function { unsigned int num_groups; }; -struct tegra_xusb_padctl_group { - const unsigned int *funcs; - unsigned int num_funcs; -}; - struct tegra_xusb_padctl_soc { const struct pinctrl_pin_desc *pins; unsigned int num_pins; -- cgit v0.10.2 From 8480c2e7b0484b8ec741bbb908455fce748f9798 Mon Sep 17 00:00:00 2001 From: Jon Hunter Date: Wed, 27 May 2015 14:11:54 +0100 Subject: pinctrl: tegra-xusb: Fix allocation of pins Commit e5b3b2d9ed20 ("pinctrl: allows not to define the get_group_pins operation") allows pin controllers not to register the get_group_pins() function. However, a side-effect of not registering this function is that pins are not allocated and potentially multiple devices could attempt to configure the same pins [1]. Although this problem exists in the pinctrl core, because only a few devices are impacted by this, fix this for tegra-xusb by adding the get_group_pins() function. Please note that in addition to adding the get_group_pins() functions the pins/lanes for the tegra-xusb also need to be registered when calling pinctrl_register(). This also allows the current pinmux state to be viewed by the debugfs node "pinmux-pins" for the tegra-xusb pad controller. [1] http://www.spinics.net/lists/linux-gpio/msg05810.html Signed-off-by: Jon Hunter Acked-by: Thierry Reding Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/pinctrl-tegra-xusb.c b/drivers/pinctrl/pinctrl-tegra-xusb.c index 3e8e4a9..6a6eebf 100644 --- a/drivers/pinctrl/pinctrl-tegra-xusb.c +++ b/drivers/pinctrl/pinctrl-tegra-xusb.c @@ -125,6 +125,21 @@ static const char *tegra_xusb_padctl_get_group_name(struct pinctrl_dev *pinctrl, return padctl->soc->pins[group].name; } +static int tegra_xusb_padctl_get_group_pins(struct pinctrl_dev *pinctrl, + unsigned group, + const unsigned **pins, + unsigned *num_pins) +{ + /* + * For the tegra-xusb pad controller groups are synonomous + * with lanes/pins and there is always one lane/pin per group. + */ + *pins = &pinctrl->desc->pins[group].number; + *num_pins = 1; + + return 0; +} + enum tegra_xusb_padctl_param { TEGRA_XUSB_PADCTL_IDDQ, }; @@ -248,6 +263,7 @@ static int tegra_xusb_padctl_dt_node_to_map(struct pinctrl_dev *pinctrl, static const struct pinctrl_ops tegra_xusb_padctl_pinctrl_ops = { .get_groups_count = tegra_xusb_padctl_get_groups_count, .get_group_name = tegra_xusb_padctl_get_group_name, + .get_group_pins = tegra_xusb_padctl_get_group_pins, .dt_node_to_map = tegra_xusb_padctl_dt_node_to_map, .dt_free_map = pinctrl_utils_dt_free_map, }; @@ -898,6 +914,8 @@ static int tegra_xusb_padctl_probe(struct platform_device *pdev) memset(&padctl->desc, 0, sizeof(padctl->desc)); padctl->desc.name = dev_name(padctl->dev); + padctl->desc.pins = tegra124_pins; + padctl->desc.npins = ARRAY_SIZE(tegra124_pins); padctl->desc.pctlops = &tegra_xusb_padctl_pinctrl_ops; padctl->desc.pmxops = &tegra_xusb_padctl_pinmux_ops; padctl->desc.confops = &tegra_xusb_padctl_pinconf_ops; -- cgit v0.10.2 From 4f652cea020aac42972cb7c9788b470ed45aa228 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Wed, 20 May 2015 17:42:30 +0900 Subject: pinctrl: zynq: fix DEFINE_ZYNQ_PINMUX_FUNCTION_MUX macro MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The offset to the mux register is missing. Fixes: add958cee967 "pinctrl: Add driver for Zynq" Signed-off-by: Masahiro Yamada Reviewed-by: Sören Brinkmann Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/pinctrl-zynq.c b/drivers/pinctrl/pinctrl-zynq.c index d66f64c..e65abaa 100644 --- a/drivers/pinctrl/pinctrl-zynq.c +++ b/drivers/pinctrl/pinctrl-zynq.c @@ -768,12 +768,13 @@ static const char * const gpio0_groups[] = {"gpio0_0_grp", .mux_val = mval, \ } -#define DEFINE_ZYNQ_PINMUX_FUNCTION_MUX(fname, mval, mux, mask, shift) \ +#define DEFINE_ZYNQ_PINMUX_FUNCTION_MUX(fname, mval, offset, mask, shift)\ [ZYNQ_PMUX_##fname] = { \ .name = #fname, \ .groups = fname##_groups, \ .ngroups = ARRAY_SIZE(fname##_groups), \ .mux_val = mval, \ + .mux = offset, \ .mux_mask = mask, \ .mux_shift = shift, \ } -- cgit v0.10.2 From 5cf021d52026c0e998756a3bdb475aae2e8a68a4 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Wed, 20 May 2015 17:42:31 +0900 Subject: pinctrl: zynq: fix offset address for {SD0,SD1}_WP_CD_SEL MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The address for SD0_WP_CD_SEL, SD1_WP_CD_SEL is 0xf8000830, 0xf8000834, respectively. Each offset address must be prefixed with 0x. Fixes: add958cee967 "pinctrl: Add driver for Zynq" Signed-off-by: Masahiro Yamada Reviewed-by: Sören Brinkmann Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/pinctrl-zynq.c b/drivers/pinctrl/pinctrl-zynq.c index e65abaa..bb18d3e 100644 --- a/drivers/pinctrl/pinctrl-zynq.c +++ b/drivers/pinctrl/pinctrl-zynq.c @@ -801,15 +801,15 @@ static const struct zynq_pinmux_function zynq_pmux_functions[] = { DEFINE_ZYNQ_PINMUX_FUNCTION(spi1_ss, 0x50), DEFINE_ZYNQ_PINMUX_FUNCTION(sdio0, 0x40), DEFINE_ZYNQ_PINMUX_FUNCTION(sdio0_pc, 0xc), - DEFINE_ZYNQ_PINMUX_FUNCTION_MUX(sdio0_wp, 0, 130, ZYNQ_SDIO_WP_MASK, + DEFINE_ZYNQ_PINMUX_FUNCTION_MUX(sdio0_wp, 0, 0x130, ZYNQ_SDIO_WP_MASK, ZYNQ_SDIO_WP_SHIFT), - DEFINE_ZYNQ_PINMUX_FUNCTION_MUX(sdio0_cd, 0, 130, ZYNQ_SDIO_CD_MASK, + DEFINE_ZYNQ_PINMUX_FUNCTION_MUX(sdio0_cd, 0, 0x130, ZYNQ_SDIO_CD_MASK, ZYNQ_SDIO_CD_SHIFT), DEFINE_ZYNQ_PINMUX_FUNCTION(sdio1, 0x40), DEFINE_ZYNQ_PINMUX_FUNCTION(sdio1_pc, 0xc), - DEFINE_ZYNQ_PINMUX_FUNCTION_MUX(sdio1_wp, 0, 134, ZYNQ_SDIO_WP_MASK, + DEFINE_ZYNQ_PINMUX_FUNCTION_MUX(sdio1_wp, 0, 0x134, ZYNQ_SDIO_WP_MASK, ZYNQ_SDIO_WP_SHIFT), - DEFINE_ZYNQ_PINMUX_FUNCTION_MUX(sdio1_cd, 0, 134, ZYNQ_SDIO_CD_MASK, + DEFINE_ZYNQ_PINMUX_FUNCTION_MUX(sdio1_cd, 0, 0x134, ZYNQ_SDIO_CD_MASK, ZYNQ_SDIO_CD_SHIFT), DEFINE_ZYNQ_PINMUX_FUNCTION(smc0_nor, 4), DEFINE_ZYNQ_PINMUX_FUNCTION(smc0_nor_cs1, 8), -- cgit v0.10.2 From 5fbf65d5c9c0fd2e5c6c48d69ce34b1c5415f2fd Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Fri, 22 May 2015 15:19:37 +0900 Subject: pinctrl: remove useless const qualifier This "const" claims the get_function_groups callback never changes the given num_groups pointer. It is always true in C language, so not worth mentioning. Signed-off-by: Masahiro Yamada Signed-off-by: Linus Walleij diff --git a/include/linux/pinctrl/pinmux.h b/include/linux/pinctrl/pinmux.h index d3740fa..ace60d7 100644 --- a/include/linux/pinctrl/pinmux.h +++ b/include/linux/pinctrl/pinmux.h @@ -69,7 +69,7 @@ struct pinmux_ops { int (*get_function_groups) (struct pinctrl_dev *pctldev, unsigned selector, const char * const **groups, - unsigned * const num_groups); + unsigned *num_groups); int (*set_mux) (struct pinctrl_dev *pctldev, unsigned func_selector, unsigned group_selector); int (*gpio_request_enable) (struct pinctrl_dev *pctldev, -- cgit v0.10.2 From b3da97ee581387cd42dafd76eb2ac23f2335cd92 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Fri, 22 May 2015 15:25:50 +0900 Subject: pinctrl: use "const struct ..." rather than "struct ... const" Only this member, pins, is defined as "struct ... const *", but the others in this struct, pinlops, pmxops, confops, etc. are defined as "const struct ... *". Swap the "struct pinctrl_pin_desc" and "const" for consistency. Signed-off-by: Masahiro Yamada Signed-off-by: Linus Walleij diff --git a/include/linux/pinctrl/pinctrl.h b/include/linux/pinctrl/pinctrl.h index 66e4697..9ba59fc 100644 --- a/include/linux/pinctrl/pinctrl.h +++ b/include/linux/pinctrl/pinctrl.h @@ -127,7 +127,7 @@ struct pinctrl_ops { */ struct pinctrl_desc { const char *name; - struct pinctrl_pin_desc const *pins; + const struct pinctrl_pin_desc *pins; unsigned int npins; const struct pinctrl_ops *pctlops; const struct pinmux_ops *pmxops; -- cgit v0.10.2 From 5b441eba3ab928ad1a2e9478fae6aa1397048860 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 21 May 2015 14:05:10 +0200 Subject: pinctrl: Spelling s/reseved/reserved/ Signed-off-by: Geert Uytterhoeven Reviewed-by: Simon Horman Acked-by: Laurent Pinchart Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/nomadik/pinctrl-ab8505.c b/drivers/pinctrl/nomadik/pinctrl-ab8505.c index bf0ef4a..42c6e1f 100644 --- a/drivers/pinctrl/nomadik/pinctrl-ab8505.c +++ b/drivers/pinctrl/nomadik/pinctrl-ab8505.c @@ -286,7 +286,7 @@ alternate_functions ab8505_alternate_functions[AB8505_GPIO_MAX_NUMBER + 1] = { ALTERNATE_FUNCTIONS(9, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO9, bit 0 reserved */ ALTERNATE_FUNCTIONS(10, 1, 0, UNUSED, 1, 0, 0), /* GPIO10, altA and altB controlled by bit 0 */ ALTERNATE_FUNCTIONS(11, 2, 1, UNUSED, 0, 0, 0), /* GPIO11, altA controlled by bit 2 */ - ALTERNATE_FUNCTIONS(12, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO12, bit3 reseved */ + ALTERNATE_FUNCTIONS(12, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO12, bit3 reserved */ ALTERNATE_FUNCTIONS(13, 4, 3, 4, 1, 0, 2), /* GPIO13, altA altB and altC controlled by bit 3 and 4 */ ALTERNATE_FUNCTIONS(14, 5, UNUSED, UNUSED, 0, 0, 0), /* GPIO14, altA controlled by bit 5 */ ALTERNATE_FUNCTIONS(15, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO15, bit 6 reserved */ diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c index 6e9ed6f..3ddf23e 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c @@ -6125,7 +6125,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32, 1, 2, 2, 2, 3, 2, 1, 1, 1, 1, 3, 2, 2, 2, 1, 2, 2, 2) { - /* RESEVED [1] */ + /* RESERVED [1] */ 0, 0, /* SEL_SCIF1 [2] */ FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3, @@ -6152,11 +6152,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_HSCIF1_2, FN_SEL_HSCIF1_3, FN_SEL_HSCIF1_4, 0, 0, 0, - /* RESEVED [2] */ + /* RESERVED [2] */ 0, 0, 0, 0, /* SEL_VI1 [2] */ FN_SEL_VI1_0, FN_SEL_VI1_1, FN_SEL_VI1_2, 0, - /* RESEVED [2] */ + /* RESERVED [2] */ 0, 0, 0, 0, /* SEL_TMU [1] */ FN_SEL_TMU1_0, FN_SEL_TMU1_1, @@ -6174,7 +6174,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3, FN_SEL_SCIF0_4, 0, 0, 0, - /* RESEVED [1] */ + /* RESERVED [1] */ 0, 0, /* SEL_SCIF [1] */ FN_SEL_SCIF_0, FN_SEL_SCIF_1, @@ -6184,13 +6184,13 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 0, 0, /* SEL_CAN1 [2] */ FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3, - /* RESEVED [1] */ + /* RESERVED [1] */ 0, 0, /* SEL_SCIFA2 [1] */ FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, /* SEL_SCIF4 [2] */ FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, 0, - /* RESEVED [2] */ + /* RESERVED [2] */ 0, 0, 0, 0, /* SEL_ADG [1] */ FN_SEL_ADG_0, FN_SEL_ADG_1, @@ -6200,7 +6200,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 0, 0, 0, /* SEL_SCIFA5 [2] */ FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2, 0, - /* RESEVED [1] */ + /* RESERVED [1] */ 0, 0, /* SEL_GPS [2] */ FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, FN_SEL_GPS_3, @@ -6210,7 +6210,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1, FN_SEL_SCIFA3_2, 0, /* SEL_SIM [1] */ FN_SEL_SIM_0, FN_SEL_SIM_1, - /* RESEVED [1] */ + /* RESERVED [1] */ 0, 0, /* SEL_SSI8 [1] */ FN_SEL_SSI8_0, FN_SEL_SSI8_1, } @@ -6240,7 +6240,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_SEL_MMC_0, FN_SEL_MMC_1, /* SEL_SCIF5 [1] */ FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, - /* RESEVED [2] */ + /* RESERVED [2] */ 0, 0, 0, 0, /* SEL_IIC2 [2] */ FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3, @@ -6250,11 +6250,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 0, 0, 0, /* SEL_IIC0 [2] */ FN_SEL_IIC0_0, FN_SEL_IIC0_1, FN_SEL_IIC0_2, 0, - /* RESEVED [2] */ + /* RESERVED [2] */ 0, 0, 0, 0, - /* RESEVED [2] */ + /* RESERVED [2] */ 0, 0, 0, 0, - /* RESEVED [1] */ + /* RESERVED [1] */ 0, 0, } }, { PINMUX_CFG_REG_VAR("MOD_SEL4", 0xE606009C, 32, @@ -6268,7 +6268,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2, 0, /* SEL_DIS [2] */ FN_SEL_DIS_0, FN_SEL_DIS_1, FN_SEL_DIS_2, 0, - /* RESEVED [1] */ + /* RESERVED [1] */ 0, 0, /* SEL_RAD [1] */ FN_SEL_RAD_0, FN_SEL_RAD_1, @@ -6280,15 +6280,15 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, FN_SEL_SCIF2_3, FN_SEL_SCIF2_4, 0, 0, 0, - /* RESEVED [2] */ + /* RESERVED [2] */ 0, 0, 0, 0, - /* RESEVED [2] */ + /* RESERVED [2] */ 0, 0, 0, 0, /* SEL_SOF2 [3] */ FN_SEL_SOF2_0, FN_SEL_SOF2_1, FN_SEL_SOF2_2, FN_SEL_SOF2_3, FN_SEL_SOF2_4, 0, 0, 0, - /* RESEVED [1] */ + /* RESERVED [1] */ 0, 0, /* SEL_SSI1 [1] */ FN_SEL_SSI1_0, FN_SEL_SSI1_1, @@ -6296,11 +6296,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_SEL_SSI0_0, FN_SEL_SSI0_1, /* SEL_SSP [2] */ FN_SEL_SSP_0, FN_SEL_SSP_1, FN_SEL_SSP_2, 0, - /* RESEVED [2] */ + /* RESERVED [2] */ 0, 0, 0, 0, - /* RESEVED [2] */ + /* RESERVED [2] */ 0, 0, 0, 0, - /* RESEVED [2] */ + /* RESERVED [2] */ 0, 0, 0, 0, } }, { }, -- cgit v0.10.2 From 257e961ddd66998b360447ea27db7936d8defaa0 Mon Sep 17 00:00:00 2001 From: Hongzhou Yang Date: Wed, 27 May 2015 02:43:54 -0700 Subject: pinctrl: mediatek: Fix bug of ies/smt setting for mt8173. Add ies/smt support for MSDC3. Also fix ies bug for pin 106 and 107. Signed-off-by: Hongzhou Yang Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8173.c b/drivers/pinctrl/mediatek/pinctrl-mt8173.c index cf4ed6e..d0c811d 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8173.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8173.c @@ -84,6 +84,10 @@ static const struct mtk_pin_ies_smt_set mt8173_smt_set[] = { MTK_PIN_IES_SMT_SPEC(16, 16, 0x930, 0), MTK_PIN_IES_SMT_SPEC(17, 17, 0x950, 2), MTK_PIN_IES_SMT_SPEC(18, 21, 0x940, 3), + MTK_PIN_IES_SMT_SPEC(22, 25, 0xce0, 13), + MTK_PIN_IES_SMT_SPEC(26, 26, 0xcc0, 13), + MTK_PIN_IES_SMT_SPEC(27, 27, 0xcd0, 13), + MTK_PIN_IES_SMT_SPEC(28, 28, 0xd70, 13), MTK_PIN_IES_SMT_SPEC(29, 32, 0x930, 3), MTK_PIN_IES_SMT_SPEC(33, 33, 0x930, 4), MTK_PIN_IES_SMT_SPEC(34, 36, 0x930, 5), @@ -133,6 +137,10 @@ static const struct mtk_pin_ies_smt_set mt8173_ies_set[] = { MTK_PIN_IES_SMT_SPEC(16, 16, 0x900, 0), MTK_PIN_IES_SMT_SPEC(17, 17, 0x920, 2), MTK_PIN_IES_SMT_SPEC(18, 21, 0x910, 3), + MTK_PIN_IES_SMT_SPEC(22, 25, 0xce0, 14), + MTK_PIN_IES_SMT_SPEC(26, 26, 0xcc0, 14), + MTK_PIN_IES_SMT_SPEC(27, 27, 0xcd0, 14), + MTK_PIN_IES_SMT_SPEC(28, 28, 0xd70, 14), MTK_PIN_IES_SMT_SPEC(29, 32, 0x900, 3), MTK_PIN_IES_SMT_SPEC(33, 33, 0x900, 4), MTK_PIN_IES_SMT_SPEC(34, 36, 0x900, 5), @@ -161,7 +169,7 @@ static const struct mtk_pin_ies_smt_set mt8173_ies_set[] = { MTK_PIN_IES_SMT_SPEC(100, 103, 0xca0, 14), MTK_PIN_IES_SMT_SPEC(104, 104, 0xc80, 14), MTK_PIN_IES_SMT_SPEC(105, 105, 0xc90, 14), - MTK_PIN_IES_SMT_SPEC(106, 107, 0x91, 4), + MTK_PIN_IES_SMT_SPEC(106, 107, 0x910, 4), MTK_PIN_IES_SMT_SPEC(108, 112, 0x910, 1), MTK_PIN_IES_SMT_SPEC(113, 116, 0x910, 2), MTK_PIN_IES_SMT_SPEC(117, 118, 0x910, 5), -- cgit v0.10.2 From fc63d854cb55bfe2b6c67317b5bd91aaa2d058c3 Mon Sep 17 00:00:00 2001 From: Hongzhou Yang Date: Wed, 27 May 2015 02:43:55 -0700 Subject: pinctrl: mediatek: Fix pinctrl register irq fail bug. Since mt6397 is no need to support interrupt controller, I judged "interrupt-controller" property to skip it last patch. But the if judgement should on the contrary, this is a bug. And find of_property_read_bool is better for this case. So using of_property_read_bool instead of of_find_property. Also fix bug of misuse pointer. Signed-off-by: Hongzhou Yang Reviewed-by: Axel Lin Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c index cd22729..f206a54 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c @@ -1280,7 +1280,7 @@ int mtk_pctrl_init(struct platform_device *pdev, goto pctrl_error; } - pctl->chip = &mtk_gpio_chip; + *pctl->chip = mtk_gpio_chip; pctl->chip->ngpio = pctl->devdata->npins; pctl->chip->label = dev_name(&pdev->dev); pctl->chip->dev = &pdev->dev; @@ -1300,7 +1300,7 @@ int mtk_pctrl_init(struct platform_device *pdev, goto chip_error; } - if (of_find_property(np, "interrupt-controller", NULL)) + if (!of_property_read_bool(np, "interrupt-controller")) return 0; /* Get EINT register base from dts. */ -- cgit v0.10.2 From c0b8555c15cc42b5baeeafd9b171b0b00091d811 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Thu, 28 May 2015 21:57:23 +0900 Subject: pinctrl: zynq: add static to zynq_pins This array is only referenced in this file. Signed-off-by: Masahiro Yamada Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/pinctrl-zynq.c b/drivers/pinctrl/pinctrl-zynq.c index bb18d3e..58c4731 100644 --- a/drivers/pinctrl/pinctrl-zynq.c +++ b/drivers/pinctrl/pinctrl-zynq.c @@ -125,7 +125,7 @@ enum zynq_pinmux_functions { ZYNQ_PMUX_MAX_FUNC }; -const struct pinctrl_pin_desc zynq_pins[] = { +static const struct pinctrl_pin_desc zynq_pins[] = { PINCTRL_PIN(0, "MIO0"), PINCTRL_PIN(1, "MIO1"), PINCTRL_PIN(2, "MIO2"), -- cgit v0.10.2 From 4fd24e220e738feb210d0c031eb16de13b87a2df Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Thu, 28 May 2015 21:57:53 +0900 Subject: pinctrl: zynq: add static const to zynq_pctrl_groups MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This array is only referenced in this file and never updated. Signed-off-by: Masahiro Yamada Acked-by: Sören Brinkmann Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/pinctrl-zynq.c b/drivers/pinctrl/pinctrl-zynq.c index 58c4731..40b2aff 100644 --- a/drivers/pinctrl/pinctrl-zynq.c +++ b/drivers/pinctrl/pinctrl-zynq.c @@ -393,7 +393,7 @@ static const unsigned int usb1_0_pins[] = {40, 41, 42, 43, 44, 45, 46, 47, 48, .npins = ARRAY_SIZE(nm ## _pins), \ } -struct zynq_pctrl_group zynq_pctrl_groups[] = { +static const struct zynq_pctrl_group zynq_pctrl_groups[] = { DEFINE_ZYNQ_PINCTRL_GRP(ethernet0_0), DEFINE_ZYNQ_PINCTRL_GRP(ethernet1_0), DEFINE_ZYNQ_PINCTRL_GRP(mdio0_0), -- cgit v0.10.2 From 7e9236ff3d92ec326f29a20d86add10f1ff4e9b3 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Thu, 28 May 2015 21:52:59 +0900 Subject: pinctrl: fix confusing debug message in pinctrl_register_map() There are two types for pinctrl maps: pinmux and pinconfig This debug message shows the number of maps of both types. The string "pinmux map" is not precise. Let's say "pinctrl map" instead. Signed-off-by: Masahiro Yamada [also fixed %d -> %u] Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/core.c b/drivers/pinctrl/core.c index 291099d..b01ee72 100644 --- a/drivers/pinctrl/core.c +++ b/drivers/pinctrl/core.c @@ -1115,7 +1115,7 @@ int pinctrl_register_map(struct pinctrl_map const *maps, unsigned num_maps, int i, ret; struct pinctrl_maps *maps_node; - pr_debug("add %d pinmux maps\n", num_maps); + pr_debug("add %u pinctrl maps\n", num_maps); /* First sanity check the new mapping */ for (i = 0; i < num_maps; i++) { -- cgit v0.10.2 From 3944e7b78c7b1bfed7808692cc539496b3f94eea Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 1 Jun 2015 09:53:59 -0300 Subject: pinctrl: Remove .owner field platform_driver does not need to set the owner field, as it will be populated by the driver core, so just remove it. The semantic patch that makes this change is available in scripts/coccinelle/api/platform_no_drv_owner.cocci. Signed-off-by: Fabio Estevam Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/freescale/pinctrl-imx7d.c b/drivers/pinctrl/freescale/pinctrl-imx7d.c index d8ab17e..1fa7530 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx7d.c +++ b/drivers/pinctrl/freescale/pinctrl-imx7d.c @@ -361,7 +361,6 @@ static int imx7d_pinctrl_probe(struct platform_device *pdev) static struct platform_driver imx7d_pinctrl_driver = { .driver = { .name = "imx7d-pinctrl", - .owner = THIS_MODULE, .of_match_table = of_match_ptr(imx7d_pinctrl_of_match), }, .probe = imx7d_pinctrl_probe, diff --git a/drivers/pinctrl/mediatek/pinctrl-mt6397.c b/drivers/pinctrl/mediatek/pinctrl-mt6397.c index 767bbdf..f9751ae 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt6397.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt6397.c @@ -61,7 +61,6 @@ static struct platform_driver mtk_pinctrl_driver = { .probe = mt6397_pinctrl_probe, .driver = { .name = "mediatek-mt6397-pinctrl", - .owner = THIS_MODULE, .of_match_table = mt6397_pctrl_match, }, }; diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8127.c b/drivers/pinctrl/mediatek/pinctrl-mt8127.c index 6a26cfa..b317b0b 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8127.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8127.c @@ -342,7 +342,6 @@ static struct platform_driver mtk_pinctrl_driver = { .probe = mt8127_pinctrl_probe, .driver = { .name = "mediatek-mt8127-pinctrl", - .owner = THIS_MODULE, .of_match_table = mt8127_pctrl_match, }, }; diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8135.c b/drivers/pinctrl/mediatek/pinctrl-mt8135.c index 203bd2a..404f117 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8135.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8135.c @@ -357,7 +357,6 @@ static struct platform_driver mtk_pinctrl_driver = { .probe = mt8135_pinctrl_probe, .driver = { .name = "mediatek-mt8135-pinctrl", - .owner = THIS_MODULE, .of_match_table = mt8135_pctrl_match, }, }; diff --git a/drivers/pinctrl/pinctrl-amd.c b/drivers/pinctrl/pinctrl-amd.c index 7de3b64..e7479125 100644 --- a/drivers/pinctrl/pinctrl-amd.c +++ b/drivers/pinctrl/pinctrl-amd.c @@ -855,7 +855,6 @@ MODULE_DEVICE_TABLE(acpi, amd_gpio_acpi_match); static struct platform_driver amd_gpio_driver = { .driver = { .name = "amd_gpio", - .owner = THIS_MODULE, .acpi_match_table = ACPI_PTR(amd_gpio_acpi_match), }, .probe = amd_gpio_probe, diff --git a/drivers/pinctrl/sirf/pinctrl-atlas7.c b/drivers/pinctrl/sirf/pinctrl-atlas7.c index 046251a..c2ced3f 100644 --- a/drivers/pinctrl/sirf/pinctrl-atlas7.c +++ b/drivers/pinctrl/sirf/pinctrl-atlas7.c @@ -4066,7 +4066,6 @@ static int atlas7_pinmux_probe(struct platform_device *pdev) pmx->pctl_desc.pctlops = &atlas7_pinctrl_ops; pmx->pctl_desc.pmxops = &atlas7_pinmux_ops; pmx->pctl_desc.confops = &atlas7_pinconf_ops; - pmx->pctl_desc.owner = THIS_MODULE; for (idx = 0; idx < banks; idx++) { pmx->regs[idx] = of_iomap(np, idx); @@ -4109,7 +4108,6 @@ static const struct of_device_id atlas7_pinmux_ids[] = { static struct platform_driver atlas7_pinmux_driver = { .driver = { .name = "atlas7-ioc", - .owner = THIS_MODULE, .of_match_table = atlas7_pinmux_ids, }, .probe = atlas7_pinmux_probe, diff --git a/drivers/pinctrl/sunxi/pinctrl-sun6i-a31s.c b/drivers/pinctrl/sunxi/pinctrl-sun6i-a31s.c index d3725dc..e570d5c 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun6i-a31s.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun6i-a31s.c @@ -804,7 +804,6 @@ static struct platform_driver sun6i_a31s_pinctrl_driver = { .probe = sun6i_a31s_pinctrl_probe, .driver = { .name = "sun6i-a31s-pinctrl", - .owner = THIS_MODULE, .of_match_table = sun6i_a31s_pinctrl_match, }, }; -- cgit v0.10.2 From 44a074ffe038a4953d8ff4091599ce997867820c Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 1 Jun 2015 09:57:04 -0300 Subject: pinctrl: samsung: Fix the pointer in PTR_ERR() PTR_ERR should access the value just tested by IS_ERR The semantic patch that makes this change is available in scripts/coccinelle/tests/odd_ptr_err.cocci. Signed-off-by: Fabio Estevam Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.c b/drivers/pinctrl/samsung/pinctrl-samsung.c index ed165ba..0fd20c5 100644 --- a/drivers/pinctrl/samsung/pinctrl-samsung.c +++ b/drivers/pinctrl/samsung/pinctrl-samsung.c @@ -806,7 +806,7 @@ static int samsung_pinctrl_parse_dt(struct platform_device *pdev, functions = samsung_pinctrl_create_functions(dev, drvdata, &func_cnt); if (IS_ERR(functions)) { dev_err(dev, "failed to parse pin functions\n"); - return PTR_ERR(groups); + return PTR_ERR(functions); } drvdata->pin_groups = groups; -- cgit v0.10.2 From 7164873e7c69d6bab74726debc3b495a86332b1f Mon Sep 17 00:00:00 2001 From: Vishnu Patekar Date: Tue, 2 Jun 2015 11:08:40 +0200 Subject: pinctrl: sunxi: Add allwinner A33 PIO controller support A33 PIO has 7 ports which starts from PB and has two interrupt ports. Signed-off-by: Vishnu Patekar Acked-by: Hans de Goede Acked-by: Maxime Ripard Signed-off-by: Hans de Goede Signed-off-by: Linus Walleij diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt index fdd8046..9462ab7 100644 --- a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt @@ -16,6 +16,8 @@ Required properties: "allwinner,sun7i-a20-pinctrl" "allwinner,sun8i-a23-pinctrl" "allwinner,sun8i-a23-r-pinctrl" + "allwinner,sun8i-a33-pinctrl" + - reg: Should contain the register physical address and length for the pin controller. diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig index 2eb893e..ae27872 100644 --- a/drivers/pinctrl/sunxi/Kconfig +++ b/drivers/pinctrl/sunxi/Kconfig @@ -38,6 +38,10 @@ config PINCTRL_SUN8I_A23 def_bool MACH_SUN8I select PINCTRL_SUNXI_COMMON +config PINCTRL_SUN8I_A33 + def_bool MACH_SUN8I + select PINCTRL_SUNXI_COMMON + config PINCTRL_SUN8I_A23_R def_bool MACH_SUN8I depends on RESET_CONTROLLER diff --git a/drivers/pinctrl/sunxi/Makefile b/drivers/pinctrl/sunxi/Makefile index b796d57..227a121 100644 --- a/drivers/pinctrl/sunxi/Makefile +++ b/drivers/pinctrl/sunxi/Makefile @@ -11,4 +11,5 @@ obj-$(CONFIG_PINCTRL_SUN6I_A31_R) += pinctrl-sun6i-a31-r.o obj-$(CONFIG_PINCTRL_SUN7I_A20) += pinctrl-sun7i-a20.o obj-$(CONFIG_PINCTRL_SUN8I_A23) += pinctrl-sun8i-a23.o obj-$(CONFIG_PINCTRL_SUN8I_A23_R) += pinctrl-sun8i-a23-r.o +obj-$(CONFIG_PINCTRL_SUN8I_A33) += pinctrl-sun8i-a33.o obj-$(CONFIG_PINCTRL_SUN9I_A80) += pinctrl-sun9i-a80.o diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c b/drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c new file mode 100644 index 0000000..00265f0 --- /dev/null +++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c @@ -0,0 +1,513 @@ +/* + * Allwinner a33 SoCs pinctrl driver. + * + * Copyright (C) 2015 Vishnu Patekar + * + * Based on pinctrl-sun8i-a23.c, which is: + * Copyright (C) 2014 Chen-Yu Tsai + * Copyright (C) 2014 Maxime Ripard + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include +#include +#include +#include +#include + +#include "pinctrl-sunxi.h" + +static const struct sunxi_desc_pin sun8i_a33_pins[] = { + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart2"), /* TX */ + SUNXI_FUNCTION(0x3, "uart0"), /* TX */ + SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 0)), /* PB_EINT0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart2"), /* RX */ + SUNXI_FUNCTION(0x3, "uart0"), /* RX */ + SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 1)), /* PB_EINT1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart2"), /* RTS */ + SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 2)), /* PB_EINT2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart2"), /* CTS */ + SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 3)), /* PB_EINT3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s0"), /* SYNC */ + SUNXI_FUNCTION(0x3, "aif2"), /* SYNC */ + SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 4)), /* PB_EINT4 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s0"), /* BCLK */ + SUNXI_FUNCTION(0x3, "aif2"), /* BCLK */ + SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 5)), /* PB_EINT5 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s0"), /* DOUT */ + SUNXI_FUNCTION(0x3, "aif2"), /* DOUT */ + SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 6)), /* PB_EINT6 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s0"), /* DIN */ + SUNXI_FUNCTION(0x3, "aif2"), /* DIN */ + SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 7)), /* PB_EINT7 */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* WE */ + SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* ALE */ + SUNXI_FUNCTION(0x3, "spi0")), /* MISO */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* CLE */ + SUNXI_FUNCTION(0x3, "spi0")), /* CLK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* CE1 */ + SUNXI_FUNCTION(0x3, "spi0")), /* CS */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0")), /* CE0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* RE */ + SUNXI_FUNCTION(0x3, "mmc2")), /* CLK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* RB0 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* CMD */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0")), /* RB1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* DQ0 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* DQ1 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* DQ2 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* DQ3 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* DQ4 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D4 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* DQ5 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D5 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand"), /* DQ6 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D6 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand"), /* DQ7 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D7 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand"), /* DQS */ + SUNXI_FUNCTION(0x3, "mmc2")), /* RST */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */ + SUNXI_FUNCTION(0x3, "mmc1")), /* CLK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */ + SUNXI_FUNCTION(0x3, "mmc1")), /* CMD */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */ + SUNXI_FUNCTION(0x3, "mmc1")), /* D0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */ + SUNXI_FUNCTION(0x3, "mmc1")), /* D1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */ + SUNXI_FUNCTION(0x3, "mmc1")), /* D2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */ + SUNXI_FUNCTION(0x3, "mmc1")), /* D3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D10 */ + SUNXI_FUNCTION(0x3, "uart1")), /* TX */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D11 */ + SUNXI_FUNCTION(0x3, "uart1")), /* RX */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */ + SUNXI_FUNCTION(0x3, "uart1")), /* RTS */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */ + SUNXI_FUNCTION(0x3, "uart1")), /* CTS */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0")), /* D14 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0")), /* D15 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */ + SUNXI_FUNCTION(0x3, "lvds0")), /* VP0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */ + SUNXI_FUNCTION(0x3, "lvds0")), /* VN0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D20 */ + SUNXI_FUNCTION(0x3, "lvds0")), /* VP1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D21 */ + SUNXI_FUNCTION(0x3, "lvds0")), /* VN1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 22), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D22 */ + SUNXI_FUNCTION(0x3, "lvds0")), /* VP2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 23), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D23 */ + SUNXI_FUNCTION(0x3, "lvds0")), /* VN2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 24), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* CLK */ + SUNXI_FUNCTION(0x3, "lvds0")), /* VPC */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 25), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* DE */ + SUNXI_FUNCTION(0x3, "lvds0")), /* VNC */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 26), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* HSYNC */ + SUNXI_FUNCTION(0x3, "lvds0")), /* VP3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 27), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* VSYNC */ + SUNXI_FUNCTION(0x3, "lvds0")), /* VN3 */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi")), /* PCLK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi")), /* MCLK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi")), /* HSYNC */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi")), /* VSYNC */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi")), /* D0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi")), /* D1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi")), /* D2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi")), /* D3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi")), /* D4 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi")), /* D5 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi")), /* D6 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi")), /* D7 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 12), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* SCK */ + SUNXI_FUNCTION(0x3, "i2c2")), /* SCK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 13), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* SDA */ + SUNXI_FUNCTION(0x3, "i2c2")), /* SDA */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 14), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 15), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 16), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 17), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out")), + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */ + SUNXI_FUNCTION(0x3, "jtag")), /* MS1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */ + SUNXI_FUNCTION(0x3, "jtag")), /* DI1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */ + SUNXI_FUNCTION(0x3, "uart0")), /* TX */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */ + SUNXI_FUNCTION(0x3, "jtag")), /* DO1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */ + SUNXI_FUNCTION(0x3, "uart0")), /* RX */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */ + SUNXI_FUNCTION(0x3, "jtag")), /* CK1 */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */ + SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 0)), /* PG_EINT0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */ + SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 1)), /* PG_EINT1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc1"), /* D0 */ + SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 2)), /* PG_EINT2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc1"), /* D1 */ + SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 3)), /* PG_EINT3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc1"), /* D2 */ + SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 4)), /* PG_EINT4 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc1"), /* D3 */ + SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 5)), /* PG_EINT5 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart1"), /* TX */ + SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 6)), /* PG_EINT6 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart1"), /* RX */ + SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 7)), /* PG_EINT7 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart2"), /* RTS */ + SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 8)), /* PG_EINT8 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart2"), /* CTS */ + SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 9)), /* PG_EINT9 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s1"), /* SYNC */ + SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 10)), /* PG_EINT10 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s1"), /* CLK */ + SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 11)), /* PG_EINT11 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s1"), /* DOUT */ + SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 12)), /* PG_EINT12 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 13), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s1"), /* DIN */ + SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 13)), /* PG_EINT13 */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "pwm0")), + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "pwm1")), + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c0")), /* SCK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c0")), /* SDA */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c1")), /* SCK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c1")), /* SDA */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi0"), /* CS */ + SUNXI_FUNCTION(0x3, "uart3")), /* TX */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi0"), /* CLK */ + SUNXI_FUNCTION(0x3, "uart3")), /* RX */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 8), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi0"), /* DOUT */ + SUNXI_FUNCTION(0x3, "uart3")), /* RTS */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 9), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi0"), /* DIN */ + SUNXI_FUNCTION(0x3, "uart3")), /* CTS */ +}; + +static const struct sunxi_pinctrl_desc sun8i_a33_pinctrl_data = { + .pins = sun8i_a33_pins, + .npins = ARRAY_SIZE(sun8i_a33_pins), + .irq_banks = 2, +}; + +static int sun8i_a33_pinctrl_probe(struct platform_device *pdev) +{ + return sunxi_pinctrl_init(pdev, + &sun8i_a33_pinctrl_data); +} + +static const struct of_device_id sun8i_a33_pinctrl_match[] = { + { .compatible = "allwinner,sun8i-a33-pinctrl", }, + {} +}; +MODULE_DEVICE_TABLE(of, sun8i_a33_pinctrl_match); + +static struct platform_driver sun8i_a33_pinctrl_driver = { + .probe = sun8i_a33_pinctrl_probe, + .driver = { + .name = "sun8i-a33-pinctrl", + .of_match_table = sun8i_a33_pinctrl_match, + }, +}; +module_platform_driver(sun8i_a33_pinctrl_driver); + +MODULE_AUTHOR("Vishnu Patekar "); +MODULE_DESCRIPTION("Allwinner a33 pinctrl driver"); +MODULE_LICENSE("GPL"); -- cgit v0.10.2 From bcb5f5b4f4176d5d413f8491c5f8d4b02b36018b Mon Sep 17 00:00:00 2001 From: Antoine Tenart Date: Tue, 2 Jun 2015 11:37:47 +0200 Subject: pinctrl: berlin: fix spi1 SS0n function name Rename function ss0 to spi1 to be consistent with the other Berlin function names. Signed-off-by: Antoine Tenart Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/berlin/berlin-bg2cd.c b/drivers/pinctrl/berlin/berlin-bg2cd.c index 19ac5a2..3fc05fb 100644 --- a/drivers/pinctrl/berlin/berlin-bg2cd.c +++ b/drivers/pinctrl/berlin/berlin-bg2cd.c @@ -68,7 +68,7 @@ static const struct berlin_desc_group berlin2cd_soc_pinctrl_groups[] = { BERLIN_PINCTRL_FUNCTION(0x1, "twsi1"), BERLIN_PINCTRL_FUNCTION(0x2, "gpio")), BERLIN_PINCTRL_GROUP("G8", 0x00, 0x3, 0x10, - BERLIN_PINCTRL_FUNCTION(0x0, "ss0"), + BERLIN_PINCTRL_FUNCTION(0x0, "spi1"), BERLIN_PINCTRL_FUNCTION(0x1, "gpio")), BERLIN_PINCTRL_GROUP("G9", 0x00, 0x3, 0x13, BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), -- cgit v0.10.2 From 2e89f4c3d900a2c17ca7a223c58ca3e9bbf1ef7f Mon Sep 17 00:00:00 2001 From: Antoine Tenart Date: Tue, 2 Jun 2015 11:37:48 +0200 Subject: pinctrl: berlin: comment the spi functions Add comments for the SPI functions, to distinguish CLK, SDI, SDO and C{0,1,2,3}n. Signed-off-by: Antoine Tenart Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/berlin/berlin-bg2.c b/drivers/pinctrl/berlin/berlin-bg2.c index b71a6ff..b467e6e 100644 --- a/drivers/pinctrl/berlin/berlin-bg2.c +++ b/drivers/pinctrl/berlin/berlin-bg2.c @@ -20,24 +20,24 @@ static const struct berlin_desc_group berlin2_soc_pinctrl_groups[] = { /* G */ BERLIN_PINCTRL_GROUP("G0", 0x00, 0x1, 0x00, - BERLIN_PINCTRL_FUNCTION(0x0, "spi1"), + BERLIN_PINCTRL_FUNCTION(0x0, "spi1"), /* SS0n */ BERLIN_PINCTRL_FUNCTION(0x1, "gpio")), BERLIN_PINCTRL_GROUP("G1", 0x00, 0x2, 0x01, - BERLIN_PINCTRL_FUNCTION(0x0, "spi1"), + BERLIN_PINCTRL_FUNCTION(0x0, "spi1"), /* SS1n */ BERLIN_PINCTRL_FUNCTION(0x1, "gpio"), BERLIN_PINCTRL_FUNCTION(0x2, "usb1")), BERLIN_PINCTRL_GROUP("G2", 0x00, 0x2, 0x02, BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), - BERLIN_PINCTRL_FUNCTION(0x1, "spi1"), + BERLIN_PINCTRL_FUNCTION(0x1, "spi1"), /* SS2n */ BERLIN_PINCTRL_FUNCTION(0x2, "pwm"), BERLIN_PINCTRL_FUNCTION(0x3, "i2s0")), BERLIN_PINCTRL_GROUP("G3", 0x00, 0x2, 0x04, BERLIN_PINCTRL_FUNCTION(0x0, "soc"), - BERLIN_PINCTRL_FUNCTION(0x1, "spi1"), + BERLIN_PINCTRL_FUNCTION(0x1, "spi1"), /* SS3n */ BERLIN_PINCTRL_FUNCTION(0x2, "gpio"), BERLIN_PINCTRL_FUNCTION(0x3, "i2s1")), BERLIN_PINCTRL_GROUP("G4", 0x00, 0x2, 0x06, - BERLIN_PINCTRL_FUNCTION(0x0, "spi1"), + BERLIN_PINCTRL_FUNCTION(0x0, "spi1"), /* CLK/SDI/SDO */ BERLIN_PINCTRL_FUNCTION(0x1, "gpio"), BERLIN_PINCTRL_FUNCTION(0x2, "pwm")), BERLIN_PINCTRL_GROUP("G5", 0x00, 0x3, 0x08, @@ -163,15 +163,15 @@ static const struct berlin_desc_group berlin2_sysmgr_pinctrl_groups[] = { /* GSM */ BERLIN_PINCTRL_GROUP("GSM0", 0x40, 0x2, 0x00, BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), - BERLIN_PINCTRL_FUNCTION(0x1, "spi2"), + BERLIN_PINCTRL_FUNCTION(0x1, "spi2"), /* SS0n */ BERLIN_PINCTRL_FUNCTION(0x2, "eth1")), BERLIN_PINCTRL_GROUP("GSM1", 0x40, 0x2, 0x02, BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), - BERLIN_PINCTRL_FUNCTION(0x1, "spi2"), + BERLIN_PINCTRL_FUNCTION(0x1, "spi2"), /* SS1n */ BERLIN_PINCTRL_FUNCTION(0x2, "eth1")), BERLIN_PINCTRL_GROUP("GSM2", 0x40, 0x2, 0x04, BERLIN_PINCTRL_FUNCTION(0x0, "twsi2"), - BERLIN_PINCTRL_FUNCTION(0x1, "spi2")), + BERLIN_PINCTRL_FUNCTION(0x1, "spi2")), /* SS2n/SS3n */ BERLIN_PINCTRL_GROUP("GSM3", 0x40, 0x2, 0x06, BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), BERLIN_PINCTRL_FUNCTION(0x1, "uart0"), /* CTS/RTS */ @@ -187,7 +187,7 @@ static const struct berlin_desc_group berlin2_sysmgr_pinctrl_groups[] = { BERLIN_PINCTRL_FUNCTION(0x3, "twsi3")), BERLIN_PINCTRL_GROUP("GSM6", 0x40, 0x2, 0x0c, BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), - BERLIN_PINCTRL_FUNCTION(0x1, "spi2"), + BERLIN_PINCTRL_FUNCTION(0x1, "spi2"), /* CLK/SDO */ BERLIN_PINCTRL_FUNCTION(0x1, "clki")), BERLIN_PINCTRL_GROUP("GSM7", 0x40, 0x1, 0x0e, BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), diff --git a/drivers/pinctrl/berlin/berlin-bg2cd.c b/drivers/pinctrl/berlin/berlin-bg2cd.c index 3fc05fb..a8b9808 100644 --- a/drivers/pinctrl/berlin/berlin-bg2cd.c +++ b/drivers/pinctrl/berlin/berlin-bg2cd.c @@ -68,17 +68,17 @@ static const struct berlin_desc_group berlin2cd_soc_pinctrl_groups[] = { BERLIN_PINCTRL_FUNCTION(0x1, "twsi1"), BERLIN_PINCTRL_FUNCTION(0x2, "gpio")), BERLIN_PINCTRL_GROUP("G8", 0x00, 0x3, 0x10, - BERLIN_PINCTRL_FUNCTION(0x0, "spi1"), + BERLIN_PINCTRL_FUNCTION(0x0, "spi1"), /* SS0n */ BERLIN_PINCTRL_FUNCTION(0x1, "gpio")), BERLIN_PINCTRL_GROUP("G9", 0x00, 0x3, 0x13, BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), - BERLIN_PINCTRL_FUNCTION(0x1, "spi1"), + BERLIN_PINCTRL_FUNCTION(0x1, "spi1"), /* SS1n/SS2n */ BERLIN_PINCTRL_FUNCTION(0x2, "twsi0")), BERLIN_PINCTRL_GROUP("G10", 0x00, 0x2, 0x16, - BERLIN_PINCTRL_FUNCTION(0x0, "spi1"), + BERLIN_PINCTRL_FUNCTION(0x0, "spi1"), /* CLK */ BERLIN_PINCTRL_FUNCTION(0x1, "gpio")), BERLIN_PINCTRL_GROUP("G11", 0x00, 0x2, 0x18, - BERLIN_PINCTRL_FUNCTION(0x0, "spi1"), + BERLIN_PINCTRL_FUNCTION(0x0, "spi1"), /* SDI/SDO */ BERLIN_PINCTRL_FUNCTION(0x1, "gpio")), BERLIN_PINCTRL_GROUP("G12", 0x00, 0x3, 0x1a, BERLIN_PINCTRL_FUNCTION(0x0, "usb1"), diff --git a/drivers/pinctrl/berlin/berlin-bg2q.c b/drivers/pinctrl/berlin/berlin-bg2q.c index bd9662e..65fb871 100644 --- a/drivers/pinctrl/berlin/berlin-bg2q.c +++ b/drivers/pinctrl/berlin/berlin-bg2q.c @@ -59,21 +59,21 @@ static const struct berlin_desc_group berlin2q_soc_pinctrl_groups[] = { BERLIN_PINCTRL_FUNCTION(0x2, "gpio"), BERLIN_PINCTRL_FUNCTION(0x3, "eddc")), BERLIN_PINCTRL_GROUP("G8", 0x18, 0x3, 0x18, - BERLIN_PINCTRL_FUNCTION(0x0, "spi1"), + BERLIN_PINCTRL_FUNCTION(0x0, "spi1"), /* CLK/SDI/SDO */ BERLIN_PINCTRL_FUNCTION(0x1, "gpio")), BERLIN_PINCTRL_GROUP("G9", 0x18, 0x3, 0x1b, - BERLIN_PINCTRL_FUNCTION(0x0, "spi1"), + BERLIN_PINCTRL_FUNCTION(0x0, "spi1"), /* SS0n/SS1n */ BERLIN_PINCTRL_FUNCTION(0x1, "gpio"), BERLIN_PINCTRL_FUNCTION(0x5, "sata")), BERLIN_PINCTRL_GROUP("G10", 0x1c, 0x3, 0x00, BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), - BERLIN_PINCTRL_FUNCTION(0x1, "spi1"), + BERLIN_PINCTRL_FUNCTION(0x1, "spi1"), /* SS2n */ BERLIN_PINCTRL_FUNCTION(0x3, "i2s0"), BERLIN_PINCTRL_FUNCTION(0x4, "pwm"), BERLIN_PINCTRL_FUNCTION(0x5, "sata")), BERLIN_PINCTRL_GROUP("G11", 0x1c, 0x3, 0x03, BERLIN_PINCTRL_FUNCTION(0x0, "jtag"), - BERLIN_PINCTRL_FUNCTION(0x1, "spi1"), + BERLIN_PINCTRL_FUNCTION(0x1, "spi1"), /* SS3n */ BERLIN_PINCTRL_FUNCTION(0x2, "gpio"), BERLIN_PINCTRL_FUNCTION(0x3, "i2s1"), BERLIN_PINCTRL_FUNCTION(0x4, "pwm"), @@ -301,19 +301,19 @@ static const struct berlin_desc_group berlin2q_sysmgr_pinctrl_groups[] = { /* GSM */ BERLIN_PINCTRL_GROUP("GSM0", 0x40, 0x2, 0x00, BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), - BERLIN_PINCTRL_FUNCTION(0x1, "spi2"), + BERLIN_PINCTRL_FUNCTION(0x1, "spi2"), /* SS0n */ BERLIN_PINCTRL_FUNCTION(0x2, "eth1")), BERLIN_PINCTRL_GROUP("GSM1", 0x40, 0x2, 0x02, BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), - BERLIN_PINCTRL_FUNCTION(0x1, "spi2"), + BERLIN_PINCTRL_FUNCTION(0x1, "spi2"), /* SS1n */ BERLIN_PINCTRL_FUNCTION(0x2, "eth1")), BERLIN_PINCTRL_GROUP("GSM2", 0x40, 0x2, 0x04, BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), - BERLIN_PINCTRL_FUNCTION(0x1, "spi2"), + BERLIN_PINCTRL_FUNCTION(0x1, "spi2"), /* SS2n/SS3n */ BERLIN_PINCTRL_FUNCTION(0x2, "eddc")), BERLIN_PINCTRL_GROUP("GSM3", 0x40, 0x2, 0x06, BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), - BERLIN_PINCTRL_FUNCTION(0x1, "spi2"), + BERLIN_PINCTRL_FUNCTION(0x1, "spi2"), /* CLK/SDO */ BERLIN_PINCTRL_FUNCTION(0x2, "eddc")), BERLIN_PINCTRL_GROUP("GSM4", 0x40, 0x1, 0x08, BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), -- cgit v0.10.2 From 6955e6b4f32f57aa156f1048ed39a607b4093003 Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Fri, 5 Jun 2015 15:52:23 -0700 Subject: pinctrl: qcom: Add MSM8660 pinctrl definitions Signed-off-by: Bjorn Andersson Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig index ea575f6..58f5632 100644 --- a/drivers/pinctrl/qcom/Kconfig +++ b/drivers/pinctrl/qcom/Kconfig @@ -31,6 +31,14 @@ config PINCTRL_IPQ8064 This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm TLMM block found in the Qualcomm IPQ8064 platform. +config PINCTRL_MSM8660 + tristate "Qualcomm 8660 pin controller driver" + depends on GPIOLIB && OF + select PINCTRL_MSM + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm TLMM block found in the Qualcomm 8660 platform. + config PINCTRL_MSM8960 tristate "Qualcomm 8960 pin controller driver" depends on GPIOLIB && OF diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile index 6895870..3666c70 100644 --- a/drivers/pinctrl/qcom/Makefile +++ b/drivers/pinctrl/qcom/Makefile @@ -3,6 +3,7 @@ obj-$(CONFIG_PINCTRL_MSM) += pinctrl-msm.o obj-$(CONFIG_PINCTRL_APQ8064) += pinctrl-apq8064.o obj-$(CONFIG_PINCTRL_APQ8084) += pinctrl-apq8084.o obj-$(CONFIG_PINCTRL_IPQ8064) += pinctrl-ipq8064.o +obj-$(CONFIG_PINCTRL_MSM8660) += pinctrl-msm8660.o obj-$(CONFIG_PINCTRL_MSM8960) += pinctrl-msm8960.o obj-$(CONFIG_PINCTRL_MSM8X74) += pinctrl-msm8x74.o obj-$(CONFIG_PINCTRL_MSM8916) += pinctrl-msm8916.o diff --git a/drivers/pinctrl/qcom/pinctrl-msm8660.c b/drivers/pinctrl/qcom/pinctrl-msm8660.c new file mode 100644 index 0000000..3e8f7ac --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-msm8660.c @@ -0,0 +1,984 @@ +/* + * Copyright (c) 2015, Sony Mobile Communications AB. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include + +#include "pinctrl-msm.h" + +static const struct pinctrl_pin_desc msm8660_pins[] = { + PINCTRL_PIN(0, "GPIO_0"), + PINCTRL_PIN(1, "GPIO_1"), + PINCTRL_PIN(2, "GPIO_2"), + PINCTRL_PIN(3, "GPIO_3"), + PINCTRL_PIN(4, "GPIO_4"), + PINCTRL_PIN(5, "GPIO_5"), + PINCTRL_PIN(6, "GPIO_6"), + PINCTRL_PIN(7, "GPIO_7"), + PINCTRL_PIN(8, "GPIO_8"), + PINCTRL_PIN(9, "GPIO_9"), + PINCTRL_PIN(10, "GPIO_10"), + PINCTRL_PIN(11, "GPIO_11"), + PINCTRL_PIN(12, "GPIO_12"), + PINCTRL_PIN(13, "GPIO_13"), + PINCTRL_PIN(14, "GPIO_14"), + PINCTRL_PIN(15, "GPIO_15"), + PINCTRL_PIN(16, "GPIO_16"), + PINCTRL_PIN(17, "GPIO_17"), + PINCTRL_PIN(18, "GPIO_18"), + PINCTRL_PIN(19, "GPIO_19"), + PINCTRL_PIN(20, "GPIO_20"), + PINCTRL_PIN(21, "GPIO_21"), + PINCTRL_PIN(22, "GPIO_22"), + PINCTRL_PIN(23, "GPIO_23"), + PINCTRL_PIN(24, "GPIO_24"), + PINCTRL_PIN(25, "GPIO_25"), + PINCTRL_PIN(26, "GPIO_26"), + PINCTRL_PIN(27, "GPIO_27"), + PINCTRL_PIN(28, "GPIO_28"), + PINCTRL_PIN(29, "GPIO_29"), + PINCTRL_PIN(30, "GPIO_30"), + PINCTRL_PIN(31, "GPIO_31"), + PINCTRL_PIN(32, "GPIO_32"), + PINCTRL_PIN(33, "GPIO_33"), + PINCTRL_PIN(34, "GPIO_34"), + PINCTRL_PIN(35, "GPIO_35"), + PINCTRL_PIN(36, "GPIO_36"), + PINCTRL_PIN(37, "GPIO_37"), + PINCTRL_PIN(38, "GPIO_38"), + PINCTRL_PIN(39, "GPIO_39"), + PINCTRL_PIN(40, "GPIO_40"), + PINCTRL_PIN(41, "GPIO_41"), + PINCTRL_PIN(42, "GPIO_42"), + PINCTRL_PIN(43, "GPIO_43"), + PINCTRL_PIN(44, "GPIO_44"), + PINCTRL_PIN(45, "GPIO_45"), + PINCTRL_PIN(46, "GPIO_46"), + PINCTRL_PIN(47, "GPIO_47"), + PINCTRL_PIN(48, "GPIO_48"), + PINCTRL_PIN(49, "GPIO_49"), + PINCTRL_PIN(50, "GPIO_50"), + PINCTRL_PIN(51, "GPIO_51"), + PINCTRL_PIN(52, "GPIO_52"), + PINCTRL_PIN(53, "GPIO_53"), + PINCTRL_PIN(54, "GPIO_54"), + PINCTRL_PIN(55, "GPIO_55"), + PINCTRL_PIN(56, "GPIO_56"), + PINCTRL_PIN(57, "GPIO_57"), + PINCTRL_PIN(58, "GPIO_58"), + PINCTRL_PIN(59, "GPIO_59"), + PINCTRL_PIN(60, "GPIO_60"), + PINCTRL_PIN(61, "GPIO_61"), + PINCTRL_PIN(62, "GPIO_62"), + PINCTRL_PIN(63, "GPIO_63"), + PINCTRL_PIN(64, "GPIO_64"), + PINCTRL_PIN(65, "GPIO_65"), + PINCTRL_PIN(66, "GPIO_66"), + PINCTRL_PIN(67, "GPIO_67"), + PINCTRL_PIN(68, "GPIO_68"), + PINCTRL_PIN(69, "GPIO_69"), + PINCTRL_PIN(70, "GPIO_70"), + PINCTRL_PIN(71, "GPIO_71"), + PINCTRL_PIN(72, "GPIO_72"), + PINCTRL_PIN(73, "GPIO_73"), + PINCTRL_PIN(74, "GPIO_74"), + PINCTRL_PIN(75, "GPIO_75"), + PINCTRL_PIN(76, "GPIO_76"), + PINCTRL_PIN(77, "GPIO_77"), + PINCTRL_PIN(78, "GPIO_78"), + PINCTRL_PIN(79, "GPIO_79"), + PINCTRL_PIN(80, "GPIO_80"), + PINCTRL_PIN(81, "GPIO_81"), + PINCTRL_PIN(82, "GPIO_82"), + PINCTRL_PIN(83, "GPIO_83"), + PINCTRL_PIN(84, "GPIO_84"), + PINCTRL_PIN(85, "GPIO_85"), + PINCTRL_PIN(86, "GPIO_86"), + PINCTRL_PIN(87, "GPIO_87"), + PINCTRL_PIN(88, "GPIO_88"), + PINCTRL_PIN(89, "GPIO_89"), + PINCTRL_PIN(90, "GPIO_90"), + PINCTRL_PIN(91, "GPIO_91"), + PINCTRL_PIN(92, "GPIO_92"), + PINCTRL_PIN(93, "GPIO_93"), + PINCTRL_PIN(94, "GPIO_94"), + PINCTRL_PIN(95, "GPIO_95"), + PINCTRL_PIN(96, "GPIO_96"), + PINCTRL_PIN(97, "GPIO_97"), + PINCTRL_PIN(98, "GPIO_98"), + PINCTRL_PIN(99, "GPIO_99"), + PINCTRL_PIN(100, "GPIO_100"), + PINCTRL_PIN(101, "GPIO_101"), + PINCTRL_PIN(102, "GPIO_102"), + PINCTRL_PIN(103, "GPIO_103"), + PINCTRL_PIN(104, "GPIO_104"), + PINCTRL_PIN(105, "GPIO_105"), + PINCTRL_PIN(106, "GPIO_106"), + PINCTRL_PIN(107, "GPIO_107"), + PINCTRL_PIN(108, "GPIO_108"), + PINCTRL_PIN(109, "GPIO_109"), + PINCTRL_PIN(110, "GPIO_110"), + PINCTRL_PIN(111, "GPIO_111"), + PINCTRL_PIN(112, "GPIO_112"), + PINCTRL_PIN(113, "GPIO_113"), + PINCTRL_PIN(114, "GPIO_114"), + PINCTRL_PIN(115, "GPIO_115"), + PINCTRL_PIN(116, "GPIO_116"), + PINCTRL_PIN(117, "GPIO_117"), + PINCTRL_PIN(118, "GPIO_118"), + PINCTRL_PIN(119, "GPIO_119"), + PINCTRL_PIN(120, "GPIO_120"), + PINCTRL_PIN(121, "GPIO_121"), + PINCTRL_PIN(122, "GPIO_122"), + PINCTRL_PIN(123, "GPIO_123"), + PINCTRL_PIN(124, "GPIO_124"), + PINCTRL_PIN(125, "GPIO_125"), + PINCTRL_PIN(126, "GPIO_126"), + PINCTRL_PIN(127, "GPIO_127"), + PINCTRL_PIN(128, "GPIO_128"), + PINCTRL_PIN(129, "GPIO_129"), + PINCTRL_PIN(130, "GPIO_130"), + PINCTRL_PIN(131, "GPIO_131"), + PINCTRL_PIN(132, "GPIO_132"), + PINCTRL_PIN(133, "GPIO_133"), + PINCTRL_PIN(134, "GPIO_134"), + PINCTRL_PIN(135, "GPIO_135"), + PINCTRL_PIN(136, "GPIO_136"), + PINCTRL_PIN(137, "GPIO_137"), + PINCTRL_PIN(138, "GPIO_138"), + PINCTRL_PIN(139, "GPIO_139"), + PINCTRL_PIN(140, "GPIO_140"), + PINCTRL_PIN(141, "GPIO_141"), + PINCTRL_PIN(142, "GPIO_142"), + PINCTRL_PIN(143, "GPIO_143"), + PINCTRL_PIN(144, "GPIO_144"), + PINCTRL_PIN(145, "GPIO_145"), + PINCTRL_PIN(146, "GPIO_146"), + PINCTRL_PIN(147, "GPIO_147"), + PINCTRL_PIN(148, "GPIO_148"), + PINCTRL_PIN(149, "GPIO_149"), + PINCTRL_PIN(150, "GPIO_150"), + PINCTRL_PIN(151, "GPIO_151"), + PINCTRL_PIN(152, "GPIO_152"), + PINCTRL_PIN(153, "GPIO_153"), + PINCTRL_PIN(154, "GPIO_154"), + PINCTRL_PIN(155, "GPIO_155"), + PINCTRL_PIN(156, "GPIO_156"), + PINCTRL_PIN(157, "GPIO_157"), + PINCTRL_PIN(158, "GPIO_158"), + PINCTRL_PIN(159, "GPIO_159"), + PINCTRL_PIN(160, "GPIO_160"), + PINCTRL_PIN(161, "GPIO_161"), + PINCTRL_PIN(162, "GPIO_162"), + PINCTRL_PIN(163, "GPIO_163"), + PINCTRL_PIN(164, "GPIO_164"), + PINCTRL_PIN(165, "GPIO_165"), + PINCTRL_PIN(166, "GPIO_166"), + PINCTRL_PIN(167, "GPIO_167"), + PINCTRL_PIN(168, "GPIO_168"), + PINCTRL_PIN(169, "GPIO_169"), + PINCTRL_PIN(170, "GPIO_170"), + PINCTRL_PIN(171, "GPIO_171"), + PINCTRL_PIN(172, "GPIO_172"), + + PINCTRL_PIN(173, "SDC1_CLK"), + PINCTRL_PIN(174, "SDC1_CMD"), + PINCTRL_PIN(175, "SDC1_DATA"), + PINCTRL_PIN(176, "SDC3_CLK"), + PINCTRL_PIN(177, "SDC3_CMD"), + PINCTRL_PIN(178, "SDC3_DATA"), +}; + +#define DECLARE_MSM_GPIO_PIN(pin) static const unsigned int gpio##pin##_pins[] = { pin } +DECLARE_MSM_GPIO_PIN(0); +DECLARE_MSM_GPIO_PIN(1); +DECLARE_MSM_GPIO_PIN(2); +DECLARE_MSM_GPIO_PIN(3); +DECLARE_MSM_GPIO_PIN(4); +DECLARE_MSM_GPIO_PIN(5); +DECLARE_MSM_GPIO_PIN(6); +DECLARE_MSM_GPIO_PIN(7); +DECLARE_MSM_GPIO_PIN(8); +DECLARE_MSM_GPIO_PIN(9); +DECLARE_MSM_GPIO_PIN(10); +DECLARE_MSM_GPIO_PIN(11); +DECLARE_MSM_GPIO_PIN(12); +DECLARE_MSM_GPIO_PIN(13); +DECLARE_MSM_GPIO_PIN(14); +DECLARE_MSM_GPIO_PIN(15); +DECLARE_MSM_GPIO_PIN(16); +DECLARE_MSM_GPIO_PIN(17); +DECLARE_MSM_GPIO_PIN(18); +DECLARE_MSM_GPIO_PIN(19); +DECLARE_MSM_GPIO_PIN(20); +DECLARE_MSM_GPIO_PIN(21); +DECLARE_MSM_GPIO_PIN(22); +DECLARE_MSM_GPIO_PIN(23); +DECLARE_MSM_GPIO_PIN(24); +DECLARE_MSM_GPIO_PIN(25); +DECLARE_MSM_GPIO_PIN(26); +DECLARE_MSM_GPIO_PIN(27); +DECLARE_MSM_GPIO_PIN(28); +DECLARE_MSM_GPIO_PIN(29); +DECLARE_MSM_GPIO_PIN(30); +DECLARE_MSM_GPIO_PIN(31); +DECLARE_MSM_GPIO_PIN(32); +DECLARE_MSM_GPIO_PIN(33); +DECLARE_MSM_GPIO_PIN(34); +DECLARE_MSM_GPIO_PIN(35); +DECLARE_MSM_GPIO_PIN(36); +DECLARE_MSM_GPIO_PIN(37); +DECLARE_MSM_GPIO_PIN(38); +DECLARE_MSM_GPIO_PIN(39); +DECLARE_MSM_GPIO_PIN(40); +DECLARE_MSM_GPIO_PIN(41); +DECLARE_MSM_GPIO_PIN(42); +DECLARE_MSM_GPIO_PIN(43); +DECLARE_MSM_GPIO_PIN(44); +DECLARE_MSM_GPIO_PIN(45); +DECLARE_MSM_GPIO_PIN(46); +DECLARE_MSM_GPIO_PIN(47); +DECLARE_MSM_GPIO_PIN(48); +DECLARE_MSM_GPIO_PIN(49); +DECLARE_MSM_GPIO_PIN(50); +DECLARE_MSM_GPIO_PIN(51); +DECLARE_MSM_GPIO_PIN(52); +DECLARE_MSM_GPIO_PIN(53); +DECLARE_MSM_GPIO_PIN(54); +DECLARE_MSM_GPIO_PIN(55); +DECLARE_MSM_GPIO_PIN(56); +DECLARE_MSM_GPIO_PIN(57); +DECLARE_MSM_GPIO_PIN(58); +DECLARE_MSM_GPIO_PIN(59); +DECLARE_MSM_GPIO_PIN(60); +DECLARE_MSM_GPIO_PIN(61); +DECLARE_MSM_GPIO_PIN(62); +DECLARE_MSM_GPIO_PIN(63); +DECLARE_MSM_GPIO_PIN(64); +DECLARE_MSM_GPIO_PIN(65); +DECLARE_MSM_GPIO_PIN(66); +DECLARE_MSM_GPIO_PIN(67); +DECLARE_MSM_GPIO_PIN(68); +DECLARE_MSM_GPIO_PIN(69); +DECLARE_MSM_GPIO_PIN(70); +DECLARE_MSM_GPIO_PIN(71); +DECLARE_MSM_GPIO_PIN(72); +DECLARE_MSM_GPIO_PIN(73); +DECLARE_MSM_GPIO_PIN(74); +DECLARE_MSM_GPIO_PIN(75); +DECLARE_MSM_GPIO_PIN(76); +DECLARE_MSM_GPIO_PIN(77); +DECLARE_MSM_GPIO_PIN(78); +DECLARE_MSM_GPIO_PIN(79); +DECLARE_MSM_GPIO_PIN(80); +DECLARE_MSM_GPIO_PIN(81); +DECLARE_MSM_GPIO_PIN(82); +DECLARE_MSM_GPIO_PIN(83); +DECLARE_MSM_GPIO_PIN(84); +DECLARE_MSM_GPIO_PIN(85); +DECLARE_MSM_GPIO_PIN(86); +DECLARE_MSM_GPIO_PIN(87); +DECLARE_MSM_GPIO_PIN(88); +DECLARE_MSM_GPIO_PIN(89); +DECLARE_MSM_GPIO_PIN(90); +DECLARE_MSM_GPIO_PIN(91); +DECLARE_MSM_GPIO_PIN(92); +DECLARE_MSM_GPIO_PIN(93); +DECLARE_MSM_GPIO_PIN(94); +DECLARE_MSM_GPIO_PIN(95); +DECLARE_MSM_GPIO_PIN(96); +DECLARE_MSM_GPIO_PIN(97); +DECLARE_MSM_GPIO_PIN(98); +DECLARE_MSM_GPIO_PIN(99); +DECLARE_MSM_GPIO_PIN(100); +DECLARE_MSM_GPIO_PIN(101); +DECLARE_MSM_GPIO_PIN(102); +DECLARE_MSM_GPIO_PIN(103); +DECLARE_MSM_GPIO_PIN(104); +DECLARE_MSM_GPIO_PIN(105); +DECLARE_MSM_GPIO_PIN(106); +DECLARE_MSM_GPIO_PIN(107); +DECLARE_MSM_GPIO_PIN(108); +DECLARE_MSM_GPIO_PIN(109); +DECLARE_MSM_GPIO_PIN(110); +DECLARE_MSM_GPIO_PIN(111); +DECLARE_MSM_GPIO_PIN(112); +DECLARE_MSM_GPIO_PIN(113); +DECLARE_MSM_GPIO_PIN(114); +DECLARE_MSM_GPIO_PIN(115); +DECLARE_MSM_GPIO_PIN(116); +DECLARE_MSM_GPIO_PIN(117); +DECLARE_MSM_GPIO_PIN(118); +DECLARE_MSM_GPIO_PIN(119); +DECLARE_MSM_GPIO_PIN(120); +DECLARE_MSM_GPIO_PIN(121); +DECLARE_MSM_GPIO_PIN(122); +DECLARE_MSM_GPIO_PIN(123); +DECLARE_MSM_GPIO_PIN(124); +DECLARE_MSM_GPIO_PIN(125); +DECLARE_MSM_GPIO_PIN(126); +DECLARE_MSM_GPIO_PIN(127); +DECLARE_MSM_GPIO_PIN(128); +DECLARE_MSM_GPIO_PIN(129); +DECLARE_MSM_GPIO_PIN(130); +DECLARE_MSM_GPIO_PIN(131); +DECLARE_MSM_GPIO_PIN(132); +DECLARE_MSM_GPIO_PIN(133); +DECLARE_MSM_GPIO_PIN(134); +DECLARE_MSM_GPIO_PIN(135); +DECLARE_MSM_GPIO_PIN(136); +DECLARE_MSM_GPIO_PIN(137); +DECLARE_MSM_GPIO_PIN(138); +DECLARE_MSM_GPIO_PIN(139); +DECLARE_MSM_GPIO_PIN(140); +DECLARE_MSM_GPIO_PIN(141); +DECLARE_MSM_GPIO_PIN(142); +DECLARE_MSM_GPIO_PIN(143); +DECLARE_MSM_GPIO_PIN(144); +DECLARE_MSM_GPIO_PIN(145); +DECLARE_MSM_GPIO_PIN(146); +DECLARE_MSM_GPIO_PIN(147); +DECLARE_MSM_GPIO_PIN(148); +DECLARE_MSM_GPIO_PIN(149); +DECLARE_MSM_GPIO_PIN(150); +DECLARE_MSM_GPIO_PIN(151); +DECLARE_MSM_GPIO_PIN(152); +DECLARE_MSM_GPIO_PIN(153); +DECLARE_MSM_GPIO_PIN(154); +DECLARE_MSM_GPIO_PIN(155); +DECLARE_MSM_GPIO_PIN(156); +DECLARE_MSM_GPIO_PIN(157); +DECLARE_MSM_GPIO_PIN(158); +DECLARE_MSM_GPIO_PIN(159); +DECLARE_MSM_GPIO_PIN(160); +DECLARE_MSM_GPIO_PIN(161); +DECLARE_MSM_GPIO_PIN(162); +DECLARE_MSM_GPIO_PIN(163); +DECLARE_MSM_GPIO_PIN(164); +DECLARE_MSM_GPIO_PIN(165); +DECLARE_MSM_GPIO_PIN(166); +DECLARE_MSM_GPIO_PIN(167); +DECLARE_MSM_GPIO_PIN(168); +DECLARE_MSM_GPIO_PIN(169); +DECLARE_MSM_GPIO_PIN(170); +DECLARE_MSM_GPIO_PIN(171); +DECLARE_MSM_GPIO_PIN(172); + +static const unsigned int sdc4_clk_pins[] = { 173 }; +static const unsigned int sdc4_cmd_pins[] = { 174 }; +static const unsigned int sdc4_data_pins[] = { 175 }; +static const unsigned int sdc3_clk_pins[] = { 176 }; +static const unsigned int sdc3_cmd_pins[] = { 177 }; +static const unsigned int sdc3_data_pins[] = { 178 }; + +#define FUNCTION(fname) \ + [MSM_MUX_##fname] = { \ + .name = #fname, \ + .groups = fname##_groups, \ + .ngroups = ARRAY_SIZE(fname##_groups), \ + } + +#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7) \ + { \ + .name = "gpio" #id, \ + .pins = gpio##id##_pins, \ + .npins = ARRAY_SIZE(gpio##id##_pins), \ + .funcs = (int[]){ \ + MSM_MUX_gpio, \ + MSM_MUX_##f1, \ + MSM_MUX_##f2, \ + MSM_MUX_##f3, \ + MSM_MUX_##f4, \ + MSM_MUX_##f5, \ + MSM_MUX_##f6, \ + MSM_MUX_##f7, \ + }, \ + .nfuncs = 8, \ + .ctl_reg = 0x1000 + 0x10 * id, \ + .io_reg = 0x1004 + 0x10 * id, \ + .intr_cfg_reg = 0x1008 + 0x10 * id, \ + .intr_status_reg = 0x100c + 0x10 * id, \ + .intr_target_reg = 0x400 + 0x4 * id, \ + .mux_bit = 2, \ + .pull_bit = 0, \ + .drv_bit = 6, \ + .oe_bit = 9, \ + .in_bit = 0, \ + .out_bit = 1, \ + .intr_enable_bit = 0, \ + .intr_status_bit = 0, \ + .intr_ack_high = 1, \ + .intr_target_bit = 0, \ + .intr_target_kpss_val = 4, \ + .intr_raw_status_bit = 3, \ + .intr_polarity_bit = 1, \ + .intr_detection_bit = 2, \ + .intr_detection_width = 1, \ + } + +#define SDC_PINGROUP(pg_name, ctl, pull, drv) \ + { \ + .name = #pg_name, \ + .pins = pg_name##_pins, \ + .npins = ARRAY_SIZE(pg_name##_pins), \ + .ctl_reg = ctl, \ + .io_reg = 0, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .mux_bit = -1, \ + .pull_bit = pull, \ + .drv_bit = drv, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = -1, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_target_kpss_val = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } + +enum msm8660_functions { + MSM_MUX_gpio, + MSM_MUX_cam_mclk, + MSM_MUX_dsub, + MSM_MUX_ext_gps, + MSM_MUX_gp_clk_0a, + MSM_MUX_gp_clk_0b, + MSM_MUX_gp_clk_1a, + MSM_MUX_gp_clk_1b, + MSM_MUX_gp_clk_2a, + MSM_MUX_gp_clk_2b, + MSM_MUX_gp_mn, + MSM_MUX_gsbi1, + MSM_MUX_gsbi1_spi_cs1_n, + MSM_MUX_gsbi1_spi_cs2a_n, + MSM_MUX_gsbi1_spi_cs2b_n, + MSM_MUX_gsbi1_spi_cs3_n, + MSM_MUX_gsbi2, + MSM_MUX_gsbi2_spi_cs1_n, + MSM_MUX_gsbi2_spi_cs2_n, + MSM_MUX_gsbi2_spi_cs3_n, + MSM_MUX_gsbi3, + MSM_MUX_gsbi3_spi_cs1_n, + MSM_MUX_gsbi3_spi_cs2_n, + MSM_MUX_gsbi3_spi_cs3_n, + MSM_MUX_gsbi4, + MSM_MUX_gsbi5, + MSM_MUX_gsbi6, + MSM_MUX_gsbi7, + MSM_MUX_gsbi8, + MSM_MUX_gsbi9, + MSM_MUX_gsbi10, + MSM_MUX_gsbi11, + MSM_MUX_gsbi12, + MSM_MUX_hdmi, + MSM_MUX_i2s, + MSM_MUX_lcdc, + MSM_MUX_mdp_vsync, + MSM_MUX_mi2s, + MSM_MUX_pcm, + MSM_MUX_ps_hold, + MSM_MUX_sdc1, + MSM_MUX_sdc2, + MSM_MUX_sdc5, + MSM_MUX_tsif1, + MSM_MUX_tsif2, + MSM_MUX_usb_fs1, + MSM_MUX_usb_fs1_oe_n, + MSM_MUX_usb_fs2, + MSM_MUX_usb_fs2_oe_n, + MSM_MUX_vfe, + MSM_MUX_vsens_alarm, + MSM_MUX__, +}; + +static const char * const gpio_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", + "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", + "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", + "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", + "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", + "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", + "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49", + "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56", + "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", + "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70", + "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77", + "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84", + "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91", + "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98", + "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104", + "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110", + "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio116", + "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", "gpio122", + "gpio123", "gpio124", "gpio125", "gpio126", "gpio127", "gpio128", + "gpio129", "gpio130", "gpio131", "gpio132", "gpio133", "gpio134", + "gpio135", "gpio136", "gpio137", "gpio138", "gpio139", "gpio140", + "gpio141", "gpio142", "gpio143", "gpio144", "gpio145", "gpio146", + "gpio147", "gpio148", "gpio149", "gpio150", "gpio151", "gpio152", + "gpio153", "gpio154", "gpio155", "gpio156", "gpio157", "gpio158", + "gpio159", "gpio160", "gpio161", "gpio162", "gpio163", "gpio164", + "gpio165", "gpio166", "gpio167", "gpio168", "gpio169", "gpio170", + "gpio171", "gpio172" +}; + +static const char * const cam_mclk_groups[] = { + "gpio32" +}; +static const char * const dsub_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", + "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", + "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", + "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27" +}; +static const char * const ext_gps_groups[] = { + "gpio66", "gpio67", "gpio68", "gpio69" +}; +static const char * const gp_clk_0a_groups[] = { + "gpio30" +}; +static const char * const gp_clk_0b_groups[] = { + "gpio115" +}; +static const char * const gp_clk_1a_groups[] = { + "gpio31" +}; +static const char * const gp_clk_1b_groups[] = { + "gpio122" +}; +static const char * const gp_clk_2a_groups[] = { + "gpio103" +}; +static const char * const gp_clk_2b_groups[] = { + "gpio70" +}; +static const char * const gp_mn_groups[] = { + "gpio29" +}; +static const char * const gsbi1_groups[] = { + "gpio33", "gpio34", "gpio35", "gpio36" +}; +static const char * const gsbi1_spi_cs1_n_groups[] = { +}; +static const char * const gsbi1_spi_cs2a_n_groups[] = { +}; +static const char * const gsbi1_spi_cs2b_n_groups[] = { +}; +static const char * const gsbi1_spi_cs3_n_groups[] = { +}; +static const char * const gsbi2_groups[] = { + "gpio37", "gpio38", "gpio39", "gpio40" +}; +static const char * const gsbi2_spi_cs1_n_groups[] = { + "gpio123" +}; +static const char * const gsbi2_spi_cs2_n_groups[] = { + "gpio124" +}; +static const char * const gsbi2_spi_cs3_n_groups[] = { + "gpio125" +}; +static const char * const gsbi3_groups[] = { + "gpio41", "gpio42", "gpio43", "gpio44" +}; +static const char * const gsbi3_spi_cs1_n_groups[] = { + "gpio62" +}; +static const char * const gsbi3_spi_cs2_n_groups[] = { + "gpio45" +}; +static const char * const gsbi3_spi_cs3_n_groups[] = { + "gpio46" +}; +static const char * const gsbi4_groups[] = { + "gpio45", "gpio56", "gpio47", "gpio48" +}; +static const char * const gsbi5_groups[] = { + "gpio49", "gpio50", "gpio51", "gpio52" +}; +static const char * const gsbi6_groups[] = { + "gpio53", "gpio54", "gpio55", "gpio56" +}; +static const char * const gsbi7_groups[] = { + "gpio57", "gpio58", "gpio59", "gpio60" +}; +static const char * const gsbi8_groups[] = { + "gpio62", "gpio63", "gpio64", "gpio65" +}; +static const char * const gsbi9_groups[] = { + "gpio66", "gpio67", "gpio68", "gpio69" +}; +static const char * const gsbi10_groups[] = { + "gpio70", "gpio71", "gpio72", "gpio73" +}; +static const char * const gsbi11_groups[] = { + "gpio103", "gpio104", "gpio105", "gpio106" +}; +static const char * const gsbi12_groups[] = { + "gpio115", "gpio116", "gpio117", "gpio118" +}; +static const char * const hdmi_groups[] = { + "gpio169", "gpio170", "gpio171", "gpio172" +}; +static const char * const i2s_groups[] = { + "gpio108", "gpio109", "gpio110", "gpio115", "gpio116", "gpio117", + "gpio118", "gpio119", "gpio120", "gpio121", "gpio122" +}; +static const char * const lcdc_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", + "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", + "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", + "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27" +}; +static const char * const mdp_vsync_groups[] = { + "gpio28", "gpio39", "gpio41" +}; +static const char * const mi2s_groups[] = { + "gpio101", "gpio102", "gpio103", "gpio104", "gpio105", "gpio106", + "gpio107" +}; +static const char * const pcm_groups[] = { + "gpio111", "gpio112", "gpio113", "gpio114" +}; +static const char * const ps_hold_groups[] = { + "gpio92" +}; +static const char * const sdc1_groups[] = { + "gpio159", "gpio160", "gpio161", "gpio162", "gpio163", "gpio164", + "gpio165", "gpio166", "gpio167", "gpio168" +}; +static const char * const sdc2_groups[] = { + "gpio143", "gpio144", "gpio145", "gpio146", "gpio147", "gpio148", + "gpio149", "gpio150", "gpio151", "gpio152" +}; +static const char * const sdc5_groups[] = { + "gpio95", "gpio96", "gpio97", "gpio98", "gpio99", "gpio100" +}; +static const char * const tsif1_groups[] = { + "gpio93", "gpio94", "gpio95", "gpio96" +}; +static const char * const tsif2_groups[] = { + "gpio97", "gpio98", "gpio99", "gpio100" +}; +static const char * const usb_fs1_groups[] = { + "gpio49", "gpio50", "gpio51" +}; +static const char * const usb_fs1_oe_n_groups[] = { + "gpio51" +}; +static const char * const usb_fs2_groups[] = { + "gpio71", "gpio72", "gpio73" +}; +static const char * const usb_fs2_oe_n_groups[] = { + "gpio73" +}; +static const char * const vfe_groups[] = { + "gpio29", "gpio30", "gpio31", "gpio42", "gpio46", "gpio105", "gpio106", + "gpio117" +}; +static const char * const vsens_alarm_groups[] = { + "gpio127" +}; + +static const struct msm_function msm8660_functions[] = { + FUNCTION(gpio), + FUNCTION(cam_mclk), + FUNCTION(dsub), + FUNCTION(ext_gps), + FUNCTION(gp_clk_0a), + FUNCTION(gp_clk_0b), + FUNCTION(gp_clk_1a), + FUNCTION(gp_clk_1b), + FUNCTION(gp_clk_2a), + FUNCTION(gp_clk_2b), + FUNCTION(gp_mn), + FUNCTION(gsbi1), + FUNCTION(gsbi1_spi_cs1_n), + FUNCTION(gsbi1_spi_cs2a_n), + FUNCTION(gsbi1_spi_cs2b_n), + FUNCTION(gsbi1_spi_cs3_n), + FUNCTION(gsbi2), + FUNCTION(gsbi2_spi_cs1_n), + FUNCTION(gsbi2_spi_cs2_n), + FUNCTION(gsbi2_spi_cs3_n), + FUNCTION(gsbi3), + FUNCTION(gsbi3_spi_cs1_n), + FUNCTION(gsbi3_spi_cs2_n), + FUNCTION(gsbi3_spi_cs3_n), + FUNCTION(gsbi4), + FUNCTION(gsbi5), + FUNCTION(gsbi6), + FUNCTION(gsbi7), + FUNCTION(gsbi8), + FUNCTION(gsbi9), + FUNCTION(gsbi10), + FUNCTION(gsbi11), + FUNCTION(gsbi12), + FUNCTION(hdmi), + FUNCTION(i2s), + FUNCTION(lcdc), + FUNCTION(mdp_vsync), + FUNCTION(mi2s), + FUNCTION(pcm), + FUNCTION(ps_hold), + FUNCTION(sdc1), + FUNCTION(sdc2), + FUNCTION(sdc5), + FUNCTION(tsif1), + FUNCTION(tsif2), + FUNCTION(usb_fs1), + FUNCTION(usb_fs1_oe_n), + FUNCTION(usb_fs2), + FUNCTION(usb_fs2_oe_n), + FUNCTION(vfe), + FUNCTION(vsens_alarm), +}; + +static const struct msm_pingroup msm8660_groups[] = { + PINGROUP(0, lcdc, dsub, _, _, _, _, _), + PINGROUP(1, lcdc, dsub, _, _, _, _, _), + PINGROUP(2, lcdc, dsub, _, _, _, _, _), + PINGROUP(3, lcdc, dsub, _, _, _, _, _), + PINGROUP(4, lcdc, dsub, _, _, _, _, _), + PINGROUP(5, lcdc, dsub, _, _, _, _, _), + PINGROUP(6, lcdc, dsub, _, _, _, _, _), + PINGROUP(7, lcdc, dsub, _, _, _, _, _), + PINGROUP(8, lcdc, dsub, _, _, _, _, _), + PINGROUP(9, lcdc, dsub, _, _, _, _, _), + PINGROUP(10, lcdc, dsub, _, _, _, _, _), + PINGROUP(11, lcdc, dsub, _, _, _, _, _), + PINGROUP(12, lcdc, dsub, _, _, _, _, _), + PINGROUP(13, lcdc, dsub, _, _, _, _, _), + PINGROUP(14, lcdc, dsub, _, _, _, _, _), + PINGROUP(15, lcdc, dsub, _, _, _, _, _), + PINGROUP(16, lcdc, dsub, _, _, _, _, _), + PINGROUP(17, lcdc, dsub, _, _, _, _, _), + PINGROUP(18, lcdc, dsub, _, _, _, _, _), + PINGROUP(19, lcdc, dsub, _, _, _, _, _), + PINGROUP(20, lcdc, dsub, _, _, _, _, _), + PINGROUP(21, lcdc, dsub, _, _, _, _, _), + PINGROUP(22, lcdc, dsub, _, _, _, _, _), + PINGROUP(23, lcdc, dsub, _, _, _, _, _), + PINGROUP(24, lcdc, dsub, _, _, _, _, _), + PINGROUP(25, lcdc, dsub, _, _, _, _, _), + PINGROUP(26, lcdc, dsub, _, _, _, _, _), + PINGROUP(27, lcdc, dsub, _, _, _, _, _), + PINGROUP(28, mdp_vsync, _, _, _, _, _, _), + PINGROUP(29, vfe, gp_mn, _, _, _, _, _), + PINGROUP(30, vfe, gp_clk_0a, _, _, _, _, _), + PINGROUP(31, vfe, gp_clk_1a, _, _, _, _, _), + PINGROUP(32, cam_mclk, _, _, _, _, _, _), + PINGROUP(33, gsbi1, _, _, _, _, _, _), + PINGROUP(34, gsbi1, _, _, _, _, _, _), + PINGROUP(35, gsbi1, _, _, _, _, _, _), + PINGROUP(36, gsbi1, _, _, _, _, _, _), + PINGROUP(37, gsbi2, _, _, _, _, _, _), + PINGROUP(38, gsbi2, _, _, _, _, _, _), + PINGROUP(39, gsbi2, _, mdp_vsync, _, _, _, _), + PINGROUP(40, gsbi2, _, _, _, _, _, _), + PINGROUP(41, gsbi3, mdp_vsync, _, _, _, _, _), + PINGROUP(42, gsbi3, vfe, _, _, _, _, _), + PINGROUP(43, gsbi3, _, _, _, _, _, _), + PINGROUP(44, gsbi3, _, _, _, _, _, _), + PINGROUP(45, gsbi4, gsbi3_spi_cs2_n, _, _, _, _, _), + PINGROUP(46, gsbi4, gsbi3_spi_cs3_n, vfe, _, _, _, _), + PINGROUP(47, gsbi4, _, _, _, _, _, _), + PINGROUP(48, gsbi4, _, _, _, _, _, _), + PINGROUP(49, gsbi5, usb_fs1, _, _, _, _, _), + PINGROUP(50, gsbi5, usb_fs1, _, _, _, _, _), + PINGROUP(51, gsbi5, usb_fs1, usb_fs1_oe_n, _, _, _, _), + PINGROUP(52, gsbi5, _, _, _, _, _, _), + PINGROUP(53, gsbi6, _, _, _, _, _, _), + PINGROUP(54, gsbi6, _, _, _, _, _, _), + PINGROUP(55, gsbi6, _, _, _, _, _, _), + PINGROUP(56, gsbi6, _, _, _, _, _, _), + PINGROUP(57, gsbi7, _, _, _, _, _, _), + PINGROUP(58, gsbi7, _, _, _, _, _, _), + PINGROUP(59, gsbi7, _, _, _, _, _, _), + PINGROUP(60, gsbi7, _, _, _, _, _, _), + PINGROUP(61, _, _, _, _, _, _, _), + PINGROUP(62, gsbi8, gsbi3_spi_cs1_n, gsbi1_spi_cs2a_n, _, _, _, _), + PINGROUP(63, gsbi8, gsbi1_spi_cs1_n, _, _, _, _, _), + PINGROUP(64, gsbi8, gsbi1_spi_cs2b_n, _, _, _, _, _), + PINGROUP(65, gsbi8, gsbi1_spi_cs3_n, _, _, _, _, _), + PINGROUP(66, gsbi9, ext_gps, _, _, _, _, _), + PINGROUP(67, gsbi9, ext_gps, _, _, _, _, _), + PINGROUP(68, gsbi9, ext_gps, _, _, _, _, _), + PINGROUP(69, gsbi9, ext_gps, _, _, _, _, _), + PINGROUP(70, gsbi10, gp_clk_2b, _, _, _, _, _), + PINGROUP(71, gsbi10, usb_fs2, _, _, _, _, _), + PINGROUP(72, gsbi10, usb_fs2, _, _, _, _, _), + PINGROUP(73, gsbi10, usb_fs2, usb_fs2_oe_n, _, _, _, _), + PINGROUP(74, _, _, _, _, _, _, _), + PINGROUP(75, _, _, _, _, _, _, _), + PINGROUP(76, _, _, _, _, _, _, _), + PINGROUP(77, _, _, _, _, _, _, _), + PINGROUP(78, _, _, _, _, _, _, _), + PINGROUP(79, _, _, _, _, _, _, _), + PINGROUP(80, _, _, _, _, _, _, _), + PINGROUP(81, _, _, _, _, _, _, _), + PINGROUP(82, _, _, _, _, _, _, _), + PINGROUP(83, _, _, _, _, _, _, _), + PINGROUP(84, _, _, _, _, _, _, _), + PINGROUP(85, _, _, _, _, _, _, _), + PINGROUP(86, _, _, _, _, _, _, _), + PINGROUP(87, _, _, _, _, _, _, _), + PINGROUP(88, _, _, _, _, _, _, _), + PINGROUP(89, _, _, _, _, _, _, _), + PINGROUP(90, _, _, _, _, _, _, _), + PINGROUP(91, _, _, _, _, _, _, _), + PINGROUP(92, ps_hold, _, _, _, _, _, _), + PINGROUP(93, tsif1, _, _, _, _, _, _), + PINGROUP(94, tsif1, _, _, _, _, _, _), + PINGROUP(95, tsif1, sdc5, _, _, _, _, _), + PINGROUP(96, tsif1, sdc5, _, _, _, _, _), + PINGROUP(97, tsif2, sdc5, _, _, _, _, _), + PINGROUP(98, tsif2, sdc5, _, _, _, _, _), + PINGROUP(99, tsif2, sdc5, _, _, _, _, _), + PINGROUP(100, tsif2, sdc5, _, _, _, _, _), + PINGROUP(101, mi2s, _, _, _, _, _, _), + PINGROUP(102, mi2s, _, _, _, _, _, _), + PINGROUP(103, mi2s, gsbi11, gp_clk_2a, _, _, _, _), + PINGROUP(104, mi2s, gsbi11, _, _, _, _, _), + PINGROUP(105, mi2s, gsbi11, vfe, _, _, _, _), + PINGROUP(106, mi2s, gsbi11, vfe, _, _, _, _), + PINGROUP(107, mi2s, _, _, _, _, _, _), + PINGROUP(108, i2s, _, _, _, _, _, _), + PINGROUP(109, i2s, _, _, _, _, _, _), + PINGROUP(110, i2s, _, _, _, _, _, _), + PINGROUP(111, pcm, _, _, _, _, _, _), + PINGROUP(112, pcm, _, _, _, _, _, _), + PINGROUP(113, pcm, _, _, _, _, _, _), + PINGROUP(114, pcm, _, _, _, _, _, _), + PINGROUP(115, i2s, gsbi12, gp_clk_0b, _, _, _, _), + PINGROUP(116, i2s, gsbi12, _, _, _, _, _), + PINGROUP(117, i2s, gsbi12, vfe, _, _, _, _), + PINGROUP(118, i2s, gsbi12, _, _, _, _, _), + PINGROUP(119, i2s, _, _, _, _, _, _), + PINGROUP(120, i2s, _, _, _, _, _, _), + PINGROUP(121, i2s, _, _, _, _, _, _), + PINGROUP(122, i2s, gp_clk_1b, _, _, _, _, _), + PINGROUP(123, _, gsbi2_spi_cs1_n, _, _, _, _, _), + PINGROUP(124, _, gsbi2_spi_cs2_n, _, _, _, _, _), + PINGROUP(125, _, gsbi2_spi_cs3_n, _, _, _, _, _), + PINGROUP(126, _, _, _, _, _, _, _), + PINGROUP(127, _, vsens_alarm, _, _, _, _, _), + PINGROUP(128, _, _, _, _, _, _, _), + PINGROUP(129, _, _, _, _, _, _, _), + PINGROUP(130, _, _, _, _, _, _, _), + PINGROUP(131, _, _, _, _, _, _, _), + PINGROUP(132, _, _, _, _, _, _, _), + PINGROUP(133, _, _, _, _, _, _, _), + PINGROUP(134, _, _, _, _, _, _, _), + PINGROUP(135, _, _, _, _, _, _, _), + PINGROUP(136, _, _, _, _, _, _, _), + PINGROUP(137, _, _, _, _, _, _, _), + PINGROUP(138, _, _, _, _, _, _, _), + PINGROUP(139, _, _, _, _, _, _, _), + PINGROUP(140, _, _, _, _, _, _, _), + PINGROUP(141, _, _, _, _, _, _, _), + PINGROUP(142, _, _, _, _, _, _, _), + PINGROUP(143, _, sdc2, _, _, _, _, _), + PINGROUP(144, _, sdc2, _, _, _, _, _), + PINGROUP(145, _, sdc2, _, _, _, _, _), + PINGROUP(146, _, sdc2, _, _, _, _, _), + PINGROUP(147, _, sdc2, _, _, _, _, _), + PINGROUP(148, _, sdc2, _, _, _, _, _), + PINGROUP(149, _, sdc2, _, _, _, _, _), + PINGROUP(150, _, sdc2, _, _, _, _, _), + PINGROUP(151, _, sdc2, _, _, _, _, _), + PINGROUP(152, _, sdc2, _, _, _, _, _), + PINGROUP(153, _, _, _, _, _, _, _), + PINGROUP(154, _, _, _, _, _, _, _), + PINGROUP(155, _, _, _, _, _, _, _), + PINGROUP(156, _, _, _, _, _, _, _), + PINGROUP(157, _, _, _, _, _, _, _), + PINGROUP(158, _, _, _, _, _, _, _), + PINGROUP(159, sdc1, _, _, _, _, _, _), + PINGROUP(160, sdc1, _, _, _, _, _, _), + PINGROUP(161, sdc1, _, _, _, _, _, _), + PINGROUP(162, sdc1, _, _, _, _, _, _), + PINGROUP(163, sdc1, _, _, _, _, _, _), + PINGROUP(164, sdc1, _, _, _, _, _, _), + PINGROUP(165, sdc1, _, _, _, _, _, _), + PINGROUP(166, sdc1, _, _, _, _, _, _), + PINGROUP(167, sdc1, _, _, _, _, _, _), + PINGROUP(168, sdc1, _, _, _, _, _, _), + PINGROUP(169, hdmi, _, _, _, _, _, _), + PINGROUP(170, hdmi, _, _, _, _, _, _), + PINGROUP(171, hdmi, _, _, _, _, _, _), + PINGROUP(172, hdmi, _, _, _, _, _, _), + + SDC_PINGROUP(sdc4_clk, 0x20a0, -1, 6), + SDC_PINGROUP(sdc4_cmd, 0x20a0, 11, 3), + SDC_PINGROUP(sdc4_data, 0x20a0, 9, 0), + + SDC_PINGROUP(sdc3_clk, 0x20a4, -1, 6), + SDC_PINGROUP(sdc3_cmd, 0x20a4, 11, 3), + SDC_PINGROUP(sdc3_data, 0x20a4, 9, 0), +}; + +#define NUM_GPIO_PINGROUPS 173 + +static const struct msm_pinctrl_soc_data msm8660_pinctrl = { + .pins = msm8660_pins, + .npins = ARRAY_SIZE(msm8660_pins), + .functions = msm8660_functions, + .nfunctions = ARRAY_SIZE(msm8660_functions), + .groups = msm8660_groups, + .ngroups = ARRAY_SIZE(msm8660_groups), + .ngpios = NUM_GPIO_PINGROUPS, +}; + +static int msm8660_pinctrl_probe(struct platform_device *pdev) +{ + return msm_pinctrl_probe(pdev, &msm8660_pinctrl); +} + +static const struct of_device_id msm8660_pinctrl_of_match[] = { + { .compatible = "qcom,msm8660-pinctrl", }, + { }, +}; + +static struct platform_driver msm8660_pinctrl_driver = { + .driver = { + .name = "msm8660-pinctrl", + .of_match_table = msm8660_pinctrl_of_match, + }, + .probe = msm8660_pinctrl_probe, + .remove = msm_pinctrl_remove, +}; + +static int __init msm8660_pinctrl_init(void) +{ + return platform_driver_register(&msm8660_pinctrl_driver); +} +arch_initcall(msm8660_pinctrl_init); + +static void __exit msm8660_pinctrl_exit(void) +{ + platform_driver_unregister(&msm8660_pinctrl_driver); +} +module_exit(msm8660_pinctrl_exit); + +MODULE_AUTHOR("Bjorn Andersson "); +MODULE_DESCRIPTION("Qualcomm MSM8660 pinctrl driver"); +MODULE_LICENSE("GPL v2"); +MODULE_DEVICE_TABLE(of, msm8660_pinctrl_of_match); -- cgit v0.10.2 From 1bb6fad359b147645e47cf826bc20e6b5b4d66b2 Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Fri, 5 Jun 2015 15:52:24 -0700 Subject: pinctrl: dt-binding: Add DT binding documentation for MSM8660 Signed-off-by: Bjorn Andersson Signed-off-by: Linus Walleij diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,msm8660-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/qcom,msm8660-pinctrl.txt new file mode 100644 index 0000000..77aa117 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,msm8660-pinctrl.txt @@ -0,0 +1,90 @@ +Qualcomm MSM8660 TLMM block + +Required properties: +- compatible: "qcom,msm8660-pinctrl" +- reg: Should be the base address and length of the TLMM block. +- interrupts: Should be the parent IRQ of the TLMM block. +- interrupt-controller: Marks the device node as an interrupt controller. +- #interrupt-cells: Should be two. +- gpio-controller: Marks the device node as a GPIO controller. +- #gpio-cells : Should be two. + The first cell is the gpio pin number and the + second cell is used for optional parameters. + +Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for +a general description of GPIO and interrupt bindings. + +Please refer to pinctrl-bindings.txt in this directory for details of the +common pinctrl bindings used by client devices, including the meaning of the +phrase "pin configuration node". + +Qualcomm's pin configuration nodes act as a container for an arbitrary number of +subnodes. Each of these subnodes represents some desired configuration for a +pin, a group, or a list of pins or groups. This configuration can include the +mux function to select on those pin(s)/group(s), and various pin configuration +parameters, such as pull-up, drive strength, etc. + +The name of each subnode is not important; all subnodes should be enumerated +and processed purely based on their content. + +Each subnode only affects those parameters that are explicitly listed. In +other words, a subnode that lists a mux function but no pin configuration +parameters implies no information about any pin configuration parameters. +Similarly, a pin subnode that describes a pullup parameter implies no +information about e.g. the mux function. + + +The following generic properties as defined in pinctrl-bindings.txt are valid +to specify in a pin configuration subnode: + + pins, function, bias-disable, bias-pull-down, bias-pull,up, drive-strength, + output-low, output-high. + +Non-empty subnodes must specify the 'pins' property. + +Valid values for pins are: + gpio0-gpio172, sdc3_clk, sdc3_cmd, sdc3_data sdc4_clk, sdc4_cmd, sdc4_data + +Valid values for function are: + gpio, cam_mclk, dsub, ext_gps, gp_clk_0a, gp_clk_0b, gp_clk_1a, gp_clk_1b, + gp_clk_2a, gp_clk_2b, gp_mn, gsbi1, gsbi1_spi_cs1_n, gsbi1_spi_cs2a_n, + gsbi1_spi_cs2b_n, gsbi1_spi_cs3_n, gsbi2, gsbi2_spi_cs1_n, gsbi2_spi_cs2_n, + gsbi2_spi_cs3_n, gsbi3, gsbi3_spi_cs1_n, gsbi3_spi_cs2_n, gsbi3_spi_cs3_n, + gsbi4, gsbi5, gsbi6, gsbi7, gsbi8, gsbi9, gsbi10, gsbi11, gsbi12, hdmi, i2s, + lcdc, mdp_vsync, mi2s, pcm, ps_hold, sdc1, sdc2, sdc5, tsif1, tsif2, usb_fs1, + usb_fs1_oe_n, usb_fs2, usb_fs2_oe_n, vfe, vsens_alarm, + +Example: + + msmgpio: pinctrl@800000 { + compatible = "qcom,msm8660-pinctrl"; + reg = <0x800000 0x4000>; + + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <0 16 0x4>; + + pinctrl-names = "default"; + pinctrl-0 = <&gsbi12_uart>; + + gsbi12_uart: gsbi12-uart { + mux { + pins = "gpio117", "gpio118"; + function = "gsbi12"; + }; + + tx { + pins = "gpio118"; + drive-strength = <8>; + bias-disable; + }; + + rx { + pins = "gpio117"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; -- cgit v0.10.2 From 9d7ebbbf2264c4ad3c8d50fcb84952126184a7ad Mon Sep 17 00:00:00 2001 From: Ludovic Desroches Date: Mon, 8 Jun 2015 17:16:37 +0200 Subject: pinctrl: don't print unavailable function groups There is no reason to try to print groups associated to a function if get_function_groups returns an error. Moreover, it can lead to a NULL pointer dereference error. Signed-off-by: Ludovic Desroches Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/pinmux.c b/drivers/pinctrl/pinmux.c index 77f82b2..e7ae890 100644 --- a/drivers/pinctrl/pinmux.c +++ b/drivers/pinctrl/pinmux.c @@ -557,9 +557,12 @@ static int pinmux_functions_show(struct seq_file *s, void *what) ret = pmxops->get_function_groups(pctldev, func_selector, &groups, &num_groups); - if (ret) + if (ret) { seq_printf(s, "function %s: COULD NOT GET GROUPS\n", func); + func_selector++; + continue; + } seq_printf(s, "function: %s, groups = [ ", func); for (i = 0; i < num_groups; i++) -- cgit v0.10.2 From 331642fbf24a1c16b2669ca0a6479b5fcd6dd5b2 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 9 Jun 2015 18:46:53 +0200 Subject: pinctrl: mvebu: armada-38x: fix PCIe functions A new revision of the Marvell Armada 38x hardware datasheet unveiled that the definition of some of the PCIe functions were not correct. This commit fixes the pinctrl driver accordingly. Some PCIe functions simply do not exist, some of the PCIe functions in fact were corresponding to other functions, and some PCIe functions have been added. Note: the seemingly unrelated removal of spi(cs2) on MPP47 is related: this function is in fact implemented on MPP43, instead of a PCIe function. Signed-off-by: Thomas Petazzoni Cc: # v3.15+ Fixes: ca6d9a084b56f ("pinctrl: mvebu: add pin-muxing driver for the Marvell Armada 380/385") Signed-off-by: Linus Walleij diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-38x-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-38x-pinctrl.txt index b17c968..4ac138a 100644 --- a/Documentation/devicetree/bindings/pinctrl/marvell,armada-38x-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-38x-pinctrl.txt @@ -27,15 +27,15 @@ mpp8 8 gpio, ge0(txd1), dev(ad10) mpp9 9 gpio, ge0(txd2), dev(ad11) mpp10 10 gpio, ge0(txd3), dev(ad12) mpp11 11 gpio, ge0(txctl), dev(ad13) -mpp12 12 gpio, ge0(rxd0), pcie0(rstout), pcie1(rstout) [1], spi0(cs1), dev(ad14) -mpp13 13 gpio, ge0(rxd1), pcie0(clkreq), pcie1(clkreq) [1], spi0(cs2), dev(ad15) -mpp14 14 gpio, ge0(rxd2), ptp(clk), m(vtt_ctrl), spi0(cs3), dev(wen1) -mpp15 15 gpio, ge0(rxd3), ge(mdc slave), pcie0(rstout), spi0(mosi), pcie1(rstout) [1] -mpp16 16 gpio, ge0(rxctl), ge(mdio slave), m(decc_err), spi0(miso), pcie0(clkreq) +mpp12 12 gpio, ge0(rxd0), pcie0(rstout), spi0(cs1), dev(ad14), pcie3(clkreq) +mpp13 13 gpio, ge0(rxd1), pcie0(clkreq), pcie1(clkreq) [1], spi0(cs2), dev(ad15), pcie2(clkreq) +mpp14 14 gpio, ge0(rxd2), ptp(clk), m(vtt_ctrl), spi0(cs3), dev(wen1), pcie3(clkreq) +mpp15 15 gpio, ge0(rxd3), ge(mdc slave), pcie0(rstout), spi0(mosi) +mpp16 16 gpio, ge0(rxctl), ge(mdio slave), m(decc_err), spi0(miso), pcie0(clkreq), pcie1(clkreq) [1] mpp17 17 gpio, ge0(rxclk), ptp(clk), ua1(rxd), spi0(sck), sata1(prsnt) -mpp18 18 gpio, ge0(rxerr), ptp(trig_gen), ua1(txd), spi0(cs0), pcie1(rstout) [1] -mpp19 19 gpio, ge0(col), ptp(event_req), pcie0(clkreq), sata1(prsnt), ua0(cts) -mpp20 20 gpio, ge0(txclk), ptp(clk), pcie1(rstout) [1], sata0(prsnt), ua0(rts) +mpp18 18 gpio, ge0(rxerr), ptp(trig_gen), ua1(txd), spi0(cs0) +mpp19 19 gpio, ge0(col), ptp(event_req), ge0(txerr), sata1(prsnt), ua0(cts) +mpp20 20 gpio, ge0(txclk), ptp(clk), sata0(prsnt), ua0(rts) mpp21 21 gpio, spi0(cs1), ge1(rxd0), sata0(prsnt), sd0(cmd), dev(bootcs) mpp22 22 gpio, spi0(mosi), dev(ad0) mpp23 23 gpio, spi0(sck), dev(ad2) @@ -58,23 +58,23 @@ mpp39 39 gpio, i2c1(sck), ge1(rxd2), ua0(cts), sd0(d1), dev(a2) mpp40 40 gpio, i2c1(sda), ge1(rxd3), ua0(rts), sd0(d2), dev(ad6) mpp41 41 gpio, ua1(rxd), ge1(rxctl), ua0(cts), spi1(cs3), dev(burst/last) mpp42 42 gpio, ua1(txd), ua0(rts), dev(ad7) -mpp43 43 gpio, pcie0(clkreq), m(vtt_ctrl), m(decc_err), pcie0(rstout), dev(clkout) -mpp44 44 gpio, sata0(prsnt), sata1(prsnt), sata2(prsnt) [2], sata3(prsnt) [3], pcie0(rstout) -mpp45 45 gpio, ref(clk_out0), pcie0(rstout), pcie1(rstout) [1], pcie2(rstout), pcie3(rstout) -mpp46 46 gpio, ref(clk_out1), pcie0(rstout), pcie1(rstout) [1], pcie2(rstout), pcie3(rstout) -mpp47 47 gpio, sata0(prsnt), sata1(prsnt), sata2(prsnt) [2], spi1(cs2), sata3(prsnt) [2] -mpp48 48 gpio, sata0(prsnt), m(vtt_ctrl), tdm2c(pclk), audio(mclk), sd0(d4) -mpp49 49 gpio, sata2(prsnt) [2], sata3(prsnt) [2], tdm2c(fsync), audio(lrclk), sd0(d5) -mpp50 50 gpio, pcie0(rstout), pcie1(rstout) [1], tdm2c(drx), audio(extclk), sd0(cmd) +mpp43 43 gpio, pcie0(clkreq), m(vtt_ctrl), m(decc_err), spi1(cs2), dev(clkout) +mpp44 44 gpio, sata0(prsnt), sata1(prsnt), sata2(prsnt) [2], sata3(prsnt) [3] +mpp45 45 gpio, ref(clk_out0), pcie0(rstout) +mpp46 46 gpio, ref(clk_out1), pcie0(rstout) +mpp47 47 gpio, sata0(prsnt), sata1(prsnt), sata2(prsnt) [2], sata3(prsnt) [2] +mpp48 48 gpio, sata0(prsnt), m(vtt_ctrl), tdm2c(pclk), audio(mclk), sd0(d4), pcie0(clkreq) +mpp49 49 gpio, sata2(prsnt) [2], sata3(prsnt) [2], tdm2c(fsync), audio(lrclk), sd0(d5), pcie1(clkreq) +mpp50 50 gpio, pcie0(rstout), tdm2c(drx), audio(extclk), sd0(cmd) mpp51 51 gpio, tdm2c(dtx), audio(sdo), m(decc_err) -mpp52 52 gpio, pcie0(rstout), pcie1(rstout) [1], tdm2c(intn), audio(sdi), sd0(d6) +mpp52 52 gpio, pcie0(rstout), tdm2c(intn), audio(sdi), sd0(d6) mpp53 53 gpio, sata1(prsnt), sata0(prsnt), tdm2c(rstn), audio(bclk), sd0(d7) -mpp54 54 gpio, sata0(prsnt), sata1(prsnt), pcie0(rstout), pcie1(rstout) [1], sd0(d3) +mpp54 54 gpio, sata0(prsnt), sata1(prsnt), pcie0(rstout), ge0(txerr), sd0(d3) mpp55 55 gpio, ua1(cts), ge(mdio), pcie1(clkreq) [1], spi1(cs1), sd0(d0) mpp56 56 gpio, ua1(rts), ge(mdc), m(decc_err), spi1(mosi) mpp57 57 gpio, spi1(sck), sd0(clk) mpp58 58 gpio, pcie1(clkreq) [1], i2c1(sck), pcie2(clkreq), spi1(miso), sd0(d1) -mpp59 59 gpio, pcie0(rstout), i2c1(sda), pcie1(rstout) [1], spi1(cs0), sd0(d2) +mpp59 59 gpio, pcie0(rstout), i2c1(sda), spi1(cs0), sd0(d2) [1]: only available on 88F6820 and 88F6828 [2]: only available on 88F6828 diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-38x.c b/drivers/pinctrl/mvebu/pinctrl-armada-38x.c index 83bbcc7..11656c7 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-38x.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-38x.c @@ -94,37 +94,39 @@ static struct mvebu_mpp_mode armada_38x_mpp_modes[] = { MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), MPP_VAR_FUNCTION(1, "ge0", "rxd0", V_88F6810_PLUS), MPP_VAR_FUNCTION(2, "pcie0", "rstout", V_88F6810_PLUS), - MPP_VAR_FUNCTION(3, "pcie1", "rstout", V_88F6820_PLUS), MPP_VAR_FUNCTION(4, "spi0", "cs1", V_88F6810_PLUS), - MPP_VAR_FUNCTION(5, "dev", "ad14", V_88F6810_PLUS)), + MPP_VAR_FUNCTION(5, "dev", "ad14", V_88F6810_PLUS), + MPP_VAR_FUNCTION(6, "pcie3", "clkreq", V_88F6810_PLUS)), MPP_MODE(13, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), MPP_VAR_FUNCTION(1, "ge0", "rxd1", V_88F6810_PLUS), MPP_VAR_FUNCTION(2, "pcie0", "clkreq", V_88F6810_PLUS), MPP_VAR_FUNCTION(3, "pcie1", "clkreq", V_88F6820_PLUS), MPP_VAR_FUNCTION(4, "spi0", "cs2", V_88F6810_PLUS), - MPP_VAR_FUNCTION(5, "dev", "ad15", V_88F6810_PLUS)), + MPP_VAR_FUNCTION(5, "dev", "ad15", V_88F6810_PLUS), + MPP_VAR_FUNCTION(6, "pcie2", "clkreq", V_88F6810_PLUS)), MPP_MODE(14, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), MPP_VAR_FUNCTION(1, "ge0", "rxd2", V_88F6810_PLUS), MPP_VAR_FUNCTION(2, "ptp", "clk", V_88F6810_PLUS), MPP_VAR_FUNCTION(3, "m", "vtt_ctrl", V_88F6810_PLUS), MPP_VAR_FUNCTION(4, "spi0", "cs3", V_88F6810_PLUS), - MPP_VAR_FUNCTION(5, "dev", "wen1", V_88F6810_PLUS)), + MPP_VAR_FUNCTION(5, "dev", "wen1", V_88F6810_PLUS), + MPP_VAR_FUNCTION(6, "pcie3", "clkreq", V_88F6810_PLUS)), MPP_MODE(15, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), MPP_VAR_FUNCTION(1, "ge0", "rxd3", V_88F6810_PLUS), MPP_VAR_FUNCTION(2, "ge", "mdc slave", V_88F6810_PLUS), MPP_VAR_FUNCTION(3, "pcie0", "rstout", V_88F6810_PLUS), - MPP_VAR_FUNCTION(4, "spi0", "mosi", V_88F6810_PLUS), - MPP_VAR_FUNCTION(5, "pcie1", "rstout", V_88F6820_PLUS)), + MPP_VAR_FUNCTION(4, "spi0", "mosi", V_88F6810_PLUS)), MPP_MODE(16, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), MPP_VAR_FUNCTION(1, "ge0", "rxctl", V_88F6810_PLUS), MPP_VAR_FUNCTION(2, "ge", "mdio slave", V_88F6810_PLUS), MPP_VAR_FUNCTION(3, "m", "decc_err", V_88F6810_PLUS), MPP_VAR_FUNCTION(4, "spi0", "miso", V_88F6810_PLUS), - MPP_VAR_FUNCTION(5, "pcie0", "clkreq", V_88F6810_PLUS)), + MPP_VAR_FUNCTION(5, "pcie0", "clkreq", V_88F6810_PLUS), + MPP_VAR_FUNCTION(6, "pcie1", "clkreq", V_88F6820_PLUS)), MPP_MODE(17, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), MPP_VAR_FUNCTION(1, "ge0", "rxclk", V_88F6810_PLUS), @@ -137,13 +139,12 @@ static struct mvebu_mpp_mode armada_38x_mpp_modes[] = { MPP_VAR_FUNCTION(1, "ge0", "rxerr", V_88F6810_PLUS), MPP_VAR_FUNCTION(2, "ptp", "trig_gen", V_88F6810_PLUS), MPP_VAR_FUNCTION(3, "ua1", "txd", V_88F6810_PLUS), - MPP_VAR_FUNCTION(4, "spi0", "cs0", V_88F6810_PLUS), - MPP_VAR_FUNCTION(5, "pcie1", "rstout", V_88F6820_PLUS)), + MPP_VAR_FUNCTION(4, "spi0", "cs0", V_88F6810_PLUS)), MPP_MODE(19, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), MPP_VAR_FUNCTION(1, "ge0", "col", V_88F6810_PLUS), MPP_VAR_FUNCTION(2, "ptp", "event_req", V_88F6810_PLUS), - MPP_VAR_FUNCTION(3, "pcie0", "clkreq", V_88F6810_PLUS), + MPP_VAR_FUNCTION(3, "ge0", "txerr", V_88F6810_PLUS), MPP_VAR_FUNCTION(4, "sata1", "prsnt", V_88F6810_PLUS), MPP_VAR_FUNCTION(5, "ua0", "cts", V_88F6810_PLUS), MPP_VAR_FUNCTION(6, "ua1", "rxd", V_88F6810_PLUS)), @@ -151,7 +152,6 @@ static struct mvebu_mpp_mode armada_38x_mpp_modes[] = { MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), MPP_VAR_FUNCTION(1, "ge0", "txclk", V_88F6810_PLUS), MPP_VAR_FUNCTION(2, "ptp", "clk", V_88F6810_PLUS), - MPP_VAR_FUNCTION(3, "pcie1", "rstout", V_88F6820_PLUS), MPP_VAR_FUNCTION(4, "sata0", "prsnt", V_88F6810_PLUS), MPP_VAR_FUNCTION(5, "ua0", "rts", V_88F6810_PLUS), MPP_VAR_FUNCTION(6, "ua1", "txd", V_88F6810_PLUS)), @@ -277,35 +277,27 @@ static struct mvebu_mpp_mode armada_38x_mpp_modes[] = { MPP_VAR_FUNCTION(1, "pcie0", "clkreq", V_88F6810_PLUS), MPP_VAR_FUNCTION(2, "m", "vtt_ctrl", V_88F6810_PLUS), MPP_VAR_FUNCTION(3, "m", "decc_err", V_88F6810_PLUS), - MPP_VAR_FUNCTION(4, "pcie0", "rstout", V_88F6810_PLUS), + MPP_VAR_FUNCTION(4, "spi1", "cs2", V_88F6810_PLUS), MPP_VAR_FUNCTION(5, "dev", "clkout", V_88F6810_PLUS)), MPP_MODE(44, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), MPP_VAR_FUNCTION(1, "sata0", "prsnt", V_88F6810_PLUS), MPP_VAR_FUNCTION(2, "sata1", "prsnt", V_88F6810_PLUS), MPP_VAR_FUNCTION(3, "sata2", "prsnt", V_88F6828), - MPP_VAR_FUNCTION(4, "sata3", "prsnt", V_88F6828), - MPP_VAR_FUNCTION(5, "pcie0", "rstout", V_88F6810_PLUS)), + MPP_VAR_FUNCTION(4, "sata3", "prsnt", V_88F6828)), MPP_MODE(45, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), MPP_VAR_FUNCTION(1, "ref", "clk_out0", V_88F6810_PLUS), - MPP_VAR_FUNCTION(2, "pcie0", "rstout", V_88F6810_PLUS), - MPP_VAR_FUNCTION(3, "pcie1", "rstout", V_88F6820_PLUS), - MPP_VAR_FUNCTION(4, "pcie2", "rstout", V_88F6810_PLUS), - MPP_VAR_FUNCTION(5, "pcie3", "rstout", V_88F6810_PLUS)), + MPP_VAR_FUNCTION(2, "pcie0", "rstout", V_88F6810_PLUS)), MPP_MODE(46, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), MPP_VAR_FUNCTION(1, "ref", "clk_out1", V_88F6810_PLUS), - MPP_VAR_FUNCTION(2, "pcie0", "rstout", V_88F6810_PLUS), - MPP_VAR_FUNCTION(3, "pcie1", "rstout", V_88F6820_PLUS), - MPP_VAR_FUNCTION(4, "pcie2", "rstout", V_88F6810_PLUS), - MPP_VAR_FUNCTION(5, "pcie3", "rstout", V_88F6810_PLUS)), + MPP_VAR_FUNCTION(2, "pcie0", "rstout", V_88F6810_PLUS)), MPP_MODE(47, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), MPP_VAR_FUNCTION(1, "sata0", "prsnt", V_88F6810_PLUS), MPP_VAR_FUNCTION(2, "sata1", "prsnt", V_88F6810_PLUS), MPP_VAR_FUNCTION(3, "sata2", "prsnt", V_88F6828), - MPP_VAR_FUNCTION(4, "spi1", "cs2", V_88F6810_PLUS), MPP_VAR_FUNCTION(5, "sata3", "prsnt", V_88F6828)), MPP_MODE(48, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), @@ -313,18 +305,19 @@ static struct mvebu_mpp_mode armada_38x_mpp_modes[] = { MPP_VAR_FUNCTION(2, "m", "vtt_ctrl", V_88F6810_PLUS), MPP_VAR_FUNCTION(3, "tdm2c", "pclk", V_88F6810_PLUS), MPP_VAR_FUNCTION(4, "audio", "mclk", V_88F6810_PLUS), - MPP_VAR_FUNCTION(5, "sd0", "d4", V_88F6810_PLUS)), + MPP_VAR_FUNCTION(5, "sd0", "d4", V_88F6810_PLUS), + MPP_VAR_FUNCTION(6, "pcie0", "clkreq", V_88F6810_PLUS)), MPP_MODE(49, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), MPP_VAR_FUNCTION(1, "sata2", "prsnt", V_88F6828), MPP_VAR_FUNCTION(2, "sata3", "prsnt", V_88F6828), MPP_VAR_FUNCTION(3, "tdm2c", "fsync", V_88F6810_PLUS), MPP_VAR_FUNCTION(4, "audio", "lrclk", V_88F6810_PLUS), - MPP_VAR_FUNCTION(5, "sd0", "d5", V_88F6810_PLUS)), + MPP_VAR_FUNCTION(5, "sd0", "d5", V_88F6810_PLUS), + MPP_VAR_FUNCTION(6, "pcie1", "clkreq", V_88F6820_PLUS)), MPP_MODE(50, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), MPP_VAR_FUNCTION(1, "pcie0", "rstout", V_88F6810_PLUS), - MPP_VAR_FUNCTION(2, "pcie1", "rstout", V_88F6820_PLUS), MPP_VAR_FUNCTION(3, "tdm2c", "drx", V_88F6810_PLUS), MPP_VAR_FUNCTION(4, "audio", "extclk", V_88F6810_PLUS), MPP_VAR_FUNCTION(5, "sd0", "cmd", V_88F6810_PLUS)), @@ -336,7 +329,6 @@ static struct mvebu_mpp_mode armada_38x_mpp_modes[] = { MPP_MODE(52, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), MPP_VAR_FUNCTION(1, "pcie0", "rstout", V_88F6810_PLUS), - MPP_VAR_FUNCTION(2, "pcie1", "rstout", V_88F6820_PLUS), MPP_VAR_FUNCTION(3, "tdm2c", "intn", V_88F6810_PLUS), MPP_VAR_FUNCTION(4, "audio", "sdi", V_88F6810_PLUS), MPP_VAR_FUNCTION(5, "sd0", "d6", V_88F6810_PLUS)), @@ -352,7 +344,7 @@ static struct mvebu_mpp_mode armada_38x_mpp_modes[] = { MPP_VAR_FUNCTION(1, "sata0", "prsnt", V_88F6810_PLUS), MPP_VAR_FUNCTION(2, "sata1", "prsnt", V_88F6810_PLUS), MPP_VAR_FUNCTION(3, "pcie0", "rstout", V_88F6810_PLUS), - MPP_VAR_FUNCTION(4, "pcie1", "rstout", V_88F6820_PLUS), + MPP_VAR_FUNCTION(4, "ge0", "txerr", V_88F6810_PLUS), MPP_VAR_FUNCTION(5, "sd0", "d3", V_88F6810_PLUS)), MPP_MODE(55, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), @@ -382,7 +374,6 @@ static struct mvebu_mpp_mode armada_38x_mpp_modes[] = { MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), MPP_VAR_FUNCTION(1, "pcie0", "rstout", V_88F6810_PLUS), MPP_VAR_FUNCTION(2, "i2c1", "sda", V_88F6810_PLUS), - MPP_VAR_FUNCTION(3, "pcie1", "rstout", V_88F6820_PLUS), MPP_VAR_FUNCTION(4, "spi1", "cs0", V_88F6810_PLUS), MPP_VAR_FUNCTION(5, "sd0", "d2", V_88F6810_PLUS)), }; -- cgit v0.10.2 From 438881dfddb9107ef0eb30b49368e91e092f0b3e Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 9 Jun 2015 18:46:54 +0200 Subject: pinctrl: mvebu: armada-370: fix spi0 pin description Due to a mistake, the CS0 and CS1 SPI0 functions were incorrectly named "spi0-1" instead of just "spi0". This commit fixes that. This DT binding change does not affect any of the in-tree users. Signed-off-by: Thomas Petazzoni Cc: # v3.7+ Fixes: 5f597bb2be57 ("pinctrl: mvebu: add pinctrl driver for Armada 370") Signed-off-by: Linus Walleij diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt index adda2a8..e357b02 100644 --- a/Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt @@ -92,5 +92,5 @@ mpp61 61 gpo, dev(wen1), uart1(txd), audio(rclk) mpp62 62 gpio, dev(a2), uart1(cts), tdm(drx), pcie(clkreq0), audio(mclk), uart0(cts) mpp63 63 gpo, spi0(sck), tclk -mpp64 64 gpio, spi0(miso), spi0-1(cs1) -mpp65 65 gpio, spi0(mosi), spi0-1(cs2) +mpp64 64 gpio, spi0(miso), spi0(cs1) +mpp65 65 gpio, spi0(mosi), spi0(cs2) diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-370.c b/drivers/pinctrl/mvebu/pinctrl-armada-370.c index 42f930f..8516cad 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-370.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-370.c @@ -370,11 +370,11 @@ static struct mvebu_mpp_mode mv88f6710_mpp_modes[] = { MPP_MODE(64, MPP_FUNCTION(0x0, "gpio", NULL), MPP_FUNCTION(0x1, "spi0", "miso"), - MPP_FUNCTION(0x2, "spi0-1", "cs1")), + MPP_FUNCTION(0x2, "spi0", "cs1")), MPP_MODE(65, MPP_FUNCTION(0x0, "gpio", NULL), MPP_FUNCTION(0x1, "spi0", "mosi"), - MPP_FUNCTION(0x2, "spi0-1", "cs2")), + MPP_FUNCTION(0x2, "spi0", "cs2")), }; static struct mvebu_pinctrl_soc_info armada_370_pinctrl_info; -- cgit v0.10.2 From e5447d26092c72ef3346615ee558c9112ef8063f Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 9 Jun 2015 18:46:55 +0200 Subject: pinctrl: mvebu: armada-375: remove non-existing NAND re/we pins After updating to a more recent version of the Armada 375, we realized that some of the pins documented as having a NAND-related functionality in fact did not have such functionality. This commit updates the pinctrl driver accordingly. Signed-off-by: Thomas Petazzoni Cc: # v3.15+ Fixes: ce3ed59dcddd ("pinctrl: mvebu: add pin-muxing driver for the Marvell Armada 375") Signed-off-by: Linus Walleij diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-375-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-375-pinctrl.txt index 7de0cda..bedbe42 100644 --- a/Documentation/devicetree/bindings/pinctrl/marvell,armada-375-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-375-pinctrl.txt @@ -22,8 +22,8 @@ mpp5 5 gpio, dev(ad7), spi0(cs2), spi1(cs2) mpp6 6 gpio, dev(ad0), led(p1), audio(rclk) mpp7 7 gpio, dev(ad1), ptp(clk), led(p2), audio(extclk) mpp8 8 gpio, dev (bootcs), spi0(cs0), spi1(cs0) -mpp9 9 gpio, nf(wen), spi0(sck), spi1(sck) -mpp10 10 gpio, nf(ren), dram(vttctrl), led(c1) +mpp9 9 gpio, spi0(sck), spi1(sck), nand(we) +mpp10 10 gpio, dram(vttctrl), led(c1), nand(re) mpp11 11 gpio, dev(a0), led(c2), audio(sdo) mpp12 12 gpio, dev(a1), audio(bclk) mpp13 13 gpio, dev(readyn), pcie0(rstoutn), pcie1(rstoutn) diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-375.c b/drivers/pinctrl/mvebu/pinctrl-armada-375.c index ca1e757..e740a42 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-375.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-375.c @@ -98,13 +98,11 @@ static struct mvebu_mpp_mode mv88f6720_mpp_modes[] = { MPP_FUNCTION(0x5, "nand", "ce")), MPP_MODE(9, MPP_FUNCTION(0x0, "gpio", NULL), - MPP_FUNCTION(0x1, "nf", "wen"), MPP_FUNCTION(0x2, "spi0", "sck"), MPP_FUNCTION(0x3, "spi1", "sck"), MPP_FUNCTION(0x5, "nand", "we")), MPP_MODE(10, MPP_FUNCTION(0x0, "gpio", NULL), - MPP_FUNCTION(0x1, "nf", "ren"), MPP_FUNCTION(0x2, "dram", "vttctrl"), MPP_FUNCTION(0x3, "led", "c1"), MPP_FUNCTION(0x5, "nand", "re"), -- cgit v0.10.2 From bc99357f3690c11817756adfee0ece811a3db2e7 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 9 Jun 2015 18:46:56 +0200 Subject: pinctrl: mvebu: armada-xp: remove non-existing NAND pins After updating to a more recent version of the Armada XP datasheet, we realized that some of the pins documented as having a NAND-related functionality in fact did not have such functionality. This commit updates the pinctrl driver accordingly. Signed-off-by: Thomas Petazzoni Cc: # v3.7+ Fixes: 463e270f766a ("pinctrl: mvebu: add pinctrl driver for Armada XP") Signed-off-by: Linus Walleij diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt index 373dbccd..974168d 100644 --- a/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt @@ -42,8 +42,8 @@ mpp20 20 gpio, ge0(rxd4), ge1(rxd2), lcd(d20), ptp(clk) mpp21 21 gpio, ge0(rxd5), ge1(rxd3), lcd(d21), mem(bat) mpp22 22 gpio, ge0(rxd6), ge1(rxctl), lcd(d22), sata0(prsnt) mpp23 23 gpio, ge0(rxd7), ge1(rxclk), lcd(d23), sata1(prsnt) -mpp24 24 gpio, lcd(hsync), sata1(prsnt), nf(bootcs-re), tdm(rst) -mpp25 25 gpio, lcd(vsync), sata0(prsnt), nf(bootcs-we), tdm(pclk) +mpp24 24 gpio, lcd(hsync), sata1(prsnt), tdm(rst) +mpp25 25 gpio, lcd(vsync), sata0(prsnt), tdm(pclk) mpp26 26 gpio, lcd(clk), tdm(fsync), vdd(cpu1-pd) mpp27 27 gpio, lcd(e), tdm(dtx), ptp(trig) mpp28 28 gpio, lcd(pwm), tdm(drx), ptp(evreq) diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-xp.c b/drivers/pinctrl/mvebu/pinctrl-armada-xp.c index 578db9f..7310c40 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-xp.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-xp.c @@ -172,13 +172,11 @@ static struct mvebu_mpp_mode armada_xp_mpp_modes[] = { MPP_MODE(24, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), MPP_VAR_FUNCTION(0x1, "sata1", "prsnt", V_MV78230_PLUS), - MPP_VAR_FUNCTION(0x2, "nf", "bootcs-re", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x3, "tdm", "rst", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x4, "lcd", "hsync", V_MV78230_PLUS)), MPP_MODE(25, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), MPP_VAR_FUNCTION(0x1, "sata0", "prsnt", V_MV78230_PLUS), - MPP_VAR_FUNCTION(0x2, "nf", "bootcs-we", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x3, "tdm", "pclk", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x4, "lcd", "vsync", V_MV78230_PLUS)), MPP_MODE(26, -- cgit v0.10.2 From 80b3d04feab5e69d51cb2375eb989a7165e43e3b Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 9 Jun 2015 18:46:57 +0200 Subject: pinctrl: mvebu: armada-xp: remove non-existing VDD cpu_pd functions The latest version of the Armada XP datasheet no longer documents the VDD cpu_pd functions, which might indicate they are not working and/or not supported. This commit ensures the pinctrl driver matches the datasheet. Signed-off-by: Thomas Petazzoni Cc: # v3.7+ Fixes: 463e270f766a ("pinctrl: mvebu: add pinctrl driver for Armada XP") Signed-off-by: Linus Walleij diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt index 974168d..b347b85 100644 --- a/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt @@ -44,13 +44,13 @@ mpp22 22 gpio, ge0(rxd6), ge1(rxctl), lcd(d22), sata0(prsnt) mpp23 23 gpio, ge0(rxd7), ge1(rxclk), lcd(d23), sata1(prsnt) mpp24 24 gpio, lcd(hsync), sata1(prsnt), tdm(rst) mpp25 25 gpio, lcd(vsync), sata0(prsnt), tdm(pclk) -mpp26 26 gpio, lcd(clk), tdm(fsync), vdd(cpu1-pd) +mpp26 26 gpio, lcd(clk), tdm(fsync) mpp27 27 gpio, lcd(e), tdm(dtx), ptp(trig) mpp28 28 gpio, lcd(pwm), tdm(drx), ptp(evreq) -mpp29 29 gpio, lcd(ref-clk), tdm(int0), ptp(clk), vdd(cpu0-pd) +mpp29 29 gpio, lcd(ref-clk), tdm(int0), ptp(clk) mpp30 30 gpio, tdm(int1), sd0(clk) -mpp31 31 gpio, tdm(int2), sd0(cmd), vdd(cpu0-pd) -mpp32 32 gpio, tdm(int3), sd0(d0), vdd(cpu1-pd) +mpp31 31 gpio, tdm(int2), sd0(cmd) +mpp32 32 gpio, tdm(int3), sd0(d0) mpp33 33 gpio, tdm(int4), sd0(d1), mem(bat) mpp34 34 gpio, tdm(int5), sd0(d2), sata0(prsnt) mpp35 35 gpio, tdm(int6), sd0(d3), sata1(prsnt) @@ -58,14 +58,11 @@ mpp36 36 gpio, spi(mosi) mpp37 37 gpio, spi(miso) mpp38 38 gpio, spi(sck) mpp39 39 gpio, spi(cs0) -mpp40 40 gpio, spi(cs1), uart2(cts), lcd(vga-hsync), vdd(cpu1-pd), - pcie(clkreq0) +mpp40 40 gpio, spi(cs1), uart2(cts), lcd(vga-hsync), pcie(clkreq0) mpp41 41 gpio, spi(cs2), uart2(rts), lcd(vga-vsync), sata1(prsnt), pcie(clkreq1) -mpp42 42 gpio, uart2(rxd), uart0(cts), tdm(int7), tdm-1(timer), - vdd(cpu0-pd) -mpp43 43 gpio, uart2(txd), uart0(rts), spi(cs3), pcie(rstout), - vdd(cpu2-3-pd){1} +mpp42 42 gpio, uart2(rxd), uart0(cts), tdm(int7), tdm-1(timer) +mpp43 43 gpio, uart2(txd), uart0(rts), spi(cs3), pcie(rstout) mpp44 44 gpio, uart2(cts), uart3(rxd), spi(cs4), pcie(clkreq2), mem(bat) mpp45 45 gpio, uart2(rts), uart3(txd), spi(cs5), sata1(prsnt) @@ -84,9 +81,9 @@ mpp51 51 gpio, dev(ad16) mpp52 52 gpio, dev(ad17) mpp53 53 gpio, dev(ad18) mpp54 54 gpio, dev(ad19) -mpp55 55 gpio, dev(ad20), vdd(cpu0-pd) -mpp56 56 gpio, dev(ad21), vdd(cpu1-pd) -mpp57 57 gpio, dev(ad22), vdd(cpu2-3-pd){1} +mpp55 55 gpio, dev(ad20) +mpp56 56 gpio, dev(ad21) +mpp57 57 gpio, dev(ad22) mpp58 58 gpio, dev(ad23) mpp59 59 gpio, dev(ad24) mpp60 60 gpio, dev(ad25) @@ -96,6 +93,3 @@ mpp63 63 gpio, dev(ad28) mpp64 64 gpio, dev(ad29) mpp65 65 gpio, dev(ad30) mpp66 66 gpio, dev(ad31) - -Notes: -* {1} vdd(cpu2-3-pd) only available on mv78460. diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-xp.c b/drivers/pinctrl/mvebu/pinctrl-armada-xp.c index 7310c40..0301bd2 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-xp.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-xp.c @@ -14,10 +14,7 @@ * available: mv78230, mv78260 and mv78460. From a pin muxing * perspective, the mv78230 has 49 MPP pins. The mv78260 and mv78460 * both have 67 MPP pins (more GPIOs and address lines for the memory - * bus mainly). The only difference between the mv78260 and the - * mv78460 in terms of pin muxing is the addition of two functions on - * pins 43 and 56 to access the VDD of the CPU2 and 3 (mv78260 has two - * cores, mv78460 has four cores). + * bus mainly). */ #include @@ -182,8 +179,7 @@ static struct mvebu_mpp_mode armada_xp_mpp_modes[] = { MPP_MODE(26, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), MPP_VAR_FUNCTION(0x3, "tdm", "fsync", V_MV78230_PLUS), - MPP_VAR_FUNCTION(0x4, "lcd", "clk", V_MV78230_PLUS), - MPP_VAR_FUNCTION(0x5, "vdd", "cpu1-pd", V_MV78230_PLUS)), + MPP_VAR_FUNCTION(0x4, "lcd", "clk", V_MV78230_PLUS)), MPP_MODE(27, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), MPP_VAR_FUNCTION(0x1, "ptp", "trig", V_MV78230_PLUS), @@ -198,8 +194,7 @@ static struct mvebu_mpp_mode armada_xp_mpp_modes[] = { MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), MPP_VAR_FUNCTION(0x1, "ptp", "clk", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x3, "tdm", "int0", V_MV78230_PLUS), - MPP_VAR_FUNCTION(0x4, "lcd", "ref-clk", V_MV78230_PLUS), - MPP_VAR_FUNCTION(0x5, "vdd", "cpu0-pd", V_MV78230_PLUS)), + MPP_VAR_FUNCTION(0x4, "lcd", "ref-clk", V_MV78230_PLUS)), MPP_MODE(30, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), MPP_VAR_FUNCTION(0x1, "sd0", "clk", V_MV78230_PLUS), @@ -207,13 +202,11 @@ static struct mvebu_mpp_mode armada_xp_mpp_modes[] = { MPP_MODE(31, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), MPP_VAR_FUNCTION(0x1, "sd0", "cmd", V_MV78230_PLUS), - MPP_VAR_FUNCTION(0x3, "tdm", "int2", V_MV78230_PLUS), - MPP_VAR_FUNCTION(0x5, "vdd", "cpu0-pd", V_MV78230_PLUS)), + MPP_VAR_FUNCTION(0x3, "tdm", "int2", V_MV78230_PLUS)), MPP_MODE(32, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), MPP_VAR_FUNCTION(0x1, "sd0", "d0", V_MV78230_PLUS), - MPP_VAR_FUNCTION(0x3, "tdm", "int3", V_MV78230_PLUS), - MPP_VAR_FUNCTION(0x5, "vdd", "cpu1-pd", V_MV78230_PLUS)), + MPP_VAR_FUNCTION(0x3, "tdm", "int3", V_MV78230_PLUS)), MPP_MODE(33, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), MPP_VAR_FUNCTION(0x1, "sd0", "d1", V_MV78230_PLUS), @@ -245,7 +238,6 @@ static struct mvebu_mpp_mode armada_xp_mpp_modes[] = { MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), MPP_VAR_FUNCTION(0x1, "spi", "cs1", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x2, "uart2", "cts", V_MV78230_PLUS), - MPP_VAR_FUNCTION(0x3, "vdd", "cpu1-pd", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x4, "lcd", "vga-hsync", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x5, "pcie", "clkreq0", V_MV78230_PLUS)), MPP_MODE(41, @@ -260,15 +252,13 @@ static struct mvebu_mpp_mode armada_xp_mpp_modes[] = { MPP_VAR_FUNCTION(0x1, "uart2", "rxd", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x2, "uart0", "cts", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x3, "tdm", "int7", V_MV78230_PLUS), - MPP_VAR_FUNCTION(0x4, "tdm-1", "timer", V_MV78230_PLUS), - MPP_VAR_FUNCTION(0x5, "vdd", "cpu0-pd", V_MV78230_PLUS)), + MPP_VAR_FUNCTION(0x4, "tdm-1", "timer", V_MV78230_PLUS)), MPP_MODE(43, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), MPP_VAR_FUNCTION(0x1, "uart2", "txd", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x2, "uart0", "rts", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x3, "spi", "cs3", V_MV78230_PLUS), - MPP_VAR_FUNCTION(0x4, "pcie", "rstout", V_MV78230_PLUS), - MPP_VAR_FUNCTION(0x5, "vdd", "cpu2-3-pd", V_MV78460)), + MPP_VAR_FUNCTION(0x4, "pcie", "rstout", V_MV78230_PLUS)), MPP_MODE(44, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), MPP_VAR_FUNCTION(0x1, "uart2", "cts", V_MV78230_PLUS), @@ -319,16 +309,13 @@ static struct mvebu_mpp_mode armada_xp_mpp_modes[] = { MPP_VAR_FUNCTION(0x1, "dev", "ad19", V_MV78260_PLUS)), MPP_MODE(55, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS), - MPP_VAR_FUNCTION(0x1, "dev", "ad20", V_MV78260_PLUS), - MPP_VAR_FUNCTION(0x2, "vdd", "cpu0-pd", V_MV78260_PLUS)), + MPP_VAR_FUNCTION(0x1, "dev", "ad20", V_MV78260_PLUS)), MPP_MODE(56, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS), - MPP_VAR_FUNCTION(0x1, "dev", "ad21", V_MV78260_PLUS), - MPP_VAR_FUNCTION(0x2, "vdd", "cpu1-pd", V_MV78260_PLUS)), + MPP_VAR_FUNCTION(0x1, "dev", "ad21", V_MV78260_PLUS)), MPP_MODE(57, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS), - MPP_VAR_FUNCTION(0x1, "dev", "ad22", V_MV78260_PLUS), - MPP_VAR_FUNCTION(0x2, "vdd", "cpu2-3-pd", V_MV78460)), + MPP_VAR_FUNCTION(0x1, "dev", "ad22", V_MV78260_PLUS)), MPP_MODE(58, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS), MPP_VAR_FUNCTION(0x1, "dev", "ad23", V_MV78260_PLUS)), -- cgit v0.10.2 From ea78b9511a54d0de026e04b5da86b30515072f31 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 9 Jun 2015 18:46:58 +0200 Subject: pinctrl: mvebu: armada-xp: fix functions of MPP48 There was a mistake in the definition of the functions for MPP48 on Marvell Armada XP. The second function is dev(clkout), and not tclk. Signed-off-by: Thomas Petazzoni Cc: # v3.7+ Fixes: 463e270f766a ("pinctrl: mvebu: add pinctrl driver for Armada XP") Signed-off-by: Linus Walleij diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt index b347b85..96e7744 100644 --- a/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt @@ -69,7 +69,7 @@ mpp45 45 gpio, uart2(rts), uart3(txd), spi(cs5), sata1(prsnt) mpp46 46 gpio, uart3(rts), uart1(rts), spi(cs6), sata0(prsnt) mpp47 47 gpio, uart3(cts), uart1(cts), spi(cs7), pcie(clkreq3), ref(clkout) -mpp48 48 gpio, tclk, dev(burst/last) +mpp48 48 gpio, dev(clkout), dev(burst/last) * Marvell Armada XP (mv78260 and mv78460 only) diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-xp.c b/drivers/pinctrl/mvebu/pinctrl-armada-xp.c index 0301bd2..d7cdb14 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-xp.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-xp.c @@ -287,7 +287,7 @@ static struct mvebu_mpp_mode armada_xp_mpp_modes[] = { MPP_VAR_FUNCTION(0x5, "pcie", "clkreq3", V_MV78230_PLUS)), MPP_MODE(48, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), - MPP_VAR_FUNCTION(0x1, "tclk", NULL, V_MV78230_PLUS), + MPP_VAR_FUNCTION(0x1, "dev", "clkout", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x2, "dev", "burst/last", V_MV78230_PLUS)), MPP_MODE(49, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS), -- cgit v0.10.2 From d538990ee12b162f7ce6c0fcef3b643800102676 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 9 Jun 2015 18:46:59 +0200 Subject: pinctrl: mvebu: armada-375: remove incorrect space in pin description There was an incorrect space in the definition of the function of one pin in the Armada 375 pinctrl driver, which this commit fixes. Signed-off-by: Thomas Petazzoni Cc: # v3.15+ Fixes: ce3ed59dcddd ("pinctrl: mvebu: add pin-muxing driver for the Marvell Armada 375") Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-375.c b/drivers/pinctrl/mvebu/pinctrl-armada-375.c index e740a42..203291b 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-375.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-375.c @@ -92,7 +92,7 @@ static struct mvebu_mpp_mode mv88f6720_mpp_modes[] = { MPP_FUNCTION(0x5, "nand", "io1")), MPP_MODE(8, MPP_FUNCTION(0x0, "gpio", NULL), - MPP_FUNCTION(0x1, "dev ", "bootcs"), + MPP_FUNCTION(0x1, "dev", "bootcs"), MPP_FUNCTION(0x2, "spi0", "cs0"), MPP_FUNCTION(0x3, "spi1", "cs0"), MPP_FUNCTION(0x5, "nand", "ce")), -- cgit v0.10.2 From 27e7cd016558bf787b128fd882cdd90409ae4036 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 9 Jun 2015 18:47:00 +0200 Subject: pinctrl: mvebu: armada-38x: fix incorrect total number of GPIOs The pinctrl_gpio_range[] array described a first bank of 32 GPIOs and a second one of 27 GPIOs. However, since there is a total of 60 MPP pins that can be muxed as GPIOs, the second bank really has 28 GPIOs. Signed-off-by: Thomas Petazzoni Cc: # v3.15+ Fixes: ca6d9a084b56f ("pinctrl: mvebu: add pin-muxing driver for the Marvell Armada 380/385") Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-38x.c b/drivers/pinctrl/mvebu/pinctrl-armada-38x.c index 11656c7..ff411a5 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-38x.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-38x.c @@ -402,7 +402,7 @@ static struct mvebu_mpp_ctrl armada_38x_mpp_controls[] = { static struct pinctrl_gpio_range armada_38x_mpp_gpio_ranges[] = { MPP_GPIO_RANGE(0, 0, 0, 32), - MPP_GPIO_RANGE(1, 32, 32, 27), + MPP_GPIO_RANGE(1, 32, 32, 28), }; static int armada_38x_pinctrl_probe(struct platform_device *pdev) -- cgit v0.10.2 From 7c580311a2cb3bb0d0188665c9c69227aed650ea Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 9 Jun 2015 18:47:01 +0200 Subject: pinctrl: mvebu: armada-39x: fix incorrect total number of GPIOs The pinctrl_gpio_range[] array described a first bank of 32 GPIOs and a second one of 27 GPIOs. However, since there is a total of 60 MPP pins that can be muxed as GPIOs, the second bank really has 28 GPIOs. Signed-off-by: Thomas Petazzoni Cc: # v4.1+ Fixes: ee086577abe7f ("pinctrl: mvebu: add pinctrl driver for Marvell Armada 39x") Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-39x.c b/drivers/pinctrl/mvebu/pinctrl-armada-39x.c index 4249162..2dcf9b4 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-39x.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-39x.c @@ -380,7 +380,7 @@ static struct mvebu_mpp_ctrl armada_39x_mpp_controls[] = { static struct pinctrl_gpio_range armada_39x_mpp_gpio_ranges[] = { MPP_GPIO_RANGE(0, 0, 0, 32), - MPP_GPIO_RANGE(1, 32, 32, 27), + MPP_GPIO_RANGE(1, 32, 32, 28), }; static int armada_39x_pinctrl_probe(struct platform_device *pdev) -- cgit v0.10.2 From 9540cf534429359699ea85df20cb7be307548b89 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 9 Jun 2015 18:47:02 +0200 Subject: pinctrl: mvebu: armada-{375,38x,39x}: normalize naming of PTP subnames The subnames are purely informative, but it's nicer when they match accross SoCs. This commit adjusts the Armada 375, Armada 38x and Armada 39x MPP definitions so that the subnames of the PTP pins match the ones used on Armada XP and Kirkwood. Signed-off-by: Thomas Petazzoni Signed-off-by: Linus Walleij diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-375-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-375-pinctrl.txt index bedbe42..e22ec5e 100644 --- a/Documentation/devicetree/bindings/pinctrl/marvell,armada-375-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-375-pinctrl.txt @@ -15,8 +15,8 @@ name pins functions ================================================================================ mpp0 0 gpio, dev(ad2), spi0(cs1), spi1(cs1) mpp1 1 gpio, dev(ad3), spi0(mosi), spi1(mosi) -mpp2 2 gpio, dev(ad4), ptp(eventreq), led(c0), audio(sdi) -mpp3 3 gpio, dev(ad5), ptp(triggen), led(p3), audio(mclk) +mpp2 2 gpio, dev(ad4), ptp(evreq), led(c0), audio(sdi) +mpp3 3 gpio, dev(ad5), ptp(trig), led(p3), audio(mclk) mpp4 4 gpio, dev(ad6), spi0(miso), spi1(miso) mpp5 5 gpio, dev(ad7), spi0(cs2), spi1(cs2) mpp6 6 gpio, dev(ad0), led(p1), audio(rclk) @@ -45,7 +45,7 @@ mpp28 28 gpio, led(p3), ge1(txctl), sd(clk) mpp29 29 gpio, pcie1(clkreq), ge1(rxclk), sd(d3) mpp30 30 gpio, ge1(txd0), spi1(cs0) mpp31 31 gpio, ge1(txd1), spi1(mosi) -mpp32 32 gpio, ge1(txd2), spi1(sck), ptp(triggen) +mpp32 32 gpio, ge1(txd2), spi1(sck), ptp(trig) mpp33 33 gpio, ge1(txd3), spi1(miso) mpp34 34 gpio, ge1(txclkout), spi1(sck) mpp35 35 gpio, ge1(rxctl), spi1(cs1), spi0(cs2) @@ -76,7 +76,7 @@ mpp59 59 gpio, led(c1) mpp60 60 gpio, uart1(txd), led(c2) mpp61 61 gpio, i2c1(sda), uart1(rxd), spi1(cs2), led(p0) mpp62 62 gpio, i2c1(sck), led(p1) -mpp63 63 gpio, ptp(triggen), led(p2) +mpp63 63 gpio, ptp(trig), led(p2) mpp64 64 gpio, dram(vttctrl), led(p3) mpp65 65 gpio, sata1(prsnt) -mpp66 66 gpio, ptp(eventreq), spi1(cs3) +mpp66 66 gpio, ptp(evreq), spi1(cs3) diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-38x-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-38x-pinctrl.txt index 4ac138a..4fe6340 100644 --- a/Documentation/devicetree/bindings/pinctrl/marvell,armada-38x-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-38x-pinctrl.txt @@ -33,8 +33,8 @@ mpp14 14 gpio, ge0(rxd2), ptp(clk), m(vtt_ctrl), spi0(cs3), dev(we mpp15 15 gpio, ge0(rxd3), ge(mdc slave), pcie0(rstout), spi0(mosi) mpp16 16 gpio, ge0(rxctl), ge(mdio slave), m(decc_err), spi0(miso), pcie0(clkreq), pcie1(clkreq) [1] mpp17 17 gpio, ge0(rxclk), ptp(clk), ua1(rxd), spi0(sck), sata1(prsnt) -mpp18 18 gpio, ge0(rxerr), ptp(trig_gen), ua1(txd), spi0(cs0) -mpp19 19 gpio, ge0(col), ptp(event_req), ge0(txerr), sata1(prsnt), ua0(cts) +mpp18 18 gpio, ge0(rxerr), ptp(trig), ua1(txd), spi0(cs0) +mpp19 19 gpio, ge0(col), ptp(evreq), ge0(txerr), sata1(prsnt), ua0(cts) mpp20 20 gpio, ge0(txclk), ptp(clk), sata0(prsnt), ua0(rts) mpp21 21 gpio, spi0(cs1), ge1(rxd0), sata0(prsnt), sd0(cmd), dev(bootcs) mpp22 22 gpio, spi0(mosi), dev(ad0) @@ -51,9 +51,9 @@ mpp32 32 gpio, ge1(txctl), dev(wen0) mpp33 33 gpio, m(decc_err), dev(ad3) mpp34 34 gpio, dev(ad1) mpp35 35 gpio, ref(clk_out1), dev(a1) -mpp36 36 gpio, ptp(trig_gen), dev(a0) +mpp36 36 gpio, ptp(trig), dev(a0) mpp37 37 gpio, ptp(clk), ge1(rxclk), sd0(d3), dev(ad8) -mpp38 38 gpio, ptp(event_req), ge1(rxd1), ref(clk_out0), sd0(d0), dev(ad4) +mpp38 38 gpio, ptp(evreq), ge1(rxd1), ref(clk_out0), sd0(d0), dev(ad4) mpp39 39 gpio, i2c1(sck), ge1(rxd2), ua0(cts), sd0(d1), dev(a2) mpp40 40 gpio, i2c1(sda), ge1(rxd3), ua0(rts), sd0(d2), dev(ad6) mpp41 41 gpio, ua1(rxd), ge1(rxctl), ua0(cts), spi1(cs3), dev(burst/last) diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-39x-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-39x-pinctrl.txt index 5b1a9dc..182a059 100644 --- a/Documentation/devicetree/bindings/pinctrl/marvell,armada-39x-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-39x-pinctrl.txt @@ -24,7 +24,7 @@ mpp6 6 gpio, dev(cs3), xsmi(mdio) mpp7 7 gpio, dev(ad9), xsmi(mdc) mpp8 8 gpio, dev(ad10), ptp(trig) mpp9 9 gpio, dev(ad11), ptp(clk) -mpp10 10 gpio, dev(ad12), ptp(event) +mpp10 10 gpio, dev(ad12), ptp(evreq) mpp11 11 gpio, dev(ad13), led(clk) mpp12 12 gpio, pcie0(rstout), dev(ad14), led(stb) mpp13 13 gpio, dev(ad15), led(data) diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-375.c b/drivers/pinctrl/mvebu/pinctrl-armada-375.c index 203291b..ba0913a 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-375.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-375.c @@ -51,7 +51,7 @@ static struct mvebu_mpp_mode mv88f6720_mpp_modes[] = { MPP_MODE(2, MPP_FUNCTION(0x0, "gpio", NULL), MPP_FUNCTION(0x1, "dev", "ad4"), - MPP_FUNCTION(0x2, "ptp", "eventreq"), + MPP_FUNCTION(0x2, "ptp", "evreq"), MPP_FUNCTION(0x3, "led", "c0"), MPP_FUNCTION(0x4, "audio", "sdi"), MPP_FUNCTION(0x5, "nand", "io4"), @@ -59,7 +59,7 @@ static struct mvebu_mpp_mode mv88f6720_mpp_modes[] = { MPP_MODE(3, MPP_FUNCTION(0x0, "gpio", NULL), MPP_FUNCTION(0x1, "dev", "ad5"), - MPP_FUNCTION(0x2, "ptp", "triggen"), + MPP_FUNCTION(0x2, "ptp", "trig"), MPP_FUNCTION(0x3, "led", "p3"), MPP_FUNCTION(0x4, "audio", "mclk"), MPP_FUNCTION(0x5, "nand", "io5"), @@ -207,7 +207,7 @@ static struct mvebu_mpp_mode mv88f6720_mpp_modes[] = { MPP_FUNCTION(0x2, "ge1", "txd0"), MPP_FUNCTION(0x3, "spi1", "cs0"), MPP_FUNCTION(0x5, "led", "p3"), - MPP_FUNCTION(0x6, "ptp", "eventreq")), + MPP_FUNCTION(0x6, "ptp", "evreq")), MPP_MODE(31, MPP_FUNCTION(0x0, "gpio", NULL), MPP_FUNCTION(0x2, "ge1", "txd1"), @@ -217,7 +217,7 @@ static struct mvebu_mpp_mode mv88f6720_mpp_modes[] = { MPP_FUNCTION(0x0, "gpio", NULL), MPP_FUNCTION(0x2, "ge1", "txd2"), MPP_FUNCTION(0x3, "spi1", "sck"), - MPP_FUNCTION(0x4, "ptp", "triggen"), + MPP_FUNCTION(0x4, "ptp", "trig"), MPP_FUNCTION(0x5, "led", "c0")), MPP_MODE(33, MPP_FUNCTION(0x0, "gpio", NULL), @@ -290,7 +290,7 @@ static struct mvebu_mpp_mode mv88f6720_mpp_modes[] = { MPP_FUNCTION(0x1, "led", "p1"), MPP_FUNCTION(0x2, "ge0", "txd1"), MPP_FUNCTION(0x3, "ge1", "txd1"), - MPP_FUNCTION(0x5, "ptp", "triggen"), + MPP_FUNCTION(0x5, "ptp", "trig"), MPP_FUNCTION(0x6, "dev", "ale0")), MPP_MODE(48, MPP_FUNCTION(0x0, "gpio", NULL), @@ -309,7 +309,7 @@ static struct mvebu_mpp_mode mv88f6720_mpp_modes[] = { MPP_FUNCTION(0x1, "led", "c0"), MPP_FUNCTION(0x2, "ge0", "rxd0"), MPP_FUNCTION(0x3, "ge1", "rxd0"), - MPP_FUNCTION(0x5, "ptp", "eventreq"), + MPP_FUNCTION(0x5, "ptp", "evreq"), MPP_FUNCTION(0x6, "dev", "ad12")), MPP_MODE(51, MPP_FUNCTION(0x0, "gpio", NULL), @@ -377,7 +377,7 @@ static struct mvebu_mpp_mode mv88f6720_mpp_modes[] = { MPP_FUNCTION(0x6, "dev", "ad15")), MPP_MODE(63, MPP_FUNCTION(0x0, "gpio", NULL), - MPP_FUNCTION(0x2, "ptp", "triggen"), + MPP_FUNCTION(0x2, "ptp", "trig"), MPP_FUNCTION(0x4, "led", "p2"), MPP_FUNCTION(0x6, "dev", "burst")), MPP_MODE(64, @@ -389,7 +389,7 @@ static struct mvebu_mpp_mode mv88f6720_mpp_modes[] = { MPP_FUNCTION(0x1, "sata1", "prsnt")), MPP_MODE(66, MPP_FUNCTION(0x0, "gpio", NULL), - MPP_FUNCTION(0x2, "ptp", "eventreq"), + MPP_FUNCTION(0x2, "ptp", "evreq"), MPP_FUNCTION(0x4, "spi1", "cs3"), MPP_FUNCTION(0x5, "pcie0", "rstoutn"), MPP_FUNCTION(0x6, "dev", "cs3")), diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-38x.c b/drivers/pinctrl/mvebu/pinctrl-armada-38x.c index ff411a5..eb4b0d8 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-38x.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-38x.c @@ -137,13 +137,13 @@ static struct mvebu_mpp_mode armada_38x_mpp_modes[] = { MPP_MODE(18, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), MPP_VAR_FUNCTION(1, "ge0", "rxerr", V_88F6810_PLUS), - MPP_VAR_FUNCTION(2, "ptp", "trig_gen", V_88F6810_PLUS), + MPP_VAR_FUNCTION(2, "ptp", "trig", V_88F6810_PLUS), MPP_VAR_FUNCTION(3, "ua1", "txd", V_88F6810_PLUS), MPP_VAR_FUNCTION(4, "spi0", "cs0", V_88F6810_PLUS)), MPP_MODE(19, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), MPP_VAR_FUNCTION(1, "ge0", "col", V_88F6810_PLUS), - MPP_VAR_FUNCTION(2, "ptp", "event_req", V_88F6810_PLUS), + MPP_VAR_FUNCTION(2, "ptp", "evreq", V_88F6810_PLUS), MPP_VAR_FUNCTION(3, "ge0", "txerr", V_88F6810_PLUS), MPP_VAR_FUNCTION(4, "sata1", "prsnt", V_88F6810_PLUS), MPP_VAR_FUNCTION(5, "ua0", "cts", V_88F6810_PLUS), @@ -231,7 +231,7 @@ static struct mvebu_mpp_mode armada_38x_mpp_modes[] = { MPP_VAR_FUNCTION(5, "dev", "a1", V_88F6810_PLUS)), MPP_MODE(36, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), - MPP_VAR_FUNCTION(1, "ptp", "trig_gen", V_88F6810_PLUS), + MPP_VAR_FUNCTION(1, "ptp", "trig", V_88F6810_PLUS), MPP_VAR_FUNCTION(5, "dev", "a0", V_88F6810_PLUS)), MPP_MODE(37, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), @@ -241,7 +241,7 @@ static struct mvebu_mpp_mode armada_38x_mpp_modes[] = { MPP_VAR_FUNCTION(5, "dev", "ad8", V_88F6810_PLUS)), MPP_MODE(38, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), - MPP_VAR_FUNCTION(1, "ptp", "event_req", V_88F6810_PLUS), + MPP_VAR_FUNCTION(1, "ptp", "evreq", V_88F6810_PLUS), MPP_VAR_FUNCTION(2, "ge1", "rxd1", V_88F6810_PLUS), MPP_VAR_FUNCTION(3, "ref", "clk_out0", V_88F6810_PLUS), MPP_VAR_FUNCTION(4, "sd0", "d0", V_88F6810_PLUS), diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-39x.c b/drivers/pinctrl/mvebu/pinctrl-armada-39x.c index 2dcf9b4..4cf7024 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-39x.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-39x.c @@ -82,7 +82,7 @@ static struct mvebu_mpp_mode armada_39x_mpp_modes[] = { MPP_MODE(10, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), MPP_VAR_FUNCTION(5, "dev", "ad12", V_88F6920_PLUS), - MPP_VAR_FUNCTION(7, "ptp", "event", V_88F6920_PLUS)), + MPP_VAR_FUNCTION(7, "ptp", "evreq", V_88F6920_PLUS)), MPP_MODE(11, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), MPP_VAR_FUNCTION(5, "dev", "ad13", V_88F6920_PLUS), -- cgit v0.10.2 From 100dc5d840951577b26274749dd099d3bf94982b Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 9 Jun 2015 18:47:03 +0200 Subject: pinctrl: mvebu: armada-{38x,39x,xp}: normalize naming of DRAM functions This commit makes the dram functions naming (both the name and subname) consistent accross SoC, by using: dram(vttctrl) dram(deccerr) in all Marvell SoCs. Due to the change to the name, it changes the DT binding, but these functions are not used by any in-tree Device Tree file, and are very unlikely to be used by anyone. Signed-off-by: Thomas Petazzoni Signed-off-by: Linus Walleij diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-38x-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-38x-pinctrl.txt index 4fe6340..4fb82c1 100644 --- a/Documentation/devicetree/bindings/pinctrl/marvell,armada-38x-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-38x-pinctrl.txt @@ -29,9 +29,9 @@ mpp10 10 gpio, ge0(txd3), dev(ad12) mpp11 11 gpio, ge0(txctl), dev(ad13) mpp12 12 gpio, ge0(rxd0), pcie0(rstout), spi0(cs1), dev(ad14), pcie3(clkreq) mpp13 13 gpio, ge0(rxd1), pcie0(clkreq), pcie1(clkreq) [1], spi0(cs2), dev(ad15), pcie2(clkreq) -mpp14 14 gpio, ge0(rxd2), ptp(clk), m(vtt_ctrl), spi0(cs3), dev(wen1), pcie3(clkreq) +mpp14 14 gpio, ge0(rxd2), ptp(clk), dram(vttctrl), spi0(cs3), dev(wen1), pcie3(clkreq) mpp15 15 gpio, ge0(rxd3), ge(mdc slave), pcie0(rstout), spi0(mosi) -mpp16 16 gpio, ge0(rxctl), ge(mdio slave), m(decc_err), spi0(miso), pcie0(clkreq), pcie1(clkreq) [1] +mpp16 16 gpio, ge0(rxctl), ge(mdio slave), dram(deccerr), spi0(miso), pcie0(clkreq), pcie1(clkreq) [1] mpp17 17 gpio, ge0(rxclk), ptp(clk), ua1(rxd), spi0(sck), sata1(prsnt) mpp18 18 gpio, ge0(rxerr), ptp(trig), ua1(txd), spi0(cs0) mpp19 19 gpio, ge0(col), ptp(evreq), ge0(txerr), sata1(prsnt), ua0(cts) @@ -48,7 +48,7 @@ mpp29 29 gpio, ge1(txd1), dev(ale0) mpp30 30 gpio, ge1(txd2), dev(oen) mpp31 31 gpio, ge1(txd3), dev(ale1) mpp32 32 gpio, ge1(txctl), dev(wen0) -mpp33 33 gpio, m(decc_err), dev(ad3) +mpp33 33 gpio, dram(deccerr), dev(ad3) mpp34 34 gpio, dev(ad1) mpp35 35 gpio, ref(clk_out1), dev(a1) mpp36 36 gpio, ptp(trig), dev(a0) @@ -58,20 +58,20 @@ mpp39 39 gpio, i2c1(sck), ge1(rxd2), ua0(cts), sd0(d1), dev(a2) mpp40 40 gpio, i2c1(sda), ge1(rxd3), ua0(rts), sd0(d2), dev(ad6) mpp41 41 gpio, ua1(rxd), ge1(rxctl), ua0(cts), spi1(cs3), dev(burst/last) mpp42 42 gpio, ua1(txd), ua0(rts), dev(ad7) -mpp43 43 gpio, pcie0(clkreq), m(vtt_ctrl), m(decc_err), spi1(cs2), dev(clkout) +mpp43 43 gpio, pcie0(clkreq), dram(vttctrl), dram(deccerr), spi1(cs2), dev(clkout) mpp44 44 gpio, sata0(prsnt), sata1(prsnt), sata2(prsnt) [2], sata3(prsnt) [3] mpp45 45 gpio, ref(clk_out0), pcie0(rstout) mpp46 46 gpio, ref(clk_out1), pcie0(rstout) mpp47 47 gpio, sata0(prsnt), sata1(prsnt), sata2(prsnt) [2], sata3(prsnt) [2] -mpp48 48 gpio, sata0(prsnt), m(vtt_ctrl), tdm2c(pclk), audio(mclk), sd0(d4), pcie0(clkreq) +mpp48 48 gpio, sata0(prsnt), dram(vttctrl), tdm2c(pclk), audio(mclk), sd0(d4), pcie0(clkreq) mpp49 49 gpio, sata2(prsnt) [2], sata3(prsnt) [2], tdm2c(fsync), audio(lrclk), sd0(d5), pcie1(clkreq) mpp50 50 gpio, pcie0(rstout), tdm2c(drx), audio(extclk), sd0(cmd) -mpp51 51 gpio, tdm2c(dtx), audio(sdo), m(decc_err) +mpp51 51 gpio, tdm2c(dtx), audio(sdo), dram(deccerr) mpp52 52 gpio, pcie0(rstout), tdm2c(intn), audio(sdi), sd0(d6) mpp53 53 gpio, sata1(prsnt), sata0(prsnt), tdm2c(rstn), audio(bclk), sd0(d7) mpp54 54 gpio, sata0(prsnt), sata1(prsnt), pcie0(rstout), ge0(txerr), sd0(d3) mpp55 55 gpio, ua1(cts), ge(mdio), pcie1(clkreq) [1], spi1(cs1), sd0(d0) -mpp56 56 gpio, ua1(rts), ge(mdc), m(decc_err), spi1(mosi) +mpp56 56 gpio, ua1(rts), ge(mdc), dram(deccerr), spi1(mosi) mpp57 57 gpio, spi1(sck), sd0(clk) mpp58 58 gpio, pcie1(clkreq) [1], i2c1(sck), pcie2(clkreq), spi1(miso), sd0(d1) mpp59 59 gpio, pcie0(rstout), i2c1(sda), spi1(cs0), sd0(d2) diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-39x-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-39x-pinctrl.txt index 182a059..8271cd2 100644 --- a/Documentation/devicetree/bindings/pinctrl/marvell,armada-39x-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-39x-pinctrl.txt @@ -28,9 +28,9 @@ mpp10 10 gpio, dev(ad12), ptp(evreq) mpp11 11 gpio, dev(ad13), led(clk) mpp12 12 gpio, pcie0(rstout), dev(ad14), led(stb) mpp13 13 gpio, dev(ad15), led(data) -mpp14 14 gpio, m(vtt), dev(wen1), ua1(txd) +mpp14 14 gpio, dram(vttctrl), dev(wen1), ua1(txd) mpp15 15 gpio, pcie0(rstout), spi0(mosi), i2c1(sck) -mpp16 16 gpio, m(decc), spi0(miso), i2c1(sda) +mpp16 16 gpio, dram(deccerr), spi0(miso), i2c1(sda) mpp17 17 gpio, ua1(rxd), spi0(sck), smi(mdio) mpp18 18 gpio, ua1(txd), spi0(cs0), i2c2(sck) mpp19 19 gpio, sata1(present) [1], ua0(cts), ua1(rxd), i2c2(sda) @@ -47,7 +47,7 @@ mpp29 29 gpio, dev(ale0), ge(txd1) mpp30 30 gpio, dev(oen), ge(txd2) mpp31 31 gpio, dev(ale1), ge(txd3) mpp32 32 gpio, dev(wen0), ge(txctl) -mpp33 33 gpio, m(decc), dev(ad3) +mpp33 33 gpio, dram(deccerr), dev(ad3) mpp34 34 gpio, dev(ad1) mpp35 35 gpio, ref(clk), dev(a1) mpp36 36 gpio, dev(a0) @@ -57,20 +57,20 @@ mpp39 39 gpio, i2c1(sck), ua0(cts), sd(d1), dev(a2), ge(rxd2) mpp40 40 gpio, i2c1(sda), ua0(rts), sd(d2), dev(ad6), ge(rxd3) mpp41 41 gpio, ua1(rxd), ua0(cts), spi1(cs3), dev(burstn), nd(rbn0), ge(rxctl) mpp42 42 gpio, ua1(txd), ua0(rts), dev(ad7) -mpp43 43 gpio, pcie0(clkreq), m(vtt), m(decc), spi1(cs2), dev(clkout), nd(rbn1) +mpp43 43 gpio, pcie0(clkreq), dram(vttctrl), dram(deccerr), spi1(cs2), dev(clkout), nd(rbn1) mpp44 44 gpio, sata0(present) [1], sata1(present) [1], led(clk) mpp45 45 gpio, ref(clk), pcie0(rstout), ua1(rxd) mpp46 46 gpio, ref(clk), pcie0(rstout), ua1(txd), led(stb) mpp47 47 gpio, sata0(present) [1], sata1(present) [1], led(data) -mpp48 48 gpio, sata0(present) [1], m(vtt), tdm(pclk) [1], audio(mclk) [1], sd(d4), pcie0(clkreq), ua1(txd) +mpp48 48 gpio, sata0(present) [1], dram(vttctrl), tdm(pclk) [1], audio(mclk) [1], sd(d4), pcie0(clkreq), ua1(txd) mpp49 49 gpio, tdm(fsync) [1], audio(lrclk) [1], sd(d5), ua2(rxd) mpp50 50 gpio, pcie0(rstout), tdm(drx) [1], audio(extclk) [1], sd(cmd), ua2(rxd) -mpp51 51 gpio, tdm(dtx) [1], audio(sdo) [1], m(decc), ua2(txd) +mpp51 51 gpio, tdm(dtx) [1], audio(sdo) [1], dram(deccerr), ua2(txd) mpp52 52 gpio, pcie0(rstout), tdm(intn) [1], audio(sdi) [1], sd(d6), i2c3(sck) mpp53 53 gpio, sata1(present) [1], sata0(present) [1], tdm(rstn) [1], audio(bclk) [1], sd(d7), i2c3(sda) mpp54 54 gpio, sata0(present) [1], sata1(present) [1], pcie0(rstout), sd(d3), ua3(txd) mpp55 55 gpio, ua1(cts), spi1(cs1), sd(d0), ua1(rxd), ua3(rxd) -mpp56 56 gpio, ua1(rts), m(decc), spi1(mosi), ua1(txd) +mpp56 56 gpio, ua1(rts), dram(deccerr), spi1(mosi), ua1(txd) mpp57 57 gpio, spi1(sck), sd(clk), ua1(txd) mpp58 58 gpio, i2c1(sck), pcie2(clkreq), spi1(miso), sd(d1), ua1(rxd) mpp59 59 gpio, pcie0(rstout), i2c1(sda), spi1(cs0), sd(d2) diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt index 96e7744..cefca17 100644 --- a/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt @@ -39,7 +39,7 @@ mpp17 17 gpio, ge0(col), ge1(txctl), lcd(d17) mpp18 18 gpio, ge0(rxerr), ge1(rxd0), lcd(d18), ptp(trig) mpp19 19 gpio, ge0(crs), ge1(rxd1), lcd(d19), ptp(evreq) mpp20 20 gpio, ge0(rxd4), ge1(rxd2), lcd(d20), ptp(clk) -mpp21 21 gpio, ge0(rxd5), ge1(rxd3), lcd(d21), mem(bat) +mpp21 21 gpio, ge0(rxd5), ge1(rxd3), lcd(d21), dram(bat) mpp22 22 gpio, ge0(rxd6), ge1(rxctl), lcd(d22), sata0(prsnt) mpp23 23 gpio, ge0(rxd7), ge1(rxclk), lcd(d23), sata1(prsnt) mpp24 24 gpio, lcd(hsync), sata1(prsnt), tdm(rst) @@ -51,7 +51,7 @@ mpp29 29 gpio, lcd(ref-clk), tdm(int0), ptp(clk) mpp30 30 gpio, tdm(int1), sd0(clk) mpp31 31 gpio, tdm(int2), sd0(cmd) mpp32 32 gpio, tdm(int3), sd0(d0) -mpp33 33 gpio, tdm(int4), sd0(d1), mem(bat) +mpp33 33 gpio, tdm(int4), sd0(d1), dram(bat) mpp34 34 gpio, tdm(int5), sd0(d2), sata0(prsnt) mpp35 35 gpio, tdm(int6), sd0(d3), sata1(prsnt) mpp36 36 gpio, spi(mosi) @@ -64,7 +64,7 @@ mpp41 41 gpio, spi(cs2), uart2(rts), lcd(vga-vsync), sata1(prsnt), mpp42 42 gpio, uart2(rxd), uart0(cts), tdm(int7), tdm-1(timer) mpp43 43 gpio, uart2(txd), uart0(rts), spi(cs3), pcie(rstout) mpp44 44 gpio, uart2(cts), uart3(rxd), spi(cs4), pcie(clkreq2), - mem(bat) + dram(bat) mpp45 45 gpio, uart2(rts), uart3(txd), spi(cs5), sata1(prsnt) mpp46 46 gpio, uart3(rts), uart1(rts), spi(cs6), sata0(prsnt) mpp47 47 gpio, uart3(cts), uart1(cts), spi(cs7), pcie(clkreq3), diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-38x.c b/drivers/pinctrl/mvebu/pinctrl-armada-38x.c index eb4b0d8..2b04923 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-38x.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-38x.c @@ -109,7 +109,7 @@ static struct mvebu_mpp_mode armada_38x_mpp_modes[] = { MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), MPP_VAR_FUNCTION(1, "ge0", "rxd2", V_88F6810_PLUS), MPP_VAR_FUNCTION(2, "ptp", "clk", V_88F6810_PLUS), - MPP_VAR_FUNCTION(3, "m", "vtt_ctrl", V_88F6810_PLUS), + MPP_VAR_FUNCTION(3, "dram", "vttctrl", V_88F6810_PLUS), MPP_VAR_FUNCTION(4, "spi0", "cs3", V_88F6810_PLUS), MPP_VAR_FUNCTION(5, "dev", "wen1", V_88F6810_PLUS), MPP_VAR_FUNCTION(6, "pcie3", "clkreq", V_88F6810_PLUS)), @@ -123,7 +123,7 @@ static struct mvebu_mpp_mode armada_38x_mpp_modes[] = { MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), MPP_VAR_FUNCTION(1, "ge0", "rxctl", V_88F6810_PLUS), MPP_VAR_FUNCTION(2, "ge", "mdio slave", V_88F6810_PLUS), - MPP_VAR_FUNCTION(3, "m", "decc_err", V_88F6810_PLUS), + MPP_VAR_FUNCTION(3, "dram", "deccerr", V_88F6810_PLUS), MPP_VAR_FUNCTION(4, "spi0", "miso", V_88F6810_PLUS), MPP_VAR_FUNCTION(5, "pcie0", "clkreq", V_88F6810_PLUS), MPP_VAR_FUNCTION(6, "pcie1", "clkreq", V_88F6820_PLUS)), @@ -220,7 +220,7 @@ static struct mvebu_mpp_mode armada_38x_mpp_modes[] = { MPP_VAR_FUNCTION(5, "dev", "wen0", V_88F6810_PLUS)), MPP_MODE(33, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), - MPP_VAR_FUNCTION(1, "m", "decc_err", V_88F6810_PLUS), + MPP_VAR_FUNCTION(1, "dram", "deccerr", V_88F6810_PLUS), MPP_VAR_FUNCTION(5, "dev", "ad3", V_88F6810_PLUS)), MPP_MODE(34, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), @@ -275,8 +275,8 @@ static struct mvebu_mpp_mode armada_38x_mpp_modes[] = { MPP_MODE(43, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), MPP_VAR_FUNCTION(1, "pcie0", "clkreq", V_88F6810_PLUS), - MPP_VAR_FUNCTION(2, "m", "vtt_ctrl", V_88F6810_PLUS), - MPP_VAR_FUNCTION(3, "m", "decc_err", V_88F6810_PLUS), + MPP_VAR_FUNCTION(2, "dram", "vttctrl", V_88F6810_PLUS), + MPP_VAR_FUNCTION(3, "dram", "deccerr", V_88F6810_PLUS), MPP_VAR_FUNCTION(4, "spi1", "cs2", V_88F6810_PLUS), MPP_VAR_FUNCTION(5, "dev", "clkout", V_88F6810_PLUS)), MPP_MODE(44, @@ -302,7 +302,7 @@ static struct mvebu_mpp_mode armada_38x_mpp_modes[] = { MPP_MODE(48, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), MPP_VAR_FUNCTION(1, "sata0", "prsnt", V_88F6810_PLUS), - MPP_VAR_FUNCTION(2, "m", "vtt_ctrl", V_88F6810_PLUS), + MPP_VAR_FUNCTION(2, "dram", "vttctrl", V_88F6810_PLUS), MPP_VAR_FUNCTION(3, "tdm2c", "pclk", V_88F6810_PLUS), MPP_VAR_FUNCTION(4, "audio", "mclk", V_88F6810_PLUS), MPP_VAR_FUNCTION(5, "sd0", "d4", V_88F6810_PLUS), @@ -325,7 +325,7 @@ static struct mvebu_mpp_mode armada_38x_mpp_modes[] = { MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), MPP_VAR_FUNCTION(3, "tdm2c", "dtx", V_88F6810_PLUS), MPP_VAR_FUNCTION(4, "audio", "sdo", V_88F6810_PLUS), - MPP_VAR_FUNCTION(5, "m", "decc_err", V_88F6810_PLUS)), + MPP_VAR_FUNCTION(5, "dram", "deccerr", V_88F6810_PLUS)), MPP_MODE(52, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), MPP_VAR_FUNCTION(1, "pcie0", "rstout", V_88F6810_PLUS), @@ -357,7 +357,7 @@ static struct mvebu_mpp_mode armada_38x_mpp_modes[] = { MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), MPP_VAR_FUNCTION(1, "ua1", "rts", V_88F6810_PLUS), MPP_VAR_FUNCTION(2, "ge", "mdc", V_88F6810_PLUS), - MPP_VAR_FUNCTION(3, "m", "decc_err", V_88F6810_PLUS), + MPP_VAR_FUNCTION(3, "dram", "deccerr", V_88F6810_PLUS), MPP_VAR_FUNCTION(4, "spi1", "mosi", V_88F6810_PLUS)), MPP_MODE(57, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-39x.c b/drivers/pinctrl/mvebu/pinctrl-armada-39x.c index 4cf7024..7cbc3fb 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-39x.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-39x.c @@ -98,7 +98,7 @@ static struct mvebu_mpp_mode armada_39x_mpp_modes[] = { MPP_VAR_FUNCTION(7, "led", "data", V_88F6920_PLUS)), MPP_MODE(14, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), - MPP_VAR_FUNCTION(3, "m", "vtt", V_88F6920_PLUS), + MPP_VAR_FUNCTION(3, "dram", "vttctrl", V_88F6920_PLUS), MPP_VAR_FUNCTION(5, "dev", "wen1", V_88F6920_PLUS), MPP_VAR_FUNCTION(7, "ua1", "txd", V_88F6920_PLUS)), MPP_MODE(15, @@ -108,7 +108,7 @@ static struct mvebu_mpp_mode armada_39x_mpp_modes[] = { MPP_VAR_FUNCTION(7, "i2c1", "sck", V_88F6920_PLUS)), MPP_MODE(16, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), - MPP_VAR_FUNCTION(3, "m", "decc", V_88F6920_PLUS), + MPP_VAR_FUNCTION(3, "dram", "deccerr", V_88F6920_PLUS), MPP_VAR_FUNCTION(4, "spi0", "miso", V_88F6920_PLUS), MPP_VAR_FUNCTION(7, "i2c1", "sda", V_88F6920_PLUS)), MPP_MODE(17, @@ -198,7 +198,7 @@ static struct mvebu_mpp_mode armada_39x_mpp_modes[] = { MPP_VAR_FUNCTION(8, "ge", "txctl", V_88F6920_PLUS)), MPP_MODE(33, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), - MPP_VAR_FUNCTION(1, "m", "decc", V_88F6920_PLUS), + MPP_VAR_FUNCTION(1, "dram", "deccerr", V_88F6920_PLUS), MPP_VAR_FUNCTION(5, "dev", "ad3", V_88F6920_PLUS)), MPP_MODE(34, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), @@ -251,8 +251,8 @@ static struct mvebu_mpp_mode armada_39x_mpp_modes[] = { MPP_MODE(43, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), MPP_VAR_FUNCTION(1, "pcie0", "clkreq", V_88F6920_PLUS), - MPP_VAR_FUNCTION(2, "m", "vtt", V_88F6920_PLUS), - MPP_VAR_FUNCTION(3, "m", "decc", V_88F6920_PLUS), + MPP_VAR_FUNCTION(2, "dram", "vttctrl", V_88F6920_PLUS), + MPP_VAR_FUNCTION(3, "dram", "deccerr", V_88F6920_PLUS), MPP_VAR_FUNCTION(4, "spi1", "cs2", V_88F6920_PLUS), MPP_VAR_FUNCTION(5, "dev", "clkout", V_88F6920_PLUS), MPP_VAR_FUNCTION(6, "nd", "rbn1", V_88F6920_PLUS)), @@ -280,7 +280,7 @@ static struct mvebu_mpp_mode armada_39x_mpp_modes[] = { MPP_MODE(48, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), MPP_VAR_FUNCTION(1, "sata0", "present", V_88F6928), - MPP_VAR_FUNCTION(2, "m", "vtt", V_88F6920_PLUS), + MPP_VAR_FUNCTION(2, "dram", "vttctrl", V_88F6920_PLUS), MPP_VAR_FUNCTION(3, "tdm", "pclk", V_88F6928), MPP_VAR_FUNCTION(4, "audio", "mclk", V_88F6928), MPP_VAR_FUNCTION(5, "sd", "d4", V_88F6920_PLUS), @@ -303,7 +303,7 @@ static struct mvebu_mpp_mode armada_39x_mpp_modes[] = { MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), MPP_VAR_FUNCTION(3, "tdm", "dtx", V_88F6928), MPP_VAR_FUNCTION(4, "audio", "sdo", V_88F6928), - MPP_VAR_FUNCTION(5, "m", "decc", V_88F6920_PLUS), + MPP_VAR_FUNCTION(5, "dram", "deccerr", V_88F6920_PLUS), MPP_VAR_FUNCTION(7, "ua2", "txd", V_88F6920_PLUS)), MPP_MODE(52, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), @@ -337,7 +337,7 @@ static struct mvebu_mpp_mode armada_39x_mpp_modes[] = { MPP_MODE(56, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), MPP_VAR_FUNCTION(1, "ua1", "rts", V_88F6920_PLUS), - MPP_VAR_FUNCTION(3, "m", "decc", V_88F6920_PLUS), + MPP_VAR_FUNCTION(3, "dram", "deccerr", V_88F6920_PLUS), MPP_VAR_FUNCTION(4, "spi1", "mosi", V_88F6920_PLUS), MPP_VAR_FUNCTION(6, "ua1", "txd", V_88F6920_PLUS)), MPP_MODE(57, diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-xp.c b/drivers/pinctrl/mvebu/pinctrl-armada-xp.c index d7cdb14..93b0485 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-xp.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-xp.c @@ -152,7 +152,7 @@ static struct mvebu_mpp_mode armada_xp_mpp_modes[] = { MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), MPP_VAR_FUNCTION(0x1, "ge0", "rxd5", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x2, "ge1", "rxd3", V_MV78230_PLUS), - MPP_VAR_FUNCTION(0x3, "mem", "bat", V_MV78230_PLUS), + MPP_VAR_FUNCTION(0x3, "dram", "bat", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x4, "lcd", "d21", V_MV78230_PLUS)), MPP_MODE(22, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), @@ -211,7 +211,7 @@ static struct mvebu_mpp_mode armada_xp_mpp_modes[] = { MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), MPP_VAR_FUNCTION(0x1, "sd0", "d1", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x3, "tdm", "int4", V_MV78230_PLUS), - MPP_VAR_FUNCTION(0x4, "mem", "bat", V_MV78230_PLUS)), + MPP_VAR_FUNCTION(0x4, "dram", "bat", V_MV78230_PLUS)), MPP_MODE(34, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), MPP_VAR_FUNCTION(0x1, "sd0", "d2", V_MV78230_PLUS), @@ -264,7 +264,7 @@ static struct mvebu_mpp_mode armada_xp_mpp_modes[] = { MPP_VAR_FUNCTION(0x1, "uart2", "cts", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x2, "uart3", "rxd", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x3, "spi", "cs4", V_MV78230_PLUS), - MPP_VAR_FUNCTION(0x4, "mem", "bat", V_MV78230_PLUS), + MPP_VAR_FUNCTION(0x4, "dram", "bat", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x5, "pcie", "clkreq2", V_MV78230_PLUS)), MPP_MODE(45, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), -- cgit v0.10.2 From 52f83174b3a142a7574f7aa652dcff773c50f5f1 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 9 Jun 2015 18:47:04 +0200 Subject: pinctrl: mvebu: armada-39x: normalize SATA present functionality naming This commit makes the naming of SATA related MPP functions consistent accross SoCs by adjusting the Armada 39x definition to use "prsnt" instead of "present". Since only the subnames are changed, the DT binding is not modified at all. Signed-off-by: Thomas Petazzoni Signed-off-by: Linus Walleij diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-39x-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-39x-pinctrl.txt index 8271cd2..46f7a5d 100644 --- a/Documentation/devicetree/bindings/pinctrl/marvell,armada-39x-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-39x-pinctrl.txt @@ -33,9 +33,9 @@ mpp15 15 gpio, pcie0(rstout), spi0(mosi), i2c1(sck) mpp16 16 gpio, dram(deccerr), spi0(miso), i2c1(sda) mpp17 17 gpio, ua1(rxd), spi0(sck), smi(mdio) mpp18 18 gpio, ua1(txd), spi0(cs0), i2c2(sck) -mpp19 19 gpio, sata1(present) [1], ua0(cts), ua1(rxd), i2c2(sda) -mpp20 20 gpio, sata0(present) [1], ua0(rts), ua1(txd), smi(mdc) -mpp21 21 gpio, spi0(cs1), sata0(present) [1], sd(cmd), dev(bootcs), ge(rxd0) +mpp19 19 gpio, sata1(prsnt) [1], ua0(cts), ua1(rxd), i2c2(sda) +mpp20 20 gpio, sata0(prsnt) [1], ua0(rts), ua1(txd), smi(mdc) +mpp21 21 gpio, spi0(cs1), sata0(prsnt) [1], sd(cmd), dev(bootcs), ge(rxd0) mpp22 22 gpio, spi0(mosi), dev(ad0) mpp23 23 gpio, spi0(sck), dev(ad2) mpp24 24 gpio, spi0(miso), ua0(cts), ua1(rxd), sd(d4), dev(readyn) @@ -58,17 +58,17 @@ mpp40 40 gpio, i2c1(sda), ua0(rts), sd(d2), dev(ad6), ge(rxd3) mpp41 41 gpio, ua1(rxd), ua0(cts), spi1(cs3), dev(burstn), nd(rbn0), ge(rxctl) mpp42 42 gpio, ua1(txd), ua0(rts), dev(ad7) mpp43 43 gpio, pcie0(clkreq), dram(vttctrl), dram(deccerr), spi1(cs2), dev(clkout), nd(rbn1) -mpp44 44 gpio, sata0(present) [1], sata1(present) [1], led(clk) +mpp44 44 gpio, sata0(prsnt) [1], sata1(prsnt) [1], led(clk) mpp45 45 gpio, ref(clk), pcie0(rstout), ua1(rxd) mpp46 46 gpio, ref(clk), pcie0(rstout), ua1(txd), led(stb) -mpp47 47 gpio, sata0(present) [1], sata1(present) [1], led(data) -mpp48 48 gpio, sata0(present) [1], dram(vttctrl), tdm(pclk) [1], audio(mclk) [1], sd(d4), pcie0(clkreq), ua1(txd) +mpp47 47 gpio, sata0(prsnt) [1], sata1(prsnt) [1], led(data) +mpp48 48 gpio, sata0(prsnt) [1], dram(vttctrl), tdm(pclk) [1], audio(mclk) [1], sd(d4), pcie0(clkreq), ua1(txd) mpp49 49 gpio, tdm(fsync) [1], audio(lrclk) [1], sd(d5), ua2(rxd) mpp50 50 gpio, pcie0(rstout), tdm(drx) [1], audio(extclk) [1], sd(cmd), ua2(rxd) mpp51 51 gpio, tdm(dtx) [1], audio(sdo) [1], dram(deccerr), ua2(txd) mpp52 52 gpio, pcie0(rstout), tdm(intn) [1], audio(sdi) [1], sd(d6), i2c3(sck) -mpp53 53 gpio, sata1(present) [1], sata0(present) [1], tdm(rstn) [1], audio(bclk) [1], sd(d7), i2c3(sda) -mpp54 54 gpio, sata0(present) [1], sata1(present) [1], pcie0(rstout), sd(d3), ua3(txd) +mpp53 53 gpio, sata1(prsnt) [1], sata0(prsnt) [1], tdm(rstn) [1], audio(bclk) [1], sd(d7), i2c3(sda) +mpp54 54 gpio, sata0(prsnt) [1], sata1(prsnt) [1], pcie0(rstout), sd(d3), ua3(txd) mpp55 55 gpio, ua1(cts), spi1(cs1), sd(d0), ua1(rxd), ua3(rxd) mpp56 56 gpio, ua1(rts), dram(deccerr), spi1(mosi), ua1(txd) mpp57 57 gpio, spi1(sck), sd(clk), ua1(txd) diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-39x.c b/drivers/pinctrl/mvebu/pinctrl-armada-39x.c index 7cbc3fb..f6cc7f1 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-39x.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-39x.c @@ -123,20 +123,20 @@ static struct mvebu_mpp_mode armada_39x_mpp_modes[] = { MPP_VAR_FUNCTION(7, "i2c2", "sck", V_88F6920_PLUS)), MPP_MODE(19, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), - MPP_VAR_FUNCTION(4, "sata1", "present", V_88F6928), + MPP_VAR_FUNCTION(4, "sata1", "prsnt", V_88F6928), MPP_VAR_FUNCTION(5, "ua0", "cts", V_88F6920_PLUS), MPP_VAR_FUNCTION(6, "ua1", "rxd", V_88F6920_PLUS), MPP_VAR_FUNCTION(7, "i2c2", "sda", V_88F6920_PLUS)), MPP_MODE(20, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), - MPP_VAR_FUNCTION(4, "sata0", "present", V_88F6928), + MPP_VAR_FUNCTION(4, "sata0", "prsnt", V_88F6928), MPP_VAR_FUNCTION(5, "ua0", "rts", V_88F6920_PLUS), MPP_VAR_FUNCTION(6, "ua1", "txd", V_88F6920_PLUS), MPP_VAR_FUNCTION(7, "smi", "mdc", V_88F6920_PLUS)), MPP_MODE(21, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), MPP_VAR_FUNCTION(1, "spi0", "cs1", V_88F6920_PLUS), - MPP_VAR_FUNCTION(3, "sata0", "present", V_88F6928), + MPP_VAR_FUNCTION(3, "sata0", "prsnt", V_88F6928), MPP_VAR_FUNCTION(4, "sd", "cmd", V_88F6920_PLUS), MPP_VAR_FUNCTION(5, "dev", "bootcs", V_88F6920_PLUS), MPP_VAR_FUNCTION(8, "ge", "rxd0", V_88F6920_PLUS)), @@ -258,8 +258,8 @@ static struct mvebu_mpp_mode armada_39x_mpp_modes[] = { MPP_VAR_FUNCTION(6, "nd", "rbn1", V_88F6920_PLUS)), MPP_MODE(44, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), - MPP_VAR_FUNCTION(1, "sata0", "present", V_88F6928), - MPP_VAR_FUNCTION(2, "sata1", "present", V_88F6928), + MPP_VAR_FUNCTION(1, "sata0", "prsnt", V_88F6928), + MPP_VAR_FUNCTION(2, "sata1", "prsnt", V_88F6928), MPP_VAR_FUNCTION(7, "led", "clk", V_88F6920_PLUS)), MPP_MODE(45, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), @@ -274,12 +274,12 @@ static struct mvebu_mpp_mode armada_39x_mpp_modes[] = { MPP_VAR_FUNCTION(7, "led", "stb", V_88F6920_PLUS)), MPP_MODE(47, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), - MPP_VAR_FUNCTION(1, "sata0", "present", V_88F6928), - MPP_VAR_FUNCTION(2, "sata1", "present", V_88F6928), + MPP_VAR_FUNCTION(1, "sata0", "prsnt", V_88F6928), + MPP_VAR_FUNCTION(2, "sata1", "prsnt", V_88F6928), MPP_VAR_FUNCTION(7, "led", "data", V_88F6920_PLUS)), MPP_MODE(48, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), - MPP_VAR_FUNCTION(1, "sata0", "present", V_88F6928), + MPP_VAR_FUNCTION(1, "sata0", "prsnt", V_88F6928), MPP_VAR_FUNCTION(2, "dram", "vttctrl", V_88F6920_PLUS), MPP_VAR_FUNCTION(3, "tdm", "pclk", V_88F6928), MPP_VAR_FUNCTION(4, "audio", "mclk", V_88F6928), @@ -314,16 +314,16 @@ static struct mvebu_mpp_mode armada_39x_mpp_modes[] = { MPP_VAR_FUNCTION(7, "i2c3", "sck", V_88F6920_PLUS)), MPP_MODE(53, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), - MPP_VAR_FUNCTION(1, "sata1", "present", V_88F6928), - MPP_VAR_FUNCTION(2, "sata0", "present", V_88F6928), + MPP_VAR_FUNCTION(1, "sata1", "prsnt", V_88F6928), + MPP_VAR_FUNCTION(2, "sata0", "prsnt", V_88F6928), MPP_VAR_FUNCTION(3, "tdm", "rstn", V_88F6928), MPP_VAR_FUNCTION(4, "audio", "bclk", V_88F6928), MPP_VAR_FUNCTION(5, "sd", "d7", V_88F6920_PLUS), MPP_VAR_FUNCTION(7, "i2c3", "sda", V_88F6920_PLUS)), MPP_MODE(54, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), - MPP_VAR_FUNCTION(1, "sata0", "present", V_88F6928), - MPP_VAR_FUNCTION(2, "sata1", "present", V_88F6928), + MPP_VAR_FUNCTION(1, "sata0", "prsnt", V_88F6928), + MPP_VAR_FUNCTION(2, "sata1", "prsnt", V_88F6928), MPP_VAR_FUNCTION(3, "pcie0", "rstout", V_88F6920_PLUS), MPP_VAR_FUNCTION(5, "sd", "d3", V_88F6920_PLUS), MPP_VAR_FUNCTION(7, "ua3", "txd", V_88F6920_PLUS)), -- cgit v0.10.2 From ddf3f19e21ab4472c3ce4aa53dc2d28d4aa07e02 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 9 Jun 2015 18:47:05 +0200 Subject: pinctrl: mvebu: armada-39x: normalize SDIO pin naming In order to be consistent with the datasheet and some other SoCs, this commit renames the SDIO pins of the Armada 39x from "sd" to "sd0". While this changes the DT binding, this is not a problem since Armada 39x is a brand new SoC which isn't used in production yet (so now is the right time to fix such things). Signed-off-by: Thomas Petazzoni Signed-off-by: Linus Walleij diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-39x-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-39x-pinctrl.txt index 46f7a5d..d36cb94 100644 --- a/Documentation/devicetree/bindings/pinctrl/marvell,armada-39x-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-39x-pinctrl.txt @@ -35,14 +35,14 @@ mpp17 17 gpio, ua1(rxd), spi0(sck), smi(mdio) mpp18 18 gpio, ua1(txd), spi0(cs0), i2c2(sck) mpp19 19 gpio, sata1(prsnt) [1], ua0(cts), ua1(rxd), i2c2(sda) mpp20 20 gpio, sata0(prsnt) [1], ua0(rts), ua1(txd), smi(mdc) -mpp21 21 gpio, spi0(cs1), sata0(prsnt) [1], sd(cmd), dev(bootcs), ge(rxd0) +mpp21 21 gpio, spi0(cs1), sata0(prsnt) [1], sd0(cmd), dev(bootcs), ge(rxd0) mpp22 22 gpio, spi0(mosi), dev(ad0) mpp23 23 gpio, spi0(sck), dev(ad2) -mpp24 24 gpio, spi0(miso), ua0(cts), ua1(rxd), sd(d4), dev(readyn) -mpp25 25 gpio, spi0(cs0), ua0(rts), ua1(txd), sd(d5), dev(cs0) -mpp26 26 gpio, spi0(cs2), i2c1(sck), sd(d6), dev(cs1) -mpp27 27 gpio, spi0(cs3), i2c1(sda), sd(d7), dev(cs2), ge(txclkout) -mpp28 28 gpio, sd(clk), dev(ad5), ge(txd0) +mpp24 24 gpio, spi0(miso), ua0(cts), ua1(rxd), sd0(d4), dev(readyn) +mpp25 25 gpio, spi0(cs0), ua0(rts), ua1(txd), sd0(d5), dev(cs0) +mpp26 26 gpio, spi0(cs2), i2c1(sck), sd0(d6), dev(cs1) +mpp27 27 gpio, spi0(cs3), i2c1(sda), sd0(d7), dev(cs2), ge(txclkout) +mpp28 28 gpio, sd0(clk), dev(ad5), ge(txd0) mpp29 29 gpio, dev(ale0), ge(txd1) mpp30 30 gpio, dev(oen), ge(txd2) mpp31 31 gpio, dev(ale1), ge(txd3) @@ -51,10 +51,10 @@ mpp33 33 gpio, dram(deccerr), dev(ad3) mpp34 34 gpio, dev(ad1) mpp35 35 gpio, ref(clk), dev(a1) mpp36 36 gpio, dev(a0) -mpp37 37 gpio, sd(d3), dev(ad8), ge(rxclk) -mpp38 38 gpio, ref(clk), sd(d0), dev(ad4), ge(rxd1) -mpp39 39 gpio, i2c1(sck), ua0(cts), sd(d1), dev(a2), ge(rxd2) -mpp40 40 gpio, i2c1(sda), ua0(rts), sd(d2), dev(ad6), ge(rxd3) +mpp37 37 gpio, sd0(d3), dev(ad8), ge(rxclk) +mpp38 38 gpio, ref(clk), sd0(d0), dev(ad4), ge(rxd1) +mpp39 39 gpio, i2c1(sck), ua0(cts), sd0(d1), dev(a2), ge(rxd2) +mpp40 40 gpio, i2c1(sda), ua0(rts), sd0(d2), dev(ad6), ge(rxd3) mpp41 41 gpio, ua1(rxd), ua0(cts), spi1(cs3), dev(burstn), nd(rbn0), ge(rxctl) mpp42 42 gpio, ua1(txd), ua0(rts), dev(ad7) mpp43 43 gpio, pcie0(clkreq), dram(vttctrl), dram(deccerr), spi1(cs2), dev(clkout), nd(rbn1) @@ -62,17 +62,17 @@ mpp44 44 gpio, sata0(prsnt) [1], sata1(prsnt) [1], led(clk) mpp45 45 gpio, ref(clk), pcie0(rstout), ua1(rxd) mpp46 46 gpio, ref(clk), pcie0(rstout), ua1(txd), led(stb) mpp47 47 gpio, sata0(prsnt) [1], sata1(prsnt) [1], led(data) -mpp48 48 gpio, sata0(prsnt) [1], dram(vttctrl), tdm(pclk) [1], audio(mclk) [1], sd(d4), pcie0(clkreq), ua1(txd) -mpp49 49 gpio, tdm(fsync) [1], audio(lrclk) [1], sd(d5), ua2(rxd) -mpp50 50 gpio, pcie0(rstout), tdm(drx) [1], audio(extclk) [1], sd(cmd), ua2(rxd) +mpp48 48 gpio, sata0(prsnt) [1], dram(vttctrl), tdm(pclk) [1], audio(mclk) [1], sd0(d4), pcie0(clkreq), ua1(txd) +mpp49 49 gpio, tdm(fsync) [1], audio(lrclk) [1], sd0(d5), ua2(rxd) +mpp50 50 gpio, pcie0(rstout), tdm(drx) [1], audio(extclk) [1], sd0(cmd), ua2(rxd) mpp51 51 gpio, tdm(dtx) [1], audio(sdo) [1], dram(deccerr), ua2(txd) -mpp52 52 gpio, pcie0(rstout), tdm(intn) [1], audio(sdi) [1], sd(d6), i2c3(sck) -mpp53 53 gpio, sata1(prsnt) [1], sata0(prsnt) [1], tdm(rstn) [1], audio(bclk) [1], sd(d7), i2c3(sda) -mpp54 54 gpio, sata0(prsnt) [1], sata1(prsnt) [1], pcie0(rstout), sd(d3), ua3(txd) -mpp55 55 gpio, ua1(cts), spi1(cs1), sd(d0), ua1(rxd), ua3(rxd) +mpp52 52 gpio, pcie0(rstout), tdm(intn) [1], audio(sdi) [1], sd0(d6), i2c3(sck) +mpp53 53 gpio, sata1(prsnt) [1], sata0(prsnt) [1], tdm(rstn) [1], audio(bclk) [1], sd0(d7), i2c3(sda) +mpp54 54 gpio, sata0(prsnt) [1], sata1(prsnt) [1], pcie0(rstout), sd0(d3), ua3(txd) +mpp55 55 gpio, ua1(cts), spi1(cs1), sd0(d0), ua1(rxd), ua3(rxd) mpp56 56 gpio, ua1(rts), dram(deccerr), spi1(mosi), ua1(txd) -mpp57 57 gpio, spi1(sck), sd(clk), ua1(txd) -mpp58 58 gpio, i2c1(sck), pcie2(clkreq), spi1(miso), sd(d1), ua1(rxd) -mpp59 59 gpio, pcie0(rstout), i2c1(sda), spi1(cs0), sd(d2) +mpp57 57 gpio, spi1(sck), sd0(clk), ua1(txd) +mpp58 58 gpio, i2c1(sck), pcie2(clkreq), spi1(miso), sd0(d1), ua1(rxd) +mpp59 59 gpio, pcie0(rstout), i2c1(sda), spi1(cs0), sd0(d2) [1]: only available on 88F6928 diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-39x.c b/drivers/pinctrl/mvebu/pinctrl-armada-39x.c index f6cc7f1..fa3042a 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-39x.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-39x.c @@ -137,7 +137,7 @@ static struct mvebu_mpp_mode armada_39x_mpp_modes[] = { MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), MPP_VAR_FUNCTION(1, "spi0", "cs1", V_88F6920_PLUS), MPP_VAR_FUNCTION(3, "sata0", "prsnt", V_88F6928), - MPP_VAR_FUNCTION(4, "sd", "cmd", V_88F6920_PLUS), + MPP_VAR_FUNCTION(4, "sd0", "cmd", V_88F6920_PLUS), MPP_VAR_FUNCTION(5, "dev", "bootcs", V_88F6920_PLUS), MPP_VAR_FUNCTION(8, "ge", "rxd0", V_88F6920_PLUS)), MPP_MODE(22, @@ -153,31 +153,31 @@ static struct mvebu_mpp_mode armada_39x_mpp_modes[] = { MPP_VAR_FUNCTION(1, "spi0", "miso", V_88F6920_PLUS), MPP_VAR_FUNCTION(2, "ua0", "cts", V_88F6920_PLUS), MPP_VAR_FUNCTION(3, "ua1", "rxd", V_88F6920_PLUS), - MPP_VAR_FUNCTION(4, "sd", "d4", V_88F6920_PLUS), + MPP_VAR_FUNCTION(4, "sd0", "d4", V_88F6920_PLUS), MPP_VAR_FUNCTION(5, "dev", "readyn", V_88F6920_PLUS)), MPP_MODE(25, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), MPP_VAR_FUNCTION(1, "spi0", "cs0", V_88F6920_PLUS), MPP_VAR_FUNCTION(2, "ua0", "rts", V_88F6920_PLUS), MPP_VAR_FUNCTION(3, "ua1", "txd", V_88F6920_PLUS), - MPP_VAR_FUNCTION(4, "sd", "d5", V_88F6920_PLUS), + MPP_VAR_FUNCTION(4, "sd0", "d5", V_88F6920_PLUS), MPP_VAR_FUNCTION(5, "dev", "cs0", V_88F6920_PLUS)), MPP_MODE(26, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), MPP_VAR_FUNCTION(1, "spi0", "cs2", V_88F6920_PLUS), MPP_VAR_FUNCTION(3, "i2c1", "sck", V_88F6920_PLUS), - MPP_VAR_FUNCTION(4, "sd", "d6", V_88F6920_PLUS), + MPP_VAR_FUNCTION(4, "sd0", "d6", V_88F6920_PLUS), MPP_VAR_FUNCTION(5, "dev", "cs1", V_88F6920_PLUS)), MPP_MODE(27, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), MPP_VAR_FUNCTION(1, "spi0", "cs3", V_88F6920_PLUS), MPP_VAR_FUNCTION(3, "i2c1", "sda", V_88F6920_PLUS), - MPP_VAR_FUNCTION(4, "sd", "d7", V_88F6920_PLUS), + MPP_VAR_FUNCTION(4, "sd0", "d7", V_88F6920_PLUS), MPP_VAR_FUNCTION(5, "dev", "cs2", V_88F6920_PLUS), MPP_VAR_FUNCTION(8, "ge", "txclkout", V_88F6920_PLUS)), MPP_MODE(28, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), - MPP_VAR_FUNCTION(4, "sd", "clk", V_88F6920_PLUS), + MPP_VAR_FUNCTION(4, "sd0", "clk", V_88F6920_PLUS), MPP_VAR_FUNCTION(5, "dev", "ad5", V_88F6920_PLUS), MPP_VAR_FUNCTION(8, "ge", "txd0", V_88F6920_PLUS)), MPP_MODE(29, @@ -212,27 +212,27 @@ static struct mvebu_mpp_mode armada_39x_mpp_modes[] = { MPP_VAR_FUNCTION(5, "dev", "a0", V_88F6920_PLUS)), MPP_MODE(37, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), - MPP_VAR_FUNCTION(4, "sd", "d3", V_88F6920_PLUS), + MPP_VAR_FUNCTION(4, "sd0", "d3", V_88F6920_PLUS), MPP_VAR_FUNCTION(5, "dev", "ad8", V_88F6920_PLUS), MPP_VAR_FUNCTION(8, "ge", "rxclk", V_88F6920_PLUS)), MPP_MODE(38, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), MPP_VAR_FUNCTION(3, "ref", "clk", V_88F6920_PLUS), - MPP_VAR_FUNCTION(4, "sd", "d0", V_88F6920_PLUS), + MPP_VAR_FUNCTION(4, "sd0", "d0", V_88F6920_PLUS), MPP_VAR_FUNCTION(5, "dev", "ad4", V_88F6920_PLUS), MPP_VAR_FUNCTION(8, "ge", "rxd1", V_88F6920_PLUS)), MPP_MODE(39, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), MPP_VAR_FUNCTION(1, "i2c1", "sck", V_88F6920_PLUS), MPP_VAR_FUNCTION(3, "ua0", "cts", V_88F6920_PLUS), - MPP_VAR_FUNCTION(4, "sd", "d1", V_88F6920_PLUS), + MPP_VAR_FUNCTION(4, "sd0", "d1", V_88F6920_PLUS), MPP_VAR_FUNCTION(5, "dev", "a2", V_88F6920_PLUS), MPP_VAR_FUNCTION(8, "ge", "rxd2", V_88F6920_PLUS)), MPP_MODE(40, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), MPP_VAR_FUNCTION(1, "i2c1", "sda", V_88F6920_PLUS), MPP_VAR_FUNCTION(3, "ua0", "rts", V_88F6920_PLUS), - MPP_VAR_FUNCTION(4, "sd", "d2", V_88F6920_PLUS), + MPP_VAR_FUNCTION(4, "sd0", "d2", V_88F6920_PLUS), MPP_VAR_FUNCTION(5, "dev", "ad6", V_88F6920_PLUS), MPP_VAR_FUNCTION(8, "ge", "rxd3", V_88F6920_PLUS)), MPP_MODE(41, @@ -283,21 +283,21 @@ static struct mvebu_mpp_mode armada_39x_mpp_modes[] = { MPP_VAR_FUNCTION(2, "dram", "vttctrl", V_88F6920_PLUS), MPP_VAR_FUNCTION(3, "tdm", "pclk", V_88F6928), MPP_VAR_FUNCTION(4, "audio", "mclk", V_88F6928), - MPP_VAR_FUNCTION(5, "sd", "d4", V_88F6920_PLUS), + MPP_VAR_FUNCTION(5, "sd0", "d4", V_88F6920_PLUS), MPP_VAR_FUNCTION(6, "pcie0", "clkreq", V_88F6920_PLUS), MPP_VAR_FUNCTION(7, "ua1", "txd", V_88F6920_PLUS)), MPP_MODE(49, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), MPP_VAR_FUNCTION(3, "tdm", "fsync", V_88F6928), MPP_VAR_FUNCTION(4, "audio", "lrclk", V_88F6928), - MPP_VAR_FUNCTION(5, "sd", "d5", V_88F6920_PLUS), + MPP_VAR_FUNCTION(5, "sd0", "d5", V_88F6920_PLUS), MPP_VAR_FUNCTION(7, "ua2", "rxd", V_88F6920_PLUS)), MPP_MODE(50, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), MPP_VAR_FUNCTION(1, "pcie0", "rstout", V_88F6920_PLUS), MPP_VAR_FUNCTION(3, "tdm", "drx", V_88F6928), MPP_VAR_FUNCTION(4, "audio", "extclk", V_88F6928), - MPP_VAR_FUNCTION(5, "sd", "cmd", V_88F6920_PLUS), + MPP_VAR_FUNCTION(5, "sd0", "cmd", V_88F6920_PLUS), MPP_VAR_FUNCTION(7, "ua2", "rxd", V_88F6920_PLUS)), MPP_MODE(51, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), @@ -310,7 +310,7 @@ static struct mvebu_mpp_mode armada_39x_mpp_modes[] = { MPP_VAR_FUNCTION(1, "pcie0", "rstout", V_88F6920_PLUS), MPP_VAR_FUNCTION(3, "tdm", "intn", V_88F6928), MPP_VAR_FUNCTION(4, "audio", "sdi", V_88F6928), - MPP_VAR_FUNCTION(5, "sd", "d6", V_88F6920_PLUS), + MPP_VAR_FUNCTION(5, "sd0", "d6", V_88F6920_PLUS), MPP_VAR_FUNCTION(7, "i2c3", "sck", V_88F6920_PLUS)), MPP_MODE(53, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), @@ -318,20 +318,20 @@ static struct mvebu_mpp_mode armada_39x_mpp_modes[] = { MPP_VAR_FUNCTION(2, "sata0", "prsnt", V_88F6928), MPP_VAR_FUNCTION(3, "tdm", "rstn", V_88F6928), MPP_VAR_FUNCTION(4, "audio", "bclk", V_88F6928), - MPP_VAR_FUNCTION(5, "sd", "d7", V_88F6920_PLUS), + MPP_VAR_FUNCTION(5, "sd0", "d7", V_88F6920_PLUS), MPP_VAR_FUNCTION(7, "i2c3", "sda", V_88F6920_PLUS)), MPP_MODE(54, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), MPP_VAR_FUNCTION(1, "sata0", "prsnt", V_88F6928), MPP_VAR_FUNCTION(2, "sata1", "prsnt", V_88F6928), MPP_VAR_FUNCTION(3, "pcie0", "rstout", V_88F6920_PLUS), - MPP_VAR_FUNCTION(5, "sd", "d3", V_88F6920_PLUS), + MPP_VAR_FUNCTION(5, "sd0", "d3", V_88F6920_PLUS), MPP_VAR_FUNCTION(7, "ua3", "txd", V_88F6920_PLUS)), MPP_MODE(55, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), MPP_VAR_FUNCTION(1, "ua1", "cts", V_88F6920_PLUS), MPP_VAR_FUNCTION(4, "spi1", "cs1", V_88F6920_PLUS), - MPP_VAR_FUNCTION(5, "sd", "d0", V_88F6920_PLUS), + MPP_VAR_FUNCTION(5, "sd0", "d0", V_88F6920_PLUS), MPP_VAR_FUNCTION(6, "ua1", "rxd", V_88F6920_PLUS), MPP_VAR_FUNCTION(7, "ua3", "rxd", V_88F6920_PLUS)), MPP_MODE(56, @@ -343,21 +343,21 @@ static struct mvebu_mpp_mode armada_39x_mpp_modes[] = { MPP_MODE(57, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), MPP_VAR_FUNCTION(4, "spi1", "sck", V_88F6920_PLUS), - MPP_VAR_FUNCTION(5, "sd", "clk", V_88F6920_PLUS), + MPP_VAR_FUNCTION(5, "sd0", "clk", V_88F6920_PLUS), MPP_VAR_FUNCTION(6, "ua1", "txd", V_88F6920_PLUS)), MPP_MODE(58, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), MPP_VAR_FUNCTION(2, "i2c1", "sck", V_88F6920_PLUS), MPP_VAR_FUNCTION(3, "pcie2", "clkreq", V_88F6920_PLUS), MPP_VAR_FUNCTION(4, "spi1", "miso", V_88F6920_PLUS), - MPP_VAR_FUNCTION(5, "sd", "d1", V_88F6920_PLUS), + MPP_VAR_FUNCTION(5, "sd0", "d1", V_88F6920_PLUS), MPP_VAR_FUNCTION(6, "ua1", "rxd", V_88F6920_PLUS)), MPP_MODE(59, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), MPP_VAR_FUNCTION(1, "pcie0", "rstout", V_88F6920_PLUS), MPP_VAR_FUNCTION(2, "i2c1", "sda", V_88F6920_PLUS), MPP_VAR_FUNCTION(4, "spi1", "cs0", V_88F6920_PLUS), - MPP_VAR_FUNCTION(5, "sd", "d2", V_88F6920_PLUS)), + MPP_VAR_FUNCTION(5, "sd0", "d2", V_88F6920_PLUS)), }; static struct mvebu_pinctrl_soc_info armada_39x_pinctrl_info; -- cgit v0.10.2 From 7bd6a26db6f9dade7dbd88a73120d17da1ee0e89 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 9 Jun 2015 18:47:06 +0200 Subject: pinctrl: mvebu: armada-{370,375,38x,39x}: normalize dev pins This commit modifies the definition of the Device Bus interface pins to be consistent accross SoCs. Especially, it removes the 'n' indicators that we don't encode in the subnames of pins: 'dev(wen0)' becomes 'dev(we0)' 'dev(wen1)' becomes 'dev(we1)' 'dev(oen)' becomes 'dev(oe)' etc. In addition, it fixes the Armada 375 DT binding documentation, which forgot to document the 'dev' function for MPP46, MPP57 and MPP63. Since only the subnames are changed, this commit does not affect DT compatibility. Signed-off-by: Thomas Petazzoni Signed-off-by: Linus Walleij diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt index e357b02..183c472 100644 --- a/Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt @@ -52,8 +52,8 @@ mpp30 30 gpio, ge0(rxd7), ge1(rxclk), i2c1(sck) mpp31 31 gpio, tclk, ge0(txerr) mpp32 32 gpio, spi0(cs0) mpp33 33 gpio, dev(bootcs), spi0(cs0) -mpp34 34 gpo, dev(wen0), spi0(mosi) -mpp35 35 gpo, dev(oen), spi0(sck) +mpp34 34 gpo, dev(we0), spi0(mosi) +mpp35 35 gpo, dev(oe), spi0(sck) mpp36 36 gpo, dev(a1), spi0(miso) mpp37 37 gpo, dev(a0), sata0(prsnt) mpp38 38 gpio, dev(ready), uart1(cts), uart0(cts) @@ -88,7 +88,7 @@ mpp58 58 gpio, dev(cs0), uart1(rts), tdm(int), audio(extclk), mpp59 59 gpo, dev(ale0), uart1(rts), uart0(rts), audio(bclk) mpp60 60 gpio, dev(ale1), uart1(rxd), sata0(prsnt), pcie(rst-out), audio(sdi) -mpp61 61 gpo, dev(wen1), uart1(txd), audio(rclk) +mpp61 61 gpo, dev(we1), uart1(txd), audio(rclk) mpp62 62 gpio, dev(a2), uart1(cts), tdm(drx), pcie(clkreq0), audio(mclk), uart0(cts) mpp63 63 gpo, spi0(sck), tclk diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-375-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-375-pinctrl.txt index e22ec5e..ce1771b 100644 --- a/Documentation/devicetree/bindings/pinctrl/marvell,armada-375-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-375-pinctrl.txt @@ -26,7 +26,7 @@ mpp9 9 gpio, spi0(sck), spi1(sck), nand(we) mpp10 10 gpio, dram(vttctrl), led(c1), nand(re) mpp11 11 gpio, dev(a0), led(c2), audio(sdo) mpp12 12 gpio, dev(a1), audio(bclk) -mpp13 13 gpio, dev(readyn), pcie0(rstoutn), pcie1(rstoutn) +mpp13 13 gpio, dev(ready), pcie0(rstoutn), pcie1(rstoutn) mpp14 14 gpio, i2c0(sda), uart1(txd) mpp15 15 gpio, i2c0(sck), uart1(rxd) mpp16 16 gpio, uart0(txd) @@ -59,7 +59,7 @@ mpp42 42 gpio, spi1(cs2), led(c0) mpp43 43 gpio, sata0(prsnt), dram(vttctrl) mpp44 44 gpio, sata0(prsnt) mpp45 45 gpio, spi0(cs2), pcie0(rstoutn) -mpp46 46 gpio, led(p0), ge0(txd0), ge1(txd0) +mpp46 46 gpio, led(p0), ge0(txd0), ge1(txd0), dev(we1) mpp47 47 gpio, led(p1), ge0(txd1), ge1(txd1) mpp48 48 gpio, led(p2), ge0(txd2), ge1(txd2) mpp49 49 gpio, led(p3), ge0(txd3), ge1(txd3) @@ -70,13 +70,13 @@ mpp53 53 gpio, pcie1(rstoutn), ge0(rxd3), ge1(rxd3) mpp54 54 gpio, pcie0(rstoutn), ge0(rxctl), ge1(rxctl) mpp55 55 gpio, ge0(rxclk), ge1(rxclk) mpp56 56 gpio, ge0(txclkout), ge1(txclkout) -mpp57 57 gpio, ge0(txctl), ge1(txctl) +mpp57 57 gpio, ge0(txctl), ge1(txctl), dev(we0) mpp58 58 gpio, led(c0) mpp59 59 gpio, led(c1) mpp60 60 gpio, uart1(txd), led(c2) mpp61 61 gpio, i2c1(sda), uart1(rxd), spi1(cs2), led(p0) mpp62 62 gpio, i2c1(sck), led(p1) -mpp63 63 gpio, ptp(trig), led(p2) +mpp63 63 gpio, ptp(trig), led(p2), dev(burst/last) mpp64 64 gpio, dram(vttctrl), led(p3) mpp65 65 gpio, sata1(prsnt) mpp66 66 gpio, ptp(evreq), spi1(cs3) diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-38x-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-38x-pinctrl.txt index 4fb82c1..9844773 100644 --- a/Documentation/devicetree/bindings/pinctrl/marvell,armada-38x-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-38x-pinctrl.txt @@ -29,7 +29,7 @@ mpp10 10 gpio, ge0(txd3), dev(ad12) mpp11 11 gpio, ge0(txctl), dev(ad13) mpp12 12 gpio, ge0(rxd0), pcie0(rstout), spi0(cs1), dev(ad14), pcie3(clkreq) mpp13 13 gpio, ge0(rxd1), pcie0(clkreq), pcie1(clkreq) [1], spi0(cs2), dev(ad15), pcie2(clkreq) -mpp14 14 gpio, ge0(rxd2), ptp(clk), dram(vttctrl), spi0(cs3), dev(wen1), pcie3(clkreq) +mpp14 14 gpio, ge0(rxd2), ptp(clk), dram(vttctrl), spi0(cs3), dev(we1), pcie3(clkreq) mpp15 15 gpio, ge0(rxd3), ge(mdc slave), pcie0(rstout), spi0(mosi) mpp16 16 gpio, ge0(rxctl), ge(mdio slave), dram(deccerr), spi0(miso), pcie0(clkreq), pcie1(clkreq) [1] mpp17 17 gpio, ge0(rxclk), ptp(clk), ua1(rxd), spi0(sck), sata1(prsnt) @@ -45,9 +45,9 @@ mpp26 26 gpio, spi0(cs2), i2c1(sck), sd0(d6), dev(cs1) mpp27 27 gpio, spi0(cs3), ge1(txclkout), i2c1(sda), sd0(d7), dev(cs2) mpp28 28 gpio, ge1(txd0), sd0(clk), dev(ad5) mpp29 29 gpio, ge1(txd1), dev(ale0) -mpp30 30 gpio, ge1(txd2), dev(oen) +mpp30 30 gpio, ge1(txd2), dev(oe) mpp31 31 gpio, ge1(txd3), dev(ale1) -mpp32 32 gpio, ge1(txctl), dev(wen0) +mpp32 32 gpio, ge1(txctl), dev(we0) mpp33 33 gpio, dram(deccerr), dev(ad3) mpp34 34 gpio, dev(ad1) mpp35 35 gpio, ref(clk_out1), dev(a1) diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-39x-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-39x-pinctrl.txt index d36cb94..34af69e 100644 --- a/Documentation/devicetree/bindings/pinctrl/marvell,armada-39x-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-39x-pinctrl.txt @@ -28,7 +28,7 @@ mpp10 10 gpio, dev(ad12), ptp(evreq) mpp11 11 gpio, dev(ad13), led(clk) mpp12 12 gpio, pcie0(rstout), dev(ad14), led(stb) mpp13 13 gpio, dev(ad15), led(data) -mpp14 14 gpio, dram(vttctrl), dev(wen1), ua1(txd) +mpp14 14 gpio, dram(vttctrl), dev(we1), ua1(txd) mpp15 15 gpio, pcie0(rstout), spi0(mosi), i2c1(sck) mpp16 16 gpio, dram(deccerr), spi0(miso), i2c1(sda) mpp17 17 gpio, ua1(rxd), spi0(sck), smi(mdio) @@ -38,15 +38,15 @@ mpp20 20 gpio, sata0(prsnt) [1], ua0(rts), ua1(txd), smi(mdc) mpp21 21 gpio, spi0(cs1), sata0(prsnt) [1], sd0(cmd), dev(bootcs), ge(rxd0) mpp22 22 gpio, spi0(mosi), dev(ad0) mpp23 23 gpio, spi0(sck), dev(ad2) -mpp24 24 gpio, spi0(miso), ua0(cts), ua1(rxd), sd0(d4), dev(readyn) +mpp24 24 gpio, spi0(miso), ua0(cts), ua1(rxd), sd0(d4), dev(ready) mpp25 25 gpio, spi0(cs0), ua0(rts), ua1(txd), sd0(d5), dev(cs0) mpp26 26 gpio, spi0(cs2), i2c1(sck), sd0(d6), dev(cs1) mpp27 27 gpio, spi0(cs3), i2c1(sda), sd0(d7), dev(cs2), ge(txclkout) mpp28 28 gpio, sd0(clk), dev(ad5), ge(txd0) mpp29 29 gpio, dev(ale0), ge(txd1) -mpp30 30 gpio, dev(oen), ge(txd2) +mpp30 30 gpio, dev(oe), ge(txd2) mpp31 31 gpio, dev(ale1), ge(txd3) -mpp32 32 gpio, dev(wen0), ge(txctl) +mpp32 32 gpio, dev(we0), ge(txctl) mpp33 33 gpio, dram(deccerr), dev(ad3) mpp34 34 gpio, dev(ad1) mpp35 35 gpio, ref(clk), dev(a1) @@ -55,7 +55,7 @@ mpp37 37 gpio, sd0(d3), dev(ad8), ge(rxclk) mpp38 38 gpio, ref(clk), sd0(d0), dev(ad4), ge(rxd1) mpp39 39 gpio, i2c1(sck), ua0(cts), sd0(d1), dev(a2), ge(rxd2) mpp40 40 gpio, i2c1(sda), ua0(rts), sd0(d2), dev(ad6), ge(rxd3) -mpp41 41 gpio, ua1(rxd), ua0(cts), spi1(cs3), dev(burstn), nd(rbn0), ge(rxctl) +mpp41 41 gpio, ua1(rxd), ua0(cts), spi1(cs3), dev(burst/last), nd(rbn0), ge(rxctl) mpp42 42 gpio, ua1(txd), ua0(rts), dev(ad7) mpp43 43 gpio, pcie0(clkreq), dram(vttctrl), dram(deccerr), spi1(cs2), dev(clkout), nd(rbn1) mpp44 44 gpio, sata0(prsnt) [1], sata1(prsnt) [1], led(clk) diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-370.c b/drivers/pinctrl/mvebu/pinctrl-armada-370.c index 8516cad..7d2be71 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-370.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-370.c @@ -207,11 +207,11 @@ static struct mvebu_mpp_mode mv88f6710_mpp_modes[] = { MPP_FUNCTION(0x2, "spi0", "cs0")), MPP_MODE(34, MPP_FUNCTION(0x0, "gpo", NULL), - MPP_FUNCTION(0x1, "dev", "wen0"), + MPP_FUNCTION(0x1, "dev", "we0"), MPP_FUNCTION(0x2, "spi0", "mosi")), MPP_MODE(35, MPP_FUNCTION(0x0, "gpo", NULL), - MPP_FUNCTION(0x1, "dev", "oen"), + MPP_FUNCTION(0x1, "dev", "oe"), MPP_FUNCTION(0x2, "spi0", "sck")), MPP_MODE(36, MPP_FUNCTION(0x0, "gpo", NULL), @@ -352,7 +352,7 @@ static struct mvebu_mpp_mode mv88f6710_mpp_modes[] = { MPP_FUNCTION(0x5, "audio", "sdi")), MPP_MODE(61, MPP_FUNCTION(0x0, "gpo", NULL), - MPP_FUNCTION(0x1, "dev", "wen1"), + MPP_FUNCTION(0x1, "dev", "we1"), MPP_FUNCTION(0x2, "uart1", "txd"), MPP_FUNCTION(0x5, "audio", "rclk")), MPP_MODE(62, diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-375.c b/drivers/pinctrl/mvebu/pinctrl-armada-375.c index ba0913a..6dfe1bf 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-375.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-375.c @@ -120,7 +120,7 @@ static struct mvebu_mpp_mode mv88f6720_mpp_modes[] = { MPP_FUNCTION(0x5, "nand", "ale")), MPP_MODE(13, MPP_FUNCTION(0x0, "gpio", NULL), - MPP_FUNCTION(0x1, "dev", "readyn"), + MPP_FUNCTION(0x1, "dev", "ready"), MPP_FUNCTION(0x2, "pcie0", "rstoutn"), MPP_FUNCTION(0x3, "pcie1", "rstoutn"), MPP_FUNCTION(0x5, "nand", "rb"), @@ -284,7 +284,7 @@ static struct mvebu_mpp_mode mv88f6720_mpp_modes[] = { MPP_FUNCTION(0x1, "led", "p0"), MPP_FUNCTION(0x2, "ge0", "txd0"), MPP_FUNCTION(0x3, "ge1", "txd0"), - MPP_FUNCTION(0x6, "dev", "wen1")), + MPP_FUNCTION(0x6, "dev", "we1")), MPP_MODE(47, MPP_FUNCTION(0x0, "gpio", NULL), MPP_FUNCTION(0x1, "led", "p1"), @@ -351,7 +351,7 @@ static struct mvebu_mpp_mode mv88f6720_mpp_modes[] = { MPP_FUNCTION(0x0, "gpio", NULL), MPP_FUNCTION(0x2, "ge0", "txctl"), MPP_FUNCTION(0x3, "ge1", "txctl"), - MPP_FUNCTION(0x6, "dev", "wen0")), + MPP_FUNCTION(0x6, "dev", "we0")), MPP_MODE(58, MPP_FUNCTION(0x0, "gpio", NULL), MPP_FUNCTION(0x4, "led", "c0")), @@ -379,7 +379,7 @@ static struct mvebu_mpp_mode mv88f6720_mpp_modes[] = { MPP_FUNCTION(0x0, "gpio", NULL), MPP_FUNCTION(0x2, "ptp", "trig"), MPP_FUNCTION(0x4, "led", "p2"), - MPP_FUNCTION(0x6, "dev", "burst")), + MPP_FUNCTION(0x6, "dev", "burst/last")), MPP_MODE(64, MPP_FUNCTION(0x0, "gpio", NULL), MPP_FUNCTION(0x2, "dram", "vttctrl"), diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-38x.c b/drivers/pinctrl/mvebu/pinctrl-armada-38x.c index 2b04923..793d0df 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-38x.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-38x.c @@ -111,7 +111,7 @@ static struct mvebu_mpp_mode armada_38x_mpp_modes[] = { MPP_VAR_FUNCTION(2, "ptp", "clk", V_88F6810_PLUS), MPP_VAR_FUNCTION(3, "dram", "vttctrl", V_88F6810_PLUS), MPP_VAR_FUNCTION(4, "spi0", "cs3", V_88F6810_PLUS), - MPP_VAR_FUNCTION(5, "dev", "wen1", V_88F6810_PLUS), + MPP_VAR_FUNCTION(5, "dev", "we1", V_88F6810_PLUS), MPP_VAR_FUNCTION(6, "pcie3", "clkreq", V_88F6810_PLUS)), MPP_MODE(15, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), @@ -209,7 +209,7 @@ static struct mvebu_mpp_mode armada_38x_mpp_modes[] = { MPP_MODE(30, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), MPP_VAR_FUNCTION(2, "ge1", "txd2", V_88F6810_PLUS), - MPP_VAR_FUNCTION(5, "dev", "oen", V_88F6810_PLUS)), + MPP_VAR_FUNCTION(5, "dev", "oe", V_88F6810_PLUS)), MPP_MODE(31, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), MPP_VAR_FUNCTION(2, "ge1", "txd3", V_88F6810_PLUS), @@ -217,7 +217,7 @@ static struct mvebu_mpp_mode armada_38x_mpp_modes[] = { MPP_MODE(32, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), MPP_VAR_FUNCTION(2, "ge1", "txctl", V_88F6810_PLUS), - MPP_VAR_FUNCTION(5, "dev", "wen0", V_88F6810_PLUS)), + MPP_VAR_FUNCTION(5, "dev", "we0", V_88F6810_PLUS)), MPP_MODE(33, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), MPP_VAR_FUNCTION(1, "dram", "deccerr", V_88F6810_PLUS), diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-39x.c b/drivers/pinctrl/mvebu/pinctrl-armada-39x.c index fa3042a..a5e3627 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-39x.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-39x.c @@ -99,7 +99,7 @@ static struct mvebu_mpp_mode armada_39x_mpp_modes[] = { MPP_MODE(14, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), MPP_VAR_FUNCTION(3, "dram", "vttctrl", V_88F6920_PLUS), - MPP_VAR_FUNCTION(5, "dev", "wen1", V_88F6920_PLUS), + MPP_VAR_FUNCTION(5, "dev", "we1", V_88F6920_PLUS), MPP_VAR_FUNCTION(7, "ua1", "txd", V_88F6920_PLUS)), MPP_MODE(15, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), @@ -154,7 +154,7 @@ static struct mvebu_mpp_mode armada_39x_mpp_modes[] = { MPP_VAR_FUNCTION(2, "ua0", "cts", V_88F6920_PLUS), MPP_VAR_FUNCTION(3, "ua1", "rxd", V_88F6920_PLUS), MPP_VAR_FUNCTION(4, "sd0", "d4", V_88F6920_PLUS), - MPP_VAR_FUNCTION(5, "dev", "readyn", V_88F6920_PLUS)), + MPP_VAR_FUNCTION(5, "dev", "ready", V_88F6920_PLUS)), MPP_MODE(25, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), MPP_VAR_FUNCTION(1, "spi0", "cs0", V_88F6920_PLUS), @@ -186,7 +186,7 @@ static struct mvebu_mpp_mode armada_39x_mpp_modes[] = { MPP_VAR_FUNCTION(8, "ge", "txd1", V_88F6920_PLUS)), MPP_MODE(30, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), - MPP_VAR_FUNCTION(5, "dev", "oen", V_88F6920_PLUS), + MPP_VAR_FUNCTION(5, "dev", "oe", V_88F6920_PLUS), MPP_VAR_FUNCTION(8, "ge", "txd2", V_88F6920_PLUS)), MPP_MODE(31, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), @@ -194,7 +194,7 @@ static struct mvebu_mpp_mode armada_39x_mpp_modes[] = { MPP_VAR_FUNCTION(8, "ge", "txd3", V_88F6920_PLUS)), MPP_MODE(32, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), - MPP_VAR_FUNCTION(5, "dev", "wen0", V_88F6920_PLUS), + MPP_VAR_FUNCTION(5, "dev", "we0", V_88F6920_PLUS), MPP_VAR_FUNCTION(8, "ge", "txctl", V_88F6920_PLUS)), MPP_MODE(33, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), @@ -240,7 +240,7 @@ static struct mvebu_mpp_mode armada_39x_mpp_modes[] = { MPP_VAR_FUNCTION(1, "ua1", "rxd", V_88F6920_PLUS), MPP_VAR_FUNCTION(3, "ua0", "cts", V_88F6920_PLUS), MPP_VAR_FUNCTION(4, "spi1", "cs3", V_88F6920_PLUS), - MPP_VAR_FUNCTION(5, "dev", "burstn", V_88F6920_PLUS), + MPP_VAR_FUNCTION(5, "dev", "burst/last", V_88F6920_PLUS), MPP_VAR_FUNCTION(6, "nd", "rbn0", V_88F6920_PLUS), MPP_VAR_FUNCTION(8, "ge", "rxctl", V_88F6920_PLUS)), MPP_MODE(42, -- cgit v0.10.2 From 5cc0de1faff6ac801286dfab88e4a31392cbb3f0 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 9 Jun 2015 18:47:07 +0200 Subject: pinctrl: mvebu: armada-39x: align NAND pin naming All SoCs use "nand" to designate NAND pins, only Armada 39x is using "nd", which is not consistent. This commit fixes that by renaming the corresponding functions. It also changes the subnames from rbn0/rbn1 to rb0/rb1, to respect the convention used everywhere that we don't encode the 'n' part of signal names. While this commit changes the main name of function, therefore potentially breaking the DT compatibility, this is not a problem since Armada 39x is a brand new SoC which isn't used in production yet. Signed-off-by: Thomas Petazzoni Signed-off-by: Linus Walleij diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-39x-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-39x-pinctrl.txt index 34af69e..b6bd9cc 100644 --- a/Documentation/devicetree/bindings/pinctrl/marvell,armada-39x-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-39x-pinctrl.txt @@ -55,9 +55,9 @@ mpp37 37 gpio, sd0(d3), dev(ad8), ge(rxclk) mpp38 38 gpio, ref(clk), sd0(d0), dev(ad4), ge(rxd1) mpp39 39 gpio, i2c1(sck), ua0(cts), sd0(d1), dev(a2), ge(rxd2) mpp40 40 gpio, i2c1(sda), ua0(rts), sd0(d2), dev(ad6), ge(rxd3) -mpp41 41 gpio, ua1(rxd), ua0(cts), spi1(cs3), dev(burst/last), nd(rbn0), ge(rxctl) +mpp41 41 gpio, ua1(rxd), ua0(cts), spi1(cs3), dev(burst/last), nand(rb0), ge(rxctl) mpp42 42 gpio, ua1(txd), ua0(rts), dev(ad7) -mpp43 43 gpio, pcie0(clkreq), dram(vttctrl), dram(deccerr), spi1(cs2), dev(clkout), nd(rbn1) +mpp43 43 gpio, pcie0(clkreq), dram(vttctrl), dram(deccerr), spi1(cs2), dev(clkout), nand(rb1) mpp44 44 gpio, sata0(prsnt) [1], sata1(prsnt) [1], led(clk) mpp45 45 gpio, ref(clk), pcie0(rstout), ua1(rxd) mpp46 46 gpio, ref(clk), pcie0(rstout), ua1(txd), led(stb) diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-39x.c b/drivers/pinctrl/mvebu/pinctrl-armada-39x.c index a5e3627..de91b35 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-39x.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-39x.c @@ -241,7 +241,7 @@ static struct mvebu_mpp_mode armada_39x_mpp_modes[] = { MPP_VAR_FUNCTION(3, "ua0", "cts", V_88F6920_PLUS), MPP_VAR_FUNCTION(4, "spi1", "cs3", V_88F6920_PLUS), MPP_VAR_FUNCTION(5, "dev", "burst/last", V_88F6920_PLUS), - MPP_VAR_FUNCTION(6, "nd", "rbn0", V_88F6920_PLUS), + MPP_VAR_FUNCTION(6, "nand", "rb0", V_88F6920_PLUS), MPP_VAR_FUNCTION(8, "ge", "rxctl", V_88F6920_PLUS)), MPP_MODE(42, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), @@ -255,7 +255,7 @@ static struct mvebu_mpp_mode armada_39x_mpp_modes[] = { MPP_VAR_FUNCTION(3, "dram", "deccerr", V_88F6920_PLUS), MPP_VAR_FUNCTION(4, "spi1", "cs2", V_88F6920_PLUS), MPP_VAR_FUNCTION(5, "dev", "clkout", V_88F6920_PLUS), - MPP_VAR_FUNCTION(6, "nd", "rbn1", V_88F6920_PLUS)), + MPP_VAR_FUNCTION(6, "nand", "rb1", V_88F6920_PLUS)), MPP_MODE(44, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), MPP_VAR_FUNCTION(1, "sata0", "prsnt", V_88F6928), -- cgit v0.10.2 From dae5597f253ae2d44432c8648d9a9205de057ddf Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 9 Jun 2015 18:47:08 +0200 Subject: pinctrl: mvebu: armada-{370,375,38x,39x,xp}: normalize TDM pins This commit normalizes the naming of the TDM pins accross the different Marvell SoCs. Mainly it consists in: * Removing the 'n' from signal names: 'intn' becomes 'int' and 'rstn' becomes 'rst' * Renaming the main name 'tdm2c' to 'tdm' on Armada 38x. * Change the main name 'tdm-1' to 'tdm' for one of the pins of the Armada XP The last two changes affect DT compatibility, but since the TDM interface is nowhere near being supported in mainline, it should not be considered to be a serious problem at this point. Signed-off-by: Thomas Petazzoni Signed-off-by: Linus Walleij diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt index 183c472..e6dce5d 100644 --- a/Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt @@ -20,7 +20,7 @@ mpp3 3 gpio, i2c0(sda), uart0(rxd) mpp4 4 gpio, cpu_pd(vdd) mpp5 5 gpo, ge0(txclko), uart1(txd), spi1(clk), audio(mclk) mpp6 6 gpio, ge0(txd0), sata0(prsnt), tdm(rst), audio(sdo) -mpp7 7 gpo, ge0(txd1), tdm(tdx), audio(lrclk) +mpp7 7 gpo, ge0(txd1), tdm(dtx), audio(lrclk) mpp8 8 gpio, ge0(txd2), uart0(rts), tdm(drx), audio(bclk) mpp9 9 gpo, ge0(txd3), uart1(txd), sd0(clk), audio(spdifo) mpp10 10 gpio, ge0(txctl), uart0(cts), tdm(fsync), audio(sdi) diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-375-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-375-pinctrl.txt index ce1771b..3140324 100644 --- a/Documentation/devicetree/bindings/pinctrl/marvell,armada-375-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-375-pinctrl.txt @@ -31,8 +31,8 @@ mpp14 14 gpio, i2c0(sda), uart1(txd) mpp15 15 gpio, i2c0(sck), uart1(rxd) mpp16 16 gpio, uart0(txd) mpp17 17 gpio, uart0(rxd) -mpp18 18 gpio, tdm(intn) -mpp19 19 gpio, tdm(rstn) +mpp18 18 gpio, tdm(int) +mpp19 19 gpio, tdm(rst) mpp20 20 gpio, tdm(pclk) mpp21 21 gpio, tdm(fsync) mpp22 22 gpio, tdm(drx) @@ -50,7 +50,7 @@ mpp33 33 gpio, ge1(txd3), spi1(miso) mpp34 34 gpio, ge1(txclkout), spi1(sck) mpp35 35 gpio, ge1(rxctl), spi1(cs1), spi0(cs2) mpp36 36 gpio, pcie0(clkreq) -mpp37 37 gpio, pcie0(clkreq), tdm(intn), ge(mdc) +mpp37 37 gpio, pcie0(clkreq), tdm(int), ge(mdc) mpp38 38 gpio, pcie1(clkreq), ge(mdio) mpp39 39 gpio, ref(clkout) mpp40 40 gpio, uart1(txd) diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-38x-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-38x-pinctrl.txt index 9844773..203220d 100644 --- a/Documentation/devicetree/bindings/pinctrl/marvell,armada-38x-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-38x-pinctrl.txt @@ -63,12 +63,12 @@ mpp44 44 gpio, sata0(prsnt), sata1(prsnt), sata2(prsnt) [2], sata3 mpp45 45 gpio, ref(clk_out0), pcie0(rstout) mpp46 46 gpio, ref(clk_out1), pcie0(rstout) mpp47 47 gpio, sata0(prsnt), sata1(prsnt), sata2(prsnt) [2], sata3(prsnt) [2] -mpp48 48 gpio, sata0(prsnt), dram(vttctrl), tdm2c(pclk), audio(mclk), sd0(d4), pcie0(clkreq) -mpp49 49 gpio, sata2(prsnt) [2], sata3(prsnt) [2], tdm2c(fsync), audio(lrclk), sd0(d5), pcie1(clkreq) -mpp50 50 gpio, pcie0(rstout), tdm2c(drx), audio(extclk), sd0(cmd) -mpp51 51 gpio, tdm2c(dtx), audio(sdo), dram(deccerr) -mpp52 52 gpio, pcie0(rstout), tdm2c(intn), audio(sdi), sd0(d6) -mpp53 53 gpio, sata1(prsnt), sata0(prsnt), tdm2c(rstn), audio(bclk), sd0(d7) +mpp48 48 gpio, sata0(prsnt), dram(vttctrl), tdm(pclk), audio(mclk), sd0(d4), pcie0(clkreq) +mpp49 49 gpio, sata2(prsnt) [2], sata3(prsnt) [2], tdm(fsync), audio(lrclk), sd0(d5), pcie1(clkreq) +mpp50 50 gpio, pcie0(rstout), tdm(drx), audio(extclk), sd0(cmd) +mpp51 51 gpio, tdm(dtx), audio(sdo), dram(deccerr) +mpp52 52 gpio, pcie0(rstout), tdm(int), audio(sdi), sd0(d6) +mpp53 53 gpio, sata1(prsnt), sata0(prsnt), tdm(rst), audio(bclk), sd0(d7) mpp54 54 gpio, sata0(prsnt), sata1(prsnt), pcie0(rstout), ge0(txerr), sd0(d3) mpp55 55 gpio, ua1(cts), ge(mdio), pcie1(clkreq) [1], spi1(cs1), sd0(d0) mpp56 56 gpio, ua1(rts), ge(mdc), dram(deccerr), spi1(mosi) diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-39x-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-39x-pinctrl.txt index b6bd9cc..1dd76e9 100644 --- a/Documentation/devicetree/bindings/pinctrl/marvell,armada-39x-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-39x-pinctrl.txt @@ -66,8 +66,8 @@ mpp48 48 gpio, sata0(prsnt) [1], dram(vttctrl), tdm(pclk) [1], audio(mclk) [1], mpp49 49 gpio, tdm(fsync) [1], audio(lrclk) [1], sd0(d5), ua2(rxd) mpp50 50 gpio, pcie0(rstout), tdm(drx) [1], audio(extclk) [1], sd0(cmd), ua2(rxd) mpp51 51 gpio, tdm(dtx) [1], audio(sdo) [1], dram(deccerr), ua2(txd) -mpp52 52 gpio, pcie0(rstout), tdm(intn) [1], audio(sdi) [1], sd0(d6), i2c3(sck) -mpp53 53 gpio, sata1(prsnt) [1], sata0(prsnt) [1], tdm(rstn) [1], audio(bclk) [1], sd0(d7), i2c3(sda) +mpp52 52 gpio, pcie0(rstout), tdm(int) [1], audio(sdi) [1], sd0(d6), i2c3(sck) +mpp53 53 gpio, sata1(prsnt) [1], sata0(prsnt) [1], tdm(rst) [1], audio(bclk) [1], sd0(d7), i2c3(sda) mpp54 54 gpio, sata0(prsnt) [1], sata1(prsnt) [1], pcie0(rstout), sd0(d3), ua3(txd) mpp55 55 gpio, ua1(cts), spi1(cs1), sd0(d0), ua1(rxd), ua3(rxd) mpp56 56 gpio, ua1(rts), dram(deccerr), spi1(mosi), ua1(txd) diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt index cefca17..561e519 100644 --- a/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt @@ -61,7 +61,7 @@ mpp39 39 gpio, spi(cs0) mpp40 40 gpio, spi(cs1), uart2(cts), lcd(vga-hsync), pcie(clkreq0) mpp41 41 gpio, spi(cs2), uart2(rts), lcd(vga-vsync), sata1(prsnt), pcie(clkreq1) -mpp42 42 gpio, uart2(rxd), uart0(cts), tdm(int7), tdm-1(timer) +mpp42 42 gpio, uart2(rxd), uart0(cts), tdm(int7), tdm(timer) mpp43 43 gpio, uart2(txd), uart0(rts), spi(cs3), pcie(rstout) mpp44 44 gpio, uart2(cts), uart3(rxd), spi(cs4), pcie(clkreq2), dram(bat) diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-370.c b/drivers/pinctrl/mvebu/pinctrl-armada-370.c index 7d2be71..fe5cfd1 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-370.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-370.c @@ -68,7 +68,7 @@ static struct mvebu_mpp_mode mv88f6710_mpp_modes[] = { MPP_MODE(7, MPP_FUNCTION(0x0, "gpo", NULL), MPP_FUNCTION(0x1, "ge0", "txd1"), - MPP_FUNCTION(0x4, "tdm", "tdx"), + MPP_FUNCTION(0x4, "tdm", "dtx"), MPP_FUNCTION(0x5, "audio", "lrclk")), MPP_MODE(8, MPP_FUNCTION(0x0, "gpio", NULL), diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-375.c b/drivers/pinctrl/mvebu/pinctrl-armada-375.c index 6dfe1bf..c41dd19 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-375.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-375.c @@ -141,10 +141,10 @@ static struct mvebu_mpp_mode mv88f6720_mpp_modes[] = { MPP_FUNCTION(0x2, "uart0", "rxd")), MPP_MODE(18, MPP_FUNCTION(0x0, "gpio", NULL), - MPP_FUNCTION(0x2, "tdm", "intn")), + MPP_FUNCTION(0x2, "tdm", "int")), MPP_MODE(19, MPP_FUNCTION(0x0, "gpio", NULL), - MPP_FUNCTION(0x2, "tdm", "rstn")), + MPP_FUNCTION(0x2, "tdm", "rst")), MPP_MODE(20, MPP_FUNCTION(0x0, "gpio", NULL), MPP_FUNCTION(0x2, "tdm", "pclk")), @@ -242,7 +242,7 @@ static struct mvebu_mpp_mode mv88f6720_mpp_modes[] = { MPP_MODE(37, MPP_FUNCTION(0x0, "gpio", NULL), MPP_FUNCTION(0x1, "pcie0", "clkreq"), - MPP_FUNCTION(0x2, "tdm", "intn"), + MPP_FUNCTION(0x2, "tdm", "int"), MPP_FUNCTION(0x4, "ge", "mdc")), MPP_MODE(38, MPP_FUNCTION(0x0, "gpio", NULL), diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-38x.c b/drivers/pinctrl/mvebu/pinctrl-armada-38x.c index 793d0df..b5006f7 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-38x.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-38x.c @@ -303,7 +303,7 @@ static struct mvebu_mpp_mode armada_38x_mpp_modes[] = { MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), MPP_VAR_FUNCTION(1, "sata0", "prsnt", V_88F6810_PLUS), MPP_VAR_FUNCTION(2, "dram", "vttctrl", V_88F6810_PLUS), - MPP_VAR_FUNCTION(3, "tdm2c", "pclk", V_88F6810_PLUS), + MPP_VAR_FUNCTION(3, "tdm", "pclk", V_88F6810_PLUS), MPP_VAR_FUNCTION(4, "audio", "mclk", V_88F6810_PLUS), MPP_VAR_FUNCTION(5, "sd0", "d4", V_88F6810_PLUS), MPP_VAR_FUNCTION(6, "pcie0", "clkreq", V_88F6810_PLUS)), @@ -311,32 +311,32 @@ static struct mvebu_mpp_mode armada_38x_mpp_modes[] = { MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), MPP_VAR_FUNCTION(1, "sata2", "prsnt", V_88F6828), MPP_VAR_FUNCTION(2, "sata3", "prsnt", V_88F6828), - MPP_VAR_FUNCTION(3, "tdm2c", "fsync", V_88F6810_PLUS), + MPP_VAR_FUNCTION(3, "tdm", "fsync", V_88F6810_PLUS), MPP_VAR_FUNCTION(4, "audio", "lrclk", V_88F6810_PLUS), MPP_VAR_FUNCTION(5, "sd0", "d5", V_88F6810_PLUS), MPP_VAR_FUNCTION(6, "pcie1", "clkreq", V_88F6820_PLUS)), MPP_MODE(50, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), MPP_VAR_FUNCTION(1, "pcie0", "rstout", V_88F6810_PLUS), - MPP_VAR_FUNCTION(3, "tdm2c", "drx", V_88F6810_PLUS), + MPP_VAR_FUNCTION(3, "tdm", "drx", V_88F6810_PLUS), MPP_VAR_FUNCTION(4, "audio", "extclk", V_88F6810_PLUS), MPP_VAR_FUNCTION(5, "sd0", "cmd", V_88F6810_PLUS)), MPP_MODE(51, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), - MPP_VAR_FUNCTION(3, "tdm2c", "dtx", V_88F6810_PLUS), + MPP_VAR_FUNCTION(3, "tdm", "dtx", V_88F6810_PLUS), MPP_VAR_FUNCTION(4, "audio", "sdo", V_88F6810_PLUS), MPP_VAR_FUNCTION(5, "dram", "deccerr", V_88F6810_PLUS)), MPP_MODE(52, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), MPP_VAR_FUNCTION(1, "pcie0", "rstout", V_88F6810_PLUS), - MPP_VAR_FUNCTION(3, "tdm2c", "intn", V_88F6810_PLUS), + MPP_VAR_FUNCTION(3, "tdm", "int", V_88F6810_PLUS), MPP_VAR_FUNCTION(4, "audio", "sdi", V_88F6810_PLUS), MPP_VAR_FUNCTION(5, "sd0", "d6", V_88F6810_PLUS)), MPP_MODE(53, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), MPP_VAR_FUNCTION(1, "sata1", "prsnt", V_88F6810_PLUS), MPP_VAR_FUNCTION(2, "sata0", "prsnt", V_88F6810_PLUS), - MPP_VAR_FUNCTION(3, "tdm2c", "rstn", V_88F6810_PLUS), + MPP_VAR_FUNCTION(3, "tdm", "rst", V_88F6810_PLUS), MPP_VAR_FUNCTION(4, "audio", "bclk", V_88F6810_PLUS), MPP_VAR_FUNCTION(5, "sd0", "d7", V_88F6810_PLUS)), MPP_MODE(54, diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-39x.c b/drivers/pinctrl/mvebu/pinctrl-armada-39x.c index de91b35..433291a 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-39x.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-39x.c @@ -308,7 +308,7 @@ static struct mvebu_mpp_mode armada_39x_mpp_modes[] = { MPP_MODE(52, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), MPP_VAR_FUNCTION(1, "pcie0", "rstout", V_88F6920_PLUS), - MPP_VAR_FUNCTION(3, "tdm", "intn", V_88F6928), + MPP_VAR_FUNCTION(3, "tdm", "int", V_88F6928), MPP_VAR_FUNCTION(4, "audio", "sdi", V_88F6928), MPP_VAR_FUNCTION(5, "sd0", "d6", V_88F6920_PLUS), MPP_VAR_FUNCTION(7, "i2c3", "sck", V_88F6920_PLUS)), @@ -316,7 +316,7 @@ static struct mvebu_mpp_mode armada_39x_mpp_modes[] = { MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), MPP_VAR_FUNCTION(1, "sata1", "prsnt", V_88F6928), MPP_VAR_FUNCTION(2, "sata0", "prsnt", V_88F6928), - MPP_VAR_FUNCTION(3, "tdm", "rstn", V_88F6928), + MPP_VAR_FUNCTION(3, "tdm", "rst", V_88F6928), MPP_VAR_FUNCTION(4, "audio", "bclk", V_88F6928), MPP_VAR_FUNCTION(5, "sd0", "d7", V_88F6920_PLUS), MPP_VAR_FUNCTION(7, "i2c3", "sda", V_88F6920_PLUS)), diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-xp.c b/drivers/pinctrl/mvebu/pinctrl-armada-xp.c index 93b0485..9a8b714 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-xp.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-xp.c @@ -252,7 +252,7 @@ static struct mvebu_mpp_mode armada_xp_mpp_modes[] = { MPP_VAR_FUNCTION(0x1, "uart2", "rxd", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x2, "uart0", "cts", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x3, "tdm", "int7", V_MV78230_PLUS), - MPP_VAR_FUNCTION(0x4, "tdm-1", "timer", V_MV78230_PLUS)), + MPP_VAR_FUNCTION(0x4, "tdm", "timer", V_MV78230_PLUS)), MPP_MODE(43, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), MPP_VAR_FUNCTION(0x1, "uart2", "txd", V_MV78230_PLUS), -- cgit v0.10.2 From d4974c16ed22f6b19b67d95d63c7244dbe87d95b Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 9 Jun 2015 18:47:09 +0200 Subject: pinctrl: mvebu: armada-{370,375}: normalize PCIe pins This commit normalizes the naming of PCIe pins to use 'rstout' instead of 'rstoutn' or 'rst-out'. Since only the subnames are changed, DT compatibility is not affected. Signed-off-by: Thomas Petazzoni Signed-off-by: Linus Walleij diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt index e6dce5d..24a7450 100644 --- a/Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt @@ -86,7 +86,7 @@ mpp57 57 gpio, dev(cs3), uart1(rxd), tdm(fsync), sata0(prsnt), mpp58 58 gpio, dev(cs0), uart1(rts), tdm(int), audio(extclk), uart0(rts) mpp59 59 gpo, dev(ale0), uart1(rts), uart0(rts), audio(bclk) -mpp60 60 gpio, dev(ale1), uart1(rxd), sata0(prsnt), pcie(rst-out), +mpp60 60 gpio, dev(ale1), uart1(rxd), sata0(prsnt), pcie(rstout), audio(sdi) mpp61 61 gpo, dev(we1), uart1(txd), audio(rclk) mpp62 62 gpio, dev(a2), uart1(cts), tdm(drx), pcie(clkreq0), diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-375-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-375-pinctrl.txt index 3140324..f942a00 100644 --- a/Documentation/devicetree/bindings/pinctrl/marvell,armada-375-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-375-pinctrl.txt @@ -26,7 +26,7 @@ mpp9 9 gpio, spi0(sck), spi1(sck), nand(we) mpp10 10 gpio, dram(vttctrl), led(c1), nand(re) mpp11 11 gpio, dev(a0), led(c2), audio(sdo) mpp12 12 gpio, dev(a1), audio(bclk) -mpp13 13 gpio, dev(ready), pcie0(rstoutn), pcie1(rstoutn) +mpp13 13 gpio, dev(ready), pcie0(rstout), pcie1(rstout) mpp14 14 gpio, i2c0(sda), uart1(txd) mpp15 15 gpio, i2c0(sck), uart1(rxd) mpp16 16 gpio, uart0(txd) @@ -58,7 +58,7 @@ mpp41 41 gpio, uart1(rxd) mpp42 42 gpio, spi1(cs2), led(c0) mpp43 43 gpio, sata0(prsnt), dram(vttctrl) mpp44 44 gpio, sata0(prsnt) -mpp45 45 gpio, spi0(cs2), pcie0(rstoutn) +mpp45 45 gpio, spi0(cs2), pcie0(rstout) mpp46 46 gpio, led(p0), ge0(txd0), ge1(txd0), dev(we1) mpp47 47 gpio, led(p1), ge0(txd1), ge1(txd1) mpp48 48 gpio, led(p2), ge0(txd2), ge1(txd2) @@ -66,8 +66,8 @@ mpp49 49 gpio, led(p3), ge0(txd3), ge1(txd3) mpp50 50 gpio, led(c0), ge0(rxd0), ge1(rxd0) mpp51 51 gpio, led(c1), ge0(rxd1), ge1(rxd1) mpp52 52 gpio, led(c2), ge0(rxd2), ge1(rxd2) -mpp53 53 gpio, pcie1(rstoutn), ge0(rxd3), ge1(rxd3) -mpp54 54 gpio, pcie0(rstoutn), ge0(rxctl), ge1(rxctl) +mpp53 53 gpio, pcie1(rstout), ge0(rxd3), ge1(rxd3) +mpp54 54 gpio, pcie0(rstout), ge0(rxctl), ge1(rxctl) mpp55 55 gpio, ge0(rxclk), ge1(rxclk) mpp56 56 gpio, ge0(txclkout), ge1(txclkout) mpp57 57 gpio, ge0(txctl), ge1(txctl), dev(we0) diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-370.c b/drivers/pinctrl/mvebu/pinctrl-armada-370.c index fe5cfd1..6ecec90 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-370.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-370.c @@ -348,7 +348,7 @@ static struct mvebu_mpp_mode mv88f6710_mpp_modes[] = { MPP_FUNCTION(0x1, "dev", "ale1"), MPP_FUNCTION(0x2, "uart1", "rxd"), MPP_FUNCTION(0x3, "sata0", "prsnt"), - MPP_FUNCTION(0x4, "pcie", "rst-out"), + MPP_FUNCTION(0x4, "pcie", "rstout"), MPP_FUNCTION(0x5, "audio", "sdi")), MPP_MODE(61, MPP_FUNCTION(0x0, "gpo", NULL), diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-375.c b/drivers/pinctrl/mvebu/pinctrl-armada-375.c index c41dd19..4d3e235 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-375.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-375.c @@ -121,8 +121,8 @@ static struct mvebu_mpp_mode mv88f6720_mpp_modes[] = { MPP_MODE(13, MPP_FUNCTION(0x0, "gpio", NULL), MPP_FUNCTION(0x1, "dev", "ready"), - MPP_FUNCTION(0x2, "pcie0", "rstoutn"), - MPP_FUNCTION(0x3, "pcie1", "rstoutn"), + MPP_FUNCTION(0x2, "pcie0", "rstout"), + MPP_FUNCTION(0x3, "pcie1", "rstout"), MPP_FUNCTION(0x5, "nand", "rb"), MPP_FUNCTION(0x6, "spi1", "mosi")), MPP_MODE(14, @@ -201,7 +201,7 @@ static struct mvebu_mpp_mode mv88f6720_mpp_modes[] = { MPP_FUNCTION(0x2, "ge1", "rxclk"), MPP_FUNCTION(0x3, "sd", "d3"), MPP_FUNCTION(0x5, "spi0", "sck"), - MPP_FUNCTION(0x6, "pcie0", "rstoutn")), + MPP_FUNCTION(0x6, "pcie0", "rstout")), MPP_MODE(30, MPP_FUNCTION(0x0, "gpio", NULL), MPP_FUNCTION(0x2, "ge1", "txd0"), @@ -276,7 +276,7 @@ static struct mvebu_mpp_mode mv88f6720_mpp_modes[] = { MPP_MODE(45, MPP_FUNCTION(0x0, "gpio", NULL), MPP_FUNCTION(0x2, "spi0", "cs2"), - MPP_FUNCTION(0x4, "pcie0", "rstoutn"), + MPP_FUNCTION(0x4, "pcie0", "rstout"), MPP_FUNCTION(0x5, "led", "c2"), MPP_FUNCTION(0x6, "spi1", "cs2")), MPP_MODE(46, @@ -326,14 +326,14 @@ static struct mvebu_mpp_mode mv88f6720_mpp_modes[] = { MPP_FUNCTION(0x6, "dev", "ad9")), MPP_MODE(53, MPP_FUNCTION(0x0, "gpio", NULL), - MPP_FUNCTION(0x1, "pcie1", "rstoutn"), + MPP_FUNCTION(0x1, "pcie1", "rstout"), MPP_FUNCTION(0x2, "ge0", "rxd3"), MPP_FUNCTION(0x3, "ge1", "rxd3"), MPP_FUNCTION(0x5, "i2c0", "sck"), MPP_FUNCTION(0x6, "dev", "ad10")), MPP_MODE(54, MPP_FUNCTION(0x0, "gpio", NULL), - MPP_FUNCTION(0x1, "pcie0", "rstoutn"), + MPP_FUNCTION(0x1, "pcie0", "rstout"), MPP_FUNCTION(0x2, "ge0", "rxctl"), MPP_FUNCTION(0x3, "ge1", "rxctl"), MPP_FUNCTION(0x6, "dev", "ad11")), @@ -391,7 +391,7 @@ static struct mvebu_mpp_mode mv88f6720_mpp_modes[] = { MPP_FUNCTION(0x0, "gpio", NULL), MPP_FUNCTION(0x2, "ptp", "evreq"), MPP_FUNCTION(0x4, "spi1", "cs3"), - MPP_FUNCTION(0x5, "pcie0", "rstoutn"), + MPP_FUNCTION(0x5, "pcie0", "rstout"), MPP_FUNCTION(0x6, "dev", "cs3")), }; -- cgit v0.10.2 From f32f01e1ba6bca9611c835eb357ce926038128e8 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 9 Jun 2015 18:47:10 +0200 Subject: pinctrl: mvebu: armada-{370,375}: normalize audio pins This commit aligns the naming of the audio 'lrclk' pin accross Marvell SoCs. Since only the subname is changed, the DT backward compatibility is not affected. Signed-off-by: Thomas Petazzoni Signed-off-by: Linus Walleij diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt index 24a7450..cc0be9d 100644 --- a/Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt @@ -88,7 +88,7 @@ mpp58 58 gpio, dev(cs0), uart1(rts), tdm(int), audio(extclk), mpp59 59 gpo, dev(ale0), uart1(rts), uart0(rts), audio(bclk) mpp60 60 gpio, dev(ale1), uart1(rxd), sata0(prsnt), pcie(rstout), audio(sdi) -mpp61 61 gpo, dev(we1), uart1(txd), audio(rclk) +mpp61 61 gpo, dev(we1), uart1(txd), audio(lrclk) mpp62 62 gpio, dev(a2), uart1(cts), tdm(drx), pcie(clkreq0), audio(mclk), uart0(cts) mpp63 63 gpo, spi0(sck), tclk diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-375-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-375-pinctrl.txt index f942a00..06e5bb0 100644 --- a/Documentation/devicetree/bindings/pinctrl/marvell,armada-375-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-375-pinctrl.txt @@ -19,7 +19,7 @@ mpp2 2 gpio, dev(ad4), ptp(evreq), led(c0), audio(sdi) mpp3 3 gpio, dev(ad5), ptp(trig), led(p3), audio(mclk) mpp4 4 gpio, dev(ad6), spi0(miso), spi1(miso) mpp5 5 gpio, dev(ad7), spi0(cs2), spi1(cs2) -mpp6 6 gpio, dev(ad0), led(p1), audio(rclk) +mpp6 6 gpio, dev(ad0), led(p1), audio(lrclk) mpp7 7 gpio, dev(ad1), ptp(clk), led(p2), audio(extclk) mpp8 8 gpio, dev (bootcs), spi0(cs0), spi1(cs0) mpp9 9 gpio, spi0(sck), spi1(sck), nand(we) diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-370.c b/drivers/pinctrl/mvebu/pinctrl-armada-370.c index 6ecec90..54fec8c 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-370.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-370.c @@ -354,7 +354,7 @@ static struct mvebu_mpp_mode mv88f6710_mpp_modes[] = { MPP_FUNCTION(0x0, "gpo", NULL), MPP_FUNCTION(0x1, "dev", "we1"), MPP_FUNCTION(0x2, "uart1", "txd"), - MPP_FUNCTION(0x5, "audio", "rclk")), + MPP_FUNCTION(0x5, "audio", "lrclk")), MPP_MODE(62, MPP_FUNCTION(0x0, "gpio", NULL), MPP_FUNCTION(0x1, "dev", "a2"), diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-375.c b/drivers/pinctrl/mvebu/pinctrl-armada-375.c index 4d3e235..54e9fbd 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-375.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-375.c @@ -81,7 +81,7 @@ static struct mvebu_mpp_mode mv88f6720_mpp_modes[] = { MPP_FUNCTION(0x0, "gpio", NULL), MPP_FUNCTION(0x1, "dev", "ad0"), MPP_FUNCTION(0x3, "led", "p1"), - MPP_FUNCTION(0x4, "audio", "rclk"), + MPP_FUNCTION(0x4, "audio", "lrclk"), MPP_FUNCTION(0x5, "nand", "io0")), MPP_MODE(7, MPP_FUNCTION(0x0, "gpio", NULL), -- cgit v0.10.2 From a361cbc575d6ea778fe3fa6f13246bf34d995519 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 9 Jun 2015 18:47:11 +0200 Subject: pinctrl: mvebu: armada-{370,xp}: normalize ethernet txclkout pins This commit normalizes the naming of the Ethernet txclkout pin to be the same accross Marvell SoCs. It is worth mentioning that the DT binding documentation of the Armada XP was wrong for MPP12: it said the function was ge1(txd0), while it is in fact ge1(txclkout). It is however not really a fix worth sending to stable since it does not change the behavior, and the driver itself was correct. Since only the subnames are changed, DT backward compatibility is not affected. Signed-off-by: Thomas Petazzoni Signed-off-by: Linus Walleij diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt index cc0be9d..44aedd5 100644 --- a/Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt @@ -18,7 +18,7 @@ mpp1 1 gpo, uart0(txd) mpp2 2 gpio, i2c0(sck), uart0(txd) mpp3 3 gpio, i2c0(sda), uart0(rxd) mpp4 4 gpio, cpu_pd(vdd) -mpp5 5 gpo, ge0(txclko), uart1(txd), spi1(clk), audio(mclk) +mpp5 5 gpo, ge0(txclkout), uart1(txd), spi1(clk), audio(mclk) mpp6 6 gpio, ge0(txd0), sata0(prsnt), tdm(rst), audio(sdo) mpp7 7 gpo, ge0(txd1), tdm(dtx), audio(lrclk) mpp8 8 gpio, ge0(txd2), uart0(rts), tdm(drx), audio(bclk) diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt index 561e519..0bd7d2f 100644 --- a/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt @@ -18,7 +18,7 @@ only for more detailed description in this document. name pins functions ================================================================================ -mpp0 0 gpio, ge0(txclko), lcd(d0) +mpp0 0 gpio, ge0(txclkout), lcd(d0) mpp1 1 gpio, ge0(txd0), lcd(d1) mpp2 2 gpio, ge0(txd1), lcd(d2) mpp3 3 gpio, ge0(txd2), lcd(d3) @@ -30,7 +30,7 @@ mpp8 8 gpio, ge0(rxd2), lcd(d8) mpp9 9 gpio, ge0(rxd3), lcd(d9) mpp10 10 gpio, ge0(rxctl), lcd(d10) mpp11 11 gpio, ge0(rxclk), lcd(d11) -mpp12 12 gpio, ge0(txd4), ge1(txd0), lcd(d12) +mpp12 12 gpio, ge0(txd4), ge1(txclkout), lcd(d12) mpp13 13 gpio, ge0(txd5), ge1(txd1), lcd(d13) mpp14 14 gpio, ge0(txd6), ge1(txd2), lcd(d15) mpp15 15 gpio, ge0(txd7), ge1(txd3), lcd(d16) diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-370.c b/drivers/pinctrl/mvebu/pinctrl-armada-370.c index 54fec8c..cabf188 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-370.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-370.c @@ -55,7 +55,7 @@ static struct mvebu_mpp_mode mv88f6710_mpp_modes[] = { MPP_FUNCTION(0x1, "cpu_pd", "vdd")), MPP_MODE(5, MPP_FUNCTION(0x0, "gpo", NULL), - MPP_FUNCTION(0x1, "ge0", "txclko"), + MPP_FUNCTION(0x1, "ge0", "txclkout"), MPP_FUNCTION(0x2, "uart1", "txd"), MPP_FUNCTION(0x4, "spi1", "clk"), MPP_FUNCTION(0x5, "audio", "mclk")), diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-xp.c b/drivers/pinctrl/mvebu/pinctrl-armada-xp.c index 9a8b714..fb5ffa5 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-xp.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-xp.c @@ -54,7 +54,7 @@ enum armada_xp_variant { static struct mvebu_mpp_mode armada_xp_mpp_modes[] = { MPP_MODE(0, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), - MPP_VAR_FUNCTION(0x1, "ge0", "txclko", V_MV78230_PLUS), + MPP_VAR_FUNCTION(0x1, "ge0", "txclkout", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x4, "lcd", "d0", V_MV78230_PLUS)), MPP_MODE(1, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), @@ -103,7 +103,7 @@ static struct mvebu_mpp_mode armada_xp_mpp_modes[] = { MPP_MODE(12, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), MPP_VAR_FUNCTION(0x1, "ge0", "txd4", V_MV78230_PLUS), - MPP_VAR_FUNCTION(0x2, "ge1", "clkout", V_MV78230_PLUS), + MPP_VAR_FUNCTION(0x2, "ge1", "txclkout", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x4, "lcd", "d12", V_MV78230_PLUS)), MPP_MODE(13, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), -- cgit v0.10.2 From f1b2db90d0f1bd5227a48ffc479bbd65e97e4327 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 9 Jun 2015 18:47:12 +0200 Subject: pinctrl: mvebu: armada-xp: fix binding documentation of ge1 pins There was an off-by-one in the documentation of the ge1(txd[0-3]) pins, which is fixed by this commit. Since the driver was correct, and the subnames are anyway not used in the DT binding itself, there is no need to push this documentation fix for stable. Signed-off-by: Thomas Petazzoni Signed-off-by: Linus Walleij diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt index 0bd7d2f..f2d2d40 100644 --- a/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt @@ -31,9 +31,9 @@ mpp9 9 gpio, ge0(rxd3), lcd(d9) mpp10 10 gpio, ge0(rxctl), lcd(d10) mpp11 11 gpio, ge0(rxclk), lcd(d11) mpp12 12 gpio, ge0(txd4), ge1(txclkout), lcd(d12) -mpp13 13 gpio, ge0(txd5), ge1(txd1), lcd(d13) -mpp14 14 gpio, ge0(txd6), ge1(txd2), lcd(d15) -mpp15 15 gpio, ge0(txd7), ge1(txd3), lcd(d16) +mpp13 13 gpio, ge0(txd5), ge1(txd0), lcd(d13) +mpp14 14 gpio, ge0(txd6), ge1(txd1), lcd(d15) +mpp15 15 gpio, ge0(txd7), ge1(txd2), lcd(d16) mpp16 16 gpio, ge0(txd7), ge1(txd3), lcd(d16) mpp17 17 gpio, ge0(col), ge1(txctl), lcd(d17) mpp18 18 gpio, ge0(rxerr), ge1(rxd0), lcd(d18), ptp(trig) -- cgit v0.10.2 From bfacb5669474e3e17d732eafd2f6965a7ad728ff Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 9 Jun 2015 18:47:13 +0200 Subject: pinctrl: mvebu: armada-370: align VDD cpu-pd pin naming with datasheet For consistency with the datasheet, this commit renames the VDD function of the MPP4 pin. While this changes the DT compatibility, it is not considered to be a problem since this pin is unlikely to be used for anything but debugging purposes. Signed-off-by: Thomas Petazzoni Signed-off-by: Linus Walleij diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt index 44aedd5..3a7dc0e 100644 --- a/Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt @@ -17,7 +17,7 @@ mpp0 0 gpio, uart0(rxd) mpp1 1 gpo, uart0(txd) mpp2 2 gpio, i2c0(sck), uart0(txd) mpp3 3 gpio, i2c0(sda), uart0(rxd) -mpp4 4 gpio, cpu_pd(vdd) +mpp4 4 gpio, vdd(cpu-pd) mpp5 5 gpo, ge0(txclkout), uart1(txd), spi1(clk), audio(mclk) mpp6 6 gpio, ge0(txd0), sata0(prsnt), tdm(rst), audio(sdo) mpp7 7 gpo, ge0(txd1), tdm(dtx), audio(lrclk) diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-370.c b/drivers/pinctrl/mvebu/pinctrl-armada-370.c index cabf188..fc16ef6 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-370.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-370.c @@ -52,7 +52,7 @@ static struct mvebu_mpp_mode mv88f6710_mpp_modes[] = { MPP_FUNCTION(0x2, "uart0", "rxd")), MPP_MODE(4, MPP_FUNCTION(0x0, "gpio", NULL), - MPP_FUNCTION(0x1, "cpu_pd", "vdd")), + MPP_FUNCTION(0x1, "vdd", "cpu-pd")), MPP_MODE(5, MPP_FUNCTION(0x0, "gpo", NULL), MPP_FUNCTION(0x1, "ge0", "txclkout"), -- cgit v0.10.2 From 9e05db29e2ac7f1fec1a4d15db8c419634290535 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 9 Jun 2015 18:47:14 +0200 Subject: pinctrl: mvebu: armada-370: align spi1 clock pin naming Across all SoCs, even on Armada 370 for SPI0, the clock pin uses the 'sck' subname and not 'clk', so this commit adjusts the code and documentation accordingly. Since this commit only changes the subname, DT backward compatibility is not affected. Signed-off-by: Thomas Petazzoni Signed-off-by: Linus Walleij diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt index 3a7dc0e..add7c38 100644 --- a/Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt @@ -18,7 +18,7 @@ mpp1 1 gpo, uart0(txd) mpp2 2 gpio, i2c0(sck), uart0(txd) mpp3 3 gpio, i2c0(sda), uart0(rxd) mpp4 4 gpio, vdd(cpu-pd) -mpp5 5 gpo, ge0(txclkout), uart1(txd), spi1(clk), audio(mclk) +mpp5 5 gpo, ge0(txclkout), uart1(txd), spi1(sck), audio(mclk) mpp6 6 gpio, ge0(txd0), sata0(prsnt), tdm(rst), audio(sdo) mpp7 7 gpo, ge0(txd1), tdm(dtx), audio(lrclk) mpp8 8 gpio, ge0(txd2), uart0(rts), tdm(drx), audio(bclk) diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-370.c b/drivers/pinctrl/mvebu/pinctrl-armada-370.c index fc16ef6..c2e5e4d 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-370.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-370.c @@ -57,7 +57,7 @@ static struct mvebu_mpp_mode mv88f6710_mpp_modes[] = { MPP_FUNCTION(0x0, "gpo", NULL), MPP_FUNCTION(0x1, "ge0", "txclkout"), MPP_FUNCTION(0x2, "uart1", "txd"), - MPP_FUNCTION(0x4, "spi1", "clk"), + MPP_FUNCTION(0x4, "spi1", "sck"), MPP_FUNCTION(0x5, "audio", "mclk")), MPP_MODE(6, MPP_FUNCTION(0x0, "gpio", NULL), -- cgit v0.10.2 From 50a7d13d241081838c6cd12b1fdabc36838f9b4c Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 9 Jun 2015 18:47:15 +0200 Subject: pinctrl: mvebu: armada-xp: rename spi to spi0 After updating to the latest Armada XP datasheet, we discovered that there is a second SPI bus accessible from the MPP pins, called 'spi1'. In order to be consistent with other SoCs having two SPI busses, this commit renames the functions of the first SPI bus to 'spi0' instead of just 'spi'. This commit obviously breaks the DT backward compatibility for the people using the "spi" function name in their Device Tree. Signed-off-by: Thomas Petazzoni Signed-off-by: Linus Walleij diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt index f2d2d40..e8e0a27 100644 --- a/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt @@ -54,20 +54,20 @@ mpp32 32 gpio, tdm(int3), sd0(d0) mpp33 33 gpio, tdm(int4), sd0(d1), dram(bat) mpp34 34 gpio, tdm(int5), sd0(d2), sata0(prsnt) mpp35 35 gpio, tdm(int6), sd0(d3), sata1(prsnt) -mpp36 36 gpio, spi(mosi) -mpp37 37 gpio, spi(miso) -mpp38 38 gpio, spi(sck) -mpp39 39 gpio, spi(cs0) -mpp40 40 gpio, spi(cs1), uart2(cts), lcd(vga-hsync), pcie(clkreq0) -mpp41 41 gpio, spi(cs2), uart2(rts), lcd(vga-vsync), sata1(prsnt), +mpp36 36 gpio, spi0(mosi) +mpp37 37 gpio, spi0(miso) +mpp38 38 gpio, spi0(sck) +mpp39 39 gpio, spi0(cs0) +mpp40 40 gpio, spi0(cs1), uart2(cts), lcd(vga-hsync), pcie(clkreq0) +mpp41 41 gpio, spi0(cs2), uart2(rts), lcd(vga-vsync), sata1(prsnt), pcie(clkreq1) mpp42 42 gpio, uart2(rxd), uart0(cts), tdm(int7), tdm(timer) -mpp43 43 gpio, uart2(txd), uart0(rts), spi(cs3), pcie(rstout) -mpp44 44 gpio, uart2(cts), uart3(rxd), spi(cs4), pcie(clkreq2), +mpp43 43 gpio, uart2(txd), uart0(rts), spi0(cs3), pcie(rstout) +mpp44 44 gpio, uart2(cts), uart3(rxd), spi0(cs4), pcie(clkreq2), dram(bat) -mpp45 45 gpio, uart2(rts), uart3(txd), spi(cs5), sata1(prsnt) -mpp46 46 gpio, uart3(rts), uart1(rts), spi(cs6), sata0(prsnt) -mpp47 47 gpio, uart3(cts), uart1(cts), spi(cs7), pcie(clkreq3), +mpp45 45 gpio, uart2(rts), uart3(txd), spi0(cs5), sata1(prsnt) +mpp46 46 gpio, uart3(rts), uart1(rts), spi0(cs6), sata0(prsnt) +mpp47 47 gpio, uart3(cts), uart1(cts), spi0(cs7), pcie(clkreq3), ref(clkout) mpp48 48 gpio, dev(clkout), dev(burst/last) diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-xp.c b/drivers/pinctrl/mvebu/pinctrl-armada-xp.c index fb5ffa5..74ff211 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-xp.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-xp.c @@ -224,25 +224,25 @@ static struct mvebu_mpp_mode armada_xp_mpp_modes[] = { MPP_VAR_FUNCTION(0x3, "tdm", "int6", V_MV78230_PLUS)), MPP_MODE(36, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), - MPP_VAR_FUNCTION(0x1, "spi", "mosi", V_MV78230_PLUS)), + MPP_VAR_FUNCTION(0x1, "spi0", "mosi", V_MV78230_PLUS)), MPP_MODE(37, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), - MPP_VAR_FUNCTION(0x1, "spi", "miso", V_MV78230_PLUS)), + MPP_VAR_FUNCTION(0x1, "spi0", "miso", V_MV78230_PLUS)), MPP_MODE(38, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), - MPP_VAR_FUNCTION(0x1, "spi", "sck", V_MV78230_PLUS)), + MPP_VAR_FUNCTION(0x1, "spi0", "sck", V_MV78230_PLUS)), MPP_MODE(39, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), - MPP_VAR_FUNCTION(0x1, "spi", "cs0", V_MV78230_PLUS)), + MPP_VAR_FUNCTION(0x1, "spi0", "cs0", V_MV78230_PLUS)), MPP_MODE(40, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), - MPP_VAR_FUNCTION(0x1, "spi", "cs1", V_MV78230_PLUS), + MPP_VAR_FUNCTION(0x1, "spi0", "cs1", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x2, "uart2", "cts", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x4, "lcd", "vga-hsync", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x5, "pcie", "clkreq0", V_MV78230_PLUS)), MPP_MODE(41, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), - MPP_VAR_FUNCTION(0x1, "spi", "cs2", V_MV78230_PLUS), + MPP_VAR_FUNCTION(0x1, "spi0", "cs2", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x2, "uart2", "rts", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x3, "sata1", "prsnt", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x4, "lcd", "vga-vsync", V_MV78230_PLUS), @@ -257,32 +257,32 @@ static struct mvebu_mpp_mode armada_xp_mpp_modes[] = { MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), MPP_VAR_FUNCTION(0x1, "uart2", "txd", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x2, "uart0", "rts", V_MV78230_PLUS), - MPP_VAR_FUNCTION(0x3, "spi", "cs3", V_MV78230_PLUS), + MPP_VAR_FUNCTION(0x3, "spi0", "cs3", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x4, "pcie", "rstout", V_MV78230_PLUS)), MPP_MODE(44, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), MPP_VAR_FUNCTION(0x1, "uart2", "cts", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x2, "uart3", "rxd", V_MV78230_PLUS), - MPP_VAR_FUNCTION(0x3, "spi", "cs4", V_MV78230_PLUS), + MPP_VAR_FUNCTION(0x3, "spi0", "cs4", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x4, "dram", "bat", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x5, "pcie", "clkreq2", V_MV78230_PLUS)), MPP_MODE(45, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), MPP_VAR_FUNCTION(0x1, "uart2", "rts", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x2, "uart3", "txd", V_MV78230_PLUS), - MPP_VAR_FUNCTION(0x3, "spi", "cs5", V_MV78230_PLUS), + MPP_VAR_FUNCTION(0x3, "spi0", "cs5", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x4, "sata1", "prsnt", V_MV78230_PLUS)), MPP_MODE(46, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), MPP_VAR_FUNCTION(0x1, "uart3", "rts", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x2, "uart1", "rts", V_MV78230_PLUS), - MPP_VAR_FUNCTION(0x3, "spi", "cs6", V_MV78230_PLUS), + MPP_VAR_FUNCTION(0x3, "spi0", "cs6", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x4, "sata0", "prsnt", V_MV78230_PLUS)), MPP_MODE(47, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), MPP_VAR_FUNCTION(0x1, "uart3", "cts", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x2, "uart1", "cts", V_MV78230_PLUS), - MPP_VAR_FUNCTION(0x3, "spi", "cs7", V_MV78230_PLUS), + MPP_VAR_FUNCTION(0x3, "spi0", "cs7", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x4, "ref", "clkout", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x5, "pcie", "clkreq3", V_MV78230_PLUS)), MPP_MODE(48, -- cgit v0.10.2 From 691a82161b88056fa1e52145446bc22197665782 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 9 Jun 2015 18:47:16 +0200 Subject: pinctrl: mvebu: armada-39x: normalize ref clock naming This commit normalizes the subnames of the reference clock MPP pins in the Armada 39x pinctrl driver to match with the name used on other SoCs. Since only the subnames are changed, DT backward compatibility is not affected. Signed-off-by: Thomas Petazzoni Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-39x.c b/drivers/pinctrl/mvebu/pinctrl-armada-39x.c index 433291a..08ee427 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-39x.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-39x.c @@ -205,7 +205,7 @@ static struct mvebu_mpp_mode armada_39x_mpp_modes[] = { MPP_VAR_FUNCTION(5, "dev", "ad1", V_88F6920_PLUS)), MPP_MODE(35, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), - MPP_VAR_FUNCTION(1, "ref", "clk", V_88F6920_PLUS), + MPP_VAR_FUNCTION(1, "ref", "clk_out1", V_88F6920_PLUS), MPP_VAR_FUNCTION(5, "dev", "a1", V_88F6920_PLUS)), MPP_MODE(36, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), @@ -217,7 +217,7 @@ static struct mvebu_mpp_mode armada_39x_mpp_modes[] = { MPP_VAR_FUNCTION(8, "ge", "rxclk", V_88F6920_PLUS)), MPP_MODE(38, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), - MPP_VAR_FUNCTION(3, "ref", "clk", V_88F6920_PLUS), + MPP_VAR_FUNCTION(3, "ref", "clk_out0", V_88F6920_PLUS), MPP_VAR_FUNCTION(4, "sd0", "d0", V_88F6920_PLUS), MPP_VAR_FUNCTION(5, "dev", "ad4", V_88F6920_PLUS), MPP_VAR_FUNCTION(8, "ge", "rxd1", V_88F6920_PLUS)), @@ -263,12 +263,12 @@ static struct mvebu_mpp_mode armada_39x_mpp_modes[] = { MPP_VAR_FUNCTION(7, "led", "clk", V_88F6920_PLUS)), MPP_MODE(45, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), - MPP_VAR_FUNCTION(1, "ref", "clk", V_88F6920_PLUS), + MPP_VAR_FUNCTION(1, "ref", "clk_out0", V_88F6920_PLUS), MPP_VAR_FUNCTION(2, "pcie0", "rstout", V_88F6920_PLUS), MPP_VAR_FUNCTION(6, "ua1", "rxd", V_88F6920_PLUS)), MPP_MODE(46, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), - MPP_VAR_FUNCTION(1, "ref", "clk", V_88F6920_PLUS), + MPP_VAR_FUNCTION(1, "ref", "clk_out1", V_88F6920_PLUS), MPP_VAR_FUNCTION(2, "pcie0", "rstout", V_88F6920_PLUS), MPP_VAR_FUNCTION(6, "ua1", "txd", V_88F6920_PLUS), MPP_VAR_FUNCTION(7, "led", "stb", V_88F6920_PLUS)), -- cgit v0.10.2 From 88b355f1e4e517b636bc5c4b2fb53ec55ccc578d Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 9 Jun 2015 18:47:17 +0200 Subject: pinctrl: mvebu: armada-xp: add spi1 function The latest Armada XP datasheet documents that some of the MPP pins can be used to access the second SPI bus, labelled 'spi1'. This commit adds the corresponding pins in the pinctrl driver and its DT binding documentation. Signed-off-by: Thomas Petazzoni Signed-off-by: Linus Walleij diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt index e8e0a27..5f64ee1 100644 --- a/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt @@ -31,11 +31,11 @@ mpp9 9 gpio, ge0(rxd3), lcd(d9) mpp10 10 gpio, ge0(rxctl), lcd(d10) mpp11 11 gpio, ge0(rxclk), lcd(d11) mpp12 12 gpio, ge0(txd4), ge1(txclkout), lcd(d12) -mpp13 13 gpio, ge0(txd5), ge1(txd0), lcd(d13) -mpp14 14 gpio, ge0(txd6), ge1(txd1), lcd(d15) +mpp13 13 gpio, ge0(txd5), ge1(txd0), spi1(mosi), lcd(d13) +mpp14 14 gpio, ge0(txd6), ge1(txd1), spi1(sck), lcd(d15) mpp15 15 gpio, ge0(txd7), ge1(txd2), lcd(d16) -mpp16 16 gpio, ge0(txd7), ge1(txd3), lcd(d16) -mpp17 17 gpio, ge0(col), ge1(txctl), lcd(d17) +mpp16 16 gpio, ge0(txd7), ge1(txd3), spi1(cs0), lcd(d16) +mpp17 17 gpio, ge0(col), ge1(txctl), spi1(miso), lcd(d17) mpp18 18 gpio, ge0(rxerr), ge1(rxd0), lcd(d18), ptp(trig) mpp19 19 gpio, ge0(crs), ge1(rxd1), lcd(d19), ptp(evreq) mpp20 20 gpio, ge0(rxd4), ge1(rxd2), lcd(d20), ptp(clk) @@ -58,17 +58,21 @@ mpp36 36 gpio, spi0(mosi) mpp37 37 gpio, spi0(miso) mpp38 38 gpio, spi0(sck) mpp39 39 gpio, spi0(cs0) -mpp40 40 gpio, spi0(cs1), uart2(cts), lcd(vga-hsync), pcie(clkreq0) +mpp40 40 gpio, spi0(cs1), uart2(cts), lcd(vga-hsync), pcie(clkreq0), + spi1(cs1) mpp41 41 gpio, spi0(cs2), uart2(rts), lcd(vga-vsync), sata1(prsnt), - pcie(clkreq1) + pcie(clkreq1), spi1(cs2) mpp42 42 gpio, uart2(rxd), uart0(cts), tdm(int7), tdm(timer) -mpp43 43 gpio, uart2(txd), uart0(rts), spi0(cs3), pcie(rstout) +mpp43 43 gpio, uart2(txd), uart0(rts), spi0(cs3), pcie(rstout), + spi1(cs3) mpp44 44 gpio, uart2(cts), uart3(rxd), spi0(cs4), pcie(clkreq2), - dram(bat) -mpp45 45 gpio, uart2(rts), uart3(txd), spi0(cs5), sata1(prsnt) -mpp46 46 gpio, uart3(rts), uart1(rts), spi0(cs6), sata0(prsnt) + dram(bat), spi1(cs4) +mpp45 45 gpio, uart2(rts), uart3(txd), spi0(cs5), sata1(prsnt), + spi1(cs5) +mpp46 46 gpio, uart3(rts), uart1(rts), spi0(cs6), sata0(prsnt), + spi1(cs6) mpp47 47 gpio, uart3(cts), uart1(cts), spi0(cs7), pcie(clkreq3), - ref(clkout) + ref(clkout), spi1(cs7) mpp48 48 gpio, dev(clkout), dev(burst/last) * Marvell Armada XP (mv78260 and mv78460 only) diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-xp.c b/drivers/pinctrl/mvebu/pinctrl-armada-xp.c index 74ff211..4674462 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-xp.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-xp.c @@ -109,11 +109,13 @@ static struct mvebu_mpp_mode armada_xp_mpp_modes[] = { MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), MPP_VAR_FUNCTION(0x1, "ge0", "txd5", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x2, "ge1", "txd0", V_MV78230_PLUS), + MPP_VAR_FUNCTION(0x3, "spi1", "mosi", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x4, "lcd", "d13", V_MV78230_PLUS)), MPP_MODE(14, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), MPP_VAR_FUNCTION(0x1, "ge0", "txd6", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x2, "ge1", "txd1", V_MV78230_PLUS), + MPP_VAR_FUNCTION(0x3, "spi1", "sck", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x4, "lcd", "d14", V_MV78230_PLUS)), MPP_MODE(15, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), @@ -124,11 +126,13 @@ static struct mvebu_mpp_mode armada_xp_mpp_modes[] = { MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), MPP_VAR_FUNCTION(0x1, "ge0", "txclk", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x2, "ge1", "txd3", V_MV78230_PLUS), + MPP_VAR_FUNCTION(0x3, "spi1", "cs0", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x4, "lcd", "d16", V_MV78230_PLUS)), MPP_MODE(17, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), MPP_VAR_FUNCTION(0x1, "ge0", "col", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x2, "ge1", "txctl", V_MV78230_PLUS), + MPP_VAR_FUNCTION(0x3, "spi1", "miso", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x4, "lcd", "d17", V_MV78230_PLUS)), MPP_MODE(18, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), @@ -239,14 +243,16 @@ static struct mvebu_mpp_mode armada_xp_mpp_modes[] = { MPP_VAR_FUNCTION(0x1, "spi0", "cs1", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x2, "uart2", "cts", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x4, "lcd", "vga-hsync", V_MV78230_PLUS), - MPP_VAR_FUNCTION(0x5, "pcie", "clkreq0", V_MV78230_PLUS)), + MPP_VAR_FUNCTION(0x5, "pcie", "clkreq0", V_MV78230_PLUS), + MPP_VAR_FUNCTION(0x6, "spi1", "cs1", V_MV78230_PLUS)), MPP_MODE(41, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), MPP_VAR_FUNCTION(0x1, "spi0", "cs2", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x2, "uart2", "rts", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x3, "sata1", "prsnt", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x4, "lcd", "vga-vsync", V_MV78230_PLUS), - MPP_VAR_FUNCTION(0x5, "pcie", "clkreq1", V_MV78230_PLUS)), + MPP_VAR_FUNCTION(0x5, "pcie", "clkreq1", V_MV78230_PLUS), + MPP_VAR_FUNCTION(0x6, "spi1", "cs2", V_MV78230_PLUS)), MPP_MODE(42, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), MPP_VAR_FUNCTION(0x1, "uart2", "rxd", V_MV78230_PLUS), @@ -258,33 +264,38 @@ static struct mvebu_mpp_mode armada_xp_mpp_modes[] = { MPP_VAR_FUNCTION(0x1, "uart2", "txd", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x2, "uart0", "rts", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x3, "spi0", "cs3", V_MV78230_PLUS), - MPP_VAR_FUNCTION(0x4, "pcie", "rstout", V_MV78230_PLUS)), + MPP_VAR_FUNCTION(0x4, "pcie", "rstout", V_MV78230_PLUS), + MPP_VAR_FUNCTION(0x6, "spi1", "cs3", V_MV78230_PLUS)), MPP_MODE(44, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), MPP_VAR_FUNCTION(0x1, "uart2", "cts", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x2, "uart3", "rxd", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x3, "spi0", "cs4", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x4, "dram", "bat", V_MV78230_PLUS), - MPP_VAR_FUNCTION(0x5, "pcie", "clkreq2", V_MV78230_PLUS)), + MPP_VAR_FUNCTION(0x5, "pcie", "clkreq2", V_MV78230_PLUS), + MPP_VAR_FUNCTION(0x6, "spi1", "cs4", V_MV78230_PLUS)), MPP_MODE(45, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), MPP_VAR_FUNCTION(0x1, "uart2", "rts", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x2, "uart3", "txd", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x3, "spi0", "cs5", V_MV78230_PLUS), - MPP_VAR_FUNCTION(0x4, "sata1", "prsnt", V_MV78230_PLUS)), + MPP_VAR_FUNCTION(0x4, "sata1", "prsnt", V_MV78230_PLUS), + MPP_VAR_FUNCTION(0x6, "spi1", "cs5", V_MV78230_PLUS)), MPP_MODE(46, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), MPP_VAR_FUNCTION(0x1, "uart3", "rts", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x2, "uart1", "rts", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x3, "spi0", "cs6", V_MV78230_PLUS), - MPP_VAR_FUNCTION(0x4, "sata0", "prsnt", V_MV78230_PLUS)), + MPP_VAR_FUNCTION(0x4, "sata0", "prsnt", V_MV78230_PLUS), + MPP_VAR_FUNCTION(0x6, "spi1", "cs6", V_MV78230_PLUS)), MPP_MODE(47, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), MPP_VAR_FUNCTION(0x1, "uart3", "cts", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x2, "uart1", "cts", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x3, "spi0", "cs7", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x4, "ref", "clkout", V_MV78230_PLUS), - MPP_VAR_FUNCTION(0x5, "pcie", "clkreq3", V_MV78230_PLUS)), + MPP_VAR_FUNCTION(0x5, "pcie", "clkreq3", V_MV78230_PLUS), + MPP_VAR_FUNCTION(0x6, "spi1", "cs7", V_MV78230_PLUS)), MPP_MODE(48, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), MPP_VAR_FUNCTION(0x1, "dev", "clkout", V_MV78230_PLUS), -- cgit v0.10.2 From fb53b61d77684b268e71246a3042a5f28ed14eb6 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 9 Jun 2015 18:47:18 +0200 Subject: pinctrl: mvebu: armada-xp: add nand rb function The latest version of the Armada XP datasheet documents a new NAND-related MPP function on MPP48, for which this commit adds support. Signed-off-by: Thomas Petazzoni Signed-off-by: Linus Walleij diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt index 5f64ee1..bd8af47 100644 --- a/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt @@ -73,7 +73,7 @@ mpp46 46 gpio, uart3(rts), uart1(rts), spi0(cs6), sata0(prsnt), spi1(cs6) mpp47 47 gpio, uart3(cts), uart1(cts), spi0(cs7), pcie(clkreq3), ref(clkout), spi1(cs7) -mpp48 48 gpio, dev(clkout), dev(burst/last) +mpp48 48 gpio, dev(clkout), dev(burst/last), nand(rb) * Marvell Armada XP (mv78260 and mv78460 only) diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-xp.c b/drivers/pinctrl/mvebu/pinctrl-armada-xp.c index 4674462..937d868 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-xp.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-xp.c @@ -299,7 +299,8 @@ static struct mvebu_mpp_mode armada_xp_mpp_modes[] = { MPP_MODE(48, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), MPP_VAR_FUNCTION(0x1, "dev", "clkout", V_MV78230_PLUS), - MPP_VAR_FUNCTION(0x2, "dev", "burst/last", V_MV78230_PLUS)), + MPP_VAR_FUNCTION(0x2, "dev", "burst/last", V_MV78230_PLUS), + MPP_VAR_FUNCTION(0x3, "nand", "rb", V_MV78230_PLUS)), MPP_MODE(49, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS), MPP_VAR_FUNCTION(0x1, "dev", "we3", V_MV78260_PLUS)), -- cgit v0.10.2 From b19bf379767943f0c094490c52f3d75f9397b503 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 9 Jun 2015 18:47:19 +0200 Subject: pinctrl: mvebu: armada-xp: add dram functions The latest Armada XP datasheet documents several new DRAM related functions on various MPPs. This commit adds the description of these new functions in the Armada XP pinctrl driver and its DT binding documentation. Signed-off-by: Thomas Petazzoni Signed-off-by: Linus Walleij diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt index bd8af47..76da722 100644 --- a/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt @@ -51,8 +51,8 @@ mpp29 29 gpio, lcd(ref-clk), tdm(int0), ptp(clk) mpp30 30 gpio, tdm(int1), sd0(clk) mpp31 31 gpio, tdm(int2), sd0(cmd) mpp32 32 gpio, tdm(int3), sd0(d0) -mpp33 33 gpio, tdm(int4), sd0(d1), dram(bat) -mpp34 34 gpio, tdm(int5), sd0(d2), sata0(prsnt) +mpp33 33 gpio, tdm(int4), sd0(d1), dram(bat), dram(vttctrl) +mpp34 34 gpio, tdm(int5), sd0(d2), sata0(prsnt), dram(deccerr) mpp35 35 gpio, tdm(int6), sd0(d3), sata1(prsnt) mpp36 36 gpio, spi0(mosi) mpp37 37 gpio, spi0(miso) @@ -68,7 +68,7 @@ mpp43 43 gpio, uart2(txd), uart0(rts), spi0(cs3), pcie(rstout), mpp44 44 gpio, uart2(cts), uart3(rxd), spi0(cs4), pcie(clkreq2), dram(bat), spi1(cs4) mpp45 45 gpio, uart2(rts), uart3(txd), spi0(cs5), sata1(prsnt), - spi1(cs5) + spi1(cs5), dram(vttctrl) mpp46 46 gpio, uart3(rts), uart1(rts), spi0(cs6), sata0(prsnt), spi1(cs6) mpp47 47 gpio, uart3(cts), uart1(cts), spi0(cs7), pcie(clkreq3), diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-xp.c b/drivers/pinctrl/mvebu/pinctrl-armada-xp.c index 937d868..bf70e09 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-xp.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-xp.c @@ -215,12 +215,14 @@ static struct mvebu_mpp_mode armada_xp_mpp_modes[] = { MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), MPP_VAR_FUNCTION(0x1, "sd0", "d1", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x3, "tdm", "int4", V_MV78230_PLUS), - MPP_VAR_FUNCTION(0x4, "dram", "bat", V_MV78230_PLUS)), + MPP_VAR_FUNCTION(0x4, "dram", "bat", V_MV78230_PLUS), + MPP_VAR_FUNCTION(0x5, "dram", "vttctrl", V_MV78230_PLUS)), MPP_MODE(34, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), MPP_VAR_FUNCTION(0x1, "sd0", "d2", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x2, "sata0", "prsnt", V_MV78230_PLUS), - MPP_VAR_FUNCTION(0x3, "tdm", "int5", V_MV78230_PLUS)), + MPP_VAR_FUNCTION(0x3, "tdm", "int5", V_MV78230_PLUS), + MPP_VAR_FUNCTION(0x4, "dram", "deccerr", V_MV78230_PLUS)), MPP_MODE(35, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), MPP_VAR_FUNCTION(0x1, "sd0", "d3", V_MV78230_PLUS), @@ -280,6 +282,7 @@ static struct mvebu_mpp_mode armada_xp_mpp_modes[] = { MPP_VAR_FUNCTION(0x2, "uart3", "txd", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x3, "spi0", "cs5", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x4, "sata1", "prsnt", V_MV78230_PLUS), + MPP_VAR_FUNCTION(0x5, "dram", "vttctrl", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x6, "spi1", "cs5", V_MV78230_PLUS)), MPP_MODE(46, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), -- cgit v0.10.2 From 503cfd9f8adc1cb886f06b700c2edc794fe14d50 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 9 Jun 2015 18:47:20 +0200 Subject: pinctrl: mvebu: armada-38x: add sata functions The latest version of the Armada 38x datasheet documents several new SATA related functions on various MPP pins. This commit adds the description of these new functions to the Armada 38x pinctrl driver as well as to its DT binding documentation. Signed-off-by: Thomas Petazzoni Signed-off-by: Linus Walleij diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-38x-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-38x-pinctrl.txt index 203220d..066e26a 100644 --- a/Documentation/devicetree/bindings/pinctrl/marvell,armada-38x-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-38x-pinctrl.txt @@ -32,11 +32,11 @@ mpp13 13 gpio, ge0(rxd1), pcie0(clkreq), pcie1(clkreq) [1], spi0(c mpp14 14 gpio, ge0(rxd2), ptp(clk), dram(vttctrl), spi0(cs3), dev(we1), pcie3(clkreq) mpp15 15 gpio, ge0(rxd3), ge(mdc slave), pcie0(rstout), spi0(mosi) mpp16 16 gpio, ge0(rxctl), ge(mdio slave), dram(deccerr), spi0(miso), pcie0(clkreq), pcie1(clkreq) [1] -mpp17 17 gpio, ge0(rxclk), ptp(clk), ua1(rxd), spi0(sck), sata1(prsnt) +mpp17 17 gpio, ge0(rxclk), ptp(clk), ua1(rxd), spi0(sck), sata1(prsnt), sata0(prsnt) mpp18 18 gpio, ge0(rxerr), ptp(trig), ua1(txd), spi0(cs0) mpp19 19 gpio, ge0(col), ptp(evreq), ge0(txerr), sata1(prsnt), ua0(cts) mpp20 20 gpio, ge0(txclk), ptp(clk), sata0(prsnt), ua0(rts) -mpp21 21 gpio, spi0(cs1), ge1(rxd0), sata0(prsnt), sd0(cmd), dev(bootcs) +mpp21 21 gpio, spi0(cs1), ge1(rxd0), sata0(prsnt), sd0(cmd), dev(bootcs), sata1(prsnt) mpp22 22 gpio, spi0(mosi), dev(ad0) mpp23 23 gpio, spi0(sck), dev(ad2) mpp24 24 gpio, spi0(miso), ua0(cts), ua1(rxd), sd0(d4), dev(ready) diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-38x.c b/drivers/pinctrl/mvebu/pinctrl-armada-38x.c index b5006f7..8b401b5 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-38x.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-38x.c @@ -133,7 +133,8 @@ static struct mvebu_mpp_mode armada_38x_mpp_modes[] = { MPP_VAR_FUNCTION(2, "ptp", "clk", V_88F6810_PLUS), MPP_VAR_FUNCTION(3, "ua1", "rxd", V_88F6810_PLUS), MPP_VAR_FUNCTION(4, "spi0", "sck", V_88F6810_PLUS), - MPP_VAR_FUNCTION(5, "sata1", "prsnt", V_88F6810_PLUS)), + MPP_VAR_FUNCTION(5, "sata1", "prsnt", V_88F6810_PLUS), + MPP_VAR_FUNCTION(6, "sata0", "prsnt", V_88F6810_PLUS)), MPP_MODE(18, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), MPP_VAR_FUNCTION(1, "ge0", "rxerr", V_88F6810_PLUS), @@ -161,7 +162,8 @@ static struct mvebu_mpp_mode armada_38x_mpp_modes[] = { MPP_VAR_FUNCTION(2, "ge1", "rxd0", V_88F6810_PLUS), MPP_VAR_FUNCTION(3, "sata0", "prsnt", V_88F6810_PLUS), MPP_VAR_FUNCTION(4, "sd0", "cmd", V_88F6810_PLUS), - MPP_VAR_FUNCTION(5, "dev", "bootcs", V_88F6810_PLUS)), + MPP_VAR_FUNCTION(5, "dev", "bootcs", V_88F6810_PLUS), + MPP_VAR_FUNCTION(6, "sata1", "prsnt", V_88F6810_PLUS)), MPP_MODE(22, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), MPP_VAR_FUNCTION(1, "spi0", "mosi", V_88F6810_PLUS), -- cgit v0.10.2 From 9ce28fccb0e69e85e0432e4f416f4d1afebb4dba Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 9 Jun 2015 18:47:21 +0200 Subject: pinctrl: mvebu: armada-38x: add nand functions The latest version of the Armada 38x datasheet documents several new NAND related functions on various MPP pins. This commit adds the description of these new functions to the Armada 38x pinctrl driver as well as to its DT binding documentation. Signed-off-by: Thomas Petazzoni Signed-off-by: Linus Walleij diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-38x-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-38x-pinctrl.txt index 066e26a..278887d 100644 --- a/Documentation/devicetree/bindings/pinctrl/marvell,armada-38x-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-38x-pinctrl.txt @@ -56,9 +56,9 @@ mpp37 37 gpio, ptp(clk), ge1(rxclk), sd0(d3), dev(ad8) mpp38 38 gpio, ptp(evreq), ge1(rxd1), ref(clk_out0), sd0(d0), dev(ad4) mpp39 39 gpio, i2c1(sck), ge1(rxd2), ua0(cts), sd0(d1), dev(a2) mpp40 40 gpio, i2c1(sda), ge1(rxd3), ua0(rts), sd0(d2), dev(ad6) -mpp41 41 gpio, ua1(rxd), ge1(rxctl), ua0(cts), spi1(cs3), dev(burst/last) +mpp41 41 gpio, ua1(rxd), ge1(rxctl), ua0(cts), spi1(cs3), dev(burst/last), nand(rb0) mpp42 42 gpio, ua1(txd), ua0(rts), dev(ad7) -mpp43 43 gpio, pcie0(clkreq), dram(vttctrl), dram(deccerr), spi1(cs2), dev(clkout) +mpp43 43 gpio, pcie0(clkreq), dram(vttctrl), dram(deccerr), spi1(cs2), dev(clkout), nand(rb1) mpp44 44 gpio, sata0(prsnt), sata1(prsnt), sata2(prsnt) [2], sata3(prsnt) [3] mpp45 45 gpio, ref(clk_out0), pcie0(rstout) mpp46 46 gpio, ref(clk_out1), pcie0(rstout) diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-38x.c b/drivers/pinctrl/mvebu/pinctrl-armada-38x.c index 8b401b5..ac8f297 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-38x.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-38x.c @@ -268,7 +268,8 @@ static struct mvebu_mpp_mode armada_38x_mpp_modes[] = { MPP_VAR_FUNCTION(2, "ge1", "rxctl", V_88F6810_PLUS), MPP_VAR_FUNCTION(3, "ua0", "cts", V_88F6810_PLUS), MPP_VAR_FUNCTION(4, "spi1", "cs3", V_88F6810_PLUS), - MPP_VAR_FUNCTION(5, "dev", "burst/last", V_88F6810_PLUS)), + MPP_VAR_FUNCTION(5, "dev", "burst/last", V_88F6810_PLUS), + MPP_VAR_FUNCTION(6, "nand", "rb0", V_88F6810_PLUS)), MPP_MODE(42, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), MPP_VAR_FUNCTION(1, "ua1", "txd", V_88F6810_PLUS), @@ -280,7 +281,8 @@ static struct mvebu_mpp_mode armada_38x_mpp_modes[] = { MPP_VAR_FUNCTION(2, "dram", "vttctrl", V_88F6810_PLUS), MPP_VAR_FUNCTION(3, "dram", "deccerr", V_88F6810_PLUS), MPP_VAR_FUNCTION(4, "spi1", "cs2", V_88F6810_PLUS), - MPP_VAR_FUNCTION(5, "dev", "clkout", V_88F6810_PLUS)), + MPP_VAR_FUNCTION(5, "dev", "clkout", V_88F6810_PLUS), + MPP_VAR_FUNCTION(6, "nand", "rb1", V_88F6810_PLUS)), MPP_MODE(44, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), MPP_VAR_FUNCTION(1, "sata0", "prsnt", V_88F6810_PLUS), -- cgit v0.10.2 From f7ad5b29ce7272da9589aabfa4d94502881b9556 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 9 Jun 2015 18:47:22 +0200 Subject: pinctrl: mvebu: armada-38x: add ua1 functions The latest version of the Armada 38x datasheet documents several new UART1 related functions on various MPP pins. This commit adds the description of these new functions to the Armada 38x pinctrl driver as well as to its DT binding documentation. Signed-off-by: Thomas Petazzoni Signed-off-by: Linus Walleij diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-38x-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-38x-pinctrl.txt index 278887d..4330676 100644 --- a/Documentation/devicetree/bindings/pinctrl/marvell,armada-38x-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-38x-pinctrl.txt @@ -60,8 +60,8 @@ mpp41 41 gpio, ua1(rxd), ge1(rxctl), ua0(cts), spi1(cs3), dev(burs mpp42 42 gpio, ua1(txd), ua0(rts), dev(ad7) mpp43 43 gpio, pcie0(clkreq), dram(vttctrl), dram(deccerr), spi1(cs2), dev(clkout), nand(rb1) mpp44 44 gpio, sata0(prsnt), sata1(prsnt), sata2(prsnt) [2], sata3(prsnt) [3] -mpp45 45 gpio, ref(clk_out0), pcie0(rstout) -mpp46 46 gpio, ref(clk_out1), pcie0(rstout) +mpp45 45 gpio, ref(clk_out0), pcie0(rstout), ua1(rxd) +mpp46 46 gpio, ref(clk_out1), pcie0(rstout), ua1(txd) mpp47 47 gpio, sata0(prsnt), sata1(prsnt), sata2(prsnt) [2], sata3(prsnt) [2] mpp48 48 gpio, sata0(prsnt), dram(vttctrl), tdm(pclk), audio(mclk), sd0(d4), pcie0(clkreq) mpp49 49 gpio, sata2(prsnt) [2], sata3(prsnt) [2], tdm(fsync), audio(lrclk), sd0(d5), pcie1(clkreq) @@ -70,10 +70,10 @@ mpp51 51 gpio, tdm(dtx), audio(sdo), dram(deccerr) mpp52 52 gpio, pcie0(rstout), tdm(int), audio(sdi), sd0(d6) mpp53 53 gpio, sata1(prsnt), sata0(prsnt), tdm(rst), audio(bclk), sd0(d7) mpp54 54 gpio, sata0(prsnt), sata1(prsnt), pcie0(rstout), ge0(txerr), sd0(d3) -mpp55 55 gpio, ua1(cts), ge(mdio), pcie1(clkreq) [1], spi1(cs1), sd0(d0) -mpp56 56 gpio, ua1(rts), ge(mdc), dram(deccerr), spi1(mosi) -mpp57 57 gpio, spi1(sck), sd0(clk) -mpp58 58 gpio, pcie1(clkreq) [1], i2c1(sck), pcie2(clkreq), spi1(miso), sd0(d1) +mpp55 55 gpio, ua1(cts), ge(mdio), pcie1(clkreq) [1], spi1(cs1), sd0(d0), ua1(rxd) +mpp56 56 gpio, ua1(rts), ge(mdc), dram(deccerr), spi1(mosi), ua1(txd) +mpp57 57 gpio, spi1(sck), sd0(clk), ua1(txd) +mpp58 58 gpio, pcie1(clkreq) [1], i2c1(sck), pcie2(clkreq), spi1(miso), sd0(d1), ua1(rxd) mpp59 59 gpio, pcie0(rstout), i2c1(sda), spi1(cs0), sd0(d2) [1]: only available on 88F6820 and 88F6828 diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-38x.c b/drivers/pinctrl/mvebu/pinctrl-armada-38x.c index ac8f297..370c73b 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-38x.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-38x.c @@ -292,11 +292,13 @@ static struct mvebu_mpp_mode armada_38x_mpp_modes[] = { MPP_MODE(45, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), MPP_VAR_FUNCTION(1, "ref", "clk_out0", V_88F6810_PLUS), - MPP_VAR_FUNCTION(2, "pcie0", "rstout", V_88F6810_PLUS)), + MPP_VAR_FUNCTION(2, "pcie0", "rstout", V_88F6810_PLUS), + MPP_VAR_FUNCTION(6, "ua1", "rxd", V_88F6810_PLUS)), MPP_MODE(46, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), MPP_VAR_FUNCTION(1, "ref", "clk_out1", V_88F6810_PLUS), - MPP_VAR_FUNCTION(2, "pcie0", "rstout", V_88F6810_PLUS)), + MPP_VAR_FUNCTION(2, "pcie0", "rstout", V_88F6810_PLUS), + MPP_VAR_FUNCTION(6, "ua1", "txd", V_88F6810_PLUS)), MPP_MODE(47, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), MPP_VAR_FUNCTION(1, "sata0", "prsnt", V_88F6810_PLUS), @@ -356,24 +358,28 @@ static struct mvebu_mpp_mode armada_38x_mpp_modes[] = { MPP_VAR_FUNCTION(2, "ge", "mdio", V_88F6810_PLUS), MPP_VAR_FUNCTION(3, "pcie1", "clkreq", V_88F6820_PLUS), MPP_VAR_FUNCTION(4, "spi1", "cs1", V_88F6810_PLUS), - MPP_VAR_FUNCTION(5, "sd0", "d0", V_88F6810_PLUS)), + MPP_VAR_FUNCTION(5, "sd0", "d0", V_88F6810_PLUS), + MPP_VAR_FUNCTION(6, "ua1", "rxd", V_88F6810_PLUS)), MPP_MODE(56, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), MPP_VAR_FUNCTION(1, "ua1", "rts", V_88F6810_PLUS), MPP_VAR_FUNCTION(2, "ge", "mdc", V_88F6810_PLUS), MPP_VAR_FUNCTION(3, "dram", "deccerr", V_88F6810_PLUS), - MPP_VAR_FUNCTION(4, "spi1", "mosi", V_88F6810_PLUS)), + MPP_VAR_FUNCTION(4, "spi1", "mosi", V_88F6810_PLUS), + MPP_VAR_FUNCTION(6, "ua1", "txd", V_88F6810_PLUS)), MPP_MODE(57, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), MPP_VAR_FUNCTION(4, "spi1", "sck", V_88F6810_PLUS), - MPP_VAR_FUNCTION(5, "sd0", "clk", V_88F6810_PLUS)), + MPP_VAR_FUNCTION(5, "sd0", "clk", V_88F6810_PLUS), + MPP_VAR_FUNCTION(6, "ua1", "txd", V_88F6810_PLUS)), MPP_MODE(58, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), MPP_VAR_FUNCTION(1, "pcie1", "clkreq", V_88F6820_PLUS), MPP_VAR_FUNCTION(2, "i2c1", "sck", V_88F6810_PLUS), MPP_VAR_FUNCTION(3, "pcie2", "clkreq", V_88F6810_PLUS), MPP_VAR_FUNCTION(4, "spi1", "miso", V_88F6810_PLUS), - MPP_VAR_FUNCTION(5, "sd0", "d1", V_88F6810_PLUS)), + MPP_VAR_FUNCTION(5, "sd0", "d1", V_88F6810_PLUS), + MPP_VAR_FUNCTION(6, "ua1", "rxd", V_88F6810_PLUS)), MPP_MODE(59, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), MPP_VAR_FUNCTION(1, "pcie0", "rstout", V_88F6810_PLUS), -- cgit v0.10.2 From f9dbbe011cce41905db77b97e38928b30b1792d5 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 9 Jun 2015 18:47:23 +0200 Subject: pinctrl: mvebu: armada-38x: add ptp functions The latest version of the Armada 38x datasheet documents several new PTP related functions on various MPP pins. This commit adds the description of these new functions to the Armada 38x pinctrl driver as well as to its DT binding documentation. Signed-off-by: Thomas Petazzoni Signed-off-by: Linus Walleij diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-38x-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-38x-pinctrl.txt index 4330676..54ec4c0 100644 --- a/Documentation/devicetree/bindings/pinctrl/marvell,armada-38x-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-38x-pinctrl.txt @@ -66,9 +66,9 @@ mpp47 47 gpio, sata0(prsnt), sata1(prsnt), sata2(prsnt) [2], sata3 mpp48 48 gpio, sata0(prsnt), dram(vttctrl), tdm(pclk), audio(mclk), sd0(d4), pcie0(clkreq) mpp49 49 gpio, sata2(prsnt) [2], sata3(prsnt) [2], tdm(fsync), audio(lrclk), sd0(d5), pcie1(clkreq) mpp50 50 gpio, pcie0(rstout), tdm(drx), audio(extclk), sd0(cmd) -mpp51 51 gpio, tdm(dtx), audio(sdo), dram(deccerr) -mpp52 52 gpio, pcie0(rstout), tdm(int), audio(sdi), sd0(d6) -mpp53 53 gpio, sata1(prsnt), sata0(prsnt), tdm(rst), audio(bclk), sd0(d7) +mpp51 51 gpio, tdm(dtx), audio(sdo), dram(deccerr), ptp(trig) +mpp52 52 gpio, pcie0(rstout), tdm(int), audio(sdi), sd0(d6), ptp(clk) +mpp53 53 gpio, sata1(prsnt), sata0(prsnt), tdm(rst), audio(bclk), sd0(d7), ptp(evreq) mpp54 54 gpio, sata0(prsnt), sata1(prsnt), pcie0(rstout), ge0(txerr), sd0(d3) mpp55 55 gpio, ua1(cts), ge(mdio), pcie1(clkreq) [1], spi1(cs1), sd0(d0), ua1(rxd) mpp56 56 gpio, ua1(rts), ge(mdc), dram(deccerr), spi1(mosi), ua1(txd) diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-38x.c b/drivers/pinctrl/mvebu/pinctrl-armada-38x.c index 370c73b..6ec82c6 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-38x.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-38x.c @@ -331,20 +331,23 @@ static struct mvebu_mpp_mode armada_38x_mpp_modes[] = { MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), MPP_VAR_FUNCTION(3, "tdm", "dtx", V_88F6810_PLUS), MPP_VAR_FUNCTION(4, "audio", "sdo", V_88F6810_PLUS), - MPP_VAR_FUNCTION(5, "dram", "deccerr", V_88F6810_PLUS)), + MPP_VAR_FUNCTION(5, "dram", "deccerr", V_88F6810_PLUS), + MPP_VAR_FUNCTION(6, "ptp", "trig", V_88F6810_PLUS)), MPP_MODE(52, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), MPP_VAR_FUNCTION(1, "pcie0", "rstout", V_88F6810_PLUS), MPP_VAR_FUNCTION(3, "tdm", "int", V_88F6810_PLUS), MPP_VAR_FUNCTION(4, "audio", "sdi", V_88F6810_PLUS), - MPP_VAR_FUNCTION(5, "sd0", "d6", V_88F6810_PLUS)), + MPP_VAR_FUNCTION(5, "sd0", "d6", V_88F6810_PLUS), + MPP_VAR_FUNCTION(6, "ptp", "clk", V_88F6810_PLUS)), MPP_MODE(53, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), MPP_VAR_FUNCTION(1, "sata1", "prsnt", V_88F6810_PLUS), MPP_VAR_FUNCTION(2, "sata0", "prsnt", V_88F6810_PLUS), MPP_VAR_FUNCTION(3, "tdm", "rst", V_88F6810_PLUS), MPP_VAR_FUNCTION(4, "audio", "bclk", V_88F6810_PLUS), - MPP_VAR_FUNCTION(5, "sd0", "d7", V_88F6810_PLUS)), + MPP_VAR_FUNCTION(5, "sd0", "d7", V_88F6810_PLUS), + MPP_VAR_FUNCTION(6, "ptp", "evreq", V_88F6810_PLUS)), MPP_MODE(54, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), MPP_VAR_FUNCTION(1, "sata0", "prsnt", V_88F6810_PLUS), -- cgit v0.10.2 From c0adb877a2491669c58afbf79e1b921d8e2b79b9 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 9 Jun 2015 18:47:24 +0200 Subject: pinctrl: mvebu: armada-39x: add missing PCIe functions The latest version of the Armada 39x datasheet documents several new PCIe related functions on various MPP pins. This commit adds the description of these new functions to the Armada 39x pinctrl driver as well as to its DT binding documentation. Signed-off-by: Thomas Petazzoni Signed-off-by: Linus Walleij diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-39x-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-39x-pinctrl.txt index 1dd76e9..2e4725f 100644 --- a/Documentation/devicetree/bindings/pinctrl/marvell,armada-39x-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-39x-pinctrl.txt @@ -27,10 +27,10 @@ mpp9 9 gpio, dev(ad11), ptp(clk) mpp10 10 gpio, dev(ad12), ptp(evreq) mpp11 11 gpio, dev(ad13), led(clk) mpp12 12 gpio, pcie0(rstout), dev(ad14), led(stb) -mpp13 13 gpio, dev(ad15), led(data) +mpp13 13 gpio, dev(ad15), pcie2(clkreq), led(data) mpp14 14 gpio, dram(vttctrl), dev(we1), ua1(txd) mpp15 15 gpio, pcie0(rstout), spi0(mosi), i2c1(sck) -mpp16 16 gpio, dram(deccerr), spi0(miso), i2c1(sda) +mpp16 16 gpio, dram(deccerr), spi0(miso), pcie0(clkreq), i2c1(sda) mpp17 17 gpio, ua1(rxd), spi0(sck), smi(mdio) mpp18 18 gpio, ua1(txd), spi0(cs0), i2c2(sck) mpp19 19 gpio, sata1(prsnt) [1], ua0(cts), ua1(rxd), i2c2(sda) diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-39x.c b/drivers/pinctrl/mvebu/pinctrl-armada-39x.c index 08ee427..afab0c1 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-39x.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-39x.c @@ -95,6 +95,7 @@ static struct mvebu_mpp_mode armada_39x_mpp_modes[] = { MPP_MODE(13, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), MPP_VAR_FUNCTION(5, "dev", "ad15", V_88F6920_PLUS), + MPP_VAR_FUNCTION(6, "pcie2", "clkreq", V_88F6920_PLUS), MPP_VAR_FUNCTION(7, "led", "data", V_88F6920_PLUS)), MPP_MODE(14, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), @@ -110,6 +111,7 @@ static struct mvebu_mpp_mode armada_39x_mpp_modes[] = { MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), MPP_VAR_FUNCTION(3, "dram", "deccerr", V_88F6920_PLUS), MPP_VAR_FUNCTION(4, "spi0", "miso", V_88F6920_PLUS), + MPP_VAR_FUNCTION(5, "pcie0", "clkreq", V_88F6920_PLUS), MPP_VAR_FUNCTION(7, "i2c1", "sda", V_88F6920_PLUS)), MPP_MODE(17, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), -- cgit v0.10.2 From 6afc0c0f5bcffd3d0c47d464b02030d54aac91bf Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 9 Jun 2015 18:47:25 +0200 Subject: pinctrl: mvebu: armada-39x: add missing SATA functions The latest version of the Armada 39x datasheet documents several new SATA related functions on various MPP pins. This commit adds the description of these new functions to the Armada 39x pinctrl driver as well as to its DT binding documentation. Signed-off-by: Thomas Petazzoni Signed-off-by: Linus Walleij diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-39x-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-39x-pinctrl.txt index 2e4725f..bceb6c5 100644 --- a/Documentation/devicetree/bindings/pinctrl/marvell,armada-39x-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-39x-pinctrl.txt @@ -31,11 +31,12 @@ mpp13 13 gpio, dev(ad15), pcie2(clkreq), led(data) mpp14 14 gpio, dram(vttctrl), dev(we1), ua1(txd) mpp15 15 gpio, pcie0(rstout), spi0(mosi), i2c1(sck) mpp16 16 gpio, dram(deccerr), spi0(miso), pcie0(clkreq), i2c1(sda) -mpp17 17 gpio, ua1(rxd), spi0(sck), smi(mdio) +mpp17 17 gpio, ua1(rxd), spi0(sck), sata1(prsnt) [1], sata0(prsnt) [1], smi(mdio) mpp18 18 gpio, ua1(txd), spi0(cs0), i2c2(sck) mpp19 19 gpio, sata1(prsnt) [1], ua0(cts), ua1(rxd), i2c2(sda) mpp20 20 gpio, sata0(prsnt) [1], ua0(rts), ua1(txd), smi(mdc) -mpp21 21 gpio, spi0(cs1), sata0(prsnt) [1], sd0(cmd), dev(bootcs), ge(rxd0) +mpp21 21 gpio, spi0(cs1), sata0(prsnt) [1], sd0(cmd), dev(bootcs), + sata1(prsnt) [1], ge(rxd0) mpp22 22 gpio, spi0(mosi), dev(ad0) mpp23 23 gpio, spi0(sck), dev(ad2) mpp24 24 gpio, spi0(miso), ua0(cts), ua1(rxd), sd0(d4), dev(ready) @@ -58,12 +59,15 @@ mpp40 40 gpio, i2c1(sda), ua0(rts), sd0(d2), dev(ad6), ge(rxd3) mpp41 41 gpio, ua1(rxd), ua0(cts), spi1(cs3), dev(burst/last), nand(rb0), ge(rxctl) mpp42 42 gpio, ua1(txd), ua0(rts), dev(ad7) mpp43 43 gpio, pcie0(clkreq), dram(vttctrl), dram(deccerr), spi1(cs2), dev(clkout), nand(rb1) -mpp44 44 gpio, sata0(prsnt) [1], sata1(prsnt) [1], led(clk) +mpp44 44 gpio, sata0(prsnt) [1], sata1(prsnt) [1], sata2(prsnt) [1], + sata3(prsnt) [1], led(clk) mpp45 45 gpio, ref(clk), pcie0(rstout), ua1(rxd) mpp46 46 gpio, ref(clk), pcie0(rstout), ua1(txd), led(stb) -mpp47 47 gpio, sata0(prsnt) [1], sata1(prsnt) [1], led(data) +mpp47 47 gpio, sata0(prsnt) [1], sata1(prsnt) [1], sata2(prsnt) [1], + sata3(prsnt) [1], led(data) mpp48 48 gpio, sata0(prsnt) [1], dram(vttctrl), tdm(pclk) [1], audio(mclk) [1], sd0(d4), pcie0(clkreq), ua1(txd) -mpp49 49 gpio, tdm(fsync) [1], audio(lrclk) [1], sd0(d5), ua2(rxd) +mpp49 49 gpio, sata2(prsnt) [1], sata3(prsnt) [1], tdm(fsync) [1], + audio(lrclk) [1], sd0(d5), ua2(rxd) mpp50 50 gpio, pcie0(rstout), tdm(drx) [1], audio(extclk) [1], sd0(cmd), ua2(rxd) mpp51 51 gpio, tdm(dtx) [1], audio(sdo) [1], dram(deccerr), ua2(txd) mpp52 52 gpio, pcie0(rstout), tdm(int) [1], audio(sdi) [1], sd0(d6), i2c3(sck) diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-39x.c b/drivers/pinctrl/mvebu/pinctrl-armada-39x.c index afab0c1..bae1199 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-39x.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-39x.c @@ -117,6 +117,8 @@ static struct mvebu_mpp_mode armada_39x_mpp_modes[] = { MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), MPP_VAR_FUNCTION(3, "ua1", "rxd", V_88F6920_PLUS), MPP_VAR_FUNCTION(4, "spi0", "sck", V_88F6920_PLUS), + MPP_VAR_FUNCTION(5, "sata1", "prsnt", V_88F6928), + MPP_VAR_FUNCTION(6, "sata0", "prsnt", V_88F6928), MPP_VAR_FUNCTION(7, "smi", "mdio", V_88F6920_PLUS)), MPP_MODE(18, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), @@ -141,6 +143,7 @@ static struct mvebu_mpp_mode armada_39x_mpp_modes[] = { MPP_VAR_FUNCTION(3, "sata0", "prsnt", V_88F6928), MPP_VAR_FUNCTION(4, "sd0", "cmd", V_88F6920_PLUS), MPP_VAR_FUNCTION(5, "dev", "bootcs", V_88F6920_PLUS), + MPP_VAR_FUNCTION(6, "sata1", "prsnt", V_88F6928), MPP_VAR_FUNCTION(8, "ge", "rxd0", V_88F6920_PLUS)), MPP_MODE(22, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), @@ -262,6 +265,8 @@ static struct mvebu_mpp_mode armada_39x_mpp_modes[] = { MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), MPP_VAR_FUNCTION(1, "sata0", "prsnt", V_88F6928), MPP_VAR_FUNCTION(2, "sata1", "prsnt", V_88F6928), + MPP_VAR_FUNCTION(3, "sata2", "prsnt", V_88F6928), + MPP_VAR_FUNCTION(4, "sata3", "prsnt", V_88F6928), MPP_VAR_FUNCTION(7, "led", "clk", V_88F6920_PLUS)), MPP_MODE(45, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), @@ -278,6 +283,8 @@ static struct mvebu_mpp_mode armada_39x_mpp_modes[] = { MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), MPP_VAR_FUNCTION(1, "sata0", "prsnt", V_88F6928), MPP_VAR_FUNCTION(2, "sata1", "prsnt", V_88F6928), + MPP_VAR_FUNCTION(3, "sata2", "prsnt", V_88F6928), + MPP_VAR_FUNCTION(5, "sata3", "prsnt", V_88F6928), MPP_VAR_FUNCTION(7, "led", "data", V_88F6920_PLUS)), MPP_MODE(48, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), @@ -290,6 +297,8 @@ static struct mvebu_mpp_mode armada_39x_mpp_modes[] = { MPP_VAR_FUNCTION(7, "ua1", "txd", V_88F6920_PLUS)), MPP_MODE(49, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), + MPP_VAR_FUNCTION(1, "sata2", "prsnt", V_88F6928), + MPP_VAR_FUNCTION(2, "sata3", "prsnt", V_88F6928), MPP_VAR_FUNCTION(3, "tdm", "fsync", V_88F6928), MPP_VAR_FUNCTION(4, "audio", "lrclk", V_88F6928), MPP_VAR_FUNCTION(5, "sd0", "d5", V_88F6920_PLUS), -- cgit v0.10.2 From e73ac02dc132dcef1add62a1fac3e77a7ce17371 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 9 Jun 2015 18:47:26 +0200 Subject: pinctrl: mvebu: armada-39x: add support for Armada 395 variant The Armada 39x SoC family has grown a new variant, the Armada 395, which sits between the Armada 390 and Armada 398 in terms of features. This commit adds support for this additional variant to the Armada 39x pinctrl driver. Signed-off-by: Thomas Petazzoni Signed-off-by: Linus Walleij diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-39x-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-39x-pinctrl.txt index bceb6c5..a40b60f1 100644 --- a/Documentation/devicetree/bindings/pinctrl/marvell,armada-39x-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-39x-pinctrl.txt @@ -4,8 +4,9 @@ Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding part and usage. Required properties: -- compatible: "marvell,88f6920-pinctrl", "marvell,88f6928-pinctrl" - depending on the specific variant of the SoC being used. +- compatible: "marvell,88f6920-pinctrl", "marvell,88f6925-pinctrl" or + "marvell,88f6928-pinctrl" depending on the specific variant of the + SoC being used. - reg: register specifier of MPP registers Available mpp pins/groups and functions: @@ -59,19 +60,19 @@ mpp40 40 gpio, i2c1(sda), ua0(rts), sd0(d2), dev(ad6), ge(rxd3) mpp41 41 gpio, ua1(rxd), ua0(cts), spi1(cs3), dev(burst/last), nand(rb0), ge(rxctl) mpp42 42 gpio, ua1(txd), ua0(rts), dev(ad7) mpp43 43 gpio, pcie0(clkreq), dram(vttctrl), dram(deccerr), spi1(cs2), dev(clkout), nand(rb1) -mpp44 44 gpio, sata0(prsnt) [1], sata1(prsnt) [1], sata2(prsnt) [1], - sata3(prsnt) [1], led(clk) +mpp44 44 gpio, sata0(prsnt) [1], sata1(prsnt) [1], sata2(prsnt) [2], + sata3(prsnt) [2], led(clk) mpp45 45 gpio, ref(clk), pcie0(rstout), ua1(rxd) mpp46 46 gpio, ref(clk), pcie0(rstout), ua1(txd), led(stb) -mpp47 47 gpio, sata0(prsnt) [1], sata1(prsnt) [1], sata2(prsnt) [1], - sata3(prsnt) [1], led(data) -mpp48 48 gpio, sata0(prsnt) [1], dram(vttctrl), tdm(pclk) [1], audio(mclk) [1], sd0(d4), pcie0(clkreq), ua1(txd) -mpp49 49 gpio, sata2(prsnt) [1], sata3(prsnt) [1], tdm(fsync) [1], - audio(lrclk) [1], sd0(d5), ua2(rxd) -mpp50 50 gpio, pcie0(rstout), tdm(drx) [1], audio(extclk) [1], sd0(cmd), ua2(rxd) -mpp51 51 gpio, tdm(dtx) [1], audio(sdo) [1], dram(deccerr), ua2(txd) -mpp52 52 gpio, pcie0(rstout), tdm(int) [1], audio(sdi) [1], sd0(d6), i2c3(sck) -mpp53 53 gpio, sata1(prsnt) [1], sata0(prsnt) [1], tdm(rst) [1], audio(bclk) [1], sd0(d7), i2c3(sda) +mpp47 47 gpio, sata0(prsnt) [1], sata1(prsnt) [1], sata2(prsnt) [2], + sata3(prsnt) [2], led(data) +mpp48 48 gpio, sata0(prsnt) [1], dram(vttctrl), tdm(pclk) [2], audio(mclk) [2], sd0(d4), pcie0(clkreq), ua1(txd) +mpp49 49 gpio, sata2(prsnt) [2], sata3(prsnt) [2], tdm(fsync) [2], + audio(lrclk) [2], sd0(d5), ua2(rxd) +mpp50 50 gpio, pcie0(rstout), tdm(drx) [2], audio(extclk) [2], sd0(cmd), ua2(rxd) +mpp51 51 gpio, tdm(dtx) [2], audio(sdo) [2], dram(deccerr), ua2(txd) +mpp52 52 gpio, pcie0(rstout), tdm(int) [2], audio(sdi) [2], sd0(d6), i2c3(sck) +mpp53 53 gpio, sata1(prsnt) [1], sata0(prsnt) [1], tdm(rst) [2], audio(bclk) [2], sd0(d7), i2c3(sda) mpp54 54 gpio, sata0(prsnt) [1], sata1(prsnt) [1], pcie0(rstout), sd0(d3), ua3(txd) mpp55 55 gpio, ua1(cts), spi1(cs1), sd0(d0), ua1(rxd), ua3(rxd) mpp56 56 gpio, ua1(rts), dram(deccerr), spi1(mosi), ua1(txd) @@ -79,4 +80,5 @@ mpp57 57 gpio, spi1(sck), sd0(clk), ua1(txd) mpp58 58 gpio, i2c1(sck), pcie2(clkreq), spi1(miso), sd0(d1), ua1(rxd) mpp59 59 gpio, pcie0(rstout), i2c1(sda), spi1(cs0), sd0(d2) -[1]: only available on 88F6928 +[1]: only available on 88F6925/88F6928 +[2]: only available on 88F6928 diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-39x.c b/drivers/pinctrl/mvebu/pinctrl-armada-39x.c index bae1199..fcfe9b4 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-39x.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-39x.c @@ -36,8 +36,10 @@ static int armada_39x_mpp_ctrl_set(unsigned pid, unsigned long config) enum { V_88F6920 = BIT(0), - V_88F6928 = BIT(1), - V_88F6920_PLUS = (V_88F6920 | V_88F6928), + V_88F6925 = BIT(1), + V_88F6928 = BIT(2), + V_88F6920_PLUS = (V_88F6920 | V_88F6925 | V_88F6928), + V_88F6925_PLUS = (V_88F6925 | V_88F6928), }; static struct mvebu_mpp_mode armada_39x_mpp_modes[] = { @@ -117,8 +119,8 @@ static struct mvebu_mpp_mode armada_39x_mpp_modes[] = { MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), MPP_VAR_FUNCTION(3, "ua1", "rxd", V_88F6920_PLUS), MPP_VAR_FUNCTION(4, "spi0", "sck", V_88F6920_PLUS), - MPP_VAR_FUNCTION(5, "sata1", "prsnt", V_88F6928), - MPP_VAR_FUNCTION(6, "sata0", "prsnt", V_88F6928), + MPP_VAR_FUNCTION(5, "sata1", "prsnt", V_88F6925_PLUS), + MPP_VAR_FUNCTION(6, "sata0", "prsnt", V_88F6925_PLUS), MPP_VAR_FUNCTION(7, "smi", "mdio", V_88F6920_PLUS)), MPP_MODE(18, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), @@ -127,23 +129,23 @@ static struct mvebu_mpp_mode armada_39x_mpp_modes[] = { MPP_VAR_FUNCTION(7, "i2c2", "sck", V_88F6920_PLUS)), MPP_MODE(19, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), - MPP_VAR_FUNCTION(4, "sata1", "prsnt", V_88F6928), + MPP_VAR_FUNCTION(4, "sata1", "prsnt", V_88F6925_PLUS), MPP_VAR_FUNCTION(5, "ua0", "cts", V_88F6920_PLUS), MPP_VAR_FUNCTION(6, "ua1", "rxd", V_88F6920_PLUS), MPP_VAR_FUNCTION(7, "i2c2", "sda", V_88F6920_PLUS)), MPP_MODE(20, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), - MPP_VAR_FUNCTION(4, "sata0", "prsnt", V_88F6928), + MPP_VAR_FUNCTION(4, "sata0", "prsnt", V_88F6925_PLUS), MPP_VAR_FUNCTION(5, "ua0", "rts", V_88F6920_PLUS), MPP_VAR_FUNCTION(6, "ua1", "txd", V_88F6920_PLUS), MPP_VAR_FUNCTION(7, "smi", "mdc", V_88F6920_PLUS)), MPP_MODE(21, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), MPP_VAR_FUNCTION(1, "spi0", "cs1", V_88F6920_PLUS), - MPP_VAR_FUNCTION(3, "sata0", "prsnt", V_88F6928), + MPP_VAR_FUNCTION(3, "sata0", "prsnt", V_88F6925_PLUS), MPP_VAR_FUNCTION(4, "sd0", "cmd", V_88F6920_PLUS), MPP_VAR_FUNCTION(5, "dev", "bootcs", V_88F6920_PLUS), - MPP_VAR_FUNCTION(6, "sata1", "prsnt", V_88F6928), + MPP_VAR_FUNCTION(6, "sata1", "prsnt", V_88F6925_PLUS), MPP_VAR_FUNCTION(8, "ge", "rxd0", V_88F6920_PLUS)), MPP_MODE(22, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), @@ -263,8 +265,8 @@ static struct mvebu_mpp_mode armada_39x_mpp_modes[] = { MPP_VAR_FUNCTION(6, "nand", "rb1", V_88F6920_PLUS)), MPP_MODE(44, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), - MPP_VAR_FUNCTION(1, "sata0", "prsnt", V_88F6928), - MPP_VAR_FUNCTION(2, "sata1", "prsnt", V_88F6928), + MPP_VAR_FUNCTION(1, "sata0", "prsnt", V_88F6925_PLUS), + MPP_VAR_FUNCTION(2, "sata1", "prsnt", V_88F6925_PLUS), MPP_VAR_FUNCTION(3, "sata2", "prsnt", V_88F6928), MPP_VAR_FUNCTION(4, "sata3", "prsnt", V_88F6928), MPP_VAR_FUNCTION(7, "led", "clk", V_88F6920_PLUS)), @@ -281,14 +283,14 @@ static struct mvebu_mpp_mode armada_39x_mpp_modes[] = { MPP_VAR_FUNCTION(7, "led", "stb", V_88F6920_PLUS)), MPP_MODE(47, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), - MPP_VAR_FUNCTION(1, "sata0", "prsnt", V_88F6928), - MPP_VAR_FUNCTION(2, "sata1", "prsnt", V_88F6928), + MPP_VAR_FUNCTION(1, "sata0", "prsnt", V_88F6925_PLUS), + MPP_VAR_FUNCTION(2, "sata1", "prsnt", V_88F6925_PLUS), MPP_VAR_FUNCTION(3, "sata2", "prsnt", V_88F6928), MPP_VAR_FUNCTION(5, "sata3", "prsnt", V_88F6928), MPP_VAR_FUNCTION(7, "led", "data", V_88F6920_PLUS)), MPP_MODE(48, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), - MPP_VAR_FUNCTION(1, "sata0", "prsnt", V_88F6928), + MPP_VAR_FUNCTION(1, "sata0", "prsnt", V_88F6925_PLUS), MPP_VAR_FUNCTION(2, "dram", "vttctrl", V_88F6920_PLUS), MPP_VAR_FUNCTION(3, "tdm", "pclk", V_88F6928), MPP_VAR_FUNCTION(4, "audio", "mclk", V_88F6928), @@ -325,16 +327,16 @@ static struct mvebu_mpp_mode armada_39x_mpp_modes[] = { MPP_VAR_FUNCTION(7, "i2c3", "sck", V_88F6920_PLUS)), MPP_MODE(53, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), - MPP_VAR_FUNCTION(1, "sata1", "prsnt", V_88F6928), - MPP_VAR_FUNCTION(2, "sata0", "prsnt", V_88F6928), + MPP_VAR_FUNCTION(1, "sata1", "prsnt", V_88F6925_PLUS), + MPP_VAR_FUNCTION(2, "sata0", "prsnt", V_88F6925_PLUS), MPP_VAR_FUNCTION(3, "tdm", "rst", V_88F6928), MPP_VAR_FUNCTION(4, "audio", "bclk", V_88F6928), MPP_VAR_FUNCTION(5, "sd0", "d7", V_88F6920_PLUS), MPP_VAR_FUNCTION(7, "i2c3", "sda", V_88F6920_PLUS)), MPP_MODE(54, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), - MPP_VAR_FUNCTION(1, "sata0", "prsnt", V_88F6928), - MPP_VAR_FUNCTION(2, "sata1", "prsnt", V_88F6928), + MPP_VAR_FUNCTION(1, "sata0", "prsnt", V_88F6925_PLUS), + MPP_VAR_FUNCTION(2, "sata1", "prsnt", V_88F6925_PLUS), MPP_VAR_FUNCTION(3, "pcie0", "rstout", V_88F6920_PLUS), MPP_VAR_FUNCTION(5, "sd0", "d3", V_88F6920_PLUS), MPP_VAR_FUNCTION(7, "ua3", "txd", V_88F6920_PLUS)), @@ -379,6 +381,10 @@ static const struct of_device_id armada_39x_pinctrl_of_match[] = { .data = (void *) V_88F6920, }, { + .compatible = "marvell,mv88f6925-pinctrl", + .data = (void *) V_88F6925, + }, + { .compatible = "marvell,mv88f6928-pinctrl", .data = (void *) V_88F6928, }, -- cgit v0.10.2 From 323de9efdf3e75d1dfb48003a52e59d6d9d4c7a5 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Tue, 9 Jun 2015 13:01:16 +0900 Subject: pinctrl: make pinctrl_register() return proper error code MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Currently, pinctrl_register() just returns NULL on error, so the callers can not know the exact reason of the failure. Some of the pinctrl drivers return -EINVAL, some -ENODEV, and some -ENOMEM on error of pinctrl_register(), although the error code might be different from the real cause of the error. This commit reworks pinctrl_register() to return the appropriate error code and modifies all of the pinctrl drivers to use IS_ERR() for the error checking and PTR_ERR() for getting the error code. Signed-off-by: Masahiro Yamada Acked-by: Patrice Chotard Acked-by: Thierry Reding Acked-by: Heiko Stuebner Tested-by: Mika Westerberg Acked-by: Mika Westerberg Acked-by: Lee Jones Acked-by: Sören Brinkmann Acked-by: Laurent Pinchart Acked-by: Ray Jui Acked-by: Antoine Tenart Acked-by: Hongzhou Yang Acked-by: Wei Chen Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/bcm/pinctrl-bcm281xx.c b/drivers/pinctrl/bcm/pinctrl-bcm281xx.c index 9641f1c..c3c692e 100644 --- a/drivers/pinctrl/bcm/pinctrl-bcm281xx.c +++ b/drivers/pinctrl/bcm/pinctrl-bcm281xx.c @@ -1425,9 +1425,9 @@ static int __init bcm281xx_pinctrl_probe(struct platform_device *pdev) pctl = pinctrl_register(&bcm281xx_pinctrl_desc, &pdev->dev, pdata); - if (!pctl) { + if (IS_ERR(pctl)) { dev_err(&pdev->dev, "Failed to register pinctrl\n"); - return -ENODEV; + return PTR_ERR(pctl); } platform_set_drvdata(pdev, pdata); diff --git a/drivers/pinctrl/bcm/pinctrl-bcm2835.c b/drivers/pinctrl/bcm/pinctrl-bcm2835.c index 8d908e3..efcf2a2 100644 --- a/drivers/pinctrl/bcm/pinctrl-bcm2835.c +++ b/drivers/pinctrl/bcm/pinctrl-bcm2835.c @@ -1036,9 +1036,9 @@ static int bcm2835_pinctrl_probe(struct platform_device *pdev) } pc->pctl_dev = pinctrl_register(&bcm2835_pinctrl_desc, dev, pc); - if (!pc->pctl_dev) { + if (IS_ERR(pc->pctl_dev)) { gpiochip_remove(&pc->gpio_chip); - return -EINVAL; + return PTR_ERR(pc->pctl_dev); } pc->gpio_range = bcm2835_pinctrl_gpio_range; diff --git a/drivers/pinctrl/bcm/pinctrl-cygnus-gpio.c b/drivers/pinctrl/bcm/pinctrl-cygnus-gpio.c index bde45ba..6af538f 100644 --- a/drivers/pinctrl/bcm/pinctrl-cygnus-gpio.c +++ b/drivers/pinctrl/bcm/pinctrl-cygnus-gpio.c @@ -748,9 +748,9 @@ static int cygnus_gpio_register_pinconf(struct cygnus_gpio *chip) pctldesc->confops = &cygnus_pconf_ops; chip->pctl = pinctrl_register(pctldesc, chip->dev, chip); - if (!chip->pctl) { + if (IS_ERR(chip->pctl)) { dev_err(chip->dev, "unable to register pinctrl device\n"); - return -EINVAL; + return PTR_ERR(chip->pctl); } return 0; diff --git a/drivers/pinctrl/bcm/pinctrl-cygnus-mux.c b/drivers/pinctrl/bcm/pinctrl-cygnus-mux.c index f9a9283..9728f3d 100644 --- a/drivers/pinctrl/bcm/pinctrl-cygnus-mux.c +++ b/drivers/pinctrl/bcm/pinctrl-cygnus-mux.c @@ -989,9 +989,9 @@ static int cygnus_pinmux_probe(struct platform_device *pdev) pinctrl->pctl = pinctrl_register(&cygnus_pinctrl_desc, &pdev->dev, pinctrl); - if (!pinctrl->pctl) { + if (IS_ERR(pinctrl->pctl)) { dev_err(&pdev->dev, "unable to register Cygnus IOMUX pinctrl\n"); - return -EINVAL; + return PTR_ERR(pinctrl->pctl); } return 0; diff --git a/drivers/pinctrl/berlin/berlin.c b/drivers/pinctrl/berlin/berlin.c index 7f0b0f9..ddbcd1d 100644 --- a/drivers/pinctrl/berlin/berlin.c +++ b/drivers/pinctrl/berlin/berlin.c @@ -320,9 +320,9 @@ int berlin_pinctrl_probe(struct platform_device *pdev, } pctrl->pctrl_dev = pinctrl_register(&berlin_pctrl_desc, dev, pctrl); - if (!pctrl->pctrl_dev) { + if (IS_ERR(pctrl->pctrl_dev)) { dev_err(dev, "failed to register pinctrl driver\n"); - return -EINVAL; + return PTR_ERR(pctrl->pctrl_dev); } return 0; diff --git a/drivers/pinctrl/core.c b/drivers/pinctrl/core.c index b01ee72..804d126 100644 --- a/drivers/pinctrl/core.c +++ b/drivers/pinctrl/core.c @@ -1706,14 +1706,14 @@ struct pinctrl_dev *pinctrl_register(struct pinctrl_desc *pctldesc, int ret; if (!pctldesc) - return NULL; + return ERR_PTR(-EINVAL); if (!pctldesc->name) - return NULL; + return ERR_PTR(-EINVAL); pctldev = kzalloc(sizeof(*pctldev), GFP_KERNEL); if (pctldev == NULL) { dev_err(dev, "failed to alloc struct pinctrl_dev\n"); - return NULL; + return ERR_PTR(-ENOMEM); } /* Initialize pin control device struct */ @@ -1726,20 +1726,23 @@ struct pinctrl_dev *pinctrl_register(struct pinctrl_desc *pctldesc, mutex_init(&pctldev->mutex); /* check core ops for sanity */ - if (pinctrl_check_ops(pctldev)) { + ret = pinctrl_check_ops(pctldev); + if (ret) { dev_err(dev, "pinctrl ops lacks necessary functions\n"); goto out_err; } /* If we're implementing pinmuxing, check the ops for sanity */ if (pctldesc->pmxops) { - if (pinmux_check_ops(pctldev)) + ret = pinmux_check_ops(pctldev); + if (ret) goto out_err; } /* If we're implementing pinconfig, check the ops for sanity */ if (pctldesc->confops) { - if (pinconf_check_ops(pctldev)) + ret = pinconf_check_ops(pctldev); + if (ret) goto out_err; } @@ -1785,7 +1788,7 @@ struct pinctrl_dev *pinctrl_register(struct pinctrl_desc *pctldesc, out_err: mutex_destroy(&pctldev->mutex); kfree(pctldev); - return NULL; + return ERR_PTR(ret); } EXPORT_SYMBOL_GPL(pinctrl_register); diff --git a/drivers/pinctrl/freescale/pinctrl-imx.c b/drivers/pinctrl/freescale/pinctrl-imx.c index e73e1ed..d7b98ba 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx.c +++ b/drivers/pinctrl/freescale/pinctrl-imx.c @@ -727,9 +727,9 @@ int imx_pinctrl_probe(struct platform_device *pdev, ipctl->dev = info->dev; platform_set_drvdata(pdev, ipctl); ipctl->pctl = pinctrl_register(&imx_pinctrl_desc, &pdev->dev, ipctl); - if (!ipctl->pctl) { + if (IS_ERR(ipctl->pctl)) { dev_err(&pdev->dev, "could not register IMX pinctrl driver\n"); - return -EINVAL; + return PTR_ERR(ipctl->pctl); } dev_info(&pdev->dev, "initialized IMX pinctrl driver\n"); diff --git a/drivers/pinctrl/freescale/pinctrl-imx1-core.c b/drivers/pinctrl/freescale/pinctrl-imx1-core.c index 5ac59fb..5fd4437 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx1-core.c +++ b/drivers/pinctrl/freescale/pinctrl-imx1-core.c @@ -633,9 +633,9 @@ int imx1_pinctrl_core_probe(struct platform_device *pdev, ipctl->dev = info->dev; platform_set_drvdata(pdev, ipctl); ipctl->pctl = pinctrl_register(pctl_desc, &pdev->dev, ipctl); - if (!ipctl->pctl) { + if (IS_ERR(ipctl->pctl)) { dev_err(&pdev->dev, "could not register IMX pinctrl driver\n"); - return -EINVAL; + return PTR_ERR(ipctl->pctl); } ret = of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev); diff --git a/drivers/pinctrl/freescale/pinctrl-mxs.c b/drivers/pinctrl/freescale/pinctrl-mxs.c index 646d5c2..f64eecb 100644 --- a/drivers/pinctrl/freescale/pinctrl-mxs.c +++ b/drivers/pinctrl/freescale/pinctrl-mxs.c @@ -540,9 +540,9 @@ int mxs_pinctrl_probe(struct platform_device *pdev, } d->pctl = pinctrl_register(&mxs_pinctrl_desc, &pdev->dev, d); - if (!d->pctl) { + if (IS_ERR(d->pctl)) { dev_err(&pdev->dev, "Couldn't register MXS pinctrl driver\n"); - ret = -EINVAL; + ret = PTR_ERR(d->pctl); goto err; } diff --git a/drivers/pinctrl/intel/pinctrl-cherryview.c b/drivers/pinctrl/intel/pinctrl-cherryview.c index 82f691e..9bed70b 100644 --- a/drivers/pinctrl/intel/pinctrl-cherryview.c +++ b/drivers/pinctrl/intel/pinctrl-cherryview.c @@ -1489,9 +1489,9 @@ static int chv_pinctrl_probe(struct platform_device *pdev) pctrl->pctldesc.npins = pctrl->community->npins; pctrl->pctldev = pinctrl_register(&pctrl->pctldesc, &pdev->dev, pctrl); - if (!pctrl->pctldev) { + if (IS_ERR(pctrl->pctldev)) { dev_err(&pdev->dev, "failed to register pinctrl driver\n"); - return -ENODEV; + return PTR_ERR(pctrl->pctldev); } ret = chv_gpio_probe(pctrl, irq); diff --git a/drivers/pinctrl/intel/pinctrl-intel.c b/drivers/pinctrl/intel/pinctrl-intel.c index 00768e5..f9ee0d6 100644 --- a/drivers/pinctrl/intel/pinctrl-intel.c +++ b/drivers/pinctrl/intel/pinctrl-intel.c @@ -1021,9 +1021,9 @@ int intel_pinctrl_probe(struct platform_device *pdev, pctrl->pctldesc.npins = pctrl->soc->npins; pctrl->pctldev = pinctrl_register(&pctrl->pctldesc, &pdev->dev, pctrl); - if (!pctrl->pctldev) { + if (IS_ERR(pctrl->pctldev)) { dev_err(&pdev->dev, "failed to register pinctrl driver\n"); - return -ENODEV; + return PTR_ERR(pctrl->pctldev); } ret = intel_gpio_probe(pctrl, irq); diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c index f206a54..35f7b01 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c @@ -1269,9 +1269,9 @@ int mtk_pctrl_init(struct platform_device *pdev, mtk_pctrl_desc.npins = pctl->devdata->npins; pctl->dev = &pdev->dev; pctl->pctl_dev = pinctrl_register(&mtk_pctrl_desc, &pdev->dev, pctl); - if (!pctl->pctl_dev) { + if (IS_ERR(pctl->pctl_dev)) { dev_err(&pdev->dev, "couldn't register pinctrl driver\n"); - return -EINVAL; + return PTR_ERR(pctl->pctl_dev); } pctl->chip = devm_kzalloc(&pdev->dev, sizeof(*pctl->chip), GFP_KERNEL); diff --git a/drivers/pinctrl/meson/pinctrl-meson.c b/drivers/pinctrl/meson/pinctrl-meson.c index edcd140..7b203bf 100644 --- a/drivers/pinctrl/meson/pinctrl-meson.c +++ b/drivers/pinctrl/meson/pinctrl-meson.c @@ -738,9 +738,9 @@ static int meson_pinctrl_probe(struct platform_device *pdev) pc->desc.npins = pc->data->num_pins; pc->pcdev = pinctrl_register(&pc->desc, pc->dev, pc); - if (!pc->pcdev) { + if (IS_ERR(pc->pcdev)) { dev_err(pc->dev, "can't register pinctrl device"); - return -EINVAL; + return PTR_ERR(pc->pcdev); } ret = meson_gpiolib_register(pc); diff --git a/drivers/pinctrl/mvebu/pinctrl-mvebu.c b/drivers/pinctrl/mvebu/pinctrl-mvebu.c index f3b426c..77d2221 100644 --- a/drivers/pinctrl/mvebu/pinctrl-mvebu.c +++ b/drivers/pinctrl/mvebu/pinctrl-mvebu.c @@ -706,9 +706,9 @@ int mvebu_pinctrl_probe(struct platform_device *pdev) } pctl->pctldev = pinctrl_register(&pctl->desc, &pdev->dev, pctl); - if (!pctl->pctldev) { + if (IS_ERR(pctl->pctldev)) { dev_err(&pdev->dev, "unable to register pinctrl driver\n"); - return -EINVAL; + return PTR_ERR(pctl->pctldev); } dev_info(&pdev->dev, "registered pinctrl driver\n"); diff --git a/drivers/pinctrl/nomadik/pinctrl-abx500.c b/drivers/pinctrl/nomadik/pinctrl-abx500.c index 15ccafd..557d0f2 100644 --- a/drivers/pinctrl/nomadik/pinctrl-abx500.c +++ b/drivers/pinctrl/nomadik/pinctrl-abx500.c @@ -1235,10 +1235,10 @@ static int abx500_gpio_probe(struct platform_device *pdev) abx500_pinctrl_desc.pins = pct->soc->pins; abx500_pinctrl_desc.npins = pct->soc->npins; pct->pctldev = pinctrl_register(&abx500_pinctrl_desc, &pdev->dev, pct); - if (!pct->pctldev) { + if (IS_ERR(pct->pctldev)) { dev_err(&pdev->dev, "could not register abx500 pinctrl driver\n"); - ret = -EINVAL; + ret = PTR_ERR(pct->pctldev); goto out_rem_chip; } dev_info(&pdev->dev, "registered pin controller\n"); diff --git a/drivers/pinctrl/nomadik/pinctrl-nomadik.c b/drivers/pinctrl/nomadik/pinctrl-nomadik.c index 2589304..809d884 100644 --- a/drivers/pinctrl/nomadik/pinctrl-nomadik.c +++ b/drivers/pinctrl/nomadik/pinctrl-nomadik.c @@ -2029,9 +2029,9 @@ static int nmk_pinctrl_probe(struct platform_device *pdev) npct->dev = &pdev->dev; npct->pctl = pinctrl_register(&nmk_pinctrl_desc, &pdev->dev, npct); - if (!npct->pctl) { + if (IS_ERR(npct->pctl)) { dev_err(&pdev->dev, "could not register Nomadik pinctrl driver\n"); - return -EINVAL; + return PTR_ERR(npct->pctl); } /* We will handle a range of GPIO pins */ diff --git a/drivers/pinctrl/pinctrl-adi2.c b/drivers/pinctrl/pinctrl-adi2.c index 49df903..873433d 100644 --- a/drivers/pinctrl/pinctrl-adi2.c +++ b/drivers/pinctrl/pinctrl-adi2.c @@ -1070,9 +1070,9 @@ static int adi_pinctrl_probe(struct platform_device *pdev) /* Now register the pin controller and all pins it handles */ pinctrl->pctl = pinctrl_register(&adi_pinmux_desc, &pdev->dev, pinctrl); - if (!pinctrl->pctl) { + if (IS_ERR(pinctrl->pctl)) { dev_err(&pdev->dev, "could not register pinctrl ADI2 driver\n"); - return -EINVAL; + return PTR_ERR(pinctrl->pctl); } platform_set_drvdata(pdev, pinctrl); diff --git a/drivers/pinctrl/pinctrl-amd.c b/drivers/pinctrl/pinctrl-amd.c index e7479125..d8e3f7c 100644 --- a/drivers/pinctrl/pinctrl-amd.c +++ b/drivers/pinctrl/pinctrl-amd.c @@ -789,9 +789,9 @@ static int amd_gpio_probe(struct platform_device *pdev) amd_pinctrl_desc.name = dev_name(&pdev->dev); gpio_dev->pctrl = pinctrl_register(&amd_pinctrl_desc, &pdev->dev, gpio_dev); - if (!gpio_dev->pctrl) { + if (IS_ERR(gpio_dev->pctrl)) { dev_err(&pdev->dev, "Couldn't register pinctrl driver\n"); - return -ENODEV; + return PTR_ERR(gpio_dev->pctrl); } ret = gpiochip_add(&gpio_dev->gc); diff --git a/drivers/pinctrl/pinctrl-as3722.c b/drivers/pinctrl/pinctrl-as3722.c index db0571f..4747e08 100644 --- a/drivers/pinctrl/pinctrl-as3722.c +++ b/drivers/pinctrl/pinctrl-as3722.c @@ -586,9 +586,9 @@ static int as3722_pinctrl_probe(struct platform_device *pdev) as3722_pinctrl_desc.npins = ARRAY_SIZE(as3722_pins_desc); as_pci->pctl = pinctrl_register(&as3722_pinctrl_desc, &pdev->dev, as_pci); - if (!as_pci->pctl) { + if (IS_ERR(as_pci->pctl)) { dev_err(&pdev->dev, "Couldn't register pinctrl driver\n"); - return -EINVAL; + return PTR_ERR(as_pci->pctl); } as_pci->gpio_chip = as3722_gpio_chip; diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c index d80ade2..a082447 100644 --- a/drivers/pinctrl/pinctrl-at91.c +++ b/drivers/pinctrl/pinctrl-at91.c @@ -1238,9 +1238,9 @@ static int at91_pinctrl_probe(struct platform_device *pdev) platform_set_drvdata(pdev, info); info->pctl = pinctrl_register(&at91_pinctrl_desc, &pdev->dev, info); - if (!info->pctl) { + if (IS_ERR(info->pctl)) { dev_err(&pdev->dev, "could not register AT91 pinctrl driver\n"); - return -EINVAL; + return PTR_ERR(info->pctl); } /* We will handle a range of GPIO pins */ diff --git a/drivers/pinctrl/pinctrl-lantiq.c b/drivers/pinctrl/pinctrl-lantiq.c index 296e5b3..fc38a85 100644 --- a/drivers/pinctrl/pinctrl-lantiq.c +++ b/drivers/pinctrl/pinctrl-lantiq.c @@ -337,9 +337,9 @@ int ltq_pinctrl_register(struct platform_device *pdev, info->dev = &pdev->dev; info->pctrl = pinctrl_register(desc, &pdev->dev, info); - if (!info->pctrl) { + if (IS_ERR(info->pctrl)) { dev_err(&pdev->dev, "failed to register LTQ pinmux driver\n"); - return -EINVAL; + return PTR_ERR(info->pctrl); } platform_set_drvdata(pdev, info); return 0; diff --git a/drivers/pinctrl/pinctrl-lpc18xx.c b/drivers/pinctrl/pinctrl-lpc18xx.c index a8bc1ad..ef0b697 100644 --- a/drivers/pinctrl/pinctrl-lpc18xx.c +++ b/drivers/pinctrl/pinctrl-lpc18xx.c @@ -1180,10 +1180,10 @@ static int lpc18xx_scu_probe(struct platform_device *pdev) platform_set_drvdata(pdev, scu); scu->pctl = pinctrl_register(&lpc18xx_scu_desc, &pdev->dev, scu); - if (!scu->pctl) { + if (IS_ERR(scu->pctl)) { dev_err(&pdev->dev, "Could not register pinctrl driver\n"); clk_disable_unprepare(scu->clk); - return -EINVAL; + return PTR_ERR(scu->pctl); } return 0; diff --git a/drivers/pinctrl/pinctrl-palmas.c b/drivers/pinctrl/pinctrl-palmas.c index 2631df0..f7e1680 100644 --- a/drivers/pinctrl/pinctrl-palmas.c +++ b/drivers/pinctrl/pinctrl-palmas.c @@ -1044,9 +1044,9 @@ static int palmas_pinctrl_probe(struct platform_device *pdev) palmas_pinctrl_desc.pins = palmas_pins_desc; palmas_pinctrl_desc.npins = ARRAY_SIZE(palmas_pins_desc); pci->pctl = pinctrl_register(&palmas_pinctrl_desc, &pdev->dev, pci); - if (!pci->pctl) { + if (IS_ERR(pci->pctl)) { dev_err(&pdev->dev, "Couldn't register pinctrl driver\n"); - return -ENODEV; + return PTR_ERR(pci->pctl); } return 0; } diff --git a/drivers/pinctrl/pinctrl-pistachio.c b/drivers/pinctrl/pinctrl-pistachio.c index 079ce8b..63100be 100644 --- a/drivers/pinctrl/pinctrl-pistachio.c +++ b/drivers/pinctrl/pinctrl-pistachio.c @@ -1474,9 +1474,9 @@ static int pistachio_pinctrl_probe(struct platform_device *pdev) pctl->pctldev = pinctrl_register(&pistachio_pinctrl_desc, &pdev->dev, pctl); - if (!pctl->pctldev) { + if (IS_ERR(pctl->pctldev)) { dev_err(&pdev->dev, "Failed to register pinctrl device\n"); - return -EINVAL; + return PTR_ERR(pctl->pctldev); } ret = pistachio_gpio_register(pctl); diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c index dee7d5f..6e7643f 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -1274,9 +1274,9 @@ static int rockchip_pinctrl_register(struct platform_device *pdev, return ret; info->pctl_dev = pinctrl_register(ctrldesc, &pdev->dev, info); - if (!info->pctl_dev) { + if (IS_ERR(info->pctl_dev)) { dev_err(&pdev->dev, "could not register pinctrl driver\n"); - return -EINVAL; + return PTR_ERR(info->pctl_dev); } for (bank = 0; bank < info->ctrl->nr_banks; ++bank) { diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c index 968e352..b2de09d 100644 --- a/drivers/pinctrl/pinctrl-single.c +++ b/drivers/pinctrl/pinctrl-single.c @@ -1921,9 +1921,9 @@ static int pcs_probe(struct platform_device *pdev) goto free; pcs->pctl = pinctrl_register(&pcs->desc, pcs->dev, pcs); - if (!pcs->pctl) { + if (IS_ERR(pcs->pctl)) { dev_err(pcs->dev, "could not register single pinctrl driver\n"); - ret = -EINVAL; + ret = PTR_ERR(pcs->pctl); goto free; } diff --git a/drivers/pinctrl/pinctrl-st.c b/drivers/pinctrl/pinctrl-st.c index 65bf73b..d34ac87 100644 --- a/drivers/pinctrl/pinctrl-st.c +++ b/drivers/pinctrl/pinctrl-st.c @@ -1737,9 +1737,9 @@ static int st_pctl_probe(struct platform_device *pdev) pctl_desc->name = dev_name(&pdev->dev); info->pctl = pinctrl_register(pctl_desc, &pdev->dev, info); - if (!info->pctl) { + if (IS_ERR(info->pctl)) { dev_err(&pdev->dev, "Failed pinctrl registration\n"); - return -EINVAL; + return PTR_ERR(info->pctl); } for (i = 0; i < info->nbanks; i++) diff --git a/drivers/pinctrl/pinctrl-tb10x.c b/drivers/pinctrl/pinctrl-tb10x.c index 160a1f5..6546b9b 100644 --- a/drivers/pinctrl/pinctrl-tb10x.c +++ b/drivers/pinctrl/pinctrl-tb10x.c @@ -807,9 +807,9 @@ static int tb10x_pinctrl_probe(struct platform_device *pdev) } state->pctl = pinctrl_register(&tb10x_pindesc, dev, state); - if (!state->pctl) { + if (IS_ERR(state->pctl)) { dev_err(dev, "could not register TB10x pin driver\n"); - ret = -EINVAL; + ret = PTR_ERR(state->pctl); goto fail; } diff --git a/drivers/pinctrl/pinctrl-tegra-xusb.c b/drivers/pinctrl/pinctrl-tegra-xusb.c index 6a6eebf..2651d04 100644 --- a/drivers/pinctrl/pinctrl-tegra-xusb.c +++ b/drivers/pinctrl/pinctrl-tegra-xusb.c @@ -922,9 +922,9 @@ static int tegra_xusb_padctl_probe(struct platform_device *pdev) padctl->desc.owner = THIS_MODULE; padctl->pinctrl = pinctrl_register(&padctl->desc, &pdev->dev, padctl); - if (!padctl->pinctrl) { + if (IS_ERR(padctl->pinctrl)) { dev_err(&pdev->dev, "failed to register pincontrol\n"); - err = -ENODEV; + err = PTR_ERR(padctl->pinctrl); goto reset; } diff --git a/drivers/pinctrl/pinctrl-tegra.c b/drivers/pinctrl/pinctrl-tegra.c index 4c95c20..0f982b8 100644 --- a/drivers/pinctrl/pinctrl-tegra.c +++ b/drivers/pinctrl/pinctrl-tegra.c @@ -703,9 +703,9 @@ int tegra_pinctrl_probe(struct platform_device *pdev, } pmx->pctl = pinctrl_register(&tegra_pinctrl_desc, &pdev->dev, pmx); - if (!pmx->pctl) { + if (IS_ERR(pmx->pctl)) { dev_err(&pdev->dev, "Couldn't register pinctrl driver\n"); - return -ENODEV; + return PTR_ERR(pmx->pctl); } pinctrl_add_gpio_range(pmx->pctl, &tegra_pinctrl_gpio_range); diff --git a/drivers/pinctrl/pinctrl-tz1090-pdc.c b/drivers/pinctrl/pinctrl-tz1090-pdc.c index 8a8911b..c349911 100644 --- a/drivers/pinctrl/pinctrl-tz1090-pdc.c +++ b/drivers/pinctrl/pinctrl-tz1090-pdc.c @@ -948,9 +948,9 @@ static int tz1090_pdc_pinctrl_probe(struct platform_device *pdev) return PTR_ERR(pmx->regs); pmx->pctl = pinctrl_register(&tz1090_pdc_pinctrl_desc, &pdev->dev, pmx); - if (!pmx->pctl) { + if (IS_ERR(pmx->pctl)) { dev_err(&pdev->dev, "Couldn't register pinctrl driver\n"); - return -ENODEV; + return PTR_ERR(pmx->pctl); } platform_set_drvdata(pdev, pmx); diff --git a/drivers/pinctrl/pinctrl-tz1090.c b/drivers/pinctrl/pinctrl-tz1090.c index fc5594a5..6d07a2f 100644 --- a/drivers/pinctrl/pinctrl-tz1090.c +++ b/drivers/pinctrl/pinctrl-tz1090.c @@ -1963,9 +1963,9 @@ static int tz1090_pinctrl_probe(struct platform_device *pdev) return PTR_ERR(pmx->regs); pmx->pctl = pinctrl_register(&tz1090_pinctrl_desc, &pdev->dev, pmx); - if (!pmx->pctl) { + if (IS_ERR(pmx->pctl)) { dev_err(&pdev->dev, "Couldn't register pinctrl driver\n"); - return -ENODEV; + return PTR_ERR(pmx->pctl); } platform_set_drvdata(pdev, pmx); diff --git a/drivers/pinctrl/pinctrl-u300.c b/drivers/pinctrl/pinctrl-u300.c index f931e65..c076021 100644 --- a/drivers/pinctrl/pinctrl-u300.c +++ b/drivers/pinctrl/pinctrl-u300.c @@ -1068,9 +1068,9 @@ static int u300_pmx_probe(struct platform_device *pdev) return PTR_ERR(upmx->virtbase); upmx->pctl = pinctrl_register(&u300_pmx_desc, &pdev->dev, upmx); - if (!upmx->pctl) { + if (IS_ERR(upmx->pctl)) { dev_err(&pdev->dev, "could not register U300 pinmux driver\n"); - return -EINVAL; + return PTR_ERR(upmx->pctl); } platform_set_drvdata(pdev, upmx); diff --git a/drivers/pinctrl/pinctrl-zynq.c b/drivers/pinctrl/pinctrl-zynq.c index 40b2aff..7ce23b6 100644 --- a/drivers/pinctrl/pinctrl-zynq.c +++ b/drivers/pinctrl/pinctrl-zynq.c @@ -1196,8 +1196,8 @@ static int zynq_pinctrl_probe(struct platform_device *pdev) pctrl->nfuncs = ARRAY_SIZE(zynq_pmux_functions); pctrl->pctrl = pinctrl_register(&zynq_desc, &pdev->dev, pctrl); - if (!pctrl->pctrl) - return -ENOMEM; + if (IS_ERR(pctrl->pctrl)) + return PTR_ERR(pctrl->pctrl); platform_set_drvdata(pdev, pctrl); diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c index f3d800f..e457d52 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm.c +++ b/drivers/pinctrl/qcom/pinctrl-msm.c @@ -906,9 +906,9 @@ int msm_pinctrl_probe(struct platform_device *pdev, msm_pinctrl_desc.pins = pctrl->soc->pins; msm_pinctrl_desc.npins = pctrl->soc->npins; pctrl->pctrl = pinctrl_register(&msm_pinctrl_desc, &pdev->dev, pctrl); - if (!pctrl->pctrl) { + if (IS_ERR(pctrl->pctrl)) { dev_err(&pdev->dev, "Couldn't register pinctrl driver\n"); - return -ENODEV; + return PTR_ERR(pctrl->pctrl); } ret = msm_gpio_init(pctrl); diff --git a/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c b/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c index b2d2221..f92f229 100644 --- a/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c +++ b/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c @@ -776,8 +776,8 @@ static int pmic_gpio_probe(struct platform_device *pdev) state->chip.can_sleep = false; state->ctrl = pinctrl_register(pctrldesc, dev, state); - if (!state->ctrl) - return -ENODEV; + if (IS_ERR(state->ctrl)) + return PTR_ERR(state->ctrl); ret = gpiochip_add(&state->chip); if (ret) { diff --git a/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c b/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c index 8f36c5f..cd7ca11 100644 --- a/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c +++ b/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c @@ -890,8 +890,8 @@ static int pmic_mpp_probe(struct platform_device *pdev) state->chip.can_sleep = false; state->ctrl = pinctrl_register(pctrldesc, dev, state); - if (!state->ctrl) - return -ENODEV; + if (IS_ERR(state->ctrl)) + return PTR_ERR(state->ctrl); ret = gpiochip_add(&state->chip); if (ret) { diff --git a/drivers/pinctrl/samsung/pinctrl-exynos5440.c b/drivers/pinctrl/samsung/pinctrl-exynos5440.c index 86192be..f5619fb 100644 --- a/drivers/pinctrl/samsung/pinctrl-exynos5440.c +++ b/drivers/pinctrl/samsung/pinctrl-exynos5440.c @@ -822,9 +822,9 @@ static int exynos5440_pinctrl_register(struct platform_device *pdev, return ret; pctl_dev = pinctrl_register(ctrldesc, &pdev->dev, priv); - if (!pctl_dev) { + if (IS_ERR(pctl_dev)) { dev_err(&pdev->dev, "could not register pinctrl driver\n"); - return -EINVAL; + return PTR_ERR(pctl_dev); } grange.name = "exynos5440-pctrl-gpio-range"; diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.c b/drivers/pinctrl/samsung/pinctrl-samsung.c index 0fd20c5..3dd5a3b 100644 --- a/drivers/pinctrl/samsung/pinctrl-samsung.c +++ b/drivers/pinctrl/samsung/pinctrl-samsung.c @@ -873,9 +873,9 @@ static int samsung_pinctrl_register(struct platform_device *pdev, return ret; drvdata->pctl_dev = pinctrl_register(ctrldesc, &pdev->dev, drvdata); - if (!drvdata->pctl_dev) { + if (IS_ERR(drvdata->pctl_dev)) { dev_err(&pdev->dev, "could not register pinctrl driver\n"); - return -EINVAL; + return PTR_ERR(drvdata->pctl_dev); } for (bank = 0; bank < drvdata->nr_banks; ++bank) { diff --git a/drivers/pinctrl/sh-pfc/pinctrl.c b/drivers/pinctrl/sh-pfc/pinctrl.c index 072e7c6..ff67896 100644 --- a/drivers/pinctrl/sh-pfc/pinctrl.c +++ b/drivers/pinctrl/sh-pfc/pinctrl.c @@ -625,8 +625,8 @@ int sh_pfc_register_pinctrl(struct sh_pfc *pfc) pmx->pctl_desc.npins = pfc->info->nr_pins; pmx->pctl = pinctrl_register(&pmx->pctl_desc, pfc->dev, pmx); - if (pmx->pctl == NULL) - return -EINVAL; + if (IS_ERR(pmx->pctl)) + return PTR_ERR(pmx->pctl); return 0; } diff --git a/drivers/pinctrl/sirf/pinctrl-atlas7.c b/drivers/pinctrl/sirf/pinctrl-atlas7.c index c2ced3f..9384e0a 100644 --- a/drivers/pinctrl/sirf/pinctrl-atlas7.c +++ b/drivers/pinctrl/sirf/pinctrl-atlas7.c @@ -4079,9 +4079,9 @@ static int atlas7_pinmux_probe(struct platform_device *pdev) /* Now register the pin controller and all pins it handles */ pmx->pctl = pinctrl_register(&pmx->pctl_desc, &pdev->dev, pmx); - if (!pmx->pctl) { + if (IS_ERR(pmx->pctl)) { dev_err(&pdev->dev, "could not register atlas7 pinmux driver\n"); - ret = -EINVAL; + ret = PTR_ERR(pmx->pctl); goto unmap_io; } diff --git a/drivers/pinctrl/sirf/pinctrl-sirf.c b/drivers/pinctrl/sirf/pinctrl-sirf.c index e2efbba..8ba26e4 100644 --- a/drivers/pinctrl/sirf/pinctrl-sirf.c +++ b/drivers/pinctrl/sirf/pinctrl-sirf.c @@ -310,9 +310,9 @@ static int sirfsoc_pinmux_probe(struct platform_device *pdev) /* Now register the pin controller and all pins it handles */ spmx->pmx = pinctrl_register(&sirfsoc_pinmux_desc, &pdev->dev, spmx); - if (!spmx->pmx) { + if (IS_ERR(spmx->pmx)) { dev_err(&pdev->dev, "could not register SIRFSOC pinmux driver\n"); - ret = -EINVAL; + ret = PTR_ERR(spmx->pmx); goto out_no_pmx; } diff --git a/drivers/pinctrl/spear/pinctrl-spear.c b/drivers/pinctrl/spear/pinctrl-spear.c index abdb05a..f87a5ea 100644 --- a/drivers/pinctrl/spear/pinctrl-spear.c +++ b/drivers/pinctrl/spear/pinctrl-spear.c @@ -396,9 +396,9 @@ int spear_pinctrl_probe(struct platform_device *pdev, spear_pinctrl_desc.npins = machdata->npins; pmx->pctl = pinctrl_register(&spear_pinctrl_desc, &pdev->dev, pmx); - if (!pmx->pctl) { + if (IS_ERR(pmx->pctl)) { dev_err(&pdev->dev, "Couldn't register pinctrl driver\n"); - return -ENODEV; + return PTR_ERR(pmx->pctl); } return 0; diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c index f8e171b..d7857c7 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c @@ -911,9 +911,9 @@ int sunxi_pinctrl_init(struct platform_device *pdev, pctl->pctl_dev = pinctrl_register(pctrl_desc, &pdev->dev, pctl); - if (!pctl->pctl_dev) { + if (IS_ERR(pctl->pctl_dev)) { dev_err(&pdev->dev, "couldn't register pinctrl driver\n"); - return -EINVAL; + return PTR_ERR(pctl->pctl_dev); } pctl->chip = devm_kzalloc(&pdev->dev, sizeof(*pctl->chip), GFP_KERNEL); diff --git a/drivers/pinctrl/vt8500/pinctrl-wmt.c b/drivers/pinctrl/vt8500/pinctrl-wmt.c index d055d63..c15316b 100644 --- a/drivers/pinctrl/vt8500/pinctrl-wmt.c +++ b/drivers/pinctrl/vt8500/pinctrl-wmt.c @@ -594,9 +594,9 @@ int wmt_pinctrl_probe(struct platform_device *pdev, data->dev = &pdev->dev; data->pctl_dev = pinctrl_register(&wmt_desc, &pdev->dev, data); - if (!data->pctl_dev) { + if (IS_ERR(data->pctl_dev)) { dev_err(&pdev->dev, "Failed to register pinctrl\n"); - return -EINVAL; + return PTR_ERR(data->pctl_dev); } err = gpiochip_add(&data->gpio_chip); -- cgit v0.10.2 From 43c4436e2f1890a7b28dc0f0d901866cda99a08c Mon Sep 17 00:00:00 2001 From: Hisashi Nakamura Date: Sat, 6 Jun 2015 01:34:48 +0300 Subject: pinctrl: sh-pfc: add R8A7794 PFC support Add PFC support for the R8A7794 SoC including pin groups for some on-chip devices such as ETH, I2C, INTC, MSIOF, QSPI, [H]SCIF... Sergei: squashed together several patches, fixed the MLB_CLK typo, added IRQ4.. IRQ9 pin groups, fixed IRQn comments, added ETH B pin group names, removed stray new line and fixed typos in the comments in the pinmux_config_regs[] initializer, removed the platform device ID, took into account limited number of signals in the GPIO1/5/6 controllers, added reasonable and removed unreasonable copyrights, modified the bindings document, renamed, added changelog. Changes in version 5: - resolved rejects, refreshed the patch; - added Laurent Pinchart's ACK. Changes in version 4: - reused the PORT_GP_26() macro to #define PORT_GP_28(). Changes in version 3: - removed the platform device ID; - added PORT_GP_26() and PORT_GP_28() macros, used them for GPIO1/5/6 in the CPU_ALL_PORT() macro. Changes in version 2: - rebased the patch. Signed-off-by: Hisashi Nakamura Signed-off-by: Sergei Shtylyov Acked-by: Laurent Pinchart Signed-off-by: Linus Walleij diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt index 6bcf851..51cee44 100644 --- a/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt @@ -18,6 +18,7 @@ Required Properties: - "renesas,pfc-r8a7790": for R8A7790 (R-Car H2) compatible pin-controller. - "renesas,pfc-r8a7791": for R8A7791 (R-Car M2-W) compatible pin-controller. - "renesas,pfc-r8a7793": for R8A7793 (R-Car M2-N) compatible pin-controller. + - "renesas,pfc-r8a7794": for R8A7794 (R-Car E2) compatible pin-controller. - "renesas,pfc-sh73a0": for SH73A0 (SH-Mobile AG5) compatible pin-controller. - reg: Base address and length of each memory resource used by the pin diff --git a/drivers/pinctrl/sh-pfc/Kconfig b/drivers/pinctrl/sh-pfc/Kconfig index 5d570fd..8e024c9 100644 --- a/drivers/pinctrl/sh-pfc/Kconfig +++ b/drivers/pinctrl/sh-pfc/Kconfig @@ -60,6 +60,11 @@ config PINCTRL_PFC_R8A7793 depends on ARCH_R8A7793 select PINCTRL_SH_PFC +config PINCTRL_PFC_R8A7794 + def_bool y + depends on ARCH_R8A7794 + select PINCTRL_SH_PFC + config PINCTRL_PFC_SH7203 def_bool y depends on CPU_SUBTYPE_SH7203 diff --git a/drivers/pinctrl/sh-pfc/Makefile b/drivers/pinctrl/sh-pfc/Makefile index 11eefcb..ea2a60e 100644 --- a/drivers/pinctrl/sh-pfc/Makefile +++ b/drivers/pinctrl/sh-pfc/Makefile @@ -11,6 +11,7 @@ obj-$(CONFIG_PINCTRL_PFC_R8A7779) += pfc-r8a7779.o obj-$(CONFIG_PINCTRL_PFC_R8A7790) += pfc-r8a7790.o obj-$(CONFIG_PINCTRL_PFC_R8A7791) += pfc-r8a7791.o obj-$(CONFIG_PINCTRL_PFC_R8A7793) += pfc-r8a7791.o +obj-$(CONFIG_PINCTRL_PFC_R8A7794) += pfc-r8a7794.o obj-$(CONFIG_PINCTRL_PFC_SH7203) += pfc-sh7203.o obj-$(CONFIG_PINCTRL_PFC_SH7264) += pfc-sh7264.o obj-$(CONFIG_PINCTRL_PFC_SH7269) += pfc-sh7269.o diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c index 9655636..865d235 100644 --- a/drivers/pinctrl/sh-pfc/core.c +++ b/drivers/pinctrl/sh-pfc/core.c @@ -487,6 +487,12 @@ static const struct of_device_id sh_pfc_of_table[] = { .data = &r8a7793_pinmux_info, }, #endif +#ifdef CONFIG_PINCTRL_PFC_R8A7794 + { + .compatible = "renesas,pfc-r8a7794", + .data = &r8a7794_pinmux_info, + }, +#endif #ifdef CONFIG_PINCTRL_PFC_SH73A0 { .compatible = "renesas,pfc-sh73a0", diff --git a/drivers/pinctrl/sh-pfc/core.h b/drivers/pinctrl/sh-pfc/core.h index b151b77..4c3c37b 100644 --- a/drivers/pinctrl/sh-pfc/core.h +++ b/drivers/pinctrl/sh-pfc/core.h @@ -72,6 +72,7 @@ extern const struct sh_pfc_soc_info r8a7779_pinmux_info; extern const struct sh_pfc_soc_info r8a7790_pinmux_info; extern const struct sh_pfc_soc_info r8a7791_pinmux_info; extern const struct sh_pfc_soc_info r8a7793_pinmux_info; +extern const struct sh_pfc_soc_info r8a7794_pinmux_info; extern const struct sh_pfc_soc_info sh7203_pinmux_info; extern const struct sh_pfc_soc_info sh7264_pinmux_info; extern const struct sh_pfc_soc_info sh7269_pinmux_info; diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7794.c b/drivers/pinctrl/sh-pfc/pfc-r8a7794.c new file mode 100644 index 0000000..0e2686a --- /dev/null +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7794.c @@ -0,0 +1,4008 @@ +/* + * r8a7794 processor support - PFC hardware block. + * + * Copyright (C) 2014 Renesas Electronics Corporation + * Copyright (C) 2015 Renesas Solutions Corp. + * Copyright (C) 2015 Cogent Embedded, Inc., + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 + * as published by the Free Software Foundation. + */ + +#include +#include + +#include "core.h" +#include "sh_pfc.h" + +#define PORT_GP_26(bank, fn, sfx) \ + PORT_GP_1(bank, 0, fn, sfx), PORT_GP_1(bank, 1, fn, sfx), \ + PORT_GP_1(bank, 2, fn, sfx), PORT_GP_1(bank, 3, fn, sfx), \ + PORT_GP_1(bank, 4, fn, sfx), PORT_GP_1(bank, 5, fn, sfx), \ + PORT_GP_1(bank, 6, fn, sfx), PORT_GP_1(bank, 7, fn, sfx), \ + PORT_GP_1(bank, 8, fn, sfx), PORT_GP_1(bank, 9, fn, sfx), \ + PORT_GP_1(bank, 10, fn, sfx), PORT_GP_1(bank, 11, fn, sfx), \ + PORT_GP_1(bank, 12, fn, sfx), PORT_GP_1(bank, 13, fn, sfx), \ + PORT_GP_1(bank, 14, fn, sfx), PORT_GP_1(bank, 15, fn, sfx), \ + PORT_GP_1(bank, 16, fn, sfx), PORT_GP_1(bank, 17, fn, sfx), \ + PORT_GP_1(bank, 18, fn, sfx), PORT_GP_1(bank, 19, fn, sfx), \ + PORT_GP_1(bank, 20, fn, sfx), PORT_GP_1(bank, 21, fn, sfx), \ + PORT_GP_1(bank, 22, fn, sfx), PORT_GP_1(bank, 23, fn, sfx), \ + PORT_GP_1(bank, 24, fn, sfx), PORT_GP_1(bank, 25, fn, sfx) + +#define PORT_GP_28(bank, fn, sfx) \ + PORT_GP_26(bank, fn, sfx), \ + PORT_GP_1(bank, 26, fn, sfx), PORT_GP_1(bank, 27, fn, sfx) + +#define CPU_ALL_PORT(fn, sfx) \ + PORT_GP_32(0, fn, sfx), \ + PORT_GP_26(1, fn, sfx), \ + PORT_GP_32(2, fn, sfx), \ + PORT_GP_32(3, fn, sfx), \ + PORT_GP_32(4, fn, sfx), \ + PORT_GP_28(5, fn, sfx), \ + PORT_GP_26(6, fn, sfx) + +enum { + PINMUX_RESERVED = 0, + + PINMUX_DATA_BEGIN, + GP_ALL(DATA), + PINMUX_DATA_END, + + PINMUX_FUNCTION_BEGIN, + GP_ALL(FN), + + /* GPSR0 */ + FN_IP0_23_22, FN_IP0_24, FN_IP0_25, FN_IP0_27_26, FN_IP0_29_28, + FN_IP0_31_30, FN_IP1_1_0, FN_IP1_3_2, FN_IP1_5_4, FN_IP1_7_6, + FN_IP1_10_8, FN_IP1_12_11, FN_IP1_14_13, FN_IP1_17_15, FN_IP1_19_18, + FN_IP1_21_20, FN_IP1_23_22, FN_IP1_24, FN_A2, FN_IP1_26, FN_IP1_27, + FN_IP1_29_28, FN_IP1_31_30, FN_IP2_1_0, FN_IP2_3_2, FN_IP2_5_4, + FN_IP2_7_6, FN_IP2_9_8, FN_IP2_11_10, FN_IP2_13_12, FN_IP2_15_14, + FN_IP2_17_16, + + /* GPSR1 */ + FN_IP2_20_18, FN_IP2_23_21, FN_IP2_26_24, FN_IP2_29_27, FN_IP2_31_30, + FN_IP3_1_0, FN_IP3_3_2, FN_IP3_5_4, FN_IP3_7_6, FN_IP3_9_8, FN_IP3_10, + FN_IP3_11, FN_IP3_12, FN_IP3_14_13, FN_IP3_17_15, FN_IP3_20_18, + FN_IP3_23_21, FN_IP3_26_24, FN_IP3_29_27, FN_IP3_30, FN_IP3_31, + FN_WE0_N, FN_WE1_N, FN_IP4_1_0 , FN_IP7_31, FN_DACK0, + + /* GPSR2 */ + FN_IP4_4_2, FN_IP4_7_5, FN_IP4_9_8, FN_IP4_11_10, FN_IP4_13_12, + FN_IP4_15_14, FN_IP4_17_16, FN_IP4_19_18, FN_IP4_22_20, FN_IP4_25_23, + FN_IP4_27_26, FN_IP4_29_28, FN_IP4_31_30, FN_IP5_1_0, FN_IP5_3_2, + FN_IP5_5_4, FN_IP5_8_6, FN_IP5_11_9, FN_IP5_13_12, FN_IP5_15_14, + FN_IP5_17_16, FN_IP5_19_18, FN_IP5_21_20, FN_IP5_23_22, FN_IP5_25_24, + FN_IP5_27_26, FN_IP5_29_28, FN_IP5_31_30, FN_IP6_1_0, FN_IP6_3_2, + FN_IP6_5_4, FN_IP6_7_6, + + /* GPSR3 */ + FN_IP6_8, FN_IP6_9, FN_IP6_10, FN_IP6_11, FN_IP6_12, FN_IP6_13, + FN_IP6_14, FN_IP6_15, FN_IP6_16, FN_IP6_19_17, FN_IP6_22_20, + FN_IP6_25_23, FN_IP6_28_26, FN_IP6_31_29, FN_IP7_2_0, FN_IP7_5_3, + FN_IP7_8_6, FN_IP7_11_9, FN_IP7_14_12, FN_IP7_17_15, FN_IP7_20_18, + FN_IP7_23_21, FN_IP7_26_24, FN_IP7_29_27, FN_IP8_2_0, FN_IP8_5_3, + FN_IP8_8_6, FN_IP8_11_9, FN_IP8_14_12, FN_IP8_16_15, FN_IP8_19_17, + FN_IP8_22_20, + + /* GPSR4 */ + FN_IP8_25_23, FN_IP8_28_26, FN_IP8_31_29, FN_IP9_2_0, FN_IP9_5_3, + FN_IP9_8_6, FN_IP9_11_9, FN_IP9_14_12, FN_IP9_16_15, FN_IP9_18_17, + FN_IP9_21_19, FN_IP9_24_22, FN_IP9_27_25, FN_IP9_30_28, FN_IP10_2_0, + FN_IP10_5_3, FN_IP10_8_6, FN_IP10_11_9, FN_IP10_14_12, FN_IP10_17_15, + FN_IP10_20_18, FN_IP10_23_21, FN_IP10_26_24, FN_IP10_29_27, + FN_IP10_31_30, FN_IP11_2_0, FN_IP11_5_3, FN_IP11_7_6, FN_IP11_10_8, + FN_IP11_13_11, FN_IP11_15_14, FN_IP11_17_16, + + /* GPSR5 */ + FN_IP11_20_18, FN_IP11_23_21, FN_IP11_26_24, FN_IP11_29_27, FN_IP12_2_0, + FN_IP12_5_3, FN_IP12_8_6, FN_IP12_10_9, FN_IP12_12_11, FN_IP12_14_13, + FN_IP12_17_15, FN_IP12_20_18, FN_IP12_23_21, FN_IP12_26_24, + FN_IP12_29_27, FN_IP13_2_0, FN_IP13_5_3, FN_IP13_8_6, FN_IP13_11_9, + FN_IP13_14_12, FN_IP13_17_15, FN_IP13_20_18, FN_IP13_23_21, + FN_IP13_26_24, FN_USB0_PWEN, FN_USB0_OVC, FN_USB1_PWEN, FN_USB1_OVC, + + /* GPSR6 */ + FN_SD0_CLK, FN_SD0_CMD, FN_SD0_DATA0, FN_SD0_DATA1, FN_SD0_DATA2, + FN_SD0_DATA3, FN_SD0_CD, FN_SD0_WP, FN_SD1_CLK, FN_SD1_CMD, + FN_SD1_DATA0, FN_SD1_DATA1, FN_SD1_DATA2, FN_SD1_DATA3, FN_IP0_0, + FN_IP0_9_8, FN_IP0_10, FN_IP0_11, FN_IP0_12, FN_IP0_13, FN_IP0_14, + FN_IP0_15, FN_IP0_16, FN_IP0_17, FN_IP0_19_18, FN_IP0_21_20, + + /* IPSR0 */ + FN_SD1_CD, FN_CAN0_RX, FN_SD1_WP, FN_IRQ7, FN_CAN0_TX, FN_MMC_CLK, + FN_SD2_CLK, FN_MMC_CMD, FN_SD2_CMD, FN_MMC_D0, FN_SD2_DATA0, FN_MMC_D1, + FN_SD2_DATA1, FN_MMC_D2, FN_SD2_DATA2, FN_MMC_D3, FN_SD2_DATA3, + FN_MMC_D4, FN_SD2_CD, FN_MMC_D5, FN_SD2_WP, FN_MMC_D6, FN_SCIF0_RXD, + FN_I2C2_SCL_B, FN_CAN1_RX, FN_MMC_D7, FN_SCIF0_TXD, FN_I2C2_SDA_B, + FN_CAN1_TX, FN_D0, FN_SCIFA3_SCK_B, FN_IRQ4, FN_D1, FN_SCIFA3_RXD_B, + FN_D2, FN_SCIFA3_TXD_B, FN_D3, FN_I2C3_SCL_B, FN_SCIF5_RXD_B, FN_D4, + FN_I2C3_SDA_B, FN_SCIF5_TXD_B, FN_D5, FN_SCIF4_RXD_B, FN_I2C0_SCL_D, + + /* IPSR1 */ + FN_D6, FN_SCIF4_TXD_B, FN_I2C0_SDA_D, FN_D7, FN_IRQ3, FN_TCLK1, + FN_PWM6_B, FN_D8, FN_HSCIF2_HRX, FN_I2C1_SCL_B, FN_D9, FN_HSCIF2_HTX, + FN_I2C1_SDA_B, FN_D10, FN_HSCIF2_HSCK, FN_SCIF1_SCK_C, FN_IRQ6, + FN_PWM5_C, FN_D11, FN_HSCIF2_HCTS_N, FN_SCIF1_RXD_C, FN_I2C1_SCL_D, + FN_D12, FN_HSCIF2_HRTS_N, FN_SCIF1_TXD_C, FN_I2C1_SDA_D, FN_D13, + FN_SCIFA1_SCK, FN_TANS1, FN_PWM2_C, FN_TCLK2_B, FN_D14, FN_SCIFA1_RXD, + FN_IIC0_SCL_B, FN_D15, FN_SCIFA1_TXD, FN_IIC0_SDA_B, FN_A0, + FN_SCIFB1_SCK, FN_PWM3_B, FN_A1, FN_SCIFB1_TXD, FN_A3, FN_SCIFB0_SCK, + FN_A4, FN_SCIFB0_TXD, FN_A5, FN_SCIFB0_RXD, FN_PWM4_B, FN_TPUTO3_C, + FN_A6, FN_SCIFB0_CTS_N, FN_SCIFA4_RXD_B, FN_TPUTO2_C, + + /* IPSR2 */ + FN_A7, FN_SCIFB0_RTS_N, FN_SCIFA4_TXD_B, FN_A8, FN_MSIOF1_RXD, + FN_SCIFA0_RXD_B, FN_A9, FN_MSIOF1_TXD, FN_SCIFA0_TXD_B, FN_A10, + FN_MSIOF1_SCK, FN_IIC1_SCL_B, FN_A11, FN_MSIOF1_SYNC, FN_IIC1_SDA_B, + FN_A12, FN_MSIOF1_SS1, FN_SCIFA5_RXD_B, FN_A13, FN_MSIOF1_SS2, + FN_SCIFA5_TXD_B, FN_A14, FN_MSIOF2_RXD, FN_HSCIF0_HRX_B, FN_DREQ1_N, + FN_A15, FN_MSIOF2_TXD, FN_HSCIF0_HTX_B, FN_DACK1, FN_A16, + FN_MSIOF2_SCK, FN_HSCIF0_HSCK_B, FN_SPEEDIN, FN_VSP, FN_CAN_CLK_C, + FN_TPUTO2_B, FN_A17, FN_MSIOF2_SYNC, FN_SCIF4_RXD_E, FN_CAN1_RX_B, + FN_AVB_AVTP_CAPTURE_B, FN_A18, FN_MSIOF2_SS1, FN_SCIF4_TXD_E, + FN_CAN1_TX_B, FN_AVB_AVTP_MATCH_B, FN_A19, FN_MSIOF2_SS2, FN_PWM4, + FN_TPUTO2, FN_MOUT0, FN_A20, FN_SPCLK, FN_MOUT1, + + /* IPSR3 */ + FN_A21, FN_MOSI_IO0, FN_MOUT2, FN_A22, FN_MISO_IO1, FN_MOUT5, + FN_ATADIR1_N, FN_A23, FN_IO2, FN_MOUT6, FN_ATAWR1_N, FN_A24, FN_IO3, + FN_EX_WAIT2, FN_A25, FN_SSL, FN_ATARD1_N, FN_CS0_N, FN_VI1_DATA8, + FN_CS1_N_A26, FN_VI1_DATA9, FN_EX_CS0_N, FN_VI1_DATA10, FN_EX_CS1_N, + FN_TPUTO3_B, FN_SCIFB2_RXD, FN_VI1_DATA11, FN_EX_CS2_N, FN_PWM0, + FN_SCIF4_RXD_C, FN_TS_SDATA_B, FN_RIF0_SYNC, FN_TPUTO3, FN_SCIFB2_TXD, + FN_SDATA_B, FN_EX_CS3_N, FN_SCIFA2_SCK, FN_SCIF4_TXD_C, FN_TS_SCK_B, + FN_RIF0_CLK, FN_BPFCLK, FN_SCIFB2_SCK, FN_MDATA_B, FN_EX_CS4_N, + FN_SCIFA2_RXD, FN_I2C2_SCL_E, FN_TS_SDEN_B, FN_RIF0_D0, FN_FMCLK, + FN_SCIFB2_CTS_N, FN_SCKZ_B, FN_EX_CS5_N, FN_SCIFA2_TXD, FN_I2C2_SDA_E, + FN_TS_SPSYNC_B, FN_RIF0_D1, FN_FMIN, FN_SCIFB2_RTS_N, FN_STM_N_B, + FN_BS_N, FN_DRACK0, FN_PWM1_C, FN_TPUTO0_C, FN_ATACS01_N, FN_MTS_N_B, + FN_RD_N, FN_ATACS11_N, FN_RD_WR_N, FN_ATAG1_N, + + /* IPSR4 */ + FN_EX_WAIT0, FN_CAN_CLK_B, FN_SCIF_CLK, FN_PWMFSW0, FN_DU0_DR0, + FN_LCDOUT16, FN_SCIF5_RXD_C, FN_I2C2_SCL_D, FN_CC50_STATE0, + FN_DU0_DR1, FN_LCDOUT17, FN_SCIF5_TXD_C, FN_I2C2_SDA_D, FN_CC50_STATE1, + FN_DU0_DR2, FN_LCDOUT18, FN_CC50_STATE2, FN_DU0_DR3, FN_LCDOUT19, + FN_CC50_STATE3, FN_DU0_DR4, FN_LCDOUT20, FN_CC50_STATE4, FN_DU0_DR5, + FN_LCDOUT21, FN_CC50_STATE5, FN_DU0_DR6, FN_LCDOUT22, FN_CC50_STATE6, + FN_DU0_DR7, FN_LCDOUT23, FN_CC50_STATE7, FN_DU0_DG0, FN_LCDOUT8, + FN_SCIFA0_RXD_C, FN_I2C3_SCL_D, FN_CC50_STATE8, FN_DU0_DG1, FN_LCDOUT9, + FN_SCIFA0_TXD_C, FN_I2C3_SDA_D, FN_CC50_STATE9, FN_DU0_DG2, FN_LCDOUT10, + FN_CC50_STATE10, FN_DU0_DG3, FN_LCDOUT11, FN_CC50_STATE11, FN_DU0_DG4, + FN_LCDOUT12, FN_CC50_STATE12, + + /* IPSR5 */ + FN_DU0_DG5, FN_LCDOUT13, FN_CC50_STATE13, FN_DU0_DG6, FN_LCDOUT14, + FN_CC50_STATE14, FN_DU0_DG7, FN_LCDOUT15, FN_CC50_STATE15, FN_DU0_DB0, + FN_LCDOUT0, FN_SCIFA4_RXD_C, FN_I2C4_SCL_D, FN_CAN0_RX_C, + FN_CC50_STATE16, FN_DU0_DB1, FN_LCDOUT1, FN_SCIFA4_TXD_C, FN_I2C4_SDA_D, + FN_CAN0_TX_C, FN_CC50_STATE17, FN_DU0_DB2, FN_LCDOUT2, FN_CC50_STATE18, + FN_DU0_DB3, FN_LCDOUT3, FN_CC50_STATE19, FN_DU0_DB4, FN_LCDOUT4, + FN_CC50_STATE20, FN_DU0_DB5, FN_LCDOUT5, FN_CC50_STATE21, FN_DU0_DB6, + FN_LCDOUT6, FN_CC50_STATE22, FN_DU0_DB7, FN_LCDOUT7, FN_CC50_STATE23, + FN_DU0_DOTCLKIN, FN_QSTVA_QVS, FN_CC50_STATE24, FN_DU0_DOTCLKOUT0, + FN_QCLK, FN_CC50_STATE25, FN_DU0_DOTCLKOUT1, FN_QSTVB_QVE, + FN_CC50_STATE26, FN_DU0_EXHSYNC_DU0_HSYNC, FN_QSTH_QHS, FN_CC50_STATE27, + + /* IPSR6 */ + FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE, FN_CC50_STATE28, + FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE, FN_CC50_STATE29, + FN_DU0_DISP, FN_QPOLA, FN_CC50_STATE30, FN_DU0_CDE, FN_QPOLB, + FN_CC50_STATE31, FN_VI0_CLK, FN_AVB_RX_CLK, FN_VI0_DATA0_VI0_B0, + FN_AVB_RX_DV, FN_VI0_DATA1_VI0_B1, FN_AVB_RXD0, FN_VI0_DATA2_VI0_B2, + FN_AVB_RXD1, FN_VI0_DATA3_VI0_B3, FN_AVB_RXD2, FN_VI0_DATA4_VI0_B4, + FN_AVB_RXD3, FN_VI0_DATA5_VI0_B5, FN_AVB_RXD4, FN_VI0_DATA6_VI0_B6, + FN_AVB_RXD5, FN_VI0_DATA7_VI0_B7, FN_AVB_RXD6, FN_VI0_CLKENB, + FN_I2C3_SCL, FN_SCIFA5_RXD_C, FN_IETX_C, FN_AVB_RXD7, FN_VI0_FIELD, + FN_I2C3_SDA, FN_SCIFA5_TXD_C, FN_IECLK_C, FN_AVB_RX_ER, FN_VI0_HSYNC_N, + FN_SCIF0_RXD_B, FN_I2C0_SCL_C, FN_IERX_C, FN_AVB_COL, FN_VI0_VSYNC_N, + FN_SCIF0_TXD_B, FN_I2C0_SDA_C, FN_AUDIO_CLKOUT_B, FN_AVB_TX_EN, + FN_ETH_MDIO, FN_VI0_G0, FN_MSIOF2_RXD_B, FN_IIC0_SCL_D, FN_AVB_TX_CLK, + FN_ADIDATA, FN_AD_DI, + + /* IPSR7 */ + FN_ETH_CRS_DV, FN_VI0_G1, FN_MSIOF2_TXD_B, FN_IIC0_SDA_D, FN_AVB_TXD0, + FN_ADICS_SAMP, FN_AD_DO, FN_ETH_RX_ER, FN_VI0_G2, FN_MSIOF2_SCK_B, + FN_CAN0_RX_B, FN_AVB_TXD1, FN_ADICLK, FN_AD_CLK, FN_ETH_RXD0, FN_VI0_G3, + FN_MSIOF2_SYNC_B, FN_CAN0_TX_B, FN_AVB_TXD2, FN_ADICHS0, FN_AD_NCS_N, + FN_ETH_RXD1, FN_VI0_G4, FN_MSIOF2_SS1_B, FN_SCIF4_RXD_D, FN_AVB_TXD3, + FN_ADICHS1, FN_ETH_LINK, FN_VI0_G5, FN_MSIOF2_SS2_B, FN_SCIF4_TXD_D, + FN_AVB_TXD4, FN_ADICHS2, FN_ETH_REFCLK, FN_VI0_G6, FN_SCIF2_SCK_C, + FN_AVB_TXD5, FN_SSI_SCK5_B, FN_ETH_TXD1, FN_VI0_G7, FN_SCIF2_RXD_C, + FN_IIC1_SCL_D, FN_AVB_TXD6, FN_SSI_WS5_B, FN_ETH_TX_EN, FN_VI0_R0, + FN_SCIF2_TXD_C, FN_IIC1_SDA_D, FN_AVB_TXD7, FN_SSI_SDATA5_B, + FN_ETH_MAGIC, FN_VI0_R1, FN_SCIF3_SCK_B, FN_AVB_TX_ER, FN_SSI_SCK6_B, + FN_ETH_TXD0, FN_VI0_R2, FN_SCIF3_RXD_B, FN_I2C4_SCL_E, FN_AVB_GTX_CLK, + FN_SSI_WS6_B, FN_DREQ0_N, FN_SCIFB1_RXD, + + /* IPSR8 */ + FN_ETH_MDC, FN_VI0_R3, FN_SCIF3_TXD_B, FN_I2C4_SDA_E, FN_AVB_MDC, + FN_SSI_SDATA6_B, FN_HSCIF0_HRX, FN_VI0_R4, FN_I2C1_SCL_C, + FN_AUDIO_CLKA_B, FN_AVB_MDIO, FN_SSI_SCK78_B, FN_HSCIF0_HTX, + FN_VI0_R5, FN_I2C1_SDA_C, FN_AUDIO_CLKB_B, FN_AVB_LINK, FN_SSI_WS78_B, + FN_HSCIF0_HCTS_N, FN_VI0_R6, FN_SCIF0_RXD_D, FN_I2C0_SCL_E, + FN_AVB_MAGIC, FN_SSI_SDATA7_B, FN_HSCIF0_HRTS_N, FN_VI0_R7, + FN_SCIF0_TXD_D, FN_I2C0_SDA_E, FN_AVB_PHY_INT, FN_SSI_SDATA8_B, + FN_HSCIF0_HSCK, FN_SCIF_CLK_B, FN_AVB_CRS, FN_AUDIO_CLKC_B, + FN_I2C0_SCL, FN_SCIF0_RXD_C, FN_PWM5, FN_TCLK1_B, FN_AVB_GTXREFCLK, + FN_CAN1_RX_D, FN_TPUTO0_B, FN_I2C0_SDA, FN_SCIF0_TXD_C, FN_TPUTO0, + FN_CAN_CLK, FN_DVC_MUTE, FN_CAN1_TX_D, FN_I2C1_SCL, FN_SCIF4_RXD, + FN_PWM5_B, FN_DU1_DR0, FN_RIF1_SYNC_B, FN_TS_SDATA_D, FN_TPUTO1_B, + FN_I2C1_SDA, FN_SCIF4_TXD, FN_IRQ5, FN_DU1_DR1, FN_RIF1_CLK_B, + FN_TS_SCK_D, FN_BPFCLK_C, FN_MSIOF0_RXD, FN_SCIF5_RXD, FN_I2C2_SCL_C, + FN_DU1_DR2, FN_RIF1_D0_B, FN_TS_SDEN_D, FN_FMCLK_C, FN_RDS_CLK, + + /* IPSR9 */ + FN_MSIOF0_TXD, FN_SCIF5_TXD, FN_I2C2_SDA_C, FN_DU1_DR3, FN_RIF1_D1_B, + FN_TS_SPSYNC_D, FN_FMIN_C, FN_RDS_DATA, FN_MSIOF0_SCK, FN_IRQ0, + FN_TS_SDATA, FN_DU1_DR4, FN_RIF1_SYNC, FN_TPUTO1_C, FN_MSIOF0_SYNC, + FN_PWM1, FN_TS_SCK, FN_DU1_DR5, FN_RIF1_CLK, FN_BPFCLK_B, FN_MSIOF0_SS1, + FN_SCIFA0_RXD, FN_TS_SDEN, FN_DU1_DR6, FN_RIF1_D0, FN_FMCLK_B, + FN_RDS_CLK_B, FN_MSIOF0_SS2, FN_SCIFA0_TXD, FN_TS_SPSYNC, FN_DU1_DR7, + FN_RIF1_D1, FN_FMIN_B, FN_RDS_DATA_B, FN_HSCIF1_HRX, FN_I2C4_SCL, + FN_PWM6, FN_DU1_DG0, FN_HSCIF1_HTX, FN_I2C4_SDA, FN_TPUTO1, FN_DU1_DG1, + FN_HSCIF1_HSCK, FN_PWM2, FN_IETX, FN_DU1_DG2, FN_REMOCON_B, + FN_SPEEDIN_B, FN_VSP_B, FN_HSCIF1_HCTS_N, FN_SCIFA4_RXD, FN_IECLK, + FN_DU1_DG3, FN_SSI_SCK1_B, FN_CAN_DEBUG_HW_TRIGGER, FN_CC50_STATE32, + FN_HSCIF1_HRTS_N, FN_SCIFA4_TXD, FN_IERX, FN_DU1_DG4, FN_SSI_WS1_B, + FN_CAN_STEP0, FN_CC50_STATE33, FN_SCIF1_SCK, FN_PWM3, FN_TCLK2, + FN_DU1_DG5, FN_SSI_SDATA1_B, FN_CAN_TXCLK, FN_CC50_STATE34, + + /* IPSR10 */ + FN_SCIF1_RXD, FN_IIC0_SCL, FN_DU1_DG6, FN_SSI_SCK2_B, FN_CAN_DEBUGOUT0, + FN_CC50_STATE35, FN_SCIF1_TXD, FN_IIC0_SDA, FN_DU1_DG7, FN_SSI_WS2_B, + FN_CAN_DEBUGOUT1, FN_CC50_STATE36, FN_SCIF2_RXD, FN_IIC1_SCL, + FN_DU1_DB0, FN_SSI_SDATA2_B, FN_USB0_EXTLP, FN_CAN_DEBUGOUT2, + FN_CC50_STATE37, FN_SCIF2_TXD, FN_IIC1_SDA, FN_DU1_DB1, FN_SSI_SCK9_B, + FN_USB0_OVC1, FN_CAN_DEBUGOUT3, FN_CC50_STATE38, FN_SCIF2_SCK, FN_IRQ1, + FN_DU1_DB2, FN_SSI_WS9_B, FN_USB0_IDIN, FN_CAN_DEBUGOUT4, + FN_CC50_STATE39, FN_SCIF3_SCK, FN_IRQ2, FN_BPFCLK_D, FN_DU1_DB3, + FN_SSI_SDATA9_B, FN_TANS2, FN_CAN_DEBUGOUT5, FN_CC50_OSCOUT, + FN_SCIF3_RXD, FN_I2C1_SCL_E, FN_FMCLK_D, FN_DU1_DB4, FN_AUDIO_CLKA_C, + FN_SSI_SCK4_B, FN_CAN_DEBUGOUT6, FN_RDS_CLK_C, FN_SCIF3_TXD, + FN_I2C1_SDA_E, FN_FMIN_D, FN_DU1_DB5, FN_AUDIO_CLKB_C, FN_SSI_WS4_B, + FN_CAN_DEBUGOUT7, FN_RDS_DATA_C, FN_I2C2_SCL, FN_SCIFA5_RXD, FN_DU1_DB6, + FN_AUDIO_CLKC_C, FN_SSI_SDATA4_B, FN_CAN_DEBUGOUT8, FN_I2C2_SDA, + FN_SCIFA5_TXD, FN_DU1_DB7, FN_AUDIO_CLKOUT_C, FN_CAN_DEBUGOUT9, + FN_SSI_SCK5, FN_SCIFA3_SCK, FN_DU1_DOTCLKIN, FN_CAN_DEBUGOUT10, + + /* IPSR11 */ + FN_SSI_WS5, FN_SCIFA3_RXD, FN_I2C3_SCL_C, FN_DU1_DOTCLKOUT0, + FN_CAN_DEBUGOUT11, FN_SSI_SDATA5, FN_SCIFA3_TXD, FN_I2C3_SDA_C, + FN_DU1_DOTCLKOUT1, FN_CAN_DEBUGOUT12, FN_SSI_SCK6, FN_SCIFA1_SCK_B, + FN_DU1_EXHSYNC_DU1_HSYNC, FN_CAN_DEBUGOUT13, FN_SSI_WS6, + FN_SCIFA1_RXD_B, FN_I2C4_SCL_C, FN_DU1_EXVSYNC_DU1_VSYNC, + FN_CAN_DEBUGOUT14, FN_SSI_SDATA6, FN_SCIFA1_TXD_B, FN_I2C4_SDA_C, + FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_CAN_DEBUGOUT15, FN_SSI_SCK78, + FN_SCIFA2_SCK_B, FN_IIC0_SDA_C, FN_DU1_DISP, FN_SSI_WS78, + FN_SCIFA2_RXD_B, FN_IIC0_SCL_C, FN_DU1_CDE, FN_SSI_SDATA7, + FN_SCIFA2_TXD_B, FN_IRQ8, FN_AUDIO_CLKA_D, FN_CAN_CLK_D, FN_PCMOE_N, + FN_SSI_SCK0129, FN_MSIOF1_RXD_B, FN_SCIF5_RXD_D, FN_ADIDATA_B, + FN_AD_DI_B, FN_PCMWE_N, FN_SSI_WS0129, FN_MSIOF1_TXD_B, FN_SCIF5_TXD_D, + FN_ADICS_SAMP_B, FN_AD_DO_B, FN_SSI_SDATA0, FN_MSIOF1_SCK_B, FN_PWM0_B, + FN_ADICLK_B, FN_AD_CLK_B, + + /* IPSR12 */ + FN_SSI_SCK34, FN_MSIOF1_SYNC_B, FN_SCIFA1_SCK_C, FN_ADICHS0_B, + FN_AD_NCS_N_B, FN_DREQ1_N_B, FN_SSI_WS34, FN_MSIOF1_SS1_B, + FN_SCIFA1_RXD_C, FN_ADICHS1_B, FN_CAN1_RX_C, FN_DACK1_B, FN_SSI_SDATA3, + FN_MSIOF1_SS2_B, FN_SCIFA1_TXD_C, FN_ADICHS2_B, FN_CAN1_TX_C, + FN_DREQ2_N, FN_SSI_SCK4, FN_MLB_CLK, FN_IETX_B, FN_IRD_TX, FN_SSI_WS4, + FN_MLB_SIG, FN_IECLK_B, FN_IRD_RX, FN_SSI_SDATA4, FN_MLB_DAT, + FN_IERX_B, FN_IRD_SCK, FN_SSI_SDATA8, FN_SCIF1_SCK_B, + FN_PWM1_B, FN_IRQ9, FN_REMOCON, FN_DACK2, FN_ETH_MDIO_B, FN_SSI_SCK1, + FN_SCIF1_RXD_B, FN_IIC1_SCL_C, FN_VI1_CLK, FN_CAN0_RX_D, + FN_AVB_AVTP_CAPTURE, FN_ETH_CRS_DV_B, FN_SSI_WS1, FN_SCIF1_TXD_B, + FN_IIC1_SDA_C, FN_VI1_DATA0, FN_CAN0_TX_D, FN_AVB_AVTP_MATCH, + FN_ETH_RX_ER_B, FN_SSI_SDATA1, FN_HSCIF1_HRX_B, FN_SDATA, FN_VI1_DATA1, + FN_ATAG0_N, FN_ETH_RXD0_B, FN_SSI_SCK2, FN_HSCIF1_HTX_B, FN_VI1_DATA2, + FN_MDATA, FN_ATAWR0_N, FN_ETH_RXD1_B, + + /* IPSR13 */ + FN_SSI_WS2, FN_HSCIF1_HCTS_N_B, FN_SCIFA0_RXD_D, FN_VI1_DATA3, FN_SCKZ, + FN_ATACS00_N, FN_ETH_LINK_B, FN_SSI_SDATA2, FN_HSCIF1_HRTS_N_B, + FN_SCIFA0_TXD_D, FN_VI1_DATA4, FN_STM_N, FN_ATACS10_N, FN_ETH_REFCLK_B, + FN_SSI_SCK9, FN_SCIF2_SCK_B, FN_PWM2_B, FN_VI1_DATA5, FN_MTS_N, + FN_EX_WAIT1, FN_ETH_TXD1_B, FN_SSI_WS9, FN_SCIF2_RXD_B, FN_I2C3_SCL_E, + FN_VI1_DATA6, FN_ATARD0_N, FN_ETH_TX_EN_B, FN_SSI_SDATA9, + FN_SCIF2_TXD_B, FN_I2C3_SDA_E, FN_VI1_DATA7, FN_ATADIR0_N, + FN_ETH_MAGIC_B, FN_AUDIO_CLKA, FN_I2C0_SCL_B, FN_SCIFA4_RXD_D, + FN_VI1_CLKENB, FN_TS_SDATA_C, FN_RIF0_SYNC_B, FN_ETH_TXD0_B, + FN_AUDIO_CLKB, FN_I2C0_SDA_B, FN_SCIFA4_TXD_D, FN_VI1_FIELD, + FN_TS_SCK_C, FN_RIF0_CLK_B, FN_BPFCLK_E, FN_ETH_MDC_B, FN_AUDIO_CLKC, + FN_I2C4_SCL_B, FN_SCIFA5_RXD_D, FN_VI1_HSYNC_N, FN_TS_SDEN_C, + FN_RIF0_D0_B, FN_FMCLK_E, FN_RDS_CLK_D, FN_AUDIO_CLKOUT, FN_I2C4_SDA_B, + FN_SCIFA5_TXD_D, FN_VI1_VSYNC_N, FN_TS_SPSYNC_C, FN_RIF0_D1_B, + FN_FMIN_E, FN_RDS_DATA_D, + + /* MOD_SEL */ + FN_SEL_ADG_0, FN_SEL_ADG_1, FN_SEL_ADG_2, FN_SEL_ADG_3, + FN_SEL_ADI_0, FN_SEL_ADI_1, FN_SEL_CAN_0, FN_SEL_CAN_1, + FN_SEL_CAN_2, FN_SEL_CAN_3, FN_SEL_DARC_0, FN_SEL_DARC_1, + FN_SEL_DARC_2, FN_SEL_DARC_3, FN_SEL_DARC_4, FN_SEL_DR0_0, + FN_SEL_DR0_1, FN_SEL_DR1_0, FN_SEL_DR1_1, FN_SEL_DR2_0, FN_SEL_DR2_1, + FN_SEL_DR3_0, FN_SEL_DR3_1, FN_SEL_ETH_0, FN_SEL_ETH_1, FN_SEL_FSN_0, + FN_SEL_FSN_1, FN_SEL_I2C00_0, FN_SEL_I2C00_1, FN_SEL_I2C00_2, + FN_SEL_I2C00_3, FN_SEL_I2C00_4, FN_SEL_I2C01_0, FN_SEL_I2C01_1, + FN_SEL_I2C01_2, FN_SEL_I2C01_3, FN_SEL_I2C01_4, FN_SEL_I2C02_0, + FN_SEL_I2C02_1, FN_SEL_I2C02_2, FN_SEL_I2C02_3, FN_SEL_I2C02_4, + FN_SEL_I2C03_0, FN_SEL_I2C03_1, FN_SEL_I2C03_2, FN_SEL_I2C03_3, + FN_SEL_I2C03_4, FN_SEL_I2C04_0, FN_SEL_I2C04_1, FN_SEL_I2C04_2, + FN_SEL_I2C04_3, FN_SEL_I2C04_4, FN_SEL_IIC00_0, FN_SEL_IIC00_1, + FN_SEL_IIC00_2, FN_SEL_IIC00_3, FN_SEL_AVB_0, FN_SEL_AVB_1, + + /* MOD_SEL2 */ + FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, FN_SEL_IIC01_0, + FN_SEL_IIC01_1, FN_SEL_IIC01_2, FN_SEL_IIC01_3, FN_SEL_LBS_0, + FN_SEL_LBS_1, FN_SEL_MSI1_0, FN_SEL_MSI1_1, FN_SEL_MSI2_0, + FN_SEL_MSI2_1, FN_SEL_RAD_0, FN_SEL_RAD_1, FN_SEL_RCN_0, + FN_SEL_RCN_1, FN_SEL_RSP_0, FN_SEL_RSP_1, FN_SEL_SCIFA0_0, + FN_SEL_SCIFA0_1, FN_SEL_SCIFA0_2, FN_SEL_SCIFA0_3, FN_SEL_SCIFA1_0, + FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, + FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1, FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, + FN_SEL_SCIFA4_2, FN_SEL_SCIFA4_3, FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, + FN_SEL_SCIFA5_2, FN_SEL_SCIFA5_3, FN_SEL_SPDM_0, FN_SEL_SPDM_1, + FN_SEL_TMU_0, FN_SEL_TMU_1, FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, + FN_SEL_TSIF0_2, FN_SEL_TSIF0_3, FN_SEL_CAN0_0, FN_SEL_CAN0_1, + FN_SEL_CAN0_2, FN_SEL_CAN0_3, FN_SEL_CAN1_0, FN_SEL_CAN1_1, + FN_SEL_CAN1_2, FN_SEL_CAN1_3, FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, + FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_RDS_0, FN_SEL_RDS_1, + FN_SEL_RDS_2, FN_SEL_RDS_3, + + /* MOD_SEL3 */ + FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3, + FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF2_0, + FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, + FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, FN_SEL_SCIF4_3, + FN_SEL_SCIF4_4, FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, FN_SEL_SCIF5_2, + FN_SEL_SCIF5_3, FN_SEL_SSI1_0, FN_SEL_SSI1_1, FN_SEL_SSI2_0, + FN_SEL_SSI2_1, FN_SEL_SSI4_0, FN_SEL_SSI4_1, FN_SEL_SSI5_0, + FN_SEL_SSI5_1, FN_SEL_SSI6_0, FN_SEL_SSI6_1, FN_SEL_SSI7_0, + FN_SEL_SSI7_1, FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI9_0, + FN_SEL_SSI9_1, + PINMUX_FUNCTION_END, + + PINMUX_MARK_BEGIN, + A2_MARK, WE0_N_MARK, WE1_N_MARK, DACK0_MARK, + + USB0_PWEN_MARK, USB0_OVC_MARK, USB1_PWEN_MARK, USB1_OVC_MARK, + + SD0_CLK_MARK, SD0_CMD_MARK, SD0_DATA0_MARK, SD0_DATA1_MARK, + SD0_DATA2_MARK, SD0_DATA3_MARK, SD0_CD_MARK, SD0_WP_MARK, + + SD1_CLK_MARK, SD1_CMD_MARK, SD1_DATA0_MARK, SD1_DATA1_MARK, + SD1_DATA2_MARK, SD1_DATA3_MARK, + + /* IPSR0 */ + SD1_CD_MARK, CAN0_RX_MARK, SD1_WP_MARK, IRQ7_MARK, CAN0_TX_MARK, + MMC_CLK_MARK, SD2_CLK_MARK, MMC_CMD_MARK, SD2_CMD_MARK, MMC_D0_MARK, + SD2_DATA0_MARK, MMC_D1_MARK, SD2_DATA1_MARK, MMC_D2_MARK, + SD2_DATA2_MARK, MMC_D3_MARK, SD2_DATA3_MARK, MMC_D4_MARK, SD2_CD_MARK, + MMC_D5_MARK, SD2_WP_MARK, MMC_D6_MARK, SCIF0_RXD_MARK, I2C2_SCL_B_MARK, + CAN1_RX_MARK, MMC_D7_MARK, SCIF0_TXD_MARK, I2C2_SDA_B_MARK, + CAN1_TX_MARK, D0_MARK, SCIFA3_SCK_B_MARK, IRQ4_MARK, D1_MARK, + SCIFA3_RXD_B_MARK, D2_MARK, SCIFA3_TXD_B_MARK, D3_MARK, I2C3_SCL_B_MARK, + SCIF5_RXD_B_MARK, D4_MARK, I2C3_SDA_B_MARK, SCIF5_TXD_B_MARK, D5_MARK, + SCIF4_RXD_B_MARK, I2C0_SCL_D_MARK, + + /* IPSR1 */ + D6_MARK, SCIF4_TXD_B_MARK, I2C0_SDA_D_MARK, D7_MARK, IRQ3_MARK, + TCLK1_MARK, PWM6_B_MARK, D8_MARK, HSCIF2_HRX_MARK, I2C1_SCL_B_MARK, + D9_MARK, HSCIF2_HTX_MARK, I2C1_SDA_B_MARK, D10_MARK, + HSCIF2_HSCK_MARK, SCIF1_SCK_C_MARK, IRQ6_MARK, PWM5_C_MARK, + D11_MARK, HSCIF2_HCTS_N_MARK, SCIF1_RXD_C_MARK, I2C1_SCL_D_MARK, + D12_MARK, HSCIF2_HRTS_N_MARK, SCIF1_TXD_C_MARK, I2C1_SDA_D_MARK, + D13_MARK, SCIFA1_SCK_MARK, TANS1_MARK, PWM2_C_MARK, TCLK2_B_MARK, + D14_MARK, SCIFA1_RXD_MARK, IIC0_SCL_B_MARK, D15_MARK, SCIFA1_TXD_MARK, + IIC0_SDA_B_MARK, A0_MARK, SCIFB1_SCK_MARK, PWM3_B_MARK, A1_MARK, + SCIFB1_TXD_MARK, A3_MARK, SCIFB0_SCK_MARK, A4_MARK, SCIFB0_TXD_MARK, + A5_MARK, SCIFB0_RXD_MARK, PWM4_B_MARK, TPUTO3_C_MARK, A6_MARK, + SCIFB0_CTS_N_MARK, SCIFA4_RXD_B_MARK, TPUTO2_C_MARK, + + /* IPSR2 */ + A7_MARK, SCIFB0_RTS_N_MARK, SCIFA4_TXD_B_MARK, A8_MARK, MSIOF1_RXD_MARK, + SCIFA0_RXD_B_MARK, A9_MARK, MSIOF1_TXD_MARK, SCIFA0_TXD_B_MARK, + A10_MARK, MSIOF1_SCK_MARK, IIC1_SCL_B_MARK, A11_MARK, MSIOF1_SYNC_MARK, + IIC1_SDA_B_MARK, A12_MARK, MSIOF1_SS1_MARK, SCIFA5_RXD_B_MARK, + A13_MARK, MSIOF1_SS2_MARK, SCIFA5_TXD_B_MARK, A14_MARK, MSIOF2_RXD_MARK, + HSCIF0_HRX_B_MARK, DREQ1_N_MARK, A15_MARK, MSIOF2_TXD_MARK, + HSCIF0_HTX_B_MARK, DACK1_MARK, A16_MARK, MSIOF2_SCK_MARK, + HSCIF0_HSCK_B_MARK, SPEEDIN_MARK, VSP_MARK, CAN_CLK_C_MARK, + TPUTO2_B_MARK, A17_MARK, MSIOF2_SYNC_MARK, SCIF4_RXD_E_MARK, + CAN1_RX_B_MARK, AVB_AVTP_CAPTURE_B_MARK, A18_MARK, MSIOF2_SS1_MARK, + SCIF4_TXD_E_MARK, CAN1_TX_B_MARK, AVB_AVTP_MATCH_B_MARK, A19_MARK, + MSIOF2_SS2_MARK, PWM4_MARK, TPUTO2_MARK, MOUT0_MARK, A20_MARK, + SPCLK_MARK, MOUT1_MARK, + + /* IPSR3 */ + A21_MARK, MOSI_IO0_MARK, MOUT2_MARK, A22_MARK, MISO_IO1_MARK, + MOUT5_MARK, ATADIR1_N_MARK, A23_MARK, IO2_MARK, MOUT6_MARK, + ATAWR1_N_MARK, A24_MARK, IO3_MARK, EX_WAIT2_MARK, A25_MARK, SSL_MARK, + ATARD1_N_MARK, CS0_N_MARK, VI1_DATA8_MARK, CS1_N_A26_MARK, + VI1_DATA9_MARK, EX_CS0_N_MARK, VI1_DATA10_MARK, EX_CS1_N_MARK, + TPUTO3_B_MARK, SCIFB2_RXD_MARK, VI1_DATA11_MARK, EX_CS2_N_MARK, + PWM0_MARK, SCIF4_RXD_C_MARK, TS_SDATA_B_MARK, RIF0_SYNC_MARK, + TPUTO3_MARK, SCIFB2_TXD_MARK, SDATA_B_MARK, EX_CS3_N_MARK, + SCIFA2_SCK_MARK, SCIF4_TXD_C_MARK, TS_SCK_B_MARK, RIF0_CLK_MARK, + BPFCLK_MARK, SCIFB2_SCK_MARK, MDATA_B_MARK, EX_CS4_N_MARK, + SCIFA2_RXD_MARK, I2C2_SCL_E_MARK, TS_SDEN_B_MARK, RIF0_D0_MARK, + FMCLK_MARK, SCIFB2_CTS_N_MARK, SCKZ_B_MARK, EX_CS5_N_MARK, + SCIFA2_TXD_MARK, I2C2_SDA_E_MARK, TS_SPSYNC_B_MARK, RIF0_D1_MARK, + FMIN_MARK, SCIFB2_RTS_N_MARK, STM_N_B_MARK, BS_N_MARK, DRACK0_MARK, + PWM1_C_MARK, TPUTO0_C_MARK, ATACS01_N_MARK, MTS_N_B_MARK, RD_N_MARK, + ATACS11_N_MARK, RD_WR_N_MARK, ATAG1_N_MARK, + + /* IPSR4 */ + EX_WAIT0_MARK, CAN_CLK_B_MARK, SCIF_CLK_MARK, PWMFSW0_MARK, + DU0_DR0_MARK, LCDOUT16_MARK, SCIF5_RXD_C_MARK, I2C2_SCL_D_MARK, + CC50_STATE0_MARK, DU0_DR1_MARK, LCDOUT17_MARK, SCIF5_TXD_C_MARK, + I2C2_SDA_D_MARK, CC50_STATE1_MARK, DU0_DR2_MARK, LCDOUT18_MARK, + CC50_STATE2_MARK, DU0_DR3_MARK, LCDOUT19_MARK, CC50_STATE3_MARK, + DU0_DR4_MARK, LCDOUT20_MARK, CC50_STATE4_MARK, DU0_DR5_MARK, + LCDOUT21_MARK, CC50_STATE5_MARK, DU0_DR6_MARK, LCDOUT22_MARK, + CC50_STATE6_MARK, DU0_DR7_MARK, LCDOUT23_MARK, CC50_STATE7_MARK, + DU0_DG0_MARK, LCDOUT8_MARK, SCIFA0_RXD_C_MARK, I2C3_SCL_D_MARK, + CC50_STATE8_MARK, DU0_DG1_MARK, LCDOUT9_MARK, SCIFA0_TXD_C_MARK, + I2C3_SDA_D_MARK, CC50_STATE9_MARK, DU0_DG2_MARK, LCDOUT10_MARK, + CC50_STATE10_MARK, DU0_DG3_MARK, LCDOUT11_MARK, CC50_STATE11_MARK, + DU0_DG4_MARK, LCDOUT12_MARK, CC50_STATE12_MARK, + + /* IPSR5 */ + DU0_DG5_MARK, LCDOUT13_MARK, CC50_STATE13_MARK, DU0_DG6_MARK, + LCDOUT14_MARK, CC50_STATE14_MARK, DU0_DG7_MARK, LCDOUT15_MARK, + CC50_STATE15_MARK, DU0_DB0_MARK, LCDOUT0_MARK, SCIFA4_RXD_C_MARK, + I2C4_SCL_D_MARK, CAN0_RX_C_MARK, CC50_STATE16_MARK, DU0_DB1_MARK, + LCDOUT1_MARK, SCIFA4_TXD_C_MARK, I2C4_SDA_D_MARK, CAN0_TX_C_MARK, + CC50_STATE17_MARK, DU0_DB2_MARK, LCDOUT2_MARK, CC50_STATE18_MARK, + DU0_DB3_MARK, LCDOUT3_MARK, CC50_STATE19_MARK, DU0_DB4_MARK, + LCDOUT4_MARK, CC50_STATE20_MARK, DU0_DB5_MARK, LCDOUT5_MARK, + CC50_STATE21_MARK, DU0_DB6_MARK, LCDOUT6_MARK, CC50_STATE22_MARK, + DU0_DB7_MARK, LCDOUT7_MARK, CC50_STATE23_MARK, DU0_DOTCLKIN_MARK, + QSTVA_QVS_MARK, CC50_STATE24_MARK, DU0_DOTCLKOUT0_MARK, + QCLK_MARK, CC50_STATE25_MARK, DU0_DOTCLKOUT1_MARK, QSTVB_QVE_MARK, + CC50_STATE26_MARK, DU0_EXHSYNC_DU0_HSYNC_MARK, QSTH_QHS_MARK, + CC50_STATE27_MARK, + + /* IPSR6 */ + DU0_EXVSYNC_DU0_VSYNC_MARK, QSTB_QHE_MARK, CC50_STATE28_MARK, + DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK, CC50_STATE29_MARK, + DU0_DISP_MARK, QPOLA_MARK, CC50_STATE30_MARK, DU0_CDE_MARK, QPOLB_MARK, + CC50_STATE31_MARK, VI0_CLK_MARK, AVB_RX_CLK_MARK, VI0_DATA0_VI0_B0_MARK, + AVB_RX_DV_MARK, VI0_DATA1_VI0_B1_MARK, AVB_RXD0_MARK, + VI0_DATA2_VI0_B2_MARK, AVB_RXD1_MARK, VI0_DATA3_VI0_B3_MARK, + AVB_RXD2_MARK, VI0_DATA4_VI0_B4_MARK, AVB_RXD3_MARK, + VI0_DATA5_VI0_B5_MARK, AVB_RXD4_MARK, VI0_DATA6_VI0_B6_MARK, + AVB_RXD5_MARK, VI0_DATA7_VI0_B7_MARK, AVB_RXD6_MARK, VI0_CLKENB_MARK, + I2C3_SCL_MARK, SCIFA5_RXD_C_MARK, IETX_C_MARK, AVB_RXD7_MARK, + VI0_FIELD_MARK, I2C3_SDA_MARK, SCIFA5_TXD_C_MARK, IECLK_C_MARK, + AVB_RX_ER_MARK, VI0_HSYNC_N_MARK, SCIF0_RXD_B_MARK, I2C0_SCL_C_MARK, + IERX_C_MARK, AVB_COL_MARK, VI0_VSYNC_N_MARK, SCIF0_TXD_B_MARK, + I2C0_SDA_C_MARK, AUDIO_CLKOUT_B_MARK, AVB_TX_EN_MARK, ETH_MDIO_MARK, + VI0_G0_MARK, MSIOF2_RXD_B_MARK, IIC0_SCL_D_MARK, AVB_TX_CLK_MARK, + ADIDATA_MARK, AD_DI_MARK, + + /* IPSR7 */ + ETH_CRS_DV_MARK, VI0_G1_MARK, MSIOF2_TXD_B_MARK, IIC0_SDA_D_MARK, + AVB_TXD0_MARK, ADICS_SAMP_MARK, AD_DO_MARK, ETH_RX_ER_MARK, VI0_G2_MARK, + MSIOF2_SCK_B_MARK, CAN0_RX_B_MARK, AVB_TXD1_MARK, ADICLK_MARK, + AD_CLK_MARK, ETH_RXD0_MARK, VI0_G3_MARK, MSIOF2_SYNC_B_MARK, + CAN0_TX_B_MARK, AVB_TXD2_MARK, ADICHS0_MARK, AD_NCS_N_MARK, + ETH_RXD1_MARK, VI0_G4_MARK, MSIOF2_SS1_B_MARK, SCIF4_RXD_D_MARK, + AVB_TXD3_MARK, ADICHS1_MARK, ETH_LINK_MARK, VI0_G5_MARK, + MSIOF2_SS2_B_MARK, SCIF4_TXD_D_MARK, AVB_TXD4_MARK, ADICHS2_MARK, + ETH_REFCLK_MARK, VI0_G6_MARK, SCIF2_SCK_C_MARK, AVB_TXD5_MARK, + SSI_SCK5_B_MARK, ETH_TXD1_MARK, VI0_G7_MARK, SCIF2_RXD_C_MARK, + IIC1_SCL_D_MARK, AVB_TXD6_MARK, SSI_WS5_B_MARK, ETH_TX_EN_MARK, + VI0_R0_MARK, SCIF2_TXD_C_MARK, IIC1_SDA_D_MARK, AVB_TXD7_MARK, + SSI_SDATA5_B_MARK, ETH_MAGIC_MARK, VI0_R1_MARK, SCIF3_SCK_B_MARK, + AVB_TX_ER_MARK, SSI_SCK6_B_MARK, ETH_TXD0_MARK, VI0_R2_MARK, + SCIF3_RXD_B_MARK, I2C4_SCL_E_MARK, AVB_GTX_CLK_MARK, SSI_WS6_B_MARK, + DREQ0_N_MARK, SCIFB1_RXD_MARK, + + /* IPSR8 */ + ETH_MDC_MARK, VI0_R3_MARK, SCIF3_TXD_B_MARK, I2C4_SDA_E_MARK, + AVB_MDC_MARK, SSI_SDATA6_B_MARK, HSCIF0_HRX_MARK, VI0_R4_MARK, + I2C1_SCL_C_MARK, AUDIO_CLKA_B_MARK, AVB_MDIO_MARK, SSI_SCK78_B_MARK, + HSCIF0_HTX_MARK, VI0_R5_MARK, I2C1_SDA_C_MARK, AUDIO_CLKB_B_MARK, + AVB_LINK_MARK, SSI_WS78_B_MARK, HSCIF0_HCTS_N_MARK, VI0_R6_MARK, + SCIF0_RXD_D_MARK, I2C0_SCL_E_MARK, AVB_MAGIC_MARK, SSI_SDATA7_B_MARK, + HSCIF0_HRTS_N_MARK, VI0_R7_MARK, SCIF0_TXD_D_MARK, I2C0_SDA_E_MARK, + AVB_PHY_INT_MARK, SSI_SDATA8_B_MARK, + HSCIF0_HSCK_MARK, SCIF_CLK_B_MARK, AVB_CRS_MARK, AUDIO_CLKC_B_MARK, + I2C0_SCL_MARK, SCIF0_RXD_C_MARK, PWM5_MARK, TCLK1_B_MARK, + AVB_GTXREFCLK_MARK, CAN1_RX_D_MARK, TPUTO0_B_MARK, I2C0_SDA_MARK, + SCIF0_TXD_C_MARK, TPUTO0_MARK, CAN_CLK_MARK, DVC_MUTE_MARK, + CAN1_TX_D_MARK, I2C1_SCL_MARK, SCIF4_RXD_MARK, PWM5_B_MARK, + DU1_DR0_MARK, RIF1_SYNC_B_MARK, TS_SDATA_D_MARK, TPUTO1_B_MARK, + I2C1_SDA_MARK, SCIF4_TXD_MARK, IRQ5_MARK, DU1_DR1_MARK, RIF1_CLK_B_MARK, + TS_SCK_D_MARK, BPFCLK_C_MARK, MSIOF0_RXD_MARK, SCIF5_RXD_MARK, + I2C2_SCL_C_MARK, DU1_DR2_MARK, RIF1_D0_B_MARK, TS_SDEN_D_MARK, + FMCLK_C_MARK, RDS_CLK_MARK, + + /* IPSR9 */ + MSIOF0_TXD_MARK, SCIF5_TXD_MARK, I2C2_SDA_C_MARK, DU1_DR3_MARK, + RIF1_D1_B_MARK, TS_SPSYNC_D_MARK, FMIN_C_MARK, RDS_DATA_MARK, + MSIOF0_SCK_MARK, IRQ0_MARK, TS_SDATA_MARK, DU1_DR4_MARK, RIF1_SYNC_MARK, + TPUTO1_C_MARK, MSIOF0_SYNC_MARK, PWM1_MARK, TS_SCK_MARK, DU1_DR5_MARK, + RIF1_CLK_MARK, BPFCLK_B_MARK, MSIOF0_SS1_MARK, SCIFA0_RXD_MARK, + TS_SDEN_MARK, DU1_DR6_MARK, RIF1_D0_MARK, FMCLK_B_MARK, RDS_CLK_B_MARK, + MSIOF0_SS2_MARK, SCIFA0_TXD_MARK, TS_SPSYNC_MARK, DU1_DR7_MARK, + RIF1_D1_MARK, FMIN_B_MARK, RDS_DATA_B_MARK, HSCIF1_HRX_MARK, + I2C4_SCL_MARK, PWM6_MARK, DU1_DG0_MARK, HSCIF1_HTX_MARK, + I2C4_SDA_MARK, TPUTO1_MARK, DU1_DG1_MARK, HSCIF1_HSCK_MARK, + PWM2_MARK, IETX_MARK, DU1_DG2_MARK, REMOCON_B_MARK, SPEEDIN_B_MARK, + VSP_B_MARK, HSCIF1_HCTS_N_MARK, SCIFA4_RXD_MARK, IECLK_MARK, + DU1_DG3_MARK, SSI_SCK1_B_MARK, CAN_DEBUG_HW_TRIGGER_MARK, + CC50_STATE32_MARK, HSCIF1_HRTS_N_MARK, SCIFA4_TXD_MARK, IERX_MARK, + DU1_DG4_MARK, SSI_WS1_B_MARK, CAN_STEP0_MARK, CC50_STATE33_MARK, + SCIF1_SCK_MARK, PWM3_MARK, TCLK2_MARK, DU1_DG5_MARK, SSI_SDATA1_B_MARK, + CAN_TXCLK_MARK, CC50_STATE34_MARK, + + /* IPSR10 */ + SCIF1_RXD_MARK, IIC0_SCL_MARK, DU1_DG6_MARK, SSI_SCK2_B_MARK, + CAN_DEBUGOUT0_MARK, CC50_STATE35_MARK, SCIF1_TXD_MARK, IIC0_SDA_MARK, + DU1_DG7_MARK, SSI_WS2_B_MARK, CAN_DEBUGOUT1_MARK, CC50_STATE36_MARK, + SCIF2_RXD_MARK, IIC1_SCL_MARK, DU1_DB0_MARK, SSI_SDATA2_B_MARK, + USB0_EXTLP_MARK, CAN_DEBUGOUT2_MARK, CC50_STATE37_MARK, SCIF2_TXD_MARK, + IIC1_SDA_MARK, DU1_DB1_MARK, SSI_SCK9_B_MARK, USB0_OVC1_MARK, + CAN_DEBUGOUT3_MARK, CC50_STATE38_MARK, SCIF2_SCK_MARK, IRQ1_MARK, + DU1_DB2_MARK, SSI_WS9_B_MARK, USB0_IDIN_MARK, CAN_DEBUGOUT4_MARK, + CC50_STATE39_MARK, SCIF3_SCK_MARK, IRQ2_MARK, BPFCLK_D_MARK, + DU1_DB3_MARK, SSI_SDATA9_B_MARK, TANS2_MARK, CAN_DEBUGOUT5_MARK, + CC50_OSCOUT_MARK, SCIF3_RXD_MARK, I2C1_SCL_E_MARK, FMCLK_D_MARK, + DU1_DB4_MARK, AUDIO_CLKA_C_MARK, SSI_SCK4_B_MARK, CAN_DEBUGOUT6_MARK, + RDS_CLK_C_MARK, SCIF3_TXD_MARK, I2C1_SDA_E_MARK, FMIN_D_MARK, + DU1_DB5_MARK, AUDIO_CLKB_C_MARK, SSI_WS4_B_MARK, CAN_DEBUGOUT7_MARK, + RDS_DATA_C_MARK, I2C2_SCL_MARK, SCIFA5_RXD_MARK, DU1_DB6_MARK, + AUDIO_CLKC_C_MARK, SSI_SDATA4_B_MARK, CAN_DEBUGOUT8_MARK, I2C2_SDA_MARK, + SCIFA5_TXD_MARK, DU1_DB7_MARK, AUDIO_CLKOUT_C_MARK, CAN_DEBUGOUT9_MARK, + SSI_SCK5_MARK, SCIFA3_SCK_MARK, DU1_DOTCLKIN_MARK, CAN_DEBUGOUT10_MARK, + + /* IPSR11 */ + SSI_WS5_MARK, SCIFA3_RXD_MARK, I2C3_SCL_C_MARK, DU1_DOTCLKOUT0_MARK, + CAN_DEBUGOUT11_MARK, SSI_SDATA5_MARK, SCIFA3_TXD_MARK, I2C3_SDA_C_MARK, + DU1_DOTCLKOUT1_MARK, CAN_DEBUGOUT12_MARK, SSI_SCK6_MARK, + SCIFA1_SCK_B_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK, CAN_DEBUGOUT13_MARK, + SSI_WS6_MARK, SCIFA1_RXD_B_MARK, I2C4_SCL_C_MARK, + DU1_EXVSYNC_DU1_VSYNC_MARK, CAN_DEBUGOUT14_MARK, SSI_SDATA6_MARK, + SCIFA1_TXD_B_MARK, I2C4_SDA_C_MARK, DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK, + CAN_DEBUGOUT15_MARK, SSI_SCK78_MARK, SCIFA2_SCK_B_MARK, IIC0_SDA_C_MARK, + DU1_DISP_MARK, SSI_WS78_MARK, SCIFA2_RXD_B_MARK, IIC0_SCL_C_MARK, + DU1_CDE_MARK, SSI_SDATA7_MARK, SCIFA2_TXD_B_MARK, IRQ8_MARK, + AUDIO_CLKA_D_MARK, CAN_CLK_D_MARK, PCMOE_N_MARK, SSI_SCK0129_MARK, + MSIOF1_RXD_B_MARK, SCIF5_RXD_D_MARK, ADIDATA_B_MARK, AD_DI_B_MARK, + PCMWE_N_MARK, SSI_WS0129_MARK, MSIOF1_TXD_B_MARK, SCIF5_TXD_D_MARK, + ADICS_SAMP_B_MARK, AD_DO_B_MARK, SSI_SDATA0_MARK, MSIOF1_SCK_B_MARK, + PWM0_B_MARK, ADICLK_B_MARK, AD_CLK_B_MARK, + + /* IPSR12 */ + SSI_SCK34_MARK, MSIOF1_SYNC_B_MARK, SCIFA1_SCK_C_MARK, ADICHS0_B_MARK, + AD_NCS_N_B_MARK, DREQ1_N_B_MARK, SSI_WS34_MARK, MSIOF1_SS1_B_MARK, + SCIFA1_RXD_C_MARK, ADICHS1_B_MARK, CAN1_RX_C_MARK, DACK1_B_MARK, + SSI_SDATA3_MARK, MSIOF1_SS2_B_MARK, SCIFA1_TXD_C_MARK, ADICHS2_B_MARK, + CAN1_TX_C_MARK, DREQ2_N_MARK, SSI_SCK4_MARK, MLB_CLK_MARK, IETX_B_MARK, + IRD_TX_MARK, SSI_WS4_MARK, MLB_SIG_MARK, IECLK_B_MARK, IRD_RX_MARK, + SSI_SDATA4_MARK, MLB_DAT_MARK, IERX_B_MARK, IRD_SCK_MARK, + SSI_SDATA8_MARK, SCIF1_SCK_B_MARK, PWM1_B_MARK, IRQ9_MARK, REMOCON_MARK, + DACK2_MARK, ETH_MDIO_B_MARK, SSI_SCK1_MARK, SCIF1_RXD_B_MARK, + IIC1_SCL_C_MARK, VI1_CLK_MARK, CAN0_RX_D_MARK, AVB_AVTP_CAPTURE_MARK, + ETH_CRS_DV_B_MARK, SSI_WS1_MARK, SCIF1_TXD_B_MARK, IIC1_SDA_C_MARK, + VI1_DATA0_MARK, CAN0_TX_D_MARK, AVB_AVTP_MATCH_MARK, ETH_RX_ER_B_MARK, + SSI_SDATA1_MARK, HSCIF1_HRX_B_MARK, VI1_DATA1_MARK, SDATA_MARK, + ATAG0_N_MARK, ETH_RXD0_B_MARK, SSI_SCK2_MARK, HSCIF1_HTX_B_MARK, + VI1_DATA2_MARK, MDATA_MARK, ATAWR0_N_MARK, ETH_RXD1_B_MARK, + + /* IPSR13 */ + SSI_WS2_MARK, HSCIF1_HCTS_N_B_MARK, SCIFA0_RXD_D_MARK, VI1_DATA3_MARK, + SCKZ_MARK, ATACS00_N_MARK, ETH_LINK_B_MARK, SSI_SDATA2_MARK, + HSCIF1_HRTS_N_B_MARK, SCIFA0_TXD_D_MARK, VI1_DATA4_MARK, STM_N_MARK, + ATACS10_N_MARK, ETH_REFCLK_B_MARK, SSI_SCK9_MARK, SCIF2_SCK_B_MARK, + PWM2_B_MARK, VI1_DATA5_MARK, MTS_N_MARK, EX_WAIT1_MARK, + ETH_TXD1_B_MARK, SSI_WS9_MARK, SCIF2_RXD_B_MARK, I2C3_SCL_E_MARK, + VI1_DATA6_MARK, ATARD0_N_MARK, ETH_TX_EN_B_MARK, SSI_SDATA9_MARK, + SCIF2_TXD_B_MARK, I2C3_SDA_E_MARK, VI1_DATA7_MARK, ATADIR0_N_MARK, + ETH_MAGIC_B_MARK, AUDIO_CLKA_MARK, I2C0_SCL_B_MARK, SCIFA4_RXD_D_MARK, + VI1_CLKENB_MARK, TS_SDATA_C_MARK, RIF0_SYNC_B_MARK, ETH_TXD0_B_MARK, + AUDIO_CLKB_MARK, I2C0_SDA_B_MARK, SCIFA4_TXD_D_MARK, VI1_FIELD_MARK, + TS_SCK_C_MARK, RIF0_CLK_B_MARK, BPFCLK_E_MARK, ETH_MDC_B_MARK, + AUDIO_CLKC_MARK, I2C4_SCL_B_MARK, SCIFA5_RXD_D_MARK, VI1_HSYNC_N_MARK, + TS_SDEN_C_MARK, RIF0_D0_B_MARK, FMCLK_E_MARK, RDS_CLK_D_MARK, + AUDIO_CLKOUT_MARK, I2C4_SDA_B_MARK, SCIFA5_TXD_D_MARK, VI1_VSYNC_N_MARK, + TS_SPSYNC_C_MARK, RIF0_D1_B_MARK, FMIN_E_MARK, RDS_DATA_D_MARK, + PINMUX_MARK_END, +}; + +static const u16 pinmux_data[] = { + PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */ + + PINMUX_DATA(A2_MARK, FN_A2), + PINMUX_DATA(WE0_N_MARK, FN_WE0_N), + PINMUX_DATA(WE1_N_MARK, FN_WE1_N), + PINMUX_DATA(DACK0_MARK, FN_DACK0), + PINMUX_DATA(USB0_PWEN_MARK, FN_USB0_PWEN), + PINMUX_DATA(USB0_OVC_MARK, FN_USB0_OVC), + PINMUX_DATA(USB1_PWEN_MARK, FN_USB1_PWEN), + PINMUX_DATA(USB1_OVC_MARK, FN_USB1_OVC), + PINMUX_DATA(SD0_CLK_MARK, FN_SD0_CLK), + PINMUX_DATA(SD0_CMD_MARK, FN_SD0_CMD), + PINMUX_DATA(SD0_DATA0_MARK, FN_SD0_DATA0), + PINMUX_DATA(SD0_DATA1_MARK, FN_SD0_DATA1), + PINMUX_DATA(SD0_DATA2_MARK, FN_SD0_DATA2), + PINMUX_DATA(SD0_DATA3_MARK, FN_SD0_DATA3), + PINMUX_DATA(SD0_CD_MARK, FN_SD0_CD), + PINMUX_DATA(SD0_WP_MARK, FN_SD0_WP), + PINMUX_DATA(SD1_CLK_MARK, FN_SD1_CLK), + PINMUX_DATA(SD1_CMD_MARK, FN_SD1_CMD), + PINMUX_DATA(SD1_DATA0_MARK, FN_SD1_DATA0), + PINMUX_DATA(SD1_DATA1_MARK, FN_SD1_DATA1), + PINMUX_DATA(SD1_DATA2_MARK, FN_SD1_DATA2), + PINMUX_DATA(SD1_DATA3_MARK, FN_SD1_DATA3), + + /* IPSR0 */ + PINMUX_IPSR_DATA(IP0_0, SD1_CD), + PINMUX_IPSR_MODSEL_DATA(IP0_0, CAN0_RX, SEL_CAN0_0), + PINMUX_IPSR_DATA(IP0_9_8, SD1_WP), + PINMUX_IPSR_DATA(IP0_9_8, IRQ7), + PINMUX_IPSR_MODSEL_DATA(IP0_9_8, CAN0_TX, SEL_CAN0_0), + PINMUX_IPSR_DATA(IP0_10, MMC_CLK), + PINMUX_IPSR_DATA(IP0_10, SD2_CLK), + PINMUX_IPSR_DATA(IP0_11, MMC_CMD), + PINMUX_IPSR_DATA(IP0_11, SD2_CMD), + PINMUX_IPSR_DATA(IP0_12, MMC_D0), + PINMUX_IPSR_DATA(IP0_12, SD2_DATA0), + PINMUX_IPSR_DATA(IP0_13, MMC_D1), + PINMUX_IPSR_DATA(IP0_13, SD2_DATA1), + PINMUX_IPSR_DATA(IP0_14, MMC_D2), + PINMUX_IPSR_DATA(IP0_14, SD2_DATA2), + PINMUX_IPSR_DATA(IP0_15, MMC_D3), + PINMUX_IPSR_DATA(IP0_15, SD2_DATA3), + PINMUX_IPSR_DATA(IP0_16, MMC_D4), + PINMUX_IPSR_DATA(IP0_16, SD2_CD), + PINMUX_IPSR_DATA(IP0_17, MMC_D5), + PINMUX_IPSR_DATA(IP0_17, SD2_WP), + PINMUX_IPSR_DATA(IP0_19_18, MMC_D6), + PINMUX_IPSR_MODSEL_DATA(IP0_19_18, SCIF0_RXD, SEL_SCIF0_0), + PINMUX_IPSR_MODSEL_DATA(IP0_19_18, I2C2_SCL_B, SEL_I2C02_1), + PINMUX_IPSR_MODSEL_DATA(IP0_19_18, CAN1_RX, SEL_CAN1_0), + PINMUX_IPSR_DATA(IP0_21_20, MMC_D7), + PINMUX_IPSR_MODSEL_DATA(IP0_21_20, SCIF0_TXD, SEL_SCIF0_0), + PINMUX_IPSR_MODSEL_DATA(IP0_21_20, I2C2_SDA_B, SEL_I2C02_1), + PINMUX_IPSR_MODSEL_DATA(IP0_21_20, CAN1_TX, SEL_CAN1_0), + PINMUX_IPSR_DATA(IP0_23_22, D0), + PINMUX_IPSR_MODSEL_DATA(IP0_23_22, SCIFA3_SCK_B, SEL_SCIFA3_1), + PINMUX_IPSR_DATA(IP0_23_22, IRQ4), + PINMUX_IPSR_DATA(IP0_24, D1), + PINMUX_IPSR_MODSEL_DATA(IP0_24, SCIFA3_RXD_B, SEL_SCIFA3_1), + PINMUX_IPSR_DATA(IP0_25, D2), + PINMUX_IPSR_MODSEL_DATA(IP0_25, SCIFA3_TXD_B, SEL_SCIFA3_1), + PINMUX_IPSR_DATA(IP0_27_26, D3), + PINMUX_IPSR_MODSEL_DATA(IP0_27_26, I2C3_SCL_B, SEL_I2C03_1), + PINMUX_IPSR_MODSEL_DATA(IP0_27_26, SCIF5_RXD_B, SEL_SCIF5_1), + PINMUX_IPSR_DATA(IP0_29_28, D4), + PINMUX_IPSR_MODSEL_DATA(IP0_29_28, I2C3_SDA_B, SEL_I2C03_1), + PINMUX_IPSR_MODSEL_DATA(IP0_29_28, SCIF5_TXD_B, SEL_SCIF5_1), + PINMUX_IPSR_DATA(IP0_31_30, D5), + PINMUX_IPSR_MODSEL_DATA(IP0_31_30, SCIF4_RXD_B, SEL_SCIF4_1), + PINMUX_IPSR_MODSEL_DATA(IP0_31_30, I2C0_SCL_D, SEL_I2C00_3), + + /* IPSR1 */ + PINMUX_IPSR_DATA(IP1_1_0, D6), + PINMUX_IPSR_MODSEL_DATA(IP1_1_0, SCIF4_TXD_B, SEL_SCIF4_1), + PINMUX_IPSR_MODSEL_DATA(IP1_1_0, I2C0_SDA_D, SEL_I2C00_3), + PINMUX_IPSR_DATA(IP1_3_2, D7), + PINMUX_IPSR_DATA(IP1_3_2, IRQ3), + PINMUX_IPSR_MODSEL_DATA(IP1_3_2, TCLK1, SEL_TMU_0), + PINMUX_IPSR_DATA(IP1_3_2, PWM6_B), + PINMUX_IPSR_DATA(IP1_5_4, D8), + PINMUX_IPSR_DATA(IP1_5_4, HSCIF2_HRX), + PINMUX_IPSR_MODSEL_DATA(IP1_5_4, I2C1_SCL_B, SEL_I2C01_1), + PINMUX_IPSR_DATA(IP1_7_6, D9), + PINMUX_IPSR_DATA(IP1_7_6, HSCIF2_HTX), + PINMUX_IPSR_MODSEL_DATA(IP1_7_6, I2C1_SDA_B, SEL_I2C01_1), + PINMUX_IPSR_DATA(IP1_10_8, D10), + PINMUX_IPSR_DATA(IP1_10_8, HSCIF2_HSCK), + PINMUX_IPSR_MODSEL_DATA(IP1_10_8, SCIF1_SCK_C, SEL_SCIF1_2), + PINMUX_IPSR_DATA(IP1_10_8, IRQ6), + PINMUX_IPSR_DATA(IP1_10_8, PWM5_C), + PINMUX_IPSR_DATA(IP1_12_11, D11), + PINMUX_IPSR_DATA(IP1_12_11, HSCIF2_HCTS_N), + PINMUX_IPSR_MODSEL_DATA(IP1_12_11, SCIF1_RXD_C, SEL_SCIF1_2), + PINMUX_IPSR_MODSEL_DATA(IP1_12_11, I2C1_SCL_D, SEL_I2C01_3), + PINMUX_IPSR_DATA(IP1_14_13, D12), + PINMUX_IPSR_DATA(IP1_14_13, HSCIF2_HRTS_N), + PINMUX_IPSR_MODSEL_DATA(IP1_14_13, SCIF1_TXD_C, SEL_SCIF1_2), + PINMUX_IPSR_MODSEL_DATA(IP1_14_13, I2C1_SDA_D, SEL_I2C01_3), + PINMUX_IPSR_DATA(IP1_17_15, D13), + PINMUX_IPSR_MODSEL_DATA(IP1_17_15, SCIFA1_SCK, SEL_SCIFA1_0), + PINMUX_IPSR_DATA(IP1_17_15, TANS1), + PINMUX_IPSR_DATA(IP1_17_15, PWM2_C), + PINMUX_IPSR_MODSEL_DATA(IP1_17_15, TCLK2_B, SEL_TMU_1), + PINMUX_IPSR_DATA(IP1_19_18, D14), + PINMUX_IPSR_MODSEL_DATA(IP1_19_18, SCIFA1_RXD, SEL_SCIFA1_0), + PINMUX_IPSR_MODSEL_DATA(IP1_19_18, IIC0_SCL_B, SEL_IIC00_1), + PINMUX_IPSR_DATA(IP1_21_20, D15), + PINMUX_IPSR_MODSEL_DATA(IP1_21_20, SCIFA1_TXD, SEL_SCIFA1_0), + PINMUX_IPSR_MODSEL_DATA(IP1_21_20, IIC0_SDA_B, SEL_IIC00_1), + PINMUX_IPSR_DATA(IP1_23_22, A0), + PINMUX_IPSR_DATA(IP1_23_22, SCIFB1_SCK), + PINMUX_IPSR_DATA(IP1_23_22, PWM3_B), + PINMUX_IPSR_DATA(IP1_24, A1), + PINMUX_IPSR_DATA(IP1_24, SCIFB1_TXD), + PINMUX_IPSR_DATA(IP1_26, A3), + PINMUX_IPSR_DATA(IP1_26, SCIFB0_SCK), + PINMUX_IPSR_DATA(IP1_27, A4), + PINMUX_IPSR_DATA(IP1_27, SCIFB0_TXD), + PINMUX_IPSR_DATA(IP1_29_28, A5), + PINMUX_IPSR_DATA(IP1_29_28, SCIFB0_RXD), + PINMUX_IPSR_DATA(IP1_29_28, PWM4_B), + PINMUX_IPSR_DATA(IP1_29_28, TPUTO3_C), + PINMUX_IPSR_DATA(IP1_31_30, A6), + PINMUX_IPSR_DATA(IP1_31_30, SCIFB0_CTS_N), + PINMUX_IPSR_MODSEL_DATA(IP1_31_30, SCIFA4_RXD_B, SEL_SCIFA4_1), + PINMUX_IPSR_DATA(IP1_31_30, TPUTO2_C), + + /* IPSR2 */ + PINMUX_IPSR_DATA(IP2_1_0, A7), + PINMUX_IPSR_DATA(IP2_1_0, SCIFB0_RTS_N), + PINMUX_IPSR_MODSEL_DATA(IP2_1_0, SCIFA4_TXD_B, SEL_SCIFA4_1), + PINMUX_IPSR_DATA(IP2_3_2, A8), + PINMUX_IPSR_MODSEL_DATA(IP2_3_2, MSIOF1_RXD, SEL_MSI1_0), + PINMUX_IPSR_MODSEL_DATA(IP2_3_2, SCIFA0_RXD_B, SEL_SCIFA0_1), + PINMUX_IPSR_DATA(IP2_5_4, A9), + PINMUX_IPSR_MODSEL_DATA(IP2_5_4, MSIOF1_TXD, SEL_MSI1_0), + PINMUX_IPSR_MODSEL_DATA(IP2_5_4, SCIFA0_TXD_B, SEL_SCIFA0_1), + PINMUX_IPSR_DATA(IP2_7_6, A10), + PINMUX_IPSR_MODSEL_DATA(IP2_7_6, MSIOF1_SCK, SEL_MSI1_0), + PINMUX_IPSR_MODSEL_DATA(IP2_7_6, IIC1_SCL_B, SEL_IIC01_1), + PINMUX_IPSR_DATA(IP2_9_8, A11), + PINMUX_IPSR_MODSEL_DATA(IP2_9_8, MSIOF1_SYNC, SEL_MSI1_0), + PINMUX_IPSR_MODSEL_DATA(IP2_9_8, IIC1_SDA_B, SEL_IIC01_1), + PINMUX_IPSR_DATA(IP2_11_10, A12), + PINMUX_IPSR_MODSEL_DATA(IP2_11_10, MSIOF1_SS1, SEL_MSI1_0), + PINMUX_IPSR_MODSEL_DATA(IP2_11_10, SCIFA5_RXD_B, SEL_SCIFA5_1), + PINMUX_IPSR_DATA(IP2_13_12, A13), + PINMUX_IPSR_MODSEL_DATA(IP2_13_12, MSIOF1_SS2, SEL_MSI1_0), + PINMUX_IPSR_MODSEL_DATA(IP2_13_12, SCIFA5_TXD_B, SEL_SCIFA5_1), + PINMUX_IPSR_DATA(IP2_15_14, A14), + PINMUX_IPSR_MODSEL_DATA(IP2_15_14, MSIOF2_RXD, SEL_MSI2_0), + PINMUX_IPSR_MODSEL_DATA(IP2_15_14, HSCIF0_HRX_B, SEL_HSCIF0_1), + PINMUX_IPSR_MODSEL_DATA(IP2_15_14, DREQ1_N, SEL_LBS_0), + PINMUX_IPSR_DATA(IP2_17_16, A15), + PINMUX_IPSR_MODSEL_DATA(IP2_17_16, MSIOF2_TXD, SEL_MSI2_0), + PINMUX_IPSR_MODSEL_DATA(IP2_17_16, HSCIF0_HTX_B, SEL_HSCIF0_1), + PINMUX_IPSR_MODSEL_DATA(IP2_17_16, DACK1, SEL_LBS_0), + PINMUX_IPSR_DATA(IP2_20_18, A16), + PINMUX_IPSR_MODSEL_DATA(IP2_20_18, MSIOF2_SCK, SEL_MSI2_0), + PINMUX_IPSR_MODSEL_DATA(IP2_20_18, HSCIF0_HSCK_B, SEL_HSCIF0_1), + PINMUX_IPSR_MODSEL_DATA(IP2_20_18, SPEEDIN, SEL_RSP_0), + PINMUX_IPSR_MODSEL_DATA(IP2_20_18, VSP, SEL_SPDM_0), + PINMUX_IPSR_MODSEL_DATA(IP2_20_18, CAN_CLK_C, SEL_CAN_2), + PINMUX_IPSR_DATA(IP2_20_18, TPUTO2_B), + PINMUX_IPSR_DATA(IP2_23_21, A17), + PINMUX_IPSR_MODSEL_DATA(IP2_23_21, MSIOF2_SYNC, SEL_MSI2_0), + PINMUX_IPSR_MODSEL_DATA(IP2_23_21, SCIF4_RXD_E, SEL_SCIF4_4), + PINMUX_IPSR_MODSEL_DATA(IP2_23_21, CAN1_RX_B, SEL_CAN1_1), + PINMUX_IPSR_MODSEL_DATA(IP2_23_21, AVB_AVTP_CAPTURE_B, SEL_AVB_1), + PINMUX_IPSR_DATA(IP2_26_24, A18), + PINMUX_IPSR_MODSEL_DATA(IP2_26_24, MSIOF2_SS1, SEL_MSI2_0), + PINMUX_IPSR_MODSEL_DATA(IP2_26_24, SCIF4_TXD_E, SEL_SCIF4_4), + PINMUX_IPSR_MODSEL_DATA(IP2_26_24, CAN1_TX_B, SEL_CAN1_1), + PINMUX_IPSR_MODSEL_DATA(IP2_26_24, AVB_AVTP_MATCH_B, SEL_AVB_1), + PINMUX_IPSR_DATA(IP2_29_27, A19), + PINMUX_IPSR_MODSEL_DATA(IP2_29_27, MSIOF2_SS2, SEL_MSI2_0), + PINMUX_IPSR_DATA(IP2_29_27, PWM4), + PINMUX_IPSR_DATA(IP2_29_27, TPUTO2), + PINMUX_IPSR_DATA(IP2_29_27, MOUT0), + PINMUX_IPSR_DATA(IP2_31_30, A20), + PINMUX_IPSR_DATA(IP2_31_30, SPCLK), + PINMUX_IPSR_DATA(IP2_29_27, MOUT1), + + /* IPSR3 */ + PINMUX_IPSR_DATA(IP3_1_0, A21), + PINMUX_IPSR_DATA(IP3_1_0, MOSI_IO0), + PINMUX_IPSR_DATA(IP3_1_0, MOUT2), + PINMUX_IPSR_DATA(IP3_3_2, A22), + PINMUX_IPSR_DATA(IP3_3_2, MISO_IO1), + PINMUX_IPSR_DATA(IP3_3_2, MOUT5), + PINMUX_IPSR_DATA(IP3_3_2, ATADIR1_N), + PINMUX_IPSR_DATA(IP3_5_4, A23), + PINMUX_IPSR_DATA(IP3_5_4, IO2), + PINMUX_IPSR_DATA(IP3_5_4, MOUT6), + PINMUX_IPSR_DATA(IP3_5_4, ATAWR1_N), + PINMUX_IPSR_DATA(IP3_7_6, A24), + PINMUX_IPSR_DATA(IP3_7_6, IO3), + PINMUX_IPSR_DATA(IP3_7_6, EX_WAIT2), + PINMUX_IPSR_DATA(IP3_9_8, A25), + PINMUX_IPSR_DATA(IP3_9_8, SSL), + PINMUX_IPSR_DATA(IP3_9_8, ATARD1_N), + PINMUX_IPSR_DATA(IP3_10, CS0_N), + PINMUX_IPSR_DATA(IP3_10, VI1_DATA8), + PINMUX_IPSR_DATA(IP3_11, CS1_N_A26), + PINMUX_IPSR_DATA(IP3_11, VI1_DATA9), + PINMUX_IPSR_DATA(IP3_12, EX_CS0_N), + PINMUX_IPSR_DATA(IP3_12, VI1_DATA10), + PINMUX_IPSR_DATA(IP3_14_13, EX_CS1_N), + PINMUX_IPSR_DATA(IP3_14_13, TPUTO3_B), + PINMUX_IPSR_DATA(IP3_14_13, SCIFB2_RXD), + PINMUX_IPSR_DATA(IP3_14_13, VI1_DATA11), + PINMUX_IPSR_DATA(IP3_17_15, EX_CS2_N), + PINMUX_IPSR_DATA(IP3_17_15, PWM0), + PINMUX_IPSR_MODSEL_DATA(IP3_17_15, SCIF4_RXD_C, SEL_SCIF4_2), + PINMUX_IPSR_MODSEL_DATA(IP3_17_15, TS_SDATA_B, SEL_TSIF0_1), + PINMUX_IPSR_MODSEL_DATA(IP3_17_15, RIF0_SYNC, SEL_DR0_0), + PINMUX_IPSR_DATA(IP3_17_15, TPUTO3), + PINMUX_IPSR_DATA(IP3_17_15, SCIFB2_TXD), + PINMUX_IPSR_MODSEL_DATA(IP3_17_15, SDATA_B, SEL_FSN_1), + PINMUX_IPSR_DATA(IP3_20_18, EX_CS3_N), + PINMUX_IPSR_MODSEL_DATA(IP3_20_18, SCIFA2_SCK, SEL_SCIFA2_0), + PINMUX_IPSR_MODSEL_DATA(IP3_20_18, SCIF4_TXD_C, SEL_SCIF4_2), + PINMUX_IPSR_MODSEL_DATA(IP3_20_18, TS_SCK_B, SEL_TSIF0_1), + PINMUX_IPSR_MODSEL_DATA(IP3_20_18, RIF0_CLK, SEL_DR0_0), + PINMUX_IPSR_MODSEL_DATA(IP3_20_18, BPFCLK, SEL_DARC_0), + PINMUX_IPSR_DATA(IP3_20_18, SCIFB2_SCK), + PINMUX_IPSR_MODSEL_DATA(IP3_20_18, MDATA_B, SEL_FSN_1), + PINMUX_IPSR_DATA(IP3_23_21, EX_CS4_N), + PINMUX_IPSR_MODSEL_DATA(IP3_23_21, SCIFA2_RXD, SEL_SCIFA2_0), + PINMUX_IPSR_MODSEL_DATA(IP3_23_21, I2C2_SCL_E, SEL_I2C02_4), + PINMUX_IPSR_MODSEL_DATA(IP3_23_21, TS_SDEN_B, SEL_TSIF0_1), + PINMUX_IPSR_MODSEL_DATA(IP3_23_21, RIF0_D0, SEL_DR0_0), + PINMUX_IPSR_MODSEL_DATA(IP3_23_21, FMCLK, SEL_DARC_0), + PINMUX_IPSR_DATA(IP3_23_21, SCIFB2_CTS_N), + PINMUX_IPSR_MODSEL_DATA(IP3_23_21, SCKZ_B, SEL_FSN_1), + PINMUX_IPSR_DATA(IP3_26_24, EX_CS5_N), + PINMUX_IPSR_MODSEL_DATA(IP3_26_24, SCIFA2_TXD, SEL_SCIFA2_0), + PINMUX_IPSR_MODSEL_DATA(IP3_26_24, I2C2_SDA_E, SEL_I2C02_4), + PINMUX_IPSR_MODSEL_DATA(IP3_26_24, TS_SPSYNC_B, SEL_TSIF0_1), + PINMUX_IPSR_MODSEL_DATA(IP3_26_24, RIF0_D1, SEL_DR1_0), + PINMUX_IPSR_MODSEL_DATA(IP3_26_24, FMIN, SEL_DARC_0), + PINMUX_IPSR_DATA(IP3_26_24, SCIFB2_RTS_N), + PINMUX_IPSR_MODSEL_DATA(IP3_26_24, STM_N_B, SEL_FSN_1), + PINMUX_IPSR_DATA(IP3_29_27, BS_N), + PINMUX_IPSR_DATA(IP3_29_27, DRACK0), + PINMUX_IPSR_DATA(IP3_29_27, PWM1_C), + PINMUX_IPSR_DATA(IP3_29_27, TPUTO0_C), + PINMUX_IPSR_DATA(IP3_29_27, ATACS01_N), + PINMUX_IPSR_MODSEL_DATA(IP3_29_27, MTS_N_B, SEL_FSN_1), + PINMUX_IPSR_DATA(IP3_30, RD_N), + PINMUX_IPSR_DATA(IP3_30, ATACS11_N), + PINMUX_IPSR_DATA(IP3_31, RD_WR_N), + PINMUX_IPSR_DATA(IP3_31, ATAG1_N), + + /* IPSR4 */ + PINMUX_IPSR_DATA(IP4_1_0, EX_WAIT0), + PINMUX_IPSR_MODSEL_DATA(IP4_1_0, CAN_CLK_B, SEL_CAN_1), + PINMUX_IPSR_MODSEL_DATA(IP4_1_0, SCIF_CLK, SEL_SCIF0_0), + PINMUX_IPSR_DATA(IP4_1_0, PWMFSW0), + PINMUX_IPSR_DATA(IP4_4_2, DU0_DR0), + PINMUX_IPSR_DATA(IP4_4_2, LCDOUT16), + PINMUX_IPSR_MODSEL_DATA(IP4_4_2, SCIF5_RXD_C, SEL_SCIF5_2), + PINMUX_IPSR_MODSEL_DATA(IP4_4_2, I2C2_SCL_D, SEL_I2C02_3), + PINMUX_IPSR_DATA(IP4_4_2, CC50_STATE0), + PINMUX_IPSR_DATA(IP4_7_5, DU0_DR1), + PINMUX_IPSR_DATA(IP4_7_5, LCDOUT17), + PINMUX_IPSR_MODSEL_DATA(IP4_7_5, SCIF5_TXD_C, SEL_SCIF5_2), + PINMUX_IPSR_MODSEL_DATA(IP4_7_5, I2C2_SDA_D, SEL_I2C02_3), + PINMUX_IPSR_DATA(IP4_9_8, CC50_STATE1), + PINMUX_IPSR_DATA(IP4_9_8, DU0_DR2), + PINMUX_IPSR_DATA(IP4_9_8, LCDOUT18), + PINMUX_IPSR_DATA(IP4_9_8, CC50_STATE2), + PINMUX_IPSR_DATA(IP4_11_10, DU0_DR3), + PINMUX_IPSR_DATA(IP4_11_10, LCDOUT19), + PINMUX_IPSR_DATA(IP4_11_10, CC50_STATE3), + PINMUX_IPSR_DATA(IP4_13_12, DU0_DR4), + PINMUX_IPSR_DATA(IP4_13_12, LCDOUT20), + PINMUX_IPSR_DATA(IP4_13_12, CC50_STATE4), + PINMUX_IPSR_DATA(IP4_15_14, DU0_DR5), + PINMUX_IPSR_DATA(IP4_15_14, LCDOUT21), + PINMUX_IPSR_DATA(IP4_15_14, CC50_STATE5), + PINMUX_IPSR_DATA(IP4_17_16, DU0_DR6), + PINMUX_IPSR_DATA(IP4_17_16, LCDOUT22), + PINMUX_IPSR_DATA(IP4_17_16, CC50_STATE6), + PINMUX_IPSR_DATA(IP4_19_18, DU0_DR7), + PINMUX_IPSR_DATA(IP4_19_18, LCDOUT23), + PINMUX_IPSR_DATA(IP4_19_18, CC50_STATE7), + PINMUX_IPSR_DATA(IP4_22_20, DU0_DG0), + PINMUX_IPSR_DATA(IP4_22_20, LCDOUT8), + PINMUX_IPSR_MODSEL_DATA(IP4_22_20, SCIFA0_RXD_C, SEL_SCIFA0_2), + PINMUX_IPSR_MODSEL_DATA(IP4_22_20, I2C3_SCL_D, SEL_I2C03_3), + PINMUX_IPSR_DATA(IP4_22_20, CC50_STATE8), + PINMUX_IPSR_DATA(IP4_25_23, DU0_DG1), + PINMUX_IPSR_DATA(IP4_25_23, LCDOUT9), + PINMUX_IPSR_MODSEL_DATA(IP4_25_23, SCIFA0_TXD_C, SEL_SCIFA0_2), + PINMUX_IPSR_MODSEL_DATA(IP4_25_23, I2C3_SDA_D, SEL_I2C03_3), + PINMUX_IPSR_DATA(IP4_25_23, CC50_STATE9), + PINMUX_IPSR_DATA(IP4_27_26, DU0_DG2), + PINMUX_IPSR_DATA(IP4_27_26, LCDOUT10), + PINMUX_IPSR_DATA(IP4_27_26, CC50_STATE10), + PINMUX_IPSR_DATA(IP4_29_28, DU0_DG3), + PINMUX_IPSR_DATA(IP4_29_28, LCDOUT11), + PINMUX_IPSR_DATA(IP4_29_28, CC50_STATE11), + PINMUX_IPSR_DATA(IP4_31_30, DU0_DG4), + PINMUX_IPSR_DATA(IP4_31_30, LCDOUT12), + PINMUX_IPSR_DATA(IP4_31_30, CC50_STATE12), + + /* IPSR5 */ + PINMUX_IPSR_DATA(IP5_1_0, DU0_DG5), + PINMUX_IPSR_DATA(IP5_1_0, LCDOUT13), + PINMUX_IPSR_DATA(IP5_1_0, CC50_STATE13), + PINMUX_IPSR_DATA(IP5_3_2, DU0_DG6), + PINMUX_IPSR_DATA(IP5_3_2, LCDOUT14), + PINMUX_IPSR_DATA(IP5_3_2, CC50_STATE14), + PINMUX_IPSR_DATA(IP5_5_4, DU0_DG7), + PINMUX_IPSR_DATA(IP5_5_4, LCDOUT15), + PINMUX_IPSR_DATA(IP5_5_4, CC50_STATE15), + PINMUX_IPSR_DATA(IP5_8_6, DU0_DB0), + PINMUX_IPSR_DATA(IP5_8_6, LCDOUT0), + PINMUX_IPSR_MODSEL_DATA(IP5_8_6, SCIFA4_RXD_C, SEL_SCIFA4_2), + PINMUX_IPSR_MODSEL_DATA(IP5_8_6, I2C4_SCL_D, SEL_I2C04_3), + PINMUX_IPSR_MODSEL_DATA(IP7_8_6, CAN0_RX_C, SEL_CAN0_2), + PINMUX_IPSR_DATA(IP5_8_6, CC50_STATE16), + PINMUX_IPSR_DATA(IP5_11_9, DU0_DB1), + PINMUX_IPSR_DATA(IP5_11_9, LCDOUT1), + PINMUX_IPSR_MODSEL_DATA(IP5_11_9, SCIFA4_TXD_C, SEL_SCIFA4_2), + PINMUX_IPSR_MODSEL_DATA(IP5_11_9, I2C4_SDA_D, SEL_I2C04_3), + PINMUX_IPSR_MODSEL_DATA(IP5_11_9, CAN0_TX_C, SEL_CAN0_2), + PINMUX_IPSR_DATA(IP5_11_9, CC50_STATE17), + PINMUX_IPSR_DATA(IP5_13_12, DU0_DB2), + PINMUX_IPSR_DATA(IP5_13_12, LCDOUT2), + PINMUX_IPSR_DATA(IP5_13_12, CC50_STATE18), + PINMUX_IPSR_DATA(IP5_15_14, DU0_DB3), + PINMUX_IPSR_DATA(IP5_15_14, LCDOUT3), + PINMUX_IPSR_DATA(IP5_15_14, CC50_STATE19), + PINMUX_IPSR_DATA(IP5_17_16, DU0_DB4), + PINMUX_IPSR_DATA(IP5_17_16, LCDOUT4), + PINMUX_IPSR_DATA(IP5_17_16, CC50_STATE20), + PINMUX_IPSR_DATA(IP5_19_18, DU0_DB5), + PINMUX_IPSR_DATA(IP5_19_18, LCDOUT5), + PINMUX_IPSR_DATA(IP5_19_18, CC50_STATE21), + PINMUX_IPSR_DATA(IP5_21_20, DU0_DB6), + PINMUX_IPSR_DATA(IP5_21_20, LCDOUT6), + PINMUX_IPSR_DATA(IP5_21_20, CC50_STATE22), + PINMUX_IPSR_DATA(IP5_23_22, DU0_DB7), + PINMUX_IPSR_DATA(IP5_23_22, LCDOUT7), + PINMUX_IPSR_DATA(IP5_23_22, CC50_STATE23), + PINMUX_IPSR_DATA(IP5_25_24, DU0_DOTCLKIN), + PINMUX_IPSR_DATA(IP5_25_24, QSTVA_QVS), + PINMUX_IPSR_DATA(IP5_25_24, CC50_STATE24), + PINMUX_IPSR_DATA(IP5_27_26, DU0_DOTCLKOUT0), + PINMUX_IPSR_DATA(IP5_27_26, QCLK), + PINMUX_IPSR_DATA(IP5_27_26, CC50_STATE25), + PINMUX_IPSR_DATA(IP5_29_28, DU0_DOTCLKOUT1), + PINMUX_IPSR_DATA(IP5_29_28, QSTVB_QVE), + PINMUX_IPSR_DATA(IP5_29_28, CC50_STATE26), + PINMUX_IPSR_DATA(IP5_31_30, DU0_EXHSYNC_DU0_HSYNC), + PINMUX_IPSR_DATA(IP5_31_30, QSTH_QHS), + PINMUX_IPSR_DATA(IP5_31_30, CC50_STATE27), + + /* IPSR6 */ + PINMUX_IPSR_DATA(IP6_1_0, DU0_EXVSYNC_DU0_VSYNC), + PINMUX_IPSR_DATA(IP6_1_0, QSTB_QHE), + PINMUX_IPSR_DATA(IP6_1_0, CC50_STATE28), + PINMUX_IPSR_DATA(IP6_3_2, DU0_EXODDF_DU0_ODDF_DISP_CDE), + PINMUX_IPSR_DATA(IP6_3_2, QCPV_QDE), + PINMUX_IPSR_DATA(IP6_3_2, CC50_STATE29), + PINMUX_IPSR_DATA(IP6_5_4, DU0_DISP), + PINMUX_IPSR_DATA(IP6_5_4, QPOLA), + PINMUX_IPSR_DATA(IP6_5_4, CC50_STATE30), + PINMUX_IPSR_DATA(IP6_7_6, DU0_CDE), + PINMUX_IPSR_DATA(IP6_7_6, QPOLB), + PINMUX_IPSR_DATA(IP6_7_6, CC50_STATE31), + PINMUX_IPSR_DATA(IP6_8, VI0_CLK), + PINMUX_IPSR_DATA(IP6_8, AVB_RX_CLK), + PINMUX_IPSR_DATA(IP6_9, VI0_DATA0_VI0_B0), + PINMUX_IPSR_DATA(IP6_9, AVB_RX_DV), + PINMUX_IPSR_DATA(IP6_10, VI0_DATA1_VI0_B1), + PINMUX_IPSR_DATA(IP6_10, AVB_RXD0), + PINMUX_IPSR_DATA(IP6_11, VI0_DATA2_VI0_B2), + PINMUX_IPSR_DATA(IP6_11, AVB_RXD1), + PINMUX_IPSR_DATA(IP6_12, VI0_DATA3_VI0_B3), + PINMUX_IPSR_DATA(IP6_12, AVB_RXD2), + PINMUX_IPSR_DATA(IP6_13, VI0_DATA4_VI0_B4), + PINMUX_IPSR_DATA(IP6_13, AVB_RXD3), + PINMUX_IPSR_DATA(IP6_14, VI0_DATA5_VI0_B5), + PINMUX_IPSR_DATA(IP6_14, AVB_RXD4), + PINMUX_IPSR_DATA(IP6_15, VI0_DATA6_VI0_B6), + PINMUX_IPSR_DATA(IP6_15, AVB_RXD5), + PINMUX_IPSR_DATA(IP6_16, VI0_DATA7_VI0_B7), + PINMUX_IPSR_DATA(IP6_16, AVB_RXD6), + PINMUX_IPSR_DATA(IP6_19_17, VI0_CLKENB), + PINMUX_IPSR_MODSEL_DATA(IP6_19_17, I2C3_SCL, SEL_I2C03_0), + PINMUX_IPSR_MODSEL_DATA(IP6_19_17, SCIFA5_RXD_C, SEL_SCIFA5_2), + PINMUX_IPSR_MODSEL_DATA(IP6_19_17, IETX_C, SEL_IEB_2), + PINMUX_IPSR_DATA(IP6_19_17, AVB_RXD7), + PINMUX_IPSR_DATA(IP6_22_20, VI0_FIELD), + PINMUX_IPSR_MODSEL_DATA(IP6_22_20, I2C3_SDA, SEL_I2C03_0), + PINMUX_IPSR_MODSEL_DATA(IP6_22_20, SCIFA5_TXD_C, SEL_SCIFA5_2), + PINMUX_IPSR_MODSEL_DATA(IP6_22_20, IECLK_C, SEL_IEB_2), + PINMUX_IPSR_DATA(IP6_22_20, AVB_RX_ER), + PINMUX_IPSR_DATA(IP6_25_23, VI0_HSYNC_N), + PINMUX_IPSR_MODSEL_DATA(IP6_25_23, SCIF0_RXD_B, SEL_SCIF0_1), + PINMUX_IPSR_MODSEL_DATA(IP6_25_23, I2C0_SCL_C, SEL_I2C00_2), + PINMUX_IPSR_MODSEL_DATA(IP6_25_23, IERX_C, SEL_IEB_2), + PINMUX_IPSR_DATA(IP6_25_23, AVB_COL), + PINMUX_IPSR_DATA(IP6_28_26, VI0_VSYNC_N), + PINMUX_IPSR_MODSEL_DATA(IP6_28_26, SCIF0_TXD_B, SEL_SCIF0_1), + PINMUX_IPSR_MODSEL_DATA(IP6_28_26, I2C0_SDA_C, SEL_I2C00_2), + PINMUX_IPSR_MODSEL_DATA(IP6_28_26, AUDIO_CLKOUT_B, SEL_ADG_1), + PINMUX_IPSR_DATA(IP6_28_26, AVB_TX_EN), + PINMUX_IPSR_MODSEL_DATA(IP6_31_29, ETH_MDIO, SEL_ETH_0), + PINMUX_IPSR_DATA(IP6_31_29, VI0_G0), + PINMUX_IPSR_MODSEL_DATA(IP6_31_29, MSIOF2_RXD_B, SEL_MSI2_1), + PINMUX_IPSR_MODSEL_DATA(IP6_31_29, IIC0_SCL_D, SEL_IIC00_3), + PINMUX_IPSR_DATA(IP6_31_29, AVB_TX_CLK), + PINMUX_IPSR_MODSEL_DATA(IP6_31_29, ADIDATA, SEL_RAD_0), + PINMUX_IPSR_MODSEL_DATA(IP6_31_29, AD_DI, SEL_ADI_0), + + /* IPSR7 */ + PINMUX_IPSR_MODSEL_DATA(IP7_2_0, ETH_CRS_DV, SEL_ETH_0), + PINMUX_IPSR_DATA(IP7_2_0, VI0_G1), + PINMUX_IPSR_MODSEL_DATA(IP7_2_0, MSIOF2_TXD_B, SEL_MSI2_1), + PINMUX_IPSR_MODSEL_DATA(IP7_2_0, IIC0_SDA_D, SEL_IIC00_3), + PINMUX_IPSR_DATA(IP7_2_0, AVB_TXD0), + PINMUX_IPSR_MODSEL_DATA(IP7_2_0, ADICS_SAMP, SEL_RAD_0), + PINMUX_IPSR_MODSEL_DATA(IP7_2_0, AD_DO, SEL_ADI_0), + PINMUX_IPSR_MODSEL_DATA(IP7_5_3, ETH_RX_ER, SEL_ETH_0), + PINMUX_IPSR_DATA(IP7_5_3, VI0_G2), + PINMUX_IPSR_MODSEL_DATA(IP7_5_3, MSIOF2_SCK_B, SEL_MSI2_1), + PINMUX_IPSR_MODSEL_DATA(IP7_5_3, CAN0_RX_B, SEL_CAN0_1), + PINMUX_IPSR_DATA(IP7_5_3, AVB_TXD1), + PINMUX_IPSR_MODSEL_DATA(IP7_5_3, ADICLK, SEL_RAD_0), + PINMUX_IPSR_MODSEL_DATA(IP7_5_3, AD_CLK, SEL_ADI_0), + PINMUX_IPSR_MODSEL_DATA(IP7_8_6, ETH_RXD0, SEL_ETH_0), + PINMUX_IPSR_DATA(IP7_8_6, VI0_G3), + PINMUX_IPSR_MODSEL_DATA(IP7_8_6, MSIOF2_SYNC_B, SEL_MSI2_1), + PINMUX_IPSR_MODSEL_DATA(IP7_8_6, CAN0_TX_B, SEL_CAN0_1), + PINMUX_IPSR_DATA(IP7_8_6, AVB_TXD2), + PINMUX_IPSR_MODSEL_DATA(IP7_8_6, ADICHS0, SEL_RAD_0), + PINMUX_IPSR_MODSEL_DATA(IP7_8_6, AD_NCS_N, SEL_ADI_0), + PINMUX_IPSR_MODSEL_DATA(IP7_11_9, ETH_RXD1, SEL_ETH_0), + PINMUX_IPSR_DATA(IP7_11_9, VI0_G4), + PINMUX_IPSR_MODSEL_DATA(IP7_11_9, MSIOF2_SS1_B, SEL_MSI2_1), + PINMUX_IPSR_MODSEL_DATA(IP7_11_9, SCIF4_RXD_D, SEL_SCIF4_3), + PINMUX_IPSR_DATA(IP7_11_9, AVB_TXD3), + PINMUX_IPSR_MODSEL_DATA(IP7_11_9, ADICHS1, SEL_RAD_0), + PINMUX_IPSR_MODSEL_DATA(IP7_14_12, ETH_LINK, SEL_ETH_0), + PINMUX_IPSR_DATA(IP7_14_12, VI0_G5), + PINMUX_IPSR_MODSEL_DATA(IP7_14_12, MSIOF2_SS2_B, SEL_MSI2_1), + PINMUX_IPSR_MODSEL_DATA(IP7_14_12, SCIF4_TXD_D, SEL_SCIF4_3), + PINMUX_IPSR_DATA(IP7_14_12, AVB_TXD4), + PINMUX_IPSR_MODSEL_DATA(IP7_14_12, ADICHS2, SEL_RAD_0), + PINMUX_IPSR_MODSEL_DATA(IP7_17_15, ETH_REFCLK, SEL_ETH_0), + PINMUX_IPSR_DATA(IP7_17_15, VI0_G6), + PINMUX_IPSR_MODSEL_DATA(IP7_17_15, SCIF2_SCK_C, SEL_SCIF2_2), + PINMUX_IPSR_DATA(IP7_17_15, AVB_TXD5), + PINMUX_IPSR_MODSEL_DATA(IP7_17_15, SSI_SCK5_B, SEL_SSI5_1), + PINMUX_IPSR_MODSEL_DATA(IP7_20_18, ETH_TXD1, SEL_ETH_0), + PINMUX_IPSR_DATA(IP7_20_18, VI0_G7), + PINMUX_IPSR_MODSEL_DATA(IP7_20_18, SCIF2_RXD_C, SEL_SCIF2_2), + PINMUX_IPSR_MODSEL_DATA(IP7_20_18, IIC1_SCL_D, SEL_IIC01_3), + PINMUX_IPSR_DATA(IP7_20_18, AVB_TXD6), + PINMUX_IPSR_MODSEL_DATA(IP7_20_18, SSI_WS5_B, SEL_SSI5_1), + PINMUX_IPSR_MODSEL_DATA(IP7_23_21, ETH_TX_EN, SEL_ETH_0), + PINMUX_IPSR_DATA(IP7_23_21, VI0_R0), + PINMUX_IPSR_MODSEL_DATA(IP7_23_21, SCIF2_TXD_C, SEL_SCIF2_2), + PINMUX_IPSR_MODSEL_DATA(IP7_23_21, IIC1_SDA_D, SEL_IIC01_3), + PINMUX_IPSR_DATA(IP7_23_21, AVB_TXD7), + PINMUX_IPSR_MODSEL_DATA(IP7_23_21, SSI_SDATA5_B, SEL_SSI5_1), + PINMUX_IPSR_MODSEL_DATA(IP7_26_24, ETH_MAGIC, SEL_ETH_0), + PINMUX_IPSR_DATA(IP7_26_24, VI0_R1), + PINMUX_IPSR_MODSEL_DATA(IP7_26_24, SCIF3_SCK_B, SEL_SCIF3_1), + PINMUX_IPSR_DATA(IP7_26_24, AVB_TX_ER), + PINMUX_IPSR_MODSEL_DATA(IP7_26_24, SSI_SCK6_B, SEL_SSI6_1), + PINMUX_IPSR_MODSEL_DATA(IP7_29_27, ETH_TXD0, SEL_ETH_0), + PINMUX_IPSR_DATA(IP7_29_27, VI0_R2), + PINMUX_IPSR_MODSEL_DATA(IP7_29_27, SCIF3_RXD_B, SEL_SCIF3_1), + PINMUX_IPSR_MODSEL_DATA(IP7_29_27, I2C4_SCL_E, SEL_I2C04_4), + PINMUX_IPSR_DATA(IP7_29_27, AVB_GTX_CLK), + PINMUX_IPSR_MODSEL_DATA(IP7_29_27, SSI_WS6_B, SEL_SSI6_1), + PINMUX_IPSR_DATA(IP7_31, DREQ0_N), + PINMUX_IPSR_DATA(IP7_31, SCIFB1_RXD), + + /* IPSR8 */ + PINMUX_IPSR_MODSEL_DATA(IP8_2_0, ETH_MDC, SEL_ETH_0), + PINMUX_IPSR_DATA(IP8_2_0, VI0_R3), + PINMUX_IPSR_MODSEL_DATA(IP8_2_0, SCIF3_TXD_B, SEL_SCIF3_1), + PINMUX_IPSR_MODSEL_DATA(IP8_2_0, I2C4_SDA_E, SEL_I2C04_4), + PINMUX_IPSR_DATA(IP8_2_0, AVB_MDC), + PINMUX_IPSR_MODSEL_DATA(IP8_2_0, SSI_SDATA6_B, SEL_SSI6_1), + PINMUX_IPSR_MODSEL_DATA(IP8_5_3, HSCIF0_HRX, SEL_HSCIF0_0), + PINMUX_IPSR_DATA(IP8_5_3, VI0_R4), + PINMUX_IPSR_MODSEL_DATA(IP8_5_3, I2C1_SCL_C, SEL_I2C01_2), + PINMUX_IPSR_MODSEL_DATA(IP8_5_3, AUDIO_CLKA_B, SEL_ADG_1), + PINMUX_IPSR_DATA(IP8_5_3, AVB_MDIO), + PINMUX_IPSR_MODSEL_DATA(IP8_5_3, SSI_SCK78_B, SEL_SSI7_1), + PINMUX_IPSR_MODSEL_DATA(IP8_8_6, HSCIF0_HTX, SEL_HSCIF0_0), + PINMUX_IPSR_DATA(IP8_8_6, VI0_R5), + PINMUX_IPSR_MODSEL_DATA(IP8_8_6, I2C1_SDA_C, SEL_I2C01_2), + PINMUX_IPSR_MODSEL_DATA(IP8_8_6, AUDIO_CLKB_B, SEL_ADG_1), + PINMUX_IPSR_DATA(IP8_5_3, AVB_LINK), + PINMUX_IPSR_MODSEL_DATA(IP8_8_6, SSI_WS78_B, SEL_SSI7_1), + PINMUX_IPSR_DATA(IP8_11_9, HSCIF0_HCTS_N), + PINMUX_IPSR_DATA(IP8_11_9, VI0_R6), + PINMUX_IPSR_MODSEL_DATA(IP8_11_9, SCIF0_RXD_D, SEL_SCIF0_3), + PINMUX_IPSR_MODSEL_DATA(IP8_11_9, I2C0_SCL_E, SEL_I2C00_4), + PINMUX_IPSR_DATA(IP8_11_9, AVB_MAGIC), + PINMUX_IPSR_MODSEL_DATA(IP8_11_9, SSI_SDATA7_B, SEL_SSI7_1), + PINMUX_IPSR_DATA(IP8_14_12, HSCIF0_HRTS_N), + PINMUX_IPSR_DATA(IP8_14_12, VI0_R7), + PINMUX_IPSR_MODSEL_DATA(IP8_14_12, SCIF0_TXD_D, SEL_SCIF0_3), + PINMUX_IPSR_MODSEL_DATA(IP8_14_12, I2C0_SDA_E, SEL_I2C00_4), + PINMUX_IPSR_DATA(IP8_14_12, AVB_PHY_INT), + PINMUX_IPSR_MODSEL_DATA(IP8_14_12, SSI_SDATA8_B, SEL_SSI8_1), + PINMUX_IPSR_MODSEL_DATA(IP8_16_15, HSCIF0_HSCK, SEL_HSCIF0_0), + PINMUX_IPSR_MODSEL_DATA(IP8_16_15, SCIF_CLK_B, SEL_SCIF0_1), + PINMUX_IPSR_DATA(IP8_16_15, AVB_CRS), + PINMUX_IPSR_MODSEL_DATA(IP8_16_15, AUDIO_CLKC_B, SEL_ADG_1), + PINMUX_IPSR_MODSEL_DATA(IP8_19_17, I2C0_SCL, SEL_I2C00_0), + PINMUX_IPSR_MODSEL_DATA(IP8_19_17, SCIF0_RXD_C, SEL_SCIF0_2), + PINMUX_IPSR_DATA(IP8_19_17, PWM5), + PINMUX_IPSR_MODSEL_DATA(IP8_19_17, TCLK1_B, SEL_TMU_1), + PINMUX_IPSR_DATA(IP8_19_17, AVB_GTXREFCLK), + PINMUX_IPSR_MODSEL_DATA(IP8_19_17, CAN1_RX_D, SEL_CAN1_3), + PINMUX_IPSR_DATA(IP8_19_17, TPUTO0_B), + PINMUX_IPSR_MODSEL_DATA(IP8_22_20, I2C0_SDA, SEL_I2C00_0), + PINMUX_IPSR_MODSEL_DATA(IP8_22_20, SCIF0_TXD_C, SEL_SCIF0_2), + PINMUX_IPSR_DATA(IP8_22_20, TPUTO0), + PINMUX_IPSR_MODSEL_DATA(IP8_22_20, CAN_CLK, SEL_CAN_0), + PINMUX_IPSR_DATA(IP8_22_20, DVC_MUTE), + PINMUX_IPSR_MODSEL_DATA(IP8_22_20, CAN1_TX_D, SEL_CAN1_3), + PINMUX_IPSR_MODSEL_DATA(IP8_25_23, I2C1_SCL, SEL_I2C01_0), + PINMUX_IPSR_MODSEL_DATA(IP8_25_23, SCIF4_RXD, SEL_SCIF4_0), + PINMUX_IPSR_DATA(IP8_25_23, PWM5_B), + PINMUX_IPSR_DATA(IP8_25_23, DU1_DR0), + PINMUX_IPSR_MODSEL_DATA(IP8_25_23, RIF1_SYNC_B, SEL_DR2_1), + PINMUX_IPSR_MODSEL_DATA(IP8_25_23, TS_SDATA_D, SEL_TSIF0_3), + PINMUX_IPSR_DATA(IP8_25_23, TPUTO1_B), + PINMUX_IPSR_MODSEL_DATA(IP8_28_26, I2C1_SDA, SEL_I2C01_0), + PINMUX_IPSR_MODSEL_DATA(IP8_28_26, SCIF4_TXD, SEL_SCIF4_0), + PINMUX_IPSR_DATA(IP8_28_26, IRQ5), + PINMUX_IPSR_DATA(IP8_28_26, DU1_DR1), + PINMUX_IPSR_MODSEL_DATA(IP8_28_26, RIF1_CLK_B, SEL_DR2_1), + PINMUX_IPSR_MODSEL_DATA(IP8_28_26, TS_SCK_D, SEL_TSIF0_3), + PINMUX_IPSR_MODSEL_DATA(IP8_28_26, BPFCLK_C, SEL_DARC_2), + PINMUX_IPSR_DATA(IP8_31_29, MSIOF0_RXD), + PINMUX_IPSR_MODSEL_DATA(IP8_31_29, SCIF5_RXD, SEL_SCIF5_0), + PINMUX_IPSR_MODSEL_DATA(IP8_31_29, I2C2_SCL_C, SEL_I2C02_2), + PINMUX_IPSR_DATA(IP8_31_29, DU1_DR2), + PINMUX_IPSR_MODSEL_DATA(IP8_31_29, RIF1_D0_B, SEL_DR2_1), + PINMUX_IPSR_MODSEL_DATA(IP8_31_29, TS_SDEN_D, SEL_TSIF0_3), + PINMUX_IPSR_MODSEL_DATA(IP8_31_29, FMCLK_C, SEL_DARC_2), + PINMUX_IPSR_MODSEL_DATA(IP8_31_29, RDS_CLK, SEL_RDS_0), + + /* IPSR9 */ + PINMUX_IPSR_DATA(IP9_2_0, MSIOF0_TXD), + PINMUX_IPSR_MODSEL_DATA(IP9_2_0, SCIF5_TXD, SEL_SCIF5_0), + PINMUX_IPSR_MODSEL_DATA(IP9_2_0, I2C2_SDA_C, SEL_I2C02_2), + PINMUX_IPSR_DATA(IP9_2_0, DU1_DR3), + PINMUX_IPSR_MODSEL_DATA(IP9_2_0, RIF1_D1_B, SEL_DR3_1), + PINMUX_IPSR_MODSEL_DATA(IP9_2_0, TS_SPSYNC_D, SEL_TSIF0_3), + PINMUX_IPSR_MODSEL_DATA(IP9_2_0, FMIN_C, SEL_DARC_2), + PINMUX_IPSR_MODSEL_DATA(IP9_2_0, RDS_DATA, SEL_RDS_0), + PINMUX_IPSR_DATA(IP9_5_3, MSIOF0_SCK), + PINMUX_IPSR_DATA(IP9_5_3, IRQ0), + PINMUX_IPSR_MODSEL_DATA(IP9_5_3, TS_SDATA, SEL_TSIF0_0), + PINMUX_IPSR_DATA(IP9_5_3, DU1_DR4), + PINMUX_IPSR_MODSEL_DATA(IP9_5_3, RIF1_SYNC, SEL_DR2_0), + PINMUX_IPSR_DATA(IP9_5_3, TPUTO1_C), + PINMUX_IPSR_DATA(IP9_8_6, MSIOF0_SYNC), + PINMUX_IPSR_DATA(IP9_8_6, PWM1), + PINMUX_IPSR_MODSEL_DATA(IP9_8_6, TS_SCK, SEL_TSIF0_0), + PINMUX_IPSR_DATA(IP9_8_6, DU1_DR5), + PINMUX_IPSR_MODSEL_DATA(IP9_8_6, RIF1_CLK, SEL_DR2_0), + PINMUX_IPSR_MODSEL_DATA(IP9_8_6, BPFCLK_B, SEL_DARC_1), + PINMUX_IPSR_DATA(IP9_11_9, MSIOF0_SS1), + PINMUX_IPSR_MODSEL_DATA(IP9_11_9, SCIFA0_RXD, SEL_SCIFA0_0), + PINMUX_IPSR_MODSEL_DATA(IP9_11_9, TS_SDEN, SEL_TSIF0_0), + PINMUX_IPSR_DATA(IP9_11_9, DU1_DR6), + PINMUX_IPSR_MODSEL_DATA(IP9_11_9, RIF1_D0, SEL_DR2_0), + PINMUX_IPSR_MODSEL_DATA(IP9_11_9, FMCLK_B, SEL_DARC_1), + PINMUX_IPSR_MODSEL_DATA(IP9_11_9, RDS_CLK_B, SEL_RDS_1), + PINMUX_IPSR_DATA(IP9_14_12, MSIOF0_SS2), + PINMUX_IPSR_MODSEL_DATA(IP9_14_12, SCIFA0_TXD, SEL_SCIFA0_0), + PINMUX_IPSR_MODSEL_DATA(IP9_14_12, TS_SPSYNC, SEL_TSIF0_0), + PINMUX_IPSR_DATA(IP9_14_12, DU1_DR7), + PINMUX_IPSR_MODSEL_DATA(IP9_14_12, RIF1_D1, SEL_DR3_0), + PINMUX_IPSR_MODSEL_DATA(IP9_14_12, FMIN_B, SEL_DARC_1), + PINMUX_IPSR_MODSEL_DATA(IP9_14_12, RDS_DATA_B, SEL_RDS_1), + PINMUX_IPSR_MODSEL_DATA(IP9_16_15, HSCIF1_HRX, SEL_HSCIF1_0), + PINMUX_IPSR_MODSEL_DATA(IP9_16_15, I2C4_SCL, SEL_I2C04_0), + PINMUX_IPSR_DATA(IP9_16_15, PWM6), + PINMUX_IPSR_DATA(IP9_16_15, DU1_DG0), + PINMUX_IPSR_MODSEL_DATA(IP9_18_17, HSCIF1_HTX, SEL_HSCIF1_0), + PINMUX_IPSR_MODSEL_DATA(IP9_18_17, I2C4_SDA, SEL_I2C04_0), + PINMUX_IPSR_DATA(IP9_18_17, TPUTO1), + PINMUX_IPSR_DATA(IP9_18_17, DU1_DG1), + PINMUX_IPSR_DATA(IP9_21_19, HSCIF1_HSCK), + PINMUX_IPSR_DATA(IP9_21_19, PWM2), + PINMUX_IPSR_MODSEL_DATA(IP9_21_19, IETX, SEL_IEB_0), + PINMUX_IPSR_DATA(IP9_21_19, DU1_DG2), + PINMUX_IPSR_MODSEL_DATA(IP9_21_19, REMOCON_B, SEL_RCN_1), + PINMUX_IPSR_MODSEL_DATA(IP9_21_19, SPEEDIN_B, SEL_RSP_1), + PINMUX_IPSR_MODSEL_DATA(IP9_21_19, VSP_B, SEL_SPDM_1), + PINMUX_IPSR_MODSEL_DATA(IP9_24_22, HSCIF1_HCTS_N, SEL_HSCIF1_0), + PINMUX_IPSR_MODSEL_DATA(IP9_24_22, SCIFA4_RXD, SEL_SCIFA4_0), + PINMUX_IPSR_MODSEL_DATA(IP9_24_22, IECLK, SEL_IEB_0), + PINMUX_IPSR_DATA(IP9_24_22, DU1_DG3), + PINMUX_IPSR_MODSEL_DATA(IP9_24_22, SSI_SCK1_B, SEL_SSI1_1), + PINMUX_IPSR_DATA(IP9_24_22, CAN_DEBUG_HW_TRIGGER), + PINMUX_IPSR_DATA(IP9_24_22, CC50_STATE32), + PINMUX_IPSR_MODSEL_DATA(IP9_27_25, HSCIF1_HRTS_N, SEL_HSCIF1_0), + PINMUX_IPSR_MODSEL_DATA(IP9_27_25, SCIFA4_TXD, SEL_SCIFA4_0), + PINMUX_IPSR_MODSEL_DATA(IP9_27_25, IERX, SEL_IEB_0), + PINMUX_IPSR_DATA(IP9_27_25, DU1_DG4), + PINMUX_IPSR_MODSEL_DATA(IP9_27_25, SSI_WS1_B, SEL_SSI1_1), + PINMUX_IPSR_DATA(IP9_27_25, CAN_STEP0), + PINMUX_IPSR_DATA(IP9_27_25, CC50_STATE33), + PINMUX_IPSR_MODSEL_DATA(IP9_30_28, SCIF1_SCK, SEL_SCIF1_0), + PINMUX_IPSR_DATA(IP9_30_28, PWM3), + PINMUX_IPSR_MODSEL_DATA(IP9_30_28, TCLK2, SEL_TMU_0), + PINMUX_IPSR_DATA(IP9_30_28, DU1_DG5), + PINMUX_IPSR_MODSEL_DATA(IP9_30_28, SSI_SDATA1_B, SEL_SSI1_1), + PINMUX_IPSR_DATA(IP9_30_28, CAN_TXCLK), + PINMUX_IPSR_DATA(IP9_30_28, CC50_STATE34), + + /* IPSR10 */ + PINMUX_IPSR_MODSEL_DATA(IP10_2_0, SCIF1_RXD, SEL_SCIF1_0), + PINMUX_IPSR_MODSEL_DATA(IP10_2_0, IIC0_SCL, SEL_IIC00_0), + PINMUX_IPSR_DATA(IP10_2_0, DU1_DG6), + PINMUX_IPSR_MODSEL_DATA(IP10_2_0, SSI_SCK2_B, SEL_SSI2_1), + PINMUX_IPSR_DATA(IP10_2_0, CAN_DEBUGOUT0), + PINMUX_IPSR_DATA(IP10_2_0, CC50_STATE35), + PINMUX_IPSR_MODSEL_DATA(IP10_5_3, SCIF1_TXD, SEL_SCIF1_0), + PINMUX_IPSR_MODSEL_DATA(IP10_5_3, IIC0_SDA, SEL_IIC00_0), + PINMUX_IPSR_DATA(IP10_5_3, DU1_DG7), + PINMUX_IPSR_MODSEL_DATA(IP10_5_3, SSI_WS2_B, SEL_SSI2_1), + PINMUX_IPSR_DATA(IP10_5_3, CAN_DEBUGOUT1), + PINMUX_IPSR_DATA(IP10_5_3, CC50_STATE36), + PINMUX_IPSR_MODSEL_DATA(IP10_8_6, SCIF2_RXD, SEL_SCIF2_0), + PINMUX_IPSR_MODSEL_DATA(IP10_8_6, IIC1_SCL, SEL_IIC01_0), + PINMUX_IPSR_DATA(IP10_8_6, DU1_DB0), + PINMUX_IPSR_MODSEL_DATA(IP10_8_6, SSI_SDATA2_B, SEL_SSI2_1), + PINMUX_IPSR_DATA(IP10_8_6, USB0_EXTLP), + PINMUX_IPSR_DATA(IP10_8_6, CAN_DEBUGOUT2), + PINMUX_IPSR_DATA(IP10_8_6, CC50_STATE37), + PINMUX_IPSR_MODSEL_DATA(IP10_11_9, SCIF2_TXD, SEL_SCIF2_0), + PINMUX_IPSR_MODSEL_DATA(IP10_11_9, IIC1_SDA, SEL_IIC01_0), + PINMUX_IPSR_DATA(IP10_11_9, DU1_DB1), + PINMUX_IPSR_MODSEL_DATA(IP10_11_9, SSI_SCK9_B, SEL_SSI9_1), + PINMUX_IPSR_DATA(IP10_11_9, USB0_OVC1), + PINMUX_IPSR_DATA(IP10_11_9, CAN_DEBUGOUT3), + PINMUX_IPSR_DATA(IP10_11_9, CC50_STATE38), + PINMUX_IPSR_MODSEL_DATA(IP10_14_12, SCIF2_SCK, SEL_SCIF2_0), + PINMUX_IPSR_DATA(IP10_14_12, IRQ1), + PINMUX_IPSR_DATA(IP10_14_12, DU1_DB2), + PINMUX_IPSR_MODSEL_DATA(IP10_14_12, SSI_WS9_B, SEL_SSI9_1), + PINMUX_IPSR_DATA(IP10_14_12, USB0_IDIN), + PINMUX_IPSR_DATA(IP10_14_12, CAN_DEBUGOUT4), + PINMUX_IPSR_DATA(IP10_14_12, CC50_STATE39), + PINMUX_IPSR_MODSEL_DATA(IP10_17_15, SCIF3_SCK, SEL_SCIF3_0), + PINMUX_IPSR_DATA(IP10_17_15, IRQ2), + PINMUX_IPSR_MODSEL_DATA(IP10_17_15, BPFCLK_D, SEL_DARC_3), + PINMUX_IPSR_DATA(IP10_17_15, DU1_DB3), + PINMUX_IPSR_MODSEL_DATA(IP10_17_15, SSI_SDATA9_B, SEL_SSI9_1), + PINMUX_IPSR_DATA(IP10_17_15, TANS2), + PINMUX_IPSR_DATA(IP10_17_15, CAN_DEBUGOUT5), + PINMUX_IPSR_DATA(IP10_17_15, CC50_OSCOUT), + PINMUX_IPSR_MODSEL_DATA(IP10_20_18, SCIF3_RXD, SEL_SCIF3_0), + PINMUX_IPSR_MODSEL_DATA(IP10_20_18, I2C1_SCL_E, SEL_I2C01_4), + PINMUX_IPSR_MODSEL_DATA(IP10_20_18, FMCLK_D, SEL_DARC_3), + PINMUX_IPSR_DATA(IP10_20_18, DU1_DB4), + PINMUX_IPSR_MODSEL_DATA(IP10_20_18, AUDIO_CLKA_C, SEL_ADG_2), + PINMUX_IPSR_MODSEL_DATA(IP10_20_18, SSI_SCK4_B, SEL_SSI4_1), + PINMUX_IPSR_DATA(IP10_20_18, CAN_DEBUGOUT6), + PINMUX_IPSR_MODSEL_DATA(IP10_20_18, RDS_CLK_C, SEL_RDS_2), + PINMUX_IPSR_MODSEL_DATA(IP10_23_21, SCIF3_TXD, SEL_SCIF3_0), + PINMUX_IPSR_MODSEL_DATA(IP10_23_21, I2C1_SDA_E, SEL_I2C01_4), + PINMUX_IPSR_MODSEL_DATA(IP10_23_21, FMIN_D, SEL_DARC_3), + PINMUX_IPSR_DATA(IP10_23_21, DU1_DB5), + PINMUX_IPSR_MODSEL_DATA(IP10_23_21, AUDIO_CLKB_C, SEL_ADG_2), + PINMUX_IPSR_MODSEL_DATA(IP10_23_21, SSI_WS4_B, SEL_SSI4_1), + PINMUX_IPSR_DATA(IP10_23_21, CAN_DEBUGOUT7), + PINMUX_IPSR_MODSEL_DATA(IP10_23_21, RDS_DATA_C, SEL_RDS_2), + PINMUX_IPSR_MODSEL_DATA(IP10_26_24, I2C2_SCL, SEL_I2C02_0), + PINMUX_IPSR_MODSEL_DATA(IP10_26_24, SCIFA5_RXD, SEL_SCIFA5_0), + PINMUX_IPSR_DATA(IP10_26_24, DU1_DB6), + PINMUX_IPSR_MODSEL_DATA(IP10_26_24, AUDIO_CLKC_C, SEL_ADG_2), + PINMUX_IPSR_MODSEL_DATA(IP10_26_24, SSI_SDATA4_B, SEL_SSI4_1), + PINMUX_IPSR_DATA(IP10_26_24, CAN_DEBUGOUT8), + PINMUX_IPSR_MODSEL_DATA(IP10_29_27, I2C2_SDA, SEL_I2C02_0), + PINMUX_IPSR_MODSEL_DATA(IP10_29_27, SCIFA5_TXD, SEL_SCIFA5_0), + PINMUX_IPSR_DATA(IP10_29_27, DU1_DB7), + PINMUX_IPSR_MODSEL_DATA(IP10_29_27, AUDIO_CLKOUT_C, SEL_ADG_2), + PINMUX_IPSR_DATA(IP10_29_27, CAN_DEBUGOUT9), + PINMUX_IPSR_MODSEL_DATA(IP10_31_30, SSI_SCK5, SEL_SSI5_0), + PINMUX_IPSR_MODSEL_DATA(IP10_31_30, SCIFA3_SCK, SEL_SCIFA3_0), + PINMUX_IPSR_DATA(IP10_31_30, DU1_DOTCLKIN), + PINMUX_IPSR_DATA(IP10_31_30, CAN_DEBUGOUT10), + + /* IPSR11 */ + PINMUX_IPSR_MODSEL_DATA(IP11_2_0, SSI_WS5, SEL_SSI5_0), + PINMUX_IPSR_MODSEL_DATA(IP11_2_0, SCIFA3_RXD, SEL_SCIFA3_0), + PINMUX_IPSR_MODSEL_DATA(IP11_2_0, I2C3_SCL_C, SEL_I2C03_2), + PINMUX_IPSR_DATA(IP11_2_0, DU1_DOTCLKOUT0), + PINMUX_IPSR_DATA(IP11_2_0, CAN_DEBUGOUT11), + PINMUX_IPSR_MODSEL_DATA(IP11_5_3, SSI_SDATA5, SEL_SSI5_0), + PINMUX_IPSR_MODSEL_DATA(IP11_5_3, SCIFA3_TXD, SEL_SCIFA3_0), + PINMUX_IPSR_MODSEL_DATA(IP11_5_3, I2C3_SDA_C, SEL_I2C03_2), + PINMUX_IPSR_DATA(IP11_5_3, DU1_DOTCLKOUT1), + PINMUX_IPSR_DATA(IP11_5_3, CAN_DEBUGOUT12), + PINMUX_IPSR_MODSEL_DATA(IP11_7_6, SSI_SCK6, SEL_SSI6_0), + PINMUX_IPSR_MODSEL_DATA(IP11_7_6, SCIFA1_SCK_B, SEL_SCIFA1_1), + PINMUX_IPSR_DATA(IP11_7_6, DU1_EXHSYNC_DU1_HSYNC), + PINMUX_IPSR_DATA(IP11_7_6, CAN_DEBUGOUT13), + PINMUX_IPSR_MODSEL_DATA(IP11_10_8, SSI_WS6, SEL_SSI6_0), + PINMUX_IPSR_MODSEL_DATA(IP11_10_8, SCIFA1_RXD_B, SEL_SCIFA1_1), + PINMUX_IPSR_MODSEL_DATA(IP11_10_8, I2C4_SCL_C, SEL_I2C04_2), + PINMUX_IPSR_DATA(IP11_10_8, DU1_EXVSYNC_DU1_VSYNC), + PINMUX_IPSR_DATA(IP11_10_8, CAN_DEBUGOUT14), + PINMUX_IPSR_MODSEL_DATA(IP11_13_11, SSI_SDATA6, SEL_SSI6_0), + PINMUX_IPSR_MODSEL_DATA(IP11_13_11, SCIFA1_TXD_B, SEL_SCIFA1_1), + PINMUX_IPSR_MODSEL_DATA(IP11_13_11, I2C4_SDA_C, SEL_I2C04_2), + PINMUX_IPSR_DATA(IP11_13_11, DU1_EXODDF_DU1_ODDF_DISP_CDE), + PINMUX_IPSR_DATA(IP11_13_11, CAN_DEBUGOUT15), + PINMUX_IPSR_MODSEL_DATA(IP11_15_14, SSI_SCK78, SEL_SSI7_0), + PINMUX_IPSR_MODSEL_DATA(IP11_15_14, SCIFA2_SCK_B, SEL_SCIFA2_1), + PINMUX_IPSR_MODSEL_DATA(IP11_15_14, IIC0_SDA_C, SEL_IIC00_2), + PINMUX_IPSR_DATA(IP11_15_14, DU1_DISP), + PINMUX_IPSR_MODSEL_DATA(IP11_17_16, SSI_WS78, SEL_SSI7_0), + PINMUX_IPSR_MODSEL_DATA(IP11_17_16, SCIFA2_RXD_B, SEL_SCIFA2_1), + PINMUX_IPSR_MODSEL_DATA(IP11_17_16, IIC0_SCL_C, SEL_IIC00_2), + PINMUX_IPSR_DATA(IP11_17_16, DU1_CDE), + PINMUX_IPSR_MODSEL_DATA(IP11_20_18, SSI_SDATA7, SEL_SSI7_0), + PINMUX_IPSR_MODSEL_DATA(IP11_20_18, SCIFA2_TXD_B, SEL_SCIFA2_1), + PINMUX_IPSR_DATA(IP11_20_18, IRQ8), + PINMUX_IPSR_MODSEL_DATA(IP11_20_18, AUDIO_CLKA_D, SEL_ADG_3), + PINMUX_IPSR_MODSEL_DATA(IP11_20_18, CAN_CLK_D, SEL_CAN_3), + PINMUX_IPSR_DATA(IP11_20_18, PCMOE_N), + PINMUX_IPSR_DATA(IP11_23_21, SSI_SCK0129), + PINMUX_IPSR_MODSEL_DATA(IP11_23_21, MSIOF1_RXD_B, SEL_MSI1_1), + PINMUX_IPSR_MODSEL_DATA(IP11_23_21, SCIF5_RXD_D, SEL_SCIF5_3), + PINMUX_IPSR_MODSEL_DATA(IP11_23_21, ADIDATA_B, SEL_RAD_1), + PINMUX_IPSR_MODSEL_DATA(IP11_23_21, AD_DI_B, SEL_ADI_1), + PINMUX_IPSR_DATA(IP11_23_21, PCMWE_N), + PINMUX_IPSR_DATA(IP11_26_24, SSI_WS0129), + PINMUX_IPSR_MODSEL_DATA(IP11_26_24, MSIOF1_TXD_B, SEL_MSI1_1), + PINMUX_IPSR_MODSEL_DATA(IP11_26_24, SCIF5_TXD_D, SEL_SCIF5_3), + PINMUX_IPSR_MODSEL_DATA(IP11_26_24, ADICS_SAMP_B, SEL_RAD_1), + PINMUX_IPSR_MODSEL_DATA(IP11_26_24, AD_DO_B, SEL_ADI_1), + PINMUX_IPSR_DATA(IP11_29_27, SSI_SDATA0), + PINMUX_IPSR_MODSEL_DATA(IP11_29_27, MSIOF1_SCK_B, SEL_MSI1_1), + PINMUX_IPSR_DATA(IP11_29_27, PWM0_B), + PINMUX_IPSR_MODSEL_DATA(IP11_29_27, ADICLK_B, SEL_RAD_1), + PINMUX_IPSR_MODSEL_DATA(IP11_29_27, AD_CLK_B, SEL_ADI_1), + + /* IPSR12 */ + PINMUX_IPSR_DATA(IP12_2_0, SSI_SCK34), + PINMUX_IPSR_MODSEL_DATA(IP12_2_0, MSIOF1_SYNC_B, SEL_MSI1_1), + PINMUX_IPSR_MODSEL_DATA(IP12_2_0, SCIFA1_SCK_C, SEL_SCIFA1_2), + PINMUX_IPSR_MODSEL_DATA(IP12_2_0, ADICHS0_B, SEL_RAD_1), + PINMUX_IPSR_MODSEL_DATA(IP12_2_0, AD_NCS_N_B, SEL_ADI_1), + PINMUX_IPSR_MODSEL_DATA(IP12_2_0, DREQ1_N_B, SEL_LBS_1), + PINMUX_IPSR_DATA(IP12_5_3, SSI_WS34), + PINMUX_IPSR_MODSEL_DATA(IP12_5_3, MSIOF1_SS1_B, SEL_MSI1_1), + PINMUX_IPSR_MODSEL_DATA(IP12_5_3, SCIFA1_RXD_C, SEL_SCIFA1_2), + PINMUX_IPSR_MODSEL_DATA(IP12_5_3, ADICHS1_B, SEL_RAD_1), + PINMUX_IPSR_MODSEL_DATA(IP12_5_3, CAN1_RX_C, SEL_CAN1_2), + PINMUX_IPSR_MODSEL_DATA(IP12_5_3, DACK1_B, SEL_LBS_1), + PINMUX_IPSR_DATA(IP12_8_6, SSI_SDATA3), + PINMUX_IPSR_MODSEL_DATA(IP12_8_6, MSIOF1_SS2_B, SEL_MSI1_1), + PINMUX_IPSR_MODSEL_DATA(IP12_8_6, SCIFA1_TXD_C, SEL_SCIFA1_2), + PINMUX_IPSR_MODSEL_DATA(IP12_8_6, ADICHS2_B, SEL_RAD_1), + PINMUX_IPSR_MODSEL_DATA(IP12_8_6, CAN1_TX_C, SEL_CAN1_2), + PINMUX_IPSR_DATA(IP12_8_6, DREQ2_N), + PINMUX_IPSR_MODSEL_DATA(IP12_10_9, SSI_SCK4, SEL_SSI4_0), + PINMUX_IPSR_DATA(IP12_10_9, MLB_CLK), + PINMUX_IPSR_MODSEL_DATA(IP12_10_9, IETX_B, SEL_IEB_1), + PINMUX_IPSR_DATA(IP12_10_9, IRD_TX), + PINMUX_IPSR_MODSEL_DATA(IP12_12_11, SSI_WS4, SEL_SSI4_0), + PINMUX_IPSR_DATA(IP12_12_11, MLB_SIG), + PINMUX_IPSR_MODSEL_DATA(IP12_12_11, IECLK_B, SEL_IEB_1), + PINMUX_IPSR_DATA(IP12_12_11, IRD_RX), + PINMUX_IPSR_MODSEL_DATA(IP12_14_13, SSI_SDATA4, SEL_SSI4_0), + PINMUX_IPSR_DATA(IP12_14_13, MLB_DAT), + PINMUX_IPSR_MODSEL_DATA(IP12_14_13, IERX_B, SEL_IEB_1), + PINMUX_IPSR_DATA(IP12_14_13, IRD_SCK), + PINMUX_IPSR_MODSEL_DATA(IP12_17_15, SSI_SDATA8, SEL_SSI8_0), + PINMUX_IPSR_MODSEL_DATA(IP12_17_15, SCIF1_SCK_B, SEL_SCIF1_1), + PINMUX_IPSR_DATA(IP12_17_15, PWM1_B), + PINMUX_IPSR_DATA(IP12_17_15, IRQ9), + PINMUX_IPSR_MODSEL_DATA(IP12_17_15, REMOCON, SEL_RCN_0), + PINMUX_IPSR_DATA(IP12_17_15, DACK2), + PINMUX_IPSR_MODSEL_DATA(IP12_17_15, ETH_MDIO_B, SEL_ETH_1), + PINMUX_IPSR_MODSEL_DATA(IP12_20_18, SSI_SCK1, SEL_SSI1_0), + PINMUX_IPSR_MODSEL_DATA(IP12_20_18, SCIF1_RXD_B, SEL_SCIF1_1), + PINMUX_IPSR_MODSEL_DATA(IP12_20_18, IIC1_SCL_C, SEL_IIC01_2), + PINMUX_IPSR_DATA(IP12_20_18, VI1_CLK), + PINMUX_IPSR_MODSEL_DATA(IP12_20_18, CAN0_RX_D, SEL_CAN0_3), + PINMUX_IPSR_MODSEL_DATA(IP12_20_18, AVB_AVTP_CAPTURE, SEL_AVB_0), + PINMUX_IPSR_MODSEL_DATA(IP12_20_18, ETH_CRS_DV_B, SEL_ETH_1), + PINMUX_IPSR_MODSEL_DATA(IP12_23_21, SSI_WS1, SEL_SSI1_0), + PINMUX_IPSR_MODSEL_DATA(IP12_23_21, SCIF1_TXD_B, SEL_SCIF1_1), + PINMUX_IPSR_MODSEL_DATA(IP12_23_21, IIC1_SDA_C, SEL_IIC01_2), + PINMUX_IPSR_DATA(IP12_23_21, VI1_DATA0), + PINMUX_IPSR_MODSEL_DATA(IP12_23_21, CAN0_TX_D, SEL_CAN0_3), + PINMUX_IPSR_MODSEL_DATA(IP12_23_21, AVB_AVTP_MATCH, SEL_AVB_0), + PINMUX_IPSR_MODSEL_DATA(IP12_23_21, ETH_RX_ER_B, SEL_ETH_1), + PINMUX_IPSR_MODSEL_DATA(IP12_26_24, SSI_SDATA1, SEL_SSI1_0), + PINMUX_IPSR_MODSEL_DATA(IP12_26_24, HSCIF1_HRX_B, SEL_HSCIF1_1), + PINMUX_IPSR_DATA(IP12_26_24, VI1_DATA1), + PINMUX_IPSR_MODSEL_DATA(IP12_26_24, SDATA, SEL_FSN_0), + PINMUX_IPSR_DATA(IP12_26_24, ATAG0_N), + PINMUX_IPSR_MODSEL_DATA(IP12_26_24, ETH_RXD0_B, SEL_ETH_1), + PINMUX_IPSR_MODSEL_DATA(IP12_29_27, SSI_SCK2, SEL_SSI2_0), + PINMUX_IPSR_MODSEL_DATA(IP12_29_27, HSCIF1_HTX_B, SEL_HSCIF1_1), + PINMUX_IPSR_DATA(IP12_29_27, VI1_DATA2), + PINMUX_IPSR_MODSEL_DATA(IP12_29_27, MDATA, SEL_FSN_0), + PINMUX_IPSR_DATA(IP12_29_27, ATAWR0_N), + PINMUX_IPSR_MODSEL_DATA(IP12_29_27, ETH_RXD1_B, SEL_ETH_1), + + /* IPSR13 */ + PINMUX_IPSR_MODSEL_DATA(IP13_2_0, SSI_WS2, SEL_SSI2_0), + PINMUX_IPSR_MODSEL_DATA(IP13_2_0, HSCIF1_HCTS_N_B, SEL_HSCIF1_1), + PINMUX_IPSR_MODSEL_DATA(IP13_2_0, SCIFA0_RXD_D, SEL_SCIFA0_3), + PINMUX_IPSR_DATA(IP13_2_0, VI1_DATA3), + PINMUX_IPSR_MODSEL_DATA(IP13_2_0, SCKZ, SEL_FSN_0), + PINMUX_IPSR_DATA(IP13_2_0, ATACS00_N), + PINMUX_IPSR_MODSEL_DATA(IP13_2_0, ETH_LINK_B, SEL_ETH_1), + PINMUX_IPSR_MODSEL_DATA(IP13_5_3, SSI_SDATA2, SEL_SSI2_0), + PINMUX_IPSR_MODSEL_DATA(IP13_5_3, HSCIF1_HRTS_N_B, SEL_HSCIF1_1), + PINMUX_IPSR_MODSEL_DATA(IP13_5_3, SCIFA0_TXD_D, SEL_SCIFA0_3), + PINMUX_IPSR_DATA(IP13_5_3, VI1_DATA4), + PINMUX_IPSR_MODSEL_DATA(IP13_5_3, STM_N, SEL_FSN_0), + PINMUX_IPSR_DATA(IP13_5_3, ATACS10_N), + PINMUX_IPSR_MODSEL_DATA(IP13_5_3, ETH_REFCLK_B, SEL_ETH_1), + PINMUX_IPSR_MODSEL_DATA(IP13_8_6, SSI_SCK9, SEL_SSI9_0), + PINMUX_IPSR_MODSEL_DATA(IP13_8_6, SCIF2_SCK_B, SEL_SCIF2_1), + PINMUX_IPSR_DATA(IP13_8_6, PWM2_B), + PINMUX_IPSR_DATA(IP13_8_6, VI1_DATA5), + PINMUX_IPSR_MODSEL_DATA(IP13_8_6, MTS_N, SEL_FSN_0), + PINMUX_IPSR_DATA(IP13_8_6, EX_WAIT1), + PINMUX_IPSR_MODSEL_DATA(IP13_8_6, ETH_TXD1_B, SEL_ETH_1), + PINMUX_IPSR_MODSEL_DATA(IP13_11_9, SSI_WS9, SEL_SSI9_0), + PINMUX_IPSR_MODSEL_DATA(IP13_11_9, SCIF2_RXD_B, SEL_SCIF2_1), + PINMUX_IPSR_MODSEL_DATA(IP13_11_9, I2C3_SCL_E, SEL_I2C03_4), + PINMUX_IPSR_DATA(IP13_11_9, VI1_DATA6), + PINMUX_IPSR_DATA(IP13_11_9, ATARD0_N), + PINMUX_IPSR_MODSEL_DATA(IP13_11_9, ETH_TX_EN_B, SEL_ETH_1), + PINMUX_IPSR_MODSEL_DATA(IP13_14_12, SSI_SDATA9, SEL_SSI9_0), + PINMUX_IPSR_MODSEL_DATA(IP13_14_12, SCIF2_TXD_B, SEL_SCIF2_1), + PINMUX_IPSR_MODSEL_DATA(IP13_14_12, I2C3_SDA_E, SEL_I2C03_4), + PINMUX_IPSR_DATA(IP13_14_12, VI1_DATA7), + PINMUX_IPSR_DATA(IP13_14_12, ATADIR0_N), + PINMUX_IPSR_MODSEL_DATA(IP13_14_12, ETH_MAGIC_B, SEL_ETH_1), + PINMUX_IPSR_MODSEL_DATA(IP13_17_15, AUDIO_CLKA, SEL_ADG_0), + PINMUX_IPSR_MODSEL_DATA(IP13_17_15, I2C0_SCL_B, SEL_I2C00_1), + PINMUX_IPSR_MODSEL_DATA(IP13_17_15, SCIFA4_RXD_D, SEL_SCIFA4_3), + PINMUX_IPSR_DATA(IP13_17_15, VI1_CLKENB), + PINMUX_IPSR_MODSEL_DATA(IP13_17_15, TS_SDATA_C, SEL_TSIF0_2), + PINMUX_IPSR_MODSEL_DATA(IP13_17_15, RIF0_SYNC_B, SEL_DR0_1), + PINMUX_IPSR_MODSEL_DATA(IP13_17_15, ETH_TXD0_B, SEL_ETH_1), + PINMUX_IPSR_MODSEL_DATA(IP13_20_18, AUDIO_CLKB, SEL_ADG_0), + PINMUX_IPSR_MODSEL_DATA(IP13_20_18, I2C0_SDA_B, SEL_I2C00_1), + PINMUX_IPSR_MODSEL_DATA(IP13_20_18, SCIFA4_TXD_D, SEL_SCIFA4_3), + PINMUX_IPSR_DATA(IP13_20_18, VI1_FIELD), + PINMUX_IPSR_MODSEL_DATA(IP13_20_18, TS_SCK_C, SEL_TSIF0_2), + PINMUX_IPSR_MODSEL_DATA(IP13_20_18, RIF0_CLK_B, SEL_DR0_1), + PINMUX_IPSR_MODSEL_DATA(IP13_20_18, BPFCLK_E, SEL_DARC_4), + PINMUX_IPSR_MODSEL_DATA(IP13_20_18, ETH_MDC_B, SEL_ETH_1), + PINMUX_IPSR_MODSEL_DATA(IP13_23_21, AUDIO_CLKC, SEL_ADG_0), + PINMUX_IPSR_MODSEL_DATA(IP13_23_21, I2C4_SCL_B, SEL_I2C04_1), + PINMUX_IPSR_MODSEL_DATA(IP13_23_21, SCIFA5_RXD_D, SEL_SCIFA5_3), + PINMUX_IPSR_DATA(IP13_23_21, VI1_HSYNC_N), + PINMUX_IPSR_MODSEL_DATA(IP13_23_21, TS_SDEN_C, SEL_TSIF0_2), + PINMUX_IPSR_MODSEL_DATA(IP13_23_21, RIF0_D0_B, SEL_DR0_1), + PINMUX_IPSR_MODSEL_DATA(IP13_23_21, FMCLK_E, SEL_DARC_4), + PINMUX_IPSR_MODSEL_DATA(IP13_23_21, RDS_CLK_D, SEL_RDS_3), + PINMUX_IPSR_MODSEL_DATA(IP13_26_24, AUDIO_CLKOUT, SEL_ADG_0), + PINMUX_IPSR_MODSEL_DATA(IP13_26_24, I2C4_SDA_B, SEL_I2C04_1), + PINMUX_IPSR_MODSEL_DATA(IP13_26_24, SCIFA5_TXD_D, SEL_SCIFA5_3), + PINMUX_IPSR_DATA(IP13_26_24, VI1_VSYNC_N), + PINMUX_IPSR_MODSEL_DATA(IP13_26_24, TS_SPSYNC_C, SEL_TSIF0_2), + PINMUX_IPSR_MODSEL_DATA(IP13_26_24, RIF0_D1_B, SEL_DR1_1), + PINMUX_IPSR_MODSEL_DATA(IP13_26_24, FMIN_E, SEL_DARC_4), + PINMUX_IPSR_MODSEL_DATA(IP13_26_24, RDS_DATA_D, SEL_RDS_3), +}; + +static const struct sh_pfc_pin pinmux_pins[] = { + PINMUX_GPIO_GP_ALL(), +}; + +/* - ETH -------------------------------------------------------------------- */ +static const unsigned int eth_link_pins[] = { + /* LINK */ + RCAR_GP_PIN(3, 18), +}; +static const unsigned int eth_link_mux[] = { + ETH_LINK_MARK, +}; +static const unsigned int eth_magic_pins[] = { + /* MAGIC */ + RCAR_GP_PIN(3, 22), +}; +static const unsigned int eth_magic_mux[] = { + ETH_MAGIC_MARK, +}; +static const unsigned int eth_mdio_pins[] = { + /* MDC, MDIO */ + RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 13), +}; +static const unsigned int eth_mdio_mux[] = { + ETH_MDC_MARK, ETH_MDIO_MARK, +}; +static const unsigned int eth_rmii_pins[] = { + /* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK */ + RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 15), + RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 20), + RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 19), +}; +static const unsigned int eth_rmii_mux[] = { + ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_RX_ER_MARK, ETH_CRS_DV_MARK, + ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK, ETH_REFCLK_MARK, +}; +static const unsigned int eth_link_b_pins[] = { + /* LINK */ + RCAR_GP_PIN(5, 15), +}; +static const unsigned int eth_link_b_mux[] = { + ETH_LINK_B_MARK, +}; +static const unsigned int eth_magic_b_pins[] = { + /* MAGIC */ + RCAR_GP_PIN(5, 19), +}; +static const unsigned int eth_magic_b_mux[] = { + ETH_MAGIC_B_MARK, +}; +static const unsigned int eth_mdio_b_pins[] = { + /* MDC, MDIO */ + RCAR_GP_PIN(5, 21), RCAR_GP_PIN(5, 10), +}; +static const unsigned int eth_mdio_b_mux[] = { + ETH_MDC_B_MARK, ETH_MDIO_B_MARK, +}; +static const unsigned int eth_rmii_b_pins[] = { + /* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK */ + RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 12), + RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 17), + RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 16), +}; +static const unsigned int eth_rmii_b_mux[] = { + ETH_RXD0_B_MARK, ETH_RXD1_B_MARK, ETH_RX_ER_B_MARK, ETH_CRS_DV_B_MARK, + ETH_TXD0_B_MARK, ETH_TXD1_B_MARK, ETH_TX_EN_B_MARK, ETH_REFCLK_B_MARK, +}; +/* - HSCIF0 ----------------------------------------------------------------- */ +static const unsigned int hscif0_data_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26), +}; +static const unsigned int hscif0_data_mux[] = { + HSCIF0_HRX_MARK, HSCIF0_HTX_MARK, +}; +static const unsigned int hscif0_clk_pins[] = { + /* SCK */ + RCAR_GP_PIN(3, 29), +}; +static const unsigned int hscif0_clk_mux[] = { + HSCIF0_HSCK_MARK, +}; +static const unsigned int hscif0_ctrl_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 27), +}; +static const unsigned int hscif0_ctrl_mux[] = { + HSCIF0_HRTS_N_MARK, HSCIF0_HCTS_N_MARK, +}; +static const unsigned int hscif0_data_b_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(0, 30), RCAR_GP_PIN(0, 31), +}; +static const unsigned int hscif0_data_b_mux[] = { + HSCIF0_HRX_B_MARK, HSCIF0_HTX_B_MARK, +}; +static const unsigned int hscif0_clk_b_pins[] = { + /* SCK */ + RCAR_GP_PIN(1, 0), +}; +static const unsigned int hscif0_clk_b_mux[] = { + HSCIF0_HSCK_B_MARK, +}; +/* - HSCIF1 ----------------------------------------------------------------- */ +static const unsigned int hscif1_data_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9), +}; +static const unsigned int hscif1_data_mux[] = { + HSCIF1_HRX_MARK, HSCIF1_HTX_MARK, +}; +static const unsigned int hscif1_clk_pins[] = { + /* SCK */ + RCAR_GP_PIN(4, 10), +}; +static const unsigned int hscif1_clk_mux[] = { + HSCIF1_HSCK_MARK, +}; +static const unsigned int hscif1_ctrl_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 11), +}; +static const unsigned int hscif1_ctrl_mux[] = { + HSCIF1_HRTS_N_MARK, HSCIF1_HCTS_N_MARK, +}; +static const unsigned int hscif1_data_b_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14), +}; +static const unsigned int hscif1_data_b_mux[] = { + HSCIF1_HRX_B_MARK, HSCIF1_HTX_B_MARK, +}; +static const unsigned int hscif1_ctrl_b_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 15), +}; +static const unsigned int hscif1_ctrl_b_mux[] = { + HSCIF1_HRTS_N_B_MARK, HSCIF1_HCTS_N_B_MARK, +}; +/* - HSCIF2 ----------------------------------------------------------------- */ +static const unsigned int hscif2_data_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), +}; +static const unsigned int hscif2_data_mux[] = { + HSCIF2_HRX_MARK, HSCIF2_HTX_MARK, +}; +static const unsigned int hscif2_clk_pins[] = { + /* SCK */ + RCAR_GP_PIN(0, 10), +}; +static const unsigned int hscif2_clk_mux[] = { + HSCIF2_HSCK_MARK, +}; +static const unsigned int hscif2_ctrl_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), +}; +static const unsigned int hscif2_ctrl_mux[] = { + HSCIF2_HRTS_N_MARK, HSCIF2_HCTS_N_MARK, +}; +/* - I2C0 ------------------------------------------------------------------- */ +static const unsigned int i2c0_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(3, 30), RCAR_GP_PIN(3, 31), +}; +static const unsigned int i2c0_mux[] = { + I2C0_SCL_MARK, I2C0_SDA_MARK, +}; +static const unsigned int i2c0_b_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 21), +}; +static const unsigned int i2c0_b_mux[] = { + I2C0_SCL_B_MARK, I2C0_SDA_B_MARK, +}; +static const unsigned int i2c0_c_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12), +}; +static const unsigned int i2c0_c_mux[] = { + I2C0_SCL_C_MARK, I2C0_SDA_C_MARK, +}; +static const unsigned int i2c0_d_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6), +}; +static const unsigned int i2c0_d_mux[] = { + I2C0_SCL_D_MARK, I2C0_SDA_D_MARK, +}; +static const unsigned int i2c0_e_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28), +}; +static const unsigned int i2c0_e_mux[] = { + I2C0_SCL_E_MARK, I2C0_SDA_E_MARK, +}; +/* - I2C1 ------------------------------------------------------------------- */ +static const unsigned int i2c1_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1), +}; +static const unsigned int i2c1_mux[] = { + I2C1_SCL_MARK, I2C1_SDA_MARK, +}; +static const unsigned int i2c1_b_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), +}; +static const unsigned int i2c1_b_mux[] = { + I2C1_SCL_B_MARK, I2C1_SDA_B_MARK, +}; +static const unsigned int i2c1_c_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26), +}; +static const unsigned int i2c1_c_mux[] = { + I2C1_SCL_C_MARK, I2C1_SDA_C_MARK, +}; +static const unsigned int i2c1_d_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 12), +}; +static const unsigned int i2c1_d_mux[] = { + I2C1_SCL_D_MARK, I2C1_SDA_D_MARK, +}; +static const unsigned int i2c1_e_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21), +}; +static const unsigned int i2c1_e_mux[] = { + I2C1_SCL_E_MARK, I2C1_SDA_E_MARK, +}; +/* - I2C2 ------------------------------------------------------------------- */ +static const unsigned int i2c2_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23), +}; +static const unsigned int i2c2_mux[] = { + I2C2_SCL_MARK, I2C2_SDA_MARK, +}; +static const unsigned int i2c2_b_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25), +}; +static const unsigned int i2c2_b_mux[] = { + I2C2_SCL_B_MARK, I2C2_SDA_B_MARK, +}; +static const unsigned int i2c2_c_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3), +}; +static const unsigned int i2c2_c_mux[] = { + I2C2_SCL_C_MARK, I2C2_SDA_C_MARK, +}; +static const unsigned int i2c2_d_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), +}; +static const unsigned int i2c2_d_mux[] = { + I2C2_SCL_D_MARK, I2C2_SDA_D_MARK, +}; +static const unsigned int i2c2_e_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 17), +}; +static const unsigned int i2c2_e_mux[] = { + I2C2_SCL_E_MARK, I2C2_SDA_E_MARK, +}; +/* - I2C3 ------------------------------------------------------------------- */ +static const unsigned int i2c3_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 10), +}; +static const unsigned int i2c3_mux[] = { + I2C3_SCL_MARK, I2C3_SDA_MARK, +}; +static const unsigned int i2c3_b_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 4), +}; +static const unsigned int i2c3_b_mux[] = { + I2C3_SCL_B_MARK, I2C3_SDA_B_MARK, +}; +static const unsigned int i2c3_c_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26), +}; +static const unsigned int i2c3_c_mux[] = { + I2C3_SCL_C_MARK, I2C3_SDA_C_MARK, +}; +static const unsigned int i2c3_d_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9), +}; +static const unsigned int i2c3_d_mux[] = { + I2C3_SCL_D_MARK, I2C3_SDA_D_MARK, +}; +static const unsigned int i2c3_e_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19), +}; +static const unsigned int i2c3_e_mux[] = { + I2C3_SCL_E_MARK, I2C3_SDA_E_MARK, +}; +/* - I2C4 ------------------------------------------------------------------- */ +static const unsigned int i2c4_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9), +}; +static const unsigned int i2c4_mux[] = { + I2C4_SCL_MARK, I2C4_SDA_MARK, +}; +static const unsigned int i2c4_b_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 23), +}; +static const unsigned int i2c4_b_mux[] = { + I2C4_SCL_B_MARK, I2C4_SDA_B_MARK, +}; +static const unsigned int i2c4_c_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29), +}; +static const unsigned int i2c4_c_mux[] = { + I2C4_SCL_C_MARK, I2C4_SDA_C_MARK, +}; +static const unsigned int i2c4_d_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17), +}; +static const unsigned int i2c4_d_mux[] = { + I2C4_SCL_D_MARK, I2C4_SDA_D_MARK, +}; +static const unsigned int i2c4_e_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 24), +}; +static const unsigned int i2c4_e_mux[] = { + I2C4_SCL_E_MARK, I2C4_SDA_E_MARK, +}; +/* - INTC ------------------------------------------------------------------- */ +static const unsigned int intc_irq0_pins[] = { + /* IRQ0 */ + RCAR_GP_PIN(4, 4), +}; +static const unsigned int intc_irq0_mux[] = { + IRQ0_MARK, +}; +static const unsigned int intc_irq1_pins[] = { + /* IRQ1 */ + RCAR_GP_PIN(4, 18), +}; +static const unsigned int intc_irq1_mux[] = { + IRQ1_MARK, +}; +static const unsigned int intc_irq2_pins[] = { + /* IRQ2 */ + RCAR_GP_PIN(4, 19), +}; +static const unsigned int intc_irq2_mux[] = { + IRQ2_MARK, +}; +static const unsigned int intc_irq3_pins[] = { + /* IRQ3 */ + RCAR_GP_PIN(0, 7), +}; +static const unsigned int intc_irq3_mux[] = { + IRQ3_MARK, +}; +static const unsigned int intc_irq4_pins[] = { + /* IRQ4 */ + RCAR_GP_PIN(0, 0), +}; +static const unsigned int intc_irq4_mux[] = { + IRQ4_MARK, +}; +static const unsigned int intc_irq5_pins[] = { + /* IRQ5 */ + RCAR_GP_PIN(4, 1), +}; +static const unsigned int intc_irq5_mux[] = { + IRQ5_MARK, +}; +static const unsigned int intc_irq6_pins[] = { + /* IRQ6 */ + RCAR_GP_PIN(0, 10), +}; +static const unsigned int intc_irq6_mux[] = { + IRQ6_MARK, +}; +static const unsigned int intc_irq7_pins[] = { + /* IRQ7 */ + RCAR_GP_PIN(6, 15), +}; +static const unsigned int intc_irq7_mux[] = { + IRQ7_MARK, +}; +static const unsigned int intc_irq8_pins[] = { + /* IRQ8 */ + RCAR_GP_PIN(5, 0), +}; +static const unsigned int intc_irq8_mux[] = { + IRQ8_MARK, +}; +static const unsigned int intc_irq9_pins[] = { + /* IRQ9 */ + RCAR_GP_PIN(5, 10), +}; +static const unsigned int intc_irq9_mux[] = { + IRQ9_MARK, +}; +/* - MSIOF0 ----------------------------------------------------------------- */ +static const unsigned int msiof0_clk_pins[] = { + /* SCK */ + RCAR_GP_PIN(4, 4), +}; +static const unsigned int msiof0_clk_mux[] = { + MSIOF0_SCK_MARK, +}; +static const unsigned int msiof0_sync_pins[] = { + /* SYNC */ + RCAR_GP_PIN(4, 5), +}; +static const unsigned int msiof0_sync_mux[] = { + MSIOF0_SYNC_MARK, +}; +static const unsigned int msiof0_ss1_pins[] = { + /* SS1 */ + RCAR_GP_PIN(4, 6), +}; +static const unsigned int msiof0_ss1_mux[] = { + MSIOF0_SS1_MARK, +}; +static const unsigned int msiof0_ss2_pins[] = { + /* SS2 */ + RCAR_GP_PIN(4, 7), +}; +static const unsigned int msiof0_ss2_mux[] = { + MSIOF0_SS2_MARK, +}; +static const unsigned int msiof0_rx_pins[] = { + /* RXD */ + RCAR_GP_PIN(4, 2), +}; +static const unsigned int msiof0_rx_mux[] = { + MSIOF0_RXD_MARK, +}; +static const unsigned int msiof0_tx_pins[] = { + /* TXD */ + RCAR_GP_PIN(4, 3), +}; +static const unsigned int msiof0_tx_mux[] = { + MSIOF0_TXD_MARK, +}; +/* - MSIOF1 ----------------------------------------------------------------- */ +static const unsigned int msiof1_clk_pins[] = { + /* SCK */ + RCAR_GP_PIN(0, 26), +}; +static const unsigned int msiof1_clk_mux[] = { + MSIOF1_SCK_MARK, +}; +static const unsigned int msiof1_sync_pins[] = { + /* SYNC */ + RCAR_GP_PIN(0, 27), +}; +static const unsigned int msiof1_sync_mux[] = { + MSIOF1_SYNC_MARK, +}; +static const unsigned int msiof1_ss1_pins[] = { + /* SS1 */ + RCAR_GP_PIN(0, 28), +}; +static const unsigned int msiof1_ss1_mux[] = { + MSIOF1_SS1_MARK, +}; +static const unsigned int msiof1_ss2_pins[] = { + /* SS2 */ + RCAR_GP_PIN(0, 29), +}; +static const unsigned int msiof1_ss2_mux[] = { + MSIOF1_SS2_MARK, +}; +static const unsigned int msiof1_rx_pins[] = { + /* RXD */ + RCAR_GP_PIN(0, 24), +}; +static const unsigned int msiof1_rx_mux[] = { + MSIOF1_RXD_MARK, +}; +static const unsigned int msiof1_tx_pins[] = { + /* TXD */ + RCAR_GP_PIN(0, 25), +}; +static const unsigned int msiof1_tx_mux[] = { + MSIOF1_TXD_MARK, +}; +static const unsigned int msiof1_clk_b_pins[] = { + /* SCK */ + RCAR_GP_PIN(5, 3), +}; +static const unsigned int msiof1_clk_b_mux[] = { + MSIOF1_SCK_B_MARK, +}; +static const unsigned int msiof1_sync_b_pins[] = { + /* SYNC */ + RCAR_GP_PIN(5, 4), +}; +static const unsigned int msiof1_sync_b_mux[] = { + MSIOF1_SYNC_B_MARK, +}; +static const unsigned int msiof1_ss1_b_pins[] = { + /* SS1 */ + RCAR_GP_PIN(5, 5), +}; +static const unsigned int msiof1_ss1_b_mux[] = { + MSIOF1_SS1_B_MARK, +}; +static const unsigned int msiof1_ss2_b_pins[] = { + /* SS2 */ + RCAR_GP_PIN(5, 6), +}; +static const unsigned int msiof1_ss2_b_mux[] = { + MSIOF1_SS2_B_MARK, +}; +static const unsigned int msiof1_rx_b_pins[] = { + /* RXD */ + RCAR_GP_PIN(5, 1), +}; +static const unsigned int msiof1_rx_b_mux[] = { + MSIOF1_RXD_B_MARK, +}; +static const unsigned int msiof1_tx_b_pins[] = { + /* TXD */ + RCAR_GP_PIN(5, 2), +}; +static const unsigned int msiof1_tx_b_mux[] = { + MSIOF1_TXD_B_MARK, +}; +/* - MSIOF2 ----------------------------------------------------------------- */ +static const unsigned int msiof2_clk_pins[] = { + /* SCK */ + RCAR_GP_PIN(1, 0), +}; +static const unsigned int msiof2_clk_mux[] = { + MSIOF2_SCK_MARK, +}; +static const unsigned int msiof2_sync_pins[] = { + /* SYNC */ + RCAR_GP_PIN(1, 1), +}; +static const unsigned int msiof2_sync_mux[] = { + MSIOF2_SYNC_MARK, +}; +static const unsigned int msiof2_ss1_pins[] = { + /* SS1 */ + RCAR_GP_PIN(1, 2), +}; +static const unsigned int msiof2_ss1_mux[] = { + MSIOF2_SS1_MARK, +}; +static const unsigned int msiof2_ss2_pins[] = { + /* SS2 */ + RCAR_GP_PIN(1, 3), +}; +static const unsigned int msiof2_ss2_mux[] = { + MSIOF2_SS2_MARK, +}; +static const unsigned int msiof2_rx_pins[] = { + /* RXD */ + RCAR_GP_PIN(0, 30), +}; +static const unsigned int msiof2_rx_mux[] = { + MSIOF2_RXD_MARK, +}; +static const unsigned int msiof2_tx_pins[] = { + /* TXD */ + RCAR_GP_PIN(0, 31), +}; +static const unsigned int msiof2_tx_mux[] = { + MSIOF2_TXD_MARK, +}; +static const unsigned int msiof2_clk_b_pins[] = { + /* SCK */ + RCAR_GP_PIN(3, 15), +}; +static const unsigned int msiof2_clk_b_mux[] = { + MSIOF2_SCK_B_MARK, +}; +static const unsigned int msiof2_sync_b_pins[] = { + /* SYNC */ + RCAR_GP_PIN(3, 16), +}; +static const unsigned int msiof2_sync_b_mux[] = { + MSIOF2_SYNC_B_MARK, +}; +static const unsigned int msiof2_ss1_b_pins[] = { + /* SS1 */ + RCAR_GP_PIN(3, 17), +}; +static const unsigned int msiof2_ss1_b_mux[] = { + MSIOF2_SS1_B_MARK, +}; +static const unsigned int msiof2_ss2_b_pins[] = { + /* SS2 */ + RCAR_GP_PIN(3, 18), +}; +static const unsigned int msiof2_ss2_b_mux[] = { + MSIOF2_SS2_B_MARK, +}; +static const unsigned int msiof2_rx_b_pins[] = { + /* RXD */ + RCAR_GP_PIN(3, 13), +}; +static const unsigned int msiof2_rx_b_mux[] = { + MSIOF2_RXD_B_MARK, +}; +static const unsigned int msiof2_tx_b_pins[] = { + /* TXD */ + RCAR_GP_PIN(3, 14), +}; +static const unsigned int msiof2_tx_b_mux[] = { + MSIOF2_TXD_B_MARK, +}; +/* - QSPI ------------------------------------------------------------------- */ +static const unsigned int qspi_ctrl_pins[] = { + /* SPCLK, SSL */ + RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 9), +}; +static const unsigned int qspi_ctrl_mux[] = { + SPCLK_MARK, SSL_MARK, +}; +static const unsigned int qspi_data2_pins[] = { + /* MOSI_IO0, MISO_IO1 */ + RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), +}; +static const unsigned int qspi_data2_mux[] = { + MOSI_IO0_MARK, MISO_IO1_MARK, +}; +static const unsigned int qspi_data4_pins[] = { + /* MOSI_IO0, MISO_IO1, IO2, IO3 */ + RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), + RCAR_GP_PIN(1, 8), +}; +static const unsigned int qspi_data4_mux[] = { + MOSI_IO0_MARK, MISO_IO1_MARK, IO2_MARK, IO3_MARK, +}; +/* - SCIF0 ------------------------------------------------------------------ */ +static const unsigned int scif0_data_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25), +}; +static const unsigned int scif0_data_mux[] = { + SCIF0_RXD_MARK, SCIF0_TXD_MARK, +}; +static const unsigned int scif0_clk_pins[] = { + /* SCK */ + RCAR_GP_PIN(1, 23), +}; +static const unsigned int scif0_clk_mux[] = { + SCIF_CLK_MARK, +}; +static const unsigned int scif0_data_b_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12), +}; +static const unsigned int scif0_data_b_mux[] = { + SCIF0_RXD_B_MARK, SCIF0_TXD_B_MARK, +}; +static const unsigned int scif0_clk_b_pins[] = { + /* SCK */ + RCAR_GP_PIN(3, 29), +}; +static const unsigned int scif0_clk_b_mux[] = { + SCIF_CLK_B_MARK, +}; +static const unsigned int scif0_data_c_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(3, 30), RCAR_GP_PIN(3, 31), +}; +static const unsigned int scif0_data_c_mux[] = { + SCIF0_RXD_C_MARK, SCIF0_TXD_C_MARK, +}; +static const unsigned int scif0_data_d_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28), +}; +static const unsigned int scif0_data_d_mux[] = { + SCIF0_RXD_D_MARK, SCIF0_TXD_D_MARK, +}; +/* - SCIF1 ------------------------------------------------------------------ */ +static const unsigned int scif1_data_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15), +}; +static const unsigned int scif1_data_mux[] = { + SCIF1_RXD_MARK, SCIF1_TXD_MARK, +}; +static const unsigned int scif1_clk_pins[] = { + /* SCK */ + RCAR_GP_PIN(4, 13), +}; +static const unsigned int scif1_clk_mux[] = { + SCIF1_SCK_MARK, +}; +static const unsigned int scif1_data_b_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 12), +}; +static const unsigned int scif1_data_b_mux[] = { + SCIF1_RXD_B_MARK, SCIF1_TXD_B_MARK, +}; +static const unsigned int scif1_clk_b_pins[] = { + /* SCK */ + RCAR_GP_PIN(5, 10), +}; +static const unsigned int scif1_clk_b_mux[] = { + SCIF1_SCK_B_MARK, +}; +static const unsigned int scif1_data_c_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 12), +}; +static const unsigned int scif1_data_c_mux[] = { + SCIF1_RXD_C_MARK, SCIF1_TXD_C_MARK, +}; +static const unsigned int scif1_clk_c_pins[] = { + /* SCK */ + RCAR_GP_PIN(0, 10), +}; +static const unsigned int scif1_clk_c_mux[] = { + SCIF1_SCK_C_MARK, +}; +/* - SCIF2 ------------------------------------------------------------------ */ +static const unsigned int scif2_data_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 17), +}; +static const unsigned int scif2_data_mux[] = { + SCIF2_RXD_MARK, SCIF2_TXD_MARK, +}; +static const unsigned int scif2_clk_pins[] = { + /* SCK */ + RCAR_GP_PIN(4, 18), +}; +static const unsigned int scif2_clk_mux[] = { + SCIF2_SCK_MARK, +}; +static const unsigned int scif2_data_b_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19), +}; +static const unsigned int scif2_data_b_mux[] = { + SCIF2_RXD_B_MARK, SCIF2_TXD_B_MARK, +}; +static const unsigned int scif2_clk_b_pins[] = { + /* SCK */ + RCAR_GP_PIN(5, 17), +}; +static const unsigned int scif2_clk_b_mux[] = { + SCIF2_SCK_B_MARK, +}; +static const unsigned int scif2_data_c_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21), +}; +static const unsigned int scif2_data_c_mux[] = { + SCIF2_RXD_C_MARK, SCIF2_TXD_C_MARK, +}; +static const unsigned int scif2_clk_c_pins[] = { + /* SCK */ + RCAR_GP_PIN(3, 19), +}; +static const unsigned int scif2_clk_c_mux[] = { + SCIF2_SCK_C_MARK, +}; +/* - SCIF3 ------------------------------------------------------------------ */ +static const unsigned int scif3_data_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21), +}; +static const unsigned int scif3_data_mux[] = { + SCIF3_RXD_MARK, SCIF3_TXD_MARK, +}; +static const unsigned int scif3_clk_pins[] = { + /* SCK */ + RCAR_GP_PIN(4, 19), +}; +static const unsigned int scif3_clk_mux[] = { + SCIF3_SCK_MARK, +}; +static const unsigned int scif3_data_b_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 24), +}; +static const unsigned int scif3_data_b_mux[] = { + SCIF3_RXD_B_MARK, SCIF3_TXD_B_MARK, +}; +static const unsigned int scif3_clk_b_pins[] = { + /* SCK */ + RCAR_GP_PIN(3, 22), +}; +static const unsigned int scif3_clk_b_mux[] = { + SCIF3_SCK_B_MARK, +}; +/* - SCIF4 ------------------------------------------------------------------ */ +static const unsigned int scif4_data_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1), +}; +static const unsigned int scif4_data_mux[] = { + SCIF4_RXD_MARK, SCIF4_TXD_MARK, +}; +static const unsigned int scif4_data_b_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6), +}; +static const unsigned int scif4_data_b_mux[] = { + SCIF4_RXD_B_MARK, SCIF4_TXD_B_MARK, +}; +static const unsigned int scif4_data_c_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15), +}; +static const unsigned int scif4_data_c_mux[] = { + SCIF4_RXD_C_MARK, SCIF4_TXD_C_MARK, +}; +static const unsigned int scif4_data_d_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 18), +}; +static const unsigned int scif4_data_d_mux[] = { + SCIF4_RXD_D_MARK, SCIF4_TXD_D_MARK, +}; +static const unsigned int scif4_data_e_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 2), +}; +static const unsigned int scif4_data_e_mux[] = { + SCIF4_RXD_E_MARK, SCIF4_TXD_E_MARK, +}; +/* - SCIF5 ------------------------------------------------------------------ */ +static const unsigned int scif5_data_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3), +}; +static const unsigned int scif5_data_mux[] = { + SCIF5_RXD_MARK, SCIF5_TXD_MARK, +}; +static const unsigned int scif5_data_b_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 4), +}; +static const unsigned int scif5_data_b_mux[] = { + SCIF5_RXD_B_MARK, SCIF5_TXD_B_MARK, +}; +static const unsigned int scif5_data_c_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 11), +}; +static const unsigned int scif5_data_c_mux[] = { + SCIF5_RXD_C_MARK, SCIF5_TXD_C_MARK, +}; +static const unsigned int scif5_data_d_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2), +}; +static const unsigned int scif5_data_d_mux[] = { + SCIF5_RXD_D_MARK, SCIF5_TXD_D_MARK, +}; +/* - SCIFA0 ----------------------------------------------------------------- */ +static const unsigned int scifa0_data_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 7), +}; +static const unsigned int scifa0_data_mux[] = { + SCIFA0_RXD_MARK, SCIFA0_TXD_MARK, +}; +static const unsigned int scifa0_data_b_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25), +}; +static const unsigned int scifa0_data_b_mux[] = { + SCIFA0_RXD_B_MARK, SCIFA0_TXD_B_MARK +}; +static const unsigned int scifa0_data_c_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9), +}; +static const unsigned int scifa0_data_c_mux[] = { + SCIFA0_RXD_C_MARK, SCIFA0_TXD_C_MARK +}; +static const unsigned int scifa0_data_d_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16), +}; +static const unsigned int scifa0_data_d_mux[] = { + SCIFA0_RXD_D_MARK, SCIFA0_TXD_D_MARK +}; +/* - SCIFA1 ----------------------------------------------------------------- */ +static const unsigned int scifa1_data_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), +}; +static const unsigned int scifa1_data_mux[] = { + SCIFA1_RXD_MARK, SCIFA1_TXD_MARK, +}; +static const unsigned int scifa1_clk_pins[] = { + /* SCK */ + RCAR_GP_PIN(0, 13), +}; +static const unsigned int scifa1_clk_mux[] = { + SCIFA1_SCK_MARK, +}; +static const unsigned int scifa1_data_b_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29), +}; +static const unsigned int scifa1_data_b_mux[] = { + SCIFA1_RXD_B_MARK, SCIFA1_TXD_B_MARK, +}; +static const unsigned int scifa1_clk_b_pins[] = { + /* SCK */ + RCAR_GP_PIN(4, 27), +}; +static const unsigned int scifa1_clk_b_mux[] = { + SCIFA1_SCK_B_MARK, +}; +static const unsigned int scifa1_data_c_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6), +}; +static const unsigned int scifa1_data_c_mux[] = { + SCIFA1_RXD_C_MARK, SCIFA1_TXD_C_MARK, +}; +static const unsigned int scifa1_clk_c_pins[] = { + /* SCK */ + RCAR_GP_PIN(5, 4), +}; +static const unsigned int scifa1_clk_c_mux[] = { + SCIFA1_SCK_C_MARK, +}; +/* - SCIFA2 ----------------------------------------------------------------- */ +static const unsigned int scifa2_data_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 17), +}; +static const unsigned int scifa2_data_mux[] = { + SCIFA2_RXD_MARK, SCIFA2_TXD_MARK, +}; +static const unsigned int scifa2_clk_pins[] = { + /* SCK */ + RCAR_GP_PIN(1, 15), +}; +static const unsigned int scifa2_clk_mux[] = { + SCIFA2_SCK_MARK, +}; +static const unsigned int scifa2_data_b_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(4, 31), RCAR_GP_PIN(5, 0), +}; +static const unsigned int scifa2_data_b_mux[] = { + SCIFA2_RXD_B_MARK, SCIFA2_TXD_B_MARK, +}; +static const unsigned int scifa2_clk_b_pins[] = { + /* SCK */ + RCAR_GP_PIN(4, 30), +}; +static const unsigned int scifa2_clk_b_mux[] = { + SCIFA2_SCK_B_MARK, +}; +/* - SCIFA3 ----------------------------------------------------------------- */ +static const unsigned int scifa3_data_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26), +}; +static const unsigned int scifa3_data_mux[] = { + SCIFA3_RXD_MARK, SCIFA3_TXD_MARK, +}; +static const unsigned int scifa3_clk_pins[] = { + /* SCK */ + RCAR_GP_PIN(4, 24), +}; +static const unsigned int scifa3_clk_mux[] = { + SCIFA3_SCK_MARK, +}; +static const unsigned int scifa3_data_b_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 2), +}; +static const unsigned int scifa3_data_b_mux[] = { + SCIFA3_RXD_B_MARK, SCIFA3_TXD_B_MARK, +}; +static const unsigned int scifa3_clk_b_pins[] = { + /* SCK */ + RCAR_GP_PIN(0, 0), +}; +static const unsigned int scifa3_clk_b_mux[] = { + SCIFA3_SCK_B_MARK, +}; +/* - SCIFA4 ----------------------------------------------------------------- */ +static const unsigned int scifa4_data_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 12), +}; +static const unsigned int scifa4_data_mux[] = { + SCIFA4_RXD_MARK, SCIFA4_TXD_MARK, +}; +static const unsigned int scifa4_data_b_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(0, 22), RCAR_GP_PIN(0, 23), +}; +static const unsigned int scifa4_data_b_mux[] = { + SCIFA4_RXD_B_MARK, SCIFA4_TXD_B_MARK, +}; +static const unsigned int scifa4_data_c_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17), +}; +static const unsigned int scifa4_data_c_mux[] = { + SCIFA4_RXD_C_MARK, SCIFA4_TXD_C_MARK, +}; +static const unsigned int scifa4_data_d_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 21), +}; +static const unsigned int scifa4_data_d_mux[] = { + SCIFA4_RXD_D_MARK, SCIFA4_TXD_D_MARK, +}; +/* - SCIFA5 ----------------------------------------------------------------- */ +static const unsigned int scifa5_data_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23), +}; +static const unsigned int scifa5_data_mux[] = { + SCIFA5_RXD_MARK, SCIFA5_TXD_MARK, +}; +static const unsigned int scifa5_data_b_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(0, 28), RCAR_GP_PIN(0, 29), +}; +static const unsigned int scifa5_data_b_mux[] = { + SCIFA5_RXD_B_MARK, SCIFA5_TXD_B_MARK, +}; +static const unsigned int scifa5_data_c_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 10), +}; +static const unsigned int scifa5_data_c_mux[] = { + SCIFA5_RXD_C_MARK, SCIFA5_TXD_C_MARK, +}; +static const unsigned int scifa5_data_d_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 23), +}; +static const unsigned int scifa5_data_d_mux[] = { + SCIFA5_RXD_D_MARK, SCIFA5_TXD_D_MARK, +}; +/* - SCIFB0 ----------------------------------------------------------------- */ +static const unsigned int scifb0_data_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(0, 21), RCAR_GP_PIN(0, 20), +}; +static const unsigned int scifb0_data_mux[] = { + SCIFB0_RXD_MARK, SCIFB0_TXD_MARK, +}; +static const unsigned int scifb0_clk_pins[] = { + /* SCK */ + RCAR_GP_PIN(0, 19), +}; +static const unsigned int scifb0_clk_mux[] = { + SCIFB0_SCK_MARK, +}; +static const unsigned int scifb0_ctrl_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(0, 23), RCAR_GP_PIN(0, 22), +}; +static const unsigned int scifb0_ctrl_mux[] = { + SCIFB0_RTS_N_MARK, SCIFB0_CTS_N_MARK, +}; +/* - SCIFB1 ----------------------------------------------------------------- */ +static const unsigned int scifb1_data_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(1, 24), RCAR_GP_PIN(0, 17), +}; +static const unsigned int scifb1_data_mux[] = { + SCIFB1_RXD_MARK, SCIFB1_TXD_MARK, +}; +static const unsigned int scifb1_clk_pins[] = { + /* SCK */ + RCAR_GP_PIN(0, 16), +}; +static const unsigned int scifb1_clk_mux[] = { + SCIFB1_SCK_MARK, +}; +/* - SCIFB2 ----------------------------------------------------------------- */ +static const unsigned int scifb2_data_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14), +}; +static const unsigned int scifb2_data_mux[] = { + SCIFB2_RXD_MARK, SCIFB2_TXD_MARK, +}; +static const unsigned int scifb2_clk_pins[] = { + /* SCK */ + RCAR_GP_PIN(1, 15), +}; +static const unsigned int scifb2_clk_mux[] = { + SCIFB2_SCK_MARK, +}; +static const unsigned int scifb2_ctrl_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16), +}; +static const unsigned int scifb2_ctrl_mux[] = { + SCIFB2_RTS_N_MARK, SCIFB2_CTS_N_MARK, +}; + +static const struct sh_pfc_pin_group pinmux_groups[] = { + SH_PFC_PIN_GROUP(eth_link), + SH_PFC_PIN_GROUP(eth_magic), + SH_PFC_PIN_GROUP(eth_mdio), + SH_PFC_PIN_GROUP(eth_rmii), + SH_PFC_PIN_GROUP(eth_link_b), + SH_PFC_PIN_GROUP(eth_magic_b), + SH_PFC_PIN_GROUP(eth_mdio_b), + SH_PFC_PIN_GROUP(eth_rmii_b), + SH_PFC_PIN_GROUP(hscif0_data), + SH_PFC_PIN_GROUP(hscif0_clk), + SH_PFC_PIN_GROUP(hscif0_ctrl), + SH_PFC_PIN_GROUP(hscif0_data_b), + SH_PFC_PIN_GROUP(hscif0_clk_b), + SH_PFC_PIN_GROUP(hscif1_data), + SH_PFC_PIN_GROUP(hscif1_clk), + SH_PFC_PIN_GROUP(hscif1_ctrl), + SH_PFC_PIN_GROUP(hscif1_data_b), + SH_PFC_PIN_GROUP(hscif1_ctrl_b), + SH_PFC_PIN_GROUP(hscif2_data), + SH_PFC_PIN_GROUP(hscif2_clk), + SH_PFC_PIN_GROUP(hscif2_ctrl), + SH_PFC_PIN_GROUP(i2c0), + SH_PFC_PIN_GROUP(i2c0_b), + SH_PFC_PIN_GROUP(i2c0_c), + SH_PFC_PIN_GROUP(i2c0_d), + SH_PFC_PIN_GROUP(i2c0_e), + SH_PFC_PIN_GROUP(i2c1), + SH_PFC_PIN_GROUP(i2c1_b), + SH_PFC_PIN_GROUP(i2c1_c), + SH_PFC_PIN_GROUP(i2c1_d), + SH_PFC_PIN_GROUP(i2c1_e), + SH_PFC_PIN_GROUP(i2c2), + SH_PFC_PIN_GROUP(i2c2_b), + SH_PFC_PIN_GROUP(i2c2_c), + SH_PFC_PIN_GROUP(i2c2_d), + SH_PFC_PIN_GROUP(i2c2_e), + SH_PFC_PIN_GROUP(i2c3), + SH_PFC_PIN_GROUP(i2c3_b), + SH_PFC_PIN_GROUP(i2c3_c), + SH_PFC_PIN_GROUP(i2c3_d), + SH_PFC_PIN_GROUP(i2c3_e), + SH_PFC_PIN_GROUP(i2c4), + SH_PFC_PIN_GROUP(i2c4_b), + SH_PFC_PIN_GROUP(i2c4_c), + SH_PFC_PIN_GROUP(i2c4_d), + SH_PFC_PIN_GROUP(i2c4_e), + SH_PFC_PIN_GROUP(intc_irq0), + SH_PFC_PIN_GROUP(intc_irq1), + SH_PFC_PIN_GROUP(intc_irq2), + SH_PFC_PIN_GROUP(intc_irq3), + SH_PFC_PIN_GROUP(intc_irq4), + SH_PFC_PIN_GROUP(intc_irq5), + SH_PFC_PIN_GROUP(intc_irq6), + SH_PFC_PIN_GROUP(intc_irq7), + SH_PFC_PIN_GROUP(intc_irq8), + SH_PFC_PIN_GROUP(intc_irq9), + SH_PFC_PIN_GROUP(msiof0_clk), + SH_PFC_PIN_GROUP(msiof0_sync), + SH_PFC_PIN_GROUP(msiof0_ss1), + SH_PFC_PIN_GROUP(msiof0_ss2), + SH_PFC_PIN_GROUP(msiof0_rx), + SH_PFC_PIN_GROUP(msiof0_tx), + SH_PFC_PIN_GROUP(msiof1_clk), + SH_PFC_PIN_GROUP(msiof1_sync), + SH_PFC_PIN_GROUP(msiof1_ss1), + SH_PFC_PIN_GROUP(msiof1_ss2), + SH_PFC_PIN_GROUP(msiof1_rx), + SH_PFC_PIN_GROUP(msiof1_tx), + SH_PFC_PIN_GROUP(msiof1_clk_b), + SH_PFC_PIN_GROUP(msiof1_sync_b), + SH_PFC_PIN_GROUP(msiof1_ss1_b), + SH_PFC_PIN_GROUP(msiof1_ss2_b), + SH_PFC_PIN_GROUP(msiof1_rx_b), + SH_PFC_PIN_GROUP(msiof1_tx_b), + SH_PFC_PIN_GROUP(msiof2_clk), + SH_PFC_PIN_GROUP(msiof2_sync), + SH_PFC_PIN_GROUP(msiof2_ss1), + SH_PFC_PIN_GROUP(msiof2_ss2), + SH_PFC_PIN_GROUP(msiof2_rx), + SH_PFC_PIN_GROUP(msiof2_tx), + SH_PFC_PIN_GROUP(msiof2_clk_b), + SH_PFC_PIN_GROUP(msiof2_sync_b), + SH_PFC_PIN_GROUP(msiof2_ss1_b), + SH_PFC_PIN_GROUP(msiof2_ss2_b), + SH_PFC_PIN_GROUP(msiof2_rx_b), + SH_PFC_PIN_GROUP(msiof2_tx_b), + SH_PFC_PIN_GROUP(qspi_ctrl), + SH_PFC_PIN_GROUP(qspi_data2), + SH_PFC_PIN_GROUP(qspi_data4), + SH_PFC_PIN_GROUP(scif0_data), + SH_PFC_PIN_GROUP(scif0_clk), + SH_PFC_PIN_GROUP(scif0_data_b), + SH_PFC_PIN_GROUP(scif0_clk_b), + SH_PFC_PIN_GROUP(scif0_data_c), + SH_PFC_PIN_GROUP(scif0_data_d), + SH_PFC_PIN_GROUP(scif1_data), + SH_PFC_PIN_GROUP(scif1_clk), + SH_PFC_PIN_GROUP(scif1_data_b), + SH_PFC_PIN_GROUP(scif1_clk_b), + SH_PFC_PIN_GROUP(scif1_data_c), + SH_PFC_PIN_GROUP(scif1_clk_c), + SH_PFC_PIN_GROUP(scif2_data), + SH_PFC_PIN_GROUP(scif2_clk), + SH_PFC_PIN_GROUP(scif2_data_b), + SH_PFC_PIN_GROUP(scif2_clk_b), + SH_PFC_PIN_GROUP(scif2_data_c), + SH_PFC_PIN_GROUP(scif2_clk_c), + SH_PFC_PIN_GROUP(scif3_data), + SH_PFC_PIN_GROUP(scif3_clk), + SH_PFC_PIN_GROUP(scif3_data_b), + SH_PFC_PIN_GROUP(scif3_clk_b), + SH_PFC_PIN_GROUP(scif4_data), + SH_PFC_PIN_GROUP(scif4_data_b), + SH_PFC_PIN_GROUP(scif4_data_c), + SH_PFC_PIN_GROUP(scif4_data_d), + SH_PFC_PIN_GROUP(scif4_data_e), + SH_PFC_PIN_GROUP(scif5_data), + SH_PFC_PIN_GROUP(scif5_data_b), + SH_PFC_PIN_GROUP(scif5_data_c), + SH_PFC_PIN_GROUP(scif5_data_d), + SH_PFC_PIN_GROUP(scifa0_data), + SH_PFC_PIN_GROUP(scifa0_data_b), + SH_PFC_PIN_GROUP(scifa0_data_c), + SH_PFC_PIN_GROUP(scifa0_data_d), + SH_PFC_PIN_GROUP(scifa1_data), + SH_PFC_PIN_GROUP(scifa1_clk), + SH_PFC_PIN_GROUP(scifa1_data_b), + SH_PFC_PIN_GROUP(scifa1_clk_b), + SH_PFC_PIN_GROUP(scifa1_data_c), + SH_PFC_PIN_GROUP(scifa1_clk_c), + SH_PFC_PIN_GROUP(scifa2_data), + SH_PFC_PIN_GROUP(scifa2_clk), + SH_PFC_PIN_GROUP(scifa2_data_b), + SH_PFC_PIN_GROUP(scifa2_clk_b), + SH_PFC_PIN_GROUP(scifa3_data), + SH_PFC_PIN_GROUP(scifa3_clk), + SH_PFC_PIN_GROUP(scifa3_data_b), + SH_PFC_PIN_GROUP(scifa3_clk_b), + SH_PFC_PIN_GROUP(scifa4_data), + SH_PFC_PIN_GROUP(scifa4_data_b), + SH_PFC_PIN_GROUP(scifa4_data_c), + SH_PFC_PIN_GROUP(scifa4_data_d), + SH_PFC_PIN_GROUP(scifa5_data), + SH_PFC_PIN_GROUP(scifa5_data_b), + SH_PFC_PIN_GROUP(scifa5_data_c), + SH_PFC_PIN_GROUP(scifa5_data_d), + SH_PFC_PIN_GROUP(scifb0_data), + SH_PFC_PIN_GROUP(scifb0_clk), + SH_PFC_PIN_GROUP(scifb0_ctrl), + SH_PFC_PIN_GROUP(scifb1_data), + SH_PFC_PIN_GROUP(scifb1_clk), + SH_PFC_PIN_GROUP(scifb2_data), + SH_PFC_PIN_GROUP(scifb2_clk), + SH_PFC_PIN_GROUP(scifb2_ctrl), +}; + +static const char * const eth_groups[] = { + "eth_link", + "eth_magic", + "eth_mdio", + "eth_rmii", + "eth_link_b", + "eth_magic_b", + "eth_mdio_b", + "eth_rmii_b", +}; + +static const char * const hscif0_groups[] = { + "hscif0_data", + "hscif0_clk", + "hscif0_ctrl", + "hscif0_data_b", + "hscif0_clk_b", +}; + +static const char * const hscif1_groups[] = { + "hscif1_data", + "hscif1_clk", + "hscif1_ctrl", + "hscif1_data_b", + "hscif1_ctrl_b", +}; + +static const char * const hscif2_groups[] = { + "hscif2_data", + "hscif2_clk", + "hscif2_ctrl", +}; + +static const char * const i2c0_groups[] = { + "i2c0", + "i2c0_b", + "i2c0_c", + "i2c0_d", + "i2c0_e", +}; + +static const char * const i2c1_groups[] = { + "i2c1", + "i2c1_b", + "i2c1_c", + "i2c1_d", + "i2c1_e", +}; + +static const char * const i2c2_groups[] = { + "i2c2", + "i2c2_b", + "i2c2_c", + "i2c2_d", + "i2c2_e", +}; + +static const char * const i2c3_groups[] = { + "i2c3", + "i2c3_b", + "i2c3_c", + "i2c3_d", + "i2c3_e", +}; + +static const char * const i2c4_groups[] = { + "i2c4", + "i2c4_b", + "i2c4_c", + "i2c4_d", + "i2c4_e", +}; + +static const char * const intc_groups[] = { + "intc_irq0", + "intc_irq1", + "intc_irq2", + "intc_irq3", + "intc_irq4", + "intc_irq5", + "intc_irq6", + "intc_irq7", + "intc_irq8", + "intc_irq9", +}; + +static const char * const msiof0_groups[] = { + "msiof0_clk", + "msiof0_sync", + "msiof0_ss1", + "msiof0_ss2", + "msiof0_rx", + "msiof0_tx", +}; + +static const char * const msiof1_groups[] = { + "msiof1_clk", + "msiof1_sync", + "msiof1_ss1", + "msiof1_ss2", + "msiof1_rx", + "msiof1_tx", + "msiof1_clk_b", + "msiof1_sync_b", + "msiof1_ss1_b", + "msiof1_ss2_b", + "msiof1_rx_b", + "msiof1_tx_b", +}; + +static const char * const msiof2_groups[] = { + "msiof2_clk", + "msiof2_sync", + "msiof2_ss1", + "msiof2_ss2", + "msiof2_rx", + "msiof2_tx", + "msiof2_clk_b", + "msiof2_sync_b", + "msiof2_ss1_b", + "msiof2_ss2_b", + "msiof2_rx_b", + "msiof2_tx_b", +}; + +static const char * const qspi_groups[] = { + "qspi_ctrl", + "qspi_data2", + "qspi_data4", +}; + +static const char * const scif0_groups[] = { + "scif0_data", + "scif0_clk", + "scif0_data_b", + "scif0_clk_b", + "scif0_data_c", + "scif0_data_d", +}; + +static const char * const scif1_groups[] = { + "scif1_data", + "scif1_clk", + "scif1_data_b", + "scif1_clk_b", + "scif1_data_c", + "scif1_clk_c", +}; + +static const char * const scif2_groups[] = { + "scif2_data", + "scif2_clk", + "scif2_data_b", + "scif2_clk_b", + "scif2_data_c", + "scif2_clk_c", +}; + +static const char * const scif3_groups[] = { + "scif3_data", + "scif3_clk", + "scif3_data_b", + "scif3_clk_b", +}; + +static const char * const scif4_groups[] = { + "scif4_data", + "scif4_data_b", + "scif4_data_c", + "scif4_data_d", + "scif4_data_e", +}; + +static const char * const scif5_groups[] = { + "scif5_data", + "scif5_data_b", + "scif5_data_c", + "scif5_data_d", +}; + +static const char * const scifa0_groups[] = { + "scifa0_data", + "scifa0_data_b", + "scifa0_data_c", + "scifa0_data_d", +}; + +static const char * const scifa1_groups[] = { + "scifa1_data", + "scifa1_clk", + "scifa1_data_b", + "scifa1_clk_b", + "scifa1_data_c", + "scifa1_clk_c", +}; + +static const char * const scifa2_groups[] = { + "scifa2_data", + "scifa2_clk", + "scifa2_data_b", + "scifa2_clk_b", +}; + +static const char * const scifa3_groups[] = { + "scifa3_data", + "scifa3_clk", + "scifa3_data_b", + "scifa3_clk_b", +}; + +static const char * const scifa4_groups[] = { + "scifa4_data", + "scifa4_data_b", + "scifa4_data_c", + "scifa4_data_d", +}; + +static const char * const scifa5_groups[] = { + "scifa5_data", + "scifa5_data_b", + "scifa5_data_c", + "scifa5_data_d", +}; + +static const char * const scifb0_groups[] = { + "scifb0_data", + "scifb0_clk", + "scifb0_ctrl", +}; + +static const char * const scifb1_groups[] = { + "scifb1_data", + "scifb1_clk", +}; + +static const char * const scifb2_groups[] = { + "scifb2_data", + "scifb2_clk", + "scifb2_ctrl", +}; + +static const struct sh_pfc_function pinmux_functions[] = { + SH_PFC_FUNCTION(eth), + SH_PFC_FUNCTION(hscif0), + SH_PFC_FUNCTION(hscif1), + SH_PFC_FUNCTION(hscif2), + SH_PFC_FUNCTION(i2c0), + SH_PFC_FUNCTION(i2c1), + SH_PFC_FUNCTION(i2c2), + SH_PFC_FUNCTION(i2c3), + SH_PFC_FUNCTION(i2c4), + SH_PFC_FUNCTION(intc), + SH_PFC_FUNCTION(msiof0), + SH_PFC_FUNCTION(msiof1), + SH_PFC_FUNCTION(msiof2), + SH_PFC_FUNCTION(qspi), + SH_PFC_FUNCTION(scif0), + SH_PFC_FUNCTION(scif1), + SH_PFC_FUNCTION(scif2), + SH_PFC_FUNCTION(scif3), + SH_PFC_FUNCTION(scif4), + SH_PFC_FUNCTION(scif5), + SH_PFC_FUNCTION(scifa0), + SH_PFC_FUNCTION(scifa1), + SH_PFC_FUNCTION(scifa2), + SH_PFC_FUNCTION(scifa3), + SH_PFC_FUNCTION(scifa4), + SH_PFC_FUNCTION(scifa5), + SH_PFC_FUNCTION(scifb0), + SH_PFC_FUNCTION(scifb1), + SH_PFC_FUNCTION(scifb2), +}; + +static const struct pinmux_cfg_reg pinmux_config_regs[] = { + { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) { + GP_0_31_FN, FN_IP2_17_16, + GP_0_30_FN, FN_IP2_15_14, + GP_0_29_FN, FN_IP2_13_12, + GP_0_28_FN, FN_IP2_11_10, + GP_0_27_FN, FN_IP2_9_8, + GP_0_26_FN, FN_IP2_7_6, + GP_0_25_FN, FN_IP2_5_4, + GP_0_24_FN, FN_IP2_3_2, + GP_0_23_FN, FN_IP2_1_0, + GP_0_22_FN, FN_IP1_31_30, + GP_0_21_FN, FN_IP1_29_28, + GP_0_20_FN, FN_IP1_27, + GP_0_19_FN, FN_IP1_26, + GP_0_18_FN, FN_A2, + GP_0_17_FN, FN_IP1_24, + GP_0_16_FN, FN_IP1_23_22, + GP_0_15_FN, FN_IP1_21_20, + GP_0_14_FN, FN_IP1_19_18, + GP_0_13_FN, FN_IP1_17_15, + GP_0_12_FN, FN_IP1_14_13, + GP_0_11_FN, FN_IP1_12_11, + GP_0_10_FN, FN_IP1_10_8, + GP_0_9_FN, FN_IP1_7_6, + GP_0_8_FN, FN_IP1_5_4, + GP_0_7_FN, FN_IP1_3_2, + GP_0_6_FN, FN_IP1_1_0, + GP_0_5_FN, FN_IP0_31_30, + GP_0_4_FN, FN_IP0_29_28, + GP_0_3_FN, FN_IP0_27_26, + GP_0_2_FN, FN_IP0_25, + GP_0_1_FN, FN_IP0_24, + GP_0_0_FN, FN_IP0_23_22, } + }, + { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) { + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + GP_1_25_FN, FN_DACK0, + GP_1_24_FN, FN_IP7_31, + GP_1_23_FN, FN_IP4_1_0, + GP_1_22_FN, FN_WE1_N, + GP_1_21_FN, FN_WE0_N, + GP_1_20_FN, FN_IP3_31, + GP_1_19_FN, FN_IP3_30, + GP_1_18_FN, FN_IP3_29_27, + GP_1_17_FN, FN_IP3_26_24, + GP_1_16_FN, FN_IP3_23_21, + GP_1_15_FN, FN_IP3_20_18, + GP_1_14_FN, FN_IP3_17_15, + GP_1_13_FN, FN_IP3_14_13, + GP_1_12_FN, FN_IP3_12, + GP_1_11_FN, FN_IP3_11, + GP_1_10_FN, FN_IP3_10, + GP_1_9_FN, FN_IP3_9_8, + GP_1_8_FN, FN_IP3_7_6, + GP_1_7_FN, FN_IP3_5_4, + GP_1_6_FN, FN_IP3_3_2, + GP_1_5_FN, FN_IP3_1_0, + GP_1_4_FN, FN_IP2_31_30, + GP_1_3_FN, FN_IP2_29_27, + GP_1_2_FN, FN_IP2_26_24, + GP_1_1_FN, FN_IP2_23_21, + GP_1_0_FN, FN_IP2_20_18, } + }, + { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) { + GP_2_31_FN, FN_IP6_7_6, + GP_2_30_FN, FN_IP6_5_4, + GP_2_29_FN, FN_IP6_3_2, + GP_2_28_FN, FN_IP6_1_0, + GP_2_27_FN, FN_IP5_31_30, + GP_2_26_FN, FN_IP5_29_28, + GP_2_25_FN, FN_IP5_27_26, + GP_2_24_FN, FN_IP5_25_24, + GP_2_23_FN, FN_IP5_23_22, + GP_2_22_FN, FN_IP5_21_20, + GP_2_21_FN, FN_IP5_19_18, + GP_2_20_FN, FN_IP5_17_16, + GP_2_19_FN, FN_IP5_15_14, + GP_2_18_FN, FN_IP5_13_12, + GP_2_17_FN, FN_IP5_11_9, + GP_2_16_FN, FN_IP5_8_6, + GP_2_15_FN, FN_IP5_5_4, + GP_2_14_FN, FN_IP5_3_2, + GP_2_13_FN, FN_IP5_1_0, + GP_2_12_FN, FN_IP4_31_30, + GP_2_11_FN, FN_IP4_29_28, + GP_2_10_FN, FN_IP4_27_26, + GP_2_9_FN, FN_IP4_25_23, + GP_2_8_FN, FN_IP4_22_20, + GP_2_7_FN, FN_IP4_19_18, + GP_2_6_FN, FN_IP4_17_16, + GP_2_5_FN, FN_IP4_15_14, + GP_2_4_FN, FN_IP4_13_12, + GP_2_3_FN, FN_IP4_11_10, + GP_2_2_FN, FN_IP4_9_8, + GP_2_1_FN, FN_IP4_7_5, + GP_2_0_FN, FN_IP4_4_2 } + }, + { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) { + GP_3_31_FN, FN_IP8_22_20, + GP_3_30_FN, FN_IP8_19_17, + GP_3_29_FN, FN_IP8_16_15, + GP_3_28_FN, FN_IP8_14_12, + GP_3_27_FN, FN_IP8_11_9, + GP_3_26_FN, FN_IP8_8_6, + GP_3_25_FN, FN_IP8_5_3, + GP_3_24_FN, FN_IP8_2_0, + GP_3_23_FN, FN_IP7_29_27, + GP_3_22_FN, FN_IP7_26_24, + GP_3_21_FN, FN_IP7_23_21, + GP_3_20_FN, FN_IP7_20_18, + GP_3_19_FN, FN_IP7_17_15, + GP_3_18_FN, FN_IP7_14_12, + GP_3_17_FN, FN_IP7_11_9, + GP_3_16_FN, FN_IP7_8_6, + GP_3_15_FN, FN_IP7_5_3, + GP_3_14_FN, FN_IP7_2_0, + GP_3_13_FN, FN_IP6_31_29, + GP_3_12_FN, FN_IP6_28_26, + GP_3_11_FN, FN_IP6_25_23, + GP_3_10_FN, FN_IP6_22_20, + GP_3_9_FN, FN_IP6_19_17, + GP_3_8_FN, FN_IP6_16, + GP_3_7_FN, FN_IP6_15, + GP_3_6_FN, FN_IP6_14, + GP_3_5_FN, FN_IP6_13, + GP_3_4_FN, FN_IP6_12, + GP_3_3_FN, FN_IP6_11, + GP_3_2_FN, FN_IP6_10, + GP_3_1_FN, FN_IP6_9, + GP_3_0_FN, FN_IP6_8 } + }, + { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) { + GP_4_31_FN, FN_IP11_17_16, + GP_4_30_FN, FN_IP11_15_14, + GP_4_29_FN, FN_IP11_13_11, + GP_4_28_FN, FN_IP11_10_8, + GP_4_27_FN, FN_IP11_7_6, + GP_4_26_FN, FN_IP11_5_3, + GP_4_25_FN, FN_IP11_2_0, + GP_4_24_FN, FN_IP10_31_30, + GP_4_23_FN, FN_IP10_29_27, + GP_4_22_FN, FN_IP10_26_24, + GP_4_21_FN, FN_IP10_23_21, + GP_4_20_FN, FN_IP10_20_18, + GP_4_19_FN, FN_IP10_17_15, + GP_4_18_FN, FN_IP10_14_12, + GP_4_17_FN, FN_IP10_11_9, + GP_4_16_FN, FN_IP10_8_6, + GP_4_15_FN, FN_IP10_5_3, + GP_4_14_FN, FN_IP10_2_0, + GP_4_13_FN, FN_IP9_30_28, + GP_4_12_FN, FN_IP9_27_25, + GP_4_11_FN, FN_IP9_24_22, + GP_4_10_FN, FN_IP9_21_19, + GP_4_9_FN, FN_IP9_18_17, + GP_4_8_FN, FN_IP9_16_15, + GP_4_7_FN, FN_IP9_14_12, + GP_4_6_FN, FN_IP9_11_9, + GP_4_5_FN, FN_IP9_8_6, + GP_4_4_FN, FN_IP9_5_3, + GP_4_3_FN, FN_IP9_2_0, + GP_4_2_FN, FN_IP8_31_29, + GP_4_1_FN, FN_IP8_28_26, + GP_4_0_FN, FN_IP8_25_23 } + }, + { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) { + 0, 0, + 0, 0, + 0, 0, + 0, 0, + GP_5_27_FN, FN_USB1_OVC, + GP_5_26_FN, FN_USB1_PWEN, + GP_5_25_FN, FN_USB0_OVC, + GP_5_24_FN, FN_USB0_PWEN, + GP_5_23_FN, FN_IP13_26_24, + GP_5_22_FN, FN_IP13_23_21, + GP_5_21_FN, FN_IP13_20_18, + GP_5_20_FN, FN_IP13_17_15, + GP_5_19_FN, FN_IP13_14_12, + GP_5_18_FN, FN_IP13_11_9, + GP_5_17_FN, FN_IP13_8_6, + GP_5_16_FN, FN_IP13_5_3, + GP_5_15_FN, FN_IP13_2_0, + GP_5_14_FN, FN_IP12_29_27, + GP_5_13_FN, FN_IP12_26_24, + GP_5_12_FN, FN_IP12_23_21, + GP_5_11_FN, FN_IP12_20_18, + GP_5_10_FN, FN_IP12_17_15, + GP_5_9_FN, FN_IP12_14_13, + GP_5_8_FN, FN_IP12_12_11, + GP_5_7_FN, FN_IP12_10_9, + GP_5_6_FN, FN_IP12_8_6, + GP_5_5_FN, FN_IP12_5_3, + GP_5_4_FN, FN_IP12_2_0, + GP_5_3_FN, FN_IP11_29_27, + GP_5_2_FN, FN_IP11_26_24, + GP_5_1_FN, FN_IP11_23_21, + GP_5_0_FN, FN_IP11_20_18 } + }, + { PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1) { + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + GP_6_25_FN, FN_IP0_21_20, + GP_6_24_FN, FN_IP0_19_18, + GP_6_23_FN, FN_IP0_17, + GP_6_22_FN, FN_IP0_16, + GP_6_21_FN, FN_IP0_15, + GP_6_20_FN, FN_IP0_14, + GP_6_19_FN, FN_IP0_13, + GP_6_18_FN, FN_IP0_12, + GP_6_17_FN, FN_IP0_11, + GP_6_16_FN, FN_IP0_10, + GP_6_15_FN, FN_IP0_9_8, + GP_6_14_FN, FN_IP0_0, + GP_6_13_FN, FN_SD1_DATA3, + GP_6_12_FN, FN_SD1_DATA2, + GP_6_11_FN, FN_SD1_DATA1, + GP_6_10_FN, FN_SD1_DATA0, + GP_6_9_FN, FN_SD1_CMD, + GP_6_8_FN, FN_SD1_CLK, + GP_6_7_FN, FN_SD0_WP, + GP_6_6_FN, FN_SD0_CD, + GP_6_5_FN, FN_SD0_DATA3, + GP_6_4_FN, FN_SD0_DATA2, + GP_6_3_FN, FN_SD0_DATA1, + GP_6_2_FN, FN_SD0_DATA0, + GP_6_1_FN, FN_SD0_CMD, + GP_6_0_FN, FN_SD0_CLK } + }, + { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32, + 2, 2, 2, 1, 1, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, + 2, 1, 1, 1, 1, 1, 1, 1, 1) { + /* IP0_31_30 [2] */ + FN_D5, FN_SCIF4_RXD_B, FN_I2C0_SCL_D, 0, + /* IP0_29_28 [2] */ + FN_D4, FN_I2C3_SDA_B, FN_SCIF5_TXD_B, 0, + /* IP0_27_26 [2] */ + FN_D3, FN_I2C3_SCL_B, FN_SCIF5_RXD_B, 0, + /* IP0_25 [1] */ + FN_D2, FN_SCIFA3_TXD_B, + /* IP0_24 [1] */ + FN_D1, FN_SCIFA3_RXD_B, + /* IP0_23_22 [2] */ + FN_D0, FN_SCIFA3_SCK_B, FN_IRQ4, 0, + /* IP0_21_20 [2] */ + FN_MMC_D7, FN_SCIF0_TXD, FN_I2C2_SDA_B, FN_CAN1_TX, + /* IP0_19_18 [2] */ + FN_MMC_D6, FN_SCIF0_RXD, FN_I2C2_SCL_B, FN_CAN1_RX, + /* IP0_17 [1] */ + FN_MMC_D5, FN_SD2_WP, + /* IP0_16 [1] */ + FN_MMC_D4, FN_SD2_CD, + /* IP0_15 [1] */ + FN_MMC_D3, FN_SD2_DATA3, + /* IP0_14 [1] */ + FN_MMC_D2, FN_SD2_DATA2, + /* IP0_13 [1] */ + FN_MMC_D1, FN_SD2_DATA1, + /* IP0_12 [1] */ + FN_MMC_D0, FN_SD2_DATA0, + /* IP0_11 [1] */ + FN_MMC_CMD, FN_SD2_CMD, + /* IP0_10 [1] */ + FN_MMC_CLK, FN_SD2_CLK, + /* IP0_9_8 [2] */ + FN_SD1_WP, FN_IRQ7, FN_CAN0_TX, 0, + /* IP0_7 [1] */ + 0, 0, + /* IP0_6 [1] */ + 0, 0, + /* IP0_5 [1] */ + 0, 0, + /* IP0_4 [1] */ + 0, 0, + /* IP0_3 [1] */ + 0, 0, + /* IP0_2 [1] */ + 0, 0, + /* IP0_1 [1] */ + 0, 0, + /* IP0_0 [1] */ + FN_SD1_CD, FN_CAN0_RX, } + }, + { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32, + 2, 2, 1, 1, 1, 1, 2, 2, 2, 3, 2, 2, 3, 2, 2, + 2, 2) { + /* IP1_31_30 [2] */ + FN_A6, FN_SCIFB0_CTS_N, FN_SCIFA4_RXD_B, FN_TPUTO2_C, + /* IP1_29_28 [2] */ + FN_A5, FN_SCIFB0_RXD, FN_PWM4_B, FN_TPUTO3_C, + /* IP1_27 [1] */ + FN_A4, FN_SCIFB0_TXD, + /* IP1_26 [1] */ + FN_A3, FN_SCIFB0_SCK, + /* IP1_25 [1] */ + 0, 0, + /* IP1_24 [1] */ + FN_A1, FN_SCIFB1_TXD, + /* IP1_23_22 [2] */ + FN_A0, FN_SCIFB1_SCK, FN_PWM3_B, 0, + /* IP1_21_20 [2] */ + FN_D15, FN_SCIFA1_TXD, FN_IIC0_SDA_B, 0, + /* IP1_19_18 [2] */ + FN_D14, FN_SCIFA1_RXD, FN_IIC0_SCL_B, 0, + /* IP1_17_15 [3] */ + FN_D13, FN_SCIFA1_SCK, FN_TANS1, FN_PWM2_C, FN_TCLK2_B, + 0, 0, 0, + /* IP1_14_13 [2] */ + FN_D12, FN_HSCIF2_HRTS_N, FN_SCIF1_TXD_C, FN_I2C1_SDA_D, + /* IP1_12_11 [2] */ + FN_D11, FN_HSCIF2_HCTS_N, FN_SCIF1_RXD_C, FN_I2C1_SCL_D, + /* IP1_10_8 [3] */ + FN_D10, FN_HSCIF2_HSCK, FN_SCIF1_SCK_C, FN_IRQ6, FN_PWM5_C, + 0, 0, 0, + /* IP1_7_6 [2] */ + FN_D9, FN_HSCIF2_HTX, FN_I2C1_SDA_B, 0, + /* IP1_5_4 [2] */ + FN_D8, FN_HSCIF2_HRX, FN_I2C1_SCL_B, 0, + /* IP1_3_2 [2] */ + FN_D7, FN_IRQ3, FN_TCLK1, FN_PWM6_B, + /* IP1_1_0 [2] */ + FN_D6, FN_SCIF4_TXD_B, FN_I2C0_SDA_D, 0, } + }, + { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32, + 2, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2) { + /* IP2_31_30 [2] */ + FN_A20, FN_SPCLK, FN_MOUT1, 0, + /* IP2_29_27 [3] */ + FN_A19, FN_MSIOF2_SS2, FN_PWM4, FN_TPUTO2, + FN_MOUT0, 0, 0, 0, + /* IP2_26_24 [3] */ + FN_A18, FN_MSIOF2_SS1, FN_SCIF4_TXD_E, FN_CAN1_TX_B, + FN_AVB_AVTP_MATCH_B, 0, 0, 0, + /* IP2_23_21 [3] */ + FN_A17, FN_MSIOF2_SYNC, FN_SCIF4_RXD_E, FN_CAN1_RX_B, + FN_AVB_AVTP_CAPTURE_B, 0, 0, 0, + /* IP2_20_18 [3] */ + FN_A16, FN_MSIOF2_SCK, FN_HSCIF0_HSCK_B, FN_SPEEDIN, + FN_VSP, FN_CAN_CLK_C, FN_TPUTO2_B, 0, + /* IP2_17_16 [2] */ + FN_A15, FN_MSIOF2_TXD, FN_HSCIF0_HTX_B, FN_DACK1, + /* IP2_15_14 [2] */ + FN_A14, FN_MSIOF2_RXD, FN_HSCIF0_HRX_B, FN_DREQ1_N, + /* IP2_13_12 [2] */ + FN_A13, FN_MSIOF1_SS2, FN_SCIFA5_TXD_B, 0, + /* IP2_11_10 [2] */ + FN_A12, FN_MSIOF1_SS1, FN_SCIFA5_RXD_B, 0, + /* IP2_9_8 [2] */ + FN_A11, FN_MSIOF1_SYNC, FN_IIC1_SDA_B, 0, + /* IP2_7_6 [2] */ + FN_A10, FN_MSIOF1_SCK, FN_IIC1_SCL_B, 0, + /* IP2_5_4 [2] */ + FN_A9, FN_MSIOF1_TXD, FN_SCIFA0_TXD_B, 0, + /* IP2_3_2 [2] */ + FN_A8, FN_MSIOF1_RXD, FN_SCIFA0_RXD_B, 0, + /* IP2_1_0 [2] */ + FN_A7, FN_SCIFB0_RTS_N, FN_SCIFA4_TXD_B, 0, } + }, + { PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32, + 1, 1, 3, 3, 3, 3, 3, 2, 1, 1, 1, 2, 2, 2, 2, 2) { + /* IP3_31 [1] */ + FN_RD_WR_N, FN_ATAG1_N, + /* IP3_30 [1] */ + FN_RD_N, FN_ATACS11_N, + /* IP3_29_27 [3] */ + FN_BS_N, FN_DRACK0, FN_PWM1_C, FN_TPUTO0_C, FN_ATACS01_N, + FN_MTS_N_B, 0, 0, + /* IP3_26_24 [3] */ + FN_EX_CS5_N, FN_SCIFA2_TXD, FN_I2C2_SDA_E, FN_TS_SPSYNC_B, + FN_RIF0_D1, FN_FMIN, FN_SCIFB2_RTS_N, FN_STM_N_B, + /* IP3_23_21 [3] */ + FN_EX_CS4_N, FN_SCIFA2_RXD, FN_I2C2_SCL_E, FN_TS_SDEN_B, + FN_RIF0_D0, FN_FMCLK, FN_SCIFB2_CTS_N, FN_SCKZ_B, + /* IP3_20_18 [3] */ + FN_EX_CS3_N, FN_SCIFA2_SCK, FN_SCIF4_TXD_C, FN_TS_SCK_B, + FN_RIF0_CLK, FN_BPFCLK, FN_SCIFB2_SCK, FN_MDATA_B, + /* IP3_17_15 [3] */ + FN_EX_CS2_N, FN_PWM0, FN_SCIF4_RXD_C, FN_TS_SDATA_B, + FN_RIF0_SYNC, FN_TPUTO3, FN_SCIFB2_TXD, FN_SDATA_B, + /* IP3_14_13 [2] */ + FN_EX_CS1_N, FN_TPUTO3_B, FN_SCIFB2_RXD, FN_VI1_DATA11, + /* IP3_12 [1] */ + FN_EX_CS0_N, FN_VI1_DATA10, + /* IP3_11 [1] */ + FN_CS1_N_A26, FN_VI1_DATA9, + /* IP3_10 [1] */ + FN_CS0_N, FN_VI1_DATA8, + /* IP3_9_8 [2] */ + FN_A25, FN_SSL, FN_ATARD1_N, 0, + /* IP3_7_6 [2] */ + FN_A24, FN_IO3, FN_EX_WAIT2, 0, + /* IP3_5_4 [2] */ + FN_A23, FN_IO2, FN_MOUT6, FN_ATAWR1_N, + /* IP3_3_2 [2] */ + FN_A22, FN_MISO_IO1, FN_MOUT5, FN_ATADIR1_N, + /* IP3_1_0 [2] */ + FN_A21, FN_MOSI_IO0, FN_MOUT2, 0, } + }, + { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32, + 2, 2, 2, 3, 3, 2, 2, 2, 2, 2, 2, 3, 3, 2) { + /* IP4_31_30 [2] */ + FN_DU0_DG4, FN_LCDOUT12, FN_CC50_STATE12, 0, + /* IP4_29_28 [2] */ + FN_DU0_DG3, FN_LCDOUT11, FN_CC50_STATE11, 0, + /* IP4_27_26 [2] */ + FN_DU0_DG2, FN_LCDOUT10, FN_CC50_STATE10, 0, + /* IP4_25_23 [3] */ + FN_DU0_DG1, FN_LCDOUT9, FN_SCIFA0_TXD_C, FN_I2C3_SDA_D, + FN_CC50_STATE9, 0, 0, 0, + /* IP4_22_20 [3] */ + FN_DU0_DG0, FN_LCDOUT8, FN_SCIFA0_RXD_C, FN_I2C3_SCL_D, + FN_CC50_STATE8, 0, 0, 0, + /* IP4_19_18 [2] */ + FN_DU0_DR7, FN_LCDOUT23, FN_CC50_STATE7, 0, + /* IP4_17_16 [2] */ + FN_DU0_DR6, FN_LCDOUT22, FN_CC50_STATE6, 0, + /* IP4_15_14 [2] */ + FN_DU0_DR5, FN_LCDOUT21, FN_CC50_STATE5, 0, + /* IP4_13_12 [2] */ + FN_DU0_DR4, FN_LCDOUT20, FN_CC50_STATE4, 0, + /* IP4_11_10 [2] */ + FN_DU0_DR3, FN_LCDOUT19, FN_CC50_STATE3, 0, + /* IP4_9_8 [2] */ + FN_DU0_DR2, FN_LCDOUT18, FN_CC50_STATE2, 0, + /* IP4_7_5 [3] */ + FN_DU0_DR1, FN_LCDOUT17, FN_SCIF5_TXD_C, FN_I2C2_SDA_D, + FN_CC50_STATE1, 0, 0, 0, + /* IP4_4_2 [3] */ + FN_DU0_DR0, FN_LCDOUT16, FN_SCIF5_RXD_C, FN_I2C2_SCL_D, + FN_CC50_STATE0, 0, 0, 0, + /* IP4_1_0 [2] */ + FN_EX_WAIT0, FN_CAN_CLK_B, FN_SCIF_CLK, FN_PWMFSW0, } + }, + { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32, + 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 3, 3, 2, 2, 2) { + /* IP5_31_30 [2] */ + FN_DU0_EXHSYNC_DU0_HSYNC, FN_QSTH_QHS, FN_CC50_STATE27, 0, + /* IP5_29_28 [2] */ + FN_DU0_DOTCLKOUT1, FN_QSTVB_QVE, FN_CC50_STATE26, 0, + /* IP5_27_26 [2] */ + FN_DU0_DOTCLKOUT0, FN_QCLK, FN_CC50_STATE25, 0, + /* IP5_25_24 [2] */ + FN_DU0_DOTCLKIN, FN_QSTVA_QVS, FN_CC50_STATE24, 0, + /* IP5_23_22 [2] */ + FN_DU0_DB7, FN_LCDOUT7, FN_CC50_STATE23, 0, + /* IP5_21_20 [2] */ + FN_DU0_DB6, FN_LCDOUT6, FN_CC50_STATE22, 0, + /* IP5_19_18 [2] */ + FN_DU0_DB5, FN_LCDOUT5, FN_CC50_STATE21, 0, + /* IP5_17_16 [2] */ + FN_DU0_DB4, FN_LCDOUT4, FN_CC50_STATE20, 0, + /* IP5_15_14 [2] */ + FN_DU0_DB3, FN_LCDOUT3, FN_CC50_STATE19, 0, + /* IP5_13_12 [2] */ + FN_DU0_DB2, FN_LCDOUT2, FN_CC50_STATE18, 0, + /* IP5_11_9 [3] */ + FN_DU0_DB1, FN_LCDOUT1, FN_SCIFA4_TXD_C, FN_I2C4_SDA_D, + FN_CAN0_TX_C, FN_CC50_STATE17, 0, 0, + /* IP5_8_6 [3] */ + FN_DU0_DB0, FN_LCDOUT0, FN_SCIFA4_RXD_C, FN_I2C4_SCL_D, + FN_CAN0_RX_C, FN_CC50_STATE16, 0, 0, + /* IP5_5_4 [2] */ + FN_DU0_DG7, FN_LCDOUT15, FN_CC50_STATE15, 0, + /* IP5_3_2 [2] */ + FN_DU0_DG6, FN_LCDOUT14, FN_CC50_STATE14, 0, + /* IP5_1_0 [2] */ + FN_DU0_DG5, FN_LCDOUT13, FN_CC50_STATE13, 0, } + }, + { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32, + 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, + 2, 2) { + /* IP6_31_29 [3] */ + FN_ETH_MDIO, FN_VI0_G0, FN_MSIOF2_RXD_B, FN_IIC0_SCL_D, + FN_AVB_TX_CLK, FN_ADIDATA, FN_AD_DI, 0, + /* IP6_28_26 [3] */ + FN_VI0_VSYNC_N, FN_SCIF0_TXD_B, FN_I2C0_SDA_C, + FN_AUDIO_CLKOUT_B, FN_AVB_TX_EN, 0, 0, 0, + /* IP6_25_23 [3] */ + FN_VI0_HSYNC_N, FN_SCIF0_RXD_B, FN_I2C0_SCL_C, FN_IERX_C, + FN_AVB_COL, 0, 0, 0, + /* IP6_22_20 [3] */ + FN_VI0_FIELD, FN_I2C3_SDA, FN_SCIFA5_TXD_C, FN_IECLK_C, + FN_AVB_RX_ER, 0, 0, 0, + /* IP6_19_17 [3] */ + FN_VI0_CLKENB, FN_I2C3_SCL, FN_SCIFA5_RXD_C, FN_IETX_C, + FN_AVB_RXD7, 0, 0, 0, + /* IP6_16 [1] */ + FN_VI0_DATA7_VI0_B7, FN_AVB_RXD6, + /* IP6_15 [1] */ + FN_VI0_DATA6_VI0_B6, FN_AVB_RXD5, + /* IP6_14 [1] */ + FN_VI0_DATA5_VI0_B5, FN_AVB_RXD4, + /* IP6_13 [1] */ + FN_VI0_DATA4_VI0_B4, FN_AVB_RXD3, + /* IP6_12 [1] */ + FN_VI0_DATA3_VI0_B3, FN_AVB_RXD2, + /* IP6_11 [1] */ + FN_VI0_DATA2_VI0_B2, FN_AVB_RXD1, + /* IP6_10 [1] */ + FN_VI0_DATA1_VI0_B1, FN_AVB_RXD0, + /* IP6_9 [1] */ + FN_VI0_DATA0_VI0_B0, FN_AVB_RX_DV, + /* IP6_8 [1] */ + FN_VI0_CLK, FN_AVB_RX_CLK, + /* IP6_7_6 [2] */ + FN_DU0_CDE, FN_QPOLB, FN_CC50_STATE31, 0, + /* IP6_5_4 [2] */ + FN_DU0_DISP, FN_QPOLA, FN_CC50_STATE30, 0, + /* IP6_3_2 [2] */ + FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE, FN_CC50_STATE29, + /* IP6_1_0 [2] */ + FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE, FN_CC50_STATE28, 0, } + }, + { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32, + 1, 1, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3) { + /* IP7_31 [1] */ + FN_DREQ0_N, FN_SCIFB1_RXD, + /* IP7_30 [1] */ + 0, 0, + /* IP7_29_27 [3] */ + FN_ETH_TXD0, FN_VI0_R2, FN_SCIF3_RXD_B, FN_I2C4_SCL_E, + FN_AVB_GTX_CLK, FN_SSI_WS6_B, 0, 0, + /* IP7_26_24 [3] */ + FN_ETH_MAGIC, FN_VI0_R1, FN_SCIF3_SCK_B, FN_AVB_TX_ER, + FN_SSI_SCK6_B, 0, 0, 0, + /* IP7_23_21 [3] */ + FN_ETH_TX_EN, FN_VI0_R0, FN_SCIF2_TXD_C, FN_IIC1_SDA_D, + FN_AVB_TXD7, FN_SSI_SDATA5_B, 0, 0, + /* IP7_20_18 [3] */ + FN_ETH_TXD1, FN_VI0_G7, FN_SCIF2_RXD_C, FN_IIC1_SCL_D, + FN_AVB_TXD6, FN_SSI_WS5_B, 0, 0, + /* IP7_17_15 [3] */ + FN_ETH_REFCLK, FN_VI0_G6, FN_SCIF2_SCK_C, FN_AVB_TXD5, + FN_SSI_SCK5_B, 0, 0, 0, + /* IP7_14_12 [3] */ + FN_ETH_LINK, FN_VI0_G5, FN_MSIOF2_SS2_B, FN_SCIF4_TXD_D, + FN_AVB_TXD4, FN_ADICHS2, 0, 0, + /* IP7_11_9 [3] */ + FN_ETH_RXD1, FN_VI0_G4, FN_MSIOF2_SS1_B, FN_SCIF4_RXD_D, + FN_AVB_TXD3, FN_ADICHS1, 0, 0, + /* IP7_8_6 [3] */ + FN_ETH_RXD0, FN_VI0_G3, FN_MSIOF2_SYNC_B, FN_CAN0_TX_B, + FN_AVB_TXD2, FN_ADICHS0, FN_AD_NCS_N, 0, + /* IP7_5_3 [3] */ + FN_ETH_RX_ER, FN_VI0_G2, FN_MSIOF2_SCK_B, FN_CAN0_RX_B, + FN_AVB_TXD1, FN_ADICLK, FN_AD_CLK, 0, + /* IP7_2_0 [3] */ + FN_ETH_CRS_DV, FN_VI0_G1, FN_MSIOF2_TXD_B, FN_IIC0_SDA_D, + FN_AVB_TXD0, FN_ADICS_SAMP, FN_AD_DO, 0, } + }, + { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32, + 3, 3, 3, 3, 3, 2, 3, 3, 3, 3, 3) { + /* IP8_31_29 [3] */ + FN_MSIOF0_RXD, FN_SCIF5_RXD, FN_I2C2_SCL_C, FN_DU1_DR2, + FN_RIF1_D0_B, FN_TS_SDEN_D, FN_FMCLK_C, FN_RDS_CLK, + /* IP8_28_26 [3] */ + FN_I2C1_SDA, FN_SCIF4_TXD, FN_IRQ5, FN_DU1_DR1, + FN_RIF1_CLK_B, FN_TS_SCK_D, FN_BPFCLK_C, 0, + /* IP8_25_23 [3] */ + FN_I2C1_SCL, FN_SCIF4_RXD, FN_PWM5_B, FN_DU1_DR0, + FN_RIF1_SYNC_B, FN_TS_SDATA_D, FN_TPUTO1_B, 0, + /* IP8_22_20 [3] */ + FN_I2C0_SDA, FN_SCIF0_TXD_C, FN_TPUTO0, FN_CAN_CLK, + FN_DVC_MUTE, FN_CAN1_TX_D, 0, 0, + /* IP8_19_17 [3] */ + FN_I2C0_SCL, FN_SCIF0_RXD_C, FN_PWM5, FN_TCLK1_B, + FN_AVB_GTXREFCLK, FN_CAN1_RX_D, FN_TPUTO0_B, 0, + /* IP8_16_15 [2] */ + FN_HSCIF0_HSCK, FN_SCIF_CLK_B, FN_AVB_CRS, FN_AUDIO_CLKC_B, + /* IP8_14_12 [3] */ + FN_HSCIF0_HRTS_N, FN_VI0_R7, FN_SCIF0_TXD_D, FN_I2C0_SDA_E, + FN_AVB_PHY_INT, FN_SSI_SDATA8_B, 0, 0, + /* IP8_11_9 [3] */ + FN_HSCIF0_HCTS_N, FN_VI0_R6, FN_SCIF0_RXD_D, FN_I2C0_SCL_E, + FN_AVB_MAGIC, FN_SSI_SDATA7_B, 0, 0, + /* IP8_8_6 [3] */ + FN_HSCIF0_HTX, FN_VI0_R5, FN_I2C1_SDA_C, FN_AUDIO_CLKB_B, + FN_AVB_LINK, FN_SSI_WS78_B, 0, 0, + /* IP8_5_3 [3] */ + FN_HSCIF0_HRX, FN_VI0_R4, FN_I2C1_SCL_C, FN_AUDIO_CLKA_B, + FN_AVB_MDIO, FN_SSI_SCK78_B, 0, 0, + /* IP8_2_0 [3] */ + FN_ETH_MDC, FN_VI0_R3, FN_SCIF3_TXD_B, FN_I2C4_SDA_E, + FN_AVB_MDC, FN_SSI_SDATA6_B, 0, 0, } + }, + { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32, + 1, 3, 3, 3, 3, 2, 2, 3, 3, 3, 3, 3, 3) { + /* IP9_31 [1] */ + 0, 0, + /* IP9_30_28 [3] */ + FN_SCIF1_SCK, FN_PWM3, FN_TCLK2, FN_DU1_DG5, + FN_SSI_SDATA1_B, FN_CAN_TXCLK, FN_CC50_STATE34, 0, + /* IP9_27_25 [3] */ + FN_HSCIF1_HRTS_N, FN_SCIFA4_TXD, FN_IERX, FN_DU1_DG4, + FN_SSI_WS1_B, FN_CAN_STEP0, FN_CC50_STATE33, 0, + /* IP9_24_22 [3] */ + FN_HSCIF1_HCTS_N, FN_SCIFA4_RXD, FN_IECLK, FN_DU1_DG3, + FN_SSI_SCK1_B, FN_CAN_DEBUG_HW_TRIGGER, FN_CC50_STATE32, 0, + /* IP9_21_19 [3] */ + FN_HSCIF1_HSCK, FN_PWM2, FN_IETX, FN_DU1_DG2, + FN_REMOCON_B, FN_SPEEDIN_B, FN_VSP_B, 0, + /* IP9_18_17 [2] */ + FN_HSCIF1_HTX, FN_I2C4_SDA, FN_TPUTO1, FN_DU1_DG1, + /* IP9_16_15 [2] */ + FN_HSCIF1_HRX, FN_I2C4_SCL, FN_PWM6, FN_DU1_DG0, + /* IP9_14_12 [3] */ + FN_MSIOF0_SS2, FN_SCIFA0_TXD, FN_TS_SPSYNC, FN_DU1_DR7, + FN_RIF1_D1, FN_FMIN_B, FN_RDS_DATA_B, 0, + /* IP9_11_9 [3] */ + FN_MSIOF0_SS1, FN_SCIFA0_RXD, FN_TS_SDEN, FN_DU1_DR6, + FN_RIF1_D0, FN_FMCLK_B, FN_RDS_CLK_B, 0, + /* IP9_8_6 [3] */ + FN_MSIOF0_SYNC, FN_PWM1, FN_TS_SCK, FN_DU1_DR5, + FN_RIF1_CLK, FN_BPFCLK_B, 0, 0, + /* IP9_5_3 [3] */ + FN_MSIOF0_SCK, FN_IRQ0, FN_TS_SDATA, FN_DU1_DR4, + FN_RIF1_SYNC, FN_TPUTO1_C, 0, 0, + /* IP9_2_0 [3] */ + FN_MSIOF0_TXD, FN_SCIF5_TXD, FN_I2C2_SDA_C, FN_DU1_DR3, + FN_RIF1_D1_B, FN_TS_SPSYNC_D, FN_FMIN_C, FN_RDS_DATA, } + }, + { PINMUX_CFG_REG_VAR("IPSR10", 0xE6060048, 32, + 2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3) { + /* IP10_31_30 [2] */ + FN_SSI_SCK5, FN_SCIFA3_SCK, FN_DU1_DOTCLKIN, FN_CAN_DEBUGOUT10, + /* IP10_29_27 [3] */ + FN_I2C2_SDA, FN_SCIFA5_TXD, FN_DU1_DB7, FN_AUDIO_CLKOUT_C, + FN_CAN_DEBUGOUT9, 0, 0, 0, + /* IP10_26_24 [3] */ + FN_I2C2_SCL, FN_SCIFA5_RXD, FN_DU1_DB6, FN_AUDIO_CLKC_C, + FN_SSI_SDATA4_B, FN_CAN_DEBUGOUT8, 0, 0, + /* IP10_23_21 [3] */ + FN_SCIF3_TXD, FN_I2C1_SDA_E, FN_FMIN_D, FN_DU1_DB5, + FN_AUDIO_CLKB_C, FN_SSI_WS4_B, FN_CAN_DEBUGOUT7, FN_RDS_DATA_C, + /* IP10_20_18 [3] */ + FN_SCIF3_RXD, FN_I2C1_SCL_E, FN_FMCLK_D, FN_DU1_DB4, + FN_AUDIO_CLKA_C, FN_SSI_SCK4_B, FN_CAN_DEBUGOUT6, FN_RDS_CLK_C, + /* IP10_17_15 [3] */ + FN_SCIF3_SCK, FN_IRQ2, FN_BPFCLK_D, FN_DU1_DB3, + FN_SSI_SDATA9_B, FN_TANS2, FN_CAN_DEBUGOUT5, FN_CC50_OSCOUT, + /* IP10_14_12 [3] */ + FN_SCIF2_SCK, FN_IRQ1, FN_DU1_DB2, FN_SSI_WS9_B, + FN_USB0_IDIN, FN_CAN_DEBUGOUT4, FN_CC50_STATE39, 0, + /* IP10_11_9 [3] */ + FN_SCIF2_TXD, FN_IIC1_SDA, FN_DU1_DB1, FN_SSI_SCK9_B, + FN_USB0_OVC1, FN_CAN_DEBUGOUT3, FN_CC50_STATE38, 0, + /* IP10_8_6 [3] */ + FN_SCIF2_RXD, FN_IIC1_SCL, FN_DU1_DB0, FN_SSI_SDATA2_B, + FN_USB0_EXTLP, FN_CAN_DEBUGOUT2, FN_CC50_STATE37, 0, + /* IP10_5_3 [3] */ + FN_SCIF1_TXD, FN_IIC0_SDA, FN_DU1_DG7, FN_SSI_WS2_B, + FN_CAN_DEBUGOUT1, FN_CC50_STATE36, 0, 0, + /* IP10_2_0 [3] */ + FN_SCIF1_RXD, FN_IIC0_SCL, FN_DU1_DG6, FN_SSI_SCK2_B, + FN_CAN_DEBUGOUT0, FN_CC50_STATE35, 0, 0, } + }, + { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32, + 2, 3, 3, 3, 3, 2, 2, 3, 3, 2, 3, 3) { + /* IP11_31_30 [2] */ + 0, 0, 0, 0, + /* IP11_29_27 [3] */ + FN_SSI_SDATA0, FN_MSIOF1_SCK_B, FN_PWM0_B, FN_ADICLK_B, + FN_AD_CLK_B, 0, 0, 0, + /* IP11_26_24 [3] */ + FN_SSI_WS0129, FN_MSIOF1_TXD_B, FN_SCIF5_TXD_D, FN_ADICS_SAMP_B, + FN_AD_DO_B, 0, 0, 0, + /* IP11_23_21 [3] */ + FN_SSI_SCK0129, FN_MSIOF1_RXD_B, FN_SCIF5_RXD_D, FN_ADIDATA_B, + FN_AD_DI_B, FN_PCMWE_N, 0, 0, + /* IP11_20_18 [3] */ + FN_SSI_SDATA7, FN_SCIFA2_TXD_B, FN_IRQ8, FN_AUDIO_CLKA_D, + FN_CAN_CLK_D, FN_PCMOE_N, 0, 0, + /* IP11_17_16 [2] */ + FN_SSI_WS78, FN_SCIFA2_RXD_B, FN_IIC0_SCL_C, FN_DU1_CDE, + /* IP11_15_14 [2] */ + FN_SSI_SCK78, FN_SCIFA2_SCK_B, FN_IIC0_SDA_C, FN_DU1_DISP, + /* IP11_13_11 [3] */ + FN_SSI_SDATA6, FN_SCIFA1_TXD_B, FN_I2C4_SDA_C, + FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_CAN_DEBUGOUT15, 0, 0, 0, + /* IP11_10_8 [3] */ + FN_SSI_WS6, FN_SCIFA1_RXD_B, FN_I2C4_SCL_C, + FN_DU1_EXVSYNC_DU1_VSYNC, FN_CAN_DEBUGOUT14, 0, 0, 0, + /* IP11_7_6 [2] */ + FN_SSI_SCK6, FN_SCIFA1_SCK_B, FN_DU1_EXHSYNC_DU1_HSYNC, + FN_CAN_DEBUGOUT13, + /* IP11_5_3 [3] */ + FN_SSI_SDATA5, FN_SCIFA3_TXD, FN_I2C3_SDA_C, FN_DU1_DOTCLKOUT1, + FN_CAN_DEBUGOUT12, 0, 0, 0, + /* IP11_2_0 [3] */ + FN_SSI_WS5, FN_SCIFA3_RXD, FN_I2C3_SCL_C, FN_DU1_DOTCLKOUT0, + FN_CAN_DEBUGOUT11, 0, 0, 0, } + }, + { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32, + 2, 3, 3, 3, 3, 3, 2, 2, 2, 3, 3, 3) { + /* IP12_31_30 [2] */ + 0, 0, 0, 0, + /* IP12_29_27 [3] */ + FN_SSI_SCK2, FN_HSCIF1_HTX_B, FN_VI1_DATA2, FN_MDATA, + FN_ATAWR0_N, FN_ETH_RXD1_B, 0, 0, + /* IP12_26_24 [3] */ + FN_SSI_SDATA1, FN_HSCIF1_HRX_B, FN_VI1_DATA1, FN_SDATA, + FN_ATAG0_N, FN_ETH_RXD0_B, 0, 0, + /* IP12_23_21 [3] */ + FN_SSI_WS1, FN_SCIF1_TXD_B, FN_IIC1_SDA_C, FN_VI1_DATA0, + FN_CAN0_TX_D, FN_AVB_AVTP_MATCH, FN_ETH_RX_ER_B, 0, + /* IP12_20_18 [3] */ + FN_SSI_SCK1, FN_SCIF1_RXD_B, FN_IIC1_SCL_C, FN_VI1_CLK, + FN_CAN0_RX_D, FN_AVB_AVTP_CAPTURE, FN_ETH_CRS_DV_B, 0, + /* IP12_17_15 [3] */ + FN_SSI_SDATA8, FN_SCIF1_SCK_B, FN_PWM1_B, FN_IRQ9, + FN_REMOCON, FN_DACK2, FN_ETH_MDIO_B, 0, + /* IP12_14_13 [2] */ + FN_SSI_SDATA4, FN_MLB_DAT, FN_IERX_B, FN_IRD_SCK, + /* IP12_12_11 [2] */ + FN_SSI_WS4, FN_MLB_SIG, FN_IECLK_B, FN_IRD_RX, + /* IP12_10_9 [2] */ + FN_SSI_SCK4, FN_MLB_CLK, FN_IETX_B, FN_IRD_TX, + /* IP12_8_6 [3] */ + FN_SSI_SDATA3, FN_MSIOF1_SS2_B, FN_SCIFA1_TXD_C, FN_ADICHS2_B, + FN_CAN1_TX_C, FN_DREQ2_N, 0, 0, + /* IP12_5_3 [3] */ + FN_SSI_WS34, FN_MSIOF1_SS1_B, FN_SCIFA1_RXD_C, FN_ADICHS1_B, + FN_CAN1_RX_C, FN_DACK1_B, 0, 0, + /* IP12_2_0 [3] */ + FN_SSI_SCK34, FN_MSIOF1_SYNC_B, FN_SCIFA1_SCK_C, FN_ADICHS0_B, + FN_AD_NCS_N_B, FN_DREQ1_N_B, 0, 0, } + }, + { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32, + 1, 1, 1, 1, 1, 3, 3, 3, 3, 3, 3, 3, 3, 3) { + /* IP13_31 [1] */ + 0, 0, + /* IP13_30 [1] */ + 0, 0, + /* IP13_29 [1] */ + 0, 0, + /* IP13_28 [1] */ + 0, 0, + /* IP13_27 [1] */ + 0, 0, + /* IP13_26_24 [3] */ + FN_AUDIO_CLKOUT, FN_I2C4_SDA_B, FN_SCIFA5_TXD_D, FN_VI1_VSYNC_N, + FN_TS_SPSYNC_C, FN_RIF0_D1_B, FN_FMIN_E, FN_RDS_DATA_D, + /* IP13_23_21 [3] */ + FN_AUDIO_CLKC, FN_I2C4_SCL_B, FN_SCIFA5_RXD_D, FN_VI1_HSYNC_N, + FN_TS_SDEN_C, FN_RIF0_D0_B, FN_FMCLK_E, FN_RDS_CLK_D, + /* IP13_20_18 [3] */ + FN_AUDIO_CLKB, FN_I2C0_SDA_B, FN_SCIFA4_TXD_D, FN_VI1_FIELD, + FN_TS_SCK_C, FN_RIF0_CLK_B, FN_BPFCLK_E, FN_ETH_MDC_B, + /* IP13_17_15 [3] */ + FN_AUDIO_CLKA, FN_I2C0_SCL_B, FN_SCIFA4_RXD_D, FN_VI1_CLKENB, + FN_TS_SDATA_C, FN_RIF0_SYNC_B, FN_ETH_TXD0_B, 0, + /* IP13_14_12 [3] */ + FN_SSI_SDATA9, FN_SCIF2_TXD_B, FN_I2C3_SDA_E, FN_VI1_DATA7, + FN_ATADIR0_N, FN_ETH_MAGIC_B, 0, 0, + /* IP13_11_9 [3] */ + FN_SSI_WS9, FN_SCIF2_RXD_B, FN_I2C3_SCL_E, FN_VI1_DATA6, + FN_ATARD0_N, FN_ETH_TX_EN_B, 0, 0, + /* IP13_8_6 [3] */ + FN_SSI_SCK9, FN_SCIF2_SCK_B, FN_PWM2_B, FN_VI1_DATA5, + FN_MTS_N, FN_EX_WAIT1, FN_ETH_TXD1_B, 0, + /* IP13_5_3 [2] */ + FN_SSI_SDATA2, FN_HSCIF1_HRTS_N_B, FN_SCIFA0_TXD_D, + FN_VI1_DATA4, FN_STM_N, FN_ATACS10_N, FN_ETH_REFCLK_B, 0, + /* IP13_2_0 [3] */ + FN_SSI_WS2, FN_HSCIF1_HCTS_N_B, FN_SCIFA0_RXD_D, FN_VI1_DATA3, + FN_SCKZ, FN_ATACS00_N, FN_ETH_LINK_B, 0, } + }, + { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32, + 2, 1, 2, 3, 1, 1, 1, 1, 1, 1, 3, 3, 3, 3, 3, + 2, 1) { + /* SEL_ADG [2] */ + FN_SEL_ADG_0, FN_SEL_ADG_1, FN_SEL_ADG_2, FN_SEL_ADG_3, + /* SEL_ADI [1] */ + FN_SEL_ADI_0, FN_SEL_ADI_1, + /* SEL_CAN [2] */ + FN_SEL_CAN_0, FN_SEL_CAN_1, FN_SEL_CAN_2, FN_SEL_CAN_3, + /* SEL_DARC [3] */ + FN_SEL_DARC_0, FN_SEL_DARC_1, FN_SEL_DARC_2, FN_SEL_DARC_3, + FN_SEL_DARC_4, 0, 0, 0, + /* SEL_DR0 [1] */ + FN_SEL_DR0_0, FN_SEL_DR0_1, + /* SEL_DR1 [1] */ + FN_SEL_DR1_0, FN_SEL_DR1_1, + /* SEL_DR2 [1] */ + FN_SEL_DR2_0, FN_SEL_DR2_1, + /* SEL_DR3 [1] */ + FN_SEL_DR3_0, FN_SEL_DR3_1, + /* SEL_ETH [1] */ + FN_SEL_ETH_0, FN_SEL_ETH_1, + /* SLE_FSN [1] */ + FN_SEL_FSN_0, FN_SEL_FSN_1, + /* SEL_IC200 [3] */ + FN_SEL_I2C00_0, FN_SEL_I2C00_1, FN_SEL_I2C00_2, FN_SEL_I2C00_3, + FN_SEL_I2C00_4, 0, 0, 0, + /* SEL_I2C01 [3] */ + FN_SEL_I2C01_0, FN_SEL_I2C01_1, FN_SEL_I2C01_2, FN_SEL_I2C01_3, + FN_SEL_I2C01_4, 0, 0, 0, + /* SEL_I2C02 [3] */ + FN_SEL_I2C02_0, FN_SEL_I2C02_1, FN_SEL_I2C02_2, FN_SEL_I2C02_3, + FN_SEL_I2C02_4, 0, 0, 0, + /* SEL_I2C03 [3] */ + FN_SEL_I2C03_0, FN_SEL_I2C03_1, FN_SEL_I2C03_2, FN_SEL_I2C03_3, + FN_SEL_I2C03_4, 0, 0, 0, + /* SEL_I2C04 [3] */ + FN_SEL_I2C04_0, FN_SEL_I2C04_1, FN_SEL_I2C04_2, FN_SEL_I2C04_3, + FN_SEL_I2C04_4, 0, 0, 0, + /* SEL_IIC00 [2] */ + FN_SEL_IIC00_0, FN_SEL_IIC00_1, FN_SEL_IIC00_2, FN_SEL_IIC00_3, + /* SEL_AVB [1] */ + FN_SEL_AVB_0, FN_SEL_AVB_1, } + }, + { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32, + 2, 2, 1, 1, 1, 1, 1, 1, 2, 2, 1, 1, 2, 2, 1, 1, + 2, 2, 2, 1, 1, 2) { + /* SEL_IEB [2] */ + FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0, + /* SEL_IIC0 [2] */ + FN_SEL_IIC01_0, FN_SEL_IIC01_1, FN_SEL_IIC01_2, FN_SEL_IIC01_3, + /* SEL_LBS [1] */ + FN_SEL_LBS_0, FN_SEL_LBS_1, + /* SEL_MSI1 [1] */ + FN_SEL_MSI1_0, FN_SEL_MSI1_1, + /* SEL_MSI2 [1] */ + FN_SEL_MSI2_0, FN_SEL_MSI2_1, + /* SEL_RAD [1] */ + FN_SEL_RAD_0, FN_SEL_RAD_1, + /* SEL_RCN [1] */ + FN_SEL_RCN_0, FN_SEL_RCN_1, + /* SEL_RSP [1] */ + FN_SEL_RSP_0, FN_SEL_RSP_1, + /* SEL_SCIFA0 [2] */ + FN_SEL_SCIFA0_0, FN_SEL_SCIFA0_1, FN_SEL_SCIFA0_2, + FN_SEL_SCIFA0_3, + /* SEL_SCIFA1 [2] */ + FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, 0, + /* SEL_SCIFA2 [1] */ + FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, + /* SEL_SCIFA3 [1] */ + FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1, + /* SEL_SCIFA4 [2] */ + FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2, + FN_SEL_SCIFA4_3, + /* SEL_SCIFA5 [2] */ + FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2, + FN_SEL_SCIFA5_3, + /* SEL_SPDM [1] */ + FN_SEL_SPDM_0, FN_SEL_SPDM_1, + /* SEL_TMU [1] */ + FN_SEL_TMU_0, FN_SEL_TMU_1, + /* SEL_TSIF0 [2] */ + FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3, + /* SEL_CAN0 [2] */ + FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3, + /* SEL_CAN1 [2] */ + FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3, + /* SEL_HSCIF0 [1] */ + FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, + /* SEL_HSCIF1 [1] */ + FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, + /* SEL_RDS [2] */ + FN_SEL_RDS_0, FN_SEL_RDS_1, FN_SEL_RDS_2, FN_SEL_RDS_3, } + }, + { PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32, + 2, 2, 2, 1, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) { + /* SEL_SCIF0 [2] */ + FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3, + /* SEL_SCIF1 [2] */ + FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, 0, + /* SEL_SCIF2 [2] */ + FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, 0, + /* SEL_SCIF3 [1] */ + FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, + /* SEL_SCIF4 [3] */ + FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, FN_SEL_SCIF4_3, + FN_SEL_SCIF4_4, 0, 0, 0, + /* SEL_SCIF5 [2] */ + FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, FN_SEL_SCIF5_2, FN_SEL_SCIF5_3, + /* SEL_SSI1 [1] */ + FN_SEL_SSI1_0, FN_SEL_SSI1_1, + /* SEL_SSI2 [1] */ + FN_SEL_SSI2_0, FN_SEL_SSI2_1, + /* SEL_SSI4 [1] */ + FN_SEL_SSI4_0, FN_SEL_SSI4_1, + /* SEL_SSI5 [1] */ + FN_SEL_SSI5_0, FN_SEL_SSI5_1, + /* SEL_SSI6 [1] */ + FN_SEL_SSI6_0, FN_SEL_SSI6_1, + /* SEL_SSI7 [1] */ + FN_SEL_SSI7_0, FN_SEL_SSI7_1, + /* SEL_SSI8 [1] */ + FN_SEL_SSI8_0, FN_SEL_SSI8_1, + /* SEL_SSI9 [1] */ + FN_SEL_SSI9_0, FN_SEL_SSI9_1, + /* RESERVED [1] */ + 0, 0, + /* RESERVED [1] */ + 0, 0, + /* RESERVED [1] */ + 0, 0, + /* RESERVED [1] */ + 0, 0, + /* RESERVED [1] */ + 0, 0, + /* RESERVED [1] */ + 0, 0, + /* RESERVED [1] */ + 0, 0, + /* RESERVED [1] */ + 0, 0, + /* RESERVED [1] */ + 0, 0, + /* RESERVED [1] */ + 0, 0, + /* RESERVED [1] */ + 0, 0, + /* RESERVED [1] */ + 0, 0, } + }, + { }, +}; + +const struct sh_pfc_soc_info r8a7794_pinmux_info = { + .name = "r8a77940_pfc", + .unlock_reg = 0xe6060000, /* PMMR */ + + .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, + + .pins = pinmux_pins, + .nr_pins = ARRAY_SIZE(pinmux_pins), + .groups = pinmux_groups, + .nr_groups = ARRAY_SIZE(pinmux_groups), + .functions = pinmux_functions, + .nr_functions = ARRAY_SIZE(pinmux_functions), + + .cfg_regs = pinmux_config_regs, + + .gpio_data = pinmux_data, + .gpio_data_size = ARRAY_SIZE(pinmux_data), +}; -- cgit v0.10.2 From f1f74b640c952e311aebaa594d9d81fecb72cc17 Mon Sep 17 00:00:00 2001 From: Shinobu Uehara Date: Sat, 6 Jun 2015 01:35:54 +0300 Subject: pinctrl: sh-pfc: r8a7794: add MMCIF pin groups Add MMCIF pin groups to R8A7794 PFC driver. Signed-off-by: Shinobu Uehara [Sergei: rebased, renamed, added changelog.] Signed-off-by: Sergei Shtylyov Acked-by: Laurent Pinchart Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7794.c b/drivers/pinctrl/sh-pfc/pfc-r8a7794.c index 0e2686a..4679ca0 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7794.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7794.c @@ -1919,6 +1919,40 @@ static const unsigned int intc_irq9_pins[] = { static const unsigned int intc_irq9_mux[] = { IRQ9_MARK, }; +/* - MMCIF ------------------------------------------------------------------ */ +static const unsigned int mmc_data1_pins[] = { + /* D[0] */ + RCAR_GP_PIN(6, 18), +}; +static const unsigned int mmc_data1_mux[] = { + MMC_D0_MARK, +}; +static const unsigned int mmc_data4_pins[] = { + /* D[0:3] */ + RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19), + RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21), +}; +static const unsigned int mmc_data4_mux[] = { + MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK, +}; +static const unsigned int mmc_data8_pins[] = { + /* D[0:7] */ + RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19), + RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21), + RCAR_GP_PIN(6, 22), RCAR_GP_PIN(6, 23), + RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25), +}; +static const unsigned int mmc_data8_mux[] = { + MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK, + MMC_D4_MARK, MMC_D5_MARK, MMC_D6_MARK, MMC_D7_MARK, +}; +static const unsigned int mmc_ctrl_pins[] = { + /* CLK, CMD */ + RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 17), +}; +static const unsigned int mmc_ctrl_mux[] = { + MMC_CLK_MARK, MMC_CMD_MARK, +}; /* - MSIOF0 ----------------------------------------------------------------- */ static const unsigned int msiof0_clk_pins[] = { /* SCK */ @@ -2683,6 +2717,10 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(intc_irq7), SH_PFC_PIN_GROUP(intc_irq8), SH_PFC_PIN_GROUP(intc_irq9), + SH_PFC_PIN_GROUP(mmc_data1), + SH_PFC_PIN_GROUP(mmc_data4), + SH_PFC_PIN_GROUP(mmc_data8), + SH_PFC_PIN_GROUP(mmc_ctrl), SH_PFC_PIN_GROUP(msiof0_clk), SH_PFC_PIN_GROUP(msiof0_sync), SH_PFC_PIN_GROUP(msiof0_ss1), @@ -2869,6 +2907,13 @@ static const char * const intc_groups[] = { "intc_irq9", }; +static const char * const mmc_groups[] = { + "mmc_data1", + "mmc_data4", + "mmc_data8", + "mmc_ctrl", +}; + static const char * const msiof0_groups[] = { "msiof0_clk", "msiof0_sync", @@ -3035,6 +3080,7 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(i2c3), SH_PFC_FUNCTION(i2c4), SH_PFC_FUNCTION(intc), + SH_PFC_FUNCTION(mmc), SH_PFC_FUNCTION(msiof0), SH_PFC_FUNCTION(msiof1), SH_PFC_FUNCTION(msiof2), -- cgit v0.10.2 From 7ac91bda80a05122ca86240b1da3a68a4cdaa982 Mon Sep 17 00:00:00 2001 From: Shinobu Uehara Date: Sat, 6 Jun 2015 01:36:50 +0300 Subject: pinctrl: sh-pfc: r8a7794: add SDHI pin groups Add SDHI0/1/2 pin groups to R8A7794 PFC driver. Signed-off-by: Shinobu Uehara [Sergei: renamed SD data pins to match the driver, rebased, renamed, added changelog.] Signed-off-by: Sergei Shtylyov Acked-by: Laurent Pinchart Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7794.c b/drivers/pinctrl/sh-pfc/pfc-r8a7794.c index 4679ca0..bfdcac4 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7794.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7794.c @@ -2659,6 +2659,117 @@ static const unsigned int scifb2_ctrl_pins[] = { static const unsigned int scifb2_ctrl_mux[] = { SCIFB2_RTS_N_MARK, SCIFB2_CTS_N_MARK, }; +/* - SDHI0 ------------------------------------------------------------------ */ +static const unsigned int sdhi0_data1_pins[] = { + /* D0 */ + RCAR_GP_PIN(6, 2), +}; +static const unsigned int sdhi0_data1_mux[] = { + SD0_DATA0_MARK, +}; +static const unsigned int sdhi0_data4_pins[] = { + /* D[0:3] */ + RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3), + RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 5), +}; +static const unsigned int sdhi0_data4_mux[] = { + SD0_DATA0_MARK, SD0_DATA1_MARK, SD0_DATA2_MARK, SD0_DATA3_MARK, +}; +static const unsigned int sdhi0_ctrl_pins[] = { + /* CLK, CMD */ + RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1), +}; +static const unsigned int sdhi0_ctrl_mux[] = { + SD0_CLK_MARK, SD0_CMD_MARK, +}; +static const unsigned int sdhi0_cd_pins[] = { + /* CD */ + RCAR_GP_PIN(6, 6), +}; +static const unsigned int sdhi0_cd_mux[] = { + SD0_CD_MARK, +}; +static const unsigned int sdhi0_wp_pins[] = { + /* WP */ + RCAR_GP_PIN(6, 7), +}; +static const unsigned int sdhi0_wp_mux[] = { + SD0_WP_MARK, +}; +/* - SDHI1 ------------------------------------------------------------------ */ +static const unsigned int sdhi1_data1_pins[] = { + /* D0 */ + RCAR_GP_PIN(6, 10), +}; +static const unsigned int sdhi1_data1_mux[] = { + SD1_DATA0_MARK, +}; +static const unsigned int sdhi1_data4_pins[] = { + /* D[0:3] */ + RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 11), + RCAR_GP_PIN(6, 12), RCAR_GP_PIN(6, 13), +}; +static const unsigned int sdhi1_data4_mux[] = { + SD1_DATA0_MARK, SD1_DATA1_MARK, SD1_DATA2_MARK, SD1_DATA3_MARK, +}; +static const unsigned int sdhi1_ctrl_pins[] = { + /* CLK, CMD */ + RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9), +}; +static const unsigned int sdhi1_ctrl_mux[] = { + SD1_CLK_MARK, SD1_CMD_MARK, +}; +static const unsigned int sdhi1_cd_pins[] = { + /* CD */ + RCAR_GP_PIN(6, 14), +}; +static const unsigned int sdhi1_cd_mux[] = { + SD1_CD_MARK, +}; +static const unsigned int sdhi1_wp_pins[] = { + /* WP */ + RCAR_GP_PIN(6, 15), +}; +static const unsigned int sdhi1_wp_mux[] = { + SD1_WP_MARK, +}; +/* - SDHI2 ------------------------------------------------------------------ */ +static const unsigned int sdhi2_data1_pins[] = { + /* D0 */ + RCAR_GP_PIN(6, 18), +}; +static const unsigned int sdhi2_data1_mux[] = { + SD2_DATA0_MARK, +}; +static const unsigned int sdhi2_data4_pins[] = { + /* D[0:3] */ + RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19), + RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21), +}; +static const unsigned int sdhi2_data4_mux[] = { + SD2_DATA0_MARK, SD2_DATA1_MARK, SD2_DATA2_MARK, SD2_DATA3_MARK, +}; +static const unsigned int sdhi2_ctrl_pins[] = { + /* CLK, CMD */ + RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 17), +}; +static const unsigned int sdhi2_ctrl_mux[] = { + SD2_CLK_MARK, SD2_CMD_MARK, +}; +static const unsigned int sdhi2_cd_pins[] = { + /* CD */ + RCAR_GP_PIN(6, 22), +}; +static const unsigned int sdhi2_cd_mux[] = { + SD2_CD_MARK, +}; +static const unsigned int sdhi2_wp_pins[] = { + /* WP */ + RCAR_GP_PIN(6, 23), +}; +static const unsigned int sdhi2_wp_mux[] = { + SD2_WP_MARK, +}; static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(eth_link), @@ -2819,6 +2930,21 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(scifb2_data), SH_PFC_PIN_GROUP(scifb2_clk), SH_PFC_PIN_GROUP(scifb2_ctrl), + SH_PFC_PIN_GROUP(sdhi0_data1), + SH_PFC_PIN_GROUP(sdhi0_data4), + SH_PFC_PIN_GROUP(sdhi0_ctrl), + SH_PFC_PIN_GROUP(sdhi0_cd), + SH_PFC_PIN_GROUP(sdhi0_wp), + SH_PFC_PIN_GROUP(sdhi1_data1), + SH_PFC_PIN_GROUP(sdhi1_data4), + SH_PFC_PIN_GROUP(sdhi1_ctrl), + SH_PFC_PIN_GROUP(sdhi1_cd), + SH_PFC_PIN_GROUP(sdhi1_wp), + SH_PFC_PIN_GROUP(sdhi2_data1), + SH_PFC_PIN_GROUP(sdhi2_data4), + SH_PFC_PIN_GROUP(sdhi2_ctrl), + SH_PFC_PIN_GROUP(sdhi2_cd), + SH_PFC_PIN_GROUP(sdhi2_wp), }; static const char * const eth_groups[] = { @@ -3069,6 +3195,30 @@ static const char * const scifb2_groups[] = { "scifb2_ctrl", }; +static const char * const sdhi0_groups[] = { + "sdhi0_data1", + "sdhi0_data4", + "sdhi0_ctrl", + "sdhi0_cd", + "sdhi0_wp", +}; + +static const char * const sdhi1_groups[] = { + "sdhi1_data1", + "sdhi1_data4", + "sdhi1_ctrl", + "sdhi1_cd", + "sdhi1_wp", +}; + +static const char * const sdhi2_groups[] = { + "sdhi2_data1", + "sdhi2_data4", + "sdhi2_ctrl", + "sdhi2_cd", + "sdhi2_wp", +}; + static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(eth), SH_PFC_FUNCTION(hscif0), @@ -3100,6 +3250,9 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(scifb0), SH_PFC_FUNCTION(scifb1), SH_PFC_FUNCTION(scifb2), + SH_PFC_FUNCTION(sdhi0), + SH_PFC_FUNCTION(sdhi1), + SH_PFC_FUNCTION(sdhi2), }; static const struct pinmux_cfg_reg pinmux_config_regs[] = { -- cgit v0.10.2 From ef17f69f5bf57defa525d958af7aa4848e338b5a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Heiko=20St=C3=BCbner?= Date: Fri, 12 Jun 2015 23:50:11 +0200 Subject: pinctrl: rockchip: generalize perpin driver-strength setting The upcoming support for the RK3368 ARM64 SoC also supports perpin drive strength settings (at different register positions), so generalize the register and offset calculation to easily support this one too. Signed-off-by: Heiko Stuebner Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c index 6e7643f..429a6ee 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -163,6 +163,9 @@ struct rockchip_pin_ctrl { void (*pull_calc_reg)(struct rockchip_pin_bank *bank, int pin_num, struct regmap **regmap, int *reg, u8 *bit); + void (*drv_calc_reg)(struct rockchip_pin_bank *bank, + int pin_num, struct regmap **regmap, + int *reg, u8 *bit); }; struct rockchip_pin_config { @@ -581,7 +584,6 @@ static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, #define RK3288_DRV_BITS_PER_PIN 2 #define RK3288_DRV_PINS_PER_REG 8 #define RK3288_DRV_BANK_STRIDE 16 -static int rk3288_drv_list[] = { 2, 4, 8, 12 }; static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, int pin_num, struct regmap **regmap, @@ -611,14 +613,19 @@ static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, } } -static int rk3288_get_drive(struct rockchip_pin_bank *bank, int pin_num) +static int rockchip_perpin_drv_list[] = { 2, 4, 8, 12 }; + +static int rockchip_get_drive_perpin(struct rockchip_pin_bank *bank, + int pin_num) { + struct rockchip_pinctrl *info = bank->drvdata; + struct rockchip_pin_ctrl *ctrl = info->ctrl; struct regmap *regmap; int reg, ret; u32 data; u8 bit; - rk3288_calc_drv_reg_and_bit(bank, pin_num, ®map, ®, &bit); + ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit); ret = regmap_read(regmap, reg, &data); if (ret) @@ -627,24 +634,25 @@ static int rk3288_get_drive(struct rockchip_pin_bank *bank, int pin_num) data >>= bit; data &= (1 << RK3288_DRV_BITS_PER_PIN) - 1; - return rk3288_drv_list[data]; + return rockchip_perpin_drv_list[data]; } -static int rk3288_set_drive(struct rockchip_pin_bank *bank, int pin_num, - int strength) +static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank, + int pin_num, int strength) { struct rockchip_pinctrl *info = bank->drvdata; + struct rockchip_pin_ctrl *ctrl = info->ctrl; struct regmap *regmap; unsigned long flags; int reg, ret, i; u32 data, rmask; u8 bit; - rk3288_calc_drv_reg_and_bit(bank, pin_num, ®map, ®, &bit); + ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit); ret = -EINVAL; - for (i = 0; i < ARRAY_SIZE(rk3288_drv_list); i++) { - if (rk3288_drv_list[i] == strength) { + for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list); i++) { + if (rockchip_perpin_drv_list[i] == strength) { ret = i; break; } @@ -983,10 +991,11 @@ static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, break; case PIN_CONFIG_DRIVE_STRENGTH: /* rk3288 is the first with per-pin drive-strength */ - if (info->ctrl->type != RK3288) + if (!info->ctrl->drv_calc_reg) return -ENOTSUPP; - rc = rk3288_set_drive(bank, pin - bank->pin_base, arg); + rc = rockchip_set_drive_perpin(bank, + pin - bank->pin_base, arg); if (rc < 0) return rc; break; @@ -1041,10 +1050,10 @@ static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin, break; case PIN_CONFIG_DRIVE_STRENGTH: /* rk3288 is the first with per-pin drive-strength */ - if (info->ctrl->type != RK3288) + if (!info->ctrl->drv_calc_reg) return -ENOTSUPP; - rc = rk3288_get_drive(bank, pin - bank->pin_base); + rc = rockchip_get_drive_perpin(bank, pin - bank->pin_base); if (rc < 0) return rc; @@ -2056,6 +2065,7 @@ static struct rockchip_pin_ctrl rk3288_pin_ctrl = { .grf_mux_offset = 0x0, .pmu_mux_offset = 0x84, .pull_calc_reg = rk3288_calc_pull_reg_and_bit, + .drv_calc_reg = rk3288_calc_drv_reg_and_bit, }; static const struct of_device_id rockchip_pinctrl_dt_match[] = { -- cgit v0.10.2 From daecdc66968f122fe53038ded8cb7abe93e0aa8c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Heiko=20St=C3=BCbner?= Date: Fri, 12 Jun 2015 23:51:01 +0200 Subject: pinctrl: rockchip: add support for the rk3368 The rk3368 is the first ARM64 soc from Rockchip, but seems to share most peripherals with the ARM32 soc, including the pinctrl functionality. The only notable difference is - as with every Rockchip soc - that the offsets in the General Register Files moved around and a split of the pmu section of the rk3288 into pmu and pmugrf (pmu general register files) sections. The pinctrl driver of course only needs the pmugrf registers for controlling the pin settings. Signed-off-by: Heiko Stuebner Signed-off-by: Linus Walleij diff --git a/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt index 388b213..391ef4b 100644 --- a/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt @@ -21,14 +21,15 @@ defined as gpio sub-nodes of the pinmux controller. Required properties for iomux controller: - compatible: one of "rockchip,rk2928-pinctrl", "rockchip,rk3066a-pinctrl" "rockchip,rk3066b-pinctrl", "rockchip,rk3188-pinctrl" - "rockchip,rk3288-pinctrl" + "rockchip,rk3288-pinctrl", "rockchip,rk3368-pinctrl" - rockchip,grf: phandle referencing a syscon providing the "general register files" Optional properties for iomux controller: - rockchip,pmu: phandle referencing a syscon providing the pmu registers as some SoCs carry parts of the iomux controller registers there. - Required for at least rk3188 and rk3288. + Required for at least rk3188 and rk3288. On the rk3368 this should + point to the PMUGRF syscon. Deprecated properties for iomux controller: - reg: first element is the general register space of the iomux controller diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c index 429a6ee..9affcd7 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -63,6 +63,7 @@ enum rockchip_pinctrl_type { RK3066B, RK3188, RK3288, + RK3368, }; /** @@ -613,6 +614,68 @@ static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, } } +#define RK3368_PULL_GRF_OFFSET 0x100 +#define RK3368_PULL_PMU_OFFSET 0x10 + +static void rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, + int pin_num, struct regmap **regmap, + int *reg, u8 *bit) +{ + struct rockchip_pinctrl *info = bank->drvdata; + + /* The first 32 pins of the first bank are located in PMU */ + if (bank->bank_num == 0) { + *regmap = info->regmap_pmu; + *reg = RK3368_PULL_PMU_OFFSET; + + *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); + *bit = pin_num % RK3188_PULL_PINS_PER_REG; + *bit *= RK3188_PULL_BITS_PER_PIN; + } else { + *regmap = info->regmap_base; + *reg = RK3368_PULL_GRF_OFFSET; + + /* correct the offset, as we're starting with the 2nd bank */ + *reg -= 0x10; + *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; + *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); + + *bit = (pin_num % RK3188_PULL_PINS_PER_REG); + *bit *= RK3188_PULL_BITS_PER_PIN; + } +} + +#define RK3368_DRV_PMU_OFFSET 0x20 +#define RK3368_DRV_GRF_OFFSET 0x200 + +static void rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, + int pin_num, struct regmap **regmap, + int *reg, u8 *bit) +{ + struct rockchip_pinctrl *info = bank->drvdata; + + /* The first 32 pins of the first bank are located in PMU */ + if (bank->bank_num == 0) { + *regmap = info->regmap_pmu; + *reg = RK3368_DRV_PMU_OFFSET; + + *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); + *bit = pin_num % RK3288_DRV_PINS_PER_REG; + *bit *= RK3288_DRV_BITS_PER_PIN; + } else { + *regmap = info->regmap_base; + *reg = RK3368_DRV_GRF_OFFSET; + + /* correct the offset, as we're starting with the 2nd bank */ + *reg -= 0x10; + *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; + *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); + + *bit = (pin_num % RK3288_DRV_PINS_PER_REG); + *bit *= RK3288_DRV_BITS_PER_PIN; + } +} + static int rockchip_perpin_drv_list[] = { 2, 4, 8, 12 }; static int rockchip_get_drive_perpin(struct rockchip_pin_bank *bank, @@ -703,6 +766,7 @@ static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num) : PIN_CONFIG_BIAS_DISABLE; case RK3188: case RK3288: + case RK3368: data >>= bit; data &= (1 << RK3188_PULL_BITS_PER_PIN) - 1; @@ -758,6 +822,7 @@ static int rockchip_set_pull(struct rockchip_pin_bank *bank, break; case RK3188: case RK3288: + case RK3368: spin_lock_irqsave(&bank->slock, flags); /* enable the write to the equivalent lower bits */ @@ -935,6 +1000,7 @@ static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl, return pull ? false : true; case RK3188: case RK3288: + case RK3368: return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT); } @@ -2068,6 +2134,29 @@ static struct rockchip_pin_ctrl rk3288_pin_ctrl = { .drv_calc_reg = rk3288_calc_drv_reg_and_bit, }; +static struct rockchip_pin_bank rk3368_pin_banks[] = { + PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU, + IOMUX_SOURCE_PMU, + IOMUX_SOURCE_PMU, + IOMUX_SOURCE_PMU + ), + PIN_BANK(1, 32, "gpio1"), + PIN_BANK(2, 32, "gpio2"), + PIN_BANK(3, 32, "gpio3"), +}; + +static struct rockchip_pin_ctrl rk3368_pin_ctrl = { + .pin_banks = rk3368_pin_banks, + .nr_banks = ARRAY_SIZE(rk3368_pin_banks), + .label = "RK3368-GPIO", + .type = RK3368, + .grf_mux_offset = 0x0, + .pmu_mux_offset = 0x0, + .pull_calc_reg = rk3368_calc_pull_reg_and_bit, + .drv_calc_reg = rk3368_calc_drv_reg_and_bit, +}; + + static const struct of_device_id rockchip_pinctrl_dt_match[] = { { .compatible = "rockchip,rk2928-pinctrl", .data = (void *)&rk2928_pin_ctrl }, @@ -2079,6 +2168,8 @@ static const struct of_device_id rockchip_pinctrl_dt_match[] = { .data = (void *)&rk3188_pin_ctrl }, { .compatible = "rockchip,rk3288-pinctrl", .data = (void *)&rk3288_pin_ctrl }, + { .compatible = "rockchip,rk3368-pinctrl", + .data = (void *)&rk3368_pin_ctrl }, {}, }; MODULE_DEVICE_TABLE(of, rockchip_pinctrl_dt_match); -- cgit v0.10.2