From 776180848b574c9c01217fa958f10843ffce584f Mon Sep 17 00:00:00 2001 From: Ludovic Desroches Date: Wed, 16 Sep 2015 17:36:57 +0200 Subject: pinctrl: introduce driver for Atmel PIO4 controller Add a pinctrl/gpio driver for Atmel PIO4 controller available on SAMA5D2 chip family. Signed-off-by: Ludovic Desroches Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 84dd2ed..b422e4e 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -67,6 +67,19 @@ config PINCTRL_AT91 help Say Y here to enable the at91 pinctrl driver +config PINCTRL_AT91PIO4 + bool "AT91 PIO4 pinctrl driver" + depends on OF + depends on ARCH_AT91 + select PINMUX + select GENERIC_PINCONF + select GPIOLIB + select GPIOLIB_IRQCHIP + select OF_GPIO + help + Say Y here to enable the at91 pinctrl/gpio driver for Atmel PIO4 + controller available on sama5d2 SoC. + config PINCTRL_AMD bool "AMD GPIO pin control" depends on GPIOLIB diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index cad077c..8bed0c2 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -12,6 +12,7 @@ obj-$(CONFIG_PINCTRL_AS3722) += pinctrl-as3722.o obj-$(CONFIG_PINCTRL_BF54x) += pinctrl-adi2-bf54x.o obj-$(CONFIG_PINCTRL_BF60x) += pinctrl-adi2-bf60x.o obj-$(CONFIG_PINCTRL_AT91) += pinctrl-at91.o +obj-$(CONFIG_PINCTRL_AT91PIO4) += pinctrl-at91-pio4.o obj-$(CONFIG_PINCTRL_AMD) += pinctrl-amd.o obj-$(CONFIG_PINCTRL_DIGICOLOR) += pinctrl-digicolor.o obj-$(CONFIG_PINCTRL_FALCON) += pinctrl-falcon.o diff --git a/drivers/pinctrl/pinctrl-at91-pio4.c b/drivers/pinctrl/pinctrl-at91-pio4.c new file mode 100644 index 0000000..6aff632 --- /dev/null +++ b/drivers/pinctrl/pinctrl-at91-pio4.c @@ -0,0 +1,1017 @@ +/* + * Driver for the Atmel PIO4 controller + * + * Copyright (C) 2015 Atmel, + * 2015 Ludovic Desroches + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "core.h" +#include "pinconf.h" +#include "pinctrl-utils.h" + +/* + * Warning: + * In order to not introduce confusion between Atmel PIO groups and pinctrl + * framework groups, Atmel PIO groups will be called banks, line is kept to + * designed the pin id into this bank. + */ + +#define ATMEL_PIO_MSKR 0x0000 +#define ATMEL_PIO_CFGR 0x0004 +#define ATMEL_PIO_CFGR_FUNC_MASK GENMASK(2, 0) +#define ATMEL_PIO_DIR_MASK BIT(8) +#define ATMEL_PIO_PUEN_MASK BIT(9) +#define ATMEL_PIO_PDEN_MASK BIT(10) +#define ATMEL_PIO_IFEN_MASK BIT(12) +#define ATMEL_PIO_IFSCEN_MASK BIT(13) +#define ATMEL_PIO_OPD_MASK BIT(14) +#define ATMEL_PIO_SCHMITT_MASK BIT(15) +#define ATMEL_PIO_CFGR_EVTSEL_MASK GENMASK(26, 24) +#define ATMEL_PIO_CFGR_EVTSEL_FALLING (0 << 24) +#define ATMEL_PIO_CFGR_EVTSEL_RISING (1 << 24) +#define ATMEL_PIO_CFGR_EVTSEL_BOTH (2 << 24) +#define ATMEL_PIO_CFGR_EVTSEL_LOW (3 << 24) +#define ATMEL_PIO_CFGR_EVTSEL_HIGH (4 << 24) +#define ATMEL_PIO_PDSR 0x0008 +#define ATMEL_PIO_LOCKSR 0x000C +#define ATMEL_PIO_SODR 0x0010 +#define ATMEL_PIO_CODR 0x0014 +#define ATMEL_PIO_ODSR 0x0018 +#define ATMEL_PIO_IER 0x0020 +#define ATMEL_PIO_IDR 0x0024 +#define ATMEL_PIO_IMR 0x0028 +#define ATMEL_PIO_ISR 0x002C +#define ATMEL_PIO_IOFR 0x003C + +#define ATMEL_PIO_NPINS_PER_BANK 32 +#define ATMEL_PIO_BANK(pin_id) (pin_id / ATMEL_PIO_NPINS_PER_BANK) +#define ATMEL_PIO_LINE(pin_id) (pin_id % ATMEL_PIO_NPINS_PER_BANK) +#define ATMEL_PIO_BANK_OFFSET 0x40 + +#define ATMEL_GET_PIN_NO(pinfunc) ((pinfunc) & 0xff) +#define ATMEL_GET_PIN_FUNC(pinfunc) ((pinfunc >> 16) & 0xf) +#define ATMEL_GET_PIN_IOSET(pinfunc) ((pinfunc >> 20) & 0xf) + +struct atmel_pioctrl_data { + unsigned nbanks; +}; + +struct atmel_group { + const char *name; + u32 pin; +}; + +struct atmel_pin { + unsigned pin_id; + unsigned mux; + unsigned ioset; + unsigned bank; + unsigned line; + const char *device; +}; + +/** + * struct atmel_pioctrl - Atmel PIO controller (pinmux + gpio) + * @reg_base: base address of the controller. + * @clk: clock of the controller. + * @nbanks: number of PIO groups, it can vary depending on the SoC. + * @pinctrl_dev: pinctrl device registered. + * @groups: groups table to provide group name and pin in the group to pinctrl. + * @group_names: group names table to provide all the group/pin names to + * pinctrl or gpio. + * @pins: pins table used for both pinctrl and gpio. pin_id, bank and line + * fields are set at probe time. Other ones are set when parsing dt + * pinctrl. + * @npins: number of pins. + * @gpio_chip: gpio chip registered. + * @irq_domain: irq domain for the gpio controller. + * @irqs: table containing the hw irq number of the bank. The index of the + * table is the bank id. + * @dev: device entry for the Atmel PIO controller. + * @node: node of the Atmel PIO controller. + */ +struct atmel_pioctrl { + void __iomem *reg_base; + struct clk *clk; + unsigned nbanks; + struct pinctrl_dev *pinctrl_dev; + struct atmel_group *groups; + const char * const *group_names; + struct atmel_pin **pins; + unsigned npins; + struct gpio_chip *gpio_chip; + struct irq_domain *irq_domain; + int *irqs; + struct device *dev; + struct device_node *node; +}; + +static const char * const atmel_functions[] = { + "GPIO", "A", "B", "C", "D", "E", "F", "G" +}; + +/* --- GPIO --- */ +static unsigned int atmel_gpio_read(struct atmel_pioctrl *atmel_pioctrl, + unsigned int bank, unsigned int reg) +{ + return readl_relaxed(atmel_pioctrl->reg_base + + ATMEL_PIO_BANK_OFFSET * bank + reg); +} + +static void atmel_gpio_write(struct atmel_pioctrl *atmel_pioctrl, + unsigned int bank, unsigned int reg, + unsigned int val) +{ + writel_relaxed(val, atmel_pioctrl->reg_base + + ATMEL_PIO_BANK_OFFSET * bank + reg); +} + +static void atmel_gpio_irq_ack(struct irq_data *d) +{ + /* + * Nothing to do, interrupt is cleared when reading the status + * register. + */ +} + +static int atmel_gpio_irq_set_type(struct irq_data *d, unsigned type) +{ + struct atmel_pioctrl *atmel_pioctrl = irq_data_get_irq_chip_data(d); + struct atmel_pin *pin = atmel_pioctrl->pins[d->hwirq]; + unsigned reg; + + atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_MSKR, + BIT(pin->line)); + reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR); + reg &= (~ATMEL_PIO_CFGR_EVTSEL_MASK); + + switch (type) { + case IRQ_TYPE_EDGE_RISING: + __irq_set_handler_locked(d->irq, handle_edge_irq); + reg |= ATMEL_PIO_CFGR_EVTSEL_RISING; + break; + case IRQ_TYPE_EDGE_FALLING: + __irq_set_handler_locked(d->irq, handle_edge_irq); + reg |= ATMEL_PIO_CFGR_EVTSEL_FALLING; + break; + case IRQ_TYPE_EDGE_BOTH: + __irq_set_handler_locked(d->irq, handle_edge_irq); + reg |= ATMEL_PIO_CFGR_EVTSEL_BOTH; + break; + case IRQ_TYPE_LEVEL_LOW: + __irq_set_handler_locked(d->irq, handle_level_irq); + reg |= ATMEL_PIO_CFGR_EVTSEL_LOW; + break; + case IRQ_TYPE_LEVEL_HIGH: + __irq_set_handler_locked(d->irq, handle_level_irq); + reg |= ATMEL_PIO_CFGR_EVTSEL_HIGH; + break; + case IRQ_TYPE_NONE: + default: + return -EINVAL; + } + + atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR, reg); + + return 0; +} + +static void atmel_gpio_irq_mask(struct irq_data *d) +{ + struct atmel_pioctrl *atmel_pioctrl = irq_data_get_irq_chip_data(d); + struct atmel_pin *pin = atmel_pioctrl->pins[d->hwirq]; + + atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_IDR, + BIT(pin->line)); +} + +static void atmel_gpio_irq_unmask(struct irq_data *d) +{ + struct atmel_pioctrl *atmel_pioctrl = irq_data_get_irq_chip_data(d); + struct atmel_pin *pin = atmel_pioctrl->pins[d->hwirq]; + + atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_IER, + BIT(pin->line)); +} + +static struct irq_chip atmel_gpio_irq_chip = { + .name = "GPIO", + .irq_ack = atmel_gpio_irq_ack, + .irq_mask = atmel_gpio_irq_mask, + .irq_unmask = atmel_gpio_irq_unmask, + .irq_set_type = atmel_gpio_irq_set_type, +}; + +static void atmel_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) +{ + struct atmel_pioctrl *atmel_pioctrl = irq_get_handler_data(irq); + struct irq_chip *chip = irq_desc_get_chip(desc); + unsigned long isr; + int n, bank = -1; + + /* Find from which bank is the irq received. */ + for (n = 0; n < atmel_pioctrl->nbanks; n++) { + if (atmel_pioctrl->irqs[n] == irq) { + bank = n; + break; + } + } + + if (bank < 0) { + dev_err(atmel_pioctrl->dev, + "no bank associated to irq %u\n", irq); + return; + } + + chained_irq_enter(chip, desc); + + for (;;) { + isr = (unsigned long)atmel_gpio_read(atmel_pioctrl, bank, + ATMEL_PIO_ISR); + isr &= (unsigned long)atmel_gpio_read(atmel_pioctrl, bank, + ATMEL_PIO_IMR); + if (!isr) + break; + + for_each_set_bit(n, &isr, BITS_PER_LONG) + generic_handle_irq(gpio_to_irq(bank * + ATMEL_PIO_NPINS_PER_BANK + n)); + } + + chained_irq_exit(chip, desc); +} + +static int atmel_gpio_direction_input(struct gpio_chip *chip, unsigned offset) +{ + struct atmel_pioctrl *atmel_pioctrl = dev_get_drvdata(chip->dev); + struct atmel_pin *pin = atmel_pioctrl->pins[offset]; + unsigned reg; + + atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_MSKR, + BIT(pin->line)); + reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR); + reg &= ~ATMEL_PIO_DIR_MASK; + atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR, reg); + + return 0; +} + +static int atmel_gpio_get(struct gpio_chip *chip, unsigned offset) +{ + struct atmel_pioctrl *atmel_pioctrl = dev_get_drvdata(chip->dev); + struct atmel_pin *pin = atmel_pioctrl->pins[offset]; + unsigned reg; + + reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_PDSR); + + return !!(reg & BIT(pin->line)); +} + +static int atmel_gpio_direction_output(struct gpio_chip *chip, unsigned offset, + int value) +{ + struct atmel_pioctrl *atmel_pioctrl = dev_get_drvdata(chip->dev); + struct atmel_pin *pin = atmel_pioctrl->pins[offset]; + unsigned reg; + + atmel_gpio_write(atmel_pioctrl, pin->bank, + value ? ATMEL_PIO_SODR : ATMEL_PIO_CODR, + BIT(pin->line)); + + atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_MSKR, + BIT(pin->line)); + reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR); + reg |= ATMEL_PIO_DIR_MASK; + atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR, reg); + + return 0; +} + +static void atmel_gpio_set(struct gpio_chip *chip, unsigned offset, int val) +{ + struct atmel_pioctrl *atmel_pioctrl = dev_get_drvdata(chip->dev); + struct atmel_pin *pin = atmel_pioctrl->pins[offset]; + + atmel_gpio_write(atmel_pioctrl, pin->bank, + val ? ATMEL_PIO_SODR : ATMEL_PIO_CODR, + BIT(pin->line)); +} + +static int atmel_gpio_to_irq(struct gpio_chip *chip, unsigned offset) +{ + struct atmel_pioctrl *atmel_pioctrl = dev_get_drvdata(chip->dev); + + return irq_find_mapping(atmel_pioctrl->irq_domain, offset); +} + +static struct gpio_chip atmel_gpio_chip = { + .direction_input = atmel_gpio_direction_input, + .get = atmel_gpio_get, + .direction_output = atmel_gpio_direction_output, + .set = atmel_gpio_set, + .to_irq = atmel_gpio_to_irq, + .base = 0, +}; + +/* --- PINCTRL --- */ +static unsigned int atmel_pin_config_read(struct pinctrl_dev *pctldev, + unsigned pin_id) +{ + struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); + unsigned bank = atmel_pioctrl->pins[pin_id]->bank; + unsigned line = atmel_pioctrl->pins[pin_id]->line; + void __iomem *addr = atmel_pioctrl->reg_base + + bank * ATMEL_PIO_BANK_OFFSET; + + writel_relaxed(BIT(line), addr + ATMEL_PIO_MSKR); + /* Have to set MSKR first, to access the right pin CFGR. */ + wmb(); + + return readl_relaxed(addr + ATMEL_PIO_CFGR); +} + +static void atmel_pin_config_write(struct pinctrl_dev *pctldev, + unsigned pin_id, u32 conf) +{ + struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); + unsigned bank = atmel_pioctrl->pins[pin_id]->bank; + unsigned line = atmel_pioctrl->pins[pin_id]->line; + void __iomem *addr = atmel_pioctrl->reg_base + + bank * ATMEL_PIO_BANK_OFFSET; + + writel_relaxed(BIT(line), addr + ATMEL_PIO_MSKR); + /* Have to set MSKR first, to access the right pin CFGR. */ + wmb(); + writel_relaxed(conf, addr + ATMEL_PIO_CFGR); +} + +static int atmel_pctl_get_groups_count(struct pinctrl_dev *pctldev) +{ + struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); + + return atmel_pioctrl->npins; +} + +static const char *atmel_pctl_get_group_name(struct pinctrl_dev *pctldev, + unsigned selector) +{ + struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); + + return atmel_pioctrl->groups[selector].name; +} + +static int atmel_pctl_get_group_pins(struct pinctrl_dev *pctldev, + unsigned selector, const unsigned **pins, + unsigned *num_pins) +{ + struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); + + *pins = (unsigned *)&atmel_pioctrl->groups[selector].pin; + *num_pins = 1; + + return 0; +} + +struct atmel_group *atmel_pctl_find_group_by_pin(struct pinctrl_dev *pctldev, + unsigned pin) +{ + struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); + int i; + + for (i = 0; i < atmel_pioctrl->npins; i++) { + struct atmel_group *grp = atmel_pioctrl->groups + i; + + if (grp->pin == pin) + return grp; + } + + return NULL; +} + +static int atmel_pctl_xlate_pinfunc(struct pinctrl_dev *pctldev, + struct device_node *np, + u32 pinfunc, const char **grp_name, + const char **func_name) +{ + struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); + unsigned pin_id, func_id; + struct atmel_group *grp; + + pin_id = ATMEL_GET_PIN_NO(pinfunc); + func_id = ATMEL_GET_PIN_FUNC(pinfunc); + + if (func_id >= ARRAY_SIZE(atmel_functions)) + return -EINVAL; + + *func_name = atmel_functions[func_id]; + + grp = atmel_pctl_find_group_by_pin(pctldev, pin_id); + if (!grp) + return -EINVAL; + *grp_name = grp->name; + + atmel_pioctrl->pins[pin_id]->mux = func_id; + atmel_pioctrl->pins[pin_id]->ioset = ATMEL_GET_PIN_IOSET(pinfunc); + /* Want the device name not the group one. */ + if (np->parent == atmel_pioctrl->node) + atmel_pioctrl->pins[pin_id]->device = np->name; + else + atmel_pioctrl->pins[pin_id]->device = np->parent->name; + + return 0; +} + +static int atmel_pctl_dt_subnode_to_map(struct pinctrl_dev *pctldev, + struct device_node *np, + struct pinctrl_map **map, + unsigned *reserved_maps, + unsigned *num_maps) +{ + unsigned num_pins, num_configs, reserve; + unsigned long *configs; + struct property *pins; + bool has_config; + u32 pinfunc; + int ret, i; + + pins = of_find_property(np, "pinmux", NULL); + if (!pins) + return -EINVAL; + + ret = pinconf_generic_parse_dt_config(np, pctldev, &configs, + &num_configs); + if (ret < 0) { + dev_err(pctldev->dev, "%s: could not parse node property\n", + of_node_full_name(np)); + return ret; + } + + if (num_configs) + has_config = true; + + num_pins = pins->length / sizeof(u32); + if (!num_pins) { + dev_err(pctldev->dev, "no pins found in node %s\n", + of_node_full_name(np)); + return -EINVAL; + } + + /* + * Reserve maps, at least there is a mux map and an optional conf + * map for each pin. + */ + reserve = 1; + if (has_config && num_pins >= 1) + reserve++; + reserve *= num_pins; + ret = pinctrl_utils_reserve_map(pctldev, map, reserved_maps, num_maps, + reserve); + if (ret < 0) + return ret; + + for (i = 0; i < num_pins; i++) { + const char *group, *func; + + ret = of_property_read_u32_index(np, "pinmux", i, &pinfunc); + if (ret) + return ret; + + ret = atmel_pctl_xlate_pinfunc(pctldev, np, pinfunc, &group, + &func); + if (ret) + return ret; + + pinctrl_utils_add_map_mux(pctldev, map, reserved_maps, num_maps, + group, func); + + if (has_config) { + ret = pinctrl_utils_add_map_configs(pctldev, map, + reserved_maps, num_maps, group, + configs, num_configs, + PIN_MAP_TYPE_CONFIGS_GROUP); + if (ret < 0) + return ret; + } + } + + return 0; +} + +static int atmel_pctl_dt_node_to_map(struct pinctrl_dev *pctldev, + struct device_node *np_config, + struct pinctrl_map **map, + unsigned *num_maps) +{ + struct device_node *np; + unsigned reserved_maps; + int ret; + + *map = NULL; + *num_maps = 0; + reserved_maps = 0; + + /* + * If all the pins of a device have the same configuration (or no one), + * it is useless to add a subnode, so directly parse node referenced by + * phandle. + */ + ret = atmel_pctl_dt_subnode_to_map(pctldev, np_config, map, + &reserved_maps, num_maps); + if (ret) { + for_each_child_of_node(np_config, np) { + ret = atmel_pctl_dt_subnode_to_map(pctldev, np, map, + &reserved_maps, num_maps); + if (ret < 0) + break; + } + } + + if (ret < 0) { + pinctrl_utils_dt_free_map(pctldev, *map, *num_maps); + dev_err(pctldev->dev, "can't create maps for node %s\n", + np_config->full_name); + } + + return ret; +} + +static const struct pinctrl_ops atmel_pctlops = { + .get_groups_count = atmel_pctl_get_groups_count, + .get_group_name = atmel_pctl_get_group_name, + .get_group_pins = atmel_pctl_get_group_pins, + .dt_node_to_map = atmel_pctl_dt_node_to_map, + .dt_free_map = pinctrl_utils_dt_free_map, +}; + +static int atmel_pmx_get_functions_count(struct pinctrl_dev *pctldev) +{ + return ARRAY_SIZE(atmel_functions); +} + +static const char *atmel_pmx_get_function_name(struct pinctrl_dev *pctldev, + unsigned selector) +{ + return atmel_functions[selector]; +} + +static int atmel_pmx_get_function_groups(struct pinctrl_dev *pctldev, + unsigned selector, + const char * const **groups, + unsigned * const num_groups) +{ + struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); + + *groups = atmel_pioctrl->group_names; + *num_groups = atmel_pioctrl->npins; + + return 0; +} + +static int atmel_pmx_set_mux(struct pinctrl_dev *pctldev, + unsigned function, + unsigned group) +{ + struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); + unsigned pin; + u32 conf; + + dev_dbg(pctldev->dev, "enable function %s group %s\n", + atmel_functions[function], atmel_pioctrl->groups[group].name); + + pin = atmel_pioctrl->groups[group].pin; + conf = atmel_pin_config_read(pctldev, pin); + conf &= (~ATMEL_PIO_CFGR_FUNC_MASK); + conf |= (function & ATMEL_PIO_CFGR_FUNC_MASK); + dev_dbg(pctldev->dev, "pin: %u, conf: 0x%08x\n", pin, conf); + atmel_pin_config_write(pctldev, pin, conf); + + return 0; +} + +static const struct pinmux_ops atmel_pmxops = { + .get_functions_count = atmel_pmx_get_functions_count, + .get_function_name = atmel_pmx_get_function_name, + .get_function_groups = atmel_pmx_get_function_groups, + .set_mux = atmel_pmx_set_mux, +}; + +static int atmel_conf_pin_config_group_get(struct pinctrl_dev *pctldev, + unsigned group, + unsigned long *config) +{ + struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); + unsigned param = pinconf_to_config_param(*config), arg = 0; + struct atmel_group *grp = atmel_pioctrl->groups + group; + unsigned pin_id = grp->pin; + u32 res; + + res = atmel_pin_config_read(pctldev, pin_id); + + switch (param) { + case PIN_CONFIG_BIAS_PULL_UP: + if (!(res & ATMEL_PIO_PUEN_MASK)) + return -EINVAL; + arg = 1; + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + if ((res & ATMEL_PIO_PUEN_MASK) || + (!(res & ATMEL_PIO_PDEN_MASK))) + return -EINVAL; + arg = 1; + break; + case PIN_CONFIG_BIAS_DISABLE: + if ((res & ATMEL_PIO_PUEN_MASK) || + ((res & ATMEL_PIO_PDEN_MASK))) + return -EINVAL; + arg = 1; + break; + case PIN_CONFIG_DRIVE_OPEN_DRAIN: + if (!(res & ATMEL_PIO_OPD_MASK)) + return -EINVAL; + arg = 1; + break; + case PIN_CONFIG_INPUT_SCHMITT_ENABLE: + if (!(res & ATMEL_PIO_SCHMITT_MASK)) + return -EINVAL; + arg = 1; + break; + default: + return -ENOTSUPP; + } + + *config = pinconf_to_config_packed(param, arg); + return 0; +} + +static int atmel_conf_pin_config_group_set(struct pinctrl_dev *pctldev, + unsigned group, + unsigned long *configs, + unsigned num_configs) +{ + struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); + struct atmel_group *grp = atmel_pioctrl->groups + group; + unsigned bank, pin, pin_id = grp->pin; + u32 mask, conf = 0; + int i; + + conf = atmel_pin_config_read(pctldev, pin_id); + + for (i = 0; i < num_configs; i++) { + unsigned param = pinconf_to_config_param(configs[i]); + unsigned arg = pinconf_to_config_argument(configs[i]); + + dev_dbg(pctldev->dev, "%s: pin=%u, config=0x%lx\n", + __func__, pin_id, configs[i]); + + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + conf &= (~ATMEL_PIO_PUEN_MASK); + conf &= (~ATMEL_PIO_PDEN_MASK); + break; + case PIN_CONFIG_BIAS_PULL_UP: + conf |= ATMEL_PIO_PUEN_MASK; + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + conf |= ATMEL_PIO_PDEN_MASK; + break; + case PIN_CONFIG_DRIVE_OPEN_DRAIN: + if (arg == 0) + conf &= (~ATMEL_PIO_OPD_MASK); + else + conf |= ATMEL_PIO_OPD_MASK; + break; + case PIN_CONFIG_INPUT_SCHMITT_ENABLE: + if (arg == 0) + conf |= ATMEL_PIO_SCHMITT_MASK; + else + conf &= (~ATMEL_PIO_SCHMITT_MASK); + break; + case PIN_CONFIG_INPUT_DEBOUNCE: + if (arg == 0) { + conf &= (~ATMEL_PIO_IFEN_MASK); + conf &= (~ATMEL_PIO_IFSCEN_MASK); + } else { + /* + * We don't care about the debounce value for several reasons: + * - can't have different debounce periods inside a same group, + * - the register to configure this period is a secure register. + * The debouncing filter can filter a pulse with a duration of less + * than 1/2 slow clock period. + */ + conf |= ATMEL_PIO_IFEN_MASK; + conf |= ATMEL_PIO_IFSCEN_MASK; + } + break; + case PIN_CONFIG_OUTPUT: + conf |= ATMEL_PIO_DIR_MASK; + bank = ATMEL_PIO_BANK(pin_id); + pin = ATMEL_PIO_LINE(pin_id); + mask = 1 << pin; + + if (arg == 0) { + writel_relaxed(mask, atmel_pioctrl->reg_base + + bank * ATMEL_PIO_BANK_OFFSET + + ATMEL_PIO_CODR); + } else { + writel_relaxed(mask, atmel_pioctrl->reg_base + + bank * ATMEL_PIO_BANK_OFFSET + + ATMEL_PIO_SODR); + } + break; + default: + dev_warn(pctldev->dev, + "unsupported configuration parameter: %u\n", + param); + continue; + } + } + + dev_dbg(pctldev->dev, "%s: reg=0x%08x\n", __func__, conf); + atmel_pin_config_write(pctldev, pin_id, conf); + + return 0; +} + +static void atmel_conf_pin_config_dbg_show(struct pinctrl_dev *pctldev, + struct seq_file *s, unsigned pin_id) +{ + struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); + u32 conf; + + if (!atmel_pioctrl->pins[pin_id]->device) + return; + + if (atmel_pioctrl->pins[pin_id]) + seq_printf(s, " (%s, ioset %u) ", + atmel_pioctrl->pins[pin_id]->device, + atmel_pioctrl->pins[pin_id]->ioset); + + conf = atmel_pin_config_read(pctldev, pin_id); + if (conf & ATMEL_PIO_PUEN_MASK) + seq_printf(s, "%s ", "pull-up"); + if (conf & ATMEL_PIO_PDEN_MASK) + seq_printf(s, "%s ", "pull-down"); + if (conf & ATMEL_PIO_IFEN_MASK) + seq_printf(s, "%s ", "debounce"); + if (conf & ATMEL_PIO_OPD_MASK) + seq_printf(s, "%s ", "open-drain"); + if (conf & ATMEL_PIO_SCHMITT_MASK) + seq_printf(s, "%s ", "schmitt"); +} + +static const struct pinconf_ops atmel_confops = { + .pin_config_group_get = atmel_conf_pin_config_group_get, + .pin_config_group_set = atmel_conf_pin_config_group_set, + .pin_config_dbg_show = atmel_conf_pin_config_dbg_show, +}; + +static struct pinctrl_desc atmel_pinctrl_desc = { + .name = "atmel_pinctrl", + .confops = &atmel_confops, + .pctlops = &atmel_pctlops, + .pmxops = &atmel_pmxops, +}; + +/* + * The number of banks can be different from a SoC to another one. + * We can have up to 16 banks. + */ +static const struct atmel_pioctrl_data atmel_sama5d2_pioctrl_data = { + .nbanks = 4, +}; + +static const struct of_device_id atmel_pctrl_of_match[] = { + { + .compatible = "atmel,sama5d2-pinctrl", + .data = &atmel_sama5d2_pioctrl_data, + }, { + /* sentinel */ + } +}; +MODULE_DEVICE_TABLE(of, atmel_pctrl_of_match); + +static int atmel_pinctrl_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct pinctrl_pin_desc *pin_desc; + const char **group_names; + const struct of_device_id *match; + int i, ret; + struct resource *res; + struct atmel_pioctrl *atmel_pioctrl; + struct atmel_pioctrl_data *atmel_pioctrl_data; + + atmel_pioctrl = devm_kzalloc(dev, sizeof(*atmel_pioctrl), GFP_KERNEL); + if (!atmel_pioctrl) + return -ENOMEM; + atmel_pioctrl->dev = dev; + atmel_pioctrl->node = dev->of_node; + platform_set_drvdata(pdev, atmel_pioctrl); + + match = of_match_node(atmel_pctrl_of_match, dev->of_node); + if (!match) { + dev_err(dev, "unknown compatible string\n"); + return -ENODEV; + } + atmel_pioctrl_data = (struct atmel_pioctrl_data *)match->data; + atmel_pioctrl->nbanks = atmel_pioctrl_data->nbanks; + atmel_pioctrl->npins = atmel_pioctrl->nbanks * ATMEL_PIO_NPINS_PER_BANK; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + dev_err(dev, "unable to get atmel pinctrl resource\n"); + return -EINVAL; + } + atmel_pioctrl->reg_base = devm_ioremap_resource(dev, res); + if (IS_ERR(atmel_pioctrl->reg_base)) + return -EINVAL; + + atmel_pioctrl->clk = devm_clk_get(dev, NULL); + if (IS_ERR(atmel_pioctrl->clk)) { + dev_err(dev, "failed to get clock\n"); + return PTR_ERR(atmel_pioctrl->clk); + } + + atmel_pioctrl->pins = devm_kzalloc(dev, sizeof(*atmel_pioctrl->pins) + * atmel_pioctrl->npins, GFP_KERNEL); + if (!atmel_pioctrl->pins) + return -ENOMEM; + + pin_desc = devm_kzalloc(dev, sizeof(*pin_desc) + * atmel_pioctrl->npins, GFP_KERNEL); + if (!pin_desc) + return -ENOMEM; + atmel_pinctrl_desc.pins = pin_desc; + atmel_pinctrl_desc.npins = atmel_pioctrl->npins; + + /* One pin is one group since a pin can achieve all functions. */ + group_names = devm_kzalloc(dev, sizeof(*group_names) + * atmel_pioctrl->npins, GFP_KERNEL); + if (!group_names) + return -ENOMEM; + atmel_pioctrl->group_names = group_names; + + atmel_pioctrl->groups = devm_kzalloc(&pdev->dev, + sizeof(*atmel_pioctrl->groups) * atmel_pioctrl->npins, + GFP_KERNEL); + if (!atmel_pioctrl->groups) + return -ENOMEM; + for (i = 0 ; i < atmel_pioctrl->npins; i++) { + struct atmel_group *group = atmel_pioctrl->groups + i; + unsigned bank = ATMEL_PIO_BANK(i); + unsigned line = ATMEL_PIO_LINE(i); + + atmel_pioctrl->pins[i] = devm_kzalloc(dev, + sizeof(**atmel_pioctrl->pins), GFP_KERNEL); + if (!atmel_pioctrl->pins[i]) + return -ENOMEM; + + atmel_pioctrl->pins[i]->pin_id = i; + atmel_pioctrl->pins[i]->bank = bank; + atmel_pioctrl->pins[i]->line = line; + + pin_desc[i].number = i; + /* Pin naming convention: P(bank_name)(bank_pin_number). */ + pin_desc[i].name = kasprintf(GFP_KERNEL, "P%c%d", + bank + 'A', line); + + group->name = group_names[i] = pin_desc[i].name; + group->pin = pin_desc[i].number; + + dev_dbg(dev, "pin_id=%u, bank=%u, line=%u", i, bank, line); + } + + atmel_pioctrl->gpio_chip = &atmel_gpio_chip; + atmel_pioctrl->gpio_chip->of_node = dev->of_node; + atmel_pioctrl->gpio_chip->ngpio = atmel_pioctrl->npins; + atmel_pioctrl->gpio_chip->label = dev_name(dev); + atmel_pioctrl->gpio_chip->dev = dev; + atmel_pioctrl->gpio_chip->names = atmel_pioctrl->group_names; + + atmel_pioctrl->irqs = devm_kzalloc(dev, sizeof(*atmel_pioctrl->irqs) + * atmel_pioctrl->nbanks, GFP_KERNEL); + if (!atmel_pioctrl->irqs) + return -ENOMEM; + + /* There is one controller but each bank has its own irq line. */ + for (i = 0; i < atmel_pioctrl->nbanks; i++) { + res = platform_get_resource(pdev, IORESOURCE_IRQ, i); + if (!res) { + dev_err(dev, "missing irq resource for group %c\n", + 'A' + i); + return -EINVAL; + } + atmel_pioctrl->irqs[i] = res->start; + irq_set_chained_handler(res->start, atmel_gpio_irq_handler); + irq_set_handler_data(res->start, atmel_pioctrl); + dev_dbg(dev, "bank %i: hwirq=%u\n", i, res->start); + } + + atmel_pioctrl->irq_domain = irq_domain_add_linear(dev->of_node, + atmel_pioctrl->gpio_chip->ngpio, + &irq_domain_simple_ops, NULL); + if (!atmel_pioctrl->irq_domain) { + dev_err(dev, "can't add the irq domain\n"); + return -ENODEV; + } + atmel_pioctrl->irq_domain->name = "atmel gpio"; + + for (i = 0; i < atmel_pioctrl->npins; i++) { + int irq = irq_create_mapping(atmel_pioctrl->irq_domain, i); + + irq_set_chip_and_handler(irq, &atmel_gpio_irq_chip, + handle_simple_irq); + irq_set_chip_data(irq, atmel_pioctrl); + dev_dbg(dev, + "atmel gpio irq domain: hwirq: %d, linux irq: %d\n", + i, irq); + } + + ret = clk_prepare_enable(atmel_pioctrl->clk); + if (ret) { + dev_err(dev, "failed to prepare and enable clock\n"); + goto clk_prepare_enable_error; + } + + atmel_pioctrl->pinctrl_dev = pinctrl_register(&atmel_pinctrl_desc, + &pdev->dev, + atmel_pioctrl); + if (!atmel_pioctrl->pinctrl_dev) { + dev_err(dev, "pinctrl registration failed\n"); + goto pinctrl_register_error; + } + + ret = gpiochip_add(atmel_pioctrl->gpio_chip); + if (ret) { + dev_err(dev, "failed to add gpiochip\n"); + goto gpiochip_add_error; + } + + ret = gpiochip_add_pin_range(atmel_pioctrl->gpio_chip, dev_name(dev), + 0, 0, atmel_pioctrl->gpio_chip->ngpio); + if (ret) { + dev_err(dev, "failed to add gpio pin range\n"); + goto gpiochip_add_pin_range_error; + } + + dev_info(&pdev->dev, "atmel pinctrl initialized\n"); + + return 0; + +clk_prepare_enable_error: + irq_domain_remove(atmel_pioctrl->irq_domain); +pinctrl_register_error: + clk_disable_unprepare(atmel_pioctrl->clk); +gpiochip_add_error: + pinctrl_unregister(atmel_pioctrl->pinctrl_dev); +gpiochip_add_pin_range_error: + gpiochip_remove(atmel_pioctrl->gpio_chip); + + return ret; +} + +int atmel_pinctrl_remove(struct platform_device *pdev) +{ + struct atmel_pioctrl *atmel_pioctrl = platform_get_drvdata(pdev); + + irq_domain_remove(atmel_pioctrl->irq_domain); + clk_disable_unprepare(atmel_pioctrl->clk); + pinctrl_unregister(atmel_pioctrl->pinctrl_dev); + gpiochip_remove(atmel_pioctrl->gpio_chip); + + return 0; +} + +static struct platform_driver atmel_pinctrl_driver = { + .driver = { + .name = "pinctrl-at91-pio4", + .of_match_table = atmel_pctrl_of_match, + }, + .probe = atmel_pinctrl_probe, + .remove = atmel_pinctrl_remove, +}; +module_platform_driver(atmel_pinctrl_driver); + +MODULE_AUTHOR(Ludovic Desroches ); +MODULE_DESCRIPTION("Atmel PIO4 pinctrl driver"); +MODULE_LICENSE("GPL v2"); -- cgit v0.10.2 From 56d794222474edef1cae2bc97732a717ab41003a Mon Sep 17 00:00:00 2001 From: Ludovic Desroches Date: Wed, 16 Sep 2015 17:36:58 +0200 Subject: pinctrl: dt-binding: Add DT binding documentation for Atmel PIO4 Add documentation for the Atmel PIO4 controller introduced with SAMA5D2 chip family. Signed-off-by: Ludovic Desroches Acked-by: Sascha Hauer Signed-off-by: Linus Walleij diff --git a/Documentation/devicetree/bindings/pinctrl/atmel,at91-pio4-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/atmel,at91-pio4-pinctrl.txt new file mode 100644 index 0000000..61ac757 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/atmel,at91-pio4-pinctrl.txt @@ -0,0 +1,90 @@ +* Atmel PIO4 Controller + +The Atmel PIO4 controller is used to select the function of a pin and to +configure it. + +Required properties: +- compatible: "atmel,sama5d2-pinctrl". +- reg: base address and length of the PIO controller. +- interrupts: interrupt outputs from the controller, one for each bank. +- interrupt-controller: mark the device node as an interrupt controller. +- #interrupt-cells: should be two. +- gpio-controller: mark the device node as a gpio controller. +- #gpio-cells: should be two. + +Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for +a general description of GPIO and interrupt bindings. + +Please refer to pinctrl-bindings.txt in this directory for details of the +common pinctrl bindings used by client devices. + +Subnode format +Each node (or subnode) will list the pins it needs and how to configured these +pins. + + node { + pinmux = ; + GENERIC_PINCONFIG; + }; + +Required properties: +- pinmux: integer array. Each integer represents a pin number plus mux and +ioset settings. Use the macros from boot/dts/-pinfunc.h file to get the +right representation of the pin. + +Optional properties: +- GENERIC_PINCONFIG: generic pinconfig options to use, bias-disable, +bias-pull-down, bias-pull-up, drive-open-drain, input-schmitt-enable, +input-debounce, output-low, output-high. + +Example: + +#include + +... +{ + pioA: pinctrl@fc038000 { + compatible = "atmel,sama5d2-pinctrl"; + reg = <0xfc038000 0x600>; + interrupts = <18 IRQ_TYPE_LEVEL_HIGH 7>, + <68 IRQ_TYPE_LEVEL_HIGH 7>, + <69 IRQ_TYPE_LEVEL_HIGH 7>, + <70 IRQ_TYPE_LEVEL_HIGH 7>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + clocks = <&pioA_clk>; + + pinctrl_i2c0_default: i2c0_default { + pinmux = , + ; + bias-disable; + }; + + pinctrl_led_gpio_default: led_gpio_default { + pinmux = , + ; + bias-pull-up; + }; + + pinctrl_sdmmc1_default: sdmmc1_default { + cmd_data { + pinmux = , + , + , + , + ; + bias-pull-up; + }; + + ck_cd { + pinmux = , + ; + bias-disable; + }; + }; + ... + }; +}; +... -- cgit v0.10.2 From 33d3690cf5c24261af69b5d415ae5403ee386e1f Mon Sep 17 00:00:00 2001 From: Ludovic Desroches Date: Wed, 16 Sep 2015 17:36:59 +0200 Subject: MAINTAINERS: Add an entry for pinctrl-at91-pio4 Add an entry for the Atmel PIO4 controller driver. Signed-off-by: Ludovic Desroches Signed-off-by: Linus Walleij diff --git a/MAINTAINERS b/MAINTAINERS index 274f854..7a9a0c8 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -8153,6 +8153,13 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained F: drivers/pinctrl/pinctrl-at91.* +PIN CONTROLLER - ATMEL AT91 PIO4 +M: Ludovic Desroches +L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) +L: linux-gpio@vger.kernel.org +S: Supported +F: drivers/pinctrl/pinctrl-at91-pio4.* + PIN CONTROLLER - INTEL M: Mika Westerberg M: Heikki Krogerus -- cgit v0.10.2 From f6c804b08ca5e04f309e88b7e8823ef8b9d054e5 Mon Sep 17 00:00:00 2001 From: Ludovic Desroches Date: Wed, 16 Sep 2015 17:37:00 +0200 Subject: ARM: at91/dt: sama5d2: add pio controller node Add pio4 controller node to enable pinmux and gpio. Signed-off-by: Ludovic Desroches Signed-off-by: Linus Walleij diff --git a/arch/arm/boot/dts/sama5d2.dtsi b/arch/arm/boot/dts/sama5d2.dtsi index 034cd48..cc05cde 100644 --- a/arch/arm/boot/dts/sama5d2.dtsi +++ b/arch/arm/boot/dts/sama5d2.dtsi @@ -921,6 +921,20 @@ clocks = <&twi1_clk>; status = "disabled"; }; + + pioA: pinctrl@fc038000 { + compatible = "atmel,sama5d2-pinctrl"; + reg = <0xfc038000 0x600>; + interrupts = <18 IRQ_TYPE_LEVEL_HIGH 7>, + <68 IRQ_TYPE_LEVEL_HIGH 7>, + <69 IRQ_TYPE_LEVEL_HIGH 7>, + <70 IRQ_TYPE_LEVEL_HIGH 7>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + clocks = <&pioA_clk>; + }; }; }; }; -- cgit v0.10.2 From c5ce767088a5ab7a051006c7c1f6e2c2ab9f460d Mon Sep 17 00:00:00 2001 From: Xing Zheng Date: Fri, 28 Aug 2015 13:46:47 +0800 Subject: pinctrl: rockchip: add support for the rk3036 Many parts of pinctrl rk3036 are similar to rk2928's. Signed-off-by: Xing Zheng Reviewed-by: Heiko Stuebner Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c index 88bb707..3d020fd 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -2089,6 +2089,21 @@ static struct rockchip_pin_ctrl rk2928_pin_ctrl = { .pull_calc_reg = rk2928_calc_pull_reg_and_bit, }; +static struct rockchip_pin_bank rk3036_pin_banks[] = { + PIN_BANK(0, 32, "gpio0"), + PIN_BANK(1, 32, "gpio1"), + PIN_BANK(2, 32, "gpio2"), +}; + +static struct rockchip_pin_ctrl rk3036_pin_ctrl = { + .pin_banks = rk3036_pin_banks, + .nr_banks = ARRAY_SIZE(rk3036_pin_banks), + .label = "RK3036-GPIO", + .type = RK2928, + .grf_mux_offset = 0xa8, + .pull_calc_reg = rk2928_calc_pull_reg_and_bit, +}; + static struct rockchip_pin_bank rk3066a_pin_banks[] = { PIN_BANK(0, 32, "gpio0"), PIN_BANK(1, 32, "gpio1"), @@ -2207,6 +2222,8 @@ static struct rockchip_pin_ctrl rk3368_pin_ctrl = { static const struct of_device_id rockchip_pinctrl_dt_match[] = { { .compatible = "rockchip,rk2928-pinctrl", .data = (void *)&rk2928_pin_ctrl }, + { .compatible = "rockchip,rk3036-pinctrl", + .data = (void *)&rk3036_pin_ctrl }, { .compatible = "rockchip,rk3066a-pinctrl", .data = (void *)&rk3066a_pin_ctrl }, { .compatible = "rockchip,rk3066b-pinctrl", -- cgit v0.10.2 From b4b05b9af35e4ba8aee4fc8fcfc4175c7feb3544 Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Sat, 29 Aug 2015 01:25:01 +0200 Subject: pinctrl: mediatek: Consistently use the BIT() macro The mediatek pinctrl driver uses the BIT() macro instead of open coding 1 << n in all but one place. Replace this occurrence with the BIT() macro for consistency. Signed-off-by: Javier Martinez Canillas Reviewed-by: Matthias Brugger Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c index 1b22f96..c40f533 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c @@ -899,7 +899,7 @@ static int mtk_eint_flip_edge(struct mtk_pinctrl *pctl, int hwirq) int start_level, curr_level; unsigned int reg_offset; const struct mtk_eint_offsets *eint_offsets = &(pctl->devdata->eint_offsets); - u32 mask = 1 << (hwirq & 0x1f); + u32 mask = BIT(hwirq & 0x1f); u32 port = (hwirq >> 5) & eint_offsets->port_mask; void __iomem *reg = pctl->eint_reg_base + (port << 2); const struct mtk_desc_pin *pin; -- cgit v0.10.2 From 18fab3995e8a6c4e3ffe2adced0ffa76eebdc989 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 4 Aug 2015 15:55:17 +0200 Subject: pinctrl: sh-pfc: Stop calling gpiochip_add_pin_range() on DT platforms On platforms where the PFC/GPIO controller is instantiated from DT, the mapping between GPIOs and pins is set up using the "gpio-ranges" property in DT. Hence stop setting up the mapping from C code on DT platforms. This code is still used for SH or ARM-legacy platforms. Signed-off-by: Geert Uytterhoeven Acked-by: Linus Walleij Acked-by: Laurent Pinchart diff --git a/drivers/pinctrl/sh-pfc/gpio.c b/drivers/pinctrl/sh-pfc/gpio.c index ba35373..b380e3f 100644 --- a/drivers/pinctrl/sh-pfc/gpio.c +++ b/drivers/pinctrl/sh-pfc/gpio.c @@ -379,22 +379,29 @@ int sh_pfc_register_gpiochip(struct sh_pfc *pfc) pfc->gpio = chip; - /* Register the GPIO to pin mappings. As pins with GPIO ports must come - * first in the ranges, skip the pins without GPIO ports by stopping at - * the first range that contains such a pin. - */ - for (i = 0; i < pfc->nr_ranges; ++i) { - const struct sh_pfc_pin_range *range = &pfc->ranges[i]; - - if (range->start >= pfc->nr_gpio_pins) - break; + if (IS_ENABLED(CONFIG_OF) && pfc->dev->of_node) + return 0; - ret = gpiochip_add_pin_range(&chip->gpio_chip, - dev_name(pfc->dev), - range->start, range->start, - range->end - range->start + 1); - if (ret < 0) - return ret; + if (IS_ENABLED(CONFIG_SUPERH) || + IS_ENABLED(CONFIG_ARCH_SHMOBILE_LEGACY)) { + /* + * Register the GPIO to pin mappings. As pins with GPIO ports + * must come first in the ranges, skip the pins without GPIO + * ports by stopping at the first range that contains such a + * pin. + */ + for (i = 0; i < pfc->nr_ranges; ++i) { + const struct sh_pfc_pin_range *range = &pfc->ranges[i]; + + if (range->start >= pfc->nr_gpio_pins) + break; + + ret = gpiochip_add_pin_range(&chip->gpio_chip, + dev_name(pfc->dev), range->start, range->start, + range->end - range->start + 1); + if (ret < 0) + return ret; + } } /* Register the function GPIOs chip. */ -- cgit v0.10.2 From 57106e5ca55bea70e3e296a3e7546aefe0d1dabe Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 4 Aug 2015 15:55:18 +0200 Subject: pinctrl: sh-pfc: Remove empty gpio_function_free() gpio_chip.free() is optional, and can just be left unimplemented. Signed-off-by: Geert Uytterhoeven Acked-by: Laurent Pinchart Acked-by: Linus Walleij diff --git a/drivers/pinctrl/sh-pfc/gpio.c b/drivers/pinctrl/sh-pfc/gpio.c index b380e3f..e464390 100644 --- a/drivers/pinctrl/sh-pfc/gpio.c +++ b/drivers/pinctrl/sh-pfc/gpio.c @@ -286,17 +286,12 @@ static int gpio_function_request(struct gpio_chip *gc, unsigned offset) return ret; } -static void gpio_function_free(struct gpio_chip *gc, unsigned offset) -{ -} - static int gpio_function_setup(struct sh_pfc_chip *chip) { struct sh_pfc *pfc = chip->pfc; struct gpio_chip *gc = &chip->gpio_chip; gc->request = gpio_function_request; - gc->free = gpio_function_free; gc->label = pfc->info->name; gc->owner = THIS_MODULE; -- cgit v0.10.2 From 56f891b46d37e8c7b04db660d6e9ad05e586203c Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 4 Aug 2015 15:55:19 +0200 Subject: pinctrl: sh-pfc: Confine legacy function GPIOs to SH Legacy function GPIOs are no longer used on ARM since commit a27c5cd1a08cc95c ("sh-pfc: sh73a0: Remove function GPIOs"). Extract its setup code into a separate function, and make all function GPIO related code and data depend on CONFIG_SUPERH. Signed-off-by: Geert Uytterhoeven Acked-by: Linus Walleij Acked-by: Laurent Pinchart diff --git a/drivers/pinctrl/sh-pfc/core.h b/drivers/pinctrl/sh-pfc/core.h index 4c3c37b..c38ace4 100644 --- a/drivers/pinctrl/sh-pfc/core.h +++ b/drivers/pinctrl/sh-pfc/core.h @@ -46,7 +46,9 @@ struct sh_pfc { unsigned int nr_gpio_pins; struct sh_pfc_chip *gpio; +#ifdef CONFIG_SUPERH struct sh_pfc_chip *func; +#endif struct sh_pfc_pinctrl *pinctrl; }; diff --git a/drivers/pinctrl/sh-pfc/gpio.c b/drivers/pinctrl/sh-pfc/gpio.c index e464390..685b3c2 100644 --- a/drivers/pinctrl/sh-pfc/gpio.c +++ b/drivers/pinctrl/sh-pfc/gpio.c @@ -261,6 +261,7 @@ static int gpio_pin_setup(struct sh_pfc_chip *chip) * Function GPIOs */ +#ifdef CONFIG_SUPERH static int gpio_function_request(struct gpio_chip *gc, unsigned offset) { static bool __print_once; @@ -300,6 +301,7 @@ static int gpio_function_setup(struct sh_pfc_chip *chip) return 0; } +#endif /* ----------------------------------------------------------------------------- * Register/unregister @@ -399,6 +401,7 @@ int sh_pfc_register_gpiochip(struct sh_pfc *pfc) } } +#ifdef CONFIG_SUPERH /* Register the function GPIOs chip. */ if (pfc->info->nr_func_gpios == 0) return 0; @@ -408,6 +411,7 @@ int sh_pfc_register_gpiochip(struct sh_pfc *pfc) return PTR_ERR(chip); pfc->func = chip; +#endif /* CONFIG_SUPERH */ return 0; } @@ -415,7 +419,8 @@ int sh_pfc_register_gpiochip(struct sh_pfc *pfc) int sh_pfc_unregister_gpiochip(struct sh_pfc *pfc) { gpiochip_remove(&pfc->gpio->gpio_chip); +#ifdef CONFIG_SUPERH gpiochip_remove(&pfc->func->gpio_chip); - +#endif return 0; } diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h index 15afd49..7cb1ed6 100644 --- a/drivers/pinctrl/sh-pfc/sh_pfc.h +++ b/drivers/pinctrl/sh-pfc/sh_pfc.h @@ -143,8 +143,10 @@ struct sh_pfc_soc_info { const struct sh_pfc_function *functions; unsigned int nr_functions; +#ifdef CONFIG_SUPERH const struct pinmux_func *func_gpios; unsigned int nr_func_gpios; +#endif const struct pinmux_cfg_reg *cfg_regs; const struct pinmux_data_reg *data_regs; -- cgit v0.10.2 From 48a7b99d75b4f48fb001057a8390a839e70e7acc Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 26 Aug 2015 19:53:58 +0200 Subject: pinctrl: sh-pfc: r8a7794: Remove bogus SCIF0 SCK pin data SCIF0 on R-Car E2 does not have an SCK pin. "SCIF_CLK" is the (H)SCIF baud rate generation clock pin, which is not yet supported. Signed-off-by: Geert Uytterhoeven Acked-by: Linus Walleij diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7794.c b/drivers/pinctrl/sh-pfc/pfc-r8a7794.c index 5248685..7a8cd9b 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7794.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7794.c @@ -2197,13 +2197,6 @@ static const unsigned int scif0_data_pins[] = { static const unsigned int scif0_data_mux[] = { SCIF0_RXD_MARK, SCIF0_TXD_MARK, }; -static const unsigned int scif0_clk_pins[] = { - /* SCK */ - RCAR_GP_PIN(1, 23), -}; -static const unsigned int scif0_clk_mux[] = { - SCIF_CLK_MARK, -}; static const unsigned int scif0_data_b_pins[] = { /* RX, TX */ RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12), @@ -2211,13 +2204,6 @@ static const unsigned int scif0_data_b_pins[] = { static const unsigned int scif0_data_b_mux[] = { SCIF0_RXD_B_MARK, SCIF0_TXD_B_MARK, }; -static const unsigned int scif0_clk_b_pins[] = { - /* SCK */ - RCAR_GP_PIN(3, 29), -}; -static const unsigned int scif0_clk_b_mux[] = { - SCIF_CLK_B_MARK, -}; static const unsigned int scif0_data_c_pins[] = { /* RX, TX */ RCAR_GP_PIN(3, 30), RCAR_GP_PIN(3, 31), @@ -2884,9 +2870,7 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(qspi_data2), SH_PFC_PIN_GROUP(qspi_data4), SH_PFC_PIN_GROUP(scif0_data), - SH_PFC_PIN_GROUP(scif0_clk), SH_PFC_PIN_GROUP(scif0_data_b), - SH_PFC_PIN_GROUP(scif0_clk_b), SH_PFC_PIN_GROUP(scif0_data_c), SH_PFC_PIN_GROUP(scif0_data_d), SH_PFC_PIN_GROUP(scif1_data), @@ -3107,9 +3091,7 @@ static const char * const qspi_groups[] = { static const char * const scif0_groups[] = { "scif0_data", - "scif0_clk", "scif0_data_b", - "scif0_clk_b", "scif0_data_c", "scif0_data_d", }; -- cgit v0.10.2 From 9e214614532a6bd7e90bdcdc778b041647cc4036 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 10 Sep 2015 14:17:03 +0200 Subject: pinctrl: sh-pfc: r8a7791/r8a7793: Correct SCIFB1_B SCK MOD_SEL value When using serial port SCIFB1_B, transmit works, but nothing is received. Receive fails because the SCIFB1_SCK_B settings configure the wrong value for the sel_scifb1 field in the Module Select Register (MOD_SEL), due to an ambiguity in the R-Car M2-W and M2-N datasheets. Tested on r8a7791/koelsch using pins 53 (TXD) and 72 (RXD) on EXIO Connector A. Signed-off-by: Geert Uytterhoeven Acked-by: Linus Walleij diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c index 25e8117..a79f3b5 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c @@ -889,7 +889,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_DATA(IP2_2_0, DACK1), PINMUX_IPSR_MODSEL_DATA(IP2_2_0, SCIFA1_TXD_C, SEL_SCIFA1_2), PINMUX_IPSR_MODSEL_DATA(IP2_2_0, SCIFB1_TXD_C, SEL_SCIFB1_2), - PINMUX_IPSR_MODSEL_DATA(IP2_2_0, SCIFB1_SCK_B, SEL_SCIFB1_0), + PINMUX_IPSR_MODSEL_DATA(IP2_2_0, SCIFB1_SCK_B, SEL_SCIFB1_1), PINMUX_IPSR_DATA(IP2_2_0, A20), PINMUX_IPSR_MODSEL_DATA(IP2_4_3, SPCLK, SEL_QSP_0), PINMUX_IPSR_DATA(IP2_6_5, A21), -- cgit v0.10.2 From 90d066130f69533fb16b395be3de613903575e69 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 27 Aug 2015 22:07:23 +0200 Subject: pinctrl: sh-pfc: Get rid of CONFIG_ARCH_SHMOBILE_LEGACY Shmobile is all multiplatform these days, so get rid of the reference to CONFIG_ARCH_SHMOBILE_LEGACY. Move the legacy code to do the non-DT mapping between GPIOs and pins inside the existing #ifdef CONFIG_SUPERH section. Signed-off-by: Geert Uytterhoeven Acked-by: Laurent Pinchart Acked-by: Linus Walleij diff --git a/drivers/pinctrl/sh-pfc/gpio.c b/drivers/pinctrl/sh-pfc/gpio.c index 685b3c2..a917c62 100644 --- a/drivers/pinctrl/sh-pfc/gpio.c +++ b/drivers/pinctrl/sh-pfc/gpio.c @@ -341,7 +341,6 @@ int sh_pfc_register_gpiochip(struct sh_pfc *pfc) struct sh_pfc_chip *chip; phys_addr_t address; unsigned int i; - int ret; if (pfc->info->data_regs == NULL) return 0; @@ -379,29 +378,27 @@ int sh_pfc_register_gpiochip(struct sh_pfc *pfc) if (IS_ENABLED(CONFIG_OF) && pfc->dev->of_node) return 0; - if (IS_ENABLED(CONFIG_SUPERH) || - IS_ENABLED(CONFIG_ARCH_SHMOBILE_LEGACY)) { - /* - * Register the GPIO to pin mappings. As pins with GPIO ports - * must come first in the ranges, skip the pins without GPIO - * ports by stopping at the first range that contains such a - * pin. - */ - for (i = 0; i < pfc->nr_ranges; ++i) { - const struct sh_pfc_pin_range *range = &pfc->ranges[i]; - - if (range->start >= pfc->nr_gpio_pins) - break; - - ret = gpiochip_add_pin_range(&chip->gpio_chip, - dev_name(pfc->dev), range->start, range->start, - range->end - range->start + 1); - if (ret < 0) - return ret; - } +#ifdef CONFIG_SUPERH + /* + * Register the GPIO to pin mappings. As pins with GPIO ports + * must come first in the ranges, skip the pins without GPIO + * ports by stopping at the first range that contains such a + * pin. + */ + for (i = 0; i < pfc->nr_ranges; ++i) { + const struct sh_pfc_pin_range *range = &pfc->ranges[i]; + int ret; + + if (range->start >= pfc->nr_gpio_pins) + break; + + ret = gpiochip_add_pin_range(&chip->gpio_chip, + dev_name(pfc->dev), range->start, range->start, + range->end - range->start + 1); + if (ret < 0) + return ret; } -#ifdef CONFIG_SUPERH /* Register the function GPIOs chip. */ if (pfc->info->nr_func_gpios == 0) return 0; -- cgit v0.10.2 From 4adeabd042422ceecd7605961d785c5c3edab9e1 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Tue, 22 Sep 2015 10:08:13 +0300 Subject: pinctrl: sh-pfc: Remove hardcoded IRQ numbers Now that all ARM-based Renesas SoCs use multiplatform kernels only the hardcoded IRQ numbers can be dropped as they're dynamically allocated. Signed-off-by: Laurent Pinchart Acked-by: Geert Uytterhoeven Signed-off-by: Geert Uytterhoeven diff --git a/drivers/pinctrl/sh-pfc/gpio.c b/drivers/pinctrl/sh-pfc/gpio.c index a917c62..db3f09a 100644 --- a/drivers/pinctrl/sh-pfc/gpio.c +++ b/drivers/pinctrl/sh-pfc/gpio.c @@ -219,10 +219,7 @@ static int gpio_pin_to_irq(struct gpio_chip *gc, unsigned offset) return -ENOSYS; found: - if (pfc->num_irqs) - return pfc->irqs[i]; - else - return pfc->info->gpio_irq[i].irq; + return pfc->irqs[i]; } static int gpio_pin_setup(struct sh_pfc_chip *chip) @@ -363,7 +360,7 @@ int sh_pfc_register_gpiochip(struct sh_pfc *pfc) return 0; /* If we have IRQ resources make sure their number is correct. */ - if (pfc->num_irqs && pfc->num_irqs != pfc->info->gpio_irq_size) { + if (pfc->num_irqs != pfc->info->gpio_irq_size) { dev_err(pfc->dev, "invalid number of IRQ resources\n"); return -EINVAL; } diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c b/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c index ba18d2e..d51d5fd 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c @@ -2603,64 +2603,64 @@ static const struct pinmux_data_reg pinmux_data_regs[] = { }; static const struct pinmux_irq pinmux_irqs[] = { - PINMUX_IRQ(irq_pin(0), 0), - PINMUX_IRQ(irq_pin(1), 1), - PINMUX_IRQ(irq_pin(2), 2), - PINMUX_IRQ(irq_pin(3), 3), - PINMUX_IRQ(irq_pin(4), 4), - PINMUX_IRQ(irq_pin(5), 5), - PINMUX_IRQ(irq_pin(6), 6), - PINMUX_IRQ(irq_pin(7), 7), - PINMUX_IRQ(irq_pin(8), 8), - PINMUX_IRQ(irq_pin(9), 9), - PINMUX_IRQ(irq_pin(10), 10), - PINMUX_IRQ(irq_pin(11), 11), - PINMUX_IRQ(irq_pin(12), 12), - PINMUX_IRQ(irq_pin(13), 13), - PINMUX_IRQ(irq_pin(14), 14), - PINMUX_IRQ(irq_pin(15), 15), - PINMUX_IRQ(irq_pin(16), 320), - PINMUX_IRQ(irq_pin(17), 321), - PINMUX_IRQ(irq_pin(18), 85), - PINMUX_IRQ(irq_pin(19), 84), - PINMUX_IRQ(irq_pin(20), 160), - PINMUX_IRQ(irq_pin(21), 161), - PINMUX_IRQ(irq_pin(22), 162), - PINMUX_IRQ(irq_pin(23), 163), - PINMUX_IRQ(irq_pin(24), 175), - PINMUX_IRQ(irq_pin(25), 176), - PINMUX_IRQ(irq_pin(26), 177), - PINMUX_IRQ(irq_pin(27), 178), - PINMUX_IRQ(irq_pin(28), 322), - PINMUX_IRQ(irq_pin(29), 323), - PINMUX_IRQ(irq_pin(30), 324), - PINMUX_IRQ(irq_pin(31), 192), - PINMUX_IRQ(irq_pin(32), 193), - PINMUX_IRQ(irq_pin(33), 194), - PINMUX_IRQ(irq_pin(34), 195), - PINMUX_IRQ(irq_pin(35), 196), - PINMUX_IRQ(irq_pin(36), 197), - PINMUX_IRQ(irq_pin(37), 198), - PINMUX_IRQ(irq_pin(38), 199), - PINMUX_IRQ(irq_pin(39), 200), - PINMUX_IRQ(irq_pin(40), 66), - PINMUX_IRQ(irq_pin(41), 102), - PINMUX_IRQ(irq_pin(42), 103), - PINMUX_IRQ(irq_pin(43), 109), - PINMUX_IRQ(irq_pin(44), 110), - PINMUX_IRQ(irq_pin(45), 111), - PINMUX_IRQ(irq_pin(46), 112), - PINMUX_IRQ(irq_pin(47), 113), - PINMUX_IRQ(irq_pin(48), 114), - PINMUX_IRQ(irq_pin(49), 115), - PINMUX_IRQ(irq_pin(50), 301), - PINMUX_IRQ(irq_pin(51), 290), - PINMUX_IRQ(irq_pin(52), 296), - PINMUX_IRQ(irq_pin(53), 325), - PINMUX_IRQ(irq_pin(54), 326), - PINMUX_IRQ(irq_pin(55), 327), - PINMUX_IRQ(irq_pin(56), 328), - PINMUX_IRQ(irq_pin(57), 329), + PINMUX_IRQ(0), /* IRQ0 */ + PINMUX_IRQ(1), /* IRQ1 */ + PINMUX_IRQ(2), /* IRQ2 */ + PINMUX_IRQ(3), /* IRQ3 */ + PINMUX_IRQ(4), /* IRQ4 */ + PINMUX_IRQ(5), /* IRQ5 */ + PINMUX_IRQ(6), /* IRQ6 */ + PINMUX_IRQ(7), /* IRQ7 */ + PINMUX_IRQ(8), /* IRQ8 */ + PINMUX_IRQ(9), /* IRQ9 */ + PINMUX_IRQ(10), /* IRQ10 */ + PINMUX_IRQ(11), /* IRQ11 */ + PINMUX_IRQ(12), /* IRQ12 */ + PINMUX_IRQ(13), /* IRQ13 */ + PINMUX_IRQ(14), /* IRQ14 */ + PINMUX_IRQ(15), /* IRQ15 */ + PINMUX_IRQ(320), /* IRQ16 */ + PINMUX_IRQ(321), /* IRQ17 */ + PINMUX_IRQ(85), /* IRQ18 */ + PINMUX_IRQ(84), /* IRQ19 */ + PINMUX_IRQ(160), /* IRQ20 */ + PINMUX_IRQ(161), /* IRQ21 */ + PINMUX_IRQ(162), /* IRQ22 */ + PINMUX_IRQ(163), /* IRQ23 */ + PINMUX_IRQ(175), /* IRQ24 */ + PINMUX_IRQ(176), /* IRQ25 */ + PINMUX_IRQ(177), /* IRQ26 */ + PINMUX_IRQ(178), /* IRQ27 */ + PINMUX_IRQ(322), /* IRQ28 */ + PINMUX_IRQ(323), /* IRQ29 */ + PINMUX_IRQ(324), /* IRQ30 */ + PINMUX_IRQ(192), /* IRQ31 */ + PINMUX_IRQ(193), /* IRQ32 */ + PINMUX_IRQ(194), /* IRQ33 */ + PINMUX_IRQ(195), /* IRQ34 */ + PINMUX_IRQ(196), /* IRQ35 */ + PINMUX_IRQ(197), /* IRQ36 */ + PINMUX_IRQ(198), /* IRQ37 */ + PINMUX_IRQ(199), /* IRQ38 */ + PINMUX_IRQ(200), /* IRQ39 */ + PINMUX_IRQ(66), /* IRQ40 */ + PINMUX_IRQ(102), /* IRQ41 */ + PINMUX_IRQ(103), /* IRQ42 */ + PINMUX_IRQ(109), /* IRQ43 */ + PINMUX_IRQ(110), /* IRQ44 */ + PINMUX_IRQ(111), /* IRQ45 */ + PINMUX_IRQ(112), /* IRQ46 */ + PINMUX_IRQ(113), /* IRQ47 */ + PINMUX_IRQ(114), /* IRQ48 */ + PINMUX_IRQ(115), /* IRQ49 */ + PINMUX_IRQ(301), /* IRQ50 */ + PINMUX_IRQ(290), /* IRQ51 */ + PINMUX_IRQ(296), /* IRQ52 */ + PINMUX_IRQ(325), /* IRQ53 */ + PINMUX_IRQ(326), /* IRQ54 */ + PINMUX_IRQ(327), /* IRQ55 */ + PINMUX_IRQ(328), /* IRQ56 */ + PINMUX_IRQ(329), /* IRQ57 */ }; #define PORTCR_PULMD_OFF (0 << 6) diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c index 82ef186..44223b3 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c @@ -3651,38 +3651,38 @@ static const struct pinmux_data_reg pinmux_data_regs[] = { }; static const struct pinmux_irq pinmux_irqs[] = { - PINMUX_IRQ(irq_pin(0), 2, 13), /* IRQ0A */ - PINMUX_IRQ(irq_pin(1), 20), /* IRQ1A */ - PINMUX_IRQ(irq_pin(2), 11, 12), /* IRQ2A */ - PINMUX_IRQ(irq_pin(3), 10, 14), /* IRQ3A */ - PINMUX_IRQ(irq_pin(4), 15, 172), /* IRQ4A */ - PINMUX_IRQ(irq_pin(5), 0, 1), /* IRQ5A */ - PINMUX_IRQ(irq_pin(6), 121, 173), /* IRQ6A */ - PINMUX_IRQ(irq_pin(7), 120, 209), /* IRQ7A */ - PINMUX_IRQ(irq_pin(8), 119), /* IRQ8A */ - PINMUX_IRQ(irq_pin(9), 118, 210), /* IRQ9A */ - PINMUX_IRQ(irq_pin(10), 19), /* IRQ10A */ - PINMUX_IRQ(irq_pin(11), 104), /* IRQ11A */ - PINMUX_IRQ(irq_pin(12), 42, 97), /* IRQ12A */ - PINMUX_IRQ(irq_pin(13), 64, 98), /* IRQ13A */ - PINMUX_IRQ(irq_pin(14), 63, 99), /* IRQ14A */ - PINMUX_IRQ(irq_pin(15), 62, 100), /* IRQ15A */ - PINMUX_IRQ(irq_pin(16), 68, 211), /* IRQ16A */ - PINMUX_IRQ(irq_pin(17), 69), /* IRQ17A */ - PINMUX_IRQ(irq_pin(18), 70), /* IRQ18A */ - PINMUX_IRQ(irq_pin(19), 71), /* IRQ19A */ - PINMUX_IRQ(irq_pin(20), 67), /* IRQ20A */ - PINMUX_IRQ(irq_pin(21), 202), /* IRQ21A */ - PINMUX_IRQ(irq_pin(22), 95), /* IRQ22A */ - PINMUX_IRQ(irq_pin(23), 96), /* IRQ23A */ - PINMUX_IRQ(irq_pin(24), 180), /* IRQ24A */ - PINMUX_IRQ(irq_pin(25), 38), /* IRQ25A */ - PINMUX_IRQ(irq_pin(26), 58, 81), /* IRQ26A */ - PINMUX_IRQ(irq_pin(27), 57, 168), /* IRQ27A */ - PINMUX_IRQ(irq_pin(28), 56, 169), /* IRQ28A */ - PINMUX_IRQ(irq_pin(29), 50, 170), /* IRQ29A */ - PINMUX_IRQ(irq_pin(30), 49, 171), /* IRQ30A */ - PINMUX_IRQ(irq_pin(31), 41, 167), /* IRQ31A */ + PINMUX_IRQ(2, 13), /* IRQ0A */ + PINMUX_IRQ(20), /* IRQ1A */ + PINMUX_IRQ(11, 12), /* IRQ2A */ + PINMUX_IRQ(10, 14), /* IRQ3A */ + PINMUX_IRQ(15, 172), /* IRQ4A */ + PINMUX_IRQ(0, 1), /* IRQ5A */ + PINMUX_IRQ(121, 173), /* IRQ6A */ + PINMUX_IRQ(120, 209), /* IRQ7A */ + PINMUX_IRQ(119), /* IRQ8A */ + PINMUX_IRQ(118, 210), /* IRQ9A */ + PINMUX_IRQ(19), /* IRQ10A */ + PINMUX_IRQ(104), /* IRQ11A */ + PINMUX_IRQ(42, 97), /* IRQ12A */ + PINMUX_IRQ(64, 98), /* IRQ13A */ + PINMUX_IRQ(63, 99), /* IRQ14A */ + PINMUX_IRQ(62, 100), /* IRQ15A */ + PINMUX_IRQ(68, 211), /* IRQ16A */ + PINMUX_IRQ(69), /* IRQ17A */ + PINMUX_IRQ(70), /* IRQ18A */ + PINMUX_IRQ(71), /* IRQ19A */ + PINMUX_IRQ(67), /* IRQ20A */ + PINMUX_IRQ(202), /* IRQ21A */ + PINMUX_IRQ(95), /* IRQ22A */ + PINMUX_IRQ(96), /* IRQ23A */ + PINMUX_IRQ(180), /* IRQ24A */ + PINMUX_IRQ(38), /* IRQ25A */ + PINMUX_IRQ(58, 81), /* IRQ26A */ + PINMUX_IRQ(57, 168), /* IRQ27A */ + PINMUX_IRQ(56, 169), /* IRQ28A */ + PINMUX_IRQ(50, 170), /* IRQ29A */ + PINMUX_IRQ(49, 171), /* IRQ30A */ + PINMUX_IRQ(41, 167), /* IRQ31A */ }; #define PORTnCR_PULMD_OFF (0 << 6) diff --git a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c index 0975265..bec2652 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c @@ -3649,38 +3649,38 @@ static const struct pinmux_data_reg pinmux_data_regs[] = { }; static const struct pinmux_irq pinmux_irqs[] = { - PINMUX_IRQ(irq_pin(0), 11), - PINMUX_IRQ(irq_pin(1), 10), - PINMUX_IRQ(irq_pin(2), 149), - PINMUX_IRQ(irq_pin(3), 224), - PINMUX_IRQ(irq_pin(4), 159), - PINMUX_IRQ(irq_pin(5), 227), - PINMUX_IRQ(irq_pin(6), 147), - PINMUX_IRQ(irq_pin(7), 150), - PINMUX_IRQ(irq_pin(8), 223), - PINMUX_IRQ(irq_pin(9), 56, 308), - PINMUX_IRQ(irq_pin(10), 54), - PINMUX_IRQ(irq_pin(11), 238), - PINMUX_IRQ(irq_pin(12), 156), - PINMUX_IRQ(irq_pin(13), 239), - PINMUX_IRQ(irq_pin(14), 251), - PINMUX_IRQ(irq_pin(15), 0), - PINMUX_IRQ(irq_pin(16), 249), - PINMUX_IRQ(irq_pin(17), 234), - PINMUX_IRQ(irq_pin(18), 13), - PINMUX_IRQ(irq_pin(19), 9), - PINMUX_IRQ(irq_pin(20), 14), - PINMUX_IRQ(irq_pin(21), 15), - PINMUX_IRQ(irq_pin(22), 40), - PINMUX_IRQ(irq_pin(23), 53), - PINMUX_IRQ(irq_pin(24), 118), - PINMUX_IRQ(irq_pin(25), 164), - PINMUX_IRQ(irq_pin(26), 115), - PINMUX_IRQ(irq_pin(27), 116), - PINMUX_IRQ(irq_pin(28), 117), - PINMUX_IRQ(irq_pin(29), 28), - PINMUX_IRQ(irq_pin(30), 27), - PINMUX_IRQ(irq_pin(31), 26), + PINMUX_IRQ(11), /* IRQ0 */ + PINMUX_IRQ(10), /* IRQ1 */ + PINMUX_IRQ(149), /* IRQ2 */ + PINMUX_IRQ(224), /* IRQ3 */ + PINMUX_IRQ(159), /* IRQ4 */ + PINMUX_IRQ(227), /* IRQ5 */ + PINMUX_IRQ(147), /* IRQ6 */ + PINMUX_IRQ(150), /* IRQ7 */ + PINMUX_IRQ(223), /* IRQ8 */ + PINMUX_IRQ(56, 308), /* IRQ9 */ + PINMUX_IRQ(54), /* IRQ10 */ + PINMUX_IRQ(238), /* IRQ11 */ + PINMUX_IRQ(156), /* IRQ12 */ + PINMUX_IRQ(239), /* IRQ13 */ + PINMUX_IRQ(251), /* IRQ14 */ + PINMUX_IRQ(0), /* IRQ15 */ + PINMUX_IRQ(249), /* IRQ16 */ + PINMUX_IRQ(234), /* IRQ17 */ + PINMUX_IRQ(13), /* IRQ18 */ + PINMUX_IRQ(9), /* IRQ19 */ + PINMUX_IRQ(14), /* IRQ20 */ + PINMUX_IRQ(15), /* IRQ21 */ + PINMUX_IRQ(40), /* IRQ22 */ + PINMUX_IRQ(53), /* IRQ23 */ + PINMUX_IRQ(118), /* IRQ24 */ + PINMUX_IRQ(164), /* IRQ25 */ + PINMUX_IRQ(115), /* IRQ26 */ + PINMUX_IRQ(116), /* IRQ27 */ + PINMUX_IRQ(117), /* IRQ28 */ + PINMUX_IRQ(28), /* IRQ29 */ + PINMUX_IRQ(27), /* IRQ30 */ + PINMUX_IRQ(26), /* IRQ31 */ }; /* ----------------------------------------------------------------------------- diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h index 7cb1ed6..1da8a1c 100644 --- a/drivers/pinctrl/sh-pfc/sh_pfc.h +++ b/drivers/pinctrl/sh-pfc/sh_pfc.h @@ -98,17 +98,11 @@ struct pinmux_data_reg { .enum_ids = (const u16 [r_width]) \ struct pinmux_irq { - int irq; const short *gpios; }; -#ifdef CONFIG_ARCH_MULTIPLATFORM -#define PINMUX_IRQ(irq_nr, ids...) \ +#define PINMUX_IRQ(ids...) \ { .gpios = (const short []) { ids, -1 } } -#else -#define PINMUX_IRQ(irq_nr, ids...) \ - { .irq = irq_nr, .gpios = (const short []) { ids, -1 } } -#endif struct pinmux_range { u16 begin; -- cgit v0.10.2 From 2b67bccb478773347717d21781cf2bfd6db5c9fd Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Thu, 3 Sep 2015 02:49:14 +0000 Subject: pinctrl: sh-pfc: modify PINMUX_IPSR_MSEL() macro order The difference between PINMUX_IPSR_MSEL() and PINMUX_IPSR_MODSEL_DATA() are FN_xxx order, and PINMUX_IPSR_MSEL() is used only from r8a7778. Now it r8a7778 works correctly with PINMUX_IPSR_MODSEL_DATA() order. This means we can merge PINMUX_IPSR_MSEL() and PINMUX_IPSR_MODSEL_DATA(). Current PFC driver is very difficult to read, because macro names are using different length. Especially PINMUX_IPSR_MODSEL_DATA() is well used macro PINMUX_IPSR_NOGP(ispr, ...) PINMUX_IPSR_DATA(ipsr, ...) PINMUX_IPSR_NOGM(ispr, ...) PINMUX_IPSR_NOFN(ipsr, ...) PINMUX_IPSR_MSEL(ipsr, ...) PINMUX_IPSR_MODSEL_DATA(ipsr, ...) It can be readable if we can merge PINMUX_IPSR_MSEL() and PINMUX_IPSR_MODSEL_DATA() PINMUX_IPSR_NOGP(ispr, ...) PINMUX_IPSR_DATA(ipsr, ...) PINMUX_IPSR_NOGM(ispr, ...) PINMUX_IPSR_NOFN(ipsr, ...) PINMUX_IPSR_MSEL(ipsr, ...) Signed-off-by: Kuninori Morimoto Acked-by: Simon Horman Acked-by: Laurent Pinchart Acked-by: Linus Walleij Signed-off-by: Geert Uytterhoeven diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h index 1da8a1c..baf9b9b 100644 --- a/drivers/pinctrl/sh-pfc/sh_pfc.h +++ b/drivers/pinctrl/sh-pfc/sh_pfc.h @@ -173,7 +173,7 @@ struct sh_pfc_soc_info { #define PINMUX_IPSR_NOFN(ipsr, fn, ms) \ PINMUX_DATA(fn##_MARK, FN_##ipsr, FN_##ms) #define PINMUX_IPSR_MSEL(ipsr, fn, ms) \ - PINMUX_DATA(fn##_MARK, FN_##fn, FN_##ipsr, FN_##ms) + PINMUX_DATA(fn##_MARK, FN_##ms, FN_##ipsr, FN_##fn) #define PINMUX_IPSR_MODSEL_DATA(ipsr, fn, ms) \ PINMUX_DATA(fn##_MARK, FN_##ms, FN_##ipsr, FN_##fn) -- cgit v0.10.2 From 3d8c120be3fc003c0a0a8dc5a0e77f2dbd20ee68 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Thu, 3 Sep 2015 02:49:36 +0000 Subject: pinctrl: sh-pfc: sh7734: use PINMUX_IPSR_MSEL() Now, PINMUX_IPSR_MSEL() and PINMUX_IPSR_MODSEL_DATA() are same. Current PFC driver is very difficult to read, because macro names are using different length. PINMUX_IPSR_NOGP(ispr, ...) PINMUX_IPSR_DATA(ipsr, ...) PINMUX_IPSR_NOGM(ispr, ...) PINMUX_IPSR_NOFN(ipsr, ...) PINMUX_IPSR_MSEL(ipsr, ...) PINMUX_IPSR_MODSEL_DATA(ipsr, ...) It can be readable if we can use PINMUX_IPSR_MSEL() instead of PINMUX_IPSR_MODSEL_DATA() PINMUX_IPSR_NOGP(ispr, ...) PINMUX_IPSR_DATA(ipsr, ...) PINMUX_IPSR_NOGM(ispr, ...) PINMUX_IPSR_NOFN(ipsr, ...) PINMUX_IPSR_MSEL(ipsr, ...) Signed-off-by: Kuninori Morimoto Acked-by: Laurent Pinchart Acked-by: Linus Walleij Signed-off-by: Geert Uytterhoeven diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7734.c b/drivers/pinctrl/sh-pfc/pfc-sh7734.c index e53dd1c..59158a7 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh7734.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh7734.c @@ -598,502 +598,502 @@ static const u16 pinmux_data[] = { /* IPSR0 */ PINMUX_IPSR_DATA(IP0_1_0, A0), PINMUX_IPSR_DATA(IP0_1_0, ST0_CLKIN), - PINMUX_IPSR_MODSEL_DATA(IP0_1_0, LCD_DATA0_A, SEL_LCDC_0), - PINMUX_IPSR_MODSEL_DATA(IP0_1_0, TCLKA_C, SEL_MTU2_CLK_1), + PINMUX_IPSR_MSEL(IP0_1_0, LCD_DATA0_A, SEL_LCDC_0), + PINMUX_IPSR_MSEL(IP0_1_0, TCLKA_C, SEL_MTU2_CLK_1), PINMUX_IPSR_DATA(IP0_3_2, A1), PINMUX_IPSR_DATA(IP0_3_2, ST0_REQ), - PINMUX_IPSR_MODSEL_DATA(IP0_3_2, LCD_DATA1_A, SEL_LCDC_0), - PINMUX_IPSR_MODSEL_DATA(IP0_3_2, TCLKB_C, SEL_MTU2_CLK_1), + PINMUX_IPSR_MSEL(IP0_3_2, LCD_DATA1_A, SEL_LCDC_0), + PINMUX_IPSR_MSEL(IP0_3_2, TCLKB_C, SEL_MTU2_CLK_1), PINMUX_IPSR_DATA(IP0_5_4, A2), PINMUX_IPSR_DATA(IP0_5_4, ST0_SYC), - PINMUX_IPSR_MODSEL_DATA(IP0_5_4, LCD_DATA2_A, SEL_LCDC_0), - PINMUX_IPSR_MODSEL_DATA(IP0_5_4, TCLKC_C, SEL_MTU2_CLK_1), + PINMUX_IPSR_MSEL(IP0_5_4, LCD_DATA2_A, SEL_LCDC_0), + PINMUX_IPSR_MSEL(IP0_5_4, TCLKC_C, SEL_MTU2_CLK_1), PINMUX_IPSR_DATA(IP0_7_6, A3), PINMUX_IPSR_DATA(IP0_7_6, ST0_VLD), - PINMUX_IPSR_MODSEL_DATA(IP0_7_6, LCD_DATA3_A, SEL_LCDC_0), - PINMUX_IPSR_MODSEL_DATA(IP0_7_6, TCLKD_C, SEL_MTU2_CLK_1), + PINMUX_IPSR_MSEL(IP0_7_6, LCD_DATA3_A, SEL_LCDC_0), + PINMUX_IPSR_MSEL(IP0_7_6, TCLKD_C, SEL_MTU2_CLK_1), PINMUX_IPSR_DATA(IP0_9_8, A4), PINMUX_IPSR_DATA(IP0_9_8, ST0_D0), - PINMUX_IPSR_MODSEL_DATA(IP0_9_8, LCD_DATA4_A, SEL_LCDC_0), - PINMUX_IPSR_MODSEL_DATA(IP0_9_8, TIOC0A_C, SEL_MTU2_CH0_1), + PINMUX_IPSR_MSEL(IP0_9_8, LCD_DATA4_A, SEL_LCDC_0), + PINMUX_IPSR_MSEL(IP0_9_8, TIOC0A_C, SEL_MTU2_CH0_1), PINMUX_IPSR_DATA(IP0_11_10, A5), PINMUX_IPSR_DATA(IP0_11_10, ST0_D1), - PINMUX_IPSR_MODSEL_DATA(IP0_11_10, LCD_DATA5_A, SEL_LCDC_0), - PINMUX_IPSR_MODSEL_DATA(IP0_11_10, TIOC0B_C, SEL_MTU2_CH0_1), + PINMUX_IPSR_MSEL(IP0_11_10, LCD_DATA5_A, SEL_LCDC_0), + PINMUX_IPSR_MSEL(IP0_11_10, TIOC0B_C, SEL_MTU2_CH0_1), PINMUX_IPSR_DATA(IP0_13_12, A6), PINMUX_IPSR_DATA(IP0_13_12, ST0_D2), - PINMUX_IPSR_MODSEL_DATA(IP0_13_12, LCD_DATA6_A, SEL_LCDC_0), - PINMUX_IPSR_MODSEL_DATA(IP0_13_12, TIOC0C_C, SEL_MTU2_CH0_1), + PINMUX_IPSR_MSEL(IP0_13_12, LCD_DATA6_A, SEL_LCDC_0), + PINMUX_IPSR_MSEL(IP0_13_12, TIOC0C_C, SEL_MTU2_CH0_1), PINMUX_IPSR_DATA(IP0_15_14, A7), PINMUX_IPSR_DATA(IP0_15_14, ST0_D3), - PINMUX_IPSR_MODSEL_DATA(IP0_15_14, LCD_DATA7_A, SEL_LCDC_0), - PINMUX_IPSR_MODSEL_DATA(IP0_15_14, TIOC0D_C, SEL_MTU2_CH0_1), + PINMUX_IPSR_MSEL(IP0_15_14, LCD_DATA7_A, SEL_LCDC_0), + PINMUX_IPSR_MSEL(IP0_15_14, TIOC0D_C, SEL_MTU2_CH0_1), PINMUX_IPSR_DATA(IP0_17_16, A8), PINMUX_IPSR_DATA(IP0_17_16, ST0_D4), - PINMUX_IPSR_MODSEL_DATA(IP0_17_16, LCD_DATA8_A, SEL_LCDC_0), - PINMUX_IPSR_MODSEL_DATA(IP0_17_16, TIOC1A_C, SEL_MTU2_CH1_2), + PINMUX_IPSR_MSEL(IP0_17_16, LCD_DATA8_A, SEL_LCDC_0), + PINMUX_IPSR_MSEL(IP0_17_16, TIOC1A_C, SEL_MTU2_CH1_2), PINMUX_IPSR_DATA(IP0_19_18, A9), PINMUX_IPSR_DATA(IP0_19_18, ST0_D5), - PINMUX_IPSR_MODSEL_DATA(IP0_19_18, LCD_DATA9_A, SEL_LCDC_0), - PINMUX_IPSR_MODSEL_DATA(IP0_19_18, TIOC1B_C, SEL_MTU2_CH1_2), + PINMUX_IPSR_MSEL(IP0_19_18, LCD_DATA9_A, SEL_LCDC_0), + PINMUX_IPSR_MSEL(IP0_19_18, TIOC1B_C, SEL_MTU2_CH1_2), PINMUX_IPSR_DATA(IP0_21_20, A10), PINMUX_IPSR_DATA(IP0_21_20, ST0_D6), - PINMUX_IPSR_MODSEL_DATA(IP0_21_20, LCD_DATA10_A, SEL_LCDC_0), - PINMUX_IPSR_MODSEL_DATA(IP0_21_20, TIOC2A_C, SEL_MTU2_CH2_2), + PINMUX_IPSR_MSEL(IP0_21_20, LCD_DATA10_A, SEL_LCDC_0), + PINMUX_IPSR_MSEL(IP0_21_20, TIOC2A_C, SEL_MTU2_CH2_2), PINMUX_IPSR_DATA(IP0_23_22, A11), PINMUX_IPSR_DATA(IP0_23_22, ST0_D7), - PINMUX_IPSR_MODSEL_DATA(IP0_23_22, LCD_DATA11_A, SEL_LCDC_0), - PINMUX_IPSR_MODSEL_DATA(IP0_23_22, TIOC2B_C, SEL_MTU2_CH2_2), + PINMUX_IPSR_MSEL(IP0_23_22, LCD_DATA11_A, SEL_LCDC_0), + PINMUX_IPSR_MSEL(IP0_23_22, TIOC2B_C, SEL_MTU2_CH2_2), PINMUX_IPSR_DATA(IP0_25_24, A12), - PINMUX_IPSR_MODSEL_DATA(IP0_25_24, LCD_DATA12_A, SEL_LCDC_0), - PINMUX_IPSR_MODSEL_DATA(IP0_25_24, TIOC3A_C, SEL_MTU2_CH3_1), + PINMUX_IPSR_MSEL(IP0_25_24, LCD_DATA12_A, SEL_LCDC_0), + PINMUX_IPSR_MSEL(IP0_25_24, TIOC3A_C, SEL_MTU2_CH3_1), PINMUX_IPSR_DATA(IP0_27_26, A13), - PINMUX_IPSR_MODSEL_DATA(IP0_27_26, LCD_DATA13_A, SEL_LCDC_0), - PINMUX_IPSR_MODSEL_DATA(IP0_27_26, TIOC3B_C, SEL_MTU2_CH3_1), + PINMUX_IPSR_MSEL(IP0_27_26, LCD_DATA13_A, SEL_LCDC_0), + PINMUX_IPSR_MSEL(IP0_27_26, TIOC3B_C, SEL_MTU2_CH3_1), PINMUX_IPSR_DATA(IP0_29_28, A14), - PINMUX_IPSR_MODSEL_DATA(IP0_29_28, LCD_DATA14_A, SEL_LCDC_0), - PINMUX_IPSR_MODSEL_DATA(IP0_29_28, TIOC3C_C, SEL_MTU2_CH3_1), + PINMUX_IPSR_MSEL(IP0_29_28, LCD_DATA14_A, SEL_LCDC_0), + PINMUX_IPSR_MSEL(IP0_29_28, TIOC3C_C, SEL_MTU2_CH3_1), PINMUX_IPSR_DATA(IP0_31_30, A15), PINMUX_IPSR_DATA(IP0_31_30, ST0_VCO_CLKIN), - PINMUX_IPSR_MODSEL_DATA(IP0_31_30, LCD_DATA15_A, SEL_LCDC_0), - PINMUX_IPSR_MODSEL_DATA(IP0_31_30, TIOC3D_C, SEL_MTU2_CH3_1), + PINMUX_IPSR_MSEL(IP0_31_30, LCD_DATA15_A, SEL_LCDC_0), + PINMUX_IPSR_MSEL(IP0_31_30, TIOC3D_C, SEL_MTU2_CH3_1), /* IPSR1 */ PINMUX_IPSR_DATA(IP1_1_0, A16), PINMUX_IPSR_DATA(IP1_1_0, ST0_PWM), - PINMUX_IPSR_MODSEL_DATA(IP1_1_0, LCD_DON_A, SEL_LCDC_0), - PINMUX_IPSR_MODSEL_DATA(IP1_1_0, TIOC4A_C, SEL_MTU2_CH4_1), + PINMUX_IPSR_MSEL(IP1_1_0, LCD_DON_A, SEL_LCDC_0), + PINMUX_IPSR_MSEL(IP1_1_0, TIOC4A_C, SEL_MTU2_CH4_1), PINMUX_IPSR_DATA(IP1_3_2, A17), PINMUX_IPSR_DATA(IP1_3_2, ST1_VCO_CLKIN), - PINMUX_IPSR_MODSEL_DATA(IP1_3_2, LCD_CL1_A, SEL_LCDC_0), - PINMUX_IPSR_MODSEL_DATA(IP1_3_2, TIOC4B_C, SEL_MTU2_CH4_1), + PINMUX_IPSR_MSEL(IP1_3_2, LCD_CL1_A, SEL_LCDC_0), + PINMUX_IPSR_MSEL(IP1_3_2, TIOC4B_C, SEL_MTU2_CH4_1), PINMUX_IPSR_DATA(IP1_5_4, A18), PINMUX_IPSR_DATA(IP1_5_4, ST1_PWM), - PINMUX_IPSR_MODSEL_DATA(IP1_5_4, LCD_CL2_A, SEL_LCDC_0), - PINMUX_IPSR_MODSEL_DATA(IP1_5_4, TIOC4C_C, SEL_MTU2_CH4_1), + PINMUX_IPSR_MSEL(IP1_5_4, LCD_CL2_A, SEL_LCDC_0), + PINMUX_IPSR_MSEL(IP1_5_4, TIOC4C_C, SEL_MTU2_CH4_1), PINMUX_IPSR_DATA(IP1_7_6, A19), PINMUX_IPSR_DATA(IP1_7_6, ST1_CLKIN), - PINMUX_IPSR_MODSEL_DATA(IP1_7_6, LCD_CLK_A, SEL_LCDC_0), - PINMUX_IPSR_MODSEL_DATA(IP1_7_6, TIOC4D_C, SEL_MTU2_CH4_1), + PINMUX_IPSR_MSEL(IP1_7_6, LCD_CLK_A, SEL_LCDC_0), + PINMUX_IPSR_MSEL(IP1_7_6, TIOC4D_C, SEL_MTU2_CH4_1), PINMUX_IPSR_DATA(IP1_9_8, A20), PINMUX_IPSR_DATA(IP1_9_8, ST1_REQ), - PINMUX_IPSR_MODSEL_DATA(IP1_9_8, LCD_FLM_A, SEL_LCDC_0), + PINMUX_IPSR_MSEL(IP1_9_8, LCD_FLM_A, SEL_LCDC_0), PINMUX_IPSR_DATA(IP1_11_10, A21), PINMUX_IPSR_DATA(IP1_11_10, ST1_SYC), - PINMUX_IPSR_MODSEL_DATA(IP1_11_10, LCD_VCPWC_A, SEL_LCDC_0), + PINMUX_IPSR_MSEL(IP1_11_10, LCD_VCPWC_A, SEL_LCDC_0), PINMUX_IPSR_DATA(IP1_13_12, A22), PINMUX_IPSR_DATA(IP1_13_12, ST1_VLD), - PINMUX_IPSR_MODSEL_DATA(IP1_13_12, LCD_VEPWC_A, SEL_LCDC_0), + PINMUX_IPSR_MSEL(IP1_13_12, LCD_VEPWC_A, SEL_LCDC_0), PINMUX_IPSR_DATA(IP1_15_14, A23), PINMUX_IPSR_DATA(IP1_15_14, ST1_D0), - PINMUX_IPSR_MODSEL_DATA(IP1_15_14, LCD_M_DISP_A, SEL_LCDC_0), + PINMUX_IPSR_MSEL(IP1_15_14, LCD_M_DISP_A, SEL_LCDC_0), PINMUX_IPSR_DATA(IP1_17_16, A24), - PINMUX_IPSR_MODSEL_DATA(IP1_17_16, RX2_D, SEL_SCIF2_3), + PINMUX_IPSR_MSEL(IP1_17_16, RX2_D, SEL_SCIF2_3), PINMUX_IPSR_DATA(IP1_17_16, ST1_D1), PINMUX_IPSR_DATA(IP1_19_18, A25), - PINMUX_IPSR_MODSEL_DATA(IP1_17_16, RX2_D, SEL_SCIF2_3), + PINMUX_IPSR_MSEL(IP1_17_16, RX2_D, SEL_SCIF2_3), PINMUX_IPSR_DATA(IP1_17_16, ST1_D2), PINMUX_IPSR_DATA(IP1_22_20, D0), - PINMUX_IPSR_MODSEL_DATA(IP1_22_20, SD0_DAT0_A, SEL_SDHI0_0), - PINMUX_IPSR_MODSEL_DATA(IP1_22_20, MMC_D0_A, SEL_MMC_0), + PINMUX_IPSR_MSEL(IP1_22_20, SD0_DAT0_A, SEL_SDHI0_0), + PINMUX_IPSR_MSEL(IP1_22_20, MMC_D0_A, SEL_MMC_0), PINMUX_IPSR_DATA(IP1_22_20, ST1_D3), - PINMUX_IPSR_MODSEL_DATA(IP1_22_20, FD0_A, SEL_FLCTL_0), + PINMUX_IPSR_MSEL(IP1_22_20, FD0_A, SEL_FLCTL_0), PINMUX_IPSR_DATA(IP1_25_23, D1), - PINMUX_IPSR_MODSEL_DATA(IP1_25_23, SD0_DAT0_A, SEL_SDHI0_0), - PINMUX_IPSR_MODSEL_DATA(IP1_25_23, MMC_D1_A, SEL_MMC_0), + PINMUX_IPSR_MSEL(IP1_25_23, SD0_DAT0_A, SEL_SDHI0_0), + PINMUX_IPSR_MSEL(IP1_25_23, MMC_D1_A, SEL_MMC_0), PINMUX_IPSR_DATA(IP1_25_23, ST1_D4), - PINMUX_IPSR_MODSEL_DATA(IP1_25_23, FD1_A, SEL_FLCTL_0), + PINMUX_IPSR_MSEL(IP1_25_23, FD1_A, SEL_FLCTL_0), PINMUX_IPSR_DATA(IP1_28_26, D2), - PINMUX_IPSR_MODSEL_DATA(IP1_28_26, SD0_DAT0_A, SEL_SDHI0_0), - PINMUX_IPSR_MODSEL_DATA(IP1_28_26, MMC_D2_A, SEL_MMC_0), + PINMUX_IPSR_MSEL(IP1_28_26, SD0_DAT0_A, SEL_SDHI0_0), + PINMUX_IPSR_MSEL(IP1_28_26, MMC_D2_A, SEL_MMC_0), PINMUX_IPSR_DATA(IP1_28_26, ST1_D5), - PINMUX_IPSR_MODSEL_DATA(IP1_28_26, FD2_A, SEL_FLCTL_0), + PINMUX_IPSR_MSEL(IP1_28_26, FD2_A, SEL_FLCTL_0), PINMUX_IPSR_DATA(IP1_31_29, D3), - PINMUX_IPSR_MODSEL_DATA(IP1_31_29, SD0_DAT0_A, SEL_SDHI0_0), - PINMUX_IPSR_MODSEL_DATA(IP1_31_29, MMC_D3_A, SEL_MMC_0), + PINMUX_IPSR_MSEL(IP1_31_29, SD0_DAT0_A, SEL_SDHI0_0), + PINMUX_IPSR_MSEL(IP1_31_29, MMC_D3_A, SEL_MMC_0), PINMUX_IPSR_DATA(IP1_31_29, ST1_D6), - PINMUX_IPSR_MODSEL_DATA(IP1_31_29, FD3_A, SEL_FLCTL_0), + PINMUX_IPSR_MSEL(IP1_31_29, FD3_A, SEL_FLCTL_0), /* IPSR2 */ PINMUX_IPSR_DATA(IP2_2_0, D4), - PINMUX_IPSR_MODSEL_DATA(IP2_2_0, SD0_CD_A, SEL_SDHI0_0), - PINMUX_IPSR_MODSEL_DATA(IP2_2_0, MMC_D4_A, SEL_MMC_0), + PINMUX_IPSR_MSEL(IP2_2_0, SD0_CD_A, SEL_SDHI0_0), + PINMUX_IPSR_MSEL(IP2_2_0, MMC_D4_A, SEL_MMC_0), PINMUX_IPSR_DATA(IP2_2_0, ST1_D7), - PINMUX_IPSR_MODSEL_DATA(IP2_2_0, FD4_A, SEL_FLCTL_0), + PINMUX_IPSR_MSEL(IP2_2_0, FD4_A, SEL_FLCTL_0), PINMUX_IPSR_DATA(IP2_4_3, D5), - PINMUX_IPSR_MODSEL_DATA(IP2_4_3, SD0_WP_A, SEL_SDHI0_0), - PINMUX_IPSR_MODSEL_DATA(IP2_4_3, MMC_D5_A, SEL_MMC_0), - PINMUX_IPSR_MODSEL_DATA(IP2_4_3, FD5_A, SEL_FLCTL_0), + PINMUX_IPSR_MSEL(IP2_4_3, SD0_WP_A, SEL_SDHI0_0), + PINMUX_IPSR_MSEL(IP2_4_3, MMC_D5_A, SEL_MMC_0), + PINMUX_IPSR_MSEL(IP2_4_3, FD5_A, SEL_FLCTL_0), PINMUX_IPSR_DATA(IP2_7_5, D6), - PINMUX_IPSR_MODSEL_DATA(IP2_7_5, RSPI_RSPCK_A, SEL_RSPI_0), - PINMUX_IPSR_MODSEL_DATA(IP2_7_5, MMC_D6_A, SEL_MMC_0), - PINMUX_IPSR_MODSEL_DATA(IP2_7_5, QSPCLK_A, SEL_RQSPI_0), - PINMUX_IPSR_MODSEL_DATA(IP2_7_5, FD6_A, SEL_FLCTL_0), + PINMUX_IPSR_MSEL(IP2_7_5, RSPI_RSPCK_A, SEL_RSPI_0), + PINMUX_IPSR_MSEL(IP2_7_5, MMC_D6_A, SEL_MMC_0), + PINMUX_IPSR_MSEL(IP2_7_5, QSPCLK_A, SEL_RQSPI_0), + PINMUX_IPSR_MSEL(IP2_7_5, FD6_A, SEL_FLCTL_0), PINMUX_IPSR_DATA(IP2_10_8, D7), - PINMUX_IPSR_MODSEL_DATA(IP2_10_8, RSPI_SSL_A, SEL_RSPI_0), - PINMUX_IPSR_MODSEL_DATA(IP2_10_8, MMC_D7_A, SEL_MMC_0), - PINMUX_IPSR_MODSEL_DATA(IP2_10_8, QSSL_A, SEL_RQSPI_0), - PINMUX_IPSR_MODSEL_DATA(IP2_10_8, FD7_A, SEL_FLCTL_0), + PINMUX_IPSR_MSEL(IP2_10_8, RSPI_SSL_A, SEL_RSPI_0), + PINMUX_IPSR_MSEL(IP2_10_8, MMC_D7_A, SEL_MMC_0), + PINMUX_IPSR_MSEL(IP2_10_8, QSSL_A, SEL_RQSPI_0), + PINMUX_IPSR_MSEL(IP2_10_8, FD7_A, SEL_FLCTL_0), PINMUX_IPSR_DATA(IP2_13_11, D8), - PINMUX_IPSR_MODSEL_DATA(IP2_13_11, SD0_CLK_A, SEL_SDHI0_0), - PINMUX_IPSR_MODSEL_DATA(IP2_13_11, MMC_CLK_A, SEL_MMC_0), - PINMUX_IPSR_MODSEL_DATA(IP2_13_11, QIO2_A, SEL_RQSPI_0), - PINMUX_IPSR_MODSEL_DATA(IP2_13_11, FCE_A, SEL_FLCTL_0), - PINMUX_IPSR_MODSEL_DATA(IP2_13_11, ET0_GTX_CLK_B, SEL_ET0_1), + PINMUX_IPSR_MSEL(IP2_13_11, SD0_CLK_A, SEL_SDHI0_0), + PINMUX_IPSR_MSEL(IP2_13_11, MMC_CLK_A, SEL_MMC_0), + PINMUX_IPSR_MSEL(IP2_13_11, QIO2_A, SEL_RQSPI_0), + PINMUX_IPSR_MSEL(IP2_13_11, FCE_A, SEL_FLCTL_0), + PINMUX_IPSR_MSEL(IP2_13_11, ET0_GTX_CLK_B, SEL_ET0_1), PINMUX_IPSR_DATA(IP2_16_14, D9), - PINMUX_IPSR_MODSEL_DATA(IP2_16_14, SD0_CMD_A, SEL_SDHI0_0), - PINMUX_IPSR_MODSEL_DATA(IP2_16_14, MMC_CMD_A, SEL_MMC_0), - PINMUX_IPSR_MODSEL_DATA(IP2_16_14, QIO3_A, SEL_RQSPI_0), - PINMUX_IPSR_MODSEL_DATA(IP2_16_14, FCLE_A, SEL_FLCTL_0), - PINMUX_IPSR_MODSEL_DATA(IP2_16_14, ET0_ETXD1_B, SEL_ET0_1), + PINMUX_IPSR_MSEL(IP2_16_14, SD0_CMD_A, SEL_SDHI0_0), + PINMUX_IPSR_MSEL(IP2_16_14, MMC_CMD_A, SEL_MMC_0), + PINMUX_IPSR_MSEL(IP2_16_14, QIO3_A, SEL_RQSPI_0), + PINMUX_IPSR_MSEL(IP2_16_14, FCLE_A, SEL_FLCTL_0), + PINMUX_IPSR_MSEL(IP2_16_14, ET0_ETXD1_B, SEL_ET0_1), PINMUX_IPSR_DATA(IP2_19_17, D10), - PINMUX_IPSR_MODSEL_DATA(IP2_19_17, RSPI_MOSI_A, SEL_RSPI_0), - PINMUX_IPSR_MODSEL_DATA(IP2_19_17, QMO_QIO0_A, SEL_RQSPI_0), - PINMUX_IPSR_MODSEL_DATA(IP2_19_17, FALE_A, SEL_FLCTL_0), - PINMUX_IPSR_MODSEL_DATA(IP2_19_17, ET0_ETXD2_B, SEL_ET0_1), + PINMUX_IPSR_MSEL(IP2_19_17, RSPI_MOSI_A, SEL_RSPI_0), + PINMUX_IPSR_MSEL(IP2_19_17, QMO_QIO0_A, SEL_RQSPI_0), + PINMUX_IPSR_MSEL(IP2_19_17, FALE_A, SEL_FLCTL_0), + PINMUX_IPSR_MSEL(IP2_19_17, ET0_ETXD2_B, SEL_ET0_1), PINMUX_IPSR_DATA(IP2_22_20, D11), - PINMUX_IPSR_MODSEL_DATA(IP2_22_20, RSPI_MISO_A, SEL_RSPI_0), - PINMUX_IPSR_MODSEL_DATA(IP2_22_20, QMI_QIO1_A, SEL_RQSPI_0), - PINMUX_IPSR_MODSEL_DATA(IP2_22_20, FRE_A, SEL_FLCTL_0), + PINMUX_IPSR_MSEL(IP2_22_20, RSPI_MISO_A, SEL_RSPI_0), + PINMUX_IPSR_MSEL(IP2_22_20, QMI_QIO1_A, SEL_RQSPI_0), + PINMUX_IPSR_MSEL(IP2_22_20, FRE_A, SEL_FLCTL_0), PINMUX_IPSR_DATA(IP2_24_23, D12), - PINMUX_IPSR_MODSEL_DATA(IP2_24_23, FWE_A, SEL_FLCTL_0), - PINMUX_IPSR_MODSEL_DATA(IP2_24_23, ET0_ETXD5_B, SEL_ET0_1), + PINMUX_IPSR_MSEL(IP2_24_23, FWE_A, SEL_FLCTL_0), + PINMUX_IPSR_MSEL(IP2_24_23, ET0_ETXD5_B, SEL_ET0_1), PINMUX_IPSR_DATA(IP2_27_25, D13), - PINMUX_IPSR_MODSEL_DATA(IP2_27_25, RX2_B, SEL_SCIF2_1), - PINMUX_IPSR_MODSEL_DATA(IP2_27_25, FRB_A, SEL_FLCTL_0), - PINMUX_IPSR_MODSEL_DATA(IP2_27_25, ET0_ETXD6_B, SEL_ET0_1), + PINMUX_IPSR_MSEL(IP2_27_25, RX2_B, SEL_SCIF2_1), + PINMUX_IPSR_MSEL(IP2_27_25, FRB_A, SEL_FLCTL_0), + PINMUX_IPSR_MSEL(IP2_27_25, ET0_ETXD6_B, SEL_ET0_1), PINMUX_IPSR_DATA(IP2_30_28, D14), - PINMUX_IPSR_MODSEL_DATA(IP2_30_28, TX2_B, SEL_SCIF2_1), - PINMUX_IPSR_MODSEL_DATA(IP2_30_28, FSE_A, SEL_FLCTL_0), - PINMUX_IPSR_MODSEL_DATA(IP2_30_28, ET0_TX_CLK_B, SEL_ET0_1), + PINMUX_IPSR_MSEL(IP2_30_28, TX2_B, SEL_SCIF2_1), + PINMUX_IPSR_MSEL(IP2_30_28, FSE_A, SEL_FLCTL_0), + PINMUX_IPSR_MSEL(IP2_30_28, ET0_TX_CLK_B, SEL_ET0_1), /* IPSR3 */ PINMUX_IPSR_DATA(IP3_1_0, D15), - PINMUX_IPSR_MODSEL_DATA(IP3_1_0, SCK2_B, SEL_SCIF2_1), + PINMUX_IPSR_MSEL(IP3_1_0, SCK2_B, SEL_SCIF2_1), PINMUX_IPSR_DATA(IP3_2, CS1_A26), - PINMUX_IPSR_MODSEL_DATA(IP3_2, QIO3_B, SEL_RQSPI_1), + PINMUX_IPSR_MSEL(IP3_2, QIO3_B, SEL_RQSPI_1), PINMUX_IPSR_DATA(IP3_5_3, EX_CS1), - PINMUX_IPSR_MODSEL_DATA(IP3_5_3, RX3_B, SEL_SCIF2_1), + PINMUX_IPSR_MSEL(IP3_5_3, RX3_B, SEL_SCIF2_1), PINMUX_IPSR_DATA(IP3_5_3, ATACS0), - PINMUX_IPSR_MODSEL_DATA(IP3_5_3, QIO2_B, SEL_RQSPI_1), + PINMUX_IPSR_MSEL(IP3_5_3, QIO2_B, SEL_RQSPI_1), PINMUX_IPSR_DATA(IP3_5_3, ET0_ETXD0), PINMUX_IPSR_DATA(IP3_8_6, EX_CS2), - PINMUX_IPSR_MODSEL_DATA(IP3_8_6, TX3_B, SEL_SCIF3_1), + PINMUX_IPSR_MSEL(IP3_8_6, TX3_B, SEL_SCIF3_1), PINMUX_IPSR_DATA(IP3_8_6, ATACS1), - PINMUX_IPSR_MODSEL_DATA(IP3_8_6, QSPCLK_B, SEL_RQSPI_1), - PINMUX_IPSR_MODSEL_DATA(IP3_8_6, ET0_GTX_CLK_A, SEL_ET0_0), + PINMUX_IPSR_MSEL(IP3_8_6, QSPCLK_B, SEL_RQSPI_1), + PINMUX_IPSR_MSEL(IP3_8_6, ET0_GTX_CLK_A, SEL_ET0_0), PINMUX_IPSR_DATA(IP3_11_9, EX_CS3), - PINMUX_IPSR_MODSEL_DATA(IP3_11_9, SD1_CD_A, SEL_SDHI1_0), + PINMUX_IPSR_MSEL(IP3_11_9, SD1_CD_A, SEL_SDHI1_0), PINMUX_IPSR_DATA(IP3_11_9, ATARD), - PINMUX_IPSR_MODSEL_DATA(IP3_11_9, QMO_QIO0_B, SEL_RQSPI_1), - PINMUX_IPSR_MODSEL_DATA(IP3_11_9, ET0_ETXD1_A, SEL_ET0_0), + PINMUX_IPSR_MSEL(IP3_11_9, QMO_QIO0_B, SEL_RQSPI_1), + PINMUX_IPSR_MSEL(IP3_11_9, ET0_ETXD1_A, SEL_ET0_0), PINMUX_IPSR_DATA(IP3_14_12, EX_CS4), - PINMUX_IPSR_MODSEL_DATA(IP3_14_12, SD1_WP_A, SEL_SDHI1_0), + PINMUX_IPSR_MSEL(IP3_14_12, SD1_WP_A, SEL_SDHI1_0), PINMUX_IPSR_DATA(IP3_14_12, ATAWR), - PINMUX_IPSR_MODSEL_DATA(IP3_14_12, QMI_QIO1_B, SEL_RQSPI_1), - PINMUX_IPSR_MODSEL_DATA(IP3_14_12, ET0_ETXD2_A, SEL_ET0_0), + PINMUX_IPSR_MSEL(IP3_14_12, QMI_QIO1_B, SEL_RQSPI_1), + PINMUX_IPSR_MSEL(IP3_14_12, ET0_ETXD2_A, SEL_ET0_0), PINMUX_IPSR_DATA(IP3_17_15, EX_CS5), - PINMUX_IPSR_MODSEL_DATA(IP3_17_15, SD1_CMD_A, SEL_SDHI1_0), + PINMUX_IPSR_MSEL(IP3_17_15, SD1_CMD_A, SEL_SDHI1_0), PINMUX_IPSR_DATA(IP3_17_15, ATADIR), - PINMUX_IPSR_MODSEL_DATA(IP3_17_15, QSSL_B, SEL_RQSPI_1), - PINMUX_IPSR_MODSEL_DATA(IP3_17_15, ET0_ETXD3_A, SEL_ET0_0), + PINMUX_IPSR_MSEL(IP3_17_15, QSSL_B, SEL_RQSPI_1), + PINMUX_IPSR_MSEL(IP3_17_15, ET0_ETXD3_A, SEL_ET0_0), PINMUX_IPSR_DATA(IP3_19_18, RD_WR), PINMUX_IPSR_DATA(IP3_19_18, TCLK0), - PINMUX_IPSR_MODSEL_DATA(IP3_19_18, CAN_CLK_B, SEL_RCAN_CLK_1), + PINMUX_IPSR_MSEL(IP3_19_18, CAN_CLK_B, SEL_RCAN_CLK_1), PINMUX_IPSR_DATA(IP3_19_18, ET0_ETXD4), PINMUX_IPSR_DATA(IP3_20, EX_WAIT0), - PINMUX_IPSR_MODSEL_DATA(IP3_20, TCLK1_B, SEL_TMU_1), + PINMUX_IPSR_MSEL(IP3_20, TCLK1_B, SEL_TMU_1), PINMUX_IPSR_DATA(IP3_23_21, EX_WAIT1), - PINMUX_IPSR_MODSEL_DATA(IP3_23_21, SD1_DAT0_A, SEL_SDHI1_0), + PINMUX_IPSR_MSEL(IP3_23_21, SD1_DAT0_A, SEL_SDHI1_0), PINMUX_IPSR_DATA(IP3_23_21, DREQ2), - PINMUX_IPSR_MODSEL_DATA(IP3_23_21, CAN1_TX_C, SEL_RCAN1_2), - PINMUX_IPSR_MODSEL_DATA(IP3_23_21, ET0_LINK_C, SEL_ET0_CTL_2), - PINMUX_IPSR_MODSEL_DATA(IP3_23_21, ET0_ETXD5_A, SEL_ET0_0), + PINMUX_IPSR_MSEL(IP3_23_21, CAN1_TX_C, SEL_RCAN1_2), + PINMUX_IPSR_MSEL(IP3_23_21, ET0_LINK_C, SEL_ET0_CTL_2), + PINMUX_IPSR_MSEL(IP3_23_21, ET0_ETXD5_A, SEL_ET0_0), PINMUX_IPSR_DATA(IP3_26_24, EX_WAIT2), - PINMUX_IPSR_MODSEL_DATA(IP3_26_24, SD1_DAT1_A, SEL_SDHI1_0), + PINMUX_IPSR_MSEL(IP3_26_24, SD1_DAT1_A, SEL_SDHI1_0), PINMUX_IPSR_DATA(IP3_26_24, DACK2), - PINMUX_IPSR_MODSEL_DATA(IP3_26_24, CAN1_RX_C, SEL_RCAN1_2), - PINMUX_IPSR_MODSEL_DATA(IP3_26_24, ET0_MAGIC_C, SEL_ET0_CTL_2), - PINMUX_IPSR_MODSEL_DATA(IP3_26_24, ET0_ETXD6_A, SEL_ET0_0), + PINMUX_IPSR_MSEL(IP3_26_24, CAN1_RX_C, SEL_RCAN1_2), + PINMUX_IPSR_MSEL(IP3_26_24, ET0_MAGIC_C, SEL_ET0_CTL_2), + PINMUX_IPSR_MSEL(IP3_26_24, ET0_ETXD6_A, SEL_ET0_0), PINMUX_IPSR_DATA(IP3_29_27, DRACK0), - PINMUX_IPSR_MODSEL_DATA(IP3_29_27, SD1_DAT2_A, SEL_SDHI1_0), + PINMUX_IPSR_MSEL(IP3_29_27, SD1_DAT2_A, SEL_SDHI1_0), PINMUX_IPSR_DATA(IP3_29_27, ATAG), - PINMUX_IPSR_MODSEL_DATA(IP3_29_27, TCLK1_A, SEL_TMU_0), + PINMUX_IPSR_MSEL(IP3_29_27, TCLK1_A, SEL_TMU_0), PINMUX_IPSR_DATA(IP3_29_27, ET0_ETXD7), /* IPSR4 */ - PINMUX_IPSR_MODSEL_DATA(IP4_2_0, HCTS0_A, SEL_HSCIF_0), - PINMUX_IPSR_MODSEL_DATA(IP4_2_0, CTS1_A, SEL_SCIF1_0), + PINMUX_IPSR_MSEL(IP4_2_0, HCTS0_A, SEL_HSCIF_0), + PINMUX_IPSR_MSEL(IP4_2_0, CTS1_A, SEL_SCIF1_0), PINMUX_IPSR_DATA(IP4_2_0, VI0_FIELD), - PINMUX_IPSR_MODSEL_DATA(IP4_2_0, RMII0_RXD1_A, SEL_RMII_0), + PINMUX_IPSR_MSEL(IP4_2_0, RMII0_RXD1_A, SEL_RMII_0), PINMUX_IPSR_DATA(IP4_2_0, ET0_ERXD7), - PINMUX_IPSR_MODSEL_DATA(IP4_5_3, HRTS0_A, SEL_HSCIF_0), - PINMUX_IPSR_MODSEL_DATA(IP4_5_3, RTS1_A, SEL_SCIF1_0), + PINMUX_IPSR_MSEL(IP4_5_3, HRTS0_A, SEL_HSCIF_0), + PINMUX_IPSR_MSEL(IP4_5_3, RTS1_A, SEL_SCIF1_0), PINMUX_IPSR_DATA(IP4_5_3, VI0_HSYNC), - PINMUX_IPSR_MODSEL_DATA(IP4_5_3, RMII0_TXD_EN_A, SEL_RMII_0), + PINMUX_IPSR_MSEL(IP4_5_3, RMII0_TXD_EN_A, SEL_RMII_0), PINMUX_IPSR_DATA(IP4_5_3, ET0_RX_DV), - PINMUX_IPSR_MODSEL_DATA(IP4_8_6, HSCK0_A, SEL_HSCIF_0), - PINMUX_IPSR_MODSEL_DATA(IP4_8_6, SCK1_A, SEL_SCIF1_0), + PINMUX_IPSR_MSEL(IP4_8_6, HSCK0_A, SEL_HSCIF_0), + PINMUX_IPSR_MSEL(IP4_8_6, SCK1_A, SEL_SCIF1_0), PINMUX_IPSR_DATA(IP4_8_6, VI0_VSYNC), - PINMUX_IPSR_MODSEL_DATA(IP4_8_6, RMII0_RX_ER_A, SEL_RMII_0), + PINMUX_IPSR_MSEL(IP4_8_6, RMII0_RX_ER_A, SEL_RMII_0), PINMUX_IPSR_DATA(IP4_8_6, ET0_RX_ER), - PINMUX_IPSR_MODSEL_DATA(IP4_11_9, HRX0_A, SEL_HSCIF_0), - PINMUX_IPSR_MODSEL_DATA(IP4_11_9, RX1_A, SEL_SCIF1_0), + PINMUX_IPSR_MSEL(IP4_11_9, HRX0_A, SEL_HSCIF_0), + PINMUX_IPSR_MSEL(IP4_11_9, RX1_A, SEL_SCIF1_0), PINMUX_IPSR_DATA(IP4_11_9, VI0_DATA0_VI0_B0), - PINMUX_IPSR_MODSEL_DATA(IP4_11_9, RMII0_CRS_DV_A, SEL_RMII_0), + PINMUX_IPSR_MSEL(IP4_11_9, RMII0_CRS_DV_A, SEL_RMII_0), PINMUX_IPSR_DATA(IP4_11_9, ET0_CRS), - PINMUX_IPSR_MODSEL_DATA(IP4_14_12, HTX0_A, SEL_HSCIF_0), - PINMUX_IPSR_MODSEL_DATA(IP4_14_12, TX1_A, SEL_SCIF1_0), + PINMUX_IPSR_MSEL(IP4_14_12, HTX0_A, SEL_HSCIF_0), + PINMUX_IPSR_MSEL(IP4_14_12, TX1_A, SEL_SCIF1_0), PINMUX_IPSR_DATA(IP4_14_12, VI0_DATA1_VI0_B1), - PINMUX_IPSR_MODSEL_DATA(IP4_14_12, RMII0_MDC_A, SEL_RMII_0), + PINMUX_IPSR_MSEL(IP4_14_12, RMII0_MDC_A, SEL_RMII_0), PINMUX_IPSR_DATA(IP4_14_12, ET0_COL), - PINMUX_IPSR_MODSEL_DATA(IP4_17_15, CTS0_B, SEL_SCIF0_1), + PINMUX_IPSR_MSEL(IP4_17_15, CTS0_B, SEL_SCIF0_1), PINMUX_IPSR_DATA(IP4_17_15, VI0_DATA2_VI0_B2), - PINMUX_IPSR_MODSEL_DATA(IP4_17_15, RMII0_MDIO_A, SEL_RMII_0), + PINMUX_IPSR_MSEL(IP4_17_15, RMII0_MDIO_A, SEL_RMII_0), PINMUX_IPSR_DATA(IP4_17_15, ET0_MDC), - PINMUX_IPSR_MODSEL_DATA(IP4_19_18, RTS0_B, SEL_SCIF0_1), + PINMUX_IPSR_MSEL(IP4_19_18, RTS0_B, SEL_SCIF0_1), PINMUX_IPSR_DATA(IP4_19_18, VI0_DATA3_VI0_B3), - PINMUX_IPSR_MODSEL_DATA(IP4_19_18, ET0_MDIO_A, SEL_ET0_0), + PINMUX_IPSR_MSEL(IP4_19_18, ET0_MDIO_A, SEL_ET0_0), - PINMUX_IPSR_MODSEL_DATA(IP4_21_20, SCK1_B, SEL_SCIF1_1), + PINMUX_IPSR_MSEL(IP4_21_20, SCK1_B, SEL_SCIF1_1), PINMUX_IPSR_DATA(IP4_21_20, VI0_DATA4_VI0_B4), - PINMUX_IPSR_MODSEL_DATA(IP4_21_20, ET0_LINK_A, SEL_ET0_CTL_0), + PINMUX_IPSR_MSEL(IP4_21_20, ET0_LINK_A, SEL_ET0_CTL_0), - PINMUX_IPSR_MODSEL_DATA(IP4_23_22, RX1_B, SEL_SCIF1_1), + PINMUX_IPSR_MSEL(IP4_23_22, RX1_B, SEL_SCIF1_1), PINMUX_IPSR_DATA(IP4_23_22, VI0_DATA5_VI0_B5), - PINMUX_IPSR_MODSEL_DATA(IP4_23_22, ET0_MAGIC_A, SEL_ET0_CTL_0), + PINMUX_IPSR_MSEL(IP4_23_22, ET0_MAGIC_A, SEL_ET0_CTL_0), - PINMUX_IPSR_MODSEL_DATA(IP4_25_24, TX1_B, SEL_SCIF1_1), + PINMUX_IPSR_MSEL(IP4_25_24, TX1_B, SEL_SCIF1_1), PINMUX_IPSR_DATA(IP4_25_24, VI0_DATA6_VI0_G0), - PINMUX_IPSR_MODSEL_DATA(IP4_25_24, ET0_PHY_INT_A, SEL_ET0_CTL_0), + PINMUX_IPSR_MSEL(IP4_25_24, ET0_PHY_INT_A, SEL_ET0_CTL_0), - PINMUX_IPSR_MODSEL_DATA(IP4_27_26, CTS1_B, SEL_SCIF1_1), + PINMUX_IPSR_MSEL(IP4_27_26, CTS1_B, SEL_SCIF1_1), PINMUX_IPSR_DATA(IP4_27_26, VI0_DATA7_VI0_G1), - PINMUX_IPSR_MODSEL_DATA(IP4_29_28, RTS1_B, SEL_SCIF1_1), + PINMUX_IPSR_MSEL(IP4_29_28, RTS1_B, SEL_SCIF1_1), PINMUX_IPSR_DATA(IP4_29_28, VI0_G2), - PINMUX_IPSR_MODSEL_DATA(IP4_31_30, SCK2_A, SEL_SCIF2_0), + PINMUX_IPSR_MSEL(IP4_31_30, SCK2_A, SEL_SCIF2_0), PINMUX_IPSR_DATA(IP4_31_30, VI0_G3), /* IPSR5 */ - PINMUX_IPSR_MODSEL_DATA(IP5_2_0, SD2_CLK_A, SEL_SDHI2_0), - PINMUX_IPSR_MODSEL_DATA(IP5_2_0, RX2_A, SEL_SCIF2_0), + PINMUX_IPSR_MSEL(IP5_2_0, SD2_CLK_A, SEL_SDHI2_0), + PINMUX_IPSR_MSEL(IP5_2_0, RX2_A, SEL_SCIF2_0), PINMUX_IPSR_DATA(IP5_2_0, VI0_G4), - PINMUX_IPSR_MODSEL_DATA(IP5_2_0, ET0_RX_CLK_B, SEL_ET0_1), + PINMUX_IPSR_MSEL(IP5_2_0, ET0_RX_CLK_B, SEL_ET0_1), - PINMUX_IPSR_MODSEL_DATA(IP5_5_3, SD2_CMD_A, SEL_SDHI2_0), - PINMUX_IPSR_MODSEL_DATA(IP5_5_3, TX2_A, SEL_SCIF2_0), + PINMUX_IPSR_MSEL(IP5_5_3, SD2_CMD_A, SEL_SDHI2_0), + PINMUX_IPSR_MSEL(IP5_5_3, TX2_A, SEL_SCIF2_0), PINMUX_IPSR_DATA(IP5_5_3, VI0_G5), - PINMUX_IPSR_MODSEL_DATA(IP5_5_3, ET0_ERXD2_B, SEL_ET0_1), + PINMUX_IPSR_MSEL(IP5_5_3, ET0_ERXD2_B, SEL_ET0_1), - PINMUX_IPSR_MODSEL_DATA(IP5_8_6, SD2_DAT0_A, SEL_SDHI2_0), - PINMUX_IPSR_MODSEL_DATA(IP5_8_6, RX3_A, SEL_SCIF3_0), + PINMUX_IPSR_MSEL(IP5_8_6, SD2_DAT0_A, SEL_SDHI2_0), + PINMUX_IPSR_MSEL(IP5_8_6, RX3_A, SEL_SCIF3_0), PINMUX_IPSR_DATA(IP4_8_6, VI0_R0), - PINMUX_IPSR_MODSEL_DATA(IP4_8_6, ET0_ERXD2_B, SEL_ET0_1), + PINMUX_IPSR_MSEL(IP4_8_6, ET0_ERXD2_B, SEL_ET0_1), - PINMUX_IPSR_MODSEL_DATA(IP5_11_9, SD2_DAT1_A, SEL_SDHI2_0), - PINMUX_IPSR_MODSEL_DATA(IP5_11_9, TX3_A, SEL_SCIF3_0), + PINMUX_IPSR_MSEL(IP5_11_9, SD2_DAT1_A, SEL_SDHI2_0), + PINMUX_IPSR_MSEL(IP5_11_9, TX3_A, SEL_SCIF3_0), PINMUX_IPSR_DATA(IP5_11_9, VI0_R1), - PINMUX_IPSR_MODSEL_DATA(IP5_11_9, ET0_MDIO_B, SEL_ET0_1), + PINMUX_IPSR_MSEL(IP5_11_9, ET0_MDIO_B, SEL_ET0_1), - PINMUX_IPSR_MODSEL_DATA(IP5_14_12, SD2_DAT2_A, SEL_SDHI2_0), - PINMUX_IPSR_MODSEL_DATA(IP5_14_12, RX4_A, SEL_SCIF4_0), + PINMUX_IPSR_MSEL(IP5_14_12, SD2_DAT2_A, SEL_SDHI2_0), + PINMUX_IPSR_MSEL(IP5_14_12, RX4_A, SEL_SCIF4_0), PINMUX_IPSR_DATA(IP5_14_12, VI0_R2), - PINMUX_IPSR_MODSEL_DATA(IP5_14_12, ET0_LINK_B, SEL_ET0_CTL_1), + PINMUX_IPSR_MSEL(IP5_14_12, ET0_LINK_B, SEL_ET0_CTL_1), - PINMUX_IPSR_MODSEL_DATA(IP5_17_15, SD2_DAT3_A, SEL_SDHI2_0), - PINMUX_IPSR_MODSEL_DATA(IP5_17_15, TX4_A, SEL_SCIF4_0), + PINMUX_IPSR_MSEL(IP5_17_15, SD2_DAT3_A, SEL_SDHI2_0), + PINMUX_IPSR_MSEL(IP5_17_15, TX4_A, SEL_SCIF4_0), PINMUX_IPSR_DATA(IP5_17_15, VI0_R3), - PINMUX_IPSR_MODSEL_DATA(IP5_17_15, ET0_MAGIC_B, SEL_ET0_CTL_1), + PINMUX_IPSR_MSEL(IP5_17_15, ET0_MAGIC_B, SEL_ET0_CTL_1), - PINMUX_IPSR_MODSEL_DATA(IP5_20_18, SD2_CD_A, SEL_SDHI2_0), - PINMUX_IPSR_MODSEL_DATA(IP5_20_18, RX5_A, SEL_SCIF5_0), + PINMUX_IPSR_MSEL(IP5_20_18, SD2_CD_A, SEL_SDHI2_0), + PINMUX_IPSR_MSEL(IP5_20_18, RX5_A, SEL_SCIF5_0), PINMUX_IPSR_DATA(IP5_20_18, VI0_R4), - PINMUX_IPSR_MODSEL_DATA(IP5_20_18, ET0_PHY_INT_B, SEL_ET0_CTL_1), + PINMUX_IPSR_MSEL(IP5_20_18, ET0_PHY_INT_B, SEL_ET0_CTL_1), - PINMUX_IPSR_MODSEL_DATA(IP5_22_21, SD2_WP_A, SEL_SDHI2_0), - PINMUX_IPSR_MODSEL_DATA(IP5_22_21, TX5_A, SEL_SCIF5_0), + PINMUX_IPSR_MSEL(IP5_22_21, SD2_WP_A, SEL_SDHI2_0), + PINMUX_IPSR_MSEL(IP5_22_21, TX5_A, SEL_SCIF5_0), PINMUX_IPSR_DATA(IP5_22_21, VI0_R5), PINMUX_IPSR_DATA(IP5_24_23, REF125CK), PINMUX_IPSR_DATA(IP5_24_23, ADTRG), - PINMUX_IPSR_MODSEL_DATA(IP5_24_23, RX5_C, SEL_SCIF5_2), + PINMUX_IPSR_MSEL(IP5_24_23, RX5_C, SEL_SCIF5_2), PINMUX_IPSR_DATA(IP5_26_25, REF50CK), - PINMUX_IPSR_MODSEL_DATA(IP5_26_25, CTS1_E, SEL_SCIF1_3), - PINMUX_IPSR_MODSEL_DATA(IP5_26_25, HCTS0_D, SEL_HSCIF_3), + PINMUX_IPSR_MSEL(IP5_26_25, CTS1_E, SEL_SCIF1_3), + PINMUX_IPSR_MSEL(IP5_26_25, HCTS0_D, SEL_HSCIF_3), /* IPSR6 */ PINMUX_IPSR_DATA(IP6_2_0, DU0_DR0), - PINMUX_IPSR_MODSEL_DATA(IP6_2_0, SCIF_CLK_B, SEL_SCIF_CLK_1), - PINMUX_IPSR_MODSEL_DATA(IP6_2_0, HRX0_D, SEL_HSCIF_3), - PINMUX_IPSR_MODSEL_DATA(IP6_2_0, IETX_A, SEL_IEBUS_0), - PINMUX_IPSR_MODSEL_DATA(IP6_2_0, TCLKA_A, SEL_MTU2_CLK_0), + PINMUX_IPSR_MSEL(IP6_2_0, SCIF_CLK_B, SEL_SCIF_CLK_1), + PINMUX_IPSR_MSEL(IP6_2_0, HRX0_D, SEL_HSCIF_3), + PINMUX_IPSR_MSEL(IP6_2_0, IETX_A, SEL_IEBUS_0), + PINMUX_IPSR_MSEL(IP6_2_0, TCLKA_A, SEL_MTU2_CLK_0), PINMUX_IPSR_DATA(IP6_2_0, HIFD00), PINMUX_IPSR_DATA(IP6_5_3, DU0_DR1), - PINMUX_IPSR_MODSEL_DATA(IP6_5_3, SCK0_B, SEL_SCIF0_1), - PINMUX_IPSR_MODSEL_DATA(IP6_5_3, HTX0_D, SEL_HSCIF_3), - PINMUX_IPSR_MODSEL_DATA(IP6_5_3, IERX_A, SEL_IEBUS_0), - PINMUX_IPSR_MODSEL_DATA(IP6_5_3, TCLKB_A, SEL_MTU2_CLK_0), + PINMUX_IPSR_MSEL(IP6_5_3, SCK0_B, SEL_SCIF0_1), + PINMUX_IPSR_MSEL(IP6_5_3, HTX0_D, SEL_HSCIF_3), + PINMUX_IPSR_MSEL(IP6_5_3, IERX_A, SEL_IEBUS_0), + PINMUX_IPSR_MSEL(IP6_5_3, TCLKB_A, SEL_MTU2_CLK_0), PINMUX_IPSR_DATA(IP6_5_3, HIFD01), PINMUX_IPSR_DATA(IP6_7_6, DU0_DR2), - PINMUX_IPSR_MODSEL_DATA(IP6_7_6, RX0_B, SEL_SCIF0_1), - PINMUX_IPSR_MODSEL_DATA(IP6_7_6, TCLKC_A, SEL_MTU2_CLK_0), + PINMUX_IPSR_MSEL(IP6_7_6, RX0_B, SEL_SCIF0_1), + PINMUX_IPSR_MSEL(IP6_7_6, TCLKC_A, SEL_MTU2_CLK_0), PINMUX_IPSR_DATA(IP6_7_6, HIFD02), PINMUX_IPSR_DATA(IP6_9_8, DU0_DR3), - PINMUX_IPSR_MODSEL_DATA(IP6_9_8, TX0_B, SEL_SCIF0_1), - PINMUX_IPSR_MODSEL_DATA(IP6_9_8, TCLKD_A, SEL_MTU2_CLK_0), + PINMUX_IPSR_MSEL(IP6_9_8, TX0_B, SEL_SCIF0_1), + PINMUX_IPSR_MSEL(IP6_9_8, TCLKD_A, SEL_MTU2_CLK_0), PINMUX_IPSR_DATA(IP6_9_8, HIFD03), PINMUX_IPSR_DATA(IP6_11_10, DU0_DR4), - PINMUX_IPSR_MODSEL_DATA(IP6_11_10, CTS0_C, SEL_SCIF0_2), - PINMUX_IPSR_MODSEL_DATA(IP6_11_10, TIOC0A_A, SEL_MTU2_CH0_0), + PINMUX_IPSR_MSEL(IP6_11_10, CTS0_C, SEL_SCIF0_2), + PINMUX_IPSR_MSEL(IP6_11_10, TIOC0A_A, SEL_MTU2_CH0_0), PINMUX_IPSR_DATA(IP6_11_10, HIFD04), PINMUX_IPSR_DATA(IP6_13_12, DU0_DR5), - PINMUX_IPSR_MODSEL_DATA(IP6_13_12, RTS0_C, SEL_SCIF0_1), - PINMUX_IPSR_MODSEL_DATA(IP6_13_12, TIOC0B_A, SEL_MTU2_CH0_0), + PINMUX_IPSR_MSEL(IP6_13_12, RTS0_C, SEL_SCIF0_1), + PINMUX_IPSR_MSEL(IP6_13_12, TIOC0B_A, SEL_MTU2_CH0_0), PINMUX_IPSR_DATA(IP6_13_12, HIFD05), PINMUX_IPSR_DATA(IP6_15_14, DU0_DR6), - PINMUX_IPSR_MODSEL_DATA(IP6_15_14, SCK1_C, SEL_SCIF1_2), - PINMUX_IPSR_MODSEL_DATA(IP6_15_14, TIOC0C_A, SEL_MTU2_CH0_0), + PINMUX_IPSR_MSEL(IP6_15_14, SCK1_C, SEL_SCIF1_2), + PINMUX_IPSR_MSEL(IP6_15_14, TIOC0C_A, SEL_MTU2_CH0_0), PINMUX_IPSR_DATA(IP6_15_14, HIFD06), PINMUX_IPSR_DATA(IP6_17_16, DU0_DR7), - PINMUX_IPSR_MODSEL_DATA(IP6_17_16, RX1_C, SEL_SCIF1_2), - PINMUX_IPSR_MODSEL_DATA(IP6_17_16, TIOC0D_A, SEL_MTU2_CH0_0), + PINMUX_IPSR_MSEL(IP6_17_16, RX1_C, SEL_SCIF1_2), + PINMUX_IPSR_MSEL(IP6_17_16, TIOC0D_A, SEL_MTU2_CH0_0), PINMUX_IPSR_DATA(IP6_17_16, HIFD07), PINMUX_IPSR_DATA(IP6_20_18, DU0_DG0), - PINMUX_IPSR_MODSEL_DATA(IP6_20_18, TX1_C, SEL_SCIF1_2), - PINMUX_IPSR_MODSEL_DATA(IP6_20_18, HSCK0_D, SEL_HSCIF_3), - PINMUX_IPSR_MODSEL_DATA(IP6_20_18, IECLK_A, SEL_IEBUS_0), - PINMUX_IPSR_MODSEL_DATA(IP6_20_18, TIOC1A_A, SEL_MTU2_CH1_0), + PINMUX_IPSR_MSEL(IP6_20_18, TX1_C, SEL_SCIF1_2), + PINMUX_IPSR_MSEL(IP6_20_18, HSCK0_D, SEL_HSCIF_3), + PINMUX_IPSR_MSEL(IP6_20_18, IECLK_A, SEL_IEBUS_0), + PINMUX_IPSR_MSEL(IP6_20_18, TIOC1A_A, SEL_MTU2_CH1_0), PINMUX_IPSR_DATA(IP6_20_18, HIFD08), PINMUX_IPSR_DATA(IP6_23_21, DU0_DG1), - PINMUX_IPSR_MODSEL_DATA(IP6_23_21, CTS1_C, SEL_SCIF1_2), - PINMUX_IPSR_MODSEL_DATA(IP6_23_21, HRTS0_D, SEL_HSCIF_3), - PINMUX_IPSR_MODSEL_DATA(IP6_23_21, TIOC1B_A, SEL_MTU2_CH1_0), + PINMUX_IPSR_MSEL(IP6_23_21, CTS1_C, SEL_SCIF1_2), + PINMUX_IPSR_MSEL(IP6_23_21, HRTS0_D, SEL_HSCIF_3), + PINMUX_IPSR_MSEL(IP6_23_21, TIOC1B_A, SEL_MTU2_CH1_0), PINMUX_IPSR_DATA(IP6_23_21, HIFD09), /* IPSR7 */ PINMUX_IPSR_DATA(IP7_2_0, DU0_DG2), - PINMUX_IPSR_MODSEL_DATA(IP7_2_0, RTS1_C, SEL_SCIF1_2), - PINMUX_IPSR_MODSEL_DATA(IP7_2_0, RMII0_MDC_B, SEL_RMII_1), - PINMUX_IPSR_MODSEL_DATA(IP7_2_0, TIOC2A_A, SEL_MTU2_CH2_0), + PINMUX_IPSR_MSEL(IP7_2_0, RTS1_C, SEL_SCIF1_2), + PINMUX_IPSR_MSEL(IP7_2_0, RMII0_MDC_B, SEL_RMII_1), + PINMUX_IPSR_MSEL(IP7_2_0, TIOC2A_A, SEL_MTU2_CH2_0), PINMUX_IPSR_DATA(IP7_2_0, HIFD10), PINMUX_IPSR_DATA(IP7_5_3, DU0_DG3), - PINMUX_IPSR_MODSEL_DATA(IP7_5_3, SCK2_C, SEL_SCIF2_2), - PINMUX_IPSR_MODSEL_DATA(IP7_5_3, RMII0_MDIO_B, SEL_RMII_1), - PINMUX_IPSR_MODSEL_DATA(IP7_5_3, TIOC2B_A, SEL_MTU2_CH2_0), + PINMUX_IPSR_MSEL(IP7_5_3, SCK2_C, SEL_SCIF2_2), + PINMUX_IPSR_MSEL(IP7_5_3, RMII0_MDIO_B, SEL_RMII_1), + PINMUX_IPSR_MSEL(IP7_5_3, TIOC2B_A, SEL_MTU2_CH2_0), PINMUX_IPSR_DATA(IP7_5_3, HIFD11), PINMUX_IPSR_DATA(IP7_8_6, DU0_DG4), - PINMUX_IPSR_MODSEL_DATA(IP7_8_6, RX2_C, SEL_SCIF2_2), - PINMUX_IPSR_MODSEL_DATA(IP7_8_6, RMII0_CRS_DV_B, SEL_RMII_1), - PINMUX_IPSR_MODSEL_DATA(IP7_8_6, TIOC3A_A, SEL_MTU2_CH3_0), + PINMUX_IPSR_MSEL(IP7_8_6, RX2_C, SEL_SCIF2_2), + PINMUX_IPSR_MSEL(IP7_8_6, RMII0_CRS_DV_B, SEL_RMII_1), + PINMUX_IPSR_MSEL(IP7_8_6, TIOC3A_A, SEL_MTU2_CH3_0), PINMUX_IPSR_DATA(IP7_8_6, HIFD12), PINMUX_IPSR_DATA(IP7_11_9, DU0_DG5), - PINMUX_IPSR_MODSEL_DATA(IP7_11_9, TX2_C, SEL_SCIF2_2), - PINMUX_IPSR_MODSEL_DATA(IP7_11_9, RMII0_RX_ER_B, SEL_RMII_1), - PINMUX_IPSR_MODSEL_DATA(IP7_11_9, TIOC3B_A, SEL_MTU2_CH3_0), + PINMUX_IPSR_MSEL(IP7_11_9, TX2_C, SEL_SCIF2_2), + PINMUX_IPSR_MSEL(IP7_11_9, RMII0_RX_ER_B, SEL_RMII_1), + PINMUX_IPSR_MSEL(IP7_11_9, TIOC3B_A, SEL_MTU2_CH3_0), PINMUX_IPSR_DATA(IP7_11_9, HIFD13), PINMUX_IPSR_DATA(IP7_14_12, DU0_DG6), - PINMUX_IPSR_MODSEL_DATA(IP7_14_12, RX3_C, SEL_SCIF3_2), - PINMUX_IPSR_MODSEL_DATA(IP7_14_12, RMII0_RXD0_B, SEL_RMII_1), - PINMUX_IPSR_MODSEL_DATA(IP7_14_12, TIOC3C_A, SEL_MTU2_CH3_0), + PINMUX_IPSR_MSEL(IP7_14_12, RX3_C, SEL_SCIF3_2), + PINMUX_IPSR_MSEL(IP7_14_12, RMII0_RXD0_B, SEL_RMII_1), + PINMUX_IPSR_MSEL(IP7_14_12, TIOC3C_A, SEL_MTU2_CH3_0), PINMUX_IPSR_DATA(IP7_14_12, HIFD14), PINMUX_IPSR_DATA(IP7_17_15, DU0_DG7), - PINMUX_IPSR_MODSEL_DATA(IP7_17_15, TX3_C, SEL_SCIF3_2), - PINMUX_IPSR_MODSEL_DATA(IP7_17_15, RMII0_RXD1_B, SEL_RMII_1), - PINMUX_IPSR_MODSEL_DATA(IP7_17_15, TIOC3D_A, SEL_MTU2_CH3_0), + PINMUX_IPSR_MSEL(IP7_17_15, TX3_C, SEL_SCIF3_2), + PINMUX_IPSR_MSEL(IP7_17_15, RMII0_RXD1_B, SEL_RMII_1), + PINMUX_IPSR_MSEL(IP7_17_15, TIOC3D_A, SEL_MTU2_CH3_0), PINMUX_IPSR_DATA(IP7_17_15, HIFD15), PINMUX_IPSR_DATA(IP7_20_18, DU0_DB0), - PINMUX_IPSR_MODSEL_DATA(IP7_20_18, RX4_C, SEL_SCIF4_2), - PINMUX_IPSR_MODSEL_DATA(IP7_20_18, RMII0_TXD_EN_B, SEL_RMII_1), - PINMUX_IPSR_MODSEL_DATA(IP7_20_18, TIOC4A_A, SEL_MTU2_CH4_0), + PINMUX_IPSR_MSEL(IP7_20_18, RX4_C, SEL_SCIF4_2), + PINMUX_IPSR_MSEL(IP7_20_18, RMII0_TXD_EN_B, SEL_RMII_1), + PINMUX_IPSR_MSEL(IP7_20_18, TIOC4A_A, SEL_MTU2_CH4_0), PINMUX_IPSR_DATA(IP7_20_18, HIFCS), PINMUX_IPSR_DATA(IP7_23_21, DU0_DB1), - PINMUX_IPSR_MODSEL_DATA(IP7_23_21, TX4_C, SEL_SCIF4_2), - PINMUX_IPSR_MODSEL_DATA(IP7_23_21, RMII0_TXD0_B, SEL_RMII_1), - PINMUX_IPSR_MODSEL_DATA(IP7_23_21, TIOC4B_A, SEL_MTU2_CH4_0), + PINMUX_IPSR_MSEL(IP7_23_21, TX4_C, SEL_SCIF4_2), + PINMUX_IPSR_MSEL(IP7_23_21, RMII0_TXD0_B, SEL_RMII_1), + PINMUX_IPSR_MSEL(IP7_23_21, TIOC4B_A, SEL_MTU2_CH4_0), PINMUX_IPSR_DATA(IP7_23_21, HIFWR), PINMUX_IPSR_DATA(IP7_26_24, DU0_DB2), - PINMUX_IPSR_MODSEL_DATA(IP7_26_24, RX5_B, SEL_SCIF5_1), - PINMUX_IPSR_MODSEL_DATA(IP7_26_24, RMII0_TXD1_B, SEL_RMII_1), - PINMUX_IPSR_MODSEL_DATA(IP7_26_24, TIOC4C_A, SEL_MTU2_CH4_0), + PINMUX_IPSR_MSEL(IP7_26_24, RX5_B, SEL_SCIF5_1), + PINMUX_IPSR_MSEL(IP7_26_24, RMII0_TXD1_B, SEL_RMII_1), + PINMUX_IPSR_MSEL(IP7_26_24, TIOC4C_A, SEL_MTU2_CH4_0), PINMUX_IPSR_DATA(IP7_28_27, DU0_DB3), - PINMUX_IPSR_MODSEL_DATA(IP7_28_27, TX5_B, SEL_SCIF5_1), - PINMUX_IPSR_MODSEL_DATA(IP7_28_27, TIOC4D_A, SEL_MTU2_CH4_0), + PINMUX_IPSR_MSEL(IP7_28_27, TX5_B, SEL_SCIF5_1), + PINMUX_IPSR_MSEL(IP7_28_27, TIOC4D_A, SEL_MTU2_CH4_0), PINMUX_IPSR_DATA(IP7_28_27, HIFRD), PINMUX_IPSR_DATA(IP7_30_29, DU0_DB4), @@ -1107,251 +1107,251 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_DATA(IP8_3_2, HIFRDY), PINMUX_IPSR_DATA(IP8_5_4, DU0_DB7), - PINMUX_IPSR_MODSEL_DATA(IP8_5_4, SSI_SCK0_B, SEL_SSI0_1), - PINMUX_IPSR_MODSEL_DATA(IP8_5_4, HIFEBL_B, SEL_HIF_1), + PINMUX_IPSR_MSEL(IP8_5_4, SSI_SCK0_B, SEL_SSI0_1), + PINMUX_IPSR_MSEL(IP8_5_4, HIFEBL_B, SEL_HIF_1), PINMUX_IPSR_DATA(IP8_7_6, DU0_DOTCLKIN), - PINMUX_IPSR_MODSEL_DATA(IP8_7_6, HSPI_CS0_C, SEL_HSPI_2), - PINMUX_IPSR_MODSEL_DATA(IP8_7_6, SSI_WS0_B, SEL_SSI0_1), + PINMUX_IPSR_MSEL(IP8_7_6, HSPI_CS0_C, SEL_HSPI_2), + PINMUX_IPSR_MSEL(IP8_7_6, SSI_WS0_B, SEL_SSI0_1), PINMUX_IPSR_DATA(IP8_9_8, DU0_DOTCLKOUT), - PINMUX_IPSR_MODSEL_DATA(IP8_9_8, HSPI_CLK0_C, SEL_HSPI_2), - PINMUX_IPSR_MODSEL_DATA(IP8_9_8, SSI_SDATA0_B, SEL_SSI0_1), + PINMUX_IPSR_MSEL(IP8_9_8, HSPI_CLK0_C, SEL_HSPI_2), + PINMUX_IPSR_MSEL(IP8_9_8, SSI_SDATA0_B, SEL_SSI0_1), PINMUX_IPSR_DATA(IP8_11_10, DU0_EXHSYNC_DU0_HSYNC), - PINMUX_IPSR_MODSEL_DATA(IP8_11_10, HSPI_TX0_C, SEL_HSPI_2), - PINMUX_IPSR_MODSEL_DATA(IP8_11_10, SSI_SCK1_B, SEL_SSI1_1), + PINMUX_IPSR_MSEL(IP8_11_10, HSPI_TX0_C, SEL_HSPI_2), + PINMUX_IPSR_MSEL(IP8_11_10, SSI_SCK1_B, SEL_SSI1_1), PINMUX_IPSR_DATA(IP8_13_12, DU0_EXVSYNC_DU0_VSYNC), - PINMUX_IPSR_MODSEL_DATA(IP8_13_12, HSPI_RX0_C, SEL_HSPI_2), - PINMUX_IPSR_MODSEL_DATA(IP8_13_12, SSI_WS1_B, SEL_SSI1_1), + PINMUX_IPSR_MSEL(IP8_13_12, HSPI_RX0_C, SEL_HSPI_2), + PINMUX_IPSR_MSEL(IP8_13_12, SSI_WS1_B, SEL_SSI1_1), PINMUX_IPSR_DATA(IP8_15_14, DU0_EXODDF_DU0_ODDF), - PINMUX_IPSR_MODSEL_DATA(IP8_15_14, CAN0_RX_B, SEL_RCAN0_1), - PINMUX_IPSR_MODSEL_DATA(IP8_15_14, HSCK0_B, SEL_HSCIF_1), - PINMUX_IPSR_MODSEL_DATA(IP8_15_14, SSI_SDATA1_B, SEL_SSI1_1), + PINMUX_IPSR_MSEL(IP8_15_14, CAN0_RX_B, SEL_RCAN0_1), + PINMUX_IPSR_MSEL(IP8_15_14, HSCK0_B, SEL_HSCIF_1), + PINMUX_IPSR_MSEL(IP8_15_14, SSI_SDATA1_B, SEL_SSI1_1), PINMUX_IPSR_DATA(IP8_17_16, DU0_DISP), - PINMUX_IPSR_MODSEL_DATA(IP8_17_16, CAN0_TX_B, SEL_RCAN0_1), - PINMUX_IPSR_MODSEL_DATA(IP8_17_16, HRX0_B, SEL_HSCIF_1), - PINMUX_IPSR_MODSEL_DATA(IP8_17_16, AUDIO_CLKA_B, SEL_AUDIO_CLKA_1), + PINMUX_IPSR_MSEL(IP8_17_16, CAN0_TX_B, SEL_RCAN0_1), + PINMUX_IPSR_MSEL(IP8_17_16, HRX0_B, SEL_HSCIF_1), + PINMUX_IPSR_MSEL(IP8_17_16, AUDIO_CLKA_B, SEL_AUDIO_CLKA_1), PINMUX_IPSR_DATA(IP8_19_18, DU0_CDE), - PINMUX_IPSR_MODSEL_DATA(IP8_19_18, HTX0_B, SEL_HSCIF_1), - PINMUX_IPSR_MODSEL_DATA(IP8_19_18, AUDIO_CLKB_B, SEL_AUDIO_CLKB_1), - PINMUX_IPSR_MODSEL_DATA(IP8_19_18, LCD_VCPWC_B, SEL_LCDC_1), + PINMUX_IPSR_MSEL(IP8_19_18, HTX0_B, SEL_HSCIF_1), + PINMUX_IPSR_MSEL(IP8_19_18, AUDIO_CLKB_B, SEL_AUDIO_CLKB_1), + PINMUX_IPSR_MSEL(IP8_19_18, LCD_VCPWC_B, SEL_LCDC_1), - PINMUX_IPSR_MODSEL_DATA(IP8_22_20, IRQ0_A, SEL_INTC_0), - PINMUX_IPSR_MODSEL_DATA(IP8_22_20, HSPI_TX_B, SEL_HSPI_1), - PINMUX_IPSR_MODSEL_DATA(IP8_22_20, RX3_E, SEL_SCIF3_4), + PINMUX_IPSR_MSEL(IP8_22_20, IRQ0_A, SEL_INTC_0), + PINMUX_IPSR_MSEL(IP8_22_20, HSPI_TX_B, SEL_HSPI_1), + PINMUX_IPSR_MSEL(IP8_22_20, RX3_E, SEL_SCIF3_4), PINMUX_IPSR_DATA(IP8_22_20, ET0_ERXD0), - PINMUX_IPSR_MODSEL_DATA(IP8_25_23, IRQ1_A, SEL_INTC_0), - PINMUX_IPSR_MODSEL_DATA(IP8_25_23, HSPI_RX_B, SEL_HSPI_1), - PINMUX_IPSR_MODSEL_DATA(IP8_25_23, TX3_E, SEL_SCIF3_4), + PINMUX_IPSR_MSEL(IP8_25_23, IRQ1_A, SEL_INTC_0), + PINMUX_IPSR_MSEL(IP8_25_23, HSPI_RX_B, SEL_HSPI_1), + PINMUX_IPSR_MSEL(IP8_25_23, TX3_E, SEL_SCIF3_4), PINMUX_IPSR_DATA(IP8_25_23, ET0_ERXD1), - PINMUX_IPSR_MODSEL_DATA(IP8_27_26, IRQ2_A, SEL_INTC_0), - PINMUX_IPSR_MODSEL_DATA(IP8_27_26, CTS0_A, SEL_SCIF0_0), - PINMUX_IPSR_MODSEL_DATA(IP8_27_26, HCTS0_B, SEL_HSCIF_1), - PINMUX_IPSR_MODSEL_DATA(IP8_27_26, ET0_ERXD2_A, SEL_ET0_0), + PINMUX_IPSR_MSEL(IP8_27_26, IRQ2_A, SEL_INTC_0), + PINMUX_IPSR_MSEL(IP8_27_26, CTS0_A, SEL_SCIF0_0), + PINMUX_IPSR_MSEL(IP8_27_26, HCTS0_B, SEL_HSCIF_1), + PINMUX_IPSR_MSEL(IP8_27_26, ET0_ERXD2_A, SEL_ET0_0), - PINMUX_IPSR_MODSEL_DATA(IP8_29_28, IRQ3_A, SEL_INTC_0), - PINMUX_IPSR_MODSEL_DATA(IP8_29_28, RTS0_A, SEL_SCIF0_0), - PINMUX_IPSR_MODSEL_DATA(IP8_29_28, HRTS0_B, SEL_HSCIF_1), - PINMUX_IPSR_MODSEL_DATA(IP8_29_28, ET0_ERXD3_A, SEL_ET0_0), + PINMUX_IPSR_MSEL(IP8_29_28, IRQ3_A, SEL_INTC_0), + PINMUX_IPSR_MSEL(IP8_29_28, RTS0_A, SEL_SCIF0_0), + PINMUX_IPSR_MSEL(IP8_29_28, HRTS0_B, SEL_HSCIF_1), + PINMUX_IPSR_MSEL(IP8_29_28, ET0_ERXD3_A, SEL_ET0_0), /* IPSR9 */ - PINMUX_IPSR_MODSEL_DATA(IP9_1_0, VI1_CLK_A, SEL_VIN1_0), - PINMUX_IPSR_MODSEL_DATA(IP9_1_0, FD0_B, SEL_FLCTL_1), - PINMUX_IPSR_MODSEL_DATA(IP9_1_0, LCD_DATA0_B, SEL_LCDC_1), + PINMUX_IPSR_MSEL(IP9_1_0, VI1_CLK_A, SEL_VIN1_0), + PINMUX_IPSR_MSEL(IP9_1_0, FD0_B, SEL_FLCTL_1), + PINMUX_IPSR_MSEL(IP9_1_0, LCD_DATA0_B, SEL_LCDC_1), - PINMUX_IPSR_MODSEL_DATA(IP9_3_2, VI1_0_A, SEL_VIN1_0), - PINMUX_IPSR_MODSEL_DATA(IP9_3_2, FD1_B, SEL_FLCTL_1), - PINMUX_IPSR_MODSEL_DATA(IP9_3_2, LCD_DATA1_B, SEL_LCDC_1), + PINMUX_IPSR_MSEL(IP9_3_2, VI1_0_A, SEL_VIN1_0), + PINMUX_IPSR_MSEL(IP9_3_2, FD1_B, SEL_FLCTL_1), + PINMUX_IPSR_MSEL(IP9_3_2, LCD_DATA1_B, SEL_LCDC_1), - PINMUX_IPSR_MODSEL_DATA(IP9_5_4, VI1_1_A, SEL_VIN1_0), - PINMUX_IPSR_MODSEL_DATA(IP9_5_4, FD2_B, SEL_FLCTL_1), - PINMUX_IPSR_MODSEL_DATA(IP9_5_4, LCD_DATA2_B, SEL_LCDC_1), + PINMUX_IPSR_MSEL(IP9_5_4, VI1_1_A, SEL_VIN1_0), + PINMUX_IPSR_MSEL(IP9_5_4, FD2_B, SEL_FLCTL_1), + PINMUX_IPSR_MSEL(IP9_5_4, LCD_DATA2_B, SEL_LCDC_1), - PINMUX_IPSR_MODSEL_DATA(IP9_7_6, VI1_2_A, SEL_VIN1_0), - PINMUX_IPSR_MODSEL_DATA(IP9_7_6, FD3_B, SEL_FLCTL_1), - PINMUX_IPSR_MODSEL_DATA(IP9_7_6, LCD_DATA3_B, SEL_LCDC_1), + PINMUX_IPSR_MSEL(IP9_7_6, VI1_2_A, SEL_VIN1_0), + PINMUX_IPSR_MSEL(IP9_7_6, FD3_B, SEL_FLCTL_1), + PINMUX_IPSR_MSEL(IP9_7_6, LCD_DATA3_B, SEL_LCDC_1), - PINMUX_IPSR_MODSEL_DATA(IP9_9_8, VI1_3_A, SEL_VIN1_0), - PINMUX_IPSR_MODSEL_DATA(IP9_9_8, FD4_B, SEL_FLCTL_1), - PINMUX_IPSR_MODSEL_DATA(IP9_9_8, LCD_DATA4_B, SEL_LCDC_1), + PINMUX_IPSR_MSEL(IP9_9_8, VI1_3_A, SEL_VIN1_0), + PINMUX_IPSR_MSEL(IP9_9_8, FD4_B, SEL_FLCTL_1), + PINMUX_IPSR_MSEL(IP9_9_8, LCD_DATA4_B, SEL_LCDC_1), - PINMUX_IPSR_MODSEL_DATA(IP9_11_10, VI1_4_A, SEL_VIN1_0), - PINMUX_IPSR_MODSEL_DATA(IP9_11_10, FD5_B, SEL_FLCTL_1), - PINMUX_IPSR_MODSEL_DATA(IP9_11_10, LCD_DATA5_B, SEL_LCDC_1), + PINMUX_IPSR_MSEL(IP9_11_10, VI1_4_A, SEL_VIN1_0), + PINMUX_IPSR_MSEL(IP9_11_10, FD5_B, SEL_FLCTL_1), + PINMUX_IPSR_MSEL(IP9_11_10, LCD_DATA5_B, SEL_LCDC_1), - PINMUX_IPSR_MODSEL_DATA(IP9_13_12, VI1_5_A, SEL_VIN1_0), - PINMUX_IPSR_MODSEL_DATA(IP9_13_12, FD6_B, SEL_FLCTL_1), - PINMUX_IPSR_MODSEL_DATA(IP9_13_12, LCD_DATA6_B, SEL_LCDC_1), + PINMUX_IPSR_MSEL(IP9_13_12, VI1_5_A, SEL_VIN1_0), + PINMUX_IPSR_MSEL(IP9_13_12, FD6_B, SEL_FLCTL_1), + PINMUX_IPSR_MSEL(IP9_13_12, LCD_DATA6_B, SEL_LCDC_1), - PINMUX_IPSR_MODSEL_DATA(IP9_15_14, VI1_6_A, SEL_VIN1_0), - PINMUX_IPSR_MODSEL_DATA(IP9_15_14, FD7_B, SEL_FLCTL_1), - PINMUX_IPSR_MODSEL_DATA(IP9_15_14, LCD_DATA7_B, SEL_LCDC_1), + PINMUX_IPSR_MSEL(IP9_15_14, VI1_6_A, SEL_VIN1_0), + PINMUX_IPSR_MSEL(IP9_15_14, FD7_B, SEL_FLCTL_1), + PINMUX_IPSR_MSEL(IP9_15_14, LCD_DATA7_B, SEL_LCDC_1), - PINMUX_IPSR_MODSEL_DATA(IP9_17_16, VI1_7_A, SEL_VIN1_0), - PINMUX_IPSR_MODSEL_DATA(IP9_17_16, FCE_B, SEL_FLCTL_1), - PINMUX_IPSR_MODSEL_DATA(IP9_17_16, LCD_DATA8_B, SEL_LCDC_1), + PINMUX_IPSR_MSEL(IP9_17_16, VI1_7_A, SEL_VIN1_0), + PINMUX_IPSR_MSEL(IP9_17_16, FCE_B, SEL_FLCTL_1), + PINMUX_IPSR_MSEL(IP9_17_16, LCD_DATA8_B, SEL_LCDC_1), - PINMUX_IPSR_MODSEL_DATA(IP9_19_18, SSI_SCK0_A, SEL_SSI0_0), - PINMUX_IPSR_MODSEL_DATA(IP9_19_18, TIOC1A_B, SEL_MTU2_CH1_1), - PINMUX_IPSR_MODSEL_DATA(IP9_19_18, LCD_DATA9_B, SEL_LCDC_1), + PINMUX_IPSR_MSEL(IP9_19_18, SSI_SCK0_A, SEL_SSI0_0), + PINMUX_IPSR_MSEL(IP9_19_18, TIOC1A_B, SEL_MTU2_CH1_1), + PINMUX_IPSR_MSEL(IP9_19_18, LCD_DATA9_B, SEL_LCDC_1), - PINMUX_IPSR_MODSEL_DATA(IP9_21_20, SSI_WS0_A, SEL_SSI0_0), - PINMUX_IPSR_MODSEL_DATA(IP9_21_20, TIOC1B_B, SEL_MTU2_CH1_1), - PINMUX_IPSR_MODSEL_DATA(IP9_21_20, LCD_DATA10_B, SEL_LCDC_1), + PINMUX_IPSR_MSEL(IP9_21_20, SSI_WS0_A, SEL_SSI0_0), + PINMUX_IPSR_MSEL(IP9_21_20, TIOC1B_B, SEL_MTU2_CH1_1), + PINMUX_IPSR_MSEL(IP9_21_20, LCD_DATA10_B, SEL_LCDC_1), - PINMUX_IPSR_MODSEL_DATA(IP9_23_22, SSI_SDATA0_A, SEL_SSI0_0), - PINMUX_IPSR_MODSEL_DATA(IP9_23_22, VI1_0_B, SEL_VIN1_1), - PINMUX_IPSR_MODSEL_DATA(IP9_23_22, TIOC2A_B, SEL_MTU2_CH2_1), - PINMUX_IPSR_MODSEL_DATA(IP9_23_22, LCD_DATA11_B, SEL_LCDC_1), + PINMUX_IPSR_MSEL(IP9_23_22, SSI_SDATA0_A, SEL_SSI0_0), + PINMUX_IPSR_MSEL(IP9_23_22, VI1_0_B, SEL_VIN1_1), + PINMUX_IPSR_MSEL(IP9_23_22, TIOC2A_B, SEL_MTU2_CH2_1), + PINMUX_IPSR_MSEL(IP9_23_22, LCD_DATA11_B, SEL_LCDC_1), - PINMUX_IPSR_MODSEL_DATA(IP9_25_24, SSI_SCK1_A, SEL_SSI1_0), - PINMUX_IPSR_MODSEL_DATA(IP9_25_24, VI1_1_B, SEL_VIN1_1), - PINMUX_IPSR_MODSEL_DATA(IP9_25_24, TIOC2B_B, SEL_MTU2_CH2_1), - PINMUX_IPSR_MODSEL_DATA(IP9_25_24, LCD_DATA12_B, SEL_LCDC_1), + PINMUX_IPSR_MSEL(IP9_25_24, SSI_SCK1_A, SEL_SSI1_0), + PINMUX_IPSR_MSEL(IP9_25_24, VI1_1_B, SEL_VIN1_1), + PINMUX_IPSR_MSEL(IP9_25_24, TIOC2B_B, SEL_MTU2_CH2_1), + PINMUX_IPSR_MSEL(IP9_25_24, LCD_DATA12_B, SEL_LCDC_1), - PINMUX_IPSR_MODSEL_DATA(IP9_27_26, SSI_WS1_A, SEL_SSI1_0), - PINMUX_IPSR_MODSEL_DATA(IP9_27_26, VI1_2_B, SEL_VIN1_1), - PINMUX_IPSR_MODSEL_DATA(IP9_27_26, LCD_DATA13_B, SEL_LCDC_1), + PINMUX_IPSR_MSEL(IP9_27_26, SSI_WS1_A, SEL_SSI1_0), + PINMUX_IPSR_MSEL(IP9_27_26, VI1_2_B, SEL_VIN1_1), + PINMUX_IPSR_MSEL(IP9_27_26, LCD_DATA13_B, SEL_LCDC_1), - PINMUX_IPSR_MODSEL_DATA(IP9_29_28, SSI_SDATA1_A, SEL_SSI1_0), - PINMUX_IPSR_MODSEL_DATA(IP9_29_28, VI1_3_B, SEL_VIN1_1), - PINMUX_IPSR_MODSEL_DATA(IP9_29_28, LCD_DATA14_B, SEL_LCDC_1), + PINMUX_IPSR_MSEL(IP9_29_28, SSI_SDATA1_A, SEL_SSI1_0), + PINMUX_IPSR_MSEL(IP9_29_28, VI1_3_B, SEL_VIN1_1), + PINMUX_IPSR_MSEL(IP9_29_28, LCD_DATA14_B, SEL_LCDC_1), /* IPSE10 */ PINMUX_IPSR_DATA(IP10_2_0, SSI_SCK23), - PINMUX_IPSR_MODSEL_DATA(IP10_2_0, VI1_4_B, SEL_VIN1_1), - PINMUX_IPSR_MODSEL_DATA(IP10_2_0, RX1_D, SEL_SCIF1_3), - PINMUX_IPSR_MODSEL_DATA(IP10_2_0, FCLE_B, SEL_FLCTL_1), - PINMUX_IPSR_MODSEL_DATA(IP10_2_0, LCD_DATA15_B, SEL_LCDC_1), + PINMUX_IPSR_MSEL(IP10_2_0, VI1_4_B, SEL_VIN1_1), + PINMUX_IPSR_MSEL(IP10_2_0, RX1_D, SEL_SCIF1_3), + PINMUX_IPSR_MSEL(IP10_2_0, FCLE_B, SEL_FLCTL_1), + PINMUX_IPSR_MSEL(IP10_2_0, LCD_DATA15_B, SEL_LCDC_1), PINMUX_IPSR_DATA(IP10_5_3, SSI_WS23), - PINMUX_IPSR_MODSEL_DATA(IP10_5_3, VI1_5_B, SEL_VIN1_1), - PINMUX_IPSR_MODSEL_DATA(IP10_5_3, TX1_D, SEL_SCIF1_3), - PINMUX_IPSR_MODSEL_DATA(IP10_5_3, HSCK0_C, SEL_HSCIF_2), - PINMUX_IPSR_MODSEL_DATA(IP10_5_3, FALE_B, SEL_FLCTL_1), - PINMUX_IPSR_MODSEL_DATA(IP10_5_3, LCD_DON_B, SEL_LCDC_1), + PINMUX_IPSR_MSEL(IP10_5_3, VI1_5_B, SEL_VIN1_1), + PINMUX_IPSR_MSEL(IP10_5_3, TX1_D, SEL_SCIF1_3), + PINMUX_IPSR_MSEL(IP10_5_3, HSCK0_C, SEL_HSCIF_2), + PINMUX_IPSR_MSEL(IP10_5_3, FALE_B, SEL_FLCTL_1), + PINMUX_IPSR_MSEL(IP10_5_3, LCD_DON_B, SEL_LCDC_1), PINMUX_IPSR_DATA(IP10_8_6, SSI_SDATA2), - PINMUX_IPSR_MODSEL_DATA(IP10_8_6, VI1_6_B, SEL_VIN1_1), - PINMUX_IPSR_MODSEL_DATA(IP10_8_6, HRX0_C, SEL_HSCIF_2), - PINMUX_IPSR_MODSEL_DATA(IP10_8_6, FRE_B, SEL_FLCTL_1), - PINMUX_IPSR_MODSEL_DATA(IP10_8_6, LCD_CL1_B, SEL_LCDC_1), + PINMUX_IPSR_MSEL(IP10_8_6, VI1_6_B, SEL_VIN1_1), + PINMUX_IPSR_MSEL(IP10_8_6, HRX0_C, SEL_HSCIF_2), + PINMUX_IPSR_MSEL(IP10_8_6, FRE_B, SEL_FLCTL_1), + PINMUX_IPSR_MSEL(IP10_8_6, LCD_CL1_B, SEL_LCDC_1), PINMUX_IPSR_DATA(IP10_11_9, SSI_SDATA3), - PINMUX_IPSR_MODSEL_DATA(IP10_11_9, VI1_7_B, SEL_VIN1_1), - PINMUX_IPSR_MODSEL_DATA(IP10_11_9, HTX0_C, SEL_HSCIF_2), - PINMUX_IPSR_MODSEL_DATA(IP10_11_9, FWE_B, SEL_FLCTL_1), - PINMUX_IPSR_MODSEL_DATA(IP10_11_9, LCD_CL2_B, SEL_LCDC_1), + PINMUX_IPSR_MSEL(IP10_11_9, VI1_7_B, SEL_VIN1_1), + PINMUX_IPSR_MSEL(IP10_11_9, HTX0_C, SEL_HSCIF_2), + PINMUX_IPSR_MSEL(IP10_11_9, FWE_B, SEL_FLCTL_1), + PINMUX_IPSR_MSEL(IP10_11_9, LCD_CL2_B, SEL_LCDC_1), - PINMUX_IPSR_MODSEL_DATA(IP10_14_12, AUDIO_CLKA_A, SEL_AUDIO_CLKA_0), - PINMUX_IPSR_MODSEL_DATA(IP10_14_12, VI1_CLK_B, SEL_VIN1_1), - PINMUX_IPSR_MODSEL_DATA(IP10_14_12, SCK1_D, SEL_SCIF1_3), - PINMUX_IPSR_MODSEL_DATA(IP10_14_12, IECLK_B, SEL_IEBUS_1), - PINMUX_IPSR_MODSEL_DATA(IP10_14_12, LCD_FLM_B, SEL_LCDC_1), + PINMUX_IPSR_MSEL(IP10_14_12, AUDIO_CLKA_A, SEL_AUDIO_CLKA_0), + PINMUX_IPSR_MSEL(IP10_14_12, VI1_CLK_B, SEL_VIN1_1), + PINMUX_IPSR_MSEL(IP10_14_12, SCK1_D, SEL_SCIF1_3), + PINMUX_IPSR_MSEL(IP10_14_12, IECLK_B, SEL_IEBUS_1), + PINMUX_IPSR_MSEL(IP10_14_12, LCD_FLM_B, SEL_LCDC_1), - PINMUX_IPSR_MODSEL_DATA(IP10_15, AUDIO_CLKB_A, SEL_AUDIO_CLKB_0), - PINMUX_IPSR_MODSEL_DATA(IP10_15, LCD_CLK_B, SEL_LCDC_1), + PINMUX_IPSR_MSEL(IP10_15, AUDIO_CLKB_A, SEL_AUDIO_CLKB_0), + PINMUX_IPSR_MSEL(IP10_15, LCD_CLK_B, SEL_LCDC_1), PINMUX_IPSR_DATA(IP10_18_16, AUDIO_CLKC), - PINMUX_IPSR_MODSEL_DATA(IP10_18_16, SCK1_E, SEL_SCIF1_4), - PINMUX_IPSR_MODSEL_DATA(IP10_18_16, HCTS0_C, SEL_HSCIF_2), - PINMUX_IPSR_MODSEL_DATA(IP10_18_16, FRB_B, SEL_FLCTL_1), - PINMUX_IPSR_MODSEL_DATA(IP10_18_16, LCD_VEPWC_B, SEL_LCDC_1), + PINMUX_IPSR_MSEL(IP10_18_16, SCK1_E, SEL_SCIF1_4), + PINMUX_IPSR_MSEL(IP10_18_16, HCTS0_C, SEL_HSCIF_2), + PINMUX_IPSR_MSEL(IP10_18_16, FRB_B, SEL_FLCTL_1), + PINMUX_IPSR_MSEL(IP10_18_16, LCD_VEPWC_B, SEL_LCDC_1), PINMUX_IPSR_DATA(IP10_21_19, AUDIO_CLKOUT), - PINMUX_IPSR_MODSEL_DATA(IP10_21_19, TX1_E, SEL_SCIF1_4), - PINMUX_IPSR_MODSEL_DATA(IP10_21_19, HRTS0_C, SEL_HSCIF_2), - PINMUX_IPSR_MODSEL_DATA(IP10_21_19, FSE_B, SEL_FLCTL_1), - PINMUX_IPSR_MODSEL_DATA(IP10_21_19, LCD_M_DISP_B, SEL_LCDC_1), + PINMUX_IPSR_MSEL(IP10_21_19, TX1_E, SEL_SCIF1_4), + PINMUX_IPSR_MSEL(IP10_21_19, HRTS0_C, SEL_HSCIF_2), + PINMUX_IPSR_MSEL(IP10_21_19, FSE_B, SEL_FLCTL_1), + PINMUX_IPSR_MSEL(IP10_21_19, LCD_M_DISP_B, SEL_LCDC_1), - PINMUX_IPSR_MODSEL_DATA(IP10_22, CAN_CLK_A, SEL_RCAN_CLK_0), - PINMUX_IPSR_MODSEL_DATA(IP10_22, RX4_D, SEL_SCIF4_3), + PINMUX_IPSR_MSEL(IP10_22, CAN_CLK_A, SEL_RCAN_CLK_0), + PINMUX_IPSR_MSEL(IP10_22, RX4_D, SEL_SCIF4_3), - PINMUX_IPSR_MODSEL_DATA(IP10_24_23, CAN0_TX_A, SEL_RCAN0_0), - PINMUX_IPSR_MODSEL_DATA(IP10_24_23, TX4_D, SEL_SCIF4_3), + PINMUX_IPSR_MSEL(IP10_24_23, CAN0_TX_A, SEL_RCAN0_0), + PINMUX_IPSR_MSEL(IP10_24_23, TX4_D, SEL_SCIF4_3), PINMUX_IPSR_DATA(IP10_24_23, MLB_CLK), - PINMUX_IPSR_MODSEL_DATA(IP10_25, CAN1_RX_A, SEL_RCAN1_0), - PINMUX_IPSR_MODSEL_DATA(IP10_25, IRQ1_B, SEL_INTC_1), + PINMUX_IPSR_MSEL(IP10_25, CAN1_RX_A, SEL_RCAN1_0), + PINMUX_IPSR_MSEL(IP10_25, IRQ1_B, SEL_INTC_1), - PINMUX_IPSR_MODSEL_DATA(IP10_27_26, CAN0_RX_A, SEL_RCAN0_0), - PINMUX_IPSR_MODSEL_DATA(IP10_27_26, IRQ0_B, SEL_INTC_1), + PINMUX_IPSR_MSEL(IP10_27_26, CAN0_RX_A, SEL_RCAN0_0), + PINMUX_IPSR_MSEL(IP10_27_26, IRQ0_B, SEL_INTC_1), PINMUX_IPSR_DATA(IP10_27_26, MLB_SIG), - PINMUX_IPSR_MODSEL_DATA(IP10_29_28, CAN1_TX_A, SEL_RCAN1_0), - PINMUX_IPSR_MODSEL_DATA(IP10_29_28, TX5_C, SEL_SCIF1_2), + PINMUX_IPSR_MSEL(IP10_29_28, CAN1_TX_A, SEL_RCAN1_0), + PINMUX_IPSR_MSEL(IP10_29_28, TX5_C, SEL_SCIF1_2), PINMUX_IPSR_DATA(IP10_29_28, MLB_DAT), /* IPSR11 */ PINMUX_IPSR_DATA(IP11_0, SCL1), - PINMUX_IPSR_MODSEL_DATA(IP11_0, SCIF_CLK_C, SEL_SCIF_CLK_2), + PINMUX_IPSR_MSEL(IP11_0, SCIF_CLK_C, SEL_SCIF_CLK_2), PINMUX_IPSR_DATA(IP11_1, SDA1), - PINMUX_IPSR_MODSEL_DATA(IP11_0, RX1_E, SEL_SCIF1_4), + PINMUX_IPSR_MSEL(IP11_0, RX1_E, SEL_SCIF1_4), PINMUX_IPSR_DATA(IP11_2, SDA0), - PINMUX_IPSR_MODSEL_DATA(IP11_2, HIFEBL_A, SEL_HIF_0), + PINMUX_IPSR_MSEL(IP11_2, HIFEBL_A, SEL_HIF_0), PINMUX_IPSR_DATA(IP11_3, SDSELF), - PINMUX_IPSR_MODSEL_DATA(IP11_3, RTS1_E, SEL_SCIF1_3), + PINMUX_IPSR_MSEL(IP11_3, RTS1_E, SEL_SCIF1_3), - PINMUX_IPSR_MODSEL_DATA(IP11_6_4, SCIF_CLK_A, SEL_SCIF_CLK_0), - PINMUX_IPSR_MODSEL_DATA(IP11_6_4, HSPI_CLK_A, SEL_HSPI_0), + PINMUX_IPSR_MSEL(IP11_6_4, SCIF_CLK_A, SEL_SCIF_CLK_0), + PINMUX_IPSR_MSEL(IP11_6_4, HSPI_CLK_A, SEL_HSPI_0), PINMUX_IPSR_DATA(IP11_6_4, VI0_CLK), - PINMUX_IPSR_MODSEL_DATA(IP11_6_4, RMII0_TXD0_A, SEL_RMII_0), + PINMUX_IPSR_MSEL(IP11_6_4, RMII0_TXD0_A, SEL_RMII_0), PINMUX_IPSR_DATA(IP11_6_4, ET0_ERXD4), - PINMUX_IPSR_MODSEL_DATA(IP11_9_7, SCK0_A, SEL_SCIF0_0), - PINMUX_IPSR_MODSEL_DATA(IP11_9_7, HSPI_CS_A, SEL_HSPI_0), + PINMUX_IPSR_MSEL(IP11_9_7, SCK0_A, SEL_SCIF0_0), + PINMUX_IPSR_MSEL(IP11_9_7, HSPI_CS_A, SEL_HSPI_0), PINMUX_IPSR_DATA(IP11_9_7, VI0_CLKENB), - PINMUX_IPSR_MODSEL_DATA(IP11_9_7, RMII0_TXD1_A, SEL_RMII_0), + PINMUX_IPSR_MSEL(IP11_9_7, RMII0_TXD1_A, SEL_RMII_0), PINMUX_IPSR_DATA(IP11_9_7, ET0_ERXD5), - PINMUX_IPSR_MODSEL_DATA(IP11_11_10, RX0_A, SEL_SCIF0_0), - PINMUX_IPSR_MODSEL_DATA(IP11_11_10, HSPI_RX_A, SEL_HSPI_0), - PINMUX_IPSR_MODSEL_DATA(IP11_11_10, RMII0_RXD0_A, SEL_RMII_0), + PINMUX_IPSR_MSEL(IP11_11_10, RX0_A, SEL_SCIF0_0), + PINMUX_IPSR_MSEL(IP11_11_10, HSPI_RX_A, SEL_HSPI_0), + PINMUX_IPSR_MSEL(IP11_11_10, RMII0_RXD0_A, SEL_RMII_0), PINMUX_IPSR_DATA(IP11_11_10, ET0_ERXD6), - PINMUX_IPSR_MODSEL_DATA(IP11_12, TX0_A, SEL_SCIF0_0), - PINMUX_IPSR_MODSEL_DATA(IP11_12, HSPI_TX_A, SEL_HSPI_0), + PINMUX_IPSR_MSEL(IP11_12, TX0_A, SEL_SCIF0_0), + PINMUX_IPSR_MSEL(IP11_12, HSPI_TX_A, SEL_HSPI_0), PINMUX_IPSR_DATA(IP11_15_13, PENC1), - PINMUX_IPSR_MODSEL_DATA(IP11_15_13, TX3_D, SEL_SCIF3_3), - PINMUX_IPSR_MODSEL_DATA(IP11_15_13, CAN1_TX_B, SEL_RCAN1_1), - PINMUX_IPSR_MODSEL_DATA(IP11_15_13, TX5_D, SEL_SCIF5_3), - PINMUX_IPSR_MODSEL_DATA(IP11_15_13, IETX_B, SEL_IEBUS_1), + PINMUX_IPSR_MSEL(IP11_15_13, TX3_D, SEL_SCIF3_3), + PINMUX_IPSR_MSEL(IP11_15_13, CAN1_TX_B, SEL_RCAN1_1), + PINMUX_IPSR_MSEL(IP11_15_13, TX5_D, SEL_SCIF5_3), + PINMUX_IPSR_MSEL(IP11_15_13, IETX_B, SEL_IEBUS_1), PINMUX_IPSR_DATA(IP11_18_16, USB_OVC1), - PINMUX_IPSR_MODSEL_DATA(IP11_18_16, RX3_D, SEL_SCIF3_3), - PINMUX_IPSR_MODSEL_DATA(IP11_18_16, CAN1_RX_B, SEL_RCAN1_1), - PINMUX_IPSR_MODSEL_DATA(IP11_18_16, RX5_D, SEL_SCIF5_3), - PINMUX_IPSR_MODSEL_DATA(IP11_18_16, IERX_B, SEL_IEBUS_1), + PINMUX_IPSR_MSEL(IP11_18_16, RX3_D, SEL_SCIF3_3), + PINMUX_IPSR_MSEL(IP11_18_16, CAN1_RX_B, SEL_RCAN1_1), + PINMUX_IPSR_MSEL(IP11_18_16, RX5_D, SEL_SCIF5_3), + PINMUX_IPSR_MSEL(IP11_18_16, IERX_B, SEL_IEBUS_1), PINMUX_IPSR_DATA(IP11_20_19, DREQ0), - PINMUX_IPSR_MODSEL_DATA(IP11_20_19, SD1_CLK_A, SEL_SDHI1_0), + PINMUX_IPSR_MSEL(IP11_20_19, SD1_CLK_A, SEL_SDHI1_0), PINMUX_IPSR_DATA(IP11_20_19, ET0_TX_EN), PINMUX_IPSR_DATA(IP11_22_21, DACK0), - PINMUX_IPSR_MODSEL_DATA(IP11_22_21, SD1_DAT3_A, SEL_SDHI1_0), + PINMUX_IPSR_MSEL(IP11_22_21, SD1_DAT3_A, SEL_SDHI1_0), PINMUX_IPSR_DATA(IP11_22_21, ET0_TX_ER), PINMUX_IPSR_DATA(IP11_25_23, DREQ1), - PINMUX_IPSR_MODSEL_DATA(IP11_25_23, HSPI_CLK_B, SEL_HSPI_1), - PINMUX_IPSR_MODSEL_DATA(IP11_25_23, RX4_B, SEL_SCIF4_1), - PINMUX_IPSR_MODSEL_DATA(IP11_25_23, ET0_PHY_INT_C, SEL_ET0_CTL_0), - PINMUX_IPSR_MODSEL_DATA(IP11_25_23, ET0_TX_CLK_A, SEL_ET0_0), + PINMUX_IPSR_MSEL(IP11_25_23, HSPI_CLK_B, SEL_HSPI_1), + PINMUX_IPSR_MSEL(IP11_25_23, RX4_B, SEL_SCIF4_1), + PINMUX_IPSR_MSEL(IP11_25_23, ET0_PHY_INT_C, SEL_ET0_CTL_0), + PINMUX_IPSR_MSEL(IP11_25_23, ET0_TX_CLK_A, SEL_ET0_0), PINMUX_IPSR_DATA(IP11_27_26, DACK1), - PINMUX_IPSR_MODSEL_DATA(IP11_27_26, HSPI_CS_B, SEL_HSPI_1), - PINMUX_IPSR_MODSEL_DATA(IP11_27_26, TX4_B, SEL_SCIF3_1), - PINMUX_IPSR_MODSEL_DATA(IP11_27_26, ET0_RX_CLK_A, SEL_ET0_0), + PINMUX_IPSR_MSEL(IP11_27_26, HSPI_CS_B, SEL_HSPI_1), + PINMUX_IPSR_MSEL(IP11_27_26, TX4_B, SEL_SCIF3_1), + PINMUX_IPSR_MSEL(IP11_27_26, ET0_RX_CLK_A, SEL_ET0_0), PINMUX_IPSR_DATA(IP11_28, PRESETOUT), PINMUX_IPSR_DATA(IP11_28, ST_CLKOUT), -- cgit v0.10.2 From adedb87fb61f5a418a1aabdb989bc0f55895e44f Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Thu, 3 Sep 2015 02:49:56 +0000 Subject: pinctrl: sh-pfc: r8a7794: use PINMUX_IPSR_MSEL() Now, PINMUX_IPSR_MSEL() and PINMUX_IPSR_MODSEL_DATA() are same. Current PFC driver is very difficult to read, because macro names are using different length. PINMUX_IPSR_NOGP(ispr, ...) PINMUX_IPSR_DATA(ipsr, ...) PINMUX_IPSR_NOGM(ispr, ...) PINMUX_IPSR_NOFN(ipsr, ...) PINMUX_IPSR_MSEL(ipsr, ...) PINMUX_IPSR_MODSEL_DATA(ipsr, ...) It can be readable if we can use PINMUX_IPSR_MSEL() instead of PINMUX_IPSR_MODSEL_DATA() PINMUX_IPSR_NOGP(ispr, ...) PINMUX_IPSR_DATA(ipsr, ...) PINMUX_IPSR_NOGM(ispr, ...) PINMUX_IPSR_NOFN(ipsr, ...) PINMUX_IPSR_MSEL(ipsr, ...) Signed-off-by: Kuninori Morimoto Acked-by: Laurent Pinchart Acked-by: Linus Walleij Signed-off-by: Geert Uytterhoeven diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7794.c b/drivers/pinctrl/sh-pfc/pfc-r8a7794.c index 7a8cd9b..2be19d0 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7794.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7794.c @@ -644,10 +644,10 @@ static const u16 pinmux_data[] = { /* IPSR0 */ PINMUX_IPSR_DATA(IP0_0, SD1_CD), - PINMUX_IPSR_MODSEL_DATA(IP0_0, CAN0_RX, SEL_CAN0_0), + PINMUX_IPSR_MSEL(IP0_0, CAN0_RX, SEL_CAN0_0), PINMUX_IPSR_DATA(IP0_9_8, SD1_WP), PINMUX_IPSR_DATA(IP0_9_8, IRQ7), - PINMUX_IPSR_MODSEL_DATA(IP0_9_8, CAN0_TX, SEL_CAN0_0), + PINMUX_IPSR_MSEL(IP0_9_8, CAN0_TX, SEL_CAN0_0), PINMUX_IPSR_DATA(IP0_10, MMC_CLK), PINMUX_IPSR_DATA(IP0_10, SD2_CLK), PINMUX_IPSR_DATA(IP0_11, MMC_CMD), @@ -665,68 +665,68 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_DATA(IP0_17, MMC_D5), PINMUX_IPSR_DATA(IP0_17, SD2_WP), PINMUX_IPSR_DATA(IP0_19_18, MMC_D6), - PINMUX_IPSR_MODSEL_DATA(IP0_19_18, SCIF0_RXD, SEL_SCIF0_0), - PINMUX_IPSR_MODSEL_DATA(IP0_19_18, I2C2_SCL_B, SEL_I2C02_1), - PINMUX_IPSR_MODSEL_DATA(IP0_19_18, CAN1_RX, SEL_CAN1_0), + PINMUX_IPSR_MSEL(IP0_19_18, SCIF0_RXD, SEL_SCIF0_0), + PINMUX_IPSR_MSEL(IP0_19_18, I2C2_SCL_B, SEL_I2C02_1), + PINMUX_IPSR_MSEL(IP0_19_18, CAN1_RX, SEL_CAN1_0), PINMUX_IPSR_DATA(IP0_21_20, MMC_D7), - PINMUX_IPSR_MODSEL_DATA(IP0_21_20, SCIF0_TXD, SEL_SCIF0_0), - PINMUX_IPSR_MODSEL_DATA(IP0_21_20, I2C2_SDA_B, SEL_I2C02_1), - PINMUX_IPSR_MODSEL_DATA(IP0_21_20, CAN1_TX, SEL_CAN1_0), + PINMUX_IPSR_MSEL(IP0_21_20, SCIF0_TXD, SEL_SCIF0_0), + PINMUX_IPSR_MSEL(IP0_21_20, I2C2_SDA_B, SEL_I2C02_1), + PINMUX_IPSR_MSEL(IP0_21_20, CAN1_TX, SEL_CAN1_0), PINMUX_IPSR_DATA(IP0_23_22, D0), - PINMUX_IPSR_MODSEL_DATA(IP0_23_22, SCIFA3_SCK_B, SEL_SCIFA3_1), + PINMUX_IPSR_MSEL(IP0_23_22, SCIFA3_SCK_B, SEL_SCIFA3_1), PINMUX_IPSR_DATA(IP0_23_22, IRQ4), PINMUX_IPSR_DATA(IP0_24, D1), - PINMUX_IPSR_MODSEL_DATA(IP0_24, SCIFA3_RXD_B, SEL_SCIFA3_1), + PINMUX_IPSR_MSEL(IP0_24, SCIFA3_RXD_B, SEL_SCIFA3_1), PINMUX_IPSR_DATA(IP0_25, D2), - PINMUX_IPSR_MODSEL_DATA(IP0_25, SCIFA3_TXD_B, SEL_SCIFA3_1), + PINMUX_IPSR_MSEL(IP0_25, SCIFA3_TXD_B, SEL_SCIFA3_1), PINMUX_IPSR_DATA(IP0_27_26, D3), - PINMUX_IPSR_MODSEL_DATA(IP0_27_26, I2C3_SCL_B, SEL_I2C03_1), - PINMUX_IPSR_MODSEL_DATA(IP0_27_26, SCIF5_RXD_B, SEL_SCIF5_1), + PINMUX_IPSR_MSEL(IP0_27_26, I2C3_SCL_B, SEL_I2C03_1), + PINMUX_IPSR_MSEL(IP0_27_26, SCIF5_RXD_B, SEL_SCIF5_1), PINMUX_IPSR_DATA(IP0_29_28, D4), - PINMUX_IPSR_MODSEL_DATA(IP0_29_28, I2C3_SDA_B, SEL_I2C03_1), - PINMUX_IPSR_MODSEL_DATA(IP0_29_28, SCIF5_TXD_B, SEL_SCIF5_1), + PINMUX_IPSR_MSEL(IP0_29_28, I2C3_SDA_B, SEL_I2C03_1), + PINMUX_IPSR_MSEL(IP0_29_28, SCIF5_TXD_B, SEL_SCIF5_1), PINMUX_IPSR_DATA(IP0_31_30, D5), - PINMUX_IPSR_MODSEL_DATA(IP0_31_30, SCIF4_RXD_B, SEL_SCIF4_1), - PINMUX_IPSR_MODSEL_DATA(IP0_31_30, I2C0_SCL_D, SEL_I2C00_3), + PINMUX_IPSR_MSEL(IP0_31_30, SCIF4_RXD_B, SEL_SCIF4_1), + PINMUX_IPSR_MSEL(IP0_31_30, I2C0_SCL_D, SEL_I2C00_3), /* IPSR1 */ PINMUX_IPSR_DATA(IP1_1_0, D6), - PINMUX_IPSR_MODSEL_DATA(IP1_1_0, SCIF4_TXD_B, SEL_SCIF4_1), - PINMUX_IPSR_MODSEL_DATA(IP1_1_0, I2C0_SDA_D, SEL_I2C00_3), + PINMUX_IPSR_MSEL(IP1_1_0, SCIF4_TXD_B, SEL_SCIF4_1), + PINMUX_IPSR_MSEL(IP1_1_0, I2C0_SDA_D, SEL_I2C00_3), PINMUX_IPSR_DATA(IP1_3_2, D7), PINMUX_IPSR_DATA(IP1_3_2, IRQ3), - PINMUX_IPSR_MODSEL_DATA(IP1_3_2, TCLK1, SEL_TMU_0), + PINMUX_IPSR_MSEL(IP1_3_2, TCLK1, SEL_TMU_0), PINMUX_IPSR_DATA(IP1_3_2, PWM6_B), PINMUX_IPSR_DATA(IP1_5_4, D8), PINMUX_IPSR_DATA(IP1_5_4, HSCIF2_HRX), - PINMUX_IPSR_MODSEL_DATA(IP1_5_4, I2C1_SCL_B, SEL_I2C01_1), + PINMUX_IPSR_MSEL(IP1_5_4, I2C1_SCL_B, SEL_I2C01_1), PINMUX_IPSR_DATA(IP1_7_6, D9), PINMUX_IPSR_DATA(IP1_7_6, HSCIF2_HTX), - PINMUX_IPSR_MODSEL_DATA(IP1_7_6, I2C1_SDA_B, SEL_I2C01_1), + PINMUX_IPSR_MSEL(IP1_7_6, I2C1_SDA_B, SEL_I2C01_1), PINMUX_IPSR_DATA(IP1_10_8, D10), PINMUX_IPSR_DATA(IP1_10_8, HSCIF2_HSCK), - PINMUX_IPSR_MODSEL_DATA(IP1_10_8, SCIF1_SCK_C, SEL_SCIF1_2), + PINMUX_IPSR_MSEL(IP1_10_8, SCIF1_SCK_C, SEL_SCIF1_2), PINMUX_IPSR_DATA(IP1_10_8, IRQ6), PINMUX_IPSR_DATA(IP1_10_8, PWM5_C), PINMUX_IPSR_DATA(IP1_12_11, D11), PINMUX_IPSR_DATA(IP1_12_11, HSCIF2_HCTS_N), - PINMUX_IPSR_MODSEL_DATA(IP1_12_11, SCIF1_RXD_C, SEL_SCIF1_2), - PINMUX_IPSR_MODSEL_DATA(IP1_12_11, I2C1_SCL_D, SEL_I2C01_3), + PINMUX_IPSR_MSEL(IP1_12_11, SCIF1_RXD_C, SEL_SCIF1_2), + PINMUX_IPSR_MSEL(IP1_12_11, I2C1_SCL_D, SEL_I2C01_3), PINMUX_IPSR_DATA(IP1_14_13, D12), PINMUX_IPSR_DATA(IP1_14_13, HSCIF2_HRTS_N), - PINMUX_IPSR_MODSEL_DATA(IP1_14_13, SCIF1_TXD_C, SEL_SCIF1_2), - PINMUX_IPSR_MODSEL_DATA(IP1_14_13, I2C1_SDA_D, SEL_I2C01_3), + PINMUX_IPSR_MSEL(IP1_14_13, SCIF1_TXD_C, SEL_SCIF1_2), + PINMUX_IPSR_MSEL(IP1_14_13, I2C1_SDA_D, SEL_I2C01_3), PINMUX_IPSR_DATA(IP1_17_15, D13), - PINMUX_IPSR_MODSEL_DATA(IP1_17_15, SCIFA1_SCK, SEL_SCIFA1_0), + PINMUX_IPSR_MSEL(IP1_17_15, SCIFA1_SCK, SEL_SCIFA1_0), PINMUX_IPSR_DATA(IP1_17_15, TANS1), PINMUX_IPSR_DATA(IP1_17_15, PWM2_C), - PINMUX_IPSR_MODSEL_DATA(IP1_17_15, TCLK2_B, SEL_TMU_1), + PINMUX_IPSR_MSEL(IP1_17_15, TCLK2_B, SEL_TMU_1), PINMUX_IPSR_DATA(IP1_19_18, D14), - PINMUX_IPSR_MODSEL_DATA(IP1_19_18, SCIFA1_RXD, SEL_SCIFA1_0), - PINMUX_IPSR_MODSEL_DATA(IP1_19_18, IIC0_SCL_B, SEL_IIC00_1), + PINMUX_IPSR_MSEL(IP1_19_18, SCIFA1_RXD, SEL_SCIFA1_0), + PINMUX_IPSR_MSEL(IP1_19_18, IIC0_SCL_B, SEL_IIC00_1), PINMUX_IPSR_DATA(IP1_21_20, D15), - PINMUX_IPSR_MODSEL_DATA(IP1_21_20, SCIFA1_TXD, SEL_SCIFA1_0), - PINMUX_IPSR_MODSEL_DATA(IP1_21_20, IIC0_SDA_B, SEL_IIC00_1), + PINMUX_IPSR_MSEL(IP1_21_20, SCIFA1_TXD, SEL_SCIFA1_0), + PINMUX_IPSR_MSEL(IP1_21_20, IIC0_SDA_B, SEL_IIC00_1), PINMUX_IPSR_DATA(IP1_23_22, A0), PINMUX_IPSR_DATA(IP1_23_22, SCIFB1_SCK), PINMUX_IPSR_DATA(IP1_23_22, PWM3_B), @@ -742,58 +742,58 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_DATA(IP1_29_28, TPUTO3_C), PINMUX_IPSR_DATA(IP1_31_30, A6), PINMUX_IPSR_DATA(IP1_31_30, SCIFB0_CTS_N), - PINMUX_IPSR_MODSEL_DATA(IP1_31_30, SCIFA4_RXD_B, SEL_SCIFA4_1), + PINMUX_IPSR_MSEL(IP1_31_30, SCIFA4_RXD_B, SEL_SCIFA4_1), PINMUX_IPSR_DATA(IP1_31_30, TPUTO2_C), /* IPSR2 */ PINMUX_IPSR_DATA(IP2_1_0, A7), PINMUX_IPSR_DATA(IP2_1_0, SCIFB0_RTS_N), - PINMUX_IPSR_MODSEL_DATA(IP2_1_0, SCIFA4_TXD_B, SEL_SCIFA4_1), + PINMUX_IPSR_MSEL(IP2_1_0, SCIFA4_TXD_B, SEL_SCIFA4_1), PINMUX_IPSR_DATA(IP2_3_2, A8), - PINMUX_IPSR_MODSEL_DATA(IP2_3_2, MSIOF1_RXD, SEL_MSI1_0), - PINMUX_IPSR_MODSEL_DATA(IP2_3_2, SCIFA0_RXD_B, SEL_SCIFA0_1), + PINMUX_IPSR_MSEL(IP2_3_2, MSIOF1_RXD, SEL_MSI1_0), + PINMUX_IPSR_MSEL(IP2_3_2, SCIFA0_RXD_B, SEL_SCIFA0_1), PINMUX_IPSR_DATA(IP2_5_4, A9), - PINMUX_IPSR_MODSEL_DATA(IP2_5_4, MSIOF1_TXD, SEL_MSI1_0), - PINMUX_IPSR_MODSEL_DATA(IP2_5_4, SCIFA0_TXD_B, SEL_SCIFA0_1), + PINMUX_IPSR_MSEL(IP2_5_4, MSIOF1_TXD, SEL_MSI1_0), + PINMUX_IPSR_MSEL(IP2_5_4, SCIFA0_TXD_B, SEL_SCIFA0_1), PINMUX_IPSR_DATA(IP2_7_6, A10), - PINMUX_IPSR_MODSEL_DATA(IP2_7_6, MSIOF1_SCK, SEL_MSI1_0), - PINMUX_IPSR_MODSEL_DATA(IP2_7_6, IIC1_SCL_B, SEL_IIC01_1), + PINMUX_IPSR_MSEL(IP2_7_6, MSIOF1_SCK, SEL_MSI1_0), + PINMUX_IPSR_MSEL(IP2_7_6, IIC1_SCL_B, SEL_IIC01_1), PINMUX_IPSR_DATA(IP2_9_8, A11), - PINMUX_IPSR_MODSEL_DATA(IP2_9_8, MSIOF1_SYNC, SEL_MSI1_0), - PINMUX_IPSR_MODSEL_DATA(IP2_9_8, IIC1_SDA_B, SEL_IIC01_1), + PINMUX_IPSR_MSEL(IP2_9_8, MSIOF1_SYNC, SEL_MSI1_0), + PINMUX_IPSR_MSEL(IP2_9_8, IIC1_SDA_B, SEL_IIC01_1), PINMUX_IPSR_DATA(IP2_11_10, A12), - PINMUX_IPSR_MODSEL_DATA(IP2_11_10, MSIOF1_SS1, SEL_MSI1_0), - PINMUX_IPSR_MODSEL_DATA(IP2_11_10, SCIFA5_RXD_B, SEL_SCIFA5_1), + PINMUX_IPSR_MSEL(IP2_11_10, MSIOF1_SS1, SEL_MSI1_0), + PINMUX_IPSR_MSEL(IP2_11_10, SCIFA5_RXD_B, SEL_SCIFA5_1), PINMUX_IPSR_DATA(IP2_13_12, A13), - PINMUX_IPSR_MODSEL_DATA(IP2_13_12, MSIOF1_SS2, SEL_MSI1_0), - PINMUX_IPSR_MODSEL_DATA(IP2_13_12, SCIFA5_TXD_B, SEL_SCIFA5_1), + PINMUX_IPSR_MSEL(IP2_13_12, MSIOF1_SS2, SEL_MSI1_0), + PINMUX_IPSR_MSEL(IP2_13_12, SCIFA5_TXD_B, SEL_SCIFA5_1), PINMUX_IPSR_DATA(IP2_15_14, A14), - PINMUX_IPSR_MODSEL_DATA(IP2_15_14, MSIOF2_RXD, SEL_MSI2_0), - PINMUX_IPSR_MODSEL_DATA(IP2_15_14, HSCIF0_HRX_B, SEL_HSCIF0_1), - PINMUX_IPSR_MODSEL_DATA(IP2_15_14, DREQ1_N, SEL_LBS_0), + PINMUX_IPSR_MSEL(IP2_15_14, MSIOF2_RXD, SEL_MSI2_0), + PINMUX_IPSR_MSEL(IP2_15_14, HSCIF0_HRX_B, SEL_HSCIF0_1), + PINMUX_IPSR_MSEL(IP2_15_14, DREQ1_N, SEL_LBS_0), PINMUX_IPSR_DATA(IP2_17_16, A15), - PINMUX_IPSR_MODSEL_DATA(IP2_17_16, MSIOF2_TXD, SEL_MSI2_0), - PINMUX_IPSR_MODSEL_DATA(IP2_17_16, HSCIF0_HTX_B, SEL_HSCIF0_1), - PINMUX_IPSR_MODSEL_DATA(IP2_17_16, DACK1, SEL_LBS_0), + PINMUX_IPSR_MSEL(IP2_17_16, MSIOF2_TXD, SEL_MSI2_0), + PINMUX_IPSR_MSEL(IP2_17_16, HSCIF0_HTX_B, SEL_HSCIF0_1), + PINMUX_IPSR_MSEL(IP2_17_16, DACK1, SEL_LBS_0), PINMUX_IPSR_DATA(IP2_20_18, A16), - PINMUX_IPSR_MODSEL_DATA(IP2_20_18, MSIOF2_SCK, SEL_MSI2_0), - PINMUX_IPSR_MODSEL_DATA(IP2_20_18, HSCIF0_HSCK_B, SEL_HSCIF0_1), - PINMUX_IPSR_MODSEL_DATA(IP2_20_18, SPEEDIN, SEL_RSP_0), - PINMUX_IPSR_MODSEL_DATA(IP2_20_18, VSP, SEL_SPDM_0), - PINMUX_IPSR_MODSEL_DATA(IP2_20_18, CAN_CLK_C, SEL_CAN_2), + PINMUX_IPSR_MSEL(IP2_20_18, MSIOF2_SCK, SEL_MSI2_0), + PINMUX_IPSR_MSEL(IP2_20_18, HSCIF0_HSCK_B, SEL_HSCIF0_1), + PINMUX_IPSR_MSEL(IP2_20_18, SPEEDIN, SEL_RSP_0), + PINMUX_IPSR_MSEL(IP2_20_18, VSP, SEL_SPDM_0), + PINMUX_IPSR_MSEL(IP2_20_18, CAN_CLK_C, SEL_CAN_2), PINMUX_IPSR_DATA(IP2_20_18, TPUTO2_B), PINMUX_IPSR_DATA(IP2_23_21, A17), - PINMUX_IPSR_MODSEL_DATA(IP2_23_21, MSIOF2_SYNC, SEL_MSI2_0), - PINMUX_IPSR_MODSEL_DATA(IP2_23_21, SCIF4_RXD_E, SEL_SCIF4_4), - PINMUX_IPSR_MODSEL_DATA(IP2_23_21, CAN1_RX_B, SEL_CAN1_1), - PINMUX_IPSR_MODSEL_DATA(IP2_23_21, AVB_AVTP_CAPTURE_B, SEL_AVB_1), + PINMUX_IPSR_MSEL(IP2_23_21, MSIOF2_SYNC, SEL_MSI2_0), + PINMUX_IPSR_MSEL(IP2_23_21, SCIF4_RXD_E, SEL_SCIF4_4), + PINMUX_IPSR_MSEL(IP2_23_21, CAN1_RX_B, SEL_CAN1_1), + PINMUX_IPSR_MSEL(IP2_23_21, AVB_AVTP_CAPTURE_B, SEL_AVB_1), PINMUX_IPSR_DATA(IP2_26_24, A18), - PINMUX_IPSR_MODSEL_DATA(IP2_26_24, MSIOF2_SS1, SEL_MSI2_0), - PINMUX_IPSR_MODSEL_DATA(IP2_26_24, SCIF4_TXD_E, SEL_SCIF4_4), - PINMUX_IPSR_MODSEL_DATA(IP2_26_24, CAN1_TX_B, SEL_CAN1_1), - PINMUX_IPSR_MODSEL_DATA(IP2_26_24, AVB_AVTP_MATCH_B, SEL_AVB_1), + PINMUX_IPSR_MSEL(IP2_26_24, MSIOF2_SS1, SEL_MSI2_0), + PINMUX_IPSR_MSEL(IP2_26_24, SCIF4_TXD_E, SEL_SCIF4_4), + PINMUX_IPSR_MSEL(IP2_26_24, CAN1_TX_B, SEL_CAN1_1), + PINMUX_IPSR_MSEL(IP2_26_24, AVB_AVTP_MATCH_B, SEL_AVB_1), PINMUX_IPSR_DATA(IP2_29_27, A19), - PINMUX_IPSR_MODSEL_DATA(IP2_29_27, MSIOF2_SS2, SEL_MSI2_0), + PINMUX_IPSR_MSEL(IP2_29_27, MSIOF2_SS2, SEL_MSI2_0), PINMUX_IPSR_DATA(IP2_29_27, PWM4), PINMUX_IPSR_DATA(IP2_29_27, TPUTO2), PINMUX_IPSR_DATA(IP2_29_27, MOUT0), @@ -831,42 +831,42 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_DATA(IP3_14_13, VI1_DATA11), PINMUX_IPSR_DATA(IP3_17_15, EX_CS2_N), PINMUX_IPSR_DATA(IP3_17_15, PWM0), - PINMUX_IPSR_MODSEL_DATA(IP3_17_15, SCIF4_RXD_C, SEL_SCIF4_2), - PINMUX_IPSR_MODSEL_DATA(IP3_17_15, TS_SDATA_B, SEL_TSIF0_1), - PINMUX_IPSR_MODSEL_DATA(IP3_17_15, RIF0_SYNC, SEL_DR0_0), + PINMUX_IPSR_MSEL(IP3_17_15, SCIF4_RXD_C, SEL_SCIF4_2), + PINMUX_IPSR_MSEL(IP3_17_15, TS_SDATA_B, SEL_TSIF0_1), + PINMUX_IPSR_MSEL(IP3_17_15, RIF0_SYNC, SEL_DR0_0), PINMUX_IPSR_DATA(IP3_17_15, TPUTO3), PINMUX_IPSR_DATA(IP3_17_15, SCIFB2_TXD), - PINMUX_IPSR_MODSEL_DATA(IP3_17_15, SDATA_B, SEL_FSN_1), + PINMUX_IPSR_MSEL(IP3_17_15, SDATA_B, SEL_FSN_1), PINMUX_IPSR_DATA(IP3_20_18, EX_CS3_N), - PINMUX_IPSR_MODSEL_DATA(IP3_20_18, SCIFA2_SCK, SEL_SCIFA2_0), - PINMUX_IPSR_MODSEL_DATA(IP3_20_18, SCIF4_TXD_C, SEL_SCIF4_2), - PINMUX_IPSR_MODSEL_DATA(IP3_20_18, TS_SCK_B, SEL_TSIF0_1), - PINMUX_IPSR_MODSEL_DATA(IP3_20_18, RIF0_CLK, SEL_DR0_0), - PINMUX_IPSR_MODSEL_DATA(IP3_20_18, BPFCLK, SEL_DARC_0), + PINMUX_IPSR_MSEL(IP3_20_18, SCIFA2_SCK, SEL_SCIFA2_0), + PINMUX_IPSR_MSEL(IP3_20_18, SCIF4_TXD_C, SEL_SCIF4_2), + PINMUX_IPSR_MSEL(IP3_20_18, TS_SCK_B, SEL_TSIF0_1), + PINMUX_IPSR_MSEL(IP3_20_18, RIF0_CLK, SEL_DR0_0), + PINMUX_IPSR_MSEL(IP3_20_18, BPFCLK, SEL_DARC_0), PINMUX_IPSR_DATA(IP3_20_18, SCIFB2_SCK), - PINMUX_IPSR_MODSEL_DATA(IP3_20_18, MDATA_B, SEL_FSN_1), + PINMUX_IPSR_MSEL(IP3_20_18, MDATA_B, SEL_FSN_1), PINMUX_IPSR_DATA(IP3_23_21, EX_CS4_N), - PINMUX_IPSR_MODSEL_DATA(IP3_23_21, SCIFA2_RXD, SEL_SCIFA2_0), - PINMUX_IPSR_MODSEL_DATA(IP3_23_21, I2C2_SCL_E, SEL_I2C02_4), - PINMUX_IPSR_MODSEL_DATA(IP3_23_21, TS_SDEN_B, SEL_TSIF0_1), - PINMUX_IPSR_MODSEL_DATA(IP3_23_21, RIF0_D0, SEL_DR0_0), - PINMUX_IPSR_MODSEL_DATA(IP3_23_21, FMCLK, SEL_DARC_0), + PINMUX_IPSR_MSEL(IP3_23_21, SCIFA2_RXD, SEL_SCIFA2_0), + PINMUX_IPSR_MSEL(IP3_23_21, I2C2_SCL_E, SEL_I2C02_4), + PINMUX_IPSR_MSEL(IP3_23_21, TS_SDEN_B, SEL_TSIF0_1), + PINMUX_IPSR_MSEL(IP3_23_21, RIF0_D0, SEL_DR0_0), + PINMUX_IPSR_MSEL(IP3_23_21, FMCLK, SEL_DARC_0), PINMUX_IPSR_DATA(IP3_23_21, SCIFB2_CTS_N), - PINMUX_IPSR_MODSEL_DATA(IP3_23_21, SCKZ_B, SEL_FSN_1), + PINMUX_IPSR_MSEL(IP3_23_21, SCKZ_B, SEL_FSN_1), PINMUX_IPSR_DATA(IP3_26_24, EX_CS5_N), - PINMUX_IPSR_MODSEL_DATA(IP3_26_24, SCIFA2_TXD, SEL_SCIFA2_0), - PINMUX_IPSR_MODSEL_DATA(IP3_26_24, I2C2_SDA_E, SEL_I2C02_4), - PINMUX_IPSR_MODSEL_DATA(IP3_26_24, TS_SPSYNC_B, SEL_TSIF0_1), - PINMUX_IPSR_MODSEL_DATA(IP3_26_24, RIF0_D1, SEL_DR1_0), - PINMUX_IPSR_MODSEL_DATA(IP3_26_24, FMIN, SEL_DARC_0), + PINMUX_IPSR_MSEL(IP3_26_24, SCIFA2_TXD, SEL_SCIFA2_0), + PINMUX_IPSR_MSEL(IP3_26_24, I2C2_SDA_E, SEL_I2C02_4), + PINMUX_IPSR_MSEL(IP3_26_24, TS_SPSYNC_B, SEL_TSIF0_1), + PINMUX_IPSR_MSEL(IP3_26_24, RIF0_D1, SEL_DR1_0), + PINMUX_IPSR_MSEL(IP3_26_24, FMIN, SEL_DARC_0), PINMUX_IPSR_DATA(IP3_26_24, SCIFB2_RTS_N), - PINMUX_IPSR_MODSEL_DATA(IP3_26_24, STM_N_B, SEL_FSN_1), + PINMUX_IPSR_MSEL(IP3_26_24, STM_N_B, SEL_FSN_1), PINMUX_IPSR_DATA(IP3_29_27, BS_N), PINMUX_IPSR_DATA(IP3_29_27, DRACK0), PINMUX_IPSR_DATA(IP3_29_27, PWM1_C), PINMUX_IPSR_DATA(IP3_29_27, TPUTO0_C), PINMUX_IPSR_DATA(IP3_29_27, ATACS01_N), - PINMUX_IPSR_MODSEL_DATA(IP3_29_27, MTS_N_B, SEL_FSN_1), + PINMUX_IPSR_MSEL(IP3_29_27, MTS_N_B, SEL_FSN_1), PINMUX_IPSR_DATA(IP3_30, RD_N), PINMUX_IPSR_DATA(IP3_30, ATACS11_N), PINMUX_IPSR_DATA(IP3_31, RD_WR_N), @@ -874,18 +874,18 @@ static const u16 pinmux_data[] = { /* IPSR4 */ PINMUX_IPSR_DATA(IP4_1_0, EX_WAIT0), - PINMUX_IPSR_MODSEL_DATA(IP4_1_0, CAN_CLK_B, SEL_CAN_1), - PINMUX_IPSR_MODSEL_DATA(IP4_1_0, SCIF_CLK, SEL_SCIF0_0), + PINMUX_IPSR_MSEL(IP4_1_0, CAN_CLK_B, SEL_CAN_1), + PINMUX_IPSR_MSEL(IP4_1_0, SCIF_CLK, SEL_SCIF0_0), PINMUX_IPSR_DATA(IP4_1_0, PWMFSW0), PINMUX_IPSR_DATA(IP4_4_2, DU0_DR0), PINMUX_IPSR_DATA(IP4_4_2, LCDOUT16), - PINMUX_IPSR_MODSEL_DATA(IP4_4_2, SCIF5_RXD_C, SEL_SCIF5_2), - PINMUX_IPSR_MODSEL_DATA(IP4_4_2, I2C2_SCL_D, SEL_I2C02_3), + PINMUX_IPSR_MSEL(IP4_4_2, SCIF5_RXD_C, SEL_SCIF5_2), + PINMUX_IPSR_MSEL(IP4_4_2, I2C2_SCL_D, SEL_I2C02_3), PINMUX_IPSR_DATA(IP4_4_2, CC50_STATE0), PINMUX_IPSR_DATA(IP4_7_5, DU0_DR1), PINMUX_IPSR_DATA(IP4_7_5, LCDOUT17), - PINMUX_IPSR_MODSEL_DATA(IP4_7_5, SCIF5_TXD_C, SEL_SCIF5_2), - PINMUX_IPSR_MODSEL_DATA(IP4_7_5, I2C2_SDA_D, SEL_I2C02_3), + PINMUX_IPSR_MSEL(IP4_7_5, SCIF5_TXD_C, SEL_SCIF5_2), + PINMUX_IPSR_MSEL(IP4_7_5, I2C2_SDA_D, SEL_I2C02_3), PINMUX_IPSR_DATA(IP4_9_8, CC50_STATE1), PINMUX_IPSR_DATA(IP4_9_8, DU0_DR2), PINMUX_IPSR_DATA(IP4_9_8, LCDOUT18), @@ -907,13 +907,13 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_DATA(IP4_19_18, CC50_STATE7), PINMUX_IPSR_DATA(IP4_22_20, DU0_DG0), PINMUX_IPSR_DATA(IP4_22_20, LCDOUT8), - PINMUX_IPSR_MODSEL_DATA(IP4_22_20, SCIFA0_RXD_C, SEL_SCIFA0_2), - PINMUX_IPSR_MODSEL_DATA(IP4_22_20, I2C3_SCL_D, SEL_I2C03_3), + PINMUX_IPSR_MSEL(IP4_22_20, SCIFA0_RXD_C, SEL_SCIFA0_2), + PINMUX_IPSR_MSEL(IP4_22_20, I2C3_SCL_D, SEL_I2C03_3), PINMUX_IPSR_DATA(IP4_22_20, CC50_STATE8), PINMUX_IPSR_DATA(IP4_25_23, DU0_DG1), PINMUX_IPSR_DATA(IP4_25_23, LCDOUT9), - PINMUX_IPSR_MODSEL_DATA(IP4_25_23, SCIFA0_TXD_C, SEL_SCIFA0_2), - PINMUX_IPSR_MODSEL_DATA(IP4_25_23, I2C3_SDA_D, SEL_I2C03_3), + PINMUX_IPSR_MSEL(IP4_25_23, SCIFA0_TXD_C, SEL_SCIFA0_2), + PINMUX_IPSR_MSEL(IP4_25_23, I2C3_SDA_D, SEL_I2C03_3), PINMUX_IPSR_DATA(IP4_25_23, CC50_STATE9), PINMUX_IPSR_DATA(IP4_27_26, DU0_DG2), PINMUX_IPSR_DATA(IP4_27_26, LCDOUT10), @@ -937,15 +937,15 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_DATA(IP5_5_4, CC50_STATE15), PINMUX_IPSR_DATA(IP5_8_6, DU0_DB0), PINMUX_IPSR_DATA(IP5_8_6, LCDOUT0), - PINMUX_IPSR_MODSEL_DATA(IP5_8_6, SCIFA4_RXD_C, SEL_SCIFA4_2), - PINMUX_IPSR_MODSEL_DATA(IP5_8_6, I2C4_SCL_D, SEL_I2C04_3), - PINMUX_IPSR_MODSEL_DATA(IP7_8_6, CAN0_RX_C, SEL_CAN0_2), + PINMUX_IPSR_MSEL(IP5_8_6, SCIFA4_RXD_C, SEL_SCIFA4_2), + PINMUX_IPSR_MSEL(IP5_8_6, I2C4_SCL_D, SEL_I2C04_3), + PINMUX_IPSR_MSEL(IP7_8_6, CAN0_RX_C, SEL_CAN0_2), PINMUX_IPSR_DATA(IP5_8_6, CC50_STATE16), PINMUX_IPSR_DATA(IP5_11_9, DU0_DB1), PINMUX_IPSR_DATA(IP5_11_9, LCDOUT1), - PINMUX_IPSR_MODSEL_DATA(IP5_11_9, SCIFA4_TXD_C, SEL_SCIFA4_2), - PINMUX_IPSR_MODSEL_DATA(IP5_11_9, I2C4_SDA_D, SEL_I2C04_3), - PINMUX_IPSR_MODSEL_DATA(IP5_11_9, CAN0_TX_C, SEL_CAN0_2), + PINMUX_IPSR_MSEL(IP5_11_9, SCIFA4_TXD_C, SEL_SCIFA4_2), + PINMUX_IPSR_MSEL(IP5_11_9, I2C4_SDA_D, SEL_I2C04_3), + PINMUX_IPSR_MSEL(IP5_11_9, CAN0_TX_C, SEL_CAN0_2), PINMUX_IPSR_DATA(IP5_11_9, CC50_STATE17), PINMUX_IPSR_DATA(IP5_13_12, DU0_DB2), PINMUX_IPSR_DATA(IP5_13_12, LCDOUT2), @@ -1010,501 +1010,501 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_DATA(IP6_16, VI0_DATA7_VI0_B7), PINMUX_IPSR_DATA(IP6_16, AVB_RXD6), PINMUX_IPSR_DATA(IP6_19_17, VI0_CLKENB), - PINMUX_IPSR_MODSEL_DATA(IP6_19_17, I2C3_SCL, SEL_I2C03_0), - PINMUX_IPSR_MODSEL_DATA(IP6_19_17, SCIFA5_RXD_C, SEL_SCIFA5_2), - PINMUX_IPSR_MODSEL_DATA(IP6_19_17, IETX_C, SEL_IEB_2), + PINMUX_IPSR_MSEL(IP6_19_17, I2C3_SCL, SEL_I2C03_0), + PINMUX_IPSR_MSEL(IP6_19_17, SCIFA5_RXD_C, SEL_SCIFA5_2), + PINMUX_IPSR_MSEL(IP6_19_17, IETX_C, SEL_IEB_2), PINMUX_IPSR_DATA(IP6_19_17, AVB_RXD7), PINMUX_IPSR_DATA(IP6_22_20, VI0_FIELD), - PINMUX_IPSR_MODSEL_DATA(IP6_22_20, I2C3_SDA, SEL_I2C03_0), - PINMUX_IPSR_MODSEL_DATA(IP6_22_20, SCIFA5_TXD_C, SEL_SCIFA5_2), - PINMUX_IPSR_MODSEL_DATA(IP6_22_20, IECLK_C, SEL_IEB_2), + PINMUX_IPSR_MSEL(IP6_22_20, I2C3_SDA, SEL_I2C03_0), + PINMUX_IPSR_MSEL(IP6_22_20, SCIFA5_TXD_C, SEL_SCIFA5_2), + PINMUX_IPSR_MSEL(IP6_22_20, IECLK_C, SEL_IEB_2), PINMUX_IPSR_DATA(IP6_22_20, AVB_RX_ER), PINMUX_IPSR_DATA(IP6_25_23, VI0_HSYNC_N), - PINMUX_IPSR_MODSEL_DATA(IP6_25_23, SCIF0_RXD_B, SEL_SCIF0_1), - PINMUX_IPSR_MODSEL_DATA(IP6_25_23, I2C0_SCL_C, SEL_I2C00_2), - PINMUX_IPSR_MODSEL_DATA(IP6_25_23, IERX_C, SEL_IEB_2), + PINMUX_IPSR_MSEL(IP6_25_23, SCIF0_RXD_B, SEL_SCIF0_1), + PINMUX_IPSR_MSEL(IP6_25_23, I2C0_SCL_C, SEL_I2C00_2), + PINMUX_IPSR_MSEL(IP6_25_23, IERX_C, SEL_IEB_2), PINMUX_IPSR_DATA(IP6_25_23, AVB_COL), PINMUX_IPSR_DATA(IP6_28_26, VI0_VSYNC_N), - PINMUX_IPSR_MODSEL_DATA(IP6_28_26, SCIF0_TXD_B, SEL_SCIF0_1), - PINMUX_IPSR_MODSEL_DATA(IP6_28_26, I2C0_SDA_C, SEL_I2C00_2), - PINMUX_IPSR_MODSEL_DATA(IP6_28_26, AUDIO_CLKOUT_B, SEL_ADG_1), + PINMUX_IPSR_MSEL(IP6_28_26, SCIF0_TXD_B, SEL_SCIF0_1), + PINMUX_IPSR_MSEL(IP6_28_26, I2C0_SDA_C, SEL_I2C00_2), + PINMUX_IPSR_MSEL(IP6_28_26, AUDIO_CLKOUT_B, SEL_ADG_1), PINMUX_IPSR_DATA(IP6_28_26, AVB_TX_EN), - PINMUX_IPSR_MODSEL_DATA(IP6_31_29, ETH_MDIO, SEL_ETH_0), + PINMUX_IPSR_MSEL(IP6_31_29, ETH_MDIO, SEL_ETH_0), PINMUX_IPSR_DATA(IP6_31_29, VI0_G0), - PINMUX_IPSR_MODSEL_DATA(IP6_31_29, MSIOF2_RXD_B, SEL_MSI2_1), - PINMUX_IPSR_MODSEL_DATA(IP6_31_29, IIC0_SCL_D, SEL_IIC00_3), + PINMUX_IPSR_MSEL(IP6_31_29, MSIOF2_RXD_B, SEL_MSI2_1), + PINMUX_IPSR_MSEL(IP6_31_29, IIC0_SCL_D, SEL_IIC00_3), PINMUX_IPSR_DATA(IP6_31_29, AVB_TX_CLK), - PINMUX_IPSR_MODSEL_DATA(IP6_31_29, ADIDATA, SEL_RAD_0), - PINMUX_IPSR_MODSEL_DATA(IP6_31_29, AD_DI, SEL_ADI_0), + PINMUX_IPSR_MSEL(IP6_31_29, ADIDATA, SEL_RAD_0), + PINMUX_IPSR_MSEL(IP6_31_29, AD_DI, SEL_ADI_0), /* IPSR7 */ - PINMUX_IPSR_MODSEL_DATA(IP7_2_0, ETH_CRS_DV, SEL_ETH_0), + PINMUX_IPSR_MSEL(IP7_2_0, ETH_CRS_DV, SEL_ETH_0), PINMUX_IPSR_DATA(IP7_2_0, VI0_G1), - PINMUX_IPSR_MODSEL_DATA(IP7_2_0, MSIOF2_TXD_B, SEL_MSI2_1), - PINMUX_IPSR_MODSEL_DATA(IP7_2_0, IIC0_SDA_D, SEL_IIC00_3), + PINMUX_IPSR_MSEL(IP7_2_0, MSIOF2_TXD_B, SEL_MSI2_1), + PINMUX_IPSR_MSEL(IP7_2_0, IIC0_SDA_D, SEL_IIC00_3), PINMUX_IPSR_DATA(IP7_2_0, AVB_TXD0), - PINMUX_IPSR_MODSEL_DATA(IP7_2_0, ADICS_SAMP, SEL_RAD_0), - PINMUX_IPSR_MODSEL_DATA(IP7_2_0, AD_DO, SEL_ADI_0), - PINMUX_IPSR_MODSEL_DATA(IP7_5_3, ETH_RX_ER, SEL_ETH_0), + PINMUX_IPSR_MSEL(IP7_2_0, ADICS_SAMP, SEL_RAD_0), + PINMUX_IPSR_MSEL(IP7_2_0, AD_DO, SEL_ADI_0), + PINMUX_IPSR_MSEL(IP7_5_3, ETH_RX_ER, SEL_ETH_0), PINMUX_IPSR_DATA(IP7_5_3, VI0_G2), - PINMUX_IPSR_MODSEL_DATA(IP7_5_3, MSIOF2_SCK_B, SEL_MSI2_1), - PINMUX_IPSR_MODSEL_DATA(IP7_5_3, CAN0_RX_B, SEL_CAN0_1), + PINMUX_IPSR_MSEL(IP7_5_3, MSIOF2_SCK_B, SEL_MSI2_1), + PINMUX_IPSR_MSEL(IP7_5_3, CAN0_RX_B, SEL_CAN0_1), PINMUX_IPSR_DATA(IP7_5_3, AVB_TXD1), - PINMUX_IPSR_MODSEL_DATA(IP7_5_3, ADICLK, SEL_RAD_0), - PINMUX_IPSR_MODSEL_DATA(IP7_5_3, AD_CLK, SEL_ADI_0), - PINMUX_IPSR_MODSEL_DATA(IP7_8_6, ETH_RXD0, SEL_ETH_0), + PINMUX_IPSR_MSEL(IP7_5_3, ADICLK, SEL_RAD_0), + PINMUX_IPSR_MSEL(IP7_5_3, AD_CLK, SEL_ADI_0), + PINMUX_IPSR_MSEL(IP7_8_6, ETH_RXD0, SEL_ETH_0), PINMUX_IPSR_DATA(IP7_8_6, VI0_G3), - PINMUX_IPSR_MODSEL_DATA(IP7_8_6, MSIOF2_SYNC_B, SEL_MSI2_1), - PINMUX_IPSR_MODSEL_DATA(IP7_8_6, CAN0_TX_B, SEL_CAN0_1), + PINMUX_IPSR_MSEL(IP7_8_6, MSIOF2_SYNC_B, SEL_MSI2_1), + PINMUX_IPSR_MSEL(IP7_8_6, CAN0_TX_B, SEL_CAN0_1), PINMUX_IPSR_DATA(IP7_8_6, AVB_TXD2), - PINMUX_IPSR_MODSEL_DATA(IP7_8_6, ADICHS0, SEL_RAD_0), - PINMUX_IPSR_MODSEL_DATA(IP7_8_6, AD_NCS_N, SEL_ADI_0), - PINMUX_IPSR_MODSEL_DATA(IP7_11_9, ETH_RXD1, SEL_ETH_0), + PINMUX_IPSR_MSEL(IP7_8_6, ADICHS0, SEL_RAD_0), + PINMUX_IPSR_MSEL(IP7_8_6, AD_NCS_N, SEL_ADI_0), + PINMUX_IPSR_MSEL(IP7_11_9, ETH_RXD1, SEL_ETH_0), PINMUX_IPSR_DATA(IP7_11_9, VI0_G4), - PINMUX_IPSR_MODSEL_DATA(IP7_11_9, MSIOF2_SS1_B, SEL_MSI2_1), - PINMUX_IPSR_MODSEL_DATA(IP7_11_9, SCIF4_RXD_D, SEL_SCIF4_3), + PINMUX_IPSR_MSEL(IP7_11_9, MSIOF2_SS1_B, SEL_MSI2_1), + PINMUX_IPSR_MSEL(IP7_11_9, SCIF4_RXD_D, SEL_SCIF4_3), PINMUX_IPSR_DATA(IP7_11_9, AVB_TXD3), - PINMUX_IPSR_MODSEL_DATA(IP7_11_9, ADICHS1, SEL_RAD_0), - PINMUX_IPSR_MODSEL_DATA(IP7_14_12, ETH_LINK, SEL_ETH_0), + PINMUX_IPSR_MSEL(IP7_11_9, ADICHS1, SEL_RAD_0), + PINMUX_IPSR_MSEL(IP7_14_12, ETH_LINK, SEL_ETH_0), PINMUX_IPSR_DATA(IP7_14_12, VI0_G5), - PINMUX_IPSR_MODSEL_DATA(IP7_14_12, MSIOF2_SS2_B, SEL_MSI2_1), - PINMUX_IPSR_MODSEL_DATA(IP7_14_12, SCIF4_TXD_D, SEL_SCIF4_3), + PINMUX_IPSR_MSEL(IP7_14_12, MSIOF2_SS2_B, SEL_MSI2_1), + PINMUX_IPSR_MSEL(IP7_14_12, SCIF4_TXD_D, SEL_SCIF4_3), PINMUX_IPSR_DATA(IP7_14_12, AVB_TXD4), - PINMUX_IPSR_MODSEL_DATA(IP7_14_12, ADICHS2, SEL_RAD_0), - PINMUX_IPSR_MODSEL_DATA(IP7_17_15, ETH_REFCLK, SEL_ETH_0), + PINMUX_IPSR_MSEL(IP7_14_12, ADICHS2, SEL_RAD_0), + PINMUX_IPSR_MSEL(IP7_17_15, ETH_REFCLK, SEL_ETH_0), PINMUX_IPSR_DATA(IP7_17_15, VI0_G6), - PINMUX_IPSR_MODSEL_DATA(IP7_17_15, SCIF2_SCK_C, SEL_SCIF2_2), + PINMUX_IPSR_MSEL(IP7_17_15, SCIF2_SCK_C, SEL_SCIF2_2), PINMUX_IPSR_DATA(IP7_17_15, AVB_TXD5), - PINMUX_IPSR_MODSEL_DATA(IP7_17_15, SSI_SCK5_B, SEL_SSI5_1), - PINMUX_IPSR_MODSEL_DATA(IP7_20_18, ETH_TXD1, SEL_ETH_0), + PINMUX_IPSR_MSEL(IP7_17_15, SSI_SCK5_B, SEL_SSI5_1), + PINMUX_IPSR_MSEL(IP7_20_18, ETH_TXD1, SEL_ETH_0), PINMUX_IPSR_DATA(IP7_20_18, VI0_G7), - PINMUX_IPSR_MODSEL_DATA(IP7_20_18, SCIF2_RXD_C, SEL_SCIF2_2), - PINMUX_IPSR_MODSEL_DATA(IP7_20_18, IIC1_SCL_D, SEL_IIC01_3), + PINMUX_IPSR_MSEL(IP7_20_18, SCIF2_RXD_C, SEL_SCIF2_2), + PINMUX_IPSR_MSEL(IP7_20_18, IIC1_SCL_D, SEL_IIC01_3), PINMUX_IPSR_DATA(IP7_20_18, AVB_TXD6), - PINMUX_IPSR_MODSEL_DATA(IP7_20_18, SSI_WS5_B, SEL_SSI5_1), - PINMUX_IPSR_MODSEL_DATA(IP7_23_21, ETH_TX_EN, SEL_ETH_0), + PINMUX_IPSR_MSEL(IP7_20_18, SSI_WS5_B, SEL_SSI5_1), + PINMUX_IPSR_MSEL(IP7_23_21, ETH_TX_EN, SEL_ETH_0), PINMUX_IPSR_DATA(IP7_23_21, VI0_R0), - PINMUX_IPSR_MODSEL_DATA(IP7_23_21, SCIF2_TXD_C, SEL_SCIF2_2), - PINMUX_IPSR_MODSEL_DATA(IP7_23_21, IIC1_SDA_D, SEL_IIC01_3), + PINMUX_IPSR_MSEL(IP7_23_21, SCIF2_TXD_C, SEL_SCIF2_2), + PINMUX_IPSR_MSEL(IP7_23_21, IIC1_SDA_D, SEL_IIC01_3), PINMUX_IPSR_DATA(IP7_23_21, AVB_TXD7), - PINMUX_IPSR_MODSEL_DATA(IP7_23_21, SSI_SDATA5_B, SEL_SSI5_1), - PINMUX_IPSR_MODSEL_DATA(IP7_26_24, ETH_MAGIC, SEL_ETH_0), + PINMUX_IPSR_MSEL(IP7_23_21, SSI_SDATA5_B, SEL_SSI5_1), + PINMUX_IPSR_MSEL(IP7_26_24, ETH_MAGIC, SEL_ETH_0), PINMUX_IPSR_DATA(IP7_26_24, VI0_R1), - PINMUX_IPSR_MODSEL_DATA(IP7_26_24, SCIF3_SCK_B, SEL_SCIF3_1), + PINMUX_IPSR_MSEL(IP7_26_24, SCIF3_SCK_B, SEL_SCIF3_1), PINMUX_IPSR_DATA(IP7_26_24, AVB_TX_ER), - PINMUX_IPSR_MODSEL_DATA(IP7_26_24, SSI_SCK6_B, SEL_SSI6_1), - PINMUX_IPSR_MODSEL_DATA(IP7_29_27, ETH_TXD0, SEL_ETH_0), + PINMUX_IPSR_MSEL(IP7_26_24, SSI_SCK6_B, SEL_SSI6_1), + PINMUX_IPSR_MSEL(IP7_29_27, ETH_TXD0, SEL_ETH_0), PINMUX_IPSR_DATA(IP7_29_27, VI0_R2), - PINMUX_IPSR_MODSEL_DATA(IP7_29_27, SCIF3_RXD_B, SEL_SCIF3_1), - PINMUX_IPSR_MODSEL_DATA(IP7_29_27, I2C4_SCL_E, SEL_I2C04_4), + PINMUX_IPSR_MSEL(IP7_29_27, SCIF3_RXD_B, SEL_SCIF3_1), + PINMUX_IPSR_MSEL(IP7_29_27, I2C4_SCL_E, SEL_I2C04_4), PINMUX_IPSR_DATA(IP7_29_27, AVB_GTX_CLK), - PINMUX_IPSR_MODSEL_DATA(IP7_29_27, SSI_WS6_B, SEL_SSI6_1), + PINMUX_IPSR_MSEL(IP7_29_27, SSI_WS6_B, SEL_SSI6_1), PINMUX_IPSR_DATA(IP7_31, DREQ0_N), PINMUX_IPSR_DATA(IP7_31, SCIFB1_RXD), /* IPSR8 */ - PINMUX_IPSR_MODSEL_DATA(IP8_2_0, ETH_MDC, SEL_ETH_0), + PINMUX_IPSR_MSEL(IP8_2_0, ETH_MDC, SEL_ETH_0), PINMUX_IPSR_DATA(IP8_2_0, VI0_R3), - PINMUX_IPSR_MODSEL_DATA(IP8_2_0, SCIF3_TXD_B, SEL_SCIF3_1), - PINMUX_IPSR_MODSEL_DATA(IP8_2_0, I2C4_SDA_E, SEL_I2C04_4), + PINMUX_IPSR_MSEL(IP8_2_0, SCIF3_TXD_B, SEL_SCIF3_1), + PINMUX_IPSR_MSEL(IP8_2_0, I2C4_SDA_E, SEL_I2C04_4), PINMUX_IPSR_DATA(IP8_2_0, AVB_MDC), - PINMUX_IPSR_MODSEL_DATA(IP8_2_0, SSI_SDATA6_B, SEL_SSI6_1), - PINMUX_IPSR_MODSEL_DATA(IP8_5_3, HSCIF0_HRX, SEL_HSCIF0_0), + PINMUX_IPSR_MSEL(IP8_2_0, SSI_SDATA6_B, SEL_SSI6_1), + PINMUX_IPSR_MSEL(IP8_5_3, HSCIF0_HRX, SEL_HSCIF0_0), PINMUX_IPSR_DATA(IP8_5_3, VI0_R4), - PINMUX_IPSR_MODSEL_DATA(IP8_5_3, I2C1_SCL_C, SEL_I2C01_2), - PINMUX_IPSR_MODSEL_DATA(IP8_5_3, AUDIO_CLKA_B, SEL_ADG_1), + PINMUX_IPSR_MSEL(IP8_5_3, I2C1_SCL_C, SEL_I2C01_2), + PINMUX_IPSR_MSEL(IP8_5_3, AUDIO_CLKA_B, SEL_ADG_1), PINMUX_IPSR_DATA(IP8_5_3, AVB_MDIO), - PINMUX_IPSR_MODSEL_DATA(IP8_5_3, SSI_SCK78_B, SEL_SSI7_1), - PINMUX_IPSR_MODSEL_DATA(IP8_8_6, HSCIF0_HTX, SEL_HSCIF0_0), + PINMUX_IPSR_MSEL(IP8_5_3, SSI_SCK78_B, SEL_SSI7_1), + PINMUX_IPSR_MSEL(IP8_8_6, HSCIF0_HTX, SEL_HSCIF0_0), PINMUX_IPSR_DATA(IP8_8_6, VI0_R5), - PINMUX_IPSR_MODSEL_DATA(IP8_8_6, I2C1_SDA_C, SEL_I2C01_2), - PINMUX_IPSR_MODSEL_DATA(IP8_8_6, AUDIO_CLKB_B, SEL_ADG_1), + PINMUX_IPSR_MSEL(IP8_8_6, I2C1_SDA_C, SEL_I2C01_2), + PINMUX_IPSR_MSEL(IP8_8_6, AUDIO_CLKB_B, SEL_ADG_1), PINMUX_IPSR_DATA(IP8_5_3, AVB_LINK), - PINMUX_IPSR_MODSEL_DATA(IP8_8_6, SSI_WS78_B, SEL_SSI7_1), + PINMUX_IPSR_MSEL(IP8_8_6, SSI_WS78_B, SEL_SSI7_1), PINMUX_IPSR_DATA(IP8_11_9, HSCIF0_HCTS_N), PINMUX_IPSR_DATA(IP8_11_9, VI0_R6), - PINMUX_IPSR_MODSEL_DATA(IP8_11_9, SCIF0_RXD_D, SEL_SCIF0_3), - PINMUX_IPSR_MODSEL_DATA(IP8_11_9, I2C0_SCL_E, SEL_I2C00_4), + PINMUX_IPSR_MSEL(IP8_11_9, SCIF0_RXD_D, SEL_SCIF0_3), + PINMUX_IPSR_MSEL(IP8_11_9, I2C0_SCL_E, SEL_I2C00_4), PINMUX_IPSR_DATA(IP8_11_9, AVB_MAGIC), - PINMUX_IPSR_MODSEL_DATA(IP8_11_9, SSI_SDATA7_B, SEL_SSI7_1), + PINMUX_IPSR_MSEL(IP8_11_9, SSI_SDATA7_B, SEL_SSI7_1), PINMUX_IPSR_DATA(IP8_14_12, HSCIF0_HRTS_N), PINMUX_IPSR_DATA(IP8_14_12, VI0_R7), - PINMUX_IPSR_MODSEL_DATA(IP8_14_12, SCIF0_TXD_D, SEL_SCIF0_3), - PINMUX_IPSR_MODSEL_DATA(IP8_14_12, I2C0_SDA_E, SEL_I2C00_4), + PINMUX_IPSR_MSEL(IP8_14_12, SCIF0_TXD_D, SEL_SCIF0_3), + PINMUX_IPSR_MSEL(IP8_14_12, I2C0_SDA_E, SEL_I2C00_4), PINMUX_IPSR_DATA(IP8_14_12, AVB_PHY_INT), - PINMUX_IPSR_MODSEL_DATA(IP8_14_12, SSI_SDATA8_B, SEL_SSI8_1), - PINMUX_IPSR_MODSEL_DATA(IP8_16_15, HSCIF0_HSCK, SEL_HSCIF0_0), - PINMUX_IPSR_MODSEL_DATA(IP8_16_15, SCIF_CLK_B, SEL_SCIF0_1), + PINMUX_IPSR_MSEL(IP8_14_12, SSI_SDATA8_B, SEL_SSI8_1), + PINMUX_IPSR_MSEL(IP8_16_15, HSCIF0_HSCK, SEL_HSCIF0_0), + PINMUX_IPSR_MSEL(IP8_16_15, SCIF_CLK_B, SEL_SCIF0_1), PINMUX_IPSR_DATA(IP8_16_15, AVB_CRS), - PINMUX_IPSR_MODSEL_DATA(IP8_16_15, AUDIO_CLKC_B, SEL_ADG_1), - PINMUX_IPSR_MODSEL_DATA(IP8_19_17, I2C0_SCL, SEL_I2C00_0), - PINMUX_IPSR_MODSEL_DATA(IP8_19_17, SCIF0_RXD_C, SEL_SCIF0_2), + PINMUX_IPSR_MSEL(IP8_16_15, AUDIO_CLKC_B, SEL_ADG_1), + PINMUX_IPSR_MSEL(IP8_19_17, I2C0_SCL, SEL_I2C00_0), + PINMUX_IPSR_MSEL(IP8_19_17, SCIF0_RXD_C, SEL_SCIF0_2), PINMUX_IPSR_DATA(IP8_19_17, PWM5), - PINMUX_IPSR_MODSEL_DATA(IP8_19_17, TCLK1_B, SEL_TMU_1), + PINMUX_IPSR_MSEL(IP8_19_17, TCLK1_B, SEL_TMU_1), PINMUX_IPSR_DATA(IP8_19_17, AVB_GTXREFCLK), - PINMUX_IPSR_MODSEL_DATA(IP8_19_17, CAN1_RX_D, SEL_CAN1_3), + PINMUX_IPSR_MSEL(IP8_19_17, CAN1_RX_D, SEL_CAN1_3), PINMUX_IPSR_DATA(IP8_19_17, TPUTO0_B), - PINMUX_IPSR_MODSEL_DATA(IP8_22_20, I2C0_SDA, SEL_I2C00_0), - PINMUX_IPSR_MODSEL_DATA(IP8_22_20, SCIF0_TXD_C, SEL_SCIF0_2), + PINMUX_IPSR_MSEL(IP8_22_20, I2C0_SDA, SEL_I2C00_0), + PINMUX_IPSR_MSEL(IP8_22_20, SCIF0_TXD_C, SEL_SCIF0_2), PINMUX_IPSR_DATA(IP8_22_20, TPUTO0), - PINMUX_IPSR_MODSEL_DATA(IP8_22_20, CAN_CLK, SEL_CAN_0), + PINMUX_IPSR_MSEL(IP8_22_20, CAN_CLK, SEL_CAN_0), PINMUX_IPSR_DATA(IP8_22_20, DVC_MUTE), - PINMUX_IPSR_MODSEL_DATA(IP8_22_20, CAN1_TX_D, SEL_CAN1_3), - PINMUX_IPSR_MODSEL_DATA(IP8_25_23, I2C1_SCL, SEL_I2C01_0), - PINMUX_IPSR_MODSEL_DATA(IP8_25_23, SCIF4_RXD, SEL_SCIF4_0), + PINMUX_IPSR_MSEL(IP8_22_20, CAN1_TX_D, SEL_CAN1_3), + PINMUX_IPSR_MSEL(IP8_25_23, I2C1_SCL, SEL_I2C01_0), + PINMUX_IPSR_MSEL(IP8_25_23, SCIF4_RXD, SEL_SCIF4_0), PINMUX_IPSR_DATA(IP8_25_23, PWM5_B), PINMUX_IPSR_DATA(IP8_25_23, DU1_DR0), - PINMUX_IPSR_MODSEL_DATA(IP8_25_23, RIF1_SYNC_B, SEL_DR2_1), - PINMUX_IPSR_MODSEL_DATA(IP8_25_23, TS_SDATA_D, SEL_TSIF0_3), + PINMUX_IPSR_MSEL(IP8_25_23, RIF1_SYNC_B, SEL_DR2_1), + PINMUX_IPSR_MSEL(IP8_25_23, TS_SDATA_D, SEL_TSIF0_3), PINMUX_IPSR_DATA(IP8_25_23, TPUTO1_B), - PINMUX_IPSR_MODSEL_DATA(IP8_28_26, I2C1_SDA, SEL_I2C01_0), - PINMUX_IPSR_MODSEL_DATA(IP8_28_26, SCIF4_TXD, SEL_SCIF4_0), + PINMUX_IPSR_MSEL(IP8_28_26, I2C1_SDA, SEL_I2C01_0), + PINMUX_IPSR_MSEL(IP8_28_26, SCIF4_TXD, SEL_SCIF4_0), PINMUX_IPSR_DATA(IP8_28_26, IRQ5), PINMUX_IPSR_DATA(IP8_28_26, DU1_DR1), - PINMUX_IPSR_MODSEL_DATA(IP8_28_26, RIF1_CLK_B, SEL_DR2_1), - PINMUX_IPSR_MODSEL_DATA(IP8_28_26, TS_SCK_D, SEL_TSIF0_3), - PINMUX_IPSR_MODSEL_DATA(IP8_28_26, BPFCLK_C, SEL_DARC_2), + PINMUX_IPSR_MSEL(IP8_28_26, RIF1_CLK_B, SEL_DR2_1), + PINMUX_IPSR_MSEL(IP8_28_26, TS_SCK_D, SEL_TSIF0_3), + PINMUX_IPSR_MSEL(IP8_28_26, BPFCLK_C, SEL_DARC_2), PINMUX_IPSR_DATA(IP8_31_29, MSIOF0_RXD), - PINMUX_IPSR_MODSEL_DATA(IP8_31_29, SCIF5_RXD, SEL_SCIF5_0), - PINMUX_IPSR_MODSEL_DATA(IP8_31_29, I2C2_SCL_C, SEL_I2C02_2), + PINMUX_IPSR_MSEL(IP8_31_29, SCIF5_RXD, SEL_SCIF5_0), + PINMUX_IPSR_MSEL(IP8_31_29, I2C2_SCL_C, SEL_I2C02_2), PINMUX_IPSR_DATA(IP8_31_29, DU1_DR2), - PINMUX_IPSR_MODSEL_DATA(IP8_31_29, RIF1_D0_B, SEL_DR2_1), - PINMUX_IPSR_MODSEL_DATA(IP8_31_29, TS_SDEN_D, SEL_TSIF0_3), - PINMUX_IPSR_MODSEL_DATA(IP8_31_29, FMCLK_C, SEL_DARC_2), - PINMUX_IPSR_MODSEL_DATA(IP8_31_29, RDS_CLK, SEL_RDS_0), + PINMUX_IPSR_MSEL(IP8_31_29, RIF1_D0_B, SEL_DR2_1), + PINMUX_IPSR_MSEL(IP8_31_29, TS_SDEN_D, SEL_TSIF0_3), + PINMUX_IPSR_MSEL(IP8_31_29, FMCLK_C, SEL_DARC_2), + PINMUX_IPSR_MSEL(IP8_31_29, RDS_CLK, SEL_RDS_0), /* IPSR9 */ PINMUX_IPSR_DATA(IP9_2_0, MSIOF0_TXD), - PINMUX_IPSR_MODSEL_DATA(IP9_2_0, SCIF5_TXD, SEL_SCIF5_0), - PINMUX_IPSR_MODSEL_DATA(IP9_2_0, I2C2_SDA_C, SEL_I2C02_2), + PINMUX_IPSR_MSEL(IP9_2_0, SCIF5_TXD, SEL_SCIF5_0), + PINMUX_IPSR_MSEL(IP9_2_0, I2C2_SDA_C, SEL_I2C02_2), PINMUX_IPSR_DATA(IP9_2_0, DU1_DR3), - PINMUX_IPSR_MODSEL_DATA(IP9_2_0, RIF1_D1_B, SEL_DR3_1), - PINMUX_IPSR_MODSEL_DATA(IP9_2_0, TS_SPSYNC_D, SEL_TSIF0_3), - PINMUX_IPSR_MODSEL_DATA(IP9_2_0, FMIN_C, SEL_DARC_2), - PINMUX_IPSR_MODSEL_DATA(IP9_2_0, RDS_DATA, SEL_RDS_0), + PINMUX_IPSR_MSEL(IP9_2_0, RIF1_D1_B, SEL_DR3_1), + PINMUX_IPSR_MSEL(IP9_2_0, TS_SPSYNC_D, SEL_TSIF0_3), + PINMUX_IPSR_MSEL(IP9_2_0, FMIN_C, SEL_DARC_2), + PINMUX_IPSR_MSEL(IP9_2_0, RDS_DATA, SEL_RDS_0), PINMUX_IPSR_DATA(IP9_5_3, MSIOF0_SCK), PINMUX_IPSR_DATA(IP9_5_3, IRQ0), - PINMUX_IPSR_MODSEL_DATA(IP9_5_3, TS_SDATA, SEL_TSIF0_0), + PINMUX_IPSR_MSEL(IP9_5_3, TS_SDATA, SEL_TSIF0_0), PINMUX_IPSR_DATA(IP9_5_3, DU1_DR4), - PINMUX_IPSR_MODSEL_DATA(IP9_5_3, RIF1_SYNC, SEL_DR2_0), + PINMUX_IPSR_MSEL(IP9_5_3, RIF1_SYNC, SEL_DR2_0), PINMUX_IPSR_DATA(IP9_5_3, TPUTO1_C), PINMUX_IPSR_DATA(IP9_8_6, MSIOF0_SYNC), PINMUX_IPSR_DATA(IP9_8_6, PWM1), - PINMUX_IPSR_MODSEL_DATA(IP9_8_6, TS_SCK, SEL_TSIF0_0), + PINMUX_IPSR_MSEL(IP9_8_6, TS_SCK, SEL_TSIF0_0), PINMUX_IPSR_DATA(IP9_8_6, DU1_DR5), - PINMUX_IPSR_MODSEL_DATA(IP9_8_6, RIF1_CLK, SEL_DR2_0), - PINMUX_IPSR_MODSEL_DATA(IP9_8_6, BPFCLK_B, SEL_DARC_1), + PINMUX_IPSR_MSEL(IP9_8_6, RIF1_CLK, SEL_DR2_0), + PINMUX_IPSR_MSEL(IP9_8_6, BPFCLK_B, SEL_DARC_1), PINMUX_IPSR_DATA(IP9_11_9, MSIOF0_SS1), - PINMUX_IPSR_MODSEL_DATA(IP9_11_9, SCIFA0_RXD, SEL_SCIFA0_0), - PINMUX_IPSR_MODSEL_DATA(IP9_11_9, TS_SDEN, SEL_TSIF0_0), + PINMUX_IPSR_MSEL(IP9_11_9, SCIFA0_RXD, SEL_SCIFA0_0), + PINMUX_IPSR_MSEL(IP9_11_9, TS_SDEN, SEL_TSIF0_0), PINMUX_IPSR_DATA(IP9_11_9, DU1_DR6), - PINMUX_IPSR_MODSEL_DATA(IP9_11_9, RIF1_D0, SEL_DR2_0), - PINMUX_IPSR_MODSEL_DATA(IP9_11_9, FMCLK_B, SEL_DARC_1), - PINMUX_IPSR_MODSEL_DATA(IP9_11_9, RDS_CLK_B, SEL_RDS_1), + PINMUX_IPSR_MSEL(IP9_11_9, RIF1_D0, SEL_DR2_0), + PINMUX_IPSR_MSEL(IP9_11_9, FMCLK_B, SEL_DARC_1), + PINMUX_IPSR_MSEL(IP9_11_9, RDS_CLK_B, SEL_RDS_1), PINMUX_IPSR_DATA(IP9_14_12, MSIOF0_SS2), - PINMUX_IPSR_MODSEL_DATA(IP9_14_12, SCIFA0_TXD, SEL_SCIFA0_0), - PINMUX_IPSR_MODSEL_DATA(IP9_14_12, TS_SPSYNC, SEL_TSIF0_0), + PINMUX_IPSR_MSEL(IP9_14_12, SCIFA0_TXD, SEL_SCIFA0_0), + PINMUX_IPSR_MSEL(IP9_14_12, TS_SPSYNC, SEL_TSIF0_0), PINMUX_IPSR_DATA(IP9_14_12, DU1_DR7), - PINMUX_IPSR_MODSEL_DATA(IP9_14_12, RIF1_D1, SEL_DR3_0), - PINMUX_IPSR_MODSEL_DATA(IP9_14_12, FMIN_B, SEL_DARC_1), - PINMUX_IPSR_MODSEL_DATA(IP9_14_12, RDS_DATA_B, SEL_RDS_1), - PINMUX_IPSR_MODSEL_DATA(IP9_16_15, HSCIF1_HRX, SEL_HSCIF1_0), - PINMUX_IPSR_MODSEL_DATA(IP9_16_15, I2C4_SCL, SEL_I2C04_0), + PINMUX_IPSR_MSEL(IP9_14_12, RIF1_D1, SEL_DR3_0), + PINMUX_IPSR_MSEL(IP9_14_12, FMIN_B, SEL_DARC_1), + PINMUX_IPSR_MSEL(IP9_14_12, RDS_DATA_B, SEL_RDS_1), + PINMUX_IPSR_MSEL(IP9_16_15, HSCIF1_HRX, SEL_HSCIF1_0), + PINMUX_IPSR_MSEL(IP9_16_15, I2C4_SCL, SEL_I2C04_0), PINMUX_IPSR_DATA(IP9_16_15, PWM6), PINMUX_IPSR_DATA(IP9_16_15, DU1_DG0), - PINMUX_IPSR_MODSEL_DATA(IP9_18_17, HSCIF1_HTX, SEL_HSCIF1_0), - PINMUX_IPSR_MODSEL_DATA(IP9_18_17, I2C4_SDA, SEL_I2C04_0), + PINMUX_IPSR_MSEL(IP9_18_17, HSCIF1_HTX, SEL_HSCIF1_0), + PINMUX_IPSR_MSEL(IP9_18_17, I2C4_SDA, SEL_I2C04_0), PINMUX_IPSR_DATA(IP9_18_17, TPUTO1), PINMUX_IPSR_DATA(IP9_18_17, DU1_DG1), PINMUX_IPSR_DATA(IP9_21_19, HSCIF1_HSCK), PINMUX_IPSR_DATA(IP9_21_19, PWM2), - PINMUX_IPSR_MODSEL_DATA(IP9_21_19, IETX, SEL_IEB_0), + PINMUX_IPSR_MSEL(IP9_21_19, IETX, SEL_IEB_0), PINMUX_IPSR_DATA(IP9_21_19, DU1_DG2), - PINMUX_IPSR_MODSEL_DATA(IP9_21_19, REMOCON_B, SEL_RCN_1), - PINMUX_IPSR_MODSEL_DATA(IP9_21_19, SPEEDIN_B, SEL_RSP_1), - PINMUX_IPSR_MODSEL_DATA(IP9_21_19, VSP_B, SEL_SPDM_1), - PINMUX_IPSR_MODSEL_DATA(IP9_24_22, HSCIF1_HCTS_N, SEL_HSCIF1_0), - PINMUX_IPSR_MODSEL_DATA(IP9_24_22, SCIFA4_RXD, SEL_SCIFA4_0), - PINMUX_IPSR_MODSEL_DATA(IP9_24_22, IECLK, SEL_IEB_0), + PINMUX_IPSR_MSEL(IP9_21_19, REMOCON_B, SEL_RCN_1), + PINMUX_IPSR_MSEL(IP9_21_19, SPEEDIN_B, SEL_RSP_1), + PINMUX_IPSR_MSEL(IP9_21_19, VSP_B, SEL_SPDM_1), + PINMUX_IPSR_MSEL(IP9_24_22, HSCIF1_HCTS_N, SEL_HSCIF1_0), + PINMUX_IPSR_MSEL(IP9_24_22, SCIFA4_RXD, SEL_SCIFA4_0), + PINMUX_IPSR_MSEL(IP9_24_22, IECLK, SEL_IEB_0), PINMUX_IPSR_DATA(IP9_24_22, DU1_DG3), - PINMUX_IPSR_MODSEL_DATA(IP9_24_22, SSI_SCK1_B, SEL_SSI1_1), + PINMUX_IPSR_MSEL(IP9_24_22, SSI_SCK1_B, SEL_SSI1_1), PINMUX_IPSR_DATA(IP9_24_22, CAN_DEBUG_HW_TRIGGER), PINMUX_IPSR_DATA(IP9_24_22, CC50_STATE32), - PINMUX_IPSR_MODSEL_DATA(IP9_27_25, HSCIF1_HRTS_N, SEL_HSCIF1_0), - PINMUX_IPSR_MODSEL_DATA(IP9_27_25, SCIFA4_TXD, SEL_SCIFA4_0), - PINMUX_IPSR_MODSEL_DATA(IP9_27_25, IERX, SEL_IEB_0), + PINMUX_IPSR_MSEL(IP9_27_25, HSCIF1_HRTS_N, SEL_HSCIF1_0), + PINMUX_IPSR_MSEL(IP9_27_25, SCIFA4_TXD, SEL_SCIFA4_0), + PINMUX_IPSR_MSEL(IP9_27_25, IERX, SEL_IEB_0), PINMUX_IPSR_DATA(IP9_27_25, DU1_DG4), - PINMUX_IPSR_MODSEL_DATA(IP9_27_25, SSI_WS1_B, SEL_SSI1_1), + PINMUX_IPSR_MSEL(IP9_27_25, SSI_WS1_B, SEL_SSI1_1), PINMUX_IPSR_DATA(IP9_27_25, CAN_STEP0), PINMUX_IPSR_DATA(IP9_27_25, CC50_STATE33), - PINMUX_IPSR_MODSEL_DATA(IP9_30_28, SCIF1_SCK, SEL_SCIF1_0), + PINMUX_IPSR_MSEL(IP9_30_28, SCIF1_SCK, SEL_SCIF1_0), PINMUX_IPSR_DATA(IP9_30_28, PWM3), - PINMUX_IPSR_MODSEL_DATA(IP9_30_28, TCLK2, SEL_TMU_0), + PINMUX_IPSR_MSEL(IP9_30_28, TCLK2, SEL_TMU_0), PINMUX_IPSR_DATA(IP9_30_28, DU1_DG5), - PINMUX_IPSR_MODSEL_DATA(IP9_30_28, SSI_SDATA1_B, SEL_SSI1_1), + PINMUX_IPSR_MSEL(IP9_30_28, SSI_SDATA1_B, SEL_SSI1_1), PINMUX_IPSR_DATA(IP9_30_28, CAN_TXCLK), PINMUX_IPSR_DATA(IP9_30_28, CC50_STATE34), /* IPSR10 */ - PINMUX_IPSR_MODSEL_DATA(IP10_2_0, SCIF1_RXD, SEL_SCIF1_0), - PINMUX_IPSR_MODSEL_DATA(IP10_2_0, IIC0_SCL, SEL_IIC00_0), + PINMUX_IPSR_MSEL(IP10_2_0, SCIF1_RXD, SEL_SCIF1_0), + PINMUX_IPSR_MSEL(IP10_2_0, IIC0_SCL, SEL_IIC00_0), PINMUX_IPSR_DATA(IP10_2_0, DU1_DG6), - PINMUX_IPSR_MODSEL_DATA(IP10_2_0, SSI_SCK2_B, SEL_SSI2_1), + PINMUX_IPSR_MSEL(IP10_2_0, SSI_SCK2_B, SEL_SSI2_1), PINMUX_IPSR_DATA(IP10_2_0, CAN_DEBUGOUT0), PINMUX_IPSR_DATA(IP10_2_0, CC50_STATE35), - PINMUX_IPSR_MODSEL_DATA(IP10_5_3, SCIF1_TXD, SEL_SCIF1_0), - PINMUX_IPSR_MODSEL_DATA(IP10_5_3, IIC0_SDA, SEL_IIC00_0), + PINMUX_IPSR_MSEL(IP10_5_3, SCIF1_TXD, SEL_SCIF1_0), + PINMUX_IPSR_MSEL(IP10_5_3, IIC0_SDA, SEL_IIC00_0), PINMUX_IPSR_DATA(IP10_5_3, DU1_DG7), - PINMUX_IPSR_MODSEL_DATA(IP10_5_3, SSI_WS2_B, SEL_SSI2_1), + PINMUX_IPSR_MSEL(IP10_5_3, SSI_WS2_B, SEL_SSI2_1), PINMUX_IPSR_DATA(IP10_5_3, CAN_DEBUGOUT1), PINMUX_IPSR_DATA(IP10_5_3, CC50_STATE36), - PINMUX_IPSR_MODSEL_DATA(IP10_8_6, SCIF2_RXD, SEL_SCIF2_0), - PINMUX_IPSR_MODSEL_DATA(IP10_8_6, IIC1_SCL, SEL_IIC01_0), + PINMUX_IPSR_MSEL(IP10_8_6, SCIF2_RXD, SEL_SCIF2_0), + PINMUX_IPSR_MSEL(IP10_8_6, IIC1_SCL, SEL_IIC01_0), PINMUX_IPSR_DATA(IP10_8_6, DU1_DB0), - PINMUX_IPSR_MODSEL_DATA(IP10_8_6, SSI_SDATA2_B, SEL_SSI2_1), + PINMUX_IPSR_MSEL(IP10_8_6, SSI_SDATA2_B, SEL_SSI2_1), PINMUX_IPSR_DATA(IP10_8_6, USB0_EXTLP), PINMUX_IPSR_DATA(IP10_8_6, CAN_DEBUGOUT2), PINMUX_IPSR_DATA(IP10_8_6, CC50_STATE37), - PINMUX_IPSR_MODSEL_DATA(IP10_11_9, SCIF2_TXD, SEL_SCIF2_0), - PINMUX_IPSR_MODSEL_DATA(IP10_11_9, IIC1_SDA, SEL_IIC01_0), + PINMUX_IPSR_MSEL(IP10_11_9, SCIF2_TXD, SEL_SCIF2_0), + PINMUX_IPSR_MSEL(IP10_11_9, IIC1_SDA, SEL_IIC01_0), PINMUX_IPSR_DATA(IP10_11_9, DU1_DB1), - PINMUX_IPSR_MODSEL_DATA(IP10_11_9, SSI_SCK9_B, SEL_SSI9_1), + PINMUX_IPSR_MSEL(IP10_11_9, SSI_SCK9_B, SEL_SSI9_1), PINMUX_IPSR_DATA(IP10_11_9, USB0_OVC1), PINMUX_IPSR_DATA(IP10_11_9, CAN_DEBUGOUT3), PINMUX_IPSR_DATA(IP10_11_9, CC50_STATE38), - PINMUX_IPSR_MODSEL_DATA(IP10_14_12, SCIF2_SCK, SEL_SCIF2_0), + PINMUX_IPSR_MSEL(IP10_14_12, SCIF2_SCK, SEL_SCIF2_0), PINMUX_IPSR_DATA(IP10_14_12, IRQ1), PINMUX_IPSR_DATA(IP10_14_12, DU1_DB2), - PINMUX_IPSR_MODSEL_DATA(IP10_14_12, SSI_WS9_B, SEL_SSI9_1), + PINMUX_IPSR_MSEL(IP10_14_12, SSI_WS9_B, SEL_SSI9_1), PINMUX_IPSR_DATA(IP10_14_12, USB0_IDIN), PINMUX_IPSR_DATA(IP10_14_12, CAN_DEBUGOUT4), PINMUX_IPSR_DATA(IP10_14_12, CC50_STATE39), - PINMUX_IPSR_MODSEL_DATA(IP10_17_15, SCIF3_SCK, SEL_SCIF3_0), + PINMUX_IPSR_MSEL(IP10_17_15, SCIF3_SCK, SEL_SCIF3_0), PINMUX_IPSR_DATA(IP10_17_15, IRQ2), - PINMUX_IPSR_MODSEL_DATA(IP10_17_15, BPFCLK_D, SEL_DARC_3), + PINMUX_IPSR_MSEL(IP10_17_15, BPFCLK_D, SEL_DARC_3), PINMUX_IPSR_DATA(IP10_17_15, DU1_DB3), - PINMUX_IPSR_MODSEL_DATA(IP10_17_15, SSI_SDATA9_B, SEL_SSI9_1), + PINMUX_IPSR_MSEL(IP10_17_15, SSI_SDATA9_B, SEL_SSI9_1), PINMUX_IPSR_DATA(IP10_17_15, TANS2), PINMUX_IPSR_DATA(IP10_17_15, CAN_DEBUGOUT5), PINMUX_IPSR_DATA(IP10_17_15, CC50_OSCOUT), - PINMUX_IPSR_MODSEL_DATA(IP10_20_18, SCIF3_RXD, SEL_SCIF3_0), - PINMUX_IPSR_MODSEL_DATA(IP10_20_18, I2C1_SCL_E, SEL_I2C01_4), - PINMUX_IPSR_MODSEL_DATA(IP10_20_18, FMCLK_D, SEL_DARC_3), + PINMUX_IPSR_MSEL(IP10_20_18, SCIF3_RXD, SEL_SCIF3_0), + PINMUX_IPSR_MSEL(IP10_20_18, I2C1_SCL_E, SEL_I2C01_4), + PINMUX_IPSR_MSEL(IP10_20_18, FMCLK_D, SEL_DARC_3), PINMUX_IPSR_DATA(IP10_20_18, DU1_DB4), - PINMUX_IPSR_MODSEL_DATA(IP10_20_18, AUDIO_CLKA_C, SEL_ADG_2), - PINMUX_IPSR_MODSEL_DATA(IP10_20_18, SSI_SCK4_B, SEL_SSI4_1), + PINMUX_IPSR_MSEL(IP10_20_18, AUDIO_CLKA_C, SEL_ADG_2), + PINMUX_IPSR_MSEL(IP10_20_18, SSI_SCK4_B, SEL_SSI4_1), PINMUX_IPSR_DATA(IP10_20_18, CAN_DEBUGOUT6), - PINMUX_IPSR_MODSEL_DATA(IP10_20_18, RDS_CLK_C, SEL_RDS_2), - PINMUX_IPSR_MODSEL_DATA(IP10_23_21, SCIF3_TXD, SEL_SCIF3_0), - PINMUX_IPSR_MODSEL_DATA(IP10_23_21, I2C1_SDA_E, SEL_I2C01_4), - PINMUX_IPSR_MODSEL_DATA(IP10_23_21, FMIN_D, SEL_DARC_3), + PINMUX_IPSR_MSEL(IP10_20_18, RDS_CLK_C, SEL_RDS_2), + PINMUX_IPSR_MSEL(IP10_23_21, SCIF3_TXD, SEL_SCIF3_0), + PINMUX_IPSR_MSEL(IP10_23_21, I2C1_SDA_E, SEL_I2C01_4), + PINMUX_IPSR_MSEL(IP10_23_21, FMIN_D, SEL_DARC_3), PINMUX_IPSR_DATA(IP10_23_21, DU1_DB5), - PINMUX_IPSR_MODSEL_DATA(IP10_23_21, AUDIO_CLKB_C, SEL_ADG_2), - PINMUX_IPSR_MODSEL_DATA(IP10_23_21, SSI_WS4_B, SEL_SSI4_1), + PINMUX_IPSR_MSEL(IP10_23_21, AUDIO_CLKB_C, SEL_ADG_2), + PINMUX_IPSR_MSEL(IP10_23_21, SSI_WS4_B, SEL_SSI4_1), PINMUX_IPSR_DATA(IP10_23_21, CAN_DEBUGOUT7), - PINMUX_IPSR_MODSEL_DATA(IP10_23_21, RDS_DATA_C, SEL_RDS_2), - PINMUX_IPSR_MODSEL_DATA(IP10_26_24, I2C2_SCL, SEL_I2C02_0), - PINMUX_IPSR_MODSEL_DATA(IP10_26_24, SCIFA5_RXD, SEL_SCIFA5_0), + PINMUX_IPSR_MSEL(IP10_23_21, RDS_DATA_C, SEL_RDS_2), + PINMUX_IPSR_MSEL(IP10_26_24, I2C2_SCL, SEL_I2C02_0), + PINMUX_IPSR_MSEL(IP10_26_24, SCIFA5_RXD, SEL_SCIFA5_0), PINMUX_IPSR_DATA(IP10_26_24, DU1_DB6), - PINMUX_IPSR_MODSEL_DATA(IP10_26_24, AUDIO_CLKC_C, SEL_ADG_2), - PINMUX_IPSR_MODSEL_DATA(IP10_26_24, SSI_SDATA4_B, SEL_SSI4_1), + PINMUX_IPSR_MSEL(IP10_26_24, AUDIO_CLKC_C, SEL_ADG_2), + PINMUX_IPSR_MSEL(IP10_26_24, SSI_SDATA4_B, SEL_SSI4_1), PINMUX_IPSR_DATA(IP10_26_24, CAN_DEBUGOUT8), - PINMUX_IPSR_MODSEL_DATA(IP10_29_27, I2C2_SDA, SEL_I2C02_0), - PINMUX_IPSR_MODSEL_DATA(IP10_29_27, SCIFA5_TXD, SEL_SCIFA5_0), + PINMUX_IPSR_MSEL(IP10_29_27, I2C2_SDA, SEL_I2C02_0), + PINMUX_IPSR_MSEL(IP10_29_27, SCIFA5_TXD, SEL_SCIFA5_0), PINMUX_IPSR_DATA(IP10_29_27, DU1_DB7), - PINMUX_IPSR_MODSEL_DATA(IP10_29_27, AUDIO_CLKOUT_C, SEL_ADG_2), + PINMUX_IPSR_MSEL(IP10_29_27, AUDIO_CLKOUT_C, SEL_ADG_2), PINMUX_IPSR_DATA(IP10_29_27, CAN_DEBUGOUT9), - PINMUX_IPSR_MODSEL_DATA(IP10_31_30, SSI_SCK5, SEL_SSI5_0), - PINMUX_IPSR_MODSEL_DATA(IP10_31_30, SCIFA3_SCK, SEL_SCIFA3_0), + PINMUX_IPSR_MSEL(IP10_31_30, SSI_SCK5, SEL_SSI5_0), + PINMUX_IPSR_MSEL(IP10_31_30, SCIFA3_SCK, SEL_SCIFA3_0), PINMUX_IPSR_DATA(IP10_31_30, DU1_DOTCLKIN), PINMUX_IPSR_DATA(IP10_31_30, CAN_DEBUGOUT10), /* IPSR11 */ - PINMUX_IPSR_MODSEL_DATA(IP11_2_0, SSI_WS5, SEL_SSI5_0), - PINMUX_IPSR_MODSEL_DATA(IP11_2_0, SCIFA3_RXD, SEL_SCIFA3_0), - PINMUX_IPSR_MODSEL_DATA(IP11_2_0, I2C3_SCL_C, SEL_I2C03_2), + PINMUX_IPSR_MSEL(IP11_2_0, SSI_WS5, SEL_SSI5_0), + PINMUX_IPSR_MSEL(IP11_2_0, SCIFA3_RXD, SEL_SCIFA3_0), + PINMUX_IPSR_MSEL(IP11_2_0, I2C3_SCL_C, SEL_I2C03_2), PINMUX_IPSR_DATA(IP11_2_0, DU1_DOTCLKOUT0), PINMUX_IPSR_DATA(IP11_2_0, CAN_DEBUGOUT11), - PINMUX_IPSR_MODSEL_DATA(IP11_5_3, SSI_SDATA5, SEL_SSI5_0), - PINMUX_IPSR_MODSEL_DATA(IP11_5_3, SCIFA3_TXD, SEL_SCIFA3_0), - PINMUX_IPSR_MODSEL_DATA(IP11_5_3, I2C3_SDA_C, SEL_I2C03_2), + PINMUX_IPSR_MSEL(IP11_5_3, SSI_SDATA5, SEL_SSI5_0), + PINMUX_IPSR_MSEL(IP11_5_3, SCIFA3_TXD, SEL_SCIFA3_0), + PINMUX_IPSR_MSEL(IP11_5_3, I2C3_SDA_C, SEL_I2C03_2), PINMUX_IPSR_DATA(IP11_5_3, DU1_DOTCLKOUT1), PINMUX_IPSR_DATA(IP11_5_3, CAN_DEBUGOUT12), - PINMUX_IPSR_MODSEL_DATA(IP11_7_6, SSI_SCK6, SEL_SSI6_0), - PINMUX_IPSR_MODSEL_DATA(IP11_7_6, SCIFA1_SCK_B, SEL_SCIFA1_1), + PINMUX_IPSR_MSEL(IP11_7_6, SSI_SCK6, SEL_SSI6_0), + PINMUX_IPSR_MSEL(IP11_7_6, SCIFA1_SCK_B, SEL_SCIFA1_1), PINMUX_IPSR_DATA(IP11_7_6, DU1_EXHSYNC_DU1_HSYNC), PINMUX_IPSR_DATA(IP11_7_6, CAN_DEBUGOUT13), - PINMUX_IPSR_MODSEL_DATA(IP11_10_8, SSI_WS6, SEL_SSI6_0), - PINMUX_IPSR_MODSEL_DATA(IP11_10_8, SCIFA1_RXD_B, SEL_SCIFA1_1), - PINMUX_IPSR_MODSEL_DATA(IP11_10_8, I2C4_SCL_C, SEL_I2C04_2), + PINMUX_IPSR_MSEL(IP11_10_8, SSI_WS6, SEL_SSI6_0), + PINMUX_IPSR_MSEL(IP11_10_8, SCIFA1_RXD_B, SEL_SCIFA1_1), + PINMUX_IPSR_MSEL(IP11_10_8, I2C4_SCL_C, SEL_I2C04_2), PINMUX_IPSR_DATA(IP11_10_8, DU1_EXVSYNC_DU1_VSYNC), PINMUX_IPSR_DATA(IP11_10_8, CAN_DEBUGOUT14), - PINMUX_IPSR_MODSEL_DATA(IP11_13_11, SSI_SDATA6, SEL_SSI6_0), - PINMUX_IPSR_MODSEL_DATA(IP11_13_11, SCIFA1_TXD_B, SEL_SCIFA1_1), - PINMUX_IPSR_MODSEL_DATA(IP11_13_11, I2C4_SDA_C, SEL_I2C04_2), + PINMUX_IPSR_MSEL(IP11_13_11, SSI_SDATA6, SEL_SSI6_0), + PINMUX_IPSR_MSEL(IP11_13_11, SCIFA1_TXD_B, SEL_SCIFA1_1), + PINMUX_IPSR_MSEL(IP11_13_11, I2C4_SDA_C, SEL_I2C04_2), PINMUX_IPSR_DATA(IP11_13_11, DU1_EXODDF_DU1_ODDF_DISP_CDE), PINMUX_IPSR_DATA(IP11_13_11, CAN_DEBUGOUT15), - PINMUX_IPSR_MODSEL_DATA(IP11_15_14, SSI_SCK78, SEL_SSI7_0), - PINMUX_IPSR_MODSEL_DATA(IP11_15_14, SCIFA2_SCK_B, SEL_SCIFA2_1), - PINMUX_IPSR_MODSEL_DATA(IP11_15_14, IIC0_SDA_C, SEL_IIC00_2), + PINMUX_IPSR_MSEL(IP11_15_14, SSI_SCK78, SEL_SSI7_0), + PINMUX_IPSR_MSEL(IP11_15_14, SCIFA2_SCK_B, SEL_SCIFA2_1), + PINMUX_IPSR_MSEL(IP11_15_14, IIC0_SDA_C, SEL_IIC00_2), PINMUX_IPSR_DATA(IP11_15_14, DU1_DISP), - PINMUX_IPSR_MODSEL_DATA(IP11_17_16, SSI_WS78, SEL_SSI7_0), - PINMUX_IPSR_MODSEL_DATA(IP11_17_16, SCIFA2_RXD_B, SEL_SCIFA2_1), - PINMUX_IPSR_MODSEL_DATA(IP11_17_16, IIC0_SCL_C, SEL_IIC00_2), + PINMUX_IPSR_MSEL(IP11_17_16, SSI_WS78, SEL_SSI7_0), + PINMUX_IPSR_MSEL(IP11_17_16, SCIFA2_RXD_B, SEL_SCIFA2_1), + PINMUX_IPSR_MSEL(IP11_17_16, IIC0_SCL_C, SEL_IIC00_2), PINMUX_IPSR_DATA(IP11_17_16, DU1_CDE), - PINMUX_IPSR_MODSEL_DATA(IP11_20_18, SSI_SDATA7, SEL_SSI7_0), - PINMUX_IPSR_MODSEL_DATA(IP11_20_18, SCIFA2_TXD_B, SEL_SCIFA2_1), + PINMUX_IPSR_MSEL(IP11_20_18, SSI_SDATA7, SEL_SSI7_0), + PINMUX_IPSR_MSEL(IP11_20_18, SCIFA2_TXD_B, SEL_SCIFA2_1), PINMUX_IPSR_DATA(IP11_20_18, IRQ8), - PINMUX_IPSR_MODSEL_DATA(IP11_20_18, AUDIO_CLKA_D, SEL_ADG_3), - PINMUX_IPSR_MODSEL_DATA(IP11_20_18, CAN_CLK_D, SEL_CAN_3), + PINMUX_IPSR_MSEL(IP11_20_18, AUDIO_CLKA_D, SEL_ADG_3), + PINMUX_IPSR_MSEL(IP11_20_18, CAN_CLK_D, SEL_CAN_3), PINMUX_IPSR_DATA(IP11_20_18, PCMOE_N), PINMUX_IPSR_DATA(IP11_23_21, SSI_SCK0129), - PINMUX_IPSR_MODSEL_DATA(IP11_23_21, MSIOF1_RXD_B, SEL_MSI1_1), - PINMUX_IPSR_MODSEL_DATA(IP11_23_21, SCIF5_RXD_D, SEL_SCIF5_3), - PINMUX_IPSR_MODSEL_DATA(IP11_23_21, ADIDATA_B, SEL_RAD_1), - PINMUX_IPSR_MODSEL_DATA(IP11_23_21, AD_DI_B, SEL_ADI_1), + PINMUX_IPSR_MSEL(IP11_23_21, MSIOF1_RXD_B, SEL_MSI1_1), + PINMUX_IPSR_MSEL(IP11_23_21, SCIF5_RXD_D, SEL_SCIF5_3), + PINMUX_IPSR_MSEL(IP11_23_21, ADIDATA_B, SEL_RAD_1), + PINMUX_IPSR_MSEL(IP11_23_21, AD_DI_B, SEL_ADI_1), PINMUX_IPSR_DATA(IP11_23_21, PCMWE_N), PINMUX_IPSR_DATA(IP11_26_24, SSI_WS0129), - PINMUX_IPSR_MODSEL_DATA(IP11_26_24, MSIOF1_TXD_B, SEL_MSI1_1), - PINMUX_IPSR_MODSEL_DATA(IP11_26_24, SCIF5_TXD_D, SEL_SCIF5_3), - PINMUX_IPSR_MODSEL_DATA(IP11_26_24, ADICS_SAMP_B, SEL_RAD_1), - PINMUX_IPSR_MODSEL_DATA(IP11_26_24, AD_DO_B, SEL_ADI_1), + PINMUX_IPSR_MSEL(IP11_26_24, MSIOF1_TXD_B, SEL_MSI1_1), + PINMUX_IPSR_MSEL(IP11_26_24, SCIF5_TXD_D, SEL_SCIF5_3), + PINMUX_IPSR_MSEL(IP11_26_24, ADICS_SAMP_B, SEL_RAD_1), + PINMUX_IPSR_MSEL(IP11_26_24, AD_DO_B, SEL_ADI_1), PINMUX_IPSR_DATA(IP11_29_27, SSI_SDATA0), - PINMUX_IPSR_MODSEL_DATA(IP11_29_27, MSIOF1_SCK_B, SEL_MSI1_1), + PINMUX_IPSR_MSEL(IP11_29_27, MSIOF1_SCK_B, SEL_MSI1_1), PINMUX_IPSR_DATA(IP11_29_27, PWM0_B), - PINMUX_IPSR_MODSEL_DATA(IP11_29_27, ADICLK_B, SEL_RAD_1), - PINMUX_IPSR_MODSEL_DATA(IP11_29_27, AD_CLK_B, SEL_ADI_1), + PINMUX_IPSR_MSEL(IP11_29_27, ADICLK_B, SEL_RAD_1), + PINMUX_IPSR_MSEL(IP11_29_27, AD_CLK_B, SEL_ADI_1), /* IPSR12 */ PINMUX_IPSR_DATA(IP12_2_0, SSI_SCK34), - PINMUX_IPSR_MODSEL_DATA(IP12_2_0, MSIOF1_SYNC_B, SEL_MSI1_1), - PINMUX_IPSR_MODSEL_DATA(IP12_2_0, SCIFA1_SCK_C, SEL_SCIFA1_2), - PINMUX_IPSR_MODSEL_DATA(IP12_2_0, ADICHS0_B, SEL_RAD_1), - PINMUX_IPSR_MODSEL_DATA(IP12_2_0, AD_NCS_N_B, SEL_ADI_1), - PINMUX_IPSR_MODSEL_DATA(IP12_2_0, DREQ1_N_B, SEL_LBS_1), + PINMUX_IPSR_MSEL(IP12_2_0, MSIOF1_SYNC_B, SEL_MSI1_1), + PINMUX_IPSR_MSEL(IP12_2_0, SCIFA1_SCK_C, SEL_SCIFA1_2), + PINMUX_IPSR_MSEL(IP12_2_0, ADICHS0_B, SEL_RAD_1), + PINMUX_IPSR_MSEL(IP12_2_0, AD_NCS_N_B, SEL_ADI_1), + PINMUX_IPSR_MSEL(IP12_2_0, DREQ1_N_B, SEL_LBS_1), PINMUX_IPSR_DATA(IP12_5_3, SSI_WS34), - PINMUX_IPSR_MODSEL_DATA(IP12_5_3, MSIOF1_SS1_B, SEL_MSI1_1), - PINMUX_IPSR_MODSEL_DATA(IP12_5_3, SCIFA1_RXD_C, SEL_SCIFA1_2), - PINMUX_IPSR_MODSEL_DATA(IP12_5_3, ADICHS1_B, SEL_RAD_1), - PINMUX_IPSR_MODSEL_DATA(IP12_5_3, CAN1_RX_C, SEL_CAN1_2), - PINMUX_IPSR_MODSEL_DATA(IP12_5_3, DACK1_B, SEL_LBS_1), + PINMUX_IPSR_MSEL(IP12_5_3, MSIOF1_SS1_B, SEL_MSI1_1), + PINMUX_IPSR_MSEL(IP12_5_3, SCIFA1_RXD_C, SEL_SCIFA1_2), + PINMUX_IPSR_MSEL(IP12_5_3, ADICHS1_B, SEL_RAD_1), + PINMUX_IPSR_MSEL(IP12_5_3, CAN1_RX_C, SEL_CAN1_2), + PINMUX_IPSR_MSEL(IP12_5_3, DACK1_B, SEL_LBS_1), PINMUX_IPSR_DATA(IP12_8_6, SSI_SDATA3), - PINMUX_IPSR_MODSEL_DATA(IP12_8_6, MSIOF1_SS2_B, SEL_MSI1_1), - PINMUX_IPSR_MODSEL_DATA(IP12_8_6, SCIFA1_TXD_C, SEL_SCIFA1_2), - PINMUX_IPSR_MODSEL_DATA(IP12_8_6, ADICHS2_B, SEL_RAD_1), - PINMUX_IPSR_MODSEL_DATA(IP12_8_6, CAN1_TX_C, SEL_CAN1_2), + PINMUX_IPSR_MSEL(IP12_8_6, MSIOF1_SS2_B, SEL_MSI1_1), + PINMUX_IPSR_MSEL(IP12_8_6, SCIFA1_TXD_C, SEL_SCIFA1_2), + PINMUX_IPSR_MSEL(IP12_8_6, ADICHS2_B, SEL_RAD_1), + PINMUX_IPSR_MSEL(IP12_8_6, CAN1_TX_C, SEL_CAN1_2), PINMUX_IPSR_DATA(IP12_8_6, DREQ2_N), - PINMUX_IPSR_MODSEL_DATA(IP12_10_9, SSI_SCK4, SEL_SSI4_0), + PINMUX_IPSR_MSEL(IP12_10_9, SSI_SCK4, SEL_SSI4_0), PINMUX_IPSR_DATA(IP12_10_9, MLB_CLK), - PINMUX_IPSR_MODSEL_DATA(IP12_10_9, IETX_B, SEL_IEB_1), + PINMUX_IPSR_MSEL(IP12_10_9, IETX_B, SEL_IEB_1), PINMUX_IPSR_DATA(IP12_10_9, IRD_TX), - PINMUX_IPSR_MODSEL_DATA(IP12_12_11, SSI_WS4, SEL_SSI4_0), + PINMUX_IPSR_MSEL(IP12_12_11, SSI_WS4, SEL_SSI4_0), PINMUX_IPSR_DATA(IP12_12_11, MLB_SIG), - PINMUX_IPSR_MODSEL_DATA(IP12_12_11, IECLK_B, SEL_IEB_1), + PINMUX_IPSR_MSEL(IP12_12_11, IECLK_B, SEL_IEB_1), PINMUX_IPSR_DATA(IP12_12_11, IRD_RX), - PINMUX_IPSR_MODSEL_DATA(IP12_14_13, SSI_SDATA4, SEL_SSI4_0), + PINMUX_IPSR_MSEL(IP12_14_13, SSI_SDATA4, SEL_SSI4_0), PINMUX_IPSR_DATA(IP12_14_13, MLB_DAT), - PINMUX_IPSR_MODSEL_DATA(IP12_14_13, IERX_B, SEL_IEB_1), + PINMUX_IPSR_MSEL(IP12_14_13, IERX_B, SEL_IEB_1), PINMUX_IPSR_DATA(IP12_14_13, IRD_SCK), - PINMUX_IPSR_MODSEL_DATA(IP12_17_15, SSI_SDATA8, SEL_SSI8_0), - PINMUX_IPSR_MODSEL_DATA(IP12_17_15, SCIF1_SCK_B, SEL_SCIF1_1), + PINMUX_IPSR_MSEL(IP12_17_15, SSI_SDATA8, SEL_SSI8_0), + PINMUX_IPSR_MSEL(IP12_17_15, SCIF1_SCK_B, SEL_SCIF1_1), PINMUX_IPSR_DATA(IP12_17_15, PWM1_B), PINMUX_IPSR_DATA(IP12_17_15, IRQ9), - PINMUX_IPSR_MODSEL_DATA(IP12_17_15, REMOCON, SEL_RCN_0), + PINMUX_IPSR_MSEL(IP12_17_15, REMOCON, SEL_RCN_0), PINMUX_IPSR_DATA(IP12_17_15, DACK2), - PINMUX_IPSR_MODSEL_DATA(IP12_17_15, ETH_MDIO_B, SEL_ETH_1), - PINMUX_IPSR_MODSEL_DATA(IP12_20_18, SSI_SCK1, SEL_SSI1_0), - PINMUX_IPSR_MODSEL_DATA(IP12_20_18, SCIF1_RXD_B, SEL_SCIF1_1), - PINMUX_IPSR_MODSEL_DATA(IP12_20_18, IIC1_SCL_C, SEL_IIC01_2), + PINMUX_IPSR_MSEL(IP12_17_15, ETH_MDIO_B, SEL_ETH_1), + PINMUX_IPSR_MSEL(IP12_20_18, SSI_SCK1, SEL_SSI1_0), + PINMUX_IPSR_MSEL(IP12_20_18, SCIF1_RXD_B, SEL_SCIF1_1), + PINMUX_IPSR_MSEL(IP12_20_18, IIC1_SCL_C, SEL_IIC01_2), PINMUX_IPSR_DATA(IP12_20_18, VI1_CLK), - PINMUX_IPSR_MODSEL_DATA(IP12_20_18, CAN0_RX_D, SEL_CAN0_3), - PINMUX_IPSR_MODSEL_DATA(IP12_20_18, AVB_AVTP_CAPTURE, SEL_AVB_0), - PINMUX_IPSR_MODSEL_DATA(IP12_20_18, ETH_CRS_DV_B, SEL_ETH_1), - PINMUX_IPSR_MODSEL_DATA(IP12_23_21, SSI_WS1, SEL_SSI1_0), - PINMUX_IPSR_MODSEL_DATA(IP12_23_21, SCIF1_TXD_B, SEL_SCIF1_1), - PINMUX_IPSR_MODSEL_DATA(IP12_23_21, IIC1_SDA_C, SEL_IIC01_2), + PINMUX_IPSR_MSEL(IP12_20_18, CAN0_RX_D, SEL_CAN0_3), + PINMUX_IPSR_MSEL(IP12_20_18, AVB_AVTP_CAPTURE, SEL_AVB_0), + PINMUX_IPSR_MSEL(IP12_20_18, ETH_CRS_DV_B, SEL_ETH_1), + PINMUX_IPSR_MSEL(IP12_23_21, SSI_WS1, SEL_SSI1_0), + PINMUX_IPSR_MSEL(IP12_23_21, SCIF1_TXD_B, SEL_SCIF1_1), + PINMUX_IPSR_MSEL(IP12_23_21, IIC1_SDA_C, SEL_IIC01_2), PINMUX_IPSR_DATA(IP12_23_21, VI1_DATA0), - PINMUX_IPSR_MODSEL_DATA(IP12_23_21, CAN0_TX_D, SEL_CAN0_3), - PINMUX_IPSR_MODSEL_DATA(IP12_23_21, AVB_AVTP_MATCH, SEL_AVB_0), - PINMUX_IPSR_MODSEL_DATA(IP12_23_21, ETH_RX_ER_B, SEL_ETH_1), - PINMUX_IPSR_MODSEL_DATA(IP12_26_24, SSI_SDATA1, SEL_SSI1_0), - PINMUX_IPSR_MODSEL_DATA(IP12_26_24, HSCIF1_HRX_B, SEL_HSCIF1_1), + PINMUX_IPSR_MSEL(IP12_23_21, CAN0_TX_D, SEL_CAN0_3), + PINMUX_IPSR_MSEL(IP12_23_21, AVB_AVTP_MATCH, SEL_AVB_0), + PINMUX_IPSR_MSEL(IP12_23_21, ETH_RX_ER_B, SEL_ETH_1), + PINMUX_IPSR_MSEL(IP12_26_24, SSI_SDATA1, SEL_SSI1_0), + PINMUX_IPSR_MSEL(IP12_26_24, HSCIF1_HRX_B, SEL_HSCIF1_1), PINMUX_IPSR_DATA(IP12_26_24, VI1_DATA1), - PINMUX_IPSR_MODSEL_DATA(IP12_26_24, SDATA, SEL_FSN_0), + PINMUX_IPSR_MSEL(IP12_26_24, SDATA, SEL_FSN_0), PINMUX_IPSR_DATA(IP12_26_24, ATAG0_N), - PINMUX_IPSR_MODSEL_DATA(IP12_26_24, ETH_RXD0_B, SEL_ETH_1), - PINMUX_IPSR_MODSEL_DATA(IP12_29_27, SSI_SCK2, SEL_SSI2_0), - PINMUX_IPSR_MODSEL_DATA(IP12_29_27, HSCIF1_HTX_B, SEL_HSCIF1_1), + PINMUX_IPSR_MSEL(IP12_26_24, ETH_RXD0_B, SEL_ETH_1), + PINMUX_IPSR_MSEL(IP12_29_27, SSI_SCK2, SEL_SSI2_0), + PINMUX_IPSR_MSEL(IP12_29_27, HSCIF1_HTX_B, SEL_HSCIF1_1), PINMUX_IPSR_DATA(IP12_29_27, VI1_DATA2), - PINMUX_IPSR_MODSEL_DATA(IP12_29_27, MDATA, SEL_FSN_0), + PINMUX_IPSR_MSEL(IP12_29_27, MDATA, SEL_FSN_0), PINMUX_IPSR_DATA(IP12_29_27, ATAWR0_N), - PINMUX_IPSR_MODSEL_DATA(IP12_29_27, ETH_RXD1_B, SEL_ETH_1), + PINMUX_IPSR_MSEL(IP12_29_27, ETH_RXD1_B, SEL_ETH_1), /* IPSR13 */ - PINMUX_IPSR_MODSEL_DATA(IP13_2_0, SSI_WS2, SEL_SSI2_0), - PINMUX_IPSR_MODSEL_DATA(IP13_2_0, HSCIF1_HCTS_N_B, SEL_HSCIF1_1), - PINMUX_IPSR_MODSEL_DATA(IP13_2_0, SCIFA0_RXD_D, SEL_SCIFA0_3), + PINMUX_IPSR_MSEL(IP13_2_0, SSI_WS2, SEL_SSI2_0), + PINMUX_IPSR_MSEL(IP13_2_0, HSCIF1_HCTS_N_B, SEL_HSCIF1_1), + PINMUX_IPSR_MSEL(IP13_2_0, SCIFA0_RXD_D, SEL_SCIFA0_3), PINMUX_IPSR_DATA(IP13_2_0, VI1_DATA3), - PINMUX_IPSR_MODSEL_DATA(IP13_2_0, SCKZ, SEL_FSN_0), + PINMUX_IPSR_MSEL(IP13_2_0, SCKZ, SEL_FSN_0), PINMUX_IPSR_DATA(IP13_2_0, ATACS00_N), - PINMUX_IPSR_MODSEL_DATA(IP13_2_0, ETH_LINK_B, SEL_ETH_1), - PINMUX_IPSR_MODSEL_DATA(IP13_5_3, SSI_SDATA2, SEL_SSI2_0), - PINMUX_IPSR_MODSEL_DATA(IP13_5_3, HSCIF1_HRTS_N_B, SEL_HSCIF1_1), - PINMUX_IPSR_MODSEL_DATA(IP13_5_3, SCIFA0_TXD_D, SEL_SCIFA0_3), + PINMUX_IPSR_MSEL(IP13_2_0, ETH_LINK_B, SEL_ETH_1), + PINMUX_IPSR_MSEL(IP13_5_3, SSI_SDATA2, SEL_SSI2_0), + PINMUX_IPSR_MSEL(IP13_5_3, HSCIF1_HRTS_N_B, SEL_HSCIF1_1), + PINMUX_IPSR_MSEL(IP13_5_3, SCIFA0_TXD_D, SEL_SCIFA0_3), PINMUX_IPSR_DATA(IP13_5_3, VI1_DATA4), - PINMUX_IPSR_MODSEL_DATA(IP13_5_3, STM_N, SEL_FSN_0), + PINMUX_IPSR_MSEL(IP13_5_3, STM_N, SEL_FSN_0), PINMUX_IPSR_DATA(IP13_5_3, ATACS10_N), - PINMUX_IPSR_MODSEL_DATA(IP13_5_3, ETH_REFCLK_B, SEL_ETH_1), - PINMUX_IPSR_MODSEL_DATA(IP13_8_6, SSI_SCK9, SEL_SSI9_0), - PINMUX_IPSR_MODSEL_DATA(IP13_8_6, SCIF2_SCK_B, SEL_SCIF2_1), + PINMUX_IPSR_MSEL(IP13_5_3, ETH_REFCLK_B, SEL_ETH_1), + PINMUX_IPSR_MSEL(IP13_8_6, SSI_SCK9, SEL_SSI9_0), + PINMUX_IPSR_MSEL(IP13_8_6, SCIF2_SCK_B, SEL_SCIF2_1), PINMUX_IPSR_DATA(IP13_8_6, PWM2_B), PINMUX_IPSR_DATA(IP13_8_6, VI1_DATA5), - PINMUX_IPSR_MODSEL_DATA(IP13_8_6, MTS_N, SEL_FSN_0), + PINMUX_IPSR_MSEL(IP13_8_6, MTS_N, SEL_FSN_0), PINMUX_IPSR_DATA(IP13_8_6, EX_WAIT1), - PINMUX_IPSR_MODSEL_DATA(IP13_8_6, ETH_TXD1_B, SEL_ETH_1), - PINMUX_IPSR_MODSEL_DATA(IP13_11_9, SSI_WS9, SEL_SSI9_0), - PINMUX_IPSR_MODSEL_DATA(IP13_11_9, SCIF2_RXD_B, SEL_SCIF2_1), - PINMUX_IPSR_MODSEL_DATA(IP13_11_9, I2C3_SCL_E, SEL_I2C03_4), + PINMUX_IPSR_MSEL(IP13_8_6, ETH_TXD1_B, SEL_ETH_1), + PINMUX_IPSR_MSEL(IP13_11_9, SSI_WS9, SEL_SSI9_0), + PINMUX_IPSR_MSEL(IP13_11_9, SCIF2_RXD_B, SEL_SCIF2_1), + PINMUX_IPSR_MSEL(IP13_11_9, I2C3_SCL_E, SEL_I2C03_4), PINMUX_IPSR_DATA(IP13_11_9, VI1_DATA6), PINMUX_IPSR_DATA(IP13_11_9, ATARD0_N), - PINMUX_IPSR_MODSEL_DATA(IP13_11_9, ETH_TX_EN_B, SEL_ETH_1), - PINMUX_IPSR_MODSEL_DATA(IP13_14_12, SSI_SDATA9, SEL_SSI9_0), - PINMUX_IPSR_MODSEL_DATA(IP13_14_12, SCIF2_TXD_B, SEL_SCIF2_1), - PINMUX_IPSR_MODSEL_DATA(IP13_14_12, I2C3_SDA_E, SEL_I2C03_4), + PINMUX_IPSR_MSEL(IP13_11_9, ETH_TX_EN_B, SEL_ETH_1), + PINMUX_IPSR_MSEL(IP13_14_12, SSI_SDATA9, SEL_SSI9_0), + PINMUX_IPSR_MSEL(IP13_14_12, SCIF2_TXD_B, SEL_SCIF2_1), + PINMUX_IPSR_MSEL(IP13_14_12, I2C3_SDA_E, SEL_I2C03_4), PINMUX_IPSR_DATA(IP13_14_12, VI1_DATA7), PINMUX_IPSR_DATA(IP13_14_12, ATADIR0_N), - PINMUX_IPSR_MODSEL_DATA(IP13_14_12, ETH_MAGIC_B, SEL_ETH_1), - PINMUX_IPSR_MODSEL_DATA(IP13_17_15, AUDIO_CLKA, SEL_ADG_0), - PINMUX_IPSR_MODSEL_DATA(IP13_17_15, I2C0_SCL_B, SEL_I2C00_1), - PINMUX_IPSR_MODSEL_DATA(IP13_17_15, SCIFA4_RXD_D, SEL_SCIFA4_3), + PINMUX_IPSR_MSEL(IP13_14_12, ETH_MAGIC_B, SEL_ETH_1), + PINMUX_IPSR_MSEL(IP13_17_15, AUDIO_CLKA, SEL_ADG_0), + PINMUX_IPSR_MSEL(IP13_17_15, I2C0_SCL_B, SEL_I2C00_1), + PINMUX_IPSR_MSEL(IP13_17_15, SCIFA4_RXD_D, SEL_SCIFA4_3), PINMUX_IPSR_DATA(IP13_17_15, VI1_CLKENB), - PINMUX_IPSR_MODSEL_DATA(IP13_17_15, TS_SDATA_C, SEL_TSIF0_2), - PINMUX_IPSR_MODSEL_DATA(IP13_17_15, RIF0_SYNC_B, SEL_DR0_1), - PINMUX_IPSR_MODSEL_DATA(IP13_17_15, ETH_TXD0_B, SEL_ETH_1), - PINMUX_IPSR_MODSEL_DATA(IP13_20_18, AUDIO_CLKB, SEL_ADG_0), - PINMUX_IPSR_MODSEL_DATA(IP13_20_18, I2C0_SDA_B, SEL_I2C00_1), - PINMUX_IPSR_MODSEL_DATA(IP13_20_18, SCIFA4_TXD_D, SEL_SCIFA4_3), + PINMUX_IPSR_MSEL(IP13_17_15, TS_SDATA_C, SEL_TSIF0_2), + PINMUX_IPSR_MSEL(IP13_17_15, RIF0_SYNC_B, SEL_DR0_1), + PINMUX_IPSR_MSEL(IP13_17_15, ETH_TXD0_B, SEL_ETH_1), + PINMUX_IPSR_MSEL(IP13_20_18, AUDIO_CLKB, SEL_ADG_0), + PINMUX_IPSR_MSEL(IP13_20_18, I2C0_SDA_B, SEL_I2C00_1), + PINMUX_IPSR_MSEL(IP13_20_18, SCIFA4_TXD_D, SEL_SCIFA4_3), PINMUX_IPSR_DATA(IP13_20_18, VI1_FIELD), - PINMUX_IPSR_MODSEL_DATA(IP13_20_18, TS_SCK_C, SEL_TSIF0_2), - PINMUX_IPSR_MODSEL_DATA(IP13_20_18, RIF0_CLK_B, SEL_DR0_1), - PINMUX_IPSR_MODSEL_DATA(IP13_20_18, BPFCLK_E, SEL_DARC_4), - PINMUX_IPSR_MODSEL_DATA(IP13_20_18, ETH_MDC_B, SEL_ETH_1), - PINMUX_IPSR_MODSEL_DATA(IP13_23_21, AUDIO_CLKC, SEL_ADG_0), - PINMUX_IPSR_MODSEL_DATA(IP13_23_21, I2C4_SCL_B, SEL_I2C04_1), - PINMUX_IPSR_MODSEL_DATA(IP13_23_21, SCIFA5_RXD_D, SEL_SCIFA5_3), + PINMUX_IPSR_MSEL(IP13_20_18, TS_SCK_C, SEL_TSIF0_2), + PINMUX_IPSR_MSEL(IP13_20_18, RIF0_CLK_B, SEL_DR0_1), + PINMUX_IPSR_MSEL(IP13_20_18, BPFCLK_E, SEL_DARC_4), + PINMUX_IPSR_MSEL(IP13_20_18, ETH_MDC_B, SEL_ETH_1), + PINMUX_IPSR_MSEL(IP13_23_21, AUDIO_CLKC, SEL_ADG_0), + PINMUX_IPSR_MSEL(IP13_23_21, I2C4_SCL_B, SEL_I2C04_1), + PINMUX_IPSR_MSEL(IP13_23_21, SCIFA5_RXD_D, SEL_SCIFA5_3), PINMUX_IPSR_DATA(IP13_23_21, VI1_HSYNC_N), - PINMUX_IPSR_MODSEL_DATA(IP13_23_21, TS_SDEN_C, SEL_TSIF0_2), - PINMUX_IPSR_MODSEL_DATA(IP13_23_21, RIF0_D0_B, SEL_DR0_1), - PINMUX_IPSR_MODSEL_DATA(IP13_23_21, FMCLK_E, SEL_DARC_4), - PINMUX_IPSR_MODSEL_DATA(IP13_23_21, RDS_CLK_D, SEL_RDS_3), - PINMUX_IPSR_MODSEL_DATA(IP13_26_24, AUDIO_CLKOUT, SEL_ADG_0), - PINMUX_IPSR_MODSEL_DATA(IP13_26_24, I2C4_SDA_B, SEL_I2C04_1), - PINMUX_IPSR_MODSEL_DATA(IP13_26_24, SCIFA5_TXD_D, SEL_SCIFA5_3), + PINMUX_IPSR_MSEL(IP13_23_21, TS_SDEN_C, SEL_TSIF0_2), + PINMUX_IPSR_MSEL(IP13_23_21, RIF0_D0_B, SEL_DR0_1), + PINMUX_IPSR_MSEL(IP13_23_21, FMCLK_E, SEL_DARC_4), + PINMUX_IPSR_MSEL(IP13_23_21, RDS_CLK_D, SEL_RDS_3), + PINMUX_IPSR_MSEL(IP13_26_24, AUDIO_CLKOUT, SEL_ADG_0), + PINMUX_IPSR_MSEL(IP13_26_24, I2C4_SDA_B, SEL_I2C04_1), + PINMUX_IPSR_MSEL(IP13_26_24, SCIFA5_TXD_D, SEL_SCIFA5_3), PINMUX_IPSR_DATA(IP13_26_24, VI1_VSYNC_N), - PINMUX_IPSR_MODSEL_DATA(IP13_26_24, TS_SPSYNC_C, SEL_TSIF0_2), - PINMUX_IPSR_MODSEL_DATA(IP13_26_24, RIF0_D1_B, SEL_DR1_1), - PINMUX_IPSR_MODSEL_DATA(IP13_26_24, FMIN_E, SEL_DARC_4), - PINMUX_IPSR_MODSEL_DATA(IP13_26_24, RDS_DATA_D, SEL_RDS_3), + PINMUX_IPSR_MSEL(IP13_26_24, TS_SPSYNC_C, SEL_TSIF0_2), + PINMUX_IPSR_MSEL(IP13_26_24, RIF0_D1_B, SEL_DR1_1), + PINMUX_IPSR_MSEL(IP13_26_24, FMIN_E, SEL_DARC_4), + PINMUX_IPSR_MSEL(IP13_26_24, RDS_DATA_D, SEL_RDS_3), }; static const struct sh_pfc_pin pinmux_pins[] = { -- cgit v0.10.2 From 13ce3c39d0c45fe32398b90422c78f7a8a2b8970 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Thu, 3 Sep 2015 02:50:16 +0000 Subject: pinctrl: sh-pfc: r8a7791: use PINMUX_IPSR_MSEL() Now, PINMUX_IPSR_MSEL() and PINMUX_IPSR_MODSEL_DATA() are same. Current PFC driver is very difficult to read, because macro names are using different length. PINMUX_IPSR_NOGP(ispr, ...) PINMUX_IPSR_DATA(ipsr, ...) PINMUX_IPSR_NOGM(ispr, ...) PINMUX_IPSR_NOFN(ipsr, ...) PINMUX_IPSR_MSEL(ipsr, ...) PINMUX_IPSR_MODSEL_DATA(ipsr, ...) It can be readable if we can use PINMUX_IPSR_MSEL() instead of PINMUX_IPSR_MODSEL_DATA() PINMUX_IPSR_NOGP(ispr, ...) PINMUX_IPSR_DATA(ipsr, ...) PINMUX_IPSR_NOGM(ispr, ...) PINMUX_IPSR_NOFN(ipsr, ...) PINMUX_IPSR_MSEL(ipsr, ...) Signed-off-by: Kuninori Morimoto Acked-by: Laurent Pinchart Acked-by: Linus Walleij Signed-off-by: Geert Uytterhoeven diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c index a79f3b5..6228419 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c @@ -824,459 +824,459 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_DATA(IP0_14, D14), PINMUX_IPSR_DATA(IP0_15, D15), PINMUX_IPSR_DATA(IP0_18_16, A0), - PINMUX_IPSR_MODSEL_DATA(IP0_18_16, ATAWR0_N_C, SEL_LBS_2), - PINMUX_IPSR_MODSEL_DATA(IP0_18_16, MSIOF0_SCK_B, SEL_SOF0_1), - PINMUX_IPSR_MODSEL_DATA(IP0_18_16, SCL0_C, SEL_IIC0_2), + PINMUX_IPSR_MSEL(IP0_18_16, ATAWR0_N_C, SEL_LBS_2), + PINMUX_IPSR_MSEL(IP0_18_16, MSIOF0_SCK_B, SEL_SOF0_1), + PINMUX_IPSR_MSEL(IP0_18_16, SCL0_C, SEL_IIC0_2), PINMUX_IPSR_DATA(IP0_18_16, PWM2_B), PINMUX_IPSR_DATA(IP0_20_19, A1), - PINMUX_IPSR_MODSEL_DATA(IP0_20_19, MSIOF0_SYNC_B, SEL_SOF0_1), + PINMUX_IPSR_MSEL(IP0_20_19, MSIOF0_SYNC_B, SEL_SOF0_1), PINMUX_IPSR_DATA(IP0_22_21, A2), - PINMUX_IPSR_MODSEL_DATA(IP0_22_21, MSIOF0_SS1_B, SEL_SOF0_1), + PINMUX_IPSR_MSEL(IP0_22_21, MSIOF0_SS1_B, SEL_SOF0_1), PINMUX_IPSR_DATA(IP0_24_23, A3), - PINMUX_IPSR_MODSEL_DATA(IP0_24_23, MSIOF0_SS2_B, SEL_SOF0_1), + PINMUX_IPSR_MSEL(IP0_24_23, MSIOF0_SS2_B, SEL_SOF0_1), PINMUX_IPSR_DATA(IP0_26_25, A4), - PINMUX_IPSR_MODSEL_DATA(IP0_26_25, MSIOF0_TXD_B, SEL_SOF0_1), + PINMUX_IPSR_MSEL(IP0_26_25, MSIOF0_TXD_B, SEL_SOF0_1), PINMUX_IPSR_DATA(IP0_28_27, A5), - PINMUX_IPSR_MODSEL_DATA(IP0_28_27, MSIOF0_RXD_B, SEL_SOF0_1), + PINMUX_IPSR_MSEL(IP0_28_27, MSIOF0_RXD_B, SEL_SOF0_1), PINMUX_IPSR_DATA(IP0_30_29, A6), - PINMUX_IPSR_MODSEL_DATA(IP0_30_29, MSIOF1_SCK, SEL_SOF1_0), + PINMUX_IPSR_MSEL(IP0_30_29, MSIOF1_SCK, SEL_SOF1_0), /* IPSR1 */ PINMUX_IPSR_DATA(IP1_1_0, A7), - PINMUX_IPSR_MODSEL_DATA(IP1_1_0, MSIOF1_SYNC, SEL_SOF1_0), + PINMUX_IPSR_MSEL(IP1_1_0, MSIOF1_SYNC, SEL_SOF1_0), PINMUX_IPSR_DATA(IP1_3_2, A8), - PINMUX_IPSR_MODSEL_DATA(IP1_3_2, MSIOF1_SS1, SEL_SOF1_0), - PINMUX_IPSR_MODSEL_DATA(IP1_3_2, SCL0, SEL_IIC0_0), + PINMUX_IPSR_MSEL(IP1_3_2, MSIOF1_SS1, SEL_SOF1_0), + PINMUX_IPSR_MSEL(IP1_3_2, SCL0, SEL_IIC0_0), PINMUX_IPSR_DATA(IP1_5_4, A9), - PINMUX_IPSR_MODSEL_DATA(IP1_5_4, MSIOF1_SS2, SEL_SOF1_0), - PINMUX_IPSR_MODSEL_DATA(IP1_5_4, SDA0, SEL_IIC0_0), + PINMUX_IPSR_MSEL(IP1_5_4, MSIOF1_SS2, SEL_SOF1_0), + PINMUX_IPSR_MSEL(IP1_5_4, SDA0, SEL_IIC0_0), PINMUX_IPSR_DATA(IP1_7_6, A10), - PINMUX_IPSR_MODSEL_DATA(IP1_7_6, MSIOF1_TXD, SEL_SOF1_0), - PINMUX_IPSR_MODSEL_DATA(IP1_7_6, MSIOF1_TXD_D, SEL_SOF1_3), + PINMUX_IPSR_MSEL(IP1_7_6, MSIOF1_TXD, SEL_SOF1_0), + PINMUX_IPSR_MSEL(IP1_7_6, MSIOF1_TXD_D, SEL_SOF1_3), PINMUX_IPSR_DATA(IP1_10_8, A11), - PINMUX_IPSR_MODSEL_DATA(IP1_10_8, MSIOF1_RXD, SEL_SOF1_0), - PINMUX_IPSR_MODSEL_DATA(IP1_10_8, SCL3_D, SEL_IIC3_3), - PINMUX_IPSR_MODSEL_DATA(IP1_10_8, MSIOF1_RXD_D, SEL_SOF1_3), + PINMUX_IPSR_MSEL(IP1_10_8, MSIOF1_RXD, SEL_SOF1_0), + PINMUX_IPSR_MSEL(IP1_10_8, SCL3_D, SEL_IIC3_3), + PINMUX_IPSR_MSEL(IP1_10_8, MSIOF1_RXD_D, SEL_SOF1_3), PINMUX_IPSR_DATA(IP1_13_11, A12), - PINMUX_IPSR_MODSEL_DATA(IP1_13_11, FMCLK, SEL_FM_0), - PINMUX_IPSR_MODSEL_DATA(IP1_13_11, SDA3_D, SEL_IIC3_3), - PINMUX_IPSR_MODSEL_DATA(IP1_13_11, MSIOF1_SCK_D, SEL_SOF1_3), + PINMUX_IPSR_MSEL(IP1_13_11, FMCLK, SEL_FM_0), + PINMUX_IPSR_MSEL(IP1_13_11, SDA3_D, SEL_IIC3_3), + PINMUX_IPSR_MSEL(IP1_13_11, MSIOF1_SCK_D, SEL_SOF1_3), PINMUX_IPSR_DATA(IP1_16_14, A13), - PINMUX_IPSR_MODSEL_DATA(IP1_16_14, ATAG0_N_C, SEL_LBS_2), - PINMUX_IPSR_MODSEL_DATA(IP1_16_14, BPFCLK, SEL_FM_0), - PINMUX_IPSR_MODSEL_DATA(IP1_16_14, MSIOF1_SS1_D, SEL_SOF1_3), + PINMUX_IPSR_MSEL(IP1_16_14, ATAG0_N_C, SEL_LBS_2), + PINMUX_IPSR_MSEL(IP1_16_14, BPFCLK, SEL_FM_0), + PINMUX_IPSR_MSEL(IP1_16_14, MSIOF1_SS1_D, SEL_SOF1_3), PINMUX_IPSR_DATA(IP1_19_17, A14), - PINMUX_IPSR_MODSEL_DATA(IP1_19_17, ATADIR0_N_C, SEL_LBS_2), - PINMUX_IPSR_MODSEL_DATA(IP1_19_17, FMIN, SEL_FM_0), - PINMUX_IPSR_MODSEL_DATA(IP1_19_17, FMIN_C, SEL_FM_2), - PINMUX_IPSR_MODSEL_DATA(IP1_19_17, MSIOF1_SYNC_D, SEL_SOF1_3), + PINMUX_IPSR_MSEL(IP1_19_17, ATADIR0_N_C, SEL_LBS_2), + PINMUX_IPSR_MSEL(IP1_19_17, FMIN, SEL_FM_0), + PINMUX_IPSR_MSEL(IP1_19_17, FMIN_C, SEL_FM_2), + PINMUX_IPSR_MSEL(IP1_19_17, MSIOF1_SYNC_D, SEL_SOF1_3), PINMUX_IPSR_DATA(IP1_22_20, A15), - PINMUX_IPSR_MODSEL_DATA(IP1_22_20, BPFCLK_C, SEL_FM_2), + PINMUX_IPSR_MSEL(IP1_22_20, BPFCLK_C, SEL_FM_2), PINMUX_IPSR_DATA(IP1_25_23, A16), - PINMUX_IPSR_MODSEL_DATA(IP1_25_23, DREQ2_B, SEL_LBS_1), - PINMUX_IPSR_MODSEL_DATA(IP1_25_23, FMCLK_C, SEL_FM_2), - PINMUX_IPSR_MODSEL_DATA(IP1_25_23, SCIFA1_SCK_B, SEL_SCIFA1_1), + PINMUX_IPSR_MSEL(IP1_25_23, DREQ2_B, SEL_LBS_1), + PINMUX_IPSR_MSEL(IP1_25_23, FMCLK_C, SEL_FM_2), + PINMUX_IPSR_MSEL(IP1_25_23, SCIFA1_SCK_B, SEL_SCIFA1_1), PINMUX_IPSR_DATA(IP1_28_26, A17), - PINMUX_IPSR_MODSEL_DATA(IP1_28_26, DACK2_B, SEL_LBS_1), - PINMUX_IPSR_MODSEL_DATA(IP1_28_26, SDA0_C, SEL_IIC0_2), + PINMUX_IPSR_MSEL(IP1_28_26, DACK2_B, SEL_LBS_1), + PINMUX_IPSR_MSEL(IP1_28_26, SDA0_C, SEL_IIC0_2), PINMUX_IPSR_DATA(IP1_31_29, A18), - PINMUX_IPSR_MODSEL_DATA(IP1_31_29, DREQ1, SEL_LBS_0), - PINMUX_IPSR_MODSEL_DATA(IP1_31_29, SCIFA1_RXD_C, SEL_SCIFA1_2), - PINMUX_IPSR_MODSEL_DATA(IP1_31_29, SCIFB1_RXD_C, SEL_SCIFB1_2), + PINMUX_IPSR_MSEL(IP1_31_29, DREQ1, SEL_LBS_0), + PINMUX_IPSR_MSEL(IP1_31_29, SCIFA1_RXD_C, SEL_SCIFA1_2), + PINMUX_IPSR_MSEL(IP1_31_29, SCIFB1_RXD_C, SEL_SCIFB1_2), /* IPSR2 */ PINMUX_IPSR_DATA(IP2_2_0, A19), PINMUX_IPSR_DATA(IP2_2_0, DACK1), - PINMUX_IPSR_MODSEL_DATA(IP2_2_0, SCIFA1_TXD_C, SEL_SCIFA1_2), - PINMUX_IPSR_MODSEL_DATA(IP2_2_0, SCIFB1_TXD_C, SEL_SCIFB1_2), - PINMUX_IPSR_MODSEL_DATA(IP2_2_0, SCIFB1_SCK_B, SEL_SCIFB1_1), + PINMUX_IPSR_MSEL(IP2_2_0, SCIFA1_TXD_C, SEL_SCIFA1_2), + PINMUX_IPSR_MSEL(IP2_2_0, SCIFB1_TXD_C, SEL_SCIFB1_2), + PINMUX_IPSR_MSEL(IP2_2_0, SCIFB1_SCK_B, SEL_SCIFB1_1), PINMUX_IPSR_DATA(IP2_2_0, A20), - PINMUX_IPSR_MODSEL_DATA(IP2_4_3, SPCLK, SEL_QSP_0), + PINMUX_IPSR_MSEL(IP2_4_3, SPCLK, SEL_QSP_0), PINMUX_IPSR_DATA(IP2_6_5, A21), - PINMUX_IPSR_MODSEL_DATA(IP2_6_5, ATAWR0_N_B, SEL_LBS_1), - PINMUX_IPSR_MODSEL_DATA(IP2_6_5, MOSI_IO0, SEL_QSP_0), + PINMUX_IPSR_MSEL(IP2_6_5, ATAWR0_N_B, SEL_LBS_1), + PINMUX_IPSR_MSEL(IP2_6_5, MOSI_IO0, SEL_QSP_0), PINMUX_IPSR_DATA(IP2_9_7, A22), - PINMUX_IPSR_MODSEL_DATA(IP2_9_7, MISO_IO1, SEL_QSP_0), - PINMUX_IPSR_MODSEL_DATA(IP2_9_7, FMCLK_B, SEL_FM_1), - PINMUX_IPSR_MODSEL_DATA(IP2_9_7, TX0, SEL_SCIF0_0), - PINMUX_IPSR_MODSEL_DATA(IP2_9_7, SCIFA0_TXD, SEL_SCFA_0), + PINMUX_IPSR_MSEL(IP2_9_7, MISO_IO1, SEL_QSP_0), + PINMUX_IPSR_MSEL(IP2_9_7, FMCLK_B, SEL_FM_1), + PINMUX_IPSR_MSEL(IP2_9_7, TX0, SEL_SCIF0_0), + PINMUX_IPSR_MSEL(IP2_9_7, SCIFA0_TXD, SEL_SCFA_0), PINMUX_IPSR_DATA(IP2_12_10, A23), - PINMUX_IPSR_MODSEL_DATA(IP2_12_10, IO2, SEL_QSP_0), - PINMUX_IPSR_MODSEL_DATA(IP2_12_10, BPFCLK_B, SEL_FM_1), - PINMUX_IPSR_MODSEL_DATA(IP2_12_10, RX0, SEL_SCIF0_0), - PINMUX_IPSR_MODSEL_DATA(IP2_12_10, SCIFA0_RXD, SEL_SCFA_0), + PINMUX_IPSR_MSEL(IP2_12_10, IO2, SEL_QSP_0), + PINMUX_IPSR_MSEL(IP2_12_10, BPFCLK_B, SEL_FM_1), + PINMUX_IPSR_MSEL(IP2_12_10, RX0, SEL_SCIF0_0), + PINMUX_IPSR_MSEL(IP2_12_10, SCIFA0_RXD, SEL_SCFA_0), PINMUX_IPSR_DATA(IP2_15_13, A24), - PINMUX_IPSR_MODSEL_DATA(IP2_15_13, DREQ2, SEL_LBS_0), - PINMUX_IPSR_MODSEL_DATA(IP2_15_13, IO3, SEL_QSP_0), - PINMUX_IPSR_MODSEL_DATA(IP2_15_13, TX1, SEL_SCIF1_0), - PINMUX_IPSR_MODSEL_DATA(IP2_15_13, SCIFA1_TXD, SEL_SCIFA1_0), + PINMUX_IPSR_MSEL(IP2_15_13, DREQ2, SEL_LBS_0), + PINMUX_IPSR_MSEL(IP2_15_13, IO3, SEL_QSP_0), + PINMUX_IPSR_MSEL(IP2_15_13, TX1, SEL_SCIF1_0), + PINMUX_IPSR_MSEL(IP2_15_13, SCIFA1_TXD, SEL_SCIFA1_0), PINMUX_IPSR_DATA(IP2_18_16, A25), - PINMUX_IPSR_MODSEL_DATA(IP2_18_16, DACK2, SEL_LBS_0), - PINMUX_IPSR_MODSEL_DATA(IP2_18_16, SSL, SEL_QSP_0), - PINMUX_IPSR_MODSEL_DATA(IP2_18_16, DREQ1_C, SEL_LBS_2), - PINMUX_IPSR_MODSEL_DATA(IP2_18_16, RX1, SEL_SCIF1_0), - PINMUX_IPSR_MODSEL_DATA(IP2_18_16, SCIFA1_RXD, SEL_SCIFA1_0), + PINMUX_IPSR_MSEL(IP2_18_16, DACK2, SEL_LBS_0), + PINMUX_IPSR_MSEL(IP2_18_16, SSL, SEL_QSP_0), + PINMUX_IPSR_MSEL(IP2_18_16, DREQ1_C, SEL_LBS_2), + PINMUX_IPSR_MSEL(IP2_18_16, RX1, SEL_SCIF1_0), + PINMUX_IPSR_MSEL(IP2_18_16, SCIFA1_RXD, SEL_SCIFA1_0), PINMUX_IPSR_DATA(IP2_20_19, CS0_N), - PINMUX_IPSR_MODSEL_DATA(IP2_20_19, ATAG0_N_B, SEL_LBS_1), - PINMUX_IPSR_MODSEL_DATA(IP2_20_19, SCL1, SEL_IIC1_0), + PINMUX_IPSR_MSEL(IP2_20_19, ATAG0_N_B, SEL_LBS_1), + PINMUX_IPSR_MSEL(IP2_20_19, SCL1, SEL_IIC1_0), PINMUX_IPSR_DATA(IP2_22_21, CS1_N_A26), - PINMUX_IPSR_MODSEL_DATA(IP2_22_21, ATADIR0_N_B, SEL_LBS_1), - PINMUX_IPSR_MODSEL_DATA(IP2_22_21, SDA1, SEL_IIC1_0), + PINMUX_IPSR_MSEL(IP2_22_21, ATADIR0_N_B, SEL_LBS_1), + PINMUX_IPSR_MSEL(IP2_22_21, SDA1, SEL_IIC1_0), PINMUX_IPSR_DATA(IP2_24_23, EX_CS1_N), - PINMUX_IPSR_MODSEL_DATA(IP2_24_23, MSIOF2_SCK, SEL_SOF2_0), + PINMUX_IPSR_MSEL(IP2_24_23, MSIOF2_SCK, SEL_SOF2_0), PINMUX_IPSR_DATA(IP2_26_25, EX_CS2_N), - PINMUX_IPSR_MODSEL_DATA(IP2_26_25, ATAWR0_N, SEL_LBS_0), - PINMUX_IPSR_MODSEL_DATA(IP2_26_25, MSIOF2_SYNC, SEL_SOF2_0), + PINMUX_IPSR_MSEL(IP2_26_25, ATAWR0_N, SEL_LBS_0), + PINMUX_IPSR_MSEL(IP2_26_25, MSIOF2_SYNC, SEL_SOF2_0), PINMUX_IPSR_DATA(IP2_29_27, EX_CS3_N), - PINMUX_IPSR_MODSEL_DATA(IP2_29_27, ATADIR0_N, SEL_LBS_0), - PINMUX_IPSR_MODSEL_DATA(IP2_29_27, MSIOF2_TXD, SEL_SOF2_0), - PINMUX_IPSR_MODSEL_DATA(IP2_29_27, ATAG0_N, SEL_LBS_0), + PINMUX_IPSR_MSEL(IP2_29_27, ATADIR0_N, SEL_LBS_0), + PINMUX_IPSR_MSEL(IP2_29_27, MSIOF2_TXD, SEL_SOF2_0), + PINMUX_IPSR_MSEL(IP2_29_27, ATAG0_N, SEL_LBS_0), PINMUX_IPSR_DATA(IP2_29_27, EX_WAIT1), /* IPSR3 */ PINMUX_IPSR_DATA(IP3_2_0, EX_CS4_N), - PINMUX_IPSR_MODSEL_DATA(IP3_2_0, ATARD0_N, SEL_LBS_0), - PINMUX_IPSR_MODSEL_DATA(IP3_2_0, MSIOF2_RXD, SEL_SOF2_0), + PINMUX_IPSR_MSEL(IP3_2_0, ATARD0_N, SEL_LBS_0), + PINMUX_IPSR_MSEL(IP3_2_0, MSIOF2_RXD, SEL_SOF2_0), PINMUX_IPSR_DATA(IP3_2_0, EX_WAIT2), PINMUX_IPSR_DATA(IP3_5_3, EX_CS5_N), PINMUX_IPSR_DATA(IP3_5_3, ATACS00_N), - PINMUX_IPSR_MODSEL_DATA(IP3_5_3, MSIOF2_SS1, SEL_SOF2_0), - PINMUX_IPSR_MODSEL_DATA(IP3_5_3, HRX1_B, SEL_HSCIF1_1), - PINMUX_IPSR_MODSEL_DATA(IP3_5_3, SCIFB1_RXD_B, SEL_SCIFB1_1), + PINMUX_IPSR_MSEL(IP3_5_3, MSIOF2_SS1, SEL_SOF2_0), + PINMUX_IPSR_MSEL(IP3_5_3, HRX1_B, SEL_HSCIF1_1), + PINMUX_IPSR_MSEL(IP3_5_3, SCIFB1_RXD_B, SEL_SCIFB1_1), PINMUX_IPSR_DATA(IP3_5_3, PWM1), PINMUX_IPSR_DATA(IP3_5_3, TPU_TO1), PINMUX_IPSR_DATA(IP3_8_6, BS_N), PINMUX_IPSR_DATA(IP3_8_6, ATACS10_N), - PINMUX_IPSR_MODSEL_DATA(IP3_8_6, MSIOF2_SS2, SEL_SOF2_0), - PINMUX_IPSR_MODSEL_DATA(IP3_8_6, HTX1_B, SEL_HSCIF1_1), - PINMUX_IPSR_MODSEL_DATA(IP3_8_6, SCIFB1_TXD_B, SEL_SCIFB1_1), + PINMUX_IPSR_MSEL(IP3_8_6, MSIOF2_SS2, SEL_SOF2_0), + PINMUX_IPSR_MSEL(IP3_8_6, HTX1_B, SEL_HSCIF1_1), + PINMUX_IPSR_MSEL(IP3_8_6, SCIFB1_TXD_B, SEL_SCIFB1_1), PINMUX_IPSR_DATA(IP3_8_6, PWM2), PINMUX_IPSR_DATA(IP3_8_6, TPU_TO2), PINMUX_IPSR_DATA(IP3_11_9, RD_WR_N), - PINMUX_IPSR_MODSEL_DATA(IP3_11_9, HRX2_B, SEL_HSCIF2_1), - PINMUX_IPSR_MODSEL_DATA(IP3_11_9, FMIN_B, SEL_FM_1), - PINMUX_IPSR_MODSEL_DATA(IP3_11_9, SCIFB0_RXD_B, SEL_SCIFB_1), - PINMUX_IPSR_MODSEL_DATA(IP3_11_9, DREQ1_D, SEL_LBS_1), + PINMUX_IPSR_MSEL(IP3_11_9, HRX2_B, SEL_HSCIF2_1), + PINMUX_IPSR_MSEL(IP3_11_9, FMIN_B, SEL_FM_1), + PINMUX_IPSR_MSEL(IP3_11_9, SCIFB0_RXD_B, SEL_SCIFB_1), + PINMUX_IPSR_MSEL(IP3_11_9, DREQ1_D, SEL_LBS_1), PINMUX_IPSR_DATA(IP3_13_12, WE0_N), - PINMUX_IPSR_MODSEL_DATA(IP3_13_12, HCTS2_N_B, SEL_HSCIF2_1), - PINMUX_IPSR_MODSEL_DATA(IP3_13_12, SCIFB0_TXD_B, SEL_SCIFB_1), + PINMUX_IPSR_MSEL(IP3_13_12, HCTS2_N_B, SEL_HSCIF2_1), + PINMUX_IPSR_MSEL(IP3_13_12, SCIFB0_TXD_B, SEL_SCIFB_1), PINMUX_IPSR_DATA(IP3_15_14, WE1_N), - PINMUX_IPSR_MODSEL_DATA(IP3_15_14, ATARD0_N_B, SEL_LBS_1), - PINMUX_IPSR_MODSEL_DATA(IP3_15_14, HTX2_B, SEL_HSCIF2_1), - PINMUX_IPSR_MODSEL_DATA(IP3_15_14, SCIFB0_RTS_N_B, SEL_SCIFB_1), + PINMUX_IPSR_MSEL(IP3_15_14, ATARD0_N_B, SEL_LBS_1), + PINMUX_IPSR_MSEL(IP3_15_14, HTX2_B, SEL_HSCIF2_1), + PINMUX_IPSR_MSEL(IP3_15_14, SCIFB0_RTS_N_B, SEL_SCIFB_1), PINMUX_IPSR_DATA(IP3_17_16, EX_WAIT0), - PINMUX_IPSR_MODSEL_DATA(IP3_17_16, HRTS2_N_B, SEL_HSCIF2_1), - PINMUX_IPSR_MODSEL_DATA(IP3_17_16, SCIFB0_CTS_N_B, SEL_SCIFB_1), + PINMUX_IPSR_MSEL(IP3_17_16, HRTS2_N_B, SEL_HSCIF2_1), + PINMUX_IPSR_MSEL(IP3_17_16, SCIFB0_CTS_N_B, SEL_SCIFB_1), PINMUX_IPSR_DATA(IP3_19_18, DREQ0), PINMUX_IPSR_DATA(IP3_19_18, PWM3), PINMUX_IPSR_DATA(IP3_19_18, TPU_TO3), PINMUX_IPSR_DATA(IP3_21_20, DACK0), PINMUX_IPSR_DATA(IP3_21_20, DRACK0), - PINMUX_IPSR_MODSEL_DATA(IP3_21_20, REMOCON, SEL_RCN_0), - PINMUX_IPSR_MODSEL_DATA(IP3_24_22, SPEEDIN, SEL_RSP_0), - PINMUX_IPSR_MODSEL_DATA(IP3_24_22, HSCK0_C, SEL_HSCIF0_2), - PINMUX_IPSR_MODSEL_DATA(IP3_24_22, HSCK2_C, SEL_HSCIF2_2), - PINMUX_IPSR_MODSEL_DATA(IP3_24_22, SCIFB0_SCK_B, SEL_SCIFB_1), - PINMUX_IPSR_MODSEL_DATA(IP3_24_22, SCIFB2_SCK_B, SEL_SCIFB2_1), - PINMUX_IPSR_MODSEL_DATA(IP3_24_22, DREQ2_C, SEL_LBS_2), - PINMUX_IPSR_MODSEL_DATA(IP3_30_28, HTX2_C, SEL_HSCIF2_2), - PINMUX_IPSR_MODSEL_DATA(IP3_27_25, SSI_SCK0129, SEL_SSI0_0), - PINMUX_IPSR_MODSEL_DATA(IP3_27_25, HRX0_C, SEL_HSCIF0_2), - PINMUX_IPSR_MODSEL_DATA(IP3_27_25, HRX2_C, SEL_HSCIF2_2), - PINMUX_IPSR_MODSEL_DATA(IP3_27_25, SCIFB0_RXD_C, SEL_SCIFB_2), - PINMUX_IPSR_MODSEL_DATA(IP3_27_25, SCIFB2_RXD_C, SEL_SCIFB2_2), - PINMUX_IPSR_MODSEL_DATA(IP3_30_28, SSI_WS0129, SEL_SSI0_0), - PINMUX_IPSR_MODSEL_DATA(IP3_30_28, HTX0_C, SEL_HSCIF0_2), - PINMUX_IPSR_MODSEL_DATA(IP3_30_28, HTX2_C, SEL_HSCIF2_2), - PINMUX_IPSR_MODSEL_DATA(IP3_30_28, SCIFB0_TXD_C, SEL_SCIFB_2), - PINMUX_IPSR_MODSEL_DATA(IP3_30_28, SCIFB2_TXD_C, SEL_SCIFB2_2), + PINMUX_IPSR_MSEL(IP3_21_20, REMOCON, SEL_RCN_0), + PINMUX_IPSR_MSEL(IP3_24_22, SPEEDIN, SEL_RSP_0), + PINMUX_IPSR_MSEL(IP3_24_22, HSCK0_C, SEL_HSCIF0_2), + PINMUX_IPSR_MSEL(IP3_24_22, HSCK2_C, SEL_HSCIF2_2), + PINMUX_IPSR_MSEL(IP3_24_22, SCIFB0_SCK_B, SEL_SCIFB_1), + PINMUX_IPSR_MSEL(IP3_24_22, SCIFB2_SCK_B, SEL_SCIFB2_1), + PINMUX_IPSR_MSEL(IP3_24_22, DREQ2_C, SEL_LBS_2), + PINMUX_IPSR_MSEL(IP3_30_28, HTX2_C, SEL_HSCIF2_2), + PINMUX_IPSR_MSEL(IP3_27_25, SSI_SCK0129, SEL_SSI0_0), + PINMUX_IPSR_MSEL(IP3_27_25, HRX0_C, SEL_HSCIF0_2), + PINMUX_IPSR_MSEL(IP3_27_25, HRX2_C, SEL_HSCIF2_2), + PINMUX_IPSR_MSEL(IP3_27_25, SCIFB0_RXD_C, SEL_SCIFB_2), + PINMUX_IPSR_MSEL(IP3_27_25, SCIFB2_RXD_C, SEL_SCIFB2_2), + PINMUX_IPSR_MSEL(IP3_30_28, SSI_WS0129, SEL_SSI0_0), + PINMUX_IPSR_MSEL(IP3_30_28, HTX0_C, SEL_HSCIF0_2), + PINMUX_IPSR_MSEL(IP3_30_28, HTX2_C, SEL_HSCIF2_2), + PINMUX_IPSR_MSEL(IP3_30_28, SCIFB0_TXD_C, SEL_SCIFB_2), + PINMUX_IPSR_MSEL(IP3_30_28, SCIFB2_TXD_C, SEL_SCIFB2_2), /* IPSR4 */ - PINMUX_IPSR_MODSEL_DATA(IP4_1_0, SSI_SDATA0, SEL_SSI0_0), - PINMUX_IPSR_MODSEL_DATA(IP4_1_0, SCL0_B, SEL_IIC0_1), - PINMUX_IPSR_MODSEL_DATA(IP4_1_0, SCL7_B, SEL_IIC7_1), - PINMUX_IPSR_MODSEL_DATA(IP4_1_0, MSIOF2_SCK_C, SEL_SOF2_2), - PINMUX_IPSR_MODSEL_DATA(IP4_4_2, SSI_SCK1, SEL_SSI1_0), - PINMUX_IPSR_MODSEL_DATA(IP4_4_2, SDA0_B, SEL_IIC0_1), - PINMUX_IPSR_MODSEL_DATA(IP4_4_2, SDA7_B, SEL_IIC7_1), - PINMUX_IPSR_MODSEL_DATA(IP4_4_2, MSIOF2_SYNC_C, SEL_SOF2_2), - PINMUX_IPSR_MODSEL_DATA(IP4_4_2, GLO_I0_D, SEL_GPS_3), - PINMUX_IPSR_MODSEL_DATA(IP4_7_5, SSI_WS1, SEL_SSI1_0), - PINMUX_IPSR_MODSEL_DATA(IP4_7_5, SCL1_B, SEL_IIC1_1), - PINMUX_IPSR_MODSEL_DATA(IP4_7_5, SCL8_B, SEL_IIC8_1), - PINMUX_IPSR_MODSEL_DATA(IP4_7_5, MSIOF2_TXD_C, SEL_SOF2_2), - PINMUX_IPSR_MODSEL_DATA(IP4_7_5, GLO_I1_D, SEL_GPS_3), - PINMUX_IPSR_MODSEL_DATA(IP4_9_8, SSI_SDATA1, SEL_SSI1_0), - PINMUX_IPSR_MODSEL_DATA(IP4_9_8, SDA1_B, SEL_IIC1_1), - PINMUX_IPSR_MODSEL_DATA(IP4_9_8, SDA8_B, SEL_IIC8_1), - PINMUX_IPSR_MODSEL_DATA(IP4_9_8, MSIOF2_RXD_C, SEL_SOF2_2), + PINMUX_IPSR_MSEL(IP4_1_0, SSI_SDATA0, SEL_SSI0_0), + PINMUX_IPSR_MSEL(IP4_1_0, SCL0_B, SEL_IIC0_1), + PINMUX_IPSR_MSEL(IP4_1_0, SCL7_B, SEL_IIC7_1), + PINMUX_IPSR_MSEL(IP4_1_0, MSIOF2_SCK_C, SEL_SOF2_2), + PINMUX_IPSR_MSEL(IP4_4_2, SSI_SCK1, SEL_SSI1_0), + PINMUX_IPSR_MSEL(IP4_4_2, SDA0_B, SEL_IIC0_1), + PINMUX_IPSR_MSEL(IP4_4_2, SDA7_B, SEL_IIC7_1), + PINMUX_IPSR_MSEL(IP4_4_2, MSIOF2_SYNC_C, SEL_SOF2_2), + PINMUX_IPSR_MSEL(IP4_4_2, GLO_I0_D, SEL_GPS_3), + PINMUX_IPSR_MSEL(IP4_7_5, SSI_WS1, SEL_SSI1_0), + PINMUX_IPSR_MSEL(IP4_7_5, SCL1_B, SEL_IIC1_1), + PINMUX_IPSR_MSEL(IP4_7_5, SCL8_B, SEL_IIC8_1), + PINMUX_IPSR_MSEL(IP4_7_5, MSIOF2_TXD_C, SEL_SOF2_2), + PINMUX_IPSR_MSEL(IP4_7_5, GLO_I1_D, SEL_GPS_3), + PINMUX_IPSR_MSEL(IP4_9_8, SSI_SDATA1, SEL_SSI1_0), + PINMUX_IPSR_MSEL(IP4_9_8, SDA1_B, SEL_IIC1_1), + PINMUX_IPSR_MSEL(IP4_9_8, SDA8_B, SEL_IIC8_1), + PINMUX_IPSR_MSEL(IP4_9_8, MSIOF2_RXD_C, SEL_SOF2_2), PINMUX_IPSR_DATA(IP4_12_10, SSI_SCK2), - PINMUX_IPSR_MODSEL_DATA(IP4_12_10, SCL2, SEL_IIC2_0), - PINMUX_IPSR_MODSEL_DATA(IP4_12_10, GPS_CLK_B, SEL_GPS_1), - PINMUX_IPSR_MODSEL_DATA(IP4_12_10, GLO_Q0_D, SEL_GPS_3), + PINMUX_IPSR_MSEL(IP4_12_10, SCL2, SEL_IIC2_0), + PINMUX_IPSR_MSEL(IP4_12_10, GPS_CLK_B, SEL_GPS_1), + PINMUX_IPSR_MSEL(IP4_12_10, GLO_Q0_D, SEL_GPS_3), PINMUX_IPSR_DATA(IP4_15_13, SSI_WS2), - PINMUX_IPSR_MODSEL_DATA(IP4_15_13, SDA2, SEL_IIC2_0), - PINMUX_IPSR_MODSEL_DATA(IP4_15_13, GPS_SIGN_B, SEL_GPS_1), - PINMUX_IPSR_MODSEL_DATA(IP4_15_13, RX2_E, SEL_SCIF2_4), - PINMUX_IPSR_MODSEL_DATA(IP4_15_13, GLO_Q1_D, SEL_GPS_3), + PINMUX_IPSR_MSEL(IP4_15_13, SDA2, SEL_IIC2_0), + PINMUX_IPSR_MSEL(IP4_15_13, GPS_SIGN_B, SEL_GPS_1), + PINMUX_IPSR_MSEL(IP4_15_13, RX2_E, SEL_SCIF2_4), + PINMUX_IPSR_MSEL(IP4_15_13, GLO_Q1_D, SEL_GPS_3), PINMUX_IPSR_DATA(IP4_18_16, SSI_SDATA2), - PINMUX_IPSR_MODSEL_DATA(IP4_18_16, GPS_MAG_B, SEL_GPS_1), - PINMUX_IPSR_MODSEL_DATA(IP4_18_16, TX2_E, SEL_SCIF2_4), + PINMUX_IPSR_MSEL(IP4_18_16, GPS_MAG_B, SEL_GPS_1), + PINMUX_IPSR_MSEL(IP4_18_16, TX2_E, SEL_SCIF2_4), PINMUX_IPSR_DATA(IP4_19, SSI_SCK34), PINMUX_IPSR_DATA(IP4_20, SSI_WS34), PINMUX_IPSR_DATA(IP4_21, SSI_SDATA3), PINMUX_IPSR_DATA(IP4_23_22, SSI_SCK4), - PINMUX_IPSR_MODSEL_DATA(IP4_23_22, GLO_SS_D, SEL_GPS_3), + PINMUX_IPSR_MSEL(IP4_23_22, GLO_SS_D, SEL_GPS_3), PINMUX_IPSR_DATA(IP4_25_24, SSI_WS4), - PINMUX_IPSR_MODSEL_DATA(IP4_25_24, GLO_RFON_D, SEL_GPS_3), + PINMUX_IPSR_MSEL(IP4_25_24, GLO_RFON_D, SEL_GPS_3), PINMUX_IPSR_DATA(IP4_27_26, SSI_SDATA4), - PINMUX_IPSR_MODSEL_DATA(IP4_27_26, MSIOF2_SCK_D, SEL_SOF2_3), + PINMUX_IPSR_MSEL(IP4_27_26, MSIOF2_SCK_D, SEL_SOF2_3), PINMUX_IPSR_DATA(IP4_30_28, SSI_SCK5), - PINMUX_IPSR_MODSEL_DATA(IP4_30_28, MSIOF1_SCK_C, SEL_SOF1_2), - PINMUX_IPSR_MODSEL_DATA(IP4_30_28, TS_SDATA0, SEL_TSIF0_0), - PINMUX_IPSR_MODSEL_DATA(IP4_30_28, GLO_I0, SEL_GPS_0), - PINMUX_IPSR_MODSEL_DATA(IP4_30_28, MSIOF2_SYNC_D, SEL_SOF2_3), + PINMUX_IPSR_MSEL(IP4_30_28, MSIOF1_SCK_C, SEL_SOF1_2), + PINMUX_IPSR_MSEL(IP4_30_28, TS_SDATA0, SEL_TSIF0_0), + PINMUX_IPSR_MSEL(IP4_30_28, GLO_I0, SEL_GPS_0), + PINMUX_IPSR_MSEL(IP4_30_28, MSIOF2_SYNC_D, SEL_SOF2_3), PINMUX_IPSR_DATA(IP4_30_28, VI1_R2_B), /* IPSR5 */ PINMUX_IPSR_DATA(IP5_2_0, SSI_WS5), - PINMUX_IPSR_MODSEL_DATA(IP5_2_0, MSIOF1_SYNC_C, SEL_SOF1_2), - PINMUX_IPSR_MODSEL_DATA(IP5_2_0, TS_SCK0, SEL_TSIF0_0), - PINMUX_IPSR_MODSEL_DATA(IP5_2_0, GLO_I1, SEL_GPS_0), - PINMUX_IPSR_MODSEL_DATA(IP5_2_0, MSIOF2_TXD_D, SEL_SOF2_3), + PINMUX_IPSR_MSEL(IP5_2_0, MSIOF1_SYNC_C, SEL_SOF1_2), + PINMUX_IPSR_MSEL(IP5_2_0, TS_SCK0, SEL_TSIF0_0), + PINMUX_IPSR_MSEL(IP5_2_0, GLO_I1, SEL_GPS_0), + PINMUX_IPSR_MSEL(IP5_2_0, MSIOF2_TXD_D, SEL_SOF2_3), PINMUX_IPSR_DATA(IP5_2_0, VI1_R3_B), PINMUX_IPSR_DATA(IP5_5_3, SSI_SDATA5), - PINMUX_IPSR_MODSEL_DATA(IP5_5_3, MSIOF1_TXD_C, SEL_SOF1_2), - PINMUX_IPSR_MODSEL_DATA(IP5_5_3, TS_SDEN0, SEL_TSIF0_0), - PINMUX_IPSR_MODSEL_DATA(IP5_5_3, GLO_Q0, SEL_GPS_0), - PINMUX_IPSR_MODSEL_DATA(IP5_5_3, MSIOF2_SS1_D, SEL_SOF2_3), + PINMUX_IPSR_MSEL(IP5_5_3, MSIOF1_TXD_C, SEL_SOF1_2), + PINMUX_IPSR_MSEL(IP5_5_3, TS_SDEN0, SEL_TSIF0_0), + PINMUX_IPSR_MSEL(IP5_5_3, GLO_Q0, SEL_GPS_0), + PINMUX_IPSR_MSEL(IP5_5_3, MSIOF2_SS1_D, SEL_SOF2_3), PINMUX_IPSR_DATA(IP5_5_3, VI1_R4_B), PINMUX_IPSR_DATA(IP5_8_6, SSI_SCK6), - PINMUX_IPSR_MODSEL_DATA(IP5_8_6, MSIOF1_RXD_C, SEL_SOF1_2), - PINMUX_IPSR_MODSEL_DATA(IP5_8_6, TS_SPSYNC0, SEL_TSIF0_0), - PINMUX_IPSR_MODSEL_DATA(IP5_8_6, GLO_Q1, SEL_GPS_0), - PINMUX_IPSR_MODSEL_DATA(IP5_8_6, MSIOF2_RXD_D, SEL_SOF2_3), + PINMUX_IPSR_MSEL(IP5_8_6, MSIOF1_RXD_C, SEL_SOF1_2), + PINMUX_IPSR_MSEL(IP5_8_6, TS_SPSYNC0, SEL_TSIF0_0), + PINMUX_IPSR_MSEL(IP5_8_6, GLO_Q1, SEL_GPS_0), + PINMUX_IPSR_MSEL(IP5_8_6, MSIOF2_RXD_D, SEL_SOF2_3), PINMUX_IPSR_DATA(IP5_8_6, VI1_R5_B), PINMUX_IPSR_DATA(IP5_11_9, SSI_WS6), - PINMUX_IPSR_MODSEL_DATA(IP5_11_9, GLO_SCLK, SEL_GPS_0), - PINMUX_IPSR_MODSEL_DATA(IP5_11_9, MSIOF2_SS2_D, SEL_SOF2_3), + PINMUX_IPSR_MSEL(IP5_11_9, GLO_SCLK, SEL_GPS_0), + PINMUX_IPSR_MSEL(IP5_11_9, MSIOF2_SS2_D, SEL_SOF2_3), PINMUX_IPSR_DATA(IP5_11_9, VI1_R6_B), PINMUX_IPSR_DATA(IP5_14_12, SSI_SDATA6), - PINMUX_IPSR_MODSEL_DATA(IP5_14_12, STP_IVCXO27_0_B, SEL_SSP_1), - PINMUX_IPSR_MODSEL_DATA(IP5_14_12, GLO_SDATA, SEL_GPS_0), + PINMUX_IPSR_MSEL(IP5_14_12, STP_IVCXO27_0_B, SEL_SSP_1), + PINMUX_IPSR_MSEL(IP5_14_12, GLO_SDATA, SEL_GPS_0), PINMUX_IPSR_DATA(IP5_14_12, VI1_R7_B), - PINMUX_IPSR_MODSEL_DATA(IP5_16_15, SSI_SCK78, SEL_SSI7_0), - PINMUX_IPSR_MODSEL_DATA(IP5_16_15, STP_ISCLK_0_B, SEL_SSP_1), - PINMUX_IPSR_MODSEL_DATA(IP5_16_15, GLO_SS, SEL_GPS_0), - PINMUX_IPSR_MODSEL_DATA(IP5_19_17, SSI_WS78, SEL_SSI7_0), - PINMUX_IPSR_MODSEL_DATA(IP5_19_17, TX0_D, SEL_SCIF0_3), - PINMUX_IPSR_MODSEL_DATA(IP5_19_17, STP_ISD_0_B, SEL_SSP_1), - PINMUX_IPSR_MODSEL_DATA(IP5_19_17, GLO_RFON, SEL_GPS_0), - PINMUX_IPSR_MODSEL_DATA(IP5_21_20, SSI_SDATA7, SEL_SSI7_0), - PINMUX_IPSR_MODSEL_DATA(IP5_21_20, RX0_D, SEL_SCIF0_3), - PINMUX_IPSR_MODSEL_DATA(IP5_21_20, STP_ISEN_0_B, SEL_SSP_1), - PINMUX_IPSR_MODSEL_DATA(IP5_23_22, SSI_SDATA8, SEL_SSI8_0), - PINMUX_IPSR_MODSEL_DATA(IP5_23_22, TX1_D, SEL_SCIF1_3), - PINMUX_IPSR_MODSEL_DATA(IP5_23_22, STP_ISSYNC_0_B, SEL_SSP_1), - PINMUX_IPSR_MODSEL_DATA(IP5_25_24, SSI_SCK9, SEL_SSI9_0), - PINMUX_IPSR_MODSEL_DATA(IP5_25_24, RX1_D, SEL_SCIF1_3), - PINMUX_IPSR_MODSEL_DATA(IP5_25_24, GLO_SCLK_D, SEL_GPS_3), - PINMUX_IPSR_MODSEL_DATA(IP5_28_26, SSI_WS9, SEL_SSI9_0), - PINMUX_IPSR_MODSEL_DATA(IP5_28_26, TX3_D, SEL_SCIF3_3), - PINMUX_IPSR_MODSEL_DATA(IP5_28_26, CAN0_TX_D, SEL_CAN0_3), - PINMUX_IPSR_MODSEL_DATA(IP5_28_26, GLO_SDATA_D, SEL_GPS_3), - PINMUX_IPSR_MODSEL_DATA(IP5_31_29, SSI_SDATA9, SEL_SSI9_0), - PINMUX_IPSR_MODSEL_DATA(IP5_31_29, RX3_D, SEL_SCIF3_3), - PINMUX_IPSR_MODSEL_DATA(IP5_31_29, CAN0_RX_D, SEL_CAN0_3), + PINMUX_IPSR_MSEL(IP5_16_15, SSI_SCK78, SEL_SSI7_0), + PINMUX_IPSR_MSEL(IP5_16_15, STP_ISCLK_0_B, SEL_SSP_1), + PINMUX_IPSR_MSEL(IP5_16_15, GLO_SS, SEL_GPS_0), + PINMUX_IPSR_MSEL(IP5_19_17, SSI_WS78, SEL_SSI7_0), + PINMUX_IPSR_MSEL(IP5_19_17, TX0_D, SEL_SCIF0_3), + PINMUX_IPSR_MSEL(IP5_19_17, STP_ISD_0_B, SEL_SSP_1), + PINMUX_IPSR_MSEL(IP5_19_17, GLO_RFON, SEL_GPS_0), + PINMUX_IPSR_MSEL(IP5_21_20, SSI_SDATA7, SEL_SSI7_0), + PINMUX_IPSR_MSEL(IP5_21_20, RX0_D, SEL_SCIF0_3), + PINMUX_IPSR_MSEL(IP5_21_20, STP_ISEN_0_B, SEL_SSP_1), + PINMUX_IPSR_MSEL(IP5_23_22, SSI_SDATA8, SEL_SSI8_0), + PINMUX_IPSR_MSEL(IP5_23_22, TX1_D, SEL_SCIF1_3), + PINMUX_IPSR_MSEL(IP5_23_22, STP_ISSYNC_0_B, SEL_SSP_1), + PINMUX_IPSR_MSEL(IP5_25_24, SSI_SCK9, SEL_SSI9_0), + PINMUX_IPSR_MSEL(IP5_25_24, RX1_D, SEL_SCIF1_3), + PINMUX_IPSR_MSEL(IP5_25_24, GLO_SCLK_D, SEL_GPS_3), + PINMUX_IPSR_MSEL(IP5_28_26, SSI_WS9, SEL_SSI9_0), + PINMUX_IPSR_MSEL(IP5_28_26, TX3_D, SEL_SCIF3_3), + PINMUX_IPSR_MSEL(IP5_28_26, CAN0_TX_D, SEL_CAN0_3), + PINMUX_IPSR_MSEL(IP5_28_26, GLO_SDATA_D, SEL_GPS_3), + PINMUX_IPSR_MSEL(IP5_31_29, SSI_SDATA9, SEL_SSI9_0), + PINMUX_IPSR_MSEL(IP5_31_29, RX3_D, SEL_SCIF3_3), + PINMUX_IPSR_MSEL(IP5_31_29, CAN0_RX_D, SEL_CAN0_3), /* IPSR6 */ - PINMUX_IPSR_MODSEL_DATA(IP6_2_0, AUDIO_CLKB, SEL_ADG_0), - PINMUX_IPSR_MODSEL_DATA(IP6_2_0, STP_OPWM_0_B, SEL_SSP_1), - PINMUX_IPSR_MODSEL_DATA(IP6_2_0, MSIOF1_SCK_B, SEL_SOF1_1), - PINMUX_IPSR_MODSEL_DATA(IP6_2_0, SCIF_CLK, SEL_SCIF_0), - PINMUX_IPSR_MODSEL_DATA(IP6_2_0, BPFCLK_E, SEL_FM_4), + PINMUX_IPSR_MSEL(IP6_2_0, AUDIO_CLKB, SEL_ADG_0), + PINMUX_IPSR_MSEL(IP6_2_0, STP_OPWM_0_B, SEL_SSP_1), + PINMUX_IPSR_MSEL(IP6_2_0, MSIOF1_SCK_B, SEL_SOF1_1), + PINMUX_IPSR_MSEL(IP6_2_0, SCIF_CLK, SEL_SCIF_0), + PINMUX_IPSR_MSEL(IP6_2_0, BPFCLK_E, SEL_FM_4), PINMUX_IPSR_DATA(IP6_5_3, AUDIO_CLKC), - PINMUX_IPSR_MODSEL_DATA(IP6_5_3, SCIFB0_SCK_C, SEL_SCIFB_2), - PINMUX_IPSR_MODSEL_DATA(IP6_5_3, MSIOF1_SYNC_B, SEL_SOF1_1), - PINMUX_IPSR_MODSEL_DATA(IP6_5_3, RX2, SEL_SCIF2_0), - PINMUX_IPSR_MODSEL_DATA(IP6_5_3, SCIFA2_RXD, SEL_SCIFA2_0), - PINMUX_IPSR_MODSEL_DATA(IP6_5_3, FMIN_E, SEL_FM_4), + PINMUX_IPSR_MSEL(IP6_5_3, SCIFB0_SCK_C, SEL_SCIFB_2), + PINMUX_IPSR_MSEL(IP6_5_3, MSIOF1_SYNC_B, SEL_SOF1_1), + PINMUX_IPSR_MSEL(IP6_5_3, RX2, SEL_SCIF2_0), + PINMUX_IPSR_MSEL(IP6_5_3, SCIFA2_RXD, SEL_SCIFA2_0), + PINMUX_IPSR_MSEL(IP6_5_3, FMIN_E, SEL_FM_4), PINMUX_IPSR_DATA(IP6_7_6, AUDIO_CLKOUT), - PINMUX_IPSR_MODSEL_DATA(IP6_7_6, MSIOF1_SS1_B, SEL_SOF1_1), - PINMUX_IPSR_MODSEL_DATA(IP6_5_3, TX2, SEL_SCIF2_0), - PINMUX_IPSR_MODSEL_DATA(IP6_7_6, SCIFA2_TXD, SEL_SCIFA2_0), + PINMUX_IPSR_MSEL(IP6_7_6, MSIOF1_SS1_B, SEL_SOF1_1), + PINMUX_IPSR_MSEL(IP6_5_3, TX2, SEL_SCIF2_0), + PINMUX_IPSR_MSEL(IP6_7_6, SCIFA2_TXD, SEL_SCIFA2_0), PINMUX_IPSR_DATA(IP6_9_8, IRQ0), - PINMUX_IPSR_MODSEL_DATA(IP6_9_8, SCIFB1_RXD_D, SEL_SCIFB1_3), + PINMUX_IPSR_MSEL(IP6_9_8, SCIFB1_RXD_D, SEL_SCIFB1_3), PINMUX_IPSR_DATA(IP6_9_8, INTC_IRQ0_N), PINMUX_IPSR_DATA(IP6_11_10, IRQ1), - PINMUX_IPSR_MODSEL_DATA(IP6_11_10, SCIFB1_SCK_C, SEL_SCIFB1_2), + PINMUX_IPSR_MSEL(IP6_11_10, SCIFB1_SCK_C, SEL_SCIFB1_2), PINMUX_IPSR_DATA(IP6_11_10, INTC_IRQ1_N), PINMUX_IPSR_DATA(IP6_13_12, IRQ2), - PINMUX_IPSR_MODSEL_DATA(IP6_13_12, SCIFB1_TXD_D, SEL_SCIFB1_3), + PINMUX_IPSR_MSEL(IP6_13_12, SCIFB1_TXD_D, SEL_SCIFB1_3), PINMUX_IPSR_DATA(IP6_13_12, INTC_IRQ2_N), PINMUX_IPSR_DATA(IP6_15_14, IRQ3), - PINMUX_IPSR_MODSEL_DATA(IP6_15_14, SCL4_C, SEL_IIC4_2), - PINMUX_IPSR_MODSEL_DATA(IP6_15_14, MSIOF2_TXD_E, SEL_SOF2_4), + PINMUX_IPSR_MSEL(IP6_15_14, SCL4_C, SEL_IIC4_2), + PINMUX_IPSR_MSEL(IP6_15_14, MSIOF2_TXD_E, SEL_SOF2_4), PINMUX_IPSR_DATA(IP6_15_14, INTC_IRQ4_N), PINMUX_IPSR_DATA(IP6_18_16, IRQ4), - PINMUX_IPSR_MODSEL_DATA(IP6_18_16, HRX1_C, SEL_HSCIF1_2), - PINMUX_IPSR_MODSEL_DATA(IP6_18_16, SDA4_C, SEL_IIC4_2), - PINMUX_IPSR_MODSEL_DATA(IP6_18_16, MSIOF2_RXD_E, SEL_SOF2_4), + PINMUX_IPSR_MSEL(IP6_18_16, HRX1_C, SEL_HSCIF1_2), + PINMUX_IPSR_MSEL(IP6_18_16, SDA4_C, SEL_IIC4_2), + PINMUX_IPSR_MSEL(IP6_18_16, MSIOF2_RXD_E, SEL_SOF2_4), PINMUX_IPSR_DATA(IP6_18_16, INTC_IRQ4_N), PINMUX_IPSR_DATA(IP6_20_19, IRQ5), - PINMUX_IPSR_MODSEL_DATA(IP6_20_19, HTX1_C, SEL_HSCIF1_2), - PINMUX_IPSR_MODSEL_DATA(IP6_20_19, SCL1_E, SEL_IIC1_4), - PINMUX_IPSR_MODSEL_DATA(IP6_20_19, MSIOF2_SCK_E, SEL_SOF2_4), + PINMUX_IPSR_MSEL(IP6_20_19, HTX1_C, SEL_HSCIF1_2), + PINMUX_IPSR_MSEL(IP6_20_19, SCL1_E, SEL_IIC1_4), + PINMUX_IPSR_MSEL(IP6_20_19, MSIOF2_SCK_E, SEL_SOF2_4), PINMUX_IPSR_DATA(IP6_23_21, IRQ6), - PINMUX_IPSR_MODSEL_DATA(IP6_23_21, HSCK1_C, SEL_HSCIF1_2), - PINMUX_IPSR_MODSEL_DATA(IP6_23_21, MSIOF1_SS2_B, SEL_SOF1_1), - PINMUX_IPSR_MODSEL_DATA(IP6_23_21, SDA1_E, SEL_IIC1_4), - PINMUX_IPSR_MODSEL_DATA(IP6_23_21, MSIOF2_SYNC_E, SEL_SOF2_4), + PINMUX_IPSR_MSEL(IP6_23_21, HSCK1_C, SEL_HSCIF1_2), + PINMUX_IPSR_MSEL(IP6_23_21, MSIOF1_SS2_B, SEL_SOF1_1), + PINMUX_IPSR_MSEL(IP6_23_21, SDA1_E, SEL_IIC1_4), + PINMUX_IPSR_MSEL(IP6_23_21, MSIOF2_SYNC_E, SEL_SOF2_4), PINMUX_IPSR_DATA(IP6_26_24, IRQ7), - PINMUX_IPSR_MODSEL_DATA(IP6_26_24, HCTS1_N_C, SEL_HSCIF1_2), - PINMUX_IPSR_MODSEL_DATA(IP6_26_24, MSIOF1_TXD_B, SEL_SOF1_1), - PINMUX_IPSR_MODSEL_DATA(IP6_26_24, GPS_CLK_C, SEL_GPS_2), - PINMUX_IPSR_MODSEL_DATA(IP6_26_24, GPS_CLK_D, SEL_GPS_3), + PINMUX_IPSR_MSEL(IP6_26_24, HCTS1_N_C, SEL_HSCIF1_2), + PINMUX_IPSR_MSEL(IP6_26_24, MSIOF1_TXD_B, SEL_SOF1_1), + PINMUX_IPSR_MSEL(IP6_26_24, GPS_CLK_C, SEL_GPS_2), + PINMUX_IPSR_MSEL(IP6_26_24, GPS_CLK_D, SEL_GPS_3), PINMUX_IPSR_DATA(IP6_29_27, IRQ8), - PINMUX_IPSR_MODSEL_DATA(IP6_29_27, HRTS1_N_C, SEL_HSCIF1_2), - PINMUX_IPSR_MODSEL_DATA(IP6_29_27, MSIOF1_RXD_B, SEL_SOF1_1), - PINMUX_IPSR_MODSEL_DATA(IP6_29_27, GPS_SIGN_C, SEL_GPS_2), - PINMUX_IPSR_MODSEL_DATA(IP6_29_27, GPS_SIGN_D, SEL_GPS_3), + PINMUX_IPSR_MSEL(IP6_29_27, HRTS1_N_C, SEL_HSCIF1_2), + PINMUX_IPSR_MSEL(IP6_29_27, MSIOF1_RXD_B, SEL_SOF1_1), + PINMUX_IPSR_MSEL(IP6_29_27, GPS_SIGN_C, SEL_GPS_2), + PINMUX_IPSR_MSEL(IP6_29_27, GPS_SIGN_D, SEL_GPS_3), /* IPSR7 */ PINMUX_IPSR_DATA(IP7_2_0, IRQ9), - PINMUX_IPSR_MODSEL_DATA(IP7_2_0, DU1_DOTCLKIN_B, SEL_DIS_1), - PINMUX_IPSR_MODSEL_DATA(IP7_2_0, CAN_CLK_D, SEL_CANCLK_3), - PINMUX_IPSR_MODSEL_DATA(IP7_2_0, GPS_MAG_C, SEL_GPS_2), - PINMUX_IPSR_MODSEL_DATA(IP7_2_0, SCIF_CLK_B, SEL_SCIF_1), - PINMUX_IPSR_MODSEL_DATA(IP7_2_0, GPS_MAG_D, SEL_GPS_3), + PINMUX_IPSR_MSEL(IP7_2_0, DU1_DOTCLKIN_B, SEL_DIS_1), + PINMUX_IPSR_MSEL(IP7_2_0, CAN_CLK_D, SEL_CANCLK_3), + PINMUX_IPSR_MSEL(IP7_2_0, GPS_MAG_C, SEL_GPS_2), + PINMUX_IPSR_MSEL(IP7_2_0, SCIF_CLK_B, SEL_SCIF_1), + PINMUX_IPSR_MSEL(IP7_2_0, GPS_MAG_D, SEL_GPS_3), PINMUX_IPSR_DATA(IP7_5_3, DU1_DR0), PINMUX_IPSR_DATA(IP7_5_3, LCDOUT0), - PINMUX_IPSR_MODSEL_DATA(IP7_5_3, VI1_DATA0_B, SEL_VI1_1), - PINMUX_IPSR_MODSEL_DATA(IP7_5_3, TX0_B, SEL_SCIF0_1), - PINMUX_IPSR_MODSEL_DATA(IP7_5_3, SCIFA0_TXD_B, SEL_SCFA_1), - PINMUX_IPSR_MODSEL_DATA(IP7_5_3, MSIOF2_SCK_B, SEL_SOF2_1), + PINMUX_IPSR_MSEL(IP7_5_3, VI1_DATA0_B, SEL_VI1_1), + PINMUX_IPSR_MSEL(IP7_5_3, TX0_B, SEL_SCIF0_1), + PINMUX_IPSR_MSEL(IP7_5_3, SCIFA0_TXD_B, SEL_SCFA_1), + PINMUX_IPSR_MSEL(IP7_5_3, MSIOF2_SCK_B, SEL_SOF2_1), PINMUX_IPSR_DATA(IP7_8_6, DU1_DR1), PINMUX_IPSR_DATA(IP7_8_6, LCDOUT1), - PINMUX_IPSR_MODSEL_DATA(IP7_8_6, VI1_DATA1_B, SEL_VI1_1), - PINMUX_IPSR_MODSEL_DATA(IP7_8_6, RX0_B, SEL_SCIF0_1), - PINMUX_IPSR_MODSEL_DATA(IP7_8_6, SCIFA0_RXD_B, SEL_SCFA_1), - PINMUX_IPSR_MODSEL_DATA(IP7_8_6, MSIOF2_SYNC_B, SEL_SOF2_1), + PINMUX_IPSR_MSEL(IP7_8_6, VI1_DATA1_B, SEL_VI1_1), + PINMUX_IPSR_MSEL(IP7_8_6, RX0_B, SEL_SCIF0_1), + PINMUX_IPSR_MSEL(IP7_8_6, SCIFA0_RXD_B, SEL_SCFA_1), + PINMUX_IPSR_MSEL(IP7_8_6, MSIOF2_SYNC_B, SEL_SOF2_1), PINMUX_IPSR_DATA(IP7_10_9, DU1_DR2), PINMUX_IPSR_DATA(IP7_10_9, LCDOUT2), - PINMUX_IPSR_MODSEL_DATA(IP7_10_9, SSI_SCK0129_B, SEL_SSI0_1), + PINMUX_IPSR_MSEL(IP7_10_9, SSI_SCK0129_B, SEL_SSI0_1), PINMUX_IPSR_DATA(IP7_12_11, DU1_DR3), PINMUX_IPSR_DATA(IP7_12_11, LCDOUT3), - PINMUX_IPSR_MODSEL_DATA(IP7_12_11, SSI_WS0129_B, SEL_SSI0_1), + PINMUX_IPSR_MSEL(IP7_12_11, SSI_WS0129_B, SEL_SSI0_1), PINMUX_IPSR_DATA(IP7_14_13, DU1_DR4), PINMUX_IPSR_DATA(IP7_14_13, LCDOUT4), - PINMUX_IPSR_MODSEL_DATA(IP7_14_13, SSI_SDATA0_B, SEL_SSI0_1), + PINMUX_IPSR_MSEL(IP7_14_13, SSI_SDATA0_B, SEL_SSI0_1), PINMUX_IPSR_DATA(IP7_16_15, DU1_DR5), PINMUX_IPSR_DATA(IP7_16_15, LCDOUT5), - PINMUX_IPSR_MODSEL_DATA(IP7_16_15, SSI_SCK1_B, SEL_SSI1_1), + PINMUX_IPSR_MSEL(IP7_16_15, SSI_SCK1_B, SEL_SSI1_1), PINMUX_IPSR_DATA(IP7_18_17, DU1_DR6), PINMUX_IPSR_DATA(IP7_18_17, LCDOUT6), - PINMUX_IPSR_MODSEL_DATA(IP7_18_17, SSI_WS1_B, SEL_SSI1_1), + PINMUX_IPSR_MSEL(IP7_18_17, SSI_WS1_B, SEL_SSI1_1), PINMUX_IPSR_DATA(IP7_20_19, DU1_DR7), PINMUX_IPSR_DATA(IP7_20_19, LCDOUT7), - PINMUX_IPSR_MODSEL_DATA(IP7_20_19, SSI_SDATA1_B, SEL_SSI1_1), + PINMUX_IPSR_MSEL(IP7_20_19, SSI_SDATA1_B, SEL_SSI1_1), PINMUX_IPSR_DATA(IP7_23_21, DU1_DG0), PINMUX_IPSR_DATA(IP7_23_21, LCDOUT8), - PINMUX_IPSR_MODSEL_DATA(IP7_23_21, VI1_DATA2_B, SEL_VI1_1), - PINMUX_IPSR_MODSEL_DATA(IP7_23_21, TX1_B, SEL_SCIF1_1), - PINMUX_IPSR_MODSEL_DATA(IP7_23_21, SCIFA1_TXD_B, SEL_SCIFA1_1), - PINMUX_IPSR_MODSEL_DATA(IP7_23_21, MSIOF2_SS1_B, SEL_SOF2_1), + PINMUX_IPSR_MSEL(IP7_23_21, VI1_DATA2_B, SEL_VI1_1), + PINMUX_IPSR_MSEL(IP7_23_21, TX1_B, SEL_SCIF1_1), + PINMUX_IPSR_MSEL(IP7_23_21, SCIFA1_TXD_B, SEL_SCIFA1_1), + PINMUX_IPSR_MSEL(IP7_23_21, MSIOF2_SS1_B, SEL_SOF2_1), PINMUX_IPSR_DATA(IP7_26_24, DU1_DG1), PINMUX_IPSR_DATA(IP7_26_24, LCDOUT9), - PINMUX_IPSR_MODSEL_DATA(IP7_26_24, VI1_DATA3_B, SEL_VI1_1), - PINMUX_IPSR_MODSEL_DATA(IP7_26_24, RX1_B, SEL_SCIF1_1), - PINMUX_IPSR_MODSEL_DATA(IP7_26_24, SCIFA1_RXD_B, SEL_SCIFA1_1), - PINMUX_IPSR_MODSEL_DATA(IP7_26_24, MSIOF2_SS2_B, SEL_SOF2_1), + PINMUX_IPSR_MSEL(IP7_26_24, VI1_DATA3_B, SEL_VI1_1), + PINMUX_IPSR_MSEL(IP7_26_24, RX1_B, SEL_SCIF1_1), + PINMUX_IPSR_MSEL(IP7_26_24, SCIFA1_RXD_B, SEL_SCIFA1_1), + PINMUX_IPSR_MSEL(IP7_26_24, MSIOF2_SS2_B, SEL_SOF2_1), PINMUX_IPSR_DATA(IP7_29_27, DU1_DG2), PINMUX_IPSR_DATA(IP7_29_27, LCDOUT10), - PINMUX_IPSR_MODSEL_DATA(IP7_29_27, VI1_DATA4_B, SEL_VI1_1), + PINMUX_IPSR_MSEL(IP7_29_27, VI1_DATA4_B, SEL_VI1_1), PINMUX_IPSR_DATA(IP7_29_27, SCIF1_SCK_B), - PINMUX_IPSR_MODSEL_DATA(IP7_29_27, SCIFA1_SCK, SEL_SCIFA1_0), - PINMUX_IPSR_MODSEL_DATA(IP7_29_27, SSI_SCK78_B, SEL_SSI7_1), + PINMUX_IPSR_MSEL(IP7_29_27, SCIFA1_SCK, SEL_SCIFA1_0), + PINMUX_IPSR_MSEL(IP7_29_27, SSI_SCK78_B, SEL_SSI7_1), /* IPSR8 */ PINMUX_IPSR_DATA(IP8_2_0, DU1_DG3), PINMUX_IPSR_DATA(IP8_2_0, LCDOUT11), - PINMUX_IPSR_MODSEL_DATA(IP8_2_0, VI1_DATA5_B, SEL_VI1_1), - PINMUX_IPSR_MODSEL_DATA(IP8_2_0, SSI_WS78_B, SEL_SSI7_1), + PINMUX_IPSR_MSEL(IP8_2_0, VI1_DATA5_B, SEL_VI1_1), + PINMUX_IPSR_MSEL(IP8_2_0, SSI_WS78_B, SEL_SSI7_1), PINMUX_IPSR_DATA(IP8_5_3, DU1_DG4), PINMUX_IPSR_DATA(IP8_5_3, LCDOUT12), - PINMUX_IPSR_MODSEL_DATA(IP8_5_3, VI1_DATA6_B, SEL_VI1_1), - PINMUX_IPSR_MODSEL_DATA(IP8_5_3, HRX0_B, SEL_HSCIF0_1), - PINMUX_IPSR_MODSEL_DATA(IP8_5_3, SCIFB2_RXD_B, SEL_SCIFB2_1), - PINMUX_IPSR_MODSEL_DATA(IP8_5_3, SSI_SDATA7_B, SEL_SSI7_1), + PINMUX_IPSR_MSEL(IP8_5_3, VI1_DATA6_B, SEL_VI1_1), + PINMUX_IPSR_MSEL(IP8_5_3, HRX0_B, SEL_HSCIF0_1), + PINMUX_IPSR_MSEL(IP8_5_3, SCIFB2_RXD_B, SEL_SCIFB2_1), + PINMUX_IPSR_MSEL(IP8_5_3, SSI_SDATA7_B, SEL_SSI7_1), PINMUX_IPSR_DATA(IP8_8_6, DU1_DG5), PINMUX_IPSR_DATA(IP8_8_6, LCDOUT13), - PINMUX_IPSR_MODSEL_DATA(IP8_8_6, VI1_DATA7_B, SEL_VI1_1), - PINMUX_IPSR_MODSEL_DATA(IP8_8_6, HCTS0_N_B, SEL_HSCIF0_1), - PINMUX_IPSR_MODSEL_DATA(IP8_8_6, SCIFB2_TXD_B, SEL_SCIFB2_1), - PINMUX_IPSR_MODSEL_DATA(IP8_8_6, SSI_SDATA8_B, SEL_SSI8_1), + PINMUX_IPSR_MSEL(IP8_8_6, VI1_DATA7_B, SEL_VI1_1), + PINMUX_IPSR_MSEL(IP8_8_6, HCTS0_N_B, SEL_HSCIF0_1), + PINMUX_IPSR_MSEL(IP8_8_6, SCIFB2_TXD_B, SEL_SCIFB2_1), + PINMUX_IPSR_MSEL(IP8_8_6, SSI_SDATA8_B, SEL_SSI8_1), PINMUX_IPSR_DATA(IP8_11_9, DU1_DG6), PINMUX_IPSR_DATA(IP8_11_9, LCDOUT14), - PINMUX_IPSR_MODSEL_DATA(IP8_11_9, HRTS0_N_B, SEL_HSCIF0_1), - PINMUX_IPSR_MODSEL_DATA(IP8_11_9, SCIFB2_CTS_N_B, SEL_SCIFB2_1), - PINMUX_IPSR_MODSEL_DATA(IP8_11_9, SSI_SCK9_B, SEL_SSI9_1), + PINMUX_IPSR_MSEL(IP8_11_9, HRTS0_N_B, SEL_HSCIF0_1), + PINMUX_IPSR_MSEL(IP8_11_9, SCIFB2_CTS_N_B, SEL_SCIFB2_1), + PINMUX_IPSR_MSEL(IP8_11_9, SSI_SCK9_B, SEL_SSI9_1), PINMUX_IPSR_DATA(IP8_14_12, DU1_DG7), PINMUX_IPSR_DATA(IP8_14_12, LCDOUT15), - PINMUX_IPSR_MODSEL_DATA(IP8_14_12, HTX0_B, SEL_HSCIF0_1), - PINMUX_IPSR_MODSEL_DATA(IP8_14_12, SCIFB2_RTS_N_B, SEL_SCIFB2_1), - PINMUX_IPSR_MODSEL_DATA(IP8_14_12, SSI_WS9_B, SEL_SSI9_1), + PINMUX_IPSR_MSEL(IP8_14_12, HTX0_B, SEL_HSCIF0_1), + PINMUX_IPSR_MSEL(IP8_14_12, SCIFB2_RTS_N_B, SEL_SCIFB2_1), + PINMUX_IPSR_MSEL(IP8_14_12, SSI_WS9_B, SEL_SSI9_1), PINMUX_IPSR_DATA(IP8_17_15, DU1_DB0), PINMUX_IPSR_DATA(IP8_17_15, LCDOUT16), - PINMUX_IPSR_MODSEL_DATA(IP8_17_15, VI1_CLK_B, SEL_VI1_1), - PINMUX_IPSR_MODSEL_DATA(IP8_17_15, TX2_B, SEL_SCIF2_1), - PINMUX_IPSR_MODSEL_DATA(IP8_17_15, SCIFA2_TXD_B, SEL_SCIFA2_1), - PINMUX_IPSR_MODSEL_DATA(IP8_17_15, MSIOF2_TXD_B, SEL_SOF2_1), + PINMUX_IPSR_MSEL(IP8_17_15, VI1_CLK_B, SEL_VI1_1), + PINMUX_IPSR_MSEL(IP8_17_15, TX2_B, SEL_SCIF2_1), + PINMUX_IPSR_MSEL(IP8_17_15, SCIFA2_TXD_B, SEL_SCIFA2_1), + PINMUX_IPSR_MSEL(IP8_17_15, MSIOF2_TXD_B, SEL_SOF2_1), PINMUX_IPSR_DATA(IP8_20_18, DU1_DB1), PINMUX_IPSR_DATA(IP8_20_18, LCDOUT17), - PINMUX_IPSR_MODSEL_DATA(IP8_20_18, VI1_HSYNC_N_B, SEL_VI1_1), - PINMUX_IPSR_MODSEL_DATA(IP8_20_18, RX2_B, SEL_SCIF2_1), - PINMUX_IPSR_MODSEL_DATA(IP8_20_18, SCIFA2_RXD_B, SEL_SCIFA2_1), - PINMUX_IPSR_MODSEL_DATA(IP8_20_18, MSIOF2_RXD_B, SEL_SOF2_1), + PINMUX_IPSR_MSEL(IP8_20_18, VI1_HSYNC_N_B, SEL_VI1_1), + PINMUX_IPSR_MSEL(IP8_20_18, RX2_B, SEL_SCIF2_1), + PINMUX_IPSR_MSEL(IP8_20_18, SCIFA2_RXD_B, SEL_SCIFA2_1), + PINMUX_IPSR_MSEL(IP8_20_18, MSIOF2_RXD_B, SEL_SOF2_1), PINMUX_IPSR_DATA(IP8_23_21, DU1_DB2), PINMUX_IPSR_DATA(IP8_23_21, LCDOUT18), - PINMUX_IPSR_MODSEL_DATA(IP8_23_21, VI1_VSYNC_N_B, SEL_VI1_1), + PINMUX_IPSR_MSEL(IP8_23_21, VI1_VSYNC_N_B, SEL_VI1_1), PINMUX_IPSR_DATA(IP8_23_21, SCIF2_SCK_B), - PINMUX_IPSR_MODSEL_DATA(IP8_23_21, SCIFA2_SCK, SEL_SCIFA2_1), - PINMUX_IPSR_MODSEL_DATA(IP8_23_21, SSI_SDATA9_B, SEL_SSI9_1), + PINMUX_IPSR_MSEL(IP8_23_21, SCIFA2_SCK, SEL_SCIFA2_1), + PINMUX_IPSR_MSEL(IP8_23_21, SSI_SDATA9_B, SEL_SSI9_1), PINMUX_IPSR_DATA(IP8_25_24, DU1_DB3), PINMUX_IPSR_DATA(IP8_25_24, LCDOUT19), - PINMUX_IPSR_MODSEL_DATA(IP8_25_24, VI1_CLKENB_B, SEL_VI1_1), + PINMUX_IPSR_MSEL(IP8_25_24, VI1_CLKENB_B, SEL_VI1_1), PINMUX_IPSR_DATA(IP8_27_26, DU1_DB4), PINMUX_IPSR_DATA(IP8_27_26, LCDOUT20), - PINMUX_IPSR_MODSEL_DATA(IP8_27_26, VI1_FIELD_B, SEL_VI1_1), - PINMUX_IPSR_MODSEL_DATA(IP8_27_26, CAN1_RX, SEL_CAN1_0), + PINMUX_IPSR_MSEL(IP8_27_26, VI1_FIELD_B, SEL_VI1_1), + PINMUX_IPSR_MSEL(IP8_27_26, CAN1_RX, SEL_CAN1_0), PINMUX_IPSR_DATA(IP8_30_28, DU1_DB5), PINMUX_IPSR_DATA(IP8_30_28, LCDOUT21), - PINMUX_IPSR_MODSEL_DATA(IP8_30_28, TX3, SEL_SCIF3_0), - PINMUX_IPSR_MODSEL_DATA(IP8_30_28, SCIFA3_TXD, SEL_SCIFA3_0), - PINMUX_IPSR_MODSEL_DATA(IP8_30_28, CAN1_TX, SEL_CAN1_0), + PINMUX_IPSR_MSEL(IP8_30_28, TX3, SEL_SCIF3_0), + PINMUX_IPSR_MSEL(IP8_30_28, SCIFA3_TXD, SEL_SCIFA3_0), + PINMUX_IPSR_MSEL(IP8_30_28, CAN1_TX, SEL_CAN1_0), /* IPSR9 */ PINMUX_IPSR_DATA(IP9_2_0, DU1_DB6), PINMUX_IPSR_DATA(IP9_2_0, LCDOUT22), - PINMUX_IPSR_MODSEL_DATA(IP9_2_0, SCL3_C, SEL_IIC3_2), - PINMUX_IPSR_MODSEL_DATA(IP9_2_0, RX3, SEL_SCIF3_0), - PINMUX_IPSR_MODSEL_DATA(IP9_2_0, SCIFA3_RXD, SEL_SCIFA3_0), + PINMUX_IPSR_MSEL(IP9_2_0, SCL3_C, SEL_IIC3_2), + PINMUX_IPSR_MSEL(IP9_2_0, RX3, SEL_SCIF3_0), + PINMUX_IPSR_MSEL(IP9_2_0, SCIFA3_RXD, SEL_SCIFA3_0), PINMUX_IPSR_DATA(IP9_5_3, DU1_DB7), PINMUX_IPSR_DATA(IP9_5_3, LCDOUT23), - PINMUX_IPSR_MODSEL_DATA(IP9_5_3, SDA3_C, SEL_IIC3_2), - PINMUX_IPSR_MODSEL_DATA(IP9_5_3, SCIF3_SCK, SEL_SCIF3_0), - PINMUX_IPSR_MODSEL_DATA(IP9_5_3, SCIFA3_SCK, SEL_SCIFA3_0), - PINMUX_IPSR_MODSEL_DATA(IP9_6, DU1_DOTCLKIN, SEL_DIS_0), + PINMUX_IPSR_MSEL(IP9_5_3, SDA3_C, SEL_IIC3_2), + PINMUX_IPSR_MSEL(IP9_5_3, SCIF3_SCK, SEL_SCIF3_0), + PINMUX_IPSR_MSEL(IP9_5_3, SCIFA3_SCK, SEL_SCIFA3_0), + PINMUX_IPSR_MSEL(IP9_6, DU1_DOTCLKIN, SEL_DIS_0), PINMUX_IPSR_DATA(IP9_6, QSTVA_QVS), PINMUX_IPSR_DATA(IP9_7, DU1_DOTCLKOUT0), PINMUX_IPSR_DATA(IP9_7, QCLK), PINMUX_IPSR_DATA(IP9_10_8, DU1_DOTCLKOUT1), PINMUX_IPSR_DATA(IP9_10_8, QSTVB_QVE), - PINMUX_IPSR_MODSEL_DATA(IP9_10_8, CAN0_TX, SEL_CAN0_0), - PINMUX_IPSR_MODSEL_DATA(IP9_10_8, TX3_B, SEL_SCIF3_1), - PINMUX_IPSR_MODSEL_DATA(IP9_10_8, SCL2_B, SEL_IIC2_1), + PINMUX_IPSR_MSEL(IP9_10_8, CAN0_TX, SEL_CAN0_0), + PINMUX_IPSR_MSEL(IP9_10_8, TX3_B, SEL_SCIF3_1), + PINMUX_IPSR_MSEL(IP9_10_8, SCL2_B, SEL_IIC2_1), PINMUX_IPSR_DATA(IP9_10_8, PWM4), PINMUX_IPSR_DATA(IP9_11, DU1_EXHSYNC_DU1_HSYNC), PINMUX_IPSR_DATA(IP9_11, QSTH_QHS), @@ -1284,280 +1284,280 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_DATA(IP9_12, QSTB_QHE), PINMUX_IPSR_DATA(IP9_15_13, DU1_EXODDF_DU1_ODDF_DISP_CDE), PINMUX_IPSR_DATA(IP9_15_13, QCPV_QDE), - PINMUX_IPSR_MODSEL_DATA(IP9_15_13, CAN0_RX, SEL_CAN0_0), - PINMUX_IPSR_MODSEL_DATA(IP9_15_13, RX3_B, SEL_SCIF3_1), - PINMUX_IPSR_MODSEL_DATA(IP9_15_13, SDA2_B, SEL_IIC2_1), + PINMUX_IPSR_MSEL(IP9_15_13, CAN0_RX, SEL_CAN0_0), + PINMUX_IPSR_MSEL(IP9_15_13, RX3_B, SEL_SCIF3_1), + PINMUX_IPSR_MSEL(IP9_15_13, SDA2_B, SEL_IIC2_1), PINMUX_IPSR_DATA(IP9_16, DU1_DISP), PINMUX_IPSR_DATA(IP9_16, QPOLA), PINMUX_IPSR_DATA(IP9_18_17, DU1_CDE), PINMUX_IPSR_DATA(IP9_18_17, QPOLB), PINMUX_IPSR_DATA(IP9_18_17, PWM4_B), PINMUX_IPSR_DATA(IP9_20_19, VI0_CLKENB), - PINMUX_IPSR_MODSEL_DATA(IP9_20_19, TX4, SEL_SCIF4_0), - PINMUX_IPSR_MODSEL_DATA(IP9_20_19, SCIFA4_TXD, SEL_SCIFA4_0), - PINMUX_IPSR_MODSEL_DATA(IP9_20_19, TS_SDATA0_D, SEL_TSIF0_3), + PINMUX_IPSR_MSEL(IP9_20_19, TX4, SEL_SCIF4_0), + PINMUX_IPSR_MSEL(IP9_20_19, SCIFA4_TXD, SEL_SCIFA4_0), + PINMUX_IPSR_MSEL(IP9_20_19, TS_SDATA0_D, SEL_TSIF0_3), PINMUX_IPSR_DATA(IP9_22_21, VI0_FIELD), - PINMUX_IPSR_MODSEL_DATA(IP9_22_21, RX4, SEL_SCIF4_0), - PINMUX_IPSR_MODSEL_DATA(IP9_22_21, SCIFA4_RXD, SEL_SCIFA4_0), - PINMUX_IPSR_MODSEL_DATA(IP9_22_21, TS_SCK0_D, SEL_TSIF0_3), + PINMUX_IPSR_MSEL(IP9_22_21, RX4, SEL_SCIF4_0), + PINMUX_IPSR_MSEL(IP9_22_21, SCIFA4_RXD, SEL_SCIFA4_0), + PINMUX_IPSR_MSEL(IP9_22_21, TS_SCK0_D, SEL_TSIF0_3), PINMUX_IPSR_DATA(IP9_24_23, VI0_HSYNC_N), - PINMUX_IPSR_MODSEL_DATA(IP9_24_23, TX5, SEL_SCIF5_0), - PINMUX_IPSR_MODSEL_DATA(IP9_24_23, SCIFA5_TXD, SEL_SCIFA5_0), - PINMUX_IPSR_MODSEL_DATA(IP9_24_23, TS_SDEN0_D, SEL_TSIF0_3), + PINMUX_IPSR_MSEL(IP9_24_23, TX5, SEL_SCIF5_0), + PINMUX_IPSR_MSEL(IP9_24_23, SCIFA5_TXD, SEL_SCIFA5_0), + PINMUX_IPSR_MSEL(IP9_24_23, TS_SDEN0_D, SEL_TSIF0_3), PINMUX_IPSR_DATA(IP9_26_25, VI0_VSYNC_N), - PINMUX_IPSR_MODSEL_DATA(IP9_26_25, RX5, SEL_SCIF5_0), - PINMUX_IPSR_MODSEL_DATA(IP9_26_25, SCIFA5_RXD, SEL_SCIFA5_0), - PINMUX_IPSR_MODSEL_DATA(IP9_26_25, TS_SPSYNC0_D, SEL_TSIF0_3), + PINMUX_IPSR_MSEL(IP9_26_25, RX5, SEL_SCIF5_0), + PINMUX_IPSR_MSEL(IP9_26_25, SCIFA5_RXD, SEL_SCIFA5_0), + PINMUX_IPSR_MSEL(IP9_26_25, TS_SPSYNC0_D, SEL_TSIF0_3), PINMUX_IPSR_DATA(IP9_28_27, VI0_DATA3_VI0_B3), - PINMUX_IPSR_MODSEL_DATA(IP9_28_27, SCIF3_SCK_B, SEL_SCIF3_1), - PINMUX_IPSR_MODSEL_DATA(IP9_28_27, SCIFA3_SCK_B, SEL_SCIFA3_1), + PINMUX_IPSR_MSEL(IP9_28_27, SCIF3_SCK_B, SEL_SCIF3_1), + PINMUX_IPSR_MSEL(IP9_28_27, SCIFA3_SCK_B, SEL_SCIFA3_1), PINMUX_IPSR_DATA(IP9_31_29, VI0_G0), - PINMUX_IPSR_MODSEL_DATA(IP9_31_29, SCL8, SEL_IIC8_0), - PINMUX_IPSR_MODSEL_DATA(IP9_31_29, STP_IVCXO27_0_C, SEL_SSP_2), - PINMUX_IPSR_MODSEL_DATA(IP9_31_29, SCL4, SEL_IIC4_0), - PINMUX_IPSR_MODSEL_DATA(IP9_31_29, HCTS2_N, SEL_HSCIF2_0), - PINMUX_IPSR_MODSEL_DATA(IP9_31_29, SCIFB2_CTS_N, SEL_SCIFB2_0), + PINMUX_IPSR_MSEL(IP9_31_29, SCL8, SEL_IIC8_0), + PINMUX_IPSR_MSEL(IP9_31_29, STP_IVCXO27_0_C, SEL_SSP_2), + PINMUX_IPSR_MSEL(IP9_31_29, SCL4, SEL_IIC4_0), + PINMUX_IPSR_MSEL(IP9_31_29, HCTS2_N, SEL_HSCIF2_0), + PINMUX_IPSR_MSEL(IP9_31_29, SCIFB2_CTS_N, SEL_SCIFB2_0), PINMUX_IPSR_DATA(IP9_31_29, ATAWR1_N), /* IPSR10 */ PINMUX_IPSR_DATA(IP10_2_0, VI0_G1), - PINMUX_IPSR_MODSEL_DATA(IP10_2_0, SDA8, SEL_IIC8_0), - PINMUX_IPSR_MODSEL_DATA(IP10_2_0, STP_ISCLK_0_C, SEL_SSP_2), - PINMUX_IPSR_MODSEL_DATA(IP10_2_0, SDA4, SEL_IIC4_0), - PINMUX_IPSR_MODSEL_DATA(IP10_2_0, HRTS2_N, SEL_HSCIF2_0), - PINMUX_IPSR_MODSEL_DATA(IP10_2_0, SCIFB2_RTS_N, SEL_SCIFB2_0), + PINMUX_IPSR_MSEL(IP10_2_0, SDA8, SEL_IIC8_0), + PINMUX_IPSR_MSEL(IP10_2_0, STP_ISCLK_0_C, SEL_SSP_2), + PINMUX_IPSR_MSEL(IP10_2_0, SDA4, SEL_IIC4_0), + PINMUX_IPSR_MSEL(IP10_2_0, HRTS2_N, SEL_HSCIF2_0), + PINMUX_IPSR_MSEL(IP10_2_0, SCIFB2_RTS_N, SEL_SCIFB2_0), PINMUX_IPSR_DATA(IP10_2_0, ATADIR1_N), PINMUX_IPSR_DATA(IP10_5_3, VI0_G2), PINMUX_IPSR_DATA(IP10_5_3, VI2_HSYNC_N), - PINMUX_IPSR_MODSEL_DATA(IP10_5_3, STP_ISD_0_C, SEL_SSP_2), - PINMUX_IPSR_MODSEL_DATA(IP10_5_3, SCL3_B, SEL_IIC3_1), - PINMUX_IPSR_MODSEL_DATA(IP10_5_3, HSCK2, SEL_HSCIF2_0), - PINMUX_IPSR_MODSEL_DATA(IP10_5_3, SCIFB2_SCK, SEL_SCIFB2_0), + PINMUX_IPSR_MSEL(IP10_5_3, STP_ISD_0_C, SEL_SSP_2), + PINMUX_IPSR_MSEL(IP10_5_3, SCL3_B, SEL_IIC3_1), + PINMUX_IPSR_MSEL(IP10_5_3, HSCK2, SEL_HSCIF2_0), + PINMUX_IPSR_MSEL(IP10_5_3, SCIFB2_SCK, SEL_SCIFB2_0), PINMUX_IPSR_DATA(IP10_5_3, ATARD1_N), PINMUX_IPSR_DATA(IP10_8_6, VI0_G3), PINMUX_IPSR_DATA(IP10_8_6, VI2_VSYNC_N), - PINMUX_IPSR_MODSEL_DATA(IP10_8_6, STP_ISEN_0_C, SEL_SSP_2), - PINMUX_IPSR_MODSEL_DATA(IP10_8_6, SDA3_B, SEL_IIC3_1), - PINMUX_IPSR_MODSEL_DATA(IP10_8_6, HRX2, SEL_HSCIF2_0), - PINMUX_IPSR_MODSEL_DATA(IP10_8_6, SCIFB2_RXD, SEL_SCIFB2_0), + PINMUX_IPSR_MSEL(IP10_8_6, STP_ISEN_0_C, SEL_SSP_2), + PINMUX_IPSR_MSEL(IP10_8_6, SDA3_B, SEL_IIC3_1), + PINMUX_IPSR_MSEL(IP10_8_6, HRX2, SEL_HSCIF2_0), + PINMUX_IPSR_MSEL(IP10_8_6, SCIFB2_RXD, SEL_SCIFB2_0), PINMUX_IPSR_DATA(IP10_8_6, ATACS01_N), PINMUX_IPSR_DATA(IP10_11_9, VI0_G4), PINMUX_IPSR_DATA(IP10_11_9, VI2_CLKENB), - PINMUX_IPSR_MODSEL_DATA(IP10_11_9, STP_ISSYNC_0_C, SEL_SSP_2), - PINMUX_IPSR_MODSEL_DATA(IP10_11_9, HTX2, SEL_HSCIF2_0), - PINMUX_IPSR_MODSEL_DATA(IP10_11_9, SCIFB2_TXD, SEL_SCIFB2_0), - PINMUX_IPSR_MODSEL_DATA(IP10_11_9, SCIFB0_SCK_D, SEL_SCIFB_3), + PINMUX_IPSR_MSEL(IP10_11_9, STP_ISSYNC_0_C, SEL_SSP_2), + PINMUX_IPSR_MSEL(IP10_11_9, HTX2, SEL_HSCIF2_0), + PINMUX_IPSR_MSEL(IP10_11_9, SCIFB2_TXD, SEL_SCIFB2_0), + PINMUX_IPSR_MSEL(IP10_11_9, SCIFB0_SCK_D, SEL_SCIFB_3), PINMUX_IPSR_DATA(IP10_14_12, VI0_G5), PINMUX_IPSR_DATA(IP10_14_12, VI2_FIELD), - PINMUX_IPSR_MODSEL_DATA(IP10_14_12, STP_OPWM_0_C, SEL_SSP_2), - PINMUX_IPSR_MODSEL_DATA(IP10_14_12, FMCLK_D, SEL_FM_3), - PINMUX_IPSR_MODSEL_DATA(IP10_14_12, CAN0_TX_E, SEL_CAN0_4), - PINMUX_IPSR_MODSEL_DATA(IP10_14_12, HTX1_D, SEL_HSCIF1_3), - PINMUX_IPSR_MODSEL_DATA(IP10_14_12, SCIFB0_TXD_D, SEL_SCIFB_3), + PINMUX_IPSR_MSEL(IP10_14_12, STP_OPWM_0_C, SEL_SSP_2), + PINMUX_IPSR_MSEL(IP10_14_12, FMCLK_D, SEL_FM_3), + PINMUX_IPSR_MSEL(IP10_14_12, CAN0_TX_E, SEL_CAN0_4), + PINMUX_IPSR_MSEL(IP10_14_12, HTX1_D, SEL_HSCIF1_3), + PINMUX_IPSR_MSEL(IP10_14_12, SCIFB0_TXD_D, SEL_SCIFB_3), PINMUX_IPSR_DATA(IP10_16_15, VI0_G6), PINMUX_IPSR_DATA(IP10_16_15, VI2_CLK), - PINMUX_IPSR_MODSEL_DATA(IP10_16_15, BPFCLK_D, SEL_FM_3), + PINMUX_IPSR_MSEL(IP10_16_15, BPFCLK_D, SEL_FM_3), PINMUX_IPSR_DATA(IP10_18_17, VI0_G7), PINMUX_IPSR_DATA(IP10_18_17, VI2_DATA0), - PINMUX_IPSR_MODSEL_DATA(IP10_18_17, FMIN_D, SEL_FM_3), + PINMUX_IPSR_MSEL(IP10_18_17, FMIN_D, SEL_FM_3), PINMUX_IPSR_DATA(IP10_21_19, VI0_R0), PINMUX_IPSR_DATA(IP10_21_19, VI2_DATA1), - PINMUX_IPSR_MODSEL_DATA(IP10_21_19, GLO_I0_B, SEL_GPS_1), - PINMUX_IPSR_MODSEL_DATA(IP10_21_19, TS_SDATA0_C, SEL_TSIF0_2), + PINMUX_IPSR_MSEL(IP10_21_19, GLO_I0_B, SEL_GPS_1), + PINMUX_IPSR_MSEL(IP10_21_19, TS_SDATA0_C, SEL_TSIF0_2), PINMUX_IPSR_DATA(IP10_21_19, ATACS11_N), PINMUX_IPSR_DATA(IP10_24_22, VI0_R1), PINMUX_IPSR_DATA(IP10_24_22, VI2_DATA2), - PINMUX_IPSR_MODSEL_DATA(IP10_24_22, GLO_I1_B, SEL_GPS_1), - PINMUX_IPSR_MODSEL_DATA(IP10_24_22, TS_SCK0_C, SEL_TSIF0_2), + PINMUX_IPSR_MSEL(IP10_24_22, GLO_I1_B, SEL_GPS_1), + PINMUX_IPSR_MSEL(IP10_24_22, TS_SCK0_C, SEL_TSIF0_2), PINMUX_IPSR_DATA(IP10_24_22, ATAG1_N), PINMUX_IPSR_DATA(IP10_26_25, VI0_R2), PINMUX_IPSR_DATA(IP10_26_25, VI2_DATA3), - PINMUX_IPSR_MODSEL_DATA(IP10_26_25, GLO_Q0_B, SEL_GPS_1), - PINMUX_IPSR_MODSEL_DATA(IP10_26_25, TS_SDEN0_C, SEL_TSIF0_2), + PINMUX_IPSR_MSEL(IP10_26_25, GLO_Q0_B, SEL_GPS_1), + PINMUX_IPSR_MSEL(IP10_26_25, TS_SDEN0_C, SEL_TSIF0_2), PINMUX_IPSR_DATA(IP10_28_27, VI0_R3), PINMUX_IPSR_DATA(IP10_28_27, VI2_DATA4), - PINMUX_IPSR_MODSEL_DATA(IP10_28_27, GLO_Q1_B, SEL_GPS_1), - PINMUX_IPSR_MODSEL_DATA(IP10_28_27, TS_SPSYNC0_C, SEL_TSIF0_2), + PINMUX_IPSR_MSEL(IP10_28_27, GLO_Q1_B, SEL_GPS_1), + PINMUX_IPSR_MSEL(IP10_28_27, TS_SPSYNC0_C, SEL_TSIF0_2), PINMUX_IPSR_DATA(IP10_31_29, VI0_R4), PINMUX_IPSR_DATA(IP10_31_29, VI2_DATA5), - PINMUX_IPSR_MODSEL_DATA(IP10_31_29, GLO_SCLK_B, SEL_GPS_1), - PINMUX_IPSR_MODSEL_DATA(IP10_31_29, TX0_C, SEL_SCIF0_2), - PINMUX_IPSR_MODSEL_DATA(IP10_31_29, SCL1_D, SEL_IIC1_3), + PINMUX_IPSR_MSEL(IP10_31_29, GLO_SCLK_B, SEL_GPS_1), + PINMUX_IPSR_MSEL(IP10_31_29, TX0_C, SEL_SCIF0_2), + PINMUX_IPSR_MSEL(IP10_31_29, SCL1_D, SEL_IIC1_3), /* IPSR11 */ PINMUX_IPSR_DATA(IP11_2_0, VI0_R5), PINMUX_IPSR_DATA(IP11_2_0, VI2_DATA6), - PINMUX_IPSR_MODSEL_DATA(IP11_2_0, GLO_SDATA_B, SEL_GPS_1), - PINMUX_IPSR_MODSEL_DATA(IP11_2_0, RX0_C, SEL_SCIF0_2), - PINMUX_IPSR_MODSEL_DATA(IP11_2_0, SDA1_D, SEL_IIC1_3), + PINMUX_IPSR_MSEL(IP11_2_0, GLO_SDATA_B, SEL_GPS_1), + PINMUX_IPSR_MSEL(IP11_2_0, RX0_C, SEL_SCIF0_2), + PINMUX_IPSR_MSEL(IP11_2_0, SDA1_D, SEL_IIC1_3), PINMUX_IPSR_DATA(IP11_5_3, VI0_R6), PINMUX_IPSR_DATA(IP11_5_3, VI2_DATA7), - PINMUX_IPSR_MODSEL_DATA(IP11_5_3, GLO_SS_B, SEL_GPS_1), - PINMUX_IPSR_MODSEL_DATA(IP11_5_3, TX1_C, SEL_SCIF1_2), - PINMUX_IPSR_MODSEL_DATA(IP11_5_3, SCL4_B, SEL_IIC4_1), + PINMUX_IPSR_MSEL(IP11_5_3, GLO_SS_B, SEL_GPS_1), + PINMUX_IPSR_MSEL(IP11_5_3, TX1_C, SEL_SCIF1_2), + PINMUX_IPSR_MSEL(IP11_5_3, SCL4_B, SEL_IIC4_1), PINMUX_IPSR_DATA(IP11_8_6, VI0_R7), - PINMUX_IPSR_MODSEL_DATA(IP11_8_6, GLO_RFON_B, SEL_GPS_1), - PINMUX_IPSR_MODSEL_DATA(IP11_8_6, RX1_C, SEL_SCIF1_2), - PINMUX_IPSR_MODSEL_DATA(IP11_8_6, CAN0_RX_E, SEL_CAN0_4), - PINMUX_IPSR_MODSEL_DATA(IP11_8_6, SDA4_B, SEL_IIC4_1), - PINMUX_IPSR_MODSEL_DATA(IP11_8_6, HRX1_D, SEL_HSCIF1_3), - PINMUX_IPSR_MODSEL_DATA(IP11_8_6, SCIFB0_RXD_D, SEL_SCIFB_3), - PINMUX_IPSR_MODSEL_DATA(IP11_11_9, VI1_HSYNC_N, SEL_VI1_0), + PINMUX_IPSR_MSEL(IP11_8_6, GLO_RFON_B, SEL_GPS_1), + PINMUX_IPSR_MSEL(IP11_8_6, RX1_C, SEL_SCIF1_2), + PINMUX_IPSR_MSEL(IP11_8_6, CAN0_RX_E, SEL_CAN0_4), + PINMUX_IPSR_MSEL(IP11_8_6, SDA4_B, SEL_IIC4_1), + PINMUX_IPSR_MSEL(IP11_8_6, HRX1_D, SEL_HSCIF1_3), + PINMUX_IPSR_MSEL(IP11_8_6, SCIFB0_RXD_D, SEL_SCIFB_3), + PINMUX_IPSR_MSEL(IP11_11_9, VI1_HSYNC_N, SEL_VI1_0), PINMUX_IPSR_DATA(IP11_11_9, AVB_RXD0), - PINMUX_IPSR_MODSEL_DATA(IP11_11_9, TS_SDATA0_B, SEL_TSIF0_1), - PINMUX_IPSR_MODSEL_DATA(IP11_11_9, TX4_B, SEL_SCIF4_1), - PINMUX_IPSR_MODSEL_DATA(IP11_11_9, SCIFA4_TXD_B, SEL_SCIFA4_1), - PINMUX_IPSR_MODSEL_DATA(IP11_14_12, VI1_VSYNC_N, SEL_VI1_0), + PINMUX_IPSR_MSEL(IP11_11_9, TS_SDATA0_B, SEL_TSIF0_1), + PINMUX_IPSR_MSEL(IP11_11_9, TX4_B, SEL_SCIF4_1), + PINMUX_IPSR_MSEL(IP11_11_9, SCIFA4_TXD_B, SEL_SCIFA4_1), + PINMUX_IPSR_MSEL(IP11_14_12, VI1_VSYNC_N, SEL_VI1_0), PINMUX_IPSR_DATA(IP11_14_12, AVB_RXD1), - PINMUX_IPSR_MODSEL_DATA(IP11_14_12, TS_SCK0_B, SEL_TSIF0_1), - PINMUX_IPSR_MODSEL_DATA(IP11_14_12, RX4_B, SEL_SCIF4_1), - PINMUX_IPSR_MODSEL_DATA(IP11_14_12, SCIFA4_RXD_B, SEL_SCIFA4_1), - PINMUX_IPSR_MODSEL_DATA(IP11_16_15, VI1_CLKENB, SEL_VI1_0), + PINMUX_IPSR_MSEL(IP11_14_12, TS_SCK0_B, SEL_TSIF0_1), + PINMUX_IPSR_MSEL(IP11_14_12, RX4_B, SEL_SCIF4_1), + PINMUX_IPSR_MSEL(IP11_14_12, SCIFA4_RXD_B, SEL_SCIFA4_1), + PINMUX_IPSR_MSEL(IP11_16_15, VI1_CLKENB, SEL_VI1_0), PINMUX_IPSR_DATA(IP11_16_15, AVB_RXD2), - PINMUX_IPSR_MODSEL_DATA(IP11_16_15, TS_SDEN0_B, SEL_TSIF0_1), - PINMUX_IPSR_MODSEL_DATA(IP11_18_17, VI1_FIELD, SEL_VI1_0), + PINMUX_IPSR_MSEL(IP11_16_15, TS_SDEN0_B, SEL_TSIF0_1), + PINMUX_IPSR_MSEL(IP11_18_17, VI1_FIELD, SEL_VI1_0), PINMUX_IPSR_DATA(IP11_18_17, AVB_RXD3), - PINMUX_IPSR_MODSEL_DATA(IP11_18_17, TS_SPSYNC0_B, SEL_TSIF0_1), - PINMUX_IPSR_MODSEL_DATA(IP11_19, VI1_CLK, SEL_VI1_0), + PINMUX_IPSR_MSEL(IP11_18_17, TS_SPSYNC0_B, SEL_TSIF0_1), + PINMUX_IPSR_MSEL(IP11_19, VI1_CLK, SEL_VI1_0), PINMUX_IPSR_DATA(IP11_19, AVB_RXD4), - PINMUX_IPSR_MODSEL_DATA(IP11_20, VI1_DATA0, SEL_VI1_0), + PINMUX_IPSR_MSEL(IP11_20, VI1_DATA0, SEL_VI1_0), PINMUX_IPSR_DATA(IP11_20, AVB_RXD5), - PINMUX_IPSR_MODSEL_DATA(IP11_21, VI1_DATA1, SEL_VI1_0), + PINMUX_IPSR_MSEL(IP11_21, VI1_DATA1, SEL_VI1_0), PINMUX_IPSR_DATA(IP11_21, AVB_RXD6), - PINMUX_IPSR_MODSEL_DATA(IP11_22, VI1_DATA2, SEL_VI1_0), + PINMUX_IPSR_MSEL(IP11_22, VI1_DATA2, SEL_VI1_0), PINMUX_IPSR_DATA(IP11_22, AVB_RXD7), - PINMUX_IPSR_MODSEL_DATA(IP11_23, VI1_DATA3, SEL_VI1_0), + PINMUX_IPSR_MSEL(IP11_23, VI1_DATA3, SEL_VI1_0), PINMUX_IPSR_DATA(IP11_23, AVB_RX_ER), - PINMUX_IPSR_MODSEL_DATA(IP11_24, VI1_DATA4, SEL_VI1_0), + PINMUX_IPSR_MSEL(IP11_24, VI1_DATA4, SEL_VI1_0), PINMUX_IPSR_DATA(IP11_24, AVB_MDIO), - PINMUX_IPSR_MODSEL_DATA(IP11_25, VI1_DATA5, SEL_VI1_0), + PINMUX_IPSR_MSEL(IP11_25, VI1_DATA5, SEL_VI1_0), PINMUX_IPSR_DATA(IP11_25, AVB_RX_DV), - PINMUX_IPSR_MODSEL_DATA(IP11_26, VI1_DATA6, SEL_VI1_0), + PINMUX_IPSR_MSEL(IP11_26, VI1_DATA6, SEL_VI1_0), PINMUX_IPSR_DATA(IP11_26, AVB_MAGIC), - PINMUX_IPSR_MODSEL_DATA(IP11_27, VI1_DATA7, SEL_VI1_0), + PINMUX_IPSR_MSEL(IP11_27, VI1_DATA7, SEL_VI1_0), PINMUX_IPSR_DATA(IP11_27, AVB_MDC), PINMUX_IPSR_DATA(IP11_29_28, ETH_MDIO), PINMUX_IPSR_DATA(IP11_29_28, AVB_RX_CLK), - PINMUX_IPSR_MODSEL_DATA(IP11_29_28, SCL2_C, SEL_IIC2_2), + PINMUX_IPSR_MSEL(IP11_29_28, SCL2_C, SEL_IIC2_2), PINMUX_IPSR_DATA(IP11_31_30, ETH_CRS_DV), PINMUX_IPSR_DATA(IP11_31_30, AVB_LINK), - PINMUX_IPSR_MODSEL_DATA(IP11_31_30, SDA2_C, SEL_IIC2_2), + PINMUX_IPSR_MSEL(IP11_31_30, SDA2_C, SEL_IIC2_2), /* IPSR12 */ PINMUX_IPSR_DATA(IP12_1_0, ETH_RX_ER), PINMUX_IPSR_DATA(IP12_1_0, AVB_CRS), - PINMUX_IPSR_MODSEL_DATA(IP12_1_0, SCL3, SEL_IIC3_0), - PINMUX_IPSR_MODSEL_DATA(IP12_1_0, SCL7, SEL_IIC7_0), + PINMUX_IPSR_MSEL(IP12_1_0, SCL3, SEL_IIC3_0), + PINMUX_IPSR_MSEL(IP12_1_0, SCL7, SEL_IIC7_0), PINMUX_IPSR_DATA(IP12_3_2, ETH_RXD0), PINMUX_IPSR_DATA(IP12_3_2, AVB_PHY_INT), - PINMUX_IPSR_MODSEL_DATA(IP12_3_2, SDA3, SEL_IIC3_0), - PINMUX_IPSR_MODSEL_DATA(IP12_3_2, SDA7, SEL_IIC7_0), + PINMUX_IPSR_MSEL(IP12_3_2, SDA3, SEL_IIC3_0), + PINMUX_IPSR_MSEL(IP12_3_2, SDA7, SEL_IIC7_0), PINMUX_IPSR_DATA(IP12_6_4, ETH_RXD1), PINMUX_IPSR_DATA(IP12_6_4, AVB_GTXREFCLK), - PINMUX_IPSR_MODSEL_DATA(IP12_6_4, CAN0_TX_C, SEL_CAN0_2), - PINMUX_IPSR_MODSEL_DATA(IP12_6_4, SCL2_D, SEL_IIC2_3), - PINMUX_IPSR_MODSEL_DATA(IP12_6_4, MSIOF1_RXD_E, SEL_SOF1_4), + PINMUX_IPSR_MSEL(IP12_6_4, CAN0_TX_C, SEL_CAN0_2), + PINMUX_IPSR_MSEL(IP12_6_4, SCL2_D, SEL_IIC2_3), + PINMUX_IPSR_MSEL(IP12_6_4, MSIOF1_RXD_E, SEL_SOF1_4), PINMUX_IPSR_DATA(IP12_9_7, ETH_LINK), PINMUX_IPSR_DATA(IP12_9_7, AVB_TXD0), - PINMUX_IPSR_MODSEL_DATA(IP12_9_7, CAN0_RX_C, SEL_CAN0_2), - PINMUX_IPSR_MODSEL_DATA(IP12_9_7, SDA2_D, SEL_IIC2_3), - PINMUX_IPSR_MODSEL_DATA(IP12_9_7, MSIOF1_SCK_E, SEL_SOF1_4), + PINMUX_IPSR_MSEL(IP12_9_7, CAN0_RX_C, SEL_CAN0_2), + PINMUX_IPSR_MSEL(IP12_9_7, SDA2_D, SEL_IIC2_3), + PINMUX_IPSR_MSEL(IP12_9_7, MSIOF1_SCK_E, SEL_SOF1_4), PINMUX_IPSR_DATA(IP12_12_10, ETH_REFCLK), PINMUX_IPSR_DATA(IP12_12_10, AVB_TXD1), - PINMUX_IPSR_MODSEL_DATA(IP12_12_10, SCIFA3_RXD_B, SEL_SCIFA3_1), - PINMUX_IPSR_MODSEL_DATA(IP12_12_10, CAN1_RX_C, SEL_CAN1_2), - PINMUX_IPSR_MODSEL_DATA(IP12_12_10, MSIOF1_SYNC_E, SEL_SOF1_4), + PINMUX_IPSR_MSEL(IP12_12_10, SCIFA3_RXD_B, SEL_SCIFA3_1), + PINMUX_IPSR_MSEL(IP12_12_10, CAN1_RX_C, SEL_CAN1_2), + PINMUX_IPSR_MSEL(IP12_12_10, MSIOF1_SYNC_E, SEL_SOF1_4), PINMUX_IPSR_DATA(IP12_15_13, ETH_TXD1), PINMUX_IPSR_DATA(IP12_15_13, AVB_TXD2), - PINMUX_IPSR_MODSEL_DATA(IP12_15_13, SCIFA3_TXD_B, SEL_SCIFA3_1), - PINMUX_IPSR_MODSEL_DATA(IP12_15_13, CAN1_TX_C, SEL_CAN1_2), - PINMUX_IPSR_MODSEL_DATA(IP12_15_13, MSIOF1_TXD_E, SEL_SOF1_4), + PINMUX_IPSR_MSEL(IP12_15_13, SCIFA3_TXD_B, SEL_SCIFA3_1), + PINMUX_IPSR_MSEL(IP12_15_13, CAN1_TX_C, SEL_CAN1_2), + PINMUX_IPSR_MSEL(IP12_15_13, MSIOF1_TXD_E, SEL_SOF1_4), PINMUX_IPSR_DATA(IP12_17_16, ETH_TX_EN), PINMUX_IPSR_DATA(IP12_17_16, AVB_TXD3), - PINMUX_IPSR_MODSEL_DATA(IP12_17_16, TCLK1_B, SEL_TMU1_0), - PINMUX_IPSR_MODSEL_DATA(IP12_17_16, CAN_CLK_B, SEL_CANCLK_1), + PINMUX_IPSR_MSEL(IP12_17_16, TCLK1_B, SEL_TMU1_0), + PINMUX_IPSR_MSEL(IP12_17_16, CAN_CLK_B, SEL_CANCLK_1), PINMUX_IPSR_DATA(IP12_19_18, ETH_MAGIC), PINMUX_IPSR_DATA(IP12_19_18, AVB_TXD4), - PINMUX_IPSR_MODSEL_DATA(IP12_19_18, IETX_C, SEL_IEB_2), + PINMUX_IPSR_MSEL(IP12_19_18, IETX_C, SEL_IEB_2), PINMUX_IPSR_DATA(IP12_21_20, ETH_TXD0), PINMUX_IPSR_DATA(IP12_21_20, AVB_TXD5), - PINMUX_IPSR_MODSEL_DATA(IP12_21_20, IECLK_C, SEL_IEB_2), + PINMUX_IPSR_MSEL(IP12_21_20, IECLK_C, SEL_IEB_2), PINMUX_IPSR_DATA(IP12_23_22, ETH_MDC), PINMUX_IPSR_DATA(IP12_23_22, AVB_TXD6), - PINMUX_IPSR_MODSEL_DATA(IP12_23_22, IERX_C, SEL_IEB_2), - PINMUX_IPSR_MODSEL_DATA(IP12_26_24, STP_IVCXO27_0, SEL_SSP_0), + PINMUX_IPSR_MSEL(IP12_23_22, IERX_C, SEL_IEB_2), + PINMUX_IPSR_MSEL(IP12_26_24, STP_IVCXO27_0, SEL_SSP_0), PINMUX_IPSR_DATA(IP12_26_24, AVB_TXD7), - PINMUX_IPSR_MODSEL_DATA(IP12_26_24, SCIFB2_TXD_D, SEL_SCIFB2_3), - PINMUX_IPSR_MODSEL_DATA(IP12_26_24, ADIDATA_B, SEL_RAD_1), - PINMUX_IPSR_MODSEL_DATA(IP12_26_24, MSIOF0_SYNC_C, SEL_SOF0_2), - PINMUX_IPSR_MODSEL_DATA(IP12_29_27, STP_ISCLK_0, SEL_SSP_0), + PINMUX_IPSR_MSEL(IP12_26_24, SCIFB2_TXD_D, SEL_SCIFB2_3), + PINMUX_IPSR_MSEL(IP12_26_24, ADIDATA_B, SEL_RAD_1), + PINMUX_IPSR_MSEL(IP12_26_24, MSIOF0_SYNC_C, SEL_SOF0_2), + PINMUX_IPSR_MSEL(IP12_29_27, STP_ISCLK_0, SEL_SSP_0), PINMUX_IPSR_DATA(IP12_29_27, AVB_TX_EN), - PINMUX_IPSR_MODSEL_DATA(IP12_29_27, SCIFB2_RXD_D, SEL_SCIFB2_3), - PINMUX_IPSR_MODSEL_DATA(IP12_29_27, ADICS_SAMP_B, SEL_RAD_1), - PINMUX_IPSR_MODSEL_DATA(IP12_29_27, MSIOF0_SCK_C, SEL_SOF0_2), + PINMUX_IPSR_MSEL(IP12_29_27, SCIFB2_RXD_D, SEL_SCIFB2_3), + PINMUX_IPSR_MSEL(IP12_29_27, ADICS_SAMP_B, SEL_RAD_1), + PINMUX_IPSR_MSEL(IP12_29_27, MSIOF0_SCK_C, SEL_SOF0_2), /* IPSR13 */ - PINMUX_IPSR_MODSEL_DATA(IP13_2_0, STP_ISD_0, SEL_SSP_0), + PINMUX_IPSR_MSEL(IP13_2_0, STP_ISD_0, SEL_SSP_0), PINMUX_IPSR_DATA(IP13_2_0, AVB_TX_ER), - PINMUX_IPSR_MODSEL_DATA(IP13_2_0, SCIFB2_SCK_C, SEL_SCIFB2_2), - PINMUX_IPSR_MODSEL_DATA(IP13_2_0, ADICLK_B, SEL_RAD_1), - PINMUX_IPSR_MODSEL_DATA(IP13_2_0, MSIOF0_SS1_C, SEL_SOF0_2), - PINMUX_IPSR_MODSEL_DATA(IP13_4_3, STP_ISEN_0, SEL_SSP_0), + PINMUX_IPSR_MSEL(IP13_2_0, SCIFB2_SCK_C, SEL_SCIFB2_2), + PINMUX_IPSR_MSEL(IP13_2_0, ADICLK_B, SEL_RAD_1), + PINMUX_IPSR_MSEL(IP13_2_0, MSIOF0_SS1_C, SEL_SOF0_2), + PINMUX_IPSR_MSEL(IP13_4_3, STP_ISEN_0, SEL_SSP_0), PINMUX_IPSR_DATA(IP13_4_3, AVB_TX_CLK), - PINMUX_IPSR_MODSEL_DATA(IP13_4_3, ADICHS0_B, SEL_RAD_1), - PINMUX_IPSR_MODSEL_DATA(IP13_4_3, MSIOF0_SS2_C, SEL_SOF0_2), - PINMUX_IPSR_MODSEL_DATA(IP13_6_5, STP_ISSYNC_0, SEL_SSP_0), + PINMUX_IPSR_MSEL(IP13_4_3, ADICHS0_B, SEL_RAD_1), + PINMUX_IPSR_MSEL(IP13_4_3, MSIOF0_SS2_C, SEL_SOF0_2), + PINMUX_IPSR_MSEL(IP13_6_5, STP_ISSYNC_0, SEL_SSP_0), PINMUX_IPSR_DATA(IP13_6_5, AVB_COL), - PINMUX_IPSR_MODSEL_DATA(IP13_6_5, ADICHS1_B, SEL_RAD_1), - PINMUX_IPSR_MODSEL_DATA(IP13_6_5, MSIOF0_RXD_C, SEL_SOF0_2), - PINMUX_IPSR_MODSEL_DATA(IP13_9_7, STP_OPWM_0, SEL_SSP_0), + PINMUX_IPSR_MSEL(IP13_6_5, ADICHS1_B, SEL_RAD_1), + PINMUX_IPSR_MSEL(IP13_6_5, MSIOF0_RXD_C, SEL_SOF0_2), + PINMUX_IPSR_MSEL(IP13_9_7, STP_OPWM_0, SEL_SSP_0), PINMUX_IPSR_DATA(IP13_9_7, AVB_GTX_CLK), PINMUX_IPSR_DATA(IP13_9_7, PWM0_B), - PINMUX_IPSR_MODSEL_DATA(IP13_9_7, ADICHS2_B, SEL_RAD_1), - PINMUX_IPSR_MODSEL_DATA(IP13_9_7, MSIOF0_TXD_C, SEL_SOF0_2), + PINMUX_IPSR_MSEL(IP13_9_7, ADICHS2_B, SEL_RAD_1), + PINMUX_IPSR_MSEL(IP13_9_7, MSIOF0_TXD_C, SEL_SOF0_2), PINMUX_IPSR_DATA(IP13_10, SD0_CLK), - PINMUX_IPSR_MODSEL_DATA(IP13_10, SPCLK_B, SEL_QSP_1), + PINMUX_IPSR_MSEL(IP13_10, SPCLK_B, SEL_QSP_1), PINMUX_IPSR_DATA(IP13_11, SD0_CMD), - PINMUX_IPSR_MODSEL_DATA(IP13_11, MOSI_IO0_B, SEL_QSP_1), + PINMUX_IPSR_MSEL(IP13_11, MOSI_IO0_B, SEL_QSP_1), PINMUX_IPSR_DATA(IP13_12, SD0_DATA0), - PINMUX_IPSR_MODSEL_DATA(IP13_12, MISO_IO1_B, SEL_QSP_1), + PINMUX_IPSR_MSEL(IP13_12, MISO_IO1_B, SEL_QSP_1), PINMUX_IPSR_DATA(IP13_13, SD0_DATA1), - PINMUX_IPSR_MODSEL_DATA(IP13_13, IO2_B, SEL_QSP_1), + PINMUX_IPSR_MSEL(IP13_13, IO2_B, SEL_QSP_1), PINMUX_IPSR_DATA(IP13_14, SD0_DATA2), - PINMUX_IPSR_MODSEL_DATA(IP13_14, IO3_B, SEL_QSP_1), + PINMUX_IPSR_MSEL(IP13_14, IO3_B, SEL_QSP_1), PINMUX_IPSR_DATA(IP13_15, SD0_DATA3), - PINMUX_IPSR_MODSEL_DATA(IP13_15, SSL_B, SEL_QSP_1), + PINMUX_IPSR_MSEL(IP13_15, SSL_B, SEL_QSP_1), PINMUX_IPSR_DATA(IP13_18_16, SD0_CD), - PINMUX_IPSR_MODSEL_DATA(IP13_18_16, MMC_D6_B, SEL_MMC_1), - PINMUX_IPSR_MODSEL_DATA(IP13_18_16, SIM0_RST_B, SEL_SIM_1), - PINMUX_IPSR_MODSEL_DATA(IP13_18_16, CAN0_RX_F, SEL_CAN0_5), - PINMUX_IPSR_MODSEL_DATA(IP13_18_16, SCIFA5_TXD_B, SEL_SCIFA5_1), - PINMUX_IPSR_MODSEL_DATA(IP13_18_16, TX3_C, SEL_SCIF3_2), + PINMUX_IPSR_MSEL(IP13_18_16, MMC_D6_B, SEL_MMC_1), + PINMUX_IPSR_MSEL(IP13_18_16, SIM0_RST_B, SEL_SIM_1), + PINMUX_IPSR_MSEL(IP13_18_16, CAN0_RX_F, SEL_CAN0_5), + PINMUX_IPSR_MSEL(IP13_18_16, SCIFA5_TXD_B, SEL_SCIFA5_1), + PINMUX_IPSR_MSEL(IP13_18_16, TX3_C, SEL_SCIF3_2), PINMUX_IPSR_DATA(IP13_21_19, SD0_WP), - PINMUX_IPSR_MODSEL_DATA(IP13_21_19, MMC_D7_B, SEL_MMC_1), - PINMUX_IPSR_MODSEL_DATA(IP13_21_19, SIM0_D_B, SEL_SIM_1), - PINMUX_IPSR_MODSEL_DATA(IP13_21_19, CAN0_TX_F, SEL_CAN0_5), - PINMUX_IPSR_MODSEL_DATA(IP13_21_19, SCIFA5_RXD_B, SEL_SCIFA5_1), - PINMUX_IPSR_MODSEL_DATA(IP13_21_19, RX3_C, SEL_SCIF3_2), + PINMUX_IPSR_MSEL(IP13_21_19, MMC_D7_B, SEL_MMC_1), + PINMUX_IPSR_MSEL(IP13_21_19, SIM0_D_B, SEL_SIM_1), + PINMUX_IPSR_MSEL(IP13_21_19, CAN0_TX_F, SEL_CAN0_5), + PINMUX_IPSR_MSEL(IP13_21_19, SCIFA5_RXD_B, SEL_SCIFA5_1), + PINMUX_IPSR_MSEL(IP13_21_19, RX3_C, SEL_SCIF3_2), PINMUX_IPSR_DATA(IP13_22, SD1_CMD), - PINMUX_IPSR_MODSEL_DATA(IP13_22, REMOCON_B, SEL_RCN_1), + PINMUX_IPSR_MSEL(IP13_22, REMOCON_B, SEL_RCN_1), PINMUX_IPSR_DATA(IP13_24_23, SD1_DATA0), - PINMUX_IPSR_MODSEL_DATA(IP13_24_23, SPEEDIN_B, SEL_RSP_1), + PINMUX_IPSR_MSEL(IP13_24_23, SPEEDIN_B, SEL_RSP_1), PINMUX_IPSR_DATA(IP13_25, SD1_DATA1), - PINMUX_IPSR_MODSEL_DATA(IP13_25, IETX_B, SEL_IEB_1), + PINMUX_IPSR_MSEL(IP13_25, IETX_B, SEL_IEB_1), PINMUX_IPSR_DATA(IP13_26, SD1_DATA2), - PINMUX_IPSR_MODSEL_DATA(IP13_26, IECLK_B, SEL_IEB_1), + PINMUX_IPSR_MSEL(IP13_26, IECLK_B, SEL_IEB_1), PINMUX_IPSR_DATA(IP13_27, SD1_DATA3), - PINMUX_IPSR_MODSEL_DATA(IP13_27, IERX_B, SEL_IEB_1), + PINMUX_IPSR_MSEL(IP13_27, IERX_B, SEL_IEB_1), PINMUX_IPSR_DATA(IP13_30_28, SD1_CD), PINMUX_IPSR_DATA(IP13_30_28, PWM0), PINMUX_IPSR_DATA(IP13_30_28, TPU_TO0), - PINMUX_IPSR_MODSEL_DATA(IP13_30_28, SCL1_C, SEL_IIC1_2), + PINMUX_IPSR_MSEL(IP13_30_28, SCL1_C, SEL_IIC1_2), /* IPSR14 */ PINMUX_IPSR_DATA(IP14_1_0, SD1_WP), PINMUX_IPSR_DATA(IP14_1_0, PWM1_B), - PINMUX_IPSR_MODSEL_DATA(IP14_1_0, SDA1_C, SEL_IIC1_2), + PINMUX_IPSR_MSEL(IP14_1_0, SDA1_C, SEL_IIC1_2), PINMUX_IPSR_DATA(IP14_2, SD2_CLK), PINMUX_IPSR_DATA(IP14_2, MMC_CLK), PINMUX_IPSR_DATA(IP14_3, SD2_CMD), @@ -1572,123 +1572,123 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_DATA(IP14_7, MMC_D3), PINMUX_IPSR_DATA(IP14_10_8, SD2_CD), PINMUX_IPSR_DATA(IP14_10_8, MMC_D4), - PINMUX_IPSR_MODSEL_DATA(IP14_10_8, SCL8_C, SEL_IIC8_2), - PINMUX_IPSR_MODSEL_DATA(IP14_10_8, TX5_B, SEL_SCIF5_1), - PINMUX_IPSR_MODSEL_DATA(IP14_10_8, SCIFA5_TXD_C, SEL_SCIFA5_2), + PINMUX_IPSR_MSEL(IP14_10_8, SCL8_C, SEL_IIC8_2), + PINMUX_IPSR_MSEL(IP14_10_8, TX5_B, SEL_SCIF5_1), + PINMUX_IPSR_MSEL(IP14_10_8, SCIFA5_TXD_C, SEL_SCIFA5_2), PINMUX_IPSR_DATA(IP14_13_11, SD2_WP), PINMUX_IPSR_DATA(IP14_13_11, MMC_D5), - PINMUX_IPSR_MODSEL_DATA(IP14_13_11, SDA8_C, SEL_IIC8_2), - PINMUX_IPSR_MODSEL_DATA(IP14_13_11, RX5_B, SEL_SCIF5_1), - PINMUX_IPSR_MODSEL_DATA(IP14_13_11, SCIFA5_RXD_C, SEL_SCIFA5_2), - PINMUX_IPSR_MODSEL_DATA(IP14_16_14, MSIOF0_SCK, SEL_SOF0_0), - PINMUX_IPSR_MODSEL_DATA(IP14_16_14, RX2_C, SEL_SCIF2_2), - PINMUX_IPSR_MODSEL_DATA(IP14_16_14, ADIDATA, SEL_RAD_0), - PINMUX_IPSR_MODSEL_DATA(IP14_16_14, VI1_CLK_C, SEL_VI1_2), + PINMUX_IPSR_MSEL(IP14_13_11, SDA8_C, SEL_IIC8_2), + PINMUX_IPSR_MSEL(IP14_13_11, RX5_B, SEL_SCIF5_1), + PINMUX_IPSR_MSEL(IP14_13_11, SCIFA5_RXD_C, SEL_SCIFA5_2), + PINMUX_IPSR_MSEL(IP14_16_14, MSIOF0_SCK, SEL_SOF0_0), + PINMUX_IPSR_MSEL(IP14_16_14, RX2_C, SEL_SCIF2_2), + PINMUX_IPSR_MSEL(IP14_16_14, ADIDATA, SEL_RAD_0), + PINMUX_IPSR_MSEL(IP14_16_14, VI1_CLK_C, SEL_VI1_2), PINMUX_IPSR_DATA(IP14_16_14, VI1_G0_B), - PINMUX_IPSR_MODSEL_DATA(IP14_19_17, MSIOF0_SYNC, SEL_SOF0_0), - PINMUX_IPSR_MODSEL_DATA(IP14_19_17, TX2_C, SEL_SCIF2_2), - PINMUX_IPSR_MODSEL_DATA(IP14_19_17, ADICS_SAMP, SEL_RAD_0), - PINMUX_IPSR_MODSEL_DATA(IP14_19_17, VI1_CLKENB_C, SEL_VI1_2), + PINMUX_IPSR_MSEL(IP14_19_17, MSIOF0_SYNC, SEL_SOF0_0), + PINMUX_IPSR_MSEL(IP14_19_17, TX2_C, SEL_SCIF2_2), + PINMUX_IPSR_MSEL(IP14_19_17, ADICS_SAMP, SEL_RAD_0), + PINMUX_IPSR_MSEL(IP14_19_17, VI1_CLKENB_C, SEL_VI1_2), PINMUX_IPSR_DATA(IP14_19_17, VI1_G1_B), - PINMUX_IPSR_MODSEL_DATA(IP14_22_20, MSIOF0_TXD, SEL_SOF0_0), - PINMUX_IPSR_MODSEL_DATA(IP14_22_20, ADICLK, SEL_RAD_0), - PINMUX_IPSR_MODSEL_DATA(IP14_22_20, VI1_FIELD_C, SEL_VI1_2), + PINMUX_IPSR_MSEL(IP14_22_20, MSIOF0_TXD, SEL_SOF0_0), + PINMUX_IPSR_MSEL(IP14_22_20, ADICLK, SEL_RAD_0), + PINMUX_IPSR_MSEL(IP14_22_20, VI1_FIELD_C, SEL_VI1_2), PINMUX_IPSR_DATA(IP14_22_20, VI1_G2_B), - PINMUX_IPSR_MODSEL_DATA(IP14_25_23, MSIOF0_RXD, SEL_SOF0_0), - PINMUX_IPSR_MODSEL_DATA(IP14_25_23, ADICHS0, SEL_RAD_0), - PINMUX_IPSR_MODSEL_DATA(IP14_25_23, VI1_DATA0_C, SEL_VI1_2), + PINMUX_IPSR_MSEL(IP14_25_23, MSIOF0_RXD, SEL_SOF0_0), + PINMUX_IPSR_MSEL(IP14_25_23, ADICHS0, SEL_RAD_0), + PINMUX_IPSR_MSEL(IP14_25_23, VI1_DATA0_C, SEL_VI1_2), PINMUX_IPSR_DATA(IP14_25_23, VI1_G3_B), - PINMUX_IPSR_MODSEL_DATA(IP14_28_26, MSIOF0_SS1, SEL_SOF0_0), - PINMUX_IPSR_MODSEL_DATA(IP14_28_26, MMC_D6, SEL_MMC_0), - PINMUX_IPSR_MODSEL_DATA(IP14_28_26, ADICHS1, SEL_RAD_0), - PINMUX_IPSR_MODSEL_DATA(IP14_28_26, TX0_E, SEL_SCIF0_4), - PINMUX_IPSR_MODSEL_DATA(IP14_28_26, VI1_HSYNC_N_C, SEL_VI1_2), - PINMUX_IPSR_MODSEL_DATA(IP14_28_26, SCL7_C, SEL_IIC7_2), + PINMUX_IPSR_MSEL(IP14_28_26, MSIOF0_SS1, SEL_SOF0_0), + PINMUX_IPSR_MSEL(IP14_28_26, MMC_D6, SEL_MMC_0), + PINMUX_IPSR_MSEL(IP14_28_26, ADICHS1, SEL_RAD_0), + PINMUX_IPSR_MSEL(IP14_28_26, TX0_E, SEL_SCIF0_4), + PINMUX_IPSR_MSEL(IP14_28_26, VI1_HSYNC_N_C, SEL_VI1_2), + PINMUX_IPSR_MSEL(IP14_28_26, SCL7_C, SEL_IIC7_2), PINMUX_IPSR_DATA(IP14_28_26, VI1_G4_B), - PINMUX_IPSR_MODSEL_DATA(IP14_31_29, MSIOF0_SS2, SEL_SOF0_0), - PINMUX_IPSR_MODSEL_DATA(IP14_31_29, MMC_D7, SEL_MMC_0), - PINMUX_IPSR_MODSEL_DATA(IP14_31_29, ADICHS2, SEL_RAD_0), - PINMUX_IPSR_MODSEL_DATA(IP14_31_29, RX0_E, SEL_SCIF0_4), - PINMUX_IPSR_MODSEL_DATA(IP14_31_29, VI1_VSYNC_N_C, SEL_VI1_2), - PINMUX_IPSR_MODSEL_DATA(IP14_31_29, SDA7_C, SEL_IIC7_2), + PINMUX_IPSR_MSEL(IP14_31_29, MSIOF0_SS2, SEL_SOF0_0), + PINMUX_IPSR_MSEL(IP14_31_29, MMC_D7, SEL_MMC_0), + PINMUX_IPSR_MSEL(IP14_31_29, ADICHS2, SEL_RAD_0), + PINMUX_IPSR_MSEL(IP14_31_29, RX0_E, SEL_SCIF0_4), + PINMUX_IPSR_MSEL(IP14_31_29, VI1_VSYNC_N_C, SEL_VI1_2), + PINMUX_IPSR_MSEL(IP14_31_29, SDA7_C, SEL_IIC7_2), PINMUX_IPSR_DATA(IP14_31_29, VI1_G5_B), /* IPSR15 */ - PINMUX_IPSR_MODSEL_DATA(IP15_1_0, SIM0_RST, SEL_SIM_0), - PINMUX_IPSR_MODSEL_DATA(IP15_1_0, IETX, SEL_IEB_0), - PINMUX_IPSR_MODSEL_DATA(IP15_1_0, CAN1_TX_D, SEL_CAN1_3), + PINMUX_IPSR_MSEL(IP15_1_0, SIM0_RST, SEL_SIM_0), + PINMUX_IPSR_MSEL(IP15_1_0, IETX, SEL_IEB_0), + PINMUX_IPSR_MSEL(IP15_1_0, CAN1_TX_D, SEL_CAN1_3), PINMUX_IPSR_DATA(IP15_3_2, SIM0_CLK), - PINMUX_IPSR_MODSEL_DATA(IP15_3_2, IECLK, SEL_IEB_0), - PINMUX_IPSR_MODSEL_DATA(IP15_3_2, CAN_CLK_C, SEL_CANCLK_2), - PINMUX_IPSR_MODSEL_DATA(IP15_5_4, SIM0_D, SEL_SIM_0), - PINMUX_IPSR_MODSEL_DATA(IP15_5_4, IERX, SEL_IEB_0), - PINMUX_IPSR_MODSEL_DATA(IP15_5_4, CAN1_RX_D, SEL_CAN1_3), - PINMUX_IPSR_MODSEL_DATA(IP15_8_6, GPS_CLK, SEL_GPS_0), - PINMUX_IPSR_MODSEL_DATA(IP15_8_6, DU1_DOTCLKIN_C, SEL_DIS_2), - PINMUX_IPSR_MODSEL_DATA(IP15_8_6, AUDIO_CLKB_B, SEL_ADG_1), + PINMUX_IPSR_MSEL(IP15_3_2, IECLK, SEL_IEB_0), + PINMUX_IPSR_MSEL(IP15_3_2, CAN_CLK_C, SEL_CANCLK_2), + PINMUX_IPSR_MSEL(IP15_5_4, SIM0_D, SEL_SIM_0), + PINMUX_IPSR_MSEL(IP15_5_4, IERX, SEL_IEB_0), + PINMUX_IPSR_MSEL(IP15_5_4, CAN1_RX_D, SEL_CAN1_3), + PINMUX_IPSR_MSEL(IP15_8_6, GPS_CLK, SEL_GPS_0), + PINMUX_IPSR_MSEL(IP15_8_6, DU1_DOTCLKIN_C, SEL_DIS_2), + PINMUX_IPSR_MSEL(IP15_8_6, AUDIO_CLKB_B, SEL_ADG_1), PINMUX_IPSR_DATA(IP15_8_6, PWM5_B), - PINMUX_IPSR_MODSEL_DATA(IP15_8_6, SCIFA3_TXD_C, SEL_SCIFA3_2), - PINMUX_IPSR_MODSEL_DATA(IP15_11_9, GPS_SIGN, SEL_GPS_0), - PINMUX_IPSR_MODSEL_DATA(IP15_11_9, TX4_C, SEL_SCIF4_2), - PINMUX_IPSR_MODSEL_DATA(IP15_11_9, SCIFA4_TXD_C, SEL_SCIFA4_2), + PINMUX_IPSR_MSEL(IP15_8_6, SCIFA3_TXD_C, SEL_SCIFA3_2), + PINMUX_IPSR_MSEL(IP15_11_9, GPS_SIGN, SEL_GPS_0), + PINMUX_IPSR_MSEL(IP15_11_9, TX4_C, SEL_SCIF4_2), + PINMUX_IPSR_MSEL(IP15_11_9, SCIFA4_TXD_C, SEL_SCIFA4_2), PINMUX_IPSR_DATA(IP15_11_9, PWM5), PINMUX_IPSR_DATA(IP15_11_9, VI1_G6_B), - PINMUX_IPSR_MODSEL_DATA(IP15_11_9, SCIFA3_RXD_C, SEL_SCIFA3_2), - PINMUX_IPSR_MODSEL_DATA(IP15_14_12, GPS_MAG, SEL_GPS_0), - PINMUX_IPSR_MODSEL_DATA(IP15_14_12, RX4_C, SEL_SCIF4_2), - PINMUX_IPSR_MODSEL_DATA(IP15_14_12, SCIFA4_RXD_C, SEL_SCIFA4_2), + PINMUX_IPSR_MSEL(IP15_11_9, SCIFA3_RXD_C, SEL_SCIFA3_2), + PINMUX_IPSR_MSEL(IP15_14_12, GPS_MAG, SEL_GPS_0), + PINMUX_IPSR_MSEL(IP15_14_12, RX4_C, SEL_SCIF4_2), + PINMUX_IPSR_MSEL(IP15_14_12, SCIFA4_RXD_C, SEL_SCIFA4_2), PINMUX_IPSR_DATA(IP15_14_12, PWM6), PINMUX_IPSR_DATA(IP15_14_12, VI1_G7_B), - PINMUX_IPSR_MODSEL_DATA(IP15_14_12, SCIFA3_SCK_C, SEL_SCIFA3_2), - PINMUX_IPSR_MODSEL_DATA(IP15_17_15, HCTS0_N, SEL_HSCIF0_0), - PINMUX_IPSR_MODSEL_DATA(IP15_17_15, SCIFB0_CTS_N, SEL_SCIFB_0), - PINMUX_IPSR_MODSEL_DATA(IP15_17_15, GLO_I0_C, SEL_GPS_2), - PINMUX_IPSR_MODSEL_DATA(IP15_17_15, TCLK1, SEL_TMU1_0), - PINMUX_IPSR_MODSEL_DATA(IP15_17_15, VI1_DATA1_C, SEL_VI1_2), - PINMUX_IPSR_MODSEL_DATA(IP15_20_18, HRTS0_N, SEL_HSCIF0_0), - PINMUX_IPSR_MODSEL_DATA(IP15_20_18, SCIFB0_RTS_N, SEL_SCIFB_0), - PINMUX_IPSR_MODSEL_DATA(IP15_20_18, GLO_I1_C, SEL_GPS_2), - PINMUX_IPSR_MODSEL_DATA(IP15_20_18, VI1_DATA2_C, SEL_VI1_2), - PINMUX_IPSR_MODSEL_DATA(IP15_23_21, HSCK0, SEL_HSCIF0_0), - PINMUX_IPSR_MODSEL_DATA(IP15_23_21, SCIFB0_SCK, SEL_SCIFB_0), - PINMUX_IPSR_MODSEL_DATA(IP15_23_21, GLO_Q0_C, SEL_GPS_2), - PINMUX_IPSR_MODSEL_DATA(IP15_23_21, CAN_CLK, SEL_CANCLK_0), + PINMUX_IPSR_MSEL(IP15_14_12, SCIFA3_SCK_C, SEL_SCIFA3_2), + PINMUX_IPSR_MSEL(IP15_17_15, HCTS0_N, SEL_HSCIF0_0), + PINMUX_IPSR_MSEL(IP15_17_15, SCIFB0_CTS_N, SEL_SCIFB_0), + PINMUX_IPSR_MSEL(IP15_17_15, GLO_I0_C, SEL_GPS_2), + PINMUX_IPSR_MSEL(IP15_17_15, TCLK1, SEL_TMU1_0), + PINMUX_IPSR_MSEL(IP15_17_15, VI1_DATA1_C, SEL_VI1_2), + PINMUX_IPSR_MSEL(IP15_20_18, HRTS0_N, SEL_HSCIF0_0), + PINMUX_IPSR_MSEL(IP15_20_18, SCIFB0_RTS_N, SEL_SCIFB_0), + PINMUX_IPSR_MSEL(IP15_20_18, GLO_I1_C, SEL_GPS_2), + PINMUX_IPSR_MSEL(IP15_20_18, VI1_DATA2_C, SEL_VI1_2), + PINMUX_IPSR_MSEL(IP15_23_21, HSCK0, SEL_HSCIF0_0), + PINMUX_IPSR_MSEL(IP15_23_21, SCIFB0_SCK, SEL_SCIFB_0), + PINMUX_IPSR_MSEL(IP15_23_21, GLO_Q0_C, SEL_GPS_2), + PINMUX_IPSR_MSEL(IP15_23_21, CAN_CLK, SEL_CANCLK_0), PINMUX_IPSR_DATA(IP15_23_21, TCLK2), - PINMUX_IPSR_MODSEL_DATA(IP15_23_21, VI1_DATA3_C, SEL_VI1_2), - PINMUX_IPSR_MODSEL_DATA(IP15_26_24, HRX0, SEL_HSCIF0_0), - PINMUX_IPSR_MODSEL_DATA(IP15_26_24, SCIFB0_RXD, SEL_SCIFB_0), - PINMUX_IPSR_MODSEL_DATA(IP15_26_24, GLO_Q1_C, SEL_GPS_2), - PINMUX_IPSR_MODSEL_DATA(IP15_26_24, CAN0_RX_B, SEL_CAN0_1), - PINMUX_IPSR_MODSEL_DATA(IP15_26_24, VI1_DATA4_C, SEL_VI1_2), - PINMUX_IPSR_MODSEL_DATA(IP15_29_27, HTX0, SEL_HSCIF0_0), - PINMUX_IPSR_MODSEL_DATA(IP15_29_27, SCIFB0_TXD, SEL_SCIFB_0), - PINMUX_IPSR_MODSEL_DATA(IP15_29_27, GLO_SCLK_C, SEL_GPS_2), - PINMUX_IPSR_MODSEL_DATA(IP15_29_27, CAN0_TX_B, SEL_CAN0_1), - PINMUX_IPSR_MODSEL_DATA(IP15_29_27, VI1_DATA5_C, SEL_VI1_2), + PINMUX_IPSR_MSEL(IP15_23_21, VI1_DATA3_C, SEL_VI1_2), + PINMUX_IPSR_MSEL(IP15_26_24, HRX0, SEL_HSCIF0_0), + PINMUX_IPSR_MSEL(IP15_26_24, SCIFB0_RXD, SEL_SCIFB_0), + PINMUX_IPSR_MSEL(IP15_26_24, GLO_Q1_C, SEL_GPS_2), + PINMUX_IPSR_MSEL(IP15_26_24, CAN0_RX_B, SEL_CAN0_1), + PINMUX_IPSR_MSEL(IP15_26_24, VI1_DATA4_C, SEL_VI1_2), + PINMUX_IPSR_MSEL(IP15_29_27, HTX0, SEL_HSCIF0_0), + PINMUX_IPSR_MSEL(IP15_29_27, SCIFB0_TXD, SEL_SCIFB_0), + PINMUX_IPSR_MSEL(IP15_29_27, GLO_SCLK_C, SEL_GPS_2), + PINMUX_IPSR_MSEL(IP15_29_27, CAN0_TX_B, SEL_CAN0_1), + PINMUX_IPSR_MSEL(IP15_29_27, VI1_DATA5_C, SEL_VI1_2), /* IPSR16 */ - PINMUX_IPSR_MODSEL_DATA(IP16_2_0, HRX1, SEL_HSCIF1_0), - PINMUX_IPSR_MODSEL_DATA(IP16_2_0, SCIFB1_RXD, SEL_SCIFB1_0), + PINMUX_IPSR_MSEL(IP16_2_0, HRX1, SEL_HSCIF1_0), + PINMUX_IPSR_MSEL(IP16_2_0, SCIFB1_RXD, SEL_SCIFB1_0), PINMUX_IPSR_DATA(IP16_2_0, VI1_R0_B), - PINMUX_IPSR_MODSEL_DATA(IP16_2_0, GLO_SDATA_C, SEL_GPS_2), - PINMUX_IPSR_MODSEL_DATA(IP16_2_0, VI1_DATA6_C, SEL_VI1_2), - PINMUX_IPSR_MODSEL_DATA(IP16_5_3, HTX1, SEL_HSCIF1_0), - PINMUX_IPSR_MODSEL_DATA(IP16_5_3, SCIFB1_TXD, SEL_SCIFB1_0), + PINMUX_IPSR_MSEL(IP16_2_0, GLO_SDATA_C, SEL_GPS_2), + PINMUX_IPSR_MSEL(IP16_2_0, VI1_DATA6_C, SEL_VI1_2), + PINMUX_IPSR_MSEL(IP16_5_3, HTX1, SEL_HSCIF1_0), + PINMUX_IPSR_MSEL(IP16_5_3, SCIFB1_TXD, SEL_SCIFB1_0), PINMUX_IPSR_DATA(IP16_5_3, VI1_R1_B), - PINMUX_IPSR_MODSEL_DATA(IP16_5_3, GLO_SS_C, SEL_GPS_2), - PINMUX_IPSR_MODSEL_DATA(IP16_5_3, VI1_DATA7_C, SEL_VI1_2), - PINMUX_IPSR_MODSEL_DATA(IP16_7_6, HSCK1, SEL_HSCIF1_0), - PINMUX_IPSR_MODSEL_DATA(IP16_7_6, SCIFB1_SCK, SEL_SCIFB1_0), + PINMUX_IPSR_MSEL(IP16_5_3, GLO_SS_C, SEL_GPS_2), + PINMUX_IPSR_MSEL(IP16_5_3, VI1_DATA7_C, SEL_VI1_2), + PINMUX_IPSR_MSEL(IP16_7_6, HSCK1, SEL_HSCIF1_0), + PINMUX_IPSR_MSEL(IP16_7_6, SCIFB1_SCK, SEL_SCIFB1_0), PINMUX_IPSR_DATA(IP16_7_6, MLB_CLK), - PINMUX_IPSR_MODSEL_DATA(IP16_7_6, GLO_RFON_C, SEL_GPS_2), - PINMUX_IPSR_MODSEL_DATA(IP16_9_8, HCTS1_N, SEL_HSCIF1_0), + PINMUX_IPSR_MSEL(IP16_7_6, GLO_RFON_C, SEL_GPS_2), + PINMUX_IPSR_MSEL(IP16_9_8, HCTS1_N, SEL_HSCIF1_0), PINMUX_IPSR_DATA(IP16_9_8, SCIFB1_CTS_N), PINMUX_IPSR_DATA(IP16_9_8, MLB_SIG), - PINMUX_IPSR_MODSEL_DATA(IP16_9_8, CAN1_TX_B, SEL_CAN1_1), - PINMUX_IPSR_MODSEL_DATA(IP16_11_10, HRTS1_N, SEL_HSCIF1_0), + PINMUX_IPSR_MSEL(IP16_9_8, CAN1_TX_B, SEL_CAN1_1), + PINMUX_IPSR_MSEL(IP16_11_10, HRTS1_N, SEL_HSCIF1_0), PINMUX_IPSR_DATA(IP16_11_10, SCIFB1_RTS_N), PINMUX_IPSR_DATA(IP16_11_10, MLB_DAT), - PINMUX_IPSR_MODSEL_DATA(IP16_11_10, CAN1_RX_B, SEL_CAN1_1), + PINMUX_IPSR_MSEL(IP16_11_10, CAN1_RX_B, SEL_CAN1_1), }; static const struct sh_pfc_pin pinmux_pins[] = { -- cgit v0.10.2 From af5132dd12c5a1fab0c2500168dfed2cbf6179b6 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Thu, 3 Sep 2015 02:50:38 +0000 Subject: pinctrl: sh-pfc: r8a7790: use PINMUX_IPSR_MSEL() Now, PINMUX_IPSR_MSEL() and PINMUX_IPSR_MODSEL_DATA() are same. Current PFC driver is very difficult to read, because macro names are using different length. PINMUX_IPSR_NOGP(ispr, ...) PINMUX_IPSR_DATA(ipsr, ...) PINMUX_IPSR_NOGM(ispr, ...) PINMUX_IPSR_NOFN(ipsr, ...) PINMUX_IPSR_MSEL(ipsr, ...) PINMUX_IPSR_MODSEL_DATA(ipsr, ...) It can be readable if we can use PINMUX_IPSR_MSEL() instead of PINMUX_IPSR_MODSEL_DATA() PINMUX_IPSR_NOGP(ispr, ...) PINMUX_IPSR_DATA(ipsr, ...) PINMUX_IPSR_NOGM(ispr, ...) PINMUX_IPSR_NOFN(ipsr, ...) PINMUX_IPSR_MSEL(ipsr, ...) Signed-off-by: Kuninori Morimoto Acked-by: Laurent Pinchart Acked-by: Linus Walleij Signed-off-by: Geert Uytterhoeven diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c index fc344a7..77a1493 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c @@ -818,103 +818,103 @@ static const u16 pinmux_data[] = { PINMUX_DATA(DU_DOTCLKIN2_MARK, FN_DU_DOTCLKIN2), PINMUX_IPSR_DATA(IP0_2_0, D0), - PINMUX_IPSR_MODSEL_DATA(IP0_2_0, MSIOF3_SCK_B, SEL_SOF3_1), - PINMUX_IPSR_MODSEL_DATA(IP0_2_0, VI3_DATA0, SEL_VI3_0), - PINMUX_IPSR_MODSEL_DATA(IP0_2_0, VI0_G4, SEL_VI0_0), - PINMUX_IPSR_MODSEL_DATA(IP0_2_0, VI0_G4_B, SEL_VI0_1), + PINMUX_IPSR_MSEL(IP0_2_0, MSIOF3_SCK_B, SEL_SOF3_1), + PINMUX_IPSR_MSEL(IP0_2_0, VI3_DATA0, SEL_VI3_0), + PINMUX_IPSR_MSEL(IP0_2_0, VI0_G4, SEL_VI0_0), + PINMUX_IPSR_MSEL(IP0_2_0, VI0_G4_B, SEL_VI0_1), PINMUX_IPSR_DATA(IP0_5_3, D1), - PINMUX_IPSR_MODSEL_DATA(IP0_5_3, MSIOF3_SYNC_B, SEL_SOF3_1), - PINMUX_IPSR_MODSEL_DATA(IP0_5_3, VI3_DATA1, SEL_VI3_0), - PINMUX_IPSR_MODSEL_DATA(IP0_5_3, VI0_G5, SEL_VI0_0), - PINMUX_IPSR_MODSEL_DATA(IP0_5_3, VI0_G5_B, SEL_VI0_1), + PINMUX_IPSR_MSEL(IP0_5_3, MSIOF3_SYNC_B, SEL_SOF3_1), + PINMUX_IPSR_MSEL(IP0_5_3, VI3_DATA1, SEL_VI3_0), + PINMUX_IPSR_MSEL(IP0_5_3, VI0_G5, SEL_VI0_0), + PINMUX_IPSR_MSEL(IP0_5_3, VI0_G5_B, SEL_VI0_1), PINMUX_IPSR_DATA(IP0_8_6, D2), - PINMUX_IPSR_MODSEL_DATA(IP0_8_6, MSIOF3_RXD_B, SEL_SOF3_1), - PINMUX_IPSR_MODSEL_DATA(IP0_8_6, VI3_DATA2, SEL_VI3_0), - PINMUX_IPSR_MODSEL_DATA(IP0_8_6, VI0_G6, SEL_VI0_0), - PINMUX_IPSR_MODSEL_DATA(IP0_8_6, VI0_G6_B, SEL_VI0_1), + PINMUX_IPSR_MSEL(IP0_8_6, MSIOF3_RXD_B, SEL_SOF3_1), + PINMUX_IPSR_MSEL(IP0_8_6, VI3_DATA2, SEL_VI3_0), + PINMUX_IPSR_MSEL(IP0_8_6, VI0_G6, SEL_VI0_0), + PINMUX_IPSR_MSEL(IP0_8_6, VI0_G6_B, SEL_VI0_1), PINMUX_IPSR_DATA(IP0_11_9, D3), - PINMUX_IPSR_MODSEL_DATA(IP0_11_9, MSIOF3_TXD_B, SEL_SOF3_1), - PINMUX_IPSR_MODSEL_DATA(IP0_11_9, VI3_DATA3, SEL_VI3_0), - PINMUX_IPSR_MODSEL_DATA(IP0_11_9, VI0_G7, SEL_VI0_0), - PINMUX_IPSR_MODSEL_DATA(IP0_11_9, VI0_G7_B, SEL_VI0_1), + PINMUX_IPSR_MSEL(IP0_11_9, MSIOF3_TXD_B, SEL_SOF3_1), + PINMUX_IPSR_MSEL(IP0_11_9, VI3_DATA3, SEL_VI3_0), + PINMUX_IPSR_MSEL(IP0_11_9, VI0_G7, SEL_VI0_0), + PINMUX_IPSR_MSEL(IP0_11_9, VI0_G7_B, SEL_VI0_1), PINMUX_IPSR_DATA(IP0_15_12, D4), - PINMUX_IPSR_MODSEL_DATA(IP0_15_12, SCIFB1_RXD_F, SEL_SCIFB1_5), - PINMUX_IPSR_MODSEL_DATA(IP0_15_12, SCIFB0_RXD_C, SEL_SCIFB_2), - PINMUX_IPSR_MODSEL_DATA(IP0_15_12, VI3_DATA4, SEL_VI3_0), - PINMUX_IPSR_MODSEL_DATA(IP0_15_12, VI0_R0, SEL_VI0_0), - PINMUX_IPSR_MODSEL_DATA(IP0_15_12, VI0_R0_B, SEL_VI0_1), - PINMUX_IPSR_MODSEL_DATA(IP0_15_12, RX0_B, SEL_SCIF0_1), + PINMUX_IPSR_MSEL(IP0_15_12, SCIFB1_RXD_F, SEL_SCIFB1_5), + PINMUX_IPSR_MSEL(IP0_15_12, SCIFB0_RXD_C, SEL_SCIFB_2), + PINMUX_IPSR_MSEL(IP0_15_12, VI3_DATA4, SEL_VI3_0), + PINMUX_IPSR_MSEL(IP0_15_12, VI0_R0, SEL_VI0_0), + PINMUX_IPSR_MSEL(IP0_15_12, VI0_R0_B, SEL_VI0_1), + PINMUX_IPSR_MSEL(IP0_15_12, RX0_B, SEL_SCIF0_1), PINMUX_IPSR_DATA(IP0_19_16, D5), - PINMUX_IPSR_MODSEL_DATA(IP0_19_16, SCIFB1_TXD_F, SEL_SCIFB1_5), - PINMUX_IPSR_MODSEL_DATA(IP0_19_16, SCIFB0_TXD_C, SEL_SCIFB_2), - PINMUX_IPSR_MODSEL_DATA(IP0_19_16, VI3_DATA5, SEL_VI3_0), - PINMUX_IPSR_MODSEL_DATA(IP0_19_16, VI0_R1, SEL_VI0_0), - PINMUX_IPSR_MODSEL_DATA(IP0_19_16, VI0_R1_B, SEL_VI0_1), - PINMUX_IPSR_MODSEL_DATA(IP0_19_16, TX0_B, SEL_SCIF0_1), + PINMUX_IPSR_MSEL(IP0_19_16, SCIFB1_TXD_F, SEL_SCIFB1_5), + PINMUX_IPSR_MSEL(IP0_19_16, SCIFB0_TXD_C, SEL_SCIFB_2), + PINMUX_IPSR_MSEL(IP0_19_16, VI3_DATA5, SEL_VI3_0), + PINMUX_IPSR_MSEL(IP0_19_16, VI0_R1, SEL_VI0_0), + PINMUX_IPSR_MSEL(IP0_19_16, VI0_R1_B, SEL_VI0_1), + PINMUX_IPSR_MSEL(IP0_19_16, TX0_B, SEL_SCIF0_1), PINMUX_IPSR_DATA(IP0_22_20, D6), - PINMUX_IPSR_MODSEL_DATA(IP0_22_20, IIC2_SCL_C, SEL_IIC2_2), - PINMUX_IPSR_MODSEL_DATA(IP0_22_20, VI3_DATA6, SEL_VI3_0), - PINMUX_IPSR_MODSEL_DATA(IP0_22_20, VI0_R2, SEL_VI0_0), - PINMUX_IPSR_MODSEL_DATA(IP0_22_20, VI0_R2_B, SEL_VI0_1), - PINMUX_IPSR_MODSEL_DATA(IP0_22_20, I2C2_SCL_C, SEL_I2C2_2), + PINMUX_IPSR_MSEL(IP0_22_20, IIC2_SCL_C, SEL_IIC2_2), + PINMUX_IPSR_MSEL(IP0_22_20, VI3_DATA6, SEL_VI3_0), + PINMUX_IPSR_MSEL(IP0_22_20, VI0_R2, SEL_VI0_0), + PINMUX_IPSR_MSEL(IP0_22_20, VI0_R2_B, SEL_VI0_1), + PINMUX_IPSR_MSEL(IP0_22_20, I2C2_SCL_C, SEL_I2C2_2), PINMUX_IPSR_DATA(IP0_26_23, D7), - PINMUX_IPSR_MODSEL_DATA(IP0_26_23, AD_DI_B, SEL_ADI_1), - PINMUX_IPSR_MODSEL_DATA(IP0_26_23, IIC2_SDA_C, SEL_IIC2_2), - PINMUX_IPSR_MODSEL_DATA(IP0_26_23, VI3_DATA7, SEL_VI3_0), - PINMUX_IPSR_MODSEL_DATA(IP0_26_23, VI0_R3, SEL_VI0_0), - PINMUX_IPSR_MODSEL_DATA(IP0_26_23, VI0_R3_B, SEL_VI0_1), - PINMUX_IPSR_MODSEL_DATA(IP0_26_23, I2C2_SDA_C, SEL_I2C2_2), - PINMUX_IPSR_MODSEL_DATA(IP0_26_23, TCLK1, SEL_TMU1_0), + PINMUX_IPSR_MSEL(IP0_26_23, AD_DI_B, SEL_ADI_1), + PINMUX_IPSR_MSEL(IP0_26_23, IIC2_SDA_C, SEL_IIC2_2), + PINMUX_IPSR_MSEL(IP0_26_23, VI3_DATA7, SEL_VI3_0), + PINMUX_IPSR_MSEL(IP0_26_23, VI0_R3, SEL_VI0_0), + PINMUX_IPSR_MSEL(IP0_26_23, VI0_R3_B, SEL_VI0_1), + PINMUX_IPSR_MSEL(IP0_26_23, I2C2_SDA_C, SEL_I2C2_2), + PINMUX_IPSR_MSEL(IP0_26_23, TCLK1, SEL_TMU1_0), PINMUX_IPSR_DATA(IP0_30_27, D8), - PINMUX_IPSR_MODSEL_DATA(IP0_30_27, SCIFA1_SCK_C, SEL_SCIFA1_2), + PINMUX_IPSR_MSEL(IP0_30_27, SCIFA1_SCK_C, SEL_SCIFA1_2), PINMUX_IPSR_DATA(IP0_30_27, AVB_TXD0), - PINMUX_IPSR_MODSEL_DATA(IP0_30_27, VI0_G0, SEL_VI0_0), - PINMUX_IPSR_MODSEL_DATA(IP0_30_27, VI0_G0_B, SEL_VI0_1), - PINMUX_IPSR_MODSEL_DATA(IP0_30_27, VI2_DATA0_VI2_B0, SEL_VI2_0), + PINMUX_IPSR_MSEL(IP0_30_27, VI0_G0, SEL_VI0_0), + PINMUX_IPSR_MSEL(IP0_30_27, VI0_G0_B, SEL_VI0_1), + PINMUX_IPSR_MSEL(IP0_30_27, VI2_DATA0_VI2_B0, SEL_VI2_0), PINMUX_IPSR_DATA(IP1_3_0, D9), - PINMUX_IPSR_MODSEL_DATA(IP1_3_0, SCIFA1_RXD_C, SEL_SCIFA1_2), + PINMUX_IPSR_MSEL(IP1_3_0, SCIFA1_RXD_C, SEL_SCIFA1_2), PINMUX_IPSR_DATA(IP1_3_0, AVB_TXD1), - PINMUX_IPSR_MODSEL_DATA(IP1_3_0, VI0_G1, SEL_VI0_0), - PINMUX_IPSR_MODSEL_DATA(IP1_3_0, VI0_G1_B, SEL_VI0_1), - PINMUX_IPSR_MODSEL_DATA(IP1_3_0, VI2_DATA1_VI2_B1, SEL_VI2_0), + PINMUX_IPSR_MSEL(IP1_3_0, VI0_G1, SEL_VI0_0), + PINMUX_IPSR_MSEL(IP1_3_0, VI0_G1_B, SEL_VI0_1), + PINMUX_IPSR_MSEL(IP1_3_0, VI2_DATA1_VI2_B1, SEL_VI2_0), PINMUX_IPSR_DATA(IP1_7_4, D10), - PINMUX_IPSR_MODSEL_DATA(IP1_7_4, SCIFA1_TXD_C, SEL_SCIFA1_2), + PINMUX_IPSR_MSEL(IP1_7_4, SCIFA1_TXD_C, SEL_SCIFA1_2), PINMUX_IPSR_DATA(IP1_7_4, AVB_TXD2), - PINMUX_IPSR_MODSEL_DATA(IP1_7_4, VI0_G2, SEL_VI0_0), - PINMUX_IPSR_MODSEL_DATA(IP1_7_4, VI0_G2_B, SEL_VI0_1), - PINMUX_IPSR_MODSEL_DATA(IP1_7_4, VI2_DATA2_VI2_B2, SEL_VI2_0), + PINMUX_IPSR_MSEL(IP1_7_4, VI0_G2, SEL_VI0_0), + PINMUX_IPSR_MSEL(IP1_7_4, VI0_G2_B, SEL_VI0_1), + PINMUX_IPSR_MSEL(IP1_7_4, VI2_DATA2_VI2_B2, SEL_VI2_0), PINMUX_IPSR_DATA(IP1_11_8, D11), - PINMUX_IPSR_MODSEL_DATA(IP1_11_8, SCIFA1_CTS_N_C, SEL_SCIFA1_2), + PINMUX_IPSR_MSEL(IP1_11_8, SCIFA1_CTS_N_C, SEL_SCIFA1_2), PINMUX_IPSR_DATA(IP1_11_8, AVB_TXD3), - PINMUX_IPSR_MODSEL_DATA(IP1_11_8, VI0_G3, SEL_VI0_0), - PINMUX_IPSR_MODSEL_DATA(IP1_11_8, VI0_G3_B, SEL_VI0_1), - PINMUX_IPSR_MODSEL_DATA(IP1_11_8, VI2_DATA3_VI2_B3, SEL_VI2_0), + PINMUX_IPSR_MSEL(IP1_11_8, VI0_G3, SEL_VI0_0), + PINMUX_IPSR_MSEL(IP1_11_8, VI0_G3_B, SEL_VI0_1), + PINMUX_IPSR_MSEL(IP1_11_8, VI2_DATA3_VI2_B3, SEL_VI2_0), PINMUX_IPSR_DATA(IP1_14_12, D12), - PINMUX_IPSR_MODSEL_DATA(IP1_14_12, SCIFA1_RTS_N_C, SEL_SCIFA1_2), + PINMUX_IPSR_MSEL(IP1_14_12, SCIFA1_RTS_N_C, SEL_SCIFA1_2), PINMUX_IPSR_DATA(IP1_14_12, AVB_TXD4), - PINMUX_IPSR_MODSEL_DATA(IP1_14_12, VI0_HSYNC_N, SEL_VI0_0), - PINMUX_IPSR_MODSEL_DATA(IP1_14_12, VI0_HSYNC_N_B, SEL_VI0_1), - PINMUX_IPSR_MODSEL_DATA(IP1_14_12, VI2_DATA4_VI2_B4, SEL_VI2_0), + PINMUX_IPSR_MSEL(IP1_14_12, VI0_HSYNC_N, SEL_VI0_0), + PINMUX_IPSR_MSEL(IP1_14_12, VI0_HSYNC_N_B, SEL_VI0_1), + PINMUX_IPSR_MSEL(IP1_14_12, VI2_DATA4_VI2_B4, SEL_VI2_0), PINMUX_IPSR_DATA(IP1_17_15, D13), PINMUX_IPSR_DATA(IP1_17_15, AVB_TXD5), - PINMUX_IPSR_MODSEL_DATA(IP1_17_15, VI0_VSYNC_N, SEL_VI0_0), - PINMUX_IPSR_MODSEL_DATA(IP1_17_15, VI0_VSYNC_N_B, SEL_VI0_1), - PINMUX_IPSR_MODSEL_DATA(IP1_17_15, VI2_DATA5_VI2_B5, SEL_VI2_0), + PINMUX_IPSR_MSEL(IP1_17_15, VI0_VSYNC_N, SEL_VI0_0), + PINMUX_IPSR_MSEL(IP1_17_15, VI0_VSYNC_N_B, SEL_VI0_1), + PINMUX_IPSR_MSEL(IP1_17_15, VI2_DATA5_VI2_B5, SEL_VI2_0), PINMUX_IPSR_DATA(IP1_21_18, D14), - PINMUX_IPSR_MODSEL_DATA(IP1_21_18, SCIFB1_RXD_C, SEL_SCIFB1_2), + PINMUX_IPSR_MSEL(IP1_21_18, SCIFB1_RXD_C, SEL_SCIFB1_2), PINMUX_IPSR_DATA(IP1_21_18, AVB_TXD6), - PINMUX_IPSR_MODSEL_DATA(IP1_21_18, RX1_B, SEL_SCIF1_1), - PINMUX_IPSR_MODSEL_DATA(IP1_21_18, VI0_CLKENB, SEL_VI0_0), - PINMUX_IPSR_MODSEL_DATA(IP1_21_18, VI0_CLKENB_B, SEL_VI0_1), - PINMUX_IPSR_MODSEL_DATA(IP1_21_18, VI2_DATA6_VI2_B6, SEL_VI2_0), + PINMUX_IPSR_MSEL(IP1_21_18, RX1_B, SEL_SCIF1_1), + PINMUX_IPSR_MSEL(IP1_21_18, VI0_CLKENB, SEL_VI0_0), + PINMUX_IPSR_MSEL(IP1_21_18, VI0_CLKENB_B, SEL_VI0_1), + PINMUX_IPSR_MSEL(IP1_21_18, VI2_DATA6_VI2_B6, SEL_VI2_0), PINMUX_IPSR_DATA(IP1_25_22, D15), - PINMUX_IPSR_MODSEL_DATA(IP1_25_22, SCIFB1_TXD_C, SEL_SCIFB1_2), + PINMUX_IPSR_MSEL(IP1_25_22, SCIFB1_TXD_C, SEL_SCIFB1_2), PINMUX_IPSR_DATA(IP1_25_22, AVB_TXD7), - PINMUX_IPSR_MODSEL_DATA(IP1_25_22, TX1_B, SEL_SCIF1_1), - PINMUX_IPSR_MODSEL_DATA(IP1_25_22, VI0_FIELD, SEL_VI0_0), - PINMUX_IPSR_MODSEL_DATA(IP1_25_22, VI0_FIELD_B, SEL_VI0_1), - PINMUX_IPSR_MODSEL_DATA(IP1_25_22, VI2_DATA7_VI2_B7, SEL_VI2_0), + PINMUX_IPSR_MSEL(IP1_25_22, TX1_B, SEL_SCIF1_1), + PINMUX_IPSR_MSEL(IP1_25_22, VI0_FIELD, SEL_VI0_0), + PINMUX_IPSR_MSEL(IP1_25_22, VI0_FIELD_B, SEL_VI0_1), + PINMUX_IPSR_MSEL(IP1_25_22, VI2_DATA7_VI2_B7, SEL_VI2_0), PINMUX_IPSR_DATA(IP1_27_26, A0), PINMUX_IPSR_DATA(IP1_27_26, PWM3), PINMUX_IPSR_DATA(IP1_29_28, A1), @@ -922,512 +922,512 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_DATA(IP2_2_0, A2), PINMUX_IPSR_DATA(IP2_2_0, PWM5), - PINMUX_IPSR_MODSEL_DATA(IP2_2_0, MSIOF1_SS1_B, SEL_SOF1_1), + PINMUX_IPSR_MSEL(IP2_2_0, MSIOF1_SS1_B, SEL_SOF1_1), PINMUX_IPSR_DATA(IP2_5_3, A3), PINMUX_IPSR_DATA(IP2_5_3, PWM6), - PINMUX_IPSR_MODSEL_DATA(IP2_5_3, MSIOF1_SS2_B, SEL_SOF1_1), + PINMUX_IPSR_MSEL(IP2_5_3, MSIOF1_SS2_B, SEL_SOF1_1), PINMUX_IPSR_DATA(IP2_8_6, A4), - PINMUX_IPSR_MODSEL_DATA(IP2_8_6, MSIOF1_TXD_B, SEL_SOF1_1), + PINMUX_IPSR_MSEL(IP2_8_6, MSIOF1_TXD_B, SEL_SOF1_1), PINMUX_IPSR_DATA(IP2_8_6, TPU0TO0), PINMUX_IPSR_DATA(IP2_11_9, A5), - PINMUX_IPSR_MODSEL_DATA(IP2_11_9, SCIFA1_TXD_B, SEL_SCIFA1_1), + PINMUX_IPSR_MSEL(IP2_11_9, SCIFA1_TXD_B, SEL_SCIFA1_1), PINMUX_IPSR_DATA(IP2_11_9, TPU0TO1), PINMUX_IPSR_DATA(IP2_14_12, A6), - PINMUX_IPSR_MODSEL_DATA(IP2_14_12, SCIFA1_RTS_N_B, SEL_SCIFA1_1), + PINMUX_IPSR_MSEL(IP2_14_12, SCIFA1_RTS_N_B, SEL_SCIFA1_1), PINMUX_IPSR_DATA(IP2_14_12, TPU0TO2), PINMUX_IPSR_DATA(IP2_17_15, A7), - PINMUX_IPSR_MODSEL_DATA(IP2_17_15, SCIFA1_SCK_B, SEL_SCIFA1_1), + PINMUX_IPSR_MSEL(IP2_17_15, SCIFA1_SCK_B, SEL_SCIFA1_1), PINMUX_IPSR_DATA(IP2_17_15, AUDIO_CLKOUT_B), PINMUX_IPSR_DATA(IP2_17_15, TPU0TO3), PINMUX_IPSR_DATA(IP2_21_18, A8), - PINMUX_IPSR_MODSEL_DATA(IP2_21_18, SCIFA1_RXD_B, SEL_SCIFA1_1), - PINMUX_IPSR_MODSEL_DATA(IP2_21_18, SSI_SCK5_B, SEL_SSI5_1), - PINMUX_IPSR_MODSEL_DATA(IP2_21_18, VI0_R4, SEL_VI0_0), - PINMUX_IPSR_MODSEL_DATA(IP2_21_18, VI0_R4_B, SEL_VI0_1), - PINMUX_IPSR_MODSEL_DATA(IP2_21_18, SCIFB2_RXD_C, SEL_SCIFB2_2), - PINMUX_IPSR_MODSEL_DATA(IP2_21_18, RX2_B, SEL_SCIF2_1), - PINMUX_IPSR_MODSEL_DATA(IP2_21_18, VI2_DATA0_VI2_B0_B, SEL_VI2_1), + PINMUX_IPSR_MSEL(IP2_21_18, SCIFA1_RXD_B, SEL_SCIFA1_1), + PINMUX_IPSR_MSEL(IP2_21_18, SSI_SCK5_B, SEL_SSI5_1), + PINMUX_IPSR_MSEL(IP2_21_18, VI0_R4, SEL_VI0_0), + PINMUX_IPSR_MSEL(IP2_21_18, VI0_R4_B, SEL_VI0_1), + PINMUX_IPSR_MSEL(IP2_21_18, SCIFB2_RXD_C, SEL_SCIFB2_2), + PINMUX_IPSR_MSEL(IP2_21_18, RX2_B, SEL_SCIF2_1), + PINMUX_IPSR_MSEL(IP2_21_18, VI2_DATA0_VI2_B0_B, SEL_VI2_1), PINMUX_IPSR_DATA(IP2_25_22, A9), - PINMUX_IPSR_MODSEL_DATA(IP2_25_22, SCIFA1_CTS_N_B, SEL_SCIFA1_1), - PINMUX_IPSR_MODSEL_DATA(IP2_25_22, SSI_WS5_B, SEL_SSI5_1), - PINMUX_IPSR_MODSEL_DATA(IP2_25_22, VI0_R5, SEL_VI0_0), - PINMUX_IPSR_MODSEL_DATA(IP2_25_22, VI0_R5_B, SEL_VI0_1), - PINMUX_IPSR_MODSEL_DATA(IP2_25_22, SCIFB2_TXD_C, SEL_SCIFB2_2), - PINMUX_IPSR_MODSEL_DATA(IP2_25_22, TX2_B, SEL_SCIF2_1), - PINMUX_IPSR_MODSEL_DATA(IP2_25_22, VI2_DATA1_VI2_B1_B, SEL_VI2_1), + PINMUX_IPSR_MSEL(IP2_25_22, SCIFA1_CTS_N_B, SEL_SCIFA1_1), + PINMUX_IPSR_MSEL(IP2_25_22, SSI_WS5_B, SEL_SSI5_1), + PINMUX_IPSR_MSEL(IP2_25_22, VI0_R5, SEL_VI0_0), + PINMUX_IPSR_MSEL(IP2_25_22, VI0_R5_B, SEL_VI0_1), + PINMUX_IPSR_MSEL(IP2_25_22, SCIFB2_TXD_C, SEL_SCIFB2_2), + PINMUX_IPSR_MSEL(IP2_25_22, TX2_B, SEL_SCIF2_1), + PINMUX_IPSR_MSEL(IP2_25_22, VI2_DATA1_VI2_B1_B, SEL_VI2_1), PINMUX_IPSR_DATA(IP2_28_26, A10), - PINMUX_IPSR_MODSEL_DATA(IP2_28_26, SSI_SDATA5_B, SEL_SSI5_1), + PINMUX_IPSR_MSEL(IP2_28_26, SSI_SDATA5_B, SEL_SSI5_1), PINMUX_IPSR_DATA(IP2_28_26, MSIOF2_SYNC), - PINMUX_IPSR_MODSEL_DATA(IP2_28_26, VI0_R6, SEL_VI0_0), - PINMUX_IPSR_MODSEL_DATA(IP2_28_26, VI0_R6_B, SEL_VI0_1), - PINMUX_IPSR_MODSEL_DATA(IP2_28_26, VI2_DATA2_VI2_B2_B, SEL_VI2_1), + PINMUX_IPSR_MSEL(IP2_28_26, VI0_R6, SEL_VI0_0), + PINMUX_IPSR_MSEL(IP2_28_26, VI0_R6_B, SEL_VI0_1), + PINMUX_IPSR_MSEL(IP2_28_26, VI2_DATA2_VI2_B2_B, SEL_VI2_1), PINMUX_IPSR_DATA(IP3_3_0, A11), - PINMUX_IPSR_MODSEL_DATA(IP3_3_0, SCIFB2_CTS_N_B, SEL_SCIFB2_1), + PINMUX_IPSR_MSEL(IP3_3_0, SCIFB2_CTS_N_B, SEL_SCIFB2_1), PINMUX_IPSR_DATA(IP3_3_0, MSIOF2_SCK), - PINMUX_IPSR_MODSEL_DATA(IP3_3_0, VI1_R0, SEL_VI1_0), - PINMUX_IPSR_MODSEL_DATA(IP3_3_0, VI1_R0_B, SEL_VI1_1), + PINMUX_IPSR_MSEL(IP3_3_0, VI1_R0, SEL_VI1_0), + PINMUX_IPSR_MSEL(IP3_3_0, VI1_R0_B, SEL_VI1_1), PINMUX_IPSR_DATA(IP3_3_0, VI2_G0), - PINMUX_IPSR_MODSEL_DATA(IP3_3_0, VI2_DATA3_VI2_B3_B, SEL_VI2_1), + PINMUX_IPSR_MSEL(IP3_3_0, VI2_DATA3_VI2_B3_B, SEL_VI2_1), PINMUX_IPSR_DATA(IP3_7_4, A12), - PINMUX_IPSR_MODSEL_DATA(IP3_7_4, SCIFB2_RXD_B, SEL_SCIFB2_1), + PINMUX_IPSR_MSEL(IP3_7_4, SCIFB2_RXD_B, SEL_SCIFB2_1), PINMUX_IPSR_DATA(IP3_7_4, MSIOF2_TXD), - PINMUX_IPSR_MODSEL_DATA(IP3_7_4, VI1_R1, SEL_VI1_0), - PINMUX_IPSR_MODSEL_DATA(IP3_7_4, VI1_R1_B, SEL_VI1_1), + PINMUX_IPSR_MSEL(IP3_7_4, VI1_R1, SEL_VI1_0), + PINMUX_IPSR_MSEL(IP3_7_4, VI1_R1_B, SEL_VI1_1), PINMUX_IPSR_DATA(IP3_7_4, VI2_G1), - PINMUX_IPSR_MODSEL_DATA(IP3_7_4, VI2_DATA4_VI2_B4_B, SEL_VI2_1), + PINMUX_IPSR_MSEL(IP3_7_4, VI2_DATA4_VI2_B4_B, SEL_VI2_1), PINMUX_IPSR_DATA(IP3_11_8, A13), - PINMUX_IPSR_MODSEL_DATA(IP3_11_8, SCIFB2_RTS_N_B, SEL_SCIFB2_1), + PINMUX_IPSR_MSEL(IP3_11_8, SCIFB2_RTS_N_B, SEL_SCIFB2_1), PINMUX_IPSR_DATA(IP3_11_8, EX_WAIT2), PINMUX_IPSR_DATA(IP3_11_8, MSIOF2_RXD), - PINMUX_IPSR_MODSEL_DATA(IP3_11_8, VI1_R2, SEL_VI1_0), - PINMUX_IPSR_MODSEL_DATA(IP3_11_8, VI1_R2_B, SEL_VI1_1), + PINMUX_IPSR_MSEL(IP3_11_8, VI1_R2, SEL_VI1_0), + PINMUX_IPSR_MSEL(IP3_11_8, VI1_R2_B, SEL_VI1_1), PINMUX_IPSR_DATA(IP3_11_8, VI2_G2), - PINMUX_IPSR_MODSEL_DATA(IP3_11_8, VI2_DATA5_VI2_B5_B, SEL_VI2_1), + PINMUX_IPSR_MSEL(IP3_11_8, VI2_DATA5_VI2_B5_B, SEL_VI2_1), PINMUX_IPSR_DATA(IP3_14_12, A14), - PINMUX_IPSR_MODSEL_DATA(IP3_14_12, SCIFB2_TXD_B, SEL_SCIFB2_1), + PINMUX_IPSR_MSEL(IP3_14_12, SCIFB2_TXD_B, SEL_SCIFB2_1), PINMUX_IPSR_DATA(IP3_14_12, ATACS11_N), PINMUX_IPSR_DATA(IP3_14_12, MSIOF2_SS1), PINMUX_IPSR_DATA(IP3_17_15, A15), - PINMUX_IPSR_MODSEL_DATA(IP3_17_15, SCIFB2_SCK_B, SEL_SCIFB2_1), + PINMUX_IPSR_MSEL(IP3_17_15, SCIFB2_SCK_B, SEL_SCIFB2_1), PINMUX_IPSR_DATA(IP3_17_15, ATARD1_N), PINMUX_IPSR_DATA(IP3_17_15, MSIOF2_SS2), PINMUX_IPSR_DATA(IP3_19_18, A16), PINMUX_IPSR_DATA(IP3_19_18, ATAWR1_N), PINMUX_IPSR_DATA(IP3_22_20, A17), - PINMUX_IPSR_MODSEL_DATA(IP3_22_20, AD_DO_B, SEL_ADI_1), + PINMUX_IPSR_MSEL(IP3_22_20, AD_DO_B, SEL_ADI_1), PINMUX_IPSR_DATA(IP3_22_20, ATADIR1_N), PINMUX_IPSR_DATA(IP3_25_23, A18), - PINMUX_IPSR_MODSEL_DATA(IP3_25_23, AD_CLK_B, SEL_ADI_1), + PINMUX_IPSR_MSEL(IP3_25_23, AD_CLK_B, SEL_ADI_1), PINMUX_IPSR_DATA(IP3_25_23, ATAG1_N), PINMUX_IPSR_DATA(IP3_28_26, A19), - PINMUX_IPSR_MODSEL_DATA(IP3_28_26, AD_NCS_N_B, SEL_ADI_1), + PINMUX_IPSR_MSEL(IP3_28_26, AD_NCS_N_B, SEL_ADI_1), PINMUX_IPSR_DATA(IP3_28_26, ATACS01_N), - PINMUX_IPSR_MODSEL_DATA(IP3_28_26, EX_WAIT0_B, SEL_LBS_1), + PINMUX_IPSR_MSEL(IP3_28_26, EX_WAIT0_B, SEL_LBS_1), PINMUX_IPSR_DATA(IP3_31_29, A20), PINMUX_IPSR_DATA(IP3_31_29, SPCLK), - PINMUX_IPSR_MODSEL_DATA(IP3_31_29, VI1_R3, SEL_VI1_0), - PINMUX_IPSR_MODSEL_DATA(IP3_31_29, VI1_R3_B, SEL_VI1_1), + PINMUX_IPSR_MSEL(IP3_31_29, VI1_R3, SEL_VI1_0), + PINMUX_IPSR_MSEL(IP3_31_29, VI1_R3_B, SEL_VI1_1), PINMUX_IPSR_DATA(IP3_31_29, VI2_G4), PINMUX_IPSR_DATA(IP4_2_0, A21), PINMUX_IPSR_DATA(IP4_2_0, MOSI_IO0), - PINMUX_IPSR_MODSEL_DATA(IP4_2_0, VI1_R4, SEL_VI1_0), - PINMUX_IPSR_MODSEL_DATA(IP4_2_0, VI1_R4_B, SEL_VI1_1), + PINMUX_IPSR_MSEL(IP4_2_0, VI1_R4, SEL_VI1_0), + PINMUX_IPSR_MSEL(IP4_2_0, VI1_R4_B, SEL_VI1_1), PINMUX_IPSR_DATA(IP4_2_0, VI2_G5), PINMUX_IPSR_DATA(IP4_5_3, A22), PINMUX_IPSR_DATA(IP4_5_3, MISO_IO1), - PINMUX_IPSR_MODSEL_DATA(IP4_5_3, VI1_R5, SEL_VI1_0), - PINMUX_IPSR_MODSEL_DATA(IP4_5_3, VI1_R5_B, SEL_VI1_1), + PINMUX_IPSR_MSEL(IP4_5_3, VI1_R5, SEL_VI1_0), + PINMUX_IPSR_MSEL(IP4_5_3, VI1_R5_B, SEL_VI1_1), PINMUX_IPSR_DATA(IP4_5_3, VI2_G6), PINMUX_IPSR_DATA(IP4_8_6, A23), PINMUX_IPSR_DATA(IP4_8_6, IO2), - PINMUX_IPSR_MODSEL_DATA(IP4_8_6, VI1_G7, SEL_VI1_0), - PINMUX_IPSR_MODSEL_DATA(IP4_8_6, VI1_G7_B, SEL_VI1_1), + PINMUX_IPSR_MSEL(IP4_8_6, VI1_G7, SEL_VI1_0), + PINMUX_IPSR_MSEL(IP4_8_6, VI1_G7_B, SEL_VI1_1), PINMUX_IPSR_DATA(IP4_8_6, VI2_G7), PINMUX_IPSR_DATA(IP4_11_9, A24), PINMUX_IPSR_DATA(IP4_11_9, IO3), - PINMUX_IPSR_MODSEL_DATA(IP4_11_9, VI1_R7, SEL_VI1_0), - PINMUX_IPSR_MODSEL_DATA(IP4_11_9, VI1_R7_B, SEL_VI1_1), - PINMUX_IPSR_MODSEL_DATA(IP4_11_9, VI2_CLKENB, SEL_VI2_0), - PINMUX_IPSR_MODSEL_DATA(IP4_11_9, VI2_CLKENB_B, SEL_VI2_1), + PINMUX_IPSR_MSEL(IP4_11_9, VI1_R7, SEL_VI1_0), + PINMUX_IPSR_MSEL(IP4_11_9, VI1_R7_B, SEL_VI1_1), + PINMUX_IPSR_MSEL(IP4_11_9, VI2_CLKENB, SEL_VI2_0), + PINMUX_IPSR_MSEL(IP4_11_9, VI2_CLKENB_B, SEL_VI2_1), PINMUX_IPSR_DATA(IP4_14_12, A25), PINMUX_IPSR_DATA(IP4_14_12, SSL), - PINMUX_IPSR_MODSEL_DATA(IP4_14_12, VI1_G6, SEL_VI1_0), - PINMUX_IPSR_MODSEL_DATA(IP4_14_12, VI1_G6_B, SEL_VI1_1), - PINMUX_IPSR_MODSEL_DATA(IP4_14_12, VI2_FIELD, SEL_VI2_0), - PINMUX_IPSR_MODSEL_DATA(IP4_14_12, VI2_FIELD_B, SEL_VI2_1), + PINMUX_IPSR_MSEL(IP4_14_12, VI1_G6, SEL_VI1_0), + PINMUX_IPSR_MSEL(IP4_14_12, VI1_G6_B, SEL_VI1_1), + PINMUX_IPSR_MSEL(IP4_14_12, VI2_FIELD, SEL_VI2_0), + PINMUX_IPSR_MSEL(IP4_14_12, VI2_FIELD_B, SEL_VI2_1), PINMUX_IPSR_DATA(IP4_17_15, CS0_N), - PINMUX_IPSR_MODSEL_DATA(IP4_17_15, VI1_R6, SEL_VI1_0), - PINMUX_IPSR_MODSEL_DATA(IP4_17_15, VI1_R6_B, SEL_VI1_1), + PINMUX_IPSR_MSEL(IP4_17_15, VI1_R6, SEL_VI1_0), + PINMUX_IPSR_MSEL(IP4_17_15, VI1_R6_B, SEL_VI1_1), PINMUX_IPSR_DATA(IP4_17_15, VI2_G3), - PINMUX_IPSR_MODSEL_DATA(IP4_17_15, MSIOF0_SS2_B, SEL_SOF0_1), + PINMUX_IPSR_MSEL(IP4_17_15, MSIOF0_SS2_B, SEL_SOF0_1), PINMUX_IPSR_DATA(IP4_20_18, CS1_N_A26), PINMUX_IPSR_DATA(IP4_20_18, SPEEDIN), - PINMUX_IPSR_MODSEL_DATA(IP4_20_18, VI0_R7, SEL_VI0_0), - PINMUX_IPSR_MODSEL_DATA(IP4_20_18, VI0_R7_B, SEL_VI0_1), - PINMUX_IPSR_MODSEL_DATA(IP4_20_18, VI2_CLK, SEL_VI2_0), - PINMUX_IPSR_MODSEL_DATA(IP4_20_18, VI2_CLK_B, SEL_VI2_1), + PINMUX_IPSR_MSEL(IP4_20_18, VI0_R7, SEL_VI0_0), + PINMUX_IPSR_MSEL(IP4_20_18, VI0_R7_B, SEL_VI0_1), + PINMUX_IPSR_MSEL(IP4_20_18, VI2_CLK, SEL_VI2_0), + PINMUX_IPSR_MSEL(IP4_20_18, VI2_CLK_B, SEL_VI2_1), PINMUX_IPSR_DATA(IP4_23_21, EX_CS0_N), - PINMUX_IPSR_MODSEL_DATA(IP4_23_21, HRX1_B, SEL_HSCIF1_1), - PINMUX_IPSR_MODSEL_DATA(IP4_23_21, VI1_G5, SEL_VI1_0), - PINMUX_IPSR_MODSEL_DATA(IP4_23_21, VI1_G5_B, SEL_VI1_1), + PINMUX_IPSR_MSEL(IP4_23_21, HRX1_B, SEL_HSCIF1_1), + PINMUX_IPSR_MSEL(IP4_23_21, VI1_G5, SEL_VI1_0), + PINMUX_IPSR_MSEL(IP4_23_21, VI1_G5_B, SEL_VI1_1), PINMUX_IPSR_DATA(IP4_23_21, VI2_R0), - PINMUX_IPSR_MODSEL_DATA(IP4_23_21, HTX0_B, SEL_HSCIF0_1), - PINMUX_IPSR_MODSEL_DATA(IP4_23_21, MSIOF0_SS1_B, SEL_SOF0_1), + PINMUX_IPSR_MSEL(IP4_23_21, HTX0_B, SEL_HSCIF0_1), + PINMUX_IPSR_MSEL(IP4_23_21, MSIOF0_SS1_B, SEL_SOF0_1), PINMUX_IPSR_DATA(IP4_26_24, EX_CS1_N), PINMUX_IPSR_DATA(IP4_26_24, GPS_CLK), - PINMUX_IPSR_MODSEL_DATA(IP4_26_24, HCTS1_N_B, SEL_HSCIF1_1), - PINMUX_IPSR_MODSEL_DATA(IP4_26_24, VI1_FIELD, SEL_VI1_0), - PINMUX_IPSR_MODSEL_DATA(IP4_26_24, VI1_FIELD_B, SEL_VI1_1), + PINMUX_IPSR_MSEL(IP4_26_24, HCTS1_N_B, SEL_HSCIF1_1), + PINMUX_IPSR_MSEL(IP4_26_24, VI1_FIELD, SEL_VI1_0), + PINMUX_IPSR_MSEL(IP4_26_24, VI1_FIELD_B, SEL_VI1_1), PINMUX_IPSR_DATA(IP4_26_24, VI2_R1), PINMUX_IPSR_DATA(IP4_29_27, EX_CS2_N), PINMUX_IPSR_DATA(IP4_29_27, GPS_SIGN), - PINMUX_IPSR_MODSEL_DATA(IP4_29_27, HRTS1_N_B, SEL_HSCIF1_1), + PINMUX_IPSR_MSEL(IP4_29_27, HRTS1_N_B, SEL_HSCIF1_1), PINMUX_IPSR_DATA(IP4_29_27, VI3_CLKENB), - PINMUX_IPSR_MODSEL_DATA(IP4_29_27, VI1_G0, SEL_VI1_0), - PINMUX_IPSR_MODSEL_DATA(IP4_29_27, VI1_G0_B, SEL_VI1_1), + PINMUX_IPSR_MSEL(IP4_29_27, VI1_G0, SEL_VI1_0), + PINMUX_IPSR_MSEL(IP4_29_27, VI1_G0_B, SEL_VI1_1), PINMUX_IPSR_DATA(IP4_29_27, VI2_R2), PINMUX_IPSR_DATA(IP5_2_0, EX_CS3_N), PINMUX_IPSR_DATA(IP5_2_0, GPS_MAG), PINMUX_IPSR_DATA(IP5_2_0, VI3_FIELD), - PINMUX_IPSR_MODSEL_DATA(IP5_2_0, VI1_G1, SEL_VI1_0), - PINMUX_IPSR_MODSEL_DATA(IP5_2_0, VI1_G1_B, SEL_VI1_1), + PINMUX_IPSR_MSEL(IP5_2_0, VI1_G1, SEL_VI1_0), + PINMUX_IPSR_MSEL(IP5_2_0, VI1_G1_B, SEL_VI1_1), PINMUX_IPSR_DATA(IP5_2_0, VI2_R3), PINMUX_IPSR_DATA(IP5_5_3, EX_CS4_N), - PINMUX_IPSR_MODSEL_DATA(IP5_5_3, MSIOF1_SCK_B, SEL_SOF1_1), + PINMUX_IPSR_MSEL(IP5_5_3, MSIOF1_SCK_B, SEL_SOF1_1), PINMUX_IPSR_DATA(IP5_5_3, VI3_HSYNC_N), - PINMUX_IPSR_MODSEL_DATA(IP5_5_3, VI2_HSYNC_N, SEL_VI2_0), - PINMUX_IPSR_MODSEL_DATA(IP5_5_3, IIC1_SCL, SEL_IIC1_0), - PINMUX_IPSR_MODSEL_DATA(IP5_5_3, VI2_HSYNC_N_B, SEL_VI2_1), + PINMUX_IPSR_MSEL(IP5_5_3, VI2_HSYNC_N, SEL_VI2_0), + PINMUX_IPSR_MSEL(IP5_5_3, IIC1_SCL, SEL_IIC1_0), + PINMUX_IPSR_MSEL(IP5_5_3, VI2_HSYNC_N_B, SEL_VI2_1), PINMUX_IPSR_DATA(IP5_5_3, INTC_EN0_N), - PINMUX_IPSR_MODSEL_DATA(IP5_5_3, I2C1_SCL, SEL_I2C1_0), + PINMUX_IPSR_MSEL(IP5_5_3, I2C1_SCL, SEL_I2C1_0), PINMUX_IPSR_DATA(IP5_9_6, EX_CS5_N), - PINMUX_IPSR_MODSEL_DATA(IP5_9_6, CAN0_RX, SEL_CAN0_0), - PINMUX_IPSR_MODSEL_DATA(IP5_9_6, MSIOF1_RXD_B, SEL_SOF1_1), + PINMUX_IPSR_MSEL(IP5_9_6, CAN0_RX, SEL_CAN0_0), + PINMUX_IPSR_MSEL(IP5_9_6, MSIOF1_RXD_B, SEL_SOF1_1), PINMUX_IPSR_DATA(IP5_9_6, VI3_VSYNC_N), - PINMUX_IPSR_MODSEL_DATA(IP5_9_6, VI1_G2, SEL_VI1_0), - PINMUX_IPSR_MODSEL_DATA(IP5_9_6, VI1_G2_B, SEL_VI1_1), + PINMUX_IPSR_MSEL(IP5_9_6, VI1_G2, SEL_VI1_0), + PINMUX_IPSR_MSEL(IP5_9_6, VI1_G2_B, SEL_VI1_1), PINMUX_IPSR_DATA(IP5_9_6, VI2_R4), - PINMUX_IPSR_MODSEL_DATA(IP5_9_6, IIC1_SDA, SEL_IIC1_0), + PINMUX_IPSR_MSEL(IP5_9_6, IIC1_SDA, SEL_IIC1_0), PINMUX_IPSR_DATA(IP5_9_6, INTC_EN1_N), - PINMUX_IPSR_MODSEL_DATA(IP5_9_6, I2C1_SDA, SEL_I2C1_0), + PINMUX_IPSR_MSEL(IP5_9_6, I2C1_SDA, SEL_I2C1_0), PINMUX_IPSR_DATA(IP5_12_10, BS_N), - PINMUX_IPSR_MODSEL_DATA(IP5_12_10, IETX, SEL_IEB_0), - PINMUX_IPSR_MODSEL_DATA(IP5_12_10, HTX1_B, SEL_HSCIF1_1), - PINMUX_IPSR_MODSEL_DATA(IP5_12_10, CAN1_TX, SEL_CAN1_0), + PINMUX_IPSR_MSEL(IP5_12_10, IETX, SEL_IEB_0), + PINMUX_IPSR_MSEL(IP5_12_10, HTX1_B, SEL_HSCIF1_1), + PINMUX_IPSR_MSEL(IP5_12_10, CAN1_TX, SEL_CAN1_0), PINMUX_IPSR_DATA(IP5_12_10, DRACK0), - PINMUX_IPSR_MODSEL_DATA(IP5_12_10, IETX_C, SEL_IEB_2), + PINMUX_IPSR_MSEL(IP5_12_10, IETX_C, SEL_IEB_2), PINMUX_IPSR_DATA(IP5_14_13, RD_N), - PINMUX_IPSR_MODSEL_DATA(IP5_14_13, CAN0_TX, SEL_CAN0_0), - PINMUX_IPSR_MODSEL_DATA(IP5_14_13, SCIFA0_SCK_B, SEL_SCFA_1), + PINMUX_IPSR_MSEL(IP5_14_13, CAN0_TX, SEL_CAN0_0), + PINMUX_IPSR_MSEL(IP5_14_13, SCIFA0_SCK_B, SEL_SCFA_1), PINMUX_IPSR_DATA(IP5_17_15, RD_WR_N), - PINMUX_IPSR_MODSEL_DATA(IP5_17_15, VI1_G3, SEL_VI1_0), - PINMUX_IPSR_MODSEL_DATA(IP5_17_15, VI1_G3_B, SEL_VI1_1), + PINMUX_IPSR_MSEL(IP5_17_15, VI1_G3, SEL_VI1_0), + PINMUX_IPSR_MSEL(IP5_17_15, VI1_G3_B, SEL_VI1_1), PINMUX_IPSR_DATA(IP5_17_15, VI2_R5), - PINMUX_IPSR_MODSEL_DATA(IP5_17_15, SCIFA0_RXD_B, SEL_SCFA_1), + PINMUX_IPSR_MSEL(IP5_17_15, SCIFA0_RXD_B, SEL_SCFA_1), PINMUX_IPSR_DATA(IP5_17_15, INTC_IRQ4_N), PINMUX_IPSR_DATA(IP5_20_18, WE0_N), - PINMUX_IPSR_MODSEL_DATA(IP5_20_18, IECLK, SEL_IEB_0), - PINMUX_IPSR_MODSEL_DATA(IP5_20_18, CAN_CLK, SEL_CANCLK_0), - PINMUX_IPSR_MODSEL_DATA(IP5_20_18, VI2_VSYNC_N, SEL_VI2_0), - PINMUX_IPSR_MODSEL_DATA(IP5_20_18, SCIFA0_TXD_B, SEL_SCFA_1), - PINMUX_IPSR_MODSEL_DATA(IP5_20_18, VI2_VSYNC_N_B, SEL_VI2_1), + PINMUX_IPSR_MSEL(IP5_20_18, IECLK, SEL_IEB_0), + PINMUX_IPSR_MSEL(IP5_20_18, CAN_CLK, SEL_CANCLK_0), + PINMUX_IPSR_MSEL(IP5_20_18, VI2_VSYNC_N, SEL_VI2_0), + PINMUX_IPSR_MSEL(IP5_20_18, SCIFA0_TXD_B, SEL_SCFA_1), + PINMUX_IPSR_MSEL(IP5_20_18, VI2_VSYNC_N_B, SEL_VI2_1), PINMUX_IPSR_DATA(IP5_23_21, WE1_N), - PINMUX_IPSR_MODSEL_DATA(IP5_23_21, IERX, SEL_IEB_0), - PINMUX_IPSR_MODSEL_DATA(IP5_23_21, CAN1_RX, SEL_CAN1_0), - PINMUX_IPSR_MODSEL_DATA(IP5_23_21, VI1_G4, SEL_VI1_0), - PINMUX_IPSR_MODSEL_DATA(IP5_23_21, VI1_G4_B, SEL_VI1_1), + PINMUX_IPSR_MSEL(IP5_23_21, IERX, SEL_IEB_0), + PINMUX_IPSR_MSEL(IP5_23_21, CAN1_RX, SEL_CAN1_0), + PINMUX_IPSR_MSEL(IP5_23_21, VI1_G4, SEL_VI1_0), + PINMUX_IPSR_MSEL(IP5_23_21, VI1_G4_B, SEL_VI1_1), PINMUX_IPSR_DATA(IP5_23_21, VI2_R6), - PINMUX_IPSR_MODSEL_DATA(IP5_23_21, SCIFA0_CTS_N_B, SEL_SCFA_1), - PINMUX_IPSR_MODSEL_DATA(IP5_23_21, IERX_C, SEL_IEB_2), - PINMUX_IPSR_MODSEL_DATA(IP5_26_24, EX_WAIT0, SEL_LBS_0), + PINMUX_IPSR_MSEL(IP5_23_21, SCIFA0_CTS_N_B, SEL_SCFA_1), + PINMUX_IPSR_MSEL(IP5_23_21, IERX_C, SEL_IEB_2), + PINMUX_IPSR_MSEL(IP5_26_24, EX_WAIT0, SEL_LBS_0), PINMUX_IPSR_DATA(IP5_26_24, IRQ3), PINMUX_IPSR_DATA(IP5_26_24, INTC_IRQ3_N), - PINMUX_IPSR_MODSEL_DATA(IP5_26_24, VI3_CLK, SEL_VI3_0), - PINMUX_IPSR_MODSEL_DATA(IP5_26_24, SCIFA0_RTS_N_B, SEL_SCFA_1), - PINMUX_IPSR_MODSEL_DATA(IP5_26_24, HRX0_B, SEL_HSCIF0_1), - PINMUX_IPSR_MODSEL_DATA(IP5_26_24, MSIOF0_SCK_B, SEL_SOF0_1), + PINMUX_IPSR_MSEL(IP5_26_24, VI3_CLK, SEL_VI3_0), + PINMUX_IPSR_MSEL(IP5_26_24, SCIFA0_RTS_N_B, SEL_SCFA_1), + PINMUX_IPSR_MSEL(IP5_26_24, HRX0_B, SEL_HSCIF0_1), + PINMUX_IPSR_MSEL(IP5_26_24, MSIOF0_SCK_B, SEL_SOF0_1), PINMUX_IPSR_DATA(IP5_29_27, DREQ0_N), - PINMUX_IPSR_MODSEL_DATA(IP5_29_27, VI1_HSYNC_N, SEL_VI1_0), - PINMUX_IPSR_MODSEL_DATA(IP5_29_27, VI1_HSYNC_N_B, SEL_VI1_1), + PINMUX_IPSR_MSEL(IP5_29_27, VI1_HSYNC_N, SEL_VI1_0), + PINMUX_IPSR_MSEL(IP5_29_27, VI1_HSYNC_N_B, SEL_VI1_1), PINMUX_IPSR_DATA(IP5_29_27, VI2_R7), - PINMUX_IPSR_MODSEL_DATA(IP5_29_27, SSI_SCK78_C, SEL_SSI7_2), - PINMUX_IPSR_MODSEL_DATA(IP5_29_27, SSI_WS78_B, SEL_SSI7_1), + PINMUX_IPSR_MSEL(IP5_29_27, SSI_SCK78_C, SEL_SSI7_2), + PINMUX_IPSR_MSEL(IP5_29_27, SSI_WS78_B, SEL_SSI7_1), PINMUX_IPSR_DATA(IP6_2_0, DACK0), PINMUX_IPSR_DATA(IP6_2_0, IRQ0), PINMUX_IPSR_DATA(IP6_2_0, INTC_IRQ0_N), - PINMUX_IPSR_MODSEL_DATA(IP6_2_0, SSI_SCK6_B, SEL_SSI6_1), - PINMUX_IPSR_MODSEL_DATA(IP6_2_0, VI1_VSYNC_N, SEL_VI1_0), - PINMUX_IPSR_MODSEL_DATA(IP6_2_0, VI1_VSYNC_N_B, SEL_VI1_1), - PINMUX_IPSR_MODSEL_DATA(IP6_2_0, SSI_WS78_C, SEL_SSI7_2), + PINMUX_IPSR_MSEL(IP6_2_0, SSI_SCK6_B, SEL_SSI6_1), + PINMUX_IPSR_MSEL(IP6_2_0, VI1_VSYNC_N, SEL_VI1_0), + PINMUX_IPSR_MSEL(IP6_2_0, VI1_VSYNC_N_B, SEL_VI1_1), + PINMUX_IPSR_MSEL(IP6_2_0, SSI_WS78_C, SEL_SSI7_2), PINMUX_IPSR_DATA(IP6_5_3, DREQ1_N), - PINMUX_IPSR_MODSEL_DATA(IP6_5_3, VI1_CLKENB, SEL_VI1_0), - PINMUX_IPSR_MODSEL_DATA(IP6_5_3, VI1_CLKENB_B, SEL_VI1_1), - PINMUX_IPSR_MODSEL_DATA(IP6_5_3, SSI_SDATA7_C, SEL_SSI7_2), - PINMUX_IPSR_MODSEL_DATA(IP6_5_3, SSI_SCK78_B, SEL_SSI7_1), + PINMUX_IPSR_MSEL(IP6_5_3, VI1_CLKENB, SEL_VI1_0), + PINMUX_IPSR_MSEL(IP6_5_3, VI1_CLKENB_B, SEL_VI1_1), + PINMUX_IPSR_MSEL(IP6_5_3, SSI_SDATA7_C, SEL_SSI7_2), + PINMUX_IPSR_MSEL(IP6_5_3, SSI_SCK78_B, SEL_SSI7_1), PINMUX_IPSR_DATA(IP6_8_6, DACK1), PINMUX_IPSR_DATA(IP6_8_6, IRQ1), PINMUX_IPSR_DATA(IP6_8_6, INTC_IRQ1_N), - PINMUX_IPSR_MODSEL_DATA(IP6_8_6, SSI_WS6_B, SEL_SSI6_1), - PINMUX_IPSR_MODSEL_DATA(IP6_8_6, SSI_SDATA8_C, SEL_SSI8_2), + PINMUX_IPSR_MSEL(IP6_8_6, SSI_WS6_B, SEL_SSI6_1), + PINMUX_IPSR_MSEL(IP6_8_6, SSI_SDATA8_C, SEL_SSI8_2), PINMUX_IPSR_DATA(IP6_10_9, DREQ2_N), - PINMUX_IPSR_MODSEL_DATA(IP6_10_9, HSCK1_B, SEL_HSCIF1_1), - PINMUX_IPSR_MODSEL_DATA(IP6_10_9, HCTS0_N_B, SEL_HSCIF0_1), - PINMUX_IPSR_MODSEL_DATA(IP6_10_9, MSIOF0_TXD_B, SEL_SOF0_1), + PINMUX_IPSR_MSEL(IP6_10_9, HSCK1_B, SEL_HSCIF1_1), + PINMUX_IPSR_MSEL(IP6_10_9, HCTS0_N_B, SEL_HSCIF0_1), + PINMUX_IPSR_MSEL(IP6_10_9, MSIOF0_TXD_B, SEL_SOF0_1), PINMUX_IPSR_DATA(IP6_13_11, DACK2), PINMUX_IPSR_DATA(IP6_13_11, IRQ2), PINMUX_IPSR_DATA(IP6_13_11, INTC_IRQ2_N), - PINMUX_IPSR_MODSEL_DATA(IP6_13_11, SSI_SDATA6_B, SEL_SSI6_1), - PINMUX_IPSR_MODSEL_DATA(IP6_13_11, HRTS0_N_B, SEL_HSCIF0_1), - PINMUX_IPSR_MODSEL_DATA(IP6_13_11, MSIOF0_RXD_B, SEL_SOF0_1), + PINMUX_IPSR_MSEL(IP6_13_11, SSI_SDATA6_B, SEL_SSI6_1), + PINMUX_IPSR_MSEL(IP6_13_11, HRTS0_N_B, SEL_HSCIF0_1), + PINMUX_IPSR_MSEL(IP6_13_11, MSIOF0_RXD_B, SEL_SOF0_1), PINMUX_IPSR_DATA(IP6_16_14, ETH_CRS_DV), - PINMUX_IPSR_MODSEL_DATA(IP6_16_14, STP_ISCLK_0_B, SEL_SSP_1), - PINMUX_IPSR_MODSEL_DATA(IP6_16_14, TS_SDEN0_D, SEL_TSIF0_3), - PINMUX_IPSR_MODSEL_DATA(IP6_16_14, GLO_Q0_C, SEL_GPS_2), - PINMUX_IPSR_MODSEL_DATA(IP6_16_14, IIC2_SCL_E, SEL_IIC2_4), - PINMUX_IPSR_MODSEL_DATA(IP6_16_14, I2C2_SCL_E, SEL_I2C2_4), + PINMUX_IPSR_MSEL(IP6_16_14, STP_ISCLK_0_B, SEL_SSP_1), + PINMUX_IPSR_MSEL(IP6_16_14, TS_SDEN0_D, SEL_TSIF0_3), + PINMUX_IPSR_MSEL(IP6_16_14, GLO_Q0_C, SEL_GPS_2), + PINMUX_IPSR_MSEL(IP6_16_14, IIC2_SCL_E, SEL_IIC2_4), + PINMUX_IPSR_MSEL(IP6_16_14, I2C2_SCL_E, SEL_I2C2_4), PINMUX_IPSR_DATA(IP6_19_17, ETH_RX_ER), - PINMUX_IPSR_MODSEL_DATA(IP6_19_17, STP_ISD_0_B, SEL_SSP_1), - PINMUX_IPSR_MODSEL_DATA(IP6_19_17, TS_SPSYNC0_D, SEL_TSIF0_3), - PINMUX_IPSR_MODSEL_DATA(IP6_19_17, GLO_Q1_C, SEL_GPS_2), - PINMUX_IPSR_MODSEL_DATA(IP6_19_17, IIC2_SDA_E, SEL_IIC2_4), - PINMUX_IPSR_MODSEL_DATA(IP6_19_17, I2C2_SDA_E, SEL_I2C2_4), + PINMUX_IPSR_MSEL(IP6_19_17, STP_ISD_0_B, SEL_SSP_1), + PINMUX_IPSR_MSEL(IP6_19_17, TS_SPSYNC0_D, SEL_TSIF0_3), + PINMUX_IPSR_MSEL(IP6_19_17, GLO_Q1_C, SEL_GPS_2), + PINMUX_IPSR_MSEL(IP6_19_17, IIC2_SDA_E, SEL_IIC2_4), + PINMUX_IPSR_MSEL(IP6_19_17, I2C2_SDA_E, SEL_I2C2_4), PINMUX_IPSR_DATA(IP6_22_20, ETH_RXD0), - PINMUX_IPSR_MODSEL_DATA(IP6_22_20, STP_ISEN_0_B, SEL_SSP_1), - PINMUX_IPSR_MODSEL_DATA(IP6_22_20, TS_SDAT0_D, SEL_TSIF0_3), - PINMUX_IPSR_MODSEL_DATA(IP6_22_20, GLO_I0_C, SEL_GPS_2), - PINMUX_IPSR_MODSEL_DATA(IP6_22_20, SCIFB1_SCK_G, SEL_SCIFB1_6), - PINMUX_IPSR_MODSEL_DATA(IP6_22_20, SCK1_E, SEL_SCIF1_4), + PINMUX_IPSR_MSEL(IP6_22_20, STP_ISEN_0_B, SEL_SSP_1), + PINMUX_IPSR_MSEL(IP6_22_20, TS_SDAT0_D, SEL_TSIF0_3), + PINMUX_IPSR_MSEL(IP6_22_20, GLO_I0_C, SEL_GPS_2), + PINMUX_IPSR_MSEL(IP6_22_20, SCIFB1_SCK_G, SEL_SCIFB1_6), + PINMUX_IPSR_MSEL(IP6_22_20, SCK1_E, SEL_SCIF1_4), PINMUX_IPSR_DATA(IP6_25_23, ETH_RXD1), - PINMUX_IPSR_MODSEL_DATA(IP6_25_23, HRX0_E, SEL_HSCIF0_4), - PINMUX_IPSR_MODSEL_DATA(IP6_25_23, STP_ISSYNC_0_B, SEL_SSP_1), - PINMUX_IPSR_MODSEL_DATA(IP6_25_23, TS_SCK0_D, SEL_TSIF0_3), - PINMUX_IPSR_MODSEL_DATA(IP6_25_23, GLO_I1_C, SEL_GPS_2), - PINMUX_IPSR_MODSEL_DATA(IP6_25_23, SCIFB1_RXD_G, SEL_SCIFB1_6), - PINMUX_IPSR_MODSEL_DATA(IP6_25_23, RX1_E, SEL_SCIF1_4), + PINMUX_IPSR_MSEL(IP6_25_23, HRX0_E, SEL_HSCIF0_4), + PINMUX_IPSR_MSEL(IP6_25_23, STP_ISSYNC_0_B, SEL_SSP_1), + PINMUX_IPSR_MSEL(IP6_25_23, TS_SCK0_D, SEL_TSIF0_3), + PINMUX_IPSR_MSEL(IP6_25_23, GLO_I1_C, SEL_GPS_2), + PINMUX_IPSR_MSEL(IP6_25_23, SCIFB1_RXD_G, SEL_SCIFB1_6), + PINMUX_IPSR_MSEL(IP6_25_23, RX1_E, SEL_SCIF1_4), PINMUX_IPSR_DATA(IP6_28_26, ETH_LINK), - PINMUX_IPSR_MODSEL_DATA(IP6_28_26, HTX0_E, SEL_HSCIF0_4), - PINMUX_IPSR_MODSEL_DATA(IP6_28_26, STP_IVCXO27_0_B, SEL_SSP_1), - PINMUX_IPSR_MODSEL_DATA(IP6_28_26, SCIFB1_TXD_G, SEL_SCIFB1_6), - PINMUX_IPSR_MODSEL_DATA(IP6_28_26, TX1_E, SEL_SCIF1_4), + PINMUX_IPSR_MSEL(IP6_28_26, HTX0_E, SEL_HSCIF0_4), + PINMUX_IPSR_MSEL(IP6_28_26, STP_IVCXO27_0_B, SEL_SSP_1), + PINMUX_IPSR_MSEL(IP6_28_26, SCIFB1_TXD_G, SEL_SCIFB1_6), + PINMUX_IPSR_MSEL(IP6_28_26, TX1_E, SEL_SCIF1_4), PINMUX_IPSR_DATA(IP6_31_29, ETH_REF_CLK), - PINMUX_IPSR_MODSEL_DATA(IP6_31_29, HCTS0_N_E, SEL_HSCIF0_4), - PINMUX_IPSR_MODSEL_DATA(IP6_31_29, STP_IVCXO27_1_B, SEL_SSP_1), - PINMUX_IPSR_MODSEL_DATA(IP6_31_29, HRX0_F, SEL_HSCIF0_5), + PINMUX_IPSR_MSEL(IP6_31_29, HCTS0_N_E, SEL_HSCIF0_4), + PINMUX_IPSR_MSEL(IP6_31_29, STP_IVCXO27_1_B, SEL_SSP_1), + PINMUX_IPSR_MSEL(IP6_31_29, HRX0_F, SEL_HSCIF0_5), PINMUX_IPSR_DATA(IP7_2_0, ETH_MDIO), - PINMUX_IPSR_MODSEL_DATA(IP7_2_0, HRTS0_N_E, SEL_HSCIF0_4), - PINMUX_IPSR_MODSEL_DATA(IP7_2_0, SIM0_D_C, SEL_SIM_2), - PINMUX_IPSR_MODSEL_DATA(IP7_2_0, HCTS0_N_F, SEL_HSCIF0_5), + PINMUX_IPSR_MSEL(IP7_2_0, HRTS0_N_E, SEL_HSCIF0_4), + PINMUX_IPSR_MSEL(IP7_2_0, SIM0_D_C, SEL_SIM_2), + PINMUX_IPSR_MSEL(IP7_2_0, HCTS0_N_F, SEL_HSCIF0_5), PINMUX_IPSR_DATA(IP7_5_3, ETH_TXD1), - PINMUX_IPSR_MODSEL_DATA(IP7_5_3, HTX0_F, SEL_HSCIF0_5), - PINMUX_IPSR_MODSEL_DATA(IP7_5_3, BPFCLK_G, SEL_FM_6), + PINMUX_IPSR_MSEL(IP7_5_3, HTX0_F, SEL_HSCIF0_5), + PINMUX_IPSR_MSEL(IP7_5_3, BPFCLK_G, SEL_FM_6), PINMUX_IPSR_DATA(IP7_7_6, ETH_TX_EN), - PINMUX_IPSR_MODSEL_DATA(IP7_7_6, SIM0_CLK_C, SEL_SIM_2), - PINMUX_IPSR_MODSEL_DATA(IP7_7_6, HRTS0_N_F, SEL_HSCIF0_5), + PINMUX_IPSR_MSEL(IP7_7_6, SIM0_CLK_C, SEL_SIM_2), + PINMUX_IPSR_MSEL(IP7_7_6, HRTS0_N_F, SEL_HSCIF0_5), PINMUX_IPSR_DATA(IP7_9_8, ETH_MAGIC), - PINMUX_IPSR_MODSEL_DATA(IP7_9_8, SIM0_RST_C, SEL_SIM_2), + PINMUX_IPSR_MSEL(IP7_9_8, SIM0_RST_C, SEL_SIM_2), PINMUX_IPSR_DATA(IP7_12_10, ETH_TXD0), - PINMUX_IPSR_MODSEL_DATA(IP7_12_10, STP_ISCLK_1_B, SEL_SSP_1), - PINMUX_IPSR_MODSEL_DATA(IP7_12_10, TS_SDEN1_C, SEL_TSIF1_2), - PINMUX_IPSR_MODSEL_DATA(IP7_12_10, GLO_SCLK_C, SEL_GPS_2), + PINMUX_IPSR_MSEL(IP7_12_10, STP_ISCLK_1_B, SEL_SSP_1), + PINMUX_IPSR_MSEL(IP7_12_10, TS_SDEN1_C, SEL_TSIF1_2), + PINMUX_IPSR_MSEL(IP7_12_10, GLO_SCLK_C, SEL_GPS_2), PINMUX_IPSR_DATA(IP7_15_13, ETH_MDC), - PINMUX_IPSR_MODSEL_DATA(IP7_15_13, STP_ISD_1_B, SEL_SSP_1), - PINMUX_IPSR_MODSEL_DATA(IP7_15_13, TS_SPSYNC1_C, SEL_TSIF1_2), - PINMUX_IPSR_MODSEL_DATA(IP7_15_13, GLO_SDATA_C, SEL_GPS_2), + PINMUX_IPSR_MSEL(IP7_15_13, STP_ISD_1_B, SEL_SSP_1), + PINMUX_IPSR_MSEL(IP7_15_13, TS_SPSYNC1_C, SEL_TSIF1_2), + PINMUX_IPSR_MSEL(IP7_15_13, GLO_SDATA_C, SEL_GPS_2), PINMUX_IPSR_DATA(IP7_18_16, PWM0), - PINMUX_IPSR_MODSEL_DATA(IP7_18_16, SCIFA2_SCK_C, SEL_SCIFA2_2), - PINMUX_IPSR_MODSEL_DATA(IP7_18_16, STP_ISEN_1_B, SEL_SSP_1), - PINMUX_IPSR_MODSEL_DATA(IP7_18_16, TS_SDAT1_C, SEL_TSIF1_2), - PINMUX_IPSR_MODSEL_DATA(IP7_18_16, GLO_SS_C, SEL_GPS_2), + PINMUX_IPSR_MSEL(IP7_18_16, SCIFA2_SCK_C, SEL_SCIFA2_2), + PINMUX_IPSR_MSEL(IP7_18_16, STP_ISEN_1_B, SEL_SSP_1), + PINMUX_IPSR_MSEL(IP7_18_16, TS_SDAT1_C, SEL_TSIF1_2), + PINMUX_IPSR_MSEL(IP7_18_16, GLO_SS_C, SEL_GPS_2), PINMUX_IPSR_DATA(IP7_21_19, PWM1), - PINMUX_IPSR_MODSEL_DATA(IP7_21_19, SCIFA2_TXD_C, SEL_SCIFA2_2), - PINMUX_IPSR_MODSEL_DATA(IP7_21_19, STP_ISSYNC_1_B, SEL_SSP_1), - PINMUX_IPSR_MODSEL_DATA(IP7_21_19, TS_SCK1_C, SEL_TSIF1_2), - PINMUX_IPSR_MODSEL_DATA(IP7_21_19, GLO_RFON_C, SEL_GPS_2), + PINMUX_IPSR_MSEL(IP7_21_19, SCIFA2_TXD_C, SEL_SCIFA2_2), + PINMUX_IPSR_MSEL(IP7_21_19, STP_ISSYNC_1_B, SEL_SSP_1), + PINMUX_IPSR_MSEL(IP7_21_19, TS_SCK1_C, SEL_TSIF1_2), + PINMUX_IPSR_MSEL(IP7_21_19, GLO_RFON_C, SEL_GPS_2), PINMUX_IPSR_DATA(IP7_21_19, PCMOE_N), PINMUX_IPSR_DATA(IP7_24_22, PWM2), PINMUX_IPSR_DATA(IP7_24_22, PWMFSW0), - PINMUX_IPSR_MODSEL_DATA(IP7_24_22, SCIFA2_RXD_C, SEL_SCIFA2_2), + PINMUX_IPSR_MSEL(IP7_24_22, SCIFA2_RXD_C, SEL_SCIFA2_2), PINMUX_IPSR_DATA(IP7_24_22, PCMWE_N), - PINMUX_IPSR_MODSEL_DATA(IP7_24_22, IECLK_C, SEL_IEB_2), + PINMUX_IPSR_MSEL(IP7_24_22, IECLK_C, SEL_IEB_2), PINMUX_IPSR_DATA(IP7_26_25, DU_DOTCLKIN1), PINMUX_IPSR_DATA(IP7_26_25, AUDIO_CLKC), PINMUX_IPSR_DATA(IP7_26_25, AUDIO_CLKOUT_C), - PINMUX_IPSR_MODSEL_DATA(IP7_28_27, VI0_CLK, SEL_VI0_0), + PINMUX_IPSR_MSEL(IP7_28_27, VI0_CLK, SEL_VI0_0), PINMUX_IPSR_DATA(IP7_28_27, ATACS00_N), PINMUX_IPSR_DATA(IP7_28_27, AVB_RXD1), - PINMUX_IPSR_MODSEL_DATA(IP7_30_29, VI0_DATA0_VI0_B0, SEL_VI0_0), + PINMUX_IPSR_MSEL(IP7_30_29, VI0_DATA0_VI0_B0, SEL_VI0_0), PINMUX_IPSR_DATA(IP7_30_29, ATACS10_N), PINMUX_IPSR_DATA(IP7_30_29, AVB_RXD2), - PINMUX_IPSR_MODSEL_DATA(IP8_1_0, VI0_DATA1_VI0_B1, SEL_VI0_0), + PINMUX_IPSR_MSEL(IP8_1_0, VI0_DATA1_VI0_B1, SEL_VI0_0), PINMUX_IPSR_DATA(IP8_1_0, ATARD0_N), PINMUX_IPSR_DATA(IP8_1_0, AVB_RXD3), - PINMUX_IPSR_MODSEL_DATA(IP8_3_2, VI0_DATA2_VI0_B2, SEL_VI0_0), + PINMUX_IPSR_MSEL(IP8_3_2, VI0_DATA2_VI0_B2, SEL_VI0_0), PINMUX_IPSR_DATA(IP8_3_2, ATAWR0_N), PINMUX_IPSR_DATA(IP8_3_2, AVB_RXD4), - PINMUX_IPSR_MODSEL_DATA(IP8_5_4, VI0_DATA3_VI0_B3, SEL_VI0_0), + PINMUX_IPSR_MSEL(IP8_5_4, VI0_DATA3_VI0_B3, SEL_VI0_0), PINMUX_IPSR_DATA(IP8_5_4, ATADIR0_N), PINMUX_IPSR_DATA(IP8_5_4, AVB_RXD5), - PINMUX_IPSR_MODSEL_DATA(IP8_7_6, VI0_DATA4_VI0_B4, SEL_VI0_0), + PINMUX_IPSR_MSEL(IP8_7_6, VI0_DATA4_VI0_B4, SEL_VI0_0), PINMUX_IPSR_DATA(IP8_7_6, ATAG0_N), PINMUX_IPSR_DATA(IP8_7_6, AVB_RXD6), - PINMUX_IPSR_MODSEL_DATA(IP8_9_8, VI0_DATA5_VI0_B5, SEL_VI0_0), + PINMUX_IPSR_MSEL(IP8_9_8, VI0_DATA5_VI0_B5, SEL_VI0_0), PINMUX_IPSR_DATA(IP8_9_8, EX_WAIT1), PINMUX_IPSR_DATA(IP8_9_8, AVB_RXD7), - PINMUX_IPSR_MODSEL_DATA(IP8_11_10, VI0_DATA6_VI0_B6, SEL_VI0_0), + PINMUX_IPSR_MSEL(IP8_11_10, VI0_DATA6_VI0_B6, SEL_VI0_0), PINMUX_IPSR_DATA(IP8_11_10, AVB_RX_ER), - PINMUX_IPSR_MODSEL_DATA(IP8_13_12, VI0_DATA7_VI0_B7, SEL_VI0_0), + PINMUX_IPSR_MSEL(IP8_13_12, VI0_DATA7_VI0_B7, SEL_VI0_0), PINMUX_IPSR_DATA(IP8_13_12, AVB_RX_CLK), - PINMUX_IPSR_MODSEL_DATA(IP8_15_14, VI1_CLK, SEL_VI1_0), + PINMUX_IPSR_MSEL(IP8_15_14, VI1_CLK, SEL_VI1_0), PINMUX_IPSR_DATA(IP8_15_14, AVB_RX_DV), - PINMUX_IPSR_MODSEL_DATA(IP8_17_16, VI1_DATA0_VI1_B0, SEL_VI1_0), - PINMUX_IPSR_MODSEL_DATA(IP8_17_16, SCIFA1_SCK_D, SEL_SCIFA1_3), + PINMUX_IPSR_MSEL(IP8_17_16, VI1_DATA0_VI1_B0, SEL_VI1_0), + PINMUX_IPSR_MSEL(IP8_17_16, SCIFA1_SCK_D, SEL_SCIFA1_3), PINMUX_IPSR_DATA(IP8_17_16, AVB_CRS), - PINMUX_IPSR_MODSEL_DATA(IP8_19_18, VI1_DATA1_VI1_B1, SEL_VI1_0), - PINMUX_IPSR_MODSEL_DATA(IP8_19_18, SCIFA1_RXD_D, SEL_SCIFA1_3), + PINMUX_IPSR_MSEL(IP8_19_18, VI1_DATA1_VI1_B1, SEL_VI1_0), + PINMUX_IPSR_MSEL(IP8_19_18, SCIFA1_RXD_D, SEL_SCIFA1_3), PINMUX_IPSR_DATA(IP8_19_18, AVB_MDC), - PINMUX_IPSR_MODSEL_DATA(IP8_21_20, VI1_DATA2_VI1_B2, SEL_VI1_0), - PINMUX_IPSR_MODSEL_DATA(IP8_21_20, SCIFA1_TXD_D, SEL_SCIFA1_3), + PINMUX_IPSR_MSEL(IP8_21_20, VI1_DATA2_VI1_B2, SEL_VI1_0), + PINMUX_IPSR_MSEL(IP8_21_20, SCIFA1_TXD_D, SEL_SCIFA1_3), PINMUX_IPSR_DATA(IP8_21_20, AVB_MDIO), - PINMUX_IPSR_MODSEL_DATA(IP8_23_22, VI1_DATA3_VI1_B3, SEL_VI1_0), - PINMUX_IPSR_MODSEL_DATA(IP8_23_22, SCIFA1_CTS_N_D, SEL_SCIFA1_3), + PINMUX_IPSR_MSEL(IP8_23_22, VI1_DATA3_VI1_B3, SEL_VI1_0), + PINMUX_IPSR_MSEL(IP8_23_22, SCIFA1_CTS_N_D, SEL_SCIFA1_3), PINMUX_IPSR_DATA(IP8_23_22, AVB_GTX_CLK), - PINMUX_IPSR_MODSEL_DATA(IP8_25_24, VI1_DATA4_VI1_B4, SEL_VI1_0), - PINMUX_IPSR_MODSEL_DATA(IP8_25_24, SCIFA1_RTS_N_D, SEL_SCIFA1_3), + PINMUX_IPSR_MSEL(IP8_25_24, VI1_DATA4_VI1_B4, SEL_VI1_0), + PINMUX_IPSR_MSEL(IP8_25_24, SCIFA1_RTS_N_D, SEL_SCIFA1_3), PINMUX_IPSR_DATA(IP8_25_24, AVB_MAGIC), - PINMUX_IPSR_MODSEL_DATA(IP8_26, VI1_DATA5_VI1_B5, SEL_VI1_0), + PINMUX_IPSR_MSEL(IP8_26, VI1_DATA5_VI1_B5, SEL_VI1_0), PINMUX_IPSR_DATA(IP8_26, AVB_PHY_INT), - PINMUX_IPSR_MODSEL_DATA(IP8_27, VI1_DATA6_VI1_B6, SEL_VI1_0), + PINMUX_IPSR_MSEL(IP8_27, VI1_DATA6_VI1_B6, SEL_VI1_0), PINMUX_IPSR_DATA(IP8_27, AVB_GTXREFCLK), PINMUX_IPSR_DATA(IP8_28, SD0_CLK), - PINMUX_IPSR_MODSEL_DATA(IP8_28, VI1_DATA0_VI1_B0_B, SEL_VI1_1), + PINMUX_IPSR_MSEL(IP8_28, VI1_DATA0_VI1_B0_B, SEL_VI1_1), PINMUX_IPSR_DATA(IP8_30_29, SD0_CMD), - PINMUX_IPSR_MODSEL_DATA(IP8_30_29, SCIFB1_SCK_B, SEL_SCIFB1_1), - PINMUX_IPSR_MODSEL_DATA(IP8_30_29, VI1_DATA1_VI1_B1_B, SEL_VI1_1), + PINMUX_IPSR_MSEL(IP8_30_29, SCIFB1_SCK_B, SEL_SCIFB1_1), + PINMUX_IPSR_MSEL(IP8_30_29, VI1_DATA1_VI1_B1_B, SEL_VI1_1), PINMUX_IPSR_DATA(IP9_1_0, SD0_DAT0), - PINMUX_IPSR_MODSEL_DATA(IP9_1_0, SCIFB1_RXD_B, SEL_SCIFB1_1), - PINMUX_IPSR_MODSEL_DATA(IP9_1_0, VI1_DATA2_VI1_B2_B, SEL_VI1_1), + PINMUX_IPSR_MSEL(IP9_1_0, SCIFB1_RXD_B, SEL_SCIFB1_1), + PINMUX_IPSR_MSEL(IP9_1_0, VI1_DATA2_VI1_B2_B, SEL_VI1_1), PINMUX_IPSR_DATA(IP9_3_2, SD0_DAT1), - PINMUX_IPSR_MODSEL_DATA(IP9_3_2, SCIFB1_TXD_B, SEL_SCIFB1_1), - PINMUX_IPSR_MODSEL_DATA(IP9_3_2, VI1_DATA3_VI1_B3_B, SEL_VI1_1), + PINMUX_IPSR_MSEL(IP9_3_2, SCIFB1_TXD_B, SEL_SCIFB1_1), + PINMUX_IPSR_MSEL(IP9_3_2, VI1_DATA3_VI1_B3_B, SEL_VI1_1), PINMUX_IPSR_DATA(IP9_5_4, SD0_DAT2), - PINMUX_IPSR_MODSEL_DATA(IP9_5_4, SCIFB1_CTS_N_B, SEL_SCIFB1_1), - PINMUX_IPSR_MODSEL_DATA(IP9_5_4, VI1_DATA4_VI1_B4_B, SEL_VI1_1), + PINMUX_IPSR_MSEL(IP9_5_4, SCIFB1_CTS_N_B, SEL_SCIFB1_1), + PINMUX_IPSR_MSEL(IP9_5_4, VI1_DATA4_VI1_B4_B, SEL_VI1_1), PINMUX_IPSR_DATA(IP9_7_6, SD0_DAT3), - PINMUX_IPSR_MODSEL_DATA(IP9_7_6, SCIFB1_RTS_N_B, SEL_SCIFB1_1), - PINMUX_IPSR_MODSEL_DATA(IP9_7_6, VI1_DATA5_VI1_B5_B, SEL_VI1_1), + PINMUX_IPSR_MSEL(IP9_7_6, SCIFB1_RTS_N_B, SEL_SCIFB1_1), + PINMUX_IPSR_MSEL(IP9_7_6, VI1_DATA5_VI1_B5_B, SEL_VI1_1), PINMUX_IPSR_DATA(IP9_11_8, SD0_CD), PINMUX_IPSR_DATA(IP9_11_8, MMC0_D6), - PINMUX_IPSR_MODSEL_DATA(IP9_11_8, TS_SDEN0_B, SEL_TSIF0_1), + PINMUX_IPSR_MSEL(IP9_11_8, TS_SDEN0_B, SEL_TSIF0_1), PINMUX_IPSR_DATA(IP9_11_8, USB0_EXTP), - PINMUX_IPSR_MODSEL_DATA(IP9_11_8, GLO_SCLK, SEL_GPS_0), - PINMUX_IPSR_MODSEL_DATA(IP9_11_8, VI1_DATA6_VI1_B6_B, SEL_VI1_1), - PINMUX_IPSR_MODSEL_DATA(IP9_11_8, IIC1_SCL_B, SEL_IIC1_1), - PINMUX_IPSR_MODSEL_DATA(IP9_11_8, I2C1_SCL_B, SEL_I2C1_1), - PINMUX_IPSR_MODSEL_DATA(IP9_11_8, VI2_DATA6_VI2_B6_B, SEL_VI2_1), + PINMUX_IPSR_MSEL(IP9_11_8, GLO_SCLK, SEL_GPS_0), + PINMUX_IPSR_MSEL(IP9_11_8, VI1_DATA6_VI1_B6_B, SEL_VI1_1), + PINMUX_IPSR_MSEL(IP9_11_8, IIC1_SCL_B, SEL_IIC1_1), + PINMUX_IPSR_MSEL(IP9_11_8, I2C1_SCL_B, SEL_I2C1_1), + PINMUX_IPSR_MSEL(IP9_11_8, VI2_DATA6_VI2_B6_B, SEL_VI2_1), PINMUX_IPSR_DATA(IP9_15_12, SD0_WP), PINMUX_IPSR_DATA(IP9_15_12, MMC0_D7), - PINMUX_IPSR_MODSEL_DATA(IP9_15_12, TS_SPSYNC0_B, SEL_TSIF0_1), + PINMUX_IPSR_MSEL(IP9_15_12, TS_SPSYNC0_B, SEL_TSIF0_1), PINMUX_IPSR_DATA(IP9_15_12, USB0_IDIN), - PINMUX_IPSR_MODSEL_DATA(IP9_15_12, GLO_SDATA, SEL_GPS_0), - PINMUX_IPSR_MODSEL_DATA(IP9_15_12, VI1_DATA7_VI1_B7_B, SEL_VI1_1), - PINMUX_IPSR_MODSEL_DATA(IP9_15_12, IIC1_SDA_B, SEL_IIC1_1), - PINMUX_IPSR_MODSEL_DATA(IP9_15_12, I2C1_SDA_B, SEL_I2C1_1), - PINMUX_IPSR_MODSEL_DATA(IP9_15_12, VI2_DATA7_VI2_B7_B, SEL_VI2_1), + PINMUX_IPSR_MSEL(IP9_15_12, GLO_SDATA, SEL_GPS_0), + PINMUX_IPSR_MSEL(IP9_15_12, VI1_DATA7_VI1_B7_B, SEL_VI1_1), + PINMUX_IPSR_MSEL(IP9_15_12, IIC1_SDA_B, SEL_IIC1_1), + PINMUX_IPSR_MSEL(IP9_15_12, I2C1_SDA_B, SEL_I2C1_1), + PINMUX_IPSR_MSEL(IP9_15_12, VI2_DATA7_VI2_B7_B, SEL_VI2_1), PINMUX_IPSR_DATA(IP9_17_16, SD1_CLK), PINMUX_IPSR_DATA(IP9_17_16, AVB_TX_EN), PINMUX_IPSR_DATA(IP9_19_18, SD1_CMD), PINMUX_IPSR_DATA(IP9_19_18, AVB_TX_ER), - PINMUX_IPSR_MODSEL_DATA(IP9_19_18, SCIFB0_SCK_B, SEL_SCIFB_1), + PINMUX_IPSR_MSEL(IP9_19_18, SCIFB0_SCK_B, SEL_SCIFB_1), PINMUX_IPSR_DATA(IP9_21_20, SD1_DAT0), PINMUX_IPSR_DATA(IP9_21_20, AVB_TX_CLK), - PINMUX_IPSR_MODSEL_DATA(IP9_21_20, SCIFB0_RXD_B, SEL_SCIFB_1), + PINMUX_IPSR_MSEL(IP9_21_20, SCIFB0_RXD_B, SEL_SCIFB_1), PINMUX_IPSR_DATA(IP9_23_22, SD1_DAT1), PINMUX_IPSR_DATA(IP9_23_22, AVB_LINK), - PINMUX_IPSR_MODSEL_DATA(IP9_23_22, SCIFB0_TXD_B, SEL_SCIFB_1), + PINMUX_IPSR_MSEL(IP9_23_22, SCIFB0_TXD_B, SEL_SCIFB_1), PINMUX_IPSR_DATA(IP9_25_24, SD1_DAT2), PINMUX_IPSR_DATA(IP9_25_24, AVB_COL), - PINMUX_IPSR_MODSEL_DATA(IP9_25_24, SCIFB0_CTS_N_B, SEL_SCIFB_1), + PINMUX_IPSR_MSEL(IP9_25_24, SCIFB0_CTS_N_B, SEL_SCIFB_1), PINMUX_IPSR_DATA(IP9_27_26, SD1_DAT3), PINMUX_IPSR_DATA(IP9_27_26, AVB_RXD0), - PINMUX_IPSR_MODSEL_DATA(IP9_27_26, SCIFB0_RTS_N_B, SEL_SCIFB_1), + PINMUX_IPSR_MSEL(IP9_27_26, SCIFB0_RTS_N_B, SEL_SCIFB_1), PINMUX_IPSR_DATA(IP9_31_28, SD1_CD), PINMUX_IPSR_DATA(IP9_31_28, MMC1_D6), - PINMUX_IPSR_MODSEL_DATA(IP9_31_28, TS_SDEN1, SEL_TSIF1_0), + PINMUX_IPSR_MSEL(IP9_31_28, TS_SDEN1, SEL_TSIF1_0), PINMUX_IPSR_DATA(IP9_31_28, USB1_EXTP), - PINMUX_IPSR_MODSEL_DATA(IP9_31_28, GLO_SS, SEL_GPS_0), - PINMUX_IPSR_MODSEL_DATA(IP9_31_28, VI0_CLK_B, SEL_VI0_1), - PINMUX_IPSR_MODSEL_DATA(IP9_31_28, IIC2_SCL_D, SEL_IIC2_3), - PINMUX_IPSR_MODSEL_DATA(IP9_31_28, I2C2_SCL_D, SEL_I2C2_3), - PINMUX_IPSR_MODSEL_DATA(IP9_31_28, SIM0_CLK_B, SEL_SIM_1), - PINMUX_IPSR_MODSEL_DATA(IP9_31_28, VI3_CLK_B, SEL_VI3_1), + PINMUX_IPSR_MSEL(IP9_31_28, GLO_SS, SEL_GPS_0), + PINMUX_IPSR_MSEL(IP9_31_28, VI0_CLK_B, SEL_VI0_1), + PINMUX_IPSR_MSEL(IP9_31_28, IIC2_SCL_D, SEL_IIC2_3), + PINMUX_IPSR_MSEL(IP9_31_28, I2C2_SCL_D, SEL_I2C2_3), + PINMUX_IPSR_MSEL(IP9_31_28, SIM0_CLK_B, SEL_SIM_1), + PINMUX_IPSR_MSEL(IP9_31_28, VI3_CLK_B, SEL_VI3_1), PINMUX_IPSR_DATA(IP10_3_0, SD1_WP), PINMUX_IPSR_DATA(IP10_3_0, MMC1_D7), - PINMUX_IPSR_MODSEL_DATA(IP10_3_0, TS_SPSYNC1, SEL_TSIF1_0), + PINMUX_IPSR_MSEL(IP10_3_0, TS_SPSYNC1, SEL_TSIF1_0), PINMUX_IPSR_DATA(IP10_3_0, USB1_IDIN), - PINMUX_IPSR_MODSEL_DATA(IP10_3_0, GLO_RFON, SEL_GPS_0), - PINMUX_IPSR_MODSEL_DATA(IP10_3_0, VI1_CLK_B, SEL_VI1_1), - PINMUX_IPSR_MODSEL_DATA(IP10_3_0, IIC2_SDA_D, SEL_IIC2_3), - PINMUX_IPSR_MODSEL_DATA(IP10_3_0, I2C2_SDA_D, SEL_I2C2_3), - PINMUX_IPSR_MODSEL_DATA(IP10_3_0, SIM0_D_B, SEL_SIM_1), + PINMUX_IPSR_MSEL(IP10_3_0, GLO_RFON, SEL_GPS_0), + PINMUX_IPSR_MSEL(IP10_3_0, VI1_CLK_B, SEL_VI1_1), + PINMUX_IPSR_MSEL(IP10_3_0, IIC2_SDA_D, SEL_IIC2_3), + PINMUX_IPSR_MSEL(IP10_3_0, I2C2_SDA_D, SEL_I2C2_3), + PINMUX_IPSR_MSEL(IP10_3_0, SIM0_D_B, SEL_SIM_1), PINMUX_IPSR_DATA(IP10_6_4, SD2_CLK), PINMUX_IPSR_DATA(IP10_6_4, MMC0_CLK), - PINMUX_IPSR_MODSEL_DATA(IP10_6_4, SIM0_CLK, SEL_SIM_0), - PINMUX_IPSR_MODSEL_DATA(IP10_6_4, VI0_DATA0_VI0_B0_B, SEL_VI0_1), - PINMUX_IPSR_MODSEL_DATA(IP10_6_4, TS_SDEN0_C, SEL_TSIF0_2), - PINMUX_IPSR_MODSEL_DATA(IP10_6_4, GLO_SCLK_B, SEL_GPS_1), - PINMUX_IPSR_MODSEL_DATA(IP10_6_4, VI3_DATA0_B, SEL_VI3_1), + PINMUX_IPSR_MSEL(IP10_6_4, SIM0_CLK, SEL_SIM_0), + PINMUX_IPSR_MSEL(IP10_6_4, VI0_DATA0_VI0_B0_B, SEL_VI0_1), + PINMUX_IPSR_MSEL(IP10_6_4, TS_SDEN0_C, SEL_TSIF0_2), + PINMUX_IPSR_MSEL(IP10_6_4, GLO_SCLK_B, SEL_GPS_1), + PINMUX_IPSR_MSEL(IP10_6_4, VI3_DATA0_B, SEL_VI3_1), PINMUX_IPSR_DATA(IP10_10_7, SD2_CMD), PINMUX_IPSR_DATA(IP10_10_7, MMC0_CMD), - PINMUX_IPSR_MODSEL_DATA(IP10_10_7, SIM0_D, SEL_SIM_0), - PINMUX_IPSR_MODSEL_DATA(IP10_10_7, VI0_DATA1_VI0_B1_B, SEL_VI0_1), - PINMUX_IPSR_MODSEL_DATA(IP10_10_7, SCIFB1_SCK_E, SEL_SCIFB1_4), - PINMUX_IPSR_MODSEL_DATA(IP10_10_7, SCK1_D, SEL_SCIF1_3), - PINMUX_IPSR_MODSEL_DATA(IP10_10_7, TS_SPSYNC0_C, SEL_TSIF0_2), - PINMUX_IPSR_MODSEL_DATA(IP10_10_7, GLO_SDATA_B, SEL_GPS_1), - PINMUX_IPSR_MODSEL_DATA(IP10_10_7, VI3_DATA1_B, SEL_VI3_1), + PINMUX_IPSR_MSEL(IP10_10_7, SIM0_D, SEL_SIM_0), + PINMUX_IPSR_MSEL(IP10_10_7, VI0_DATA1_VI0_B1_B, SEL_VI0_1), + PINMUX_IPSR_MSEL(IP10_10_7, SCIFB1_SCK_E, SEL_SCIFB1_4), + PINMUX_IPSR_MSEL(IP10_10_7, SCK1_D, SEL_SCIF1_3), + PINMUX_IPSR_MSEL(IP10_10_7, TS_SPSYNC0_C, SEL_TSIF0_2), + PINMUX_IPSR_MSEL(IP10_10_7, GLO_SDATA_B, SEL_GPS_1), + PINMUX_IPSR_MSEL(IP10_10_7, VI3_DATA1_B, SEL_VI3_1), PINMUX_IPSR_DATA(IP10_14_11, SD2_DAT0), PINMUX_IPSR_DATA(IP10_14_11, MMC0_D0), - PINMUX_IPSR_MODSEL_DATA(IP10_14_11, FMCLK_B, SEL_FM_1), - PINMUX_IPSR_MODSEL_DATA(IP10_14_11, VI0_DATA2_VI0_B2_B, SEL_VI0_1), - PINMUX_IPSR_MODSEL_DATA(IP10_14_11, SCIFB1_RXD_E, SEL_SCIFB1_4), - PINMUX_IPSR_MODSEL_DATA(IP10_14_11, RX1_D, SEL_SCIF1_3), - PINMUX_IPSR_MODSEL_DATA(IP10_14_11, TS_SDAT0_C, SEL_TSIF0_2), - PINMUX_IPSR_MODSEL_DATA(IP10_14_11, GLO_SS_B, SEL_GPS_1), - PINMUX_IPSR_MODSEL_DATA(IP10_14_11, VI3_DATA2_B, SEL_VI3_1), + PINMUX_IPSR_MSEL(IP10_14_11, FMCLK_B, SEL_FM_1), + PINMUX_IPSR_MSEL(IP10_14_11, VI0_DATA2_VI0_B2_B, SEL_VI0_1), + PINMUX_IPSR_MSEL(IP10_14_11, SCIFB1_RXD_E, SEL_SCIFB1_4), + PINMUX_IPSR_MSEL(IP10_14_11, RX1_D, SEL_SCIF1_3), + PINMUX_IPSR_MSEL(IP10_14_11, TS_SDAT0_C, SEL_TSIF0_2), + PINMUX_IPSR_MSEL(IP10_14_11, GLO_SS_B, SEL_GPS_1), + PINMUX_IPSR_MSEL(IP10_14_11, VI3_DATA2_B, SEL_VI3_1), PINMUX_IPSR_DATA(IP10_18_15, SD2_DAT1), PINMUX_IPSR_DATA(IP10_18_15, MMC0_D1), - PINMUX_IPSR_MODSEL_DATA(IP10_18_15, FMIN_B, SEL_FM_1), - PINMUX_IPSR_MODSEL_DATA(IP10_18_15, VI0_DATA3_VI0_B3_B, SEL_VI0_1), - PINMUX_IPSR_MODSEL_DATA(IP10_18_15, SCIFB1_TXD_E, SEL_SCIFB1_4), - PINMUX_IPSR_MODSEL_DATA(IP10_18_15, TX1_D, SEL_SCIF1_3), - PINMUX_IPSR_MODSEL_DATA(IP10_18_15, TS_SCK0_C, SEL_TSIF0_2), - PINMUX_IPSR_MODSEL_DATA(IP10_18_15, GLO_RFON_B, SEL_GPS_1), - PINMUX_IPSR_MODSEL_DATA(IP10_18_15, VI3_DATA3_B, SEL_VI3_1), + PINMUX_IPSR_MSEL(IP10_18_15, FMIN_B, SEL_FM_1), + PINMUX_IPSR_MSEL(IP10_18_15, VI0_DATA3_VI0_B3_B, SEL_VI0_1), + PINMUX_IPSR_MSEL(IP10_18_15, SCIFB1_TXD_E, SEL_SCIFB1_4), + PINMUX_IPSR_MSEL(IP10_18_15, TX1_D, SEL_SCIF1_3), + PINMUX_IPSR_MSEL(IP10_18_15, TS_SCK0_C, SEL_TSIF0_2), + PINMUX_IPSR_MSEL(IP10_18_15, GLO_RFON_B, SEL_GPS_1), + PINMUX_IPSR_MSEL(IP10_18_15, VI3_DATA3_B, SEL_VI3_1), PINMUX_IPSR_DATA(IP10_22_19, SD2_DAT2), PINMUX_IPSR_DATA(IP10_22_19, MMC0_D2), - PINMUX_IPSR_MODSEL_DATA(IP10_22_19, BPFCLK_B, SEL_FM_1), - PINMUX_IPSR_MODSEL_DATA(IP10_22_19, VI0_DATA4_VI0_B4_B, SEL_VI0_1), - PINMUX_IPSR_MODSEL_DATA(IP10_22_19, HRX0_D, SEL_HSCIF0_3), - PINMUX_IPSR_MODSEL_DATA(IP10_22_19, TS_SDEN1_B, SEL_TSIF1_1), - PINMUX_IPSR_MODSEL_DATA(IP10_22_19, GLO_Q0_B, SEL_GPS_1), - PINMUX_IPSR_MODSEL_DATA(IP10_22_19, VI3_DATA4_B, SEL_VI3_1), + PINMUX_IPSR_MSEL(IP10_22_19, BPFCLK_B, SEL_FM_1), + PINMUX_IPSR_MSEL(IP10_22_19, VI0_DATA4_VI0_B4_B, SEL_VI0_1), + PINMUX_IPSR_MSEL(IP10_22_19, HRX0_D, SEL_HSCIF0_3), + PINMUX_IPSR_MSEL(IP10_22_19, TS_SDEN1_B, SEL_TSIF1_1), + PINMUX_IPSR_MSEL(IP10_22_19, GLO_Q0_B, SEL_GPS_1), + PINMUX_IPSR_MSEL(IP10_22_19, VI3_DATA4_B, SEL_VI3_1), PINMUX_IPSR_DATA(IP10_25_23, SD2_DAT3), PINMUX_IPSR_DATA(IP10_25_23, MMC0_D3), - PINMUX_IPSR_MODSEL_DATA(IP10_25_23, SIM0_RST, SEL_SIM_0), - PINMUX_IPSR_MODSEL_DATA(IP10_25_23, VI0_DATA5_VI0_B5_B, SEL_VI0_1), - PINMUX_IPSR_MODSEL_DATA(IP10_25_23, HTX0_D, SEL_HSCIF0_3), - PINMUX_IPSR_MODSEL_DATA(IP10_25_23, TS_SPSYNC1_B, SEL_TSIF1_1), - PINMUX_IPSR_MODSEL_DATA(IP10_25_23, GLO_Q1_B, SEL_GPS_1), - PINMUX_IPSR_MODSEL_DATA(IP10_25_23, VI3_DATA5_B, SEL_VI3_1), + PINMUX_IPSR_MSEL(IP10_25_23, SIM0_RST, SEL_SIM_0), + PINMUX_IPSR_MSEL(IP10_25_23, VI0_DATA5_VI0_B5_B, SEL_VI0_1), + PINMUX_IPSR_MSEL(IP10_25_23, HTX0_D, SEL_HSCIF0_3), + PINMUX_IPSR_MSEL(IP10_25_23, TS_SPSYNC1_B, SEL_TSIF1_1), + PINMUX_IPSR_MSEL(IP10_25_23, GLO_Q1_B, SEL_GPS_1), + PINMUX_IPSR_MSEL(IP10_25_23, VI3_DATA5_B, SEL_VI3_1), PINMUX_IPSR_DATA(IP10_29_26, SD2_CD), PINMUX_IPSR_DATA(IP10_29_26, MMC0_D4), - PINMUX_IPSR_MODSEL_DATA(IP10_29_26, TS_SDAT0_B, SEL_TSIF0_1), + PINMUX_IPSR_MSEL(IP10_29_26, TS_SDAT0_B, SEL_TSIF0_1), PINMUX_IPSR_DATA(IP10_29_26, USB2_EXTP), - PINMUX_IPSR_MODSEL_DATA(IP10_29_26, GLO_I0, SEL_GPS_0), - PINMUX_IPSR_MODSEL_DATA(IP10_29_26, VI0_DATA6_VI0_B6_B, SEL_VI0_1), - PINMUX_IPSR_MODSEL_DATA(IP10_29_26, HCTS0_N_D, SEL_HSCIF0_3), - PINMUX_IPSR_MODSEL_DATA(IP10_29_26, TS_SDAT1_B, SEL_TSIF1_1), - PINMUX_IPSR_MODSEL_DATA(IP10_29_26, GLO_I0_B, SEL_GPS_1), - PINMUX_IPSR_MODSEL_DATA(IP10_29_26, VI3_DATA6_B, SEL_VI3_1), + PINMUX_IPSR_MSEL(IP10_29_26, GLO_I0, SEL_GPS_0), + PINMUX_IPSR_MSEL(IP10_29_26, VI0_DATA6_VI0_B6_B, SEL_VI0_1), + PINMUX_IPSR_MSEL(IP10_29_26, HCTS0_N_D, SEL_HSCIF0_3), + PINMUX_IPSR_MSEL(IP10_29_26, TS_SDAT1_B, SEL_TSIF1_1), + PINMUX_IPSR_MSEL(IP10_29_26, GLO_I0_B, SEL_GPS_1), + PINMUX_IPSR_MSEL(IP10_29_26, VI3_DATA6_B, SEL_VI3_1), PINMUX_IPSR_DATA(IP11_3_0, SD2_WP), PINMUX_IPSR_DATA(IP11_3_0, MMC0_D5), - PINMUX_IPSR_MODSEL_DATA(IP11_3_0, TS_SCK0_B, SEL_TSIF0_1), + PINMUX_IPSR_MSEL(IP11_3_0, TS_SCK0_B, SEL_TSIF0_1), PINMUX_IPSR_DATA(IP11_3_0, USB2_IDIN), - PINMUX_IPSR_MODSEL_DATA(IP11_3_0, GLO_I1, SEL_GPS_0), - PINMUX_IPSR_MODSEL_DATA(IP11_3_0, VI0_DATA7_VI0_B7_B, SEL_VI0_1), - PINMUX_IPSR_MODSEL_DATA(IP11_3_0, HRTS0_N_D, SEL_HSCIF0_3), - PINMUX_IPSR_MODSEL_DATA(IP11_3_0, TS_SCK1_B, SEL_TSIF1_1), - PINMUX_IPSR_MODSEL_DATA(IP11_3_0, GLO_I1_B, SEL_GPS_1), - PINMUX_IPSR_MODSEL_DATA(IP11_3_0, VI3_DATA7_B, SEL_VI3_1), + PINMUX_IPSR_MSEL(IP11_3_0, GLO_I1, SEL_GPS_0), + PINMUX_IPSR_MSEL(IP11_3_0, VI0_DATA7_VI0_B7_B, SEL_VI0_1), + PINMUX_IPSR_MSEL(IP11_3_0, HRTS0_N_D, SEL_HSCIF0_3), + PINMUX_IPSR_MSEL(IP11_3_0, TS_SCK1_B, SEL_TSIF1_1), + PINMUX_IPSR_MSEL(IP11_3_0, GLO_I1_B, SEL_GPS_1), + PINMUX_IPSR_MSEL(IP11_3_0, VI3_DATA7_B, SEL_VI3_1), PINMUX_IPSR_DATA(IP11_4, SD3_CLK), PINMUX_IPSR_DATA(IP11_4, MMC1_CLK), PINMUX_IPSR_DATA(IP11_6_5, SD3_CMD), @@ -1447,298 +1447,298 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_DATA(IP11_14_13, SCKZ), PINMUX_IPSR_DATA(IP11_17_15, SD3_CD), PINMUX_IPSR_DATA(IP11_17_15, MMC1_D4), - PINMUX_IPSR_MODSEL_DATA(IP11_17_15, TS_SDAT1, SEL_TSIF1_0), + PINMUX_IPSR_MSEL(IP11_17_15, TS_SDAT1, SEL_TSIF1_0), PINMUX_IPSR_DATA(IP11_17_15, VSP), - PINMUX_IPSR_MODSEL_DATA(IP11_17_15, GLO_Q0, SEL_GPS_0), - PINMUX_IPSR_MODSEL_DATA(IP11_17_15, SIM0_RST_B, SEL_SIM_1), + PINMUX_IPSR_MSEL(IP11_17_15, GLO_Q0, SEL_GPS_0), + PINMUX_IPSR_MSEL(IP11_17_15, SIM0_RST_B, SEL_SIM_1), PINMUX_IPSR_DATA(IP11_21_18, SD3_WP), PINMUX_IPSR_DATA(IP11_21_18, MMC1_D5), - PINMUX_IPSR_MODSEL_DATA(IP11_21_18, TS_SCK1, SEL_TSIF1_0), - PINMUX_IPSR_MODSEL_DATA(IP11_21_18, GLO_Q1, SEL_GPS_0), - PINMUX_IPSR_MODSEL_DATA(IP11_21_18, FMIN_C, SEL_FM_2), - PINMUX_IPSR_MODSEL_DATA(IP11_21_18, FMIN_E, SEL_FM_4), - PINMUX_IPSR_MODSEL_DATA(IP11_21_18, FMIN_F, SEL_FM_5), + PINMUX_IPSR_MSEL(IP11_21_18, TS_SCK1, SEL_TSIF1_0), + PINMUX_IPSR_MSEL(IP11_21_18, GLO_Q1, SEL_GPS_0), + PINMUX_IPSR_MSEL(IP11_21_18, FMIN_C, SEL_FM_2), + PINMUX_IPSR_MSEL(IP11_21_18, FMIN_E, SEL_FM_4), + PINMUX_IPSR_MSEL(IP11_21_18, FMIN_F, SEL_FM_5), PINMUX_IPSR_DATA(IP11_23_22, MLB_CLK), - PINMUX_IPSR_MODSEL_DATA(IP11_23_22, IIC2_SCL_B, SEL_IIC2_1), - PINMUX_IPSR_MODSEL_DATA(IP11_23_22, I2C2_SCL_B, SEL_I2C2_1), + PINMUX_IPSR_MSEL(IP11_23_22, IIC2_SCL_B, SEL_IIC2_1), + PINMUX_IPSR_MSEL(IP11_23_22, I2C2_SCL_B, SEL_I2C2_1), PINMUX_IPSR_DATA(IP11_26_24, MLB_SIG), - PINMUX_IPSR_MODSEL_DATA(IP11_26_24, SCIFB1_RXD_D, SEL_SCIFB1_3), - PINMUX_IPSR_MODSEL_DATA(IP11_26_24, RX1_C, SEL_SCIF1_2), - PINMUX_IPSR_MODSEL_DATA(IP11_26_24, IIC2_SDA_B, SEL_IIC2_1), - PINMUX_IPSR_MODSEL_DATA(IP11_26_24, I2C2_SDA_B, SEL_I2C2_1), + PINMUX_IPSR_MSEL(IP11_26_24, SCIFB1_RXD_D, SEL_SCIFB1_3), + PINMUX_IPSR_MSEL(IP11_26_24, RX1_C, SEL_SCIF1_2), + PINMUX_IPSR_MSEL(IP11_26_24, IIC2_SDA_B, SEL_IIC2_1), + PINMUX_IPSR_MSEL(IP11_26_24, I2C2_SDA_B, SEL_I2C2_1), PINMUX_IPSR_DATA(IP11_29_27, MLB_DAT), - PINMUX_IPSR_MODSEL_DATA(IP11_29_27, SCIFB1_TXD_D, SEL_SCIFB1_3), - PINMUX_IPSR_MODSEL_DATA(IP11_29_27, TX1_C, SEL_SCIF1_2), - PINMUX_IPSR_MODSEL_DATA(IP11_29_27, BPFCLK_C, SEL_FM_2), + PINMUX_IPSR_MSEL(IP11_29_27, SCIFB1_TXD_D, SEL_SCIFB1_3), + PINMUX_IPSR_MSEL(IP11_29_27, TX1_C, SEL_SCIF1_2), + PINMUX_IPSR_MSEL(IP11_29_27, BPFCLK_C, SEL_FM_2), PINMUX_IPSR_DATA(IP11_31_30, SSI_SCK0129), - PINMUX_IPSR_MODSEL_DATA(IP11_31_30, CAN_CLK_B, SEL_CANCLK_1), + PINMUX_IPSR_MSEL(IP11_31_30, CAN_CLK_B, SEL_CANCLK_1), PINMUX_IPSR_DATA(IP11_31_30, MOUT0), PINMUX_IPSR_DATA(IP12_1_0, SSI_WS0129), - PINMUX_IPSR_MODSEL_DATA(IP12_1_0, CAN0_TX_B, SEL_CAN0_1), + PINMUX_IPSR_MSEL(IP12_1_0, CAN0_TX_B, SEL_CAN0_1), PINMUX_IPSR_DATA(IP12_1_0, MOUT1), PINMUX_IPSR_DATA(IP12_3_2, SSI_SDATA0), - PINMUX_IPSR_MODSEL_DATA(IP12_3_2, CAN0_RX_B, SEL_CAN0_1), + PINMUX_IPSR_MSEL(IP12_3_2, CAN0_RX_B, SEL_CAN0_1), PINMUX_IPSR_DATA(IP12_3_2, MOUT2), PINMUX_IPSR_DATA(IP12_5_4, SSI_SDATA1), - PINMUX_IPSR_MODSEL_DATA(IP12_5_4, CAN1_TX_B, SEL_CAN1_1), + PINMUX_IPSR_MSEL(IP12_5_4, CAN1_TX_B, SEL_CAN1_1), PINMUX_IPSR_DATA(IP12_5_4, MOUT5), PINMUX_IPSR_DATA(IP12_7_6, SSI_SDATA2), - PINMUX_IPSR_MODSEL_DATA(IP12_7_6, CAN1_RX_B, SEL_CAN1_1), + PINMUX_IPSR_MSEL(IP12_7_6, CAN1_RX_B, SEL_CAN1_1), PINMUX_IPSR_DATA(IP12_7_6, SSI_SCK1), PINMUX_IPSR_DATA(IP12_7_6, MOUT6), PINMUX_IPSR_DATA(IP12_10_8, SSI_SCK34), PINMUX_IPSR_DATA(IP12_10_8, STP_OPWM_0), - PINMUX_IPSR_MODSEL_DATA(IP12_10_8, SCIFB0_SCK, SEL_SCIFB_0), - PINMUX_IPSR_MODSEL_DATA(IP12_10_8, MSIOF1_SCK, SEL_SOF1_0), + PINMUX_IPSR_MSEL(IP12_10_8, SCIFB0_SCK, SEL_SCIFB_0), + PINMUX_IPSR_MSEL(IP12_10_8, MSIOF1_SCK, SEL_SOF1_0), PINMUX_IPSR_DATA(IP12_10_8, CAN_DEBUG_HW_TRIGGER), PINMUX_IPSR_DATA(IP12_13_11, SSI_WS34), - PINMUX_IPSR_MODSEL_DATA(IP12_13_11, STP_IVCXO27_0, SEL_SSP_0), - PINMUX_IPSR_MODSEL_DATA(IP12_13_11, SCIFB0_RXD, SEL_SCIFB_0), + PINMUX_IPSR_MSEL(IP12_13_11, STP_IVCXO27_0, SEL_SSP_0), + PINMUX_IPSR_MSEL(IP12_13_11, SCIFB0_RXD, SEL_SCIFB_0), PINMUX_IPSR_DATA(IP12_13_11, MSIOF1_SYNC), PINMUX_IPSR_DATA(IP12_13_11, CAN_STEP0), PINMUX_IPSR_DATA(IP12_16_14, SSI_SDATA3), - PINMUX_IPSR_MODSEL_DATA(IP12_16_14, STP_ISCLK_0, SEL_SSP_0), - PINMUX_IPSR_MODSEL_DATA(IP12_16_14, SCIFB0_TXD, SEL_SCIFB_0), - PINMUX_IPSR_MODSEL_DATA(IP12_16_14, MSIOF1_SS1, SEL_SOF1_0), + PINMUX_IPSR_MSEL(IP12_16_14, STP_ISCLK_0, SEL_SSP_0), + PINMUX_IPSR_MSEL(IP12_16_14, SCIFB0_TXD, SEL_SCIFB_0), + PINMUX_IPSR_MSEL(IP12_16_14, MSIOF1_SS1, SEL_SOF1_0), PINMUX_IPSR_DATA(IP12_16_14, CAN_TXCLK), PINMUX_IPSR_DATA(IP12_19_17, SSI_SCK4), - PINMUX_IPSR_MODSEL_DATA(IP12_19_17, STP_ISD_0, SEL_SSP_0), - PINMUX_IPSR_MODSEL_DATA(IP12_19_17, SCIFB0_CTS_N, SEL_SCIFB_0), - PINMUX_IPSR_MODSEL_DATA(IP12_19_17, MSIOF1_SS2, SEL_SOF1_0), - PINMUX_IPSR_MODSEL_DATA(IP12_19_17, SSI_SCK5_C, SEL_SSI5_2), + PINMUX_IPSR_MSEL(IP12_19_17, STP_ISD_0, SEL_SSP_0), + PINMUX_IPSR_MSEL(IP12_19_17, SCIFB0_CTS_N, SEL_SCIFB_0), + PINMUX_IPSR_MSEL(IP12_19_17, MSIOF1_SS2, SEL_SOF1_0), + PINMUX_IPSR_MSEL(IP12_19_17, SSI_SCK5_C, SEL_SSI5_2), PINMUX_IPSR_DATA(IP12_19_17, CAN_DEBUGOUT0), PINMUX_IPSR_DATA(IP12_22_20, SSI_WS4), - PINMUX_IPSR_MODSEL_DATA(IP12_22_20, STP_ISEN_0, SEL_SSP_0), - PINMUX_IPSR_MODSEL_DATA(IP12_22_20, SCIFB0_RTS_N, SEL_SCIFB_0), - PINMUX_IPSR_MODSEL_DATA(IP12_22_20, MSIOF1_TXD, SEL_SOF1_0), - PINMUX_IPSR_MODSEL_DATA(IP12_22_20, SSI_WS5_C, SEL_SSI5_2), + PINMUX_IPSR_MSEL(IP12_22_20, STP_ISEN_0, SEL_SSP_0), + PINMUX_IPSR_MSEL(IP12_22_20, SCIFB0_RTS_N, SEL_SCIFB_0), + PINMUX_IPSR_MSEL(IP12_22_20, MSIOF1_TXD, SEL_SOF1_0), + PINMUX_IPSR_MSEL(IP12_22_20, SSI_WS5_C, SEL_SSI5_2), PINMUX_IPSR_DATA(IP12_22_20, CAN_DEBUGOUT1), PINMUX_IPSR_DATA(IP12_24_23, SSI_SDATA4), - PINMUX_IPSR_MODSEL_DATA(IP12_24_23, STP_ISSYNC_0, SEL_SSP_0), - PINMUX_IPSR_MODSEL_DATA(IP12_24_23, MSIOF1_RXD, SEL_SOF1_0), + PINMUX_IPSR_MSEL(IP12_24_23, STP_ISSYNC_0, SEL_SSP_0), + PINMUX_IPSR_MSEL(IP12_24_23, MSIOF1_RXD, SEL_SOF1_0), PINMUX_IPSR_DATA(IP12_24_23, CAN_DEBUGOUT2), - PINMUX_IPSR_MODSEL_DATA(IP12_27_25, SSI_SCK5, SEL_SSI5_0), - PINMUX_IPSR_MODSEL_DATA(IP12_27_25, SCIFB1_SCK, SEL_SCIFB1_0), - PINMUX_IPSR_MODSEL_DATA(IP12_27_25, IERX_B, SEL_IEB_1), + PINMUX_IPSR_MSEL(IP12_27_25, SSI_SCK5, SEL_SSI5_0), + PINMUX_IPSR_MSEL(IP12_27_25, SCIFB1_SCK, SEL_SCIFB1_0), + PINMUX_IPSR_MSEL(IP12_27_25, IERX_B, SEL_IEB_1), PINMUX_IPSR_DATA(IP12_27_25, DU2_EXHSYNC_DU2_HSYNC), PINMUX_IPSR_DATA(IP12_27_25, QSTH_QHS), PINMUX_IPSR_DATA(IP12_27_25, CAN_DEBUGOUT3), - PINMUX_IPSR_MODSEL_DATA(IP12_30_28, SSI_WS5, SEL_SSI5_0), - PINMUX_IPSR_MODSEL_DATA(IP12_30_28, SCIFB1_RXD, SEL_SCIFB1_0), - PINMUX_IPSR_MODSEL_DATA(IP12_30_28, IECLK_B, SEL_IEB_1), + PINMUX_IPSR_MSEL(IP12_30_28, SSI_WS5, SEL_SSI5_0), + PINMUX_IPSR_MSEL(IP12_30_28, SCIFB1_RXD, SEL_SCIFB1_0), + PINMUX_IPSR_MSEL(IP12_30_28, IECLK_B, SEL_IEB_1), PINMUX_IPSR_DATA(IP12_30_28, DU2_EXVSYNC_DU2_VSYNC), PINMUX_IPSR_DATA(IP12_30_28, QSTB_QHE), PINMUX_IPSR_DATA(IP12_30_28, CAN_DEBUGOUT4), - PINMUX_IPSR_MODSEL_DATA(IP13_2_0, SSI_SDATA5, SEL_SSI5_0), - PINMUX_IPSR_MODSEL_DATA(IP13_2_0, SCIFB1_TXD, SEL_SCIFB1_0), - PINMUX_IPSR_MODSEL_DATA(IP13_2_0, IETX_B, SEL_IEB_1), + PINMUX_IPSR_MSEL(IP13_2_0, SSI_SDATA5, SEL_SSI5_0), + PINMUX_IPSR_MSEL(IP13_2_0, SCIFB1_TXD, SEL_SCIFB1_0), + PINMUX_IPSR_MSEL(IP13_2_0, IETX_B, SEL_IEB_1), PINMUX_IPSR_DATA(IP13_2_0, DU2_DR2), PINMUX_IPSR_DATA(IP13_2_0, LCDOUT2), PINMUX_IPSR_DATA(IP13_2_0, CAN_DEBUGOUT5), - PINMUX_IPSR_MODSEL_DATA(IP13_6_3, SSI_SCK6, SEL_SSI6_0), - PINMUX_IPSR_MODSEL_DATA(IP13_6_3, SCIFB1_CTS_N, SEL_SCIFB1_0), - PINMUX_IPSR_MODSEL_DATA(IP13_6_3, BPFCLK_D, SEL_FM_3), + PINMUX_IPSR_MSEL(IP13_6_3, SSI_SCK6, SEL_SSI6_0), + PINMUX_IPSR_MSEL(IP13_6_3, SCIFB1_CTS_N, SEL_SCIFB1_0), + PINMUX_IPSR_MSEL(IP13_6_3, BPFCLK_D, SEL_FM_3), PINMUX_IPSR_DATA(IP13_6_3, DU2_DR3), PINMUX_IPSR_DATA(IP13_6_3, LCDOUT3), PINMUX_IPSR_DATA(IP13_6_3, CAN_DEBUGOUT6), - PINMUX_IPSR_MODSEL_DATA(IP13_6_3, BPFCLK_F, SEL_FM_5), - PINMUX_IPSR_MODSEL_DATA(IP13_9_7, SSI_WS6, SEL_SSI6_0), - PINMUX_IPSR_MODSEL_DATA(IP13_9_7, SCIFB1_RTS_N, SEL_SCIFB1_0), - PINMUX_IPSR_MODSEL_DATA(IP13_9_7, CAN0_TX_D, SEL_CAN0_3), + PINMUX_IPSR_MSEL(IP13_6_3, BPFCLK_F, SEL_FM_5), + PINMUX_IPSR_MSEL(IP13_9_7, SSI_WS6, SEL_SSI6_0), + PINMUX_IPSR_MSEL(IP13_9_7, SCIFB1_RTS_N, SEL_SCIFB1_0), + PINMUX_IPSR_MSEL(IP13_9_7, CAN0_TX_D, SEL_CAN0_3), PINMUX_IPSR_DATA(IP13_9_7, DU2_DR4), PINMUX_IPSR_DATA(IP13_9_7, LCDOUT4), PINMUX_IPSR_DATA(IP13_9_7, CAN_DEBUGOUT7), - PINMUX_IPSR_MODSEL_DATA(IP13_12_10, SSI_SDATA6, SEL_SSI6_0), - PINMUX_IPSR_MODSEL_DATA(IP13_12_10, FMIN_D, SEL_FM_3), + PINMUX_IPSR_MSEL(IP13_12_10, SSI_SDATA6, SEL_SSI6_0), + PINMUX_IPSR_MSEL(IP13_12_10, FMIN_D, SEL_FM_3), PINMUX_IPSR_DATA(IP13_12_10, DU2_DR5), PINMUX_IPSR_DATA(IP13_12_10, LCDOUT5), PINMUX_IPSR_DATA(IP13_12_10, CAN_DEBUGOUT8), - PINMUX_IPSR_MODSEL_DATA(IP13_15_13, SSI_SCK78, SEL_SSI7_0), - PINMUX_IPSR_MODSEL_DATA(IP13_15_13, STP_IVCXO27_1, SEL_SSP_0), - PINMUX_IPSR_MODSEL_DATA(IP13_15_13, SCK1, SEL_SCIF1_0), - PINMUX_IPSR_MODSEL_DATA(IP13_15_13, SCIFA1_SCK, SEL_SCIFA1_0), + PINMUX_IPSR_MSEL(IP13_15_13, SSI_SCK78, SEL_SSI7_0), + PINMUX_IPSR_MSEL(IP13_15_13, STP_IVCXO27_1, SEL_SSP_0), + PINMUX_IPSR_MSEL(IP13_15_13, SCK1, SEL_SCIF1_0), + PINMUX_IPSR_MSEL(IP13_15_13, SCIFA1_SCK, SEL_SCIFA1_0), PINMUX_IPSR_DATA(IP13_15_13, DU2_DR6), PINMUX_IPSR_DATA(IP13_15_13, LCDOUT6), PINMUX_IPSR_DATA(IP13_15_13, CAN_DEBUGOUT9), - PINMUX_IPSR_MODSEL_DATA(IP13_18_16, SSI_WS78, SEL_SSI7_0), - PINMUX_IPSR_MODSEL_DATA(IP13_18_16, STP_ISCLK_1, SEL_SSP_0), - PINMUX_IPSR_MODSEL_DATA(IP13_18_16, SCIFB2_SCK, SEL_SCIFB2_0), + PINMUX_IPSR_MSEL(IP13_18_16, SSI_WS78, SEL_SSI7_0), + PINMUX_IPSR_MSEL(IP13_18_16, STP_ISCLK_1, SEL_SSP_0), + PINMUX_IPSR_MSEL(IP13_18_16, SCIFB2_SCK, SEL_SCIFB2_0), PINMUX_IPSR_DATA(IP13_18_16, SCIFA2_CTS_N), PINMUX_IPSR_DATA(IP13_18_16, DU2_DR7), PINMUX_IPSR_DATA(IP13_18_16, LCDOUT7), PINMUX_IPSR_DATA(IP13_18_16, CAN_DEBUGOUT10), - PINMUX_IPSR_MODSEL_DATA(IP13_22_19, SSI_SDATA7, SEL_SSI7_0), - PINMUX_IPSR_MODSEL_DATA(IP13_22_19, STP_ISD_1, SEL_SSP_0), - PINMUX_IPSR_MODSEL_DATA(IP13_22_19, SCIFB2_RXD, SEL_SCIFB2_0), + PINMUX_IPSR_MSEL(IP13_22_19, SSI_SDATA7, SEL_SSI7_0), + PINMUX_IPSR_MSEL(IP13_22_19, STP_ISD_1, SEL_SSP_0), + PINMUX_IPSR_MSEL(IP13_22_19, SCIFB2_RXD, SEL_SCIFB2_0), PINMUX_IPSR_DATA(IP13_22_19, SCIFA2_RTS_N), PINMUX_IPSR_DATA(IP13_22_19, TCLK2), PINMUX_IPSR_DATA(IP13_22_19, QSTVA_QVS), PINMUX_IPSR_DATA(IP13_22_19, CAN_DEBUGOUT11), - PINMUX_IPSR_MODSEL_DATA(IP13_22_19, BPFCLK_E, SEL_FM_4), - PINMUX_IPSR_MODSEL_DATA(IP13_22_19, SSI_SDATA7_B, SEL_SSI7_1), - PINMUX_IPSR_MODSEL_DATA(IP13_22_19, FMIN_G, SEL_FM_6), - PINMUX_IPSR_MODSEL_DATA(IP13_25_23, SSI_SDATA8, SEL_SSI8_0), - PINMUX_IPSR_MODSEL_DATA(IP13_25_23, STP_ISEN_1, SEL_SSP_0), - PINMUX_IPSR_MODSEL_DATA(IP13_25_23, SCIFB2_TXD, SEL_SCIFB2_0), - PINMUX_IPSR_MODSEL_DATA(IP13_25_23, CAN0_TX_C, SEL_CAN0_2), + PINMUX_IPSR_MSEL(IP13_22_19, BPFCLK_E, SEL_FM_4), + PINMUX_IPSR_MSEL(IP13_22_19, SSI_SDATA7_B, SEL_SSI7_1), + PINMUX_IPSR_MSEL(IP13_22_19, FMIN_G, SEL_FM_6), + PINMUX_IPSR_MSEL(IP13_25_23, SSI_SDATA8, SEL_SSI8_0), + PINMUX_IPSR_MSEL(IP13_25_23, STP_ISEN_1, SEL_SSP_0), + PINMUX_IPSR_MSEL(IP13_25_23, SCIFB2_TXD, SEL_SCIFB2_0), + PINMUX_IPSR_MSEL(IP13_25_23, CAN0_TX_C, SEL_CAN0_2), PINMUX_IPSR_DATA(IP13_25_23, CAN_DEBUGOUT12), - PINMUX_IPSR_MODSEL_DATA(IP13_25_23, SSI_SDATA8_B, SEL_SSI8_1), + PINMUX_IPSR_MSEL(IP13_25_23, SSI_SDATA8_B, SEL_SSI8_1), PINMUX_IPSR_DATA(IP13_28_26, SSI_SDATA9), - PINMUX_IPSR_MODSEL_DATA(IP13_28_26, STP_ISSYNC_1, SEL_SSP_0), - PINMUX_IPSR_MODSEL_DATA(IP13_28_26, SCIFB2_CTS_N, SEL_SCIFB2_0), + PINMUX_IPSR_MSEL(IP13_28_26, STP_ISSYNC_1, SEL_SSP_0), + PINMUX_IPSR_MSEL(IP13_28_26, SCIFB2_CTS_N, SEL_SCIFB2_0), PINMUX_IPSR_DATA(IP13_28_26, SSI_WS1), - PINMUX_IPSR_MODSEL_DATA(IP13_28_26, SSI_SDATA5_C, SEL_SSI5_2), + PINMUX_IPSR_MSEL(IP13_28_26, SSI_SDATA5_C, SEL_SSI5_2), PINMUX_IPSR_DATA(IP13_28_26, CAN_DEBUGOUT13), PINMUX_IPSR_DATA(IP13_30_29, AUDIO_CLKA), - PINMUX_IPSR_MODSEL_DATA(IP13_30_29, SCIFB2_RTS_N, SEL_SCIFB2_0), + PINMUX_IPSR_MSEL(IP13_30_29, SCIFB2_RTS_N, SEL_SCIFB2_0), PINMUX_IPSR_DATA(IP13_30_29, CAN_DEBUGOUT14), PINMUX_IPSR_DATA(IP14_2_0, AUDIO_CLKB), - PINMUX_IPSR_MODSEL_DATA(IP14_2_0, SCIF_CLK, SEL_SCIFCLK_0), - PINMUX_IPSR_MODSEL_DATA(IP14_2_0, CAN0_RX_D, SEL_CAN0_3), + PINMUX_IPSR_MSEL(IP14_2_0, SCIF_CLK, SEL_SCIFCLK_0), + PINMUX_IPSR_MSEL(IP14_2_0, CAN0_RX_D, SEL_CAN0_3), PINMUX_IPSR_DATA(IP14_2_0, DVC_MUTE), - PINMUX_IPSR_MODSEL_DATA(IP14_2_0, CAN0_RX_C, SEL_CAN0_2), + PINMUX_IPSR_MSEL(IP14_2_0, CAN0_RX_C, SEL_CAN0_2), PINMUX_IPSR_DATA(IP14_2_0, CAN_DEBUGOUT15), PINMUX_IPSR_DATA(IP14_2_0, REMOCON), - PINMUX_IPSR_MODSEL_DATA(IP14_5_3, SCIFA0_SCK, SEL_SCFA_0), - PINMUX_IPSR_MODSEL_DATA(IP14_5_3, HSCK1, SEL_HSCIF1_0), + PINMUX_IPSR_MSEL(IP14_5_3, SCIFA0_SCK, SEL_SCFA_0), + PINMUX_IPSR_MSEL(IP14_5_3, HSCK1, SEL_HSCIF1_0), PINMUX_IPSR_DATA(IP14_5_3, SCK0), PINMUX_IPSR_DATA(IP14_5_3, MSIOF3_SS2), PINMUX_IPSR_DATA(IP14_5_3, DU2_DG2), PINMUX_IPSR_DATA(IP14_5_3, LCDOUT10), - PINMUX_IPSR_MODSEL_DATA(IP14_5_3, IIC1_SDA_C, SEL_IIC1_2), - PINMUX_IPSR_MODSEL_DATA(IP14_5_3, I2C1_SDA_C, SEL_I2C1_2), - PINMUX_IPSR_MODSEL_DATA(IP14_8_6, SCIFA0_RXD, SEL_SCFA_0), - PINMUX_IPSR_MODSEL_DATA(IP14_8_6, HRX1, SEL_HSCIF1_0), - PINMUX_IPSR_MODSEL_DATA(IP14_8_6, RX0, SEL_SCIF0_0), + PINMUX_IPSR_MSEL(IP14_5_3, IIC1_SDA_C, SEL_IIC1_2), + PINMUX_IPSR_MSEL(IP14_5_3, I2C1_SDA_C, SEL_I2C1_2), + PINMUX_IPSR_MSEL(IP14_8_6, SCIFA0_RXD, SEL_SCFA_0), + PINMUX_IPSR_MSEL(IP14_8_6, HRX1, SEL_HSCIF1_0), + PINMUX_IPSR_MSEL(IP14_8_6, RX0, SEL_SCIF0_0), PINMUX_IPSR_DATA(IP14_8_6, DU2_DR0), PINMUX_IPSR_DATA(IP14_8_6, LCDOUT0), - PINMUX_IPSR_MODSEL_DATA(IP14_11_9, SCIFA0_TXD, SEL_SCFA_0), - PINMUX_IPSR_MODSEL_DATA(IP14_11_9, HTX1, SEL_HSCIF1_0), - PINMUX_IPSR_MODSEL_DATA(IP14_11_9, TX0, SEL_SCIF0_0), + PINMUX_IPSR_MSEL(IP14_11_9, SCIFA0_TXD, SEL_SCFA_0), + PINMUX_IPSR_MSEL(IP14_11_9, HTX1, SEL_HSCIF1_0), + PINMUX_IPSR_MSEL(IP14_11_9, TX0, SEL_SCIF0_0), PINMUX_IPSR_DATA(IP14_11_9, DU2_DR1), PINMUX_IPSR_DATA(IP14_11_9, LCDOUT1), - PINMUX_IPSR_MODSEL_DATA(IP14_15_12, SCIFA0_CTS_N, SEL_SCFA_0), - PINMUX_IPSR_MODSEL_DATA(IP14_15_12, HCTS1_N, SEL_HSCIF1_0), + PINMUX_IPSR_MSEL(IP14_15_12, SCIFA0_CTS_N, SEL_SCFA_0), + PINMUX_IPSR_MSEL(IP14_15_12, HCTS1_N, SEL_HSCIF1_0), PINMUX_IPSR_DATA(IP14_15_12, CTS0_N), - PINMUX_IPSR_MODSEL_DATA(IP14_15_12, MSIOF3_SYNC, SEL_SOF3_0), + PINMUX_IPSR_MSEL(IP14_15_12, MSIOF3_SYNC, SEL_SOF3_0), PINMUX_IPSR_DATA(IP14_15_12, DU2_DG3), PINMUX_IPSR_DATA(IP14_15_12, LCDOUT11), PINMUX_IPSR_DATA(IP14_15_12, PWM0_B), - PINMUX_IPSR_MODSEL_DATA(IP14_15_12, IIC1_SCL_C, SEL_IIC1_2), - PINMUX_IPSR_MODSEL_DATA(IP14_15_12, I2C1_SCL_C, SEL_I2C1_2), - PINMUX_IPSR_MODSEL_DATA(IP14_18_16, SCIFA0_RTS_N, SEL_SCFA_0), - PINMUX_IPSR_MODSEL_DATA(IP14_18_16, HRTS1_N, SEL_HSCIF1_0), + PINMUX_IPSR_MSEL(IP14_15_12, IIC1_SCL_C, SEL_IIC1_2), + PINMUX_IPSR_MSEL(IP14_15_12, I2C1_SCL_C, SEL_I2C1_2), + PINMUX_IPSR_MSEL(IP14_18_16, SCIFA0_RTS_N, SEL_SCFA_0), + PINMUX_IPSR_MSEL(IP14_18_16, HRTS1_N, SEL_HSCIF1_0), PINMUX_IPSR_DATA(IP14_18_16, RTS0_N), PINMUX_IPSR_DATA(IP14_18_16, MSIOF3_SS1), PINMUX_IPSR_DATA(IP14_18_16, DU2_DG0), PINMUX_IPSR_DATA(IP14_18_16, LCDOUT8), PINMUX_IPSR_DATA(IP14_18_16, PWM1_B), - PINMUX_IPSR_MODSEL_DATA(IP14_21_19, SCIFA1_RXD, SEL_SCIFA1_0), - PINMUX_IPSR_MODSEL_DATA(IP14_21_19, AD_DI, SEL_ADI_0), - PINMUX_IPSR_MODSEL_DATA(IP14_21_19, RX1, SEL_SCIF1_0), + PINMUX_IPSR_MSEL(IP14_21_19, SCIFA1_RXD, SEL_SCIFA1_0), + PINMUX_IPSR_MSEL(IP14_21_19, AD_DI, SEL_ADI_0), + PINMUX_IPSR_MSEL(IP14_21_19, RX1, SEL_SCIF1_0), PINMUX_IPSR_DATA(IP14_21_19, DU2_EXODDF_DU2_ODDF_DISP_CDE), PINMUX_IPSR_DATA(IP14_21_19, QCPV_QDE), - PINMUX_IPSR_MODSEL_DATA(IP14_24_22, SCIFA1_TXD, SEL_SCIFA1_0), - PINMUX_IPSR_MODSEL_DATA(IP14_24_22, AD_DO, SEL_ADI_0), - PINMUX_IPSR_MODSEL_DATA(IP14_24_22, TX1, SEL_SCIF1_0), + PINMUX_IPSR_MSEL(IP14_24_22, SCIFA1_TXD, SEL_SCIFA1_0), + PINMUX_IPSR_MSEL(IP14_24_22, AD_DO, SEL_ADI_0), + PINMUX_IPSR_MSEL(IP14_24_22, TX1, SEL_SCIF1_0), PINMUX_IPSR_DATA(IP14_24_22, DU2_DG1), PINMUX_IPSR_DATA(IP14_24_22, LCDOUT9), - PINMUX_IPSR_MODSEL_DATA(IP14_27_25, SCIFA1_CTS_N, SEL_SCIFA1_0), - PINMUX_IPSR_MODSEL_DATA(IP14_27_25, AD_CLK, SEL_ADI_0), + PINMUX_IPSR_MSEL(IP14_27_25, SCIFA1_CTS_N, SEL_SCIFA1_0), + PINMUX_IPSR_MSEL(IP14_27_25, AD_CLK, SEL_ADI_0), PINMUX_IPSR_DATA(IP14_27_25, CTS1_N), - PINMUX_IPSR_MODSEL_DATA(IP14_27_25, MSIOF3_RXD, SEL_SOF3_0), + PINMUX_IPSR_MSEL(IP14_27_25, MSIOF3_RXD, SEL_SOF3_0), PINMUX_IPSR_DATA(IP14_27_25, DU0_DOTCLKOUT), PINMUX_IPSR_DATA(IP14_27_25, QCLK), - PINMUX_IPSR_MODSEL_DATA(IP14_30_28, SCIFA1_RTS_N, SEL_SCIFA1_0), - PINMUX_IPSR_MODSEL_DATA(IP14_30_28, AD_NCS_N, SEL_ADI_0), + PINMUX_IPSR_MSEL(IP14_30_28, SCIFA1_RTS_N, SEL_SCIFA1_0), + PINMUX_IPSR_MSEL(IP14_30_28, AD_NCS_N, SEL_ADI_0), PINMUX_IPSR_DATA(IP14_30_28, RTS1_N), - PINMUX_IPSR_MODSEL_DATA(IP14_30_28, MSIOF3_TXD, SEL_SOF3_0), + PINMUX_IPSR_MSEL(IP14_30_28, MSIOF3_TXD, SEL_SOF3_0), PINMUX_IPSR_DATA(IP14_30_28, DU1_DOTCLKOUT), PINMUX_IPSR_DATA(IP14_30_28, QSTVB_QVE), - PINMUX_IPSR_MODSEL_DATA(IP14_30_28, HRTS0_N_C, SEL_HSCIF0_2), + PINMUX_IPSR_MSEL(IP14_30_28, HRTS0_N_C, SEL_HSCIF0_2), - PINMUX_IPSR_MODSEL_DATA(IP15_2_0, SCIFA2_SCK, SEL_SCIFA2_0), - PINMUX_IPSR_MODSEL_DATA(IP15_2_0, FMCLK, SEL_FM_0), + PINMUX_IPSR_MSEL(IP15_2_0, SCIFA2_SCK, SEL_SCIFA2_0), + PINMUX_IPSR_MSEL(IP15_2_0, FMCLK, SEL_FM_0), PINMUX_IPSR_DATA(IP15_2_0, SCK2), - PINMUX_IPSR_MODSEL_DATA(IP15_2_0, MSIOF3_SCK, SEL_SOF3_0), + PINMUX_IPSR_MSEL(IP15_2_0, MSIOF3_SCK, SEL_SOF3_0), PINMUX_IPSR_DATA(IP15_2_0, DU2_DG7), PINMUX_IPSR_DATA(IP15_2_0, LCDOUT15), - PINMUX_IPSR_MODSEL_DATA(IP15_2_0, SCIF_CLK_B, SEL_SCIFCLK_1), - PINMUX_IPSR_MODSEL_DATA(IP15_5_3, SCIFA2_RXD, SEL_SCIFA2_0), - PINMUX_IPSR_MODSEL_DATA(IP15_5_3, FMIN, SEL_FM_0), - PINMUX_IPSR_MODSEL_DATA(IP15_5_3, TX2, SEL_SCIF2_0), + PINMUX_IPSR_MSEL(IP15_2_0, SCIF_CLK_B, SEL_SCIFCLK_1), + PINMUX_IPSR_MSEL(IP15_5_3, SCIFA2_RXD, SEL_SCIFA2_0), + PINMUX_IPSR_MSEL(IP15_5_3, FMIN, SEL_FM_0), + PINMUX_IPSR_MSEL(IP15_5_3, TX2, SEL_SCIF2_0), PINMUX_IPSR_DATA(IP15_5_3, DU2_DB0), PINMUX_IPSR_DATA(IP15_5_3, LCDOUT16), - PINMUX_IPSR_MODSEL_DATA(IP15_5_3, IIC2_SCL, SEL_IIC2_0), - PINMUX_IPSR_MODSEL_DATA(IP15_5_3, I2C2_SCL, SEL_I2C2_0), - PINMUX_IPSR_MODSEL_DATA(IP15_8_6, SCIFA2_TXD, SEL_SCIFA2_0), - PINMUX_IPSR_MODSEL_DATA(IP15_8_6, BPFCLK, SEL_FM_0), - PINMUX_IPSR_MODSEL_DATA(IP15_8_6, RX2, SEL_SCIF2_0), + PINMUX_IPSR_MSEL(IP15_5_3, IIC2_SCL, SEL_IIC2_0), + PINMUX_IPSR_MSEL(IP15_5_3, I2C2_SCL, SEL_I2C2_0), + PINMUX_IPSR_MSEL(IP15_8_6, SCIFA2_TXD, SEL_SCIFA2_0), + PINMUX_IPSR_MSEL(IP15_8_6, BPFCLK, SEL_FM_0), + PINMUX_IPSR_MSEL(IP15_8_6, RX2, SEL_SCIF2_0), PINMUX_IPSR_DATA(IP15_8_6, DU2_DB1), PINMUX_IPSR_DATA(IP15_8_6, LCDOUT17), - PINMUX_IPSR_MODSEL_DATA(IP15_8_6, IIC2_SDA, SEL_IIC2_0), - PINMUX_IPSR_MODSEL_DATA(IP15_8_6, I2C2_SDA, SEL_I2C2_0), + PINMUX_IPSR_MSEL(IP15_8_6, IIC2_SDA, SEL_IIC2_0), + PINMUX_IPSR_MSEL(IP15_8_6, I2C2_SDA, SEL_I2C2_0), PINMUX_IPSR_DATA(IP15_11_9, HSCK0), - PINMUX_IPSR_MODSEL_DATA(IP15_11_9, TS_SDEN0, SEL_TSIF0_0), + PINMUX_IPSR_MSEL(IP15_11_9, TS_SDEN0, SEL_TSIF0_0), PINMUX_IPSR_DATA(IP15_11_9, DU2_DG4), PINMUX_IPSR_DATA(IP15_11_9, LCDOUT12), - PINMUX_IPSR_MODSEL_DATA(IP15_11_9, HCTS0_N_C, SEL_HSCIF0_2), - PINMUX_IPSR_MODSEL_DATA(IP15_13_12, HRX0, SEL_HSCIF0_0), + PINMUX_IPSR_MSEL(IP15_11_9, HCTS0_N_C, SEL_HSCIF0_2), + PINMUX_IPSR_MSEL(IP15_13_12, HRX0, SEL_HSCIF0_0), PINMUX_IPSR_DATA(IP15_13_12, DU2_DB2), PINMUX_IPSR_DATA(IP15_13_12, LCDOUT18), - PINMUX_IPSR_MODSEL_DATA(IP15_15_14, HTX0, SEL_HSCIF0_0), + PINMUX_IPSR_MSEL(IP15_15_14, HTX0, SEL_HSCIF0_0), PINMUX_IPSR_DATA(IP15_15_14, DU2_DB3), PINMUX_IPSR_DATA(IP15_15_14, LCDOUT19), - PINMUX_IPSR_MODSEL_DATA(IP15_17_16, HCTS0_N, SEL_HSCIF0_0), + PINMUX_IPSR_MSEL(IP15_17_16, HCTS0_N, SEL_HSCIF0_0), PINMUX_IPSR_DATA(IP15_17_16, SSI_SCK9), PINMUX_IPSR_DATA(IP15_17_16, DU2_DB4), PINMUX_IPSR_DATA(IP15_17_16, LCDOUT20), - PINMUX_IPSR_MODSEL_DATA(IP15_19_18, HRTS0_N, SEL_HSCIF0_0), + PINMUX_IPSR_MSEL(IP15_19_18, HRTS0_N, SEL_HSCIF0_0), PINMUX_IPSR_DATA(IP15_19_18, SSI_WS9), PINMUX_IPSR_DATA(IP15_19_18, DU2_DB5), PINMUX_IPSR_DATA(IP15_19_18, LCDOUT21), - PINMUX_IPSR_MODSEL_DATA(IP15_22_20, MSIOF0_SCK, SEL_SOF0_0), - PINMUX_IPSR_MODSEL_DATA(IP15_22_20, TS_SDAT0, SEL_TSIF0_0), + PINMUX_IPSR_MSEL(IP15_22_20, MSIOF0_SCK, SEL_SOF0_0), + PINMUX_IPSR_MSEL(IP15_22_20, TS_SDAT0, SEL_TSIF0_0), PINMUX_IPSR_DATA(IP15_22_20, ADICLK), PINMUX_IPSR_DATA(IP15_22_20, DU2_DB6), PINMUX_IPSR_DATA(IP15_22_20, LCDOUT22), PINMUX_IPSR_DATA(IP15_25_23, MSIOF0_SYNC), - PINMUX_IPSR_MODSEL_DATA(IP15_25_23, TS_SCK0, SEL_TSIF0_0), + PINMUX_IPSR_MSEL(IP15_25_23, TS_SCK0, SEL_TSIF0_0), PINMUX_IPSR_DATA(IP15_25_23, SSI_SCK2), PINMUX_IPSR_DATA(IP15_25_23, ADIDATA), PINMUX_IPSR_DATA(IP15_25_23, DU2_DB7), PINMUX_IPSR_DATA(IP15_25_23, LCDOUT23), - PINMUX_IPSR_MODSEL_DATA(IP15_25_23, HRX0_C, SEL_SCIFA2_1), - PINMUX_IPSR_MODSEL_DATA(IP15_27_26, MSIOF0_SS1, SEL_SOF0_0), + PINMUX_IPSR_MSEL(IP15_25_23, HRX0_C, SEL_SCIFA2_1), + PINMUX_IPSR_MSEL(IP15_27_26, MSIOF0_SS1, SEL_SOF0_0), PINMUX_IPSR_DATA(IP15_27_26, ADICHS0), PINMUX_IPSR_DATA(IP15_27_26, DU2_DG5), PINMUX_IPSR_DATA(IP15_27_26, LCDOUT13), - PINMUX_IPSR_MODSEL_DATA(IP15_29_28, MSIOF0_TXD, SEL_SOF0_0), + PINMUX_IPSR_MSEL(IP15_29_28, MSIOF0_TXD, SEL_SOF0_0), PINMUX_IPSR_DATA(IP15_29_28, ADICHS1), PINMUX_IPSR_DATA(IP15_29_28, DU2_DG6), PINMUX_IPSR_DATA(IP15_29_28, LCDOUT14), - PINMUX_IPSR_MODSEL_DATA(IP16_2_0, MSIOF0_SS2, SEL_SOF0_0), + PINMUX_IPSR_MSEL(IP16_2_0, MSIOF0_SS2, SEL_SOF0_0), PINMUX_IPSR_DATA(IP16_2_0, AUDIO_CLKOUT), PINMUX_IPSR_DATA(IP16_2_0, ADICHS2), PINMUX_IPSR_DATA(IP16_2_0, DU2_DISP), PINMUX_IPSR_DATA(IP16_2_0, QPOLA), - PINMUX_IPSR_MODSEL_DATA(IP16_2_0, HTX0_C, SEL_HSCIF0_2), - PINMUX_IPSR_MODSEL_DATA(IP16_2_0, SCIFA2_TXD_B, SEL_SCIFA2_1), - PINMUX_IPSR_MODSEL_DATA(IP16_5_3, MSIOF0_RXD, SEL_SOF0_0), - PINMUX_IPSR_MODSEL_DATA(IP16_5_3, TS_SPSYNC0, SEL_TSIF0_0), + PINMUX_IPSR_MSEL(IP16_2_0, HTX0_C, SEL_HSCIF0_2), + PINMUX_IPSR_MSEL(IP16_2_0, SCIFA2_TXD_B, SEL_SCIFA2_1), + PINMUX_IPSR_MSEL(IP16_5_3, MSIOF0_RXD, SEL_SOF0_0), + PINMUX_IPSR_MSEL(IP16_5_3, TS_SPSYNC0, SEL_TSIF0_0), PINMUX_IPSR_DATA(IP16_5_3, SSI_WS2), PINMUX_IPSR_DATA(IP16_5_3, ADICS_SAMP), PINMUX_IPSR_DATA(IP16_5_3, DU2_CDE), PINMUX_IPSR_DATA(IP16_5_3, QPOLB), - PINMUX_IPSR_MODSEL_DATA(IP16_5_3, SCIFA2_RXD_B, SEL_HSCIF0_2), + PINMUX_IPSR_MSEL(IP16_5_3, SCIFA2_RXD_B, SEL_HSCIF0_2), PINMUX_IPSR_DATA(IP16_6, USB1_PWEN), PINMUX_IPSR_DATA(IP16_6, AUDIO_CLKOUT_D), PINMUX_IPSR_DATA(IP16_7, USB1_OVC), - PINMUX_IPSR_MODSEL_DATA(IP16_7, TCLK1_B, SEL_TMU1_1), + PINMUX_IPSR_MSEL(IP16_7, TCLK1_B, SEL_TMU1_1), PINMUX_DATA(IIC0_SCL_MARK, FN_SEL_IIC0_0), PINMUX_DATA(IIC0_SDA_MARK, FN_SEL_IIC0_0), -- cgit v0.10.2 From 759151401c9dc2e929b34c8d7d863c78c8240496 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Thu, 3 Sep 2015 02:50:58 +0000 Subject: pinctrl: sh-pfc: r8a7779: use PINMUX_IPSR_MSEL() Now, PINMUX_IPSR_MSEL() and PINMUX_IPSR_MODSEL_DATA() are same. Current PFC driver is very difficult to read, because macro names are using different length. PINMUX_IPSR_NOGP(ispr, ...) PINMUX_IPSR_DATA(ipsr, ...) PINMUX_IPSR_NOGM(ispr, ...) PINMUX_IPSR_NOFN(ipsr, ...) PINMUX_IPSR_MSEL(ipsr, ...) PINMUX_IPSR_MODSEL_DATA(ipsr, ...) It can be readable if we can use PINMUX_IPSR_MSEL() instead of PINMUX_IPSR_MODSEL_DATA() PINMUX_IPSR_NOGP(ispr, ...) PINMUX_IPSR_DATA(ipsr, ...) PINMUX_IPSR_NOGM(ispr, ...) PINMUX_IPSR_NOFN(ipsr, ...) PINMUX_IPSR_MSEL(ipsr, ...) Signed-off-by: Kuninori Morimoto Acked-by: Laurent Pinchart Acked-by: Linus Walleij Signed-off-by: Geert Uytterhoeven diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c index f5c01e1..4be082e 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c @@ -620,18 +620,18 @@ static const u16 pinmux_data[] = { PINMUX_DATA(USB_PENC1_MARK, FN_USB_PENC1), PINMUX_IPSR_DATA(IP0_2_0, USB_PENC2), - PINMUX_IPSR_MODSEL_DATA(IP0_2_0, SCK0, SEL_SCIF0_0), + PINMUX_IPSR_MSEL(IP0_2_0, SCK0, SEL_SCIF0_0), PINMUX_IPSR_DATA(IP0_2_0, PWM1), - PINMUX_IPSR_MODSEL_DATA(IP0_2_0, PWMFSW0, SEL_PWMFSW_0), - PINMUX_IPSR_MODSEL_DATA(IP0_2_0, SCIF_CLK, SEL_SCIF_0), - PINMUX_IPSR_MODSEL_DATA(IP0_2_0, TCLK0_C, SEL_TMU0_2), + PINMUX_IPSR_MSEL(IP0_2_0, PWMFSW0, SEL_PWMFSW_0), + PINMUX_IPSR_MSEL(IP0_2_0, SCIF_CLK, SEL_SCIF_0), + PINMUX_IPSR_MSEL(IP0_2_0, TCLK0_C, SEL_TMU0_2), PINMUX_IPSR_DATA(IP0_5_3, BS), PINMUX_IPSR_DATA(IP0_5_3, SD1_DAT2), PINMUX_IPSR_DATA(IP0_5_3, MMC0_D2), PINMUX_IPSR_DATA(IP0_5_3, FD2), PINMUX_IPSR_DATA(IP0_5_3, ATADIR0), PINMUX_IPSR_DATA(IP0_5_3, SDSELF), - PINMUX_IPSR_MODSEL_DATA(IP0_5_3, HCTS1, SEL_HSCIF1_0), + PINMUX_IPSR_MSEL(IP0_5_3, HCTS1, SEL_HSCIF1_0), PINMUX_IPSR_DATA(IP0_5_3, TX4_C), PINMUX_IPSR_DATA(IP0_7_6, A0), PINMUX_IPSR_DATA(IP0_7_6, SD1_DAT3), @@ -641,37 +641,37 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_DATA(IP0_9_8, TX5_D), PINMUX_IPSR_DATA(IP0_9_8, HSPI_TX2_B), PINMUX_IPSR_DATA(IP0_11_10, A21), - PINMUX_IPSR_MODSEL_DATA(IP0_11_10, SCK5_D, SEL_SCIF5_3), - PINMUX_IPSR_MODSEL_DATA(IP0_11_10, HSPI_CLK2_B, SEL_HSPI2_1), + PINMUX_IPSR_MSEL(IP0_11_10, SCK5_D, SEL_SCIF5_3), + PINMUX_IPSR_MSEL(IP0_11_10, HSPI_CLK2_B, SEL_HSPI2_1), PINMUX_IPSR_DATA(IP0_13_12, A22), - PINMUX_IPSR_MODSEL_DATA(IP0_13_12, RX5_D, SEL_SCIF5_3), - PINMUX_IPSR_MODSEL_DATA(IP0_13_12, HSPI_RX2_B, SEL_HSPI2_1), + PINMUX_IPSR_MSEL(IP0_13_12, RX5_D, SEL_SCIF5_3), + PINMUX_IPSR_MSEL(IP0_13_12, HSPI_RX2_B, SEL_HSPI2_1), PINMUX_IPSR_DATA(IP0_13_12, VI1_R0), PINMUX_IPSR_DATA(IP0_15_14, A23), PINMUX_IPSR_DATA(IP0_15_14, FCLE), - PINMUX_IPSR_MODSEL_DATA(IP0_15_14, HSPI_CLK2, SEL_HSPI2_0), + PINMUX_IPSR_MSEL(IP0_15_14, HSPI_CLK2, SEL_HSPI2_0), PINMUX_IPSR_DATA(IP0_15_14, VI1_R1), PINMUX_IPSR_DATA(IP0_18_16, A24), PINMUX_IPSR_DATA(IP0_18_16, SD1_CD), PINMUX_IPSR_DATA(IP0_18_16, MMC0_D4), PINMUX_IPSR_DATA(IP0_18_16, FD4), - PINMUX_IPSR_MODSEL_DATA(IP0_18_16, HSPI_CS2, SEL_HSPI2_0), + PINMUX_IPSR_MSEL(IP0_18_16, HSPI_CS2, SEL_HSPI2_0), PINMUX_IPSR_DATA(IP0_18_16, VI1_R2), - PINMUX_IPSR_MODSEL_DATA(IP0_18_16, SSI_WS78_B, SEL_SSI7_1), + PINMUX_IPSR_MSEL(IP0_18_16, SSI_WS78_B, SEL_SSI7_1), PINMUX_IPSR_DATA(IP0_22_19, A25), PINMUX_IPSR_DATA(IP0_22_19, SD1_WP), PINMUX_IPSR_DATA(IP0_22_19, MMC0_D5), PINMUX_IPSR_DATA(IP0_22_19, FD5), - PINMUX_IPSR_MODSEL_DATA(IP0_22_19, HSPI_RX2, SEL_HSPI2_0), + PINMUX_IPSR_MSEL(IP0_22_19, HSPI_RX2, SEL_HSPI2_0), PINMUX_IPSR_DATA(IP0_22_19, VI1_R3), PINMUX_IPSR_DATA(IP0_22_19, TX5_B), - PINMUX_IPSR_MODSEL_DATA(IP0_22_19, SSI_SDATA7_B, SEL_SSI7_1), - PINMUX_IPSR_MODSEL_DATA(IP0_22_19, CTS0_B, SEL_SCIF0_1), + PINMUX_IPSR_MSEL(IP0_22_19, SSI_SDATA7_B, SEL_SSI7_1), + PINMUX_IPSR_MSEL(IP0_22_19, CTS0_B, SEL_SCIF0_1), PINMUX_IPSR_DATA(IP0_24_23, CLKOUT), PINMUX_IPSR_DATA(IP0_24_23, TX3C_IRDA_TX_C), PINMUX_IPSR_DATA(IP0_24_23, PWM0_B), PINMUX_IPSR_DATA(IP0_25, CS0), - PINMUX_IPSR_MODSEL_DATA(IP0_25, HSPI_CS2_B, SEL_HSPI2_1), + PINMUX_IPSR_MSEL(IP0_25, HSPI_CS2_B, SEL_HSPI2_1), PINMUX_IPSR_DATA(IP0_27_26, CS1_A26), PINMUX_IPSR_DATA(IP0_27_26, HSPI_TX2), PINMUX_IPSR_DATA(IP0_27_26, SDSELF_B), @@ -679,11 +679,11 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_DATA(IP0_30_28, FWE), PINMUX_IPSR_DATA(IP0_30_28, ATAG0), PINMUX_IPSR_DATA(IP0_30_28, VI1_R7), - PINMUX_IPSR_MODSEL_DATA(IP0_30_28, HRTS1, SEL_HSCIF1_0), - PINMUX_IPSR_MODSEL_DATA(IP0_30_28, RX4_C, SEL_SCIF4_2), + PINMUX_IPSR_MSEL(IP0_30_28, HRTS1, SEL_HSCIF1_0), + PINMUX_IPSR_MSEL(IP0_30_28, RX4_C, SEL_SCIF4_2), PINMUX_IPSR_DATA(IP1_1_0, EX_CS0), - PINMUX_IPSR_MODSEL_DATA(IP1_1_0, RX3_C_IRDA_RX_C, SEL_SCIF3_2), + PINMUX_IPSR_MSEL(IP1_1_0, RX3_C_IRDA_RX_C, SEL_SCIF3_2), PINMUX_IPSR_DATA(IP1_1_0, MMC0_D6), PINMUX_IPSR_DATA(IP1_1_0, FD6), PINMUX_IPSR_DATA(IP1_3_2, EX_CS1), @@ -700,45 +700,45 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_DATA(IP1_10_7, FRE), PINMUX_IPSR_DATA(IP1_10_7, ATACS10), PINMUX_IPSR_DATA(IP1_10_7, VI1_R4), - PINMUX_IPSR_MODSEL_DATA(IP1_10_7, RX5_B, SEL_SCIF5_1), - PINMUX_IPSR_MODSEL_DATA(IP1_10_7, HSCK1, SEL_HSCIF1_0), - PINMUX_IPSR_MODSEL_DATA(IP1_10_7, SSI_SDATA8_B, SEL_SSI8_1), - PINMUX_IPSR_MODSEL_DATA(IP1_10_7, RTS0_B_TANS_B, SEL_SCIF0_1), - PINMUX_IPSR_MODSEL_DATA(IP1_10_7, SSI_SDATA9, SEL_SSI9_0), + PINMUX_IPSR_MSEL(IP1_10_7, RX5_B, SEL_SCIF5_1), + PINMUX_IPSR_MSEL(IP1_10_7, HSCK1, SEL_HSCIF1_0), + PINMUX_IPSR_MSEL(IP1_10_7, SSI_SDATA8_B, SEL_SSI8_1), + PINMUX_IPSR_MSEL(IP1_10_7, RTS0_B_TANS_B, SEL_SCIF0_1), + PINMUX_IPSR_MSEL(IP1_10_7, SSI_SDATA9, SEL_SSI9_0), PINMUX_IPSR_DATA(IP1_14_11, EX_CS4), PINMUX_IPSR_DATA(IP1_14_11, SD1_DAT0), PINMUX_IPSR_DATA(IP1_14_11, MMC0_D0), PINMUX_IPSR_DATA(IP1_14_11, FD0), PINMUX_IPSR_DATA(IP1_14_11, ATARD0), PINMUX_IPSR_DATA(IP1_14_11, VI1_R5), - PINMUX_IPSR_MODSEL_DATA(IP1_14_11, SCK5_B, SEL_SCIF5_1), + PINMUX_IPSR_MSEL(IP1_14_11, SCK5_B, SEL_SCIF5_1), PINMUX_IPSR_DATA(IP1_14_11, HTX1), PINMUX_IPSR_DATA(IP1_14_11, TX2_E), PINMUX_IPSR_DATA(IP1_14_11, TX0_B), - PINMUX_IPSR_MODSEL_DATA(IP1_14_11, SSI_SCK9, SEL_SSI9_0), + PINMUX_IPSR_MSEL(IP1_14_11, SSI_SCK9, SEL_SSI9_0), PINMUX_IPSR_DATA(IP1_18_15, EX_CS5), PINMUX_IPSR_DATA(IP1_18_15, SD1_DAT1), PINMUX_IPSR_DATA(IP1_18_15, MMC0_D1), PINMUX_IPSR_DATA(IP1_18_15, FD1), PINMUX_IPSR_DATA(IP1_18_15, ATAWR0), PINMUX_IPSR_DATA(IP1_18_15, VI1_R6), - PINMUX_IPSR_MODSEL_DATA(IP1_18_15, HRX1, SEL_HSCIF1_0), - PINMUX_IPSR_MODSEL_DATA(IP1_18_15, RX2_E, SEL_SCIF2_4), - PINMUX_IPSR_MODSEL_DATA(IP1_18_15, RX0_B, SEL_SCIF0_1), - PINMUX_IPSR_MODSEL_DATA(IP1_18_15, SSI_WS9, SEL_SSI9_0), + PINMUX_IPSR_MSEL(IP1_18_15, HRX1, SEL_HSCIF1_0), + PINMUX_IPSR_MSEL(IP1_18_15, RX2_E, SEL_SCIF2_4), + PINMUX_IPSR_MSEL(IP1_18_15, RX0_B, SEL_SCIF0_1), + PINMUX_IPSR_MSEL(IP1_18_15, SSI_WS9, SEL_SSI9_0), PINMUX_IPSR_DATA(IP1_20_19, MLB_CLK), PINMUX_IPSR_DATA(IP1_20_19, PWM2), - PINMUX_IPSR_MODSEL_DATA(IP1_20_19, SCK4, SEL_SCIF4_0), + PINMUX_IPSR_MSEL(IP1_20_19, SCK4, SEL_SCIF4_0), PINMUX_IPSR_DATA(IP1_22_21, MLB_SIG), PINMUX_IPSR_DATA(IP1_22_21, PWM3), PINMUX_IPSR_DATA(IP1_22_21, TX4), PINMUX_IPSR_DATA(IP1_24_23, MLB_DAT), PINMUX_IPSR_DATA(IP1_24_23, PWM4), - PINMUX_IPSR_MODSEL_DATA(IP1_24_23, RX4, SEL_SCIF4_0), + PINMUX_IPSR_MSEL(IP1_24_23, RX4, SEL_SCIF4_0), PINMUX_IPSR_DATA(IP1_28_25, HTX0), PINMUX_IPSR_DATA(IP1_28_25, TX1), PINMUX_IPSR_DATA(IP1_28_25, SDATA), - PINMUX_IPSR_MODSEL_DATA(IP1_28_25, CTS0_C, SEL_SCIF0_2), + PINMUX_IPSR_MSEL(IP1_28_25, CTS0_C, SEL_SCIF0_2), PINMUX_IPSR_DATA(IP1_28_25, SUB_TCK), PINMUX_IPSR_DATA(IP1_28_25, CC5_STATE2), PINMUX_IPSR_DATA(IP1_28_25, CC5_STATE10), @@ -746,39 +746,39 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_DATA(IP1_28_25, CC5_STATE26), PINMUX_IPSR_DATA(IP1_28_25, CC5_STATE34), - PINMUX_IPSR_MODSEL_DATA(IP2_3_0, HRX0, SEL_HSCIF0_0), - PINMUX_IPSR_MODSEL_DATA(IP2_3_0, RX1, SEL_SCIF1_0), + PINMUX_IPSR_MSEL(IP2_3_0, HRX0, SEL_HSCIF0_0), + PINMUX_IPSR_MSEL(IP2_3_0, RX1, SEL_SCIF1_0), PINMUX_IPSR_DATA(IP2_3_0, SCKZ), - PINMUX_IPSR_MODSEL_DATA(IP2_3_0, RTS0_C_TANS_C, SEL_SCIF0_2), + PINMUX_IPSR_MSEL(IP2_3_0, RTS0_C_TANS_C, SEL_SCIF0_2), PINMUX_IPSR_DATA(IP2_3_0, SUB_TDI), PINMUX_IPSR_DATA(IP2_3_0, CC5_STATE3), PINMUX_IPSR_DATA(IP2_3_0, CC5_STATE11), PINMUX_IPSR_DATA(IP2_3_0, CC5_STATE19), PINMUX_IPSR_DATA(IP2_3_0, CC5_STATE27), PINMUX_IPSR_DATA(IP2_3_0, CC5_STATE35), - PINMUX_IPSR_MODSEL_DATA(IP2_7_4, HSCK0, SEL_HSCIF0_0), - PINMUX_IPSR_MODSEL_DATA(IP2_7_4, SCK1, SEL_SCIF1_0), + PINMUX_IPSR_MSEL(IP2_7_4, HSCK0, SEL_HSCIF0_0), + PINMUX_IPSR_MSEL(IP2_7_4, SCK1, SEL_SCIF1_0), PINMUX_IPSR_DATA(IP2_7_4, MTS), PINMUX_IPSR_DATA(IP2_7_4, PWM5), - PINMUX_IPSR_MODSEL_DATA(IP2_7_4, SCK0_C, SEL_SCIF0_2), - PINMUX_IPSR_MODSEL_DATA(IP2_7_4, SSI_SDATA9_B, SEL_SSI9_1), + PINMUX_IPSR_MSEL(IP2_7_4, SCK0_C, SEL_SCIF0_2), + PINMUX_IPSR_MSEL(IP2_7_4, SSI_SDATA9_B, SEL_SSI9_1), PINMUX_IPSR_DATA(IP2_7_4, SUB_TDO), PINMUX_IPSR_DATA(IP2_7_4, CC5_STATE0), PINMUX_IPSR_DATA(IP2_7_4, CC5_STATE8), PINMUX_IPSR_DATA(IP2_7_4, CC5_STATE16), PINMUX_IPSR_DATA(IP2_7_4, CC5_STATE24), PINMUX_IPSR_DATA(IP2_7_4, CC5_STATE32), - PINMUX_IPSR_MODSEL_DATA(IP2_11_8, HCTS0, SEL_HSCIF0_0), - PINMUX_IPSR_MODSEL_DATA(IP2_11_8, CTS1, SEL_SCIF1_0), + PINMUX_IPSR_MSEL(IP2_11_8, HCTS0, SEL_HSCIF0_0), + PINMUX_IPSR_MSEL(IP2_11_8, CTS1, SEL_SCIF1_0), PINMUX_IPSR_DATA(IP2_11_8, STM), PINMUX_IPSR_DATA(IP2_11_8, PWM0_D), - PINMUX_IPSR_MODSEL_DATA(IP2_11_8, RX0_C, SEL_SCIF0_2), - PINMUX_IPSR_MODSEL_DATA(IP2_11_8, SCIF_CLK_C, SEL_SCIF_2), + PINMUX_IPSR_MSEL(IP2_11_8, RX0_C, SEL_SCIF0_2), + PINMUX_IPSR_MSEL(IP2_11_8, SCIF_CLK_C, SEL_SCIF_2), PINMUX_IPSR_DATA(IP2_11_8, SUB_TRST), - PINMUX_IPSR_MODSEL_DATA(IP2_11_8, TCLK1_B, SEL_TMU1_1), + PINMUX_IPSR_MSEL(IP2_11_8, TCLK1_B, SEL_TMU1_1), PINMUX_IPSR_DATA(IP2_11_8, CC5_OSCOUT), - PINMUX_IPSR_MODSEL_DATA(IP2_15_12, HRTS0, SEL_HSCIF0_0), - PINMUX_IPSR_MODSEL_DATA(IP2_15_12, RTS1_TANS, SEL_SCIF1_0), + PINMUX_IPSR_MSEL(IP2_15_12, HRTS0, SEL_HSCIF0_0), + PINMUX_IPSR_MSEL(IP2_15_12, RTS1_TANS, SEL_SCIF1_0), PINMUX_IPSR_DATA(IP2_15_12, MDATA), PINMUX_IPSR_DATA(IP2_15_12, TX0_C), PINMUX_IPSR_DATA(IP2_15_12, SUB_TMS), @@ -789,17 +789,17 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_DATA(IP2_15_12, CC5_STATE33), PINMUX_IPSR_DATA(IP2_18_16, DU0_DR0), PINMUX_IPSR_DATA(IP2_18_16, LCDOUT0), - PINMUX_IPSR_MODSEL_DATA(IP2_18_16, DREQ0, SEL_EXBUS0_0), - PINMUX_IPSR_MODSEL_DATA(IP2_18_16, GPS_CLK_B, SEL_GPS_1), + PINMUX_IPSR_MSEL(IP2_18_16, DREQ0, SEL_EXBUS0_0), + PINMUX_IPSR_MSEL(IP2_18_16, GPS_CLK_B, SEL_GPS_1), PINMUX_IPSR_DATA(IP2_18_16, AUDATA0), PINMUX_IPSR_DATA(IP2_18_16, TX5_C), PINMUX_IPSR_DATA(IP2_21_19, DU0_DR1), PINMUX_IPSR_DATA(IP2_21_19, LCDOUT1), PINMUX_IPSR_DATA(IP2_21_19, DACK0), PINMUX_IPSR_DATA(IP2_21_19, DRACK0), - PINMUX_IPSR_MODSEL_DATA(IP2_21_19, GPS_SIGN_B, SEL_GPS_1), + PINMUX_IPSR_MSEL(IP2_21_19, GPS_SIGN_B, SEL_GPS_1), PINMUX_IPSR_DATA(IP2_21_19, AUDATA1), - PINMUX_IPSR_MODSEL_DATA(IP2_21_19, RX5_C, SEL_SCIF5_2), + PINMUX_IPSR_MSEL(IP2_21_19, RX5_C, SEL_SCIF5_2), PINMUX_IPSR_DATA(IP2_22, DU0_DR2), PINMUX_IPSR_DATA(IP2_22, LCDOUT2), PINMUX_IPSR_DATA(IP2_23, DU0_DR3), @@ -814,14 +814,14 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_DATA(IP2_27, LCDOUT7), PINMUX_IPSR_DATA(IP2_30_28, DU0_DG0), PINMUX_IPSR_DATA(IP2_30_28, LCDOUT8), - PINMUX_IPSR_MODSEL_DATA(IP2_30_28, DREQ1, SEL_EXBUS1_0), - PINMUX_IPSR_MODSEL_DATA(IP2_30_28, SCL2, SEL_I2C2_0), + PINMUX_IPSR_MSEL(IP2_30_28, DREQ1, SEL_EXBUS1_0), + PINMUX_IPSR_MSEL(IP2_30_28, SCL2, SEL_I2C2_0), PINMUX_IPSR_DATA(IP2_30_28, AUDATA2), PINMUX_IPSR_DATA(IP3_2_0, DU0_DG1), PINMUX_IPSR_DATA(IP3_2_0, LCDOUT9), PINMUX_IPSR_DATA(IP3_2_0, DACK1), - PINMUX_IPSR_MODSEL_DATA(IP3_2_0, SDA2, SEL_I2C2_0), + PINMUX_IPSR_MSEL(IP3_2_0, SDA2, SEL_I2C2_0), PINMUX_IPSR_DATA(IP3_2_0, AUDATA3), PINMUX_IPSR_DATA(IP3_3, DU0_DG2), PINMUX_IPSR_DATA(IP3_3, LCDOUT10), @@ -838,16 +838,16 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_DATA(IP3_11_9, DU0_DB0), PINMUX_IPSR_DATA(IP3_11_9, LCDOUT16), PINMUX_IPSR_DATA(IP3_11_9, EX_WAIT1), - PINMUX_IPSR_MODSEL_DATA(IP3_11_9, SCL1, SEL_I2C1_0), - PINMUX_IPSR_MODSEL_DATA(IP3_11_9, TCLK1, SEL_TMU1_0), + PINMUX_IPSR_MSEL(IP3_11_9, SCL1, SEL_I2C1_0), + PINMUX_IPSR_MSEL(IP3_11_9, TCLK1, SEL_TMU1_0), PINMUX_IPSR_DATA(IP3_11_9, AUDATA4), PINMUX_IPSR_DATA(IP3_14_12, DU0_DB1), PINMUX_IPSR_DATA(IP3_14_12, LCDOUT17), PINMUX_IPSR_DATA(IP3_14_12, EX_WAIT2), - PINMUX_IPSR_MODSEL_DATA(IP3_14_12, SDA1, SEL_I2C1_0), - PINMUX_IPSR_MODSEL_DATA(IP3_14_12, GPS_MAG_B, SEL_GPS_1), + PINMUX_IPSR_MSEL(IP3_14_12, SDA1, SEL_I2C1_0), + PINMUX_IPSR_MSEL(IP3_14_12, GPS_MAG_B, SEL_GPS_1), PINMUX_IPSR_DATA(IP3_14_12, AUDATA5), - PINMUX_IPSR_MODSEL_DATA(IP3_14_12, SCK5_C, SEL_SCIF5_2), + PINMUX_IPSR_MSEL(IP3_14_12, SCK5_C, SEL_SCIF5_2), PINMUX_IPSR_DATA(IP3_15, DU0_DB2), PINMUX_IPSR_DATA(IP3_15, LCDOUT18), PINMUX_IPSR_DATA(IP3_16, DU0_DB3), @@ -863,14 +863,14 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_DATA(IP3_22_21, DU0_DOTCLKIN), PINMUX_IPSR_DATA(IP3_22_21, QSTVA_QVS), PINMUX_IPSR_DATA(IP3_22_21, TX3_D_IRDA_TX_D), - PINMUX_IPSR_MODSEL_DATA(IP3_22_21, SCL3_B, SEL_I2C3_1), + PINMUX_IPSR_MSEL(IP3_22_21, SCL3_B, SEL_I2C3_1), PINMUX_IPSR_DATA(IP3_23, DU0_DOTCLKOUT0), PINMUX_IPSR_DATA(IP3_23, QCLK), PINMUX_IPSR_DATA(IP3_26_24, DU0_DOTCLKOUT1), PINMUX_IPSR_DATA(IP3_26_24, QSTVB_QVE), - PINMUX_IPSR_MODSEL_DATA(IP3_26_24, RX3_D_IRDA_RX_D, SEL_SCIF3_3), - PINMUX_IPSR_MODSEL_DATA(IP3_26_24, SDA3_B, SEL_I2C3_1), - PINMUX_IPSR_MODSEL_DATA(IP3_26_24, SDA2_C, SEL_I2C2_2), + PINMUX_IPSR_MSEL(IP3_26_24, RX3_D_IRDA_RX_D, SEL_SCIF3_3), + PINMUX_IPSR_MSEL(IP3_26_24, SDA3_B, SEL_I2C3_1), + PINMUX_IPSR_MSEL(IP3_26_24, SDA2_C, SEL_I2C2_2), PINMUX_IPSR_DATA(IP3_26_24, DACK0_B), PINMUX_IPSR_DATA(IP3_26_24, DRACK0_B), PINMUX_IPSR_DATA(IP3_27, DU0_EXHSYNC_DU0_HSYNC), @@ -881,34 +881,34 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_DATA(IP3_31_29, QCPV_QDE), PINMUX_IPSR_DATA(IP3_31_29, CAN1_TX), PINMUX_IPSR_DATA(IP3_31_29, TX2_C), - PINMUX_IPSR_MODSEL_DATA(IP3_31_29, SCL2_C, SEL_I2C2_2), + PINMUX_IPSR_MSEL(IP3_31_29, SCL2_C, SEL_I2C2_2), PINMUX_IPSR_DATA(IP3_31_29, REMOCON), PINMUX_IPSR_DATA(IP4_1_0, DU0_DISP), PINMUX_IPSR_DATA(IP4_1_0, QPOLA), - PINMUX_IPSR_MODSEL_DATA(IP4_1_0, CAN_CLK_C, SEL_CANCLK_2), - PINMUX_IPSR_MODSEL_DATA(IP4_1_0, SCK2_C, SEL_SCIF2_2), + PINMUX_IPSR_MSEL(IP4_1_0, CAN_CLK_C, SEL_CANCLK_2), + PINMUX_IPSR_MSEL(IP4_1_0, SCK2_C, SEL_SCIF2_2), PINMUX_IPSR_DATA(IP4_4_2, DU0_CDE), PINMUX_IPSR_DATA(IP4_4_2, QPOLB), PINMUX_IPSR_DATA(IP4_4_2, CAN1_RX), - PINMUX_IPSR_MODSEL_DATA(IP4_4_2, RX2_C, SEL_SCIF2_2), - PINMUX_IPSR_MODSEL_DATA(IP4_4_2, DREQ0_B, SEL_EXBUS0_1), - PINMUX_IPSR_MODSEL_DATA(IP4_4_2, SSI_SCK78_B, SEL_SSI7_1), - PINMUX_IPSR_MODSEL_DATA(IP4_4_2, SCK0_B, SEL_SCIF0_1), + PINMUX_IPSR_MSEL(IP4_4_2, RX2_C, SEL_SCIF2_2), + PINMUX_IPSR_MSEL(IP4_4_2, DREQ0_B, SEL_EXBUS0_1), + PINMUX_IPSR_MSEL(IP4_4_2, SSI_SCK78_B, SEL_SSI7_1), + PINMUX_IPSR_MSEL(IP4_4_2, SCK0_B, SEL_SCIF0_1), PINMUX_IPSR_DATA(IP4_7_5, DU1_DR0), PINMUX_IPSR_DATA(IP4_7_5, VI2_DATA0_VI2_B0), PINMUX_IPSR_DATA(IP4_7_5, PWM6), PINMUX_IPSR_DATA(IP4_7_5, SD3_CLK), PINMUX_IPSR_DATA(IP4_7_5, TX3_E_IRDA_TX_E), PINMUX_IPSR_DATA(IP4_7_5, AUDCK), - PINMUX_IPSR_MODSEL_DATA(IP4_7_5, PWMFSW0_B, SEL_PWMFSW_1), + PINMUX_IPSR_MSEL(IP4_7_5, PWMFSW0_B, SEL_PWMFSW_1), PINMUX_IPSR_DATA(IP4_10_8, DU1_DR1), PINMUX_IPSR_DATA(IP4_10_8, VI2_DATA1_VI2_B1), PINMUX_IPSR_DATA(IP4_10_8, PWM0), PINMUX_IPSR_DATA(IP4_10_8, SD3_CMD), - PINMUX_IPSR_MODSEL_DATA(IP4_10_8, RX3_E_IRDA_RX_E, SEL_SCIF3_4), + PINMUX_IPSR_MSEL(IP4_10_8, RX3_E_IRDA_RX_E, SEL_SCIF3_4), PINMUX_IPSR_DATA(IP4_10_8, AUDSYNC), - PINMUX_IPSR_MODSEL_DATA(IP4_10_8, CTS0_D, SEL_SCIF0_3), + PINMUX_IPSR_MSEL(IP4_10_8, CTS0_D, SEL_SCIF0_3), PINMUX_IPSR_DATA(IP4_11, DU1_DR2), PINMUX_IPSR_DATA(IP4_11, VI2_G0), PINMUX_IPSR_DATA(IP4_12, DU1_DR3), @@ -923,18 +923,18 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_DATA(IP4_16, VI2_G5), PINMUX_IPSR_DATA(IP4_19_17, DU1_DG0), PINMUX_IPSR_DATA(IP4_19_17, VI2_DATA2_VI2_B2), - PINMUX_IPSR_MODSEL_DATA(IP4_19_17, SCL1_B, SEL_I2C1_1), + PINMUX_IPSR_MSEL(IP4_19_17, SCL1_B, SEL_I2C1_1), PINMUX_IPSR_DATA(IP4_19_17, SD3_DAT2), - PINMUX_IPSR_MODSEL_DATA(IP4_19_17, SCK3_E, SEL_SCIF3_4), + PINMUX_IPSR_MSEL(IP4_19_17, SCK3_E, SEL_SCIF3_4), PINMUX_IPSR_DATA(IP4_19_17, AUDATA6), PINMUX_IPSR_DATA(IP4_19_17, TX0_D), PINMUX_IPSR_DATA(IP4_22_20, DU1_DG1), PINMUX_IPSR_DATA(IP4_22_20, VI2_DATA3_VI2_B3), - PINMUX_IPSR_MODSEL_DATA(IP4_22_20, SDA1_B, SEL_I2C1_1), + PINMUX_IPSR_MSEL(IP4_22_20, SDA1_B, SEL_I2C1_1), PINMUX_IPSR_DATA(IP4_22_20, SD3_DAT3), - PINMUX_IPSR_MODSEL_DATA(IP4_22_20, SCK5, SEL_SCIF5_0), + PINMUX_IPSR_MSEL(IP4_22_20, SCK5, SEL_SCIF5_0), PINMUX_IPSR_DATA(IP4_22_20, AUDATA7), - PINMUX_IPSR_MODSEL_DATA(IP4_22_20, RX0_D, SEL_SCIF0_3), + PINMUX_IPSR_MSEL(IP4_22_20, RX0_D, SEL_SCIF0_3), PINMUX_IPSR_DATA(IP4_23, DU1_DG2), PINMUX_IPSR_DATA(IP4_23, VI2_G6), PINMUX_IPSR_DATA(IP4_24, DU1_DG3), @@ -949,17 +949,17 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_DATA(IP4_28, VI2_R3), PINMUX_IPSR_DATA(IP4_31_29, DU1_DB0), PINMUX_IPSR_DATA(IP4_31_29, VI2_DATA4_VI2_B4), - PINMUX_IPSR_MODSEL_DATA(IP4_31_29, SCL2_B, SEL_I2C2_1), + PINMUX_IPSR_MSEL(IP4_31_29, SCL2_B, SEL_I2C2_1), PINMUX_IPSR_DATA(IP4_31_29, SD3_DAT0), PINMUX_IPSR_DATA(IP4_31_29, TX5), - PINMUX_IPSR_MODSEL_DATA(IP4_31_29, SCK0_D, SEL_SCIF0_3), + PINMUX_IPSR_MSEL(IP4_31_29, SCK0_D, SEL_SCIF0_3), PINMUX_IPSR_DATA(IP5_2_0, DU1_DB1), PINMUX_IPSR_DATA(IP5_2_0, VI2_DATA5_VI2_B5), - PINMUX_IPSR_MODSEL_DATA(IP5_2_0, SDA2_B, SEL_I2C2_1), + PINMUX_IPSR_MSEL(IP5_2_0, SDA2_B, SEL_I2C2_1), PINMUX_IPSR_DATA(IP5_2_0, SD3_DAT1), - PINMUX_IPSR_MODSEL_DATA(IP5_2_0, RX5, SEL_SCIF5_0), - PINMUX_IPSR_MODSEL_DATA(IP5_2_0, RTS0_D_TANS_D, SEL_SCIF0_3), + PINMUX_IPSR_MSEL(IP5_2_0, RX5, SEL_SCIF5_0), + PINMUX_IPSR_MSEL(IP5_2_0, RTS0_D_TANS_D, SEL_SCIF0_3), PINMUX_IPSR_DATA(IP5_3, DU1_DB2), PINMUX_IPSR_DATA(IP5_3, VI2_R4), PINMUX_IPSR_DATA(IP5_4, DU1_DB3), @@ -969,16 +969,16 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_DATA(IP5_6, DU1_DB5), PINMUX_IPSR_DATA(IP5_6, VI2_R7), PINMUX_IPSR_DATA(IP5_7, DU1_DB6), - PINMUX_IPSR_MODSEL_DATA(IP5_7, SCL2_D, SEL_I2C2_3), + PINMUX_IPSR_MSEL(IP5_7, SCL2_D, SEL_I2C2_3), PINMUX_IPSR_DATA(IP5_8, DU1_DB7), - PINMUX_IPSR_MODSEL_DATA(IP5_8, SDA2_D, SEL_I2C2_3), + PINMUX_IPSR_MSEL(IP5_8, SDA2_D, SEL_I2C2_3), PINMUX_IPSR_DATA(IP5_10_9, DU1_DOTCLKIN), PINMUX_IPSR_DATA(IP5_10_9, VI2_CLKENB), - PINMUX_IPSR_MODSEL_DATA(IP5_10_9, HSPI_CS1, SEL_HSPI1_0), - PINMUX_IPSR_MODSEL_DATA(IP5_10_9, SCL1_D, SEL_I2C1_3), + PINMUX_IPSR_MSEL(IP5_10_9, HSPI_CS1, SEL_HSPI1_0), + PINMUX_IPSR_MSEL(IP5_10_9, SCL1_D, SEL_I2C1_3), PINMUX_IPSR_DATA(IP5_12_11, DU1_DOTCLKOUT), PINMUX_IPSR_DATA(IP5_12_11, VI2_FIELD), - PINMUX_IPSR_MODSEL_DATA(IP5_12_11, SDA1_D, SEL_I2C1_3), + PINMUX_IPSR_MSEL(IP5_12_11, SDA1_D, SEL_I2C1_3), PINMUX_IPSR_DATA(IP5_14_13, DU1_EXHSYNC_DU1_HSYNC), PINMUX_IPSR_DATA(IP5_14_13, VI2_HSYNC), PINMUX_IPSR_DATA(IP5_14_13, VI3_HSYNC), @@ -995,26 +995,26 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_DATA(IP5_20_17, AUDIO_CLKC), PINMUX_IPSR_DATA(IP5_20_17, TX2_D), PINMUX_IPSR_DATA(IP5_20_17, SPEEDIN), - PINMUX_IPSR_MODSEL_DATA(IP5_20_17, GPS_SIGN_D, SEL_GPS_3), + PINMUX_IPSR_MSEL(IP5_20_17, GPS_SIGN_D, SEL_GPS_3), PINMUX_IPSR_DATA(IP5_23_21, DU1_DISP), PINMUX_IPSR_DATA(IP5_23_21, VI2_DATA6_VI2_B6), - PINMUX_IPSR_MODSEL_DATA(IP5_23_21, TCLK0, SEL_TMU0_0), + PINMUX_IPSR_MSEL(IP5_23_21, TCLK0, SEL_TMU0_0), PINMUX_IPSR_DATA(IP5_23_21, QSTVA_B_QVS_B), - PINMUX_IPSR_MODSEL_DATA(IP5_23_21, HSPI_CLK1, SEL_HSPI1_0), - PINMUX_IPSR_MODSEL_DATA(IP5_23_21, SCK2_D, SEL_SCIF2_3), + PINMUX_IPSR_MSEL(IP5_23_21, HSPI_CLK1, SEL_HSPI1_0), + PINMUX_IPSR_MSEL(IP5_23_21, SCK2_D, SEL_SCIF2_3), PINMUX_IPSR_DATA(IP5_23_21, AUDIO_CLKOUT_B), - PINMUX_IPSR_MODSEL_DATA(IP5_23_21, GPS_MAG_D, SEL_GPS_3), + PINMUX_IPSR_MSEL(IP5_23_21, GPS_MAG_D, SEL_GPS_3), PINMUX_IPSR_DATA(IP5_27_24, DU1_CDE), PINMUX_IPSR_DATA(IP5_27_24, VI2_DATA7_VI2_B7), - PINMUX_IPSR_MODSEL_DATA(IP5_27_24, RX3_B_IRDA_RX_B, SEL_SCIF3_1), + PINMUX_IPSR_MSEL(IP5_27_24, RX3_B_IRDA_RX_B, SEL_SCIF3_1), PINMUX_IPSR_DATA(IP5_27_24, SD3_WP), - PINMUX_IPSR_MODSEL_DATA(IP5_27_24, HSPI_RX1, SEL_HSPI1_0), + PINMUX_IPSR_MSEL(IP5_27_24, HSPI_RX1, SEL_HSPI1_0), PINMUX_IPSR_DATA(IP5_27_24, VI1_FIELD), PINMUX_IPSR_DATA(IP5_27_24, VI3_FIELD), PINMUX_IPSR_DATA(IP5_27_24, AUDIO_CLKOUT), - PINMUX_IPSR_MODSEL_DATA(IP5_27_24, RX2_D, SEL_SCIF2_3), - PINMUX_IPSR_MODSEL_DATA(IP5_27_24, GPS_CLK_C, SEL_GPS_2), - PINMUX_IPSR_MODSEL_DATA(IP5_27_24, GPS_CLK_D, SEL_GPS_3), + PINMUX_IPSR_MSEL(IP5_27_24, RX2_D, SEL_SCIF2_3), + PINMUX_IPSR_MSEL(IP5_27_24, GPS_CLK_C, SEL_GPS_2), + PINMUX_IPSR_MSEL(IP5_27_24, GPS_CLK_D, SEL_GPS_3), PINMUX_IPSR_DATA(IP5_28, AUDIO_CLKA), PINMUX_IPSR_DATA(IP5_28, CAN_TXCLK), PINMUX_IPSR_DATA(IP5_30_29, AUDIO_CLKB), @@ -1039,82 +1039,82 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_DATA(IP6_11_9, SSI_SCK34), PINMUX_IPSR_DATA(IP6_11_9, CAN_DEBUGOUT6), PINMUX_IPSR_DATA(IP6_11_9, CAN0_TX_B), - PINMUX_IPSR_MODSEL_DATA(IP6_11_9, IERX, SEL_IE_0), - PINMUX_IPSR_MODSEL_DATA(IP6_11_9, SSI_SCK9_C, SEL_SSI9_2), + PINMUX_IPSR_MSEL(IP6_11_9, IERX, SEL_IE_0), + PINMUX_IPSR_MSEL(IP6_11_9, SSI_SCK9_C, SEL_SSI9_2), PINMUX_IPSR_DATA(IP6_14_12, SSI_WS34), PINMUX_IPSR_DATA(IP6_14_12, CAN_DEBUGOUT7), - PINMUX_IPSR_MODSEL_DATA(IP6_14_12, CAN0_RX_B, SEL_CAN0_1), + PINMUX_IPSR_MSEL(IP6_14_12, CAN0_RX_B, SEL_CAN0_1), PINMUX_IPSR_DATA(IP6_14_12, IETX), - PINMUX_IPSR_MODSEL_DATA(IP6_14_12, SSI_WS9_C, SEL_SSI9_2), + PINMUX_IPSR_MSEL(IP6_14_12, SSI_WS9_C, SEL_SSI9_2), PINMUX_IPSR_DATA(IP6_17_15, SSI_SDATA3), PINMUX_IPSR_DATA(IP6_17_15, PWM0_C), PINMUX_IPSR_DATA(IP6_17_15, CAN_DEBUGOUT8), - PINMUX_IPSR_MODSEL_DATA(IP6_17_15, CAN_CLK_B, SEL_CANCLK_1), - PINMUX_IPSR_MODSEL_DATA(IP6_17_15, IECLK, SEL_IE_0), - PINMUX_IPSR_MODSEL_DATA(IP6_17_15, SCIF_CLK_B, SEL_SCIF_1), - PINMUX_IPSR_MODSEL_DATA(IP6_17_15, TCLK0_B, SEL_TMU0_1), + PINMUX_IPSR_MSEL(IP6_17_15, CAN_CLK_B, SEL_CANCLK_1), + PINMUX_IPSR_MSEL(IP6_17_15, IECLK, SEL_IE_0), + PINMUX_IPSR_MSEL(IP6_17_15, SCIF_CLK_B, SEL_SCIF_1), + PINMUX_IPSR_MSEL(IP6_17_15, TCLK0_B, SEL_TMU0_1), PINMUX_IPSR_DATA(IP6_19_18, SSI_SDATA4), PINMUX_IPSR_DATA(IP6_19_18, CAN_DEBUGOUT9), - PINMUX_IPSR_MODSEL_DATA(IP6_19_18, SSI_SDATA9_C, SEL_SSI9_2), + PINMUX_IPSR_MSEL(IP6_19_18, SSI_SDATA9_C, SEL_SSI9_2), PINMUX_IPSR_DATA(IP6_22_20, SSI_SCK5), PINMUX_IPSR_DATA(IP6_22_20, ADICLK), PINMUX_IPSR_DATA(IP6_22_20, CAN_DEBUGOUT10), - PINMUX_IPSR_MODSEL_DATA(IP6_22_20, SCK3, SEL_SCIF3_0), - PINMUX_IPSR_MODSEL_DATA(IP6_22_20, TCLK0_D, SEL_TMU0_3), + PINMUX_IPSR_MSEL(IP6_22_20, SCK3, SEL_SCIF3_0), + PINMUX_IPSR_MSEL(IP6_22_20, TCLK0_D, SEL_TMU0_3), PINMUX_IPSR_DATA(IP6_24_23, SSI_WS5), - PINMUX_IPSR_MODSEL_DATA(IP6_24_23, ADICS_SAMP, SEL_ADI_0), + PINMUX_IPSR_MSEL(IP6_24_23, ADICS_SAMP, SEL_ADI_0), PINMUX_IPSR_DATA(IP6_24_23, CAN_DEBUGOUT11), PINMUX_IPSR_DATA(IP6_24_23, TX3_IRDA_TX), PINMUX_IPSR_DATA(IP6_26_25, SSI_SDATA5), - PINMUX_IPSR_MODSEL_DATA(IP6_26_25, ADIDATA, SEL_ADI_0), + PINMUX_IPSR_MSEL(IP6_26_25, ADIDATA, SEL_ADI_0), PINMUX_IPSR_DATA(IP6_26_25, CAN_DEBUGOUT12), - PINMUX_IPSR_MODSEL_DATA(IP6_26_25, RX3_IRDA_RX, SEL_SCIF3_0), + PINMUX_IPSR_MSEL(IP6_26_25, RX3_IRDA_RX, SEL_SCIF3_0), PINMUX_IPSR_DATA(IP6_30_29, SSI_SCK6), PINMUX_IPSR_DATA(IP6_30_29, ADICHS0), PINMUX_IPSR_DATA(IP6_30_29, CAN0_TX), - PINMUX_IPSR_MODSEL_DATA(IP6_30_29, IERX_B, SEL_IE_1), + PINMUX_IPSR_MSEL(IP6_30_29, IERX_B, SEL_IE_1), PINMUX_IPSR_DATA(IP7_1_0, SSI_WS6), PINMUX_IPSR_DATA(IP7_1_0, ADICHS1), - PINMUX_IPSR_MODSEL_DATA(IP7_1_0, CAN0_RX, SEL_CAN0_0), + PINMUX_IPSR_MSEL(IP7_1_0, CAN0_RX, SEL_CAN0_0), PINMUX_IPSR_DATA(IP7_1_0, IETX_B), PINMUX_IPSR_DATA(IP7_3_2, SSI_SDATA6), PINMUX_IPSR_DATA(IP7_3_2, ADICHS2), - PINMUX_IPSR_MODSEL_DATA(IP7_3_2, CAN_CLK, SEL_CANCLK_0), - PINMUX_IPSR_MODSEL_DATA(IP7_3_2, IECLK_B, SEL_IE_1), - PINMUX_IPSR_MODSEL_DATA(IP7_6_4, SSI_SCK78, SEL_SSI7_0), + PINMUX_IPSR_MSEL(IP7_3_2, CAN_CLK, SEL_CANCLK_0), + PINMUX_IPSR_MSEL(IP7_3_2, IECLK_B, SEL_IE_1), + PINMUX_IPSR_MSEL(IP7_6_4, SSI_SCK78, SEL_SSI7_0), PINMUX_IPSR_DATA(IP7_6_4, CAN_DEBUGOUT13), - PINMUX_IPSR_MODSEL_DATA(IP7_6_4, IRQ0_B, SEL_INT0_1), - PINMUX_IPSR_MODSEL_DATA(IP7_6_4, SSI_SCK9_B, SEL_SSI9_1), - PINMUX_IPSR_MODSEL_DATA(IP7_6_4, HSPI_CLK1_C, SEL_HSPI1_2), - PINMUX_IPSR_MODSEL_DATA(IP7_9_7, SSI_WS78, SEL_SSI7_0), + PINMUX_IPSR_MSEL(IP7_6_4, IRQ0_B, SEL_INT0_1), + PINMUX_IPSR_MSEL(IP7_6_4, SSI_SCK9_B, SEL_SSI9_1), + PINMUX_IPSR_MSEL(IP7_6_4, HSPI_CLK1_C, SEL_HSPI1_2), + PINMUX_IPSR_MSEL(IP7_9_7, SSI_WS78, SEL_SSI7_0), PINMUX_IPSR_DATA(IP7_9_7, CAN_DEBUGOUT14), - PINMUX_IPSR_MODSEL_DATA(IP7_9_7, IRQ1_B, SEL_INT1_1), - PINMUX_IPSR_MODSEL_DATA(IP7_9_7, SSI_WS9_B, SEL_SSI9_1), - PINMUX_IPSR_MODSEL_DATA(IP7_9_7, HSPI_CS1_C, SEL_HSPI1_2), - PINMUX_IPSR_MODSEL_DATA(IP7_12_10, SSI_SDATA7, SEL_SSI7_0), + PINMUX_IPSR_MSEL(IP7_9_7, IRQ1_B, SEL_INT1_1), + PINMUX_IPSR_MSEL(IP7_9_7, SSI_WS9_B, SEL_SSI9_1), + PINMUX_IPSR_MSEL(IP7_9_7, HSPI_CS1_C, SEL_HSPI1_2), + PINMUX_IPSR_MSEL(IP7_12_10, SSI_SDATA7, SEL_SSI7_0), PINMUX_IPSR_DATA(IP7_12_10, CAN_DEBUGOUT15), - PINMUX_IPSR_MODSEL_DATA(IP7_12_10, IRQ2_B, SEL_INT2_1), - PINMUX_IPSR_MODSEL_DATA(IP7_12_10, TCLK1_C, SEL_TMU1_2), + PINMUX_IPSR_MSEL(IP7_12_10, IRQ2_B, SEL_INT2_1), + PINMUX_IPSR_MSEL(IP7_12_10, TCLK1_C, SEL_TMU1_2), PINMUX_IPSR_DATA(IP7_12_10, HSPI_TX1_C), - PINMUX_IPSR_MODSEL_DATA(IP7_14_13, SSI_SDATA8, SEL_SSI8_0), + PINMUX_IPSR_MSEL(IP7_14_13, SSI_SDATA8, SEL_SSI8_0), PINMUX_IPSR_DATA(IP7_14_13, VSP), - PINMUX_IPSR_MODSEL_DATA(IP7_14_13, IRQ3_B, SEL_INT3_1), - PINMUX_IPSR_MODSEL_DATA(IP7_14_13, HSPI_RX1_C, SEL_HSPI1_2), + PINMUX_IPSR_MSEL(IP7_14_13, IRQ3_B, SEL_INT3_1), + PINMUX_IPSR_MSEL(IP7_14_13, HSPI_RX1_C, SEL_HSPI1_2), PINMUX_IPSR_DATA(IP7_16_15, SD0_CLK), PINMUX_IPSR_DATA(IP7_16_15, ATACS01), - PINMUX_IPSR_MODSEL_DATA(IP7_16_15, SCK1_B, SEL_SCIF1_1), + PINMUX_IPSR_MSEL(IP7_16_15, SCK1_B, SEL_SCIF1_1), PINMUX_IPSR_DATA(IP7_18_17, SD0_CMD), PINMUX_IPSR_DATA(IP7_18_17, ATACS11), PINMUX_IPSR_DATA(IP7_18_17, TX1_B), PINMUX_IPSR_DATA(IP7_18_17, CC5_TDO), PINMUX_IPSR_DATA(IP7_20_19, SD0_DAT0), PINMUX_IPSR_DATA(IP7_20_19, ATADIR1), - PINMUX_IPSR_MODSEL_DATA(IP7_20_19, RX1_B, SEL_SCIF1_1), + PINMUX_IPSR_MSEL(IP7_20_19, RX1_B, SEL_SCIF1_1), PINMUX_IPSR_DATA(IP7_20_19, CC5_TRST), PINMUX_IPSR_DATA(IP7_22_21, SD0_DAT1), PINMUX_IPSR_DATA(IP7_22_21, ATAG1), - PINMUX_IPSR_MODSEL_DATA(IP7_22_21, SCK2_B, SEL_SCIF2_1), + PINMUX_IPSR_MSEL(IP7_22_21, SCK2_B, SEL_SCIF2_1), PINMUX_IPSR_DATA(IP7_22_21, CC5_TMS), PINMUX_IPSR_DATA(IP7_24_23, SD0_DAT2), PINMUX_IPSR_DATA(IP7_24_23, ATARD1), @@ -1122,17 +1122,17 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_DATA(IP7_24_23, CC5_TCK), PINMUX_IPSR_DATA(IP7_26_25, SD0_DAT3), PINMUX_IPSR_DATA(IP7_26_25, ATAWR1), - PINMUX_IPSR_MODSEL_DATA(IP7_26_25, RX2_B, SEL_SCIF2_1), + PINMUX_IPSR_MSEL(IP7_26_25, RX2_B, SEL_SCIF2_1), PINMUX_IPSR_DATA(IP7_26_25, CC5_TDI), PINMUX_IPSR_DATA(IP7_28_27, SD0_CD), - PINMUX_IPSR_MODSEL_DATA(IP7_28_27, DREQ2, SEL_EXBUS2_0), - PINMUX_IPSR_MODSEL_DATA(IP7_28_27, RTS1_B_TANS_B, SEL_SCIF1_1), + PINMUX_IPSR_MSEL(IP7_28_27, DREQ2, SEL_EXBUS2_0), + PINMUX_IPSR_MSEL(IP7_28_27, RTS1_B_TANS_B, SEL_SCIF1_1), PINMUX_IPSR_DATA(IP7_30_29, SD0_WP), PINMUX_IPSR_DATA(IP7_30_29, DACK2), - PINMUX_IPSR_MODSEL_DATA(IP7_30_29, CTS1_B, SEL_SCIF1_1), + PINMUX_IPSR_MSEL(IP7_30_29, CTS1_B, SEL_SCIF1_1), PINMUX_IPSR_DATA(IP8_3_0, HSPI_CLK0), - PINMUX_IPSR_MODSEL_DATA(IP8_3_0, CTS0, SEL_SCIF0_0), + PINMUX_IPSR_MSEL(IP8_3_0, CTS0, SEL_SCIF0_0), PINMUX_IPSR_DATA(IP8_3_0, USB_OVC0), PINMUX_IPSR_DATA(IP8_3_0, AD_CLK), PINMUX_IPSR_DATA(IP8_3_0, CC5_STATE4), @@ -1141,7 +1141,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_DATA(IP8_3_0, CC5_STATE28), PINMUX_IPSR_DATA(IP8_3_0, CC5_STATE36), PINMUX_IPSR_DATA(IP8_7_4, HSPI_CS0), - PINMUX_IPSR_MODSEL_DATA(IP8_7_4, RTS0_TANS, SEL_SCIF0_0), + PINMUX_IPSR_MSEL(IP8_7_4, RTS0_TANS, SEL_SCIF0_0), PINMUX_IPSR_DATA(IP8_7_4, USB_OVC1), PINMUX_IPSR_DATA(IP8_7_4, AD_DI), PINMUX_IPSR_DATA(IP8_7_4, CC5_STATE5), @@ -1159,7 +1159,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_DATA(IP8_11_8, CC5_STATE30), PINMUX_IPSR_DATA(IP8_11_8, CC5_STATE38), PINMUX_IPSR_DATA(IP8_15_12, HSPI_RX0), - PINMUX_IPSR_MODSEL_DATA(IP8_15_12, RX0, SEL_SCIF0_0), + PINMUX_IPSR_MSEL(IP8_15_12, RX0, SEL_SCIF0_0), PINMUX_IPSR_DATA(IP8_15_12, CAN_STEP0), PINMUX_IPSR_DATA(IP8_15_12, AD_NCS), PINMUX_IPSR_DATA(IP8_15_12, CC5_STATE7), @@ -1181,25 +1181,25 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_DATA(IP8_22_21, HTX1_B), PINMUX_IPSR_DATA(IP8_22_21, MT1_SYNC), PINMUX_IPSR_DATA(IP8_24_23, VI0_FIELD), - PINMUX_IPSR_MODSEL_DATA(IP8_24_23, RX1_C, SEL_SCIF1_2), - PINMUX_IPSR_MODSEL_DATA(IP8_24_23, HRX1_B, SEL_HSCIF1_1), + PINMUX_IPSR_MSEL(IP8_24_23, RX1_C, SEL_SCIF1_2), + PINMUX_IPSR_MSEL(IP8_24_23, HRX1_B, SEL_HSCIF1_1), PINMUX_IPSR_DATA(IP8_27_25, VI0_HSYNC), - PINMUX_IPSR_MODSEL_DATA(IP8_27_25, VI0_DATA0_B_VI0_B0_B, SEL_VI0_1), - PINMUX_IPSR_MODSEL_DATA(IP8_27_25, CTS1_C, SEL_SCIF1_2), + PINMUX_IPSR_MSEL(IP8_27_25, VI0_DATA0_B_VI0_B0_B, SEL_VI0_1), + PINMUX_IPSR_MSEL(IP8_27_25, CTS1_C, SEL_SCIF1_2), PINMUX_IPSR_DATA(IP8_27_25, TX4_D), PINMUX_IPSR_DATA(IP8_27_25, MMC1_CMD), - PINMUX_IPSR_MODSEL_DATA(IP8_27_25, HSCK1_B, SEL_HSCIF1_1), + PINMUX_IPSR_MSEL(IP8_27_25, HSCK1_B, SEL_HSCIF1_1), PINMUX_IPSR_DATA(IP8_30_28, VI0_VSYNC), - PINMUX_IPSR_MODSEL_DATA(IP8_30_28, VI0_DATA1_B_VI0_B1_B, SEL_VI0_1), - PINMUX_IPSR_MODSEL_DATA(IP8_30_28, RTS1_C_TANS_C, SEL_SCIF1_2), - PINMUX_IPSR_MODSEL_DATA(IP8_30_28, RX4_D, SEL_SCIF4_3), - PINMUX_IPSR_MODSEL_DATA(IP8_30_28, PWMFSW0_C, SEL_PWMFSW_2), + PINMUX_IPSR_MSEL(IP8_30_28, VI0_DATA1_B_VI0_B1_B, SEL_VI0_1), + PINMUX_IPSR_MSEL(IP8_30_28, RTS1_C_TANS_C, SEL_SCIF1_2), + PINMUX_IPSR_MSEL(IP8_30_28, RX4_D, SEL_SCIF4_3), + PINMUX_IPSR_MSEL(IP8_30_28, PWMFSW0_C, SEL_PWMFSW_2), - PINMUX_IPSR_MODSEL_DATA(IP9_1_0, VI0_DATA0_VI0_B0, SEL_VI0_0), - PINMUX_IPSR_MODSEL_DATA(IP9_1_0, HRTS1_B, SEL_HSCIF1_1), + PINMUX_IPSR_MSEL(IP9_1_0, VI0_DATA0_VI0_B0, SEL_VI0_0), + PINMUX_IPSR_MSEL(IP9_1_0, HRTS1_B, SEL_HSCIF1_1), PINMUX_IPSR_DATA(IP9_1_0, MT1_VCXO), - PINMUX_IPSR_MODSEL_DATA(IP9_3_2, VI0_DATA1_VI0_B1, SEL_VI0_0), - PINMUX_IPSR_MODSEL_DATA(IP9_3_2, HCTS1_B, SEL_HSCIF1_1), + PINMUX_IPSR_MSEL(IP9_3_2, VI0_DATA1_VI0_B1, SEL_VI0_0), + PINMUX_IPSR_MSEL(IP9_3_2, HCTS1_B, SEL_HSCIF1_1), PINMUX_IPSR_DATA(IP9_3_2, MT1_PWM), PINMUX_IPSR_DATA(IP9_4, VI0_DATA2_VI0_B2), PINMUX_IPSR_DATA(IP9_4, MMC1_D0), @@ -1216,12 +1216,12 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_DATA(IP9_11_10, MMC1_D5), PINMUX_IPSR_DATA(IP9_11_10, ARM_TRACEDATA_1), PINMUX_IPSR_DATA(IP9_13_12, VI0_G0), - PINMUX_IPSR_MODSEL_DATA(IP9_13_12, SSI_SCK78_C, SEL_SSI7_2), - PINMUX_IPSR_MODSEL_DATA(IP9_13_12, IRQ0, SEL_INT0_0), + PINMUX_IPSR_MSEL(IP9_13_12, SSI_SCK78_C, SEL_SSI7_2), + PINMUX_IPSR_MSEL(IP9_13_12, IRQ0, SEL_INT0_0), PINMUX_IPSR_DATA(IP9_13_12, ARM_TRACEDATA_2), PINMUX_IPSR_DATA(IP9_15_14, VI0_G1), - PINMUX_IPSR_MODSEL_DATA(IP9_15_14, SSI_WS78_C, SEL_SSI7_2), - PINMUX_IPSR_MODSEL_DATA(IP9_15_14, IRQ1, SEL_INT1_0), + PINMUX_IPSR_MSEL(IP9_15_14, SSI_WS78_C, SEL_SSI7_2), + PINMUX_IPSR_MSEL(IP9_15_14, IRQ1, SEL_INT1_0), PINMUX_IPSR_DATA(IP9_15_14, ARM_TRACEDATA_3), PINMUX_IPSR_DATA(IP9_18_16, VI0_G2), PINMUX_IPSR_DATA(IP9_18_16, ETH_TXD1), @@ -1235,29 +1235,29 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_DATA(IP9_21_19, TS_SDAT0), PINMUX_IPSR_DATA(IP9_23_22, VI0_G4), PINMUX_IPSR_DATA(IP9_23_22, ETH_TX_EN), - PINMUX_IPSR_MODSEL_DATA(IP9_23_22, SD2_DAT0_B, SEL_SD2_1), + PINMUX_IPSR_MSEL(IP9_23_22, SD2_DAT0_B, SEL_SD2_1), PINMUX_IPSR_DATA(IP9_23_22, ARM_TRACEDATA_6), PINMUX_IPSR_DATA(IP9_25_24, VI0_G5), PINMUX_IPSR_DATA(IP9_25_24, ETH_RX_ER), - PINMUX_IPSR_MODSEL_DATA(IP9_25_24, SD2_DAT1_B, SEL_SD2_1), + PINMUX_IPSR_MSEL(IP9_25_24, SD2_DAT1_B, SEL_SD2_1), PINMUX_IPSR_DATA(IP9_25_24, ARM_TRACEDATA_7), PINMUX_IPSR_DATA(IP9_27_26, VI0_G6), PINMUX_IPSR_DATA(IP9_27_26, ETH_RXD0), - PINMUX_IPSR_MODSEL_DATA(IP9_27_26, SD2_DAT2_B, SEL_SD2_1), + PINMUX_IPSR_MSEL(IP9_27_26, SD2_DAT2_B, SEL_SD2_1), PINMUX_IPSR_DATA(IP9_27_26, ARM_TRACEDATA_8), PINMUX_IPSR_DATA(IP9_29_28, VI0_G7), PINMUX_IPSR_DATA(IP9_29_28, ETH_RXD1), - PINMUX_IPSR_MODSEL_DATA(IP9_29_28, SD2_DAT3_B, SEL_SD2_1), + PINMUX_IPSR_MSEL(IP9_29_28, SD2_DAT3_B, SEL_SD2_1), PINMUX_IPSR_DATA(IP9_29_28, ARM_TRACEDATA_9), PINMUX_IPSR_DATA(IP10_2_0, VI0_R0), - PINMUX_IPSR_MODSEL_DATA(IP10_2_0, SSI_SDATA7_C, SEL_SSI7_2), - PINMUX_IPSR_MODSEL_DATA(IP10_2_0, SCK1_C, SEL_SCIF1_2), - PINMUX_IPSR_MODSEL_DATA(IP10_2_0, DREQ1_B, SEL_EXBUS1_0), + PINMUX_IPSR_MSEL(IP10_2_0, SSI_SDATA7_C, SEL_SSI7_2), + PINMUX_IPSR_MSEL(IP10_2_0, SCK1_C, SEL_SCIF1_2), + PINMUX_IPSR_MSEL(IP10_2_0, DREQ1_B, SEL_EXBUS1_0), PINMUX_IPSR_DATA(IP10_2_0, ARM_TRACEDATA_10), - PINMUX_IPSR_MODSEL_DATA(IP10_2_0, DREQ0_C, SEL_EXBUS0_2), + PINMUX_IPSR_MSEL(IP10_2_0, DREQ0_C, SEL_EXBUS0_2), PINMUX_IPSR_DATA(IP10_5_3, VI0_R1), - PINMUX_IPSR_MODSEL_DATA(IP10_5_3, SSI_SDATA8_C, SEL_SSI8_2), + PINMUX_IPSR_MSEL(IP10_5_3, SSI_SDATA8_C, SEL_SSI8_2), PINMUX_IPSR_DATA(IP10_5_3, DACK1_B), PINMUX_IPSR_DATA(IP10_5_3, ARM_TRACEDATA_11), PINMUX_IPSR_DATA(IP10_5_3, DACK0_C), @@ -1265,74 +1265,74 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_DATA(IP10_8_6, VI0_R2), PINMUX_IPSR_DATA(IP10_8_6, ETH_LINK), PINMUX_IPSR_DATA(IP10_8_6, SD2_CLK_B), - PINMUX_IPSR_MODSEL_DATA(IP10_8_6, IRQ2, SEL_INT2_0), + PINMUX_IPSR_MSEL(IP10_8_6, IRQ2, SEL_INT2_0), PINMUX_IPSR_DATA(IP10_8_6, ARM_TRACEDATA_12), PINMUX_IPSR_DATA(IP10_11_9, VI0_R3), PINMUX_IPSR_DATA(IP10_11_9, ETH_MAGIC), - PINMUX_IPSR_MODSEL_DATA(IP10_11_9, SD2_CMD_B, SEL_SD2_1), - PINMUX_IPSR_MODSEL_DATA(IP10_11_9, IRQ3, SEL_INT3_0), + PINMUX_IPSR_MSEL(IP10_11_9, SD2_CMD_B, SEL_SD2_1), + PINMUX_IPSR_MSEL(IP10_11_9, IRQ3, SEL_INT3_0), PINMUX_IPSR_DATA(IP10_11_9, ARM_TRACEDATA_13), PINMUX_IPSR_DATA(IP10_14_12, VI0_R4), PINMUX_IPSR_DATA(IP10_14_12, ETH_REFCLK), - PINMUX_IPSR_MODSEL_DATA(IP10_14_12, SD2_CD_B, SEL_SD2_1), - PINMUX_IPSR_MODSEL_DATA(IP10_14_12, HSPI_CLK1_B, SEL_HSPI1_1), + PINMUX_IPSR_MSEL(IP10_14_12, SD2_CD_B, SEL_SD2_1), + PINMUX_IPSR_MSEL(IP10_14_12, HSPI_CLK1_B, SEL_HSPI1_1), PINMUX_IPSR_DATA(IP10_14_12, ARM_TRACEDATA_14), PINMUX_IPSR_DATA(IP10_14_12, MT1_CLK), PINMUX_IPSR_DATA(IP10_14_12, TS_SCK0), PINMUX_IPSR_DATA(IP10_17_15, VI0_R5), PINMUX_IPSR_DATA(IP10_17_15, ETH_TXD0), - PINMUX_IPSR_MODSEL_DATA(IP10_17_15, SD2_WP_B, SEL_SD2_1), - PINMUX_IPSR_MODSEL_DATA(IP10_17_15, HSPI_CS1_B, SEL_HSPI1_1), + PINMUX_IPSR_MSEL(IP10_17_15, SD2_WP_B, SEL_SD2_1), + PINMUX_IPSR_MSEL(IP10_17_15, HSPI_CS1_B, SEL_HSPI1_1), PINMUX_IPSR_DATA(IP10_17_15, ARM_TRACEDATA_15), PINMUX_IPSR_DATA(IP10_17_15, MT1_D), PINMUX_IPSR_DATA(IP10_17_15, TS_SDEN0), PINMUX_IPSR_DATA(IP10_20_18, VI0_R6), PINMUX_IPSR_DATA(IP10_20_18, ETH_MDC), - PINMUX_IPSR_MODSEL_DATA(IP10_20_18, DREQ2_C, SEL_EXBUS2_2), + PINMUX_IPSR_MSEL(IP10_20_18, DREQ2_C, SEL_EXBUS2_2), PINMUX_IPSR_DATA(IP10_20_18, HSPI_TX1_B), PINMUX_IPSR_DATA(IP10_20_18, TRACECLK), PINMUX_IPSR_DATA(IP10_20_18, MT1_BEN), - PINMUX_IPSR_MODSEL_DATA(IP10_20_18, PWMFSW0_D, SEL_PWMFSW_3), + PINMUX_IPSR_MSEL(IP10_20_18, PWMFSW0_D, SEL_PWMFSW_3), PINMUX_IPSR_DATA(IP10_23_21, VI0_R7), PINMUX_IPSR_DATA(IP10_23_21, ETH_MDIO), PINMUX_IPSR_DATA(IP10_23_21, DACK2_C), - PINMUX_IPSR_MODSEL_DATA(IP10_23_21, HSPI_RX1_B, SEL_HSPI1_1), - PINMUX_IPSR_MODSEL_DATA(IP10_23_21, SCIF_CLK_D, SEL_SCIF_3), + PINMUX_IPSR_MSEL(IP10_23_21, HSPI_RX1_B, SEL_HSPI1_1), + PINMUX_IPSR_MSEL(IP10_23_21, SCIF_CLK_D, SEL_SCIF_3), PINMUX_IPSR_DATA(IP10_23_21, TRACECTL), PINMUX_IPSR_DATA(IP10_23_21, MT1_PEN), PINMUX_IPSR_DATA(IP10_25_24, VI1_CLK), - PINMUX_IPSR_MODSEL_DATA(IP10_25_24, SIM_D, SEL_SIM_0), - PINMUX_IPSR_MODSEL_DATA(IP10_25_24, SDA3, SEL_I2C3_0), + PINMUX_IPSR_MSEL(IP10_25_24, SIM_D, SEL_SIM_0), + PINMUX_IPSR_MSEL(IP10_25_24, SDA3, SEL_I2C3_0), PINMUX_IPSR_DATA(IP10_28_26, VI1_HSYNC), PINMUX_IPSR_DATA(IP10_28_26, VI3_CLK), PINMUX_IPSR_DATA(IP10_28_26, SSI_SCK4), - PINMUX_IPSR_MODSEL_DATA(IP10_28_26, GPS_SIGN_C, SEL_GPS_2), - PINMUX_IPSR_MODSEL_DATA(IP10_28_26, PWMFSW0_E, SEL_PWMFSW_4), + PINMUX_IPSR_MSEL(IP10_28_26, GPS_SIGN_C, SEL_GPS_2), + PINMUX_IPSR_MSEL(IP10_28_26, PWMFSW0_E, SEL_PWMFSW_4), PINMUX_IPSR_DATA(IP10_31_29, VI1_VSYNC), PINMUX_IPSR_DATA(IP10_31_29, AUDIO_CLKOUT_C), PINMUX_IPSR_DATA(IP10_31_29, SSI_WS4), PINMUX_IPSR_DATA(IP10_31_29, SIM_CLK), - PINMUX_IPSR_MODSEL_DATA(IP10_31_29, GPS_MAG_C, SEL_GPS_2), + PINMUX_IPSR_MSEL(IP10_31_29, GPS_MAG_C, SEL_GPS_2), PINMUX_IPSR_DATA(IP10_31_29, SPV_TRST), - PINMUX_IPSR_MODSEL_DATA(IP10_31_29, SCL3, SEL_I2C3_0), + PINMUX_IPSR_MSEL(IP10_31_29, SCL3, SEL_I2C3_0), PINMUX_IPSR_DATA(IP11_2_0, VI1_DATA0_VI1_B0), - PINMUX_IPSR_MODSEL_DATA(IP11_2_0, SD2_DAT0, SEL_SD2_0), + PINMUX_IPSR_MSEL(IP11_2_0, SD2_DAT0, SEL_SD2_0), PINMUX_IPSR_DATA(IP11_2_0, SIM_RST), PINMUX_IPSR_DATA(IP11_2_0, SPV_TCK), PINMUX_IPSR_DATA(IP11_2_0, ADICLK_B), PINMUX_IPSR_DATA(IP11_5_3, VI1_DATA1_VI1_B1), - PINMUX_IPSR_MODSEL_DATA(IP11_5_3, SD2_DAT1, SEL_SD2_0), + PINMUX_IPSR_MSEL(IP11_5_3, SD2_DAT1, SEL_SD2_0), PINMUX_IPSR_DATA(IP11_5_3, MT0_CLK), PINMUX_IPSR_DATA(IP11_5_3, SPV_TMS), - PINMUX_IPSR_MODSEL_DATA(IP11_5_3, ADICS_B_SAMP_B, SEL_ADI_1), + PINMUX_IPSR_MSEL(IP11_5_3, ADICS_B_SAMP_B, SEL_ADI_1), PINMUX_IPSR_DATA(IP11_8_6, VI1_DATA2_VI1_B2), - PINMUX_IPSR_MODSEL_DATA(IP11_8_6, SD2_DAT2, SEL_SD2_0), + PINMUX_IPSR_MSEL(IP11_8_6, SD2_DAT2, SEL_SD2_0), PINMUX_IPSR_DATA(IP11_8_6, MT0_D), PINMUX_IPSR_DATA(IP11_8_6, SPVTDI), - PINMUX_IPSR_MODSEL_DATA(IP11_8_6, ADIDATA_B, SEL_ADI_1), + PINMUX_IPSR_MSEL(IP11_8_6, ADIDATA_B, SEL_ADI_1), PINMUX_IPSR_DATA(IP11_11_9, VI1_DATA3_VI1_B3), - PINMUX_IPSR_MODSEL_DATA(IP11_11_9, SD2_DAT3, SEL_SD2_0), + PINMUX_IPSR_MSEL(IP11_11_9, SD2_DAT3, SEL_SD2_0), PINMUX_IPSR_DATA(IP11_11_9, MT0_BEN), PINMUX_IPSR_DATA(IP11_11_9, SPV_TDO), PINMUX_IPSR_DATA(IP11_11_9, ADICHS0_B), @@ -1340,74 +1340,74 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_DATA(IP11_14_12, SD2_CLK), PINMUX_IPSR_DATA(IP11_14_12, MT0_PEN), PINMUX_IPSR_DATA(IP11_14_12, SPA_TRST), - PINMUX_IPSR_MODSEL_DATA(IP11_14_12, HSPI_CLK1_D, SEL_HSPI1_3), + PINMUX_IPSR_MSEL(IP11_14_12, HSPI_CLK1_D, SEL_HSPI1_3), PINMUX_IPSR_DATA(IP11_14_12, ADICHS1_B), PINMUX_IPSR_DATA(IP11_17_15, VI1_DATA5_VI1_B5), - PINMUX_IPSR_MODSEL_DATA(IP11_17_15, SD2_CMD, SEL_SD2_0), + PINMUX_IPSR_MSEL(IP11_17_15, SD2_CMD, SEL_SD2_0), PINMUX_IPSR_DATA(IP11_17_15, MT0_SYNC), PINMUX_IPSR_DATA(IP11_17_15, SPA_TCK), - PINMUX_IPSR_MODSEL_DATA(IP11_17_15, HSPI_CS1_D, SEL_HSPI1_3), + PINMUX_IPSR_MSEL(IP11_17_15, HSPI_CS1_D, SEL_HSPI1_3), PINMUX_IPSR_DATA(IP11_17_15, ADICHS2_B), PINMUX_IPSR_DATA(IP11_20_18, VI1_DATA6_VI1_B6), - PINMUX_IPSR_MODSEL_DATA(IP11_20_18, SD2_CD, SEL_SD2_0), + PINMUX_IPSR_MSEL(IP11_20_18, SD2_CD, SEL_SD2_0), PINMUX_IPSR_DATA(IP11_20_18, MT0_VCXO), PINMUX_IPSR_DATA(IP11_20_18, SPA_TMS), PINMUX_IPSR_DATA(IP11_20_18, HSPI_TX1_D), PINMUX_IPSR_DATA(IP11_23_21, VI1_DATA7_VI1_B7), - PINMUX_IPSR_MODSEL_DATA(IP11_23_21, SD2_WP, SEL_SD2_0), + PINMUX_IPSR_MSEL(IP11_23_21, SD2_WP, SEL_SD2_0), PINMUX_IPSR_DATA(IP11_23_21, MT0_PWM), PINMUX_IPSR_DATA(IP11_23_21, SPA_TDI), - PINMUX_IPSR_MODSEL_DATA(IP11_23_21, HSPI_RX1_D, SEL_HSPI1_3), + PINMUX_IPSR_MSEL(IP11_23_21, HSPI_RX1_D, SEL_HSPI1_3), PINMUX_IPSR_DATA(IP11_26_24, VI1_G0), PINMUX_IPSR_DATA(IP11_26_24, VI3_DATA0), PINMUX_IPSR_DATA(IP11_26_24, TS_SCK1), - PINMUX_IPSR_MODSEL_DATA(IP11_26_24, DREQ2_B, SEL_EXBUS2_1), + PINMUX_IPSR_MSEL(IP11_26_24, DREQ2_B, SEL_EXBUS2_1), PINMUX_IPSR_DATA(IP11_26_24, TX2), PINMUX_IPSR_DATA(IP11_26_24, SPA_TDO), - PINMUX_IPSR_MODSEL_DATA(IP11_26_24, HCTS0_B, SEL_HSCIF0_1), + PINMUX_IPSR_MSEL(IP11_26_24, HCTS0_B, SEL_HSCIF0_1), PINMUX_IPSR_DATA(IP11_29_27, VI1_G1), PINMUX_IPSR_DATA(IP11_29_27, VI3_DATA1), PINMUX_IPSR_DATA(IP11_29_27, SSI_SCK1), PINMUX_IPSR_DATA(IP11_29_27, TS_SDEN1), PINMUX_IPSR_DATA(IP11_29_27, DACK2_B), - PINMUX_IPSR_MODSEL_DATA(IP11_29_27, RX2, SEL_SCIF2_0), - PINMUX_IPSR_MODSEL_DATA(IP11_29_27, HRTS0_B, SEL_HSCIF0_1), + PINMUX_IPSR_MSEL(IP11_29_27, RX2, SEL_SCIF2_0), + PINMUX_IPSR_MSEL(IP11_29_27, HRTS0_B, SEL_HSCIF0_1), PINMUX_IPSR_DATA(IP12_2_0, VI1_G2), PINMUX_IPSR_DATA(IP12_2_0, VI3_DATA2), PINMUX_IPSR_DATA(IP12_2_0, SSI_WS1), PINMUX_IPSR_DATA(IP12_2_0, TS_SPSYNC1), - PINMUX_IPSR_MODSEL_DATA(IP12_2_0, SCK2, SEL_SCIF2_0), - PINMUX_IPSR_MODSEL_DATA(IP12_2_0, HSCK0_B, SEL_HSCIF0_1), + PINMUX_IPSR_MSEL(IP12_2_0, SCK2, SEL_SCIF2_0), + PINMUX_IPSR_MSEL(IP12_2_0, HSCK0_B, SEL_HSCIF0_1), PINMUX_IPSR_DATA(IP12_5_3, VI1_G3), PINMUX_IPSR_DATA(IP12_5_3, VI3_DATA3), PINMUX_IPSR_DATA(IP12_5_3, SSI_SCK2), PINMUX_IPSR_DATA(IP12_5_3, TS_SDAT1), - PINMUX_IPSR_MODSEL_DATA(IP12_5_3, SCL1_C, SEL_I2C1_2), + PINMUX_IPSR_MSEL(IP12_5_3, SCL1_C, SEL_I2C1_2), PINMUX_IPSR_DATA(IP12_5_3, HTX0_B), PINMUX_IPSR_DATA(IP12_8_6, VI1_G4), PINMUX_IPSR_DATA(IP12_8_6, VI3_DATA4), PINMUX_IPSR_DATA(IP12_8_6, SSI_WS2), - PINMUX_IPSR_MODSEL_DATA(IP12_8_6, SDA1_C, SEL_I2C1_2), + PINMUX_IPSR_MSEL(IP12_8_6, SDA1_C, SEL_I2C1_2), PINMUX_IPSR_DATA(IP12_8_6, SIM_RST_B), - PINMUX_IPSR_MODSEL_DATA(IP12_8_6, HRX0_B, SEL_HSCIF0_1), + PINMUX_IPSR_MSEL(IP12_8_6, HRX0_B, SEL_HSCIF0_1), PINMUX_IPSR_DATA(IP12_11_9, VI1_G5), PINMUX_IPSR_DATA(IP12_11_9, VI3_DATA5), - PINMUX_IPSR_MODSEL_DATA(IP12_11_9, GPS_CLK, SEL_GPS_0), + PINMUX_IPSR_MSEL(IP12_11_9, GPS_CLK, SEL_GPS_0), PINMUX_IPSR_DATA(IP12_11_9, FSE), PINMUX_IPSR_DATA(IP12_11_9, TX4_B), - PINMUX_IPSR_MODSEL_DATA(IP12_11_9, SIM_D_B, SEL_SIM_1), + PINMUX_IPSR_MSEL(IP12_11_9, SIM_D_B, SEL_SIM_1), PINMUX_IPSR_DATA(IP12_14_12, VI1_G6), PINMUX_IPSR_DATA(IP12_14_12, VI3_DATA6), - PINMUX_IPSR_MODSEL_DATA(IP12_14_12, GPS_SIGN, SEL_GPS_0), + PINMUX_IPSR_MSEL(IP12_14_12, GPS_SIGN, SEL_GPS_0), PINMUX_IPSR_DATA(IP12_14_12, FRB), - PINMUX_IPSR_MODSEL_DATA(IP12_14_12, RX4_B, SEL_SCIF4_1), + PINMUX_IPSR_MSEL(IP12_14_12, RX4_B, SEL_SCIF4_1), PINMUX_IPSR_DATA(IP12_14_12, SIM_CLK_B), PINMUX_IPSR_DATA(IP12_17_15, VI1_G7), PINMUX_IPSR_DATA(IP12_17_15, VI3_DATA7), - PINMUX_IPSR_MODSEL_DATA(IP12_17_15, GPS_MAG, SEL_GPS_0), + PINMUX_IPSR_MSEL(IP12_17_15, GPS_MAG, SEL_GPS_0), PINMUX_IPSR_DATA(IP12_17_15, FCE), - PINMUX_IPSR_MODSEL_DATA(IP12_17_15, SCK4_B, SEL_SCIF4_1), + PINMUX_IPSR_MSEL(IP12_17_15, SCK4_B, SEL_SCIF4_1), }; static const struct sh_pfc_pin pinmux_pins[] = { -- cgit v0.10.2 From 5451d09259d59e37430575676e3344cf41735b33 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Thu, 3 Sep 2015 02:51:21 +0000 Subject: pinctrl: sh-pfc: remove unused PINMUX_IPSR_MODSEL_DATA() Now, all PINMUX_IPSR_MODSEL_DATA() are replased to PINMUX_IPSR_MSEL() Let's remove unused PINMUX_IPSR_MODSEL_DATA() Signed-off-by: Kuninori Morimoto Acked-by: Laurent Pinchart Acked-by: Linus Walleij Signed-off-by: Geert Uytterhoeven diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h index baf9b9b..e00a4b1 100644 --- a/drivers/pinctrl/sh-pfc/sh_pfc.h +++ b/drivers/pinctrl/sh-pfc/sh_pfc.h @@ -174,8 +174,6 @@ struct sh_pfc_soc_info { PINMUX_DATA(fn##_MARK, FN_##ipsr, FN_##ms) #define PINMUX_IPSR_MSEL(ipsr, fn, ms) \ PINMUX_DATA(fn##_MARK, FN_##ms, FN_##ipsr, FN_##fn) -#define PINMUX_IPSR_MODSEL_DATA(ipsr, fn, ms) \ - PINMUX_DATA(fn##_MARK, FN_##ms, FN_##ipsr, FN_##fn) /* * GP port style (32 ports banks) -- cgit v0.10.2 From 0b0ffc96dbe30fa9d966a6f8a9ce9f276fd4007f Mon Sep 17 00:00:00 2001 From: Takeshi Kihara Date: Thu, 3 Sep 2015 02:51:49 +0000 Subject: pinctrl: sh-pfc: Initial R8A7795 PFC support Add PFC base support for the R8A7795 SoC. Signed-off-by: Takeshi Kihara [Morimoto-san: updated] Signed-off-by: Kuninori Morimoto Acked-by: Linus Walleij Signed-off-by: Geert Uytterhoeven diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt index 9496934..ffadb7a 100644 --- a/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt @@ -19,6 +19,7 @@ Required Properties: - "renesas,pfc-r8a7791": for R8A7791 (R-Car M2-W) compatible pin-controller. - "renesas,pfc-r8a7793": for R8A7793 (R-Car M2-N) compatible pin-controller. - "renesas,pfc-r8a7794": for R8A7794 (R-Car E2) compatible pin-controller. + - "renesas,pfc-r8a7795": for R8A7795 (R-Car H3) compatible pin-controller. - "renesas,pfc-sh73a0": for SH73A0 (SH-Mobile AG5) compatible pin-controller. - reg: Base address and length of each memory resource used by the pin diff --git a/drivers/pinctrl/sh-pfc/Kconfig b/drivers/pinctrl/sh-pfc/Kconfig index 8e024c9..35d6e95 100644 --- a/drivers/pinctrl/sh-pfc/Kconfig +++ b/drivers/pinctrl/sh-pfc/Kconfig @@ -65,6 +65,11 @@ config PINCTRL_PFC_R8A7794 depends on ARCH_R8A7794 select PINCTRL_SH_PFC +config PINCTRL_PFC_R8A7795 + def_bool y + depends on ARCH_R8A7795 + select PINCTRL_SH_PFC + config PINCTRL_PFC_SH7203 def_bool y depends on CPU_SUBTYPE_SH7203 diff --git a/drivers/pinctrl/sh-pfc/Makefile b/drivers/pinctrl/sh-pfc/Makefile index ea2a60e..173305f 100644 --- a/drivers/pinctrl/sh-pfc/Makefile +++ b/drivers/pinctrl/sh-pfc/Makefile @@ -12,6 +12,7 @@ obj-$(CONFIG_PINCTRL_PFC_R8A7790) += pfc-r8a7790.o obj-$(CONFIG_PINCTRL_PFC_R8A7791) += pfc-r8a7791.o obj-$(CONFIG_PINCTRL_PFC_R8A7793) += pfc-r8a7791.o obj-$(CONFIG_PINCTRL_PFC_R8A7794) += pfc-r8a7794.o +obj-$(CONFIG_PINCTRL_PFC_R8A7795) += pfc-r8a7795.o obj-$(CONFIG_PINCTRL_PFC_SH7203) += pfc-sh7203.o obj-$(CONFIG_PINCTRL_PFC_SH7264) += pfc-sh7264.o obj-$(CONFIG_PINCTRL_PFC_SH7269) += pfc-sh7269.o diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c index fb9c448..bcf3017 100644 --- a/drivers/pinctrl/sh-pfc/core.c +++ b/drivers/pinctrl/sh-pfc/core.c @@ -489,6 +489,12 @@ static const struct of_device_id sh_pfc_of_table[] = { .data = &r8a7794_pinmux_info, }, #endif +#ifdef CONFIG_PINCTRL_PFC_R8A7795 + { + .compatible = "renesas,pfc-r8a7795", + .data = &r8a7795_pinmux_info, + }, +#endif #ifdef CONFIG_PINCTRL_PFC_SH73A0 { .compatible = "renesas,pfc-sh73a0", diff --git a/drivers/pinctrl/sh-pfc/core.h b/drivers/pinctrl/sh-pfc/core.h index c38ace4..62f53b2 100644 --- a/drivers/pinctrl/sh-pfc/core.h +++ b/drivers/pinctrl/sh-pfc/core.h @@ -75,6 +75,7 @@ extern const struct sh_pfc_soc_info r8a7790_pinmux_info; extern const struct sh_pfc_soc_info r8a7791_pinmux_info; extern const struct sh_pfc_soc_info r8a7793_pinmux_info; extern const struct sh_pfc_soc_info r8a7794_pinmux_info; +extern const struct sh_pfc_soc_info r8a7795_pinmux_info; extern const struct sh_pfc_soc_info sh7203_pinmux_info; extern const struct sh_pfc_soc_info sh7264_pinmux_info; extern const struct sh_pfc_soc_info sh7269_pinmux_info; diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c new file mode 100644 index 0000000..79abfaa --- /dev/null +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c @@ -0,0 +1,2005 @@ +/* + * R-Car Gen3 processor support - PFC hardware block. + * + * Copyright (C) 2015 Renesas Electronics Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + */ + +#include +#include + +#include "core.h" +#include "sh_pfc.h" + +#define PORT_GP_3(bank, fn, sfx) \ + PORT_GP_1(bank, 0, fn, sfx), PORT_GP_1(bank, 1, fn, sfx), \ + PORT_GP_1(bank, 2, fn, sfx), PORT_GP_1(bank, 3, fn, sfx) + +#define PORT_GP_14(bank, fn, sfx) \ + PORT_GP_3(bank, fn, sfx), \ + PORT_GP_1(bank, 4, fn, sfx), PORT_GP_1(bank, 5, fn, sfx), \ + PORT_GP_1(bank, 6, fn, sfx), PORT_GP_1(bank, 7, fn, sfx), \ + PORT_GP_1(bank, 8, fn, sfx), PORT_GP_1(bank, 9, fn, sfx), \ + PORT_GP_1(bank, 10, fn, sfx), PORT_GP_1(bank, 11, fn, sfx), \ + PORT_GP_1(bank, 12, fn, sfx), PORT_GP_1(bank, 13, fn, sfx), \ + PORT_GP_1(bank, 14, fn, sfx) + +#define PORT_GP_15(bank, fn, sfx) \ + PORT_GP_14(bank, fn, sfx), PORT_GP_1(bank, 15, fn, sfx) + +#define PORT_GP_17(bank, fn, sfx) \ + PORT_GP_15(bank, fn, sfx), \ + PORT_GP_1(bank, 16, fn, sfx), PORT_GP_1(bank, 17, fn, sfx) + +#define PORT_GP_25(bank, fn, sfx) \ + PORT_GP_17(bank, fn, sfx), \ + PORT_GP_1(bank, 18, fn, sfx), PORT_GP_1(bank, 19, fn, sfx), \ + PORT_GP_1(bank, 20, fn, sfx), PORT_GP_1(bank, 21, fn, sfx), \ + PORT_GP_1(bank, 22, fn, sfx), PORT_GP_1(bank, 23, fn, sfx), \ + PORT_GP_1(bank, 24, fn, sfx), PORT_GP_1(bank, 25, fn, sfx) + +#define PORT_GP_27(bank, fn, sfx) \ + PORT_GP_25(bank, fn, sfx), \ + PORT_GP_1(bank, 26, fn, sfx), PORT_GP_1(bank, 27, fn, sfx) + +#define CPU_ALL_PORT(fn, sfx) \ + PORT_GP_15(0, fn, sfx), \ + PORT_GP_27(1, fn, sfx), \ + PORT_GP_14(2, fn, sfx), \ + PORT_GP_15(3, fn, sfx), \ + PORT_GP_17(4, fn, sfx), \ + PORT_GP_25(5, fn, sfx), \ + PORT_GP_32(6, fn, sfx), \ + PORT_GP_3(7, fn, sfx) +/* + * F_() : just information + * FM() : macro for FN_xxx / xxx_MARK + */ + +/* GPSR0 */ +#define GPSR0_15 F_(D15, IP7_11_8) +#define GPSR0_14 F_(D14, IP7_7_4) +#define GPSR0_13 F_(D13, IP7_3_0) +#define GPSR0_12 F_(D12, IP6_31_28) +#define GPSR0_11 F_(D11, IP6_27_24) +#define GPSR0_10 F_(D10, IP6_23_20) +#define GPSR0_9 F_(D9, IP6_19_16) +#define GPSR0_8 F_(D8, IP6_15_12) +#define GPSR0_7 F_(D7, IP6_11_8) +#define GPSR0_6 F_(D6, IP6_7_4) +#define GPSR0_5 F_(D5, IP6_3_0) +#define GPSR0_4 F_(D4, IP5_31_28) +#define GPSR0_3 F_(D3, IP5_27_24) +#define GPSR0_2 F_(D2, IP5_23_20) +#define GPSR0_1 F_(D1, IP5_19_16) +#define GPSR0_0 F_(D0, IP5_15_12) + +/* GPSR1 */ +#define GPSR1_27 F_(EX_WAIT0_A, IP5_11_8) +#define GPSR1_26 F_(WE1_N, IP5_7_4) +#define GPSR1_25 F_(WE0_N, IP5_3_0) +#define GPSR1_24 F_(RD_WR_N, IP4_31_28) +#define GPSR1_23 F_(RD_N, IP4_27_24) +#define GPSR1_22 F_(BS_N, IP4_23_20) +#define GPSR1_21 F_(CS1_N_A26, IP4_19_16) +#define GPSR1_20 F_(CS0_N, IP4_15_12) +#define GPSR1_19 F_(A19, IP4_11_8) +#define GPSR1_18 F_(A18, IP4_7_4) +#define GPSR1_17 F_(A17, IP4_3_0) +#define GPSR1_16 F_(A16, IP3_31_28) +#define GPSR1_15 F_(A15, IP3_27_24) +#define GPSR1_14 F_(A14, IP3_23_20) +#define GPSR1_13 F_(A13, IP3_19_16) +#define GPSR1_12 F_(A12, IP3_15_12) +#define GPSR1_11 F_(A11, IP3_11_8) +#define GPSR1_10 F_(A10, IP3_7_4) +#define GPSR1_9 F_(A9, IP3_3_0) +#define GPSR1_8 F_(A8, IP2_31_28) +#define GPSR1_7 F_(A7, IP2_27_24) +#define GPSR1_6 F_(A6, IP2_23_20) +#define GPSR1_5 F_(A5, IP2_19_16) +#define GPSR1_4 F_(A4, IP2_15_12) +#define GPSR1_3 F_(A3, IP2_11_8) +#define GPSR1_2 F_(A2, IP2_7_4) +#define GPSR1_1 F_(A1, IP2_3_0) +#define GPSR1_0 F_(A0, IP1_31_28) + +/* GPSR2 */ +#define GPSR2_14 F_(AVB_AVTP_CAPTURE_A, IP0_23_20) +#define GPSR2_13 F_(AVB_AVTP_MATCH_A, IP0_19_16) +#define GPSR2_12 F_(AVB_LINK, IP0_15_12) +#define GPSR2_11 F_(AVB_PHY_INT, IP0_11_8) +#define GPSR2_10 F_(AVB_MAGIC, IP0_7_4) +#define GPSR2_9 F_(AVB_MDC, IP0_3_0) +#define GPSR2_8 F_(PWM2_A, IP1_27_24) +#define GPSR2_7 F_(PWM1_A, IP1_23_20) +#define GPSR2_6 F_(PWM0, IP1_19_16) +#define GPSR2_5 F_(IRQ5, IP1_15_12) +#define GPSR2_4 F_(IRQ4, IP1_11_8) +#define GPSR2_3 F_(IRQ3, IP1_7_4) +#define GPSR2_2 F_(IRQ2, IP1_3_0) +#define GPSR2_1 F_(IRQ1, IP0_31_28) +#define GPSR2_0 F_(IRQ0, IP0_27_24) + +/* GPSR3 */ +#define GPSR3_15 F_(SD1_WP, IP10_23_20) +#define GPSR3_14 F_(SD1_CD, IP10_19_16) +#define GPSR3_13 F_(SD0_WP, IP10_15_12) +#define GPSR3_12 F_(SD0_CD, IP10_11_8) +#define GPSR3_11 F_(SD1_DAT3, IP8_31_28) +#define GPSR3_10 F_(SD1_DAT2, IP8_27_24) +#define GPSR3_9 F_(SD1_DAT1, IP8_23_20) +#define GPSR3_8 F_(SD1_DAT0, IP8_19_16) +#define GPSR3_7 F_(SD1_CMD, IP8_15_12) +#define GPSR3_6 F_(SD1_CLK, IP8_11_8) +#define GPSR3_5 F_(SD0_DAT3, IP8_7_4) +#define GPSR3_4 F_(SD0_DAT2, IP8_3_0) +#define GPSR3_3 F_(SD0_DAT1, IP7_31_28) +#define GPSR3_2 F_(SD0_DAT0, IP7_27_24) +#define GPSR3_1 F_(SD0_CMD, IP7_23_20) +#define GPSR3_0 F_(SD0_CLK, IP7_19_16) + +/* GPSR4 */ +#define GPSR4_17 FM(SD3_DS) +#define GPSR4_16 F_(SD3_DAT7, IP10_7_4) +#define GPSR4_15 F_(SD3_DAT6, IP10_3_0) +#define GPSR4_14 F_(SD3_DAT5, IP9_31_28) +#define GPSR4_13 F_(SD3_DAT4, IP9_27_24) +#define GPSR4_12 FM(SD3_DAT3) +#define GPSR4_11 FM(SD3_DAT2) +#define GPSR4_10 FM(SD3_DAT1) +#define GPSR4_9 FM(SD3_DAT0) +#define GPSR4_8 FM(SD3_CMD) +#define GPSR4_7 FM(SD3_CLK) +#define GPSR4_6 F_(SD2_DS, IP9_23_20) +#define GPSR4_5 F_(SD2_DAT3, IP9_19_16) +#define GPSR4_4 F_(SD2_DAT2, IP9_15_12) +#define GPSR4_3 F_(SD2_DAT1, IP9_11_8) +#define GPSR4_2 F_(SD2_DAT0, IP9_7_4) +#define GPSR4_1 FM(SD2_CMD) +#define GPSR4_0 F_(SD2_CLK, IP9_3_0) + +/* GPSR5 */ +#define GPSR5_25 F_(MLB_DAT, IP13_19_16) +#define GPSR5_24 F_(MLB_SIG, IP13_15_12) +#define GPSR5_23 F_(MLB_CLK, IP13_11_8) +#define GPSR5_22 FM(MSIOF0_RXD) +#define GPSR5_21 F_(MSIOF0_SS2, IP13_7_4) +#define GPSR5_20 FM(MSIOF0_TXD) +#define GPSR5_19 F_(MSIOF0_SS1, IP13_3_0) +#define GPSR5_18 F_(MSIOF0_SYNC, IP12_31_28) +#define GPSR5_17 FM(MSIOF0_SCK) +#define GPSR5_16 F_(HRTS0_N, IP12_27_24) +#define GPSR5_15 F_(HCTS0_N, IP12_23_20) +#define GPSR5_14 F_(HTX0, IP12_19_16) +#define GPSR5_13 F_(HRX0, IP12_15_12) +#define GPSR5_12 F_(HSCK0, IP12_11_8) +#define GPSR5_11 F_(RX2_A, IP12_7_4) +#define GPSR5_10 F_(TX2_A, IP12_3_0) +#define GPSR5_9 F_(SCK2, IP11_31_28) +#define GPSR5_8 F_(RTS1_N_TANS, IP11_27_24) +#define GPSR5_7 F_(CTS1_N, IP11_23_20) +#define GPSR5_6 F_(TX1_A, IP11_19_16) +#define GPSR5_5 F_(RX1_A, IP11_15_12) +#define GPSR5_4 F_(RTS0_N_TANS, IP11_11_8) +#define GPSR5_3 F_(CTS0_N, IP11_7_4) +#define GPSR5_2 F_(TX0, IP11_3_0) +#define GPSR5_1 F_(RX0, IP10_31_28) +#define GPSR5_0 F_(SCK0, IP10_27_24) + +/* GPSR6 */ +#define GPSR6_31 F_(USB31_OVC, IP17_7_4) +#define GPSR6_30 F_(USB31_PWEN, IP17_3_0) +#define GPSR6_29 F_(USB30_OVC, IP16_31_28) +#define GPSR6_28 F_(USB30_PWEN, IP16_27_24) +#define GPSR6_27 F_(USB1_OVC, IP16_23_20) +#define GPSR6_26 F_(USB1_PWEN, IP16_19_16) +#define GPSR6_25 F_(USB0_OVC, IP16_15_12) +#define GPSR6_24 F_(USB0_PWEN, IP16_11_8) +#define GPSR6_23 F_(AUDIO_CLKB_B, IP16_7_4) +#define GPSR6_22 F_(AUDIO_CLKA_A, IP16_3_0) +#define GPSR6_21 F_(SSI_SDATA9_A, IP15_31_28) +#define GPSR6_20 F_(SSI_SDATA8, IP15_27_24) +#define GPSR6_19 F_(SSI_SDATA7, IP15_23_20) +#define GPSR6_18 F_(SSI_WS78, IP15_19_16) +#define GPSR6_17 F_(SSI_SCK78, IP15_15_12) +#define GPSR6_16 F_(SSI_SDATA6, IP15_11_8) +#define GPSR6_15 F_(SSI_WS6, IP15_7_4) +#define GPSR6_14 F_(SSI_SCK6, IP15_3_0) +#define GPSR6_13 FM(SSI_SDATA5) +#define GPSR6_12 FM(SSI_WS5) +#define GPSR6_11 FM(SSI_SCK5) +#define GPSR6_10 F_(SSI_SDATA4, IP14_31_28) +#define GPSR6_9 F_(SSI_WS4, IP14_27_24) +#define GPSR6_8 F_(SSI_SCK4, IP14_23_20) +#define GPSR6_7 F_(SSI_SDATA3, IP14_19_16) +#define GPSR6_6 F_(SSI_WS34, IP14_15_12) +#define GPSR6_5 F_(SSI_SCK34, IP14_11_8) +#define GPSR6_4 F_(SSI_SDATA2_A, IP14_7_4) +#define GPSR6_3 F_(SSI_SDATA1_A, IP14_3_0) +#define GPSR6_2 F_(SSI_SDATA0, IP13_31_28) +#define GPSR6_1 F_(SSI_WS0129, IP13_27_24) +#define GPSR6_0 F_(SSI_SCK0129, IP13_23_20) + +/* GPSR7 */ +#define GPSR7_3 FM(HDMI1_CEC) +#define GPSR7_2 FM(HDMI0_CEC) +#define GPSR7_1 FM(AVS2) +#define GPSR7_0 FM(AVS1) + + +/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */ +#define IP0_3_0 FM(AVB_MDC) F_(0, 0) FM(MSIOF2_SS2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0_7_4 FM(AVB_MAGIC) F_(0, 0) FM(MSIOF2_SS1_C) FM(SCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0_11_8 FM(AVB_PHY_INT) F_(0, 0) FM(MSIOF2_SYNC_C) FM(RX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0_15_12 FM(AVB_LINK) F_(0, 0) FM(MSIOF2_SCK_C) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0_19_16 FM(AVB_AVTP_MATCH_A) F_(0, 0) FM(MSIOF2_RXD_C) FM(CTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0_23_20 FM(AVB_AVTP_CAPTURE_A) F_(0, 0) FM(MSIOF2_TXD_C) FM(RTS4_N_TANS_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0_27_24 FM(IRQ0) FM(QPOLB) F_(0, 0) FM(DU_CDE) FM(VI4_DATA0_B) FM(CAN0_TX_B) FM(CANFD0_TX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANFD0_RX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1_3_0 FM(IRQ2) FM(QCPV_QDE) F_(0, 0) FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(VI4_DATA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1_7_4 FM(IRQ3) FM(QSTVB_QVE) FM(A25) FM(DU_DOTCLKOUT1) FM(VI4_DATA3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1_11_8 FM(IRQ4) FM(QSTH_QHS) FM(A24) FM(DU_EXHSYNC_DU_HSYNC) FM(VI4_DATA4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1_15_12 FM(IRQ5) FM(QSTB_QHE) FM(A23) FM(DU_EXVSYNC_DU_VSYNC) FM(VI4_DATA5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1_19_16 FM(PWM0) FM(AVB_AVTP_PPS)FM(A22) F_(0, 0) FM(VI4_DATA6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IECLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1_23_20 FM(PWM1_A) F_(0, 0) FM(A21) FM(HRX3_D) FM(VI4_DATA7_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IERX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1_27_24 FM(PWM2_A) F_(0, 0) FM(A20) FM(HTX3_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IETX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1_31_28 FM(A0) FM(LCDOUT16) FM(MSIOF3_SYNC_B) F_(0, 0) FM(VI4_DATA8) F_(0, 0) FM(DU_DB0) F_(0, 0) F_(0, 0) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2_3_0 FM(A1) FM(LCDOUT17) FM(MSIOF3_TXD_B) F_(0, 0) FM(VI4_DATA9) F_(0, 0) FM(DU_DB1) F_(0, 0) F_(0, 0) FM(PWM4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2_7_4 FM(A2) FM(LCDOUT18) FM(MSIOF3_SCK_B) F_(0, 0) FM(VI4_DATA10) F_(0, 0) FM(DU_DB2) F_(0, 0) F_(0, 0) FM(PWM5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2_11_8 FM(A3) FM(LCDOUT19) FM(MSIOF3_RXD_B) F_(0, 0) FM(VI4_DATA11) F_(0, 0) FM(DU_DB3) F_(0, 0) F_(0, 0) FM(PWM6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) + +/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */ +#define IP2_15_12 FM(A4) FM(LCDOUT20) FM(MSIOF3_SS1_B) F_(0, 0) FM(VI4_DATA12) FM(VI5_DATA12) FM(DU_DB4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2_19_16 FM(A5) FM(LCDOUT21) FM(MSIOF3_SS2_B) FM(SCK4_B) FM(VI4_DATA13) FM(VI5_DATA13) FM(DU_DB5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2_23_20 FM(A6) FM(LCDOUT22) FM(MSIOF2_SS1_A) FM(RX4_B) FM(VI4_DATA14) FM(VI5_DATA14) FM(DU_DB6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2_27_24 FM(A7) FM(LCDOUT23) FM(MSIOF2_SS2_A) FM(TX4_B) FM(VI4_DATA15) FM(VI5_DATA15) FM(DU_DB7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2_31_28 FM(A8) FM(RX3_B) FM(MSIOF2_SYNC_A) FM(HRX4_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(SDA6_A) FM(AVB_AVTP_MATCH_B) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP3_3_0 FM(A9) F_(0, 0) FM(MSIOF2_SCK_A) FM(CTS4_N_B) F_(0, 0) FM(VI5_VSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP3_7_4 FM(A10) F_(0, 0) FM(MSIOF2_RXD_A) FM(RTS4_N_TANS_B) F_(0, 0) FM(VI5_HSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP3_11_8 FM(A11) FM(TX3_B) FM(MSIOF2_TXD_A) FM(HTX4_B) FM(HSCK4) FM(VI5_FIELD) F_(0, 0) FM(SCL6_A) FM(AVB_AVTP_CAPTURE_B) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP3_15_12 FM(A12) FM(LCDOUT12) FM(MSIOF3_SCK_C) F_(0, 0) FM(HRX4_A) FM(VI5_DATA8) FM(DU_DG4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP3_19_16 FM(A13) FM(LCDOUT13) FM(MSIOF3_SYNC_C) F_(0, 0) FM(HTX4_A) FM(VI5_DATA9) FM(DU_DG5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP3_23_20 FM(A14) FM(LCDOUT14) FM(MSIOF3_RXD_C) F_(0, 0) FM(HCTS4_N) FM(VI5_DATA10) FM(DU_DG6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP3_27_24 FM(A15) FM(LCDOUT15) FM(MSIOF3_TXD_C) F_(0, 0) FM(HRTS4_N) FM(VI5_DATA11) FM(DU_DG7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP3_31_28 FM(A16) FM(LCDOUT8) F_(0, 0) F_(0, 0) FM(VI4_FIELD) F_(0, 0) FM(DU_DG0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP4_3_0 FM(A17) FM(LCDOUT9) F_(0, 0) F_(0, 0) FM(VI4_VSYNC_N) F_(0, 0) FM(DU_DG1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP4_7_4 FM(A18) FM(LCDOUT10) F_(0, 0) F_(0, 0) FM(VI4_HSYNC_N) F_(0, 0) FM(DU_DG2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP4_11_8 FM(A19) FM(LCDOUT11) F_(0, 0) F_(0, 0) FM(VI4_CLKENB) F_(0, 0) FM(DU_DG3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP4_15_12 FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLKENB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP4_19_16 FM(CS1_N_A26) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLK) F_(0, 0) FM(EX_WAIT0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP4_23_20 FM(BS_N) FM(QSTVA_QVS) FM(MSIOF3_SCK_D) FM(SCK3) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN1_TX) FM(CANFD1_TX) FM(IETX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP4_27_24 FM(RD_N) F_(0, 0) FM(MSIOF3_SYNC_D) FM(RX3_A) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_TX_A) FM(CANFD0_TX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP4_31_28 FM(RD_WR_N) F_(0, 0) FM(MSIOF3_RXD_D) FM(TX3_A) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_RX_A) FM(CANFD0_RX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP5_3_0 FM(WE0_N) F_(0, 0) FM(MSIOF3_TXD_D) FM(CTS3_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) FM(SCL6_B) FM(CAN_CLK) F_(0, 0) FM(IECLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP5_7_4 FM(WE1_N) F_(0, 0) FM(MSIOF3_SS1_D) FM(RTS3_N_TANS) FM(HRTS3_N) F_(0, 0) F_(0, 0) FM(SDA6_B) FM(CAN1_RX) FM(CANFD1_RX) FM(IERX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP5_11_8 FM(EX_WAIT0_A) FM(QCLK) F_(0, 0) F_(0, 0) FM(VI4_CLK) F_(0, 0) FM(DU_DOTCLKOUT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP5_15_12 FM(D0) FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A) F_(0, 0) FM(VI4_DATA16) FM(VI5_DATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP5_19_16 FM(D1) FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A) F_(0, 0) FM(VI4_DATA17) FM(VI5_DATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP5_23_20 FM(D2) F_(0, 0) FM(MSIOF3_RXD_A) F_(0, 0) FM(VI4_DATA18) FM(VI5_DATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP5_27_24 FM(D3) F_(0, 0) FM(MSIOF3_TXD_A) F_(0, 0) FM(VI4_DATA19) FM(VI5_DATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP5_31_28 FM(D4) FM(MSIOF2_SCK_B)F_(0, 0) F_(0, 0) FM(VI4_DATA20) FM(VI5_DATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP6_3_0 FM(D5) FM(MSIOF2_SYNC_B)F_(0, 0) F_(0, 0) FM(VI4_DATA21) FM(VI5_DATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP6_7_4 FM(D6) FM(MSIOF2_RXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA22) FM(VI5_DATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP6_11_8 FM(D7) FM(MSIOF2_TXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA23) FM(VI5_DATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP6_15_12 FM(D8) FM(LCDOUT0) FM(MSIOF2_SCK_D) FM(SCK4_C) FM(VI4_DATA0_A) F_(0, 0) FM(DU_DR0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP6_19_16 FM(D9) FM(LCDOUT1) FM(MSIOF2_SYNC_D) F_(0, 0) FM(VI4_DATA1_A) F_(0, 0) FM(DU_DR1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP6_23_20 FM(D10) FM(LCDOUT2) FM(MSIOF2_RXD_D) FM(HRX3_B) FM(VI4_DATA2_A) FM(CTS4_N_C) FM(DU_DR2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP6_27_24 FM(D11) FM(LCDOUT3) FM(MSIOF2_TXD_D) FM(HTX3_B) FM(VI4_DATA3_A) FM(RTS4_N_TANS_C)FM(DU_DR3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP6_31_28 FM(D12) FM(LCDOUT4) FM(MSIOF2_SS1_D) FM(RX4_C) FM(VI4_DATA4_A) F_(0, 0) FM(DU_DR4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP7_3_0 FM(D13) FM(LCDOUT5) FM(MSIOF2_SS2_D) FM(TX4_C) FM(VI4_DATA5_A) F_(0, 0) FM(DU_DR5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP7_7_4 FM(D14) FM(LCDOUT6) FM(MSIOF3_SS1_A) FM(HRX3_C) FM(VI4_DATA6_A) F_(0, 0) FM(DU_DR6) FM(SCL6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP7_11_8 FM(D15) FM(LCDOUT7) FM(MSIOF3_SS2_A) FM(HTX3_C) FM(VI4_DATA7_A) F_(0, 0) FM(DU_DR7) FM(SDA6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP7_15_12 FM(FSCLKST) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP7_19_16 FM(SD0_CLK) F_(0, 0) FM(MSIOF1_SCK_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) + +/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */ +#define IP7_23_20 FM(SD0_CMD) F_(0, 0) FM(MSIOF1_SYNC_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP7_27_24 FM(SD0_DAT0) F_(0, 0) FM(MSIOF1_RXD_E) F_(0, 0) F_(0, 0) FM(TS_SCK0_B) FM(STP_ISCLK_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP7_31_28 FM(SD0_DAT1) F_(0, 0) FM(MSIOF1_TXD_E) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_B)FM(STP_ISSYNC_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP8_3_0 FM(SD0_DAT2) F_(0, 0) FM(MSIOF1_SS1_E) F_(0, 0) F_(0, 0) FM(TS_SDAT0_B) FM(STP_ISD_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP8_7_4 FM(SD0_DAT3) F_(0, 0) FM(MSIOF1_SS2_E) F_(0, 0) F_(0, 0) FM(TS_SDEN0_B) FM(STP_ISEN_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP8_11_8 FM(SD1_CLK) F_(0, 0) FM(MSIOF1_SCK_G) F_(0, 0) F_(0, 0) FM(SIM0_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP8_15_12 FM(SD1_CMD) F_(0, 0) FM(MSIOF1_SYNC_G) F_(0, 0) F_(0, 0) FM(SIM0_D_A) FM(STP_IVCXO27_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP8_19_16 FM(SD1_DAT0) FM(SD2_DAT4) FM(MSIOF1_RXD_G) F_(0, 0) F_(0, 0) FM(TS_SCK1_B) FM(STP_ISCLK_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP8_23_20 FM(SD1_DAT1) FM(SD2_DAT5) FM(MSIOF1_TXD_G) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP8_27_24 FM(SD1_DAT2) FM(SD2_DAT6) FM(MSIOF1_SS1_G) F_(0, 0) F_(0, 0) FM(TS_SDAT1_B) FM(STP_ISD_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP8_31_28 FM(SD1_DAT3) FM(SD2_DAT7) FM(MSIOF1_SS2_G) F_(0, 0) F_(0, 0) FM(TS_SDEN1_B) FM(STP_ISEN_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP9_3_0 FM(SD2_CLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP9_7_4 FM(SD2_DAT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP9_11_8 FM(SD2_DAT1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP9_15_12 FM(SD2_DAT2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP9_19_16 FM(SD2_DAT3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP9_23_20 FM(SD2_DS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP9_27_24 FM(SD3_DAT4) FM(SD2_CD_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP9_31_28 FM(SD3_DAT5) FM(SD2_WP_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP10_3_0 FM(SD3_DAT6) FM(SD3_CD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP10_7_4 FM(SD3_DAT7) FM(SD3_WP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP10_11_8 FM(SD0_CD) F_(0, 0) F_(0, 0) F_(0, 0) FM(SCL2_B) FM(SIM0_RST_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP10_15_12 FM(SD0_WP) F_(0, 0) F_(0, 0) F_(0, 0) FM(SDA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP10_19_16 FM(SD1_CD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SIM0_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP10_23_20 FM(SD1_WP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SIM0_D_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP10_27_24 FM(SCK0) FM(HSCK1_B) FM(MSIOF1_SS2_B) FM(AUDIO_CLKC_B) FM(SDA2_A) FM(SIM0_RST_B) FM(STP_OPWM_0_C) FM(RIF0_CLK_B) F_(0, 0) FM(ADICHS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP10_31_28 FM(RX0) FM(HRX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK0_C) FM(STP_ISCLK_0_C) FM(RIF0_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP11_3_0 FM(TX0) FM(HTX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C) FM(RIF0_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP11_7_4 FM(CTS0_N) FM(HCTS1_N_B) FM(MSIOF1_SYNC_B) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C) FM(RIF1_SYNC_B) FM(AUDIO_CLKOUT_C) FM(ADICS_SAMP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP11_11_8 FM(RTS0_N_TANS) FM(HRTS1_N_B) FM(MSIOF1_SS1_B) FM(AUDIO_CLKA_B) FM(SCL2_A) F_(0, 0) FM(STP_IVCXO27_1_C) FM(RIF0_SYNC_B) F_(0, 0) FM(ADICHS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP11_15_12 FM(RX1_A) FM(HRX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT0_C) FM(STP_ISD_0_C) FM(RIF1_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP11_19_16 FM(TX1_A) FM(HTX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDEN0_C) FM(STP_ISEN_0_C) FM(RIF1_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP11_23_20 FM(CTS1_N) FM(HCTS1_N_A) FM(MSIOF1_RXD_B) F_(0, 0) F_(0, 0) FM(TS_SDEN1_C) FM(STP_ISEN_1_C) FM(RIF1_D0_B) F_(0, 0) FM(ADIDATA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP11_27_24 FM(RTS1_N_TANS) FM(HRTS1_N_A) FM(MSIOF1_TXD_B) F_(0, 0) F_(0, 0) FM(TS_SDAT1_C) FM(STP_ISD_1_C) FM(RIF1_D1_B) F_(0, 0) FM(ADICHS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP11_31_28 FM(SCK2) FM(SCIF_CLK_B) FM(MSIOF1_SCK_B) F_(0, 0) F_(0, 0) FM(TS_SCK1_C) FM(STP_ISCLK_1_C) FM(RIF1_CLK_B) F_(0, 0) FM(ADICLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP12_3_0 FM(TX2_A) F_(0, 0) F_(0, 0) FM(SD2_CD_B) FM(SCL1_A) F_(0, 0) FM(FMCLK_A) FM(RIF1_D1_C) F_(0, 0) FM(FSO_CFE_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP12_7_4 FM(RX2_A) F_(0, 0) F_(0, 0) FM(SD2_WP_B) FM(SDA1_A) F_(0, 0) FM(FMIN_A) FM(RIF1_SYNC_C) F_(0, 0) FM(FSO_CFE_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP12_11_8 FM(HSCK0) F_(0, 0) FM(MSIOF1_SCK_D) FM(AUDIO_CLKB_A) FM(SSI_SDATA1_B)FM(TS_SCK0_D) FM(STP_ISCLK_0_D) FM(RIF0_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP12_15_12 FM(HRX0) F_(0, 0) FM(MSIOF1_RXD_D) F_(0, 0) FM(SSI_SDATA2_B)FM(TS_SDEN0_D) FM(STP_ISEN_0_D) FM(RIF0_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP12_19_16 FM(HTX0) F_(0, 0) FM(MSIOF1_TXD_D) F_(0, 0) FM(SSI_SDATA9_B)FM(TS_SDAT0_D) FM(STP_ISD_0_D) FM(RIF0_D1_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP12_23_20 FM(HCTS0_N) FM(RX2_B) FM(MSIOF1_SYNC_D) F_(0, 0) FM(SSI_SCK9_A) FM(TS_SPSYNC0_D)FM(STP_ISSYNC_0_D) FM(RIF0_SYNC_C) FM(AUDIO_CLKOUT1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP12_27_24 FM(HRTS0_N) FM(TX2_B) FM(MSIOF1_SS1_D) F_(0, 0) FM(SSI_WS9_A) F_(0, 0) FM(STP_IVCXO27_0_D) FM(BPFCLK_A) FM(AUDIO_CLKOUT2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) + +/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */ +#define IP12_31_28 FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP13_3_0 FM(MSIOF0_SS1) FM(RX5) F_(0, 0) FM(AUDIO_CLKA_C) FM(SSI_SCK2_A) F_(0, 0) FM(STP_IVCXO27_0_C) F_(0, 0) FM(AUDIO_CLKOUT3_A) F_(0, 0) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP13_7_4 FM(MSIOF0_SS2) FM(TX5) FM(MSIOF1_SS2_D) FM(AUDIO_CLKC_A) FM(SSI_WS2_A) F_(0, 0) FM(STP_OPWM_0_D) F_(0, 0) FM(AUDIO_CLKOUT_D) F_(0, 0) FM(SPEEDIN_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP13_11_8 FM(MLB_CLK) F_(0, 0) FM(MSIOF1_SCK_F) F_(0, 0) FM(SCL1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP13_15_12 FM(MLB_SIG) FM(RX1_B) FM(MSIOF1_SYNC_F) F_(0, 0) FM(SDA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP13_19_16 FM(MLB_DAT) FM(TX1_B) FM(MSIOF1_RXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP13_23_20 FM(SSI_SCK0129) F_(0, 0) FM(MSIOF1_TXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP13_27_24 FM(SSI_WS0129) F_(0, 0) FM(MSIOF1_SS1_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP13_31_28 FM(SSI_SDATA0) F_(0, 0) FM(MSIOF1_SS2_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP14_3_0 FM(SSI_SDATA1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP14_7_4 FM(SSI_SDATA2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(SSI_SCK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP14_11_8 FM(SSI_SCK34) F_(0, 0) FM(MSIOF1_SS1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP14_15_12 FM(SSI_WS34) FM(HCTS2_N_A) FM(MSIOF1_SS2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP14_19_16 FM(SSI_SDATA3) FM(HRTS2_N_A) FM(MSIOF1_TXD_A) F_(0, 0) F_(0, 0) FM(TS_SCK0_A) FM(STP_ISCLK_0_A) FM(RIF0_D1_A) FM(RIF2_D0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP14_23_20 FM(SSI_SCK4) FM(HRX2_A) FM(MSIOF1_SCK_A) F_(0, 0) F_(0, 0) FM(TS_SDAT0_A) FM(STP_ISD_0_A) FM(RIF0_CLK_A) FM(RIF2_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP14_27_24 FM(SSI_WS4) FM(HTX2_A) FM(MSIOF1_SYNC_A) F_(0, 0) F_(0, 0) FM(TS_SDEN0_A) FM(STP_ISEN_0_A) FM(RIF0_SYNC_A) FM(RIF2_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP14_31_28 FM(SSI_SDATA4) FM(HSCK2_A) FM(MSIOF1_RXD_A) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_A)FM(STP_ISSYNC_0_A) FM(RIF0_D0_A) FM(RIF2_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP15_3_0 FM(SSI_SCK6) FM(USB2_PWEN) F_(0, 0) FM(SIM0_RST_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP15_7_4 FM(SSI_WS6) FM(USB2_OVC) F_(0, 0) FM(SIM0_D_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP15_11_8 FM(SSI_SDATA6) F_(0, 0) F_(0, 0) FM(SIM0_CLK_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP15_15_12 FM(SSI_SCK78) FM(HRX2_B) FM(MSIOF1_SCK_C) F_(0, 0) F_(0, 0) FM(TS_SCK1_A) FM(STP_ISCLK_1_A) FM(RIF1_CLK_A) FM(RIF3_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP15_19_16 FM(SSI_WS78) FM(HTX2_B) FM(MSIOF1_SYNC_C) F_(0, 0) F_(0, 0) FM(TS_SDAT1_A) FM(STP_ISD_1_A) FM(RIF1_SYNC_A) FM(RIF3_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP15_23_20 FM(SSI_SDATA7) FM(HCTS2_N_B) FM(MSIOF1_RXD_C) F_(0, 0) F_(0, 0) FM(TS_SDEN1_A) FM(STP_ISEN_1_A) FM(RIF1_D0_A) FM(RIF3_D0_A) F_(0, 0) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP15_27_24 FM(SSI_SDATA8) FM(HRTS2_N_B) FM(MSIOF1_TXD_C) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A) FM(RIF1_D1_A) FM(RIF3_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP15_31_28 FM(SSI_SDATA9_A) FM(HSCK2_B) FM(MSIOF1_SS1_C) FM(HSCK1_A) FM(SSI_WS1_B) FM(SCK1) FM(STP_IVCXO27_1_A) FM(SCK5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP16_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP16_7_4 FM(AUDIO_CLKB_B) FM(SCIF_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_1_D) FM(REMOCON_A) F_(0, 0) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP16_11_8 FM(USB0_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_RST_C) F_(0, 0) FM(TS_SCK1_D) FM(STP_ISCLK_1_D) FM(BPFCLK_B) FM(RIF3_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP16_15_12 FM(USB0_OVC) F_(0, 0) F_(0, 0) FM(SIM0_D_C) F_(0, 0) FM(TS_SDAT1_D) FM(STP_ISD_1_D) F_(0, 0) FM(RIF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP16_19_16 FM(USB1_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_CLK_C) FM(SSI_SCK1_A) FM(TS_SCK0_E) FM(STP_ISCLK_0_E) FM(FMCLK_B) FM(RIF2_CLK_B) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP16_23_20 FM(USB1_OVC) F_(0, 0) FM(MSIOF1_SS2_C) F_(0, 0) FM(SSI_WS1_A) FM(TS_SDAT0_E) FM(STP_ISD_0_E) FM(FMIN_B) FM(RIF2_SYNC_B) F_(0, 0) FM(REMOCON_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP16_27_24 FM(USB30_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_B) FM(SSI_SCK2_B) FM(TS_SDEN1_D) FM(STP_ISEN_1_D) FM(STP_OPWM_0_E)FM(RIF3_D0_B) F_(0, 0) FM(TCLK2_B) FM(TPU0TO0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP16_31_28 FM(USB30_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT1_B) FM(SSI_WS2_B) FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D) FM(STP_IVCXO27_0_E)FM(RIF3_D1_B) F_(0, 0) FM(FSO_TOE_B) FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP17_3_0 FM(USB31_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT2_B) FM(SSI_SCK9_B) FM(TS_SDEN0_E) FM(STP_ISEN_0_E) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) F_(0, 0) FM(TPU0TO2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP17_7_4 FM(USB31_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT3_B) FM(SSI_WS9_B) FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) F_(0, 0) FM(TPU0TO3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) + +#define PINMUX_GPSR \ +\ + GPSR6_31 \ + GPSR6_30 \ + GPSR6_29 \ + GPSR6_28 \ + GPSR1_27 GPSR6_27 \ + GPSR1_26 GPSR6_26 \ + GPSR1_25 GPSR5_25 GPSR6_25 \ + GPSR1_24 GPSR5_24 GPSR6_24 \ + GPSR1_23 GPSR5_23 GPSR6_23 \ + GPSR1_22 GPSR5_22 GPSR6_22 \ + GPSR1_21 GPSR5_21 GPSR6_21 \ + GPSR1_20 GPSR5_20 GPSR6_20 \ + GPSR1_19 GPSR5_19 GPSR6_19 \ + GPSR1_18 GPSR5_18 GPSR6_18 \ + GPSR1_17 GPSR4_17 GPSR5_17 GPSR6_17 \ + GPSR1_16 GPSR4_16 GPSR5_16 GPSR6_16 \ +GPSR0_15 GPSR1_15 GPSR3_15 GPSR4_15 GPSR5_15 GPSR6_15 \ +GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR4_14 GPSR5_14 GPSR6_14 \ +GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR4_13 GPSR5_13 GPSR6_13 \ +GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR4_12 GPSR5_12 GPSR6_12 \ +GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR4_11 GPSR5_11 GPSR6_11 \ +GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 GPSR6_10 \ +GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 \ +GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 \ +GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 \ +GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 \ +GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 \ +GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 \ +GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 GPSR7_3 \ +GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 GPSR7_2 \ +GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 GPSR7_1 \ +GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0 GPSR7_0 + +#define PINMUX_IPSR \ +\ +FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \ +FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \ +FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \ +FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \ +FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \ +FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \ +FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \ +FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \ +\ +FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \ +FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \ +FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \ +FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 FM(IP7_15_12) IP7_15_12 \ +FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \ +FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \ +FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \ +FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \ +\ +FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 FM(IP11_3_0) IP11_3_0 \ +FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 FM(IP11_7_4) IP11_7_4 \ +FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 FM(IP11_11_8) IP11_11_8 \ +FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 FM(IP11_15_12) IP11_15_12 \ +FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 FM(IP11_19_16) IP11_19_16 \ +FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 FM(IP11_23_20) IP11_23_20 \ +FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 FM(IP11_27_24) IP11_27_24 \ +FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28 FM(IP11_31_28) IP11_31_28 \ +\ +FM(IP12_3_0) IP12_3_0 FM(IP13_3_0) IP13_3_0 FM(IP14_3_0) IP14_3_0 FM(IP15_3_0) IP15_3_0 \ +FM(IP12_7_4) IP12_7_4 FM(IP13_7_4) IP13_7_4 FM(IP14_7_4) IP14_7_4 FM(IP15_7_4) IP15_7_4 \ +FM(IP12_11_8) IP12_11_8 FM(IP13_11_8) IP13_11_8 FM(IP14_11_8) IP14_11_8 FM(IP15_11_8) IP15_11_8 \ +FM(IP12_15_12) IP12_15_12 FM(IP13_15_12) IP13_15_12 FM(IP14_15_12) IP14_15_12 FM(IP15_15_12) IP15_15_12 \ +FM(IP12_19_16) IP12_19_16 FM(IP13_19_16) IP13_19_16 FM(IP14_19_16) IP14_19_16 FM(IP15_19_16) IP15_19_16 \ +FM(IP12_23_20) IP12_23_20 FM(IP13_23_20) IP13_23_20 FM(IP14_23_20) IP14_23_20 FM(IP15_23_20) IP15_23_20 \ +FM(IP12_27_24) IP12_27_24 FM(IP13_27_24) IP13_27_24 FM(IP14_27_24) IP14_27_24 FM(IP15_27_24) IP15_27_24 \ +FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM(IP15_31_28) IP15_31_28 \ +\ +FM(IP16_3_0) IP16_3_0 FM(IP17_3_0) IP17_3_0 \ +FM(IP16_7_4) IP16_7_4 FM(IP17_7_4) IP17_7_4 \ +FM(IP16_11_8) IP16_11_8 \ +FM(IP16_15_12) IP16_15_12 \ +FM(IP16_19_16) IP16_19_16 \ +FM(IP16_23_20) IP16_23_20 \ +FM(IP16_27_24) IP16_27_24 \ +FM(IP16_31_28) IP16_31_28 + +/* MOD_SEL0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ +#define MOD_SEL0_30_29 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1) FM(SEL_MSIOF3_2) FM(SEL_MSIOF3_3) +#define MOD_SEL0_28_27 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1) FM(SEL_MSIOF2_2) FM(SEL_MSIOF2_3) +#define MOD_SEL0_26_25_24 FM(SEL_MSIOF1_0) FM(SEL_MSIOF1_1) FM(SEL_MSIOF1_2) FM(SEL_MSIOF1_3) FM(SEL_MSIOF1_4) FM(SEL_MSIOF1_5) FM(SEL_MSIOF1_6) F_(0, 0) +#define MOD_SEL0_23 FM(SEL_LBSC_0) FM(SEL_LBSC_1) +#define MOD_SEL0_22 FM(SEL_IEBUS_0) FM(SEL_IEBUS_1) +#define MOD_SEL0_21_20 FM(SEL_I2C6_0) FM(SEL_I2C6_1) FM(SEL_I2C6_2) F_(0, 0) +#define MOD_SEL0_19 FM(SEL_I2C2_0) FM(SEL_I2C2_1) +#define MOD_SEL0_18 FM(SEL_I2C1_0) FM(SEL_I2C1_1) +#define MOD_SEL0_17 FM(SEL_HSCIF4_0) FM(SEL_HSCIF4_1) +#define MOD_SEL0_16_15 FM(SEL_HSCIF3_0) FM(SEL_HSCIF3_1) FM(SEL_HSCIF3_2) FM(SEL_HSCIF3_3) +#define MOD_SEL0_14 FM(SEL_HSCIF2_0) FM(SEL_HSCIF2_1) +#define MOD_SEL0_13 FM(SEL_HSCIF1_0) FM(SEL_HSCIF1_1) +#define MOD_SEL0_12 FM(SEL_FSO_0) FM(SEL_FSO_1) +#define MOD_SEL0_11 FM(SEL_FM_0) FM(SEL_FM_1) +#define MOD_SEL0_10 FM(SEL_ETHERAVB_0) FM(SEL_ETHERAVB_1) +#define MOD_SEL0_9 FM(SEL_DRIF3_0) FM(SEL_DRIF3_1) +#define MOD_SEL0_8 FM(SEL_DRIF2_0) FM(SEL_DRIF2_1) +#define MOD_SEL0_7_6 FM(SEL_DRIF1_0) FM(SEL_DRIF1_1) FM(SEL_DRIF1_2) F_(0, 0) +#define MOD_SEL0_5_4 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) FM(SEL_DRIF0_2) F_(0, 0) +#define MOD_SEL0_3 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1) +#define MOD_SEL0_2_1 FM(SEL_ADG_0) FM(SEL_ADG_1) FM(SEL_ADG_2) FM(SEL_ADG_3) + +/* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ +#define MOD_SEL1_31_30 FM(SEL_TSIF1_0) FM(SEL_TSIF1_1) FM(SEL_TSIF1_2) FM(SEL_TSIF1_3) +#define MOD_SEL1_29_28_27 FM(SEL_TSIF0_0) FM(SEL_TSIF0_1) FM(SEL_TSIF0_2) FM(SEL_TSIF0_3) FM(SEL_TSIF0_4) F_(0, 0) F_(0, 0) F_(0, 0) +#define MOD_SEL1_26 FM(SEL_TIMER_TMU_0) FM(SEL_TIMER_TMU_1) +#define MOD_SEL1_25_24 FM(SEL_SSP1_1_0) FM(SEL_SSP1_1_1) FM(SEL_SSP1_1_2) FM(SEL_SSP1_1_3) +#define MOD_SEL1_23_22_21 FM(SEL_SSP1_0_0) FM(SEL_SSP1_0_1) FM(SEL_SSP1_0_2) FM(SEL_SSP1_0_3) FM(SEL_SSP1_0_4) F_(0, 0) F_(0, 0) F_(0, 0) +#define MOD_SEL1_20 FM(SEL_SSI_0) FM(SEL_SSI_1) +#define MOD_SEL1_19 FM(SEL_SPEED_PULSE_0) FM(SEL_SPEED_PULSE_1) +#define MOD_SEL1_18_17 FM(SEL_SIMCARD_0) FM(SEL_SIMCARD_1) FM(SEL_SIMCARD_2) FM(SEL_SIMCARD_3) +#define MOD_SEL1_16 FM(SEL_SDHI2_0) FM(SEL_SDHI2_1) +#define MOD_SEL1_15_14 FM(SEL_SCIF4_0) FM(SEL_SCIF4_1) FM(SEL_SCIF4_2) F_(0, 0) +#define MOD_SEL1_13 FM(SEL_SCIF3_0) FM(SEL_SCIF3_1) +#define MOD_SEL1_12 FM(SEL_SCIF2_0) FM(SEL_SCIF2_1) +#define MOD_SEL1_11 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1) +#define MOD_SEL1_10 FM(SEL_SCIF_0) FM(SEL_SCIF_1) +#define MOD_SEL1_9 FM(SEL_REMOCON_0) FM(SEL_REMOCON_1) +#define MOD_SEL1_6 FM(SEL_RCAN0_0) FM(SEL_RCAN0_1) +#define MOD_SEL1_5 FM(SEL_PWM6_0) FM(SEL_PWM6_1) +#define MOD_SEL1_4 FM(SEL_PWM5_0) FM(SEL_PWM5_1) +#define MOD_SEL1_3 FM(SEL_PWM4_0) FM(SEL_PWM4_1) +#define MOD_SEL1_2 FM(SEL_PWM3_0) FM(SEL_PWM3_1) +#define MOD_SEL1_1 FM(SEL_PWM2_0) FM(SEL_PWM2_1) +#define MOD_SEL1_0 FM(SEL_PWM1_0) FM(SEL_PWM1_1) + +/* MOD_SEL2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ +#define MOD_SEL2_31 FM(I2C_SEL_5_0) FM(I2C_SEL_5_1) +#define MOD_SEL2_30 FM(I2C_SEL_3_0) FM(I2C_SEL_3_1) +#define MOD_SEL2_29 FM(I2C_SEL_0_0) FM(I2C_SEL_0_1) +#define MOD_SEL2_2_1 FM(SEL_VSP_0) FM(SEL_VSP_1) FM(SEL_VSP_2) FM(SEL_VSP_3) +#define MOD_SEL2_0 FM(SEL_VIN4_0) FM(SEL_VIN4_1) + +#define PINMUX_MOD_SELS\ +\ + MOD_SEL1_31_30 MOD_SEL2_31 \ +MOD_SEL0_30_29 MOD_SEL2_30 \ + MOD_SEL1_29_28_27 MOD_SEL2_29 \ +MOD_SEL0_28_27 \ +\ +MOD_SEL0_26_25_24 MOD_SEL1_26 \ + MOD_SEL1_25_24 \ +\ +MOD_SEL0_23 MOD_SEL1_23_22_21 \ +MOD_SEL0_22 \ +MOD_SEL0_21_20 \ + MOD_SEL1_20 \ +MOD_SEL0_19 MOD_SEL1_19 \ +MOD_SEL0_18 MOD_SEL1_18_17 \ +MOD_SEL0_17 \ +MOD_SEL0_16_15 MOD_SEL1_16 \ + MOD_SEL1_15_14 \ +MOD_SEL0_14 \ +MOD_SEL0_13 MOD_SEL1_13 \ +MOD_SEL0_12 MOD_SEL1_12 \ +MOD_SEL0_11 MOD_SEL1_11 \ +MOD_SEL0_10 MOD_SEL1_10 \ +MOD_SEL0_9 MOD_SEL1_9 \ +MOD_SEL0_8 \ +MOD_SEL0_7_6 \ + MOD_SEL1_6 \ +MOD_SEL0_5_4 MOD_SEL1_5 \ + MOD_SEL1_4 \ +MOD_SEL0_3 MOD_SEL1_3 \ +MOD_SEL0_2_1 MOD_SEL1_2 MOD_SEL2_2_1 \ + MOD_SEL1_1 \ + MOD_SEL1_0 MOD_SEL2_0 + + +enum { + PINMUX_RESERVED = 0, + + PINMUX_DATA_BEGIN, + GP_ALL(DATA), + PINMUX_DATA_END, + +#define F_(x, y) +#define FM(x) FN_##x, + PINMUX_FUNCTION_BEGIN, + GP_ALL(FN), + PINMUX_GPSR + PINMUX_IPSR + PINMUX_MOD_SELS + PINMUX_FUNCTION_END, +#undef F_ +#undef FM + +#define F_(x, y) +#define FM(x) x##_MARK, + PINMUX_MARK_BEGIN, + PINMUX_GPSR + PINMUX_IPSR + PINMUX_MOD_SELS + PINMUX_MARK_END, +#undef F_ +#undef FM +}; + +static const u16 pinmux_data[] = { + PINMUX_DATA_GP_ALL(), + + /* IPSR0 */ + PINMUX_IPSR_DATA(IP0_3_0, AVB_MDC), + PINMUX_IPSR_MSEL(IP0_3_0, MSIOF2_SS2_C, SEL_MSIOF2_2), + + PINMUX_IPSR_DATA(IP0_7_4, AVB_MAGIC), + PINMUX_IPSR_MSEL(IP0_7_4, MSIOF2_SS1_C, SEL_MSIOF2_2), + PINMUX_IPSR_MSEL(IP0_7_4, SCK4_A, SEL_SCIF4_0), + + PINMUX_IPSR_DATA(IP0_11_8, AVB_PHY_INT), + PINMUX_IPSR_MSEL(IP0_11_8, MSIOF2_SYNC_C, SEL_MSIOF2_2), + PINMUX_IPSR_MSEL(IP0_11_8, RX4_A, SEL_SCIF4_0), + + PINMUX_IPSR_DATA(IP0_15_12, AVB_LINK), + PINMUX_IPSR_MSEL(IP0_15_12, MSIOF2_SCK_C, SEL_MSIOF2_2), + PINMUX_IPSR_MSEL(IP0_15_12, TX4_A, SEL_SCIF4_0), + + PINMUX_IPSR_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, SEL_ETHERAVB_0), + PINMUX_IPSR_MSEL(IP0_19_16, MSIOF2_RXD_C, SEL_MSIOF2_2), + PINMUX_IPSR_MSEL(IP0_19_16, CTS4_N_A, SEL_SCIF4_0), + + PINMUX_IPSR_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, SEL_ETHERAVB_0), + PINMUX_IPSR_MSEL(IP0_23_20, MSIOF2_TXD_C, SEL_MSIOF2_2), + PINMUX_IPSR_MSEL(IP0_23_20, RTS4_N_TANS_A, SEL_SCIF4_0), + + PINMUX_IPSR_DATA(IP0_27_24, IRQ0), + PINMUX_IPSR_DATA(IP0_27_24, QPOLB), + PINMUX_IPSR_DATA(IP0_27_24, DU_CDE), + PINMUX_IPSR_MSEL(IP0_27_24, VI4_DATA0_B, SEL_VIN4_1), + PINMUX_IPSR_MSEL(IP0_27_24, CAN0_TX_B, SEL_RCAN0_1), + PINMUX_IPSR_MSEL(IP0_27_24, CANFD0_TX_B, SEL_CANFD0_1), + + PINMUX_IPSR_DATA(IP0_31_28, IRQ1), + PINMUX_IPSR_DATA(IP0_31_28, QPOLA), + PINMUX_IPSR_DATA(IP0_31_28, DU_DISP), + PINMUX_IPSR_MSEL(IP0_31_28, VI4_DATA1_B, SEL_VIN4_1), + PINMUX_IPSR_MSEL(IP0_31_28, CAN0_RX_B, SEL_RCAN0_1), + PINMUX_IPSR_MSEL(IP0_31_28, CANFD0_RX_B, SEL_CANFD0_1), + + /* IPSR1 */ + PINMUX_IPSR_DATA(IP1_3_0, IRQ2), + PINMUX_IPSR_DATA(IP1_3_0, QCPV_QDE), + PINMUX_IPSR_DATA(IP1_3_0, DU_EXODDF_DU_ODDF_DISP_CDE), + PINMUX_IPSR_MSEL(IP1_3_0, VI4_DATA2_B, SEL_VIN4_1), + PINMUX_IPSR_MSEL(IP1_3_0, PWM3_B, SEL_PWM3_1), + + PINMUX_IPSR_DATA(IP1_7_4, IRQ3), + PINMUX_IPSR_DATA(IP1_7_4, QSTVB_QVE), + PINMUX_IPSR_DATA(IP1_7_4, A25), + PINMUX_IPSR_DATA(IP1_7_4, DU_DOTCLKOUT1), + PINMUX_IPSR_MSEL(IP1_7_4, VI4_DATA3_B, SEL_VIN4_1), + PINMUX_IPSR_MSEL(IP1_7_4, PWM4_B, SEL_PWM4_1), + + PINMUX_IPSR_DATA(IP1_11_8, IRQ4), + PINMUX_IPSR_DATA(IP1_11_8, QSTH_QHS), + PINMUX_IPSR_DATA(IP1_11_8, A24), + PINMUX_IPSR_DATA(IP1_11_8, DU_EXHSYNC_DU_HSYNC), + PINMUX_IPSR_MSEL(IP1_11_8, VI4_DATA4_B, SEL_VIN4_1), + PINMUX_IPSR_MSEL(IP1_11_8, PWM5_B, SEL_PWM5_1), + + PINMUX_IPSR_DATA(IP1_15_12, IRQ5), + PINMUX_IPSR_DATA(IP1_15_12, QSTB_QHE), + PINMUX_IPSR_DATA(IP1_15_12, A23), + PINMUX_IPSR_DATA(IP1_15_12, DU_EXVSYNC_DU_VSYNC), + PINMUX_IPSR_MSEL(IP1_15_12, VI4_DATA5_B, SEL_VIN4_1), + PINMUX_IPSR_MSEL(IP1_15_12, PWM6_B, SEL_PWM6_1), + + PINMUX_IPSR_DATA(IP1_19_16, PWM0), + PINMUX_IPSR_DATA(IP1_19_16, AVB_AVTP_PPS), + PINMUX_IPSR_DATA(IP1_19_16, A22), + PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B, SEL_VIN4_1), + PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B, SEL_IEBUS_1), + + PINMUX_IPSR_MSEL(IP1_23_20, PWM1_A, SEL_PWM1_0), + PINMUX_IPSR_DATA(IP1_23_20, A21), + PINMUX_IPSR_MSEL(IP1_23_20, HRX3_D, SEL_HSCIF3_3), + PINMUX_IPSR_MSEL(IP1_23_20, VI4_DATA7_B, SEL_VIN4_1), + PINMUX_IPSR_MSEL(IP1_23_20, IERX_B, SEL_IEBUS_1), + + PINMUX_IPSR_MSEL(IP1_27_24, PWM2_A, SEL_PWM2_0), + PINMUX_IPSR_DATA(IP1_27_24, A20), + PINMUX_IPSR_MSEL(IP1_27_24, HTX3_D, SEL_HSCIF3_3), + PINMUX_IPSR_MSEL(IP1_27_24, IETX_B, SEL_IEBUS_1), + + PINMUX_IPSR_DATA(IP1_31_28, A0), + PINMUX_IPSR_DATA(IP1_31_28, LCDOUT16), + PINMUX_IPSR_MSEL(IP1_31_28, MSIOF3_SYNC_B, SEL_MSIOF3_1), + PINMUX_IPSR_DATA(IP1_31_28, VI4_DATA8), + PINMUX_IPSR_DATA(IP1_31_28, DU_DB0), + PINMUX_IPSR_MSEL(IP1_31_28, PWM3_A, SEL_PWM3_0), + + /* IPSR2 */ + PINMUX_IPSR_DATA(IP2_3_0, A1), + PINMUX_IPSR_DATA(IP2_3_0, LCDOUT17), + PINMUX_IPSR_MSEL(IP2_3_0, MSIOF3_TXD_B, SEL_MSIOF3_1), + PINMUX_IPSR_DATA(IP2_3_0, VI4_DATA9), + PINMUX_IPSR_DATA(IP2_3_0, DU_DB1), + PINMUX_IPSR_MSEL(IP2_3_0, PWM4_A, SEL_PWM4_0), + + PINMUX_IPSR_DATA(IP2_7_4, A2), + PINMUX_IPSR_DATA(IP2_7_4, LCDOUT18), + PINMUX_IPSR_MSEL(IP2_7_4, MSIOF3_SCK_B, SEL_MSIOF3_1), + PINMUX_IPSR_DATA(IP2_7_4, VI4_DATA10), + PINMUX_IPSR_DATA(IP2_7_4, DU_DB2), + PINMUX_IPSR_MSEL(IP2_7_4, PWM5_A, SEL_PWM5_0), + + PINMUX_IPSR_DATA(IP2_11_8, A3), + PINMUX_IPSR_DATA(IP2_11_8, LCDOUT19), + PINMUX_IPSR_MSEL(IP2_11_8, MSIOF3_RXD_B, SEL_MSIOF3_1), + PINMUX_IPSR_DATA(IP2_11_8, VI4_DATA11), + PINMUX_IPSR_DATA(IP2_11_8, DU_DB3), + PINMUX_IPSR_MSEL(IP2_11_8, PWM6_A, SEL_PWM6_0), + + PINMUX_IPSR_DATA(IP2_15_12, A4), + PINMUX_IPSR_DATA(IP2_15_12, LCDOUT20), + PINMUX_IPSR_MSEL(IP2_15_12, MSIOF3_SS1_B, SEL_MSIOF3_1), + PINMUX_IPSR_DATA(IP2_15_12, VI4_DATA12), + PINMUX_IPSR_DATA(IP2_15_12, VI5_DATA12), + PINMUX_IPSR_DATA(IP2_15_12, DU_DB4), + + PINMUX_IPSR_DATA(IP2_19_16, A5), + PINMUX_IPSR_DATA(IP2_19_16, LCDOUT21), + PINMUX_IPSR_MSEL(IP2_19_16, MSIOF3_SS2_B, SEL_MSIOF3_1), + PINMUX_IPSR_MSEL(IP2_19_16, SCK4_B, SEL_SCIF4_1), + PINMUX_IPSR_DATA(IP2_19_16, VI4_DATA13), + PINMUX_IPSR_DATA(IP2_19_16, VI5_DATA13), + PINMUX_IPSR_DATA(IP2_19_16, DU_DB5), + + PINMUX_IPSR_DATA(IP2_23_20, A6), + PINMUX_IPSR_DATA(IP2_23_20, LCDOUT22), + PINMUX_IPSR_MSEL(IP2_23_20, MSIOF2_SS1_A, SEL_MSIOF2_0), + PINMUX_IPSR_MSEL(IP2_23_20, RX4_B, SEL_SCIF4_1), + PINMUX_IPSR_DATA(IP2_23_20, VI4_DATA14), + PINMUX_IPSR_DATA(IP2_23_20, VI5_DATA14), + PINMUX_IPSR_DATA(IP2_23_20, DU_DB6), + + PINMUX_IPSR_DATA(IP2_27_24, A7), + PINMUX_IPSR_DATA(IP2_27_24, LCDOUT23), + PINMUX_IPSR_MSEL(IP2_27_24, MSIOF2_SS2_A, SEL_MSIOF2_0), + PINMUX_IPSR_MSEL(IP2_27_24, TX4_B, SEL_SCIF4_1), + PINMUX_IPSR_DATA(IP2_27_24, VI4_DATA15), + PINMUX_IPSR_DATA(IP2_27_24, VI5_DATA15), + PINMUX_IPSR_DATA(IP2_27_24, DU_DB7), + + PINMUX_IPSR_DATA(IP2_31_28, A8), + PINMUX_IPSR_MSEL(IP2_31_28, RX3_B, SEL_SCIF3_1), + PINMUX_IPSR_MSEL(IP2_31_28, MSIOF2_SYNC_A, SEL_MSIOF2_0), + PINMUX_IPSR_MSEL(IP2_31_28, HRX4_B, SEL_HSCIF4_1), + PINMUX_IPSR_MSEL(IP2_31_28, SDA6_A, SEL_I2C6_0), + PINMUX_IPSR_MSEL(IP2_31_28, AVB_AVTP_MATCH_B, SEL_ETHERAVB_1), + PINMUX_IPSR_MSEL(IP2_31_28, PWM1_B, SEL_PWM1_1), + + /* IPSR3 */ + PINMUX_IPSR_DATA(IP3_3_0, A9), + PINMUX_IPSR_MSEL(IP3_3_0, MSIOF2_SCK_A, SEL_MSIOF2_0), + PINMUX_IPSR_MSEL(IP3_3_0, CTS4_N_B, SEL_SCIF4_1), + PINMUX_IPSR_DATA(IP3_3_0, VI5_VSYNC_N), + + PINMUX_IPSR_DATA(IP3_7_4, A10), + PINMUX_IPSR_MSEL(IP3_7_4, MSIOF2_RXD_A, SEL_MSIOF2_0), + PINMUX_IPSR_MSEL(IP3_7_4, RTS4_N_TANS_B, SEL_SCIF4_1), + PINMUX_IPSR_DATA(IP3_7_4, VI5_HSYNC_N), + + PINMUX_IPSR_DATA(IP3_11_8, A11), + PINMUX_IPSR_MSEL(IP3_11_8, TX3_B, SEL_SCIF3_1), + PINMUX_IPSR_MSEL(IP3_11_8, MSIOF2_TXD_A, SEL_MSIOF2_0), + PINMUX_IPSR_MSEL(IP3_11_8, HTX4_B, SEL_HSCIF4_1), + PINMUX_IPSR_DATA(IP3_11_8, HSCK4), + PINMUX_IPSR_DATA(IP3_11_8, VI5_FIELD), + PINMUX_IPSR_MSEL(IP3_11_8, SCL6_A, SEL_I2C6_0), + PINMUX_IPSR_MSEL(IP3_11_8, AVB_AVTP_CAPTURE_B, SEL_ETHERAVB_1), + PINMUX_IPSR_MSEL(IP3_11_8, PWM2_B, SEL_PWM2_1), + + PINMUX_IPSR_DATA(IP3_15_12, A12), + PINMUX_IPSR_DATA(IP3_15_12, LCDOUT12), + PINMUX_IPSR_MSEL(IP3_15_12, MSIOF3_SCK_C, SEL_MSIOF3_2), + PINMUX_IPSR_MSEL(IP3_15_12, HRX4_A, SEL_HSCIF4_0), + PINMUX_IPSR_DATA(IP3_15_12, VI5_DATA8), + PINMUX_IPSR_DATA(IP3_15_12, DU_DG4), + + PINMUX_IPSR_DATA(IP3_19_16, A13), + PINMUX_IPSR_DATA(IP3_19_16, LCDOUT13), + PINMUX_IPSR_MSEL(IP3_19_16, MSIOF3_SYNC_C, SEL_MSIOF3_2), + PINMUX_IPSR_MSEL(IP3_19_16, HTX4_A, SEL_HSCIF4_0), + PINMUX_IPSR_DATA(IP3_19_16, VI5_DATA9), + PINMUX_IPSR_DATA(IP3_19_16, DU_DG5), + + PINMUX_IPSR_DATA(IP3_23_20, A14), + PINMUX_IPSR_DATA(IP3_23_20, LCDOUT14), + PINMUX_IPSR_MSEL(IP3_23_20, MSIOF3_RXD_C, SEL_MSIOF3_2), + PINMUX_IPSR_DATA(IP3_23_20, HCTS4_N), + PINMUX_IPSR_DATA(IP3_23_20, VI5_DATA10), + PINMUX_IPSR_DATA(IP3_23_20, DU_DG6), + + PINMUX_IPSR_DATA(IP3_27_24, A15), + PINMUX_IPSR_DATA(IP3_27_24, LCDOUT15), + PINMUX_IPSR_MSEL(IP3_27_24, MSIOF3_TXD_C, SEL_MSIOF3_2), + PINMUX_IPSR_DATA(IP3_27_24, HRTS4_N), + PINMUX_IPSR_DATA(IP3_27_24, VI5_DATA11), + PINMUX_IPSR_DATA(IP3_27_24, DU_DG7), + + PINMUX_IPSR_DATA(IP3_31_28, A16), + PINMUX_IPSR_DATA(IP3_31_28, LCDOUT8), + PINMUX_IPSR_DATA(IP3_31_28, VI4_FIELD), + PINMUX_IPSR_DATA(IP3_31_28, DU_DG0), + + /* IPSR4 */ + PINMUX_IPSR_DATA(IP4_3_0, A17), + PINMUX_IPSR_DATA(IP4_3_0, LCDOUT9), + PINMUX_IPSR_DATA(IP4_3_0, VI4_VSYNC_N), + PINMUX_IPSR_DATA(IP4_3_0, DU_DG1), + + PINMUX_IPSR_DATA(IP4_7_4, A18), + PINMUX_IPSR_DATA(IP4_7_4, LCDOUT10), + PINMUX_IPSR_DATA(IP4_7_4, VI4_HSYNC_N), + PINMUX_IPSR_DATA(IP4_7_4, DU_DG2), + + PINMUX_IPSR_DATA(IP4_11_8, A19), + PINMUX_IPSR_DATA(IP4_11_8, LCDOUT11), + PINMUX_IPSR_DATA(IP4_11_8, VI4_CLKENB), + PINMUX_IPSR_DATA(IP4_11_8, DU_DG3), + + PINMUX_IPSR_DATA(IP4_15_12, CS0_N), + PINMUX_IPSR_DATA(IP4_15_12, VI5_CLKENB), + + PINMUX_IPSR_DATA(IP4_19_16, CS1_N_A26), + PINMUX_IPSR_DATA(IP4_19_16, VI5_CLK), + PINMUX_IPSR_MSEL(IP4_19_16, EX_WAIT0_B, SEL_LBSC_1), + + PINMUX_IPSR_DATA(IP4_23_20, BS_N), + PINMUX_IPSR_DATA(IP4_23_20, QSTVA_QVS), + PINMUX_IPSR_MSEL(IP4_23_20, MSIOF3_SCK_D, SEL_MSIOF3_3), + PINMUX_IPSR_DATA(IP4_23_20, SCK3), + PINMUX_IPSR_DATA(IP4_23_20, HSCK3), + PINMUX_IPSR_DATA(IP4_23_20, CAN1_TX), + PINMUX_IPSR_DATA(IP4_23_20, CANFD1_TX), + PINMUX_IPSR_MSEL(IP4_23_20, IETX_A, SEL_IEBUS_0), + + PINMUX_IPSR_DATA(IP4_27_24, RD_N), + PINMUX_IPSR_MSEL(IP4_27_24, MSIOF3_SYNC_D, SEL_MSIOF3_3), + PINMUX_IPSR_MSEL(IP4_27_24, RX3_A, SEL_SCIF3_0), + PINMUX_IPSR_MSEL(IP4_27_24, HRX3_A, SEL_HSCIF3_0), + PINMUX_IPSR_MSEL(IP4_27_24, CAN0_TX_A, SEL_RCAN0_0), + PINMUX_IPSR_MSEL(IP4_27_24, CANFD0_TX_A, SEL_CANFD0_0), + + PINMUX_IPSR_DATA(IP4_31_28, RD_WR_N), + PINMUX_IPSR_MSEL(IP4_31_28, MSIOF3_RXD_D, SEL_MSIOF3_3), + PINMUX_IPSR_MSEL(IP4_31_28, TX3_A, SEL_SCIF3_0), + PINMUX_IPSR_MSEL(IP4_31_28, HTX3_A, SEL_HSCIF3_0), + PINMUX_IPSR_MSEL(IP4_31_28, CAN0_RX_A, SEL_RCAN0_0), + PINMUX_IPSR_MSEL(IP4_31_28, CANFD0_RX_A, SEL_CANFD0_0), + + /* IPSR5 */ + PINMUX_IPSR_DATA(IP5_3_0, WE0_N), + PINMUX_IPSR_MSEL(IP5_3_0, MSIOF3_TXD_D, SEL_MSIOF3_3), + PINMUX_IPSR_DATA(IP5_3_0, CTS3_N), + PINMUX_IPSR_DATA(IP5_3_0, HCTS3_N), + PINMUX_IPSR_MSEL(IP5_3_0, SCL6_B, SEL_I2C6_1), + PINMUX_IPSR_DATA(IP5_3_0, CAN_CLK), + PINMUX_IPSR_MSEL(IP5_3_0, IECLK_A, SEL_IEBUS_0), + + PINMUX_IPSR_DATA(IP5_7_4, WE1_N), + PINMUX_IPSR_MSEL(IP5_7_4, MSIOF3_SS1_D, SEL_MSIOF3_3), + PINMUX_IPSR_DATA(IP5_7_4, RTS3_N_TANS), + PINMUX_IPSR_DATA(IP5_7_4, HRTS3_N), + PINMUX_IPSR_MSEL(IP5_7_4, SDA6_B, SEL_I2C6_1), + PINMUX_IPSR_DATA(IP5_7_4, CAN1_RX), + PINMUX_IPSR_DATA(IP5_7_4, CANFD1_RX), + PINMUX_IPSR_MSEL(IP5_7_4, IERX_A, SEL_IEBUS_0), + + PINMUX_IPSR_MSEL(IP5_11_8, EX_WAIT0_A, SEL_LBSC_0), + PINMUX_IPSR_DATA(IP5_11_8, QCLK), + PINMUX_IPSR_DATA(IP5_11_8, VI4_CLK), + PINMUX_IPSR_DATA(IP5_11_8, DU_DOTCLKOUT0), + + PINMUX_IPSR_DATA(IP5_15_12, D0), + PINMUX_IPSR_MSEL(IP5_15_12, MSIOF2_SS1_B, SEL_MSIOF2_1), + PINMUX_IPSR_MSEL(IP5_15_12, MSIOF3_SCK_A, SEL_MSIOF3_0), + PINMUX_IPSR_DATA(IP5_15_12, VI4_DATA16), + PINMUX_IPSR_DATA(IP5_15_12, VI5_DATA0), + + PINMUX_IPSR_DATA(IP5_19_16, D1), + PINMUX_IPSR_MSEL(IP5_19_16, MSIOF2_SS2_B, SEL_MSIOF2_1), + PINMUX_IPSR_MSEL(IP5_19_16, MSIOF3_SYNC_A, SEL_MSIOF3_0), + PINMUX_IPSR_DATA(IP5_19_16, VI4_DATA17), + PINMUX_IPSR_DATA(IP5_19_16, VI5_DATA1), + + PINMUX_IPSR_DATA(IP5_23_20, D2), + PINMUX_IPSR_MSEL(IP5_23_20, MSIOF3_RXD_A, SEL_MSIOF3_0), + PINMUX_IPSR_DATA(IP5_23_20, VI4_DATA18), + PINMUX_IPSR_DATA(IP5_23_20, VI5_DATA2), + + PINMUX_IPSR_DATA(IP5_27_24, D3), + PINMUX_IPSR_MSEL(IP5_27_24, MSIOF3_TXD_A, SEL_MSIOF3_0), + PINMUX_IPSR_DATA(IP5_27_24, VI4_DATA19), + PINMUX_IPSR_DATA(IP5_27_24, VI5_DATA3), + + PINMUX_IPSR_DATA(IP5_31_28, D4), + PINMUX_IPSR_MSEL(IP5_31_28, MSIOF2_SCK_B, SEL_MSIOF2_1), + PINMUX_IPSR_DATA(IP5_31_28, VI4_DATA20), + PINMUX_IPSR_DATA(IP5_31_28, VI5_DATA4), + + /* IPSR6 */ + PINMUX_IPSR_DATA(IP6_3_0, D5), + PINMUX_IPSR_MSEL(IP6_3_0, MSIOF2_SYNC_B, SEL_MSIOF2_1), + PINMUX_IPSR_DATA(IP6_3_0, VI4_DATA21), + PINMUX_IPSR_DATA(IP6_3_0, VI5_DATA5), + + PINMUX_IPSR_DATA(IP6_7_4, D6), + PINMUX_IPSR_MSEL(IP6_7_4, MSIOF2_RXD_B, SEL_MSIOF2_1), + PINMUX_IPSR_DATA(IP6_7_4, VI4_DATA22), + PINMUX_IPSR_DATA(IP6_7_4, VI5_DATA6), + + PINMUX_IPSR_DATA(IP6_11_8, D7), + PINMUX_IPSR_MSEL(IP6_11_8, MSIOF2_TXD_B, SEL_MSIOF2_1), + PINMUX_IPSR_DATA(IP6_11_8, VI4_DATA23), + PINMUX_IPSR_DATA(IP6_11_8, VI5_DATA7), + + PINMUX_IPSR_DATA(IP6_15_12, D8), + PINMUX_IPSR_DATA(IP6_15_12, LCDOUT0), + PINMUX_IPSR_MSEL(IP6_15_12, MSIOF2_SCK_D, SEL_MSIOF2_3), + PINMUX_IPSR_MSEL(IP6_15_12, SCK4_C, SEL_SCIF4_2), + PINMUX_IPSR_MSEL(IP6_15_12, VI4_DATA0_A, SEL_VIN4_0), + PINMUX_IPSR_DATA(IP6_15_12, DU_DR0), + + PINMUX_IPSR_DATA(IP6_19_16, D9), + PINMUX_IPSR_DATA(IP6_19_16, LCDOUT1), + PINMUX_IPSR_MSEL(IP6_19_16, MSIOF2_SYNC_D, SEL_MSIOF2_3), + PINMUX_IPSR_MSEL(IP6_19_16, VI4_DATA1_A, SEL_VIN4_0), + PINMUX_IPSR_DATA(IP6_19_16, DU_DR1), + + PINMUX_IPSR_DATA(IP6_23_20, D10), + PINMUX_IPSR_DATA(IP6_23_20, LCDOUT2), + PINMUX_IPSR_MSEL(IP6_23_20, MSIOF2_RXD_D, SEL_MSIOF2_3), + PINMUX_IPSR_MSEL(IP6_23_20, HRX3_B, SEL_HSCIF3_1), + PINMUX_IPSR_MSEL(IP6_23_20, VI4_DATA2_A, SEL_VIN4_0), + PINMUX_IPSR_MSEL(IP6_23_20, CTS4_N_C, SEL_SCIF4_2), + PINMUX_IPSR_DATA(IP6_23_20, DU_DR2), + + PINMUX_IPSR_DATA(IP6_27_24, D11), + PINMUX_IPSR_DATA(IP6_27_24, LCDOUT3), + PINMUX_IPSR_MSEL(IP6_27_24, MSIOF2_TXD_D, SEL_MSIOF2_3), + PINMUX_IPSR_MSEL(IP6_27_24, HTX3_B, SEL_HSCIF3_1), + PINMUX_IPSR_MSEL(IP6_27_24, VI4_DATA3_A, SEL_VIN4_0), + PINMUX_IPSR_MSEL(IP6_27_24, RTS4_N_TANS_C, SEL_SCIF4_2), + PINMUX_IPSR_DATA(IP6_27_24, DU_DR3), + + PINMUX_IPSR_DATA(IP6_31_28, D12), + PINMUX_IPSR_DATA(IP6_31_28, LCDOUT4), + PINMUX_IPSR_MSEL(IP6_31_28, MSIOF2_SS1_D, SEL_MSIOF2_3), + PINMUX_IPSR_MSEL(IP6_31_28, RX4_C, SEL_SCIF4_2), + PINMUX_IPSR_MSEL(IP6_31_28, VI4_DATA4_A, SEL_VIN4_0), + PINMUX_IPSR_DATA(IP6_31_28, DU_DR4), + + /* IPSR7 */ + PINMUX_IPSR_DATA(IP7_3_0, D13), + PINMUX_IPSR_DATA(IP7_3_0, LCDOUT5), + PINMUX_IPSR_MSEL(IP7_3_0, MSIOF2_SS2_D, SEL_MSIOF2_3), + PINMUX_IPSR_MSEL(IP7_3_0, TX4_C, SEL_SCIF4_2), + PINMUX_IPSR_MSEL(IP7_3_0, VI4_DATA5_A, SEL_VIN4_0), + PINMUX_IPSR_DATA(IP7_3_0, DU_DR5), + + PINMUX_IPSR_DATA(IP7_7_4, D14), + PINMUX_IPSR_DATA(IP7_7_4, LCDOUT6), + PINMUX_IPSR_MSEL(IP7_7_4, MSIOF3_SS1_A, SEL_MSIOF3_0), + PINMUX_IPSR_MSEL(IP7_7_4, HRX3_C, SEL_HSCIF3_2), + PINMUX_IPSR_MSEL(IP7_7_4, VI4_DATA6_A, SEL_VIN4_0), + PINMUX_IPSR_DATA(IP7_7_4, DU_DR6), + PINMUX_IPSR_MSEL(IP7_7_4, SCL6_C, SEL_I2C6_2), + + PINMUX_IPSR_DATA(IP7_11_8, D15), + PINMUX_IPSR_DATA(IP7_11_8, LCDOUT7), + PINMUX_IPSR_MSEL(IP7_11_8, MSIOF3_SS2_A, SEL_MSIOF3_0), + PINMUX_IPSR_MSEL(IP7_11_8, HTX3_C, SEL_HSCIF3_2), + PINMUX_IPSR_MSEL(IP7_11_8, VI4_DATA7_A, SEL_VIN4_0), + PINMUX_IPSR_DATA(IP7_11_8, DU_DR7), + PINMUX_IPSR_MSEL(IP7_11_8, SDA6_C, SEL_I2C6_2), + + PINMUX_IPSR_DATA(IP7_15_12, FSCLKST), + + PINMUX_IPSR_DATA(IP7_19_16, SD0_CLK), + PINMUX_IPSR_MSEL(IP7_19_16, MSIOF1_SCK_E, SEL_MSIOF1_4), + PINMUX_IPSR_MSEL(IP7_19_16, STP_OPWM_0_B, SEL_SSP1_0_1), + + PINMUX_IPSR_DATA(IP7_23_20, SD0_CMD), + PINMUX_IPSR_MSEL(IP7_23_20, MSIOF1_SYNC_E, SEL_MSIOF1_4), + PINMUX_IPSR_MSEL(IP7_23_20, STP_IVCXO27_0_B, SEL_SSP1_0_1), + + PINMUX_IPSR_DATA(IP7_27_24, SD0_DAT0), + PINMUX_IPSR_MSEL(IP7_27_24, MSIOF1_RXD_E, SEL_MSIOF1_4), + PINMUX_IPSR_MSEL(IP7_27_24, TS_SCK0_B, SEL_TSIF0_1), + PINMUX_IPSR_MSEL(IP7_27_24, STP_ISCLK_0_B, SEL_SSP1_0_1), + + PINMUX_IPSR_DATA(IP7_31_28, SD0_DAT1), + PINMUX_IPSR_MSEL(IP7_31_28, MSIOF1_TXD_E, SEL_MSIOF1_4), + PINMUX_IPSR_MSEL(IP7_31_28, TS_SPSYNC0_B, SEL_TSIF0_1), + PINMUX_IPSR_MSEL(IP7_31_28, STP_ISSYNC_0_B, SEL_SSP1_0_1), + + /* IPSR8 */ + PINMUX_IPSR_DATA(IP8_3_0, SD0_DAT2), + PINMUX_IPSR_MSEL(IP8_3_0, MSIOF1_SS1_E, SEL_MSIOF1_4), + PINMUX_IPSR_MSEL(IP8_3_0, TS_SDAT0_B, SEL_TSIF0_1), + PINMUX_IPSR_MSEL(IP8_3_0, STP_ISD_0_B, SEL_SSP1_0_1), + + PINMUX_IPSR_DATA(IP8_7_4, SD0_DAT3), + PINMUX_IPSR_MSEL(IP8_7_4, MSIOF1_SS2_E, SEL_MSIOF1_4), + PINMUX_IPSR_MSEL(IP8_7_4, TS_SDEN0_B, SEL_TSIF0_1), + PINMUX_IPSR_MSEL(IP8_7_4, STP_ISEN_0_B, SEL_SSP1_0_1), + + PINMUX_IPSR_DATA(IP8_11_8, SD1_CLK), + PINMUX_IPSR_MSEL(IP8_11_8, MSIOF1_SCK_G, SEL_MSIOF1_6), + PINMUX_IPSR_MSEL(IP8_11_8, SIM0_CLK_A, SEL_SIMCARD_0), + + PINMUX_IPSR_DATA(IP8_15_12, SD1_CMD), + PINMUX_IPSR_MSEL(IP8_15_12, MSIOF1_SYNC_G, SEL_MSIOF1_6), + PINMUX_IPSR_MSEL(IP8_15_12, SIM0_D_A, SEL_SIMCARD_0), + PINMUX_IPSR_MSEL(IP8_15_12, STP_IVCXO27_1_B, SEL_SSP1_1_1), + + PINMUX_IPSR_DATA(IP8_19_16, SD1_DAT0), + PINMUX_IPSR_DATA(IP8_19_16, SD2_DAT4), + PINMUX_IPSR_MSEL(IP8_19_16, MSIOF1_RXD_G, SEL_MSIOF1_6), + PINMUX_IPSR_MSEL(IP8_19_16, TS_SCK1_B, SEL_TSIF1_1), + PINMUX_IPSR_MSEL(IP8_19_16, STP_ISCLK_1_B, SEL_SSP1_1_1), + + PINMUX_IPSR_DATA(IP8_23_20, SD1_DAT1), + PINMUX_IPSR_DATA(IP8_23_20, SD2_DAT5), + PINMUX_IPSR_MSEL(IP8_23_20, MSIOF1_TXD_G, SEL_MSIOF1_6), + PINMUX_IPSR_MSEL(IP8_23_20, TS_SPSYNC1_B, SEL_TSIF1_1), + PINMUX_IPSR_MSEL(IP8_23_20, STP_ISSYNC_1_B, SEL_SSP1_1_1), + + PINMUX_IPSR_DATA(IP8_27_24, SD1_DAT2), + PINMUX_IPSR_DATA(IP8_27_24, SD2_DAT6), + PINMUX_IPSR_MSEL(IP8_27_24, MSIOF1_SS1_G, SEL_MSIOF1_6), + PINMUX_IPSR_MSEL(IP8_27_24, TS_SDAT1_B, SEL_TSIF1_1), + PINMUX_IPSR_MSEL(IP8_27_24, STP_ISD_1_B, SEL_SSP1_1_1), + + PINMUX_IPSR_DATA(IP8_31_28, SD1_DAT3), + PINMUX_IPSR_DATA(IP8_31_28, SD2_DAT7), + PINMUX_IPSR_MSEL(IP8_31_28, MSIOF1_SS2_G, SEL_MSIOF1_6), + PINMUX_IPSR_MSEL(IP8_31_28, TS_SDEN1_B, SEL_TSIF1_1), + PINMUX_IPSR_MSEL(IP8_31_28, STP_ISEN_1_B, SEL_SSP1_1_1), + + /* IPSR9 */ + PINMUX_IPSR_DATA(IP9_3_0, SD2_CLK), + + PINMUX_IPSR_DATA(IP9_7_4, SD2_DAT0), + + PINMUX_IPSR_DATA(IP9_11_8, SD2_DAT1), + + PINMUX_IPSR_DATA(IP9_15_12, SD2_DAT2), + + PINMUX_IPSR_DATA(IP9_19_16, SD2_DAT3), + + PINMUX_IPSR_DATA(IP9_23_20, SD2_DS), + PINMUX_IPSR_MSEL(IP9_23_20, SATA_DEVSLP_B, SEL_SCIF_1), + + PINMUX_IPSR_DATA(IP9_27_24, SD3_DAT4), + PINMUX_IPSR_MSEL(IP9_27_24, SD2_CD_A, SEL_SDHI2_0), + + PINMUX_IPSR_DATA(IP9_31_28, SD3_DAT5), + PINMUX_IPSR_MSEL(IP9_31_28, SD2_WP_A, SEL_SDHI2_0), + + /* IPSR10 */ + PINMUX_IPSR_DATA(IP10_3_0, SD3_DAT6), + PINMUX_IPSR_DATA(IP10_3_0, SD3_CD), + + PINMUX_IPSR_DATA(IP10_7_4, SD3_DAT7), + PINMUX_IPSR_DATA(IP10_7_4, SD3_WP), + + PINMUX_IPSR_DATA(IP10_11_8, SD0_CD), + PINMUX_IPSR_MSEL(IP10_11_8, SCL2_B, SEL_I2C2_1), + PINMUX_IPSR_MSEL(IP10_11_8, SIM0_RST_A, SEL_SIMCARD_0), + + PINMUX_IPSR_DATA(IP10_15_12, SD0_WP), + PINMUX_IPSR_MSEL(IP10_15_12, SDA2_B, SEL_I2C2_1), + + PINMUX_IPSR_DATA(IP10_19_16, SD1_CD), + PINMUX_IPSR_MSEL(IP10_19_16, SIM0_CLK_B, SEL_SIMCARD_1), + + PINMUX_IPSR_DATA(IP10_23_20, SD1_WP), + PINMUX_IPSR_MSEL(IP10_23_20, SIM0_D_B, SEL_SIMCARD_1), + + PINMUX_IPSR_DATA(IP10_27_24, SCK0), + PINMUX_IPSR_MSEL(IP10_27_24, HSCK1_B, SEL_HSCIF1_1), + PINMUX_IPSR_MSEL(IP10_27_24, MSIOF1_SS2_B, SEL_MSIOF1_1), + PINMUX_IPSR_MSEL(IP10_27_24, AUDIO_CLKC_B, SEL_ADG_1), + PINMUX_IPSR_MSEL(IP10_27_24, SDA2_A, SEL_I2C2_0), + PINMUX_IPSR_MSEL(IP10_27_24, SIM0_RST_B, SEL_SIMCARD_1), + PINMUX_IPSR_MSEL(IP10_27_24, STP_OPWM_0_C, SEL_SSP1_0_2), + PINMUX_IPSR_MSEL(IP10_27_24, RIF0_CLK_B, SEL_DRIF0_1), + PINMUX_IPSR_DATA(IP10_27_24, ADICHS2), + + PINMUX_IPSR_DATA(IP10_31_28, RX0), + PINMUX_IPSR_MSEL(IP10_31_28, HRX1_B, SEL_HSCIF1_1), + PINMUX_IPSR_MSEL(IP10_31_28, TS_SCK0_C, SEL_TSIF0_2), + PINMUX_IPSR_MSEL(IP10_31_28, STP_ISCLK_0_C, SEL_SSP1_0_2), + PINMUX_IPSR_MSEL(IP10_31_28, RIF0_D0_B, SEL_DRIF0_1), + + /* IPSR11 */ + PINMUX_IPSR_DATA(IP11_3_0, TX0), + PINMUX_IPSR_MSEL(IP11_3_0, HTX1_B, SEL_HSCIF1_1), + PINMUX_IPSR_MSEL(IP11_3_0, TS_SPSYNC0_C, SEL_TSIF0_2), + PINMUX_IPSR_MSEL(IP11_3_0, STP_ISSYNC_0_C, SEL_SSP1_0_2), + PINMUX_IPSR_MSEL(IP11_3_0, RIF0_D1_B, SEL_DRIF0_1), + + PINMUX_IPSR_DATA(IP11_7_4, CTS0_N), + PINMUX_IPSR_MSEL(IP11_7_4, HCTS1_N_B, SEL_HSCIF1_1), + PINMUX_IPSR_MSEL(IP11_7_4, MSIOF1_SYNC_B, SEL_MSIOF1_1), + PINMUX_IPSR_MSEL(IP11_7_4, TS_SPSYNC1_C, SEL_TSIF1_2), + PINMUX_IPSR_MSEL(IP11_7_4, STP_ISSYNC_1_C, SEL_SSP1_1_2), + PINMUX_IPSR_MSEL(IP11_7_4, RIF1_SYNC_B, SEL_DRIF1_1), + PINMUX_IPSR_MSEL(IP11_7_4, AUDIO_CLKOUT_C, SEL_ADG_2), + PINMUX_IPSR_DATA(IP11_7_4, ADICS_SAMP), + + PINMUX_IPSR_DATA(IP11_11_8, RTS0_N_TANS), + PINMUX_IPSR_MSEL(IP11_11_8, HRTS1_N_B, SEL_HSCIF1_1), + PINMUX_IPSR_MSEL(IP11_11_8, MSIOF1_SS1_B, SEL_MSIOF1_1), + PINMUX_IPSR_MSEL(IP11_11_8, AUDIO_CLKA_B, SEL_ADG_1), + PINMUX_IPSR_MSEL(IP11_11_8, SCL2_A, SEL_I2C2_0), + PINMUX_IPSR_MSEL(IP11_11_8, STP_IVCXO27_1_C, SEL_SSP1_1_2), + PINMUX_IPSR_MSEL(IP11_11_8, RIF0_SYNC_B, SEL_DRIF0_1), + PINMUX_IPSR_DATA(IP11_11_8, ADICHS1), + + PINMUX_IPSR_MSEL(IP11_15_12, RX1_A, SEL_SCIF1_0), + PINMUX_IPSR_MSEL(IP11_15_12, HRX1_A, SEL_HSCIF1_0), + PINMUX_IPSR_MSEL(IP11_15_12, TS_SDAT0_C, SEL_TSIF0_2), + PINMUX_IPSR_MSEL(IP11_15_12, STP_ISD_0_C, SEL_SSP1_0_2), + PINMUX_IPSR_MSEL(IP11_15_12, RIF1_CLK_C, SEL_DRIF1_2), + + PINMUX_IPSR_MSEL(IP11_19_16, TX1_A, SEL_SCIF1_0), + PINMUX_IPSR_MSEL(IP11_19_16, HTX1_A, SEL_HSCIF1_0), + PINMUX_IPSR_MSEL(IP11_19_16, TS_SDEN0_C, SEL_TSIF0_2), + PINMUX_IPSR_MSEL(IP11_19_16, STP_ISEN_0_C, SEL_SSP1_0_2), + PINMUX_IPSR_MSEL(IP11_19_16, RIF1_D0_C, SEL_DRIF1_2), + + PINMUX_IPSR_DATA(IP11_23_20, CTS1_N), + PINMUX_IPSR_MSEL(IP11_23_20, HCTS1_N_A, SEL_HSCIF1_0), + PINMUX_IPSR_MSEL(IP11_23_20, MSIOF1_RXD_B, SEL_MSIOF1_1), + PINMUX_IPSR_MSEL(IP11_23_20, TS_SDEN1_C, SEL_TSIF1_2), + PINMUX_IPSR_MSEL(IP11_23_20, STP_ISEN_1_C, SEL_SSP1_1_2), + PINMUX_IPSR_MSEL(IP11_23_20, RIF1_D0_B, SEL_DRIF1_1), + PINMUX_IPSR_DATA(IP11_23_20, ADIDATA), + + PINMUX_IPSR_DATA(IP11_27_24, RTS1_N_TANS), + PINMUX_IPSR_MSEL(IP11_27_24, HRTS1_N_A, SEL_HSCIF1_0), + PINMUX_IPSR_MSEL(IP11_27_24, MSIOF1_TXD_B, SEL_MSIOF1_1), + PINMUX_IPSR_MSEL(IP11_27_24, TS_SDAT1_C, SEL_TSIF1_2), + PINMUX_IPSR_MSEL(IP11_27_24, STP_ISD_1_C, SEL_SSP1_1_2), + PINMUX_IPSR_MSEL(IP11_27_24, RIF1_D1_B, SEL_DRIF1_1), + PINMUX_IPSR_DATA(IP11_27_24, ADICHS0), + + PINMUX_IPSR_DATA(IP11_31_28, SCK2), + PINMUX_IPSR_MSEL(IP11_31_28, SCIF_CLK_B, SEL_SCIF1_1), + PINMUX_IPSR_MSEL(IP11_31_28, MSIOF1_SCK_B, SEL_MSIOF1_1), + PINMUX_IPSR_MSEL(IP11_31_28, TS_SCK1_C, SEL_TSIF1_2), + PINMUX_IPSR_MSEL(IP11_31_28, STP_ISCLK_1_C, SEL_SSP1_1_2), + PINMUX_IPSR_MSEL(IP11_31_28, RIF1_CLK_B, SEL_DRIF1_1), + PINMUX_IPSR_DATA(IP11_31_28, ADICLK), + + /* IPSR12 */ + PINMUX_IPSR_MSEL(IP12_3_0, TX2_A, SEL_SCIF2_0), + PINMUX_IPSR_MSEL(IP12_3_0, SD2_CD_B, SEL_SDHI2_1), + PINMUX_IPSR_MSEL(IP12_3_0, SCL1_A, SEL_I2C1_0), + PINMUX_IPSR_MSEL(IP12_3_0, FMCLK_A, SEL_FM_0), + PINMUX_IPSR_MSEL(IP12_3_0, RIF1_D1_C, SEL_DRIF1_2), + PINMUX_IPSR_MSEL(IP12_3_0, FSO_CFE_0_B, SEL_FSO_1), + + PINMUX_IPSR_MSEL(IP12_7_4, RX2_A, SEL_SCIF2_0), + PINMUX_IPSR_MSEL(IP12_7_4, SD2_WP_B, SEL_SDHI2_1), + PINMUX_IPSR_MSEL(IP12_7_4, SDA1_A, SEL_I2C1_0), + PINMUX_IPSR_MSEL(IP12_7_4, FMIN_A, SEL_FM_0), + PINMUX_IPSR_MSEL(IP12_7_4, RIF1_SYNC_C, SEL_DRIF1_2), + PINMUX_IPSR_MSEL(IP12_7_4, FSO_CFE_1_B, SEL_FSO_1), + + PINMUX_IPSR_DATA(IP12_11_8, HSCK0), + PINMUX_IPSR_MSEL(IP12_11_8, MSIOF1_SCK_D, SEL_MSIOF1_3), + PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKB_A, SEL_ADG_0), + PINMUX_IPSR_MSEL(IP12_11_8, SSI_SDATA1_B, SEL_SSI_1), + PINMUX_IPSR_MSEL(IP12_11_8, TS_SCK0_D, SEL_TSIF0_3), + PINMUX_IPSR_MSEL(IP12_11_8, STP_ISCLK_0_D, SEL_SSP1_0_3), + PINMUX_IPSR_MSEL(IP12_11_8, RIF0_CLK_C, SEL_DRIF0_2), + + PINMUX_IPSR_DATA(IP12_15_12, HRX0), + PINMUX_IPSR_MSEL(IP12_15_12, MSIOF1_RXD_D, SEL_MSIOF1_3), + PINMUX_IPSR_MSEL(IP12_15_12, SSI_SDATA2_B, SEL_SSI_1), + PINMUX_IPSR_MSEL(IP12_15_12, TS_SDEN0_D, SEL_TSIF0_3), + PINMUX_IPSR_MSEL(IP12_15_12, STP_ISEN_0_D, SEL_SSP1_0_3), + PINMUX_IPSR_MSEL(IP12_15_12, RIF0_D0_C, SEL_DRIF0_2), + + PINMUX_IPSR_DATA(IP12_19_16, HTX0), + PINMUX_IPSR_MSEL(IP12_19_16, MSIOF1_TXD_D, SEL_MSIOF1_3), + PINMUX_IPSR_MSEL(IP12_19_16, SSI_SDATA9_B, SEL_SSI_1), + PINMUX_IPSR_MSEL(IP12_19_16, TS_SDAT0_D, SEL_TSIF0_3), + PINMUX_IPSR_MSEL(IP12_19_16, STP_ISD_0_D, SEL_SSP1_0_3), + PINMUX_IPSR_MSEL(IP12_19_16, RIF0_D1_C, SEL_DRIF0_2), + + PINMUX_IPSR_DATA(IP12_23_20, HCTS0_N), + PINMUX_IPSR_MSEL(IP12_23_20, RX2_B, SEL_SCIF2_1), + PINMUX_IPSR_MSEL(IP12_23_20, MSIOF1_SYNC_D, SEL_MSIOF1_3), + PINMUX_IPSR_MSEL(IP12_23_20, SSI_SCK9_A, SEL_SSI_0), + PINMUX_IPSR_MSEL(IP12_23_20, TS_SPSYNC0_D, SEL_TSIF0_3), + PINMUX_IPSR_MSEL(IP12_23_20, STP_ISSYNC_0_D, SEL_SSP1_0_3), + PINMUX_IPSR_MSEL(IP12_23_20, RIF0_SYNC_C, SEL_DRIF0_2), + PINMUX_IPSR_MSEL(IP12_23_20, AUDIO_CLKOUT1_A, SEL_ADG_0), + + PINMUX_IPSR_DATA(IP12_27_24, HRTS0_N), + PINMUX_IPSR_MSEL(IP12_27_24, TX2_B, SEL_SCIF2_1), + PINMUX_IPSR_MSEL(IP12_27_24, MSIOF1_SS1_D, SEL_MSIOF1_3), + PINMUX_IPSR_MSEL(IP12_27_24, SSI_WS9_A, SEL_SSI_0), + PINMUX_IPSR_MSEL(IP12_27_24, STP_IVCXO27_0_D, SEL_SSP1_0_3), + PINMUX_IPSR_MSEL(IP12_27_24, BPFCLK_A, SEL_FM_0), + PINMUX_IPSR_MSEL(IP12_27_24, AUDIO_CLKOUT2_A, SEL_ADG_0), + + PINMUX_IPSR_DATA(IP12_31_28, MSIOF0_SYNC), + PINMUX_IPSR_MSEL(IP12_31_28, AUDIO_CLKOUT_A, SEL_ADG_0), + + /* IPSR13 */ + PINMUX_IPSR_DATA(IP13_3_0, MSIOF0_SS1), + PINMUX_IPSR_DATA(IP13_3_0, RX5), + PINMUX_IPSR_MSEL(IP13_3_0, AUDIO_CLKA_C, SEL_ADG_2), + PINMUX_IPSR_MSEL(IP13_3_0, SSI_SCK2_A, SEL_SSI_0), + PINMUX_IPSR_MSEL(IP13_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2), + PINMUX_IPSR_MSEL(IP13_3_0, AUDIO_CLKOUT3_A, SEL_ADG_0), + PINMUX_IPSR_MSEL(IP13_3_0, TCLK1_B, SEL_TIMER_TMU_1), + + PINMUX_IPSR_DATA(IP13_7_4, MSIOF0_SS2), + PINMUX_IPSR_DATA(IP13_7_4, TX5), + PINMUX_IPSR_MSEL(IP13_7_4, MSIOF1_SS2_D, SEL_MSIOF1_3), + PINMUX_IPSR_MSEL(IP13_7_4, AUDIO_CLKC_A, SEL_ADG_0), + PINMUX_IPSR_MSEL(IP13_7_4, SSI_WS2_A, SEL_SSI_0), + PINMUX_IPSR_MSEL(IP13_7_4, STP_OPWM_0_D, SEL_SSP1_0_3), + PINMUX_IPSR_MSEL(IP13_7_4, AUDIO_CLKOUT_D, SEL_ADG_3), + PINMUX_IPSR_MSEL(IP13_7_4, SPEEDIN_B, SEL_SPEED_PULSE_1), + + PINMUX_IPSR_DATA(IP13_11_8, MLB_CLK), + PINMUX_IPSR_MSEL(IP13_11_8, MSIOF1_SCK_F, SEL_MSIOF1_5), + PINMUX_IPSR_MSEL(IP13_11_8, SCL1_B, SEL_I2C1_1), + + PINMUX_IPSR_DATA(IP13_15_12, MLB_SIG), + PINMUX_IPSR_MSEL(IP13_15_12, RX1_B, SEL_SCIF1_1), + PINMUX_IPSR_MSEL(IP13_15_12, MSIOF1_SYNC_F, SEL_MSIOF1_5), + PINMUX_IPSR_MSEL(IP13_15_12, SDA1_B, SEL_I2C1_1), + + PINMUX_IPSR_DATA(IP13_19_16, MLB_DAT), + PINMUX_IPSR_MSEL(IP13_19_16, TX1_B, SEL_SCIF1_1), + PINMUX_IPSR_MSEL(IP13_19_16, MSIOF1_RXD_F, SEL_MSIOF1_5), + + PINMUX_IPSR_DATA(IP13_23_20, SSI_SCK0129), + PINMUX_IPSR_MSEL(IP13_23_20, MSIOF1_TXD_F, SEL_MSIOF1_5), + + PINMUX_IPSR_DATA(IP13_27_24, SSI_WS0129), + PINMUX_IPSR_MSEL(IP13_27_24, MSIOF1_SS1_F, SEL_MSIOF1_5), + + PINMUX_IPSR_DATA(IP13_31_28, SSI_SDATA0), + PINMUX_IPSR_MSEL(IP13_31_28, MSIOF1_SS2_F, SEL_MSIOF1_5), + + /* IPSR14 */ + PINMUX_IPSR_MSEL(IP14_3_0, SSI_SDATA1_A, SEL_SSI_0), + + PINMUX_IPSR_MSEL(IP14_7_4, SSI_SDATA2_A, SEL_SSI_0), + PINMUX_IPSR_MSEL(IP14_7_4, SSI_SCK1_B, SEL_SSI_1), + + PINMUX_IPSR_DATA(IP14_11_8, SSI_SCK34), + PINMUX_IPSR_MSEL(IP14_11_8, MSIOF1_SS1_A, SEL_MSIOF1_0), + PINMUX_IPSR_MSEL(IP14_11_8, STP_OPWM_0_A, SEL_SSP1_0_0), + + PINMUX_IPSR_DATA(IP14_15_12, SSI_WS34), + PINMUX_IPSR_MSEL(IP14_15_12, HCTS2_N_A, SEL_HSCIF2_0), + PINMUX_IPSR_MSEL(IP14_15_12, MSIOF1_SS2_A, SEL_MSIOF1_0), + PINMUX_IPSR_MSEL(IP14_15_12, STP_IVCXO27_0_A, SEL_SSP1_0_0), + + PINMUX_IPSR_DATA(IP14_19_16, SSI_SDATA3), + PINMUX_IPSR_MSEL(IP14_19_16, HRTS2_N_A, SEL_HSCIF2_0), + PINMUX_IPSR_MSEL(IP14_19_16, MSIOF1_TXD_A, SEL_MSIOF1_0), + PINMUX_IPSR_MSEL(IP14_19_16, TS_SCK0_A, SEL_TSIF0_0), + PINMUX_IPSR_MSEL(IP14_19_16, STP_ISCLK_0_A, SEL_SSP1_0_0), + PINMUX_IPSR_MSEL(IP14_19_16, RIF0_D1_A, SEL_DRIF0_0), + PINMUX_IPSR_MSEL(IP14_19_16, RIF2_D0_A, SEL_DRIF2_0), + + PINMUX_IPSR_DATA(IP14_23_20, SSI_SCK4), + PINMUX_IPSR_MSEL(IP14_23_20, HRX2_A, SEL_HSCIF2_0), + PINMUX_IPSR_MSEL(IP14_23_20, MSIOF1_SCK_A, SEL_MSIOF1_0), + PINMUX_IPSR_MSEL(IP14_23_20, TS_SDAT0_A, SEL_TSIF0_0), + PINMUX_IPSR_MSEL(IP14_23_20, STP_ISD_0_A, SEL_SSP1_0_0), + PINMUX_IPSR_MSEL(IP14_23_20, RIF0_CLK_A, SEL_DRIF0_0), + PINMUX_IPSR_MSEL(IP14_23_20, RIF2_CLK_A, SEL_DRIF2_0), + + PINMUX_IPSR_DATA(IP14_27_24, SSI_WS4), + PINMUX_IPSR_MSEL(IP14_27_24, HTX2_A, SEL_HSCIF2_0), + PINMUX_IPSR_MSEL(IP14_27_24, MSIOF1_SYNC_A, SEL_MSIOF1_0), + PINMUX_IPSR_MSEL(IP14_27_24, TS_SDEN0_A, SEL_TSIF0_0), + PINMUX_IPSR_MSEL(IP14_27_24, STP_ISEN_0_A, SEL_SSP1_0_0), + PINMUX_IPSR_MSEL(IP14_27_24, RIF0_SYNC_A, SEL_DRIF0_0), + PINMUX_IPSR_MSEL(IP14_27_24, RIF2_SYNC_A, SEL_DRIF2_0), + + PINMUX_IPSR_DATA(IP14_31_28, SSI_SDATA4), + PINMUX_IPSR_MSEL(IP14_31_28, HSCK2_A, SEL_HSCIF2_0), + PINMUX_IPSR_MSEL(IP14_31_28, MSIOF1_RXD_A, SEL_MSIOF1_0), + PINMUX_IPSR_MSEL(IP14_31_28, TS_SPSYNC0_A, SEL_TSIF0_0), + PINMUX_IPSR_MSEL(IP14_31_28, STP_ISSYNC_0_A, SEL_SSP1_0_0), + PINMUX_IPSR_MSEL(IP14_31_28, RIF0_D0_A, SEL_DRIF0_0), + PINMUX_IPSR_MSEL(IP14_31_28, RIF2_D1_A, SEL_DRIF2_0), + + /* IPSR15 */ + PINMUX_IPSR_DATA(IP15_3_0, SSI_SCK6), + PINMUX_IPSR_DATA(IP15_3_0, USB2_PWEN), + PINMUX_IPSR_MSEL(IP15_3_0, SIM0_RST_D, SEL_SIMCARD_3), + + PINMUX_IPSR_DATA(IP15_7_4, SSI_WS6), + PINMUX_IPSR_DATA(IP15_7_4, USB2_OVC), + PINMUX_IPSR_MSEL(IP15_7_4, SIM0_D_D, SEL_SIMCARD_3), + + PINMUX_IPSR_DATA(IP15_11_8, SSI_SDATA6), + PINMUX_IPSR_MSEL(IP15_11_8, SIM0_CLK_D, SEL_SIMCARD_3), + PINMUX_IPSR_MSEL(IP15_11_8, SATA_DEVSLP_A, SEL_SCIF_0), + + PINMUX_IPSR_DATA(IP15_15_12, SSI_SCK78), + PINMUX_IPSR_MSEL(IP15_15_12, HRX2_B, SEL_HSCIF2_1), + PINMUX_IPSR_MSEL(IP15_15_12, MSIOF1_SCK_C, SEL_MSIOF1_2), + PINMUX_IPSR_MSEL(IP15_15_12, TS_SCK1_A, SEL_TSIF1_0), + PINMUX_IPSR_MSEL(IP15_15_12, STP_ISCLK_1_A, SEL_SSP1_1_0), + PINMUX_IPSR_MSEL(IP15_15_12, RIF1_CLK_A, SEL_DRIF1_0), + PINMUX_IPSR_MSEL(IP15_15_12, RIF3_CLK_A, SEL_DRIF3_0), + + PINMUX_IPSR_DATA(IP15_19_16, SSI_WS78), + PINMUX_IPSR_MSEL(IP15_19_16, HTX2_B, SEL_HSCIF2_1), + PINMUX_IPSR_MSEL(IP15_19_16, MSIOF1_SYNC_C, SEL_MSIOF1_2), + PINMUX_IPSR_MSEL(IP15_19_16, TS_SDAT1_A, SEL_TSIF1_0), + PINMUX_IPSR_MSEL(IP15_19_16, STP_ISD_1_A, SEL_SSP1_1_0), + PINMUX_IPSR_MSEL(IP15_19_16, RIF1_SYNC_A, SEL_DRIF1_0), + PINMUX_IPSR_MSEL(IP15_19_16, RIF3_SYNC_A, SEL_DRIF3_0), + + PINMUX_IPSR_DATA(IP15_23_20, SSI_SDATA7), + PINMUX_IPSR_MSEL(IP15_23_20, HCTS2_N_B, SEL_HSCIF2_1), + PINMUX_IPSR_MSEL(IP15_23_20, MSIOF1_RXD_C, SEL_MSIOF1_2), + PINMUX_IPSR_MSEL(IP15_23_20, TS_SDEN1_A, SEL_TSIF1_0), + PINMUX_IPSR_MSEL(IP15_23_20, STP_ISEN_1_A, SEL_SSP1_1_0), + PINMUX_IPSR_MSEL(IP15_23_20, RIF1_D0_A, SEL_DRIF1_0), + PINMUX_IPSR_MSEL(IP15_23_20, RIF3_D0_A, SEL_DRIF3_0), + PINMUX_IPSR_MSEL(IP15_23_20, TCLK2_A, SEL_TIMER_TMU_0), + + PINMUX_IPSR_DATA(IP15_27_24, SSI_SDATA8), + PINMUX_IPSR_MSEL(IP15_27_24, HRTS2_N_B, SEL_HSCIF2_1), + PINMUX_IPSR_MSEL(IP15_27_24, MSIOF1_TXD_C, SEL_MSIOF1_2), + PINMUX_IPSR_MSEL(IP15_27_24, TS_SPSYNC1_A, SEL_TSIF1_0), + PINMUX_IPSR_MSEL(IP15_27_24, STP_ISSYNC_1_A, SEL_SSP1_1_0), + PINMUX_IPSR_MSEL(IP15_27_24, RIF1_D1_A, SEL_DRIF1_0), + PINMUX_IPSR_MSEL(IP15_27_24, RIF3_D1_A, SEL_DRIF3_0), + + PINMUX_IPSR_MSEL(IP15_31_28, SSI_SDATA9_A, SEL_SSI_0), + PINMUX_IPSR_MSEL(IP15_31_28, HSCK2_B, SEL_HSCIF2_1), + PINMUX_IPSR_MSEL(IP15_31_28, MSIOF1_SS1_C, SEL_MSIOF1_2), + PINMUX_IPSR_MSEL(IP15_31_28, HSCK1_A, SEL_HSCIF1_0), + PINMUX_IPSR_MSEL(IP15_31_28, SSI_WS1_B, SEL_SSI_1), + PINMUX_IPSR_DATA(IP15_31_28, SCK1), + PINMUX_IPSR_MSEL(IP15_31_28, STP_IVCXO27_1_A, SEL_SSP1_1_0), + PINMUX_IPSR_DATA(IP15_31_28, SCK5), + + /* IPSR16 */ + PINMUX_IPSR_MSEL(IP16_3_0, AUDIO_CLKA_A, SEL_ADG_0), + PINMUX_IPSR_DATA(IP16_3_0, CC5_OSCOUT), + + PINMUX_IPSR_MSEL(IP16_7_4, AUDIO_CLKB_B, SEL_ADG_1), + PINMUX_IPSR_MSEL(IP16_7_4, SCIF_CLK_A, SEL_SCIF1_0), + PINMUX_IPSR_MSEL(IP16_7_4, STP_IVCXO27_1_D, SEL_SSP1_1_3), + PINMUX_IPSR_MSEL(IP16_7_4, REMOCON_A, SEL_REMOCON_0), + PINMUX_IPSR_MSEL(IP16_7_4, TCLK1_A, SEL_TIMER_TMU_0), + + PINMUX_IPSR_DATA(IP16_11_8, USB0_PWEN), + PINMUX_IPSR_MSEL(IP16_11_8, SIM0_RST_C, SEL_SIMCARD_2), + PINMUX_IPSR_MSEL(IP16_11_8, TS_SCK1_D, SEL_TSIF1_3), + PINMUX_IPSR_MSEL(IP16_11_8, STP_ISCLK_1_D, SEL_SSP1_1_3), + PINMUX_IPSR_MSEL(IP16_11_8, BPFCLK_B, SEL_FM_1), + PINMUX_IPSR_MSEL(IP16_11_8, RIF3_CLK_B, SEL_DRIF3_1), + + PINMUX_IPSR_DATA(IP16_15_12, USB0_OVC), + PINMUX_IPSR_MSEL(IP16_11_8, SIM0_D_C, SEL_SIMCARD_2), + PINMUX_IPSR_MSEL(IP16_11_8, TS_SDAT1_D, SEL_TSIF1_3), + PINMUX_IPSR_MSEL(IP16_11_8, STP_ISD_1_D, SEL_SSP1_1_3), + PINMUX_IPSR_MSEL(IP16_11_8, RIF3_SYNC_B, SEL_DRIF3_1), + + PINMUX_IPSR_DATA(IP16_19_16, USB1_PWEN), + PINMUX_IPSR_MSEL(IP16_19_16, SIM0_CLK_C, SEL_SIMCARD_2), + PINMUX_IPSR_MSEL(IP16_19_16, SSI_SCK1_A, SEL_SSI_0), + PINMUX_IPSR_MSEL(IP16_19_16, TS_SCK0_E, SEL_TSIF0_4), + PINMUX_IPSR_MSEL(IP16_19_16, STP_ISCLK_0_E, SEL_SSP1_0_4), + PINMUX_IPSR_MSEL(IP16_19_16, FMCLK_B, SEL_FM_1), + PINMUX_IPSR_MSEL(IP16_19_16, RIF2_CLK_B, SEL_DRIF2_1), + PINMUX_IPSR_MSEL(IP16_19_16, SPEEDIN_A, SEL_SPEED_PULSE_0), + + PINMUX_IPSR_DATA(IP16_23_20, USB1_OVC), + PINMUX_IPSR_MSEL(IP16_23_20, MSIOF1_SS2_C, SEL_MSIOF1_2), + PINMUX_IPSR_MSEL(IP16_23_20, SSI_WS1_A, SEL_SSI_0), + PINMUX_IPSR_MSEL(IP16_23_20, TS_SDAT0_E, SEL_TSIF0_4), + PINMUX_IPSR_MSEL(IP16_23_20, STP_ISD_0_E, SEL_SSP1_0_4), + PINMUX_IPSR_MSEL(IP16_23_20, FMIN_B, SEL_FM_1), + PINMUX_IPSR_MSEL(IP16_23_20, RIF2_SYNC_B, SEL_DRIF2_1), + PINMUX_IPSR_MSEL(IP16_23_20, REMOCON_B, SEL_REMOCON_1), + + PINMUX_IPSR_DATA(IP16_27_24, USB30_PWEN), + PINMUX_IPSR_MSEL(IP16_27_24, AUDIO_CLKOUT_B, SEL_ADG_1), + PINMUX_IPSR_MSEL(IP16_27_24, SSI_SCK2_B, SEL_SSI_1), + PINMUX_IPSR_MSEL(IP16_27_24, TS_SDEN1_D, SEL_TSIF1_3), + PINMUX_IPSR_MSEL(IP16_27_24, STP_ISEN_1_D, SEL_SSP1_1_2), + PINMUX_IPSR_MSEL(IP16_27_24, STP_OPWM_0_E, SEL_SSP1_0_4), + PINMUX_IPSR_MSEL(IP16_27_24, RIF3_D0_B, SEL_DRIF3_1), + PINMUX_IPSR_MSEL(IP16_27_24, TCLK2_B, SEL_TIMER_TMU_1), + PINMUX_IPSR_DATA(IP16_27_24, TPU0TO0), + + PINMUX_IPSR_DATA(IP16_31_28, USB30_OVC), + PINMUX_IPSR_MSEL(IP16_31_28, AUDIO_CLKOUT1_B, SEL_ADG_1), + PINMUX_IPSR_MSEL(IP16_31_28, SSI_WS2_B, SEL_SSI_1), + PINMUX_IPSR_MSEL(IP16_31_28, TS_SPSYNC1_D, SEL_TSIF1_3), + PINMUX_IPSR_MSEL(IP16_31_28, STP_ISSYNC_1_D, SEL_SSP1_1_3), + PINMUX_IPSR_MSEL(IP16_31_28, STP_IVCXO27_0_E, SEL_SSP1_0_4), + PINMUX_IPSR_MSEL(IP16_31_28, RIF3_D1_B, SEL_DRIF3_1), + PINMUX_IPSR_MSEL(IP16_31_28, FSO_TOE_B, SEL_FSO_1), + PINMUX_IPSR_DATA(IP16_31_28, TPU0TO1), + + /* IPSR17 */ + PINMUX_IPSR_DATA(IP17_3_0, USB31_PWEN), + PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKOUT2_B, SEL_ADG_1), + PINMUX_IPSR_MSEL(IP17_3_0, SSI_SCK9_B, SEL_SSI_1), + PINMUX_IPSR_MSEL(IP17_3_0, TS_SDEN0_E, SEL_TSIF0_4), + PINMUX_IPSR_MSEL(IP17_3_0, STP_ISEN_0_E, SEL_SSP1_0_4), + PINMUX_IPSR_MSEL(IP17_3_0, RIF2_D0_B, SEL_DRIF2_1), + PINMUX_IPSR_DATA(IP17_3_0, TPU0TO2), + + PINMUX_IPSR_DATA(IP17_7_4, USB31_OVC), + PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKOUT3_B, SEL_ADG_1), + PINMUX_IPSR_MSEL(IP17_7_4, SSI_WS9_B, SEL_SSI_1), + PINMUX_IPSR_MSEL(IP17_7_4, TS_SPSYNC0_E, SEL_TSIF0_4), + PINMUX_IPSR_MSEL(IP17_7_4, STP_ISSYNC_0_E, SEL_SSP1_0_4), + PINMUX_IPSR_MSEL(IP17_7_4, RIF2_D1_B, SEL_DRIF2_1), + PINMUX_IPSR_DATA(IP17_7_4, TPU0TO3), + + /* I2C */ + PINMUX_IPSR_NOGP(0, I2C_SEL_0_1), + PINMUX_IPSR_NOGP(0, I2C_SEL_3_1), + PINMUX_IPSR_NOGP(0, I2C_SEL_5_1), +}; + +static const struct sh_pfc_pin pinmux_pins[] = { + PINMUX_GPIO_GP_ALL(), +}; + +static const struct sh_pfc_pin_group pinmux_groups[] = { +}; + +static const struct sh_pfc_function pinmux_functions[] = { +}; + +static const struct pinmux_cfg_reg pinmux_config_regs[] = { +#define F_(x, y) FN_##y +#define FM(x) FN_##x + { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) { + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + GP_0_15_FN, GPSR0_15, + GP_0_14_FN, GPSR0_14, + GP_0_13_FN, GPSR0_13, + GP_0_12_FN, GPSR0_12, + GP_0_11_FN, GPSR0_11, + GP_0_10_FN, GPSR0_10, + GP_0_9_FN, GPSR0_9, + GP_0_8_FN, GPSR0_8, + GP_0_7_FN, GPSR0_7, + GP_0_6_FN, GPSR0_6, + GP_0_5_FN, GPSR0_5, + GP_0_4_FN, GPSR0_4, + GP_0_3_FN, GPSR0_3, + GP_0_2_FN, GPSR0_2, + GP_0_1_FN, GPSR0_1, + GP_0_0_FN, GPSR0_0, } + }, + { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) { + 0, 0, + 0, 0, + 0, 0, + 0, 0, + GP_1_27_FN, GPSR1_27, + GP_1_26_FN, GPSR1_26, + GP_1_25_FN, GPSR1_25, + GP_1_24_FN, GPSR1_24, + GP_1_23_FN, GPSR1_23, + GP_1_22_FN, GPSR1_22, + GP_1_21_FN, GPSR1_21, + GP_1_20_FN, GPSR1_20, + GP_1_19_FN, GPSR1_19, + GP_1_18_FN, GPSR1_18, + GP_1_17_FN, GPSR1_17, + GP_1_16_FN, GPSR1_16, + GP_1_15_FN, GPSR1_15, + GP_1_14_FN, GPSR1_14, + GP_1_13_FN, GPSR1_13, + GP_1_12_FN, GPSR1_12, + GP_1_11_FN, GPSR1_11, + GP_1_10_FN, GPSR1_10, + GP_1_9_FN, GPSR1_9, + GP_1_8_FN, GPSR1_8, + GP_1_7_FN, GPSR1_7, + GP_1_6_FN, GPSR1_6, + GP_1_5_FN, GPSR1_5, + GP_1_4_FN, GPSR1_4, + GP_1_3_FN, GPSR1_3, + GP_1_2_FN, GPSR1_2, + GP_1_1_FN, GPSR1_1, + GP_1_0_FN, GPSR1_0, } + }, + { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) { + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + GP_2_14_FN, GPSR2_14, + GP_2_13_FN, GPSR2_13, + GP_2_12_FN, GPSR2_12, + GP_2_11_FN, GPSR2_11, + GP_2_10_FN, GPSR2_10, + GP_2_9_FN, GPSR2_9, + GP_2_8_FN, GPSR2_8, + GP_2_7_FN, GPSR2_7, + GP_2_6_FN, GPSR2_6, + GP_2_5_FN, GPSR2_5, + GP_2_4_FN, GPSR2_4, + GP_2_3_FN, GPSR2_3, + GP_2_2_FN, GPSR2_2, + GP_2_1_FN, GPSR2_1, + GP_2_0_FN, GPSR2_0, } + }, + { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) { + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + GP_3_15_FN, GPSR3_15, + GP_3_14_FN, GPSR3_14, + GP_3_13_FN, GPSR3_13, + GP_3_12_FN, GPSR3_12, + GP_3_11_FN, GPSR3_11, + GP_3_10_FN, GPSR3_10, + GP_3_9_FN, GPSR3_9, + GP_3_8_FN, GPSR3_8, + GP_3_7_FN, GPSR3_7, + GP_3_6_FN, GPSR3_6, + GP_3_5_FN, GPSR3_5, + GP_3_4_FN, GPSR3_4, + GP_3_3_FN, GPSR3_3, + GP_3_2_FN, GPSR3_2, + GP_3_1_FN, GPSR3_1, + GP_3_0_FN, GPSR3_0, } + }, + { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) { + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + GP_4_17_FN, GPSR4_17, + GP_4_16_FN, GPSR4_16, + GP_4_15_FN, GPSR4_15, + GP_4_14_FN, GPSR4_14, + GP_4_13_FN, GPSR4_13, + GP_4_12_FN, GPSR4_12, + GP_4_11_FN, GPSR4_11, + GP_4_10_FN, GPSR4_10, + GP_4_9_FN, GPSR4_9, + GP_4_8_FN, GPSR4_8, + GP_4_7_FN, GPSR4_7, + GP_4_6_FN, GPSR4_6, + GP_4_5_FN, GPSR4_5, + GP_4_4_FN, GPSR4_4, + GP_4_3_FN, GPSR4_3, + GP_4_2_FN, GPSR4_2, + GP_4_1_FN, GPSR4_1, + GP_4_0_FN, GPSR4_0, } + }, + { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) { + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + GP_5_25_FN, GPSR5_25, + GP_5_24_FN, GPSR5_24, + GP_5_23_FN, GPSR5_23, + GP_5_22_FN, GPSR5_22, + GP_5_21_FN, GPSR5_21, + GP_5_20_FN, GPSR5_20, + GP_5_19_FN, GPSR5_19, + GP_5_18_FN, GPSR5_18, + GP_5_17_FN, GPSR5_17, + GP_5_16_FN, GPSR5_16, + GP_5_15_FN, GPSR5_15, + GP_5_14_FN, GPSR5_14, + GP_5_13_FN, GPSR5_13, + GP_5_12_FN, GPSR5_12, + GP_5_11_FN, GPSR5_11, + GP_5_10_FN, GPSR5_10, + GP_5_9_FN, GPSR5_9, + GP_5_8_FN, GPSR5_8, + GP_5_7_FN, GPSR5_7, + GP_5_6_FN, GPSR5_6, + GP_5_5_FN, GPSR5_5, + GP_5_4_FN, GPSR5_4, + GP_5_3_FN, GPSR5_3, + GP_5_2_FN, GPSR5_2, + GP_5_1_FN, GPSR5_1, + GP_5_0_FN, GPSR5_0, } + }, + { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1) { + GP_6_31_FN, GPSR6_31, + GP_6_30_FN, GPSR6_30, + GP_6_29_FN, GPSR6_29, + GP_6_28_FN, GPSR6_28, + GP_6_27_FN, GPSR6_27, + GP_6_26_FN, GPSR6_26, + GP_6_25_FN, GPSR6_25, + GP_6_24_FN, GPSR6_24, + GP_6_23_FN, GPSR6_23, + GP_6_22_FN, GPSR6_22, + GP_6_21_FN, GPSR6_21, + GP_6_20_FN, GPSR6_20, + GP_6_19_FN, GPSR6_19, + GP_6_18_FN, GPSR6_18, + GP_6_17_FN, GPSR6_17, + GP_6_16_FN, GPSR6_16, + GP_6_15_FN, GPSR6_15, + GP_6_14_FN, GPSR6_14, + GP_6_13_FN, GPSR6_13, + GP_6_12_FN, GPSR6_12, + GP_6_11_FN, GPSR6_11, + GP_6_10_FN, GPSR6_10, + GP_6_9_FN, GPSR6_9, + GP_6_8_FN, GPSR6_8, + GP_6_7_FN, GPSR6_7, + GP_6_6_FN, GPSR6_6, + GP_6_5_FN, GPSR6_5, + GP_6_4_FN, GPSR6_4, + GP_6_3_FN, GPSR6_3, + GP_6_2_FN, GPSR6_2, + GP_6_1_FN, GPSR6_1, + GP_6_0_FN, GPSR6_0, } + }, + { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1) { + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + GP_7_3_FN, GPSR7_3, + GP_7_2_FN, GPSR7_2, + GP_7_1_FN, GPSR7_1, + GP_7_0_FN, GPSR7_0, } + }, +#undef F_ +#undef FM + +#define F_(x, y) x, +#define FM(x) FN_##x, + { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) { + IP0_31_28 + IP0_27_24 + IP0_23_20 + IP0_19_16 + IP0_15_12 + IP0_11_8 + IP0_7_4 + IP0_3_0 } + }, + { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) { + IP1_31_28 + IP1_27_24 + IP1_23_20 + IP1_19_16 + IP1_15_12 + IP1_11_8 + IP1_7_4 + IP1_3_0 } + }, + { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) { + IP2_31_28 + IP2_27_24 + IP2_23_20 + IP2_19_16 + IP2_15_12 + IP2_11_8 + IP2_7_4 + IP2_3_0 } + }, + { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) { + IP3_31_28 + IP3_27_24 + IP3_23_20 + IP3_19_16 + IP3_15_12 + IP3_11_8 + IP3_7_4 + IP3_3_0 } + }, + { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) { + IP4_31_28 + IP4_27_24 + IP4_23_20 + IP4_19_16 + IP4_15_12 + IP4_11_8 + IP4_7_4 + IP4_3_0 } + }, + { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) { + IP5_31_28 + IP5_27_24 + IP5_23_20 + IP5_19_16 + IP5_15_12 + IP5_11_8 + IP5_7_4 + IP5_3_0 } + }, + { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) { + IP6_31_28 + IP6_27_24 + IP6_23_20 + IP6_19_16 + IP6_15_12 + IP6_11_8 + IP6_7_4 + IP6_3_0 } + }, + { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) { + IP7_31_28 + IP7_27_24 + IP7_23_20 + IP7_19_16 + IP7_15_12 + IP7_11_8 + IP7_7_4 + IP7_3_0 } + }, + { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) { + IP8_31_28 + IP8_27_24 + IP8_23_20 + IP8_19_16 + IP8_15_12 + IP8_11_8 + IP8_7_4 + IP8_3_0 } + }, + { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4) { + IP9_31_28 + IP9_27_24 + IP9_23_20 + IP9_19_16 + IP9_15_12 + IP9_11_8 + IP9_7_4 + IP9_3_0 } + }, + { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4) { + IP10_31_28 + IP10_27_24 + IP10_23_20 + IP10_19_16 + IP10_15_12 + IP10_11_8 + IP10_7_4 + IP10_3_0 } + }, + { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4) { + IP11_31_28 + IP11_27_24 + IP11_23_20 + IP11_19_16 + IP11_15_12 + IP11_11_8 + IP11_7_4 + IP11_3_0 } + }, + { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4) { + IP12_31_28 + IP12_27_24 + IP12_23_20 + IP12_19_16 + IP12_15_12 + IP12_11_8 + IP12_7_4 + IP12_3_0 } + }, + { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4) { + IP13_31_28 + IP13_27_24 + IP13_23_20 + IP13_19_16 + IP13_15_12 + IP13_11_8 + IP13_7_4 + IP13_3_0 } + }, + { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4) { + IP14_31_28 + IP14_27_24 + IP14_23_20 + IP14_19_16 + IP14_15_12 + IP14_11_8 + IP14_7_4 + IP14_3_0 } + }, + { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4) { + IP15_31_28 + IP15_27_24 + IP15_23_20 + IP15_19_16 + IP15_15_12 + IP15_11_8 + IP15_7_4 + IP15_3_0 } + }, + { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4) { + IP16_31_28 + IP16_27_24 + IP16_23_20 + IP16_19_16 + IP16_15_12 + IP16_11_8 + IP16_7_4 + IP16_3_0 } + }, + { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4) { + /* IP17_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP17_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP17_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP17_19_16 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP17_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP17_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + IP17_7_4 + IP17_3_0 } + }, +#undef F_ +#undef FM + +#define F_(x, y) x, +#define FM(x) FN_##x, + { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32, + 1, 2, 2, 3, 1, 1, 2, 1, 1, 1, + 2, 1, 1, 1, 1, 1, 1, 1, 2, 2, 1, 2, 1) { + 0, 0, /* RESERVED 31 */ + MOD_SEL0_30_29 + MOD_SEL0_28_27 + MOD_SEL0_26_25_24 + MOD_SEL0_23 + MOD_SEL0_22 + MOD_SEL0_21_20 + MOD_SEL0_19 + MOD_SEL0_18 + MOD_SEL0_17 + MOD_SEL0_16_15 + MOD_SEL0_14 + MOD_SEL0_13 + MOD_SEL0_12 + MOD_SEL0_11 + MOD_SEL0_10 + MOD_SEL0_9 + MOD_SEL0_8 + MOD_SEL0_7_6 + MOD_SEL0_5_4 + MOD_SEL0_3 + MOD_SEL0_2_1 + 0, 0, /* RESERVED 0 */ } + }, + { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32, + 2, 3, 1, 2, 3, 1, 1, 2, 1, + 2, 1, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1) { + MOD_SEL1_31_30 + MOD_SEL1_29_28_27 + MOD_SEL1_26 + MOD_SEL1_25_24 + MOD_SEL1_23_22_21 + MOD_SEL1_20 + MOD_SEL1_19 + MOD_SEL1_18_17 + MOD_SEL1_16 + MOD_SEL1_15_14 + MOD_SEL1_13 + MOD_SEL1_12 + MOD_SEL1_11 + MOD_SEL1_10 + MOD_SEL1_9 + 0, 0, 0, 0, /* RESERVED 8, 7 */ + MOD_SEL1_6 + MOD_SEL1_5 + MOD_SEL1_4 + MOD_SEL1_3 + MOD_SEL1_2 + MOD_SEL1_1 + MOD_SEL1_0 } + }, + { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32, + 1, 1, 1, 1, 4, 4, 4, + 4, 4, 4, 1, 2, 1) { + MOD_SEL2_31 + MOD_SEL2_30 + MOD_SEL2_29 + /* RESERVED 28 */ + 0, 0, + /* RESERVED 27, 26, 25, 24 */ + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + /* RESERVED 23, 22, 21, 20 */ + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + /* RESERVED 19, 18, 17, 16 */ + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + /* RESERVED 15, 14, 13, 12 */ + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + /* RESERVED 11, 10, 9, 8 */ + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + /* RESERVED 7, 6, 5, 4 */ + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + /* RESERVED 3 */ + 0, 0, + MOD_SEL2_2_1 + MOD_SEL2_0 } + }, + { }, +}; + +const struct sh_pfc_soc_info r8a7795_pinmux_info = { + .name = "r8a77950_pfc", + .unlock_reg = 0xe6060000, /* PMMR */ + + .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, + + .pins = pinmux_pins, + .nr_pins = ARRAY_SIZE(pinmux_pins), + .groups = pinmux_groups, + .nr_groups = ARRAY_SIZE(pinmux_groups), + .functions = pinmux_functions, + .nr_functions = ARRAY_SIZE(pinmux_functions), + + .cfg_regs = pinmux_config_regs, + + .gpio_data = pinmux_data, + .gpio_data_size = ARRAY_SIZE(pinmux_data), +}; -- cgit v0.10.2 From ff8459a5061670960f944fcefc4b69af77e14739 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 3 Sep 2015 02:52:07 +0000 Subject: pinctrl: sh-pfc: r8a7795: add SCIFx support This patch adds SCIF0/1/2/3/4/5 Signed-off-by: Geert Uytterhoeven [Morimoto-san: Updated] Signed-off-by: Kuninori Morimoto Acked-by: Laurent Pinchart Acked-by: Linus Walleij diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c index 79abfaa..aff3895 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c @@ -1426,10 +1426,267 @@ static const struct sh_pfc_pin pinmux_pins[] = { PINMUX_GPIO_GP_ALL(), }; +/* - SCIF0 ------------------------------------------------------------------ */ +static const unsigned int scif0_data_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2), +}; +static const unsigned int scif0_data_mux[] = { + RX0_MARK, TX0_MARK, +}; +static const unsigned int scif0_clk_pins[] = { + /* SCK */ + RCAR_GP_PIN(5, 0), +}; +static const unsigned int scif0_clk_mux[] = { + SCK0_MARK, +}; +static const unsigned int scif0_ctrl_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3), +}; +static const unsigned int scif0_ctrl_mux[] = { + RTS0_N_TANS_MARK, CTS0_N_MARK, +}; +/* - SCIF1 ------------------------------------------------------------------ */ +static const unsigned int scif1_data_a_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6), +}; +static const unsigned int scif1_data_a_mux[] = { + RX1_A_MARK, TX1_A_MARK, +}; +static const unsigned int scif1_clk_pins[] = { + /* SCK */ + RCAR_GP_PIN(6, 21), +}; +static const unsigned int scif1_clk_mux[] = { + SCK1_MARK, +}; +static const unsigned int scif1_ctrl_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7), +}; +static const unsigned int scif1_ctrl_mux[] = { + RTS1_N_TANS_MARK, CTS1_N_MARK, +}; + +static const unsigned int scif1_data_b_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25), +}; +static const unsigned int scif1_data_b_mux[] = { + RX1_B_MARK, TX1_B_MARK, +}; +/* - SCIF2 ------------------------------------------------------------------ */ +static const unsigned int scif2_data_a_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10), +}; +static const unsigned int scif2_data_a_mux[] = { + RX2_A_MARK, TX2_A_MARK, +}; +static const unsigned int scif2_clk_pins[] = { + /* SCK */ + RCAR_GP_PIN(5, 9), +}; +static const unsigned int scif2_clk_mux[] = { + SCK2_MARK, +}; +static const unsigned int scif2_data_b_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16), +}; +static const unsigned int scif2_data_b_mux[] = { + RX2_B_MARK, TX2_B_MARK, +}; +/* - SCIF3 ------------------------------------------------------------------ */ +static const unsigned int scif3_data_a_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24), +}; +static const unsigned int scif3_data_a_mux[] = { + RX3_A_MARK, TX3_A_MARK, +}; +static const unsigned int scif3_clk_pins[] = { + /* SCK */ + RCAR_GP_PIN(1, 22), +}; +static const unsigned int scif3_clk_mux[] = { + SCK3_MARK, +}; +static const unsigned int scif3_ctrl_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25), +}; +static const unsigned int scif3_ctrl_mux[] = { + RTS3_N_TANS_MARK, CTS3_N_MARK, +}; +static const unsigned int scif3_data_b_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11), +}; +static const unsigned int scif3_data_b_mux[] = { + RX3_B_MARK, TX3_B_MARK, +}; +/* - SCIF4 ------------------------------------------------------------------ */ +static const unsigned int scif4_data_a_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12), +}; +static const unsigned int scif4_data_a_mux[] = { + RX4_A_MARK, TX4_A_MARK, +}; +static const unsigned int scif4_clk_a_pins[] = { + /* SCK */ + RCAR_GP_PIN(2, 10), +}; +static const unsigned int scif4_clk_a_mux[] = { + SCK4_A_MARK, +}; +static const unsigned int scif4_ctrl_a_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13), +}; +static const unsigned int scif4_ctrl_a_mux[] = { + RTS4_N_TANS_A_MARK, CTS4_N_A_MARK, +}; +static const unsigned int scif4_data_b_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), +}; +static const unsigned int scif4_data_b_mux[] = { + RX4_B_MARK, TX4_B_MARK, +}; +static const unsigned int scif4_clk_b_pins[] = { + /* SCK */ + RCAR_GP_PIN(1, 5), +}; +static const unsigned int scif4_clk_b_mux[] = { + SCK4_B_MARK, +}; +static const unsigned int scif4_ctrl_b_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9), +}; +static const unsigned int scif4_ctrl_b_mux[] = { + RTS4_N_TANS_B_MARK, CTS4_N_B_MARK, +}; +static const unsigned int scif4_data_c_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), +}; +static const unsigned int scif4_data_c_mux[] = { + RX4_C_MARK, TX4_C_MARK, +}; +static const unsigned int scif4_clk_c_pins[] = { + /* SCK */ + RCAR_GP_PIN(0, 8), +}; +static const unsigned int scif4_clk_c_mux[] = { + SCK4_C_MARK, +}; +static const unsigned int scif4_ctrl_c_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10), +}; +static const unsigned int scif4_ctrl_c_mux[] = { + RTS4_N_TANS_C_MARK, CTS4_N_C_MARK, +}; +/* - SCIF5 ------------------------------------------------------------------ */ +static const unsigned int scif5_data_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21), +}; +static const unsigned int scif5_data_mux[] = { + RX5_MARK, TX5_MARK, +}; +static const unsigned int scif5_clk_pins[] = { + /* SCK */ + RCAR_GP_PIN(6, 21), +}; +static const unsigned int scif5_clk_mux[] = { + SCK5_MARK, +}; + static const struct sh_pfc_pin_group pinmux_groups[] = { + SH_PFC_PIN_GROUP(scif0_data), + SH_PFC_PIN_GROUP(scif0_clk), + SH_PFC_PIN_GROUP(scif0_ctrl), + SH_PFC_PIN_GROUP(scif1_data_a), + SH_PFC_PIN_GROUP(scif1_clk), + SH_PFC_PIN_GROUP(scif1_ctrl), + SH_PFC_PIN_GROUP(scif1_data_b), + SH_PFC_PIN_GROUP(scif2_data_a), + SH_PFC_PIN_GROUP(scif2_clk), + SH_PFC_PIN_GROUP(scif2_data_b), + SH_PFC_PIN_GROUP(scif3_data_a), + SH_PFC_PIN_GROUP(scif3_clk), + SH_PFC_PIN_GROUP(scif3_ctrl), + SH_PFC_PIN_GROUP(scif3_data_b), + SH_PFC_PIN_GROUP(scif4_data_a), + SH_PFC_PIN_GROUP(scif4_clk_a), + SH_PFC_PIN_GROUP(scif4_ctrl_a), + SH_PFC_PIN_GROUP(scif4_data_b), + SH_PFC_PIN_GROUP(scif4_clk_b), + SH_PFC_PIN_GROUP(scif4_ctrl_b), + SH_PFC_PIN_GROUP(scif4_data_c), + SH_PFC_PIN_GROUP(scif4_clk_c), + SH_PFC_PIN_GROUP(scif4_ctrl_c), + SH_PFC_PIN_GROUP(scif5_data), + SH_PFC_PIN_GROUP(scif5_clk), +}; + +static const char * const scif0_groups[] = { + "scif0_data", + "scif0_clk", + "scif0_ctrl", +}; + +static const char * const scif1_groups[] = { + "scif1_data_a", + "scif1_clk", + "scif1_ctrl", + "scif1_data_b", +}; + +static const char * const scif2_groups[] = { + "scif2_data_a", + "scif2_clk", + "scif2_data_b", +}; + +static const char * const scif3_groups[] = { + "scif3_data_a", + "scif3_clk", + "scif3_ctrl", + "scif3_data_b", +}; + +static const char * const scif4_groups[] = { + "scif4_data_a", + "scif4_clk_a", + "scif4_ctrl_a", + "scif4_data_b", + "scif4_clk_b", + "scif4_ctrl_b", + "scif4_data_c", + "scif4_clk_c", + "scif4_ctrl_c", +}; + +static const char * const scif5_groups[] = { + "scif5_data", + "scif5_clk", }; static const struct sh_pfc_function pinmux_functions[] = { + SH_PFC_FUNCTION(scif0), + SH_PFC_FUNCTION(scif1), + SH_PFC_FUNCTION(scif2), + SH_PFC_FUNCTION(scif3), + SH_PFC_FUNCTION(scif4), + SH_PFC_FUNCTION(scif5), }; static const struct pinmux_cfg_reg pinmux_config_regs[] = { -- cgit v0.10.2 From 2544ef72306a34344cc636272d8567f5682ca4fb Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Fri, 18 Sep 2015 01:53:33 +0000 Subject: pinctrl: sh-pfc: r8a7795: add I2C pin support Signed-off-by: Kuninori Morimoto Reviewed-by: Geert Uytterhoeven Signed-off-by: Geert Uytterhoeven diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c index aff3895..f6afe71 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c @@ -1426,6 +1426,57 @@ static const struct sh_pfc_pin pinmux_pins[] = { PINMUX_GPIO_GP_ALL(), }; +/* - I2C -------------------------------------------------------------------- */ +static const unsigned int i2c1_a_pins[] = { + /* SDA, SCL */ + RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10), +}; +static const unsigned int i2c1_a_mux[] = { + SDA1_A_MARK, SCL1_A_MARK, +}; +static const unsigned int i2c1_b_pins[] = { + /* SDA, SCL */ + RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23), +}; +static const unsigned int i2c1_b_mux[] = { + SDA1_B_MARK, SCL1_B_MARK, +}; +static const unsigned int i2c2_a_pins[] = { + /* SDA, SCL */ + RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4), +}; +static const unsigned int i2c2_a_mux[] = { + SDA2_A_MARK, SCL2_A_MARK, +}; +static const unsigned int i2c2_b_pins[] = { + /* SDA, SCL */ + RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12), +}; +static const unsigned int i2c2_b_mux[] = { + SDA2_B_MARK, SCL2_B_MARK, +}; +static const unsigned int i2c6_a_pins[] = { + /* SDA, SCL */ + RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11), +}; +static const unsigned int i2c6_a_mux[] = { + SDA6_A_MARK, SCL6_A_MARK, +}; +static const unsigned int i2c6_b_pins[] = { + /* SDA, SCL */ + RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25), +}; +static const unsigned int i2c6_b_mux[] = { + SDA6_B_MARK, SCL6_B_MARK, +}; +static const unsigned int i2c6_c_pins[] = { + /* SDA, SCL */ + RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), +}; +static const unsigned int i2c6_c_mux[] = { + SDA6_C_MARK, SCL6_C_MARK, +}; + /* - SCIF0 ------------------------------------------------------------------ */ static const unsigned int scif0_data_pins[] = { /* RX, TX */ @@ -1610,6 +1661,13 @@ static const unsigned int scif5_clk_mux[] = { }; static const struct sh_pfc_pin_group pinmux_groups[] = { + SH_PFC_PIN_GROUP(i2c1_a), + SH_PFC_PIN_GROUP(i2c1_b), + SH_PFC_PIN_GROUP(i2c2_a), + SH_PFC_PIN_GROUP(i2c2_b), + SH_PFC_PIN_GROUP(i2c6_a), + SH_PFC_PIN_GROUP(i2c6_b), + SH_PFC_PIN_GROUP(i2c6_c), SH_PFC_PIN_GROUP(scif0_data), SH_PFC_PIN_GROUP(scif0_clk), SH_PFC_PIN_GROUP(scif0_ctrl), @@ -1637,6 +1695,22 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(scif5_clk), }; +static const char * const i2c1_groups[] = { + "i2c1_a", + "i2c1_b", +}; + +static const char * const i2c2_groups[] = { + "i2c2_a", + "i2c2_b", +}; + +static const char * const i2c6_groups[] = { + "i2c6_a", + "i2c6_b", + "i2c6_c", +}; + static const char * const scif0_groups[] = { "scif0_data", "scif0_clk", @@ -1681,6 +1755,9 @@ static const char * const scif5_groups[] = { }; static const struct sh_pfc_function pinmux_functions[] = { + SH_PFC_FUNCTION(i2c1), + SH_PFC_FUNCTION(i2c2), + SH_PFC_FUNCTION(i2c6), SH_PFC_FUNCTION(scif0), SH_PFC_FUNCTION(scif1), SH_PFC_FUNCTION(scif2), -- cgit v0.10.2 From c33a7fe39975f64edbbbfafcaef268fb162d5d63 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Fri, 18 Sep 2015 01:54:02 +0000 Subject: pinctrl: sh-pfc: r8a7795: add Audio clock pin support Signed-off-by: Kuninori Morimoto Reviewed-by: Geert Uytterhoeven Signed-off-by: Geert Uytterhoeven diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c index f6afe71..7ef2f71 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c @@ -1426,6 +1426,128 @@ static const struct sh_pfc_pin pinmux_pins[] = { PINMUX_GPIO_GP_ALL(), }; +/* - AUDIO CLOCK ------------------------------------------------------------ */ +static const unsigned int audio_clk_a_a_pins[] = { + /* CLK A */ + RCAR_GP_PIN(6, 22), +}; +static const unsigned int audio_clk_a_a_mux[] = { + AUDIO_CLKA_A_MARK, +}; +static const unsigned int audio_clk_a_b_pins[] = { + /* CLK A */ + RCAR_GP_PIN(5, 4), +}; +static const unsigned int audio_clk_a_b_mux[] = { + AUDIO_CLKA_B_MARK, +}; +static const unsigned int audio_clk_a_c_pins[] = { + /* CLK A */ + RCAR_GP_PIN(5, 19), +}; +static const unsigned int audio_clk_a_c_mux[] = { + AUDIO_CLKA_C_MARK, +}; +static const unsigned int audio_clk_b_a_pins[] = { + /* CLK B */ + RCAR_GP_PIN(5, 12), +}; +static const unsigned int audio_clk_b_a_mux[] = { + AUDIO_CLKB_A_MARK, +}; +static const unsigned int audio_clk_b_b_pins[] = { + /* CLK B */ + RCAR_GP_PIN(6, 23), +}; +static const unsigned int audio_clk_b_b_mux[] = { + AUDIO_CLKB_B_MARK, +}; +static const unsigned int audio_clk_c_a_pins[] = { + /* CLK C */ + RCAR_GP_PIN(5, 21), +}; +static const unsigned int audio_clk_c_a_mux[] = { + AUDIO_CLKC_A_MARK, +}; +static const unsigned int audio_clk_c_b_pins[] = { + /* CLK C */ + RCAR_GP_PIN(5, 0), +}; +static const unsigned int audio_clk_c_b_mux[] = { + AUDIO_CLKC_B_MARK, +}; +static const unsigned int audio_clkout_a_pins[] = { + /* CLKOUT */ + RCAR_GP_PIN(5, 18), +}; +static const unsigned int audio_clkout_a_mux[] = { + AUDIO_CLKOUT_A_MARK, +}; +static const unsigned int audio_clkout_b_pins[] = { + /* CLKOUT */ + RCAR_GP_PIN(6, 28), +}; +static const unsigned int audio_clkout_b_mux[] = { + AUDIO_CLKOUT_B_MARK, +}; +static const unsigned int audio_clkout_c_pins[] = { + /* CLKOUT */ + RCAR_GP_PIN(5, 3), +}; +static const unsigned int audio_clkout_c_mux[] = { + AUDIO_CLKOUT_C_MARK, +}; +static const unsigned int audio_clkout_d_pins[] = { + /* CLKOUT */ + RCAR_GP_PIN(5, 21), +}; +static const unsigned int audio_clkout_d_mux[] = { + AUDIO_CLKOUT_D_MARK, +}; +static const unsigned int audio_clkout1_a_pins[] = { + /* CLKOUT1 */ + RCAR_GP_PIN(5, 15), +}; +static const unsigned int audio_clkout1_a_mux[] = { + AUDIO_CLKOUT1_A_MARK, +}; +static const unsigned int audio_clkout1_b_pins[] = { + /* CLKOUT1 */ + RCAR_GP_PIN(6, 29), +}; +static const unsigned int audio_clkout1_b_mux[] = { + AUDIO_CLKOUT1_B_MARK, +}; +static const unsigned int audio_clkout2_a_pins[] = { + /* CLKOUT2 */ + RCAR_GP_PIN(5, 16), +}; +static const unsigned int audio_clkout2_a_mux[] = { + AUDIO_CLKOUT2_A_MARK, +}; +static const unsigned int audio_clkout2_b_pins[] = { + /* CLKOUT2 */ + RCAR_GP_PIN(6, 30), +}; +static const unsigned int audio_clkout2_b_mux[] = { + AUDIO_CLKOUT2_B_MARK, +}; + +static const unsigned int audio_clkout3_a_pins[] = { + /* CLKOUT3 */ + RCAR_GP_PIN(5, 19), +}; +static const unsigned int audio_clkout3_a_mux[] = { + AUDIO_CLKOUT3_A_MARK, +}; +static const unsigned int audio_clkout3_b_pins[] = { + /* CLKOUT3 */ + RCAR_GP_PIN(6, 31), +}; +static const unsigned int audio_clkout3_b_mux[] = { + AUDIO_CLKOUT3_B_MARK, +}; + /* - I2C -------------------------------------------------------------------- */ static const unsigned int i2c1_a_pins[] = { /* SDA, SCL */ @@ -1661,6 +1783,23 @@ static const unsigned int scif5_clk_mux[] = { }; static const struct sh_pfc_pin_group pinmux_groups[] = { + SH_PFC_PIN_GROUP(audio_clk_a_a), + SH_PFC_PIN_GROUP(audio_clk_a_b), + SH_PFC_PIN_GROUP(audio_clk_a_c), + SH_PFC_PIN_GROUP(audio_clk_b_a), + SH_PFC_PIN_GROUP(audio_clk_b_b), + SH_PFC_PIN_GROUP(audio_clk_c_a), + SH_PFC_PIN_GROUP(audio_clk_c_b), + SH_PFC_PIN_GROUP(audio_clkout_a), + SH_PFC_PIN_GROUP(audio_clkout_b), + SH_PFC_PIN_GROUP(audio_clkout_c), + SH_PFC_PIN_GROUP(audio_clkout_d), + SH_PFC_PIN_GROUP(audio_clkout1_a), + SH_PFC_PIN_GROUP(audio_clkout1_b), + SH_PFC_PIN_GROUP(audio_clkout2_a), + SH_PFC_PIN_GROUP(audio_clkout2_b), + SH_PFC_PIN_GROUP(audio_clkout3_a), + SH_PFC_PIN_GROUP(audio_clkout3_b), SH_PFC_PIN_GROUP(i2c1_a), SH_PFC_PIN_GROUP(i2c1_b), SH_PFC_PIN_GROUP(i2c2_a), @@ -1695,6 +1834,26 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(scif5_clk), }; +static const char * const audio_clk_groups[] = { + "audio_clk_a_a", + "audio_clk_a_b", + "audio_clk_a_c", + "audio_clk_b_a", + "audio_clk_b_b", + "audio_clk_c_a", + "audio_clk_c_b", + "audio_clkout_a", + "audio_clkout_b", + "audio_clkout_c", + "audio_clkout_d", + "audio_clkout1_a", + "audio_clkout1_b", + "audio_clkout2_a", + "audio_clkout2_b", + "audio_clkout3_a", + "audio_clkout3_b", +}; + static const char * const i2c1_groups[] = { "i2c1_a", "i2c1_b", @@ -1755,6 +1914,7 @@ static const char * const scif5_groups[] = { }; static const struct sh_pfc_function pinmux_functions[] = { + SH_PFC_FUNCTION(audio_clk), SH_PFC_FUNCTION(i2c1), SH_PFC_FUNCTION(i2c2), SH_PFC_FUNCTION(i2c6), -- cgit v0.10.2 From 9b132ba3e31773ad9371f4a296c5a99ac483fb40 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Fri, 18 Sep 2015 01:54:25 +0000 Subject: pinctrl: sh-pfc: r8a7795: add Audio SSI pin support Signed-off-by: Kuninori Morimoto Reviewed-by: Geert Uytterhoeven Signed-off-by: Geert Uytterhoeven diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c index 7ef2f71..e9be4ac 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c @@ -1782,6 +1782,183 @@ static const unsigned int scif5_clk_mux[] = { SCK5_MARK, }; +/* - SSI -------------------------------------------------------------------- */ +static const unsigned int ssi0_data_pins[] = { + /* SDATA */ + RCAR_GP_PIN(6, 2), +}; +static const unsigned int ssi0_data_mux[] = { + SSI_SDATA0_MARK, +}; +static const unsigned int ssi01239_ctrl_pins[] = { + /* SCK, WS */ + RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1), +}; +static const unsigned int ssi01239_ctrl_mux[] = { + SSI_SCK0129_MARK, SSI_WS0129_MARK, +}; +static const unsigned int ssi1_data_a_pins[] = { + /* SDATA */ + RCAR_GP_PIN(6, 3), +}; +static const unsigned int ssi1_data_a_mux[] = { + SSI_SDATA1_A_MARK, +}; +static const unsigned int ssi1_data_b_pins[] = { + /* SDATA */ + RCAR_GP_PIN(5, 12), +}; +static const unsigned int ssi1_data_b_mux[] = { + SSI_SDATA1_B_MARK, +}; +static const unsigned int ssi1_ctrl_a_pins[] = { + /* SCK, WS */ + RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27), +}; +static const unsigned int ssi1_ctrl_a_mux[] = { + SSI_SCK1_A_MARK, SSI_WS1_A_MARK, +}; +static const unsigned int ssi1_ctrl_b_pins[] = { + /* SCK, WS */ + RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 21), +}; +static const unsigned int ssi1_ctrl_b_mux[] = { + SSI_SCK1_B_MARK, SSI_WS1_B_MARK, +}; +static const unsigned int ssi2_data_a_pins[] = { + /* SDATA */ + RCAR_GP_PIN(6, 4), +}; +static const unsigned int ssi2_data_a_mux[] = { + SSI_SDATA2_A_MARK, +}; +static const unsigned int ssi2_data_b_pins[] = { + /* SDATA */ + RCAR_GP_PIN(5, 13), +}; +static const unsigned int ssi2_data_b_mux[] = { + SSI_SDATA2_B_MARK, +}; +static const unsigned int ssi2_ctrl_a_pins[] = { + /* SCK, WS */ + RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21), +}; +static const unsigned int ssi2_ctrl_a_mux[] = { + SSI_SCK2_A_MARK, SSI_WS2_A_MARK, +}; +static const unsigned int ssi2_ctrl_b_pins[] = { + /* SCK, WS */ + RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29), +}; +static const unsigned int ssi2_ctrl_b_mux[] = { + SSI_SCK2_B_MARK, SSI_WS2_B_MARK, +}; +static const unsigned int ssi3_data_pins[] = { + /* SDATA */ + RCAR_GP_PIN(6, 7), +}; +static const unsigned int ssi3_data_mux[] = { + SSI_SDATA3_MARK, +}; +static const unsigned int ssi34_ctrl_pins[] = { + /* SCK, WS */ + RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 6), +}; +static const unsigned int ssi34_ctrl_mux[] = { + SSI_SCK34_MARK, SSI_WS34_MARK, +}; +static const unsigned int ssi4_data_pins[] = { + /* SDATA */ + RCAR_GP_PIN(6, 10), +}; +static const unsigned int ssi4_data_mux[] = { + SSI_SDATA4_MARK, +}; +static const unsigned int ssi4_ctrl_pins[] = { + /* SCK, WS */ + RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9), +}; +static const unsigned int ssi4_ctrl_mux[] = { + SSI_SCK4_MARK, SSI_WS4_MARK, +}; +static const unsigned int ssi5_data_pins[] = { + /* SDATA */ + RCAR_GP_PIN(6, 13), +}; +static const unsigned int ssi5_data_mux[] = { + SSI_SDATA5_MARK, +}; +static const unsigned int ssi5_ctrl_pins[] = { + /* SCK, WS */ + RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12), +}; +static const unsigned int ssi5_ctrl_mux[] = { + SSI_SCK5_MARK, SSI_WS5_MARK, +}; +static const unsigned int ssi6_data_pins[] = { + /* SDATA */ + RCAR_GP_PIN(6, 16), +}; +static const unsigned int ssi6_data_mux[] = { + SSI_SDATA6_MARK, +}; +static const unsigned int ssi6_ctrl_pins[] = { + /* SCK, WS */ + RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15), +}; +static const unsigned int ssi6_ctrl_mux[] = { + SSI_SCK6_MARK, SSI_WS6_MARK, +}; +static const unsigned int ssi7_data_pins[] = { + /* SDATA */ + RCAR_GP_PIN(6, 19), +}; +static const unsigned int ssi7_data_mux[] = { + SSI_SDATA7_MARK, +}; +static const unsigned int ssi78_ctrl_pins[] = { + /* SCK, WS */ + RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18), +}; +static const unsigned int ssi78_ctrl_mux[] = { + SSI_SCK78_MARK, SSI_WS78_MARK, +}; +static const unsigned int ssi8_data_pins[] = { + /* SDATA */ + RCAR_GP_PIN(6, 20), +}; +static const unsigned int ssi8_data_mux[] = { + SSI_SDATA8_MARK, +}; +static const unsigned int ssi9_data_a_pins[] = { + /* SDATA */ + RCAR_GP_PIN(6, 21), +}; +static const unsigned int ssi9_data_a_mux[] = { + SSI_SDATA9_A_MARK, +}; +static const unsigned int ssi9_data_b_pins[] = { + /* SDATA */ + RCAR_GP_PIN(5, 14), +}; +static const unsigned int ssi9_data_b_mux[] = { + SSI_SDATA9_B_MARK, +}; +static const unsigned int ssi9_ctrl_a_pins[] = { + /* SCK, WS */ + RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16), +}; +static const unsigned int ssi9_ctrl_a_mux[] = { + SSI_SCK9_A_MARK, SSI_WS9_A_MARK, +}; +static const unsigned int ssi9_ctrl_b_pins[] = { + /* SCK, WS */ + RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31), +}; +static const unsigned int ssi9_ctrl_b_mux[] = { + SSI_SCK9_B_MARK, SSI_WS9_B_MARK, +}; + static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(audio_clk_a_a), SH_PFC_PIN_GROUP(audio_clk_a_b), @@ -1832,6 +2009,31 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(scif4_ctrl_c), SH_PFC_PIN_GROUP(scif5_data), SH_PFC_PIN_GROUP(scif5_clk), + SH_PFC_PIN_GROUP(ssi0_data), + SH_PFC_PIN_GROUP(ssi01239_ctrl), + SH_PFC_PIN_GROUP(ssi1_data_a), + SH_PFC_PIN_GROUP(ssi1_data_b), + SH_PFC_PIN_GROUP(ssi1_ctrl_a), + SH_PFC_PIN_GROUP(ssi1_ctrl_b), + SH_PFC_PIN_GROUP(ssi2_data_a), + SH_PFC_PIN_GROUP(ssi2_data_b), + SH_PFC_PIN_GROUP(ssi2_ctrl_a), + SH_PFC_PIN_GROUP(ssi2_ctrl_b), + SH_PFC_PIN_GROUP(ssi3_data), + SH_PFC_PIN_GROUP(ssi34_ctrl), + SH_PFC_PIN_GROUP(ssi4_data), + SH_PFC_PIN_GROUP(ssi4_ctrl), + SH_PFC_PIN_GROUP(ssi5_data), + SH_PFC_PIN_GROUP(ssi5_ctrl), + SH_PFC_PIN_GROUP(ssi6_data), + SH_PFC_PIN_GROUP(ssi6_ctrl), + SH_PFC_PIN_GROUP(ssi7_data), + SH_PFC_PIN_GROUP(ssi78_ctrl), + SH_PFC_PIN_GROUP(ssi8_data), + SH_PFC_PIN_GROUP(ssi9_data_a), + SH_PFC_PIN_GROUP(ssi9_data_b), + SH_PFC_PIN_GROUP(ssi9_ctrl_a), + SH_PFC_PIN_GROUP(ssi9_ctrl_b), }; static const char * const audio_clk_groups[] = { @@ -1913,6 +2115,34 @@ static const char * const scif5_groups[] = { "scif5_clk", }; +static const char * const ssi_groups[] = { + "ssi0_data", + "ssi01239_ctrl", + "ssi1_data_a", + "ssi1_data_b", + "ssi1_ctrl_a", + "ssi1_ctrl_b", + "ssi2_data_a", + "ssi2_data_b", + "ssi2_ctrl_a", + "ssi2_ctrl_b", + "ssi3_data", + "ssi34_ctrl", + "ssi4_data", + "ssi4_ctrl", + "ssi5_data", + "ssi5_ctrl", + "ssi6_data", + "ssi6_ctrl", + "ssi7_data", + "ssi78_ctrl", + "ssi8_data", + "ssi9_data_a", + "ssi9_data_b", + "ssi9_ctrl_a", + "ssi9_ctrl_b", +}; + static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(audio_clk), SH_PFC_FUNCTION(i2c1), @@ -1924,6 +2154,7 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(scif3), SH_PFC_FUNCTION(scif4), SH_PFC_FUNCTION(scif5), + SH_PFC_FUNCTION(ssi), }; static const struct pinmux_cfg_reg pinmux_config_regs[] = { -- cgit v0.10.2 From 819fd4bfcc84805c48291de511c917596e911ffa Mon Sep 17 00:00:00 2001 From: Takeshi Kihara Date: Tue, 15 Sep 2015 14:49:15 +0900 Subject: pinctrl: sh-pfc: r8a7795: add EtherAVB support This patch adds EthernetAVB Based on a much lager patch by Takeshi Kihara which was originally posted by Kuninori Morimoto. Signed-off-by: Takeshi Kihara Signed-off-by: Kuninori Morimoto [horms: extracted from a larger patch; corrected swapped {MATCH,CAPTURE_A} pins] Signed-off-by: Simon Horman Reviewed-by: Geert Uytterhoeven Signed-off-by: Geert Uytterhoeven diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c index e9be4ac..dce06ed0 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c @@ -1548,6 +1548,71 @@ static const unsigned int audio_clkout3_b_mux[] = { AUDIO_CLKOUT3_B_MARK, }; +/* - EtherAVB --------------------------------------------------------------- */ +static const unsigned int avb_link_pins[] = { + /* AVB_LINK */ + RCAR_GP_PIN(2, 12), +}; +static const unsigned int avb_link_mux[] = { + AVB_LINK_MARK, +}; +static const unsigned int avb_magic_pins[] = { + /* AVB_MAGIC_ */ + RCAR_GP_PIN(2, 10), +}; +static const unsigned int avb_magic_mux[] = { + AVB_MAGIC_MARK, +}; +static const unsigned int avb_phy_int_pins[] = { + /* AVB_PHY_INT */ + RCAR_GP_PIN(2, 11), +}; +static const unsigned int avb_phy_int_mux[] = { + AVB_PHY_INT_MARK, +}; +static const unsigned int avb_mdc_pins[] = { + /* AVB_MDC */ + RCAR_GP_PIN(2, 9), +}; +static const unsigned int avb_mdc_mux[] = { + AVB_MDC_MARK, +}; +static const unsigned int avb_avtp_pps_pins[] = { + /* AVB_AVTP_PPS */ + RCAR_GP_PIN(2, 6), +}; +static const unsigned int avb_avtp_pps_mux[] = { + AVB_AVTP_PPS_MARK, +}; +static const unsigned int avb_avtp_match_a_pins[] = { + /* AVB_AVTP_MATCH_A */ + RCAR_GP_PIN(2, 13), +}; +static const unsigned int avb_avtp_match_a_mux[] = { + AVB_AVTP_MATCH_A_MARK, +}; +static const unsigned int avb_avtp_capture_a_pins[] = { + /* AVB_AVTP_CAPTURE_A */ + RCAR_GP_PIN(2, 14), +}; +static const unsigned int avb_avtp_capture_a_mux[] = { + AVB_AVTP_CAPTURE_A_MARK, +}; +static const unsigned int avb_avtp_match_b_pins[] = { + /* AVB_AVTP_MATCH_B */ + RCAR_GP_PIN(1, 8), +}; +static const unsigned int avb_avtp_match_b_mux[] = { + AVB_AVTP_MATCH_B_MARK, +}; +static const unsigned int avb_avtp_capture_b_pins[] = { + /* AVB_AVTP_CAPTURE_B */ + RCAR_GP_PIN(1, 11), +}; +static const unsigned int avb_avtp_capture_b_mux[] = { + AVB_AVTP_CAPTURE_B_MARK, +}; + /* - I2C -------------------------------------------------------------------- */ static const unsigned int i2c1_a_pins[] = { /* SDA, SCL */ @@ -1977,6 +2042,15 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(audio_clkout2_b), SH_PFC_PIN_GROUP(audio_clkout3_a), SH_PFC_PIN_GROUP(audio_clkout3_b), + SH_PFC_PIN_GROUP(avb_link), + SH_PFC_PIN_GROUP(avb_magic), + SH_PFC_PIN_GROUP(avb_phy_int), + SH_PFC_PIN_GROUP(avb_mdc), + SH_PFC_PIN_GROUP(avb_avtp_pps), + SH_PFC_PIN_GROUP(avb_avtp_match_a), + SH_PFC_PIN_GROUP(avb_avtp_capture_a), + SH_PFC_PIN_GROUP(avb_avtp_match_b), + SH_PFC_PIN_GROUP(avb_avtp_capture_b), SH_PFC_PIN_GROUP(i2c1_a), SH_PFC_PIN_GROUP(i2c1_b), SH_PFC_PIN_GROUP(i2c2_a), @@ -2056,6 +2130,18 @@ static const char * const audio_clk_groups[] = { "audio_clkout3_b", }; +static const char * const avb_groups[] = { + "avb_link", + "avb_magic", + "avb_phy_int", + "avb_mdc", + "avb_avtp_pps", + "avb_avtp_match_a", + "avb_avtp_capture_a", + "avb_avtp_match_b", + "avb_avtp_capture_b", +}; + static const char * const i2c1_groups[] = { "i2c1_a", "i2c1_b", @@ -2145,6 +2231,7 @@ static const char * const ssi_groups[] = { static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(audio_clk), + SH_PFC_FUNCTION(avb), SH_PFC_FUNCTION(i2c1), SH_PFC_FUNCTION(i2c2), SH_PFC_FUNCTION(i2c6), -- cgit v0.10.2 From 916888838441e13155495f4d7e812e3bb0f5b875 Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Wed, 16 Sep 2015 10:28:26 +0200 Subject: pinctrl: tz1090: Remove unneded semicolons They aren't needed and are just creating null statements so remove it. Signed-off-by: Javier Martinez Canillas Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/pinctrl-tz1090.c b/drivers/pinctrl/pinctrl-tz1090.c index 6d07a2f..5425299 100644 --- a/drivers/pinctrl/pinctrl-tz1090.c +++ b/drivers/pinctrl/pinctrl-tz1090.c @@ -1661,7 +1661,7 @@ static int tz1090_pinconf_reg(struct pinctrl_dev *pctldev, break; default: return -ENOTSUPP; - }; + } /* Only input bias parameters supported */ pu = &tz1090_pinconf_pullup[pin]; @@ -1790,7 +1790,7 @@ static int tz1090_pinconf_group_reg(struct pinctrl_dev *pctldev, break; default: return -ENOTSUPP; - }; + } /* Calculate field information */ *shift = g->slw_bit * *width; -- cgit v0.10.2 From 1978c5ec0f8310df856a4a725048635725b673fa Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Wed, 16 Sep 2015 10:28:27 +0200 Subject: pinctrl: tz1090-pdc: Remove unneded semicolons They aren't needed and are just creating null statements so remove it. Signed-off-by: Javier Martinez Canillas Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/pinctrl-tz1090-pdc.c b/drivers/pinctrl/pinctrl-tz1090-pdc.c index c349911..b89ad3c 100644 --- a/drivers/pinctrl/pinctrl-tz1090-pdc.c +++ b/drivers/pinctrl/pinctrl-tz1090-pdc.c @@ -668,7 +668,7 @@ static int tz1090_pdc_pinconf_reg(struct pinctrl_dev *pctldev, break; default: return -ENOTSUPP; - }; + } /* Only input bias parameters supported */ *reg = REG_GPIO_CONTROL2; @@ -801,7 +801,7 @@ static int tz1090_pdc_pinconf_group_reg(struct pinctrl_dev *pctldev, break; default: return -ENOTSUPP; - }; + } /* Calculate field information */ *mask = (BIT(*width) - 1) << *shift; -- cgit v0.10.2 From 14316c4ca9675ee086e3635b58340aaa7f6976e5 Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Wed, 16 Sep 2015 10:28:28 +0200 Subject: pinctrl: mxs: Remove unneded semicolon MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit It's not needed an is just creating a null statement, so remove it. Signed-off-by: Javier Martinez Canillas Acked-by: Uwe Kleine-König Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/freescale/pinctrl-mxs.c b/drivers/pinctrl/freescale/pinctrl-mxs.c index f64eecb..6bbda6b 100644 --- a/drivers/pinctrl/freescale/pinctrl-mxs.c +++ b/drivers/pinctrl/freescale/pinctrl-mxs.c @@ -474,7 +474,7 @@ static int mxs_pinctrl_probe_dt(struct platform_device *pdev, f->name = fn = child->name; } f->ngroups++; - }; + } /* Get groups for each function */ idxf = 0; -- cgit v0.10.2 From 5c99c0ffa4ee284961a0214b171748df0edf16f4 Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Wed, 16 Sep 2015 10:28:29 +0200 Subject: pinctrl: sunxi: Remove unneeded semicolon It's not needed an is just creating a null statement, so remove it. Signed-off-by: Javier Martinez Canillas Acked-by: Maxime Ripard Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c index 38e0c7b..fe2c74a 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c @@ -1029,7 +1029,7 @@ int sunxi_pinctrl_init(struct platform_device *pdev, irq_set_chip_and_handler(irqno, &sunxi_pinctrl_edge_irq_chip, handle_edge_irq); irq_set_chip_data(irqno, pctl); - }; + } for (i = 0; i < pctl->desc->irq_banks; i++) { /* Mask and clear all IRQs before registering a handler */ -- cgit v0.10.2 From e44118997523cc62c893ba019a1fd3e0c43d6877 Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Wed, 16 Sep 2015 10:28:30 +0200 Subject: pinctrl: mediatek: Remove unneded semicolon It's not needed an is just creating a null statement, so remove it. Signed-off-by: Javier Martinez Canillas Acked-by: Hongzhou Yang Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c index c40f533..5279e23 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c @@ -1436,7 +1436,7 @@ int mtk_pctrl_init(struct platform_device *pdev, irq_set_chip_and_handler(virq, &mtk_pinctrl_irq_chip, handle_level_irq); irq_set_chip_data(virq, pctl); - }; + } irq_set_chained_handler_and_data(irq, mtk_eint_irq_handler, pctl); return 0; -- cgit v0.10.2 From be2cbd4dbbe63cfb6888f6ce96f1ac87eddae513 Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Wed, 16 Sep 2015 10:28:31 +0200 Subject: pinctrl: samsung: Remove unneded semicolon It's not needed an is just creating a null statement, so remove it. Signed-off-by: Javier Martinez Canillas Reviewed-by: Krzysztof Kozlowski Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/samsung/pinctrl-exynos5440.c b/drivers/pinctrl/samsung/pinctrl-exynos5440.c index 9ce0b86..82dc109 100644 --- a/drivers/pinctrl/samsung/pinctrl-exynos5440.c +++ b/drivers/pinctrl/samsung/pinctrl-exynos5440.c @@ -284,7 +284,7 @@ static void exynos5440_dt_free_map(struct pinctrl_dev *pctldev, if (!idx) kfree(map[idx].data.configs.group_or_pin); } - }; + } kfree(map); } -- cgit v0.10.2 From e86c62066e7be8b9f5284842ca8347991dd02edf Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Thu, 24 Sep 2015 21:26:47 +0900 Subject: pinctrl: uniphier: add SD card pinmux settings Add SD card pinmux settings for PH1-LD4, PH1-Pro4, PH1-sLD8, PH1-Pro5, ProXstream2, and PH1-LD6b SoCs. Signed-off-by: Masahiro Yamada Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/uniphier/pinctrl-ph1-ld4.c b/drivers/pinctrl/uniphier/pinctrl-ph1-ld4.c index 7beb87e..a7056dc 100644 --- a/drivers/pinctrl/uniphier/pinctrl-ph1-ld4.c +++ b/drivers/pinctrl/uniphier/pinctrl-ph1-ld4.c @@ -537,6 +537,8 @@ static const unsigned nand_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; static const unsigned nand_cs1_pins[] = {22, 23}; static const unsigned nand_cs1_muxvals[] = {0, 0}; +static const unsigned sd_pins[] = {44, 45, 46, 47, 48, 49, 50, 51, 52}; +static const unsigned sd_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0}; static const unsigned uart0_pins[] = {85, 88}; static const unsigned uart0_muxvals[] = {1, 1}; static const unsigned uart1_pins[] = {155, 156}; @@ -619,6 +621,7 @@ static const struct uniphier_pinctrl_group ph1_ld4_groups[] = { UNIPHIER_PINCTRL_GROUP(i2c3), UNIPHIER_PINCTRL_GROUP(nand), UNIPHIER_PINCTRL_GROUP(nand_cs1), + UNIPHIER_PINCTRL_GROUP(sd), UNIPHIER_PINCTRL_GROUP(uart0), UNIPHIER_PINCTRL_GROUP(uart1), UNIPHIER_PINCTRL_GROUP(uart1b), @@ -776,6 +779,7 @@ static const char * const i2c1_groups[] = {"i2c1"}; static const char * const i2c2_groups[] = {"i2c2"}; static const char * const i2c3_groups[] = {"i2c3"}; static const char * const nand_groups[] = {"nand", "nand_cs1"}; +static const char * const sd_groups[] = {"sd"}; static const char * const uart0_groups[] = {"uart0"}; static const char * const uart1_groups[] = {"uart1", "uart1b"}; static const char * const uart2_groups[] = {"uart2"}; @@ -831,6 +835,7 @@ static const struct uniphier_pinmux_function ph1_ld4_functions[] = { UNIPHIER_PINMUX_FUNCTION(i2c2), UNIPHIER_PINMUX_FUNCTION(i2c3), UNIPHIER_PINMUX_FUNCTION(nand), + UNIPHIER_PINMUX_FUNCTION(sd), UNIPHIER_PINMUX_FUNCTION(uart0), UNIPHIER_PINMUX_FUNCTION(uart1), UNIPHIER_PINMUX_FUNCTION(uart2), diff --git a/drivers/pinctrl/uniphier/pinctrl-ph1-ld6b.c b/drivers/pinctrl/uniphier/pinctrl-ph1-ld6b.c index 9720e697..1824831 100644 --- a/drivers/pinctrl/uniphier/pinctrl-ph1-ld6b.c +++ b/drivers/pinctrl/uniphier/pinctrl-ph1-ld6b.c @@ -761,6 +761,8 @@ static const unsigned nand_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; static const unsigned nand_cs1_pins[] = {37, 38}; static const unsigned nand_cs1_muxvals[] = {0, 0}; +static const unsigned sd_pins[] = {47, 48, 49, 50, 51, 52, 53, 54, 55}; +static const unsigned sd_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0}; static const unsigned uart0_pins[] = {135, 136}; static const unsigned uart0_muxvals[] = {3, 3}; static const unsigned uart0b_pins[] = {11, 12}; @@ -866,6 +868,7 @@ static const struct uniphier_pinctrl_group ph1_ld6b_groups[] = { UNIPHIER_PINCTRL_GROUP(i2c3), UNIPHIER_PINCTRL_GROUP(nand), UNIPHIER_PINCTRL_GROUP(nand_cs1), + UNIPHIER_PINCTRL_GROUP(sd), UNIPHIER_PINCTRL_GROUP(uart0), UNIPHIER_PINCTRL_GROUP(uart0b), UNIPHIER_PINCTRL_GROUP(uart1), @@ -1136,6 +1139,7 @@ static const char * const i2c1_groups[] = {"i2c1"}; static const char * const i2c2_groups[] = {"i2c2"}; static const char * const i2c3_groups[] = {"i2c3"}; static const char * const nand_groups[] = {"nand", "nand_cs1"}; +static const char * const sd_groups[] = {"sd"}; static const char * const uart0_groups[] = {"uart0", "uart0b"}; static const char * const uart1_groups[] = {"uart1", "uart1b"}; static const char * const uart2_groups[] = {"uart2", "uart2b"}; @@ -1219,6 +1223,7 @@ static const struct uniphier_pinmux_function ph1_ld6b_functions[] = { UNIPHIER_PINMUX_FUNCTION(i2c2), UNIPHIER_PINMUX_FUNCTION(i2c3), UNIPHIER_PINMUX_FUNCTION(nand), + UNIPHIER_PINMUX_FUNCTION(sd), UNIPHIER_PINMUX_FUNCTION(uart0), UNIPHIER_PINMUX_FUNCTION(uart1), UNIPHIER_PINMUX_FUNCTION(uart2), diff --git a/drivers/pinctrl/uniphier/pinctrl-ph1-pro4.c b/drivers/pinctrl/uniphier/pinctrl-ph1-pro4.c index 96921e4..ec8e92d 100644 --- a/drivers/pinctrl/uniphier/pinctrl-ph1-pro4.c +++ b/drivers/pinctrl/uniphier/pinctrl-ph1-pro4.c @@ -1031,6 +1031,11 @@ static const unsigned nand_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; static const unsigned nand_cs1_pins[] = {131, 132}; static const unsigned nand_cs1_muxvals[] = {1, 1}; +static const unsigned sd_pins[] = {150, 151, 152, 153, 154, 155, 156, 157, 158}; +static const unsigned sd_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0}; +static const unsigned sd1_pins[] = {319, 320, 321, 322, 323, 324, 325, 326, + 327}; +static const unsigned sd1_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0}; static const unsigned uart0_pins[] = {127, 128}; static const unsigned uart0_muxvals[] = {0, 0}; static const unsigned uart1_pins[] = {129, 130}; @@ -1140,6 +1145,8 @@ static const struct uniphier_pinctrl_group ph1_pro4_groups[] = { UNIPHIER_PINCTRL_GROUP(i2c6), UNIPHIER_PINCTRL_GROUP(nand), UNIPHIER_PINCTRL_GROUP(nand_cs1), + UNIPHIER_PINCTRL_GROUP(sd), + UNIPHIER_PINCTRL_GROUP(sd1), UNIPHIER_PINCTRL_GROUP(uart0), UNIPHIER_PINCTRL_GROUP(uart1), UNIPHIER_PINCTRL_GROUP(uart2), @@ -1412,6 +1419,8 @@ static const char * const i2c2_groups[] = {"i2c2"}; static const char * const i2c3_groups[] = {"i2c3"}; static const char * const i2c6_groups[] = {"i2c6"}; static const char * const nand_groups[] = {"nand", "nand_cs1"}; +static const char * const sd_groups[] = {"sd"}; +static const char * const sd1_groups[] = {"sd1"}; static const char * const uart0_groups[] = {"uart0"}; static const char * const uart1_groups[] = {"uart1"}; static const char * const uart2_groups[] = {"uart2"}; @@ -1498,6 +1507,8 @@ static const struct uniphier_pinmux_function ph1_pro4_functions[] = { UNIPHIER_PINMUX_FUNCTION(i2c3), UNIPHIER_PINMUX_FUNCTION(i2c6), UNIPHIER_PINMUX_FUNCTION(nand), + UNIPHIER_PINMUX_FUNCTION(sd), + UNIPHIER_PINMUX_FUNCTION(sd1), UNIPHIER_PINMUX_FUNCTION(uart0), UNIPHIER_PINMUX_FUNCTION(uart1), UNIPHIER_PINMUX_FUNCTION(uart2), diff --git a/drivers/pinctrl/uniphier/pinctrl-ph1-pro5.c b/drivers/pinctrl/uniphier/pinctrl-ph1-pro5.c index 9af4559..e3d648e 100644 --- a/drivers/pinctrl/uniphier/pinctrl-ph1-pro5.c +++ b/drivers/pinctrl/uniphier/pinctrl-ph1-pro5.c @@ -818,6 +818,8 @@ static const unsigned nand_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; static const unsigned nand_cs1_pins[] = {26, 27}; static const unsigned nand_cs1_muxvals[] = {0, 0}; +static const unsigned sd_pins[] = {250, 251, 252, 253, 254, 255, 256, 257, 258}; +static const unsigned sd_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0}; static const unsigned uart0_pins[] = {47, 48}; static const unsigned uart0_muxvals[] = {0, 0}; static const unsigned uart0b_pins[] = {227, 228}; @@ -930,6 +932,7 @@ static const struct uniphier_pinctrl_group ph1_pro5_groups[] = { UNIPHIER_PINCTRL_GROUP(i2c5b), UNIPHIER_PINCTRL_GROUP(i2c5c), UNIPHIER_PINCTRL_GROUP(i2c6), + UNIPHIER_PINCTRL_GROUP(sd), UNIPHIER_PINCTRL_GROUP(uart0), UNIPHIER_PINCTRL_GROUP(uart0b), UNIPHIER_PINCTRL_GROUP(uart1), @@ -1209,6 +1212,7 @@ static const char * const i2c3_groups[] = {"i2c3"}; static const char * const i2c5_groups[] = {"i2c5", "i2c5b", "i2c5c"}; static const char * const i2c6_groups[] = {"i2c6"}; static const char * const nand_groups[] = {"nand", "nand_cs1"}; +static const char * const sd_groups[] = {"sd"}; static const char * const uart0_groups[] = {"uart0", "uart0b"}; static const char * const uart1_groups[] = {"uart1"}; static const char * const uart2_groups[] = {"uart2"}; @@ -1296,6 +1300,7 @@ static const struct uniphier_pinmux_function ph1_pro5_functions[] = { UNIPHIER_PINMUX_FUNCTION(i2c5), UNIPHIER_PINMUX_FUNCTION(i2c6), UNIPHIER_PINMUX_FUNCTION(nand), + UNIPHIER_PINMUX_FUNCTION(sd), UNIPHIER_PINMUX_FUNCTION(uart0), UNIPHIER_PINMUX_FUNCTION(uart1), UNIPHIER_PINMUX_FUNCTION(uart2), diff --git a/drivers/pinctrl/uniphier/pinctrl-ph1-sld8.c b/drivers/pinctrl/uniphier/pinctrl-ph1-sld8.c index 7e9dae5..37bfd3f 100644 --- a/drivers/pinctrl/uniphier/pinctrl-ph1-sld8.c +++ b/drivers/pinctrl/uniphier/pinctrl-ph1-sld8.c @@ -450,6 +450,8 @@ static const unsigned nand_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; static const unsigned nand_cs1_pins[] = {22, 23}; static const unsigned nand_cs1_muxvals[] = {0, 0}; +static const unsigned sd_pins[] = {32, 33, 34, 35, 36, 37, 38, 39, 40}; +static const unsigned sd_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0}; static const unsigned uart0_pins[] = {70, 71}; static const unsigned uart0_muxvals[] = {3, 3}; static const unsigned uart1_pins[] = {114, 115}; @@ -536,6 +538,7 @@ static const struct uniphier_pinctrl_group ph1_sld8_groups[] = { UNIPHIER_PINCTRL_GROUP(i2c3), UNIPHIER_PINCTRL_GROUP(nand), UNIPHIER_PINCTRL_GROUP(nand_cs1), + UNIPHIER_PINCTRL_GROUP(sd), UNIPHIER_PINCTRL_GROUP(uart0), UNIPHIER_PINCTRL_GROUP(uart1), UNIPHIER_PINCTRL_GROUP(uart2), @@ -684,6 +687,7 @@ static const char * const i2c1_groups[] = {"i2c1"}; static const char * const i2c2_groups[] = {"i2c2"}; static const char * const i2c3_groups[] = {"i2c3"}; static const char * const nand_groups[] = {"nand", "nand_cs1"}; +static const char * const sd_groups[] = {"sd"}; static const char * const uart0_groups[] = {"uart0"}; static const char * const uart1_groups[] = {"uart1"}; static const char * const uart2_groups[] = {"uart2"}; @@ -739,6 +743,7 @@ static const struct uniphier_pinmux_function ph1_sld8_functions[] = { UNIPHIER_PINMUX_FUNCTION(i2c2), UNIPHIER_PINMUX_FUNCTION(i2c3), UNIPHIER_PINMUX_FUNCTION(nand), + UNIPHIER_PINMUX_FUNCTION(sd), UNIPHIER_PINMUX_FUNCTION(uart0), UNIPHIER_PINMUX_FUNCTION(uart1), UNIPHIER_PINMUX_FUNCTION(uart2), diff --git a/drivers/pinctrl/uniphier/pinctrl-proxstream2.c b/drivers/pinctrl/uniphier/pinctrl-proxstream2.c index 3f036e2..bc00d75 100644 --- a/drivers/pinctrl/uniphier/pinctrl-proxstream2.c +++ b/drivers/pinctrl/uniphier/pinctrl-proxstream2.c @@ -751,6 +751,8 @@ static const unsigned nand_muxvals[] = {8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8}; static const unsigned nand_cs1_pins[] = {37, 38}; static const unsigned nand_cs1_muxvals[] = {8, 8}; +static const unsigned sd_pins[] = {47, 48, 49, 50, 51, 52, 53, 54, 55}; +static const unsigned sd_muxvals[] = {8, 8, 8, 8, 8, 8, 8, 8, 8}; static const unsigned uart0_pins[] = {217, 218}; static const unsigned uart0_muxvals[] = {8, 8}; static const unsigned uart0b_pins[] = {179, 180}; @@ -857,6 +859,7 @@ static const struct uniphier_pinctrl_group proxstream2_groups[] = { UNIPHIER_PINCTRL_GROUP(i2c6), UNIPHIER_PINCTRL_GROUP(nand), UNIPHIER_PINCTRL_GROUP(nand_cs1), + UNIPHIER_PINCTRL_GROUP(sd), UNIPHIER_PINCTRL_GROUP(uart0), UNIPHIER_PINCTRL_GROUP(uart0b), UNIPHIER_PINCTRL_GROUP(uart1), @@ -1128,6 +1131,7 @@ static const char * const i2c3_groups[] = {"i2c3"}; static const char * const i2c5_groups[] = {"i2c5"}; static const char * const i2c6_groups[] = {"i2c6"}; static const char * const nand_groups[] = {"nand", "nand_cs1"}; +static const char * const sd_groups[] = {"sd"}; static const char * const uart0_groups[] = {"uart0", "uart0b"}; static const char * const uart1_groups[] = {"uart1"}; static const char * const uart2_groups[] = {"uart2"}; @@ -1213,6 +1217,7 @@ static const struct uniphier_pinmux_function proxstream2_functions[] = { UNIPHIER_PINMUX_FUNCTION(i2c5), UNIPHIER_PINMUX_FUNCTION(i2c6), UNIPHIER_PINMUX_FUNCTION(nand), + UNIPHIER_PINMUX_FUNCTION(sd), UNIPHIER_PINMUX_FUNCTION(uart0), UNIPHIER_PINMUX_FUNCTION(uart1), UNIPHIER_PINMUX_FUNCTION(uart2), -- cgit v0.10.2 From 4730f33f0d822fd8d0f5d2229793a5df674fed5c Mon Sep 17 00:00:00 2001 From: Vishnu Patekar Date: Tue, 22 Sep 2015 23:38:55 +0800 Subject: pinctrl: sunxi: add allwinner A83T PIO controller support Allwinner A83T soc port controller has 8 ports. It has 3 IRQ banks namely PB, PG, PH. Pinmuxing are different for some pins as compared to sun8i A23 and A33. Signed-off-by: Vishnu Patekar Acked-by: Maxime Ripard Signed-off-by: Linus Walleij diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt index 3c821cd..b321b26 100644 --- a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt @@ -17,6 +17,7 @@ Required properties: "allwinner,sun8i-a23-pinctrl" "allwinner,sun8i-a23-r-pinctrl" "allwinner,sun8i-a33-pinctrl" + "allwinner,sun8i-a83t-pinctrl" - reg: Should contain the register physical address and length for the pin controller. diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig index ae27872..e68fd95 100644 --- a/drivers/pinctrl/sunxi/Kconfig +++ b/drivers/pinctrl/sunxi/Kconfig @@ -42,6 +42,10 @@ config PINCTRL_SUN8I_A33 def_bool MACH_SUN8I select PINCTRL_SUNXI_COMMON +config PINCTRL_SUN8I_A83T + def_bool MACH_SUN8I + select PINCTRL_SUNXI_COMMON + config PINCTRL_SUN8I_A23_R def_bool MACH_SUN8I depends on RESET_CONTROLLER diff --git a/drivers/pinctrl/sunxi/Makefile b/drivers/pinctrl/sunxi/Makefile index 227a121..e080290 100644 --- a/drivers/pinctrl/sunxi/Makefile +++ b/drivers/pinctrl/sunxi/Makefile @@ -12,4 +12,5 @@ obj-$(CONFIG_PINCTRL_SUN7I_A20) += pinctrl-sun7i-a20.o obj-$(CONFIG_PINCTRL_SUN8I_A23) += pinctrl-sun8i-a23.o obj-$(CONFIG_PINCTRL_SUN8I_A23_R) += pinctrl-sun8i-a23-r.o obj-$(CONFIG_PINCTRL_SUN8I_A33) += pinctrl-sun8i-a33.o +obj-$(CONFIG_PINCTRL_SUN8I_A83T) += pinctrl-sun8i-a83t.o obj-$(CONFIG_PINCTRL_SUN9I_A80) += pinctrl-sun9i-a80.o diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-a83t.c b/drivers/pinctrl/sunxi/pinctrl-sun8i-a83t.c new file mode 100644 index 0000000..90b973e --- /dev/null +++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-a83t.c @@ -0,0 +1,603 @@ +/* + * Allwinner a83t SoCs pinctrl driver. + * + * Copyright (C) 2015 Vishnu Patekar + * + * Based on pinctrl-sun8i-a23.c, which is: + * Copyright (C) 2014 Chen-Yu Tsai + * Copyright (C) 2014 Maxime Ripard + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include +#include +#include +#include +#include + +#include "pinctrl-sunxi.h" + +static const struct sunxi_desc_pin sun8i_a83t_pins[] = { + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart2"), /* TX */ + SUNXI_FUNCTION(0x3, "jtag"), /* MS0 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)), /* PB_EINT0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart2"), /* RX */ + SUNXI_FUNCTION(0x3, "jtag"), /* CK0 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)), /* PB_EINT1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart2"), /* RTS */ + SUNXI_FUNCTION(0x3, "jtag"), /* DO0 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)), /* PB_EINT2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart2"), /* CTS */ + SUNXI_FUNCTION(0x3, "jtag"), /* DI0 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)), /* PB_EINT3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s0"), /* LRCK */ + SUNXI_FUNCTION(0x3, "tdm"), /* LRCK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)), /* PB_EINT4 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s0"), /* BCLK */ + SUNXI_FUNCTION(0x3, "tdm"), /* BCLK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)), /* PB_EINT5 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s0"), /* DOUT */ + SUNXI_FUNCTION(0x3, "tdm"), /* DOUT */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)), /* PB_EINT6 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s0"), /* DIN */ + SUNXI_FUNCTION(0x3, "tdm"), /* DIN */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)), /* PB_EINT7 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 8), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s0"), /* MCLK */ + SUNXI_FUNCTION(0x3, "tdm"), /* MCLK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)), /* PB_EINT8 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 9), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart0"), /* TX */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)), /* PB_EINT9 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 10), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart0"), /* RX */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)), /* PB_EINT10 */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* WE */ + SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* ALE */ + SUNXI_FUNCTION(0x3, "spi0")), /* MISO */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* CLE */ + SUNXI_FUNCTION(0x3, "spi0")), /* CLK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* CE1 */ + SUNXI_FUNCTION(0x3, "spi0")), /* CS */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0")), /* CE0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* RE */ + SUNXI_FUNCTION(0x3, "mmc2")), /* CLK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* RB0 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* CMD */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0")), /* RB1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* DQ0 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* DQ1 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* DQ2 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* DQ3 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* DQ4 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D4 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* DQ5 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D5 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand"), /* DQ6 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D6 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand"), /* DQ7 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D7 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand"), /* DQS */ + SUNXI_FUNCTION(0x3, "mmc2")), /* RST */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 17), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand")), /* CE2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 18), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand")), /* CE3 */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */ + SUNXI_FUNCTION(0x4, "gmac")), /* RGMII / MII RXD3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */ + SUNXI_FUNCTION(0x4, "gmac")), /* RGMII / MII RXD2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */ + SUNXI_FUNCTION(0x4, "gmac")), /* RGMII / MII RXD1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */ + SUNXI_FUNCTION(0x4, "gmac")), /* RGMII / MII RXD0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */ + SUNXI_FUNCTION(0x4, "gmac")), /* RGMII / MII RXCK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */ + SUNXI_FUNCTION(0x4, "gmac")), /* RGMII / MII RXDV */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D10 */ + SUNXI_FUNCTION(0x4, "gmac")), /* RGMII / MII RXERR */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D11 */ + SUNXI_FUNCTION(0x4, "gmac")), /* RGMII / MII TXD3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */ + SUNXI_FUNCTION(0x4, "gmac")), /* RGMII / MII TXD2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */ + SUNXI_FUNCTION(0x4, "gmac")), /* RGMII / MII TXD1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D14 */ + SUNXI_FUNCTION(0x4, "gmac")), /* RGMII / MII TXD0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D15 */ + SUNXI_FUNCTION(0x4, "gmac")), /* RGMII-NULL / MII-CRS */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */ + SUNXI_FUNCTION(0x3, "lvds0"), /* VP0 */ + SUNXI_FUNCTION(0x4, "gmac")), /* GTXCK / ETXCK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */ + SUNXI_FUNCTION(0x3, "lvds0"), /* VN0 */ + SUNXI_FUNCTION(0x4, "gmac")), /* GTXCTL / ETXEL */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D20 */ + SUNXI_FUNCTION(0x3, "lvds0"), /* VP1 */ + SUNXI_FUNCTION(0x4, "gmac")), /* GNULL / ETXERR */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D21 */ + SUNXI_FUNCTION(0x3, "lvds0"), /* VN1 */ + SUNXI_FUNCTION(0x4, "gmac")), /* GCLKIN / ECOL */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 22), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D22 */ + SUNXI_FUNCTION(0x3, "lvds0"), /* VP2 */ + SUNXI_FUNCTION(0x4, "gmac")), /* GMDC */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 23), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D23 */ + SUNXI_FUNCTION(0x3, "lvds0"), /* VN2 */ + SUNXI_FUNCTION(0x4, "gmac")), /* GMDIO */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 24), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* CLK */ + SUNXI_FUNCTION(0x3, "lvds0")), /* VPC */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 25), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* DE */ + SUNXI_FUNCTION(0x3, "lvds0")), /* VNC */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 26), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* HSYNC */ + SUNXI_FUNCTION(0x3, "lvds0")), /* VP3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 27), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* VSYNC */ + SUNXI_FUNCTION(0x3, "lvds0")), /* VN3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 28), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "pwm")), /* PWM */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 29), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out")), + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* PCLK */ + SUNXI_FUNCTION(0x4, "ccir")), /* CLK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* MCLK */ + SUNXI_FUNCTION(0x4, "ccir")), /* DE */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* HSYNC */ + SUNXI_FUNCTION(0x4, "ccir")), /* HSYNC */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* VSYNC */ + SUNXI_FUNCTION(0x4, "ccir")), /* VSYNC */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi")), /* D0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi")), /* D1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D2 */ + SUNXI_FUNCTION(0x4, "ccir")), /* D0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D3 */ + SUNXI_FUNCTION(0x4, "ccir")), /* D1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D4 */ + SUNXI_FUNCTION(0x4, "ccir")), /* D2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D5 */ + SUNXI_FUNCTION(0x4, "ccir")), /* D3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D6 */ + SUNXI_FUNCTION(0x3, "uart4"), /* TX */ + SUNXI_FUNCTION(0x4, "ccir")), /* D4 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D7 */ + SUNXI_FUNCTION(0x3, "uart4"), /* RX */ + SUNXI_FUNCTION(0x4, "ccir")), /* D5 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 12), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D8 */ + SUNXI_FUNCTION(0x3, "uart4"), /* RTS */ + SUNXI_FUNCTION(0x4, "ccir")), /* D6 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 13), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D9 */ + SUNXI_FUNCTION(0x3, "uart4"), /* CTS */ + SUNXI_FUNCTION(0x4, "ccir")), /* D7 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 14), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* SCK */ + SUNXI_FUNCTION(0x3, "i2c2")), /* SCK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 15), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* SDA */ + SUNXI_FUNCTION(0x3, "i2c2")), /* SDA */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 16), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 17), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 18), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x3, "owa")), /* DOUT */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 19), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out")), + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */ + SUNXI_FUNCTION(0x3, "jtag")), /* MS1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */ + SUNXI_FUNCTION(0x3, "jtag")), /* DI1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */ + SUNXI_FUNCTION(0x3, "uart0")), /* TX */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */ + SUNXI_FUNCTION(0x3, "jtag")), /* DO1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */ + SUNXI_FUNCTION(0x3, "uart0")), /* RX */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */ + SUNXI_FUNCTION(0x3, "jtag")), /* CK1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out")), + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 0)), /* PG_EINT0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 1)), /* PG_EINT1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc1"), /* D0 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 2)), /* PG_EINT2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc1"), /* D1 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 3)), /* PG_EINT3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc1"), /* D2 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 4)), /* PG_EINT4 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc1"), /* D3 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 5)), /* PG_EINT5 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart1"), /* TX */ + SUNXI_FUNCTION(0x3, "spi1"), /* CS */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 6)), /* PG_EINT6 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart1"), /* RX */ + SUNXI_FUNCTION(0x3, "spi1"), /* CLK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 7)), /* PG_EINT7 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart1"), /* RTS */ + SUNXI_FUNCTION(0x3, "spi1"), /* MOSI */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 8)), /* PG_EINT8 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart1"), /* CTS */ + SUNXI_FUNCTION(0x3, "spi1"), /* MISO */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 9)), /* PG_EINT9 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s1"), /* BCLK */ + SUNXI_FUNCTION(0x3, "uart3"), /* TX */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 10)), /* PG_EINT10 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s1"), /* LRCK */ + SUNXI_FUNCTION(0x3, "uart3"), /* RX */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 11)), /* PG_EINT11 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s1"), /* DOUT */ + SUNXI_FUNCTION(0x3, "uart3"), /* RTS */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 12)), /* PG_EINT12 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 13), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s1"), /* DIN */ + SUNXI_FUNCTION(0x3, "uart3"), /* CTS */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 13)), /* PG_EINT13 */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c0"), /* SCK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 0)), /* PH_EINT0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c0"), /* SDA */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 1)), /* PH_EINT1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c1"), /* SCK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 2)), /* PH_EINT2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c1"), /* SDA */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 3)), /* PH_EINT3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c2"), /* SCK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 4)), /* PH_EINT4 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c2"), /* SDA */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 5)), /* PH_EINT5 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "hdmi"), /* HSCL */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 6)), /* PH_EINT6 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "hdmi"), /* HSDA */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 7)), /* PH_EINT7 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 8), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "hdmi"), /* HCEC */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 8)), /* PH_EINT8 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 9), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 9)), /* PH_EINT9 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 10), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 10)), /* PH_EINT10 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 11), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 1)), /* PH_EINT11 */ +}; + +static const struct sunxi_pinctrl_desc sun8i_a83t_pinctrl_data = { + .pins = sun8i_a83t_pins, + .npins = ARRAY_SIZE(sun8i_a83t_pins), + .irq_banks = 3, +}; + +static int sun8i_a83t_pinctrl_probe(struct platform_device *pdev) +{ + return sunxi_pinctrl_init(pdev, + &sun8i_a83t_pinctrl_data); +} + +static const struct of_device_id sun8i_a83t_pinctrl_match[] = { + { .compatible = "allwinner,sun8i-a83t-pinctrl", }, + {} +}; +MODULE_DEVICE_TABLE(of, sun8i_a83t_pinctrl_match); + +static struct platform_driver sun8i_a83t_pinctrl_driver = { + .probe = sun8i_a83t_pinctrl_probe, + .driver = { + .name = "sun8i-a83t-pinctrl", + .of_match_table = sun8i_a83t_pinctrl_match, + }, +}; +module_platform_driver(sun8i_a83t_pinctrl_driver); + +MODULE_AUTHOR("Vishnu Patekar "); +MODULE_DESCRIPTION("Allwinner a83t pinctrl driver"); +MODULE_LICENSE("GPL"); -- cgit v0.10.2 From de4e882f3fbef586304837518c424787bdfca8b8 Mon Sep 17 00:00:00 2001 From: Ludovic Desroches Date: Fri, 25 Sep 2015 11:14:09 +0200 Subject: pinctrl: at91-pio4: add PM stuff Allow GPIOs to be configured as wakeup sources. When going to suspend, disable all GPIO irqs excepting the one configured as wakeup sources. Signed-off-by: Ludovic Desroches Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/pinctrl-at91-pio4.c b/drivers/pinctrl/pinctrl-at91-pio4.c index 6aff632..5e2189f 100644 --- a/drivers/pinctrl/pinctrl-at91-pio4.c +++ b/drivers/pinctrl/pinctrl-at91-pio4.c @@ -16,6 +16,7 @@ #include #include +#include #include #include #include @@ -122,6 +123,8 @@ struct atmel_pioctrl { struct gpio_chip *gpio_chip; struct irq_domain *irq_domain; int *irqs; + unsigned *pm_wakeup_sources; + unsigned *pm_suspend_backup; struct device *dev; struct device_node *node; }; @@ -214,12 +217,35 @@ static void atmel_gpio_irq_unmask(struct irq_data *d) BIT(pin->line)); } +#ifdef CONFIG_PM_SLEEP + +static int atmel_gpio_irq_set_wake(struct irq_data *d, unsigned int on) +{ + struct atmel_pioctrl *atmel_pioctrl = irq_data_get_irq_chip_data(d); + int bank = ATMEL_PIO_BANK(d->hwirq); + int line = ATMEL_PIO_LINE(d->hwirq); + + /* The gpio controller has one interrupt line per bank. */ + irq_set_irq_wake(atmel_pioctrl->irqs[bank], on); + + if (on) + atmel_pioctrl->pm_wakeup_sources[bank] |= BIT(line); + else + atmel_pioctrl->pm_wakeup_sources[bank] &= ~(BIT(line)); + + return 0; +} +#else +#define atmel_gpio_irq_set_wake NULL +#endif /* CONFIG_PM_SLEEP */ + static struct irq_chip atmel_gpio_irq_chip = { .name = "GPIO", .irq_ack = atmel_gpio_irq_ack, .irq_mask = atmel_gpio_irq_mask, .irq_unmask = atmel_gpio_irq_unmask, .irq_set_type = atmel_gpio_irq_set_type, + .irq_set_wake = atmel_gpio_irq_set_wake, }; static void atmel_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) @@ -792,6 +818,43 @@ static struct pinctrl_desc atmel_pinctrl_desc = { .pmxops = &atmel_pmxops, }; +static int atmel_pctrl_suspend(struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + struct atmel_pioctrl *atmel_pioctrl = platform_get_drvdata(pdev); + int i; + + /* + * For each bank, save IMR to restore it later and disable all GPIO + * interrupts excepting the ones marked as wakeup sources. + */ + for (i = 0; i < atmel_pioctrl->nbanks; i++) { + atmel_pioctrl->pm_suspend_backup[i] = + atmel_gpio_read(atmel_pioctrl, i, ATMEL_PIO_IMR); + atmel_gpio_write(atmel_pioctrl, i, ATMEL_PIO_IDR, + ~atmel_pioctrl->pm_wakeup_sources[i]); + } + + return 0; +} + +static int atmel_pctrl_resume(struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + struct atmel_pioctrl *atmel_pioctrl = platform_get_drvdata(pdev); + int i; + + for (i = 0; i < atmel_pioctrl->nbanks; i++) + atmel_gpio_write(atmel_pioctrl, i, ATMEL_PIO_IER, + atmel_pioctrl->pm_suspend_backup[i]); + + return 0; +} + +static const struct dev_pm_ops atmel_pctrl_pm_ops = { + SET_SYSTEM_SLEEP_PM_OPS(atmel_pctrl_suspend, atmel_pctrl_resume) +}; + /* * The number of banks can be different from a SoC to another one. * We can have up to 16 banks. @@ -908,6 +971,18 @@ static int atmel_pinctrl_probe(struct platform_device *pdev) atmel_pioctrl->gpio_chip->dev = dev; atmel_pioctrl->gpio_chip->names = atmel_pioctrl->group_names; + atmel_pioctrl->pm_wakeup_sources = devm_kzalloc(dev, + sizeof(*atmel_pioctrl->pm_wakeup_sources) + * atmel_pioctrl->nbanks, GFP_KERNEL); + if (!atmel_pioctrl->pm_wakeup_sources) + return -ENOMEM; + + atmel_pioctrl->pm_suspend_backup = devm_kzalloc(dev, + sizeof(*atmel_pioctrl->pm_suspend_backup) + * atmel_pioctrl->nbanks, GFP_KERNEL); + if (!atmel_pioctrl->pm_suspend_backup) + return -ENOMEM; + atmel_pioctrl->irqs = devm_kzalloc(dev, sizeof(*atmel_pioctrl->irqs) * atmel_pioctrl->nbanks, GFP_KERNEL); if (!atmel_pioctrl->irqs) @@ -1006,6 +1081,7 @@ static struct platform_driver atmel_pinctrl_driver = { .driver = { .name = "pinctrl-at91-pio4", .of_match_table = atmel_pctrl_of_match, + .pm = &atmel_pctrl_pm_ops, }, .probe = atmel_pinctrl_probe, .remove = atmel_pinctrl_remove, -- cgit v0.10.2 From ee1635180a8437b8ea4ea2233fd3d3ab1ae95a49 Mon Sep 17 00:00:00 2001 From: Robin Gong Date: Thu, 24 Sep 2015 15:53:57 -0500 Subject: pinctrl: freescale: imx: fix system crash if enable two pinctl instances Fix system chrash caused by groups whose number is smaller than the number of groups of the last pinctl instance which is not initialized. iMX7D supports two iomux controllers (iomuxc-lpsr and iomuxc) on probing the second instance (iomuxc) the chrash below occurs. Uncompressing Linux... done, booting the kernel. [ 0.000000] Booting Linux on physical CPU 0x0 [ 0.000000] Linux version 4.2.0-next-20150901-00006-gebfa43c (aalonso@bluefly) [ 0.000000] CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7) [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasin instruction cache [ 0.000000] Machine model: Freescale i.MX7 SabreSD Board [ 0.661012] [<802a6cb0>] (strcmp) from [<802cc80c>] (imx_dt_node_to_map+0x58/0x208) [ 0.668879] [<802cc80c>] (imx_dt_node_to_map) from [<802cbe24>] (pinctrl_dt_to_map+0x174/0x2b0) [ 0.677654] [<802cbe24>] (pinctrl_dt_to_map) from [<802c8f18>] (pinctrl_get+0x100/0x424) [ 0.685878] [<802c8f18>] (pinctrl_get) from [<802c9510>] (pinctrl_register+0x26c/0x480) [ 0.694104] [<802c9510>] (pinctrl_register) from [<802ccf3c>] (imx_pinctrl_probe+0x580/0x6e8) [ 0.702706] [<802ccf3c>] (imx_pinctrl_probe) from [<80351b58>] (platform_drv_probe+0x44/0xa4) [ 0.711455] [<80351b58>] (platform_drv_probe) from [<803503ec>] (driver_probe_device+0x174/0x2b4) [ 0.720405] [<803503ec>] (driver_probe_device) from [<803505fc>] (__driver_attach+0x8c/0x90) [ 0.728982] [<803505fc>] (__driver_attach) from [<8034e930>] (bus_for_each_dev+0x6c/0xa0) [ 0.737381] [<8034e930>] (bus_for_each_dev) from [<8034fb88>] (bus_add_driver+0x148/0x1f0) [ 0.745804] [<8034fb88>] (bus_add_driver) from [<80350c00>] (driver_register+0x78/0xf8) [ 0.753880] [<80350c00>] (driver_register) from [<800097d0>] (do_one_initcall+0x8c/0x1d4) [ 0.762282] [<800097d0>] (do_one_initcall) from [<80987dac>] (kernel_init_freeable+0x144/0x1e4) [ 0.771061] [<80987dac>] (kernel_init_freeable) from [<806d9c7c>] (kernel_init+0x8/0xe8) [ 0.779285] [<806d9c7c>] (kernel_init) from [<8000f628>] (ret_from_fork+0x14/0x2c) [ 0.786981] Code: e3520000 e5e32001 1afffffb e12fff1e (e4d03001) Signed-off-by: Robin Gong Signed-off-by: Adrian Alonso Acked-by: Shawn Guo Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/freescale/pinctrl-imx.c b/drivers/pinctrl/freescale/pinctrl-imx.c index d7b98ba..b9c6deb 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx.c +++ b/drivers/pinctrl/freescale/pinctrl-imx.c @@ -580,7 +580,6 @@ static int imx_pinctrl_parse_functions(struct device_node *np, struct device_node *child; struct imx_pmx_func *func; struct imx_pin_group *grp; - static u32 grp_index; u32 i = 0; dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name); @@ -599,7 +598,7 @@ static int imx_pinctrl_parse_functions(struct device_node *np, for_each_child_of_node(np, child) { func->groups[i] = child->name; - grp = &info->groups[grp_index++]; + grp = &info->groups[info->group_index++]; imx_pinctrl_parse_groups(child, grp, info, i++); } diff --git a/drivers/pinctrl/freescale/pinctrl-imx.h b/drivers/pinctrl/freescale/pinctrl-imx.h index 49e55d3..2a5fe72 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx.h +++ b/drivers/pinctrl/freescale/pinctrl-imx.h @@ -78,6 +78,7 @@ struct imx_pinctrl_soc_info { struct imx_pin_reg *pin_regs; struct imx_pin_group *groups; unsigned int ngroups; + unsigned int group_index; struct imx_pmx_func *functions; unsigned int nfunctions; unsigned int flags; -- cgit v0.10.2 From e7b37a522aa92da5f47106aa07b6c1fc58bfd922 Mon Sep 17 00:00:00 2001 From: Adrian Alonso Date: Fri, 25 Sep 2015 16:05:59 -0500 Subject: pinctrl: freescale: imx: allow mux_reg offset zero Allow mux_reg offset zero to be a valid pin_id, on imx7d mux_conf reg offset is zero for iomuxc-lspr controller Signed-off-by: Adrian Alonso Acked-by: Shawn Guo Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/freescale/pinctrl-imx.c b/drivers/pinctrl/freescale/pinctrl-imx.c index b9c6deb..151d50d 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx.c +++ b/drivers/pinctrl/freescale/pinctrl-imx.c @@ -542,6 +542,9 @@ static int imx_pinctrl_parse_groups(struct device_node *np, struct imx_pin_reg *pin_reg; struct imx_pin *pin = &grp->pins[i]; + if (!(info->flags & ZERO_OFFSET_VALID) && !mux_reg) + mux_reg = -1; + if (info->flags & SHARE_MUX_CONF_REG) { conf_reg = mux_reg; } else { @@ -550,7 +553,7 @@ static int imx_pinctrl_parse_groups(struct device_node *np, conf_reg = -1; } - pin_id = mux_reg ? mux_reg / 4 : conf_reg / 4; + pin_id = (mux_reg != -1) ? mux_reg / 4 : conf_reg / 4; pin_reg = &info->pin_regs[pin_id]; pin->pin = pin_id; grp->pin_ids[i] = pin_id; diff --git a/drivers/pinctrl/freescale/pinctrl-imx.h b/drivers/pinctrl/freescale/pinctrl-imx.h index 2a5fe72..2a592f6 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx.h +++ b/drivers/pinctrl/freescale/pinctrl-imx.h @@ -85,6 +85,7 @@ struct imx_pinctrl_soc_info { }; #define SHARE_MUX_CONF_REG 0x1 +#define ZERO_OFFSET_VALID 0x2 #define NO_MUX 0x0 #define NO_PAD 0x0 -- cgit v0.10.2 From 26d8cde5260b5d0236d50501b6ef1a444774b33b Mon Sep 17 00:00:00 2001 From: Adrian Alonso Date: Fri, 25 Sep 2015 16:06:00 -0500 Subject: pinctrl: freescale: imx: add shared input select reg support - Add shared input select register support - imx7d has two iomux controllers iomuxc and iomuxc-lpsr which share select_input register for daisy chain settings Signed-off-by: Adrian Alonso Acked-by: Shawn Guo Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/freescale/pinctrl-imx.c b/drivers/pinctrl/freescale/pinctrl-imx.c index 151d50d..a5bb939 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx.c +++ b/drivers/pinctrl/freescale/pinctrl-imx.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include #include @@ -39,6 +40,7 @@ struct imx_pinctrl { struct device *dev; struct pinctrl_dev *pctl; void __iomem *base; + void __iomem *input_sel_base; const struct imx_pinctrl_soc_info *info; }; @@ -254,7 +256,12 @@ static int imx_pmx_set(struct pinctrl_dev *pctldev, unsigned selector, * Regular select input register can never be at offset * 0, and we only print register value for regular case. */ - writel(pin->input_val, ipctl->base + pin->input_reg); + if (ipctl->input_sel_base) + writel(pin->input_val, ipctl->input_sel_base + + pin->input_reg); + else + writel(pin->input_val, ipctl->base + + pin->input_reg); dev_dbg(ipctl->dev, "==>select_input: offset 0x%x val 0x%x\n", pin->input_reg, pin->input_val); @@ -685,6 +692,8 @@ static int imx_pinctrl_probe_dt(struct platform_device *pdev, int imx_pinctrl_probe(struct platform_device *pdev, struct imx_pinctrl_soc_info *info) { + struct device_node *dev_np = pdev->dev.of_node; + struct device_node *np; struct imx_pinctrl *ipctl; struct resource *res; int ret, i; @@ -715,6 +724,23 @@ int imx_pinctrl_probe(struct platform_device *pdev, if (IS_ERR(ipctl->base)) return PTR_ERR(ipctl->base); + if (of_property_read_bool(dev_np, "fsl,input-sel")) { + np = of_parse_phandle(dev_np, "fsl,input-sel", 0); + if (np) { + ipctl->input_sel_base = of_iomap(np, 0); + if (IS_ERR(ipctl->input_sel_base)) { + of_node_put(np); + dev_err(&pdev->dev, + "iomuxc input select base address not found\n"); + return PTR_ERR(ipctl->input_sel_base); + } + } else { + dev_err(&pdev->dev, "iomuxc fsl,input-sel property not found\n"); + return -EINVAL; + } + of_node_put(np); + } + imx_pinctrl_desc.name = dev_name(&pdev->dev); imx_pinctrl_desc.pins = info->pins; imx_pinctrl_desc.npins = info->npins; -- cgit v0.10.2 From 978fd1d7265aee0d8be501f416017d029e6977a7 Mon Sep 17 00:00:00 2001 From: Adrian Alonso Date: Wed, 30 Sep 2015 11:11:08 -0500 Subject: pinctrl: freescale: imx7d: support iomux lpsr controller iMX7D has two iomuxc controllers, iomuxc controller similar as previous iMX SoC generation and iomuxc-lpsr which provides low power state rentetion capabilities on gpios that are part of iomuxc-lpsr Add iomuxc-lpsr gpio group id's Signed-off-by: Adrian Alonso Acked-by: Shawn Guo Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/freescale/pinctrl-imx7d.c b/drivers/pinctrl/freescale/pinctrl-imx7d.c index 1fa7530..16dc925 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx7d.c +++ b/drivers/pinctrl/freescale/pinctrl-imx7d.c @@ -174,6 +174,17 @@ enum imx7d_pads { MX7D_PAD_ENET1_COL = 154, }; +enum imx7d_lpsr_pads { + MX7D_PAD_GPIO1_IO00 = 0, + MX7D_PAD_GPIO1_IO01 = 1, + MX7D_PAD_GPIO1_IO02 = 2, + MX7D_PAD_GPIO1_IO03 = 3, + MX7D_PAD_GPIO1_IO04 = 4, + MX7D_PAD_GPIO1_IO05 = 5, + MX7D_PAD_GPIO1_IO06 = 6, + MX7D_PAD_GPIO1_IO07 = 7, +}; + /* Pad names for the pinmux subsystem */ static const struct pinctrl_pin_desc imx7d_pinctrl_pads[] = { IMX_PINCTRL_PIN(MX7D_PAD_RESERVE0), @@ -333,13 +344,32 @@ static const struct pinctrl_pin_desc imx7d_pinctrl_pads[] = { IMX_PINCTRL_PIN(MX7D_PAD_ENET1_COL), }; +/* Pad names for the pinmux subsystem */ +static const struct pinctrl_pin_desc imx7d_lpsr_pinctrl_pads[] = { + IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO00), + IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO01), + IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO02), + IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO03), + IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO04), + IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO05), + IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO06), + IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO07), +}; + static struct imx_pinctrl_soc_info imx7d_pinctrl_info = { .pins = imx7d_pinctrl_pads, .npins = ARRAY_SIZE(imx7d_pinctrl_pads), }; +static struct imx_pinctrl_soc_info imx7d_lpsr_pinctrl_info = { + .pins = imx7d_lpsr_pinctrl_pads, + .npins = ARRAY_SIZE(imx7d_lpsr_pinctrl_pads), + .flags = ZERO_OFFSET_VALID, +}; + static struct of_device_id imx7d_pinctrl_of_match[] = { { .compatible = "fsl,imx7d-iomuxc", .data = &imx7d_pinctrl_info, }, + { .compatible = "fsl,imx7d-iomuxc-lpsr", .data = &imx7d_lpsr_pinctrl_info }, { /* sentinel */ } }; -- cgit v0.10.2 From a169400b506e98bb90a92c7211f4bed751341750 Mon Sep 17 00:00:00 2001 From: Adrian Alonso Date: Wed, 30 Sep 2015 11:11:09 -0500 Subject: pinctrl: freescale: imx: imx7d iomuxc-lpsr devicetree bindings Add iomuxc-lpsr devicetree bindings documentation Provide documentation context as well an example on pheriperals that could use pad from either iomuxc controller supported by iMX7D SoC Signed-off-by: Adrian Alonso Acked-by: Shawn Guo Signed-off-by: Linus Walleij diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt index 8bbf25d..457b2c6 100644 --- a/Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt @@ -1,16 +1,42 @@ * Freescale i.MX7 Dual IOMUX Controller +iMX7D supports two iomuxc controllers, fsl,imx7d-iomuxc controller is similar +as previous iMX SoC generation and fsl,imx7d-iomuxc-lpsr which provides low +power state retention capabilities on gpios that are part of iomuxc-lpsr +(GPIO1_IO7..GPIO1_IO0). While iomuxc-lpsr provides its own set of registers for +mux and pad control settings, it shares the input select register from main +iomuxc controller for daisy chain settings, the fsl,input-sel property extends +fsl,imx-pinctrl driver to support iomuxc-lpsr controller. + +iomuxc_lpsr: iomuxc-lpsr@302c0000 { + compatible = "fsl,imx7d-iomuxc-lpsr"; + reg = <0x302c0000 0x10000>; + fsl,input-sel = <&iomuxc>; +}; + +iomuxc: iomuxc@30330000 { + compatible = "fsl,imx7d-iomuxc"; + reg = <0x30330000 0x10000>; +}; + +Pheriparials using pads from iomuxc-lpsr support low state retention power +state, under LPSR mode GPIO's state of pads are retain. + Please refer to fsl,imx-pinctrl.txt in this directory for common binding part and usage. Required properties: -- compatible: "fsl,imx7d-iomuxc" +- compatible: "fsl,imx7d-iomuxc" for main IOMUXC controller, or + "fsl,imx7d-iomuxc-lpsr" for Low Power State Retention IOMUXC controller. - fsl,pins: each entry consists of 6 integers and represents the mux and config setting for one pin. The first 5 integers are specified using a PIN_FUNC_ID macro, which can be found in imx7d-pinfunc.h under device tree source folder. The last integer CONFIG is the pad setting value like pull-up on this pin. Please refer to i.MX7 Dual Reference Manual for detailed CONFIG settings. +- fsl,input-sel: required property for iomuxc-lpsr controller, this property is + a phandle for main iomuxc controller which shares the input select register for + daisy chain settings. CONFIG bits definition: PAD_CTL_PUS_100K_DOWN (0 << 5) @@ -25,3 +51,38 @@ PAD_CTL_DSE_X1 (0 << 0) PAD_CTL_DSE_X2 (1 << 0) PAD_CTL_DSE_X3 (2 << 0) PAD_CTL_DSE_X4 (3 << 0) + +Examples: +While iomuxc-lpsr is intended to be used by dedicated peripherals to take +advantages of LPSR power mode, is also possible that an IP to use pads from +any of the iomux controllers. For example the I2C1 IP can use SCL pad from +iomuxc-lpsr controller and SDA pad from iomuxc controller as: + +i2c1: i2c@30a20000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1_1 &pinctrl_i2c1_2>; + status = "okay"; +}; + +iomuxc-lpsr@302c0000 { + compatible = "fsl,imx7d-iomuxc-lpsr"; + reg = <0x302c0000 0x10000>; + fsl,input-sel = <&iomuxc>; + + pinctrl_i2c1_1: i2c1grp-1 { + fsl,pins = < + MX7D_PAD_GPIO1_IO04__I2C1_SCL 0x4000007f + >; + }; +}; + +iomuxc@30330000 { + compatible = "fsl,imx7d-iomuxc"; + reg = <0x30330000 0x10000>; + + pinctrl_i2c1_2: i2c1grp-2 { + fsl,pins = < + MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f + >; + }; +}; -- cgit v0.10.2 From 3fd550c6b3cb364a0d3f0e4abf64618b998dc6b4 Mon Sep 17 00:00:00 2001 From: Ludovic Desroches Date: Mon, 28 Sep 2015 11:41:12 +0200 Subject: pinctrl: at91-pio4: use irq_set_handler_locked Use irq_set_handler_locked() as it avoids a redundant lookup of the irq descriptor. Signed-off-by: Ludovic Desroches Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/pinctrl-at91-pio4.c b/drivers/pinctrl/pinctrl-at91-pio4.c index 5e2189f..1f1a64e 100644 --- a/drivers/pinctrl/pinctrl-at91-pio4.c +++ b/drivers/pinctrl/pinctrl-at91-pio4.c @@ -170,23 +170,23 @@ static int atmel_gpio_irq_set_type(struct irq_data *d, unsigned type) switch (type) { case IRQ_TYPE_EDGE_RISING: - __irq_set_handler_locked(d->irq, handle_edge_irq); + irq_set_handler_locked(d, handle_edge_irq); reg |= ATMEL_PIO_CFGR_EVTSEL_RISING; break; case IRQ_TYPE_EDGE_FALLING: - __irq_set_handler_locked(d->irq, handle_edge_irq); + irq_set_handler_locked(d, handle_edge_irq); reg |= ATMEL_PIO_CFGR_EVTSEL_FALLING; break; case IRQ_TYPE_EDGE_BOTH: - __irq_set_handler_locked(d->irq, handle_edge_irq); + irq_set_handler_locked(d, handle_edge_irq); reg |= ATMEL_PIO_CFGR_EVTSEL_BOTH; break; case IRQ_TYPE_LEVEL_LOW: - __irq_set_handler_locked(d->irq, handle_level_irq); + irq_set_handler_locked(d, handle_level_irq); reg |= ATMEL_PIO_CFGR_EVTSEL_LOW; break; case IRQ_TYPE_LEVEL_HIGH: - __irq_set_handler_locked(d->irq, handle_level_irq); + irq_set_handler_locked(d, handle_level_irq); reg |= ATMEL_PIO_CFGR_EVTSEL_HIGH; break; case IRQ_TYPE_NONE: -- cgit v0.10.2 From 89092fb0701d3b4070ade6d0aa04640720f52fbd Mon Sep 17 00:00:00 2001 From: Ludovic Desroches Date: Mon, 28 Sep 2015 11:41:13 +0200 Subject: pinctrl: at91-pio4: irq argument as been removed from irq flow handlers Irq argument as been removed from irq flow handlers so use the irq descriptor to retrieve data we need. Signed-off-by: Ludovic Desroches Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/pinctrl-at91-pio4.c b/drivers/pinctrl/pinctrl-at91-pio4.c index 1f1a64e..33edd07 100644 --- a/drivers/pinctrl/pinctrl-at91-pio4.c +++ b/drivers/pinctrl/pinctrl-at91-pio4.c @@ -248,9 +248,10 @@ static struct irq_chip atmel_gpio_irq_chip = { .irq_set_wake = atmel_gpio_irq_set_wake, }; -static void atmel_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) +static void atmel_gpio_irq_handler(struct irq_desc *desc) { - struct atmel_pioctrl *atmel_pioctrl = irq_get_handler_data(irq); + unsigned int irq = irq_desc_get_irq(desc); + struct atmel_pioctrl *atmel_pioctrl = irq_desc_get_handler_data(desc); struct irq_chip *chip = irq_desc_get_chip(desc); unsigned long isr; int n, bank = -1; -- cgit v0.10.2 From 3c4b23dd71ea6f68be9731b68877fbc05f4fb693 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Wed, 30 Sep 2015 21:07:17 +0900 Subject: pinctrl: pinconf-generic: sort pin configuration params alphabetically Currently, the dt_params array in drivers/pinctrl/pinconf-generic.c is not sorted in the same order as the enum pin_config_param in include/linux/pinctrl/pinconf-generic.h. Sort enum pin_config_param, conf_items, dt_params, alphabetically for consistency. Signed-off-by: Masahiro Yamada Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/pinconf-generic.c b/drivers/pinctrl/pinconf-generic.c index e63ad9f..a88a559 100644 --- a/drivers/pinctrl/pinconf-generic.c +++ b/drivers/pinctrl/pinconf-generic.c @@ -28,25 +28,25 @@ #ifdef CONFIG_DEBUG_FS static const struct pin_config_item conf_items[] = { + PCONFDUMP(PIN_CONFIG_BIAS_BUS_HOLD, "input bias bus hold", NULL, false), PCONFDUMP(PIN_CONFIG_BIAS_DISABLE, "input bias disabled", NULL, false), PCONFDUMP(PIN_CONFIG_BIAS_HIGH_IMPEDANCE, "input bias high impedance", NULL, false), - PCONFDUMP(PIN_CONFIG_BIAS_BUS_HOLD, "input bias bus hold", NULL, false), - PCONFDUMP(PIN_CONFIG_BIAS_PULL_UP, "input bias pull up", NULL, false), PCONFDUMP(PIN_CONFIG_BIAS_PULL_DOWN, "input bias pull down", NULL, false), PCONFDUMP(PIN_CONFIG_BIAS_PULL_PIN_DEFAULT, "input bias pull to pin specific state", NULL, false), - PCONFDUMP(PIN_CONFIG_DRIVE_PUSH_PULL, "output drive push pull", NULL, false), + PCONFDUMP(PIN_CONFIG_BIAS_PULL_UP, "input bias pull up", NULL, false), PCONFDUMP(PIN_CONFIG_DRIVE_OPEN_DRAIN, "output drive open drain", NULL, false), PCONFDUMP(PIN_CONFIG_DRIVE_OPEN_SOURCE, "output drive open source", NULL, false), + PCONFDUMP(PIN_CONFIG_DRIVE_PUSH_PULL, "output drive push pull", NULL, false), PCONFDUMP(PIN_CONFIG_DRIVE_STRENGTH, "output drive strength", "mA", true), + PCONFDUMP(PIN_CONFIG_INPUT_DEBOUNCE, "input debounce", "usec", true), PCONFDUMP(PIN_CONFIG_INPUT_ENABLE, "input enabled", NULL, false), - PCONFDUMP(PIN_CONFIG_INPUT_SCHMITT_ENABLE, "input schmitt enabled", NULL, false), PCONFDUMP(PIN_CONFIG_INPUT_SCHMITT, "input schmitt trigger", NULL, false), - PCONFDUMP(PIN_CONFIG_INPUT_DEBOUNCE, "input debounce", "usec", true), - PCONFDUMP(PIN_CONFIG_POWER_SOURCE, "pin power source", "selector", true), - PCONFDUMP(PIN_CONFIG_SLEW_RATE, "slew rate", NULL, true), + PCONFDUMP(PIN_CONFIG_INPUT_SCHMITT_ENABLE, "input schmitt enabled", NULL, false), PCONFDUMP(PIN_CONFIG_LOW_POWER_MODE, "pin low power", "mode", true), PCONFDUMP(PIN_CONFIG_OUTPUT, "pin output", "level", true), + PCONFDUMP(PIN_CONFIG_POWER_SOURCE, "pin power source", "selector", true), + PCONFDUMP(PIN_CONFIG_SLEW_RATE, "slew rate", NULL, true), }; static void pinconf_generic_dump_one(struct pinctrl_dev *pctldev, @@ -150,27 +150,27 @@ EXPORT_SYMBOL_GPL(pinconf_generic_dump_config); #ifdef CONFIG_OF static const struct pinconf_generic_params dt_params[] = { + { "bias-bus-hold", PIN_CONFIG_BIAS_BUS_HOLD, 0 }, { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 }, { "bias-high-impedance", PIN_CONFIG_BIAS_HIGH_IMPEDANCE, 0 }, - { "bias-bus-hold", PIN_CONFIG_BIAS_BUS_HOLD, 0 }, { "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 1 }, - { "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN, 1 }, { "bias-pull-pin-default", PIN_CONFIG_BIAS_PULL_PIN_DEFAULT, 1 }, - { "drive-push-pull", PIN_CONFIG_DRIVE_PUSH_PULL, 0 }, + { "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN, 1 }, { "drive-open-drain", PIN_CONFIG_DRIVE_OPEN_DRAIN, 0 }, { "drive-open-source", PIN_CONFIG_DRIVE_OPEN_SOURCE, 0 }, + { "drive-push-pull", PIN_CONFIG_DRIVE_PUSH_PULL, 0 }, { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 0 }, - { "input-enable", PIN_CONFIG_INPUT_ENABLE, 1 }, + { "input-debounce", PIN_CONFIG_INPUT_DEBOUNCE, 0 }, { "input-disable", PIN_CONFIG_INPUT_ENABLE, 0 }, - { "input-schmitt-enable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 1 }, + { "input-enable", PIN_CONFIG_INPUT_ENABLE, 1 }, { "input-schmitt-disable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 0 }, - { "input-debounce", PIN_CONFIG_INPUT_DEBOUNCE, 0 }, - { "power-source", PIN_CONFIG_POWER_SOURCE, 0 }, - { "low-power-enable", PIN_CONFIG_LOW_POWER_MODE, 1 }, + { "input-schmitt-enable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 1 }, { "low-power-disable", PIN_CONFIG_LOW_POWER_MODE, 0 }, - { "output-low", PIN_CONFIG_OUTPUT, 0, }, + { "low-power-enable", PIN_CONFIG_LOW_POWER_MODE, 1 }, { "output-high", PIN_CONFIG_OUTPUT, 1, }, - { "slew-rate", PIN_CONFIG_SLEW_RATE, 0}, + { "output-low", PIN_CONFIG_OUTPUT, 0, }, + { "power-source", PIN_CONFIG_POWER_SOURCE, 0 }, + { "slew-rate", PIN_CONFIG_SLEW_RATE, 0 }, }; /** diff --git a/include/linux/pinctrl/pinconf-generic.h b/include/linux/pinctrl/pinconf-generic.h index fe65962..d921afd 100644 --- a/include/linux/pinctrl/pinconf-generic.h +++ b/include/linux/pinctrl/pinconf-generic.h @@ -20,6 +20,11 @@ /** * enum pin_config_param - possible pin configuration parameters + * @PIN_CONFIG_BIAS_BUS_HOLD: the pin will be set to weakly latch so that it + * weakly drives the last value on a tristate bus, also known as a "bus + * holder", "bus keeper" or "repeater". This allows another device on the + * bus to change the value by driving the bus high or low and switching to + * tristate. The argument is ignored. * @PIN_CONFIG_BIAS_DISABLE: disable any pin bias on the pin, a * transition from say pull-up to pull-down implies that you disable * pull-up in the process, this setting disables all biasing. @@ -29,14 +34,6 @@ * if for example some other pin is going to drive the signal connected * to it for a while. Pins used for input are usually always high * impedance. - * @PIN_CONFIG_BIAS_BUS_HOLD: the pin will be set to weakly latch so that it - * weakly drives the last value on a tristate bus, also known as a "bus - * holder", "bus keeper" or "repeater". This allows another device on the - * bus to change the value by driving the bus high or low and switching to - * tristate. The argument is ignored. - * @PIN_CONFIG_BIAS_PULL_UP: the pin will be pulled up (usually with high - * impedance to VDD). If the argument is != 0 pull-up is enabled, - * if it is 0, pull-up is total, i.e. the pin is connected to VDD. * @PIN_CONFIG_BIAS_PULL_DOWN: the pin will be pulled down (usually with high * impedance to GROUND). If the argument is != 0 pull-down is enabled, * if it is 0, pull-down is total, i.e. the pin is connected to GROUND. @@ -48,10 +45,9 @@ * If the argument is != 0 pull up/down is enabled, if it is 0, the * configuration is ignored. The proper way to disable it is to use * @PIN_CONFIG_BIAS_DISABLE. - * @PIN_CONFIG_DRIVE_PUSH_PULL: the pin will be driven actively high and - * low, this is the most typical case and is typically achieved with two - * active transistors on the output. Setting this config will enable - * push-pull mode, the argument is ignored. + * @PIN_CONFIG_BIAS_PULL_UP: the pin will be pulled up (usually with high + * impedance to VDD). If the argument is != 0 pull-up is enabled, + * if it is 0, pull-up is total, i.e. the pin is connected to VDD. * @PIN_CONFIG_DRIVE_OPEN_DRAIN: the pin will be driven with open drain (open * collector) which means it is usually wired with other output ports * which are then pulled up with an external resistor. Setting this @@ -59,28 +55,26 @@ * @PIN_CONFIG_DRIVE_OPEN_SOURCE: the pin will be driven with open source * (open emitter). Setting this config will enable open source mode, the * argument is ignored. + * @PIN_CONFIG_DRIVE_PUSH_PULL: the pin will be driven actively high and + * low, this is the most typical case and is typically achieved with two + * active transistors on the output. Setting this config will enable + * push-pull mode, the argument is ignored. * @PIN_CONFIG_DRIVE_STRENGTH: the pin will sink or source at most the current * passed as argument. The argument is in mA. + * @PIN_CONFIG_INPUT_DEBOUNCE: this will configure the pin to debounce mode, + * which means it will wait for signals to settle when reading inputs. The + * argument gives the debounce time in usecs. Setting the + * argument to zero turns debouncing off. * @PIN_CONFIG_INPUT_ENABLE: enable the pin's input. Note that this does not * affect the pin's ability to drive output. 1 enables input, 0 disables * input. - * @PIN_CONFIG_INPUT_SCHMITT_ENABLE: control schmitt-trigger mode on the pin. - * If the argument != 0, schmitt-trigger mode is enabled. If it's 0, - * schmitt-trigger mode is disabled. * @PIN_CONFIG_INPUT_SCHMITT: this will configure an input pin to run in * schmitt-trigger mode. If the schmitt-trigger has adjustable hysteresis, * the threshold value is given on a custom format as argument when * setting pins to this mode. - * @PIN_CONFIG_INPUT_DEBOUNCE: this will configure the pin to debounce mode, - * which means it will wait for signals to settle when reading inputs. The - * argument gives the debounce time in usecs. Setting the - * argument to zero turns debouncing off. - * @PIN_CONFIG_POWER_SOURCE: if the pin can select between different power - * supplies, the argument to this parameter (on a custom format) tells - * the driver which alternative power source to use. - * @PIN_CONFIG_SLEW_RATE: if the pin can select slew rate, the argument to - * this parameter (on a custom format) tells the driver which alternative - * slew rate to use. + * @PIN_CONFIG_INPUT_SCHMITT_ENABLE: control schmitt-trigger mode on the pin. + * If the argument != 0, schmitt-trigger mode is enabled. If it's 0, + * schmitt-trigger mode is disabled. * @PIN_CONFIG_LOW_POWER_MODE: this will configure the pin for low power * operation, if several modes of operation are supported these can be * passed in the argument on a custom form, else just use argument 1 @@ -89,29 +83,35 @@ * 1 to indicate high level, argument 0 to indicate low level. (Please * see Documentation/pinctrl.txt, section "GPIO mode pitfalls" for a * discussion around this parameter.) + * @PIN_CONFIG_POWER_SOURCE: if the pin can select between different power + * supplies, the argument to this parameter (on a custom format) tells + * the driver which alternative power source to use. + * @PIN_CONFIG_SLEW_RATE: if the pin can select slew rate, the argument to + * this parameter (on a custom format) tells the driver which alternative + * slew rate to use. * @PIN_CONFIG_END: this is the last enumerator for pin configurations, if * you need to pass in custom configurations to the pin controller, use * PIN_CONFIG_END+1 as the base offset. */ enum pin_config_param { + PIN_CONFIG_BIAS_BUS_HOLD, PIN_CONFIG_BIAS_DISABLE, PIN_CONFIG_BIAS_HIGH_IMPEDANCE, - PIN_CONFIG_BIAS_BUS_HOLD, - PIN_CONFIG_BIAS_PULL_UP, PIN_CONFIG_BIAS_PULL_DOWN, PIN_CONFIG_BIAS_PULL_PIN_DEFAULT, - PIN_CONFIG_DRIVE_PUSH_PULL, + PIN_CONFIG_BIAS_PULL_UP, PIN_CONFIG_DRIVE_OPEN_DRAIN, PIN_CONFIG_DRIVE_OPEN_SOURCE, + PIN_CONFIG_DRIVE_PUSH_PULL, PIN_CONFIG_DRIVE_STRENGTH, + PIN_CONFIG_INPUT_DEBOUNCE, PIN_CONFIG_INPUT_ENABLE, - PIN_CONFIG_INPUT_SCHMITT_ENABLE, PIN_CONFIG_INPUT_SCHMITT, - PIN_CONFIG_INPUT_DEBOUNCE, - PIN_CONFIG_POWER_SOURCE, - PIN_CONFIG_SLEW_RATE, + PIN_CONFIG_INPUT_SCHMITT_ENABLE, PIN_CONFIG_LOW_POWER_MODE, PIN_CONFIG_OUTPUT, + PIN_CONFIG_POWER_SOURCE, + PIN_CONFIG_SLEW_RATE, PIN_CONFIG_END = 0x7FFF, }; -- cgit v0.10.2 From 69c308e2bcc303ab3eebb9b554de598dd4597b75 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Wed, 30 Sep 2015 21:07:18 +0900 Subject: pinctrl: pinconf-generic: add "input-schmitt" DT property PIN_CONFIG_INPUT_SCHMITT is defined in enum_pin_config_param, but the corresponding DT property is missing. Signed-off-by: Masahiro Yamada Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/pinconf-generic.c b/drivers/pinctrl/pinconf-generic.c index a88a559..099a344 100644 --- a/drivers/pinctrl/pinconf-generic.c +++ b/drivers/pinctrl/pinconf-generic.c @@ -163,6 +163,7 @@ static const struct pinconf_generic_params dt_params[] = { { "input-debounce", PIN_CONFIG_INPUT_DEBOUNCE, 0 }, { "input-disable", PIN_CONFIG_INPUT_ENABLE, 0 }, { "input-enable", PIN_CONFIG_INPUT_ENABLE, 1 }, + { "input-schmitt", PIN_CONFIG_INPUT_SCHMITT, 0 }, { "input-schmitt-disable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 0 }, { "input-schmitt-enable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 1 }, { "low-power-disable", PIN_CONFIG_LOW_POWER_MODE, 0 }, -- cgit v0.10.2 From d5c79fcb193ff825e5d5759cdbbb4a16385fb08f Mon Sep 17 00:00:00 2001 From: Jisheng Zhang Date: Fri, 16 Oct 2015 15:37:06 +0800 Subject: pinctrl: berlin: introduce berlin_pinctrl_probe_regmap() This is to prepare for the next berlin4ct support, where we won't use simple-mfd any more. Signed-off-by: Jisheng Zhang Acked-by: Sebastian Hesselbarth Acked-by: Antoine Tenart Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/berlin/berlin.c b/drivers/pinctrl/berlin/berlin.c index f495806..898afa4 100644 --- a/drivers/pinctrl/berlin/berlin.c +++ b/drivers/pinctrl/berlin/berlin.c @@ -292,20 +292,14 @@ static struct pinctrl_desc berlin_pctrl_desc = { .owner = THIS_MODULE, }; -int berlin_pinctrl_probe(struct platform_device *pdev, - const struct berlin_pinctrl_desc *desc) +int berlin_pinctrl_probe_regmap(struct platform_device *pdev, + const struct berlin_pinctrl_desc *desc, + struct regmap *regmap) { struct device *dev = &pdev->dev; - struct device_node *parent_np = of_get_parent(dev->of_node); struct berlin_pinctrl *pctrl; - struct regmap *regmap; int ret; - regmap = syscon_node_to_regmap(parent_np); - of_node_put(parent_np); - if (IS_ERR(regmap)) - return PTR_ERR(regmap); - pctrl = devm_kzalloc(dev, sizeof(*pctrl), GFP_KERNEL); if (!pctrl) return -ENOMEM; @@ -330,3 +324,17 @@ int berlin_pinctrl_probe(struct platform_device *pdev, return 0; } + +int berlin_pinctrl_probe(struct platform_device *pdev, + const struct berlin_pinctrl_desc *desc) +{ + struct device *dev = &pdev->dev; + struct device_node *parent_np = of_get_parent(dev->of_node); + struct regmap *regmap = syscon_node_to_regmap(parent_np); + + of_node_put(parent_np); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + return berlin_pinctrl_probe_regmap(pdev, desc, regmap); +} diff --git a/drivers/pinctrl/berlin/berlin.h b/drivers/pinctrl/berlin/berlin.h index e1aa841..dabbd2a 100644 --- a/drivers/pinctrl/berlin/berlin.h +++ b/drivers/pinctrl/berlin/berlin.h @@ -58,4 +58,8 @@ struct berlin_pinctrl_function { int berlin_pinctrl_probe(struct platform_device *pdev, const struct berlin_pinctrl_desc *desc); +int berlin_pinctrl_probe_regmap(struct platform_device *pdev, + const struct berlin_pinctrl_desc *desc, + struct regmap *regmap); + #endif /* __PINCTRL_BERLIN_H */ -- cgit v0.10.2 From 2df26ef7da6f1960622f37c2a7c57d238603f0d6 Mon Sep 17 00:00:00 2001 From: Jisheng Zhang Date: Fri, 16 Oct 2015 15:37:07 +0800 Subject: pinctrl: berlin: Make berlin pinctrl driver visible if COMPILE_TEST=y It is good to allow berlin pinctrl driver to build with COMPILE_TEST, so make the it menu visible when compile-testing. Signed-off-by: Jisheng Zhang Acked-by: Sebastian Hesselbarth Acked-by: Antoine Tenart Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/berlin/Kconfig b/drivers/pinctrl/berlin/Kconfig index b18322b..f7e45c8 100644 --- a/drivers/pinctrl/berlin/Kconfig +++ b/drivers/pinctrl/berlin/Kconfig @@ -1,4 +1,4 @@ -if ARCH_BERLIN +if (ARCH_BERLIN || COMPILE_TEST) config PINCTRL_BERLIN bool -- cgit v0.10.2 From bb3ba9558af081c15df2677e17d31861ee689f7b Mon Sep 17 00:00:00 2001 From: Jisheng Zhang Date: Fri, 16 Oct 2015 15:37:08 +0800 Subject: pinctrl: berlin: add the berlin4ct pinctrl driver Add the pin-controller driver for Marvell Berlin BG4CT SoC, with definition of its groups and functions. This uses the core Berlin pinctrl driver. Signed-off-by: Jisheng Zhang Acked-by: Sebastian Hesselbarth Acked-by: Antoine Tenart Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/berlin/Kconfig b/drivers/pinctrl/berlin/Kconfig index f7e45c8..aaafd56 100644 --- a/drivers/pinctrl/berlin/Kconfig +++ b/drivers/pinctrl/berlin/Kconfig @@ -17,4 +17,9 @@ config PINCTRL_BERLIN_BG2Q bool select PINCTRL_BERLIN +config PINCTRL_BERLIN_BG4CT + bool "Marvell berlin4ct pin controller driver" + depends on OF + select PINCTRL_BERLIN + endif diff --git a/drivers/pinctrl/berlin/Makefile b/drivers/pinctrl/berlin/Makefile index deb0c6b..06f9402 100644 --- a/drivers/pinctrl/berlin/Makefile +++ b/drivers/pinctrl/berlin/Makefile @@ -2,3 +2,4 @@ obj-$(CONFIG_PINCTRL_BERLIN) += berlin.o obj-$(CONFIG_PINCTRL_BERLIN_BG2) += berlin-bg2.o obj-$(CONFIG_PINCTRL_BERLIN_BG2CD) += berlin-bg2cd.o obj-$(CONFIG_PINCTRL_BERLIN_BG2Q) += berlin-bg2q.o +obj-$(CONFIG_PINCTRL_BERLIN_BG4CT) += berlin-bg4ct.o diff --git a/drivers/pinctrl/berlin/berlin-bg4ct.c b/drivers/pinctrl/berlin/berlin-bg4ct.c new file mode 100644 index 0000000..0917204 --- /dev/null +++ b/drivers/pinctrl/berlin/berlin-bg4ct.c @@ -0,0 +1,503 @@ +/* + * Marvell berlin4ct pinctrl driver + * + * Copyright (C) 2015 Marvell Technology Group Ltd. + * + * Author: Jisheng Zhang + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + */ + +#include +#include +#include +#include + +#include "berlin.h" + +static const struct berlin_desc_group berlin4ct_soc_pinctrl_groups[] = { + BERLIN_PINCTRL_GROUP("EMMC_RSTn", 0x0, 0x3, 0x00, + BERLIN_PINCTRL_FUNCTION(0x0, "emmc"), /* RSTn */ + BERLIN_PINCTRL_FUNCTION(0x1, "gpio")), /* GPIO47 */ + BERLIN_PINCTRL_GROUP("NAND_IO0", 0x0, 0x3, 0x03, + BERLIN_PINCTRL_FUNCTION(0x0, "nand"), /* IO0 */ + BERLIN_PINCTRL_FUNCTION(0x1, "rgmii"), /* RXD0 */ + BERLIN_PINCTRL_FUNCTION(0x2, "sd1"), /* CLK */ + BERLIN_PINCTRL_FUNCTION(0x3, "gpio")), /* GPIO0 */ + BERLIN_PINCTRL_GROUP("NAND_IO1", 0x0, 0x3, 0x06, + BERLIN_PINCTRL_FUNCTION(0x0, "nand"), /* IO1 */ + BERLIN_PINCTRL_FUNCTION(0x1, "rgmii"), /* RXD1 */ + BERLIN_PINCTRL_FUNCTION(0x2, "sd1"), /* CDn */ + BERLIN_PINCTRL_FUNCTION(0x3, "gpio")), /* GPIO1 */ + BERLIN_PINCTRL_GROUP("NAND_IO2", 0x0, 0x3, 0x09, + BERLIN_PINCTRL_FUNCTION(0x0, "nand"), /* IO2 */ + BERLIN_PINCTRL_FUNCTION(0x1, "rgmii"), /* RXD2 */ + BERLIN_PINCTRL_FUNCTION(0x2, "sd1"), /* DAT0 */ + BERLIN_PINCTRL_FUNCTION(0x3, "gpio")), /* GPIO2 */ + BERLIN_PINCTRL_GROUP("NAND_IO3", 0x0, 0x3, 0x0c, + BERLIN_PINCTRL_FUNCTION(0x0, "nand"), /* IO3 */ + BERLIN_PINCTRL_FUNCTION(0x1, "rgmii"), /* RXD3 */ + BERLIN_PINCTRL_FUNCTION(0x2, "sd1"), /* DAT1 */ + BERLIN_PINCTRL_FUNCTION(0x3, "gpio")), /* GPIO3 */ + BERLIN_PINCTRL_GROUP("NAND_IO4", 0x0, 0x3, 0x0f, + BERLIN_PINCTRL_FUNCTION(0x0, "nand"), /* IO4 */ + BERLIN_PINCTRL_FUNCTION(0x1, "rgmii"), /* RXC */ + BERLIN_PINCTRL_FUNCTION(0x2, "sd1"), /* DAT2 */ + BERLIN_PINCTRL_FUNCTION(0x3, "gpio")), /* GPIO4 */ + BERLIN_PINCTRL_GROUP("NAND_IO5", 0x0, 0x3, 0x12, + BERLIN_PINCTRL_FUNCTION(0x0, "nand"), /* IO5 */ + BERLIN_PINCTRL_FUNCTION(0x1, "rgmii"), /* RXCTL */ + BERLIN_PINCTRL_FUNCTION(0x2, "sd1"), /* DAT3 */ + BERLIN_PINCTRL_FUNCTION(0x3, "gpio")), /* GPIO5 */ + BERLIN_PINCTRL_GROUP("NAND_IO6", 0x0, 0x3, 0x15, + BERLIN_PINCTRL_FUNCTION(0x0, "nand"), /* IO6 */ + BERLIN_PINCTRL_FUNCTION(0x1, "rgmii"), /* MDC */ + BERLIN_PINCTRL_FUNCTION(0x2, "sd1"), /* CMD */ + BERLIN_PINCTRL_FUNCTION(0x3, "gpio")), /* GPIO6 */ + BERLIN_PINCTRL_GROUP("NAND_IO7", 0x0, 0x3, 0x18, + BERLIN_PINCTRL_FUNCTION(0x0, "nand"), /* IO7 */ + BERLIN_PINCTRL_FUNCTION(0x1, "rgmii"), /* MDIO */ + BERLIN_PINCTRL_FUNCTION(0x2, "sd1"), /* WP */ + BERLIN_PINCTRL_FUNCTION(0x3, "gpio")), /* GPIO7 */ + BERLIN_PINCTRL_GROUP("NAND_ALE", 0x0, 0x3, 0x1b, + BERLIN_PINCTRL_FUNCTION(0x0, "nand"), /* ALE */ + BERLIN_PINCTRL_FUNCTION(0x1, "rgmii"), /* TXD0 */ + BERLIN_PINCTRL_FUNCTION(0x3, "gpio")), /* GPIO8 */ + BERLIN_PINCTRL_GROUP("NAND_CLE", 0x4, 0x3, 0x00, + BERLIN_PINCTRL_FUNCTION(0x0, "nand"), /* CLE */ + BERLIN_PINCTRL_FUNCTION(0x1, "rgmii"), /* TXD1 */ + BERLIN_PINCTRL_FUNCTION(0x3, "gpio")), /* GPIO9 */ + BERLIN_PINCTRL_GROUP("NAND_WEn", 0x4, 0x3, 0x03, + BERLIN_PINCTRL_FUNCTION(0x0, "nand"), /* WEn */ + BERLIN_PINCTRL_FUNCTION(0x1, "rgmii"), /* TXD2 */ + BERLIN_PINCTRL_FUNCTION(0x3, "gpio")), /* GPIO10 */ + BERLIN_PINCTRL_GROUP("NAND_REn", 0x4, 0x3, 0x06, + BERLIN_PINCTRL_FUNCTION(0x0, "nand"), /* REn */ + BERLIN_PINCTRL_FUNCTION(0x1, "rgmii"), /* TXD3 */ + BERLIN_PINCTRL_FUNCTION(0x3, "gpio")), /* GPIO11 */ + BERLIN_PINCTRL_GROUP("NAND_WPn", 0x4, 0x3, 0x09, + BERLIN_PINCTRL_FUNCTION(0x0, "nand"), /* WPn */ + BERLIN_PINCTRL_FUNCTION(0x3, "gpio")), /* GPIO12 */ + BERLIN_PINCTRL_GROUP("NAND_CEn", 0x4, 0x3, 0x0c, + BERLIN_PINCTRL_FUNCTION(0x0, "nand"), /* CEn */ + BERLIN_PINCTRL_FUNCTION(0x1, "rgmii"), /* TXC */ + BERLIN_PINCTRL_FUNCTION(0x3, "gpio")), /* GPIO13 */ + BERLIN_PINCTRL_GROUP("NAND_RDY", 0x4, 0x3, 0x0f, + BERLIN_PINCTRL_FUNCTION(0x0, "nand"), /* RDY */ + BERLIN_PINCTRL_FUNCTION(0x1, "rgmii"), /* TXCTL */ + BERLIN_PINCTRL_FUNCTION(0x3, "gpio")), /* GPIO14 */ + BERLIN_PINCTRL_GROUP("SD0_CLK", 0x4, 0x3, 0x12, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO29 */ + BERLIN_PINCTRL_FUNCTION(0x1, "sd0"), /* CLK*/ + BERLIN_PINCTRL_FUNCTION(0x2, "sts4"), /* CLK */ + BERLIN_PINCTRL_FUNCTION(0x5, "v4g"), /* DBG8 */ + BERLIN_PINCTRL_FUNCTION(0x7, "phy")), /* DBG8 */ + BERLIN_PINCTRL_GROUP("SD0_DAT0", 0x4, 0x3, 0x15, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO30 */ + BERLIN_PINCTRL_FUNCTION(0x1, "sd0"), /* DAT0 */ + BERLIN_PINCTRL_FUNCTION(0x2, "sts4"), /* SOP */ + BERLIN_PINCTRL_FUNCTION(0x5, "v4g"), /* DBG9 */ + BERLIN_PINCTRL_FUNCTION(0x7, "phy")), /* DBG9 */ + BERLIN_PINCTRL_GROUP("SD0_DAT1", 0x4, 0x3, 0x18, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO31 */ + BERLIN_PINCTRL_FUNCTION(0x1, "sd0"), /* DAT1 */ + BERLIN_PINCTRL_FUNCTION(0x2, "sts4"), /* SD */ + BERLIN_PINCTRL_FUNCTION(0x5, "v4g"), /* DBG10 */ + BERLIN_PINCTRL_FUNCTION(0x7, "phy")), /* DBG10 */ + BERLIN_PINCTRL_GROUP("SD0_DAT2", 0x4, 0x3, 0x1b, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO32 */ + BERLIN_PINCTRL_FUNCTION(0x1, "sd0"), /* DAT2 */ + BERLIN_PINCTRL_FUNCTION(0x2, "sts4"), /* VALD */ + BERLIN_PINCTRL_FUNCTION(0x5, "v4g"), /* DBG11 */ + BERLIN_PINCTRL_FUNCTION(0x7, "phy")), /* DBG11 */ + BERLIN_PINCTRL_GROUP("SD0_DAT3", 0x8, 0x3, 0x00, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO33 */ + BERLIN_PINCTRL_FUNCTION(0x1, "sd0"), /* DAT3 */ + BERLIN_PINCTRL_FUNCTION(0x2, "sts5"), /* CLK */ + BERLIN_PINCTRL_FUNCTION(0x5, "v4g"), /* DBG12 */ + BERLIN_PINCTRL_FUNCTION(0x7, "phy")), /* DBG12 */ + BERLIN_PINCTRL_GROUP("SD0_CDn", 0x8, 0x3, 0x03, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO34 */ + BERLIN_PINCTRL_FUNCTION(0x1, "sd0"), /* CDn */ + BERLIN_PINCTRL_FUNCTION(0x2, "sts5"), /* SOP */ + BERLIN_PINCTRL_FUNCTION(0x5, "v4g"), /* DBG13 */ + BERLIN_PINCTRL_FUNCTION(0x7, "phy")), /* DBG13 */ + BERLIN_PINCTRL_GROUP("SD0_CMD", 0x8, 0x3, 0x06, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO35 */ + BERLIN_PINCTRL_FUNCTION(0x1, "sd0"), /* CMD */ + BERLIN_PINCTRL_FUNCTION(0x2, "sts5"), /* SD */ + BERLIN_PINCTRL_FUNCTION(0x5, "v4g"), /* DBG14 */ + BERLIN_PINCTRL_FUNCTION(0x7, "phy")), /* DBG14 */ + BERLIN_PINCTRL_GROUP("SD0_WP", 0x8, 0x3, 0x09, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO36 */ + BERLIN_PINCTRL_FUNCTION(0x1, "sd0"), /* WP */ + BERLIN_PINCTRL_FUNCTION(0x2, "sts5"), /* VALD */ + BERLIN_PINCTRL_FUNCTION(0x5, "v4g"), /* DBG15 */ + BERLIN_PINCTRL_FUNCTION(0x7, "phy")), /* DBG15 */ + BERLIN_PINCTRL_GROUP("STS0_CLK", 0x8, 0x3, 0x0c, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO21 */ + BERLIN_PINCTRL_FUNCTION(0x1, "sts0"), /* CLK */ + BERLIN_PINCTRL_FUNCTION(0x2, "cpupll"), /* CLKO */ + BERLIN_PINCTRL_FUNCTION(0x5, "v4g"), /* DBG0 */ + BERLIN_PINCTRL_FUNCTION(0x7, "phy")), /* DBG0 */ + BERLIN_PINCTRL_GROUP("STS0_SOP", 0x8, 0x3, 0x0f, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO22 */ + BERLIN_PINCTRL_FUNCTION(0x1, "sts0"), /* SOP */ + BERLIN_PINCTRL_FUNCTION(0x2, "syspll"), /* CLKO */ + BERLIN_PINCTRL_FUNCTION(0x5, "v4g"), /* DBG1 */ + BERLIN_PINCTRL_FUNCTION(0x7, "phy")), /* DBG1 */ + BERLIN_PINCTRL_GROUP("STS0_SD", 0x8, 0x3, 0x12, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO23 */ + BERLIN_PINCTRL_FUNCTION(0x1, "sts0"), /* SD */ + BERLIN_PINCTRL_FUNCTION(0x2, "mempll"), /* CLKO */ + BERLIN_PINCTRL_FUNCTION(0x5, "v4g"), /* DBG2 */ + BERLIN_PINCTRL_FUNCTION(0x7, "phy")), /* DBG2 */ + BERLIN_PINCTRL_GROUP("STS0_VALD", 0x8, 0x3, 0x15, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO24 */ + BERLIN_PINCTRL_FUNCTION(0x1, "sts0"), /* VALD */ + BERLIN_PINCTRL_FUNCTION(0x5, "v4g"), /* DBG3 */ + BERLIN_PINCTRL_FUNCTION(0x7, "phy")), /* DBG3 */ + BERLIN_PINCTRL_GROUP("STS1_CLK", 0x8, 0x3, 0x18, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO25 */ + BERLIN_PINCTRL_FUNCTION(0x1, "sts1"), /* CLK */ + BERLIN_PINCTRL_FUNCTION(0x2, "pwm0"), + BERLIN_PINCTRL_FUNCTION(0x5, "v4g"), /* DBG4 */ + BERLIN_PINCTRL_FUNCTION(0x7, "phy")), /* DBG4 */ + BERLIN_PINCTRL_GROUP("STS1_SOP", 0x8, 0x3, 0x1b, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO26 */ + BERLIN_PINCTRL_FUNCTION(0x1, "sts1"), /* SOP */ + BERLIN_PINCTRL_FUNCTION(0x2, "pwm1"), + BERLIN_PINCTRL_FUNCTION(0x5, "v4g"), /* DBG5 */ + BERLIN_PINCTRL_FUNCTION(0x7, "phy")), /* DBG5 */ + BERLIN_PINCTRL_GROUP("STS1_SD", 0xc, 0x3, 0x00, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO27 */ + BERLIN_PINCTRL_FUNCTION(0x1, "sts1"), /* SD */ + BERLIN_PINCTRL_FUNCTION(0x2, "pwm2"), + BERLIN_PINCTRL_FUNCTION(0x5, "v4g"), /* DBG6 */ + BERLIN_PINCTRL_FUNCTION(0x7, "phy")), /* DBG6 */ + BERLIN_PINCTRL_GROUP("STS1_VALD", 0xc, 0x3, 0x03, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO28 */ + BERLIN_PINCTRL_FUNCTION(0x1, "sts1"), /* VALD */ + BERLIN_PINCTRL_FUNCTION(0x2, "pwm3"), + BERLIN_PINCTRL_FUNCTION(0x5, "v4g"), /* DBG7 */ + BERLIN_PINCTRL_FUNCTION(0x7, "phy")), /* DBG7 */ + BERLIN_PINCTRL_GROUP("SCRD0_RST", 0xc, 0x3, 0x06, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO15 */ + BERLIN_PINCTRL_FUNCTION(0x1, "scrd0"), /* RST */ + BERLIN_PINCTRL_FUNCTION(0x3, "sd1a")), /* CLK */ + BERLIN_PINCTRL_GROUP("SCRD0_DCLK", 0xc, 0x3, 0x09, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO16 */ + BERLIN_PINCTRL_FUNCTION(0x1, "scrd0"), /* DCLK */ + BERLIN_PINCTRL_FUNCTION(0x3, "sd1a")), /* CMD */ + BERLIN_PINCTRL_GROUP("SCRD0_GPIO0", 0xc, 0x3, 0x0c, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO17 */ + BERLIN_PINCTRL_FUNCTION(0x1, "scrd0"), /* SCRD0 GPIO0 */ + BERLIN_PINCTRL_FUNCTION(0x2, "sif"), /* DIO */ + BERLIN_PINCTRL_FUNCTION(0x3, "sd1a")), /* DAT0 */ + BERLIN_PINCTRL_GROUP("SCRD0_GPIO1", 0xc, 0x3, 0x0f, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO18 */ + BERLIN_PINCTRL_FUNCTION(0x1, "scrd0"), /* SCRD0 GPIO1 */ + BERLIN_PINCTRL_FUNCTION(0x2, "sif"), /* CLK */ + BERLIN_PINCTRL_FUNCTION(0x3, "sd1a")), /* DAT1 */ + BERLIN_PINCTRL_GROUP("SCRD0_DIO", 0xc, 0x3, 0x12, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO19 */ + BERLIN_PINCTRL_FUNCTION(0x1, "scrd0"), /* DIO */ + BERLIN_PINCTRL_FUNCTION(0x2, "sif"), /* DEN */ + BERLIN_PINCTRL_FUNCTION(0x3, "sd1a")), /* DAT2 */ + BERLIN_PINCTRL_GROUP("SCRD0_CRD_PRES", 0xc, 0x3, 0x15, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO20 */ + BERLIN_PINCTRL_FUNCTION(0x1, "scrd0"), /* crd pres */ + BERLIN_PINCTRL_FUNCTION(0x1, "sd1a")), /* DAT3 */ + BERLIN_PINCTRL_GROUP("SPI1_SS0n", 0xc, 0x3, 0x18, + BERLIN_PINCTRL_FUNCTION(0x0, "spi1"), /* SS0n */ + BERLIN_PINCTRL_FUNCTION(0x1, "gpio"), /* GPIO37 */ + BERLIN_PINCTRL_FUNCTION(0x2, "sts2")), /* CLK */ + BERLIN_PINCTRL_GROUP("SPI1_SS1n", 0xc, 0x3, 0x1b, + BERLIN_PINCTRL_FUNCTION(0x0, "spi1"), /* SS1n */ + BERLIN_PINCTRL_FUNCTION(0x1, "gpio"), /* GPIO38 */ + BERLIN_PINCTRL_FUNCTION(0x2, "sts2"), /* SOP */ + BERLIN_PINCTRL_FUNCTION(0x4, "pwm1")), + BERLIN_PINCTRL_GROUP("SPI1_SS2n", 0x10, 0x3, 0x00, + BERLIN_PINCTRL_FUNCTION(0x0, "spi1"), /* SS2n */ + BERLIN_PINCTRL_FUNCTION(0x1, "gpio"), /* GPIO39 */ + BERLIN_PINCTRL_FUNCTION(0x2, "sts2"), /* SD */ + BERLIN_PINCTRL_FUNCTION(0x4, "pwm0")), + BERLIN_PINCTRL_GROUP("SPI1_SS3n", 0x10, 0x3, 0x03, + BERLIN_PINCTRL_FUNCTION(0x0, "spi1"), /* SS3n */ + BERLIN_PINCTRL_FUNCTION(0x1, "gpio"), /* GPIO40 */ + BERLIN_PINCTRL_FUNCTION(0x2, "sts2")), /* VALD */ + BERLIN_PINCTRL_GROUP("SPI1_SCLK", 0x10, 0x3, 0x06, + BERLIN_PINCTRL_FUNCTION(0x0, "spi1"), /* SCLK */ + BERLIN_PINCTRL_FUNCTION(0x1, "gpio"), /* GPIO41 */ + BERLIN_PINCTRL_FUNCTION(0x2, "sts3")), /* CLK */ + BERLIN_PINCTRL_GROUP("SPI1_SDO", 0x10, 0x3, 0x09, + BERLIN_PINCTRL_FUNCTION(0x0, "spi1"), /* SDO */ + BERLIN_PINCTRL_FUNCTION(0x1, "gpio"), /* GPIO42 */ + BERLIN_PINCTRL_FUNCTION(0x2, "sts3")), /* SOP */ + BERLIN_PINCTRL_GROUP("SPI1_SDI", 0x10, 0x3, 0x0c, + BERLIN_PINCTRL_FUNCTION(0x0, "spi1"), /* SDI */ + BERLIN_PINCTRL_FUNCTION(0x1, "gpio"), /* GPIO43 */ + BERLIN_PINCTRL_FUNCTION(0x2, "sts3")), /* SD */ + BERLIN_PINCTRL_GROUP("USB0_DRV_VBUS", 0x10, 0x3, 0x0f, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO44 */ + BERLIN_PINCTRL_FUNCTION(0x1, "usb0"), /* VBUS */ + BERLIN_PINCTRL_FUNCTION(0x2, "sts3")), /* VALD */ + BERLIN_PINCTRL_GROUP("TW0_SCL", 0x10, 0x3, 0x12, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO45 */ + BERLIN_PINCTRL_FUNCTION(0x1, "tw0")), /* SCL */ + BERLIN_PINCTRL_GROUP("TW0_SDA", 0x10, 0x3, 0x15, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO46 */ + BERLIN_PINCTRL_FUNCTION(0x1, "tw0")), /* SDA */ +}; + +static const struct berlin_desc_group berlin4ct_avio_pinctrl_groups[] = { + BERLIN_PINCTRL_GROUP("TX_EDDC_SCL", 0x0, 0x3, 0x00, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* AVIO GPIO0 */ + BERLIN_PINCTRL_FUNCTION(0x1, "tx_eddc"), /* SCL */ + BERLIN_PINCTRL_FUNCTION(0x2, "tw1")), /* SCL */ + BERLIN_PINCTRL_GROUP("TX_EDDC_SDA", 0x0, 0x3, 0x03, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* AVIO GPIO1 */ + BERLIN_PINCTRL_FUNCTION(0x1, "tx_eddc"), /* SDA */ + BERLIN_PINCTRL_FUNCTION(0x2, "tw1")), /* SDA */ + BERLIN_PINCTRL_GROUP("I2S1_LRCKO", 0x0, 0x3, 0x06, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* AVIO GPIO2 */ + BERLIN_PINCTRL_FUNCTION(0x1, "i2s1"), /* LRCKO */ + BERLIN_PINCTRL_FUNCTION(0x3, "sts6"), /* CLK */ + BERLIN_PINCTRL_FUNCTION(0x4, "adac"), /* DBG0 */ + BERLIN_PINCTRL_FUNCTION(0x6, "sd1b"), /* CLK */ + BERLIN_PINCTRL_FUNCTION(0x7, "avio")), /* DBG0 */ + BERLIN_PINCTRL_GROUP("I2S1_BCLKO", 0x0, 0x3, 0x09, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* AVIO GPIO3 */ + BERLIN_PINCTRL_FUNCTION(0x1, "i2s1"), /* BCLKO */ + BERLIN_PINCTRL_FUNCTION(0x3, "sts6"), /* SOP */ + BERLIN_PINCTRL_FUNCTION(0x4, "adac"), /* DBG1 */ + BERLIN_PINCTRL_FUNCTION(0x6, "sd1b"), /* CMD */ + BERLIN_PINCTRL_FUNCTION(0x7, "avio")), /* DBG1 */ + BERLIN_PINCTRL_GROUP("I2S1_DO", 0x0, 0x3, 0x0c, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* AVIO GPIO4 */ + BERLIN_PINCTRL_FUNCTION(0x1, "i2s1"), /* DO */ + BERLIN_PINCTRL_FUNCTION(0x3, "sts6"), /* SD */ + BERLIN_PINCTRL_FUNCTION(0x4, "adac"), /* DBG2 */ + BERLIN_PINCTRL_FUNCTION(0x6, "sd1b"), /* DAT0 */ + BERLIN_PINCTRL_FUNCTION(0x7, "avio")), /* DBG2 */ + BERLIN_PINCTRL_GROUP("I2S1_MCLK", 0x0, 0x3, 0x0f, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* AVIO GPIO5 */ + BERLIN_PINCTRL_FUNCTION(0x1, "i2s1"), /* MCLK */ + BERLIN_PINCTRL_FUNCTION(0x3, "sts6"), /* VALD */ + BERLIN_PINCTRL_FUNCTION(0x4, "adac_test"), /* MCLK */ + BERLIN_PINCTRL_FUNCTION(0x6, "sd1b"), /* DAT1 */ + BERLIN_PINCTRL_FUNCTION(0x7, "avio")), /* DBG3 */ + BERLIN_PINCTRL_GROUP("SPDIFO", 0x0, 0x3, 0x12, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* AVIO GPIO6 */ + BERLIN_PINCTRL_FUNCTION(0x1, "spdifo"), + BERLIN_PINCTRL_FUNCTION(0x2, "avpll"), /* CLKO */ + BERLIN_PINCTRL_FUNCTION(0x4, "adac")), /* DBG3 */ + BERLIN_PINCTRL_GROUP("I2S2_MCLK", 0x0, 0x3, 0x15, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* AVIO GPIO7 */ + BERLIN_PINCTRL_FUNCTION(0x1, "i2s2"), /* MCLK */ + BERLIN_PINCTRL_FUNCTION(0x4, "hdmi"), /* FBCLK */ + BERLIN_PINCTRL_FUNCTION(0x5, "pdm")), /* CLKO */ + BERLIN_PINCTRL_GROUP("I2S2_LRCKI", 0x0, 0x3, 0x18, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* AVIO GPIO8 */ + BERLIN_PINCTRL_FUNCTION(0x1, "i2s2"), /* LRCKI */ + BERLIN_PINCTRL_FUNCTION(0x2, "pwm0"), + BERLIN_PINCTRL_FUNCTION(0x3, "sts7"), /* CLK */ + BERLIN_PINCTRL_FUNCTION(0x4, "adac_test"), /* LRCK */ + BERLIN_PINCTRL_FUNCTION(0x6, "sd1b")), /* DAT2 */ + BERLIN_PINCTRL_GROUP("I2S2_BCLKI", 0x0, 0x3, 0x1b, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* AVIO GPIO9 */ + BERLIN_PINCTRL_FUNCTION(0x1, "i2s2"), /* BCLKI */ + BERLIN_PINCTRL_FUNCTION(0x2, "pwm1"), + BERLIN_PINCTRL_FUNCTION(0x3, "sts7"), /* SOP */ + BERLIN_PINCTRL_FUNCTION(0x4, "adac_test"), /* BCLK */ + BERLIN_PINCTRL_FUNCTION(0x6, "sd1b")), /* DAT3 */ + BERLIN_PINCTRL_GROUP("I2S2_DI0", 0x4, 0x3, 0x00, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* AVIO GPIO10 */ + BERLIN_PINCTRL_FUNCTION(0x1, "i2s2"), /* DI0 */ + BERLIN_PINCTRL_FUNCTION(0x2, "pwm2"), + BERLIN_PINCTRL_FUNCTION(0x3, "sts7"), /* SD */ + BERLIN_PINCTRL_FUNCTION(0x4, "adac_test"), /* SDIN */ + BERLIN_PINCTRL_FUNCTION(0x5, "pdm"), /* DI0 */ + BERLIN_PINCTRL_FUNCTION(0x6, "sd1b")), /* CDn */ + BERLIN_PINCTRL_GROUP("I2S2_DI1", 0x4, 0x3, 0x03, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* AVIO GPIO11 */ + BERLIN_PINCTRL_FUNCTION(0x1, "i2s2"), /* DI1 */ + BERLIN_PINCTRL_FUNCTION(0x2, "pwm3"), + BERLIN_PINCTRL_FUNCTION(0x3, "sts7"), /* VALD */ + BERLIN_PINCTRL_FUNCTION(0x4, "adac_test"), /* PWMCLK */ + BERLIN_PINCTRL_FUNCTION(0x5, "pdm"), /* DI1 */ + BERLIN_PINCTRL_FUNCTION(0x6, "sd1b")), /* WP */ +}; + +static const struct berlin_desc_group berlin4ct_sysmgr_pinctrl_groups[] = { + BERLIN_PINCTRL_GROUP("SM_TW2_SCL", 0x0, 0x3, 0x00, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* SM GPIO19 */ + BERLIN_PINCTRL_FUNCTION(0x1, "tw2")), /* SCL */ + BERLIN_PINCTRL_GROUP("SM_TW2_SDA", 0x0, 0x3, 0x03, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* SM GPIO20 */ + BERLIN_PINCTRL_FUNCTION(0x1, "tw2")), /* SDA */ + BERLIN_PINCTRL_GROUP("SM_TW3_SCL", 0x0, 0x3, 0x06, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* SM GPIO21 */ + BERLIN_PINCTRL_FUNCTION(0x1, "tw3")), /* SCL */ + BERLIN_PINCTRL_GROUP("SM_TW3_SDA", 0x0, 0x3, 0x09, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* SM GPIO22 */ + BERLIN_PINCTRL_FUNCTION(0x1, "tw3")), /* SDA */ + BERLIN_PINCTRL_GROUP("SM_TMS", 0x0, 0x3, 0x0c, + BERLIN_PINCTRL_FUNCTION(0x0, "jtag"), /* TMS */ + BERLIN_PINCTRL_FUNCTION(0x1, "gpio"), /* SM GPIO0 */ + BERLIN_PINCTRL_FUNCTION(0x2, "pwm0")), + BERLIN_PINCTRL_GROUP("SM_TDI", 0x0, 0x3, 0x0f, + BERLIN_PINCTRL_FUNCTION(0x0, "jtag"), /* TDI */ + BERLIN_PINCTRL_FUNCTION(0x1, "gpio"), /* SM GPIO1 */ + BERLIN_PINCTRL_FUNCTION(0x2, "pwm1")), + BERLIN_PINCTRL_GROUP("SM_TDO", 0x0, 0x3, 0x12, + BERLIN_PINCTRL_FUNCTION(0x0, "jtag"), /* TDO */ + BERLIN_PINCTRL_FUNCTION(0x1, "gpio")), /* SM GPIO2 */ + BERLIN_PINCTRL_GROUP("SM_URT0_TXD", 0x0, 0x3, 0x15, + BERLIN_PINCTRL_FUNCTION(0x0, "uart0"), /* TXD */ + BERLIN_PINCTRL_FUNCTION(0x1, "gpio")), /* SM GPIO3 */ + BERLIN_PINCTRL_GROUP("SM_URT0_RXD", 0x0, 0x3, 0x18, + BERLIN_PINCTRL_FUNCTION(0x0, "uart0"), /* RXD */ + BERLIN_PINCTRL_FUNCTION(0x1, "gpio")), /* SM GPIO4 */ + BERLIN_PINCTRL_GROUP("SM_URT1_TXD", 0x0, 0x3, 0x1b, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* SM GPIO5 */ + BERLIN_PINCTRL_FUNCTION(0x1, "uart1"), /* TXD */ + BERLIN_PINCTRL_FUNCTION(0x2, "eth1"), /* RXCLK */ + BERLIN_PINCTRL_FUNCTION(0x3, "pwm2"), + BERLIN_PINCTRL_FUNCTION(0x4, "timer0"), + BERLIN_PINCTRL_FUNCTION(0x5, "clk_25m")), + BERLIN_PINCTRL_GROUP("SM_URT1_RXD", 0x4, 0x3, 0x00, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* SM GPIO6 */ + BERLIN_PINCTRL_FUNCTION(0x1, "uart1"), /* RXD */ + BERLIN_PINCTRL_FUNCTION(0x3, "pwm3"), + BERLIN_PINCTRL_FUNCTION(0x4, "timer1")), + BERLIN_PINCTRL_GROUP("SM_SPI2_SS0n", 0x4, 0x3, 0x03, + BERLIN_PINCTRL_FUNCTION(0x0, "spi2"), /* SS0 n*/ + BERLIN_PINCTRL_FUNCTION(0x1, "gpio")), /* SM GPIO7 */ + BERLIN_PINCTRL_GROUP("SM_SPI2_SS1n", 0x4, 0x3, 0x06, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* SM GPIO8 */ + BERLIN_PINCTRL_FUNCTION(0x1, "spi2")), /* SS1n */ + BERLIN_PINCTRL_GROUP("SM_SPI2_SS2n", 0x4, 0x3, 0x09, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* SM GPIO9 */ + BERLIN_PINCTRL_FUNCTION(0x1, "spi2"), /* SS2n */ + BERLIN_PINCTRL_FUNCTION(0x2, "eth1"), /* MDC */ + BERLIN_PINCTRL_FUNCTION(0x3, "pwm0"), + BERLIN_PINCTRL_FUNCTION(0x4, "timer0"), + BERLIN_PINCTRL_FUNCTION(0x5, "clk_25m")), + BERLIN_PINCTRL_GROUP("SM_SPI2_SS3n", 0x4, 0x3, 0x0c, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* SM GPIO10 */ + BERLIN_PINCTRL_FUNCTION(0x1, "spi2"), /* SS3n */ + BERLIN_PINCTRL_FUNCTION(0x2, "eth1"), /* MDIO */ + BERLIN_PINCTRL_FUNCTION(0x3, "pwm1"), + BERLIN_PINCTRL_FUNCTION(0x4, "timer1")), + BERLIN_PINCTRL_GROUP("SM_SPI2_SDO", 0x4, 0x3, 0x0f, + BERLIN_PINCTRL_FUNCTION(0x0, "spi2"), /* SDO */ + BERLIN_PINCTRL_FUNCTION(0x1, "gpio")), /* SM GPIO11 */ + BERLIN_PINCTRL_GROUP("SM_SPI2_SDI", 0x4, 0x3, 0x12, + BERLIN_PINCTRL_FUNCTION(0x0, "spi2"), /* SDI */ + BERLIN_PINCTRL_FUNCTION(0x1, "gpio")), /* SM GPIO12 */ + BERLIN_PINCTRL_GROUP("SM_SPI2_SCLK", 0x4, 0x3, 0x15, + BERLIN_PINCTRL_FUNCTION(0x0, "spi2"), /* SCLK */ + BERLIN_PINCTRL_FUNCTION(0x1, "gpio")), /* SM GPIO13 */ + BERLIN_PINCTRL_GROUP("SM_FE_LED0", 0x4, 0x3, 0x18, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* SM GPIO14 */ + BERLIN_PINCTRL_FUNCTION(0x2, "led")), /* LED0 */ + BERLIN_PINCTRL_GROUP("SM_FE_LED1", 0x4, 0x3, 0x1b, + BERLIN_PINCTRL_FUNCTION(0x0, "pwr"), + BERLIN_PINCTRL_FUNCTION(0x1, "gpio"), /* SM GPIO 15 */ + BERLIN_PINCTRL_FUNCTION(0x2, "led")), /* LED1 */ + BERLIN_PINCTRL_GROUP("SM_FE_LED2", 0x8, 0x3, 0x00, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* SM GPIO16 */ + BERLIN_PINCTRL_FUNCTION(0x2, "led")), /* LED2 */ + BERLIN_PINCTRL_GROUP("SM_HDMI_HPD", 0x8, 0x3, 0x03, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* SM GPIO17 */ + BERLIN_PINCTRL_FUNCTION(0x1, "hdmi")), /* HPD */ + BERLIN_PINCTRL_GROUP("SM_HDMI_CEC", 0x8, 0x3, 0x06, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* SM GPIO18 */ + BERLIN_PINCTRL_FUNCTION(0x1, "hdmi")), /* CEC */ +}; + +static const struct berlin_pinctrl_desc berlin4ct_soc_pinctrl_data = { + .groups = berlin4ct_soc_pinctrl_groups, + .ngroups = ARRAY_SIZE(berlin4ct_soc_pinctrl_groups), +}; + +static const struct berlin_pinctrl_desc berlin4ct_avio_pinctrl_data = { + .groups = berlin4ct_avio_pinctrl_groups, + .ngroups = ARRAY_SIZE(berlin4ct_avio_pinctrl_groups), +}; + +static const struct berlin_pinctrl_desc berlin4ct_sysmgr_pinctrl_data = { + .groups = berlin4ct_sysmgr_pinctrl_groups, + .ngroups = ARRAY_SIZE(berlin4ct_sysmgr_pinctrl_groups), +}; + +static const struct of_device_id berlin4ct_pinctrl_match[] = { + { + .compatible = "marvell,berlin4ct-soc-pinctrl", + .data = &berlin4ct_soc_pinctrl_data, + }, + { + .compatible = "marvell,berlin4ct-avio-pinctrl", + .data = &berlin4ct_avio_pinctrl_data, + }, + { + .compatible = "marvell,berlin4ct-system-pinctrl", + .data = &berlin4ct_sysmgr_pinctrl_data, + }, + {} +}; +MODULE_DEVICE_TABLE(of, berlin4ct_pinctrl_match); + +static int berlin4ct_pinctrl_probe(struct platform_device *pdev) +{ + const struct of_device_id *match = + of_match_device(berlin4ct_pinctrl_match, &pdev->dev); + struct regmap_config *rmconfig; + struct regmap *regmap; + struct resource *res; + void __iomem *base; + + rmconfig = devm_kzalloc(&pdev->dev, sizeof(*rmconfig), GFP_KERNEL); + if (!rmconfig) + return -ENOMEM; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(base)) + return PTR_ERR(base); + + rmconfig->reg_bits = 32, + rmconfig->val_bits = 32, + rmconfig->reg_stride = 4, + rmconfig->max_register = resource_size(res); + + regmap = devm_regmap_init_mmio(&pdev->dev, base, rmconfig); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + return berlin_pinctrl_probe_regmap(pdev, match->data, regmap); +} + +static struct platform_driver berlin4ct_pinctrl_driver = { + .probe = berlin4ct_pinctrl_probe, + .driver = { + .name = "berlin4ct-pinctrl", + .of_match_table = berlin4ct_pinctrl_match, + }, +}; +module_platform_driver(berlin4ct_pinctrl_driver); + +MODULE_AUTHOR("Jisheng Zhang "); +MODULE_DESCRIPTION("Marvell berlin4ct pinctrl driver"); +MODULE_LICENSE("GPL"); -- cgit v0.10.2 From c55a7746111144b0fa2c27dd28098f14d4ca79ee Mon Sep 17 00:00:00 2001 From: Jisheng Zhang Date: Fri, 16 Oct 2015 15:37:10 +0800 Subject: pinctrl: dt-binding: document berlin4ct SoC pinctrl Add berlin4ct to existing berlin pinctrl device tree binding. Signed-off-by: Jisheng Zhang Acked-by: Sebastian Hesselbarth Acked-by: Antoine Tenart Signed-off-by: Linus Walleij diff --git a/Documentation/devicetree/bindings/pinctrl/berlin,pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/berlin,pinctrl.txt index a8bb5e2..f8fa28c 100644 --- a/Documentation/devicetree/bindings/pinctrl/berlin,pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/berlin,pinctrl.txt @@ -20,7 +20,10 @@ Required properties: "marvell,berlin2cd-soc-pinctrl", "marvell,berlin2cd-system-pinctrl", "marvell,berlin2q-soc-pinctrl", - "marvell,berlin2q-system-pinctrl" + "marvell,berlin2q-system-pinctrl", + "marvell,berlin4ct-avio-pinctrl", + "marvell,berlin4ct-soc-pinctrl", + "marvell,berlin4ct-system-pinctrl" Required subnode-properties: - groups: a list of strings describing the group names. -- cgit v0.10.2 From d02f997d61b30ef6f89ad2f2dc4d41613c8b8b88 Mon Sep 17 00:00:00 2001 From: Antoine Tenart Date: Tue, 13 Oct 2015 23:31:37 +0200 Subject: pinctrl: berlin: select the pinctrl driver according to the SoC used This patch prepares to remove the pinctrl driver selection from the mach-berlin Kconfig. To do so, bool is replaced by def_bool. Signed-off-by: Antoine Tenart Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/berlin/Kconfig b/drivers/pinctrl/berlin/Kconfig index aaafd56..7117125 100644 --- a/drivers/pinctrl/berlin/Kconfig +++ b/drivers/pinctrl/berlin/Kconfig @@ -6,15 +6,15 @@ config PINCTRL_BERLIN select REGMAP_MMIO config PINCTRL_BERLIN_BG2 - bool + def_bool MACH_BERLIN_BG2 select PINCTRL_BERLIN config PINCTRL_BERLIN_BG2CD - bool + def_bool MACH_BERLIN_BG2CD select PINCTRL_BERLIN config PINCTRL_BERLIN_BG2Q - bool + def_bool MACH_BERLIN_BG2Q select PINCTRL_BERLIN config PINCTRL_BERLIN_BG4CT -- cgit v0.10.2 From 9c160bbd6c298c8b4f76b245e26f78bd4bba3993 Mon Sep 17 00:00:00 2001 From: Antoine Tenart Date: Tue, 13 Oct 2015 23:31:39 +0200 Subject: pinctrl: berlin: add explicit dependency on OF Berlin pinctrl drivers depends on CONFIG_OF. This patch adds this dependency explicitly. Signed-off-by: Antoine Tenart Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/berlin/Kconfig b/drivers/pinctrl/berlin/Kconfig index 7117125..8fe6ad7 100644 --- a/drivers/pinctrl/berlin/Kconfig +++ b/drivers/pinctrl/berlin/Kconfig @@ -7,14 +7,17 @@ config PINCTRL_BERLIN config PINCTRL_BERLIN_BG2 def_bool MACH_BERLIN_BG2 + depends on OF select PINCTRL_BERLIN config PINCTRL_BERLIN_BG2CD def_bool MACH_BERLIN_BG2CD + depends on OF select PINCTRL_BERLIN config PINCTRL_BERLIN_BG2Q def_bool MACH_BERLIN_BG2Q + depends on OF select PINCTRL_BERLIN config PINCTRL_BERLIN_BG4CT -- cgit v0.10.2 From 1d48fb6e4aeec5946574712c512c12a053ce82c0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Antoine=20T=C3=A9nart?= Date: Tue, 13 Oct 2015 23:31:41 +0200 Subject: pinctrl: berlin: fix my family name spelling MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit My family name contained an accent when I submitted the Berlin pinctrl series in the first place. There was an encoding issue when the series was applied. Fix this. Signed-off-by: Antoine Ténart Acked-by: Sebastian Hesselbarth [Je me rendis tous les accents aigus] Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/berlin/berlin-bg2.c b/drivers/pinctrl/berlin/berlin-bg2.c index 274c553..fabe728 100644 --- a/drivers/pinctrl/berlin/berlin-bg2.c +++ b/drivers/pinctrl/berlin/berlin-bg2.c @@ -3,7 +3,7 @@ * * Copyright (C) 2014 Marvell Technology Group Ltd. * - * Antoine Ténart + * Antoine Ténart * * This file is licensed under the terms of the GNU General Public * License version 2. This program is licensed "as is" without any @@ -246,6 +246,6 @@ static struct platform_driver berlin2_pinctrl_driver = { }; module_platform_driver(berlin2_pinctrl_driver); -MODULE_AUTHOR("Antoine Ténart "); +MODULE_AUTHOR("Antoine Ténart "); MODULE_DESCRIPTION("Marvell Berlin BG2 pinctrl driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/pinctrl/berlin/berlin-bg2cd.c b/drivers/pinctrl/berlin/berlin-bg2cd.c index 0cb793a..aff7f6a 100644 --- a/drivers/pinctrl/berlin/berlin-bg2cd.c +++ b/drivers/pinctrl/berlin/berlin-bg2cd.c @@ -3,7 +3,7 @@ * * Copyright (C) 2014 Marvell Technology Group Ltd. * - * Antoine Ténart + * Antoine Ténart * * This file is licensed under the terms of the GNU General Public * License version 2. This program is licensed "as is" without any @@ -189,6 +189,6 @@ static struct platform_driver berlin2cd_pinctrl_driver = { }; module_platform_driver(berlin2cd_pinctrl_driver); -MODULE_AUTHOR("Antoine Ténart "); +MODULE_AUTHOR("Antoine Ténart "); MODULE_DESCRIPTION("Marvell Berlin BG2CD pinctrl driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/pinctrl/berlin/berlin-bg2q.c b/drivers/pinctrl/berlin/berlin-bg2q.c index a466054..cd171ae 100644 --- a/drivers/pinctrl/berlin/berlin-bg2q.c +++ b/drivers/pinctrl/berlin/berlin-bg2q.c @@ -3,7 +3,7 @@ * * Copyright (C) 2014 Marvell Technology Group Ltd. * - * Antoine Ténart + * Antoine Ténart * * This file is licensed under the terms of the GNU General Public * License version 2. This program is licensed "as is" without any @@ -408,6 +408,6 @@ static struct platform_driver berlin2q_pinctrl_driver = { }; module_platform_driver(berlin2q_pinctrl_driver); -MODULE_AUTHOR("Antoine Ténart "); +MODULE_AUTHOR("Antoine Ténart "); MODULE_DESCRIPTION("Marvell Berlin BG2Q pinctrl driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/pinctrl/berlin/berlin.c b/drivers/pinctrl/berlin/berlin.c index 898afa4..46f2b48 100644 --- a/drivers/pinctrl/berlin/berlin.c +++ b/drivers/pinctrl/berlin/berlin.c @@ -3,7 +3,7 @@ * * Copyright (C) 2014 Marvell Technology Group Ltd. * - * Antoine Ténart + * Antoine Ténart * * This file is licensed under the terms of the GNU General Public * License version 2. This program is licensed "as is" without any diff --git a/drivers/pinctrl/berlin/berlin.h b/drivers/pinctrl/berlin/berlin.h index dabbd2a..e9b30f9 100644 --- a/drivers/pinctrl/berlin/berlin.h +++ b/drivers/pinctrl/berlin/berlin.h @@ -3,7 +3,7 @@ * * Copyright (C) 2014 Marvell Technology Group Ltd. * - * Antoine Ténart + * Antoine Ténart * * This file is licensed under the terms of the GNU General Public * License version 2. This program is licensed "as is" without any -- cgit v0.10.2 From 3c6531c7461b80c18284d43b59791c60cd67582f Mon Sep 17 00:00:00 2001 From: Thomas Hebb Date: Tue, 6 Oct 2015 22:56:37 +0200 Subject: pinctrl: berlin: fix BG2CD field widths The previous register layout was incorrect, many of the fields having fewer bits than were needed to represent all their modes. The new layout is taken from the bootloader source of a BG2CD device. Signed-off-by: Thomas Hebb Acked-by: Sebastian Hesselbarth Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/berlin/berlin-bg2cd.c b/drivers/pinctrl/berlin/berlin-bg2cd.c index aff7f6a..ad8c758 100644 --- a/drivers/pinctrl/berlin/berlin-bg2cd.c +++ b/drivers/pinctrl/berlin/berlin-bg2cd.c @@ -19,24 +19,24 @@ static const struct berlin_desc_group berlin2cd_soc_pinctrl_groups[] = { /* G */ - BERLIN_PINCTRL_GROUP("G0", 0x00, 0x1, 0x00, + BERLIN_PINCTRL_GROUP("G0", 0x00, 0x3, 0x00, BERLIN_PINCTRL_FUNCTION(0x0, "jtag"), BERLIN_PINCTRL_FUNCTION(0x1, "gpio"), BERLIN_PINCTRL_FUNCTION(0x2, "led"), BERLIN_PINCTRL_FUNCTION(0x3, "pwm")), - BERLIN_PINCTRL_GROUP("G1", 0x00, 0x2, 0x01, + BERLIN_PINCTRL_GROUP("G1", 0x00, 0x3, 0x03, BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), BERLIN_PINCTRL_FUNCTION(0x1, "sd0"), BERLIN_PINCTRL_FUNCTION(0x6, "usb0_dbg"), BERLIN_PINCTRL_FUNCTION(0x7, "usb1_dbg")), - BERLIN_PINCTRL_GROUP("G2", 0x00, 0x2, 0x02, + BERLIN_PINCTRL_GROUP("G2", 0x00, 0x3, 0x06, BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), BERLIN_PINCTRL_FUNCTION(0x1, "sd0"), BERLIN_PINCTRL_FUNCTION(0x2, "fe"), BERLIN_PINCTRL_FUNCTION(0x3, "pll"), BERLIN_PINCTRL_FUNCTION(0x6, "usb0_dbg"), BERLIN_PINCTRL_FUNCTION(0x7, "usb1_dbg")), - BERLIN_PINCTRL_GROUP("G3", 0x00, 0x2, 0x04, + BERLIN_PINCTRL_GROUP("G3", 0x00, 0x3, 0x09, BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), BERLIN_PINCTRL_FUNCTION(0x1, "sd0"), BERLIN_PINCTRL_FUNCTION(0x2, "twsi2"), @@ -44,7 +44,7 @@ static const struct berlin_desc_group berlin2cd_soc_pinctrl_groups[] = { BERLIN_PINCTRL_FUNCTION(0x4, "fe"), BERLIN_PINCTRL_FUNCTION(0x6, "usb0_dbg"), BERLIN_PINCTRL_FUNCTION(0x7, "usb1_dbg")), - BERLIN_PINCTRL_GROUP("G4", 0x00, 0x2, 0x06, + BERLIN_PINCTRL_GROUP("G4", 0x00, 0x3, 0x0c, BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), BERLIN_PINCTRL_FUNCTION(0x1, "sd0"), BERLIN_PINCTRL_FUNCTION(0x2, "twsi3"), @@ -52,7 +52,7 @@ static const struct berlin_desc_group berlin2cd_soc_pinctrl_groups[] = { BERLIN_PINCTRL_FUNCTION(0x4, "pwm"), BERLIN_PINCTRL_FUNCTION(0x6, "usb0_dbg"), BERLIN_PINCTRL_FUNCTION(0x7, "usb1_dbg")), - BERLIN_PINCTRL_GROUP("G5", 0x00, 0x3, 0x08, + BERLIN_PINCTRL_GROUP("G5", 0x00, 0x3, 0x0f, BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), BERLIN_PINCTRL_FUNCTION(0x1, "sd0"), BERLIN_PINCTRL_FUNCTION(0x2, "twsi3"), @@ -60,64 +60,66 @@ static const struct berlin_desc_group berlin2cd_soc_pinctrl_groups[] = { BERLIN_PINCTRL_FUNCTION(0x4, "pwm"), BERLIN_PINCTRL_FUNCTION(0x6, "usb0_dbg"), BERLIN_PINCTRL_FUNCTION(0x7, "usb1_dbg")), - BERLIN_PINCTRL_GROUP("G6", 0x00, 0x2, 0x0b, + BERLIN_PINCTRL_GROUP("G6", 0x00, 0x3, 0x12, BERLIN_PINCTRL_FUNCTION(0x0, "uart0"), /* RX/TX */ BERLIN_PINCTRL_FUNCTION(0x1, "gpio")), - BERLIN_PINCTRL_GROUP("G7", 0x00, 0x3, 0x0d, + BERLIN_PINCTRL_GROUP("G7", 0x00, 0x3, 0x15, BERLIN_PINCTRL_FUNCTION(0x0, "eddc"), BERLIN_PINCTRL_FUNCTION(0x1, "twsi1"), BERLIN_PINCTRL_FUNCTION(0x2, "gpio")), - BERLIN_PINCTRL_GROUP("G8", 0x00, 0x3, 0x10, + BERLIN_PINCTRL_GROUP("G8", 0x00, 0x3, 0x18, BERLIN_PINCTRL_FUNCTION(0x0, "spi1"), /* SS0n */ BERLIN_PINCTRL_FUNCTION(0x1, "gpio")), - BERLIN_PINCTRL_GROUP("G9", 0x00, 0x3, 0x13, + BERLIN_PINCTRL_GROUP("G9", 0x00, 0x3, 0x1b, BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), BERLIN_PINCTRL_FUNCTION(0x1, "spi1"), /* SS1n/SS2n */ - BERLIN_PINCTRL_FUNCTION(0x2, "twsi0")), - BERLIN_PINCTRL_GROUP("G10", 0x00, 0x2, 0x16, + BERLIN_PINCTRL_FUNCTION(0x3, "twsi0")), + BERLIN_PINCTRL_GROUP("G10", 0x00, 0x2, 0x1e, BERLIN_PINCTRL_FUNCTION(0x0, "spi1"), /* CLK */ BERLIN_PINCTRL_FUNCTION(0x1, "gpio")), - BERLIN_PINCTRL_GROUP("G11", 0x00, 0x2, 0x18, + BERLIN_PINCTRL_GROUP("G11", 0x04, 0x2, 0x00, BERLIN_PINCTRL_FUNCTION(0x0, "spi1"), /* SDI/SDO */ BERLIN_PINCTRL_FUNCTION(0x1, "gpio")), - BERLIN_PINCTRL_GROUP("G12", 0x00, 0x3, 0x1a, + BERLIN_PINCTRL_GROUP("G12", 0x04, 0x3, 0x02, BERLIN_PINCTRL_FUNCTION(0x0, "usb1"), BERLIN_PINCTRL_FUNCTION(0x1, "gpio")), - BERLIN_PINCTRL_GROUP("G13", 0x04, 0x3, 0x00, + BERLIN_PINCTRL_GROUP("G13", 0x04, 0x3, 0x05, BERLIN_PINCTRL_FUNCTION(0x0, "nand"), BERLIN_PINCTRL_FUNCTION(0x1, "usb0_dbg"), BERLIN_PINCTRL_FUNCTION(0x2, "usb1_dbg")), - BERLIN_PINCTRL_GROUP("G14", 0x04, 0x1, 0x03, + BERLIN_PINCTRL_GROUP("G14", 0x04, 0x1, 0x08, BERLIN_PINCTRL_FUNCTION(0x0, "nand"), BERLIN_PINCTRL_FUNCTION(0x1, "gpio")), - BERLIN_PINCTRL_GROUP("G15", 0x04, 0x2, 0x04, + BERLIN_PINCTRL_GROUP("G15", 0x04, 0x3, 0x09, BERLIN_PINCTRL_FUNCTION(0x0, "jtag"), BERLIN_PINCTRL_FUNCTION(0x1, "gpio")), - BERLIN_PINCTRL_GROUP("G16", 0x04, 0x3, 0x06, + BERLIN_PINCTRL_GROUP("G16", 0x04, 0x3, 0x0c, BERLIN_PINCTRL_FUNCTION_UNKNOWN), - BERLIN_PINCTRL_GROUP("G17", 0x04, 0x3, 0x09, + BERLIN_PINCTRL_GROUP("G17", 0x04, 0x3, 0x0f, BERLIN_PINCTRL_FUNCTION_UNKNOWN), - BERLIN_PINCTRL_GROUP("G18", 0x04, 0x1, 0x0c, + BERLIN_PINCTRL_GROUP("G18", 0x04, 0x2, 0x12, BERLIN_PINCTRL_FUNCTION_UNKNOWN), - BERLIN_PINCTRL_GROUP("G19", 0x04, 0x1, 0x0d, + BERLIN_PINCTRL_GROUP("G19", 0x04, 0x2, 0x14, BERLIN_PINCTRL_FUNCTION_UNKNOWN), - BERLIN_PINCTRL_GROUP("G20", 0x04, 0x1, 0x0e, + BERLIN_PINCTRL_GROUP("G20", 0x04, 0x2, 0x16, BERLIN_PINCTRL_FUNCTION_UNKNOWN), - BERLIN_PINCTRL_GROUP("G21", 0x04, 0x3, 0x0f, + BERLIN_PINCTRL_GROUP("G21", 0x04, 0x3, 0x18, BERLIN_PINCTRL_FUNCTION_UNKNOWN), - BERLIN_PINCTRL_GROUP("G22", 0x04, 0x3, 0x12, + BERLIN_PINCTRL_GROUP("G22", 0x04, 0x3, 0x1b, BERLIN_PINCTRL_FUNCTION_UNKNOWN), - BERLIN_PINCTRL_GROUP("G23", 0x04, 0x3, 0x15, + BERLIN_PINCTRL_GROUP("G23", 0x08, 0x3, 0x00, BERLIN_PINCTRL_FUNCTION_UNKNOWN), - BERLIN_PINCTRL_GROUP("G24", 0x04, 0x2, 0x18, + BERLIN_PINCTRL_GROUP("G24", 0x08, 0x2, 0x03, BERLIN_PINCTRL_FUNCTION_UNKNOWN), - BERLIN_PINCTRL_GROUP("G25", 0x04, 0x2, 0x1a, + BERLIN_PINCTRL_GROUP("G25", 0x08, 0x2, 0x05, BERLIN_PINCTRL_FUNCTION_UNKNOWN), - BERLIN_PINCTRL_GROUP("G26", 0x04, 0x1, 0x1c, + BERLIN_PINCTRL_GROUP("G26", 0x08, 0x1, 0x07, BERLIN_PINCTRL_FUNCTION_UNKNOWN), - BERLIN_PINCTRL_GROUP("G27", 0x04, 0x1, 0x1d, + BERLIN_PINCTRL_GROUP("G27", 0x08, 0x2, 0x08, BERLIN_PINCTRL_FUNCTION_UNKNOWN), - BERLIN_PINCTRL_GROUP("G28", 0x04, 0x2, 0x1e, + BERLIN_PINCTRL_GROUP("G28", 0x08, 0x3, 0x0a, + BERLIN_PINCTRL_FUNCTION_UNKNOWN), + BERLIN_PINCTRL_GROUP("G29", 0x08, 0x3, 0x0d, BERLIN_PINCTRL_FUNCTION_UNKNOWN), }; -- cgit v0.10.2 From 3fa508cd233da76eb00377440600f53eebfec08a Mon Sep 17 00:00:00 2001 From: Wei Chen Date: Fri, 9 Oct 2015 06:31:18 +0000 Subject: pinctrl: atlas7: support atlas7 step B changes The the pin groups and pin functions have been changed in atlas7 step B soc. We have to update the driver to support step B chip. Changes: 1. add 5 jtag pins to IOC_TOP: "jtag_tdo", "jtag_tms","jtag_tck", "jtag_tdi", "jtag_trstn" these 5 pins can be mutiplex with other functions, so we have to conver these 5 pins in pinmux. 2. add pin groups for audio digmic, audio spdif, can transceiver en, can transceiver stb, i2s0, i2s1 and jtag. 3. serval pins can be located to more PADs: audio_uart0_urfs, audio_uart1_urfs, audio_uart2_urfs, audio_uart2_urxd, audio_uart2_usclk, audio_uart2_utfs, audio_uart2_utxd, can0_rxd, can0_txd, can1_rxd, can1_txd jtag_ntrst, jtag_swdiotms, jtag_tck, jtag_tdi, jtag_tdo, pw_cko0, pw_cko1, pw_i2s01, pw_pwm0, pw_pwm1, sd2_cdb, sd2_wpb, uart2_cts, uart2_rts, uart2_rxd, uart2_txd, uart3_cts, uart3_rts, uart3_rxd, uart3_txd, uart4_cts, uart4_rts, usb0_drvvbus, usb1_drvvbus. Because of Changes#3, some functions should have more than one pin groups. So we have to split the original pin group to serval pin groups. For example: audio_uart0 has 5 pins, on STEPA, each of these 5 pins only has one related PAD. But on STEPB, audio_uart0_urfs has 4 related PAD. So we place the 4 pins with one PAD into a single pin group: audio_uart0_basic_group. and place urfs pin wtih different PADs to 4 different pin groups: audio_uart0_urfs_group0, ..., audio_uart0_urfs_group3 A full audio_uart0 pin group can be: pinctrl-0 = <&audio_uart0_basic_group &audio_uart0_urfs_group0>; If audio_uart0 pin group encountered some confiction, we only have to change the urfs group: pinctrl-0 = <&audio_uart0_basic_group &audio_uart0_urfs_group2>; Signed-off-by: Wei Chen Signed-off-by: Barry Song Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/sirf/pinctrl-atlas7.c b/drivers/pinctrl/sirf/pinctrl-atlas7.c index 0d24d9e..829018c 100644 --- a/drivers/pinctrl/sirf/pinctrl-atlas7.c +++ b/drivers/pinctrl/sirf/pinctrl-atlas7.c @@ -544,6 +544,11 @@ static const struct pinctrl_pin_desc atlas7_ioc_pads[] = { PINCTRL_PIN(156, "lvds_tx0d1n"), PINCTRL_PIN(157, "lvds_tx0d0p"), PINCTRL_PIN(158, "lvds_tx0d0n"), + PINCTRL_PIN(159, "jtag_tdo"), + PINCTRL_PIN(160, "jtag_tms"), + PINCTRL_PIN(161, "jtag_tck"), + PINCTRL_PIN(162, "jtag_tdi"), + PINCTRL_PIN(163, "jtag_trstn"), }; struct atlas7_pad_config atlas7_ioc_pad_confs[] = { @@ -708,6 +713,11 @@ struct atlas7_pad_config atlas7_ioc_pad_confs[] = { PADCONF(156, 7, 0x130, 0x270, -1, 0x480, 28, 14, 0, 7), PADCONF(157, 7, 0x138, 0x278, -1, 0x480, 0, 0, 0, 8), PADCONF(158, 7, 0x138, 0x278, -1, 0x480, 4, 2, 0, 9), + PADCONF(159, 5, 0x140, 0x280, 0x380, -1, 0, 0, 0, 0), + PADCONF(160, 6, 0x140, 0x280, 0x380, -1, 4, 2, 2, 0), + PADCONF(161, 5, 0x140, 0x280, 0x380, -1, 8, 4, 4, 0), + PADCONF(162, 6, 0x140, 0x280, 0x380, -1, 12, 6, 6, 0), + PADCONF(163, 6, 0x140, 0x280, 0x380, -1, 16, 8, 8, 0), }; /* pin list of each pin group */ @@ -724,12 +734,15 @@ static const unsigned int sp_rgmii_gpio_pins[] = { 97, 98, 99, 100, 101, 102, 141, 142, 143, 144, 145, 146, 147, 148, }; static const unsigned int lvds_gpio_pins[] = { 157, 158, 155, 156, 153, 154, 151, 152, 149, 150, }; -static const unsigned int uart_nand_gpio_pins[] = { 44, 43, 42, 41, 40, 39, - 38, 37, 46, 47, 48, 49, 50, 52, 51, 45, 133, 134, 135, 136, - 137, 138, 139, 140, }; +static const unsigned int jtag_uart_nand_gpio_pins[] = { 44, 43, 42, 41, 40, + 39, 38, 37, 46, 47, 48, 49, 50, 52, 51, 45, 133, 134, 135, + 136, 137, 138, 139, 140, 159, 160, 161, 162, 163, }; static const unsigned int rtc_gpio_pins[] = { 0, 1, 2, 3, 4, 10, 11, 12, 13, - 14, 15, 16, 17, }; + 14, 15, 16, 17, 9, }; static const unsigned int audio_ac97_pins[] = { 113, 118, 115, 114, }; +static const unsigned int audio_digmic_pins0[] = { 51, }; +static const unsigned int audio_digmic_pins1[] = { 122, }; +static const unsigned int audio_digmic_pins2[] = { 161, }; static const unsigned int audio_func_dbg_pins[] = { 141, 144, 44, 43, 42, 41, 40, 39, 38, 37, 74, 75, 76, 77, 78, 79, 81, 113, 114, 118, 115, 49, 50, 142, 143, 80, }; @@ -737,16 +750,49 @@ static const unsigned int audio_i2s_pins[] = { 118, 115, 116, 117, 112, 113, 114, }; static const unsigned int audio_i2s_2ch_pins[] = { 118, 115, 112, 113, 114, }; static const unsigned int audio_i2s_extclk_pins[] = { 112, }; -static const unsigned int audio_uart0_pins[] = { 143, 142, 141, 144, }; -static const unsigned int audio_uart1_pins[] = { 147, 146, 145, 148, }; -static const unsigned int audio_uart2_pins0[] = { 20, 21, 19, 18, }; -static const unsigned int audio_uart2_pins1[] = { 109, 110, 101, 111, }; -static const unsigned int c_can_trnsvr_pins[] = { 1, }; -static const unsigned int c0_can_pins0[] = { 11, 10, }; -static const unsigned int c0_can_pins1[] = { 2, 3, }; -static const unsigned int c1_can_pins0[] = { 138, 137, }; -static const unsigned int c1_can_pins1[] = { 147, 146, }; -static const unsigned int c1_can_pins2[] = { 2, 3, }; +static const unsigned int audio_spdif_out_pins0[] = { 112, }; +static const unsigned int audio_spdif_out_pins1[] = { 116, }; +static const unsigned int audio_spdif_out_pins2[] = { 142, }; +static const unsigned int audio_uart0_basic_pins[] = { 143, 142, 141, 144, }; +static const unsigned int audio_uart0_urfs_pins0[] = { 117, }; +static const unsigned int audio_uart0_urfs_pins1[] = { 139, }; +static const unsigned int audio_uart0_urfs_pins2[] = { 163, }; +static const unsigned int audio_uart0_urfs_pins3[] = { 162, }; +static const unsigned int audio_uart1_basic_pins[] = { 147, 146, 145, 148, }; +static const unsigned int audio_uart1_urfs_pins0[] = { 117, }; +static const unsigned int audio_uart1_urfs_pins1[] = { 140, }; +static const unsigned int audio_uart1_urfs_pins2[] = { 163, }; +static const unsigned int audio_uart2_urfs_pins0[] = { 139, }; +static const unsigned int audio_uart2_urfs_pins1[] = { 163, }; +static const unsigned int audio_uart2_urfs_pins2[] = { 96, }; +static const unsigned int audio_uart2_urxd_pins0[] = { 20, }; +static const unsigned int audio_uart2_urxd_pins1[] = { 109, }; +static const unsigned int audio_uart2_urxd_pins2[] = { 93, }; +static const unsigned int audio_uart2_usclk_pins0[] = { 19, }; +static const unsigned int audio_uart2_usclk_pins1[] = { 101, }; +static const unsigned int audio_uart2_usclk_pins2[] = { 91, }; +static const unsigned int audio_uart2_utfs_pins0[] = { 18, }; +static const unsigned int audio_uart2_utfs_pins1[] = { 111, }; +static const unsigned int audio_uart2_utfs_pins2[] = { 94, }; +static const unsigned int audio_uart2_utxd_pins0[] = { 21, }; +static const unsigned int audio_uart2_utxd_pins1[] = { 110, }; +static const unsigned int audio_uart2_utxd_pins2[] = { 92, }; +static const unsigned int c_can_trnsvr_en_pins0[] = { 2, }; +static const unsigned int c_can_trnsvr_en_pins1[] = { 0, }; +static const unsigned int c_can_trnsvr_intr_pins[] = { 1, }; +static const unsigned int c_can_trnsvr_stb_n_pins[] = { 3, }; +static const unsigned int c0_can_rxd_trnsv0_pins[] = { 11, }; +static const unsigned int c0_can_rxd_trnsv1_pins[] = { 2, }; +static const unsigned int c0_can_txd_trnsv0_pins[] = { 10, }; +static const unsigned int c0_can_txd_trnsv1_pins[] = { 3, }; +static const unsigned int c1_can_rxd_pins0[] = { 138, }; +static const unsigned int c1_can_rxd_pins1[] = { 147, }; +static const unsigned int c1_can_rxd_pins2[] = { 2, }; +static const unsigned int c1_can_rxd_pins3[] = { 162, }; +static const unsigned int c1_can_txd_pins0[] = { 137, }; +static const unsigned int c1_can_txd_pins1[] = { 146, }; +static const unsigned int c1_can_txd_pins2[] = { 3, }; +static const unsigned int c1_can_txd_pins3[] = { 161, }; static const unsigned int ca_audio_lpc_pins[] = { 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, }; static const unsigned int ca_bt_lpc_pins[] = { 85, 86, 87, 88, 89, 90, }; @@ -804,7 +850,29 @@ static const unsigned int gn_trg_shutdown_pins2[] = { 117, }; static const unsigned int gn_trg_shutdown_pins3[] = { 123, }; static const unsigned int i2c0_pins[] = { 128, 127, }; static const unsigned int i2c1_pins[] = { 126, 125, }; -static const unsigned int jtag_pins0[] = { 125, 4, 2, 0, 1, 3, }; +static const unsigned int i2s0_pins[] = { 91, 93, 94, 92, }; +static const unsigned int i2s1_basic_pins[] = { 95, 96, }; +static const unsigned int i2s1_rxd0_pins0[] = { 61, }; +static const unsigned int i2s1_rxd0_pins1[] = { 131, }; +static const unsigned int i2s1_rxd0_pins2[] = { 129, }; +static const unsigned int i2s1_rxd0_pins3[] = { 117, }; +static const unsigned int i2s1_rxd0_pins4[] = { 83, }; +static const unsigned int i2s1_rxd1_pins0[] = { 72, }; +static const unsigned int i2s1_rxd1_pins1[] = { 132, }; +static const unsigned int i2s1_rxd1_pins2[] = { 130, }; +static const unsigned int i2s1_rxd1_pins3[] = { 118, }; +static const unsigned int i2s1_rxd1_pins4[] = { 84, }; +static const unsigned int jtag_jt_dbg_nsrst_pins[] = { 125, }; +static const unsigned int jtag_ntrst_pins0[] = { 4, }; +static const unsigned int jtag_ntrst_pins1[] = { 163, }; +static const unsigned int jtag_swdiotms_pins0[] = { 2, }; +static const unsigned int jtag_swdiotms_pins1[] = { 160, }; +static const unsigned int jtag_tck_pins0[] = { 0, }; +static const unsigned int jtag_tck_pins1[] = { 161, }; +static const unsigned int jtag_tdi_pins0[] = { 1, }; +static const unsigned int jtag_tdi_pins1[] = { 162, }; +static const unsigned int jtag_tdo_pins0[] = { 3, }; +static const unsigned int jtag_tdo_pins1[] = { 159, }; static const unsigned int ks_kas_spi_pins0[] = { 141, 144, 143, 142, }; static const unsigned int ld_ldd_pins[] = { 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 74, 75, 76, 77, 78, 79, 80, @@ -821,7 +889,7 @@ static const unsigned int nd_df_pins[] = { 44, 43, 42, 41, 40, 39, 38, 37, 47, 46, 52, 51, 45, 49, 50, 48, 124, }; static const unsigned int nd_df_nowp_pins[] = { 44, 43, 42, 41, 40, 39, 38, 37, 47, 46, 52, 51, 45, 49, 50, 48, }; -static const unsigned int ps_pins[] = { 120, 119, }; +static const unsigned int ps_pins[] = { 120, 119, 121, }; static const unsigned int pwc_core_on_pins[] = { 8, }; static const unsigned int pwc_ext_on_pins[] = { 6, }; static const unsigned int pwc_gpio3_clk_pins[] = { 3, }; @@ -836,18 +904,26 @@ static const unsigned int pwc_wakeup_src3_pins[] = { 3, }; static const unsigned int pw_cko0_pins0[] = { 123, }; static const unsigned int pw_cko0_pins1[] = { 101, }; static const unsigned int pw_cko0_pins2[] = { 82, }; +static const unsigned int pw_cko0_pins3[] = { 162, }; static const unsigned int pw_cko1_pins0[] = { 124, }; static const unsigned int pw_cko1_pins1[] = { 110, }; +static const unsigned int pw_cko1_pins2[] = { 163, }; static const unsigned int pw_i2s01_clk_pins0[] = { 125, }; static const unsigned int pw_i2s01_clk_pins1[] = { 117, }; -static const unsigned int pw_pwm0_pins[] = { 119, }; -static const unsigned int pw_pwm1_pins[] = { 120, }; +static const unsigned int pw_i2s01_clk_pins2[] = { 132, }; +static const unsigned int pw_pwm0_pins0[] = { 119, }; +static const unsigned int pw_pwm0_pins1[] = { 159, }; +static const unsigned int pw_pwm1_pins0[] = { 120, }; +static const unsigned int pw_pwm1_pins1[] = { 160, }; +static const unsigned int pw_pwm1_pins2[] = { 131, }; static const unsigned int pw_pwm2_pins0[] = { 121, }; static const unsigned int pw_pwm2_pins1[] = { 98, }; +static const unsigned int pw_pwm2_pins2[] = { 161, }; static const unsigned int pw_pwm3_pins0[] = { 122, }; static const unsigned int pw_pwm3_pins1[] = { 73, }; static const unsigned int pw_pwm_cpu_vol_pins0[] = { 121, }; static const unsigned int pw_pwm_cpu_vol_pins1[] = { 98, }; +static const unsigned int pw_pwm_cpu_vol_pins2[] = { 161, }; static const unsigned int pw_backlight_pins0[] = { 122, }; static const unsigned int pw_backlight_pins1[] = { 73, }; static const unsigned int rg_eth_mac_pins[] = { 108, 103, 104, 105, 106, 107, @@ -863,8 +939,11 @@ static const unsigned int sd1_pins[] = { 48, 49, 44, 43, 42, 41, 40, 39, 38, 37, }; static const unsigned int sd1_4bit_pins0[] = { 48, 49, 44, 43, 42, 41, }; static const unsigned int sd1_4bit_pins1[] = { 48, 49, 40, 39, 38, 37, }; -static const unsigned int sd2_pins0[] = { 124, 31, 32, 33, 34, 35, 36, 123, }; -static const unsigned int sd2_no_cdb_pins0[] = { 31, 32, 33, 34, 35, 36, 123, }; +static const unsigned int sd2_basic_pins[] = { 31, 32, 33, 34, 35, 36, }; +static const unsigned int sd2_cdb_pins0[] = { 124, }; +static const unsigned int sd2_cdb_pins1[] = { 161, }; +static const unsigned int sd2_wpb_pins0[] = { 123, }; +static const unsigned int sd2_wpb_pins1[] = { 163, }; static const unsigned int sd3_pins[] = { 85, 86, 87, 88, 89, 90, }; static const unsigned int sd5_pins[] = { 91, 92, 93, 94, 95, 96, }; static const unsigned int sd6_pins0[] = { 79, 78, 74, 75, 76, 77, }; @@ -877,19 +956,39 @@ static const unsigned int tpiu_trace_pins[] = { 53, 56, 57, 58, 59, 60, 61, static const unsigned int uart0_pins[] = { 121, 120, 134, 133, }; static const unsigned int uart0_nopause_pins[] = { 134, 133, }; static const unsigned int uart1_pins[] = { 136, 135, }; -static const unsigned int uart2_pins[] = { 11, 10, }; -static const unsigned int uart3_pins0[] = { 125, 126, 138, 137, }; -static const unsigned int uart3_pins1[] = { 111, 109, 84, 83, }; -static const unsigned int uart3_pins2[] = { 140, 139, 138, 137, }; -static const unsigned int uart3_pins3[] = { 139, 140, 84, 83, }; -static const unsigned int uart3_nopause_pins0[] = { 138, 137, }; -static const unsigned int uart3_nopause_pins1[] = { 84, 83, }; -static const unsigned int uart4_pins0[] = { 122, 123, 140, 139, }; -static const unsigned int uart4_pins1[] = { 100, 99, 140, 139, }; -static const unsigned int uart4_pins2[] = { 117, 116, 140, 139, }; -static const unsigned int uart4_nopause_pins[] = { 140, 139, }; -static const unsigned int usb0_drvvbus_pins[] = { 51, }; -static const unsigned int usb1_drvvbus_pins[] = { 134, }; +static const unsigned int uart2_cts_pins0[] = { 132, }; +static const unsigned int uart2_cts_pins1[] = { 162, }; +static const unsigned int uart2_rts_pins0[] = { 131, }; +static const unsigned int uart2_rts_pins1[] = { 161, }; +static const unsigned int uart2_rxd_pins0[] = { 11, }; +static const unsigned int uart2_rxd_pins1[] = { 160, }; +static const unsigned int uart2_rxd_pins2[] = { 130, }; +static const unsigned int uart2_txd_pins0[] = { 10, }; +static const unsigned int uart2_txd_pins1[] = { 159, }; +static const unsigned int uart2_txd_pins2[] = { 129, }; +static const unsigned int uart3_cts_pins0[] = { 125, }; +static const unsigned int uart3_cts_pins1[] = { 111, }; +static const unsigned int uart3_cts_pins2[] = { 140, }; +static const unsigned int uart3_rts_pins0[] = { 126, }; +static const unsigned int uart3_rts_pins1[] = { 109, }; +static const unsigned int uart3_rts_pins2[] = { 139, }; +static const unsigned int uart3_rxd_pins0[] = { 138, }; +static const unsigned int uart3_rxd_pins1[] = { 84, }; +static const unsigned int uart3_rxd_pins2[] = { 162, }; +static const unsigned int uart3_txd_pins0[] = { 137, }; +static const unsigned int uart3_txd_pins1[] = { 83, }; +static const unsigned int uart3_txd_pins2[] = { 161, }; +static const unsigned int uart4_basic_pins[] = { 140, 139, }; +static const unsigned int uart4_cts_pins0[] = { 122, }; +static const unsigned int uart4_cts_pins1[] = { 100, }; +static const unsigned int uart4_cts_pins2[] = { 117, }; +static const unsigned int uart4_rts_pins0[] = { 123, }; +static const unsigned int uart4_rts_pins1[] = { 99, }; +static const unsigned int uart4_rts_pins2[] = { 116, }; +static const unsigned int usb0_drvvbus_pins0[] = { 51, }; +static const unsigned int usb0_drvvbus_pins1[] = { 162, }; +static const unsigned int usb1_drvvbus_pins0[] = { 134, }; +static const unsigned int usb1_drvvbus_pins1[] = { 163, }; static const unsigned int visbus_dout_pins[] = { 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 53, 54, 55, 56, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, }; @@ -910,23 +1009,59 @@ struct atlas7_pin_group altas7_pin_groups[] = { GROUP("sdio_i2s_gpio_grp", sdio_i2s_gpio_pins), GROUP("sp_rgmii_gpio_grp", sp_rgmii_gpio_pins), GROUP("lvds_gpio_grp", lvds_gpio_pins), - GROUP("uart_nand_gpio_grp", uart_nand_gpio_pins), + GROUP("jtag_uart_nand_gpio_grp", jtag_uart_nand_gpio_pins), GROUP("rtc_gpio_grp", rtc_gpio_pins), GROUP("audio_ac97_grp", audio_ac97_pins), + GROUP("audio_digmic_grp0", audio_digmic_pins0), + GROUP("audio_digmic_grp1", audio_digmic_pins1), + GROUP("audio_digmic_grp2", audio_digmic_pins2), GROUP("audio_func_dbg_grp", audio_func_dbg_pins), GROUP("audio_i2s_grp", audio_i2s_pins), GROUP("audio_i2s_2ch_grp", audio_i2s_2ch_pins), GROUP("audio_i2s_extclk_grp", audio_i2s_extclk_pins), - GROUP("audio_uart0_grp", audio_uart0_pins), - GROUP("audio_uart1_grp", audio_uart1_pins), - GROUP("audio_uart2_grp0", audio_uart2_pins0), - GROUP("audio_uart2_grp1", audio_uart2_pins1), - GROUP("c_can_trnsvr_grp", c_can_trnsvr_pins), - GROUP("c0_can_grp0", c0_can_pins0), - GROUP("c0_can_grp1", c0_can_pins1), - GROUP("c1_can_grp0", c1_can_pins0), - GROUP("c1_can_grp1", c1_can_pins1), - GROUP("c1_can_grp2", c1_can_pins2), + GROUP("audio_spdif_out_grp0", audio_spdif_out_pins0), + GROUP("audio_spdif_out_grp1", audio_spdif_out_pins1), + GROUP("audio_spdif_out_grp2", audio_spdif_out_pins2), + GROUP("audio_uart0_basic_grp", audio_uart0_basic_pins), + GROUP("audio_uart0_urfs_grp0", audio_uart0_urfs_pins0), + GROUP("audio_uart0_urfs_grp1", audio_uart0_urfs_pins1), + GROUP("audio_uart0_urfs_grp2", audio_uart0_urfs_pins2), + GROUP("audio_uart0_urfs_grp3", audio_uart0_urfs_pins3), + GROUP("audio_uart1_basic_grp", audio_uart1_basic_pins), + GROUP("audio_uart1_urfs_grp0", audio_uart1_urfs_pins0), + GROUP("audio_uart1_urfs_grp1", audio_uart1_urfs_pins1), + GROUP("audio_uart1_urfs_grp2", audio_uart1_urfs_pins2), + GROUP("audio_uart2_urfs_grp0", audio_uart2_urfs_pins0), + GROUP("audio_uart2_urfs_grp1", audio_uart2_urfs_pins1), + GROUP("audio_uart2_urfs_grp2", audio_uart2_urfs_pins2), + GROUP("audio_uart2_urxd_grp0", audio_uart2_urxd_pins0), + GROUP("audio_uart2_urxd_grp1", audio_uart2_urxd_pins1), + GROUP("audio_uart2_urxd_grp2", audio_uart2_urxd_pins2), + GROUP("audio_uart2_usclk_grp0", audio_uart2_usclk_pins0), + GROUP("audio_uart2_usclk_grp1", audio_uart2_usclk_pins1), + GROUP("audio_uart2_usclk_grp2", audio_uart2_usclk_pins2), + GROUP("audio_uart2_utfs_grp0", audio_uart2_utfs_pins0), + GROUP("audio_uart2_utfs_grp1", audio_uart2_utfs_pins1), + GROUP("audio_uart2_utfs_grp2", audio_uart2_utfs_pins2), + GROUP("audio_uart2_utxd_grp0", audio_uart2_utxd_pins0), + GROUP("audio_uart2_utxd_grp1", audio_uart2_utxd_pins1), + GROUP("audio_uart2_utxd_grp2", audio_uart2_utxd_pins2), + GROUP("c_can_trnsvr_en_grp0", c_can_trnsvr_en_pins0), + GROUP("c_can_trnsvr_en_grp1", c_can_trnsvr_en_pins1), + GROUP("c_can_trnsvr_intr_grp", c_can_trnsvr_intr_pins), + GROUP("c_can_trnsvr_stb_n_grp", c_can_trnsvr_stb_n_pins), + GROUP("c0_can_rxd_trnsv0_grp", c0_can_rxd_trnsv0_pins), + GROUP("c0_can_rxd_trnsv1_grp", c0_can_rxd_trnsv1_pins), + GROUP("c0_can_txd_trnsv0_grp", c0_can_txd_trnsv0_pins), + GROUP("c0_can_txd_trnsv1_grp", c0_can_txd_trnsv1_pins), + GROUP("c1_can_rxd_grp0", c1_can_rxd_pins0), + GROUP("c1_can_rxd_grp1", c1_can_rxd_pins1), + GROUP("c1_can_rxd_grp2", c1_can_rxd_pins2), + GROUP("c1_can_rxd_grp3", c1_can_rxd_pins3), + GROUP("c1_can_txd_grp0", c1_can_txd_pins0), + GROUP("c1_can_txd_grp1", c1_can_txd_pins1), + GROUP("c1_can_txd_grp2", c1_can_txd_pins2), + GROUP("c1_can_txd_grp3", c1_can_txd_pins3), GROUP("ca_audio_lpc_grp", ca_audio_lpc_pins), GROUP("ca_bt_lpc_grp", ca_bt_lpc_pins), GROUP("ca_coex_grp", ca_coex_pins), @@ -977,7 +1112,29 @@ struct atlas7_pin_group altas7_pin_groups[] = { GROUP("gn_trg_shutdown_grp3", gn_trg_shutdown_pins3), GROUP("i2c0_grp", i2c0_pins), GROUP("i2c1_grp", i2c1_pins), - GROUP("jtag_grp0", jtag_pins0), + GROUP("i2s0_grp", i2s0_pins), + GROUP("i2s1_basic_grp", i2s1_basic_pins), + GROUP("i2s1_rxd0_grp0", i2s1_rxd0_pins0), + GROUP("i2s1_rxd0_grp1", i2s1_rxd0_pins1), + GROUP("i2s1_rxd0_grp2", i2s1_rxd0_pins2), + GROUP("i2s1_rxd0_grp3", i2s1_rxd0_pins3), + GROUP("i2s1_rxd0_grp4", i2s1_rxd0_pins4), + GROUP("i2s1_rxd1_grp0", i2s1_rxd1_pins0), + GROUP("i2s1_rxd1_grp1", i2s1_rxd1_pins1), + GROUP("i2s1_rxd1_grp2", i2s1_rxd1_pins2), + GROUP("i2s1_rxd1_grp3", i2s1_rxd1_pins3), + GROUP("i2s1_rxd1_grp4", i2s1_rxd1_pins4), + GROUP("jtag_jt_dbg_nsrst_grp", jtag_jt_dbg_nsrst_pins), + GROUP("jtag_ntrst_grp0", jtag_ntrst_pins0), + GROUP("jtag_ntrst_grp1", jtag_ntrst_pins1), + GROUP("jtag_swdiotms_grp0", jtag_swdiotms_pins0), + GROUP("jtag_swdiotms_grp1", jtag_swdiotms_pins1), + GROUP("jtag_tck_grp0", jtag_tck_pins0), + GROUP("jtag_tck_grp1", jtag_tck_pins1), + GROUP("jtag_tdi_grp0", jtag_tdi_pins0), + GROUP("jtag_tdi_grp1", jtag_tdi_pins1), + GROUP("jtag_tdo_grp0", jtag_tdo_pins0), + GROUP("jtag_tdo_grp1", jtag_tdo_pins1), GROUP("ks_kas_spi_grp0", ks_kas_spi_pins0), GROUP("ld_ldd_grp", ld_ldd_pins), GROUP("ld_ldd_16bit_grp", ld_ldd_16bit_pins), @@ -1002,18 +1159,26 @@ struct atlas7_pin_group altas7_pin_groups[] = { GROUP("pw_cko0_grp0", pw_cko0_pins0), GROUP("pw_cko0_grp1", pw_cko0_pins1), GROUP("pw_cko0_grp2", pw_cko0_pins2), + GROUP("pw_cko0_grp3", pw_cko0_pins3), GROUP("pw_cko1_grp0", pw_cko1_pins0), GROUP("pw_cko1_grp1", pw_cko1_pins1), + GROUP("pw_cko1_grp2", pw_cko1_pins2), GROUP("pw_i2s01_clk_grp0", pw_i2s01_clk_pins0), GROUP("pw_i2s01_clk_grp1", pw_i2s01_clk_pins1), - GROUP("pw_pwm0_grp", pw_pwm0_pins), - GROUP("pw_pwm1_grp", pw_pwm1_pins), + GROUP("pw_i2s01_clk_grp2", pw_i2s01_clk_pins2), + GROUP("pw_pwm0_grp0", pw_pwm0_pins0), + GROUP("pw_pwm0_grp1", pw_pwm0_pins1), + GROUP("pw_pwm1_grp0", pw_pwm1_pins0), + GROUP("pw_pwm1_grp1", pw_pwm1_pins1), + GROUP("pw_pwm1_grp2", pw_pwm1_pins2), GROUP("pw_pwm2_grp0", pw_pwm2_pins0), GROUP("pw_pwm2_grp1", pw_pwm2_pins1), + GROUP("pw_pwm2_grp2", pw_pwm2_pins2), GROUP("pw_pwm3_grp0", pw_pwm3_pins0), GROUP("pw_pwm3_grp1", pw_pwm3_pins1), GROUP("pw_pwm_cpu_vol_grp0", pw_pwm_cpu_vol_pins0), GROUP("pw_pwm_cpu_vol_grp1", pw_pwm_cpu_vol_pins1), + GROUP("pw_pwm_cpu_vol_grp2", pw_pwm_cpu_vol_pins2), GROUP("pw_backlight_grp0", pw_backlight_pins0), GROUP("pw_backlight_grp1", pw_backlight_pins1), GROUP("rg_eth_mac_grp", rg_eth_mac_pins), @@ -1026,8 +1191,11 @@ struct atlas7_pin_group altas7_pin_groups[] = { GROUP("sd1_grp", sd1_pins), GROUP("sd1_4bit_grp0", sd1_4bit_pins0), GROUP("sd1_4bit_grp1", sd1_4bit_pins1), - GROUP("sd2_grp0", sd2_pins0), - GROUP("sd2_no_cdb_grp0", sd2_no_cdb_pins0), + GROUP("sd2_basic_grp", sd2_basic_pins), + GROUP("sd2_cdb_grp0", sd2_cdb_pins0), + GROUP("sd2_cdb_grp1", sd2_cdb_pins1), + GROUP("sd2_wpb_grp0", sd2_wpb_pins0), + GROUP("sd2_wpb_grp1", sd2_wpb_pins1), GROUP("sd3_grp", sd3_pins), GROUP("sd5_grp", sd5_pins), GROUP("sd6_grp0", sd6_pins0), @@ -1039,19 +1207,39 @@ struct atlas7_pin_group altas7_pin_groups[] = { GROUP("uart0_grp", uart0_pins), GROUP("uart0_nopause_grp", uart0_nopause_pins), GROUP("uart1_grp", uart1_pins), - GROUP("uart2_grp", uart2_pins), - GROUP("uart3_grp0", uart3_pins0), - GROUP("uart3_grp1", uart3_pins1), - GROUP("uart3_grp2", uart3_pins2), - GROUP("uart3_grp3", uart3_pins3), - GROUP("uart3_nopause_grp0", uart3_nopause_pins0), - GROUP("uart3_nopause_grp1", uart3_nopause_pins1), - GROUP("uart4_grp0", uart4_pins0), - GROUP("uart4_grp1", uart4_pins1), - GROUP("uart4_grp2", uart4_pins2), - GROUP("uart4_nopause_grp", uart4_nopause_pins), - GROUP("usb0_drvvbus_grp", usb0_drvvbus_pins), - GROUP("usb1_drvvbus_grp", usb1_drvvbus_pins), + GROUP("uart2_cts_grp0", uart2_cts_pins0), + GROUP("uart2_cts_grp1", uart2_cts_pins1), + GROUP("uart2_rts_grp0", uart2_rts_pins0), + GROUP("uart2_rts_grp1", uart2_rts_pins1), + GROUP("uart2_rxd_grp0", uart2_rxd_pins0), + GROUP("uart2_rxd_grp1", uart2_rxd_pins1), + GROUP("uart2_rxd_grp2", uart2_rxd_pins2), + GROUP("uart2_txd_grp0", uart2_txd_pins0), + GROUP("uart2_txd_grp1", uart2_txd_pins1), + GROUP("uart2_txd_grp2", uart2_txd_pins2), + GROUP("uart3_cts_grp0", uart3_cts_pins0), + GROUP("uart3_cts_grp1", uart3_cts_pins1), + GROUP("uart3_cts_grp2", uart3_cts_pins2), + GROUP("uart3_rts_grp0", uart3_rts_pins0), + GROUP("uart3_rts_grp1", uart3_rts_pins1), + GROUP("uart3_rts_grp2", uart3_rts_pins2), + GROUP("uart3_rxd_grp0", uart3_rxd_pins0), + GROUP("uart3_rxd_grp1", uart3_rxd_pins1), + GROUP("uart3_rxd_grp2", uart3_rxd_pins2), + GROUP("uart3_txd_grp0", uart3_txd_pins0), + GROUP("uart3_txd_grp1", uart3_txd_pins1), + GROUP("uart3_txd_grp2", uart3_txd_pins2), + GROUP("uart4_basic_grp", uart4_basic_pins), + GROUP("uart4_cts_grp0", uart4_cts_pins0), + GROUP("uart4_cts_grp1", uart4_cts_pins1), + GROUP("uart4_cts_grp2", uart4_cts_pins2), + GROUP("uart4_rts_grp0", uart4_rts_pins0), + GROUP("uart4_rts_grp1", uart4_rts_pins1), + GROUP("uart4_rts_grp2", uart4_rts_pins2), + GROUP("usb0_drvvbus_grp0", usb0_drvvbus_pins0), + GROUP("usb0_drvvbus_grp1", usb0_drvvbus_pins1), + GROUP("usb1_drvvbus_grp0", usb1_drvvbus_pins0), + GROUP("usb1_drvvbus_grp1", usb1_drvvbus_pins1), GROUP("visbus_dout_grp", visbus_dout_pins), GROUP("vi_vip1_grp", vi_vip1_pins), GROUP("vi_vip1_ext_grp", vi_vip1_ext_pins), @@ -1065,23 +1253,90 @@ static const char * const lcd_vip_gpio_grp[] = { "lcd_vip_gpio_grp", }; static const char * const sdio_i2s_gpio_grp[] = { "sdio_i2s_gpio_grp", }; static const char * const sp_rgmii_gpio_grp[] = { "sp_rgmii_gpio_grp", }; static const char * const lvds_gpio_grp[] = { "lvds_gpio_grp", }; -static const char * const uart_nand_gpio_grp[] = { "uart_nand_gpio_grp", }; +static const char * const jtag_uart_nand_gpio_grp[] = { + "jtag_uart_nand_gpio_grp", }; static const char * const rtc_gpio_grp[] = { "rtc_gpio_grp", }; static const char * const audio_ac97_grp[] = { "audio_ac97_grp", }; +static const char * const audio_digmic_grp0[] = { "audio_digmic_grp0", }; +static const char * const audio_digmic_grp1[] = { "audio_digmic_grp1", }; +static const char * const audio_digmic_grp2[] = { "audio_digmic_grp2", }; static const char * const audio_func_dbg_grp[] = { "audio_func_dbg_grp", }; static const char * const audio_i2s_grp[] = { "audio_i2s_grp", }; static const char * const audio_i2s_2ch_grp[] = { "audio_i2s_2ch_grp", }; static const char * const audio_i2s_extclk_grp[] = { "audio_i2s_extclk_grp", }; -static const char * const audio_uart0_grp[] = { "audio_uart0_grp", }; -static const char * const audio_uart1_grp[] = { "audio_uart1_grp", }; -static const char * const audio_uart2_grp0[] = { "audio_uart2_grp0", }; -static const char * const audio_uart2_grp1[] = { "audio_uart2_grp1", }; -static const char * const c_can_trnsvr_grp[] = { "c_can_trnsvr_grp", }; -static const char * const c0_can_grp0[] = { "c0_can_grp0", }; -static const char * const c0_can_grp1[] = { "c0_can_grp1", }; -static const char * const c1_can_grp0[] = { "c1_can_grp0", }; -static const char * const c1_can_grp1[] = { "c1_can_grp1", }; -static const char * const c1_can_grp2[] = { "c1_can_grp2", }; +static const char * const audio_spdif_out_grp0[] = { "audio_spdif_out_grp0", }; +static const char * const audio_spdif_out_grp1[] = { "audio_spdif_out_grp1", }; +static const char * const audio_spdif_out_grp2[] = { "audio_spdif_out_grp2", }; +static const char * const audio_uart0_basic_grp[] = { + "audio_uart0_basic_grp", }; +static const char * const audio_uart0_urfs_grp0[] = { + "audio_uart0_urfs_grp0", }; +static const char * const audio_uart0_urfs_grp1[] = { + "audio_uart0_urfs_grp1", }; +static const char * const audio_uart0_urfs_grp2[] = { + "audio_uart0_urfs_grp2", }; +static const char * const audio_uart0_urfs_grp3[] = { + "audio_uart0_urfs_grp3", }; +static const char * const audio_uart1_basic_grp[] = { + "audio_uart1_basic_grp", }; +static const char * const audio_uart1_urfs_grp0[] = { + "audio_uart1_urfs_grp0", }; +static const char * const audio_uart1_urfs_grp1[] = { + "audio_uart1_urfs_grp1", }; +static const char * const audio_uart1_urfs_grp2[] = { + "audio_uart1_urfs_grp2", }; +static const char * const audio_uart2_urfs_grp0[] = { + "audio_uart2_urfs_grp0", }; +static const char * const audio_uart2_urfs_grp1[] = { + "audio_uart2_urfs_grp1", }; +static const char * const audio_uart2_urfs_grp2[] = { + "audio_uart2_urfs_grp2", }; +static const char * const audio_uart2_urxd_grp0[] = { + "audio_uart2_urxd_grp0", }; +static const char * const audio_uart2_urxd_grp1[] = { + "audio_uart2_urxd_grp1", }; +static const char * const audio_uart2_urxd_grp2[] = { + "audio_uart2_urxd_grp2", }; +static const char * const audio_uart2_usclk_grp0[] = { + "audio_uart2_usclk_grp0", }; +static const char * const audio_uart2_usclk_grp1[] = { + "audio_uart2_usclk_grp1", }; +static const char * const audio_uart2_usclk_grp2[] = { + "audio_uart2_usclk_grp2", }; +static const char * const audio_uart2_utfs_grp0[] = { + "audio_uart2_utfs_grp0", }; +static const char * const audio_uart2_utfs_grp1[] = { + "audio_uart2_utfs_grp1", }; +static const char * const audio_uart2_utfs_grp2[] = { + "audio_uart2_utfs_grp2", }; +static const char * const audio_uart2_utxd_grp0[] = { + "audio_uart2_utxd_grp0", }; +static const char * const audio_uart2_utxd_grp1[] = { + "audio_uart2_utxd_grp1", }; +static const char * const audio_uart2_utxd_grp2[] = { + "audio_uart2_utxd_grp2", }; +static const char * const c_can_trnsvr_en_grp0[] = { "c_can_trnsvr_en_grp0", }; +static const char * const c_can_trnsvr_en_grp1[] = { "c_can_trnsvr_en_grp1", }; +static const char * const c_can_trnsvr_intr_grp[] = { + "c_can_trnsvr_intr_grp", }; +static const char * const c_can_trnsvr_stb_n_grp[] = { + "c_can_trnsvr_stb_n_grp", }; +static const char * const c0_can_rxd_trnsv0_grp[] = { + "c0_can_rxd_trnsv0_grp", }; +static const char * const c0_can_rxd_trnsv1_grp[] = { + "c0_can_rxd_trnsv1_grp", }; +static const char * const c0_can_txd_trnsv0_grp[] = { + "c0_can_txd_trnsv0_grp", }; +static const char * const c0_can_txd_trnsv1_grp[] = { + "c0_can_txd_trnsv1_grp", }; +static const char * const c1_can_rxd_grp0[] = { "c1_can_rxd_grp0", }; +static const char * const c1_can_rxd_grp1[] = { "c1_can_rxd_grp1", }; +static const char * const c1_can_rxd_grp2[] = { "c1_can_rxd_grp2", }; +static const char * const c1_can_rxd_grp3[] = { "c1_can_rxd_grp3", }; +static const char * const c1_can_txd_grp0[] = { "c1_can_txd_grp0", }; +static const char * const c1_can_txd_grp1[] = { "c1_can_txd_grp1", }; +static const char * const c1_can_txd_grp2[] = { "c1_can_txd_grp2", }; +static const char * const c1_can_txd_grp3[] = { "c1_can_txd_grp3", }; static const char * const ca_audio_lpc_grp[] = { "ca_audio_lpc_grp", }; static const char * const ca_bt_lpc_grp[] = { "ca_bt_lpc_grp", }; static const char * const ca_coex_grp[] = { "ca_coex_grp", }; @@ -1135,7 +1390,30 @@ static const char * const gn_trg_shutdown_grp2[] = { "gn_trg_shutdown_grp2", }; static const char * const gn_trg_shutdown_grp3[] = { "gn_trg_shutdown_grp3", }; static const char * const i2c0_grp[] = { "i2c0_grp", }; static const char * const i2c1_grp[] = { "i2c1_grp", }; -static const char * const jtag_grp0[] = { "jtag_grp0", }; +static const char * const i2s0_grp[] = { "i2s0_grp", }; +static const char * const i2s1_basic_grp[] = { "i2s1_basic_grp", }; +static const char * const i2s1_rxd0_grp0[] = { "i2s1_rxd0_grp0", }; +static const char * const i2s1_rxd0_grp1[] = { "i2s1_rxd0_grp1", }; +static const char * const i2s1_rxd0_grp2[] = { "i2s1_rxd0_grp2", }; +static const char * const i2s1_rxd0_grp3[] = { "i2s1_rxd0_grp3", }; +static const char * const i2s1_rxd0_grp4[] = { "i2s1_rxd0_grp4", }; +static const char * const i2s1_rxd1_grp0[] = { "i2s1_rxd1_grp0", }; +static const char * const i2s1_rxd1_grp1[] = { "i2s1_rxd1_grp1", }; +static const char * const i2s1_rxd1_grp2[] = { "i2s1_rxd1_grp2", }; +static const char * const i2s1_rxd1_grp3[] = { "i2s1_rxd1_grp3", }; +static const char * const i2s1_rxd1_grp4[] = { "i2s1_rxd1_grp4", }; +static const char * const jtag_jt_dbg_nsrst_grp[] = { + "jtag_jt_dbg_nsrst_grp", }; +static const char * const jtag_ntrst_grp0[] = { "jtag_ntrst_grp0", }; +static const char * const jtag_ntrst_grp1[] = { "jtag_ntrst_grp1", }; +static const char * const jtag_swdiotms_grp0[] = { "jtag_swdiotms_grp0", }; +static const char * const jtag_swdiotms_grp1[] = { "jtag_swdiotms_grp1", }; +static const char * const jtag_tck_grp0[] = { "jtag_tck_grp0", }; +static const char * const jtag_tck_grp1[] = { "jtag_tck_grp1", }; +static const char * const jtag_tdi_grp0[] = { "jtag_tdi_grp0", }; +static const char * const jtag_tdi_grp1[] = { "jtag_tdi_grp1", }; +static const char * const jtag_tdo_grp0[] = { "jtag_tdo_grp0", }; +static const char * const jtag_tdo_grp1[] = { "jtag_tdo_grp1", }; static const char * const ks_kas_spi_grp0[] = { "ks_kas_spi_grp0", }; static const char * const ld_ldd_grp[] = { "ld_ldd_grp", }; static const char * const ld_ldd_16bit_grp[] = { "ld_ldd_16bit_grp", }; @@ -1160,18 +1438,26 @@ static const char * const pwc_wakeup_src3_grp[] = { "pwc_wakeup_src3_grp", }; static const char * const pw_cko0_grp0[] = { "pw_cko0_grp0", }; static const char * const pw_cko0_grp1[] = { "pw_cko0_grp1", }; static const char * const pw_cko0_grp2[] = { "pw_cko0_grp2", }; +static const char * const pw_cko0_grp3[] = { "pw_cko0_grp3", }; static const char * const pw_cko1_grp0[] = { "pw_cko1_grp0", }; static const char * const pw_cko1_grp1[] = { "pw_cko1_grp1", }; +static const char * const pw_cko1_grp2[] = { "pw_cko1_grp2", }; static const char * const pw_i2s01_clk_grp0[] = { "pw_i2s01_clk_grp0", }; static const char * const pw_i2s01_clk_grp1[] = { "pw_i2s01_clk_grp1", }; -static const char * const pw_pwm0_grp[] = { "pw_pwm0_grp", }; -static const char * const pw_pwm1_grp[] = { "pw_pwm1_grp", }; +static const char * const pw_i2s01_clk_grp2[] = { "pw_i2s01_clk_grp2", }; +static const char * const pw_pwm0_grp0[] = { "pw_pwm0_grp0", }; +static const char * const pw_pwm0_grp1[] = { "pw_pwm0_grp1", }; +static const char * const pw_pwm1_grp0[] = { "pw_pwm1_grp0", }; +static const char * const pw_pwm1_grp1[] = { "pw_pwm1_grp1", }; +static const char * const pw_pwm1_grp2[] = { "pw_pwm1_grp2", }; static const char * const pw_pwm2_grp0[] = { "pw_pwm2_grp0", }; static const char * const pw_pwm2_grp1[] = { "pw_pwm2_grp1", }; +static const char * const pw_pwm2_grp2[] = { "pw_pwm2_grp2", }; static const char * const pw_pwm3_grp0[] = { "pw_pwm3_grp0", }; static const char * const pw_pwm3_grp1[] = { "pw_pwm3_grp1", }; static const char * const pw_pwm_cpu_vol_grp0[] = { "pw_pwm_cpu_vol_grp0", }; static const char * const pw_pwm_cpu_vol_grp1[] = { "pw_pwm_cpu_vol_grp1", }; +static const char * const pw_pwm_cpu_vol_grp2[] = { "pw_pwm_cpu_vol_grp2", }; static const char * const pw_backlight_grp0[] = { "pw_backlight_grp0", }; static const char * const pw_backlight_grp1[] = { "pw_backlight_grp1", }; static const char * const rg_eth_mac_grp[] = { "rg_eth_mac_grp", }; @@ -1187,8 +1473,11 @@ static const char * const sd0_4bit_grp[] = { "sd0_4bit_grp", }; static const char * const sd1_grp[] = { "sd1_grp", }; static const char * const sd1_4bit_grp0[] = { "sd1_4bit_grp0", }; static const char * const sd1_4bit_grp1[] = { "sd1_4bit_grp1", }; -static const char * const sd2_grp0[] = { "sd2_grp0", }; -static const char * const sd2_no_cdb_grp0[] = { "sd2_no_cdb_grp0", }; +static const char * const sd2_basic_grp[] = { "sd2_basic_grp", }; +static const char * const sd2_cdb_grp0[] = { "sd2_cdb_grp0", }; +static const char * const sd2_cdb_grp1[] = { "sd2_cdb_grp1", }; +static const char * const sd2_wpb_grp0[] = { "sd2_wpb_grp0", }; +static const char * const sd2_wpb_grp1[] = { "sd2_wpb_grp1", }; static const char * const sd3_grp[] = { "sd3_grp", }; static const char * const sd5_grp[] = { "sd5_grp", }; static const char * const sd6_grp0[] = { "sd6_grp0", }; @@ -1200,19 +1489,39 @@ static const char * const tpiu_trace_grp[] = { "tpiu_trace_grp", }; static const char * const uart0_grp[] = { "uart0_grp", }; static const char * const uart0_nopause_grp[] = { "uart0_nopause_grp", }; static const char * const uart1_grp[] = { "uart1_grp", }; -static const char * const uart2_grp[] = { "uart2_grp", }; -static const char * const uart3_grp0[] = { "uart3_grp0", }; -static const char * const uart3_grp1[] = { "uart3_grp1", }; -static const char * const uart3_grp2[] = { "uart3_grp2", }; -static const char * const uart3_grp3[] = { "uart3_grp3", }; -static const char * const uart3_nopause_grp0[] = { "uart3_nopause_grp0", }; -static const char * const uart3_nopause_grp1[] = { "uart3_nopause_grp1", }; -static const char * const uart4_grp0[] = { "uart4_grp0", }; -static const char * const uart4_grp1[] = { "uart4_grp1", }; -static const char * const uart4_grp2[] = { "uart4_grp2", }; -static const char * const uart4_nopause_grp[] = { "uart4_nopause_grp", }; -static const char * const usb0_drvvbus_grp[] = { "usb0_drvvbus_grp", }; -static const char * const usb1_drvvbus_grp[] = { "usb1_drvvbus_grp", }; +static const char * const uart2_cts_grp0[] = { "uart2_cts_grp0", }; +static const char * const uart2_cts_grp1[] = { "uart2_cts_grp1", }; +static const char * const uart2_rts_grp0[] = { "uart2_rts_grp0", }; +static const char * const uart2_rts_grp1[] = { "uart2_rts_grp1", }; +static const char * const uart2_rxd_grp0[] = { "uart2_rxd_grp0", }; +static const char * const uart2_rxd_grp1[] = { "uart2_rxd_grp1", }; +static const char * const uart2_rxd_grp2[] = { "uart2_rxd_grp2", }; +static const char * const uart2_txd_grp0[] = { "uart2_txd_grp0", }; +static const char * const uart2_txd_grp1[] = { "uart2_txd_grp1", }; +static const char * const uart2_txd_grp2[] = { "uart2_txd_grp2", }; +static const char * const uart3_cts_grp0[] = { "uart3_cts_grp0", }; +static const char * const uart3_cts_grp1[] = { "uart3_cts_grp1", }; +static const char * const uart3_cts_grp2[] = { "uart3_cts_grp2", }; +static const char * const uart3_rts_grp0[] = { "uart3_rts_grp0", }; +static const char * const uart3_rts_grp1[] = { "uart3_rts_grp1", }; +static const char * const uart3_rts_grp2[] = { "uart3_rts_grp2", }; +static const char * const uart3_rxd_grp0[] = { "uart3_rxd_grp0", }; +static const char * const uart3_rxd_grp1[] = { "uart3_rxd_grp1", }; +static const char * const uart3_rxd_grp2[] = { "uart3_rxd_grp2", }; +static const char * const uart3_txd_grp0[] = { "uart3_txd_grp0", }; +static const char * const uart3_txd_grp1[] = { "uart3_txd_grp1", }; +static const char * const uart3_txd_grp2[] = { "uart3_txd_grp2", }; +static const char * const uart4_basic_grp[] = { "uart4_basic_grp", }; +static const char * const uart4_cts_grp0[] = { "uart4_cts_grp0", }; +static const char * const uart4_cts_grp1[] = { "uart4_cts_grp1", }; +static const char * const uart4_cts_grp2[] = { "uart4_cts_grp2", }; +static const char * const uart4_rts_grp0[] = { "uart4_rts_grp0", }; +static const char * const uart4_rts_grp1[] = { "uart4_rts_grp1", }; +static const char * const uart4_rts_grp2[] = { "uart4_rts_grp2", }; +static const char * const usb0_drvvbus_grp0[] = { "usb0_drvvbus_grp0", }; +static const char * const usb0_drvvbus_grp1[] = { "usb0_drvvbus_grp1", }; +static const char * const usb1_drvvbus_grp0[] = { "usb1_drvvbus_grp0", }; +static const char * const usb1_drvvbus_grp1[] = { "usb1_drvvbus_grp1", }; static const char * const visbus_dout_grp[] = { "visbus_dout_grp", }; static const char * const vi_vip1_grp[] = { "vi_vip1_grp", }; static const char * const vi_vip1_ext_grp[] = { "vi_vip1_ext_grp", }; @@ -1376,7 +1685,7 @@ static struct atlas7_grp_mux lvds_gpio_grp_mux = { .pad_mux_list = lvds_gpio_grp_pad_mux, }; -static struct atlas7_pad_mux uart_nand_gpio_grp_pad_mux[] = { +static struct atlas7_pad_mux jtag_uart_nand_gpio_grp_pad_mux[] = { MUX(1, 44, 0, N, N, N, N), MUX(1, 43, 0, N, N, N, N), MUX(1, 42, 0, N, N, N, N), @@ -1401,11 +1710,16 @@ static struct atlas7_pad_mux uart_nand_gpio_grp_pad_mux[] = { MUX(1, 138, 0, N, N, N, N), MUX(1, 139, 0, N, N, N, N), MUX(1, 140, 0, N, N, N, N), + MUX(1, 159, 0, N, N, N, N), + MUX(1, 160, 0, N, N, N, N), + MUX(1, 161, 0, N, N, N, N), + MUX(1, 162, 0, N, N, N, N), + MUX(1, 163, 0, N, N, N, N), }; -static struct atlas7_grp_mux uart_nand_gpio_grp_mux = { - .pad_mux_count = ARRAY_SIZE(uart_nand_gpio_grp_pad_mux), - .pad_mux_list = uart_nand_gpio_grp_pad_mux, +static struct atlas7_grp_mux jtag_uart_nand_gpio_grp_mux = { + .pad_mux_count = ARRAY_SIZE(jtag_uart_nand_gpio_grp_pad_mux), + .pad_mux_list = jtag_uart_nand_gpio_grp_pad_mux, }; static struct atlas7_pad_mux rtc_gpio_grp_pad_mux[] = { @@ -1422,6 +1736,7 @@ static struct atlas7_pad_mux rtc_gpio_grp_pad_mux[] = { MUX(0, 15, 0, N, N, N, N), MUX(0, 16, 0, N, N, N, N), MUX(0, 17, 0, N, N, N, N), + MUX(0, 9, 0, N, N, N, N), }; static struct atlas7_grp_mux rtc_gpio_grp_mux = { @@ -1441,6 +1756,33 @@ static struct atlas7_grp_mux audio_ac97_grp_mux = { .pad_mux_list = audio_ac97_grp_pad_mux, }; +static struct atlas7_pad_mux audio_digmic_grp0_pad_mux[] = { + MUX(1, 51, 3, 0xa10, 20, 0xa90, 20), +}; + +static struct atlas7_grp_mux audio_digmic_grp0_mux = { + .pad_mux_count = ARRAY_SIZE(audio_digmic_grp0_pad_mux), + .pad_mux_list = audio_digmic_grp0_pad_mux, +}; + +static struct atlas7_pad_mux audio_digmic_grp1_pad_mux[] = { + MUX(1, 122, 5, 0xa10, 20, 0xa90, 20), +}; + +static struct atlas7_grp_mux audio_digmic_grp1_mux = { + .pad_mux_count = ARRAY_SIZE(audio_digmic_grp1_pad_mux), + .pad_mux_list = audio_digmic_grp1_pad_mux, +}; + +static struct atlas7_pad_mux audio_digmic_grp2_pad_mux[] = { + MUX(1, 161, 7, 0xa10, 20, 0xa90, 20), +}; + +static struct atlas7_grp_mux audio_digmic_grp2_mux = { + .pad_mux_count = ARRAY_SIZE(audio_digmic_grp2_pad_mux), + .pad_mux_list = audio_digmic_grp2_pad_mux, +}; + static struct atlas7_pad_mux audio_func_dbg_grp_pad_mux[] = { MUX(1, 141, 4, N, N, N, N), MUX(1, 144, 4, N, N, N, N), @@ -1512,111 +1854,397 @@ static struct atlas7_grp_mux audio_i2s_extclk_grp_mux = { .pad_mux_list = audio_i2s_extclk_grp_pad_mux, }; -static struct atlas7_pad_mux audio_uart0_grp_pad_mux[] = { +static struct atlas7_pad_mux audio_spdif_out_grp0_pad_mux[] = { + MUX(1, 112, 3, N, N, N, N), +}; + +static struct atlas7_grp_mux audio_spdif_out_grp0_mux = { + .pad_mux_count = ARRAY_SIZE(audio_spdif_out_grp0_pad_mux), + .pad_mux_list = audio_spdif_out_grp0_pad_mux, +}; + +static struct atlas7_pad_mux audio_spdif_out_grp1_pad_mux[] = { + MUX(1, 116, 3, N, N, N, N), +}; + +static struct atlas7_grp_mux audio_spdif_out_grp1_mux = { + .pad_mux_count = ARRAY_SIZE(audio_spdif_out_grp1_pad_mux), + .pad_mux_list = audio_spdif_out_grp1_pad_mux, +}; + +static struct atlas7_pad_mux audio_spdif_out_grp2_pad_mux[] = { + MUX(1, 142, 3, N, N, N, N), +}; + +static struct atlas7_grp_mux audio_spdif_out_grp2_mux = { + .pad_mux_count = ARRAY_SIZE(audio_spdif_out_grp2_pad_mux), + .pad_mux_list = audio_spdif_out_grp2_pad_mux, +}; + +static struct atlas7_pad_mux audio_uart0_basic_grp_pad_mux[] = { MUX(1, 143, 1, N, N, N, N), MUX(1, 142, 1, N, N, N, N), MUX(1, 141, 1, N, N, N, N), MUX(1, 144, 1, N, N, N, N), }; -static struct atlas7_grp_mux audio_uart0_grp_mux = { - .pad_mux_count = ARRAY_SIZE(audio_uart0_grp_pad_mux), - .pad_mux_list = audio_uart0_grp_pad_mux, +static struct atlas7_grp_mux audio_uart0_basic_grp_mux = { + .pad_mux_count = ARRAY_SIZE(audio_uart0_basic_grp_pad_mux), + .pad_mux_list = audio_uart0_basic_grp_pad_mux, +}; + +static struct atlas7_pad_mux audio_uart0_urfs_grp0_pad_mux[] = { + MUX(1, 117, 5, 0xa10, 28, 0xa90, 28), }; -static struct atlas7_pad_mux audio_uart1_grp_pad_mux[] = { - MUX(1, 147, 1, N, N, N, N), - MUX(1, 146, 1, N, N, N, N), - MUX(1, 145, 1, N, N, N, N), - MUX(1, 148, 1, N, N, N, N), +static struct atlas7_grp_mux audio_uart0_urfs_grp0_mux = { + .pad_mux_count = ARRAY_SIZE(audio_uart0_urfs_grp0_pad_mux), + .pad_mux_list = audio_uart0_urfs_grp0_pad_mux, }; -static struct atlas7_grp_mux audio_uart1_grp_mux = { - .pad_mux_count = ARRAY_SIZE(audio_uart1_grp_pad_mux), - .pad_mux_list = audio_uart1_grp_pad_mux, +static struct atlas7_pad_mux audio_uart0_urfs_grp1_pad_mux[] = { + MUX(1, 139, 3, 0xa10, 28, 0xa90, 28), }; -static struct atlas7_pad_mux audio_uart2_grp0_pad_mux[] = { +static struct atlas7_grp_mux audio_uart0_urfs_grp1_mux = { + .pad_mux_count = ARRAY_SIZE(audio_uart0_urfs_grp1_pad_mux), + .pad_mux_list = audio_uart0_urfs_grp1_pad_mux, +}; + +static struct atlas7_pad_mux audio_uart0_urfs_grp2_pad_mux[] = { + MUX(1, 163, 3, 0xa10, 28, 0xa90, 28), +}; + +static struct atlas7_grp_mux audio_uart0_urfs_grp2_mux = { + .pad_mux_count = ARRAY_SIZE(audio_uart0_urfs_grp2_pad_mux), + .pad_mux_list = audio_uart0_urfs_grp2_pad_mux, +}; + +static struct atlas7_pad_mux audio_uart0_urfs_grp3_pad_mux[] = { + MUX(1, 162, 6, 0xa10, 28, 0xa90, 28), +}; + +static struct atlas7_grp_mux audio_uart0_urfs_grp3_mux = { + .pad_mux_count = ARRAY_SIZE(audio_uart0_urfs_grp3_pad_mux), + .pad_mux_list = audio_uart0_urfs_grp3_pad_mux, +}; + +static struct atlas7_pad_mux audio_uart1_basic_grp_pad_mux[] = { + MUX(1, 147, 1, 0xa10, 24, 0xa90, 24), + MUX(1, 146, 1, 0xa10, 25, 0xa90, 25), + MUX(1, 145, 1, 0xa10, 23, 0xa90, 23), + MUX(1, 148, 1, 0xa10, 22, 0xa90, 22), +}; + +static struct atlas7_grp_mux audio_uart1_basic_grp_mux = { + .pad_mux_count = ARRAY_SIZE(audio_uart1_basic_grp_pad_mux), + .pad_mux_list = audio_uart1_basic_grp_pad_mux, +}; + +static struct atlas7_pad_mux audio_uart1_urfs_grp0_pad_mux[] = { + MUX(1, 117, 6, 0xa10, 29, 0xa90, 29), +}; + +static struct atlas7_grp_mux audio_uart1_urfs_grp0_mux = { + .pad_mux_count = ARRAY_SIZE(audio_uart1_urfs_grp0_pad_mux), + .pad_mux_list = audio_uart1_urfs_grp0_pad_mux, +}; + +static struct atlas7_pad_mux audio_uart1_urfs_grp1_pad_mux[] = { + MUX(1, 140, 3, 0xa10, 29, 0xa90, 29), +}; + +static struct atlas7_grp_mux audio_uart1_urfs_grp1_mux = { + .pad_mux_count = ARRAY_SIZE(audio_uart1_urfs_grp1_pad_mux), + .pad_mux_list = audio_uart1_urfs_grp1_pad_mux, +}; + +static struct atlas7_pad_mux audio_uart1_urfs_grp2_pad_mux[] = { + MUX(1, 163, 4, 0xa10, 29, 0xa90, 29), +}; + +static struct atlas7_grp_mux audio_uart1_urfs_grp2_mux = { + .pad_mux_count = ARRAY_SIZE(audio_uart1_urfs_grp2_pad_mux), + .pad_mux_list = audio_uart1_urfs_grp2_pad_mux, +}; + +static struct atlas7_pad_mux audio_uart2_urfs_grp0_pad_mux[] = { + MUX(1, 139, 4, 0xa10, 30, 0xa90, 30), +}; + +static struct atlas7_grp_mux audio_uart2_urfs_grp0_mux = { + .pad_mux_count = ARRAY_SIZE(audio_uart2_urfs_grp0_pad_mux), + .pad_mux_list = audio_uart2_urfs_grp0_pad_mux, +}; + +static struct atlas7_pad_mux audio_uart2_urfs_grp1_pad_mux[] = { + MUX(1, 163, 6, 0xa10, 30, 0xa90, 30), +}; + +static struct atlas7_grp_mux audio_uart2_urfs_grp1_mux = { + .pad_mux_count = ARRAY_SIZE(audio_uart2_urfs_grp1_pad_mux), + .pad_mux_list = audio_uart2_urfs_grp1_pad_mux, +}; + +static struct atlas7_pad_mux audio_uart2_urfs_grp2_pad_mux[] = { + MUX(1, 96, 3, 0xa10, 30, 0xa90, 30), +}; + +static struct atlas7_grp_mux audio_uart2_urfs_grp2_mux = { + .pad_mux_count = ARRAY_SIZE(audio_uart2_urfs_grp2_pad_mux), + .pad_mux_list = audio_uart2_urfs_grp2_pad_mux, +}; + +static struct atlas7_pad_mux audio_uart2_urxd_grp0_pad_mux[] = { MUX(1, 20, 2, 0xa00, 24, 0xa80, 24), - MUX(1, 21, 2, 0xa00, 25, 0xa80, 25), - MUX(1, 19, 2, 0xa00, 23, 0xa80, 23), - MUX(1, 18, 2, 0xa00, 22, 0xa80, 22), }; -static struct atlas7_grp_mux audio_uart2_grp0_mux = { - .pad_mux_count = ARRAY_SIZE(audio_uart2_grp0_pad_mux), - .pad_mux_list = audio_uart2_grp0_pad_mux, +static struct atlas7_grp_mux audio_uart2_urxd_grp0_mux = { + .pad_mux_count = ARRAY_SIZE(audio_uart2_urxd_grp0_pad_mux), + .pad_mux_list = audio_uart2_urxd_grp0_pad_mux, }; -static struct atlas7_pad_mux audio_uart2_grp1_pad_mux[] = { +static struct atlas7_pad_mux audio_uart2_urxd_grp1_pad_mux[] = { MUX(1, 109, 2, 0xa00, 24, 0xa80, 24), - MUX(1, 110, 2, 0xa00, 25, 0xa80, 25), +}; + +static struct atlas7_grp_mux audio_uart2_urxd_grp1_mux = { + .pad_mux_count = ARRAY_SIZE(audio_uart2_urxd_grp1_pad_mux), + .pad_mux_list = audio_uart2_urxd_grp1_pad_mux, +}; + +static struct atlas7_pad_mux audio_uart2_urxd_grp2_pad_mux[] = { + MUX(1, 93, 3, 0xa00, 24, 0xa80, 24), +}; + +static struct atlas7_grp_mux audio_uart2_urxd_grp2_mux = { + .pad_mux_count = ARRAY_SIZE(audio_uart2_urxd_grp2_pad_mux), + .pad_mux_list = audio_uart2_urxd_grp2_pad_mux, +}; + +static struct atlas7_pad_mux audio_uart2_usclk_grp0_pad_mux[] = { + MUX(1, 19, 2, 0xa00, 23, 0xa80, 23), +}; + +static struct atlas7_grp_mux audio_uart2_usclk_grp0_mux = { + .pad_mux_count = ARRAY_SIZE(audio_uart2_usclk_grp0_pad_mux), + .pad_mux_list = audio_uart2_usclk_grp0_pad_mux, +}; + +static struct atlas7_pad_mux audio_uart2_usclk_grp1_pad_mux[] = { MUX(1, 101, 2, 0xa00, 23, 0xa80, 23), +}; + +static struct atlas7_grp_mux audio_uart2_usclk_grp1_mux = { + .pad_mux_count = ARRAY_SIZE(audio_uart2_usclk_grp1_pad_mux), + .pad_mux_list = audio_uart2_usclk_grp1_pad_mux, +}; + +static struct atlas7_pad_mux audio_uart2_usclk_grp2_pad_mux[] = { + MUX(1, 91, 3, 0xa00, 23, 0xa80, 23), +}; + +static struct atlas7_grp_mux audio_uart2_usclk_grp2_mux = { + .pad_mux_count = ARRAY_SIZE(audio_uart2_usclk_grp2_pad_mux), + .pad_mux_list = audio_uart2_usclk_grp2_pad_mux, +}; + +static struct atlas7_pad_mux audio_uart2_utfs_grp0_pad_mux[] = { + MUX(1, 18, 2, 0xa00, 22, 0xa80, 22), +}; + +static struct atlas7_grp_mux audio_uart2_utfs_grp0_mux = { + .pad_mux_count = ARRAY_SIZE(audio_uart2_utfs_grp0_pad_mux), + .pad_mux_list = audio_uart2_utfs_grp0_pad_mux, +}; + +static struct atlas7_pad_mux audio_uart2_utfs_grp1_pad_mux[] = { MUX(1, 111, 2, 0xa00, 22, 0xa80, 22), }; -static struct atlas7_grp_mux audio_uart2_grp1_mux = { - .pad_mux_count = ARRAY_SIZE(audio_uart2_grp1_pad_mux), - .pad_mux_list = audio_uart2_grp1_pad_mux, +static struct atlas7_grp_mux audio_uart2_utfs_grp1_mux = { + .pad_mux_count = ARRAY_SIZE(audio_uart2_utfs_grp1_pad_mux), + .pad_mux_list = audio_uart2_utfs_grp1_pad_mux, +}; + +static struct atlas7_pad_mux audio_uart2_utfs_grp2_pad_mux[] = { + MUX(1, 94, 3, 0xa00, 22, 0xa80, 22), +}; + +static struct atlas7_grp_mux audio_uart2_utfs_grp2_mux = { + .pad_mux_count = ARRAY_SIZE(audio_uart2_utfs_grp2_pad_mux), + .pad_mux_list = audio_uart2_utfs_grp2_pad_mux, +}; + +static struct atlas7_pad_mux audio_uart2_utxd_grp0_pad_mux[] = { + MUX(1, 21, 2, 0xa00, 25, 0xa80, 25), +}; + +static struct atlas7_grp_mux audio_uart2_utxd_grp0_mux = { + .pad_mux_count = ARRAY_SIZE(audio_uart2_utxd_grp0_pad_mux), + .pad_mux_list = audio_uart2_utxd_grp0_pad_mux, +}; + +static struct atlas7_pad_mux audio_uart2_utxd_grp1_pad_mux[] = { + MUX(1, 110, 2, 0xa00, 25, 0xa80, 25), +}; + +static struct atlas7_grp_mux audio_uart2_utxd_grp1_mux = { + .pad_mux_count = ARRAY_SIZE(audio_uart2_utxd_grp1_pad_mux), + .pad_mux_list = audio_uart2_utxd_grp1_pad_mux, +}; + +static struct atlas7_pad_mux audio_uart2_utxd_grp2_pad_mux[] = { + MUX(1, 92, 3, 0xa00, 25, 0xa80, 25), +}; + +static struct atlas7_grp_mux audio_uart2_utxd_grp2_mux = { + .pad_mux_count = ARRAY_SIZE(audio_uart2_utxd_grp2_pad_mux), + .pad_mux_list = audio_uart2_utxd_grp2_pad_mux, +}; + +static struct atlas7_pad_mux c_can_trnsvr_en_grp0_pad_mux[] = { + MUX(0, 2, 6, N, N, N, N), }; -static struct atlas7_pad_mux c_can_trnsvr_grp_pad_mux[] = { +static struct atlas7_grp_mux c_can_trnsvr_en_grp0_mux = { + .pad_mux_count = ARRAY_SIZE(c_can_trnsvr_en_grp0_pad_mux), + .pad_mux_list = c_can_trnsvr_en_grp0_pad_mux, +}; + +static struct atlas7_pad_mux c_can_trnsvr_en_grp1_pad_mux[] = { + MUX(0, 0, 2, N, N, N, N), +}; + +static struct atlas7_grp_mux c_can_trnsvr_en_grp1_mux = { + .pad_mux_count = ARRAY_SIZE(c_can_trnsvr_en_grp1_pad_mux), + .pad_mux_list = c_can_trnsvr_en_grp1_pad_mux, +}; + +static struct atlas7_pad_mux c_can_trnsvr_intr_grp_pad_mux[] = { MUX(0, 1, 2, N, N, N, N), }; -static struct atlas7_grp_mux c_can_trnsvr_grp_mux = { - .pad_mux_count = ARRAY_SIZE(c_can_trnsvr_grp_pad_mux), - .pad_mux_list = c_can_trnsvr_grp_pad_mux, +static struct atlas7_grp_mux c_can_trnsvr_intr_grp_mux = { + .pad_mux_count = ARRAY_SIZE(c_can_trnsvr_intr_grp_pad_mux), + .pad_mux_list = c_can_trnsvr_intr_grp_pad_mux, }; -static struct atlas7_pad_mux c0_can_grp0_pad_mux[] = { +static struct atlas7_pad_mux c_can_trnsvr_stb_n_grp_pad_mux[] = { + MUX(0, 3, 6, N, N, N, N), +}; + +static struct atlas7_grp_mux c_can_trnsvr_stb_n_grp_mux = { + .pad_mux_count = ARRAY_SIZE(c_can_trnsvr_stb_n_grp_pad_mux), + .pad_mux_list = c_can_trnsvr_stb_n_grp_pad_mux, +}; + +static struct atlas7_pad_mux c0_can_rxd_trnsv0_grp_pad_mux[] = { MUX(0, 11, 1, 0xa08, 9, 0xa88, 9), +}; + +static struct atlas7_grp_mux c0_can_rxd_trnsv0_grp_mux = { + .pad_mux_count = ARRAY_SIZE(c0_can_rxd_trnsv0_grp_pad_mux), + .pad_mux_list = c0_can_rxd_trnsv0_grp_pad_mux, +}; + +static struct atlas7_pad_mux c0_can_rxd_trnsv1_grp_pad_mux[] = { + MUX(0, 2, 5, 0xa10, 9, 0xa90, 9), +}; + +static struct atlas7_grp_mux c0_can_rxd_trnsv1_grp_mux = { + .pad_mux_count = ARRAY_SIZE(c0_can_rxd_trnsv1_grp_pad_mux), + .pad_mux_list = c0_can_rxd_trnsv1_grp_pad_mux, +}; + +static struct atlas7_pad_mux c0_can_txd_trnsv0_grp_pad_mux[] = { MUX(0, 10, 1, N, N, N, N), }; -static struct atlas7_grp_mux c0_can_grp0_mux = { - .pad_mux_count = ARRAY_SIZE(c0_can_grp0_pad_mux), - .pad_mux_list = c0_can_grp0_pad_mux, +static struct atlas7_grp_mux c0_can_txd_trnsv0_grp_mux = { + .pad_mux_count = ARRAY_SIZE(c0_can_txd_trnsv0_grp_pad_mux), + .pad_mux_list = c0_can_txd_trnsv0_grp_pad_mux, }; -static struct atlas7_pad_mux c0_can_grp1_pad_mux[] = { - MUX(0, 2, 5, 0xa08, 9, 0xa88, 9), +static struct atlas7_pad_mux c0_can_txd_trnsv1_grp_pad_mux[] = { MUX(0, 3, 5, N, N, N, N), }; -static struct atlas7_grp_mux c0_can_grp1_mux = { - .pad_mux_count = ARRAY_SIZE(c0_can_grp1_pad_mux), - .pad_mux_list = c0_can_grp1_pad_mux, +static struct atlas7_grp_mux c0_can_txd_trnsv1_grp_mux = { + .pad_mux_count = ARRAY_SIZE(c0_can_txd_trnsv1_grp_pad_mux), + .pad_mux_list = c0_can_txd_trnsv1_grp_pad_mux, }; -static struct atlas7_pad_mux c1_can_grp0_pad_mux[] = { +static struct atlas7_pad_mux c1_can_rxd_grp0_pad_mux[] = { MUX(1, 138, 2, 0xa00, 4, 0xa80, 4), - MUX(1, 137, 2, N, N, N, N), }; -static struct atlas7_grp_mux c1_can_grp0_mux = { - .pad_mux_count = ARRAY_SIZE(c1_can_grp0_pad_mux), - .pad_mux_list = c1_can_grp0_pad_mux, +static struct atlas7_grp_mux c1_can_rxd_grp0_mux = { + .pad_mux_count = ARRAY_SIZE(c1_can_rxd_grp0_pad_mux), + .pad_mux_list = c1_can_rxd_grp0_pad_mux, }; -static struct atlas7_pad_mux c1_can_grp1_pad_mux[] = { +static struct atlas7_pad_mux c1_can_rxd_grp1_pad_mux[] = { MUX(1, 147, 2, 0xa00, 4, 0xa80, 4), - MUX(1, 146, 2, N, N, N, N), }; -static struct atlas7_grp_mux c1_can_grp1_mux = { - .pad_mux_count = ARRAY_SIZE(c1_can_grp1_pad_mux), - .pad_mux_list = c1_can_grp1_pad_mux, +static struct atlas7_grp_mux c1_can_rxd_grp1_mux = { + .pad_mux_count = ARRAY_SIZE(c1_can_rxd_grp1_pad_mux), + .pad_mux_list = c1_can_rxd_grp1_pad_mux, }; -static struct atlas7_pad_mux c1_can_grp2_pad_mux[] = { +static struct atlas7_pad_mux c1_can_rxd_grp2_pad_mux[] = { MUX(0, 2, 2, 0xa00, 4, 0xa80, 4), +}; + +static struct atlas7_grp_mux c1_can_rxd_grp2_mux = { + .pad_mux_count = ARRAY_SIZE(c1_can_rxd_grp2_pad_mux), + .pad_mux_list = c1_can_rxd_grp2_pad_mux, +}; + +static struct atlas7_pad_mux c1_can_rxd_grp3_pad_mux[] = { + MUX(1, 162, 4, 0xa00, 4, 0xa80, 4), +}; + +static struct atlas7_grp_mux c1_can_rxd_grp3_mux = { + .pad_mux_count = ARRAY_SIZE(c1_can_rxd_grp3_pad_mux), + .pad_mux_list = c1_can_rxd_grp3_pad_mux, +}; + +static struct atlas7_pad_mux c1_can_txd_grp0_pad_mux[] = { + MUX(1, 137, 2, N, N, N, N), +}; + +static struct atlas7_grp_mux c1_can_txd_grp0_mux = { + .pad_mux_count = ARRAY_SIZE(c1_can_txd_grp0_pad_mux), + .pad_mux_list = c1_can_txd_grp0_pad_mux, +}; + +static struct atlas7_pad_mux c1_can_txd_grp1_pad_mux[] = { + MUX(1, 146, 2, N, N, N, N), +}; + +static struct atlas7_grp_mux c1_can_txd_grp1_mux = { + .pad_mux_count = ARRAY_SIZE(c1_can_txd_grp1_pad_mux), + .pad_mux_list = c1_can_txd_grp1_pad_mux, +}; + +static struct atlas7_pad_mux c1_can_txd_grp2_pad_mux[] = { MUX(0, 3, 2, N, N, N, N), }; -static struct atlas7_grp_mux c1_can_grp2_mux = { - .pad_mux_count = ARRAY_SIZE(c1_can_grp2_pad_mux), - .pad_mux_list = c1_can_grp2_pad_mux, +static struct atlas7_grp_mux c1_can_txd_grp2_mux = { + .pad_mux_count = ARRAY_SIZE(c1_can_txd_grp2_pad_mux), + .pad_mux_list = c1_can_txd_grp2_pad_mux, +}; + +static struct atlas7_pad_mux c1_can_txd_grp3_pad_mux[] = { + MUX(1, 161, 4, N, N, N, N), +}; + +static struct atlas7_grp_mux c1_can_txd_grp3_mux = { + .pad_mux_count = ARRAY_SIZE(c1_can_txd_grp3_pad_mux), + .pad_mux_list = c1_can_txd_grp3_pad_mux, }; static struct atlas7_pad_mux ca_audio_lpc_grp_pad_mux[] = { @@ -2198,18 +2826,215 @@ static struct atlas7_grp_mux i2c1_grp_mux = { .pad_mux_list = i2c1_grp_pad_mux, }; -static struct atlas7_pad_mux jtag_grp0_pad_mux[] = { +static struct atlas7_pad_mux i2s0_grp_pad_mux[] = { + MUX(1, 91, 2, 0xa10, 12, 0xa90, 12), + MUX(1, 93, 2, 0xa10, 13, 0xa90, 13), + MUX(1, 94, 2, 0xa10, 14, 0xa90, 14), + MUX(1, 92, 2, 0xa10, 15, 0xa90, 15), +}; + +static struct atlas7_grp_mux i2s0_grp_mux = { + .pad_mux_count = ARRAY_SIZE(i2s0_grp_pad_mux), + .pad_mux_list = i2s0_grp_pad_mux, +}; + +static struct atlas7_pad_mux i2s1_basic_grp_pad_mux[] = { + MUX(1, 95, 2, 0xa10, 16, 0xa90, 16), + MUX(1, 96, 2, 0xa10, 19, 0xa90, 19), +}; + +static struct atlas7_grp_mux i2s1_basic_grp_mux = { + .pad_mux_count = ARRAY_SIZE(i2s1_basic_grp_pad_mux), + .pad_mux_list = i2s1_basic_grp_pad_mux, +}; + +static struct atlas7_pad_mux i2s1_rxd0_grp0_pad_mux[] = { + MUX(1, 61, 4, 0xa10, 17, 0xa90, 17), +}; + +static struct atlas7_grp_mux i2s1_rxd0_grp0_mux = { + .pad_mux_count = ARRAY_SIZE(i2s1_rxd0_grp0_pad_mux), + .pad_mux_list = i2s1_rxd0_grp0_pad_mux, +}; + +static struct atlas7_pad_mux i2s1_rxd0_grp1_pad_mux[] = { + MUX(1, 131, 4, 0xa10, 17, 0xa90, 17), +}; + +static struct atlas7_grp_mux i2s1_rxd0_grp1_mux = { + .pad_mux_count = ARRAY_SIZE(i2s1_rxd0_grp1_pad_mux), + .pad_mux_list = i2s1_rxd0_grp1_pad_mux, +}; + +static struct atlas7_pad_mux i2s1_rxd0_grp2_pad_mux[] = { + MUX(1, 129, 2, 0xa10, 17, 0xa90, 17), +}; + +static struct atlas7_grp_mux i2s1_rxd0_grp2_mux = { + .pad_mux_count = ARRAY_SIZE(i2s1_rxd0_grp2_pad_mux), + .pad_mux_list = i2s1_rxd0_grp2_pad_mux, +}; + +static struct atlas7_pad_mux i2s1_rxd0_grp3_pad_mux[] = { + MUX(1, 117, 7, 0xa10, 17, 0xa90, 17), +}; + +static struct atlas7_grp_mux i2s1_rxd0_grp3_mux = { + .pad_mux_count = ARRAY_SIZE(i2s1_rxd0_grp3_pad_mux), + .pad_mux_list = i2s1_rxd0_grp3_pad_mux, +}; + +static struct atlas7_pad_mux i2s1_rxd0_grp4_pad_mux[] = { + MUX(1, 83, 4, 0xa10, 17, 0xa90, 17), +}; + +static struct atlas7_grp_mux i2s1_rxd0_grp4_mux = { + .pad_mux_count = ARRAY_SIZE(i2s1_rxd0_grp4_pad_mux), + .pad_mux_list = i2s1_rxd0_grp4_pad_mux, +}; + +static struct atlas7_pad_mux i2s1_rxd1_grp0_pad_mux[] = { + MUX(1, 72, 4, 0xa10, 18, 0xa90, 18), +}; + +static struct atlas7_grp_mux i2s1_rxd1_grp0_mux = { + .pad_mux_count = ARRAY_SIZE(i2s1_rxd1_grp0_pad_mux), + .pad_mux_list = i2s1_rxd1_grp0_pad_mux, +}; + +static struct atlas7_pad_mux i2s1_rxd1_grp1_pad_mux[] = { + MUX(1, 132, 4, 0xa10, 18, 0xa90, 18), +}; + +static struct atlas7_grp_mux i2s1_rxd1_grp1_mux = { + .pad_mux_count = ARRAY_SIZE(i2s1_rxd1_grp1_pad_mux), + .pad_mux_list = i2s1_rxd1_grp1_pad_mux, +}; + +static struct atlas7_pad_mux i2s1_rxd1_grp2_pad_mux[] = { + MUX(1, 130, 2, 0xa10, 18, 0xa90, 18), +}; + +static struct atlas7_grp_mux i2s1_rxd1_grp2_mux = { + .pad_mux_count = ARRAY_SIZE(i2s1_rxd1_grp2_pad_mux), + .pad_mux_list = i2s1_rxd1_grp2_pad_mux, +}; + +static struct atlas7_pad_mux i2s1_rxd1_grp3_pad_mux[] = { + MUX(1, 118, 7, 0xa10, 18, 0xa90, 18), +}; + +static struct atlas7_grp_mux i2s1_rxd1_grp3_mux = { + .pad_mux_count = ARRAY_SIZE(i2s1_rxd1_grp3_pad_mux), + .pad_mux_list = i2s1_rxd1_grp3_pad_mux, +}; + +static struct atlas7_pad_mux i2s1_rxd1_grp4_pad_mux[] = { + MUX(1, 84, 4, 0xa10, 18, 0xa90, 18), +}; + +static struct atlas7_grp_mux i2s1_rxd1_grp4_mux = { + .pad_mux_count = ARRAY_SIZE(i2s1_rxd1_grp4_pad_mux), + .pad_mux_list = i2s1_rxd1_grp4_pad_mux, +}; + +static struct atlas7_pad_mux jtag_jt_dbg_nsrst_grp_pad_mux[] = { MUX(1, 125, 5, 0xa08, 2, 0xa88, 2), +}; + +static struct atlas7_grp_mux jtag_jt_dbg_nsrst_grp_mux = { + .pad_mux_count = ARRAY_SIZE(jtag_jt_dbg_nsrst_grp_pad_mux), + .pad_mux_list = jtag_jt_dbg_nsrst_grp_pad_mux, +}; + +static struct atlas7_pad_mux jtag_ntrst_grp0_pad_mux[] = { MUX(0, 4, 3, 0xa08, 3, 0xa88, 3), - MUX(0, 2, 3, N, N, N, N), - MUX(0, 0, 3, N, N, N, N), - MUX(0, 1, 3, N, N, N, N), +}; + +static struct atlas7_grp_mux jtag_ntrst_grp0_mux = { + .pad_mux_count = ARRAY_SIZE(jtag_ntrst_grp0_pad_mux), + .pad_mux_list = jtag_ntrst_grp0_pad_mux, +}; + +static struct atlas7_pad_mux jtag_ntrst_grp1_pad_mux[] = { + MUX(1, 163, 1, 0xa08, 3, 0xa88, 3), +}; + +static struct atlas7_grp_mux jtag_ntrst_grp1_mux = { + .pad_mux_count = ARRAY_SIZE(jtag_ntrst_grp1_pad_mux), + .pad_mux_list = jtag_ntrst_grp1_pad_mux, +}; + +static struct atlas7_pad_mux jtag_swdiotms_grp0_pad_mux[] = { + MUX(0, 2, 3, 0xa10, 10, 0xa90, 10), +}; + +static struct atlas7_grp_mux jtag_swdiotms_grp0_mux = { + .pad_mux_count = ARRAY_SIZE(jtag_swdiotms_grp0_pad_mux), + .pad_mux_list = jtag_swdiotms_grp0_pad_mux, +}; + +static struct atlas7_pad_mux jtag_swdiotms_grp1_pad_mux[] = { + MUX(1, 160, 1, 0xa10, 10, 0xa90, 10), +}; + +static struct atlas7_grp_mux jtag_swdiotms_grp1_mux = { + .pad_mux_count = ARRAY_SIZE(jtag_swdiotms_grp1_pad_mux), + .pad_mux_list = jtag_swdiotms_grp1_pad_mux, +}; + +static struct atlas7_pad_mux jtag_tck_grp0_pad_mux[] = { + MUX(0, 0, 3, 0xa10, 11, 0xa90, 11), +}; + +static struct atlas7_grp_mux jtag_tck_grp0_mux = { + .pad_mux_count = ARRAY_SIZE(jtag_tck_grp0_pad_mux), + .pad_mux_list = jtag_tck_grp0_pad_mux, +}; + +static struct atlas7_pad_mux jtag_tck_grp1_pad_mux[] = { + MUX(1, 161, 1, 0xa10, 11, 0xa90, 11), +}; + +static struct atlas7_grp_mux jtag_tck_grp1_mux = { + .pad_mux_count = ARRAY_SIZE(jtag_tck_grp1_pad_mux), + .pad_mux_list = jtag_tck_grp1_pad_mux, +}; + +static struct atlas7_pad_mux jtag_tdi_grp0_pad_mux[] = { + MUX(0, 1, 3, 0xa10, 31, 0xa90, 31), +}; + +static struct atlas7_grp_mux jtag_tdi_grp0_mux = { + .pad_mux_count = ARRAY_SIZE(jtag_tdi_grp0_pad_mux), + .pad_mux_list = jtag_tdi_grp0_pad_mux, +}; + +static struct atlas7_pad_mux jtag_tdi_grp1_pad_mux[] = { + MUX(1, 162, 1, 0xa10, 31, 0xa90, 31), +}; + +static struct atlas7_grp_mux jtag_tdi_grp1_mux = { + .pad_mux_count = ARRAY_SIZE(jtag_tdi_grp1_pad_mux), + .pad_mux_list = jtag_tdi_grp1_pad_mux, +}; + +static struct atlas7_pad_mux jtag_tdo_grp0_pad_mux[] = { MUX(0, 3, 3, N, N, N, N), }; -static struct atlas7_grp_mux jtag_grp0_mux = { - .pad_mux_count = ARRAY_SIZE(jtag_grp0_pad_mux), - .pad_mux_list = jtag_grp0_pad_mux, +static struct atlas7_grp_mux jtag_tdo_grp0_mux = { + .pad_mux_count = ARRAY_SIZE(jtag_tdo_grp0_pad_mux), + .pad_mux_list = jtag_tdo_grp0_pad_mux, +}; + +static struct atlas7_pad_mux jtag_tdo_grp1_pad_mux[] = { + MUX(1, 159, 1, N, N, N, N), +}; + +static struct atlas7_grp_mux jtag_tdo_grp1_mux = { + .pad_mux_count = ARRAY_SIZE(jtag_tdo_grp1_pad_mux), + .pad_mux_list = jtag_tdo_grp1_pad_mux, }; static struct atlas7_pad_mux ks_kas_spi_grp0_pad_mux[] = { @@ -2401,6 +3226,7 @@ static struct atlas7_grp_mux nd_df_nowp_grp_mux = { static struct atlas7_pad_mux ps_grp_pad_mux[] = { MUX(1, 120, 2, N, N, N, N), MUX(1, 119, 2, N, N, N, N), + MUX(1, 121, 5, N, N, N, N), }; static struct atlas7_grp_mux ps_grp_mux = { @@ -2534,6 +3360,15 @@ static struct atlas7_grp_mux pw_cko0_grp2_mux = { .pad_mux_list = pw_cko0_grp2_pad_mux, }; +static struct atlas7_pad_mux pw_cko0_grp3_pad_mux[] = { + MUX(1, 162, 5, N, N, N, N), +}; + +static struct atlas7_grp_mux pw_cko0_grp3_mux = { + .pad_mux_count = ARRAY_SIZE(pw_cko0_grp3_pad_mux), + .pad_mux_list = pw_cko0_grp3_pad_mux, +}; + static struct atlas7_pad_mux pw_cko1_grp0_pad_mux[] = { MUX(1, 124, 3, N, N, N, N), }; @@ -2552,6 +3387,15 @@ static struct atlas7_grp_mux pw_cko1_grp1_mux = { .pad_mux_list = pw_cko1_grp1_pad_mux, }; +static struct atlas7_pad_mux pw_cko1_grp2_pad_mux[] = { + MUX(1, 163, 5, N, N, N, N), +}; + +static struct atlas7_grp_mux pw_cko1_grp2_mux = { + .pad_mux_count = ARRAY_SIZE(pw_cko1_grp2_pad_mux), + .pad_mux_list = pw_cko1_grp2_pad_mux, +}; + static struct atlas7_pad_mux pw_i2s01_clk_grp0_pad_mux[] = { MUX(1, 125, 3, N, N, N, N), }; @@ -2570,22 +3414,58 @@ static struct atlas7_grp_mux pw_i2s01_clk_grp1_mux = { .pad_mux_list = pw_i2s01_clk_grp1_pad_mux, }; -static struct atlas7_pad_mux pw_pwm0_grp_pad_mux[] = { +static struct atlas7_pad_mux pw_i2s01_clk_grp2_pad_mux[] = { + MUX(1, 132, 2, N, N, N, N), +}; + +static struct atlas7_grp_mux pw_i2s01_clk_grp2_mux = { + .pad_mux_count = ARRAY_SIZE(pw_i2s01_clk_grp2_pad_mux), + .pad_mux_list = pw_i2s01_clk_grp2_pad_mux, +}; + +static struct atlas7_pad_mux pw_pwm0_grp0_pad_mux[] = { MUX(1, 119, 3, N, N, N, N), }; -static struct atlas7_grp_mux pw_pwm0_grp_mux = { - .pad_mux_count = ARRAY_SIZE(pw_pwm0_grp_pad_mux), - .pad_mux_list = pw_pwm0_grp_pad_mux, +static struct atlas7_grp_mux pw_pwm0_grp0_mux = { + .pad_mux_count = ARRAY_SIZE(pw_pwm0_grp0_pad_mux), + .pad_mux_list = pw_pwm0_grp0_pad_mux, +}; + +static struct atlas7_pad_mux pw_pwm0_grp1_pad_mux[] = { + MUX(1, 159, 5, N, N, N, N), +}; + +static struct atlas7_grp_mux pw_pwm0_grp1_mux = { + .pad_mux_count = ARRAY_SIZE(pw_pwm0_grp1_pad_mux), + .pad_mux_list = pw_pwm0_grp1_pad_mux, }; -static struct atlas7_pad_mux pw_pwm1_grp_pad_mux[] = { +static struct atlas7_pad_mux pw_pwm1_grp0_pad_mux[] = { MUX(1, 120, 3, N, N, N, N), }; -static struct atlas7_grp_mux pw_pwm1_grp_mux = { - .pad_mux_count = ARRAY_SIZE(pw_pwm1_grp_pad_mux), - .pad_mux_list = pw_pwm1_grp_pad_mux, +static struct atlas7_grp_mux pw_pwm1_grp0_mux = { + .pad_mux_count = ARRAY_SIZE(pw_pwm1_grp0_pad_mux), + .pad_mux_list = pw_pwm1_grp0_pad_mux, +}; + +static struct atlas7_pad_mux pw_pwm1_grp1_pad_mux[] = { + MUX(1, 160, 5, N, N, N, N), +}; + +static struct atlas7_grp_mux pw_pwm1_grp1_mux = { + .pad_mux_count = ARRAY_SIZE(pw_pwm1_grp1_pad_mux), + .pad_mux_list = pw_pwm1_grp1_pad_mux, +}; + +static struct atlas7_pad_mux pw_pwm1_grp2_pad_mux[] = { + MUX(1, 131, 2, N, N, N, N), +}; + +static struct atlas7_grp_mux pw_pwm1_grp2_mux = { + .pad_mux_count = ARRAY_SIZE(pw_pwm1_grp2_pad_mux), + .pad_mux_list = pw_pwm1_grp2_pad_mux, }; static struct atlas7_pad_mux pw_pwm2_grp0_pad_mux[] = { @@ -2606,6 +3486,15 @@ static struct atlas7_grp_mux pw_pwm2_grp1_mux = { .pad_mux_list = pw_pwm2_grp1_pad_mux, }; +static struct atlas7_pad_mux pw_pwm2_grp2_pad_mux[] = { + MUX(1, 161, 5, N, N, N, N), +}; + +static struct atlas7_grp_mux pw_pwm2_grp2_mux = { + .pad_mux_count = ARRAY_SIZE(pw_pwm2_grp2_pad_mux), + .pad_mux_list = pw_pwm2_grp2_pad_mux, +}; + static struct atlas7_pad_mux pw_pwm3_grp0_pad_mux[] = { MUX(1, 122, 3, N, N, N, N), }; @@ -2642,6 +3531,15 @@ static struct atlas7_grp_mux pw_pwm_cpu_vol_grp1_mux = { .pad_mux_list = pw_pwm_cpu_vol_grp1_pad_mux, }; +static struct atlas7_pad_mux pw_pwm_cpu_vol_grp2_pad_mux[] = { + MUX(1, 161, 5, N, N, N, N), +}; + +static struct atlas7_grp_mux pw_pwm_cpu_vol_grp2_mux = { + .pad_mux_count = ARRAY_SIZE(pw_pwm_cpu_vol_grp2_pad_mux), + .pad_mux_list = pw_pwm_cpu_vol_grp2_pad_mux, +}; + static struct atlas7_pad_mux pw_backlight_grp0_pad_mux[] = { MUX(1, 122, 3, N, N, N, N), }; @@ -2795,35 +3693,54 @@ static struct atlas7_grp_mux sd1_4bit_grp1_mux = { .pad_mux_list = sd1_4bit_grp1_pad_mux, }; -static struct atlas7_pad_mux sd2_grp0_pad_mux[] = { - MUX(1, 124, 2, 0xa08, 7, 0xa88, 7), +static struct atlas7_pad_mux sd2_basic_grp_pad_mux[] = { MUX(1, 31, 1, N, N, N, N), MUX(1, 32, 1, N, N, N, N), MUX(1, 33, 1, N, N, N, N), MUX(1, 34, 1, N, N, N, N), MUX(1, 35, 1, N, N, N, N), MUX(1, 36, 1, N, N, N, N), - MUX(1, 123, 2, N, N, N, N), }; -static struct atlas7_grp_mux sd2_grp0_mux = { - .pad_mux_count = ARRAY_SIZE(sd2_grp0_pad_mux), - .pad_mux_list = sd2_grp0_pad_mux, +static struct atlas7_grp_mux sd2_basic_grp_mux = { + .pad_mux_count = ARRAY_SIZE(sd2_basic_grp_pad_mux), + .pad_mux_list = sd2_basic_grp_pad_mux, }; -static struct atlas7_pad_mux sd2_no_cdb_grp0_pad_mux[] = { - MUX(1, 31, 1, N, N, N, N), - MUX(1, 32, 1, N, N, N, N), - MUX(1, 33, 1, N, N, N, N), - MUX(1, 34, 1, N, N, N, N), - MUX(1, 35, 1, N, N, N, N), - MUX(1, 36, 1, N, N, N, N), - MUX(1, 123, 2, N, N, N, N), +static struct atlas7_pad_mux sd2_cdb_grp0_pad_mux[] = { + MUX(1, 124, 2, 0xa08, 7, 0xa88, 7), }; -static struct atlas7_grp_mux sd2_no_cdb_grp0_mux = { - .pad_mux_count = ARRAY_SIZE(sd2_no_cdb_grp0_pad_mux), - .pad_mux_list = sd2_no_cdb_grp0_pad_mux, +static struct atlas7_grp_mux sd2_cdb_grp0_mux = { + .pad_mux_count = ARRAY_SIZE(sd2_cdb_grp0_pad_mux), + .pad_mux_list = sd2_cdb_grp0_pad_mux, +}; + +static struct atlas7_pad_mux sd2_cdb_grp1_pad_mux[] = { + MUX(1, 161, 6, 0xa08, 7, 0xa88, 7), +}; + +static struct atlas7_grp_mux sd2_cdb_grp1_mux = { + .pad_mux_count = ARRAY_SIZE(sd2_cdb_grp1_pad_mux), + .pad_mux_list = sd2_cdb_grp1_pad_mux, +}; + +static struct atlas7_pad_mux sd2_wpb_grp0_pad_mux[] = { + MUX(1, 123, 2, 0xa10, 6, 0xa90, 6), +}; + +static struct atlas7_grp_mux sd2_wpb_grp0_mux = { + .pad_mux_count = ARRAY_SIZE(sd2_wpb_grp0_pad_mux), + .pad_mux_list = sd2_wpb_grp0_pad_mux, +}; + +static struct atlas7_pad_mux sd2_wpb_grp1_pad_mux[] = { + MUX(1, 163, 7, 0xa10, 6, 0xa90, 6), +}; + +static struct atlas7_grp_mux sd2_wpb_grp1_mux = { + .pad_mux_count = ARRAY_SIZE(sd2_wpb_grp1_pad_mux), + .pad_mux_list = sd2_wpb_grp1_pad_mux, }; static struct atlas7_pad_mux sd3_grp_pad_mux[] = { @@ -2975,146 +3892,302 @@ static struct atlas7_grp_mux uart1_grp_mux = { .pad_mux_list = uart1_grp_pad_mux, }; -static struct atlas7_pad_mux uart2_grp_pad_mux[] = { - MUX(0, 11, 2, N, N, N, N), +static struct atlas7_pad_mux uart2_cts_grp0_pad_mux[] = { + MUX(1, 132, 3, 0xa10, 2, 0xa90, 2), +}; + +static struct atlas7_grp_mux uart2_cts_grp0_mux = { + .pad_mux_count = ARRAY_SIZE(uart2_cts_grp0_pad_mux), + .pad_mux_list = uart2_cts_grp0_pad_mux, +}; + +static struct atlas7_pad_mux uart2_cts_grp1_pad_mux[] = { + MUX(1, 162, 2, 0xa10, 2, 0xa90, 2), +}; + +static struct atlas7_grp_mux uart2_cts_grp1_mux = { + .pad_mux_count = ARRAY_SIZE(uart2_cts_grp1_pad_mux), + .pad_mux_list = uart2_cts_grp1_pad_mux, +}; + +static struct atlas7_pad_mux uart2_rts_grp0_pad_mux[] = { + MUX(1, 131, 3, N, N, N, N), +}; + +static struct atlas7_grp_mux uart2_rts_grp0_mux = { + .pad_mux_count = ARRAY_SIZE(uart2_rts_grp0_pad_mux), + .pad_mux_list = uart2_rts_grp0_pad_mux, +}; + +static struct atlas7_pad_mux uart2_rts_grp1_pad_mux[] = { + MUX(1, 161, 2, N, N, N, N), +}; + +static struct atlas7_grp_mux uart2_rts_grp1_mux = { + .pad_mux_count = ARRAY_SIZE(uart2_rts_grp1_pad_mux), + .pad_mux_list = uart2_rts_grp1_pad_mux, +}; + +static struct atlas7_pad_mux uart2_rxd_grp0_pad_mux[] = { + MUX(0, 11, 2, 0xa10, 5, 0xa90, 5), +}; + +static struct atlas7_grp_mux uart2_rxd_grp0_mux = { + .pad_mux_count = ARRAY_SIZE(uart2_rxd_grp0_pad_mux), + .pad_mux_list = uart2_rxd_grp0_pad_mux, +}; + +static struct atlas7_pad_mux uart2_rxd_grp1_pad_mux[] = { + MUX(1, 160, 2, 0xa10, 5, 0xa90, 5), +}; + +static struct atlas7_grp_mux uart2_rxd_grp1_mux = { + .pad_mux_count = ARRAY_SIZE(uart2_rxd_grp1_pad_mux), + .pad_mux_list = uart2_rxd_grp1_pad_mux, +}; + +static struct atlas7_pad_mux uart2_rxd_grp2_pad_mux[] = { + MUX(1, 130, 3, 0xa10, 5, 0xa90, 5), +}; + +static struct atlas7_grp_mux uart2_rxd_grp2_mux = { + .pad_mux_count = ARRAY_SIZE(uart2_rxd_grp2_pad_mux), + .pad_mux_list = uart2_rxd_grp2_pad_mux, +}; + +static struct atlas7_pad_mux uart2_txd_grp0_pad_mux[] = { MUX(0, 10, 2, N, N, N, N), }; -static struct atlas7_grp_mux uart2_grp_mux = { - .pad_mux_count = ARRAY_SIZE(uart2_grp_pad_mux), - .pad_mux_list = uart2_grp_pad_mux, +static struct atlas7_grp_mux uart2_txd_grp0_mux = { + .pad_mux_count = ARRAY_SIZE(uart2_txd_grp0_pad_mux), + .pad_mux_list = uart2_txd_grp0_pad_mux, +}; + +static struct atlas7_pad_mux uart2_txd_grp1_pad_mux[] = { + MUX(1, 159, 2, N, N, N, N), }; -static struct atlas7_pad_mux uart3_grp0_pad_mux[] = { +static struct atlas7_grp_mux uart2_txd_grp1_mux = { + .pad_mux_count = ARRAY_SIZE(uart2_txd_grp1_pad_mux), + .pad_mux_list = uart2_txd_grp1_pad_mux, +}; + +static struct atlas7_pad_mux uart2_txd_grp2_pad_mux[] = { + MUX(1, 129, 3, N, N, N, N), +}; + +static struct atlas7_grp_mux uart2_txd_grp2_mux = { + .pad_mux_count = ARRAY_SIZE(uart2_txd_grp2_pad_mux), + .pad_mux_list = uart2_txd_grp2_pad_mux, +}; + +static struct atlas7_pad_mux uart3_cts_grp0_pad_mux[] = { MUX(1, 125, 2, 0xa08, 0, 0xa88, 0), - MUX(1, 126, 2, N, N, N, N), - MUX(1, 138, 1, 0xa00, 5, 0xa80, 5), - MUX(1, 137, 1, N, N, N, N), }; -static struct atlas7_grp_mux uart3_grp0_mux = { - .pad_mux_count = ARRAY_SIZE(uart3_grp0_pad_mux), - .pad_mux_list = uart3_grp0_pad_mux, +static struct atlas7_grp_mux uart3_cts_grp0_mux = { + .pad_mux_count = ARRAY_SIZE(uart3_cts_grp0_pad_mux), + .pad_mux_list = uart3_cts_grp0_pad_mux, }; -static struct atlas7_pad_mux uart3_grp1_pad_mux[] = { +static struct atlas7_pad_mux uart3_cts_grp1_pad_mux[] = { MUX(1, 111, 4, 0xa08, 0, 0xa88, 0), - MUX(1, 109, 4, N, N, N, N), - MUX(1, 84, 2, 0xa00, 5, 0xa80, 5), - MUX(1, 83, 2, N, N, N, N), }; -static struct atlas7_grp_mux uart3_grp1_mux = { - .pad_mux_count = ARRAY_SIZE(uart3_grp1_pad_mux), - .pad_mux_list = uart3_grp1_pad_mux, +static struct atlas7_grp_mux uart3_cts_grp1_mux = { + .pad_mux_count = ARRAY_SIZE(uart3_cts_grp1_pad_mux), + .pad_mux_list = uart3_cts_grp1_pad_mux, }; -static struct atlas7_pad_mux uart3_grp2_pad_mux[] = { +static struct atlas7_pad_mux uart3_cts_grp2_pad_mux[] = { MUX(1, 140, 2, 0xa08, 0, 0xa88, 0), +}; + +static struct atlas7_grp_mux uart3_cts_grp2_mux = { + .pad_mux_count = ARRAY_SIZE(uart3_cts_grp2_pad_mux), + .pad_mux_list = uart3_cts_grp2_pad_mux, +}; + +static struct atlas7_pad_mux uart3_rts_grp0_pad_mux[] = { + MUX(1, 126, 2, N, N, N, N), +}; + +static struct atlas7_grp_mux uart3_rts_grp0_mux = { + .pad_mux_count = ARRAY_SIZE(uart3_rts_grp0_pad_mux), + .pad_mux_list = uart3_rts_grp0_pad_mux, +}; + +static struct atlas7_pad_mux uart3_rts_grp1_pad_mux[] = { + MUX(1, 109, 4, N, N, N, N), +}; + +static struct atlas7_grp_mux uart3_rts_grp1_mux = { + .pad_mux_count = ARRAY_SIZE(uart3_rts_grp1_pad_mux), + .pad_mux_list = uart3_rts_grp1_pad_mux, +}; + +static struct atlas7_pad_mux uart3_rts_grp2_pad_mux[] = { MUX(1, 139, 2, N, N, N, N), +}; + +static struct atlas7_grp_mux uart3_rts_grp2_mux = { + .pad_mux_count = ARRAY_SIZE(uart3_rts_grp2_pad_mux), + .pad_mux_list = uart3_rts_grp2_pad_mux, +}; + +static struct atlas7_pad_mux uart3_rxd_grp0_pad_mux[] = { MUX(1, 138, 1, 0xa00, 5, 0xa80, 5), - MUX(1, 137, 1, N, N, N, N), }; -static struct atlas7_grp_mux uart3_grp2_mux = { - .pad_mux_count = ARRAY_SIZE(uart3_grp2_pad_mux), - .pad_mux_list = uart3_grp2_pad_mux, +static struct atlas7_grp_mux uart3_rxd_grp0_mux = { + .pad_mux_count = ARRAY_SIZE(uart3_rxd_grp0_pad_mux), + .pad_mux_list = uart3_rxd_grp0_pad_mux, }; -static struct atlas7_pad_mux uart3_grp3_pad_mux[] = { - MUX(1, 139, 2, N, N, N, N), - MUX(1, 140, 2, 0xa08, 0, 0xa88, 0), +static struct atlas7_pad_mux uart3_rxd_grp1_pad_mux[] = { MUX(1, 84, 2, 0xa00, 5, 0xa80, 5), - MUX(1, 83, 2, N, N, N, N), }; -static struct atlas7_grp_mux uart3_grp3_mux = { - .pad_mux_count = ARRAY_SIZE(uart3_grp3_pad_mux), - .pad_mux_list = uart3_grp3_pad_mux, +static struct atlas7_grp_mux uart3_rxd_grp1_mux = { + .pad_mux_count = ARRAY_SIZE(uart3_rxd_grp1_pad_mux), + .pad_mux_list = uart3_rxd_grp1_pad_mux, }; -static struct atlas7_pad_mux uart3_nopause_grp0_pad_mux[] = { - MUX(1, 138, 1, 0xa00, 5, 0xa80, 5), +static struct atlas7_pad_mux uart3_rxd_grp2_pad_mux[] = { + MUX(1, 162, 3, 0xa00, 5, 0xa80, 5), +}; + +static struct atlas7_grp_mux uart3_rxd_grp2_mux = { + .pad_mux_count = ARRAY_SIZE(uart3_rxd_grp2_pad_mux), + .pad_mux_list = uart3_rxd_grp2_pad_mux, +}; + +static struct atlas7_pad_mux uart3_txd_grp0_pad_mux[] = { MUX(1, 137, 1, N, N, N, N), }; -static struct atlas7_grp_mux uart3_nopause_grp0_mux = { - .pad_mux_count = ARRAY_SIZE(uart3_nopause_grp0_pad_mux), - .pad_mux_list = uart3_nopause_grp0_pad_mux, +static struct atlas7_grp_mux uart3_txd_grp0_mux = { + .pad_mux_count = ARRAY_SIZE(uart3_txd_grp0_pad_mux), + .pad_mux_list = uart3_txd_grp0_pad_mux, }; -static struct atlas7_pad_mux uart3_nopause_grp1_pad_mux[] = { - MUX(1, 84, 2, 0xa00, 5, 0xa80, 5), +static struct atlas7_pad_mux uart3_txd_grp1_pad_mux[] = { MUX(1, 83, 2, N, N, N, N), }; -static struct atlas7_grp_mux uart3_nopause_grp1_mux = { - .pad_mux_count = ARRAY_SIZE(uart3_nopause_grp1_pad_mux), - .pad_mux_list = uart3_nopause_grp1_pad_mux, +static struct atlas7_grp_mux uart3_txd_grp1_mux = { + .pad_mux_count = ARRAY_SIZE(uart3_txd_grp1_pad_mux), + .pad_mux_list = uart3_txd_grp1_pad_mux, }; -static struct atlas7_pad_mux uart4_grp0_pad_mux[] = { - MUX(1, 122, 4, 0xa08, 1, 0xa88, 1), - MUX(1, 123, 4, N, N, N, N), +static struct atlas7_pad_mux uart3_txd_grp2_pad_mux[] = { + MUX(1, 161, 3, N, N, N, N), +}; + +static struct atlas7_grp_mux uart3_txd_grp2_mux = { + .pad_mux_count = ARRAY_SIZE(uart3_txd_grp2_pad_mux), + .pad_mux_list = uart3_txd_grp2_pad_mux, +}; + +static struct atlas7_pad_mux uart4_basic_grp_pad_mux[] = { MUX(1, 140, 1, N, N, N, N), MUX(1, 139, 1, N, N, N, N), }; -static struct atlas7_grp_mux uart4_grp0_mux = { - .pad_mux_count = ARRAY_SIZE(uart4_grp0_pad_mux), - .pad_mux_list = uart4_grp0_pad_mux, +static struct atlas7_grp_mux uart4_basic_grp_mux = { + .pad_mux_count = ARRAY_SIZE(uart4_basic_grp_pad_mux), + .pad_mux_list = uart4_basic_grp_pad_mux, +}; + +static struct atlas7_pad_mux uart4_cts_grp0_pad_mux[] = { + MUX(1, 122, 4, 0xa08, 1, 0xa88, 1), +}; + +static struct atlas7_grp_mux uart4_cts_grp0_mux = { + .pad_mux_count = ARRAY_SIZE(uart4_cts_grp0_pad_mux), + .pad_mux_list = uart4_cts_grp0_pad_mux, }; -static struct atlas7_pad_mux uart4_grp1_pad_mux[] = { +static struct atlas7_pad_mux uart4_cts_grp1_pad_mux[] = { MUX(1, 100, 4, 0xa08, 1, 0xa88, 1), - MUX(1, 99, 4, N, N, N, N), - MUX(1, 140, 1, N, N, N, N), - MUX(1, 139, 1, N, N, N, N), }; -static struct atlas7_grp_mux uart4_grp1_mux = { - .pad_mux_count = ARRAY_SIZE(uart4_grp1_pad_mux), - .pad_mux_list = uart4_grp1_pad_mux, +static struct atlas7_grp_mux uart4_cts_grp1_mux = { + .pad_mux_count = ARRAY_SIZE(uart4_cts_grp1_pad_mux), + .pad_mux_list = uart4_cts_grp1_pad_mux, }; -static struct atlas7_pad_mux uart4_grp2_pad_mux[] = { +static struct atlas7_pad_mux uart4_cts_grp2_pad_mux[] = { MUX(1, 117, 2, 0xa08, 1, 0xa88, 1), - MUX(1, 116, 2, N, N, N, N), - MUX(1, 140, 1, N, N, N, N), - MUX(1, 139, 1, N, N, N, N), }; -static struct atlas7_grp_mux uart4_grp2_mux = { - .pad_mux_count = ARRAY_SIZE(uart4_grp2_pad_mux), - .pad_mux_list = uart4_grp2_pad_mux, +static struct atlas7_grp_mux uart4_cts_grp2_mux = { + .pad_mux_count = ARRAY_SIZE(uart4_cts_grp2_pad_mux), + .pad_mux_list = uart4_cts_grp2_pad_mux, }; -static struct atlas7_pad_mux uart4_nopause_grp_pad_mux[] = { - MUX(1, 140, 1, N, N, N, N), - MUX(1, 139, 1, N, N, N, N), +static struct atlas7_pad_mux uart4_rts_grp0_pad_mux[] = { + MUX(1, 123, 4, N, N, N, N), }; -static struct atlas7_grp_mux uart4_nopause_grp_mux = { - .pad_mux_count = ARRAY_SIZE(uart4_nopause_grp_pad_mux), - .pad_mux_list = uart4_nopause_grp_pad_mux, +static struct atlas7_grp_mux uart4_rts_grp0_mux = { + .pad_mux_count = ARRAY_SIZE(uart4_rts_grp0_pad_mux), + .pad_mux_list = uart4_rts_grp0_pad_mux, }; -static struct atlas7_pad_mux usb0_drvvbus_grp_pad_mux[] = { +static struct atlas7_pad_mux uart4_rts_grp1_pad_mux[] = { + MUX(1, 99, 4, N, N, N, N), +}; + +static struct atlas7_grp_mux uart4_rts_grp1_mux = { + .pad_mux_count = ARRAY_SIZE(uart4_rts_grp1_pad_mux), + .pad_mux_list = uart4_rts_grp1_pad_mux, +}; + +static struct atlas7_pad_mux uart4_rts_grp2_pad_mux[] = { + MUX(1, 116, 2, N, N, N, N), +}; + +static struct atlas7_grp_mux uart4_rts_grp2_mux = { + .pad_mux_count = ARRAY_SIZE(uart4_rts_grp2_pad_mux), + .pad_mux_list = uart4_rts_grp2_pad_mux, +}; + +static struct atlas7_pad_mux usb0_drvvbus_grp0_pad_mux[] = { MUX(1, 51, 2, N, N, N, N), }; -static struct atlas7_grp_mux usb0_drvvbus_grp_mux = { - .pad_mux_count = ARRAY_SIZE(usb0_drvvbus_grp_pad_mux), - .pad_mux_list = usb0_drvvbus_grp_pad_mux, +static struct atlas7_grp_mux usb0_drvvbus_grp0_mux = { + .pad_mux_count = ARRAY_SIZE(usb0_drvvbus_grp0_pad_mux), + .pad_mux_list = usb0_drvvbus_grp0_pad_mux, +}; + +static struct atlas7_pad_mux usb0_drvvbus_grp1_pad_mux[] = { + MUX(1, 162, 7, N, N, N, N), }; -static struct atlas7_pad_mux usb1_drvvbus_grp_pad_mux[] = { +static struct atlas7_grp_mux usb0_drvvbus_grp1_mux = { + .pad_mux_count = ARRAY_SIZE(usb0_drvvbus_grp1_pad_mux), + .pad_mux_list = usb0_drvvbus_grp1_pad_mux, +}; + +static struct atlas7_pad_mux usb1_drvvbus_grp0_pad_mux[] = { MUX(1, 134, 2, N, N, N, N), }; -static struct atlas7_grp_mux usb1_drvvbus_grp_mux = { - .pad_mux_count = ARRAY_SIZE(usb1_drvvbus_grp_pad_mux), - .pad_mux_list = usb1_drvvbus_grp_pad_mux, +static struct atlas7_grp_mux usb1_drvvbus_grp0_mux = { + .pad_mux_count = ARRAY_SIZE(usb1_drvvbus_grp0_pad_mux), + .pad_mux_list = usb1_drvvbus_grp0_pad_mux, +}; + +static struct atlas7_pad_mux usb1_drvvbus_grp1_pad_mux[] = { + MUX(1, 163, 2, N, N, N, N), +}; + +static struct atlas7_grp_mux usb1_drvvbus_grp1_mux = { + .pad_mux_count = ARRAY_SIZE(usb1_drvvbus_grp1_pad_mux), + .pad_mux_list = usb1_drvvbus_grp1_pad_mux, }; static struct atlas7_pad_mux visbus_dout_grp_pad_mux[] = { @@ -3252,11 +4325,20 @@ static struct atlas7_pmx_func atlas7_pmx_functions[] = { FUNCTION("sdio_i2s_gpio", sdio_i2s_gpio_grp, &sdio_i2s_gpio_grp_mux), FUNCTION("sp_rgmii_gpio", sp_rgmii_gpio_grp, &sp_rgmii_gpio_grp_mux), FUNCTION("lvds_gpio", lvds_gpio_grp, &lvds_gpio_grp_mux), - FUNCTION("uart_nand_gpio", - uart_nand_gpio_grp, - &uart_nand_gpio_grp_mux), + FUNCTION("jtag_uart_nand_gpio", + jtag_uart_nand_gpio_grp, + &jtag_uart_nand_gpio_grp_mux), FUNCTION("rtc_gpio", rtc_gpio_grp, &rtc_gpio_grp_mux), FUNCTION("audio_ac97", audio_ac97_grp, &audio_ac97_grp_mux), + FUNCTION("audio_digmic_m0", + audio_digmic_grp0, + &audio_digmic_grp0_mux), + FUNCTION("audio_digmic_m1", + audio_digmic_grp1, + &audio_digmic_grp1_mux), + FUNCTION("audio_digmic_m2", + audio_digmic_grp2, + &audio_digmic_grp2_mux), FUNCTION("audio_func_dbg", audio_func_dbg_grp, &audio_func_dbg_grp_mux), @@ -3265,16 +4347,119 @@ static struct atlas7_pmx_func atlas7_pmx_functions[] = { FUNCTION("audio_i2s_extclk", audio_i2s_extclk_grp, &audio_i2s_extclk_grp_mux), - FUNCTION("audio_uart0", audio_uart0_grp, &audio_uart0_grp_mux), - FUNCTION("audio_uart1", audio_uart1_grp, &audio_uart1_grp_mux), - FUNCTION("audio_uart2_m0", audio_uart2_grp0, &audio_uart2_grp0_mux), - FUNCTION("audio_uart2_m1", audio_uart2_grp1, &audio_uart2_grp1_mux), - FUNCTION("c_can_trnsvr", c_can_trnsvr_grp, &c_can_trnsvr_grp_mux), - FUNCTION("c0_can_m0", c0_can_grp0, &c0_can_grp0_mux), - FUNCTION("c0_can_m1", c0_can_grp1, &c0_can_grp1_mux), - FUNCTION("c1_can_m0", c1_can_grp0, &c1_can_grp0_mux), - FUNCTION("c1_can_m1", c1_can_grp1, &c1_can_grp1_mux), - FUNCTION("c1_can_m2", c1_can_grp2, &c1_can_grp2_mux), + FUNCTION("audio_spdif_out_m0", + audio_spdif_out_grp0, + &audio_spdif_out_grp0_mux), + FUNCTION("audio_spdif_out_m1", + audio_spdif_out_grp1, + &audio_spdif_out_grp1_mux), + FUNCTION("audio_spdif_out_m2", + audio_spdif_out_grp2, + &audio_spdif_out_grp2_mux), + FUNCTION("audio_uart0_basic", + audio_uart0_basic_grp, + &audio_uart0_basic_grp_mux), + FUNCTION("audio_uart0_urfs_m0", + audio_uart0_urfs_grp0, + &audio_uart0_urfs_grp0_mux), + FUNCTION("audio_uart0_urfs_m1", + audio_uart0_urfs_grp1, + &audio_uart0_urfs_grp1_mux), + FUNCTION("audio_uart0_urfs_m2", + audio_uart0_urfs_grp2, + &audio_uart0_urfs_grp2_mux), + FUNCTION("audio_uart0_urfs_m3", + audio_uart0_urfs_grp3, + &audio_uart0_urfs_grp3_mux), + FUNCTION("audio_uart1_basic", + audio_uart1_basic_grp, + &audio_uart1_basic_grp_mux), + FUNCTION("audio_uart1_urfs_m0", + audio_uart1_urfs_grp0, + &audio_uart1_urfs_grp0_mux), + FUNCTION("audio_uart1_urfs_m1", + audio_uart1_urfs_grp1, + &audio_uart1_urfs_grp1_mux), + FUNCTION("audio_uart1_urfs_m2", + audio_uart1_urfs_grp2, + &audio_uart1_urfs_grp2_mux), + FUNCTION("audio_uart2_urfs_m0", + audio_uart2_urfs_grp0, + &audio_uart2_urfs_grp0_mux), + FUNCTION("audio_uart2_urfs_m1", + audio_uart2_urfs_grp1, + &audio_uart2_urfs_grp1_mux), + FUNCTION("audio_uart2_urfs_m2", + audio_uart2_urfs_grp2, + &audio_uart2_urfs_grp2_mux), + FUNCTION("audio_uart2_urxd_m0", + audio_uart2_urxd_grp0, + &audio_uart2_urxd_grp0_mux), + FUNCTION("audio_uart2_urxd_m1", + audio_uart2_urxd_grp1, + &audio_uart2_urxd_grp1_mux), + FUNCTION("audio_uart2_urxd_m2", + audio_uart2_urxd_grp2, + &audio_uart2_urxd_grp2_mux), + FUNCTION("audio_uart2_usclk_m0", + audio_uart2_usclk_grp0, + &audio_uart2_usclk_grp0_mux), + FUNCTION("audio_uart2_usclk_m1", + audio_uart2_usclk_grp1, + &audio_uart2_usclk_grp1_mux), + FUNCTION("audio_uart2_usclk_m2", + audio_uart2_usclk_grp2, + &audio_uart2_usclk_grp2_mux), + FUNCTION("audio_uart2_utfs_m0", + audio_uart2_utfs_grp0, + &audio_uart2_utfs_grp0_mux), + FUNCTION("audio_uart2_utfs_m1", + audio_uart2_utfs_grp1, + &audio_uart2_utfs_grp1_mux), + FUNCTION("audio_uart2_utfs_m2", + audio_uart2_utfs_grp2, + &audio_uart2_utfs_grp2_mux), + FUNCTION("audio_uart2_utxd_m0", + audio_uart2_utxd_grp0, + &audio_uart2_utxd_grp0_mux), + FUNCTION("audio_uart2_utxd_m1", + audio_uart2_utxd_grp1, + &audio_uart2_utxd_grp1_mux), + FUNCTION("audio_uart2_utxd_m2", + audio_uart2_utxd_grp2, + &audio_uart2_utxd_grp2_mux), + FUNCTION("c_can_trnsvr_en_m0", + c_can_trnsvr_en_grp0, + &c_can_trnsvr_en_grp0_mux), + FUNCTION("c_can_trnsvr_en_m1", + c_can_trnsvr_en_grp1, + &c_can_trnsvr_en_grp1_mux), + FUNCTION("c_can_trnsvr_intr", + c_can_trnsvr_intr_grp, + &c_can_trnsvr_intr_grp_mux), + FUNCTION("c_can_trnsvr_stb_n", + c_can_trnsvr_stb_n_grp, + &c_can_trnsvr_stb_n_grp_mux), + FUNCTION("c0_can_rxd_trnsv0", + c0_can_rxd_trnsv0_grp, + &c0_can_rxd_trnsv0_grp_mux), + FUNCTION("c0_can_rxd_trnsv1", + c0_can_rxd_trnsv1_grp, + &c0_can_rxd_trnsv1_grp_mux), + FUNCTION("c0_can_txd_trnsv0", + c0_can_txd_trnsv0_grp, + &c0_can_txd_trnsv0_grp_mux), + FUNCTION("c0_can_txd_trnsv1", + c0_can_txd_trnsv1_grp, + &c0_can_txd_trnsv1_grp_mux), + FUNCTION("c1_can_rxd_m0", c1_can_rxd_grp0, &c1_can_rxd_grp0_mux), + FUNCTION("c1_can_rxd_m1", c1_can_rxd_grp1, &c1_can_rxd_grp1_mux), + FUNCTION("c1_can_rxd_m2", c1_can_rxd_grp2, &c1_can_rxd_grp2_mux), + FUNCTION("c1_can_rxd_m3", c1_can_rxd_grp3, &c1_can_rxd_grp3_mux), + FUNCTION("c1_can_txd_m0", c1_can_txd_grp0, &c1_can_txd_grp0_mux), + FUNCTION("c1_can_txd_m1", c1_can_txd_grp1, &c1_can_txd_grp1_mux), + FUNCTION("c1_can_txd_m2", c1_can_txd_grp2, &c1_can_txd_grp2_mux), + FUNCTION("c1_can_txd_m3", c1_can_txd_grp3, &c1_can_txd_grp3_mux), FUNCTION("ca_audio_lpc", ca_audio_lpc_grp, &ca_audio_lpc_grp_mux), FUNCTION("ca_bt_lpc", ca_bt_lpc_grp, &ca_bt_lpc_grp_mux), FUNCTION("ca_coex", ca_coex_grp, &ca_coex_grp_mux), @@ -3377,7 +4562,35 @@ static struct atlas7_pmx_func atlas7_pmx_functions[] = { &gn_trg_shutdown_grp3_mux), FUNCTION("i2c0", i2c0_grp, &i2c0_grp_mux), FUNCTION("i2c1", i2c1_grp, &i2c1_grp_mux), - FUNCTION("jtag_m0", jtag_grp0, &jtag_grp0_mux), + FUNCTION("i2s0", i2s0_grp, &i2s0_grp_mux), + FUNCTION("i2s1_basic", i2s1_basic_grp, &i2s1_basic_grp_mux), + FUNCTION("i2s1_rxd0_m0", i2s1_rxd0_grp0, &i2s1_rxd0_grp0_mux), + FUNCTION("i2s1_rxd0_m1", i2s1_rxd0_grp1, &i2s1_rxd0_grp1_mux), + FUNCTION("i2s1_rxd0_m2", i2s1_rxd0_grp2, &i2s1_rxd0_grp2_mux), + FUNCTION("i2s1_rxd0_m3", i2s1_rxd0_grp3, &i2s1_rxd0_grp3_mux), + FUNCTION("i2s1_rxd0_m4", i2s1_rxd0_grp4, &i2s1_rxd0_grp4_mux), + FUNCTION("i2s1_rxd1_m0", i2s1_rxd1_grp0, &i2s1_rxd1_grp0_mux), + FUNCTION("i2s1_rxd1_m1", i2s1_rxd1_grp1, &i2s1_rxd1_grp1_mux), + FUNCTION("i2s1_rxd1_m2", i2s1_rxd1_grp2, &i2s1_rxd1_grp2_mux), + FUNCTION("i2s1_rxd1_m3", i2s1_rxd1_grp3, &i2s1_rxd1_grp3_mux), + FUNCTION("i2s1_rxd1_m4", i2s1_rxd1_grp4, &i2s1_rxd1_grp4_mux), + FUNCTION("jtag_jt_dbg_nsrst", + jtag_jt_dbg_nsrst_grp, + &jtag_jt_dbg_nsrst_grp_mux), + FUNCTION("jtag_ntrst_m0", jtag_ntrst_grp0, &jtag_ntrst_grp0_mux), + FUNCTION("jtag_ntrst_m1", jtag_ntrst_grp1, &jtag_ntrst_grp1_mux), + FUNCTION("jtag_swdiotms_m0", + jtag_swdiotms_grp0, + &jtag_swdiotms_grp0_mux), + FUNCTION("jtag_swdiotms_m1", + jtag_swdiotms_grp1, + &jtag_swdiotms_grp1_mux), + FUNCTION("jtag_tck_m0", jtag_tck_grp0, &jtag_tck_grp0_mux), + FUNCTION("jtag_tck_m1", jtag_tck_grp1, &jtag_tck_grp1_mux), + FUNCTION("jtag_tdi_m0", jtag_tdi_grp0, &jtag_tdi_grp0_mux), + FUNCTION("jtag_tdi_m1", jtag_tdi_grp1, &jtag_tdi_grp1_mux), + FUNCTION("jtag_tdo_m0", jtag_tdo_grp0, &jtag_tdo_grp0_mux), + FUNCTION("jtag_tdo_m1", jtag_tdo_grp1, &jtag_tdo_grp1_mux), FUNCTION("ks_kas_spi_m0", ks_kas_spi_grp0, &ks_kas_spi_grp0_mux), FUNCTION("ld_ldd", ld_ldd_grp, &ld_ldd_grp_mux), FUNCTION("ld_ldd_16bit", ld_ldd_16bit_grp, &ld_ldd_16bit_grp_mux), @@ -3414,18 +4627,27 @@ static struct atlas7_pmx_func atlas7_pmx_functions[] = { FUNCTION("pw_cko0_m0", pw_cko0_grp0, &pw_cko0_grp0_mux), FUNCTION("pw_cko0_m1", pw_cko0_grp1, &pw_cko0_grp1_mux), FUNCTION("pw_cko0_m2", pw_cko0_grp2, &pw_cko0_grp2_mux), + FUNCTION("pw_cko0_m3", pw_cko0_grp3, &pw_cko0_grp3_mux), FUNCTION("pw_cko1_m0", pw_cko1_grp0, &pw_cko1_grp0_mux), FUNCTION("pw_cko1_m1", pw_cko1_grp1, &pw_cko1_grp1_mux), + FUNCTION("pw_cko1_m2", pw_cko1_grp2, &pw_cko1_grp2_mux), FUNCTION("pw_i2s01_clk_m0", pw_i2s01_clk_grp0, &pw_i2s01_clk_grp0_mux), FUNCTION("pw_i2s01_clk_m1", pw_i2s01_clk_grp1, &pw_i2s01_clk_grp1_mux), - FUNCTION("pw_pwm0", pw_pwm0_grp, &pw_pwm0_grp_mux), - FUNCTION("pw_pwm1", pw_pwm1_grp, &pw_pwm1_grp_mux), + FUNCTION("pw_i2s01_clk_m2", + pw_i2s01_clk_grp2, + &pw_i2s01_clk_grp2_mux), + FUNCTION("pw_pwm0_m0", pw_pwm0_grp0, &pw_pwm0_grp0_mux), + FUNCTION("pw_pwm0_m1", pw_pwm0_grp1, &pw_pwm0_grp1_mux), + FUNCTION("pw_pwm1_m0", pw_pwm1_grp0, &pw_pwm1_grp0_mux), + FUNCTION("pw_pwm1_m1", pw_pwm1_grp1, &pw_pwm1_grp1_mux), + FUNCTION("pw_pwm1_m2", pw_pwm1_grp2, &pw_pwm1_grp2_mux), FUNCTION("pw_pwm2_m0", pw_pwm2_grp0, &pw_pwm2_grp0_mux), FUNCTION("pw_pwm2_m1", pw_pwm2_grp1, &pw_pwm2_grp1_mux), + FUNCTION("pw_pwm2_m2", pw_pwm2_grp2, &pw_pwm2_grp2_mux), FUNCTION("pw_pwm3_m0", pw_pwm3_grp0, &pw_pwm3_grp0_mux), FUNCTION("pw_pwm3_m1", pw_pwm3_grp1, &pw_pwm3_grp1_mux), FUNCTION("pw_pwm_cpu_vol_m0", @@ -3434,6 +4656,9 @@ static struct atlas7_pmx_func atlas7_pmx_functions[] = { FUNCTION("pw_pwm_cpu_vol_m1", pw_pwm_cpu_vol_grp1, &pw_pwm_cpu_vol_grp1_mux), + FUNCTION("pw_pwm_cpu_vol_m2", + pw_pwm_cpu_vol_grp2, + &pw_pwm_cpu_vol_grp2_mux), FUNCTION("pw_backlight_m0", pw_backlight_grp0, &pw_backlight_grp0_mux), @@ -3456,8 +4681,11 @@ static struct atlas7_pmx_func atlas7_pmx_functions[] = { FUNCTION("sd1", sd1_grp, &sd1_grp_mux), FUNCTION("sd1_4bit_m0", sd1_4bit_grp0, &sd1_4bit_grp0_mux), FUNCTION("sd1_4bit_m1", sd1_4bit_grp1, &sd1_4bit_grp1_mux), - FUNCTION("sd2_m0", sd2_grp0, &sd2_grp0_mux), - FUNCTION("sd2_no_cdb_m0", sd2_no_cdb_grp0, &sd2_no_cdb_grp0_mux), + FUNCTION("sd2_basic", sd2_basic_grp, &sd2_basic_grp_mux), + FUNCTION("sd2_cdb_m0", sd2_cdb_grp0, &sd2_cdb_grp0_mux), + FUNCTION("sd2_cdb_m1", sd2_cdb_grp1, &sd2_cdb_grp1_mux), + FUNCTION("sd2_wpb_m0", sd2_wpb_grp0, &sd2_wpb_grp0_mux), + FUNCTION("sd2_wpb_m1", sd2_wpb_grp1, &sd2_wpb_grp1_mux), FUNCTION("sd3", sd3_grp, &sd3_grp_mux), FUNCTION("sd5", sd5_grp, &sd5_grp_mux), FUNCTION("sd6_m0", sd6_grp0, &sd6_grp0_mux), @@ -3471,23 +4699,47 @@ static struct atlas7_pmx_func atlas7_pmx_functions[] = { FUNCTION("uart0", uart0_grp, &uart0_grp_mux), FUNCTION("uart0_nopause", uart0_nopause_grp, &uart0_nopause_grp_mux), FUNCTION("uart1", uart1_grp, &uart1_grp_mux), - FUNCTION("uart2", uart2_grp, &uart2_grp_mux), - FUNCTION("uart3_m0", uart3_grp0, &uart3_grp0_mux), - FUNCTION("uart3_m1", uart3_grp1, &uart3_grp1_mux), - FUNCTION("uart3_m2", uart3_grp2, &uart3_grp2_mux), - FUNCTION("uart3_m3", uart3_grp3, &uart3_grp3_mux), - FUNCTION("uart3_nopause_m0", - uart3_nopause_grp0, - &uart3_nopause_grp0_mux), - FUNCTION("uart3_nopause_m1", - uart3_nopause_grp1, - &uart3_nopause_grp1_mux), - FUNCTION("uart4_m0", uart4_grp0, &uart4_grp0_mux), - FUNCTION("uart4_m1", uart4_grp1, &uart4_grp1_mux), - FUNCTION("uart4_m2", uart4_grp2, &uart4_grp2_mux), - FUNCTION("uart4_nopause", uart4_nopause_grp, &uart4_nopause_grp_mux), - FUNCTION("usb0_drvvbus", usb0_drvvbus_grp, &usb0_drvvbus_grp_mux), - FUNCTION("usb1_drvvbus", usb1_drvvbus_grp, &usb1_drvvbus_grp_mux), + FUNCTION("uart2_cts_m0", uart2_cts_grp0, &uart2_cts_grp0_mux), + FUNCTION("uart2_cts_m1", uart2_cts_grp1, &uart2_cts_grp1_mux), + FUNCTION("uart2_rts_m0", uart2_rts_grp0, &uart2_rts_grp0_mux), + FUNCTION("uart2_rts_m1", uart2_rts_grp1, &uart2_rts_grp1_mux), + FUNCTION("uart2_rxd_m0", uart2_rxd_grp0, &uart2_rxd_grp0_mux), + FUNCTION("uart2_rxd_m1", uart2_rxd_grp1, &uart2_rxd_grp1_mux), + FUNCTION("uart2_rxd_m2", uart2_rxd_grp2, &uart2_rxd_grp2_mux), + FUNCTION("uart2_txd_m0", uart2_txd_grp0, &uart2_txd_grp0_mux), + FUNCTION("uart2_txd_m1", uart2_txd_grp1, &uart2_txd_grp1_mux), + FUNCTION("uart2_txd_m2", uart2_txd_grp2, &uart2_txd_grp2_mux), + FUNCTION("uart3_cts_m0", uart3_cts_grp0, &uart3_cts_grp0_mux), + FUNCTION("uart3_cts_m1", uart3_cts_grp1, &uart3_cts_grp1_mux), + FUNCTION("uart3_cts_m2", uart3_cts_grp2, &uart3_cts_grp2_mux), + FUNCTION("uart3_rts_m0", uart3_rts_grp0, &uart3_rts_grp0_mux), + FUNCTION("uart3_rts_m1", uart3_rts_grp1, &uart3_rts_grp1_mux), + FUNCTION("uart3_rts_m2", uart3_rts_grp2, &uart3_rts_grp2_mux), + FUNCTION("uart3_rxd_m0", uart3_rxd_grp0, &uart3_rxd_grp0_mux), + FUNCTION("uart3_rxd_m1", uart3_rxd_grp1, &uart3_rxd_grp1_mux), + FUNCTION("uart3_rxd_m2", uart3_rxd_grp2, &uart3_rxd_grp2_mux), + FUNCTION("uart3_txd_m0", uart3_txd_grp0, &uart3_txd_grp0_mux), + FUNCTION("uart3_txd_m1", uart3_txd_grp1, &uart3_txd_grp1_mux), + FUNCTION("uart3_txd_m2", uart3_txd_grp2, &uart3_txd_grp2_mux), + FUNCTION("uart4_basic", uart4_basic_grp, &uart4_basic_grp_mux), + FUNCTION("uart4_cts_m0", uart4_cts_grp0, &uart4_cts_grp0_mux), + FUNCTION("uart4_cts_m1", uart4_cts_grp1, &uart4_cts_grp1_mux), + FUNCTION("uart4_cts_m2", uart4_cts_grp2, &uart4_cts_grp2_mux), + FUNCTION("uart4_rts_m0", uart4_rts_grp0, &uart4_rts_grp0_mux), + FUNCTION("uart4_rts_m1", uart4_rts_grp1, &uart4_rts_grp1_mux), + FUNCTION("uart4_rts_m2", uart4_rts_grp2, &uart4_rts_grp2_mux), + FUNCTION("usb0_drvvbus_m0", + usb0_drvvbus_grp0, + &usb0_drvvbus_grp0_mux), + FUNCTION("usb0_drvvbus_m1", + usb0_drvvbus_grp1, + &usb0_drvvbus_grp1_mux), + FUNCTION("usb1_drvvbus_m0", + usb1_drvvbus_grp0, + &usb1_drvvbus_grp0_mux), + FUNCTION("usb1_drvvbus_m1", + usb1_drvvbus_grp1, + &usb1_drvvbus_grp1_mux), FUNCTION("visbus_dout", visbus_dout_grp, &visbus_dout_grp_mux), FUNCTION("vi_vip1", vi_vip1_grp, &vi_vip1_grp_mux), FUNCTION("vi_vip1_ext", vi_vip1_ext_grp, &vi_vip1_ext_grp_mux), -- cgit v0.10.2 From 11091fb0a1227d569d09353e1ce1f88694a033dc Mon Sep 17 00:00:00 2001 From: Jonas Gorski Date: Sun, 11 Oct 2015 17:39:31 +0200 Subject: pinctrl: qcom: ssbi: fix compilation with DEBUG_FS=n MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The DEBUG_FS=n #defines for the dbg_show functions were missed when renaming the driver from msm_ to pm8xxx_, causing it to break the build when DEBUG_FS isn't enabled: CC [M] drivers/pinctrl/qcom/pinctrl-ssbi-gpio.o drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c:597:14: error: ‘pm8xxx_gpio_dbg_show’ undeclared here (not in a function) .dbg_show = pm8xxx_gpio_dbg_show, Fix this by renaming them correctly. Fixes: b4c45fe974bc ("pinctrl: qcom: ssbi: Family A gpio & mpp drivers") Signed-off-by: Jonas Gorski Reviewed-by: Bjorn Andersson Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c b/drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c index e1a3721..d809c9e 100644 --- a/drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c +++ b/drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c @@ -584,7 +584,7 @@ static void pm8xxx_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) } #else -#define msm_gpio_dbg_show NULL +#define pm8xxx_gpio_dbg_show NULL #endif static struct gpio_chip pm8xxx_gpio_template = { diff --git a/drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c b/drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c index 6652b8d..8982027 100644 --- a/drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c +++ b/drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c @@ -639,7 +639,7 @@ static void pm8xxx_mpp_dbg_show(struct seq_file *s, struct gpio_chip *chip) } #else -#define msm_mpp_dbg_show NULL +#define pm8xxx_mpp_dbg_show NULL #endif static struct gpio_chip pm8xxx_mpp_template = { -- cgit v0.10.2 From f487bbf309759153f56bac7d7ba5ee63196ce584 Mon Sep 17 00:00:00 2001 From: Mika Westerberg Date: Tue, 13 Oct 2015 17:51:25 +0300 Subject: pinctrl: intel: Fix compilation warning when !CONFIG_PM_SLEEP MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We get following warning when CONFIG_PM_SLEEP is not set warning: ‘intel_gpio_irq_init’ defined but not used [-Wunused-function] Since the function is only called from intel_pinctrl_resume() move it inside CONFIG_PM_SLEEP guard as well. Signed-off-by: Mika Westerberg Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/intel/pinctrl-intel.c b/drivers/pinctrl/intel/pinctrl-intel.c index 54848b8..613ba1b 100644 --- a/drivers/pinctrl/intel/pinctrl-intel.c +++ b/drivers/pinctrl/intel/pinctrl-intel.c @@ -861,26 +861,6 @@ static struct irq_chip intel_gpio_irqchip = { .irq_set_wake = intel_gpio_irq_wake, }; -static void intel_gpio_irq_init(struct intel_pinctrl *pctrl) -{ - size_t i; - - for (i = 0; i < pctrl->ncommunities; i++) { - const struct intel_community *community; - void __iomem *base; - unsigned gpp; - - community = &pctrl->communities[i]; - base = community->regs; - - for (gpp = 0; gpp < community->ngpps; gpp++) { - /* Mask and clear all interrupts */ - writel(0, base + community->ie_offset + gpp * 4); - writel(0xffff, base + GPI_IS + gpp * 4); - } - } -} - static int intel_gpio_probe(struct intel_pinctrl *pctrl, int irq) { int ret; @@ -1087,6 +1067,26 @@ int intel_pinctrl_suspend(struct device *dev) } EXPORT_SYMBOL_GPL(intel_pinctrl_suspend); +static void intel_gpio_irq_init(struct intel_pinctrl *pctrl) +{ + size_t i; + + for (i = 0; i < pctrl->ncommunities; i++) { + const struct intel_community *community; + void __iomem *base; + unsigned gpp; + + community = &pctrl->communities[i]; + base = community->regs; + + for (gpp = 0; gpp < community->ngpps; gpp++) { + /* Mask and clear all interrupts */ + writel(0, base + community->ie_offset + gpp * 4); + writel(0xffff, base + GPI_IS + gpp * 4); + } + } +} + int intel_pinctrl_resume(struct device *dev) { struct platform_device *pdev = to_platform_device(dev); -- cgit v0.10.2 From ec879f1272283c040bc70e1a1fff5edbb547be59 Mon Sep 17 00:00:00 2001 From: Mika Westerberg Date: Tue, 13 Oct 2015 17:51:26 +0300 Subject: pinctrl: baytrail: Fix compilation warnings when !CONFIG_PM MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit When CONFIG_PM is not set we get following compilation warnings: warning: ‘byt_gpio_runtime_suspend’ defined but not used [-Wunused-function] warning: ‘byt_gpio_runtime_resume’ defined but not used [-Wunused-function] Fix this by guarding byt_gpio_runtime_suspend()/byt_gpio_runtime_resume() with #ifdef CONFIG_PM. Signed-off-by: Mika Westerberg Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/intel/pinctrl-baytrail.c b/drivers/pinctrl/intel/pinctrl-baytrail.c index f79ea43..b59ce75 100644 --- a/drivers/pinctrl/intel/pinctrl-baytrail.c +++ b/drivers/pinctrl/intel/pinctrl-baytrail.c @@ -696,6 +696,7 @@ static int byt_gpio_resume(struct device *dev) } #endif +#ifdef CONFIG_PM static int byt_gpio_runtime_suspend(struct device *dev) { return 0; @@ -705,6 +706,7 @@ static int byt_gpio_runtime_resume(struct device *dev) { return 0; } +#endif static const struct dev_pm_ops byt_gpio_pm_ops = { SET_LATE_SYSTEM_SLEEP_PM_OPS(byt_gpio_suspend, byt_gpio_resume) -- cgit v0.10.2 From 423caa52534ff15a63a8f86f8ecb99cfa8e9cbca Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Sat, 3 Oct 2015 02:21:15 +0300 Subject: pinctrl: sh-pfc: r8a779[01]: Move 'union vin_data' to shared header file R8A7790/1 PFC drivers use almost identical 'union vin_data' and completely identical VIN_DATA_PIN_GROUP() macro; we thus can move them into the shared header file... Suggested-by: Geert Uytterhoeven Signed-off-by: Sergei Shtylyov Acked-by: Laurent Pinchart Signed-off-by: Geert Uytterhoeven diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c index 77a1493..8e45e30 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c @@ -3624,25 +3624,6 @@ static const unsigned int usb2_pins[] = { static const unsigned int usb2_mux[] = { USB2_PWEN_MARK, USB2_OVC_MARK, }; - -union vin_data { - unsigned int data24[24]; - unsigned int data20[20]; - unsigned int data16[16]; - unsigned int data12[12]; - unsigned int data10[10]; - unsigned int data8[8]; - unsigned int data4[4]; -}; - -#define VIN_DATA_PIN_GROUP(n, s) \ - { \ - .name = #n#s, \ - .pins = n##_pins.data##s, \ - .mux = n##_mux.data##s, \ - .nr_pins = ARRAY_SIZE(n##_pins.data##s), \ - } - /* - VIN0 ------------------------------------------------------------------- */ static const union vin_data vin0_data_pins = { .data24 = { diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c index 6228419..a58a0de 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c @@ -3986,24 +3986,6 @@ static const unsigned int usb1_mux[] = { USB1_PWEN_MARK, USB1_OVC_MARK, }; - -union vin_data { - unsigned int data24[24]; - unsigned int data20[20]; - unsigned int data16[16]; - unsigned int data12[12]; - unsigned int data10[10]; - unsigned int data8[8]; -}; - -#define VIN_DATA_PIN_GROUP(n, s) \ - { \ - .name = #n#s, \ - .pins = n##_pins.data##s, \ - .mux = n##_mux.data##s, \ - .nr_pins = ARRAY_SIZE(n##_pins.data##s), \ - } - /* - VIN0 ------------------------------------------------------------------- */ static const union vin_data vin0_data_pins = { .data24 = { diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h index e00a4b1..6ab4b46 100644 --- a/drivers/pinctrl/sh-pfc/sh_pfc.h +++ b/drivers/pinctrl/sh-pfc/sh_pfc.h @@ -52,6 +52,29 @@ struct sh_pfc_pin_group { unsigned int nr_pins; }; +/* + * Using union vin_data saves memory occupied by the VIN data pins. + * VIN_DATA_PIN_GROUP() is a macro used to describe the VIN pin groups + * in this case. + */ +#define VIN_DATA_PIN_GROUP(n, s) \ + { \ + .name = #n#s, \ + .pins = n##_pins.data##s, \ + .mux = n##_mux.data##s, \ + .nr_pins = ARRAY_SIZE(n##_pins.data##s), \ + } + +union vin_data { + unsigned int data24[24]; + unsigned int data20[20]; + unsigned int data16[16]; + unsigned int data12[12]; + unsigned int data10[10]; + unsigned int data8[8]; + unsigned int data4[4]; +}; + #define SH_PFC_FUNCTION(n) \ { \ .name = #n, \ -- cgit v0.10.2 From 0f7711aa300355d46e2a532d9c5cd13ca67d1b02 Mon Sep 17 00:00:00 2001 From: Koji Matsuoka Date: Sat, 3 Oct 2015 02:21:49 +0300 Subject: pinctrl: sh-pfc: r8a7794: Add VIN pin groups Add VIN0/1 pin groups to R8A7794 PFC driver. Sergei: rebased, renamed, added changelog, gathered 12 VIN1 data pins into a single pin group, added "vin1_data10" pin group, used 'union vin_data' and VIN_DATA_PIN_GROUP() macro to describe VIN1 pins, reversed the order of the VIN1 pin groups, removed unneeded empty lines, fixed VIN1 separator comment. Signed-off-by: Koji Matsuoka Signed-off-by: Sergei Shtylyov Signed-off-by: Geert Uytterhoeven diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7794.c b/drivers/pinctrl/sh-pfc/pfc-r8a7794.c index 2be19d0..f9b9dc3 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7794.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7794.c @@ -2774,6 +2774,146 @@ static const unsigned int usb1_mux[] = { USB1_PWEN_MARK, USB1_OVC_MARK, }; +/* - VIN0 ------------------------------------------------------------------- */ +static const union vin_data vin0_data_pins = { + .data24 = { + /* B */ + RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 2), + RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4), + RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6), + RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 8), + /* G */ + RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14), + RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16), + RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 18), + RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20), + /* R */ + RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 22), + RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 24), + RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26), + RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28), + }, +}; +static const union vin_data vin0_data_mux = { + .data24 = { + /* B */ + VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK, + VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK, + VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK, + VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK, + /* G */ + VI0_G0_MARK, VI0_G1_MARK, + VI0_G2_MARK, VI0_G3_MARK, + VI0_G4_MARK, VI0_G5_MARK, + VI0_G6_MARK, VI0_G7_MARK, + /* R */ + VI0_R0_MARK, VI0_R1_MARK, + VI0_R2_MARK, VI0_R3_MARK, + VI0_R4_MARK, VI0_R5_MARK, + VI0_R6_MARK, VI0_R7_MARK, + }, +}; +static const unsigned int vin0_data18_pins[] = { + /* B */ + RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4), + RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6), + RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 8), + /* G */ + RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16), + RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 18), + RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20), + /* R */ + RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 24), + RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26), + RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28), +}; +static const unsigned int vin0_data18_mux[] = { + /* B */ + VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK, + VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK, + VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK, + /* G */ + VI0_G2_MARK, VI0_G3_MARK, + VI0_G4_MARK, VI0_G5_MARK, + VI0_G6_MARK, VI0_G7_MARK, + /* R */ + VI0_R2_MARK, VI0_R3_MARK, + VI0_R4_MARK, VI0_R5_MARK, + VI0_R6_MARK, VI0_R7_MARK, +}; +static const unsigned int vin0_sync_pins[] = { + RCAR_GP_PIN(3, 11), /* HSYNC */ + RCAR_GP_PIN(3, 12), /* VSYNC */ +}; +static const unsigned int vin0_sync_mux[] = { + VI0_HSYNC_N_MARK, + VI0_VSYNC_N_MARK, +}; +static const unsigned int vin0_field_pins[] = { + RCAR_GP_PIN(3, 10), +}; +static const unsigned int vin0_field_mux[] = { + VI0_FIELD_MARK, +}; +static const unsigned int vin0_clkenb_pins[] = { + RCAR_GP_PIN(3, 9), +}; +static const unsigned int vin0_clkenb_mux[] = { + VI0_CLKENB_MARK, +}; +static const unsigned int vin0_clk_pins[] = { + RCAR_GP_PIN(3, 0), +}; +static const unsigned int vin0_clk_mux[] = { + VI0_CLK_MARK, +}; +/* - VIN1 ------------------------------------------------------------------- */ +static const union vin_data vin1_data_pins = { + .data12 = { + RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 13), + RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15), + RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 17), + RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19), + RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 11), + RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13), + }, +}; +static const union vin_data vin1_data_mux = { + .data12 = { + VI1_DATA0_MARK, VI1_DATA1_MARK, + VI1_DATA2_MARK, VI1_DATA3_MARK, + VI1_DATA4_MARK, VI1_DATA5_MARK, + VI1_DATA6_MARK, VI1_DATA7_MARK, + VI1_DATA8_MARK, VI1_DATA9_MARK, + VI1_DATA10_MARK, VI1_DATA11_MARK, + }, +}; +static const unsigned int vin1_sync_pins[] = { + RCAR_GP_PIN(5, 22), /* HSYNC */ + RCAR_GP_PIN(5, 23), /* VSYNC */ +}; +static const unsigned int vin1_sync_mux[] = { + VI1_HSYNC_N_MARK, + VI1_VSYNC_N_MARK, +}; +static const unsigned int vin1_field_pins[] = { + RCAR_GP_PIN(5, 21), +}; +static const unsigned int vin1_field_mux[] = { + VI1_FIELD_MARK, +}; +static const unsigned int vin1_clkenb_pins[] = { + RCAR_GP_PIN(5, 20), +}; +static const unsigned int vin1_clkenb_mux[] = { + VI1_CLKENB_MARK, +}; +static const unsigned int vin1_clk_pins[] = { + RCAR_GP_PIN(5, 11), +}; +static const unsigned int vin1_clk_mux[] = { + VI1_CLK_MARK, +}; static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(eth_link), @@ -2949,6 +3089,24 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(sdhi2_wp), SH_PFC_PIN_GROUP(usb0), SH_PFC_PIN_GROUP(usb1), + VIN_DATA_PIN_GROUP(vin0_data, 24), + VIN_DATA_PIN_GROUP(vin0_data, 20), + SH_PFC_PIN_GROUP(vin0_data18), + VIN_DATA_PIN_GROUP(vin0_data, 16), + VIN_DATA_PIN_GROUP(vin0_data, 12), + VIN_DATA_PIN_GROUP(vin0_data, 10), + VIN_DATA_PIN_GROUP(vin0_data, 8), + SH_PFC_PIN_GROUP(vin0_sync), + SH_PFC_PIN_GROUP(vin0_field), + SH_PFC_PIN_GROUP(vin0_clkenb), + SH_PFC_PIN_GROUP(vin0_clk), + VIN_DATA_PIN_GROUP(vin1_data, 12), + VIN_DATA_PIN_GROUP(vin1_data, 10), + VIN_DATA_PIN_GROUP(vin1_data, 8), + SH_PFC_PIN_GROUP(vin1_sync), + SH_PFC_PIN_GROUP(vin1_field), + SH_PFC_PIN_GROUP(vin1_clkenb), + SH_PFC_PIN_GROUP(vin1_clk), }; static const char * const eth_groups[] = { @@ -3229,6 +3387,30 @@ static const char * const usb1_groups[] = { "usb1", }; +static const char * const vin0_groups[] = { + "vin0_data24", + "vin0_data20", + "vin0_data18", + "vin0_data16", + "vin0_data12", + "vin0_data10", + "vin0_data8", + "vin0_sync", + "vin0_field", + "vin0_clkenb", + "vin0_clk", +}; + +static const char * const vin1_groups[] = { + "vin1_data12", + "vin1_data10", + "vin1_data8", + "vin1_sync", + "vin1_field", + "vin1_clkenb", + "vin1_clk", +}; + static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(eth), SH_PFC_FUNCTION(hscif0), @@ -3265,6 +3447,8 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(sdhi2), SH_PFC_FUNCTION(usb0), SH_PFC_FUNCTION(usb1), + SH_PFC_FUNCTION(vin0), + SH_PFC_FUNCTION(vin1), }; static const struct pinmux_cfg_reg pinmux_config_regs[] = { -- cgit v0.10.2 From 22768fc60abbf58b04601b27796268f0363ab185 Mon Sep 17 00:00:00 2001 From: Ulrich Hecht Date: Mon, 5 Oct 2015 16:55:53 +0200 Subject: pinctrl: sh-pfc: Add macros defining GP ports with config flags PORT_GP_CFG_1 and PORT_GP_CFG_32 work like their non-CFG counterparts but accept an extra argument with config flags. Signed-off-by: Ulrich Hecht Acked-by: Laurent Pinchart Acked-by: Linus Walleij Signed-off-by: Geert Uytterhoeven diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h index 6ab4b46..8b14536 100644 --- a/drivers/pinctrl/sh-pfc/sh_pfc.h +++ b/drivers/pinctrl/sh-pfc/sh_pfc.h @@ -202,25 +202,27 @@ struct sh_pfc_soc_info { * GP port style (32 ports banks) */ -#define PORT_GP_1(bank, pin, fn, sfx) fn(bank, pin, GP_##bank##_##pin, sfx) - -#define PORT_GP_32(bank, fn, sfx) \ - PORT_GP_1(bank, 0, fn, sfx), PORT_GP_1(bank, 1, fn, sfx), \ - PORT_GP_1(bank, 2, fn, sfx), PORT_GP_1(bank, 3, fn, sfx), \ - PORT_GP_1(bank, 4, fn, sfx), PORT_GP_1(bank, 5, fn, sfx), \ - PORT_GP_1(bank, 6, fn, sfx), PORT_GP_1(bank, 7, fn, sfx), \ - PORT_GP_1(bank, 8, fn, sfx), PORT_GP_1(bank, 9, fn, sfx), \ - PORT_GP_1(bank, 10, fn, sfx), PORT_GP_1(bank, 11, fn, sfx), \ - PORT_GP_1(bank, 12, fn, sfx), PORT_GP_1(bank, 13, fn, sfx), \ - PORT_GP_1(bank, 14, fn, sfx), PORT_GP_1(bank, 15, fn, sfx), \ - PORT_GP_1(bank, 16, fn, sfx), PORT_GP_1(bank, 17, fn, sfx), \ - PORT_GP_1(bank, 18, fn, sfx), PORT_GP_1(bank, 19, fn, sfx), \ - PORT_GP_1(bank, 20, fn, sfx), PORT_GP_1(bank, 21, fn, sfx), \ - PORT_GP_1(bank, 22, fn, sfx), PORT_GP_1(bank, 23, fn, sfx), \ - PORT_GP_1(bank, 24, fn, sfx), PORT_GP_1(bank, 25, fn, sfx), \ - PORT_GP_1(bank, 26, fn, sfx), PORT_GP_1(bank, 27, fn, sfx), \ - PORT_GP_1(bank, 28, fn, sfx), PORT_GP_1(bank, 29, fn, sfx), \ - PORT_GP_1(bank, 30, fn, sfx), PORT_GP_1(bank, 31, fn, sfx) +#define PORT_GP_CFG_1(bank, pin, fn, sfx, cfg) fn(bank, pin, GP_##bank##_##pin, sfx, cfg) +#define PORT_GP_1(bank, pin, fn, sfx) PORT_GP_CFG_1(bank, pin, fn, sfx, 0) + +#define PORT_GP_CFG_32(bank, fn, sfx, cfg) \ + PORT_GP_CFG_1(bank, 0, fn, sfx, cfg), PORT_GP_CFG_1(bank, 1, fn, sfx, cfg), \ + PORT_GP_CFG_1(bank, 2, fn, sfx, cfg), PORT_GP_CFG_1(bank, 3, fn, sfx, cfg), \ + PORT_GP_CFG_1(bank, 4, fn, sfx, cfg), PORT_GP_CFG_1(bank, 5, fn, sfx, cfg), \ + PORT_GP_CFG_1(bank, 6, fn, sfx, cfg), PORT_GP_CFG_1(bank, 7, fn, sfx, cfg), \ + PORT_GP_CFG_1(bank, 8, fn, sfx, cfg), PORT_GP_CFG_1(bank, 9, fn, sfx, cfg), \ + PORT_GP_CFG_1(bank, 10, fn, sfx, cfg), PORT_GP_CFG_1(bank, 11, fn, sfx, cfg), \ + PORT_GP_CFG_1(bank, 12, fn, sfx, cfg), PORT_GP_CFG_1(bank, 13, fn, sfx, cfg), \ + PORT_GP_CFG_1(bank, 14, fn, sfx, cfg), PORT_GP_CFG_1(bank, 15, fn, sfx, cfg), \ + PORT_GP_CFG_1(bank, 16, fn, sfx, cfg), PORT_GP_CFG_1(bank, 17, fn, sfx, cfg), \ + PORT_GP_CFG_1(bank, 18, fn, sfx, cfg), PORT_GP_CFG_1(bank, 19, fn, sfx, cfg), \ + PORT_GP_CFG_1(bank, 20, fn, sfx, cfg), PORT_GP_CFG_1(bank, 21, fn, sfx, cfg), \ + PORT_GP_CFG_1(bank, 22, fn, sfx, cfg), PORT_GP_CFG_1(bank, 23, fn, sfx, cfg), \ + PORT_GP_CFG_1(bank, 24, fn, sfx, cfg), PORT_GP_CFG_1(bank, 25, fn, sfx, cfg), \ + PORT_GP_CFG_1(bank, 26, fn, sfx, cfg), PORT_GP_CFG_1(bank, 27, fn, sfx, cfg), \ + PORT_GP_CFG_1(bank, 28, fn, sfx, cfg), PORT_GP_CFG_1(bank, 29, fn, sfx, cfg), \ + PORT_GP_CFG_1(bank, 30, fn, sfx, cfg), PORT_GP_CFG_1(bank, 31, fn, sfx, cfg) +#define PORT_GP_32(bank, fn, sfx) PORT_GP_CFG_32(bank, fn, sfx, 0) #define PORT_GP_32_REV(bank, fn, sfx) \ PORT_GP_1(bank, 31, fn, sfx), PORT_GP_1(bank, 30, fn, sfx), \ @@ -241,20 +243,21 @@ struct sh_pfc_soc_info { PORT_GP_1(bank, 1, fn, sfx), PORT_GP_1(bank, 0, fn, sfx) /* GP_ALL(suffix) - Expand to a list of GP_#_#_suffix */ -#define _GP_ALL(bank, pin, name, sfx) name##_##sfx +#define _GP_ALL(bank, pin, name, sfx, cfg) name##_##sfx #define GP_ALL(str) CPU_ALL_PORT(_GP_ALL, str) /* PINMUX_GPIO_GP_ALL - Expand to a list of sh_pfc_pin entries */ -#define _GP_GPIO(bank, _pin, _name, sfx) \ +#define _GP_GPIO(bank, _pin, _name, sfx, cfg) \ { \ .pin = (bank * 32) + _pin, \ .name = __stringify(_name), \ .enum_id = _name##_DATA, \ + .configs = cfg, \ } #define PINMUX_GPIO_GP_ALL() CPU_ALL_PORT(_GP_GPIO, unused) /* PINMUX_DATA_GP_ALL - Expand to a list of name_DATA, name_FN marks */ -#define _GP_DATA(bank, pin, name, sfx) PINMUX_DATA(name##_DATA, name##_FN) +#define _GP_DATA(bank, pin, name, sfx, cfg) PINMUX_DATA(name##_DATA, name##_FN) #define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_GP_DATA, unused) /* -- cgit v0.10.2 From ae7465a0972aee889d79d94dbd1e65d3fab07414 Mon Sep 17 00:00:00 2001 From: Ulrich Hecht Date: Mon, 5 Oct 2015 16:55:54 +0200 Subject: pinctrl: sh-pfc: r8a7778: Add bias (pull-up) pinconf support On this SoC there is no simple mapping of GP pins to pull-up register bits, so we need a table. Signed-off-by: Ulrich Hecht Reviewed-by: Geert Uytterhoeven Acked-by: Laurent Pinchart Acked-by: Linus Walleij Signed-off-by: Geert Uytterhoeven diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7778.c b/drivers/pinctrl/sh-pfc/pfc-r8a7778.c index c7d610d..1a4e851 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7778.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7778.c @@ -4,6 +4,7 @@ * Copyright (C) 2013 Renesas Solutions Corp. * Copyright (C) 2013 Kuninori Morimoto * Copyright (C) 2013 Cogent Embedded, Inc. + * Copyright (C) 2015 Ulrich Hecht * * based on * Copyright (C) 2011 Renesas Solutions Corp. @@ -19,32 +20,38 @@ * GNU General Public License for more details. */ -#include +#include #include +#include +#include +#include "core.h" #include "sh_pfc.h" -#define PORT_GP_27(bank, fn, sfx) \ - PORT_GP_1(bank, 0, fn, sfx), PORT_GP_1(bank, 1, fn, sfx), \ - PORT_GP_1(bank, 2, fn, sfx), PORT_GP_1(bank, 3, fn, sfx), \ - PORT_GP_1(bank, 4, fn, sfx), PORT_GP_1(bank, 5, fn, sfx), \ - PORT_GP_1(bank, 6, fn, sfx), PORT_GP_1(bank, 7, fn, sfx), \ - PORT_GP_1(bank, 8, fn, sfx), PORT_GP_1(bank, 9, fn, sfx), \ - PORT_GP_1(bank, 10, fn, sfx), PORT_GP_1(bank, 11, fn, sfx), \ - PORT_GP_1(bank, 12, fn, sfx), PORT_GP_1(bank, 13, fn, sfx), \ - PORT_GP_1(bank, 14, fn, sfx), PORT_GP_1(bank, 15, fn, sfx), \ - PORT_GP_1(bank, 16, fn, sfx), PORT_GP_1(bank, 17, fn, sfx), \ - PORT_GP_1(bank, 18, fn, sfx), PORT_GP_1(bank, 19, fn, sfx), \ - PORT_GP_1(bank, 20, fn, sfx), PORT_GP_1(bank, 21, fn, sfx), \ - PORT_GP_1(bank, 22, fn, sfx), PORT_GP_1(bank, 23, fn, sfx), \ - PORT_GP_1(bank, 24, fn, sfx), PORT_GP_1(bank, 25, fn, sfx), \ - PORT_GP_1(bank, 26, fn, sfx) +#define PORT_GP_PUP_1(bank, pin, fn, sfx) \ + PORT_GP_CFG_1(bank, pin, fn, sfx, SH_PFC_PIN_CFG_PULL_UP) + +#define PORT_GP_PUP_27(bank, fn, sfx) \ + PORT_GP_PUP_1(bank, 0, fn, sfx), PORT_GP_PUP_1(bank, 1, fn, sfx), \ + PORT_GP_PUP_1(bank, 2, fn, sfx), PORT_GP_PUP_1(bank, 3, fn, sfx), \ + PORT_GP_PUP_1(bank, 4, fn, sfx), PORT_GP_PUP_1(bank, 5, fn, sfx), \ + PORT_GP_PUP_1(bank, 6, fn, sfx), PORT_GP_PUP_1(bank, 7, fn, sfx), \ + PORT_GP_PUP_1(bank, 8, fn, sfx), PORT_GP_PUP_1(bank, 9, fn, sfx), \ + PORT_GP_PUP_1(bank, 10, fn, sfx), PORT_GP_PUP_1(bank, 11, fn, sfx), \ + PORT_GP_PUP_1(bank, 12, fn, sfx), PORT_GP_PUP_1(bank, 13, fn, sfx), \ + PORT_GP_PUP_1(bank, 14, fn, sfx), PORT_GP_PUP_1(bank, 15, fn, sfx), \ + PORT_GP_PUP_1(bank, 16, fn, sfx), PORT_GP_PUP_1(bank, 17, fn, sfx), \ + PORT_GP_PUP_1(bank, 18, fn, sfx), PORT_GP_PUP_1(bank, 19, fn, sfx), \ + PORT_GP_PUP_1(bank, 20, fn, sfx), PORT_GP_PUP_1(bank, 21, fn, sfx), \ + PORT_GP_PUP_1(bank, 22, fn, sfx), PORT_GP_PUP_1(bank, 23, fn, sfx), \ + PORT_GP_PUP_1(bank, 24, fn, sfx), PORT_GP_PUP_1(bank, 25, fn, sfx), \ + PORT_GP_PUP_1(bank, 26, fn, sfx) #define CPU_ALL_PORT(fn, sfx) \ - PORT_GP_32(0, fn, sfx), \ - PORT_GP_32(1, fn, sfx), \ - PORT_GP_32(2, fn, sfx), \ - PORT_GP_32(3, fn, sfx), \ - PORT_GP_27(4, fn, sfx) + PORT_GP_CFG_32(0, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_32(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_32(2, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_32(3, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_PUP_27(4, fn, sfx) enum { PINMUX_RESERVED = 0, @@ -2905,8 +2912,222 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { { }, }; +#define PUPR0 0x100 +#define PUPR1 0x104 +#define PUPR2 0x108 +#define PUPR3 0x10c +#define PUPR4 0x110 +#define PUPR5 0x114 + +static const struct { + u16 reg : 11; + u16 bit : 5; +} pullups[] = { + [RCAR_GP_PIN(0, 6)] = { PUPR0, 0 }, /* A0 */ + [RCAR_GP_PIN(0, 7)] = { PUPR0, 1 }, /* A1 */ + [RCAR_GP_PIN(0, 8)] = { PUPR0, 2 }, /* A2 */ + [RCAR_GP_PIN(0, 9)] = { PUPR0, 3 }, /* A3 */ + [RCAR_GP_PIN(0, 10)] = { PUPR0, 4 }, /* A4 */ + [RCAR_GP_PIN(0, 11)] = { PUPR0, 5 }, /* A5 */ + [RCAR_GP_PIN(0, 12)] = { PUPR0, 6 }, /* A6 */ + [RCAR_GP_PIN(0, 13)] = { PUPR0, 7 }, /* A7 */ + [RCAR_GP_PIN(0, 14)] = { PUPR0, 8 }, /* A8 */ + [RCAR_GP_PIN(0, 15)] = { PUPR0, 9 }, /* A9 */ + [RCAR_GP_PIN(0, 16)] = { PUPR0, 10 }, /* A10 */ + [RCAR_GP_PIN(0, 17)] = { PUPR0, 11 }, /* A11 */ + [RCAR_GP_PIN(0, 18)] = { PUPR0, 12 }, /* A12 */ + [RCAR_GP_PIN(0, 19)] = { PUPR0, 13 }, /* A13 */ + [RCAR_GP_PIN(0, 20)] = { PUPR0, 14 }, /* A14 */ + [RCAR_GP_PIN(0, 21)] = { PUPR0, 15 }, /* A15 */ + [RCAR_GP_PIN(0, 22)] = { PUPR0, 16 }, /* A16 */ + [RCAR_GP_PIN(0, 23)] = { PUPR0, 17 }, /* A17 */ + [RCAR_GP_PIN(0, 24)] = { PUPR0, 18 }, /* A18 */ + [RCAR_GP_PIN(0, 25)] = { PUPR0, 19 }, /* A19 */ + [RCAR_GP_PIN(0, 26)] = { PUPR0, 20 }, /* A20 */ + [RCAR_GP_PIN(0, 27)] = { PUPR0, 21 }, /* A21 */ + [RCAR_GP_PIN(0, 28)] = { PUPR0, 22 }, /* A22 */ + [RCAR_GP_PIN(0, 29)] = { PUPR0, 23 }, /* A23 */ + [RCAR_GP_PIN(0, 30)] = { PUPR0, 24 }, /* A24 */ + [RCAR_GP_PIN(0, 31)] = { PUPR0, 25 }, /* A25 */ + [RCAR_GP_PIN(1, 3)] = { PUPR0, 26 }, /* /EX_CS0 */ + [RCAR_GP_PIN(1, 4)] = { PUPR0, 27 }, /* /EX_CS1 */ + [RCAR_GP_PIN(1, 5)] = { PUPR0, 28 }, /* /EX_CS2 */ + [RCAR_GP_PIN(1, 6)] = { PUPR0, 29 }, /* /EX_CS3 */ + [RCAR_GP_PIN(1, 7)] = { PUPR0, 30 }, /* /EX_CS4 */ + [RCAR_GP_PIN(1, 8)] = { PUPR0, 31 }, /* /EX_CS5 */ + + [RCAR_GP_PIN(0, 0)] = { PUPR1, 0 }, /* /PRESETOUT */ + [RCAR_GP_PIN(0, 5)] = { PUPR1, 1 }, /* /BS */ + [RCAR_GP_PIN(1, 0)] = { PUPR1, 2 }, /* RD//WR */ + [RCAR_GP_PIN(1, 1)] = { PUPR1, 3 }, /* /WE0 */ + [RCAR_GP_PIN(1, 2)] = { PUPR1, 4 }, /* /WE1 */ + [RCAR_GP_PIN(1, 11)] = { PUPR1, 5 }, /* EX_WAIT0 */ + [RCAR_GP_PIN(1, 9)] = { PUPR1, 6 }, /* DREQ0 */ + [RCAR_GP_PIN(1, 10)] = { PUPR1, 7 }, /* DACK0 */ + [RCAR_GP_PIN(1, 12)] = { PUPR1, 8 }, /* IRQ0 */ + [RCAR_GP_PIN(1, 13)] = { PUPR1, 9 }, /* IRQ1 */ + + [RCAR_GP_PIN(1, 22)] = { PUPR2, 0 }, /* DU0_DR0 */ + [RCAR_GP_PIN(1, 23)] = { PUPR2, 1 }, /* DU0_DR1 */ + [RCAR_GP_PIN(1, 24)] = { PUPR2, 2 }, /* DU0_DR2 */ + [RCAR_GP_PIN(1, 25)] = { PUPR2, 3 }, /* DU0_DR3 */ + [RCAR_GP_PIN(1, 26)] = { PUPR2, 4 }, /* DU0_DR4 */ + [RCAR_GP_PIN(1, 27)] = { PUPR2, 5 }, /* DU0_DR5 */ + [RCAR_GP_PIN(1, 28)] = { PUPR2, 6 }, /* DU0_DR6 */ + [RCAR_GP_PIN(1, 29)] = { PUPR2, 7 }, /* DU0_DR7 */ + [RCAR_GP_PIN(1, 30)] = { PUPR2, 8 }, /* DU0_DG0 */ + [RCAR_GP_PIN(1, 31)] = { PUPR2, 9 }, /* DU0_DG1 */ + [RCAR_GP_PIN(2, 0)] = { PUPR2, 10 }, /* DU0_DG2 */ + [RCAR_GP_PIN(2, 1)] = { PUPR2, 11 }, /* DU0_DG3 */ + [RCAR_GP_PIN(2, 2)] = { PUPR2, 12 }, /* DU0_DG4 */ + [RCAR_GP_PIN(2, 3)] = { PUPR2, 13 }, /* DU0_DG5 */ + [RCAR_GP_PIN(2, 4)] = { PUPR2, 14 }, /* DU0_DG6 */ + [RCAR_GP_PIN(2, 5)] = { PUPR2, 15 }, /* DU0_DG7 */ + [RCAR_GP_PIN(2, 6)] = { PUPR2, 16 }, /* DU0_DB0 */ + [RCAR_GP_PIN(2, 7)] = { PUPR2, 17 }, /* DU0_DB1 */ + [RCAR_GP_PIN(2, 8)] = { PUPR2, 18 }, /* DU0_DB2 */ + [RCAR_GP_PIN(2, 9)] = { PUPR2, 19 }, /* DU0_DB3 */ + [RCAR_GP_PIN(2, 10)] = { PUPR2, 20 }, /* DU0_DB4 */ + [RCAR_GP_PIN(2, 11)] = { PUPR2, 21 }, /* DU0_DB5 */ + [RCAR_GP_PIN(2, 12)] = { PUPR2, 22 }, /* DU0_DB6 */ + [RCAR_GP_PIN(2, 13)] = { PUPR2, 23 }, /* DU0_DB7 */ + [RCAR_GP_PIN(2, 14)] = { PUPR2, 24 }, /* DU0_DOTCLKIN */ + [RCAR_GP_PIN(2, 15)] = { PUPR2, 25 }, /* DU0_DOTCLKOUT0 */ + [RCAR_GP_PIN(2, 17)] = { PUPR2, 26 }, /* DU0_HSYNC */ + [RCAR_GP_PIN(2, 18)] = { PUPR2, 27 }, /* DU0_VSYNC */ + [RCAR_GP_PIN(2, 19)] = { PUPR2, 28 }, /* DU0_EXODDF */ + [RCAR_GP_PIN(2, 20)] = { PUPR2, 29 }, /* DU0_DISP */ + [RCAR_GP_PIN(2, 21)] = { PUPR2, 30 }, /* DU0_CDE */ + [RCAR_GP_PIN(2, 16)] = { PUPR2, 31 }, /* DU0_DOTCLKOUT1 */ + + [RCAR_GP_PIN(3, 24)] = { PUPR3, 0 }, /* VI0_CLK */ + [RCAR_GP_PIN(3, 25)] = { PUPR3, 1 }, /* VI0_CLKENB */ + [RCAR_GP_PIN(3, 26)] = { PUPR3, 2 }, /* VI0_FIELD */ + [RCAR_GP_PIN(3, 27)] = { PUPR3, 3 }, /* /VI0_HSYNC */ + [RCAR_GP_PIN(3, 28)] = { PUPR3, 4 }, /* /VI0_VSYNC */ + [RCAR_GP_PIN(3, 29)] = { PUPR3, 5 }, /* VI0_DATA0 */ + [RCAR_GP_PIN(3, 30)] = { PUPR3, 6 }, /* VI0_DATA1 */ + [RCAR_GP_PIN(3, 31)] = { PUPR3, 7 }, /* VI0_DATA2 */ + [RCAR_GP_PIN(4, 0)] = { PUPR3, 8 }, /* VI0_DATA3 */ + [RCAR_GP_PIN(4, 1)] = { PUPR3, 9 }, /* VI0_DATA4 */ + [RCAR_GP_PIN(4, 2)] = { PUPR3, 10 }, /* VI0_DATA5 */ + [RCAR_GP_PIN(4, 3)] = { PUPR3, 11 }, /* VI0_DATA6 */ + [RCAR_GP_PIN(4, 4)] = { PUPR3, 12 }, /* VI0_DATA7 */ + [RCAR_GP_PIN(4, 5)] = { PUPR3, 13 }, /* VI0_G2 */ + [RCAR_GP_PIN(4, 6)] = { PUPR3, 14 }, /* VI0_G3 */ + [RCAR_GP_PIN(4, 7)] = { PUPR3, 15 }, /* VI0_G4 */ + [RCAR_GP_PIN(4, 8)] = { PUPR3, 16 }, /* VI0_G5 */ + [RCAR_GP_PIN(4, 21)] = { PUPR3, 17 }, /* VI1_DATA12 */ + [RCAR_GP_PIN(4, 22)] = { PUPR3, 18 }, /* VI1_DATA13 */ + [RCAR_GP_PIN(4, 23)] = { PUPR3, 19 }, /* VI1_DATA14 */ + [RCAR_GP_PIN(4, 24)] = { PUPR3, 20 }, /* VI1_DATA15 */ + [RCAR_GP_PIN(4, 9)] = { PUPR3, 21 }, /* ETH_REF_CLK */ + [RCAR_GP_PIN(4, 10)] = { PUPR3, 22 }, /* ETH_TXD0 */ + [RCAR_GP_PIN(4, 11)] = { PUPR3, 23 }, /* ETH_TXD1 */ + [RCAR_GP_PIN(4, 12)] = { PUPR3, 24 }, /* ETH_CRS_DV */ + [RCAR_GP_PIN(4, 13)] = { PUPR3, 25 }, /* ETH_TX_EN */ + [RCAR_GP_PIN(4, 14)] = { PUPR3, 26 }, /* ETH_RX_ER */ + [RCAR_GP_PIN(4, 15)] = { PUPR3, 27 }, /* ETH_RXD0 */ + [RCAR_GP_PIN(4, 16)] = { PUPR3, 28 }, /* ETH_RXD1 */ + [RCAR_GP_PIN(4, 17)] = { PUPR3, 29 }, /* ETH_MDC */ + [RCAR_GP_PIN(4, 18)] = { PUPR3, 30 }, /* ETH_MDIO */ + [RCAR_GP_PIN(4, 19)] = { PUPR3, 31 }, /* ETH_LINK */ + + [RCAR_GP_PIN(3, 6)] = { PUPR4, 0 }, /* SSI_SCK012 */ + [RCAR_GP_PIN(3, 7)] = { PUPR4, 1 }, /* SSI_WS012 */ + [RCAR_GP_PIN(3, 10)] = { PUPR4, 2 }, /* SSI_SDATA0 */ + [RCAR_GP_PIN(3, 9)] = { PUPR4, 3 }, /* SSI_SDATA1 */ + [RCAR_GP_PIN(3, 8)] = { PUPR4, 4 }, /* SSI_SDATA2 */ + [RCAR_GP_PIN(3, 2)] = { PUPR4, 5 }, /* SSI_SCK34 */ + [RCAR_GP_PIN(3, 3)] = { PUPR4, 6 }, /* SSI_WS34 */ + [RCAR_GP_PIN(3, 5)] = { PUPR4, 7 }, /* SSI_SDATA3 */ + [RCAR_GP_PIN(3, 4)] = { PUPR4, 8 }, /* SSI_SDATA4 */ + [RCAR_GP_PIN(2, 31)] = { PUPR4, 9 }, /* SSI_SCK5 */ + [RCAR_GP_PIN(3, 0)] = { PUPR4, 10 }, /* SSI_WS5 */ + [RCAR_GP_PIN(3, 1)] = { PUPR4, 11 }, /* SSI_SDATA5 */ + [RCAR_GP_PIN(2, 28)] = { PUPR4, 12 }, /* SSI_SCK6 */ + [RCAR_GP_PIN(2, 29)] = { PUPR4, 13 }, /* SSI_WS6 */ + [RCAR_GP_PIN(2, 30)] = { PUPR4, 14 }, /* SSI_SDATA6 */ + [RCAR_GP_PIN(2, 24)] = { PUPR4, 15 }, /* SSI_SCK78 */ + [RCAR_GP_PIN(2, 25)] = { PUPR4, 16 }, /* SSI_WS78 */ + [RCAR_GP_PIN(2, 27)] = { PUPR4, 17 }, /* SSI_SDATA7 */ + [RCAR_GP_PIN(2, 26)] = { PUPR4, 18 }, /* SSI_SDATA8 */ + [RCAR_GP_PIN(3, 23)] = { PUPR4, 19 }, /* TCLK0 */ + [RCAR_GP_PIN(3, 11)] = { PUPR4, 20 }, /* SD0_CLK */ + [RCAR_GP_PIN(3, 12)] = { PUPR4, 21 }, /* SD0_CMD */ + [RCAR_GP_PIN(3, 13)] = { PUPR4, 22 }, /* SD0_DAT0 */ + [RCAR_GP_PIN(3, 14)] = { PUPR4, 23 }, /* SD0_DAT1 */ + [RCAR_GP_PIN(3, 15)] = { PUPR4, 24 }, /* SD0_DAT2 */ + [RCAR_GP_PIN(3, 16)] = { PUPR4, 25 }, /* SD0_DAT3 */ + [RCAR_GP_PIN(3, 17)] = { PUPR4, 26 }, /* SD0_CD */ + [RCAR_GP_PIN(3, 18)] = { PUPR4, 27 }, /* SD0_WP */ + [RCAR_GP_PIN(2, 22)] = { PUPR4, 28 }, /* AUDIO_CLKA */ + [RCAR_GP_PIN(2, 23)] = { PUPR4, 29 }, /* AUDIO_CLKB */ + [RCAR_GP_PIN(1, 14)] = { PUPR4, 30 }, /* IRQ2 */ + [RCAR_GP_PIN(1, 15)] = { PUPR4, 31 }, /* IRQ3 */ + + [RCAR_GP_PIN(0, 1)] = { PUPR5, 0 }, /* PENC0 */ + [RCAR_GP_PIN(0, 2)] = { PUPR5, 1 }, /* PENC1 */ + [RCAR_GP_PIN(0, 3)] = { PUPR5, 2 }, /* USB_OVC0 */ + [RCAR_GP_PIN(0, 4)] = { PUPR5, 3 }, /* USB_OVC1 */ + [RCAR_GP_PIN(1, 16)] = { PUPR5, 4 }, /* SCIF_CLK */ + [RCAR_GP_PIN(1, 17)] = { PUPR5, 5 }, /* TX0 */ + [RCAR_GP_PIN(1, 18)] = { PUPR5, 6 }, /* RX0 */ + [RCAR_GP_PIN(1, 19)] = { PUPR5, 7 }, /* SCK0 */ + [RCAR_GP_PIN(1, 20)] = { PUPR5, 8 }, /* /CTS0 */ + [RCAR_GP_PIN(1, 21)] = { PUPR5, 9 }, /* /RTS0 */ + [RCAR_GP_PIN(3, 19)] = { PUPR5, 10 }, /* HSPI_CLK0 */ + [RCAR_GP_PIN(3, 20)] = { PUPR5, 11 }, /* /HSPI_CS0 */ + [RCAR_GP_PIN(3, 21)] = { PUPR5, 12 }, /* HSPI_RX0 */ + [RCAR_GP_PIN(3, 22)] = { PUPR5, 13 }, /* HSPI_TX0 */ + [RCAR_GP_PIN(4, 20)] = { PUPR5, 14 }, /* ETH_MAGIC */ + [RCAR_GP_PIN(4, 25)] = { PUPR5, 15 }, /* AVS1 */ + [RCAR_GP_PIN(4, 26)] = { PUPR5, 16 }, /* AVS2 */ +}; + +static unsigned int r8a7778_pinmux_get_bias(struct sh_pfc *pfc, + unsigned int pin) +{ + void __iomem *addr; + + if (WARN_ON_ONCE(!pullups[pin].reg)) + return PIN_CONFIG_BIAS_DISABLE; + + addr = pfc->windows->virt + pullups[pin].reg; + + if (ioread32(addr) & BIT(pullups[pin].bit)) + return PIN_CONFIG_BIAS_PULL_UP; + else + return PIN_CONFIG_BIAS_DISABLE; +} + +static void r8a7778_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, + unsigned int bias) +{ + void __iomem *addr; + u32 value; + u32 bit; + + if (WARN_ON_ONCE(!pullups[pin].reg)) + return; + + addr = pfc->windows->virt + pullups[pin].reg; + bit = BIT(pullups[pin].bit); + + value = ioread32(addr) & ~bit; + if (bias == PIN_CONFIG_BIAS_PULL_UP) + value |= bit; + iowrite32(value, addr); +} + +static const struct sh_pfc_soc_operations r8a7778_pfc_ops = { + .get_bias = r8a7778_pinmux_get_bias, + .set_bias = r8a7778_pinmux_set_bias, +}; + const struct sh_pfc_soc_info r8a7778_pinmux_info = { .name = "r8a7778_pfc", + .ops = &r8a7778_pfc_ops, .unlock_reg = 0xfffc0000, /* PMMR */ -- cgit v0.10.2 From b8b47d678a5f0b5826044242780a988f8af50b22 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 21 Sep 2015 16:27:23 +0200 Subject: pinctrl: sh-pfc: Rename .gpio_data[] to .pinmux_data[] The sh_pfc_soc_info.gpio_data[] array contains not only GPIO data, but also various other pinmux-related data (functions and marks). Every single driver already calls its local array pinmux_data[]. Hence rename the sh_pfc_soc_info member to "pinmux_data". Signed-off-by: Geert Uytterhoeven Acked-by: Linus Walleij Acked-by: Laurent Pinchart diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c index bcf3017..e6a5174 100644 --- a/drivers/pinctrl/sh-pfc/core.c +++ b/drivers/pinctrl/sh-pfc/core.c @@ -272,7 +272,7 @@ static int sh_pfc_get_config_reg(struct sh_pfc *pfc, u16 enum_id, static int sh_pfc_mark_to_enum(struct sh_pfc *pfc, u16 mark, int pos, u16 *enum_idp) { - const u16 *data = pfc->info->gpio_data; + const u16 *data = pfc->info->pinmux_data; unsigned int k; if (pos) { @@ -280,7 +280,7 @@ static int sh_pfc_mark_to_enum(struct sh_pfc *pfc, u16 mark, int pos, return pos + 1; } - for (k = 0; k < pfc->info->gpio_data_size; k++) { + for (k = 0; k < pfc->info->pinmux_data_size; k++) { if (data[k] == mark) { *enum_idp = data[k + 1]; return k + 1; diff --git a/drivers/pinctrl/sh-pfc/pfc-emev2.c b/drivers/pinctrl/sh-pfc/pfc-emev2.c index 849c694..02118ab 100644 --- a/drivers/pinctrl/sh-pfc/pfc-emev2.c +++ b/drivers/pinctrl/sh-pfc/pfc-emev2.c @@ -1706,6 +1706,6 @@ const struct sh_pfc_soc_info emev2_pinmux_info = { .cfg_regs = pinmux_config_regs, - .gpio_data = pinmux_data, - .gpio_data_size = ARRAY_SIZE(pinmux_data), + .pinmux_data = pinmux_data, + .pinmux_data_size = ARRAY_SIZE(pinmux_data), }; diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c b/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c index d51d5fd..d9d9228 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c @@ -2734,11 +2734,11 @@ const struct sh_pfc_soc_info r8a73a4_pinmux_info = { .functions = pinmux_functions, .nr_functions = ARRAY_SIZE(pinmux_functions), - .cfg_regs = pinmux_config_regs, - .data_regs = pinmux_data_regs, + .cfg_regs = pinmux_config_regs, + .data_regs = pinmux_data_regs, - .gpio_data = pinmux_data, - .gpio_data_size = ARRAY_SIZE(pinmux_data), + .pinmux_data = pinmux_data, + .pinmux_data_size = ARRAY_SIZE(pinmux_data), .gpio_irq = pinmux_irqs, .gpio_irq_size = ARRAY_SIZE(pinmux_irqs), diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c index 44223b3..279e9dd 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c @@ -3774,8 +3774,8 @@ const struct sh_pfc_soc_info r8a7740_pinmux_info = { .cfg_regs = pinmux_config_regs, .data_regs = pinmux_data_regs, - .gpio_data = pinmux_data, - .gpio_data_size = ARRAY_SIZE(pinmux_data), + .pinmux_data = pinmux_data, + .pinmux_data_size = ARRAY_SIZE(pinmux_data), .gpio_irq = pinmux_irqs, .gpio_irq_size = ARRAY_SIZE(pinmux_irqs), diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7778.c b/drivers/pinctrl/sh-pfc/pfc-r8a7778.c index 1a4e851..f35a3fc 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7778.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7778.c @@ -3144,6 +3144,6 @@ const struct sh_pfc_soc_info r8a7778_pinmux_info = { .cfg_regs = pinmux_config_regs, - .gpio_data = pinmux_data, - .gpio_data_size = ARRAY_SIZE(pinmux_data), + .pinmux_data = pinmux_data, + .pinmux_data_size = ARRAY_SIZE(pinmux_data), }; diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c index 4be082e..71fb5e4 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c @@ -3868,6 +3868,6 @@ const struct sh_pfc_soc_info r8a7779_pinmux_info = { .cfg_regs = pinmux_config_regs, - .gpio_data = pinmux_data, - .gpio_data_size = ARRAY_SIZE(pinmux_data), + .pinmux_data = pinmux_data, + .pinmux_data_size = ARRAY_SIZE(pinmux_data), }; diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c index 8e45e30..ab80f0a 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c @@ -5700,6 +5700,6 @@ const struct sh_pfc_soc_info r8a7790_pinmux_info = { .cfg_regs = pinmux_config_regs, - .gpio_data = pinmux_data, - .gpio_data_size = ARRAY_SIZE(pinmux_data), + .pinmux_data = pinmux_data, + .pinmux_data_size = ARRAY_SIZE(pinmux_data), }; diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c index a58a0de..156f88d 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c @@ -6319,8 +6319,8 @@ const struct sh_pfc_soc_info r8a7791_pinmux_info = { .cfg_regs = pinmux_config_regs, - .gpio_data = pinmux_data, - .gpio_data_size = ARRAY_SIZE(pinmux_data), + .pinmux_data = pinmux_data, + .pinmux_data_size = ARRAY_SIZE(pinmux_data), }; #endif @@ -6340,7 +6340,7 @@ const struct sh_pfc_soc_info r8a7793_pinmux_info = { .cfg_regs = pinmux_config_regs, - .gpio_data = pinmux_data, - .gpio_data_size = ARRAY_SIZE(pinmux_data), + .pinmux_data = pinmux_data, + .pinmux_data_size = ARRAY_SIZE(pinmux_data), }; #endif diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7794.c b/drivers/pinctrl/sh-pfc/pfc-r8a7794.c index f9b9dc3..7fc23ab 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7794.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7794.c @@ -4398,6 +4398,6 @@ const struct sh_pfc_soc_info r8a7794_pinmux_info = { .cfg_regs = pinmux_config_regs, - .gpio_data = pinmux_data, - .gpio_data_size = ARRAY_SIZE(pinmux_data), + .pinmux_data = pinmux_data, + .pinmux_data_size = ARRAY_SIZE(pinmux_data), }; diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c index dce06ed0..4d3337c 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c @@ -2812,6 +2812,6 @@ const struct sh_pfc_soc_info r8a7795_pinmux_info = { .cfg_regs = pinmux_config_regs, - .gpio_data = pinmux_data, - .gpio_data_size = ARRAY_SIZE(pinmux_data), + .pinmux_data = pinmux_data, + .pinmux_data_size = ARRAY_SIZE(pinmux_data), }; diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7203.c b/drivers/pinctrl/sh-pfc/pfc-sh7203.c index 3bda7ba..61b27ec 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh7203.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh7203.c @@ -1587,6 +1587,6 @@ const struct sh_pfc_soc_info sh7203_pinmux_info = { .cfg_regs = pinmux_config_regs, .data_regs = pinmux_data_regs, - .gpio_data = pinmux_data, - .gpio_data_size = ARRAY_SIZE(pinmux_data), + .pinmux_data = pinmux_data, + .pinmux_data_size = ARRAY_SIZE(pinmux_data), }; diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7264.c b/drivers/pinctrl/sh-pfc/pfc-sh7264.c index e1cb6dc..8070765 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh7264.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh7264.c @@ -2126,6 +2126,6 @@ const struct sh_pfc_soc_info sh7264_pinmux_info = { .cfg_regs = pinmux_config_regs, .data_regs = pinmux_data_regs, - .gpio_data = pinmux_data, - .gpio_data_size = ARRAY_SIZE(pinmux_data), + .pinmux_data = pinmux_data, + .pinmux_data_size = ARRAY_SIZE(pinmux_data), }; diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7269.c b/drivers/pinctrl/sh-pfc/pfc-sh7269.c index 7a11320..a50d22b 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh7269.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh7269.c @@ -2830,6 +2830,6 @@ const struct sh_pfc_soc_info sh7269_pinmux_info = { .cfg_regs = pinmux_config_regs, .data_regs = pinmux_data_regs, - .gpio_data = pinmux_data, - .gpio_data_size = ARRAY_SIZE(pinmux_data), + .pinmux_data = pinmux_data, + .pinmux_data_size = ARRAY_SIZE(pinmux_data), }; diff --git a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c index bec2652..6a69c8c 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c @@ -3865,8 +3865,8 @@ const struct sh_pfc_soc_info sh73a0_pinmux_info = { .cfg_regs = pinmux_config_regs, .data_regs = pinmux_data_regs, - .gpio_data = pinmux_data, - .gpio_data_size = ARRAY_SIZE(pinmux_data), + .pinmux_data = pinmux_data, + .pinmux_data_size = ARRAY_SIZE(pinmux_data), .gpio_irq = pinmux_irqs, .gpio_irq_size = ARRAY_SIZE(pinmux_irqs), diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7720.c b/drivers/pinctrl/sh-pfc/pfc-sh7720.c index 13d05f8..e07a82d 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh7720.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh7720.c @@ -1201,6 +1201,6 @@ const struct sh_pfc_soc_info sh7720_pinmux_info = { .cfg_regs = pinmux_config_regs, .data_regs = pinmux_data_regs, - .gpio_data = pinmux_data, - .gpio_data_size = ARRAY_SIZE(pinmux_data), + .pinmux_data = pinmux_data, + .pinmux_data_size = ARRAY_SIZE(pinmux_data), }; diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7722.c b/drivers/pinctrl/sh-pfc/pfc-sh7722.c index 914d872..29c6913 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh7722.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh7722.c @@ -1741,6 +1741,6 @@ const struct sh_pfc_soc_info sh7722_pinmux_info = { .cfg_regs = pinmux_config_regs, .data_regs = pinmux_data_regs, - .gpio_data = pinmux_data, - .gpio_data_size = ARRAY_SIZE(pinmux_data), + .pinmux_data = pinmux_data, + .pinmux_data_size = ARRAY_SIZE(pinmux_data), }; diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7723.c b/drivers/pinctrl/sh-pfc/pfc-sh7723.c index 4eb7eae..8ea18df 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh7723.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh7723.c @@ -1893,6 +1893,6 @@ const struct sh_pfc_soc_info sh7723_pinmux_info = { .cfg_regs = pinmux_config_regs, .data_regs = pinmux_data_regs, - .gpio_data = pinmux_data, - .gpio_data_size = ARRAY_SIZE(pinmux_data), + .pinmux_data = pinmux_data, + .pinmux_data_size = ARRAY_SIZE(pinmux_data), }; diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7724.c b/drivers/pinctrl/sh-pfc/pfc-sh7724.c index 74a1a7f..7f6c36c 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh7724.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh7724.c @@ -2175,6 +2175,6 @@ const struct sh_pfc_soc_info sh7724_pinmux_info = { .cfg_regs = pinmux_config_regs, .data_regs = pinmux_data_regs, - .gpio_data = pinmux_data, - .gpio_data_size = ARRAY_SIZE(pinmux_data), + .pinmux_data = pinmux_data, + .pinmux_data_size = ARRAY_SIZE(pinmux_data), }; diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7734.c b/drivers/pinctrl/sh-pfc/pfc-sh7734.c index 59158a7..e7deb51 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh7734.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh7734.c @@ -2445,6 +2445,6 @@ const struct sh_pfc_soc_info sh7734_pinmux_info = { .cfg_regs = pinmux_config_regs, .data_regs = pinmux_data_regs, - .gpio_data = pinmux_data, - .gpio_data_size = ARRAY_SIZE(pinmux_data), + .pinmux_data = pinmux_data, + .pinmux_data_size = ARRAY_SIZE(pinmux_data), }; diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7757.c b/drivers/pinctrl/sh-pfc/pfc-sh7757.c index 625661a..0555a1f 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh7757.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh7757.c @@ -2238,6 +2238,6 @@ const struct sh_pfc_soc_info sh7757_pinmux_info = { .cfg_regs = pinmux_config_regs, .data_regs = pinmux_data_regs, - .gpio_data = pinmux_data, - .gpio_data_size = ARRAY_SIZE(pinmux_data), + .pinmux_data = pinmux_data, + .pinmux_data_size = ARRAY_SIZE(pinmux_data), }; diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7785.c b/drivers/pinctrl/sh-pfc/pfc-sh7785.c index b38dd7e..1934cbe 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh7785.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh7785.c @@ -1269,6 +1269,6 @@ const struct sh_pfc_soc_info sh7785_pinmux_info = { .cfg_regs = pinmux_config_regs, .data_regs = pinmux_data_regs, - .gpio_data = pinmux_data, - .gpio_data_size = ARRAY_SIZE(pinmux_data), + .pinmux_data = pinmux_data, + .pinmux_data_size = ARRAY_SIZE(pinmux_data), }; diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7786.c b/drivers/pinctrl/sh-pfc/pfc-sh7786.c index 6cb4e0a..c98585d 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh7786.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh7786.c @@ -813,6 +813,6 @@ const struct sh_pfc_soc_info sh7786_pinmux_info = { .cfg_regs = pinmux_config_regs, .data_regs = pinmux_data_regs, - .gpio_data = pinmux_data, - .gpio_data_size = ARRAY_SIZE(pinmux_data), + .pinmux_data = pinmux_data, + .pinmux_data_size = ARRAY_SIZE(pinmux_data), }; diff --git a/drivers/pinctrl/sh-pfc/pfc-shx3.c b/drivers/pinctrl/sh-pfc/pfc-shx3.c index a3fcb22..3f60c90 100644 --- a/drivers/pinctrl/sh-pfc/pfc-shx3.c +++ b/drivers/pinctrl/sh-pfc/pfc-shx3.c @@ -554,8 +554,8 @@ const struct sh_pfc_soc_info shx3_pinmux_info = { .nr_pins = ARRAY_SIZE(pinmux_pins), .func_gpios = pinmux_func_gpios, .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios), - .gpio_data = pinmux_data, - .gpio_data_size = ARRAY_SIZE(pinmux_data), + .pinmux_data = pinmux_data, + .pinmux_data_size = ARRAY_SIZE(pinmux_data), .cfg_regs = pinmux_config_regs, .data_regs = pinmux_data_regs, }; diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h index 8b14536..f2c092e 100644 --- a/drivers/pinctrl/sh-pfc/sh_pfc.h +++ b/drivers/pinctrl/sh-pfc/sh_pfc.h @@ -168,8 +168,8 @@ struct sh_pfc_soc_info { const struct pinmux_cfg_reg *cfg_regs; const struct pinmux_data_reg *data_regs; - const u16 *gpio_data; - unsigned int gpio_data_size; + const u16 *pinmux_data; + unsigned int pinmux_data_size; const struct pinmux_irq *gpio_irq; unsigned int gpio_irq_size; @@ -182,7 +182,7 @@ struct sh_pfc_soc_info { */ /* - * sh_pfc_soc_info gpio_data array macros + * sh_pfc_soc_info pinmux_data array macros */ #define PINMUX_DATA(data_or_mark, ids...) data_or_mark, ids, 0 -- cgit v0.10.2 From f15f30449ab252fdc9405f99d46edacc225328cf Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 25 Sep 2015 10:51:02 +0200 Subject: usb: renesas_usbhs: Remove unneeded #include This header file will be removed soon. Signed-off-by: Geert Uytterhoeven Acked-by: Yoshihiro Shimoda Acked-by: Greg Kroah-Hartman Acked-by: Felipe Balbi diff --git a/drivers/usb/renesas_usbhs/rcar2.c b/drivers/usb/renesas_usbhs/rcar2.c index 8fc15c0..277160b 100644 --- a/drivers/usb/renesas_usbhs/rcar2.c +++ b/drivers/usb/renesas_usbhs/rcar2.c @@ -13,7 +13,6 @@ #include #include #include -#include #include #include "common.h" #include "rcar2.h" -- cgit v0.10.2 From 69af775a18ff1d07f527b2f6caec171af5e1397e Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 25 Sep 2015 10:55:44 +0200 Subject: pinctrl: sh-pfc: Stop including This header file will be removed soon. Copy the helper macro RCAR_GP_PIN(), which is used by the pinctrl drivers only, to sh_pfc.h, and drop the #include. Signed-off-by: Geert Uytterhoeven Acked-by: Linus Walleij diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7778.c b/drivers/pinctrl/sh-pfc/pfc-r8a7778.c index f35a3fc..bbd35dc 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7778.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7778.c @@ -23,7 +23,6 @@ #include #include #include -#include #include "core.h" #include "sh_pfc.h" diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c index 71fb5e4..ed4e078 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c @@ -20,7 +20,6 @@ */ #include -#include #include "sh_pfc.h" diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c index ab80f0a..d9924b0 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c @@ -22,7 +22,6 @@ */ #include -#include #include "core.h" #include "sh_pfc.h" diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c index 156f88d..87a4f44 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c @@ -9,7 +9,6 @@ */ #include -#include #include "core.h" #include "sh_pfc.h" diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7794.c b/drivers/pinctrl/sh-pfc/pfc-r8a7794.c index 7fc23ab..086f679 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7794.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7794.c @@ -11,7 +11,6 @@ */ #include -#include #include "core.h" #include "sh_pfc.h" diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c index 4d3337c..7ddb2ad 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c @@ -9,7 +9,6 @@ */ #include -#include #include "core.h" #include "sh_pfc.h" diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h index f2c092e..7b373d43 100644 --- a/drivers/pinctrl/sh-pfc/sh_pfc.h +++ b/drivers/pinctrl/sh-pfc/sh_pfc.h @@ -346,4 +346,9 @@ struct sh_pfc_soc_info { } \ } +/* + * GPIO number helper macro for R-Car + */ +#define RCAR_GP_PIN(bank, pin) (((bank) * 32) + (pin)) + #endif /* __SH_PFC_H */ -- cgit v0.10.2 From 5eb6fc210ea2f988731f54eda0497d0518b89347 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 25 Sep 2015 11:27:19 +0200 Subject: pinctrl: sh-pfc: Remove obsolete r8a7779 platform_device_id entry Since the removal of the r8a7779 legacy SoC code in commit c99cd90d98a98aa1 ("ARM: shmobile: r8a7779: Remove legacy SoC code"), r8a7779 is only supported in generic DT-only ARM multi-platform builds. The driver doesn't need to match platform devices by name anymore, hence remove the corresponding platform_device_id entry. Signed-off-by: Geert Uytterhoeven Acked-by: Laurent Pinchart Acked-by: Linus Walleij diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c index e6a5174..c6be17f 100644 --- a/drivers/pinctrl/sh-pfc/core.c +++ b/drivers/pinctrl/sh-pfc/core.c @@ -596,9 +596,6 @@ static const struct platform_device_id sh_pfc_id_table[] = { #ifdef CONFIG_PINCTRL_PFC_R8A7778 { "pfc-r8a7778", (kernel_ulong_t)&r8a7778_pinmux_info }, #endif -#ifdef CONFIG_PINCTRL_PFC_R8A7779 - { "pfc-r8a7779", (kernel_ulong_t)&r8a7779_pinmux_info }, -#endif #ifdef CONFIG_PINCTRL_PFC_SH7203 { "pfc-sh7203", (kernel_ulong_t)&sh7203_pinmux_info }, #endif -- cgit v0.10.2 From 660c40bd9837854b3d3cc75e6ddb41cc8ac32a1d Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 25 Sep 2015 11:29:01 +0200 Subject: pinctrl: sh-pfc: Remove obsolete r8a7778 platform_device_id entry Since the removal of the r8a7778 legacy SoC code in commit 4baadb9e05c68962 ("ARM: shmobile: r8a7778: remove obsolete setup code"), r8a7778 is only supported in generic DT-only ARM multi-platform builds. The driver doesn't need to match platform devices by name anymore, hence remove the corresponding platform_device_id entry. Signed-off-by: Geert Uytterhoeven Acked-by: Laurent Pinchart Acked-by: Linus Walleij diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c index c6be17f..181ea98 100644 --- a/drivers/pinctrl/sh-pfc/core.c +++ b/drivers/pinctrl/sh-pfc/core.c @@ -593,9 +593,6 @@ static int sh_pfc_remove(struct platform_device *pdev) } static const struct platform_device_id sh_pfc_id_table[] = { -#ifdef CONFIG_PINCTRL_PFC_R8A7778 - { "pfc-r8a7778", (kernel_ulong_t)&r8a7778_pinmux_info }, -#endif #ifdef CONFIG_PINCTRL_PFC_SH7203 { "pfc-sh7203", (kernel_ulong_t)&sh7203_pinmux_info }, #endif -- cgit v0.10.2 From 8297992cad599e8a214e65959ccdde51738fe5a2 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Fri, 16 Oct 2015 09:46:11 +0200 Subject: pinctrl: sunxi: Fix irq_of_xlate for the r_pio pinctrl block The r_pio gpio / pin controller has a pin_base of non 0, we need to adjust for this before calling sunxi_pinctrl_desc_find_function_by_pin. Signed-off-by: Hans de Goede Acked-by: Chen-Yu Tsai Acked-by: Maxime Ripard Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c index fe2c74a..21fd638 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c @@ -716,6 +716,7 @@ static int sunxi_pinctrl_irq_of_xlate(struct irq_domain *d, unsigned long *out_hwirq, unsigned int *out_type) { + struct sunxi_pinctrl *pctl = d->host_data; struct sunxi_desc_function *desc; int pin, base; @@ -723,10 +724,9 @@ static int sunxi_pinctrl_irq_of_xlate(struct irq_domain *d, return -EINVAL; base = PINS_PER_BANK * intspec[0]; - pin = base + intspec[1]; + pin = pctl->desc->pin_base + base + intspec[1]; - desc = sunxi_pinctrl_desc_find_function_by_pin(d->host_data, - pin, "irq"); + desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, pin, "irq"); if (!desc) return -EINVAL; -- cgit v0.10.2 From 3f84ccf62c9fdd39d2cb1caa725663191c817b65 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Fri, 16 Oct 2015 09:46:12 +0200 Subject: pinctrl: sunxi: Add irq pinmuxing to sun6i "r" pincontroller Add pinmuxing for external interrupt functionality through the sun6i "r" pincontroller. Signed-off-by: Hans de Goede Acked-by: Chen-Yu Tsai Acked-by: Maxime Ripard Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/sunxi/pinctrl-sun6i-a31-r.c b/drivers/pinctrl/sunxi/pinctrl-sun6i-a31-r.c index 9596b0a3..d4bc4f0 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun6i-a31-r.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun6i-a31-r.c @@ -47,45 +47,57 @@ static const struct sunxi_desc_pin sun6i_a31_r_pins[] = { SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 5), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION_IRQ_BANK(0x2, 0, 0), /* PL_EINT0 */ SUNXI_FUNCTION(0x3, "s_jtag")), /* MS */ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 6), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION_IRQ_BANK(0x2, 0, 1), /* PL_EINT1 */ SUNXI_FUNCTION(0x3, "s_jtag")), /* CK */ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 7), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION_IRQ_BANK(0x2, 0, 2), /* PL_EINT2 */ SUNXI_FUNCTION(0x3, "s_jtag")), /* DO */ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 8), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION_IRQ_BANK(0x2, 0, 3), /* PL_EINT3 */ SUNXI_FUNCTION(0x3, "s_jtag")), /* DI */ /* Hole */ SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 0), SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION_IRQ_BANK(0x2, 1, 0)), /* PM_EINT0 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 1), SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION_IRQ_BANK(0x2, 1, 1)), /* PM_EINT1 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 2), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION_IRQ_BANK(0x2, 1, 2), /* PM_EINT2 */ SUNXI_FUNCTION(0x3, "1wire")), SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 3), SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION_IRQ_BANK(0x2, 1, 3)), /* PM_EINT3 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 4), SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION_IRQ_BANK(0x2, 1, 4)), /* PM_EINT4 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 5), SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION_IRQ_BANK(0x2, 1, 5)), /* PM_EINT5 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 6), SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION_IRQ_BANK(0x2, 1, 6)), /* PM_EINT6 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 7), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION_IRQ_BANK(0x2, 1, 7), /* PM_EINT7 */ SUNXI_FUNCTION(0x3, "rtc")), /* CLKO */ }; -- cgit v0.10.2 From 03e09bc18580c84961c8a05470e8d5ed197ecd84 Mon Sep 17 00:00:00 2001 From: Pramod Kumar Date: Mon, 19 Oct 2015 11:13:08 +0530 Subject: pinctrl: cygnus: Optional DT property to support pin mappings If GPIO controller's pins are muxed, pin-controller subsystem need to be intimated by defining mapping between gpio and pinmux controller. This patch adds required properties to define this mapping via DT. Signed-off-by: Pramod Kumar Reviewed-by: Ray Jui Reviewed-by: Scott Branden Acked-by: Rob Herring Signed-off-by: Linus Walleij diff --git a/Documentation/devicetree/bindings/pinctrl/brcm,cygnus-gpio.txt b/Documentation/devicetree/bindings/pinctrl/brcm,cygnus-gpio.txt index 6540ca5..25a5002 100644 --- a/Documentation/devicetree/bindings/pinctrl/brcm,cygnus-gpio.txt +++ b/Documentation/devicetree/bindings/pinctrl/brcm,cygnus-gpio.txt @@ -26,9 +26,13 @@ Optional properties: - interrupt-controller: Specifies that the node is an interrupt controller -- pinmux: - Specifies the phandle to the IOMUX device, where pins can be individually -muxed to GPIO +- gpio-ranges: + Specifies the mapping between gpio controller and pin-controllers pins. + This requires 4 fields in cells defined as - + 1. Phandle of pin-controller. + 2. GPIO base pin offset. + 3 Pin-control base pin offset. + 4. number of gpio pins which are linearly mapped from pin base. Supported generic PINCONF properties in child nodes: @@ -78,6 +82,8 @@ Example: gpio-controller; interrupts = ; interrupt-controller; + gpio-ranges = <&pinctrl 0 42 1>, + <&pinctrl 1 44 3>; }; /* -- cgit v0.10.2 From ea92211c0844afbe8b3f83809ea2f51bc53acc68 Mon Sep 17 00:00:00 2001 From: Pramod Kumar Date: Mon, 19 Oct 2015 11:13:09 +0530 Subject: pinctrl: cygnus: Remove GPIO to Pinctrl pin mapping from driver Remove gpio to pinctrl pin mapping code from driver and address this through standard property "gpio-ranges". Signed-off-by: Pramod Kumar Reviewed-by: Ray Jui Reviewed-by: Scott Branden Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/bcm/pinctrl-cygnus-gpio.c b/drivers/pinctrl/bcm/pinctrl-cygnus-gpio.c index 1ca7830..12a48f4 100644 --- a/drivers/pinctrl/bcm/pinctrl-cygnus-gpio.c +++ b/drivers/pinctrl/bcm/pinctrl-cygnus-gpio.c @@ -29,7 +29,6 @@ #include #include #include -#include #include #include @@ -597,127 +596,6 @@ static const struct pinconf_ops cygnus_pconf_ops = { }; /* - * Map a GPIO in the local gpio_chip pin space to a pin in the Cygnus IOMUX - * pinctrl pin space - */ -struct cygnus_gpio_pin_range { - unsigned offset; - unsigned pin_base; - unsigned num_pins; -}; - -#define CYGNUS_PINRANGE(o, p, n) { .offset = o, .pin_base = p, .num_pins = n } - -/* - * Pin mapping table for mapping local GPIO pins to Cygnus IOMUX pinctrl pins - */ -static const struct cygnus_gpio_pin_range cygnus_gpio_pintable[] = { - CYGNUS_PINRANGE(0, 42, 1), - CYGNUS_PINRANGE(1, 44, 3), - CYGNUS_PINRANGE(4, 48, 1), - CYGNUS_PINRANGE(5, 50, 3), - CYGNUS_PINRANGE(8, 126, 1), - CYGNUS_PINRANGE(9, 155, 1), - CYGNUS_PINRANGE(10, 152, 1), - CYGNUS_PINRANGE(11, 154, 1), - CYGNUS_PINRANGE(12, 153, 1), - CYGNUS_PINRANGE(13, 127, 3), - CYGNUS_PINRANGE(16, 140, 1), - CYGNUS_PINRANGE(17, 145, 7), - CYGNUS_PINRANGE(24, 130, 10), - CYGNUS_PINRANGE(34, 141, 4), - CYGNUS_PINRANGE(38, 54, 1), - CYGNUS_PINRANGE(39, 56, 3), - CYGNUS_PINRANGE(42, 60, 3), - CYGNUS_PINRANGE(45, 64, 3), - CYGNUS_PINRANGE(48, 68, 2), - CYGNUS_PINRANGE(50, 84, 6), - CYGNUS_PINRANGE(56, 94, 6), - CYGNUS_PINRANGE(62, 72, 1), - CYGNUS_PINRANGE(63, 70, 1), - CYGNUS_PINRANGE(64, 80, 1), - CYGNUS_PINRANGE(65, 74, 3), - CYGNUS_PINRANGE(68, 78, 1), - CYGNUS_PINRANGE(69, 82, 1), - CYGNUS_PINRANGE(70, 156, 17), - CYGNUS_PINRANGE(87, 104, 12), - CYGNUS_PINRANGE(99, 102, 2), - CYGNUS_PINRANGE(101, 90, 4), - CYGNUS_PINRANGE(105, 116, 6), - CYGNUS_PINRANGE(111, 100, 2), - CYGNUS_PINRANGE(113, 122, 4), - CYGNUS_PINRANGE(123, 11, 1), - CYGNUS_PINRANGE(124, 38, 4), - CYGNUS_PINRANGE(128, 43, 1), - CYGNUS_PINRANGE(129, 47, 1), - CYGNUS_PINRANGE(130, 49, 1), - CYGNUS_PINRANGE(131, 53, 1), - CYGNUS_PINRANGE(132, 55, 1), - CYGNUS_PINRANGE(133, 59, 1), - CYGNUS_PINRANGE(134, 63, 1), - CYGNUS_PINRANGE(135, 67, 1), - CYGNUS_PINRANGE(136, 71, 1), - CYGNUS_PINRANGE(137, 73, 1), - CYGNUS_PINRANGE(138, 77, 1), - CYGNUS_PINRANGE(139, 79, 1), - CYGNUS_PINRANGE(140, 81, 1), - CYGNUS_PINRANGE(141, 83, 1), - CYGNUS_PINRANGE(142, 10, 1) -}; - -/* - * The Cygnus IOMUX controller mainly supports group based mux configuration, - * but certain pins can be muxed to GPIO individually. Only the ASIU GPIO - * controller can support this, so it's an optional configuration - * - * Return -ENODEV means no support and that's fine - */ -static int cygnus_gpio_pinmux_add_range(struct cygnus_gpio *chip) -{ - struct device_node *node = chip->dev->of_node; - struct device_node *pinmux_node; - struct platform_device *pinmux_pdev; - struct gpio_chip *gc = &chip->gc; - int i, ret = 0; - - /* parse DT to find the phandle to the pinmux controller */ - pinmux_node = of_parse_phandle(node, "pinmux", 0); - if (!pinmux_node) - return -ENODEV; - - pinmux_pdev = of_find_device_by_node(pinmux_node); - /* no longer need the pinmux node */ - of_node_put(pinmux_node); - if (!pinmux_pdev) { - dev_err(chip->dev, "failed to get pinmux device\n"); - return -EINVAL; - } - - /* now need to create the mapping between local GPIO and PINMUX pins */ - for (i = 0; i < ARRAY_SIZE(cygnus_gpio_pintable); i++) { - ret = gpiochip_add_pin_range(gc, dev_name(&pinmux_pdev->dev), - cygnus_gpio_pintable[i].offset, - cygnus_gpio_pintable[i].pin_base, - cygnus_gpio_pintable[i].num_pins); - if (ret) { - dev_err(chip->dev, "unable to add GPIO pin range\n"); - goto err_put_device; - } - } - - chip->pinmux_is_supported = true; - - /* no need for pinmux_pdev device reference anymore */ - put_device(&pinmux_pdev->dev); - return 0; - -err_put_device: - put_device(&pinmux_pdev->dev); - gpiochip_remove_pin_ranges(gc); - return ret; -} - -/* * Cygnus GPIO controller supports some PINCONF related configurations such as * pull up, pull down, and drive strength, when the pin is configured to GPIO * @@ -851,18 +729,15 @@ static int cygnus_gpio_probe(struct platform_device *pdev) gc->set = cygnus_gpio_set; gc->get = cygnus_gpio_get; + chip->pinmux_is_supported = of_property_read_bool(dev->of_node, + "gpio-ranges"); + ret = gpiochip_add(gc); if (ret < 0) { dev_err(dev, "unable to add GPIO chip\n"); return ret; } - ret = cygnus_gpio_pinmux_add_range(chip); - if (ret && ret != -ENODEV) { - dev_err(dev, "unable to add GPIO pin range\n"); - goto err_rm_gpiochip; - } - ret = cygnus_gpio_register_pinconf(chip); if (ret) { dev_err(dev, "unable to register pinconf\n"); -- cgit v0.10.2 From e0548004d433e4454c5d129a5c5b0905442bfe8e Mon Sep 17 00:00:00 2001 From: Pramod Kumar Date: Mon, 19 Oct 2015 11:13:11 +0530 Subject: pinctrl: cygnus: Add new compatible string for gpio controller driver This new compatible string, "brcm,iproc-gpio", should be used for all new iproc-based future SoCs. Signed-off-by: Pramod Kumar Reviewed-by: Ray Jui Reviewed-by: Scott Branden Signed-off-by: Linus Walleij diff --git a/Documentation/devicetree/bindings/pinctrl/brcm,cygnus-gpio.txt b/Documentation/devicetree/bindings/pinctrl/brcm,cygnus-gpio.txt index 25a5002..16589fb6 100644 --- a/Documentation/devicetree/bindings/pinctrl/brcm,cygnus-gpio.txt +++ b/Documentation/devicetree/bindings/pinctrl/brcm,cygnus-gpio.txt @@ -3,8 +3,8 @@ Broadcom Cygnus GPIO/PINCONF Controller Required properties: - compatible: - Must be "brcm,cygnus-ccm-gpio", "brcm,cygnus-asiu-gpio", or - "brcm,cygnus-crmu-gpio" + Must be "brcm,cygnus-ccm-gpio", "brcm,cygnus-asiu-gpio", + "brcm,cygnus-crmu-gpio" or "brcm,iproc-gpio" - reg: Define the base and range of the I/O address space that contains the Cygnus -- cgit v0.10.2 From bac7f4c1bf5e7c6ccd5bb71edc015b26c77f7460 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Tue, 20 Oct 2015 17:25:09 +0900 Subject: pinctrl: uniphier: set input-enable before pin-muxing While IECTRL is disabled, input signals are pulled-down internally. If pin-muxing is set up first, glitch signals (Low to High transition) might be input to hardware blocks. Bad case scenario: [1] The hardware block is already running before pinctrl is handled. (the reset is de-asserted by default or by a firmware, for example) [2] The pin-muxing is set up. The input signals to hardware block are pulled-down by the chip-internal biasing. [3] The pins are input-enabled. The signals from the board reach the hardware block. Actually, one invalid character is input to the UART blocks for such SoCs as PH1-LD4, PH1-sLD8, where UART devices start to run at the power on reset. To avoid such problems, pins should be input-enabled before muxing. Fixes: 6e9088920258 ("pinctrl: UniPhier: add UniPhier pinctrl core support") Signed-off-by: Masahiro Yamada Reported-by: Dai Okamura Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c index 918f3b6..589872c 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c @@ -539,6 +539,12 @@ static int uniphier_pmx_set_one_mux(struct pinctrl_dev *pctldev, unsigned pin, unsigned reg, reg_end, shift, mask; int ret; + /* some pins need input-enabling */ + ret = uniphier_conf_pin_input_enable(pctldev, + &pctldev->desc->pins[pin], 1); + if (ret) + return ret; + reg = UNIPHIER_PINCTRL_PINMUX_BASE + pin * mux_bits / 32 * reg_stride; reg_end = reg + reg_stride; shift = pin * mux_bits % 32; @@ -563,9 +569,7 @@ static int uniphier_pmx_set_one_mux(struct pinctrl_dev *pctldev, unsigned pin, return ret; } - /* some pins need input-enabling */ - return uniphier_conf_pin_input_enable(pctldev, - &pctldev->desc->pins[pin], 1); + return 0; } static int uniphier_pmx_set_mux(struct pinctrl_dev *pctldev, -- cgit v0.10.2 From ef0eebc05130b0d22b0ea65c0cd014ee16fc89c7 Mon Sep 17 00:00:00 2001 From: Douglas Anderson Date: Tue, 20 Oct 2015 21:15:06 -0700 Subject: drivers/pinctrl: Add the concept of an "init" state For pinctrl the "default" state is applied to pins before the driver's probe function is called. This is normally a sensible thing to do, but in some cases can cause problems. That's because the pins will change state before the driver is given a chance to program how those pins should behave. As an example you might have a regulator that is controlled by a PWM (output high = high voltage, output low = low voltage). The firmware might leave this pin as driven high. If we allow the driver core to reconfigure this pin as a PWM pin before the PWM's probe function runs then you might end up running at too low of a voltage while we probe. Let's introudce a new "init" state. If this is defined we'll set pinctrl to this state before probe and then "default" after probe (unless the driver explicitly changed states already). An alternative idea that was thought of was to use the pre-existing "sleep" or "idle" states and add a boolean property that we should start in that mode. This was not done because the "init" state is needed for correctness and those other states are only present (and only transitioned in to and out of) when (optional) power management is enabled. Changes in v3: - Moved declarations to pinctrl/devinfo.h - Fixed author/SoB Changes in v2: - Added comment to pinctrl_init_done() as per Linus W. Signed-off-by: Douglas Anderson Acked-by: Greg Kroah-Hartman Tested-by: Caesar Wang Signed-off-by: Linus Walleij diff --git a/drivers/base/dd.c b/drivers/base/dd.c index be0eb46..a641cf3 100644 --- a/drivers/base/dd.c +++ b/drivers/base/dd.c @@ -322,6 +322,8 @@ static int really_probe(struct device *dev, struct device_driver *drv) goto probe_failed; } + pinctrl_init_done(dev); + if (dev->pm_domain && dev->pm_domain->sync) dev->pm_domain->sync(dev); diff --git a/drivers/base/pinctrl.c b/drivers/base/pinctrl.c index 5fb74b4..0762975 100644 --- a/drivers/base/pinctrl.c +++ b/drivers/base/pinctrl.c @@ -42,9 +42,20 @@ int pinctrl_bind_pins(struct device *dev) goto cleanup_get; } - ret = pinctrl_select_state(dev->pins->p, dev->pins->default_state); + dev->pins->init_state = pinctrl_lookup_state(dev->pins->p, + PINCTRL_STATE_INIT); + if (IS_ERR(dev->pins->init_state)) { + /* Not supplying this state is perfectly legal */ + dev_dbg(dev, "no init pinctrl state\n"); + + ret = pinctrl_select_state(dev->pins->p, + dev->pins->default_state); + } else { + ret = pinctrl_select_state(dev->pins->p, dev->pins->init_state); + } + if (ret) { - dev_dbg(dev, "failed to activate default pinctrl state\n"); + dev_dbg(dev, "failed to activate initial pinctrl state\n"); goto cleanup_get; } diff --git a/drivers/pinctrl/core.c b/drivers/pinctrl/core.c index 9638a00..2686a44 100644 --- a/drivers/pinctrl/core.c +++ b/drivers/pinctrl/core.c @@ -1240,6 +1240,38 @@ int pinctrl_force_default(struct pinctrl_dev *pctldev) } EXPORT_SYMBOL_GPL(pinctrl_force_default); +/** + * pinctrl_init_done() - tell pinctrl probe is done + * + * We'll use this time to switch the pins from "init" to "default" unless the + * driver selected some other state. + * + * @dev: device to that's done probing + */ +int pinctrl_init_done(struct device *dev) +{ + struct dev_pin_info *pins = dev->pins; + int ret; + + if (!pins) + return 0; + + if (IS_ERR(pins->init_state)) + return 0; /* No such state */ + + if (pins->p->state != pins->init_state) + return 0; /* Not at init anyway */ + + if (IS_ERR(pins->default_state)) + return 0; /* No default state */ + + ret = pinctrl_select_state(pins->p, pins->default_state); + if (ret) + dev_err(dev, "failed to activate default pinctrl state\n"); + + return ret; +} + #ifdef CONFIG_PM /** diff --git a/include/linux/pinctrl/devinfo.h b/include/linux/pinctrl/devinfo.h index 281cb91..05082e4 100644 --- a/include/linux/pinctrl/devinfo.h +++ b/include/linux/pinctrl/devinfo.h @@ -24,10 +24,14 @@ * struct dev_pin_info - pin state container for devices * @p: pinctrl handle for the containing device * @default_state: the default state for the handle, if found + * @init_state: the state at probe time, if found + * @sleep_state: the state at suspend time, if found + * @idle_state: the state at idle (runtime suspend) time, if found */ struct dev_pin_info { struct pinctrl *p; struct pinctrl_state *default_state; + struct pinctrl_state *init_state; #ifdef CONFIG_PM struct pinctrl_state *sleep_state; struct pinctrl_state *idle_state; @@ -35,6 +39,7 @@ struct dev_pin_info { }; extern int pinctrl_bind_pins(struct device *dev); +extern int pinctrl_init_done(struct device *dev); #else @@ -45,5 +50,10 @@ static inline int pinctrl_bind_pins(struct device *dev) return 0; } +static inline int pinctrl_init_done(struct device *dev) +{ + return 0; +} + #endif /* CONFIG_PINCTRL */ #endif /* PINCTRL_DEVINFO_H */ diff --git a/include/linux/pinctrl/pinctrl-state.h b/include/linux/pinctrl/pinctrl-state.h index b5919f8..2307351 100644 --- a/include/linux/pinctrl/pinctrl-state.h +++ b/include/linux/pinctrl/pinctrl-state.h @@ -9,6 +9,13 @@ * hogs to configure muxing and pins at boot, and also as a state * to go into when returning from sleep and idle in * .pm_runtime_resume() or ordinary .resume() for example. + * @PINCTRL_STATE_INIT: normally the pinctrl will be set to "default" + * before the driver's probe() function is called. There are some + * drivers where that is not appropriate becausing doing so would + * glitch the pins. In those cases you can add an "init" pinctrl + * which is the state of the pins before drive probe. After probe + * if the pins are still in "init" state they'll be moved to + * "default". * @PINCTRL_STATE_IDLE: the state the pinctrl handle shall be put into * when the pins are idle. This is a state where the system is relaxed * but not fully sleeping - some power may be on but clocks gated for @@ -20,5 +27,6 @@ * ordinary .suspend() function. */ #define PINCTRL_STATE_DEFAULT "default" +#define PINCTRL_STATE_INIT "init" #define PINCTRL_STATE_IDLE "idle" #define PINCTRL_STATE_SLEEP "sleep" -- cgit v0.10.2 From 193b40c8258f781d8dc395909b2971472aad6796 Mon Sep 17 00:00:00 2001 From: Mika Westerberg Date: Wed, 21 Oct 2015 13:08:43 +0300 Subject: pinctrl: intel: Add support for multiple GPIO chips sharing the interrupt On Intel Broxton the GPIO hardware consists of several chips that all share the parent interrupt. It is not possible to handle this by setting chained handler for each chip (as they will overwrite each other). To overcome this we need to request the interrupt using devm_request_irq() and pass IRQF_SHARED with the flags. Signed-off-by: Mika Westerberg Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/intel/pinctrl-intel.c b/drivers/pinctrl/intel/pinctrl-intel.c index 613ba1b..19b73de 100644 --- a/drivers/pinctrl/intel/pinctrl-intel.c +++ b/drivers/pinctrl/intel/pinctrl-intel.c @@ -12,6 +12,7 @@ #include #include +#include #include #include #include @@ -803,9 +804,11 @@ static int intel_gpio_irq_wake(struct irq_data *d, unsigned int on) return 0; } -static void intel_gpio_community_irq_handler(struct gpio_chip *gc, +static irqreturn_t intel_gpio_community_irq_handler(struct intel_pinctrl *pctrl, const struct intel_community *community) { + struct gpio_chip *gc = &pctrl->chip; + irqreturn_t ret = IRQ_NONE; int gpp; for (gpp = 0; gpp < community->ngpps; gpp++) { @@ -832,24 +835,28 @@ static void intel_gpio_community_irq_handler(struct gpio_chip *gc, irq = irq_find_mapping(gc->irqdomain, community->pin_base + padno); generic_handle_irq(irq); + + ret |= IRQ_HANDLED; } } + + return ret; } -static void intel_gpio_irq_handler(struct irq_desc *desc) +static irqreturn_t intel_gpio_irq(int irq, void *data) { - struct gpio_chip *gc = irq_desc_get_handler_data(desc); - struct intel_pinctrl *pctrl = gpiochip_to_pinctrl(gc); - struct irq_chip *chip = irq_desc_get_chip(desc); + const struct intel_community *community; + struct intel_pinctrl *pctrl = data; + irqreturn_t ret = IRQ_NONE; int i; - chained_irq_enter(chip, desc); - /* Need to check all communities for pending interrupts */ - for (i = 0; i < pctrl->ncommunities; i++) - intel_gpio_community_irq_handler(gc, &pctrl->communities[i]); + for (i = 0; i < pctrl->ncommunities; i++) { + community = &pctrl->communities[i]; + ret |= intel_gpio_community_irq_handler(pctrl, community); + } - chained_irq_exit(chip, desc); + return ret; } static struct irq_chip intel_gpio_irqchip = { @@ -882,21 +889,36 @@ static int intel_gpio_probe(struct intel_pinctrl *pctrl, int irq) 0, 0, pctrl->soc->npins); if (ret) { dev_err(pctrl->dev, "failed to add GPIO pin range\n"); - gpiochip_remove(&pctrl->chip); - return ret; + goto fail; + } + + /* + * We need to request the interrupt here (instead of providing chip + * to the irq directly) because on some platforms several GPIO + * controllers share the same interrupt line. + */ + ret = devm_request_irq(pctrl->dev, irq, intel_gpio_irq, IRQF_SHARED, + dev_name(pctrl->dev), pctrl); + if (ret) { + dev_err(pctrl->dev, "failed to request interrupt\n"); + goto fail; } ret = gpiochip_irqchip_add(&pctrl->chip, &intel_gpio_irqchip, 0, handle_simple_irq, IRQ_TYPE_NONE); if (ret) { dev_err(pctrl->dev, "failed to add irqchip\n"); - gpiochip_remove(&pctrl->chip); - return ret; + goto fail; } gpiochip_set_chained_irqchip(&pctrl->chip, &intel_gpio_irqchip, irq, - intel_gpio_irq_handler); + NULL); return 0; + +fail: + gpiochip_remove(&pctrl->chip); + + return ret; } static int intel_pinctrl_pm_init(struct intel_pinctrl *pctrl) -- cgit v0.10.2 From 4341e8a5458f10cb7265167061fa06ebf3a3a903 Mon Sep 17 00:00:00 2001 From: Mika Westerberg Date: Wed, 21 Oct 2015 13:08:44 +0300 Subject: pinctrl: intel: Allow requesting pins which are in ACPI mode as GPIOs Reserved for ACPI actually means that in such case the GPIO hardware will not update the interrupt status register (GPI_IS) even if the pin is configured to trigger an interrupt. It will update GPI_GPE_STS instead and does not trigger an interrupt. Allow using such pins as GPIOs, only prevent their usage as interrupts. We also rename function intel_pad_reserved_for_acpi() to be intel_pad_acpi_mode() which reflects the actual meaning better. Signed-off-by: Mika Westerberg Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/intel/pinctrl-intel.c b/drivers/pinctrl/intel/pinctrl-intel.c index 19b73de..c427454 100644 --- a/drivers/pinctrl/intel/pinctrl-intel.c +++ b/drivers/pinctrl/intel/pinctrl-intel.c @@ -160,8 +160,7 @@ static bool intel_pad_owned_by_host(struct intel_pinctrl *pctrl, unsigned pin) return !(readl(padown) & PADOWN_MASK(padno)); } -static bool intel_pad_reserved_for_acpi(struct intel_pinctrl *pctrl, - unsigned pin) +static bool intel_pad_acpi_mode(struct intel_pinctrl *pctrl, unsigned pin) { const struct intel_community *community; unsigned padno, gpp, offset; @@ -217,7 +216,6 @@ static bool intel_pad_locked(struct intel_pinctrl *pctrl, unsigned pin) static bool intel_pad_usable(struct intel_pinctrl *pctrl, unsigned pin) { return intel_pad_owned_by_host(pctrl, pin) && - !intel_pad_reserved_for_acpi(pctrl, pin) && !intel_pad_locked(pctrl, pin); } @@ -270,7 +268,7 @@ static void intel_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, seq_printf(s, "0x%08x 0x%08x", cfg0, cfg1); locked = intel_pad_locked(pctrl, pin); - acpi = intel_pad_reserved_for_acpi(pctrl, pin); + acpi = intel_pad_acpi_mode(pctrl, pin); if (locked || acpi) { seq_puts(s, " ["); @@ -737,6 +735,16 @@ static int intel_gpio_irq_type(struct irq_data *d, unsigned type) if (!reg) return -EINVAL; + /* + * If the pin is in ACPI mode it is still usable as a GPIO but it + * cannot be used as IRQ because GPI_IS status bit will not be + * updated by the host controller hardware. + */ + if (intel_pad_acpi_mode(pctrl, pin)) { + dev_warn(pctrl->dev, "pin %u cannot be used as IRQ\n", pin); + return -EPERM; + } + spin_lock_irqsave(&pctrl->lock, flags); value = readl(reg); -- cgit v0.10.2 From ee1a6ca43dba07465c71f6ab661702d703f5eb06 Mon Sep 17 00:00:00 2001 From: Mika Westerberg Date: Wed, 21 Oct 2015 13:08:45 +0300 Subject: pinctrl: intel: Add Intel Broxton pin controller support This driver adds pinctrl/GPIO support for Intel Broxton. The GPIO controller is based on the same hardware design that is already used in Intel Sunrisepoint so we leverage the core driver here. Signed-off-by: Mika Westerberg Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/intel/Kconfig b/drivers/pinctrl/intel/Kconfig index fe5e07d..4d2efad 100644 --- a/drivers/pinctrl/intel/Kconfig +++ b/drivers/pinctrl/intel/Kconfig @@ -34,6 +34,14 @@ config PINCTRL_INTEL select GPIOLIB select GPIOLIB_IRQCHIP +config PINCTRL_BROXTON + tristate "Intel Broxton pinctrl and GPIO driver" + depends on ACPI + select PINCTRL_INTEL + help + Broxton pinctrl driver provides an interface that allows + configuring of SoC pins and using them as GPIOs. + config PINCTRL_SUNRISEPOINT tristate "Intel Sunrisepoint pinctrl and GPIO driver" depends on ACPI diff --git a/drivers/pinctrl/intel/Makefile b/drivers/pinctrl/intel/Makefile index fee756e..03bc68e 100644 --- a/drivers/pinctrl/intel/Makefile +++ b/drivers/pinctrl/intel/Makefile @@ -3,4 +3,5 @@ obj-$(CONFIG_PINCTRL_BAYTRAIL) += pinctrl-baytrail.o obj-$(CONFIG_PINCTRL_CHERRYVIEW) += pinctrl-cherryview.o obj-$(CONFIG_PINCTRL_INTEL) += pinctrl-intel.o +obj-$(CONFIG_PINCTRL_BROXTON) += pinctrl-broxton.o obj-$(CONFIG_PINCTRL_SUNRISEPOINT) += pinctrl-sunrisepoint.o diff --git a/drivers/pinctrl/intel/pinctrl-broxton.c b/drivers/pinctrl/intel/pinctrl-broxton.c new file mode 100644 index 0000000..e42d5d4 --- /dev/null +++ b/drivers/pinctrl/intel/pinctrl-broxton.c @@ -0,0 +1,1065 @@ +/* + * Intel Broxton SoC pinctrl/GPIO driver + * + * Copyright (C) 2015, Intel Corporation + * Author: Mika Westerberg + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include + +#include "pinctrl-intel.h" + +#define BXT_PAD_OWN 0x020 +#define BXT_HOSTSW_OWN 0x080 +#define BXT_PADCFGLOCK 0x090 +#define BXT_GPI_IE 0x110 + +#define BXT_COMMUNITY(s, e) \ + { \ + .padown_offset = BXT_PAD_OWN, \ + .padcfglock_offset = BXT_PADCFGLOCK, \ + .hostown_offset = BXT_HOSTSW_OWN, \ + .ie_offset = BXT_GPI_IE, \ + .pin_base = (s), \ + .npins = ((e) - (s) + 1), \ + } + +/* BXT */ +static const struct pinctrl_pin_desc bxt_north_pins[] = { + PINCTRL_PIN(0, "GPIO_0"), + PINCTRL_PIN(1, "GPIO_1"), + PINCTRL_PIN(2, "GPIO_2"), + PINCTRL_PIN(3, "GPIO_3"), + PINCTRL_PIN(4, "GPIO_4"), + PINCTRL_PIN(5, "GPIO_5"), + PINCTRL_PIN(6, "GPIO_6"), + PINCTRL_PIN(7, "GPIO_7"), + PINCTRL_PIN(8, "GPIO_8"), + PINCTRL_PIN(9, "GPIO_9"), + PINCTRL_PIN(10, "GPIO_10"), + PINCTRL_PIN(11, "GPIO_11"), + PINCTRL_PIN(12, "GPIO_12"), + PINCTRL_PIN(13, "GPIO_13"), + PINCTRL_PIN(14, "GPIO_14"), + PINCTRL_PIN(15, "GPIO_15"), + PINCTRL_PIN(16, "GPIO_16"), + PINCTRL_PIN(17, "GPIO_17"), + PINCTRL_PIN(18, "GPIO_18"), + PINCTRL_PIN(19, "GPIO_19"), + PINCTRL_PIN(20, "GPIO_20"), + PINCTRL_PIN(21, "GPIO_21"), + PINCTRL_PIN(22, "GPIO_22"), + PINCTRL_PIN(23, "GPIO_23"), + PINCTRL_PIN(24, "GPIO_24"), + PINCTRL_PIN(25, "GPIO_25"), + PINCTRL_PIN(26, "GPIO_26"), + PINCTRL_PIN(27, "GPIO_27"), + PINCTRL_PIN(28, "GPIO_28"), + PINCTRL_PIN(29, "GPIO_29"), + PINCTRL_PIN(30, "GPIO_30"), + PINCTRL_PIN(31, "GPIO_31"), + PINCTRL_PIN(32, "GPIO_32"), + PINCTRL_PIN(33, "GPIO_33"), + PINCTRL_PIN(34, "PWM0"), + PINCTRL_PIN(35, "PWM1"), + PINCTRL_PIN(36, "PWM2"), + PINCTRL_PIN(37, "PWM3"), + PINCTRL_PIN(38, "LPSS_UART0_RXD"), + PINCTRL_PIN(39, "LPSS_UART0_TXD"), + PINCTRL_PIN(40, "LPSS_UART0_RTS_B"), + PINCTRL_PIN(41, "LPSS_UART0_CTS_B"), + PINCTRL_PIN(42, "LPSS_UART1_RXD"), + PINCTRL_PIN(43, "LPSS_UART1_TXD"), + PINCTRL_PIN(44, "LPSS_UART1_RTS_B"), + PINCTRL_PIN(45, "LPSS_UART1_CTS_B"), + PINCTRL_PIN(46, "LPSS_UART2_RXD"), + PINCTRL_PIN(47, "LPSS_UART2_TXD"), + PINCTRL_PIN(48, "LPSS_UART2_RTS_B"), + PINCTRL_PIN(49, "LPSS_UART2_CTS_B"), + PINCTRL_PIN(50, "ISH_UART0_RXD"), + PINCTRL_PIN(51, "ISH_UART0_TXT"), + PINCTRL_PIN(52, "ISH_UART0_RTS_B"), + PINCTRL_PIN(53, "ISH_UART0_CTS_B"), + PINCTRL_PIN(54, "ISH_UART1_RXD"), + PINCTRL_PIN(55, "ISH_UART1_TXT"), + PINCTRL_PIN(56, "ISH_UART1_RTS_B"), + PINCTRL_PIN(57, "ISH_UART1_CTS_B"), + PINCTRL_PIN(58, "ISH_UART2_RXD"), + PINCTRL_PIN(59, "ISH_UART2_TXD"), + PINCTRL_PIN(60, "ISH_UART2_RTS_B"), + PINCTRL_PIN(61, "ISH_UART2_CTS_B"), + PINCTRL_PIN(62, "GP_CAMERASB00"), + PINCTRL_PIN(63, "GP_CAMERASB01"), + PINCTRL_PIN(64, "GP_CAMERASB02"), + PINCTRL_PIN(65, "GP_CAMERASB03"), + PINCTRL_PIN(66, "GP_CAMERASB04"), + PINCTRL_PIN(67, "GP_CAMERASB05"), + PINCTRL_PIN(68, "GP_CAMERASB06"), + PINCTRL_PIN(69, "GP_CAMERASB07"), + PINCTRL_PIN(70, "GP_CAMERASB08"), + PINCTRL_PIN(71, "GP_CAMERASB09"), + PINCTRL_PIN(72, "GP_CAMERASB10"), + PINCTRL_PIN(73, "GP_CAMERASB11"), + PINCTRL_PIN(74, "TCK"), + PINCTRL_PIN(75, "TRST_B"), + PINCTRL_PIN(76, "TMS"), + PINCTRL_PIN(77, "TDI"), + PINCTRL_PIN(78, "CX_PMODE"), + PINCTRL_PIN(79, "CX_PREQ_B"), + PINCTRL_PIN(80, "JTAGX"), + PINCTRL_PIN(81, "CX_PRDY_B"), + PINCTRL_PIN(82, "TDO"), +}; + +static const unsigned bxt_north_pwm0_pins[] = { 34 }; +static const unsigned bxt_north_pwm1_pins[] = { 35 }; +static const unsigned bxt_north_pwm2_pins[] = { 36 }; +static const unsigned bxt_north_pwm3_pins[] = { 37 }; +static const unsigned bxt_north_uart0_pins[] = { 38, 39, 40, 41 }; +static const unsigned bxt_north_uart1_pins[] = { 42, 43, 44, 45 }; +static const unsigned bxt_north_uart2_pins[] = { 46, 47, 48, 49 }; +static const unsigned bxt_north_uart0b_pins[] = { 50, 51, 52, 53 }; +static const unsigned bxt_north_uart1b_pins[] = { 54, 55, 56, 57 }; +static const unsigned bxt_north_uart2b_pins[] = { 58, 59, 60, 61 }; +static const unsigned bxt_north_uart3_pins[] = { 58, 59, 60, 61 }; + +static const struct intel_pingroup bxt_north_groups[] = { + PIN_GROUP("pwm0_grp", bxt_north_pwm0_pins, 1), + PIN_GROUP("pwm1_grp", bxt_north_pwm1_pins, 1), + PIN_GROUP("pwm2_grp", bxt_north_pwm2_pins, 1), + PIN_GROUP("pwm3_grp", bxt_north_pwm3_pins, 1), + PIN_GROUP("uart0_grp", bxt_north_uart0_pins, 1), + PIN_GROUP("uart1_grp", bxt_north_uart1_pins, 1), + PIN_GROUP("uart2_grp", bxt_north_uart2_pins, 1), + PIN_GROUP("uart0b_grp", bxt_north_uart0b_pins, 2), + PIN_GROUP("uart1b_grp", bxt_north_uart1b_pins, 2), + PIN_GROUP("uart2b_grp", bxt_north_uart2b_pins, 2), + PIN_GROUP("uart3_grp", bxt_north_uart3_pins, 3), +}; + +static const char * const bxt_north_pwm0_groups[] = { "pwm0_grp" }; +static const char * const bxt_north_pwm1_groups[] = { "pwm1_grp" }; +static const char * const bxt_north_pwm2_groups[] = { "pwm2_grp" }; +static const char * const bxt_north_pwm3_groups[] = { "pwm3_grp" }; +static const char * const bxt_north_uart0_groups[] = { + "uart0_grp", "uart0b_grp", +}; +static const char * const bxt_north_uart1_groups[] = { + "uart1_grp", "uart1b_grp", +}; +static const char * const bxt_north_uart2_groups[] = { + "uart2_grp", "uart2b_grp", +}; +static const char * const bxt_north_uart3_groups[] = { "uart3_grp" }; + +static const struct intel_function bxt_north_functions[] = { + FUNCTION("pwm0", bxt_north_pwm0_groups), + FUNCTION("pwm1", bxt_north_pwm1_groups), + FUNCTION("pwm2", bxt_north_pwm2_groups), + FUNCTION("pwm3", bxt_north_pwm3_groups), + FUNCTION("uart0", bxt_north_uart0_groups), + FUNCTION("uart1", bxt_north_uart1_groups), + FUNCTION("uart2", bxt_north_uart2_groups), + FUNCTION("uart3", bxt_north_uart3_groups), +}; + +static const struct intel_community bxt_north_communities[] = { + BXT_COMMUNITY(0, 82), +}; + +static const struct intel_pinctrl_soc_data bxt_north_soc_data = { + .uid = "1", + .pins = bxt_north_pins, + .npins = ARRAY_SIZE(bxt_north_pins), + .groups = bxt_north_groups, + .ngroups = ARRAY_SIZE(bxt_north_groups), + .functions = bxt_north_functions, + .nfunctions = ARRAY_SIZE(bxt_north_functions), + .communities = bxt_north_communities, + .ncommunities = ARRAY_SIZE(bxt_north_communities), +}; + +static const struct pinctrl_pin_desc bxt_northwest_pins[] = { + PINCTRL_PIN(0, "PMC_SPI_FS0"), + PINCTRL_PIN(1, "PMC_SPI_FS1"), + PINCTRL_PIN(2, "PMC_SPI_FS2"), + PINCTRL_PIN(3, "PMC_SPI_RXD"), + PINCTRL_PIN(4, "PMC_SPI_TXD"), + PINCTRL_PIN(5, "PMC_SPI_CLK"), + PINCTRL_PIN(6, "PMC_UART_RXD"), + PINCTRL_PIN(7, "PMC_UART_TXD"), + PINCTRL_PIN(8, "PMIC_PWRGOOD"), + PINCTRL_PIN(9, "PMIC_RESET_B"), + PINCTRL_PIN(10, "RTC_CLK"), + PINCTRL_PIN(11, "PMIC_SDWN_B"), + PINCTRL_PIN(12, "PMIC_BCUDISW2"), + PINCTRL_PIN(13, "PMIC_BCUDISCRIT"), + PINCTRL_PIN(14, "PMIC_THERMTRIP_B"), + PINCTRL_PIN(15, "PMIC_STDBY"), + PINCTRL_PIN(16, "SVID0_ALERT_B"), + PINCTRL_PIN(17, "SVID0_DATA"), + PINCTRL_PIN(18, "SVID0_CLK"), + PINCTRL_PIN(19, "PMIC_I2C_SCL"), + PINCTRL_PIN(20, "PMIC_I2C_SDA"), + PINCTRL_PIN(21, "AVS_I2S1_MCLK"), + PINCTRL_PIN(22, "AVS_I2S1_BCLK"), + PINCTRL_PIN(23, "AVS_I2S1_WS_SYNC"), + PINCTRL_PIN(24, "AVS_I2S1_SDI"), + PINCTRL_PIN(25, "AVS_I2S1_SDO"), + PINCTRL_PIN(26, "AVS_M_CLK_A1"), + PINCTRL_PIN(27, "AVS_M_CLK_B1"), + PINCTRL_PIN(28, "AVS_M_DATA_1"), + PINCTRL_PIN(29, "AVS_M_CLK_AB2"), + PINCTRL_PIN(30, "AVS_M_DATA_2"), + PINCTRL_PIN(31, "AVS_I2S2_MCLK"), + PINCTRL_PIN(32, "AVS_I2S2_BCLK"), + PINCTRL_PIN(33, "AVS_I2S2_WS_SYNC"), + PINCTRL_PIN(34, "AVS_I2S2_SDI"), + PINCTRL_PIN(35, "AVS_I2S2_SDOK"), + PINCTRL_PIN(36, "AVS_I2S3_BCLK"), + PINCTRL_PIN(37, "AVS_I2S3_WS_SYNC"), + PINCTRL_PIN(38, "AVS_I2S3_SDI"), + PINCTRL_PIN(39, "AVS_I2S3_SDO"), + PINCTRL_PIN(40, "AVS_I2S4_BCLK"), + PINCTRL_PIN(41, "AVS_I2S4_WS_SYNC"), + PINCTRL_PIN(42, "AVS_I2S4_SDI"), + PINCTRL_PIN(43, "AVS_I2S4_SDO"), + PINCTRL_PIN(44, "PROCHOT_B"), + PINCTRL_PIN(45, "FST_SPI_CS0_B"), + PINCTRL_PIN(46, "FST_SPI_CS1_B"), + PINCTRL_PIN(47, "FST_SPI_MOSI_IO0"), + PINCTRL_PIN(48, "FST_SPI_MISO_IO1"), + PINCTRL_PIN(49, "FST_SPI_IO2"), + PINCTRL_PIN(50, "FST_SPI_IO3"), + PINCTRL_PIN(51, "FST_SPI_CLK"), + PINCTRL_PIN(52, "FST_SPI_CLK_FB"), + PINCTRL_PIN(53, "GP_SSP_0_CLK"), + PINCTRL_PIN(54, "GP_SSP_0_FS0"), + PINCTRL_PIN(55, "GP_SSP_0_FS1"), + PINCTRL_PIN(56, "GP_SSP_0_FS2"), + PINCTRL_PIN(57, "GP_SSP_0_RXD"), + PINCTRL_PIN(58, "GP_SSP_0_TXD"), + PINCTRL_PIN(59, "GP_SSP_1_CLK"), + PINCTRL_PIN(60, "GP_SSP_1_FS0"), + PINCTRL_PIN(61, "GP_SSP_1_FS1"), + PINCTRL_PIN(62, "GP_SSP_1_FS2"), + PINCTRL_PIN(63, "GP_SSP_1_FS3"), + PINCTRL_PIN(64, "GP_SSP_1_RXD"), + PINCTRL_PIN(65, "GP_SSP_1_TXD"), + PINCTRL_PIN(66, "GP_SSP_2_CLK"), + PINCTRL_PIN(67, "GP_SSP_2_FS0"), + PINCTRL_PIN(68, "GP_SSP_2_FS1"), + PINCTRL_PIN(69, "GP_SSP_2_FS2"), + PINCTRL_PIN(70, "GP_SSP_2_RXD"), + PINCTRL_PIN(71, "GP_SSP_2_TXD"), +}; + +static const unsigned bxt_northwest_ssp0_pins[] = { 53, 54, 55, 56, 57, 58 }; +static const unsigned bxt_northwest_ssp1_pins[] = { + 59, 60, 61, 62, 63, 64, 65 +}; +static const unsigned bxt_northwest_ssp2_pins[] = { 66, 67, 68, 69, 70, 71 }; +static const unsigned bxt_northwest_uart3_pins[] = { 67, 68, 69, 70 }; + +static const struct intel_pingroup bxt_northwest_groups[] = { + PIN_GROUP("ssp0_grp", bxt_northwest_ssp0_pins, 1), + PIN_GROUP("ssp1_grp", bxt_northwest_ssp1_pins, 1), + PIN_GROUP("ssp2_grp", bxt_northwest_ssp2_pins, 1), + PIN_GROUP("uart3_grp", bxt_northwest_uart3_pins, 2), +}; + +static const char * const bxt_northwest_ssp0_groups[] = { "ssp0_grp" }; +static const char * const bxt_northwest_ssp1_groups[] = { "ssp1_grp" }; +static const char * const bxt_northwest_ssp2_groups[] = { "ssp2_grp" }; +static const char * const bxt_northwest_uart3_groups[] = { "uart3_grp" }; + +static const struct intel_function bxt_northwest_functions[] = { + FUNCTION("ssp0", bxt_northwest_ssp0_groups), + FUNCTION("ssp1", bxt_northwest_ssp1_groups), + FUNCTION("ssp2", bxt_northwest_ssp2_groups), + FUNCTION("uart3", bxt_northwest_uart3_groups), +}; + +static const struct intel_community bxt_northwest_communities[] = { + BXT_COMMUNITY(0, 71), +}; + +static const struct intel_pinctrl_soc_data bxt_northwest_soc_data = { + .uid = "2", + .pins = bxt_northwest_pins, + .npins = ARRAY_SIZE(bxt_northwest_pins), + .groups = bxt_northwest_groups, + .ngroups = ARRAY_SIZE(bxt_northwest_groups), + .functions = bxt_northwest_functions, + .nfunctions = ARRAY_SIZE(bxt_northwest_functions), + .communities = bxt_northwest_communities, + .ncommunities = ARRAY_SIZE(bxt_northwest_communities), +}; + +static const struct pinctrl_pin_desc bxt_west_pins[] = { + PINCTRL_PIN(0, "LPSS_I2C0_SDA"), + PINCTRL_PIN(1, "LPSS_I2C0_SCL"), + PINCTRL_PIN(2, "LPSS_I2C1_SDA"), + PINCTRL_PIN(3, "LPSS_I2C1_SCL"), + PINCTRL_PIN(4, "LPSS_I2C2_SDA"), + PINCTRL_PIN(5, "LPSS_I2C2_SCL"), + PINCTRL_PIN(6, "LPSS_I2C3_SDA"), + PINCTRL_PIN(7, "LPSS_I2C3_SCL"), + PINCTRL_PIN(8, "LPSS_I2C4_SDA"), + PINCTRL_PIN(9, "LPSS_I2C4_SCL"), + PINCTRL_PIN(10, "LPSS_I2C5_SDA"), + PINCTRL_PIN(11, "LPSS_I2C5_SCL"), + PINCTRL_PIN(12, "LPSS_I2C6_SDA"), + PINCTRL_PIN(13, "LPSS_I2C6_SCL"), + PINCTRL_PIN(14, "LPSS_I2C7_SDA"), + PINCTRL_PIN(15, "LPSS_I2C7_SCL"), + PINCTRL_PIN(16, "ISH_I2C0_SDA"), + PINCTRL_PIN(17, "ISH_I2C0_SCL"), + PINCTRL_PIN(18, "ISH_I2C1_SDA"), + PINCTRL_PIN(19, "ISH_I2C1_SCL"), + PINCTRL_PIN(20, "ISH_I2C2_SDA"), + PINCTRL_PIN(21, "ISH_I2C2_SCL"), + PINCTRL_PIN(22, "ISH_GPIO_0"), + PINCTRL_PIN(23, "ISH_GPIO_1"), + PINCTRL_PIN(24, "ISH_GPIO_2"), + PINCTRL_PIN(25, "ISH_GPIO_3"), + PINCTRL_PIN(26, "ISH_GPIO_4"), + PINCTRL_PIN(27, "ISH_GPIO_5"), + PINCTRL_PIN(28, "ISH_GPIO_6"), + PINCTRL_PIN(29, "ISH_GPIO_7"), + PINCTRL_PIN(30, "ISH_GPIO_8"), + PINCTRL_PIN(31, "ISH_GPIO_9"), + PINCTRL_PIN(32, "MODEM_CLKREQ"), + PINCTRL_PIN(33, "DGCLKDBG_PMC_0"), + PINCTRL_PIN(34, "DGCLKDBG_PMC_1"), + PINCTRL_PIN(35, "DGCLKDBG_PMC_2"), + PINCTRL_PIN(36, "DGCLKDBG_ICLK_0"), + PINCTRL_PIN(37, "DGCLKDBG_ICLK_1"), + PINCTRL_PIN(38, "OSC_CLK_OUT_0"), + PINCTRL_PIN(39, "OSC_CLK_OUT_1"), + PINCTRL_PIN(40, "OSC_CLK_OUT_2"), + PINCTRL_PIN(41, "OSC_CLK_OUT_3"), +}; + +static const unsigned bxt_west_i2c0_pins[] = { 0, 1 }; +static const unsigned bxt_west_i2c1_pins[] = { 2, 3 }; +static const unsigned bxt_west_i2c2_pins[] = { 4, 5 }; +static const unsigned bxt_west_i2c3_pins[] = { 6, 7 }; +static const unsigned bxt_west_i2c4_pins[] = { 8, 9 }; +static const unsigned bxt_west_i2c5_pins[] = { 10, 11 }; +static const unsigned bxt_west_i2c6_pins[] = { 12, 13 }; +static const unsigned bxt_west_i2c7_pins[] = { 14, 15 }; +static const unsigned bxt_west_i2c5b_pins[] = { 16, 17 }; +static const unsigned bxt_west_i2c6b_pins[] = { 18, 19 }; +static const unsigned bxt_west_i2c7b_pins[] = { 20, 21 }; + +static const struct intel_pingroup bxt_west_groups[] = { + PIN_GROUP("i2c0_grp", bxt_west_i2c0_pins, 1), + PIN_GROUP("i2c1_grp", bxt_west_i2c1_pins, 1), + PIN_GROUP("i2c2_grp", bxt_west_i2c2_pins, 1), + PIN_GROUP("i2c3_grp", bxt_west_i2c3_pins, 1), + PIN_GROUP("i2c4_grp", bxt_west_i2c4_pins, 1), + PIN_GROUP("i2c5_grp", bxt_west_i2c5_pins, 1), + PIN_GROUP("i2c6_grp", bxt_west_i2c6_pins, 1), + PIN_GROUP("i2c7_grp", bxt_west_i2c7_pins, 1), + PIN_GROUP("i2c5b_grp", bxt_west_i2c5b_pins, 2), + PIN_GROUP("i2c6b_grp", bxt_west_i2c6b_pins, 2), + PIN_GROUP("i2c7b_grp", bxt_west_i2c7b_pins, 2), +}; + +static const char * const bxt_west_i2c0_groups[] = { "i2c0_grp" }; +static const char * const bxt_west_i2c1_groups[] = { "i2c1_grp" }; +static const char * const bxt_west_i2c2_groups[] = { "i2c2_grp" }; +static const char * const bxt_west_i2c3_groups[] = { "i2c3_grp" }; +static const char * const bxt_west_i2c4_groups[] = { "i2c4_grp" }; +static const char * const bxt_west_i2c5_groups[] = { "i2c5_grp", "i2c5b_grp" }; +static const char * const bxt_west_i2c6_groups[] = { "i2c6_grp", "i2c6b_grp" }; +static const char * const bxt_west_i2c7_groups[] = { "i2c7_grp", "i2c7b_grp" }; + +static const struct intel_function bxt_west_functions[] = { + FUNCTION("i2c0", bxt_west_i2c0_groups), + FUNCTION("i2c1", bxt_west_i2c1_groups), + FUNCTION("i2c2", bxt_west_i2c2_groups), + FUNCTION("i2c3", bxt_west_i2c3_groups), + FUNCTION("i2c4", bxt_west_i2c4_groups), + FUNCTION("i2c5", bxt_west_i2c5_groups), + FUNCTION("i2c6", bxt_west_i2c6_groups), + FUNCTION("i2c7", bxt_west_i2c7_groups), +}; + +static const struct intel_community bxt_west_communities[] = { + BXT_COMMUNITY(0, 41), +}; + +static const struct intel_pinctrl_soc_data bxt_west_soc_data = { + .uid = "3", + .pins = bxt_west_pins, + .npins = ARRAY_SIZE(bxt_west_pins), + .groups = bxt_west_groups, + .ngroups = ARRAY_SIZE(bxt_west_groups), + .functions = bxt_west_functions, + .nfunctions = ARRAY_SIZE(bxt_west_functions), + .communities = bxt_west_communities, + .ncommunities = ARRAY_SIZE(bxt_west_communities), +}; + +static const struct pinctrl_pin_desc bxt_southwest_pins[] = { + PINCTRL_PIN(0, "EMMC0_CLK"), + PINCTRL_PIN(1, "EMMC0_D0"), + PINCTRL_PIN(2, "EMMC0_D1"), + PINCTRL_PIN(3, "EMMC0_D2"), + PINCTRL_PIN(4, "EMMC0_D3"), + PINCTRL_PIN(5, "EMMC0_D4"), + PINCTRL_PIN(6, "EMMC0_D5"), + PINCTRL_PIN(7, "EMMC0_D6"), + PINCTRL_PIN(8, "EMMC0_D7"), + PINCTRL_PIN(9, "EMMC0_CMD"), + PINCTRL_PIN(10, "SDIO_CLK"), + PINCTRL_PIN(11, "SDIO_D0"), + PINCTRL_PIN(12, "SDIO_D1"), + PINCTRL_PIN(13, "SDIO_D2"), + PINCTRL_PIN(14, "SDIO_D3"), + PINCTRL_PIN(15, "SDIO_CMD"), + PINCTRL_PIN(16, "SDCARD_CLK"), + PINCTRL_PIN(17, "SDCARD_D0"), + PINCTRL_PIN(18, "SDCARD_D1"), + PINCTRL_PIN(19, "SDCARD_D2"), + PINCTRL_PIN(20, "SDCARD_D3"), + PINCTRL_PIN(21, "SDCARD_CD_B"), + PINCTRL_PIN(22, "SDCARD_CMD"), + PINCTRL_PIN(23, "SDCARD_LVL_CLK_FB"), + PINCTRL_PIN(24, "SDCARD_LVL_CMD_DIR"), + PINCTRL_PIN(25, "SDCARD_LVL_DAT_DIR"), + PINCTRL_PIN(26, "EMMC0_STROBE"), + PINCTRL_PIN(27, "SDIO_PWR_DOWN_B"), + PINCTRL_PIN(28, "SDCARD_PWR_DOWN_B"), + PINCTRL_PIN(29, "SDCARD_LVL_SEL"), + PINCTRL_PIN(30, "SDCARD_LVL_WP"), +}; + +static const unsigned bxt_southwest_emmc0_pins[] = { + 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 26, +}; +static const unsigned bxt_southwest_sdio_pins[] = { + 10, 11, 12, 13, 14, 15, 27, +}; +static const unsigned bxt_southwest_sdcard_pins[] = { + 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 28, 29, 30, +}; + +static const struct intel_pingroup bxt_southwest_groups[] = { + PIN_GROUP("emmc0_grp", bxt_southwest_emmc0_pins, 1), + PIN_GROUP("sdio_grp", bxt_southwest_sdio_pins, 1), + PIN_GROUP("sdcard_grp", bxt_southwest_sdcard_pins, 1), +}; + +static const char * const bxt_southwest_emmc0_groups[] = { "emmc0_grp" }; +static const char * const bxt_southwest_sdio_groups[] = { "sdio_grp" }; +static const char * const bxt_southwest_sdcard_groups[] = { "sdcard_grp" }; + +static const struct intel_function bxt_southwest_functions[] = { + FUNCTION("emmc0", bxt_southwest_emmc0_groups), + FUNCTION("sdio", bxt_southwest_sdio_groups), + FUNCTION("sdcard", bxt_southwest_sdcard_groups), +}; + +static const struct intel_community bxt_southwest_communities[] = { + BXT_COMMUNITY(0, 30), +}; + +static const struct intel_pinctrl_soc_data bxt_southwest_soc_data = { + .uid = "4", + .pins = bxt_southwest_pins, + .npins = ARRAY_SIZE(bxt_southwest_pins), + .groups = bxt_southwest_groups, + .ngroups = ARRAY_SIZE(bxt_southwest_groups), + .functions = bxt_southwest_functions, + .nfunctions = ARRAY_SIZE(bxt_southwest_functions), + .communities = bxt_southwest_communities, + .ncommunities = ARRAY_SIZE(bxt_southwest_communities), +}; + +static const struct pinctrl_pin_desc bxt_south_pins[] = { + PINCTRL_PIN(0, "HV_DDI0_DDC_SDA"), + PINCTRL_PIN(1, "HV_DDI0_DDC_SCL"), + PINCTRL_PIN(2, "HV_DDI1_DDC_SDA"), + PINCTRL_PIN(3, "HV_DDI1_DDC_SCL"), + PINCTRL_PIN(4, "DBI_SDA"), + PINCTRL_PIN(5, "DBI_SCL"), + PINCTRL_PIN(6, "PANEL0_VDDEN"), + PINCTRL_PIN(7, "PANEL0_BKLTEN"), + PINCTRL_PIN(8, "PANEL0_BKLTCTL"), + PINCTRL_PIN(9, "PANEL1_VDDEN"), + PINCTRL_PIN(10, "PANEL1_BKLTEN"), + PINCTRL_PIN(11, "PANEL1_BKLTCTL"), + PINCTRL_PIN(12, "DBI_CSX"), + PINCTRL_PIN(13, "DBI_RESX"), + PINCTRL_PIN(14, "GP_INTD_DSI_TE1"), + PINCTRL_PIN(15, "GP_INTD_DSI_TE2"), + PINCTRL_PIN(16, "USB_OC0_B"), + PINCTRL_PIN(17, "USB_OC1_B"), + PINCTRL_PIN(18, "MEX_WAKE0_B"), + PINCTRL_PIN(19, "MEX_WAKE1_B"), +}; + +static const struct intel_community bxt_south_communities[] = { + BXT_COMMUNITY(0, 19), +}; + +static const struct intel_pinctrl_soc_data bxt_south_soc_data = { + .uid = "5", + .pins = bxt_south_pins, + .npins = ARRAY_SIZE(bxt_south_pins), + .communities = bxt_south_communities, + .ncommunities = ARRAY_SIZE(bxt_south_communities), +}; + +static const struct intel_pinctrl_soc_data *bxt_pinctrl_soc_data[] = { + &bxt_north_soc_data, + &bxt_northwest_soc_data, + &bxt_west_soc_data, + &bxt_southwest_soc_data, + &bxt_south_soc_data, + NULL, +}; + +/* APL */ +static const struct pinctrl_pin_desc apl_north_pins[] = { + PINCTRL_PIN(0, "GPIO_0"), + PINCTRL_PIN(1, "GPIO_1"), + PINCTRL_PIN(2, "GPIO_2"), + PINCTRL_PIN(3, "GPIO_3"), + PINCTRL_PIN(4, "GPIO_4"), + PINCTRL_PIN(5, "GPIO_5"), + PINCTRL_PIN(6, "GPIO_6"), + PINCTRL_PIN(7, "GPIO_7"), + PINCTRL_PIN(8, "GPIO_8"), + PINCTRL_PIN(9, "GPIO_9"), + PINCTRL_PIN(10, "GPIO_10"), + PINCTRL_PIN(11, "GPIO_11"), + PINCTRL_PIN(12, "GPIO_12"), + PINCTRL_PIN(13, "GPIO_13"), + PINCTRL_PIN(14, "GPIO_14"), + PINCTRL_PIN(15, "GPIO_15"), + PINCTRL_PIN(16, "GPIO_16"), + PINCTRL_PIN(17, "GPIO_17"), + PINCTRL_PIN(18, "GPIO_18"), + PINCTRL_PIN(19, "GPIO_19"), + PINCTRL_PIN(20, "GPIO_20"), + PINCTRL_PIN(21, "GPIO_21"), + PINCTRL_PIN(22, "GPIO_22"), + PINCTRL_PIN(23, "GPIO_23"), + PINCTRL_PIN(24, "GPIO_24"), + PINCTRL_PIN(25, "GPIO_25"), + PINCTRL_PIN(26, "GPIO_26"), + PINCTRL_PIN(27, "GPIO_27"), + PINCTRL_PIN(28, "GPIO_28"), + PINCTRL_PIN(29, "GPIO_29"), + PINCTRL_PIN(30, "GPIO_30"), + PINCTRL_PIN(31, "GPIO_31"), + PINCTRL_PIN(32, "GPIO_32"), + PINCTRL_PIN(33, "GPIO_33"), + PINCTRL_PIN(34, "PWM0"), + PINCTRL_PIN(35, "PWM1"), + PINCTRL_PIN(36, "PWM2"), + PINCTRL_PIN(37, "PWM3"), + PINCTRL_PIN(38, "LPSS_UART0_RXD"), + PINCTRL_PIN(39, "LPSS_UART0_TXD"), + PINCTRL_PIN(40, "LPSS_UART0_RTS_B"), + PINCTRL_PIN(41, "LPSS_UART0_CTS_B"), + PINCTRL_PIN(42, "LPSS_UART1_RXD"), + PINCTRL_PIN(43, "LPSS_UART1_TXD"), + PINCTRL_PIN(44, "LPSS_UART1_RTS_B"), + PINCTRL_PIN(45, "LPSS_UART1_CTS_B"), + PINCTRL_PIN(46, "LPSS_UART2_RXD"), + PINCTRL_PIN(47, "LPSS_UART2_TXD"), + PINCTRL_PIN(48, "LPSS_UART2_RTS_B"), + PINCTRL_PIN(49, "LPSS_UART2_CTS_B"), + PINCTRL_PIN(50, "GP_CAMERASB00"), + PINCTRL_PIN(51, "GP_CAMERASB01"), + PINCTRL_PIN(52, "GP_CAMERASB02"), + PINCTRL_PIN(53, "GP_CAMERASB03"), + PINCTRL_PIN(54, "GP_CAMERASB04"), + PINCTRL_PIN(55, "GP_CAMERASB05"), + PINCTRL_PIN(56, "GP_CAMERASB06"), + PINCTRL_PIN(57, "GP_CAMERASB07"), + PINCTRL_PIN(58, "GP_CAMERASB08"), + PINCTRL_PIN(59, "GP_CAMERASB09"), + PINCTRL_PIN(60, "GP_CAMERASB10"), + PINCTRL_PIN(61, "GP_CAMERASB11"), + PINCTRL_PIN(62, "TCK"), + PINCTRL_PIN(63, "TRST_B"), + PINCTRL_PIN(64, "TMS"), + PINCTRL_PIN(65, "TDI"), + PINCTRL_PIN(66, "CX_PMODE"), + PINCTRL_PIN(67, "CX_PREQ_B"), + PINCTRL_PIN(68, "JTAGX"), + PINCTRL_PIN(69, "CX_PRDY_B"), + PINCTRL_PIN(70, "TDO"), + PINCTRL_PIN(71, "CNV_BRI_DT"), + PINCTRL_PIN(72, "CNV_BRI_RSP"), + PINCTRL_PIN(73, "CNV_RGI_DT"), + PINCTRL_PIN(74, "CNV_RGI_RSP"), + PINCTRL_PIN(75, "SVID0_ALERT_B"), + PINCTRL_PIN(76, "SVID0_DATA"), + PINCTRL_PIN(77, "SVID0_CLK"), +}; + +static const unsigned apl_north_pwm0_pins[] = { 34 }; +static const unsigned apl_north_pwm1_pins[] = { 35 }; +static const unsigned apl_north_pwm2_pins[] = { 36 }; +static const unsigned apl_north_pwm3_pins[] = { 37 }; +static const unsigned apl_north_uart0_pins[] = { 38, 39, 40, 41 }; +static const unsigned apl_north_uart1_pins[] = { 42, 43, 44, 45 }; +static const unsigned apl_north_uart2_pins[] = { 46, 47, 48, 49 }; + +static const struct intel_pingroup apl_north_groups[] = { + PIN_GROUP("pwm0_grp", apl_north_pwm0_pins, 1), + PIN_GROUP("pwm1_grp", apl_north_pwm1_pins, 1), + PIN_GROUP("pwm2_grp", apl_north_pwm2_pins, 1), + PIN_GROUP("pwm3_grp", apl_north_pwm3_pins, 1), + PIN_GROUP("uart0_grp", apl_north_uart0_pins, 1), + PIN_GROUP("uart1_grp", apl_north_uart1_pins, 1), + PIN_GROUP("uart2_grp", apl_north_uart2_pins, 1), +}; + +static const char * const apl_north_pwm0_groups[] = { "pwm0_grp" }; +static const char * const apl_north_pwm1_groups[] = { "pwm1_grp" }; +static const char * const apl_north_pwm2_groups[] = { "pwm2_grp" }; +static const char * const apl_north_pwm3_groups[] = { "pwm3_grp" }; +static const char * const apl_north_uart0_groups[] = { "uart0_grp" }; +static const char * const apl_north_uart1_groups[] = { "uart1_grp" }; +static const char * const apl_north_uart2_groups[] = { "uart2_grp" }; + +static const struct intel_function apl_north_functions[] = { + FUNCTION("pwm0", apl_north_pwm0_groups), + FUNCTION("pwm1", apl_north_pwm1_groups), + FUNCTION("pwm2", apl_north_pwm2_groups), + FUNCTION("pwm3", apl_north_pwm3_groups), + FUNCTION("uart0", apl_north_uart0_groups), + FUNCTION("uart1", apl_north_uart1_groups), + FUNCTION("uart2", apl_north_uart2_groups), +}; + +static const struct intel_community apl_north_communities[] = { + BXT_COMMUNITY(0, 77), +}; + +static const struct intel_pinctrl_soc_data apl_north_soc_data = { + .uid = "1", + .pins = apl_north_pins, + .npins = ARRAY_SIZE(apl_north_pins), + .groups = apl_north_groups, + .ngroups = ARRAY_SIZE(apl_north_groups), + .functions = apl_north_functions, + .nfunctions = ARRAY_SIZE(apl_north_functions), + .communities = apl_north_communities, + .ncommunities = ARRAY_SIZE(apl_north_communities), +}; + +static const struct pinctrl_pin_desc apl_northwest_pins[] = { + PINCTRL_PIN(0, "HV_DDI0_DDC_SDA"), + PINCTRL_PIN(1, "HV_DDI0_DDC_SCL"), + PINCTRL_PIN(2, "HV_DDI1_DDC_SDA"), + PINCTRL_PIN(3, "HV_DDI1_DDC_SCL"), + PINCTRL_PIN(4, "DBI_SDA"), + PINCTRL_PIN(5, "DBI_SCL"), + PINCTRL_PIN(6, "PANEL0_VDDEN"), + PINCTRL_PIN(7, "PANEL0_BKLTEN"), + PINCTRL_PIN(8, "PANEL0_BKLTCTL"), + PINCTRL_PIN(9, "PANEL1_VDDEN"), + PINCTRL_PIN(10, "PANEL1_BKLTEN"), + PINCTRL_PIN(11, "PANEL1_BKLTCTL"), + PINCTRL_PIN(12, "DBI_CSX"), + PINCTRL_PIN(13, "DBI_RESX"), + PINCTRL_PIN(14, "GP_INTD_DSI_TE1"), + PINCTRL_PIN(15, "GP_INTD_DSI_TE2"), + PINCTRL_PIN(16, "USB_OC0_B"), + PINCTRL_PIN(17, "USB_OC1_B"), + PINCTRL_PIN(18, "PMC_SPI_FS0"), + PINCTRL_PIN(19, "PMC_SPI_FS1"), + PINCTRL_PIN(20, "PMC_SPI_FS2"), + PINCTRL_PIN(21, "PMC_SPI_RXD"), + PINCTRL_PIN(22, "PMC_SPI_TXD"), + PINCTRL_PIN(23, "PMC_SPI_CLK"), + PINCTRL_PIN(24, "PMIC_PWRGOOD"), + PINCTRL_PIN(25, "PMIC_RESET_B"), + PINCTRL_PIN(26, "PMIC_SDWN_B"), + PINCTRL_PIN(27, "PMIC_BCUDISW2"), + PINCTRL_PIN(28, "PMIC_BCUDISCRIT"), + PINCTRL_PIN(29, "PMIC_THERMTRIP_B"), + PINCTRL_PIN(30, "PMIC_STDBY"), + PINCTRL_PIN(31, "PROCHOT_B"), + PINCTRL_PIN(32, "PMIC_I2C_SCL"), + PINCTRL_PIN(33, "PMIC_I2C_SDA"), + PINCTRL_PIN(34, "AVS_I2S1_MCLK"), + PINCTRL_PIN(35, "AVS_I2S1_BCLK"), + PINCTRL_PIN(36, "AVS_I2S1_WS_SYNC"), + PINCTRL_PIN(37, "AVS_I2S1_SDI"), + PINCTRL_PIN(38, "AVS_I2S1_SDO"), + PINCTRL_PIN(39, "AVS_M_CLK_A1"), + PINCTRL_PIN(40, "AVS_M_CLK_B1"), + PINCTRL_PIN(41, "AVS_M_DATA_1"), + PINCTRL_PIN(42, "AVS_M_CLK_AB2"), + PINCTRL_PIN(43, "AVS_M_DATA_2"), + PINCTRL_PIN(44, "AVS_I2S2_MCLK"), + PINCTRL_PIN(45, "AVS_I2S2_BCLK"), + PINCTRL_PIN(46, "AVS_I2S2_WS_SYNC"), + PINCTRL_PIN(47, "AVS_I2S2_SDI"), + PINCTRL_PIN(48, "AVS_I2S2_SDO"), + PINCTRL_PIN(49, "AVS_I2S3_BCLK"), + PINCTRL_PIN(50, "AVS_I2S3_WS_SYNC"), + PINCTRL_PIN(51, "AVS_I2S3_SDI"), + PINCTRL_PIN(52, "AVS_I2S3_SDO"), + PINCTRL_PIN(53, "FST_SPI_CS0_B"), + PINCTRL_PIN(54, "FST_SPI_CS1_B"), + PINCTRL_PIN(55, "FST_SPI_MOSI_IO0"), + PINCTRL_PIN(56, "FST_SPI_MISO_IO1"), + PINCTRL_PIN(57, "FST_SPI_IO2"), + PINCTRL_PIN(58, "FST_SPI_IO3"), + PINCTRL_PIN(59, "FST_SPI_CLK"), + PINCTRL_PIN(60, "FST_SPI_CLK_FB"), + PINCTRL_PIN(61, "GP_SSP_0_CLK"), + PINCTRL_PIN(62, "GP_SSP_0_FS0"), + PINCTRL_PIN(63, "GP_SSP_0_FS1"), + PINCTRL_PIN(64, "GP_SSP_0_RXD"), + PINCTRL_PIN(65, "GP_SSP_0_TXD"), + PINCTRL_PIN(66, "GP_SSP_1_CLK"), + PINCTRL_PIN(67, "GP_SSP_1_FS0"), + PINCTRL_PIN(68, "GP_SSP_1_FS1"), + PINCTRL_PIN(69, "GP_SSP_1_RXD"), + PINCTRL_PIN(70, "GP_SSP_1_TXD"), + PINCTRL_PIN(71, "GP_SSP_2_CLK"), + PINCTRL_PIN(72, "GP_SSP_2_FS0"), + PINCTRL_PIN(73, "GP_SSP_2_FS1"), + PINCTRL_PIN(74, "GP_SSP_2_FS2"), + PINCTRL_PIN(75, "GP_SSP_2_RXD"), + PINCTRL_PIN(76, "GP_SSP_2_TXD"), +}; + +static const unsigned apl_northwest_ssp0_pins[] = { 61, 62, 63, 64, 65 }; +static const unsigned apl_northwest_ssp1_pins[] = { 66, 67, 68, 69, 70 }; +static const unsigned apl_northwest_ssp2_pins[] = { 71, 72, 73, 74, 75, 76 }; +static const unsigned apl_northwest_uart3_pins[] = { 67, 68, 69, 70 }; + +static const struct intel_pingroup apl_northwest_groups[] = { + PIN_GROUP("ssp0_grp", apl_northwest_ssp0_pins, 1), + PIN_GROUP("ssp1_grp", apl_northwest_ssp1_pins, 1), + PIN_GROUP("ssp2_grp", apl_northwest_ssp2_pins, 1), + PIN_GROUP("uart3_grp", apl_northwest_uart3_pins, 2), +}; + +static const char * const apl_northwest_ssp0_groups[] = { "ssp0_grp" }; +static const char * const apl_northwest_ssp1_groups[] = { "ssp1_grp" }; +static const char * const apl_northwest_ssp2_groups[] = { "ssp2_grp" }; +static const char * const apl_northwest_uart3_groups[] = { "uart3_grp" }; + +static const struct intel_function apl_northwest_functions[] = { + FUNCTION("ssp0", apl_northwest_ssp0_groups), + FUNCTION("ssp1", apl_northwest_ssp1_groups), + FUNCTION("ssp2", apl_northwest_ssp2_groups), + FUNCTION("uart3", apl_northwest_uart3_groups), +}; + +static const struct intel_community apl_northwest_communities[] = { + BXT_COMMUNITY(0, 76), +}; + +static const struct intel_pinctrl_soc_data apl_northwest_soc_data = { + .uid = "2", + .pins = apl_northwest_pins, + .npins = ARRAY_SIZE(apl_northwest_pins), + .groups = apl_northwest_groups, + .ngroups = ARRAY_SIZE(apl_northwest_groups), + .functions = apl_northwest_functions, + .nfunctions = ARRAY_SIZE(apl_northwest_functions), + .communities = apl_northwest_communities, + .ncommunities = ARRAY_SIZE(apl_northwest_communities), +}; + +static const struct pinctrl_pin_desc apl_west_pins[] = { + PINCTRL_PIN(0, "LPSS_I2C0_SDA"), + PINCTRL_PIN(1, "LPSS_I2C0_SCL"), + PINCTRL_PIN(2, "LPSS_I2C1_SDA"), + PINCTRL_PIN(3, "LPSS_I2C1_SCL"), + PINCTRL_PIN(4, "LPSS_I2C2_SDA"), + PINCTRL_PIN(5, "LPSS_I2C2_SCL"), + PINCTRL_PIN(6, "LPSS_I2C3_SDA"), + PINCTRL_PIN(7, "LPSS_I2C3_SCL"), + PINCTRL_PIN(8, "LPSS_I2C4_SDA"), + PINCTRL_PIN(9, "LPSS_I2C4_SCL"), + PINCTRL_PIN(10, "LPSS_I2C5_SDA"), + PINCTRL_PIN(11, "LPSS_I2C5_SCL"), + PINCTRL_PIN(12, "LPSS_I2C6_SDA"), + PINCTRL_PIN(13, "LPSS_I2C6_SCL"), + PINCTRL_PIN(14, "LPSS_I2C7_SDA"), + PINCTRL_PIN(15, "LPSS_I2C7_SCL"), + PINCTRL_PIN(16, "ISH_GPIO_0"), + PINCTRL_PIN(17, "ISH_GPIO_1"), + PINCTRL_PIN(18, "ISH_GPIO_2"), + PINCTRL_PIN(19, "ISH_GPIO_3"), + PINCTRL_PIN(20, "ISH_GPIO_4"), + PINCTRL_PIN(21, "ISH_GPIO_5"), + PINCTRL_PIN(22, "ISH_GPIO_6"), + PINCTRL_PIN(23, "ISH_GPIO_7"), + PINCTRL_PIN(24, "ISH_GPIO_8"), + PINCTRL_PIN(25, "ISH_GPIO_9"), + PINCTRL_PIN(26, "PCIE_CLKREQ0_B"), + PINCTRL_PIN(27, "PCIE_CLKREQ1_B"), + PINCTRL_PIN(28, "PCIE_CLKREQ2_B"), + PINCTRL_PIN(29, "PCIE_CLKREQ3_B"), + PINCTRL_PIN(30, "OSC_CLK_OUT_0"), + PINCTRL_PIN(31, "OSC_CLK_OUT_1"), + PINCTRL_PIN(32, "OSC_CLK_OUT_2"), + PINCTRL_PIN(33, "OSC_CLK_OUT_3"), + PINCTRL_PIN(34, "OSC_CLK_OUT_4"), + PINCTRL_PIN(35, "PMU_AC_PRESENT"), + PINCTRL_PIN(36, "PMU_BATLOW_B"), + PINCTRL_PIN(37, "PMU_PLTRST_B"), + PINCTRL_PIN(38, "PMU_PWRBTN_B"), + PINCTRL_PIN(39, "PMU_RESETBUTTON_B"), + PINCTRL_PIN(40, "PMU_SLP_S0_B"), + PINCTRL_PIN(41, "PMU_SLP_S3_B"), + PINCTRL_PIN(42, "PMU_SLP_S4_B"), + PINCTRL_PIN(43, "PMU_SUSCLK"), + PINCTRL_PIN(44, "PMU_WAKE_B"), + PINCTRL_PIN(45, "SUS_STAT_B"), + PINCTRL_PIN(46, "SUSPWRDNACK"), +}; + +static const unsigned apl_west_i2c0_pins[] = { 0, 1 }; +static const unsigned apl_west_i2c1_pins[] = { 2, 3 }; +static const unsigned apl_west_i2c2_pins[] = { 4, 5 }; +static const unsigned apl_west_i2c3_pins[] = { 6, 7 }; +static const unsigned apl_west_i2c4_pins[] = { 8, 9 }; +static const unsigned apl_west_i2c5_pins[] = { 10, 11 }; +static const unsigned apl_west_i2c6_pins[] = { 12, 13 }; +static const unsigned apl_west_i2c7_pins[] = { 14, 15 }; +static const unsigned apl_west_uart2_pins[] = { 20, 21, 22, 34 }; + +static const struct intel_pingroup apl_west_groups[] = { + PIN_GROUP("i2c0_grp", apl_west_i2c0_pins, 1), + PIN_GROUP("i2c1_grp", apl_west_i2c1_pins, 1), + PIN_GROUP("i2c2_grp", apl_west_i2c2_pins, 1), + PIN_GROUP("i2c3_grp", apl_west_i2c3_pins, 1), + PIN_GROUP("i2c4_grp", apl_west_i2c4_pins, 1), + PIN_GROUP("i2c5_grp", apl_west_i2c5_pins, 1), + PIN_GROUP("i2c6_grp", apl_west_i2c6_pins, 1), + PIN_GROUP("i2c7_grp", apl_west_i2c7_pins, 1), + PIN_GROUP("uart2_grp", apl_west_uart2_pins, 3), +}; + +static const char * const apl_west_i2c0_groups[] = { "i2c0_grp" }; +static const char * const apl_west_i2c1_groups[] = { "i2c1_grp" }; +static const char * const apl_west_i2c2_groups[] = { "i2c2_grp" }; +static const char * const apl_west_i2c3_groups[] = { "i2c3_grp" }; +static const char * const apl_west_i2c4_groups[] = { "i2c4_grp" }; +static const char * const apl_west_i2c5_groups[] = { "i2c5_grp" }; +static const char * const apl_west_i2c6_groups[] = { "i2c6_grp" }; +static const char * const apl_west_i2c7_groups[] = { "i2c7_grp" }; +static const char * const apl_west_uart2_groups[] = { "uart2_grp" }; + +static const struct intel_function apl_west_functions[] = { + FUNCTION("i2c0", apl_west_i2c0_groups), + FUNCTION("i2c1", apl_west_i2c1_groups), + FUNCTION("i2c2", apl_west_i2c2_groups), + FUNCTION("i2c3", apl_west_i2c3_groups), + FUNCTION("i2c4", apl_west_i2c4_groups), + FUNCTION("i2c5", apl_west_i2c5_groups), + FUNCTION("i2c6", apl_west_i2c6_groups), + FUNCTION("i2c7", apl_west_i2c7_groups), + FUNCTION("uart2", apl_west_uart2_groups), +}; + +static const struct intel_community apl_west_communities[] = { + BXT_COMMUNITY(0, 46), +}; + +static const struct intel_pinctrl_soc_data apl_west_soc_data = { + .uid = "3", + .pins = apl_west_pins, + .npins = ARRAY_SIZE(apl_west_pins), + .groups = apl_west_groups, + .ngroups = ARRAY_SIZE(apl_west_groups), + .functions = apl_west_functions, + .nfunctions = ARRAY_SIZE(apl_west_functions), + .communities = apl_west_communities, + .ncommunities = ARRAY_SIZE(apl_west_communities), +}; + +static const struct pinctrl_pin_desc apl_southwest_pins[] = { + PINCTRL_PIN(0, "PCIE_WAKE0_B"), + PINCTRL_PIN(1, "PCIE_WAKE1_B"), + PINCTRL_PIN(2, "PCIE_WAKE2_B"), + PINCTRL_PIN(3, "PCIE_WAKE3_B"), + PINCTRL_PIN(4, "EMMC0_CLK"), + PINCTRL_PIN(5, "EMMC0_D0"), + PINCTRL_PIN(6, "EMMC0_D1"), + PINCTRL_PIN(7, "EMMC0_D2"), + PINCTRL_PIN(8, "EMMC0_D3"), + PINCTRL_PIN(9, "EMMC0_D4"), + PINCTRL_PIN(10, "EMMC0_D5"), + PINCTRL_PIN(11, "EMMC0_D6"), + PINCTRL_PIN(12, "EMMC0_D7"), + PINCTRL_PIN(13, "EMMC0_CMD"), + PINCTRL_PIN(14, "SDIO_CLK"), + PINCTRL_PIN(15, "SDIO_D0"), + PINCTRL_PIN(16, "SDIO_D1"), + PINCTRL_PIN(17, "SDIO_D2"), + PINCTRL_PIN(18, "SDIO_D3"), + PINCTRL_PIN(19, "SDIO_CMD"), + PINCTRL_PIN(20, "SDCARD_CLK"), + PINCTRL_PIN(21, "SDCARD_CLK_FB"), + PINCTRL_PIN(22, "SDCARD_D0"), + PINCTRL_PIN(23, "SDCARD_D1"), + PINCTRL_PIN(24, "SDCARD_D2"), + PINCTRL_PIN(25, "SDCARD_D3"), + PINCTRL_PIN(26, "SDCARD_CD_B"), + PINCTRL_PIN(27, "SDCARD_CMD"), + PINCTRL_PIN(28, "SDCARD_LVL_WP"), + PINCTRL_PIN(29, "EMMC0_STROBE"), + PINCTRL_PIN(30, "SDIO_PWR_DOWN_B"), + PINCTRL_PIN(31, "SMB_ALERTB"), + PINCTRL_PIN(32, "SMB_CLK"), + PINCTRL_PIN(33, "SMB_DATA"), + PINCTRL_PIN(34, "LPC_ILB_SERIRQ"), + PINCTRL_PIN(35, "LPC_CLKOUT0"), + PINCTRL_PIN(36, "LPC_CLKOUT1"), + PINCTRL_PIN(37, "LPC_AD0"), + PINCTRL_PIN(38, "LPC_AD1"), + PINCTRL_PIN(39, "LPC_AD2"), + PINCTRL_PIN(40, "LPC_AD3"), + PINCTRL_PIN(41, "LPC_CLKRUNB"), + PINCTRL_PIN(42, "LPC_FRAMEB"), +}; + +static const unsigned apl_southwest_emmc0_pins[] = { + 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 29, +}; +static const unsigned apl_southwest_sdio_pins[] = { + 14, 15, 16, 17, 18, 19, 30, +}; +static const unsigned apl_southwest_sdcard_pins[] = { + 20, 21, 22, 23, 24, 25, 26, 27, 28, +}; +static const unsigned apl_southwest_i2c7_pins[] = { 32, 33 }; + +static const struct intel_pingroup apl_southwest_groups[] = { + PIN_GROUP("emmc0_grp", apl_southwest_emmc0_pins, 1), + PIN_GROUP("sdio_grp", apl_southwest_sdio_pins, 1), + PIN_GROUP("sdcard_grp", apl_southwest_sdcard_pins, 1), + PIN_GROUP("i2c7_grp", apl_southwest_i2c7_pins, 2), +}; + +static const char * const apl_southwest_emmc0_groups[] = { "emmc0_grp" }; +static const char * const apl_southwest_sdio_groups[] = { "sdio_grp" }; +static const char * const apl_southwest_sdcard_groups[] = { "sdcard_grp" }; +static const char * const apl_southwest_i2c7_groups[] = { "i2c7_grp" }; + +static const struct intel_function apl_southwest_functions[] = { + FUNCTION("emmc0", apl_southwest_emmc0_groups), + FUNCTION("sdio", apl_southwest_sdio_groups), + FUNCTION("sdcard", apl_southwest_sdcard_groups), + FUNCTION("i2c7", apl_southwest_i2c7_groups), +}; + +static const struct intel_community apl_southwest_communities[] = { + BXT_COMMUNITY(0, 42), +}; + +static const struct intel_pinctrl_soc_data apl_southwest_soc_data = { + .uid = "4", + .pins = apl_southwest_pins, + .npins = ARRAY_SIZE(apl_southwest_pins), + .groups = apl_southwest_groups, + .ngroups = ARRAY_SIZE(apl_southwest_groups), + .functions = apl_southwest_functions, + .nfunctions = ARRAY_SIZE(apl_southwest_functions), + .communities = apl_southwest_communities, + .ncommunities = ARRAY_SIZE(apl_southwest_communities), +}; + +static const struct intel_pinctrl_soc_data *apl_pinctrl_soc_data[] = { + &apl_north_soc_data, + &apl_northwest_soc_data, + &apl_west_soc_data, + &apl_southwest_soc_data, + NULL, +}; + +static const struct acpi_device_id bxt_pinctrl_acpi_match[] = { + { "INT3452", (kernel_ulong_t)apl_pinctrl_soc_data }, + { "INT34D1", (kernel_ulong_t)bxt_pinctrl_soc_data }, + { } +}; +MODULE_DEVICE_TABLE(acpi, bxt_pinctrl_acpi_match); + +static int bxt_pinctrl_probe(struct platform_device *pdev) +{ + const struct intel_pinctrl_soc_data *soc_data = NULL; + const struct intel_pinctrl_soc_data **soc_table; + const struct acpi_device_id *id; + struct acpi_device *adev; + int i; + + adev = ACPI_COMPANION(&pdev->dev); + if (!adev) + return -ENODEV; + + id = acpi_match_device(bxt_pinctrl_acpi_match, &pdev->dev); + if (!id) + return -ENODEV; + + soc_table = (const struct intel_pinctrl_soc_data **)id->driver_data; + + for (i = 0; soc_table[i]; i++) { + if (!strcmp(adev->pnp.unique_id, soc_table[i]->uid)) { + soc_data = soc_table[i]; + break; + } + } + + if (!soc_data) + return -ENODEV; + + return intel_pinctrl_probe(pdev, soc_data); +} + +static const struct dev_pm_ops bxt_pinctrl_pm_ops = { + SET_LATE_SYSTEM_SLEEP_PM_OPS(intel_pinctrl_suspend, + intel_pinctrl_resume) +}; + +static struct platform_driver bxt_pinctrl_driver = { + .probe = bxt_pinctrl_probe, + .remove = intel_pinctrl_remove, + .driver = { + .name = "broxton-pinctrl", + .acpi_match_table = bxt_pinctrl_acpi_match, + .pm = &bxt_pinctrl_pm_ops, + }, +}; + +static int __init bxt_pinctrl_init(void) +{ + return platform_driver_register(&bxt_pinctrl_driver); +} +subsys_initcall(bxt_pinctrl_init); + +static void __exit bxt_pinctrl_exit(void) +{ + platform_driver_unregister(&bxt_pinctrl_driver); +} +module_exit(bxt_pinctrl_exit); + +MODULE_AUTHOR("Mika Westerberg "); +MODULE_DESCRIPTION("Intel Broxton SoC pinctrl/GPIO driver"); +MODULE_LICENSE("GPL v2"); -- cgit v0.10.2 From 9d4cc85d290578ec07e37d063d73f0e8707ea3eb Mon Sep 17 00:00:00 2001 From: Jon Hunter Date: Fri, 16 Oct 2015 10:24:01 +0100 Subject: pinctrl: tegra-xusb: Correct lane mux options The description of the XUSB_PADCTL_USB3_PAD_MUX_0 register in the Tegra124 documentation implies that all functions (pcie, usb3 and sata) can be muxed onto to all lanes (pcie lanes 0-4 and sata lane 0). However, it has been confirmed that this is not the case and the mux'ing options much more limited. Unfortunately, the public documentation has not been updated to reflect this and so detail the actual mux'ing options here by function: Function: Lanes: pcie1 x2: pcie3, pcie4 pcie1 x4: pcie1, pcie2, pcie3, pcie4 pcie2 x1 (option1): pcie0 pcie2 x1 (option2): pcie2 usb3 port 0: pcie0 usb3 port 1 (option 1): pcie1 usb3 port 1 (option 2): sata0 sata: sata0 Signed-off-by: Jon Hunter Acked-by: Stephen Warren Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/pinctrl-tegra-xusb.c b/drivers/pinctrl/pinctrl-tegra-xusb.c index 2651d04..84a43e6 100644 --- a/drivers/pinctrl/pinctrl-tegra-xusb.c +++ b/drivers/pinctrl/pinctrl-tegra-xusb.c @@ -760,24 +760,15 @@ static const char * const tegra124_pcie_groups[] = { "pcie-2", "pcie-3", "pcie-4", - "sata-0", }; static const char * const tegra124_usb3_groups[] = { "pcie-0", "pcie-1", - "pcie-2", - "pcie-3", - "pcie-4", "sata-0", }; static const char * const tegra124_sata_groups[] = { - "pcie-0", - "pcie-1", - "pcie-2", - "pcie-3", - "pcie-4", "sata-0", }; -- cgit v0.10.2 From d94b986aa734efea09fbc8f59390ba2e4e00f9d0 Mon Sep 17 00:00:00 2001 From: Julia Lawall Date: Sat, 24 Oct 2015 16:42:35 +0200 Subject: pinctrl: at91: add missing of_node_put for_each_child_of_node performs an of_node_get on each iteration, so a break out of the loop requires an of_node_put. A simplified version of the semantic patch that fixes this problem is as follows (http://coccinelle.lip6.fr): // @@ expression root,e; local idexpression child; @@ for_each_child_of_node(root, child) { ... when != of_node_put(child) when != e = child ( return child; | + of_node_put(child); ? return ...; ) ... } // Signed-off-by: Julia Lawall Acked-by: Ludovic Desroches Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c index b0fde0f..7a828ae 100644 --- a/drivers/pinctrl/pinctrl-at91.c +++ b/drivers/pinctrl/pinctrl-at91.c @@ -1122,8 +1122,10 @@ static int at91_pinctrl_parse_functions(struct device_node *np, func->groups[i] = child->name; grp = &info->groups[grp_index++]; ret = at91_pinctrl_parse_groups(child, grp, info, i++); - if (ret) + if (ret) { + of_node_put(child); return ret; + } } return 0; @@ -1196,6 +1198,7 @@ static int at91_pinctrl_probe_dt(struct platform_device *pdev, ret = at91_pinctrl_parse_functions(child, info, i++); if (ret) { dev_err(&pdev->dev, "failed to parse function\n"); + of_node_put(child); return ret; } } -- cgit v0.10.2 From 13e3008fae342c86dd645b2ec4c669bbb40c5d33 Mon Sep 17 00:00:00 2001 From: Mike Looijmans Date: Thu, 22 Oct 2015 13:30:20 +0200 Subject: pinctrl: zynq: Initialize early MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Supplying pinmux configuration for e.g. gpio pins leads to deferred probes because the pinctrl device is probed much later than gpio. Move the init call to a much earlier stage so it probes before the devices that may need it. Signed-off-by: Mike Looijmans Tested-by: Sören Brinkmann Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/pinctrl-zynq.c b/drivers/pinctrl/pinctrl-zynq.c index 5aafea8..9aefc60 100644 --- a/drivers/pinctrl/pinctrl-zynq.c +++ b/drivers/pinctrl/pinctrl-zynq.c @@ -1230,7 +1230,17 @@ static struct platform_driver zynq_pinctrl_driver = { .remove = zynq_pinctrl_remove, }; -module_platform_driver(zynq_pinctrl_driver); +static int __init zynq_pinctrl_init(void) +{ + return platform_driver_register(&zynq_pinctrl_driver); +} +arch_initcall(zynq_pinctrl_init); + +static void __exit zynq_pinctrl_exit(void) +{ + platform_driver_unregister(&zynq_pinctrl_driver); +} +module_exit(zynq_pinctrl_exit); MODULE_AUTHOR("Sören Brinkmann "); MODULE_DESCRIPTION("Xilinx Zynq pinctrl driver"); -- cgit v0.10.2 From a7c6f30c02326a5acccc602b0d0f08a9853eec3f Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Fri, 30 Oct 2015 15:04:37 +0100 Subject: pinctrl: zynq: fix UTF-8 errors MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Fix up Sören's name in the Zynq driver. I caused this. I fix it. Acked-by: Sören Brinkmann Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/pinctrl-zynq.c b/drivers/pinctrl/pinctrl-zynq.c index 9aefc60..d57b5ec 100644 --- a/drivers/pinctrl/pinctrl-zynq.c +++ b/drivers/pinctrl/pinctrl-zynq.c @@ -3,7 +3,7 @@ * * Copyright (C) 2014 Xilinx * - * Sören Brinkmann + * Sören Brinkmann * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -1242,6 +1242,6 @@ static void __exit zynq_pinctrl_exit(void) } module_exit(zynq_pinctrl_exit); -MODULE_AUTHOR("Sören Brinkmann "); +MODULE_AUTHOR("Sören Brinkmann "); MODULE_DESCRIPTION("Xilinx Zynq pinctrl driver"); MODULE_LICENSE("GPL"); -- cgit v0.10.2 From 241297c2af8bf0459a590c143a1d15b93779fab1 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Fri, 30 Oct 2015 19:28:15 +0900 Subject: pinctrl: uniphier: guard uniphier directory with CONFIG_PINCTRL_UNIPHIER CONFIG_PINCTRL_UNIPHIER is more suitable than CONFIG_ARCH_UNIPHIER to guard the drivers/pinctrl/uniphier directory. The current CONFIG_PINCTRL_UNIPHIER_CORE is a bit long (it would break the indentation in drivers/pinctrl/Makefile), so rename it into CONFIG_PINCTRL_UNIPHIER. Signed-off-by: Masahiro Yamada Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index 8bed0c2..738cb49 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -51,6 +51,6 @@ obj-$(CONFIG_PINCTRL_SAMSUNG) += samsung/ obj-$(CONFIG_PINCTRL_SH_PFC) += sh-pfc/ obj-$(CONFIG_PLAT_SPEAR) += spear/ obj-$(CONFIG_ARCH_SUNXI) += sunxi/ -obj-$(CONFIG_ARCH_UNIPHIER) += uniphier/ +obj-$(CONFIG_PINCTRL_UNIPHIER) += uniphier/ obj-$(CONFIG_ARCH_VT8500) += vt8500/ obj-$(CONFIG_ARCH_MEDIATEK) += mediatek/ diff --git a/drivers/pinctrl/uniphier/Kconfig b/drivers/pinctrl/uniphier/Kconfig index eab23ef..ad90707 100644 --- a/drivers/pinctrl/uniphier/Kconfig +++ b/drivers/pinctrl/uniphier/Kconfig @@ -1,32 +1,32 @@ if ARCH_UNIPHIER -config PINCTRL_UNIPHIER_CORE +config PINCTRL_UNIPHIER bool select PINMUX select GENERIC_PINCONF config PINCTRL_UNIPHIER_PH1_LD4 tristate "UniPhier PH1-LD4 SoC pinctrl driver" - select PINCTRL_UNIPHIER_CORE + select PINCTRL_UNIPHIER config PINCTRL_UNIPHIER_PH1_PRO4 tristate "UniPhier PH1-Pro4 SoC pinctrl driver" - select PINCTRL_UNIPHIER_CORE + select PINCTRL_UNIPHIER config PINCTRL_UNIPHIER_PH1_SLD8 tristate "UniPhier PH1-sLD8 SoC pinctrl driver" - select PINCTRL_UNIPHIER_CORE + select PINCTRL_UNIPHIER config PINCTRL_UNIPHIER_PH1_PRO5 tristate "UniPhier PH1-Pro5 SoC pinctrl driver" - select PINCTRL_UNIPHIER_CORE + select PINCTRL_UNIPHIER config PINCTRL_UNIPHIER_PROXSTREAM2 tristate "UniPhier ProXstream2 SoC pinctrl driver" - select PINCTRL_UNIPHIER_CORE + select PINCTRL_UNIPHIER config PINCTRL_UNIPHIER_PH1_LD6B tristate "UniPhier PH1-LD6b SoC pinctrl driver" - select PINCTRL_UNIPHIER_CORE + select PINCTRL_UNIPHIER endif diff --git a/drivers/pinctrl/uniphier/Makefile b/drivers/pinctrl/uniphier/Makefile index e215b10..e7ce967 100644 --- a/drivers/pinctrl/uniphier/Makefile +++ b/drivers/pinctrl/uniphier/Makefile @@ -1,4 +1,4 @@ -obj-$(CONFIG_PINCTRL_UNIPHIER_CORE) += pinctrl-uniphier-core.o +obj-y += pinctrl-uniphier-core.o obj-$(CONFIG_PINCTRL_UNIPHIER_PH1_LD4) += pinctrl-ph1-ld4.o obj-$(CONFIG_PINCTRL_UNIPHIER_PH1_PRO4) += pinctrl-ph1-pro4.o -- cgit v0.10.2 From d99c8053fc2473115f506782822cb7c33c687513 Mon Sep 17 00:00:00 2001 From: Laurent Meunier Date: Fri, 30 Oct 2015 15:15:51 +0100 Subject: pinctrl: pinconf: remove needless loop This removes a needless loop which was caught in pinconf.c. Suggested-by: Andy Shevchenko Signed-off-by: Laurent Meunier Reviewed-by: Andy Shevchenko Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/pinconf.c b/drivers/pinctrl/pinconf.c index 29a7bb1..4dd7722 100644 --- a/drivers/pinctrl/pinconf.c +++ b/drivers/pinctrl/pinconf.c @@ -411,7 +411,7 @@ static int pinconf_dbg_config_print(struct seq_file *s, void *d) const struct pinctrl_map *found = NULL; struct pinctrl_dev *pctldev; struct dbg_cfg *dbg = &pinconf_dbg_conf; - int i, j; + int i; mutex_lock(&pinctrl_maps_mutex); @@ -424,13 +424,10 @@ static int pinconf_dbg_config_print(struct seq_file *s, void *d) if (strcmp(map->name, dbg->state_name)) continue; - for (j = 0; j < map->data.configs.num_configs; j++) { - if (!strcmp(map->data.configs.group_or_pin, - dbg->pin_name)) { - /* We found the right pin / state */ - found = map; - break; - } + if (!strcmp(map->data.configs.group_or_pin, dbg->pin_name)) { + /* We found the right pin */ + found = map; + break; } } -- cgit v0.10.2