From 989ff3fdf939b15f0cb91406746da0ded0c06ef0 Mon Sep 17 00:00:00 2001 From: Kyungmin Park Date: Fri, 9 May 2014 06:19:18 +0900 Subject: ARM: EXYNOS: fix the secondary CPU boot of exynos4212 This patch fixes the offset of CPU boot address and changes the parameter of smc call for SMC_CMD_CPU1BOOT command on exynos4212. Signed-off-by: Kyungmin Park Signed-off-by: Chanwoo Choi Reviewed-by: Tomasz Figa Signed-off-by: Kukjin Kim diff --git a/arch/arm/mach-exynos/firmware.c b/arch/arm/mach-exynos/firmware.c index 932129e..aa01c42 100644 --- a/arch/arm/mach-exynos/firmware.c +++ b/arch/arm/mach-exynos/firmware.c @@ -18,6 +18,8 @@ #include +#include + #include "smc.h" static int exynos_do_idle(void) @@ -28,13 +30,24 @@ static int exynos_do_idle(void) static int exynos_cpu_boot(int cpu) { + /* + * The second parameter of SMC_CMD_CPU1BOOT command means CPU id. + * But, Exynos4212 has only one secondary CPU so second parameter + * isn't used for informing secure firmware about CPU id. + */ + if (soc_is_exynos4212()) + cpu = 0; + exynos_smc(SMC_CMD_CPU1BOOT, cpu, 0, 0); return 0; } static int exynos_set_cpu_boot_addr(int cpu, unsigned long boot_addr) { - void __iomem *boot_reg = S5P_VA_SYSRAM_NS + 0x1c + 4*cpu; + void __iomem *boot_reg = S5P_VA_SYSRAM_NS + 0x1c; + + if (!soc_is_exynos4212()) + boot_reg += 4*cpu; __raw_writel(boot_addr, boot_reg); return 0; -- cgit v0.10.2 From e6015c1f8a9032c2aecb78d23edf49582563bd47 Mon Sep 17 00:00:00 2001 From: Seungwon Jeon Date: Fri, 9 May 2014 07:02:33 +0900 Subject: ARM: dts: disable MDMA1 node for exynos5420 This change places MDMA1 in disabled node for Exynos5420. If MDMA1 region is configured with secure mode, it makes the boot failure with the following on smdk5420 board. ("Unhandled fault: imprecise external abort (0x1406) at 0x00000000") Thus, arndale-octa board don't need to do the same thing anymore. Signed-off-by: Seungwon Jeon Tested-by: Javi Merino Signed-off-by: Kukjin Kim diff --git a/arch/arm/boot/dts/exynos5420-arndale-octa.dts b/arch/arm/boot/dts/exynos5420-arndale-octa.dts index 80a3bf4..896a2a6 100644 --- a/arch/arm/boot/dts/exynos5420-arndale-octa.dts +++ b/arch/arm/boot/dts/exynos5420-arndale-octa.dts @@ -364,16 +364,4 @@ gpio-key,wakeup; }; }; - - amba { - mdma1: mdma@11C10000 { - /* - * MDMA1 can support both secure and non-secure - * AXI transactions. When this is enabled in the kernel - * for boards that run in secure mode, we are getting - * imprecise external aborts causing the kernel to oops. - */ - status = "disabled"; - }; - }; }; diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index c3a9a66..97cbcdd 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -336,6 +336,13 @@ #dma-cells = <1>; #dma-channels = <8>; #dma-requests = <1>; + /* + * MDMA1 can support both secure and non-secure + * AXI transactions. When this is enabled in the kernel + * for boards that run in secure mode, we are getting + * imprecise external aborts causing the kernel to oops. + */ + status = "disabled"; }; }; -- cgit v0.10.2 From a8f1d0889e902cbac8c18a40ec927a109e48a52e Mon Sep 17 00:00:00 2001 From: Sachin Kamat Date: Thu, 15 May 2014 04:14:16 +0900 Subject: ARM: exynos_defconfig: enable HS-I2C to fix for mmc partition mount High speed I2C is used on Exynos5 based SoCs. Enable it. The MMC partition for Root filesystem cannot be mounted without this enabling HS-I2C and regulators on many boards are connected HS-I2C bus so the regulators don't come by default without this. Actually, we are not able to get arndale-octa board to boot and mount an MMC partition without this change. Signed-off-by: Sachin Kamat Tested-by: Javi Merino [kgene.kim@samsung.com: modified description] Signed-off-by: Kukjin Kim diff --git a/arch/arm/configs/exynos_defconfig b/arch/arm/configs/exynos_defconfig index 4ce7b70..e07a227 100644 --- a/arch/arm/configs/exynos_defconfig +++ b/arch/arm/configs/exynos_defconfig @@ -65,6 +65,7 @@ CONFIG_TCG_TIS_I2C_INFINEON=y CONFIG_I2C=y CONFIG_I2C_MUX=y CONFIG_I2C_ARB_GPIO_CHALLENGE=y +CONFIG_I2C_EXYNOS5=y CONFIG_I2C_S3C2410=y CONFIG_DEBUG_GPIO=y # CONFIG_HWMON is not set -- cgit v0.10.2 From c5b817e44bc97a3d119822459f69ea7d1dc528ee Mon Sep 17 00:00:00 2001 From: Tushar Behera Date: Thu, 15 May 2014 04:16:03 +0900 Subject: ARM: dts: Remove mau_pd node for exynos5420 MAU powerdomain provides clocks for Audio sub-system block. This block comprises of the I2S audio controller, audio DMA blocks and Audio sub-system clock registers. Right now, there is no way to hook up power-domains with clock providers. During late boot when this power-domain gets disabled, we get following external abort. Unhandled fault: imprecise external abort (0x1406) at 0x00000000 Kernel panic - not syncing: Attempted to kill init! exitcode=0x00000007 Signed-off-by: Tushar Behera Tested-by: Doug Anderson Signed-off-by: Kukjin Kim diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index 97cbcdd..430ba1f 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -219,11 +219,6 @@ reg = <0x100440C0 0x20>; }; - mau_pd: power-domain@100440E0 { - compatible = "samsung,exynos4210-pd"; - reg = <0x100440E0 0x20>; - }; - g2d_pd: power-domain@10044100 { compatible = "samsung,exynos4210-pd"; reg = <0x10044100 0x20>; -- cgit v0.10.2 From 702b691e4a711e699cf3cccba879c1d945665c0d Mon Sep 17 00:00:00 2001 From: Arun Kumar K Date: Thu, 15 May 2014 04:17:17 +0900 Subject: ARM: dts: Remove g2d_pd node for exynos5420 G2D power domain also controls the CMU block of G2D. Since clock registers can be accessed anytime for viewing clk_summary, it can cause a system crash if g2d power domain is disabled. Signed-off-by: Arun Kumar K Signed-off-by: Kukjin Kim diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index 430ba1f..418f250 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -219,11 +219,6 @@ reg = <0x100440C0 0x20>; }; - g2d_pd: power-domain@10044100 { - compatible = "samsung,exynos4210-pd"; - reg = <0x10044100 0x20>; - }; - msc_pd: power-domain@10044120 { compatible = "samsung,exynos4210-pd"; reg = <0x10044120 0x20>; @@ -732,6 +727,5 @@ interrupts = <0 112 0>; clocks = <&clock 471>; clock-names = "secss"; - samsung,power-domain = <&g2d_pd>; }; }; -- cgit v0.10.2 From 75ad2ab28f0f184a7ba7f816b62be04c3c0ba80a Mon Sep 17 00:00:00 2001 From: Leela Krishna Amudala Date: Fri, 9 May 2014 22:51:04 +0900 Subject: ARM: EXYNOS: use v7_exit_coherency_flush macro for cache disabling A common macro v7_exit_coherency_flush available which does the below tasks in the seqeunce. -clearing C bit -clearing L1 cache -exit SMP -instruction and data synchronization So removing the local functions which does the same thing and use the macro instead. Signed-off-by: Leela Krishna Amudala Acked-by: Nicolas Pitre [cw00.choi@samsung.com: tested on exynos3250 based board] Tested-by: Chanwoo Choi Signed-off-by: Kukjin Kim diff --git a/arch/arm/mach-exynos/hotplug.c b/arch/arm/mach-exynos/hotplug.c index 5eead53..9ca692d 100644 --- a/arch/arm/mach-exynos/hotplug.c +++ b/arch/arm/mach-exynos/hotplug.c @@ -24,56 +24,6 @@ #include "common.h" #include "regs-pmu.h" -static inline void cpu_enter_lowpower_a9(void) -{ - unsigned int v; - - asm volatile( - " mcr p15, 0, %1, c7, c5, 0\n" - " mcr p15, 0, %1, c7, c10, 4\n" - /* - * Turn off coherency - */ - " mrc p15, 0, %0, c1, c0, 1\n" - " bic %0, %0, %3\n" - " mcr p15, 0, %0, c1, c0, 1\n" - " mrc p15, 0, %0, c1, c0, 0\n" - " bic %0, %0, %2\n" - " mcr p15, 0, %0, c1, c0, 0\n" - : "=&r" (v) - : "r" (0), "Ir" (CR_C), "Ir" (0x40) - : "cc"); -} - -static inline void cpu_enter_lowpower_a15(void) -{ - unsigned int v; - - asm volatile( - " mrc p15, 0, %0, c1, c0, 0\n" - " bic %0, %0, %1\n" - " mcr p15, 0, %0, c1, c0, 0\n" - : "=&r" (v) - : "Ir" (CR_C) - : "cc"); - - flush_cache_louis(); - - asm volatile( - /* - * Turn off coherency - */ - " mrc p15, 0, %0, c1, c0, 1\n" - " bic %0, %0, %1\n" - " mcr p15, 0, %0, c1, c0, 1\n" - : "=&r" (v) - : "Ir" (0x40) - : "cc"); - - isb(); - dsb(); -} - static inline void cpu_leave_lowpower(void) { unsigned int v; @@ -132,19 +82,8 @@ static inline void platform_do_lowpower(unsigned int cpu, int *spurious) void __ref exynos_cpu_die(unsigned int cpu) { int spurious = 0; - int primary_part = 0; - /* - * we're ready for shutdown now, so do it. - * Exynos4 is A9 based while Exynos5 is A15; check the CPU part - * number by reading the Main ID register and then perform the - * appropriate sequence for entering low power. - */ - asm("mrc p15, 0, %0, c0, c0, 0" : "=r"(primary_part) : : "cc"); - if ((primary_part & 0xfff0) == 0xc0f0) - cpu_enter_lowpower_a15(); - else - cpu_enter_lowpower_a9(); + v7_exit_coherency_flush(louis); platform_do_lowpower(cpu, &spurious); -- cgit v0.10.2 From fd5770658f3f2ad9c9c9d7afd11a77d9980429d6 Mon Sep 17 00:00:00 2001 From: Sachin Kamat Date: Tue, 13 May 2014 07:11:50 +0900 Subject: ARM: EXYNOS: Remove duplicate lines in Makefile Group all files compiled under common config option together. Signed-off-by: Sachin Kamat Reviewed-by: Tomasz Figa Signed-off-by: Kukjin Kim diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile index a656dbe..f6dcc25 100644 --- a/arch/arm/mach-exynos/Makefile +++ b/arch/arm/mach-exynos/Makefile @@ -12,20 +12,15 @@ obj- := # Core -obj-$(CONFIG_ARCH_EXYNOS) += exynos.o +obj-$(CONFIG_ARCH_EXYNOS) += exynos.o pmu.o exynos-smc.o firmware.o obj-$(CONFIG_PM_SLEEP) += pm.o sleep.o obj-$(CONFIG_PM_GENERIC_DOMAINS) += pm_domains.o obj-$(CONFIG_CPU_IDLE) += cpuidle.o -obj-$(CONFIG_ARCH_EXYNOS) += pmu.o - obj-$(CONFIG_SMP) += platsmp.o headsmp.o obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o -obj-$(CONFIG_ARCH_EXYNOS) += exynos-smc.o -obj-$(CONFIG_ARCH_EXYNOS) += firmware.o - plus_sec := $(call as-instr,.arch_extension sec,+sec) AFLAGS_exynos-smc.o :=-Wa,-march=armv7-a$(plus_sec) -- cgit v0.10.2 From ced2d24584da35c5cd45faecf3c6db7abb7e16c9 Mon Sep 17 00:00:00 2001 From: Sachin Kamat Date: Tue, 13 May 2014 07:11:53 +0900 Subject: ARM: EXYNOS: Remove exynos_subsys registration 'exynos_subsys' has no users. Remove this code. Signed-off-by: Sachin Kamat Reviewed-by: Tomasz Figa Signed-off-by: Kukjin Kim diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c index b32a907..eb1a431 100644 --- a/arch/arm/mach-exynos/exynos.c +++ b/arch/arm/mach-exynos/exynos.c @@ -308,17 +308,6 @@ void __init exynos_init_io(void) exynos_map_io(); } -struct bus_type exynos_subsys = { - .name = "exynos-core", - .dev_name = "exynos-core", -}; - -static int __init exynos_core_init(void) -{ - return subsys_system_register(&exynos_subsys, NULL); -} -core_initcall(exynos_core_init); - static int __init exynos4_l2x0_cache_init(void) { int ret; diff --git a/arch/arm/plat-samsung/include/plat/cpu.h b/arch/arm/plat-samsung/include/plat/cpu.h index 5992b8d..930b4be 100644 --- a/arch/arm/plat-samsung/include/plat/cpu.h +++ b/arch/arm/plat-samsung/include/plat/cpu.h @@ -239,7 +239,6 @@ extern struct bus_type s3c2443_subsys; extern struct bus_type s3c6410_subsys; extern struct bus_type s5p64x0_subsys; extern struct bus_type s5pv210_subsys; -extern struct bus_type exynos_subsys; extern void (*s5pc1xx_idle)(void); -- cgit v0.10.2 From 7cb2ded128ab34d8172f25e6da417d732d7e3520 Mon Sep 17 00:00:00 2001 From: Sachin Kamat Date: Tue, 13 May 2014 07:11:57 +0900 Subject: ARM: EXYNOS: Migrate Exynos specific macros from plat to mach Move Exynos specific macros to mach-exynos from plat-samsung to avoid unnecessary dependency on plat based header files. Signed-off-by: Sachin Kamat Reviewed-by: Tomasz Figa Signed-off-by: Kukjin Kim diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h index 9ef3f83..c1a2f22 100644 --- a/arch/arm/mach-exynos/common.h +++ b/arch/arm/mach-exynos/common.h @@ -15,6 +15,75 @@ #include #include +#define EXYNOS4210_CPU_ID 0x43210000 +#define EXYNOS4212_CPU_ID 0x43220000 +#define EXYNOS4412_CPU_ID 0xE4412200 +#define EXYNOS4_CPU_MASK 0xFFFE0000 + +#define EXYNOS5250_SOC_ID 0x43520000 +#define EXYNOS5420_SOC_ID 0xE5420000 +#define EXYNOS5440_SOC_ID 0xE5440000 +#define EXYNOS5_SOC_MASK 0xFFFFF000 + +extern unsigned long samsung_cpu_id; + +#define IS_SAMSUNG_CPU(name, id, mask) \ +static inline int is_samsung_##name(void) \ +{ \ + return ((samsung_cpu_id & mask) == (id & mask)); \ +} + +IS_SAMSUNG_CPU(exynos4210, EXYNOS4210_CPU_ID, EXYNOS4_CPU_MASK) +IS_SAMSUNG_CPU(exynos4212, EXYNOS4212_CPU_ID, EXYNOS4_CPU_MASK) +IS_SAMSUNG_CPU(exynos4412, EXYNOS4412_CPU_ID, EXYNOS4_CPU_MASK) +IS_SAMSUNG_CPU(exynos5250, EXYNOS5250_SOC_ID, EXYNOS5_SOC_MASK) +IS_SAMSUNG_CPU(exynos5420, EXYNOS5420_SOC_ID, EXYNOS5_SOC_MASK) +IS_SAMSUNG_CPU(exynos5440, EXYNOS5440_SOC_ID, EXYNOS5_SOC_MASK) + +#if defined(CONFIG_CPU_EXYNOS4210) +# define soc_is_exynos4210() is_samsung_exynos4210() +#else +# define soc_is_exynos4210() 0 +#endif + +#if defined(CONFIG_SOC_EXYNOS4212) +# define soc_is_exynos4212() is_samsung_exynos4212() +#else +# define soc_is_exynos4212() 0 +#endif + +#if defined(CONFIG_SOC_EXYNOS4412) +# define soc_is_exynos4412() is_samsung_exynos4412() +#else +# define soc_is_exynos4412() 0 +#endif + +#define EXYNOS4210_REV_0 (0x0) +#define EXYNOS4210_REV_1_0 (0x10) +#define EXYNOS4210_REV_1_1 (0x11) + +#if defined(CONFIG_SOC_EXYNOS5250) +# define soc_is_exynos5250() is_samsung_exynos5250() +#else +# define soc_is_exynos5250() 0 +#endif + +#if defined(CONFIG_SOC_EXYNOS5420) +# define soc_is_exynos5420() is_samsung_exynos5420() +#else +# define soc_is_exynos5420() 0 +#endif + +#if defined(CONFIG_SOC_EXYNOS5440) +# define soc_is_exynos5440() is_samsung_exynos5440() +#else +# define soc_is_exynos5440() 0 +#endif + +#define soc_is_exynos4() (soc_is_exynos4210() || soc_is_exynos4212() || \ + soc_is_exynos4412()) +#define soc_is_exynos5() (soc_is_exynos5250() || soc_is_exynos5420()) + void mct_init(void __iomem *base, int irq_g0, int irq_l0, int irq_l1); struct map_desc; @@ -63,4 +132,7 @@ struct exynos_pmu_conf { extern void exynos_sys_powerdown_conf(enum sys_powerdown mode); +extern void s5p_init_cpu(void __iomem *cpuid_addr); +extern unsigned int samsung_rev(void); + #endif /* __ARCH_ARM_MACH_EXYNOS_COMMON_H */ diff --git a/arch/arm/plat-samsung/include/plat/cpu.h b/arch/arm/plat-samsung/include/plat/cpu.h index 930b4be..5a237db 100644 --- a/arch/arm/plat-samsung/include/plat/cpu.h +++ b/arch/arm/plat-samsung/include/plat/cpu.h @@ -43,16 +43,6 @@ extern unsigned long samsung_cpu_id; #define S5PV210_CPU_ID 0x43110000 #define S5PV210_CPU_MASK 0xFFFFF000 -#define EXYNOS4210_CPU_ID 0x43210000 -#define EXYNOS4212_CPU_ID 0x43220000 -#define EXYNOS4412_CPU_ID 0xE4412200 -#define EXYNOS4_CPU_MASK 0xFFFE0000 - -#define EXYNOS5250_SOC_ID 0x43520000 -#define EXYNOS5420_SOC_ID 0xE5420000 -#define EXYNOS5440_SOC_ID 0xE5440000 -#define EXYNOS5_SOC_MASK 0xFFFFF000 - #define IS_SAMSUNG_CPU(name, id, mask) \ static inline int is_samsung_##name(void) \ { \ @@ -68,12 +58,6 @@ IS_SAMSUNG_CPU(s5p6440, S5P6440_CPU_ID, S5P64XX_CPU_MASK) IS_SAMSUNG_CPU(s5p6450, S5P6450_CPU_ID, S5P64XX_CPU_MASK) IS_SAMSUNG_CPU(s5pc100, S5PC100_CPU_ID, S5PC100_CPU_MASK) IS_SAMSUNG_CPU(s5pv210, S5PV210_CPU_ID, S5PV210_CPU_MASK) -IS_SAMSUNG_CPU(exynos4210, EXYNOS4210_CPU_ID, EXYNOS4_CPU_MASK) -IS_SAMSUNG_CPU(exynos4212, EXYNOS4212_CPU_ID, EXYNOS4_CPU_MASK) -IS_SAMSUNG_CPU(exynos4412, EXYNOS4412_CPU_ID, EXYNOS4_CPU_MASK) -IS_SAMSUNG_CPU(exynos5250, EXYNOS5250_SOC_ID, EXYNOS5_SOC_MASK) -IS_SAMSUNG_CPU(exynos5420, EXYNOS5420_SOC_ID, EXYNOS5_SOC_MASK) -IS_SAMSUNG_CPU(exynos5440, EXYNOS5440_SOC_ID, EXYNOS5_SOC_MASK) #if defined(CONFIG_CPU_S3C2410) || defined(CONFIG_CPU_S3C2412) || \ defined(CONFIG_CPU_S3C2416) || defined(CONFIG_CPU_S3C2440) || \ @@ -126,50 +110,6 @@ IS_SAMSUNG_CPU(exynos5440, EXYNOS5440_SOC_ID, EXYNOS5_SOC_MASK) # define soc_is_s5pv210() 0 #endif -#if defined(CONFIG_CPU_EXYNOS4210) -# define soc_is_exynos4210() is_samsung_exynos4210() -#else -# define soc_is_exynos4210() 0 -#endif - -#if defined(CONFIG_SOC_EXYNOS4212) -# define soc_is_exynos4212() is_samsung_exynos4212() -#else -# define soc_is_exynos4212() 0 -#endif - -#if defined(CONFIG_SOC_EXYNOS4412) -# define soc_is_exynos4412() is_samsung_exynos4412() -#else -# define soc_is_exynos4412() 0 -#endif - -#define EXYNOS4210_REV_0 (0x0) -#define EXYNOS4210_REV_1_0 (0x10) -#define EXYNOS4210_REV_1_1 (0x11) - -#if defined(CONFIG_SOC_EXYNOS5250) -# define soc_is_exynos5250() is_samsung_exynos5250() -#else -# define soc_is_exynos5250() 0 -#endif - -#if defined(CONFIG_SOC_EXYNOS5420) -# define soc_is_exynos5420() is_samsung_exynos5420() -#else -# define soc_is_exynos5420() 0 -#endif - -#if defined(CONFIG_SOC_EXYNOS5440) -# define soc_is_exynos5440() is_samsung_exynos5440() -#else -# define soc_is_exynos5440() 0 -#endif - -#define soc_is_exynos4() (soc_is_exynos4210() || soc_is_exynos4212() || \ - soc_is_exynos4412()) -#define soc_is_exynos5() (soc_is_exynos5250() || soc_is_exynos5420()) - #define IODESC_ENT(x) { (unsigned long)S3C24XX_VA_##x, __phys_to_pfn(S3C24XX_PA_##x), S3C24XX_SZ_##x, MT_DEVICE } #ifndef KHZ -- cgit v0.10.2 From 4b245edc99f056f05a61cb2b1fd4604875cf8eab Mon Sep 17 00:00:00 2001 From: Sachin Kamat Date: Tue, 13 May 2014 07:12:00 +0900 Subject: ARM: EXYNOS: Remove unnecessary inclusion of cpu.h Exynos specific macros and declarations have been moved to mach-exynos. Inclusion of plat/cpu.h is no more necessary. Signed-off-by: Sachin Kamat Reviewed-by: Tomasz Figa Signed-off-by: Kukjin Kim diff --git a/arch/arm/mach-exynos/cpuidle.c b/arch/arm/mach-exynos/cpuidle.c index c57cae0..3dd385e 100644 --- a/arch/arm/mach-exynos/cpuidle.c +++ b/arch/arm/mach-exynos/cpuidle.c @@ -24,7 +24,6 @@ #include #include -#include #include #include diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c index eb1a431..59aab75 100644 --- a/arch/arm/mach-exynos/exynos.c +++ b/arch/arm/mach-exynos/exynos.c @@ -26,8 +26,6 @@ #include #include -#include - #include "common.h" #include "mfc.h" #include "regs-pmu.h" diff --git a/arch/arm/mach-exynos/firmware.c b/arch/arm/mach-exynos/firmware.c index aa01c42..f6cb510 100644 --- a/arch/arm/mach-exynos/firmware.c +++ b/arch/arm/mach-exynos/firmware.c @@ -18,8 +18,7 @@ #include -#include - +#include "common.h" #include "smc.h" static int exynos_do_idle(void) diff --git a/arch/arm/mach-exynos/hotplug.c b/arch/arm/mach-exynos/hotplug.c index 9ca692d..3cab3f5 100644 --- a/arch/arm/mach-exynos/hotplug.c +++ b/arch/arm/mach-exynos/hotplug.c @@ -19,8 +19,6 @@ #include #include -#include - #include "common.h" #include "regs-pmu.h" diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c index 03e5e9f..c28cdb1 100644 --- a/arch/arm/mach-exynos/platsmp.c +++ b/arch/arm/mach-exynos/platsmp.c @@ -26,8 +26,6 @@ #include #include -#include - #include "common.h" #include "regs-pmu.h" diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c index 15af0ce..ca672e2 100644 --- a/arch/arm/mach-exynos/pm.c +++ b/arch/arm/mach-exynos/pm.c @@ -26,7 +26,6 @@ #include #include -#include #include #include #include diff --git a/arch/arm/mach-exynos/pmu.c b/arch/arm/mach-exynos/pmu.c index 05c7ce1..fb0deda 100644 --- a/arch/arm/mach-exynos/pmu.c +++ b/arch/arm/mach-exynos/pmu.c @@ -13,8 +13,6 @@ #include #include -#include - #include "common.h" #include "regs-pmu.h" -- cgit v0.10.2 From 46f34abc750c66fdb4daa9a8bc9d7f955e95eb9c Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Fri, 16 May 2014 06:59:18 +0900 Subject: ARM: compressed/head.S: remove s3c24xx special case addruart from the generic debug macro is doing exactly the same using the common lowlevel uart definition, so there is no cause for this special casing for s3c24xx. Signed-off-by: Heiko Stuebner Signed-off-by: Kukjin Kim diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S index 066b034..3a8b32d 100644 --- a/arch/arm/boot/compressed/head.S +++ b/arch/arm/boot/compressed/head.S @@ -60,11 +60,6 @@ add \rb, \rb, #0x00010000 @ Ser1 #endif .endm -#elif defined(CONFIG_ARCH_S3C24XX) - .macro loadsp, rb, tmp - mov \rb, #0x50000000 - add \rb, \rb, #0x4000 * CONFIG_S3C_LOWLEVEL_UART_PORT - .endm #else .macro loadsp, rb, tmp addruart \rb, \tmp -- cgit v0.10.2 From daf67dfc5989495c887cfdbe76be72b7db724e60 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Fri, 16 May 2014 06:59:18 +0900 Subject: ARM: S3C24XX: trim down debug uart handling Using the lowlevel debug uart is a corner case - even more so in a multiplatform environment. So it seems reasonable to simply let the developer set the appropriate uart type for the debugged SoC. Signed-off-by: Heiko Stuebner Signed-off-by: Kukjin Kim diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug index eab8ecb..8c72e10 100644 --- a/arch/arm/Kconfig.debug +++ b/arch/arm/Kconfig.debug @@ -670,6 +670,33 @@ choice The uncompressor code port configuration is now handled by CONFIG_S3C_LOWLEVEL_UART_PORT. + config DEBUG_S3C2410_UART0 + depends on ARCH_S3C24XX + select DEBUG_S3C2410_UART + bool "Use S3C2410/S3C2412 UART 0 for low-level debug" + help + Say Y here if you want the debug print routines to direct + their output to UART 0. The port must have been initialised + by the boot-loader before use. + + config DEBUG_S3C2410_UART1 + depends on ARCH_S3C24XX + select DEBUG_S3C2410_UART + bool "Use S3C2410/S3C2412 UART 1 for low-level debug" + help + Say Y here if you want the debug print routines to direct + their output to UART 1. The port must have been initialised + by the boot-loader before use. + + config DEBUG_S3C2410_UART2 + depends on ARCH_S3C24XX + select DEBUG_S3C2410_UART + bool "Use S3C2410/S3C2412 UART 2 for low-level debug" + help + Say Y here if you want the debug print routines to direct + their output to UART 2. The port must have been initialised + by the boot-loader before use. + config DEBUG_SOCFPGA_UART depends on ARCH_SOCFPGA bool "Use SOCFPGA UART for low-level debug" @@ -921,6 +948,9 @@ endchoice config DEBUG_EXYNOS_UART bool +config DEBUG_S3C2410_UART + bool + config DEBUG_OMAP2PLUS_UART bool depends on ARCH_OMAP2PLUS diff --git a/arch/arm/mach-s3c24xx/Kconfig b/arch/arm/mach-s3c24xx/Kconfig index 22d149b..45a7026 100644 --- a/arch/arm/mach-s3c24xx/Kconfig +++ b/arch/arm/mach-s3c24xx/Kconfig @@ -39,7 +39,6 @@ config CPU_S3C2410 default y select COMMON_CLK select CPU_ARM920T - select CPU_LLSERIAL_S3C2410 select S3C2410_COMMON_CLK select S3C2410_DMA if S3C24XX_DMA select ARM_S3C2410_CPUFREQ if ARM_S3C24XX_CPUFREQ @@ -53,7 +52,6 @@ config CPU_S3C2412 bool "SAMSUNG S3C2412" select COMMON_CLK select CPU_ARM926T - select CPU_LLSERIAL_S3C2440 select S3C2412_COMMON_CLK select S3C2412_DMA if S3C24XX_DMA select S3C2412_PM if PM @@ -64,7 +62,6 @@ config CPU_S3C2416 bool "SAMSUNG S3C2416/S3C2450" select COMMON_CLK select CPU_ARM926T - select CPU_LLSERIAL_S3C2440 select S3C2416_PM if PM select S3C2443_COMMON_CLK select S3C2443_DMA if S3C24XX_DMA @@ -75,7 +72,6 @@ config CPU_S3C2440 bool "SAMSUNG S3C2440" select COMMON_CLK select CPU_ARM920T - select CPU_LLSERIAL_S3C2440 select S3C2410_COMMON_CLK select S3C2410_PM if PM select S3C2440_DMA if S3C24XX_DMA @@ -86,7 +82,6 @@ config CPU_S3C2442 bool "SAMSUNG S3C2442" select COMMON_CLK select CPU_ARM920T - select CPU_LLSERIAL_S3C2440 select S3C2410_COMMON_CLK select S3C2410_DMA if S3C24XX_DMA select S3C2410_PM if PM @@ -102,7 +97,6 @@ config CPU_S3C2443 bool "SAMSUNG S3C2443" select COMMON_CLK select CPU_ARM920T - select CPU_LLSERIAL_S3C2440 select S3C2443_COMMON_CLK select S3C2443_DMA if S3C24XX_DMA help @@ -164,28 +158,6 @@ config S3C2410_PM help Power Management code common to S3C2410 and better -# low-level serial option nodes - -config CPU_LLSERIAL_S3C2410_ONLY - bool - default y if CPU_LLSERIAL_S3C2410 && !CPU_LLSERIAL_S3C2440 - -config CPU_LLSERIAL_S3C2440_ONLY - bool - default y if CPU_LLSERIAL_S3C2440 && !CPU_LLSERIAL_S3C2410 - -config CPU_LLSERIAL_S3C2410 - bool - help - Selected if there is an S3C2410 (or register compatible) serial - low-level implementation needed - -config CPU_LLSERIAL_S3C2440 - bool - help - Selected if there is an S3C2440 (or register compatible) serial - low-level implementation needed - config S3C24XX_PLL bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)" depends on ARM_S3C24XX_CPUFREQ diff --git a/arch/arm/mach-s3c24xx/include/mach/debug-macro.S b/arch/arm/mach-s3c24xx/include/mach/debug-macro.S index 2f39737..fbe3e71 100644 --- a/arch/arm/mach-s3c24xx/include/mach/debug-macro.S +++ b/arch/arm/mach-s3c24xx/include/mach/debug-macro.S @@ -13,11 +13,9 @@ */ #include -#include #include #define S3C2410_UART1_OFF (0x4000) -#define SHIFT_2440TXF (14-9) .macro addruart, rp, rv, tmp ldr \rp, = S3C24XX_PA_UART @@ -28,56 +26,11 @@ #endif .endm - .macro fifo_full_s3c24xx rd, rx - @ check for arm920 vs arm926. currently assume all arm926 - @ devices have an 64 byte FIFO identical to the s3c2440 - mrc p15, 0, \rd, c0, c0 - and \rd, \rd, #0xff0 - teq \rd, #0x260 - beq 1004f - mrc p15, 0, \rd, c1, c0 - tst \rd, #1 - addeq \rd, \rx, #(S3C24XX_PA_GPIO - S3C24XX_PA_UART) - addne \rd, \rx, #(S3C24XX_VA_GPIO - S3C24XX_VA_UART) - bic \rd, \rd, #0xff000 - ldr \rd, [\rd, # S3C2410_GSTATUS1 - S3C2410_GPIOREG(0)] - and \rd, \rd, #0x00ff0000 - teq \rd, #0x00440000 @ is it 2440? -1004: - ldr \rd, [\rx, # S3C2410_UFSTAT] - moveq \rd, \rd, lsr #SHIFT_2440TXF - tst \rd, #S3C2410_UFSTAT_TXFULL - .endm - .macro fifo_full_s3c2410 rd, rx ldr \rd, [\rx, # S3C2410_UFSTAT] tst \rd, #S3C2410_UFSTAT_TXFULL .endm -/* fifo level reading */ - - .macro fifo_level_s3c24xx rd, rx - @ check for arm920 vs arm926. currently assume all arm926 - @ devices have an 64 byte FIFO identical to the s3c2440 - mrc p15, 0, \rd, c0, c0 - and \rd, \rd, #0xff0 - teq \rd, #0x260 - beq 10000f - mrc p15, 0, \rd, c1, c0 - tst \rd, #1 - addeq \rd, \rx, #(S3C24XX_PA_GPIO - S3C24XX_PA_UART) - addne \rd, \rx, #(S3C24XX_VA_GPIO - S3C24XX_VA_UART) - bic \rd, \rd, #0xff000 - ldr \rd, [\rd, # S3C2410_GSTATUS1 - S3C2410_GPIOREG(0)] - and \rd, \rd, #0x00ff0000 - teq \rd, #0x00440000 @ is it 2440? - -10000: - ldr \rd, [\rx, # S3C2410_UFSTAT] - andne \rd, \rd, #S3C2410_UFSTAT_TXMASK - andeq \rd, \rd, #S3C2440_UFSTAT_TXMASK - .endm - .macro fifo_level_s3c2410 rd, rx ldr \rd, [\rx, # S3C2410_UFSTAT] and \rd, \rd, #S3C2410_UFSTAT_TXMASK @@ -88,12 +41,9 @@ * used variants of these */ -#if defined(CONFIG_CPU_LLSERIAL_S3C2410_ONLY) +#if defined(CONFIG_DEBUG_S3C2410_UART) #define fifo_full fifo_full_s3c2410 #define fifo_level fifo_level_s3c2410 -#elif !defined(CONFIG_CPU_LLSERIAL_S3C2440_ONLY) -#define fifo_full fifo_full_s3c24xx -#define fifo_level fifo_level_s3c24xx #endif /* include the reset of the code which will do the work */ -- cgit v0.10.2 From 1899de2894970fbeece3a97dd69d5321fb00972b Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Fri, 16 May 2014 06:59:18 +0900 Subject: ARM: S3C24XX: use generic DEBUG_UART_PHY/_VIRT in debug macro This removes the need for mach/-headers in the debug macro. Signed-off-by: Heiko Stuebner Signed-off-by: Kukjin Kim diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug index 8c72e10..104c8fb 100644 --- a/arch/arm/Kconfig.debug +++ b/arch/arm/Kconfig.debug @@ -625,6 +625,7 @@ choice config DEBUG_S3C_UART0 depends on PLAT_SAMSUNG select DEBUG_EXYNOS_UART if ARCH_EXYNOS + select DEBUG_S3C24XX_UART if ARCH_S3C24XX bool "Use S3C UART 0 for low-level debug" help Say Y here if you want the debug print routines to direct @@ -637,6 +638,7 @@ choice config DEBUG_S3C_UART1 depends on PLAT_SAMSUNG select DEBUG_EXYNOS_UART if ARCH_EXYNOS + select DEBUG_S3C24XX_UART if ARCH_S3C24XX bool "Use S3C UART 1 for low-level debug" help Say Y here if you want the debug print routines to direct @@ -649,6 +651,7 @@ choice config DEBUG_S3C_UART2 depends on PLAT_SAMSUNG select DEBUG_EXYNOS_UART if ARCH_EXYNOS + select DEBUG_S3C24XX_UART if ARCH_S3C24XX bool "Use S3C UART 2 for low-level debug" help Say Y here if you want the debug print routines to direct @@ -950,6 +953,10 @@ config DEBUG_EXYNOS_UART config DEBUG_S3C2410_UART bool + select DEBUG_S3C24XX_UART + +config DEBUG_S3C24XX_UART + bool config DEBUG_OMAP2PLUS_UART bool @@ -1059,6 +1066,12 @@ config DEBUG_UART_PHYS default 0x40090000 if ARCH_LPC32XX default 0x40100000 if DEBUG_PXA_UART1 default 0x42000000 if ARCH_GEMINI + default 0x50000000 if DEBUG_S3C24XX_UART && (DEBUG_S3C_UART0 || \ + DEBUG_S3C2410_UART0) + default 0x50004000 if DEBUG_S3C24XX_UART && (DEBUG_S3C_UART1 || \ + DEBUG_S3C2410_UART1) + default 0x50008000 if DEBUG_S3C24XX_UART && (DEBUG_S3C_UART2 || \ + DEBUG_S3C2410_UART2) default 0x7c0003f8 if FOOTBRIDGE default 0x80070000 if DEBUG_IMX23_UART default 0x80074000 if DEBUG_IMX28_UART @@ -1088,7 +1101,7 @@ config DEBUG_UART_PHYS default 0xfffff700 if ARCH_IOP33X depends on DEBUG_LL_UART_8250 || DEBUG_LL_UART_PL01X || \ DEBUG_LL_UART_EFM32 || \ - DEBUG_UART_8250 || DEBUG_UART_PL01X + DEBUG_UART_8250 || DEBUG_UART_PL01X || DEBUG_S3C24XX_UART config DEBUG_UART_VIRT hex "Virtual base address of debug UART" @@ -1105,6 +1118,12 @@ config DEBUG_UART_VIRT default 0xf2100000 if DEBUG_PXA_UART1 default 0xf4090000 if ARCH_LPC32XX default 0xf4200000 if ARCH_GEMINI + default 0xf7000000 if DEBUG_S3C24XX_UART && (DEBUG_S3C_UART0 || \ + DEBUG_S3C2410_UART0) + default 0xf7004000 if DEBUG_S3C24XX_UART && (DEBUG_S3C_UART1 || \ + DEBUG_S3C2410_UART1) + default 0xf7008000 if DEBUG_S3C24XX_UART && (DEBUG_S3C_UART2 || \ + DEBUG_S3C2410_UART2) default 0xf7fc9000 if DEBUG_BERLIN_UART default 0xf8009000 if DEBUG_VEXPRESS_UART0_CA9 default 0xf8090000 if DEBUG_VEXPRESS_UART0_RS1 @@ -1146,7 +1165,7 @@ config DEBUG_UART_VIRT default 0xff003000 if DEBUG_U300_UART default DEBUG_UART_PHYS if !MMU depends on DEBUG_LL_UART_8250 || DEBUG_LL_UART_PL01X || \ - DEBUG_UART_8250 || DEBUG_UART_PL01X + DEBUG_UART_8250 || DEBUG_UART_PL01X || DEBUG_S3C24XX_UART config DEBUG_UART_8250_SHIFT int "Register offset shift for the 8250 debug UART" diff --git a/arch/arm/mach-s3c24xx/include/mach/debug-macro.S b/arch/arm/mach-s3c24xx/include/mach/debug-macro.S index fbe3e71..b1f54dc 100644 --- a/arch/arm/mach-s3c24xx/include/mach/debug-macro.S +++ b/arch/arm/mach-s3c24xx/include/mach/debug-macro.S @@ -12,18 +12,13 @@ * published by the Free Software Foundation. */ -#include #include #define S3C2410_UART1_OFF (0x4000) .macro addruart, rp, rv, tmp - ldr \rp, = S3C24XX_PA_UART - ldr \rv, = S3C24XX_VA_UART -#if CONFIG_DEBUG_S3C_UART != 0 - add \rp, \rp, #(S3C2410_UART1_OFF * CONFIG_DEBUG_S3C_UART) - add \rv, \rv, #(S3C2410_UART1_OFF * CONFIG_DEBUG_S3C_UART) -#endif + ldr \rp, = CONFIG_DEBUG_UART_PHYS + ldr \rv, = CONFIG_DEBUG_UART_VIRT .endm .macro fifo_full_s3c2410 rd, rx -- cgit v0.10.2 From 2cd62bd4e5226ae5fa61f58ade8148f2e4643335 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Fri, 16 May 2014 06:59:18 +0900 Subject: ARM: S3C24XX: move debug-macro.S into the common space Move debug-macro.S from mach/include to include/debug where all other common debug macros are. Signed-off-by: Heiko Stuebner Signed-off-by: Kukjin Kim diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug index 104c8fb..4678870 100644 --- a/arch/arm/Kconfig.debug +++ b/arch/arm/Kconfig.debug @@ -1010,6 +1010,7 @@ config DEBUG_LL_INCLUDE DEBUG_IMX6SL_UART default "debug/msm.S" if DEBUG_MSM_UART default "debug/omap2plus.S" if DEBUG_OMAP2PLUS_UART + default "debug/s3c24xx.S" if DEBUG_S3C24XX_UART default "debug/sirf.S" if DEBUG_SIRFPRIMA2_UART1 || DEBUG_SIRFMARCO_UART1 default "debug/sti.S" if DEBUG_STI_UART default "debug/tegra.S" if DEBUG_TEGRA_UART diff --git a/arch/arm/include/debug/s3c24xx.S b/arch/arm/include/debug/s3c24xx.S new file mode 100644 index 0000000..b1f54dc --- /dev/null +++ b/arch/arm/include/debug/s3c24xx.S @@ -0,0 +1,46 @@ +/* arch/arm/mach-s3c2410/include/mach/debug-macro.S + * + * Debugging macro include header + * + * Copyright (C) 1994-1999 Russell King + * Copyright (C) 2005 Simtec Electronics + * + * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include + +#define S3C2410_UART1_OFF (0x4000) + + .macro addruart, rp, rv, tmp + ldr \rp, = CONFIG_DEBUG_UART_PHYS + ldr \rv, = CONFIG_DEBUG_UART_VIRT + .endm + + .macro fifo_full_s3c2410 rd, rx + ldr \rd, [\rx, # S3C2410_UFSTAT] + tst \rd, #S3C2410_UFSTAT_TXFULL + .endm + + .macro fifo_level_s3c2410 rd, rx + ldr \rd, [\rx, # S3C2410_UFSTAT] + and \rd, \rd, #S3C2410_UFSTAT_TXMASK + .endm + +/* Select the correct implementation depending on the configuration. The + * S3C2440 will get selected by default, as these are the most widely + * used variants of these +*/ + +#if defined(CONFIG_DEBUG_S3C2410_UART) +#define fifo_full fifo_full_s3c2410 +#define fifo_level fifo_level_s3c2410 +#endif + +/* include the reset of the code which will do the work */ + +#include diff --git a/arch/arm/mach-s3c24xx/include/mach/debug-macro.S b/arch/arm/mach-s3c24xx/include/mach/debug-macro.S deleted file mode 100644 index b1f54dc..0000000 --- a/arch/arm/mach-s3c24xx/include/mach/debug-macro.S +++ /dev/null @@ -1,46 +0,0 @@ -/* arch/arm/mach-s3c2410/include/mach/debug-macro.S - * - * Debugging macro include header - * - * Copyright (C) 1994-1999 Russell King - * Copyright (C) 2005 Simtec Electronics - * - * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include - -#define S3C2410_UART1_OFF (0x4000) - - .macro addruart, rp, rv, tmp - ldr \rp, = CONFIG_DEBUG_UART_PHYS - ldr \rv, = CONFIG_DEBUG_UART_VIRT - .endm - - .macro fifo_full_s3c2410 rd, rx - ldr \rd, [\rx, # S3C2410_UFSTAT] - tst \rd, #S3C2410_UFSTAT_TXFULL - .endm - - .macro fifo_level_s3c2410 rd, rx - ldr \rd, [\rx, # S3C2410_UFSTAT] - and \rd, \rd, #S3C2410_UFSTAT_TXMASK - .endm - -/* Select the correct implementation depending on the configuration. The - * S3C2440 will get selected by default, as these are the most widely - * used variants of these -*/ - -#if defined(CONFIG_DEBUG_S3C2410_UART) -#define fifo_full fifo_full_s3c2410 -#define fifo_level fifo_level_s3c2410 -#endif - -/* include the reset of the code which will do the work */ - -#include -- cgit v0.10.2 From be1f7c8d7e2bc8b8c76846aa6f276e8d2ef8975a Mon Sep 17 00:00:00 2001 From: Jonghwan Choi Date: Sat, 17 May 2014 08:19:30 +0900 Subject: cpufreq: exynos: Fix the compile error Commit 7da83a80 ("ARM: EXYNOS: Migrate Exynos specific macros from plat to mach") which lands in samsung tree causes build breakage for cpufreq-exynos like following: drivers/cpufreq/exynos-cpufreq.c: In function 'exynos_cpufreq_probe': drivers/cpufreq/exynos-cpufreq.c:166:2: error: implicit declaration of function 'soc_is_exynos4210' [-Werror=implicit-function-declaration] drivers/cpufreq/exynos-cpufreq.c:168:2: error: implicit declaration of function 'soc_is_exynos4212' [-Werror=implicit-function-declaration] drivers/cpufreq/exynos-cpufreq.c:168:2: error: implicit declaration of function 'soc_is_exynos4412' [-Werror=implicit-function-declaration] drivers/cpufreq/exynos-cpufreq.c:170:2: error: implicit declaration of function 'soc_is_exynos5250' [-Werror=implicit-function-declaration] cc1: some warnings being treated as errors make[2]: *** [drivers/cpufreq/exynos-cpufreq.o] Error 1 make[2]: *** Waiting for unfinished jobs.... drivers/cpufreq/exynos4x12-cpufreq.c: In function 'exynos4x12_set_clkdiv': drivers/cpufreq/exynos4x12-cpufreq.c:118:2: error: implicit declaration of function 'soc_is_exynos4212' [-Werror=implicit-function-declaration] cc1: some warnings being treated as errors make[2]: *** [drivers/cpufreq/exynos4x12-cpufreq.o] Error 1 make[1]: *** [drivers/cpufreq] Error 2 This fixes above error with getting SoC information via of_machine_is_compatible() instead of soc_is_exynosXXXX(). Suggested-by: Tomasz Figa Signed-off-by: Jonghwan Choi [kgene.kim@samsung.com: fixed typo and modified as per Viresh's suggestion] [kgene.kim@samsung.com: Rafael agreed] Signed-off-by: Kukjin Kim diff --git a/drivers/cpufreq/exynos-cpufreq.c b/drivers/cpufreq/exynos-cpufreq.c index f99cfe2..e8a4a7e 100644 --- a/drivers/cpufreq/exynos-cpufreq.c +++ b/drivers/cpufreq/exynos-cpufreq.c @@ -17,6 +17,7 @@ #include #include #include +#include #include @@ -163,14 +164,22 @@ static int exynos_cpufreq_probe(struct platform_device *pdev) if (!exynos_info) return -ENOMEM; - if (soc_is_exynos4210()) + if (of_machine_is_compatible("samsung,exynos4210")) { + exynos_info->type = EXYNOS_SOC_4210; ret = exynos4210_cpufreq_init(exynos_info); - else if (soc_is_exynos4212() || soc_is_exynos4412()) + } else if (of_machine_is_compatible("samsung,exynos4212")) { + exynos_info->type = EXYNOS_SOC_4212; ret = exynos4x12_cpufreq_init(exynos_info); - else if (soc_is_exynos5250()) + } else if (of_machine_is_compatible("samsung,exynos4412")) { + exynos_info->type = EXYNOS_SOC_4412; + ret = exynos4x12_cpufreq_init(exynos_info); + } else if (of_machine_is_compatible("samsung,exynos5250")) { + exynos_info->type = EXYNOS_SOC_5250; ret = exynos5250_cpufreq_init(exynos_info); - else - return 0; + } else { + pr_err("%s: Unknown SoC type\n", __func__); + return -ENODEV; + } if (ret) goto err_vdd_arm; diff --git a/drivers/cpufreq/exynos-cpufreq.h b/drivers/cpufreq/exynos-cpufreq.h index 3ddade8..f189547 100644 --- a/drivers/cpufreq/exynos-cpufreq.h +++ b/drivers/cpufreq/exynos-cpufreq.h @@ -17,6 +17,13 @@ enum cpufreq_level_index { L20, }; +enum exynos_soc_type { + EXYNOS_SOC_4210, + EXYNOS_SOC_4212, + EXYNOS_SOC_4412, + EXYNOS_SOC_5250, +}; + #define APLL_FREQ(f, a0, a1, a2, a3, a4, a5, a6, a7, b0, b1, b2, m, p, s) \ { \ .freq = (f) * 1000, \ @@ -34,6 +41,7 @@ struct apll_freq { }; struct exynos_dvfs_info { + enum exynos_soc_type type; unsigned long mpll_freq_khz; unsigned int pll_safe_idx; struct clk *cpu_clk; diff --git a/drivers/cpufreq/exynos4x12-cpufreq.c b/drivers/cpufreq/exynos4x12-cpufreq.c index 466c76a..63a3907 100644 --- a/drivers/cpufreq/exynos4x12-cpufreq.c +++ b/drivers/cpufreq/exynos4x12-cpufreq.c @@ -100,7 +100,6 @@ static struct apll_freq apll_freq_4412[] = { static void exynos4x12_set_clkdiv(unsigned int div_index) { unsigned int tmp; - unsigned int stat_cpu1; /* Change Divider - CPU0 */ @@ -115,13 +114,11 @@ static void exynos4x12_set_clkdiv(unsigned int div_index) tmp = apll_freq_4x12[div_index].clk_div_cpu1; __raw_writel(tmp, EXYNOS4_CLKDIV_CPU1); - if (soc_is_exynos4212()) - stat_cpu1 = 0x11; - else - stat_cpu1 = 0x111; - while (__raw_readl(EXYNOS4_CLKDIV_STATCPU1) & stat_cpu1) + do { cpu_relax(); + tmp = __raw_readl(EXYNOS4_CLKDIV_STATCPU1); + } while (tmp != 0x0); } static void exynos4x12_set_apll(unsigned int index) @@ -184,7 +181,7 @@ int exynos4x12_cpufreq_init(struct exynos_dvfs_info *info) if (IS_ERR(mout_apll)) goto err_mout_apll; - if (soc_is_exynos4212()) + if (info->type == EXYNOS_SOC_4212) apll_freq_4x12 = apll_freq_4212; else apll_freq_4x12 = apll_freq_4412; -- cgit v0.10.2 From bfed1074f213051e94648bfad0d0611a16d81366 Mon Sep 17 00:00:00 2001 From: Cho KyongHo Date: Thu, 22 May 2014 07:23:19 +0900 Subject: clk: exynos5250: Add missing sysmmu clocks for DISP and ISP blocks This patch adds the missing sysmmu clocks for Display and ISP blocks. Signed-off-by: Cho KyongHo Signed-off-by: Shaik Ameer Basha Acked-by: Tomasz Figa Signed-off-by: Kukjin Kim diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c index 8848859..870e18b 100644 --- a/drivers/clk/samsung/clk-exynos5250.c +++ b/drivers/clk/samsung/clk-exynos5250.c @@ -28,6 +28,8 @@ #define MPLL_CON0 0x4100 #define SRC_CORE1 0x4204 #define GATE_IP_ACP 0x8800 +#define GATE_IP_ISP0 0xc800 +#define GATE_IP_ISP1 0xc804 #define CPLL_LOCK 0x10020 #define EPLL_LOCK 0x10030 #define VPLL_LOCK 0x10040 @@ -145,6 +147,8 @@ static unsigned long exynos5250_clk_regs[] __initdata = { PLL_DIV2_SEL, GATE_IP_DISP1, GATE_IP_ACP, + GATE_IP_ISP0, + GATE_IP_ISP1, }; static int exynos5250_clk_suspend(void) @@ -202,6 +206,7 @@ PNAME(mout_aclk400_p) = { "mout_aclk400_g3d_mid", "mout_gpll" }; PNAME(mout_aclk200_sub_p) = { "fin_pll", "div_aclk200" }; PNAME(mout_aclk266_sub_p) = { "fin_pll", "div_aclk266" }; PNAME(mout_aclk333_sub_p) = { "fin_pll", "div_aclk333" }; +PNAME(mout_aclk400_isp_sub_p) = { "fin_pll", "div_aclk400_isp" }; PNAME(mout_hdmi_p) = { "div_hdmi_pixel", "sclk_hdmiphy" }; PNAME(mout_usb3_p) = { "mout_mpll_user", "mout_cpll" }; PNAME(mout_group1_p) = { "fin_pll", "fin_pll", "sclk_hdmi27m", @@ -281,6 +286,7 @@ static struct samsung_mux_clock exynos5250_mux_clks[] __initdata = { MUX(0, "mout_aclk333", mout_aclk166_p, SRC_TOP0, 16, 1), MUX(0, "mout_aclk400_g3d_mid", mout_aclk200_p, SRC_TOP0, 20, 1), + MUX(0, "mout_aclk400_isp", mout_aclk200_p, SRC_TOP1, 24, 1), MUX(0, "mout_aclk400_g3d", mout_aclk400_p, SRC_TOP1, 28, 1), MUX(0, "mout_cpll", mout_cpll_p, SRC_TOP2, 8, 1), @@ -292,6 +298,9 @@ static struct samsung_mux_clock exynos5250_mux_clks[] __initdata = { MUX(0, "mout_aclk200_disp1_sub", mout_aclk200_sub_p, SRC_TOP3, 4, 1), MUX(0, "mout_aclk266_gscl_sub", mout_aclk266_sub_p, SRC_TOP3, 8, 1), + MUX(0, "mout_aclk_266_isp_sub", mout_aclk266_sub_p, SRC_TOP3, 16, 1), + MUX(0, "mout_aclk_400_isp_sub", mout_aclk400_isp_sub_p, + SRC_TOP3, 20, 1), MUX(0, "mout_aclk333_sub", mout_aclk333_sub_p, SRC_TOP3, 24, 1), MUX(0, "mout_cam_bayer", mout_group1_p, SRC_GSCL, 12, 4), @@ -364,6 +373,7 @@ static struct samsung_div_clock exynos5250_div_clks[] __initdata = { DIV(0, "div_aclk400_g3d", "mout_aclk400_g3d", DIV_TOP0, 24, 3), + DIV(0, "div_aclk400_isp", "mout_aclk400_isp", DIV_TOP1, 20, 3), DIV(0, "div_aclk66_pre", "mout_mpll_user", DIV_TOP1, 24, 3), DIV(0, "div_cam_bayer", "mout_cam_bayer", DIV_GSCL, 12, 4), @@ -629,6 +639,31 @@ static struct samsung_gate_clock exynos5250_gate_clks[] __initdata = { GATE(CLK_WDT, "wdt", "div_aclk66", GATE_IP_PERIS, 19, 0, 0), GATE(CLK_RTC, "rtc", "div_aclk66", GATE_IP_PERIS, 20, 0, 0), GATE(CLK_TMU, "tmu", "div_aclk66", GATE_IP_PERIS, 21, 0, 0), + GATE(CLK_SMMU_TV, "smmu_tv", "mout_aclk200_disp1_sub", + GATE_IP_DISP1, 2, 0, 0), + GATE(CLK_SMMU_FIMD1, "smmu_fimd1", "mout_aclk200_disp1_sub", + GATE_IP_DISP1, 8, 0, 0), + GATE(CLK_SMMU_2D, "smmu_2d", "div_aclk200", GATE_IP_ACP, 7, 0, 0), + GATE(CLK_SMMU_FIMC_ISP, "smmu_fimc_isp", "mout_aclk_266_isp_sub", + GATE_IP_ISP0, 8, 0, 0), + GATE(CLK_SMMU_FIMC_DRC, "smmu_fimc_drc", "mout_aclk_266_isp_sub", + GATE_IP_ISP0, 9, 0, 0), + GATE(CLK_SMMU_FIMC_FD, "smmu_fimc_fd", "mout_aclk_266_isp_sub", + GATE_IP_ISP0, 10, 0, 0), + GATE(CLK_SMMU_FIMC_SCC, "smmu_fimc_scc", "mout_aclk_266_isp_sub", + GATE_IP_ISP0, 11, 0, 0), + GATE(CLK_SMMU_FIMC_SCP, "smmu_fimc_scp", "mout_aclk_266_isp_sub", + GATE_IP_ISP0, 12, 0, 0), + GATE(CLK_SMMU_FIMC_MCU, "smmu_fimc_mcu", "mout_aclk_400_isp_sub", + GATE_IP_ISP0, 13, 0, 0), + GATE(CLK_SMMU_FIMC_ODC, "smmu_fimc_odc", "mout_aclk_266_isp_sub", + GATE_IP_ISP1, 4, 0, 0), + GATE(CLK_SMMU_FIMC_DIS0, "smmu_fimc_dis0", "mout_aclk_266_isp_sub", + GATE_IP_ISP1, 5, 0, 0), + GATE(CLK_SMMU_FIMC_DIS1, "smmu_fimc_dis1", "mout_aclk_266_isp_sub", + GATE_IP_ISP1, 6, 0, 0), + GATE(CLK_SMMU_FIMC_3DNR, "smmu_fimc_3dnr", "mout_aclk_266_isp_sub", + GATE_IP_ISP1, 7, 0, 0), }; static struct samsung_pll_rate_table vpll_24mhz_tbl[] __initdata = { diff --git a/include/dt-bindings/clock/exynos5250.h b/include/dt-bindings/clock/exynos5250.h index 415d447..be6e97c 100644 --- a/include/dt-bindings/clock/exynos5250.h +++ b/include/dt-bindings/clock/exynos5250.h @@ -152,6 +152,22 @@ #define CLK_SMMU_MDMA0 347 #define CLK_SSS 348 #define CLK_G3D 349 +#define CLK_SMMU_TV 350 +#define CLK_SMMU_FIMD1 351 +#define CLK_SMMU_2D 352 +#define CLK_SMMU_FIMC_ISP 353 +#define CLK_SMMU_FIMC_DRC 354 +#define CLK_SMMU_FIMC_SCC 355 +#define CLK_SMMU_FIMC_SCP 356 +#define CLK_SMMU_FIMC_FD 357 +#define CLK_SMMU_FIMC_MCU 358 +#define CLK_SMMU_FIMC_ODC 359 +#define CLK_SMMU_FIMC_DIS0 360 +#define CLK_SMMU_FIMC_DIS1 361 +#define CLK_SMMU_FIMC_3DNR 362 +#define CLK_SMMU_FIMC_LITE0 363 +#define CLK_SMMU_FIMC_LITE1 364 +#define CLK_CAMIF_TOP 365 /* mux clocks */ #define CLK_MOUT_HDMI 1024 -- cgit v0.10.2 From ed08f10397cc18cd35fa3938fc55e4effa4fb66f Mon Sep 17 00:00:00 2001 From: Pankaj Dubey Date: Mon, 26 May 2014 04:28:17 +0900 Subject: ARM: EXYNOS: initial board support for exynos5260 SoC This patch add basic arch side support for exynos5260 SoC. Note that this is required to enable build for clock driver. Signed-off-by: Pankaj Dubey Signed-off-by: Rahul Sharma Signed-off-by: Kukjin Kim diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index fc8bf18..bf4ed87 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig @@ -84,6 +84,11 @@ config SOC_EXYNOS5250 help Enable EXYNOS5250 SoC support +config SOC_EXYNOS5260 + bool "SAMSUNG EXYNOS5260" + default y + depends on ARCH_EXYNOS5 + config SOC_EXYNOS5420 bool "SAMSUNG EXYNOS5420" default y diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c index 59aab75..6d74947 100644 --- a/arch/arm/mach-exynos/exynos.c +++ b/arch/arm/mach-exynos/exynos.c @@ -363,6 +363,7 @@ static char const *exynos_dt_compat[] __initconst = { "samsung,exynos4412", "samsung,exynos5", "samsung,exynos5250", + "samsung,exynos5260", "samsung,exynos5420", "samsung,exynos5440", NULL -- cgit v0.10.2 From 86c6f1488d9e53894cafc5671487269e80286d10 Mon Sep 17 00:00:00 2001 From: Arun Kumar K Date: Mon, 26 May 2014 04:16:11 +0900 Subject: ARM: EXYNOS: Add 5800 SoC support Exynos5800 is an octa core SoC which is based on the 5420 platform. This patch adds the basic support for it in the mach-exynos. Signed-off-by: Arun Kumar K Signed-off-by: Kukjin Kim diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index bf4ed87..8390096 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig @@ -113,6 +113,11 @@ config SOC_EXYNOS5440 help Enable EXYNOS5440 SoC support +config SOC_EXYNOS5800 + bool "SAMSUNG EXYNOS5800" + default y + depends on SOC_EXYNOS5420 + endmenu endif diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h index c1a2f22..d439ed2 100644 --- a/arch/arm/mach-exynos/common.h +++ b/arch/arm/mach-exynos/common.h @@ -23,6 +23,7 @@ #define EXYNOS5250_SOC_ID 0x43520000 #define EXYNOS5420_SOC_ID 0xE5420000 #define EXYNOS5440_SOC_ID 0xE5440000 +#define EXYNOS5800_SOC_ID 0xE5422000 #define EXYNOS5_SOC_MASK 0xFFFFF000 extern unsigned long samsung_cpu_id; @@ -39,6 +40,7 @@ IS_SAMSUNG_CPU(exynos4412, EXYNOS4412_CPU_ID, EXYNOS4_CPU_MASK) IS_SAMSUNG_CPU(exynos5250, EXYNOS5250_SOC_ID, EXYNOS5_SOC_MASK) IS_SAMSUNG_CPU(exynos5420, EXYNOS5420_SOC_ID, EXYNOS5_SOC_MASK) IS_SAMSUNG_CPU(exynos5440, EXYNOS5440_SOC_ID, EXYNOS5_SOC_MASK) +IS_SAMSUNG_CPU(exynos5800, EXYNOS5800_SOC_ID, EXYNOS5_SOC_MASK) #if defined(CONFIG_CPU_EXYNOS4210) # define soc_is_exynos4210() is_samsung_exynos4210() @@ -80,9 +82,16 @@ IS_SAMSUNG_CPU(exynos5440, EXYNOS5440_SOC_ID, EXYNOS5_SOC_MASK) # define soc_is_exynos5440() 0 #endif +#if defined(CONFIG_SOC_EXYNOS5800) +# define soc_is_exynos5800() is_samsung_exynos5800() +#else +# define soc_is_exynos5800() 0 +#endif + #define soc_is_exynos4() (soc_is_exynos4210() || soc_is_exynos4212() || \ soc_is_exynos4412()) -#define soc_is_exynos5() (soc_is_exynos5250() || soc_is_exynos5420()) +#define soc_is_exynos5() (soc_is_exynos5250() || soc_is_exynos5420() || \ + soc_is_exynos5800()) void mct_init(void __iomem *base, int irq_g0, int irq_l0, int irq_l1); diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c index c28cdb1..f5ec7e80 100644 --- a/arch/arm/mach-exynos/platsmp.c +++ b/arch/arm/mach-exynos/platsmp.c @@ -45,7 +45,7 @@ static inline void __iomem *cpu_boot_reg(int cpu) boot_reg = cpu_boot_reg_base(); if (soc_is_exynos4412()) boot_reg += 4*cpu; - else if (soc_is_exynos5420()) + else if (soc_is_exynos5420() || soc_is_exynos5800()) boot_reg += 4; return boot_reg; } -- cgit v0.10.2 From 940bc58de51454f4f6c4be754ad62bd0cb8bc396 Mon Sep 17 00:00:00 2001 From: Chanwoo Choi Date: Mon, 26 May 2014 04:12:26 +0900 Subject: ARM: EXYNOS: Add Exynos3250 SoC ID This patch add Exynos3250's SoC ID. Exynos 3250 is SoC that is based on the 32-bit RISC processor for Smartphone. Exynos3250 uses Cortex-A7 dual cores and has a target speed of 1.0GHz. Signed-off-by: Chanwoo Choi Acked-by: Kyungmin Park Reviewed-by: Tomasz Figa Signed-off-by: Kukjin Kim diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index 8390096..ec3403c 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig @@ -11,6 +11,17 @@ if ARCH_EXYNOS menu "SAMSUNG EXYNOS SoCs Support" +config ARCH_EXYNOS3 + bool "SAMSUNG EXYNOS3" + select ARM_AMBA + select CLKSRC_OF + select HAVE_ARM_SCU if SMP + select HAVE_SMP + select PINCTRL + select PM_GENERIC_DOMAINS if PM_RUNTIME + help + Samsung EXYNOS3 SoCs based systems + config ARCH_EXYNOS4 bool "SAMSUNG EXYNOS4" default y @@ -41,6 +52,17 @@ config ARCH_EXYNOS5 comment "EXYNOS SoCs" +config SOC_EXYNOS3250 + bool "SAMSUNG EXYNOS3250" + default y + depends on ARCH_EXYNOS3 + select ARCH_HAS_BANDGAP + select ARM_CPU_SUSPEND if PM + select PINCTRL_EXYNOS + select SAMSUNG_DMADEV + help + Enable EXYNOS3250 CPU support + config CPU_EXYNOS4210 bool "SAMSUNG EXYNOS4210" default y diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h index d439ed2..26218e7 100644 --- a/arch/arm/mach-exynos/common.h +++ b/arch/arm/mach-exynos/common.h @@ -15,6 +15,9 @@ #include #include +#define EXYNOS3250_SOC_ID 0xE3472000 +#define EXYNOS3_SOC_MASK 0xFFFFF000 + #define EXYNOS4210_CPU_ID 0x43210000 #define EXYNOS4212_CPU_ID 0x43220000 #define EXYNOS4412_CPU_ID 0xE4412200 @@ -34,6 +37,7 @@ static inline int is_samsung_##name(void) \ return ((samsung_cpu_id & mask) == (id & mask)); \ } +IS_SAMSUNG_CPU(exynos3250, EXYNOS3250_SOC_ID, EXYNOS3_SOC_MASK) IS_SAMSUNG_CPU(exynos4210, EXYNOS4210_CPU_ID, EXYNOS4_CPU_MASK) IS_SAMSUNG_CPU(exynos4212, EXYNOS4212_CPU_ID, EXYNOS4_CPU_MASK) IS_SAMSUNG_CPU(exynos4412, EXYNOS4412_CPU_ID, EXYNOS4_CPU_MASK) @@ -42,6 +46,12 @@ IS_SAMSUNG_CPU(exynos5420, EXYNOS5420_SOC_ID, EXYNOS5_SOC_MASK) IS_SAMSUNG_CPU(exynos5440, EXYNOS5440_SOC_ID, EXYNOS5_SOC_MASK) IS_SAMSUNG_CPU(exynos5800, EXYNOS5800_SOC_ID, EXYNOS5_SOC_MASK) +#if defined(CONFIG_SOC_EXYNOS3250) +# define soc_is_exynos3250() is_samsung_exynos3250() +#else +# define soc_is_exynos3250() 0 +#endif + #if defined(CONFIG_CPU_EXYNOS4210) # define soc_is_exynos4210() is_samsung_exynos4210() #else diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c index 6d74947..0bcf11c 100644 --- a/arch/arm/mach-exynos/exynos.c +++ b/arch/arm/mach-exynos/exynos.c @@ -357,6 +357,8 @@ static void __init exynos_dt_machine_init(void) } static char const *exynos_dt_compat[] __initconst = { + "samsung,exynos3", + "samsung,exynos3250", "samsung,exynos4", "samsung,exynos4210", "samsung,exynos4212", -- cgit v0.10.2 From 6457158acc30ece42f62d50f4b8f19264203b15e Mon Sep 17 00:00:00 2001 From: Chanwoo Choi Date: Mon, 26 May 2014 04:12:32 +0900 Subject: ARM: EXYNOS: Support secondary CPU boot of Exynos3250 This patch fix the offset of CPU boot address and don't need to send smc call of SMC_CMD_CPU1BOOT command for secondary CPU boot because Exynos3250 removes WFE in secure mode. Signed-off-by: Chanwoo Choi Acked-by: Kyungmin Park Reviewed-by: Tomasz Figa Signed-off-by: Kukjin Kim diff --git a/arch/arm/mach-exynos/firmware.c b/arch/arm/mach-exynos/firmware.c index f6cb510..1120c28 100644 --- a/arch/arm/mach-exynos/firmware.c +++ b/arch/arm/mach-exynos/firmware.c @@ -30,6 +30,13 @@ static int exynos_do_idle(void) static int exynos_cpu_boot(int cpu) { /* + * Exynos3250 doesn't need to send smc command for secondary CPU boot + * because Exynos3250 removes WFE in secure mode. + */ + if (soc_is_exynos3250()) + return 0; + + /* * The second parameter of SMC_CMD_CPU1BOOT command means CPU id. * But, Exynos4212 has only one secondary CPU so second parameter * isn't used for informing secure firmware about CPU id. @@ -45,7 +52,7 @@ static int exynos_set_cpu_boot_addr(int cpu, unsigned long boot_addr) { void __iomem *boot_reg = S5P_VA_SYSRAM_NS + 0x1c; - if (!soc_is_exynos4212()) + if (!soc_is_exynos4212() && !soc_is_exynos3250()) boot_reg += 4*cpu; __raw_writel(boot_addr, boot_reg); -- cgit v0.10.2 From 723c9c7e1674468975494e728d2cb78947809163 Mon Sep 17 00:00:00 2001 From: Tarek Dakhran Date: Tue, 27 May 2014 06:54:12 +0900 Subject: ARM: EXYNOS: Add support for EXYNOS5410 SoC EXYNOS5410 is SoC in Samsung's Exynos5 SoC series. Add initial support for this SoC. Signed-off-by: Tarek Dakhran Signed-off-by: Vyacheslav Tyrtov Reviewed-by: Tomasz Figa Signed-off-by: Kukjin Kim diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index ec3403c..d249746 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig @@ -111,6 +111,11 @@ config SOC_EXYNOS5260 default y depends on ARCH_EXYNOS5 +config SOC_EXYNOS5410 + bool "SAMSUNG EXYNOS5410" + default y + depends on ARCH_EXYNOS5 + config SOC_EXYNOS5420 bool "SAMSUNG EXYNOS5420" default y diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h index 26218e7..099b22f 100644 --- a/arch/arm/mach-exynos/common.h +++ b/arch/arm/mach-exynos/common.h @@ -24,6 +24,7 @@ #define EXYNOS4_CPU_MASK 0xFFFE0000 #define EXYNOS5250_SOC_ID 0x43520000 +#define EXYNOS5410_SOC_ID 0xE5410000 #define EXYNOS5420_SOC_ID 0xE5420000 #define EXYNOS5440_SOC_ID 0xE5440000 #define EXYNOS5800_SOC_ID 0xE5422000 @@ -42,6 +43,7 @@ IS_SAMSUNG_CPU(exynos4210, EXYNOS4210_CPU_ID, EXYNOS4_CPU_MASK) IS_SAMSUNG_CPU(exynos4212, EXYNOS4212_CPU_ID, EXYNOS4_CPU_MASK) IS_SAMSUNG_CPU(exynos4412, EXYNOS4412_CPU_ID, EXYNOS4_CPU_MASK) IS_SAMSUNG_CPU(exynos5250, EXYNOS5250_SOC_ID, EXYNOS5_SOC_MASK) +IS_SAMSUNG_CPU(exynos5410, EXYNOS5410_SOC_ID, EXYNOS5_SOC_MASK) IS_SAMSUNG_CPU(exynos5420, EXYNOS5420_SOC_ID, EXYNOS5_SOC_MASK) IS_SAMSUNG_CPU(exynos5440, EXYNOS5440_SOC_ID, EXYNOS5_SOC_MASK) IS_SAMSUNG_CPU(exynos5800, EXYNOS5800_SOC_ID, EXYNOS5_SOC_MASK) @@ -80,6 +82,12 @@ IS_SAMSUNG_CPU(exynos5800, EXYNOS5800_SOC_ID, EXYNOS5_SOC_MASK) # define soc_is_exynos5250() 0 #endif +#if defined(CONFIG_SOC_EXYNOS5410) +# define soc_is_exynos5410() is_samsung_exynos5410() +#else +# define soc_is_exynos5410() 0 +#endif + #if defined(CONFIG_SOC_EXYNOS5420) # define soc_is_exynos5420() is_samsung_exynos5420() #else @@ -100,8 +108,8 @@ IS_SAMSUNG_CPU(exynos5800, EXYNOS5800_SOC_ID, EXYNOS5_SOC_MASK) #define soc_is_exynos4() (soc_is_exynos4210() || soc_is_exynos4212() || \ soc_is_exynos4412()) -#define soc_is_exynos5() (soc_is_exynos5250() || soc_is_exynos5420() || \ - soc_is_exynos5800()) +#define soc_is_exynos5() (soc_is_exynos5250() || soc_is_exynos5410() || \ + soc_is_exynos5420() || soc_is_exynos5800()) void mct_init(void __iomem *base, int irq_g0, int irq_l0, int irq_l1); -- cgit v0.10.2 From 9a1013285f73692e38bb7267d8bdebe081c71cf7 Mon Sep 17 00:00:00 2001 From: Sachin Kamat Date: Mon, 26 May 2014 05:58:42 +0900 Subject: ARM: EXYNOS: Consolidate Kconfig entries Instead of repeating the Kconfig entries for every SoC, move them under ARCH_EXYNOS3, 4 and 5 and move the entries common to 3, 4 and 5 under ARCH_EXYNOS. Signed-off-by: Sachin Kamat Acked-by: Arnd Bergmann Signed-off-by: Kukjin Kim diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 044e32b..ccacd23 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -831,18 +831,28 @@ config ARCH_S5PV210 config ARCH_EXYNOS bool "Samsung EXYNOS" + select ARCH_HAS_BANDGAP select ARCH_HAS_CPUFREQ select ARCH_HAS_HOLES_MEMORYMODEL select ARCH_REQUIRE_GPIOLIB select ARCH_SPARSEMEM_ENABLE + select ARM_AMBA select ARM_GIC + select CLKSRC_OF select COMMON_CLK_SAMSUNG select CPU_V7 select GENERIC_CLOCKEVENTS + select HAVE_ARM_SCU if SMP select HAVE_S3C2410_I2C if I2C select HAVE_S3C2410_WATCHDOG if WATCHDOG select HAVE_S3C_RTC if RTC_CLASS + select HAVE_SMP select NEED_MACH_MEMORY_H + select PINCTRL + select PINCTRL_EXYNOS + select PM_GENERIC_DOMAINS if PM_RUNTIME + select S5P_DEV_MFC + select SAMSUNG_DMADEV select SPARSE_IRQ select USE_OF help diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index d249746..28f1a61 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig @@ -13,42 +13,27 @@ menu "SAMSUNG EXYNOS SoCs Support" config ARCH_EXYNOS3 bool "SAMSUNG EXYNOS3" - select ARM_AMBA - select CLKSRC_OF - select HAVE_ARM_SCU if SMP - select HAVE_SMP - select PINCTRL - select PM_GENERIC_DOMAINS if PM_RUNTIME + select ARM_CPU_SUSPEND if PM help - Samsung EXYNOS3 SoCs based systems + Samsung EXYNOS3 (Crotex-A7) SoC based systems config ARCH_EXYNOS4 bool "SAMSUNG EXYNOS4" default y - select ARM_AMBA - select CLKSRC_OF + select ARM_CPU_SUSPEND if PM_SLEEP select CLKSRC_SAMSUNG_PWM if CPU_EXYNOS4210 select CPU_EXYNOS4210 select GIC_NON_BANKED select KEYBOARD_SAMSUNG if INPUT_KEYBOARD - select HAVE_ARM_SCU if SMP - select HAVE_SMP select MIGHT_HAVE_CACHE_L2X0 - select PINCTRL - select PM_GENERIC_DOMAINS if PM_RUNTIME - select S5P_DEV_MFC help - Samsung EXYNOS4 SoCs based systems + Samsung EXYNOS4 (Cortex-A9) SoC based systems config ARCH_EXYNOS5 bool "SAMSUNG EXYNOS5" - select ARM_AMBA - select CLKSRC_OF - select HAVE_ARM_SCU if SMP - select HAVE_SMP - select PINCTRL + default y help - Samsung EXYNOS5 (Cortex-A15) SoC based systems + Samsung EXYNOS5 (Cortex-A15/A7) SoC based systems comment "EXYNOS SoCs" @@ -56,55 +41,26 @@ config SOC_EXYNOS3250 bool "SAMSUNG EXYNOS3250" default y depends on ARCH_EXYNOS3 - select ARCH_HAS_BANDGAP - select ARM_CPU_SUSPEND if PM - select PINCTRL_EXYNOS - select SAMSUNG_DMADEV - help - Enable EXYNOS3250 CPU support config CPU_EXYNOS4210 bool "SAMSUNG EXYNOS4210" default y depends on ARCH_EXYNOS4 - select ARCH_HAS_BANDGAP - select ARM_CPU_SUSPEND if PM_SLEEP - select PINCTRL_EXYNOS - select SAMSUNG_DMADEV - help - Enable EXYNOS4210 CPU support config SOC_EXYNOS4212 bool "SAMSUNG EXYNOS4212" default y depends on ARCH_EXYNOS4 - select ARCH_HAS_BANDGAP - select PINCTRL_EXYNOS - select SAMSUNG_DMADEV - help - Enable EXYNOS4212 SoC support config SOC_EXYNOS4412 bool "SAMSUNG EXYNOS4412" default y depends on ARCH_EXYNOS4 - select ARCH_HAS_BANDGAP - select PINCTRL_EXYNOS - select SAMSUNG_DMADEV - help - Enable EXYNOS4412 SoC support config SOC_EXYNOS5250 bool "SAMSUNG EXYNOS5250" default y depends on ARCH_EXYNOS5 - select ARCH_HAS_BANDGAP - select PINCTRL_EXYNOS - select PM_GENERIC_DOMAINS if PM_RUNTIME - select S5P_DEV_MFC - select SAMSUNG_DMADEV - help - Enable EXYNOS5250 SoC support config SOC_EXYNOS5260 bool "SAMSUNG EXYNOS5260" @@ -120,16 +76,12 @@ config SOC_EXYNOS5420 bool "SAMSUNG EXYNOS5420" default y depends on ARCH_EXYNOS5 - select PM_GENERIC_DOMAINS if PM_RUNTIME - help - Enable EXYNOS5420 SoC support config SOC_EXYNOS5440 bool "SAMSUNG EXYNOS5440" default y depends on ARCH_EXYNOS5 select ARCH_DMA_ADDR_T_64BIT if ARM_LPAE - select ARCH_HAS_BANDGAP select ARCH_HAS_OPP select HAVE_ARM_ARCH_TIMER select AUTO_ZRELADDR -- cgit v0.10.2 From 9dfa92ec4033c348aae6bafc1881e07229fabaa6 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Mon, 26 May 2014 06:09:57 +0900 Subject: ARM: EXYNOS: Enable multi-platform build support This makes it possible to enable the Exynos platform as part of a multiplatform kernel. Signed-off-by: Arnd Bergmann Signed-off-by: Sachin Kamat Signed-off-by: Kukjin Kim diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index ccacd23..c08413c 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -829,35 +829,6 @@ config ARCH_S5PV210 help Samsung S5PV210/S5PC110 series based systems -config ARCH_EXYNOS - bool "Samsung EXYNOS" - select ARCH_HAS_BANDGAP - select ARCH_HAS_CPUFREQ - select ARCH_HAS_HOLES_MEMORYMODEL - select ARCH_REQUIRE_GPIOLIB - select ARCH_SPARSEMEM_ENABLE - select ARM_AMBA - select ARM_GIC - select CLKSRC_OF - select COMMON_CLK_SAMSUNG - select CPU_V7 - select GENERIC_CLOCKEVENTS - select HAVE_ARM_SCU if SMP - select HAVE_S3C2410_I2C if I2C - select HAVE_S3C2410_WATCHDOG if WATCHDOG - select HAVE_S3C_RTC if RTC_CLASS - select HAVE_SMP - select NEED_MACH_MEMORY_H - select PINCTRL - select PINCTRL_EXYNOS - select PM_GENERIC_DOMAINS if PM_RUNTIME - select S5P_DEV_MFC - select SAMSUNG_DMADEV - select SPARSE_IRQ - select USE_OF - help - Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5) - config ARCH_DAVINCI bool "TI DaVinci" select ARCH_HAS_HOLES_MEMORYMODEL diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index 28f1a61..0031a57 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig @@ -7,6 +7,27 @@ # Configuration options for the EXYNOS4 +config ARCH_EXYNOS + bool "Samsung EXYNOS" if ARCH_MULTI_V7 + select ARCH_HAS_BANDGAP + select ARCH_HAS_CPUFREQ + select ARCH_HAS_HOLES_MEMORYMODEL + select ARCH_REQUIRE_GPIOLIB + select ARM_AMBA + select ARM_GIC + select COMMON_CLK_SAMSUNG + select HAVE_ARM_SCU if SMP + select HAVE_S3C2410_I2C if I2C + select HAVE_S3C2410_WATCHDOG if WATCHDOG + select HAVE_S3C_RTC if RTC_CLASS + select PINCTRL + select PINCTRL_EXYNOS + select PM_GENERIC_DOMAINS if PM_RUNTIME + select S5P_DEV_MFC + select SRAM + help + Support for SAMSUNG EXYNOS SoCs (EXYNOS4/5) + if ARCH_EXYNOS menu "SAMSUNG EXYNOS SoCs Support" diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile index f6dcc25..24a8efe 100644 --- a/arch/arm/mach-exynos/Makefile +++ b/arch/arm/mach-exynos/Makefile @@ -5,6 +5,8 @@ # # Licensed under GPLv2 +ccflags-$(CONFIG_ARCH_MULTIPLATFORM) += -I$(srctree)/$(src)/include -I$(srctree)/arch/arm/plat-samsung/include + obj-y := obj-m := obj-n := diff --git a/arch/arm/plat-samsung/Makefile b/arch/arm/plat-samsung/Makefile index 25c826e..5e5beaa 100644 --- a/arch/arm/plat-samsung/Makefile +++ b/arch/arm/plat-samsung/Makefile @@ -4,6 +4,9 @@ # # Licensed under GPLv2 +ccflags-$(CONFIG_ARCH_MULTI_V7) += -I$(srctree)/$(src)/include +ccflags-$(CONFIG_ARCH_EXYNOS) += -I$(srctree)/arch/arm/mach-exynos/include + obj-y := obj-m := obj-n := dummy.o -- cgit v0.10.2 From 4c8d819343461d3c3b8d99874cb2ae0ec59ad34a Mon Sep 17 00:00:00 2001 From: Tomasz Figa Date: Mon, 26 May 2014 06:26:03 +0900 Subject: cpufreq: exynos: Fix driver compilation with ARCH_MULTIPLATFORM Currently Exynos cpufreq drivers rely on globally mapped clock controller registers to configure frequency of CPU cores. This is obviously wrong and will be removed in near future, but to enable support for multi-platform builds without introducing a regression it needs to be worked around. This patch hacks the code to look for clock controller node in device tree and map its registers using of_iomap(), instead of relying on global mapping, so dependencies on platform headers are removed and the driver can compile again with multiplatform support. Signed-off-by: Tomasz Figa Acked-by: Viresh Kumar Signed-off-by: Kukjin Kim diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm index 5805035..d2c7b4b 100644 --- a/drivers/cpufreq/Kconfig.arm +++ b/drivers/cpufreq/Kconfig.arm @@ -30,7 +30,7 @@ config ARM_EXYNOS_CPUFREQ config ARM_EXYNOS4210_CPUFREQ bool "SAMSUNG EXYNOS4210" - depends on CPU_EXYNOS4210 && !ARCH_MULTIPLATFORM + depends on CPU_EXYNOS4210 default y select ARM_EXYNOS_CPUFREQ help @@ -41,7 +41,7 @@ config ARM_EXYNOS4210_CPUFREQ config ARM_EXYNOS4X12_CPUFREQ bool "SAMSUNG EXYNOS4x12" - depends on (SOC_EXYNOS4212 || SOC_EXYNOS4412) && !ARCH_MULTIPLATFORM + depends on SOC_EXYNOS4212 || SOC_EXYNOS4412 default y select ARM_EXYNOS_CPUFREQ help @@ -52,7 +52,7 @@ config ARM_EXYNOS4X12_CPUFREQ config ARM_EXYNOS5250_CPUFREQ bool "SAMSUNG EXYNOS5250" - depends on SOC_EXYNOS5250 && !ARCH_MULTIPLATFORM + depends on SOC_EXYNOS5250 default y select ARM_EXYNOS_CPUFREQ help diff --git a/drivers/cpufreq/exynos-cpufreq.c b/drivers/cpufreq/exynos-cpufreq.c index e8a4a7e..348c8ba 100644 --- a/drivers/cpufreq/exynos-cpufreq.c +++ b/drivers/cpufreq/exynos-cpufreq.c @@ -19,8 +19,6 @@ #include #include -#include - #include "exynos-cpufreq.h" static struct exynos_dvfs_info *exynos_info; diff --git a/drivers/cpufreq/exynos-cpufreq.h b/drivers/cpufreq/exynos-cpufreq.h index f189547..51af42e 100644 --- a/drivers/cpufreq/exynos-cpufreq.h +++ b/drivers/cpufreq/exynos-cpufreq.h @@ -49,6 +49,7 @@ struct exynos_dvfs_info { struct cpufreq_frequency_table *freq_table; void (*set_freq)(unsigned int, unsigned int); bool (*need_apll_change)(unsigned int, unsigned int); + void __iomem *cmu_regs; }; #ifdef CONFIG_ARM_EXYNOS4210_CPUFREQ @@ -76,24 +77,21 @@ static inline int exynos5250_cpufreq_init(struct exynos_dvfs_info *info) } #endif -#include -#include +#define EXYNOS4_CLKSRC_CPU 0x14200 +#define EXYNOS4_CLKMUX_STATCPU 0x14400 -#define EXYNOS4_CLKSRC_CPU (S5P_VA_CMU + 0x14200) -#define EXYNOS4_CLKMUX_STATCPU (S5P_VA_CMU + 0x14400) - -#define EXYNOS4_CLKDIV_CPU (S5P_VA_CMU + 0x14500) -#define EXYNOS4_CLKDIV_CPU1 (S5P_VA_CMU + 0x14504) -#define EXYNOS4_CLKDIV_STATCPU (S5P_VA_CMU + 0x14600) -#define EXYNOS4_CLKDIV_STATCPU1 (S5P_VA_CMU + 0x14604) +#define EXYNOS4_CLKDIV_CPU 0x14500 +#define EXYNOS4_CLKDIV_CPU1 0x14504 +#define EXYNOS4_CLKDIV_STATCPU 0x14600 +#define EXYNOS4_CLKDIV_STATCPU1 0x14604 #define EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT (16) #define EXYNOS4_CLKMUX_STATCPU_MUXCORE_MASK (0x7 << EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT) -#define EXYNOS5_APLL_LOCK (S5P_VA_CMU + 0x00000) -#define EXYNOS5_APLL_CON0 (S5P_VA_CMU + 0x00100) -#define EXYNOS5_CLKMUX_STATCPU (S5P_VA_CMU + 0x00400) -#define EXYNOS5_CLKDIV_CPU0 (S5P_VA_CMU + 0x00500) -#define EXYNOS5_CLKDIV_CPU1 (S5P_VA_CMU + 0x00504) -#define EXYNOS5_CLKDIV_STATCPU0 (S5P_VA_CMU + 0x00600) -#define EXYNOS5_CLKDIV_STATCPU1 (S5P_VA_CMU + 0x00604) +#define EXYNOS5_APLL_LOCK 0x00000 +#define EXYNOS5_APLL_CON0 0x00100 +#define EXYNOS5_CLKMUX_STATCPU 0x00400 +#define EXYNOS5_CLKDIV_CPU0 0x00500 +#define EXYNOS5_CLKDIV_CPU1 0x00504 +#define EXYNOS5_CLKDIV_STATCPU0 0x00600 +#define EXYNOS5_CLKDIV_STATCPU1 0x00604 diff --git a/drivers/cpufreq/exynos4210-cpufreq.c b/drivers/cpufreq/exynos4210-cpufreq.c index 6384e5b..61a5431 100644 --- a/drivers/cpufreq/exynos4210-cpufreq.c +++ b/drivers/cpufreq/exynos4210-cpufreq.c @@ -16,6 +16,8 @@ #include #include #include +#include +#include #include "exynos-cpufreq.h" @@ -23,6 +25,7 @@ static struct clk *cpu_clk; static struct clk *moutcore; static struct clk *mout_mpll; static struct clk *mout_apll; +static struct exynos_dvfs_info *cpufreq; static unsigned int exynos4210_volt_table[] = { 1250000, 1150000, 1050000, 975000, 950000, @@ -60,20 +63,20 @@ static void exynos4210_set_clkdiv(unsigned int div_index) tmp = apll_freq_4210[div_index].clk_div_cpu0; - __raw_writel(tmp, EXYNOS4_CLKDIV_CPU); + __raw_writel(tmp, cpufreq->cmu_regs + EXYNOS4_CLKDIV_CPU); do { - tmp = __raw_readl(EXYNOS4_CLKDIV_STATCPU); + tmp = __raw_readl(cpufreq->cmu_regs + EXYNOS4_CLKDIV_STATCPU); } while (tmp & 0x1111111); /* Change Divider - CPU1 */ tmp = apll_freq_4210[div_index].clk_div_cpu1; - __raw_writel(tmp, EXYNOS4_CLKDIV_CPU1); + __raw_writel(tmp, cpufreq->cmu_regs + EXYNOS4_CLKDIV_CPU1); do { - tmp = __raw_readl(EXYNOS4_CLKDIV_STATCPU1); + tmp = __raw_readl(cpufreq->cmu_regs + EXYNOS4_CLKDIV_STATCPU1); } while (tmp & 0x11); } @@ -85,7 +88,7 @@ static void exynos4210_set_apll(unsigned int index) clk_set_parent(moutcore, mout_mpll); do { - tmp = (__raw_readl(EXYNOS4_CLKMUX_STATCPU) + tmp = (__raw_readl(cpufreq->cmu_regs + EXYNOS4_CLKMUX_STATCPU) >> EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT); tmp &= 0x7; } while (tmp != 0x2); @@ -96,7 +99,7 @@ static void exynos4210_set_apll(unsigned int index) clk_set_parent(moutcore, mout_apll); do { - tmp = __raw_readl(EXYNOS4_CLKMUX_STATCPU); + tmp = __raw_readl(cpufreq->cmu_regs + EXYNOS4_CLKMUX_STATCPU); tmp &= EXYNOS4_CLKMUX_STATCPU_MUXCORE_MASK; } while (tmp != (0x1 << EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT)); } @@ -115,8 +118,30 @@ static void exynos4210_set_frequency(unsigned int old_index, int exynos4210_cpufreq_init(struct exynos_dvfs_info *info) { + struct device_node *np; unsigned long rate; + /* + * HACK: This is a temporary workaround to get access to clock + * controller registers directly and remove static mappings and + * dependencies on platform headers. It is necessary to enable + * Exynos multi-platform support and will be removed together with + * this whole driver as soon as Exynos gets migrated to use + * cpufreq-cpu0 driver. + */ + np = of_find_compatible_node(NULL, NULL, "samsung,exynos4210-clock"); + if (!np) { + pr_err("%s: failed to find clock controller DT node\n", + __func__); + return -ENODEV; + } + + info->cmu_regs = of_iomap(np, 0); + if (!info->cmu_regs) { + pr_err("%s: failed to map CMU registers\n", __func__); + return -EFAULT; + } + cpu_clk = clk_get(NULL, "armclk"); if (IS_ERR(cpu_clk)) return PTR_ERR(cpu_clk); @@ -143,6 +168,8 @@ int exynos4210_cpufreq_init(struct exynos_dvfs_info *info) info->freq_table = exynos4210_freq_table; info->set_freq = exynos4210_set_frequency; + cpufreq = info; + return 0; err_mout_apll: diff --git a/drivers/cpufreq/exynos4x12-cpufreq.c b/drivers/cpufreq/exynos4x12-cpufreq.c index 63a3907..351a207 100644 --- a/drivers/cpufreq/exynos4x12-cpufreq.c +++ b/drivers/cpufreq/exynos4x12-cpufreq.c @@ -16,6 +16,8 @@ #include #include #include +#include +#include #include "exynos-cpufreq.h" @@ -23,6 +25,7 @@ static struct clk *cpu_clk; static struct clk *moutcore; static struct clk *mout_mpll; static struct clk *mout_apll; +static struct exynos_dvfs_info *cpufreq; static unsigned int exynos4x12_volt_table[] = { 1350000, 1287500, 1250000, 1187500, 1137500, 1087500, 1037500, @@ -105,19 +108,20 @@ static void exynos4x12_set_clkdiv(unsigned int div_index) tmp = apll_freq_4x12[div_index].clk_div_cpu0; - __raw_writel(tmp, EXYNOS4_CLKDIV_CPU); + __raw_writel(tmp, cpufreq->cmu_regs + EXYNOS4_CLKDIV_CPU); - while (__raw_readl(EXYNOS4_CLKDIV_STATCPU) & 0x11111111) + while (__raw_readl(cpufreq->cmu_regs + EXYNOS4_CLKDIV_STATCPU) + & 0x11111111) cpu_relax(); /* Change Divider - CPU1 */ tmp = apll_freq_4x12[div_index].clk_div_cpu1; - __raw_writel(tmp, EXYNOS4_CLKDIV_CPU1); + __raw_writel(tmp, cpufreq->cmu_regs + EXYNOS4_CLKDIV_CPU1); do { cpu_relax(); - tmp = __raw_readl(EXYNOS4_CLKDIV_STATCPU1); + tmp = __raw_readl(cpufreq->cmu_regs + EXYNOS4_CLKDIV_STATCPU1); } while (tmp != 0x0); } @@ -130,7 +134,7 @@ static void exynos4x12_set_apll(unsigned int index) do { cpu_relax(); - tmp = (__raw_readl(EXYNOS4_CLKMUX_STATCPU) + tmp = (__raw_readl(cpufreq->cmu_regs + EXYNOS4_CLKMUX_STATCPU) >> EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT); tmp &= 0x7; } while (tmp != 0x2); @@ -142,7 +146,7 @@ static void exynos4x12_set_apll(unsigned int index) do { cpu_relax(); - tmp = __raw_readl(EXYNOS4_CLKMUX_STATCPU); + tmp = __raw_readl(cpufreq->cmu_regs + EXYNOS4_CLKMUX_STATCPU); tmp &= EXYNOS4_CLKMUX_STATCPU_MUXCORE_MASK; } while (tmp != (0x1 << EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT)); } @@ -161,8 +165,30 @@ static void exynos4x12_set_frequency(unsigned int old_index, int exynos4x12_cpufreq_init(struct exynos_dvfs_info *info) { + struct device_node *np; unsigned long rate; + /* + * HACK: This is a temporary workaround to get access to clock + * controller registers directly and remove static mappings and + * dependencies on platform headers. It is necessary to enable + * Exynos multi-platform support and will be removed together with + * this whole driver as soon as Exynos gets migrated to use + * cpufreq-cpu0 driver. + */ + np = of_find_compatible_node(NULL, NULL, "samsung,exynos4412-clock"); + if (!np) { + pr_err("%s: failed to find clock controller DT node\n", + __func__); + return -ENODEV; + } + + info->cmu_regs = of_iomap(np, 0); + if (!info->cmu_regs) { + pr_err("%s: failed to map CMU registers\n", __func__); + return -EFAULT; + } + cpu_clk = clk_get(NULL, "armclk"); if (IS_ERR(cpu_clk)) return PTR_ERR(cpu_clk); @@ -194,6 +220,8 @@ int exynos4x12_cpufreq_init(struct exynos_dvfs_info *info) info->freq_table = exynos4x12_freq_table; info->set_freq = exynos4x12_set_frequency; + cpufreq = info; + return 0; err_mout_apll: diff --git a/drivers/cpufreq/exynos5250-cpufreq.c b/drivers/cpufreq/exynos5250-cpufreq.c index 363a0b3..c91ce69 100644 --- a/drivers/cpufreq/exynos5250-cpufreq.c +++ b/drivers/cpufreq/exynos5250-cpufreq.c @@ -16,8 +16,8 @@ #include #include #include - -#include +#include +#include #include "exynos-cpufreq.h" @@ -25,6 +25,7 @@ static struct clk *cpu_clk; static struct clk *moutcore; static struct clk *mout_mpll; static struct clk *mout_apll; +static struct exynos_dvfs_info *cpufreq; static unsigned int exynos5250_volt_table[] = { 1300000, 1250000, 1225000, 1200000, 1150000, @@ -87,17 +88,18 @@ static void set_clkdiv(unsigned int div_index) tmp = apll_freq_5250[div_index].clk_div_cpu0; - __raw_writel(tmp, EXYNOS5_CLKDIV_CPU0); + __raw_writel(tmp, cpufreq->cmu_regs + EXYNOS5_CLKDIV_CPU0); - while (__raw_readl(EXYNOS5_CLKDIV_STATCPU0) & 0x11111111) + while (__raw_readl(cpufreq->cmu_regs + EXYNOS5_CLKDIV_STATCPU0) + & 0x11111111) cpu_relax(); /* Change Divider - CPU1 */ tmp = apll_freq_5250[div_index].clk_div_cpu1; - __raw_writel(tmp, EXYNOS5_CLKDIV_CPU1); + __raw_writel(tmp, cpufreq->cmu_regs + EXYNOS5_CLKDIV_CPU1); - while (__raw_readl(EXYNOS5_CLKDIV_STATCPU1) & 0x11) + while (__raw_readl(cpufreq->cmu_regs + EXYNOS5_CLKDIV_STATCPU1) & 0x11) cpu_relax(); } @@ -111,7 +113,8 @@ static void set_apll(unsigned int index) do { cpu_relax(); - tmp = (__raw_readl(EXYNOS5_CLKMUX_STATCPU) >> 16); + tmp = (__raw_readl(cpufreq->cmu_regs + EXYNOS5_CLKMUX_STATCPU) + >> 16); tmp &= 0x7; } while (tmp != 0x2); @@ -122,7 +125,7 @@ static void set_apll(unsigned int index) do { cpu_relax(); - tmp = __raw_readl(EXYNOS5_CLKMUX_STATCPU); + tmp = __raw_readl(cpufreq->cmu_regs + EXYNOS5_CLKMUX_STATCPU); tmp &= (0x7 << 16); } while (tmp != (0x1 << 16)); } @@ -141,8 +144,30 @@ static void exynos5250_set_frequency(unsigned int old_index, int exynos5250_cpufreq_init(struct exynos_dvfs_info *info) { + struct device_node *np; unsigned long rate; + /* + * HACK: This is a temporary workaround to get access to clock + * controller registers directly and remove static mappings and + * dependencies on platform headers. It is necessary to enable + * Exynos multi-platform support and will be removed together with + * this whole driver as soon as Exynos gets migrated to use + * cpufreq-cpu0 driver. + */ + np = of_find_compatible_node(NULL, NULL, "samsung,exynos5250-clock"); + if (!np) { + pr_err("%s: failed to find clock controller DT node\n", + __func__); + return -ENODEV; + } + + info->cmu_regs = of_iomap(np, 0); + if (!info->cmu_regs) { + pr_err("%s: failed to map CMU registers\n", __func__); + return -EFAULT; + } + cpu_clk = clk_get(NULL, "armclk"); if (IS_ERR(cpu_clk)) return PTR_ERR(cpu_clk); @@ -169,6 +194,8 @@ int exynos5250_cpufreq_init(struct exynos_dvfs_info *info) info->freq_table = exynos5250_freq_table; info->set_freq = exynos5250_set_frequency; + cpufreq = info; + return 0; err_mout_apll: -- cgit v0.10.2