From 87fa28e972c223f69c1315a1b2ddb2a11d33ad0e Mon Sep 17 00:00:00 2001 From: David Brown Date: Tue, 4 Jan 2011 17:02:48 -0800 Subject: msm: Add CPU queries Create runtime queries to distinguish the various MSM targets. Although these would probably be better named soc_is..., use cpu_is... to match convention in the rest of the kernel. Hard code the tests based on config options for now. When runtime device detection is implemented, these can be made dynamic. Signed-off-by: David Brown diff --git a/arch/arm/mach-msm/include/mach/cpu.h b/arch/arm/mach-msm/include/mach/cpu.h new file mode 100644 index 0000000..e1ba9db --- /dev/null +++ b/arch/arm/mach-msm/include/mach/cpu.h @@ -0,0 +1,48 @@ +/* Copyright (c) 2011, Code Aurora Forum. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + */ + +#ifndef __ARCH_ARM_MACH_MSM_CPU_H__ +#define __ARCH_ARM_MACH_MSM_CPU_H__ + +/* TODO: For now, only one CPU can be compiled at a time. */ + +#define cpu_is_msm7x01() 0 +#define cpu_is_msm7x30() 0 +#define cpu_is_qsd8x50() 0 +#define cpu_is_msm8x60() 0 + +#ifdef CONFIG_ARCH_MSM7X00A +# undef cpu_is_msm7x01 +# define cpu_is_msm7x01() 1 +#endif + +#ifdef CONFIG_ARCH_MSM7X30 +# undef cpu_is_msm7x30 +# define cpu_is_msm7x30() 1 +#endif + +#ifdef CONFIG_ARCH_QSD8X50 +# undef cpu_is_qsd8x50 +# define cpu_is_qsd8x50() 1 +#endif + +#ifdef CONFIG_ARCH_MSM8X60 +# undef cpu_is_msm8x60 +# define cpu_is_msm8x60() 1 +#endif + +#endif -- cgit v0.10.2 From 8c27e6f305242ffab0c88eed5dea8394b8ce86d0 Mon Sep 17 00:00:00 2001 From: David Brown Date: Fri, 7 Jan 2011 10:20:49 -0800 Subject: msm: Generalize timer register mappings Allow the timer register to be determined dynamically instead of at compile time. Use common virtual addresses for the registers across all MSM chips, and select the register mappings based on the detected CPU. Signed-off-by: David Brown diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h b/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h index cfff0e7..1e75ed7 100644 --- a/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h +++ b/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h @@ -1,6 +1,7 @@ /* arch/arm/mach-msm/include/mach/msm_iomap.h * * Copyright (C) 2007 Google, Inc. + * Copyright (c) 2011, Code Aurora Forum. All rights reserved. * Author: Brian Swetland * * This software is licensed under the terms of the GNU General Public @@ -47,13 +48,8 @@ #define MSM_VIC_PHYS 0xC0000000 #define MSM_VIC_SIZE SZ_4K -#define MSM_CSR_BASE IOMEM(0xE0001000) -#define MSM_CSR_PHYS 0xC0100000 -#define MSM_CSR_SIZE SZ_4K - -#define MSM_GPT_PHYS MSM_CSR_PHYS -#define MSM_GPT_BASE MSM_CSR_BASE -#define MSM_GPT_SIZE SZ_4K +#define MSM7X00_CSR_PHYS 0xC0100000 +#define MSM7X00_CSR_SIZE SZ_4K #define MSM_DMOV_BASE IOMEM(0xE0002000) #define MSM_DMOV_PHYS 0xA9700000 diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-7x30.h b/arch/arm/mach-msm/include/mach/msm_iomap-7x30.h index 0fd7b68..4d84be1 100644 --- a/arch/arm/mach-msm/include/mach/msm_iomap-7x30.h +++ b/arch/arm/mach-msm/include/mach/msm_iomap-7x30.h @@ -1,6 +1,6 @@ /* * Copyright (C) 2007 Google, Inc. - * Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved. + * Copyright (c) 2008-2011 Code Aurora Forum. All rights reserved. * Author: Brian Swetland * * This software is licensed under the terms of the GNU General Public @@ -39,16 +39,8 @@ #define MSM_VIC_PHYS 0xC0080000 #define MSM_VIC_SIZE SZ_4K -#define MSM_CSR_BASE IOMEM(0xE0001000) -#define MSM_CSR_PHYS 0xC0100000 -#define MSM_CSR_SIZE SZ_4K - -#define MSM_TMR_PHYS MSM_CSR_PHYS -#define MSM_TMR_BASE MSM_CSR_BASE -#define MSM_TMR_SIZE SZ_4K - -#define MSM_GPT_BASE (MSM_TMR_BASE + 0x4) -#define MSM_DGT_BASE (MSM_TMR_BASE + 0x24) +#define MSM7X30_CSR_PHYS 0xC0100000 +#define MSM7X30_CSR_SIZE SZ_4K #define MSM_DMOV_BASE IOMEM(0xE0002000) #define MSM_DMOV_PHYS 0xAC400000 diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h b/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h index acc819e..cf1c2df 100644 --- a/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h +++ b/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h @@ -1,6 +1,6 @@ /* * Copyright (C) 2007 Google, Inc. - * Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved. + * Copyright (c) 2008-2011 Code Aurora Forum. All rights reserved. * Author: Brian Swetland * * This software is licensed under the terms of the GNU General Public @@ -39,16 +39,8 @@ #define MSM_VIC_PHYS 0xAC000000 #define MSM_VIC_SIZE SZ_4K -#define MSM_CSR_BASE IOMEM(0xE0001000) -#define MSM_CSR_PHYS 0xAC100000 -#define MSM_CSR_SIZE SZ_4K - -#define MSM_TMR_PHYS MSM_CSR_PHYS -#define MSM_TMR_BASE MSM_CSR_BASE -#define MSM_TMR_SIZE SZ_4K - -#define MSM_GPT_BASE MSM_TMR_BASE -#define MSM_DGT_BASE (MSM_TMR_BASE + 0x10) +#define QSD8X50_CSR_PHYS 0xAC100000 +#define QSD8X50_CSR_SIZE SZ_4K #define MSM_DMOV_BASE IOMEM(0xE0002000) #define MSM_DMOV_PHYS 0xA9700000 diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h b/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h index a54e33b..d5482d6 100644 --- a/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h +++ b/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h @@ -1,6 +1,6 @@ /* * Copyright (C) 2007 Google, Inc. - * Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved. + * Copyright (c) 2008-2011, Code Aurora Forum. All rights reserved. * Author: Brian Swetland * * This software is licensed under the terms of the GNU General Public @@ -58,16 +58,11 @@ #define MSM_SHARED_RAM_BASE IOMEM(0xF0100000) #define MSM_SHARED_RAM_SIZE SZ_1M -#define MSM_TMR_BASE IOMEM(0xF0200000) -#define MSM_TMR_PHYS 0x02000000 -#define MSM_TMR_SIZE SZ_4K +#define MSM8X60_TMR_PHYS 0x02000000 +#define MSM8X60_TMR_SIZE SZ_4K -#define MSM_TMR0_BASE IOMEM(0xF0201000) -#define MSM_TMR0_PHYS 0x02040000 -#define MSM_TMR0_SIZE SZ_4K - -#define MSM_GPT_BASE (MSM_TMR_BASE + 0x4) -#define MSM_DGT_BASE (MSM_TMR_BASE + 0x24) +#define MSM8X60_TMR0_PHYS 0x02040000 +#define MSM8X60_TMR0_SIZE SZ_4K #define MSM_IOMMU_JPEGD_PHYS 0x07300000 #define MSM_IOMMU_JPEGD_SIZE SZ_1M diff --git a/arch/arm/mach-msm/include/mach/msm_iomap.h b/arch/arm/mach-msm/include/mach/msm_iomap.h index 8e24dd8..0243bd0 100644 --- a/arch/arm/mach-msm/include/mach/msm_iomap.h +++ b/arch/arm/mach-msm/include/mach/msm_iomap.h @@ -1,6 +1,6 @@ /* * Copyright (C) 2007 Google, Inc. - * Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved. + * Copyright (c) 2008-2011, Code Aurora Forum. All rights reserved. * Author: Brian Swetland * * This software is licensed under the terms of the GNU General Public @@ -53,6 +53,9 @@ #include "msm_iomap-7x00.h" #endif - +/* Virtual addressses shared across all MSM targets. */ +#define MSM_CSR_BASE IOMEM(0xE0001000) +#define MSM_TMR_BASE IOMEM(0xF0200000) +#define MSM_TMR0_BASE IOMEM(0xF0201000) #endif diff --git a/arch/arm/mach-msm/io.c b/arch/arm/mach-msm/io.c index 1260007..97dcd8c 100644 --- a/arch/arm/mach-msm/io.c +++ b/arch/arm/mach-msm/io.c @@ -3,7 +3,7 @@ * MSM7K, QSD io support * * Copyright (C) 2007 Google, Inc. - * Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved. + * Copyright (c) 2008-2011, Code Aurora Forum. All rights reserved. * Author: Brian Swetland * * This software is licensed under the terms of the GNU General Public @@ -28,18 +28,20 @@ #include -#define MSM_DEVICE(name) { \ +#define MSM_CHIP_DEVICE(name, chip) { \ .virtual = (unsigned long) MSM_##name##_BASE, \ - .pfn = __phys_to_pfn(MSM_##name##_PHYS), \ - .length = MSM_##name##_SIZE, \ + .pfn = __phys_to_pfn(chip##_##name##_PHYS), \ + .length = chip##_##name##_SIZE, \ .type = MT_DEVICE_NONSHARED, \ } +#define MSM_DEVICE(name) MSM_CHIP_DEVICE(name, MSM) + #if defined(CONFIG_ARCH_MSM7X00A) || defined(CONFIG_ARCH_MSM7X27) \ || defined(CONFIG_ARCH_MSM7X25) static struct map_desc msm_io_desc[] __initdata = { MSM_DEVICE(VIC), - MSM_DEVICE(CSR), + MSM_CHIP_DEVICE(CSR, MSM7X00), MSM_DEVICE(GPT), MSM_DEVICE(DMOV), MSM_DEVICE(GPIO1), @@ -73,8 +75,7 @@ void __init msm_map_common_io(void) #ifdef CONFIG_ARCH_QSD8X50 static struct map_desc qsd8x50_io_desc[] __initdata = { MSM_DEVICE(VIC), - MSM_DEVICE(CSR), - MSM_DEVICE(TMR), + MSM_CHIP_DEVICE(CSR, QSD8X50), MSM_DEVICE(DMOV), MSM_DEVICE(GPIO1), MSM_DEVICE(GPIO2), @@ -104,8 +105,8 @@ void __init msm_map_qsd8x50_io(void) static struct map_desc msm8x60_io_desc[] __initdata = { MSM_DEVICE(QGIC_DIST), MSM_DEVICE(QGIC_CPU), - MSM_DEVICE(TMR), - MSM_DEVICE(TMR0), + MSM_CHIP_DEVICE(TMR, MSM8X60), + MSM_CHIP_DEVICE(TMR0, MSM8X60), MSM_DEVICE(ACC), MSM_DEVICE(GCC), }; @@ -119,8 +120,7 @@ void __init msm_map_msm8x60_io(void) #ifdef CONFIG_ARCH_MSM7X30 static struct map_desc msm7x30_io_desc[] __initdata = { MSM_DEVICE(VIC), - MSM_DEVICE(CSR), - MSM_DEVICE(TMR), + MSM_CHIP_DEVICE(CSR, MSM7X30), MSM_DEVICE(DMOV), MSM_DEVICE(GPIO1), MSM_DEVICE(GPIO2), diff --git a/arch/arm/mach-msm/timer.c b/arch/arm/mach-msm/timer.c index c105d28..5548b15 100644 --- a/arch/arm/mach-msm/timer.c +++ b/arch/arm/mach-msm/timer.c @@ -24,10 +24,7 @@ #include #include - -#ifndef MSM_DGT_BASE -#define MSM_DGT_BASE (MSM_GPT_BASE + 0x10) -#endif +#include #define TIMER_MATCH_VAL 0x0000 #define TIMER_COUNT_VAL 0x0004 @@ -52,14 +49,9 @@ enum timer_location { GLOBAL_TIMER = 1, }; -#ifdef MSM_TMR0_BASE -#define MSM_TMR_GLOBAL (MSM_TMR0_BASE - MSM_TMR_BASE) -#else -#define MSM_TMR_GLOBAL 0 -#endif - #define MSM_GLOBAL_TIMER MSM_CLOCK_DGT +/* TODO: Remove these ifdefs */ #if defined(CONFIG_ARCH_QSD8X50) #define DGT_HZ (19200000 / 4) /* 19.2 MHz / 4 by default */ #define MSM_DGT_SHIFT (0) @@ -177,11 +169,7 @@ static struct msm_clock msm_clocks[] = { .dev_id = &msm_clocks[0].clockevent, .irq = INT_GP_TIMER_EXP }, - .regbase = MSM_GPT_BASE, .freq = GPT_HZ, - .local_counter = MSM_GPT_BASE + TIMER_COUNT_VAL, - .global_counter = MSM_GPT_BASE + TIMER_COUNT_VAL + - MSM_TMR_GLOBAL, }, [MSM_CLOCK_DGT] = { .clockevent = { @@ -206,12 +194,8 @@ static struct msm_clock msm_clocks[] = { .dev_id = &msm_clocks[1].clockevent, .irq = INT_DEBUG_TIMER_EXP }, - .regbase = MSM_DGT_BASE, .freq = DGT_HZ >> MSM_DGT_SHIFT, .shift = MSM_DGT_SHIFT, - .local_counter = MSM_DGT_BASE + TIMER_COUNT_VAL, - .global_counter = MSM_DGT_BASE + TIMER_COUNT_VAL + - MSM_TMR_GLOBAL, } }; @@ -219,6 +203,25 @@ static void __init msm_timer_init(void) { int i; int res; + int global_offset = 0; + + if (cpu_is_msm7x01()) { + msm_clocks[MSM_CLOCK_GPT].regbase = MSM_CSR_BASE; + msm_clocks[MSM_CLOCK_DGT].regbase = MSM_CSR_BASE + 0x10; + } else if (cpu_is_msm7x30()) { + msm_clocks[MSM_CLOCK_GPT].regbase = MSM_CSR_BASE + 0x04; + msm_clocks[MSM_CLOCK_DGT].regbase = MSM_CSR_BASE + 0x24; + } else if (cpu_is_qsd8x50()) { + msm_clocks[MSM_CLOCK_GPT].regbase = MSM_CSR_BASE; + msm_clocks[MSM_CLOCK_DGT].regbase = MSM_CSR_BASE + 0x10; + } else if (cpu_is_msm8x60()) { + msm_clocks[MSM_CLOCK_GPT].regbase = MSM_TMR_BASE + 0x04; + msm_clocks[MSM_CLOCK_DGT].regbase = MSM_TMR_BASE + 0x24; + + /* Use CPU0's timer as the global timer. */ + global_offset = MSM_TMR0_BASE - MSM_TMR_BASE; + } else + BUG(); #ifdef CONFIG_ARCH_MSM_SCORPIONMP writel(DGT_CLK_CTL_DIV_4, MSM_TMR_BASE + DGT_CLK_CTL); @@ -228,6 +231,10 @@ static void __init msm_timer_init(void) struct msm_clock *clock = &msm_clocks[i]; struct clock_event_device *ce = &clock->clockevent; struct clocksource *cs = &clock->clocksource; + + clock->local_counter = clock->regbase + TIMER_COUNT_VAL; + clock->global_counter = clock->local_counter + global_offset; + writel(0, clock->regbase + TIMER_ENABLE); writel(0, clock->regbase + TIMER_CLEAR); writel(~0, clock->regbase + TIMER_MATCH_VAL); -- cgit v0.10.2 From 8bb06444804c58dffcb5d048381c6378d2b007f7 Mon Sep 17 00:00:00 2001 From: David Brown Date: Tue, 4 Jan 2011 11:02:59 -0800 Subject: msm: Generalize QGIC registers The QGIC registers are mapped to the same virtual addresses across targets, only the physical address changes. Move the BASE address out of target-specific files, and add a SOC name to the base addresses. Signed-off-by: David Brown diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h b/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h index d5482d6..5bd18db 100644 --- a/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h +++ b/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h @@ -35,13 +35,11 @@ * */ -#define MSM_QGIC_DIST_BASE IOMEM(0xF0000000) -#define MSM_QGIC_DIST_PHYS 0x02080000 -#define MSM_QGIC_DIST_SIZE SZ_4K +#define MSM8X60_QGIC_DIST_PHYS 0x02080000 +#define MSM8X60_QGIC_DIST_SIZE SZ_4K -#define MSM_QGIC_CPU_BASE IOMEM(0xF0001000) -#define MSM_QGIC_CPU_PHYS 0x02081000 -#define MSM_QGIC_CPU_SIZE SZ_4K +#define MSM8X60_QGIC_CPU_PHYS 0x02081000 +#define MSM8X60_QGIC_CPU_SIZE SZ_4K #define MSM_ACC_BASE IOMEM(0xF0002000) #define MSM_ACC_PHYS 0x02001000 diff --git a/arch/arm/mach-msm/include/mach/msm_iomap.h b/arch/arm/mach-msm/include/mach/msm_iomap.h index 0243bd0..bb42de3 100644 --- a/arch/arm/mach-msm/include/mach/msm_iomap.h +++ b/arch/arm/mach-msm/include/mach/msm_iomap.h @@ -55,6 +55,8 @@ /* Virtual addressses shared across all MSM targets. */ #define MSM_CSR_BASE IOMEM(0xE0001000) +#define MSM_QGIC_DIST_BASE IOMEM(0xF0000000) +#define MSM_QGIC_CPU_BASE IOMEM(0xF0001000) #define MSM_TMR_BASE IOMEM(0xF0200000) #define MSM_TMR0_BASE IOMEM(0xF0201000) diff --git a/arch/arm/mach-msm/io.c b/arch/arm/mach-msm/io.c index 97dcd8c..49692bb 100644 --- a/arch/arm/mach-msm/io.c +++ b/arch/arm/mach-msm/io.c @@ -103,8 +103,8 @@ void __init msm_map_qsd8x50_io(void) #ifdef CONFIG_ARCH_MSM8X60 static struct map_desc msm8x60_io_desc[] __initdata = { - MSM_DEVICE(QGIC_DIST), - MSM_DEVICE(QGIC_CPU), + MSM_CHIP_DEVICE(QGIC_DIST, MSM8X60), + MSM_CHIP_DEVICE(QGIC_CPU, MSM8X60), MSM_CHIP_DEVICE(TMR, MSM8X60), MSM_CHIP_DEVICE(TMR0, MSM8X60), MSM_DEVICE(ACC), -- cgit v0.10.2 From 5d0afd74b7f5202cad2d26b5bcd1fc1bdf44858f Mon Sep 17 00:00:00 2001 From: Stepan Moskovchenko Date: Wed, 1 Dec 2010 19:05:49 -0800 Subject: msm: io: I/O register definitions for MSM8960 Add the register address definitions for the basic hardware blocks on the Qualcomm MSM8960 chip. Signed-off-by: Stepan Moskovchenko Signed-off-by: David Brown diff --git a/arch/arm/mach-msm/include/mach/io.h b/arch/arm/mach-msm/include/mach/io.h index 7386e73..dc1b928 100644 --- a/arch/arm/mach-msm/include/mach/io.h +++ b/arch/arm/mach-msm/include/mach/io.h @@ -29,6 +29,7 @@ void __iomem *__msm_ioremap(unsigned long phys_addr, size_t size, unsigned int m void msm_map_qsd8x50_io(void); void msm_map_msm7x30_io(void); void msm_map_msm8x60_io(void); +void msm_map_msm8960_io(void); extern unsigned int msm_shared_ram_phys; diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-8960.h b/arch/arm/mach-msm/include/mach/msm_iomap-8960.h new file mode 100644 index 0000000..3c9d960 --- /dev/null +++ b/arch/arm/mach-msm/include/mach/msm_iomap-8960.h @@ -0,0 +1,48 @@ +/* + * Copyright (C) 2007 Google, Inc. + * Copyright (c) 2008-2011, Code Aurora Forum. All rights reserved. + * Author: Brian Swetland + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * + * The MSM peripherals are spread all over across 768MB of physical + * space, which makes just having a simple IO_ADDRESS macro to slide + * them into the right virtual location rough. Instead, we will + * provide a master phys->virt mapping for peripherals here. + * + */ + +#ifndef __ASM_ARCH_MSM_IOMAP_8960_H +#define __ASM_ARCH_MSM_IOMAP_8960_H + +/* Physical base address and size of peripherals. + * Ordered by the virtual base addresses they will be mapped at. + * + * If you add or remove entries here, you'll want to edit the + * msm_io_desc array in arch/arm/mach-msm/io.c to reflect your + * changes. + * + */ + + +#define MSM8960_QGIC_DIST_PHYS 0x02000000 +#define MSM8960_QGIC_DIST_SIZE SZ_4K + +#define MSM8960_QGIC_CPU_PHYS 0x02002000 +#define MSM8960_QGIC_CPU_SIZE SZ_4K + +#define MSM8960_TMR_PHYS 0x0200A000 +#define MSM8960_TMR_SIZE SZ_4K + +#define MSM8960_TMR0_PHYS 0x0208A000 +#define MSM8960_TMR0_SIZE SZ_4K + +#endif diff --git a/arch/arm/mach-msm/include/mach/msm_iomap.h b/arch/arm/mach-msm/include/mach/msm_iomap.h index bb42de3..c98c759 100644 --- a/arch/arm/mach-msm/include/mach/msm_iomap.h +++ b/arch/arm/mach-msm/include/mach/msm_iomap.h @@ -53,6 +53,8 @@ #include "msm_iomap-7x00.h" #endif +#include "msm_iomap-8960.h" + /* Virtual addressses shared across all MSM targets. */ #define MSM_CSR_BASE IOMEM(0xE0001000) #define MSM_QGIC_DIST_BASE IOMEM(0xF0000000) diff --git a/arch/arm/mach-msm/io.c b/arch/arm/mach-msm/io.c index 49692bb..d8d9be5 100644 --- a/arch/arm/mach-msm/io.c +++ b/arch/arm/mach-msm/io.c @@ -117,6 +117,20 @@ void __init msm_map_msm8x60_io(void) } #endif /* CONFIG_ARCH_MSM8X60 */ +#ifdef CONFIG_ARCH_MSM8960 +static struct map_desc msm8960_io_desc[] __initdata = { + MSM_CHIP_DEVICE(QGIC_DIST, MSM8960), + MSM_CHIP_DEVICE(QGIC_CPU, MSM8960), + MSM_CHIP_DEVICE(TMR, MSM8960), + MSM_CHIP_DEVICE(TMR0, MSM8960), +}; + +void __init msm_map_msm8960_io(void) +{ + iotable_init(msm8960_io_desc, ARRAY_SIZE(msm8960_io_desc)); +} +#endif /* CONFIG_ARCH_MSM8960 */ + #ifdef CONFIG_ARCH_MSM7X30 static struct map_desc msm7x30_io_desc[] __initdata = { MSM_DEVICE(VIC), -- cgit v0.10.2 From a2ad9421ce19f57e99b7a5e8798b8697b916d673 Mon Sep 17 00:00:00 2001 From: Stepan Moskovchenko Date: Wed, 1 Dec 2010 20:06:26 -0800 Subject: msm: Physical offset for MSM8960 Add the physical memory offset value for the Qualcomm MSM8960 chip. Signed-off-by: Stepan Moskovchenko Signed-off-by: David Brown diff --git a/arch/arm/mach-msm/include/mach/memory.h b/arch/arm/mach-msm/include/mach/memory.h index 070e17d..014bbd3 100644 --- a/arch/arm/mach-msm/include/mach/memory.h +++ b/arch/arm/mach-msm/include/mach/memory.h @@ -25,6 +25,8 @@ #define PHYS_OFFSET UL(0x00200000) #elif defined(CONFIG_ARCH_MSM8X60) #define PHYS_OFFSET UL(0x40200000) +#elif defined(CONFIG_ARCH_MSM8960) +#define PHYS_OFFSET UL(0x40200000) #else #define PHYS_OFFSET UL(0x10000000) #endif -- cgit v0.10.2 From a6481cd3d901165100e12f9f1f7787293d757574 Mon Sep 17 00:00:00 2001 From: Stepan Moskovchenko Date: Wed, 1 Dec 2010 19:30:35 -0800 Subject: msm: irqs-8960: Interrupt map for MSM8960 Add the interrupt map for the Qualcomm MSM8960 chip. This chip has an interrupt map that is different from previous targets. Signed-off-by: Stepan Moskovchenko Signed-off-by: David Brown diff --git a/arch/arm/mach-msm/include/mach/irqs-8960.h b/arch/arm/mach-msm/include/mach/irqs-8960.h new file mode 100644 index 0000000..c7f083c --- /dev/null +++ b/arch/arm/mach-msm/include/mach/irqs-8960.h @@ -0,0 +1,293 @@ +/* Copyright (c) 2011 Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Code Aurora nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __ASM_ARCH_MSM_IRQS_8960_H +#define __ASM_ARCH_MSM_IRQS_8960_H + +/* MSM ACPU Interrupt Numbers */ + +/* 0-15: STI/SGI (software triggered/generated interrupts) + 16-31: PPI (private peripheral interrupts) + 32+: SPI (shared peripheral interrupts) */ + +#define GIC_PPI_START 16 +#define GIC_SPI_START 32 + +#define INT_VGIC (GIC_PPI_START + 0) +#define INT_DEBUG_TIMER_EXP (GIC_PPI_START + 1) +#define INT_GP_TIMER_EXP (GIC_PPI_START + 2) +#define INT_GP_TIMER2_EXP (GIC_PPI_START + 3) +#define WDT0_ACCSCSSNBARK_INT (GIC_PPI_START + 4) +#define WDT1_ACCSCSSNBARK_INT (GIC_PPI_START + 5) +#define AVS_SVICINT (GIC_PPI_START + 6) +#define AVS_SVICINTSWDONE (GIC_PPI_START + 7) +#define CPU_DBGCPUXCOMMRXFULL (GIC_PPI_START + 8) +#define CPU_DBGCPUXCOMMTXEMPTY (GIC_PPI_START + 9) +#define CPU_SICCPUXPERFMONIRPTREQ (GIC_PPI_START + 10) +#define SC_AVSCPUXDOWN (GIC_PPI_START + 11) +#define SC_AVSCPUXUP (GIC_PPI_START + 12) +#define SC_SICCPUXACGIRPTREQ (GIC_PPI_START + 13) +#define SC_SICCPUXEXTFAULTIRPTREQ (GIC_PPI_START + 14) +/* PPI 15 is unused */ + +#define SC_SICMPUIRPTREQ (GIC_SPI_START + 0) +#define SC_SICL2IRPTREQ (GIC_SPI_START + 1) +#define SC_SICL2PERFMONIRPTREQ (GIC_SPI_START + 2) +#define SC_SICAGCIRPTREQ (GIC_SPI_START + 3) +#define TLMM_APCC_DIR_CONN_IRQ_0 (GIC_SPI_START + 4) +#define TLMM_APCC_DIR_CONN_IRQ_1 (GIC_SPI_START + 5) +#define TLMM_APCC_DIR_CONN_IRQ_2 (GIC_SPI_START + 6) +#define TLMM_APCC_DIR_CONN_IRQ_3 (GIC_SPI_START + 7) +#define TLMM_APCC_DIR_CONN_IRQ_4 (GIC_SPI_START + 8) +#define TLMM_APCC_DIR_CONN_IRQ_5 (GIC_SPI_START + 9) +#define TLMM_APCC_DIR_CONN_IRQ_6 (GIC_SPI_START + 10) +#define TLMM_APCC_DIR_CONN_IRQ_7 (GIC_SPI_START + 11) +#define TLMM_APCC_DIR_CONN_IRQ_8 (GIC_SPI_START + 12) +#define TLMM_APCC_DIR_CONN_IRQ_9 (GIC_SPI_START + 13) +#define PM8921_SEC_IRQ_103 (GIC_SPI_START + 14) +#define PM8018_SEC_IRQ_106 (GIC_SPI_START + 15) +#define TLMM_APCC_SUMMARY_IRQ (GIC_SPI_START + 16) +#define SPDM_RT_1_IRQ (GIC_SPI_START + 17) +#define SPDM_DIAG_IRQ (GIC_SPI_START + 18) +#define RPM_APCC_CPU0_GP_HIGH_IRQ (GIC_SPI_START + 19) +#define RPM_APCC_CPU0_GP_MEDIUM_IRQ (GIC_SPI_START + 20) +#define RPM_APCC_CPU0_GP_LOW_IRQ (GIC_SPI_START + 21) +#define RPM_APCC_CPU0_WAKE_UP_IRQ (GIC_SPI_START + 22) +#define RPM_APCC_CPU1_GP_HIGH_IRQ (GIC_SPI_START + 23) +#define RPM_APCC_CPU1_GP_MEDIUM_IRQ (GIC_SPI_START + 24) +#define RPM_APCC_CPU1_GP_LOW_IRQ (GIC_SPI_START + 25) +#define RPM_APCC_CPU1_WAKE_UP_IRQ (GIC_SPI_START + 26) +#define SSBI2_2_SC_CPU0_SECURE_IRQ (GIC_SPI_START + 27) +#define SSBI2_2_SC_CPU0_NON_SECURE_IRQ (GIC_SPI_START + 28) +#define SSBI2_1_SC_CPU0_SECURE_IRQ (GIC_SPI_START + 29) +#define SSBI2_1_SC_CPU0_NON_SECURE_IRQ (GIC_SPI_START + 30) +#define MSMC_SC_SEC_CE_IRQ (GIC_SPI_START + 31) +#define MSMC_SC_PRI_CE_IRQ (GIC_SPI_START + 32) +#define SLIMBUS0_CORE_EE1_IRQ (GIC_SPI_START + 33) +#define SLIMBUS0_BAM_EE1_IRQ (GIC_SPI_START + 34) +#define Q6FW_WDOG_EXPIRED_IRQ (GIC_SPI_START + 35) +#define Q6SW_WDOG_EXPIRED_IRQ (GIC_SPI_START + 36) +#define MSS_TO_APPS_IRQ_0 (GIC_SPI_START + 37) +#define MSS_TO_APPS_IRQ_1 (GIC_SPI_START + 38) +#define MSS_TO_APPS_IRQ_2 (GIC_SPI_START + 39) +#define MSS_TO_APPS_IRQ_3 (GIC_SPI_START + 40) +#define MSS_TO_APPS_IRQ_4 (GIC_SPI_START + 41) +#define MSS_TO_APPS_IRQ_5 (GIC_SPI_START + 42) +#define MSS_TO_APPS_IRQ_6 (GIC_SPI_START + 43) +#define MSS_TO_APPS_IRQ_7 (GIC_SPI_START + 44) +#define MSS_TO_APPS_IRQ_8 (GIC_SPI_START + 45) +#define MSS_TO_APPS_IRQ_9 (GIC_SPI_START + 46) +#define VPE_IRQ (GIC_SPI_START + 47) +#define VFE_IRQ (GIC_SPI_START + 48) +#define VCODEC_IRQ (GIC_SPI_START + 49) +#define TV_ENC_IRQ (GIC_SPI_START + 50) +#define SMMU_VPE_CB_SC_SECURE_IRQ (GIC_SPI_START + 51) +#define SMMU_VPE_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 52) +#define SMMU_VFE_CB_SC_SECURE_IRQ (GIC_SPI_START + 53) +#define SMMU_VFE_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 54) +#define SMMU_VCODEC_B_CB_SC_SECURE_IRQ (GIC_SPI_START + 55) +#define SMMU_VCODEC_B_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 56) +#define SMMU_VCODEC_A_CB_SC_SECURE_IRQ (GIC_SPI_START + 57) +#define SMMU_VCODEC_A_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 58) +#define SMMU_ROT_CB_SC_SECURE_IRQ (GIC_SPI_START + 59) +#define SMMU_ROT_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 60) +#define SMMU_MDP1_CB_SC_SECURE_IRQ (GIC_SPI_START + 61) +#define SMMU_MDP1_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 62) +#define SMMU_MDP0_CB_SC_SECURE_IRQ (GIC_SPI_START + 63) +#define SMMU_MDP0_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 64) +#define SMMU_JPEGD_CB_SC_SECURE_IRQ (GIC_SPI_START + 65) +#define SMMU_JPEGD_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 66) +#define SMMU_IJPEG_CB_SC_SECURE_IRQ (GIC_SPI_START + 67) +#define SMMU_IJPEG_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 68) +#define SMMU_GFX3D_CB_SC_SECURE_IRQ (GIC_SPI_START + 69) +#define SMMU_GFX3D_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 70) +#define SMMU_GFX2D0_CB_SC_SECURE_IRQ (GIC_SPI_START + 71) +#define SMMU_GFX2D0_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 72) +#define ROT_IRQ (GIC_SPI_START + 73) +#define MMSS_FABRIC_IRQ (GIC_SPI_START + 74) +#define MDP_IRQ (GIC_SPI_START + 75) +#define JPEGD_IRQ (GIC_SPI_START + 76) +#define JPEG_IRQ (GIC_SPI_START + 77) +#define MMSS_IMEM_IRQ (GIC_SPI_START + 78) +#define HDMI_IRQ (GIC_SPI_START + 79) +#define GFX3D_IRQ (GIC_SPI_START + 80) +#define GFX2D0_IRQ (GIC_SPI_START + 81) +#define DSI1_IRQ (GIC_SPI_START + 82) +#define CSI_1_IRQ (GIC_SPI_START + 83) +#define CSI_0_IRQ (GIC_SPI_START + 84) +#define LPASS_SCSS_AUDIO_IF_OUT0_IRQ (GIC_SPI_START + 85) +#define LPASS_SCSS_MIDI_IRQ (GIC_SPI_START + 86) +#define LPASS_Q6SS_WDOG_EXPIRED (GIC_SPI_START + 87) +#define LPASS_SCSS_GP_LOW_IRQ (GIC_SPI_START + 88) +#define LPASS_SCSS_GP_MEDIUM_IRQ (GIC_SPI_START + 89) +#define LPASS_SCSS_GP_HIGH_IRQ (GIC_SPI_START + 90) +#define TOP_IMEM_IRQ (GIC_SPI_START + 91) +#define FABRIC_SYS_IRQ (GIC_SPI_START + 92) +#define FABRIC_APPS_IRQ (GIC_SPI_START + 93) +#define USB1_HS_BAM_IRQ (GIC_SPI_START + 94) +#define SDC4_BAM_IRQ (GIC_SPI_START + 95) +#define SDC3_BAM_IRQ (GIC_SPI_START + 96) +#define SDC2_BAM_IRQ (GIC_SPI_START + 97) +#define SDC1_BAM_IRQ (GIC_SPI_START + 98) +#define FABRIC_SPS_IRQ (GIC_SPI_START + 99) +#define USB1_HS_IRQ (GIC_SPI_START + 100) +#define SDC4_IRQ_0 (GIC_SPI_START + 101) +#define SDC3_IRQ_0 (GIC_SPI_START + 102) +#define SDC2_IRQ_0 (GIC_SPI_START + 103) +#define SDC1_IRQ_0 (GIC_SPI_START + 104) +#define SPS_BAM_DMA_IRQ (GIC_SPI_START + 105) +#define SPS_SEC_VIOL_IRQ (GIC_SPI_START + 106) +#define SPS_MTI_0 (GIC_SPI_START + 107) +#define SPS_MTI_1 (GIC_SPI_START + 108) +#define SPS_MTI_2 (GIC_SPI_START + 109) +#define SPS_MTI_3 (GIC_SPI_START + 110) +#define SPS_MTI_4 (GIC_SPI_START + 111) +#define SPS_MTI_5 (GIC_SPI_START + 112) +#define SPS_MTI_6 (GIC_SPI_START + 113) +#define SPS_MTI_7 (GIC_SPI_START + 114) +#define SPS_MTI_8 (GIC_SPI_START + 115) +#define SPS_MTI_9 (GIC_SPI_START + 116) +#define SPS_MTI_10 (GIC_SPI_START + 117) +#define SPS_MTI_11 (GIC_SPI_START + 118) +#define SPS_MTI_12 (GIC_SPI_START + 119) +#define SPS_MTI_13 (GIC_SPI_START + 120) +#define SPS_MTI_14 (GIC_SPI_START + 121) +#define SPS_MTI_15 (GIC_SPI_START + 122) +#define SPS_MTI_16 (GIC_SPI_START + 123) +#define SPS_MTI_17 (GIC_SPI_START + 124) +#define SPS_MTI_18 (GIC_SPI_START + 125) +#define SPS_MTI_19 (GIC_SPI_START + 126) +#define SPS_MTI_20 (GIC_SPI_START + 127) +#define SPS_MTI_21 (GIC_SPI_START + 128) +#define SPS_MTI_22 (GIC_SPI_START + 129) +#define SPS_MTI_23 (GIC_SPI_START + 130) +#define SPS_MTI_24 (GIC_SPI_START + 131) +#define SPS_MTI_25 (GIC_SPI_START + 132) +#define SPS_MTI_26 (GIC_SPI_START + 133) +#define SPS_MTI_27 (GIC_SPI_START + 134) +#define SPS_MTI_28 (GIC_SPI_START + 135) +#define SPS_MTI_29 (GIC_SPI_START + 136) +#define SPS_MTI_30 (GIC_SPI_START + 137) +#define SPS_MTI_31 (GIC_SPI_START + 138) +#define CSIPHY_4LN_IRQ (GIC_SPI_START + 139) +#define CSIPHY_2LN_IRQ (GIC_SPI_START + 140) +#define USB2_IRQ (GIC_SPI_START + 141) +#define USB1_IRQ (GIC_SPI_START + 142) +#define TSSC_SSBI_IRQ (GIC_SPI_START + 143) +#define TSSC_SAMPLE_IRQ (GIC_SPI_START + 144) +#define TSSC_PENUP_IRQ (GIC_SPI_START + 145) +#define GSBI1_UARTDM_IRQ (GIC_SPI_START + 146) +#define GSBI1_QUP_IRQ (GIC_SPI_START + 147) +#define GSBI2_UARTDM_IRQ (GIC_SPI_START + 148) +#define GSBI2_QUP_IRQ (GIC_SPI_START + 149) +#define GSBI3_UARTDM_IRQ (GIC_SPI_START + 150) +#define GSBI3_QUP_IRQ (GIC_SPI_START + 151) +#define GSBI4_UARTDM_IRQ (GIC_SPI_START + 152) +#define GSBI4_QUP_IRQ (GIC_SPI_START + 153) +#define GSBI5_UARTDM_IRQ (GIC_SPI_START + 154) +#define GSBI5_QUP_IRQ (GIC_SPI_START + 155) +#define GSBI6_UARTDM_IRQ (GIC_SPI_START + 156) +#define GSBI6_QUP_IRQ (GIC_SPI_START + 157) +#define GSBI7_UARTDM_IRQ (GIC_SPI_START + 158) +#define GSBI7_QUP_IRQ (GIC_SPI_START + 159) +#define GSBI8_UARTDM_IRQ (GIC_SPI_START + 160) +#define GSBI8_QUP_IRQ (GIC_SPI_START + 161) +#define TSIF_TSPP_IRQ (GIC_SPI_START + 162) +#define TSIF_BAM_IRQ (GIC_SPI_START + 163) +#define TSIF2_IRQ (GIC_SPI_START + 164) +#define TSIF1_IRQ (GIC_SPI_START + 165) +#define DSI2_IRQ (GIC_SPI_START + 166) +#define ISPIF_IRQ (GIC_SPI_START + 167) +#define MSMC_SC_SEC_TMR_IRQ (GIC_SPI_START + 168) +#define MSMC_SC_SEC_WDOG_BARK_IRQ (GIC_SPI_START + 169) +#define INT_ADM0_SCSS_0_IRQ (GIC_SPI_START + 170) +#define INT_ADM0_SCSS_1_IRQ (GIC_SPI_START + 171) +#define INT_ADM0_SCSS_2_IRQ (GIC_SPI_START + 172) +#define INT_ADM0_SCSS_3_IRQ (GIC_SPI_START + 173) +#define CC_SCSS_WDT1CPU1BITEEXPIRED (GIC_SPI_START + 174) +#define CC_SCSS_WDT1CPU0BITEEXPIRED (GIC_SPI_START + 175) +#define CC_SCSS_WDT0CPU1BITEEXPIRED (GIC_SPI_START + 176) +#define CC_SCSS_WDT0CPU0BITEEXPIRED (GIC_SPI_START + 177) +#define TSENS_UPPER_LOWER_INT (GIC_SPI_START + 178) +#define SSBI2_2_SC_CPU1_SECURE_INT (GIC_SPI_START + 179) +#define SSBI2_2_SC_CPU1_NON_SECURE_INT (GIC_SPI_START + 180) +#define SSBI2_1_SC_CPU1_SECURE_INT (GIC_SPI_START + 181) +#define SSBI2_1_SC_CPU1_NON_SECURE_INT (GIC_SPI_START + 182) +#define XPU_SUMMARY_IRQ (GIC_SPI_START + 183) +#define BUS_EXCEPTION_SUMMARY_IRQ (GIC_SPI_START + 184) +#define HSDDRX_EBI1CH0_IRQ (GIC_SPI_START + 185) +#define HSDDRX_EBI1CH1_IRQ (GIC_SPI_START + 186) +#define SDC5_BAM_IRQ (GIC_SPI_START + 187) +#define SDC5_IRQ_0 (GIC_SPI_START + 188) +#define GSBI9_UARTDM_IRQ (GIC_SPI_START + 189) +#define GSBI9_QUP_IRQ (GIC_SPI_START + 190) +#define GSBI10_UARTDM_IRQ (GIC_SPI_START + 191) +#define GSBI10_QUP_IRQ (GIC_SPI_START + 192) +#define GSBI11_UARTDM_IRQ (GIC_SPI_START + 193) +#define GSBI11_QUP_IRQ (GIC_SPI_START + 194) +#define GSBI12_UARTDM_IRQ (GIC_SPI_START + 195) +#define GSBI12_QUP_IRQ (GIC_SPI_START + 196) +#define RIVA_APSS_LTECOEX_IRQ (GIC_SPI_START + 197) +#define RIVA_APSS_SPARE_IRQ (GIC_SPI_START + 198) +#define RIVA_APSS_WDOG_BITE_RESET_RDY_IRQ (GIC_SPI_START + 199) +#define RIVA_ASS_RESET_DONE_IRQ (GIC_SPI_START + 200) +#define RIVA_APSS_ASIC_IRQ (GIC_SPI_START + 201) +#define RIVA_APPS_WLAN_RX_DATA_AVAIL_IRQ (GIC_SPI_START + 202) +#define RIVA_APPS_WLAN_DATA_XFER_DONE_IRQ (GIC_SPI_START + 203) +#define RIVA_APPS_WLAM_SMSM_IRQ (GIC_SPI_START + 204) +#define RIVA_APPS_LOG_CTRL_IRQ (GIC_SPI_START + 205) +#define RIVA_APPS_FM_CTRL_IRQ (GIC_SPI_START + 206) +#define RIVA_APPS_HCI_IRQ (GIC_SPI_START + 207) +#define RIVA_APPS_WLAN_CTRL_IRQ (GIC_SPI_START + 208) +#define A2_BAM_IRQ (GIC_SPI_START + 209) +#define SMMU_GFX2D1_CB_SC_SECURE_IRQ (GIC_SPI_START + 210) +#define SMMU_GFX2D1_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 211) +#define GFX2D1_IRQ (GIC_SPI_START + 212) +#define PPSS_WDOG_TIMER_IRQ (GIC_SPI_START + 213) +#define SPS_SLIMBUS_CORE_EE0_IRQ (GIC_SPI_START + 214) +#define SPS_SLIMBUS_BAM_EE0_IRQ (GIC_SPI_START + 215) +#define QDSS_ETB_IRQ (GIC_SPI_START + 216) +#define QDSS_CTI2KPSS_CPU1_IRQ (GIC_SPI_START + 217) +#define QDSS_CTI2KPSS_CPU0_IRQ (GIC_SPI_START + 218) +#define TLMM_APCC_DIR_CONN_IRQ_16 (GIC_SPI_START + 219) +#define TLMM_APCC_DIR_CONN_IRQ_17 (GIC_SPI_START + 220) +#define TLMM_APCC_DIR_CONN_IRQ_18 (GIC_SPI_START + 221) +#define TLMM_APCC_DIR_CONN_IRQ_19 (GIC_SPI_START + 222) +#define TLMM_APCC_DIR_CONN_IRQ_20 (GIC_SPI_START + 223) +#define TLMM_APCC_DIR_CONN_IRQ_21 (GIC_SPI_START + 224) +#define PM8921_SEC_IRQ_104 (GIC_SPI_START + 225) +#define PM8018_SEC_IRQ_107 (GIC_SPI_START + 226) + +/* For now, use the maximum number of interrupts until a pending GIC issue + * is sorted out */ +#define NR_MSM_IRQS 1020 +#define NR_BOARD_IRQS 0 +#define NR_GPIO_IRQS 0 + +#endif + diff --git a/arch/arm/mach-msm/include/mach/irqs.h b/arch/arm/mach-msm/include/mach/irqs.h index 8679a45..3cd78b1 100644 --- a/arch/arm/mach-msm/include/mach/irqs.h +++ b/arch/arm/mach-msm/include/mach/irqs.h @@ -26,6 +26,9 @@ #include "sirc.h" #elif defined(CONFIG_ARCH_MSM8X60) #include "irqs-8x60.h" +#elif defined(CONFIG_ARCH_MSM8960) +/* TODO: Make these not generic. */ +#include "irqs-8960.h" #elif defined(CONFIG_ARCH_MSM_ARM11) #include "irqs-7x00.h" #else -- cgit v0.10.2 From b83ce5812a1581655df8d1502398f03408539ba5 Mon Sep 17 00:00:00 2001 From: David Brown Date: Wed, 12 Jan 2011 12:55:16 -0800 Subject: msm: Add MSM 8960 cpu_is check Signed-off-by: David Brown diff --git a/arch/arm/mach-msm/include/mach/cpu.h b/arch/arm/mach-msm/include/mach/cpu.h index e1ba9db..a9481b0 100644 --- a/arch/arm/mach-msm/include/mach/cpu.h +++ b/arch/arm/mach-msm/include/mach/cpu.h @@ -24,6 +24,7 @@ #define cpu_is_msm7x30() 0 #define cpu_is_qsd8x50() 0 #define cpu_is_msm8x60() 0 +#define cpu_is_msm8960() 0 #ifdef CONFIG_ARCH_MSM7X00A # undef cpu_is_msm7x01 @@ -45,4 +46,9 @@ # define cpu_is_msm8x60() 1 #endif +#ifdef CONFIG_ARCH_MSM8960 +# undef cpu_is_msm8960 +# define cpu_is_msm8960() 1 +#endif + #endif -- cgit v0.10.2 From a81c8c38ed06c5f59d62a2257d21ed02d2af38fe Mon Sep 17 00:00:00 2001 From: Stepan Moskovchenko Date: Wed, 1 Dec 2010 19:25:14 -0800 Subject: msm: timer: Timer support for MSM8960 Modify the macros in the MSM timer driver to support the MSM8960 chip. Signed-off-by: Stepan Moskovchenko Signed-off-by: David Brown diff --git a/arch/arm/mach-msm/timer.c b/arch/arm/mach-msm/timer.c index 5548b15..e7f8e5a 100644 --- a/arch/arm/mach-msm/timer.c +++ b/arch/arm/mach-msm/timer.c @@ -55,7 +55,8 @@ enum timer_location { #if defined(CONFIG_ARCH_QSD8X50) #define DGT_HZ (19200000 / 4) /* 19.2 MHz / 4 by default */ #define MSM_DGT_SHIFT (0) -#elif defined(CONFIG_ARCH_MSM7X30) || defined(CONFIG_ARCH_MSM8X60) +#elif defined(CONFIG_ARCH_MSM7X30) || defined(CONFIG_ARCH_MSM8X60) || \ + defined(CONFIG_ARCH_MSM8960) #define DGT_HZ (24576000 / 4) /* 24.576 MHz (LPXO) / 4 by default */ #define MSM_DGT_SHIFT (0) #else @@ -214,7 +215,7 @@ static void __init msm_timer_init(void) } else if (cpu_is_qsd8x50()) { msm_clocks[MSM_CLOCK_GPT].regbase = MSM_CSR_BASE; msm_clocks[MSM_CLOCK_DGT].regbase = MSM_CSR_BASE + 0x10; - } else if (cpu_is_msm8x60()) { + } else if (cpu_is_msm8x60() || cpu_is_msm8960()) { msm_clocks[MSM_CLOCK_GPT].regbase = MSM_TMR_BASE + 0x04; msm_clocks[MSM_CLOCK_DGT].regbase = MSM_TMR_BASE + 0x24; -- cgit v0.10.2 From decd4a9d3671cd95a46ca0e004700077d81c370d Mon Sep 17 00:00:00 2001 From: Stepan Moskovchenko Date: Thu, 9 Dec 2010 19:16:13 -0800 Subject: msm: Makefile cleanup Clean up some of the conditionals in the Makefile in preparation for adding build support for MSM8960. Signed-off-by: Stepan Moskovchenko Signed-off-by: David Brown diff --git a/arch/arm/mach-msm/Makefile b/arch/arm/mach-msm/Makefile index 94195c1..3e15ff3 100644 --- a/arch/arm/mach-msm/Makefile +++ b/arch/arm/mach-msm/Makefile @@ -1,21 +1,15 @@ obj-y += io.o idle.o timer.o -ifndef CONFIG_ARCH_MSM8X60 -obj-y += acpuclock-arm11.o -obj-y += dma.o -endif -ifdef CONFIG_MSM_VIC -obj-y += irq-vic.o -else -ifndef CONFIG_ARCH_MSM8X60 -obj-y += irq.o -endif -endif +obj-$(CONFIG_MSM_VIC) += irq-vic.o +obj-$(CONFIG_ARCH_MSM7X00A) += dma.o irq.o acpuclock-arm11.o +obj-$(CONFIG_ARCH_MSM7X30) += dma.o +obj-$(CONFIG_ARCH_QSD8X50) += dma.o sirc.o obj-$(CONFIG_ARCH_MSM8X60) += clock-dummy.o iommu.o iommu_dev.o devices-msm8x60-iommu.o + obj-$(CONFIG_MSM_PROC_COMM) += proc_comm.o clock-pcom.o vreg.o obj-$(CONFIG_MSM_PROC_COMM) += clock.o -obj-$(CONFIG_ARCH_QSD8X50) += sirc.o + obj-$(CONFIG_MSM_SMD) += smd.o smd_debug.o obj-$(CONFIG_MSM_SMD) += last_radio_log.o obj-$(CONFIG_MSM_SCM) += scm.o scm-boot.o -- cgit v0.10.2 From f441ca2d403cf74ebffbc07a3ccd402efd995799 Mon Sep 17 00:00:00 2001 From: Stepan Moskovchenko Date: Wed, 1 Dec 2010 19:31:16 -0800 Subject: msm: Support for the MSM8960 Simulator target Add the board file, Kconfig options, and Makefile options needed to build for the MSM8960 Simulator target. Signed-off-by: Stepan Moskovchenko Signed-off-by: David Brown diff --git a/arch/arm/mach-msm/Kconfig b/arch/arm/mach-msm/Kconfig index 5d3d9ad..adca96c 100644 --- a/arch/arm/mach-msm/Kconfig +++ b/arch/arm/mach-msm/Kconfig @@ -48,6 +48,16 @@ config ARCH_MSM8X60 select IOMMU_API select MSM_SCM if SMP +config ARCH_MSM8960 + bool "MSM8960" + select ARCH_MSM_SCORPIONMP + select MACH_MSM8960_SIM + select ARM_GIC + select CPU_V7 + select MSM_V2_TLMM + select MSM_GPIOMUX + select MSM_SCM if SMP + endchoice config MSM_SOC_REV_A @@ -125,6 +135,12 @@ config MACH_MSM8X60_FFA help Support for the Qualcomm MSM8x60 FFA eval board. +config MACH_MSM8960_SIM + depends on ARCH_MSM8960 + bool "MSM8960 Simulator" + help + Support for the Qualcomm MSM8960 simulator. + endmenu config IOMMU_PGTABLES_L2 diff --git a/arch/arm/mach-msm/Makefile b/arch/arm/mach-msm/Makefile index 3e15ff3..0229427 100644 --- a/arch/arm/mach-msm/Makefile +++ b/arch/arm/mach-msm/Makefile @@ -6,6 +6,7 @@ obj-$(CONFIG_ARCH_MSM7X00A) += dma.o irq.o acpuclock-arm11.o obj-$(CONFIG_ARCH_MSM7X30) += dma.o obj-$(CONFIG_ARCH_QSD8X50) += dma.o sirc.o obj-$(CONFIG_ARCH_MSM8X60) += clock-dummy.o iommu.o iommu_dev.o devices-msm8x60-iommu.o +obj-$(CONFIG_ARCH_MSM8960) += clock-dummy.o obj-$(CONFIG_MSM_PROC_COMM) += proc_comm.o clock-pcom.o vreg.o obj-$(CONFIG_MSM_PROC_COMM) += clock.o @@ -23,12 +24,16 @@ obj-$(CONFIG_MACH_HALIBUT) += board-halibut.o devices-msm7x00.o obj-$(CONFIG_ARCH_MSM7X30) += board-msm7x30.o devices-msm7x30.o obj-$(CONFIG_ARCH_QSD8X50) += board-qsd8x50.o devices-qsd8x50.o obj-$(CONFIG_ARCH_MSM8X60) += board-msm8x60.o +obj-$(CONFIG_ARCH_MSM8960) += board-msm8960.o obj-$(CONFIG_ARCH_MSM7X30) += gpiomux-7x30.o gpiomux-v1.o gpiomux.o obj-$(CONFIG_ARCH_QSD8X50) += gpiomux-8x50.o gpiomux-v1.o gpiomux.o obj-$(CONFIG_ARCH_MSM8X60) += gpiomux-8x60.o gpiomux-v2.o gpiomux.o ifdef CONFIG_MSM_V2_TLMM +ifndef CONFIG_ARCH_MSM8960 +# TODO: TLMM Mapping issues need to be resolved obj-y += gpio-v2.o +endif else obj-y += gpio.o endif diff --git a/arch/arm/mach-msm/board-msm8960.c b/arch/arm/mach-msm/board-msm8960.c new file mode 100644 index 0000000..90efd54 --- /dev/null +++ b/arch/arm/mach-msm/board-msm8960.c @@ -0,0 +1,58 @@ +/* Copyright (c) 2011, Code Aurora Forum. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ +#include +#include +#include +#include + +#include +#include +#include + +#include +#include + +static void __init msm8960_map_io(void) +{ + msm_map_msm8960_io(); +} + +static void __init msm8960_init_irq(void) +{ + unsigned int i; + gic_init(0, GIC_PPI_START, MSM_QGIC_DIST_BASE, + (void *)MSM_QGIC_CPU_BASE); + + /* Edge trigger PPIs except AVS_SVICINT and AVS_SVICINTSWDONE */ + writel(0xFFFFD7FF, MSM_QGIC_DIST_BASE + GIC_DIST_CONFIG + 4); + + /* FIXME: Not installing AVS_SVICINT and AVS_SVICINTSWDONE yet + * as they are configured as level, which does not play nice with + * handle_percpu_irq. + */ + for (i = GIC_PPI_START; i < GIC_SPI_START; i++) { + if (i != AVS_SVICINT && i != AVS_SVICINTSWDONE) + set_irq_handler(i, handle_percpu_irq); + } +} + +MACHINE_START(MSM8960_SIM, "QCT MSM8960 SIMULATOR") + .map_io = msm8960_map_io, + .init_irq = msm8960_init_irq, + .timer = &msm_timer, +MACHINE_END -- cgit v0.10.2 From 50ede4e39aa5b61685ca87f58422478b1a538ca8 Mon Sep 17 00:00:00 2001 From: Stepan Moskovchenko Date: Mon, 13 Dec 2010 18:12:19 -0800 Subject: msm: Support for the MSM8960 RUMI3 target Add the machine record, init code, and build support for the MSM8960 RUMI3. Signed-off-by: Stepan Moskovchenko Signed-off-by: David Brown diff --git a/arch/arm/mach-msm/Kconfig b/arch/arm/mach-msm/Kconfig index adca96c..df9d74e 100644 --- a/arch/arm/mach-msm/Kconfig +++ b/arch/arm/mach-msm/Kconfig @@ -51,7 +51,7 @@ config ARCH_MSM8X60 config ARCH_MSM8960 bool "MSM8960" select ARCH_MSM_SCORPIONMP - select MACH_MSM8960_SIM + select MACH_MSM8960_SIM if (!MACH_MSM8960_RUMI3) select ARM_GIC select CPU_V7 select MSM_V2_TLMM @@ -141,6 +141,12 @@ config MACH_MSM8960_SIM help Support for the Qualcomm MSM8960 simulator. +config MACH_MSM8960_RUMI3 + depends on ARCH_MSM8960 + bool "MSM8960 RUMI3" + help + Support for the Qualcomm MSM8960 RUMI3 emulator. + endmenu config IOMMU_PGTABLES_L2 diff --git a/arch/arm/mach-msm/board-msm8960.c b/arch/arm/mach-msm/board-msm8960.c index 90efd54..2b09573 100644 --- a/arch/arm/mach-msm/board-msm8960.c +++ b/arch/arm/mach-msm/board-msm8960.c @@ -41,6 +41,9 @@ static void __init msm8960_init_irq(void) /* Edge trigger PPIs except AVS_SVICINT and AVS_SVICINTSWDONE */ writel(0xFFFFD7FF, MSM_QGIC_DIST_BASE + GIC_DIST_CONFIG + 4); + if (machine_is_msm8960_rumi3()) + writel(0x0000FFFF, MSM_QGIC_DIST_BASE + GIC_DIST_ENABLE_SET); + /* FIXME: Not installing AVS_SVICINT and AVS_SVICINTSWDONE yet * as they are configured as level, which does not play nice with * handle_percpu_irq. @@ -56,3 +59,10 @@ MACHINE_START(MSM8960_SIM, "QCT MSM8960 SIMULATOR") .init_irq = msm8960_init_irq, .timer = &msm_timer, MACHINE_END + +MACHINE_START(MSM8960_RUMI3, "QCT MSM8960 RUMI3") + .map_io = msm8960_map_io, + .init_irq = msm8960_init_irq, + .timer = &msm_timer, +MACHINE_END + -- cgit v0.10.2 From d41cb8c95681345ded5ef1e78d235d06d68baee2 Mon Sep 17 00:00:00 2001 From: Stepan Moskovchenko Date: Mon, 17 Jan 2011 20:33:32 -0800 Subject: msm: Add name field to UART resources Add a name field to the I/O resources for the UARTs on MSM targets in preparation for updates to the msm_serial driver. The driver assumed there is one I/O resource per UART, which is not the case on all targets. Signed-off-by: Stepan Moskovchenko Signed-off-by: David Brown diff --git a/arch/arm/mach-msm/devices-msm7x00.c b/arch/arm/mach-msm/devices-msm7x00.c index fb548a8..2549fb2 100644 --- a/arch/arm/mach-msm/devices-msm7x00.c +++ b/arch/arm/mach-msm/devices-msm7x00.c @@ -38,6 +38,7 @@ static struct resource resources_uart1[] = { .start = MSM_UART1_PHYS, .end = MSM_UART1_PHYS + MSM_UART1_SIZE - 1, .flags = IORESOURCE_MEM, + .name = "uart_resource" }, }; @@ -51,6 +52,7 @@ static struct resource resources_uart2[] = { .start = MSM_UART2_PHYS, .end = MSM_UART2_PHYS + MSM_UART2_SIZE - 1, .flags = IORESOURCE_MEM, + .name = "uart_resource" }, }; @@ -64,6 +66,7 @@ static struct resource resources_uart3[] = { .start = MSM_UART3_PHYS, .end = MSM_UART3_PHYS + MSM_UART3_SIZE - 1, .flags = IORESOURCE_MEM, + .name = "uart_resource" }, }; diff --git a/arch/arm/mach-msm/devices-msm7x30.c b/arch/arm/mach-msm/devices-msm7x30.c index 4e9a0ab..d4c7afc 100644 --- a/arch/arm/mach-msm/devices-msm7x30.c +++ b/arch/arm/mach-msm/devices-msm7x30.c @@ -1,6 +1,6 @@ /* * Copyright (C) 2008 Google, Inc. - * Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved. + * Copyright (c) 2008-2011, Code Aurora Forum. All rights reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and @@ -41,6 +41,7 @@ static struct resource resources_uart2[] = { .start = MSM_UART2_PHYS, .end = MSM_UART2_PHYS + MSM_UART2_SIZE - 1, .flags = IORESOURCE_MEM, + .name = "uart_resource" }, }; diff --git a/arch/arm/mach-msm/devices-qsd8x50.c b/arch/arm/mach-msm/devices-qsd8x50.c index a4b798f..93bddac 100644 --- a/arch/arm/mach-msm/devices-qsd8x50.c +++ b/arch/arm/mach-msm/devices-qsd8x50.c @@ -1,6 +1,6 @@ /* * Copyright (C) 2008 Google, Inc. - * Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved. + * Copyright (c) 2008-2011, Code Aurora Forum. All rights reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and @@ -38,6 +38,7 @@ static struct resource resources_uart3[] = { .start = MSM_UART3_PHYS, .end = MSM_UART3_PHYS + MSM_UART3_SIZE - 1, .flags = IORESOURCE_MEM, + .name = "uart_resource" }, }; -- cgit v0.10.2 From ec8f29e70edceb93c021148a99a5c3889cdc1b08 Mon Sep 17 00:00:00 2001 From: Stepan Moskovchenko Date: Tue, 21 Dec 2010 12:38:05 -0800 Subject: serial: msm: Add support for UARTDM cores Add support for the next-generation version of the MSM UART to the msm_serial driver. This version of the hardware is similar to the original version, but has some DMA capabilities that are used in PIO mode in this driver. Signed-off-by: Stepan Moskovchenko Signed-off-by: David Brown diff --git a/drivers/serial/msm_serial.c b/drivers/serial/msm_serial.c index 8e43a7b..bfee9b4 100644 --- a/drivers/serial/msm_serial.c +++ b/drivers/serial/msm_serial.c @@ -3,6 +3,7 @@ * * Copyright (C) 2007 Google, Inc. * Author: Robert Love + * Copyright (c) 2011, Code Aurora Forum. All rights reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and @@ -31,6 +32,7 @@ #include #include #include +#include #include "msm_serial.h" @@ -38,9 +40,20 @@ struct msm_port { struct uart_port uart; char name[16]; struct clk *clk; + struct clk *pclk; unsigned int imr; + unsigned int *gsbi_base; + int is_uartdm; + unsigned int old_snap_state; }; +static inline void wait_for_xmitr(struct uart_port *port, int bits) +{ + if (!(msm_read(port, UART_SR) & UART_SR_TX_EMPTY)) + while ((msm_read(port, UART_ISR) & bits) != bits) + cpu_relax(); +} + static void msm_stop_tx(struct uart_port *port) { struct msm_port *msm_port = UART_TO_MSM(port); @@ -73,6 +86,61 @@ static void msm_enable_ms(struct uart_port *port) msm_write(port, msm_port->imr, UART_IMR); } +static void handle_rx_dm(struct uart_port *port, unsigned int misr) +{ + struct tty_struct *tty = port->state->port.tty; + unsigned int sr; + int count = 0; + struct msm_port *msm_port = UART_TO_MSM(port); + + if ((msm_read(port, UART_SR) & UART_SR_OVERRUN)) { + port->icount.overrun++; + tty_insert_flip_char(tty, 0, TTY_OVERRUN); + msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR); + } + + if (misr & UART_IMR_RXSTALE) { + count = msm_read(port, UARTDM_RX_TOTAL_SNAP) - + msm_port->old_snap_state; + msm_port->old_snap_state = 0; + } else { + count = 4 * (msm_read(port, UART_RFWR)); + msm_port->old_snap_state += count; + } + + /* TODO: Precise error reporting */ + + port->icount.rx += count; + + while (count > 0) { + unsigned int c; + + sr = msm_read(port, UART_SR); + if ((sr & UART_SR_RX_READY) == 0) { + msm_port->old_snap_state -= count; + break; + } + c = msm_read(port, UARTDM_RF); + if (sr & UART_SR_RX_BREAK) { + port->icount.brk++; + if (uart_handle_break(port)) + continue; + } else if (sr & UART_SR_PAR_FRAME_ERR) + port->icount.frame++; + + /* TODO: handle sysrq */ + tty_insert_flip_string(tty, (char *) &c, + (count > 4) ? 4 : count); + count -= 4; + } + + tty_flip_buffer_push(tty); + if (misr & (UART_IMR_RXSTALE)) + msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR); + msm_write(port, 0xFFFFFF, UARTDM_DMRX); + msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR); +} + static void handle_rx(struct uart_port *port) { struct tty_struct *tty = port->state->port.tty; @@ -121,6 +189,12 @@ static void handle_rx(struct uart_port *port) tty_flip_buffer_push(tty); } +static void reset_dm_count(struct uart_port *port) +{ + wait_for_xmitr(port, UART_ISR_TX_READY); + msm_write(port, 1, UARTDM_NCF_TX); +} + static void handle_tx(struct uart_port *port) { struct circ_buf *xmit = &port->state->xmit; @@ -128,11 +202,18 @@ static void handle_tx(struct uart_port *port) int sent_tx; if (port->x_char) { - msm_write(port, port->x_char, UART_TF); + if (msm_port->is_uartdm) + reset_dm_count(port); + + msm_write(port, port->x_char, + msm_port->is_uartdm ? UARTDM_TF : UART_TF); port->icount.tx++; port->x_char = 0; } + if (msm_port->is_uartdm) + reset_dm_count(port); + while (msm_read(port, UART_SR) & UART_SR_TX_READY) { if (uart_circ_empty(xmit)) { /* disable tx interrupts */ @@ -140,8 +221,11 @@ static void handle_tx(struct uart_port *port) msm_write(port, msm_port->imr, UART_IMR); break; } + msm_write(port, xmit->buf[xmit->tail], + msm_port->is_uartdm ? UARTDM_TF : UART_TF); - msm_write(port, xmit->buf[xmit->tail], UART_TF); + if (msm_port->is_uartdm) + reset_dm_count(port); xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); port->icount.tx++; @@ -169,8 +253,12 @@ static irqreturn_t msm_irq(int irq, void *dev_id) misr = msm_read(port, UART_MISR); msm_write(port, 0, UART_IMR); /* disable interrupt */ - if (misr & (UART_IMR_RXLEV | UART_IMR_RXSTALE)) - handle_rx(port); + if (misr & (UART_IMR_RXLEV | UART_IMR_RXSTALE)) { + if (msm_port->is_uartdm) + handle_rx_dm(port, misr); + else + handle_rx(port); + } if (misr & UART_IMR_TXLEV) handle_tx(port); if (misr & UART_IMR_DELTA_CTS) @@ -192,10 +280,21 @@ static unsigned int msm_get_mctrl(struct uart_port *port) return TIOCM_CAR | TIOCM_CTS | TIOCM_DSR | TIOCM_RTS; } -static void msm_set_mctrl(struct uart_port *port, unsigned int mctrl) + +static void msm_reset(struct uart_port *port) { - unsigned int mr; + /* reset everything */ + msm_write(port, UART_CR_CMD_RESET_RX, UART_CR); + msm_write(port, UART_CR_CMD_RESET_TX, UART_CR); + msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR); + msm_write(port, UART_CR_CMD_RESET_BREAK_INT, UART_CR); + msm_write(port, UART_CR_CMD_RESET_CTS, UART_CR); + msm_write(port, UART_CR_CMD_SET_RFR, UART_CR); +} +void msm_set_mctrl(struct uart_port *port, unsigned int mctrl) +{ + unsigned int mr; mr = msm_read(port, UART_MR1); if (!(mctrl & TIOCM_RTS)) { @@ -219,6 +318,7 @@ static void msm_break_ctl(struct uart_port *port, int break_ctl) static int msm_set_baud_rate(struct uart_port *port, unsigned int baud) { unsigned int baud_code, rxstale, watermark; + struct msm_port *msm_port = UART_TO_MSM(port); switch (baud) { case 300: @@ -273,6 +373,9 @@ static int msm_set_baud_rate(struct uart_port *port, unsigned int baud) break; } + if (msm_port->is_uartdm) + msm_write(port, UART_CR_CMD_RESET_RX, UART_CR); + msm_write(port, baud_code, UART_CSR); /* RX stale watermark */ @@ -288,25 +391,23 @@ static int msm_set_baud_rate(struct uart_port *port, unsigned int baud) /* set TX watermark */ msm_write(port, 10, UART_TFWR); + if (msm_port->is_uartdm) { + msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR); + msm_write(port, 0xFFFFFF, UARTDM_DMRX); + msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR); + } + return baud; } -static void msm_reset(struct uart_port *port) -{ - /* reset everything */ - msm_write(port, UART_CR_CMD_RESET_RX, UART_CR); - msm_write(port, UART_CR_CMD_RESET_TX, UART_CR); - msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR); - msm_write(port, UART_CR_CMD_RESET_BREAK_INT, UART_CR); - msm_write(port, UART_CR_CMD_RESET_CTS, UART_CR); - msm_write(port, UART_CR_CMD_SET_RFR, UART_CR); -} static void msm_init_clock(struct uart_port *port) { struct msm_port *msm_port = UART_TO_MSM(port); clk_enable(msm_port->clk); + if (!IS_ERR(msm_port->pclk)) + clk_enable(msm_port->pclk); msm_serial_set_mnd_regs(port); } @@ -347,15 +448,31 @@ static int msm_startup(struct uart_port *port) msm_write(port, data, UART_IPR); } - msm_reset(port); + data = 0; + if (!port->cons || (port->cons && !(port->cons->flags & CON_ENABLED))) { + msm_write(port, UART_CR_CMD_PROTECTION_EN, UART_CR); + msm_reset(port); + data = UART_CR_TX_ENABLE; + } + + data |= UART_CR_RX_ENABLE; + msm_write(port, data, UART_CR); /* enable TX & RX */ - msm_write(port, 0x05, UART_CR); /* enable TX & RX */ + /* Make sure IPR is not 0 to start with*/ + if (msm_port->is_uartdm) + msm_write(port, UART_IPR_STALE_LSB, UART_IPR); /* turn on RX and CTS interrupts */ msm_port->imr = UART_IMR_RXLEV | UART_IMR_RXSTALE | UART_IMR_CURRENT_CTS; - msm_write(port, msm_port->imr, UART_IMR); + if (msm_port->is_uartdm) { + msm_write(port, 0xFFFFFF, UARTDM_DMRX); + msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR); + msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR); + } + + msm_write(port, msm_port->imr, UART_IMR); return 0; } @@ -384,7 +501,7 @@ static void msm_set_termios(struct uart_port *port, struct ktermios *termios, baud = msm_set_baud_rate(port, baud); if (tty_termios_baud_rate(termios)) tty_termios_encode_baud_rate(termios, baud, baud); - + /* calculate parity */ mr = msm_read(port, UART_MR2); mr &= ~UART_MR2_PARITY_MODE; @@ -454,48 +571,105 @@ static const char *msm_type(struct uart_port *port) static void msm_release_port(struct uart_port *port) { struct platform_device *pdev = to_platform_device(port->dev); - struct resource *resource; + struct msm_port *msm_port = UART_TO_MSM(port); + struct resource *uart_resource; + struct resource *gsbi_resource; resource_size_t size; - resource = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (unlikely(!resource)) + uart_resource = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (unlikely(!uart_resource)) return; - size = resource->end - resource->start + 1; + size = resource_size(uart_resource); release_mem_region(port->mapbase, size); iounmap(port->membase); port->membase = NULL; + + if (msm_port->gsbi_base) { + iowrite32(GSBI_PROTOCOL_IDLE, msm_port->gsbi_base + + GSBI_CONTROL); + + gsbi_resource = platform_get_resource_byname(pdev, + IORESOURCE_MEM, + "gsbi_resource"); + + if (unlikely(!gsbi_resource)) + return; + + size = resource_size(gsbi_resource); + release_mem_region(gsbi_resource->start, size); + iounmap(msm_port->gsbi_base); + msm_port->gsbi_base = NULL; + } } static int msm_request_port(struct uart_port *port) { + struct msm_port *msm_port = UART_TO_MSM(port); struct platform_device *pdev = to_platform_device(port->dev); - struct resource *resource; + struct resource *uart_resource; + struct resource *gsbi_resource; resource_size_t size; + int ret; - resource = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (unlikely(!resource)) + uart_resource = platform_get_resource_byname(pdev, IORESOURCE_MEM, + "uart_resource"); + if (unlikely(!uart_resource)) return -ENXIO; - size = resource->end - resource->start + 1; - if (unlikely(!request_mem_region(port->mapbase, size, "msm_serial"))) + size = resource_size(uart_resource); + + if (!request_mem_region(port->mapbase, size, "msm_serial")) return -EBUSY; port->membase = ioremap(port->mapbase, size); if (!port->membase) { - release_mem_region(port->mapbase, size); - return -EBUSY; + ret = -EBUSY; + goto fail_release_port; + } + + gsbi_resource = platform_get_resource_byname(pdev, IORESOURCE_MEM, + "gsbi_resource"); + /* Is this a GSBI-based port? */ + if (gsbi_resource) { + size = resource_size(gsbi_resource); + + if (!request_mem_region(gsbi_resource->start, size, + "msm_serial")) { + ret = -EBUSY; + goto fail_release_port; + } + + msm_port->gsbi_base = ioremap(gsbi_resource->start, size); + if (!msm_port->gsbi_base) { + ret = -EBUSY; + goto fail_release_gsbi; + } } return 0; + +fail_release_gsbi: + release_mem_region(gsbi_resource->start, size); +fail_release_port: + release_mem_region(port->mapbase, size); + return ret; } static void msm_config_port(struct uart_port *port, int flags) { + struct msm_port *msm_port = UART_TO_MSM(port); + int ret; if (flags & UART_CONFIG_TYPE) { port->type = PORT_MSM; - msm_request_port(port); + ret = msm_request_port(port); + if (ret) + return; } + + if (msm_port->is_uartdm) + iowrite32(GSBI_PROTOCOL_UART, msm_port->gsbi_base + + GSBI_CONTROL); } static int msm_verify_port(struct uart_port *port, struct serial_struct *ser) @@ -515,9 +689,13 @@ static void msm_power(struct uart_port *port, unsigned int state, switch (state) { case 0: clk_enable(msm_port->clk); + if (!IS_ERR(msm_port->pclk)) + clk_enable(msm_port->pclk); break; case 3: clk_disable(msm_port->clk); + if (!IS_ERR(msm_port->pclk)) + clk_disable(msm_port->pclk); break; default: printk(KERN_ERR "msm_serial: Unknown PM state %d\n", state); @@ -550,7 +728,7 @@ static struct msm_port msm_uart_ports[] = { .iotype = UPIO_MEM, .ops = &msm_uart_pops, .flags = UPF_BOOT_AUTOCONF, - .fifosize = 512, + .fifosize = 64, .line = 0, }, }, @@ -559,7 +737,7 @@ static struct msm_port msm_uart_ports[] = { .iotype = UPIO_MEM, .ops = &msm_uart_pops, .flags = UPF_BOOT_AUTOCONF, - .fifosize = 512, + .fifosize = 64, .line = 1, }, }, @@ -585,9 +763,14 @@ static inline struct uart_port *get_port_from_line(unsigned int line) static void msm_console_putchar(struct uart_port *port, int c) { + struct msm_port *msm_port = UART_TO_MSM(port); + + if (msm_port->is_uartdm) + reset_dm_count(port); + while (!(msm_read(port, UART_SR) & UART_SR_TX_READY)) ; - msm_write(port, c, UART_TF); + msm_write(port, c, msm_port->is_uartdm ? UARTDM_TF : UART_TF); } static void msm_console_write(struct console *co, const char *s, @@ -609,12 +792,14 @@ static void msm_console_write(struct console *co, const char *s, static int __init msm_console_setup(struct console *co, char *options) { struct uart_port *port; + struct msm_port *msm_port; int baud, flow, bits, parity; if (unlikely(co->index >= UART_NR || co->index < 0)) return -ENXIO; port = get_port_from_line(co->index); + msm_port = UART_TO_MSM(port); if (unlikely(!port->membase)) return -ENXIO; @@ -638,6 +823,11 @@ static int __init msm_console_setup(struct console *co, char *options) msm_reset(port); + if (msm_port->is_uartdm) { + msm_write(port, UART_CR_CMD_PROTECTION_EN, UART_CR); + msm_write(port, UART_CR_TX_ENABLE, UART_CR); + } + printk(KERN_INFO "msm_serial: console setup on port #%d\n", port->line); return uart_set_options(port, co, baud, parity, bits, flow); @@ -685,14 +875,32 @@ static int __init msm_serial_probe(struct platform_device *pdev) port->dev = &pdev->dev; msm_port = UART_TO_MSM(port); - msm_port->clk = clk_get(&pdev->dev, "uart_clk"); - if (IS_ERR(msm_port->clk)) - return PTR_ERR(msm_port->clk); + if (platform_get_resource_byname(pdev, IORESOURCE_MEM, "gsbi_resource")) + msm_port->is_uartdm = 1; + else + msm_port->is_uartdm = 0; + + if (msm_port->is_uartdm) { + msm_port->clk = clk_get(&pdev->dev, "gsbi_uart_clk"); + msm_port->pclk = clk_get(&pdev->dev, "gsbi_pclk"); + } else { + msm_port->clk = clk_get(&pdev->dev, "uart_clk"); + msm_port->pclk = ERR_PTR(-ENOENT); + } + + if (unlikely(IS_ERR(msm_port->clk) || (IS_ERR(msm_port->pclk) && + msm_port->is_uartdm))) + return PTR_ERR(msm_port->clk); + + if (msm_port->is_uartdm) + clk_set_rate(msm_port->clk, 7372800); + port->uartclk = clk_get_rate(msm_port->clk); printk(KERN_INFO "uartclk = %d\n", port->uartclk); - resource = platform_get_resource(pdev, IORESOURCE_MEM, 0); + resource = platform_get_resource_byname(pdev, IORESOURCE_MEM, + "uart_resource"); if (unlikely(!resource)) return -ENXIO; port->mapbase = resource->start; diff --git a/drivers/serial/msm_serial.h b/drivers/serial/msm_serial.h index f6ca9ca..9b8dc5d 100644 --- a/drivers/serial/msm_serial.h +++ b/drivers/serial/msm_serial.h @@ -3,6 +3,7 @@ * * Copyright (C) 2007 Google, Inc. * Author: Robert Love + * Copyright (c) 2011, Code Aurora Forum. All rights reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and @@ -54,6 +55,7 @@ #define UART_CSR_300 0x22 #define UART_TF 0x000C +#define UARTDM_TF 0x0070 #define UART_CR 0x0010 #define UART_CR_CMD_NULL (0 << 4) @@ -64,14 +66,17 @@ #define UART_CR_CMD_START_BREAK (5 << 4) #define UART_CR_CMD_STOP_BREAK (6 << 4) #define UART_CR_CMD_RESET_CTS (7 << 4) +#define UART_CR_CMD_RESET_STALE_INT (8 << 4) #define UART_CR_CMD_PACKET_MODE (9 << 4) #define UART_CR_CMD_MODE_RESET (12 << 4) #define UART_CR_CMD_SET_RFR (13 << 4) #define UART_CR_CMD_RESET_RFR (14 << 4) +#define UART_CR_CMD_PROTECTION_EN (16 << 4) +#define UART_CR_CMD_STALE_EVENT_ENABLE (80 << 4) #define UART_CR_TX_DISABLE (1 << 3) -#define UART_CR_TX_ENABLE (1 << 3) -#define UART_CR_RX_DISABLE (1 << 3) -#define UART_CR_RX_ENABLE (1 << 3) +#define UART_CR_TX_ENABLE (1 << 2) +#define UART_CR_RX_DISABLE (1 << 1) +#define UART_CR_RX_ENABLE (1 << 0) #define UART_IMR 0x0014 #define UART_IMR_TXLEV (1 << 0) @@ -110,9 +115,20 @@ #define UART_SR_RX_FULL (1 << 1) #define UART_SR_RX_READY (1 << 0) -#define UART_RF 0x000C -#define UART_MISR 0x0010 -#define UART_ISR 0x0014 +#define UART_RF 0x000C +#define UARTDM_RF 0x0070 +#define UART_MISR 0x0010 +#define UART_ISR 0x0014 +#define UART_ISR_TX_READY (1 << 7) + +#define GSBI_CONTROL 0x0 +#define GSBI_PROTOCOL_CODE 0x30 +#define GSBI_PROTOCOL_UART 0x40 +#define GSBI_PROTOCOL_IDLE 0x0 + +#define UARTDM_DMRX 0x34 +#define UARTDM_NCF_TX 0x40 +#define UARTDM_RX_TOTAL_SNAP 0x38 #define UART_TO_MSM(uart_port) ((struct msm_port *) uart_port) -- cgit v0.10.2 From 7a89248a47d201e6ade2daddd79b0fd902cad400 Mon Sep 17 00:00:00 2001 From: Sahitya Tummala Date: Tue, 18 Jan 2011 11:22:49 +0530 Subject: mmc: msm_sdcc: Add gpio handling function to driver Configure SDCC GPIOs when the host is powered up or powered off. Signed-off-by: Sahitya Tummala diff --git a/arch/arm/mach-msm/include/mach/mmc.h b/arch/arm/mach-msm/include/mach/mmc.h index d54b6b0..5631b51 100644 --- a/arch/arm/mach-msm/include/mach/mmc.h +++ b/arch/arm/mach-msm/include/mach/mmc.h @@ -15,12 +15,23 @@ struct embedded_sdio_data { int num_funcs; }; +struct msm_mmc_gpio { + unsigned no; + const char *name; +}; + +struct msm_mmc_gpio_data { + struct msm_mmc_gpio *gpio; + u8 size; +}; + struct msm_mmc_platform_data { unsigned int ocr_mask; /* available voltages */ u32 (*translate_vdd)(struct device *, unsigned int); unsigned int (*status)(struct device *); struct embedded_sdio_data *embedded_sdio; int (*register_status_notify)(void (*callback)(int card_present, void *dev_id), void *dev_id); + struct msm_mmc_gpio_data *gpio_data; }; #endif diff --git a/drivers/mmc/host/msm_sdcc.c b/drivers/mmc/host/msm_sdcc.c index 153ab97..97c9b363 100644 --- a/drivers/mmc/host/msm_sdcc.c +++ b/drivers/mmc/host/msm_sdcc.c @@ -36,6 +36,7 @@ #include #include #include +#include #include #include @@ -941,6 +942,38 @@ msmsdcc_request(struct mmc_host *mmc, struct mmc_request *mrq) spin_unlock_irqrestore(&host->lock, flags); } +static void msmsdcc_setup_gpio(struct msmsdcc_host *host, bool enable) +{ + struct msm_mmc_gpio_data *curr; + int i, rc = 0; + + if (!host->plat->gpio_data && host->gpio_config_status == enable) + return; + + curr = host->plat->gpio_data; + for (i = 0; i < curr->size; i++) { + if (enable) { + rc = gpio_request(curr->gpio[i].no, + curr->gpio[i].name); + if (rc) { + pr_err("%s: gpio_request(%d, %s) failed %d\n", + mmc_hostname(host->mmc), + curr->gpio[i].no, + curr->gpio[i].name, rc); + goto free_gpios; + } + } else { + gpio_free(curr->gpio[i].no); + } + } + host->gpio_config_status = enable; + return; + +free_gpios: + for (; i >= 0; i--) + gpio_free(curr->gpio[i].no); +} + static void msmsdcc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) { @@ -953,6 +986,8 @@ msmsdcc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) msmsdcc_enable_clocks(host); + spin_unlock_irqrestore(&host->lock, flags); + if (ios->clock) { if (ios->clock != host->clk_rate) { rc = clk_set_rate(host->clk, ios->clock); @@ -979,9 +1014,11 @@ msmsdcc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) switch (ios->power_mode) { case MMC_POWER_OFF: + msmsdcc_setup_gpio(host, false); break; case MMC_POWER_UP: pwr |= MCI_PWR_UP; + msmsdcc_setup_gpio(host, true); break; case MMC_POWER_ON: pwr |= MCI_PWR_ON; @@ -998,9 +1035,10 @@ msmsdcc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) msmsdcc_writel(host, pwr, MMCIPOWER); } #if BUSCLK_PWRSAVE + spin_lock_irqsave(&host->lock, flags); msmsdcc_disable_clocks(host, 1); -#endif spin_unlock_irqrestore(&host->lock, flags); +#endif } static void msmsdcc_enable_sdio_irq(struct mmc_host *mmc, int enable) diff --git a/drivers/mmc/host/msm_sdcc.h b/drivers/mmc/host/msm_sdcc.h index 939557a..42d7bbc 100644 --- a/drivers/mmc/host/msm_sdcc.h +++ b/drivers/mmc/host/msm_sdcc.h @@ -243,6 +243,7 @@ struct msmsdcc_host { unsigned int cmd_datactrl; struct mmc_command *cmd_cmd; u32 cmd_c; + bool gpio_config_status; bool prog_scan; bool prog_enable; -- cgit v0.10.2 From 8b4d95fc76b85696c508f316810a6fbc15a7b8c5 Mon Sep 17 00:00:00 2001 From: Sahitya Tummala Date: Tue, 18 Jan 2011 11:22:50 +0530 Subject: msm: 8x50: Add initial support for SDCC Signed-off-by: Sahitya Tummala diff --git a/arch/arm/mach-msm/board-qsd8x50.c b/arch/arm/mach-msm/board-qsd8x50.c index 2e83913..12863f7 100644 --- a/arch/arm/mach-msm/board-qsd8x50.c +++ b/arch/arm/mach-msm/board-qsd8x50.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2008-2009, Code Aurora Forum. All rights reserved. +/* Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -21,6 +21,7 @@ #include #include #include +#include #include #include @@ -31,6 +32,8 @@ #include #include #include +#include +#include #include "devices.h" @@ -95,6 +98,81 @@ static struct platform_device *devices[] __initdata = { &msm_device_hsusb_host, }; +static struct msm_mmc_gpio sdc1_gpio_cfg[] = { + {51, "sdc1_dat_3"}, + {52, "sdc1_dat_2"}, + {53, "sdc1_dat_1"}, + {54, "sdc1_dat_0"}, + {55, "sdc1_cmd"}, + {56, "sdc1_clk"} +}; + +static struct vreg *vreg_mmc; +static unsigned long vreg_sts; + +static uint32_t msm_sdcc_setup_power(struct device *dv, unsigned int vdd) +{ + int rc = 0; + struct platform_device *pdev; + + pdev = container_of(dv, struct platform_device, dev); + + if (vdd == 0) { + if (!vreg_sts) + return 0; + + clear_bit(pdev->id, &vreg_sts); + + if (!vreg_sts) { + rc = vreg_disable(vreg_mmc); + if (rc) + pr_err("vreg_mmc disable failed for slot " + "%d: %d\n", pdev->id, rc); + } + return 0; + } + + if (!vreg_sts) { + rc = vreg_set_level(vreg_mmc, 2900); + if (rc) + pr_err("vreg_mmc set level failed for slot %d: %d\n", + pdev->id, rc); + rc = vreg_enable(vreg_mmc); + if (rc) + pr_err("vreg_mmc enable failed for slot %d: %d\n", + pdev->id, rc); + } + set_bit(pdev->id, &vreg_sts); + return 0; +} + +static struct msm_mmc_gpio_data sdc1_gpio = { + .gpio = sdc1_gpio_cfg, + .size = ARRAY_SIZE(sdc1_gpio_cfg), +}; + +static struct msm_mmc_platform_data qsd8x50_sdc1_data = { + .ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29, + .translate_vdd = msm_sdcc_setup_power, + .gpio_data = &sdc1_gpio, +}; + +static void __init qsd8x50_init_mmc(void) +{ + if (machine_is_qsd8x50_ffa() || machine_is_qsd8x50a_ffa()) + vreg_mmc = vreg_get(NULL, "gp6"); + else + vreg_mmc = vreg_get(NULL, "gp5"); + + if (IS_ERR(vreg_mmc)) { + pr_err("vreg get for vreg_mmc failed (%ld)\n", + PTR_ERR(vreg_mmc)); + return; + } + + msm_add_sdcc(1, &qsd8x50_sdc1_data, 0, 0); +} + static void __init qsd8x50_map_io(void) { msm_map_qsd8x50_io(); @@ -113,6 +191,7 @@ static void __init qsd8x50_init(void) msm_device_hsusb.dev.parent = &msm_device_otg.dev; msm_device_hsusb_host.dev.parent = &msm_device_otg.dev; platform_add_devices(devices, ARRAY_SIZE(devices)); + qsd8x50_init_mmc(); } MACHINE_START(QSD8X50_SURF, "QCT QSD8X50 SURF") diff --git a/arch/arm/mach-msm/devices-qsd8x50.c b/arch/arm/mach-msm/devices-qsd8x50.c index a4b798f..b1a8f0f 100644 --- a/arch/arm/mach-msm/devices-qsd8x50.c +++ b/arch/arm/mach-msm/devices-qsd8x50.c @@ -124,6 +124,194 @@ struct platform_device msm_device_hsusb_host = { }, }; +static struct resource resources_sdc1[] = { + { + .start = MSM_SDC1_PHYS, + .end = MSM_SDC1_PHYS + MSM_SDC1_SIZE - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = INT_SDC1_0, + .end = INT_SDC1_0, + .flags = IORESOURCE_IRQ, + .name = "cmd_irq", + }, + { + .start = INT_SDC1_1, + .end = INT_SDC1_1, + .flags = IORESOURCE_IRQ, + .name = "pio_irq", + }, + { + .flags = IORESOURCE_IRQ | IORESOURCE_DISABLED, + .name = "status_irq" + }, + { + .start = 8, + .end = 8, + .flags = IORESOURCE_DMA, + }, +}; + +static struct resource resources_sdc2[] = { + { + .start = MSM_SDC2_PHYS, + .end = MSM_SDC2_PHYS + MSM_SDC2_SIZE - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = INT_SDC2_0, + .end = INT_SDC2_0, + .flags = IORESOURCE_IRQ, + .name = "cmd_irq", + }, + { + .start = INT_SDC2_1, + .end = INT_SDC2_1, + .flags = IORESOURCE_IRQ, + .name = "pio_irq", + }, + { + .flags = IORESOURCE_IRQ | IORESOURCE_DISABLED, + .name = "status_irq" + }, + { + .start = 8, + .end = 8, + .flags = IORESOURCE_DMA, + }, +}; + +static struct resource resources_sdc3[] = { + { + .start = MSM_SDC3_PHYS, + .end = MSM_SDC3_PHYS + MSM_SDC3_SIZE - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = INT_SDC3_0, + .end = INT_SDC3_0, + .flags = IORESOURCE_IRQ, + .name = "cmd_irq", + }, + { + .start = INT_SDC3_1, + .end = INT_SDC3_1, + .flags = IORESOURCE_IRQ, + .name = "pio_irq", + }, + { + .flags = IORESOURCE_IRQ | IORESOURCE_DISABLED, + .name = "status_irq" + }, + { + .start = 8, + .end = 8, + .flags = IORESOURCE_DMA, + }, +}; + +static struct resource resources_sdc4[] = { + { + .start = MSM_SDC4_PHYS, + .end = MSM_SDC4_PHYS + MSM_SDC4_SIZE - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = INT_SDC4_0, + .end = INT_SDC4_0, + .flags = IORESOURCE_IRQ, + .name = "cmd_irq", + }, + { + .start = INT_SDC4_1, + .end = INT_SDC4_1, + .flags = IORESOURCE_IRQ, + .name = "pio_irq", + }, + { + .flags = IORESOURCE_IRQ | IORESOURCE_DISABLED, + .name = "status_irq" + }, + { + .start = 8, + .end = 8, + .flags = IORESOURCE_DMA, + }, +}; + +struct platform_device msm_device_sdc1 = { + .name = "msm_sdcc", + .id = 1, + .num_resources = ARRAY_SIZE(resources_sdc1), + .resource = resources_sdc1, + .dev = { + .coherent_dma_mask = 0xffffffff, + }, +}; + +struct platform_device msm_device_sdc2 = { + .name = "msm_sdcc", + .id = 2, + .num_resources = ARRAY_SIZE(resources_sdc2), + .resource = resources_sdc2, + .dev = { + .coherent_dma_mask = 0xffffffff, + }, +}; + +struct platform_device msm_device_sdc3 = { + .name = "msm_sdcc", + .id = 3, + .num_resources = ARRAY_SIZE(resources_sdc3), + .resource = resources_sdc3, + .dev = { + .coherent_dma_mask = 0xffffffff, + }, +}; + +struct platform_device msm_device_sdc4 = { + .name = "msm_sdcc", + .id = 4, + .num_resources = ARRAY_SIZE(resources_sdc4), + .resource = resources_sdc4, + .dev = { + .coherent_dma_mask = 0xffffffff, + }, +}; + +static struct platform_device *msm_sdcc_devices[] __initdata = { + &msm_device_sdc1, + &msm_device_sdc2, + &msm_device_sdc3, + &msm_device_sdc4, +}; + +int __init msm_add_sdcc(unsigned int controller, + struct msm_mmc_platform_data *plat, + unsigned int stat_irq, unsigned long stat_irq_flags) +{ + struct platform_device *pdev; + struct resource *res; + + if (controller < 1 || controller > 4) + return -EINVAL; + + pdev = msm_sdcc_devices[controller-1]; + pdev->dev.platform_data = plat; + + res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "status_irq"); + if (!res) + return -EINVAL; + else if (stat_irq) { + res->start = res->end = stat_irq; + res->flags &= ~IORESOURCE_DISABLED; + res->flags |= stat_irq_flags; + } + + return platform_device_register(pdev); +} + struct clk msm_clocks_8x50[] = { CLK_PCOM("adm_clk", ADM_CLK, NULL, 0), CLK_PCOM("ebi1_clk", EBI1_CLK, NULL, CLK_MIN), @@ -144,6 +332,14 @@ struct clk msm_clocks_8x50[] = { CLK_PCOM("pbus_clk", PBUS_CLK, NULL, CLK_MIN), CLK_PCOM("pcm_clk", PCM_CLK, NULL, 0), CLK_PCOM("sdac_clk", SDAC_CLK, NULL, OFF), + CLK_PCOM("sdc_clk", SDC1_CLK, &msm_device_sdc1.dev, OFF), + CLK_PCOM("sdc_pclk", SDC1_P_CLK, &msm_device_sdc1.dev, OFF), + CLK_PCOM("sdc_clk", SDC2_CLK, &msm_device_sdc2.dev, OFF), + CLK_PCOM("sdc_pclk", SDC2_P_CLK, &msm_device_sdc2.dev, OFF), + CLK_PCOM("sdc_clk", SDC3_CLK, &msm_device_sdc3.dev, OFF), + CLK_PCOM("sdc_pclk", SDC3_P_CLK, &msm_device_sdc3.dev, OFF), + CLK_PCOM("sdc_clk", SDC4_CLK, &msm_device_sdc4.dev, OFF), + CLK_PCOM("sdc_pclk", SDC4_P_CLK, &msm_device_sdc4.dev, OFF), CLK_PCOM("spi_clk", SPI_CLK, NULL, 0), CLK_PCOM("tsif_clk", TSIF_CLK, NULL, 0), CLK_PCOM("tsif_ref_clk", TSIF_REF_CLK, NULL, 0), diff --git a/arch/arm/mach-msm/gpiomux-8x50.c b/arch/arm/mach-msm/gpiomux-8x50.c index 4406e0f..f7a4ea5 100644 --- a/arch/arm/mach-msm/gpiomux-8x50.c +++ b/arch/arm/mach-msm/gpiomux-8x50.c @@ -16,6 +16,19 @@ */ #include "gpiomux.h" +#if defined(CONFIG_MMC_MSM) || defined(CONFIG_MMC_MSM_MODULE) + #define SDCC_DAT_0_3_CMD_ACTV_CFG (GPIOMUX_VALID | GPIOMUX_PULL_UP\ + | GPIOMUX_FUNC_1 | GPIOMUX_DRV_8MA) + #define SDCC_CLK_ACTV_CFG (GPIOMUX_VALID | GPIOMUX_PULL_NONE\ + | GPIOMUX_FUNC_1 | GPIOMUX_DRV_8MA) +#else + #define SDCC_DAT_0_3_CMD_ACTV_CFG 0 + #define SDCC_CLK_ACTV_CFG 0 +#endif + +#define SDC1_SUSPEND_CONFIG (GPIOMUX_VALID | GPIOMUX_PULL_DOWN\ + | GPIOMUX_FUNC_GPIO | GPIOMUX_DRV_2MA) + struct msm_gpiomux_config msm_gpiomux_configs[GPIOMUX_NGPIOS] = { [86] = { /* UART3 RX */ .suspended = GPIOMUX_DRV_2MA | GPIOMUX_PULL_DOWN | @@ -25,4 +38,14 @@ struct msm_gpiomux_config msm_gpiomux_configs[GPIOMUX_NGPIOS] = { .suspended = GPIOMUX_DRV_2MA | GPIOMUX_PULL_DOWN | GPIOMUX_FUNC_1 | GPIOMUX_VALID, }, + /* SDC1 data[3:0] & CMD */ + [51 ... 55] = { + .active = SDCC_DAT_0_3_CMD_ACTV_CFG, + .suspended = SDC1_SUSPEND_CONFIG + }, + /* SDC1 CLK */ + [56] = { + .active = SDCC_CLK_ACTV_CFG, + .suspended = SDC1_SUSPEND_CONFIG + }, }; diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h b/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h index acc819e..732a965 100644 --- a/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h +++ b/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h @@ -132,16 +132,16 @@ #define MSM_UART2DM_PHYS 0xA0900000 -#define MSM_SDC1_PHYS 0xA0400000 +#define MSM_SDC1_PHYS 0xA0300000 #define MSM_SDC1_SIZE SZ_4K -#define MSM_SDC2_PHYS 0xA0500000 +#define MSM_SDC2_PHYS 0xA0400000 #define MSM_SDC2_SIZE SZ_4K -#define MSM_SDC3_PHYS 0xA0600000 +#define MSM_SDC3_PHYS 0xA0500000 #define MSM_SDC3_SIZE SZ_4K -#define MSM_SDC4_PHYS 0xA0700000 +#define MSM_SDC4_PHYS 0xA0600000 #define MSM_SDC4_SIZE SZ_4K #endif -- cgit v0.10.2 From ba5499ebfb7bc7859039d782099c75d92c394016 Mon Sep 17 00:00:00 2001 From: Dima Zavin Date: Mon, 10 Jan 2011 11:00:30 -0800 Subject: ARM: msm: 7x30: don't force a gpiomux table for the whole arch This is completely board specific and therefore must be provided on a per-board basis. Signed-off-by: Dima Zavin Signed-off-by: David Brown diff --git a/arch/arm/mach-msm/Makefile b/arch/arm/mach-msm/Makefile index 94195c1..f460125 100644 --- a/arch/arm/mach-msm/Makefile +++ b/arch/arm/mach-msm/Makefile @@ -30,7 +30,7 @@ obj-$(CONFIG_ARCH_MSM7X30) += board-msm7x30.o devices-msm7x30.o obj-$(CONFIG_ARCH_QSD8X50) += board-qsd8x50.o devices-qsd8x50.o obj-$(CONFIG_ARCH_MSM8X60) += board-msm8x60.o -obj-$(CONFIG_ARCH_MSM7X30) += gpiomux-7x30.o gpiomux-v1.o gpiomux.o +obj-$(CONFIG_ARCH_MSM7X30) += gpiomux-v1.o gpiomux.o obj-$(CONFIG_ARCH_QSD8X50) += gpiomux-8x50.o gpiomux-v1.o gpiomux.o obj-$(CONFIG_ARCH_MSM8X60) += gpiomux-8x60.o gpiomux-v2.o gpiomux.o ifdef CONFIG_MSM_V2_TLMM diff --git a/arch/arm/mach-msm/board-msm7x30.c b/arch/arm/mach-msm/board-msm7x30.c index 6f3b973..0707cc0 100644 --- a/arch/arm/mach-msm/board-msm7x30.c +++ b/arch/arm/mach-msm/board-msm7x30.c @@ -36,6 +36,7 @@ #include #include "devices.h" +#include "gpiomux.h" #include "proc_comm.h" extern struct sys_timer msm_timer; @@ -52,6 +53,27 @@ static struct msm_otg_platform_data msm_otg_pdata = { .otg_control = OTG_PHY_CONTROL, }; +struct msm_gpiomux_config msm_gpiomux_configs[GPIOMUX_NGPIOS] = { +#ifdef CONFIG_SERIAL_MSM_CONSOLE + [49] = { /* UART2 RFR */ + .suspended = GPIOMUX_DRV_2MA | GPIOMUX_PULL_DOWN | + GPIOMUX_FUNC_2 | GPIOMUX_VALID, + }, + [50] = { /* UART2 CTS */ + .suspended = GPIOMUX_DRV_2MA | GPIOMUX_PULL_DOWN | + GPIOMUX_FUNC_2 | GPIOMUX_VALID, + }, + [51] = { /* UART2 RX */ + .suspended = GPIOMUX_DRV_2MA | GPIOMUX_PULL_DOWN | + GPIOMUX_FUNC_2 | GPIOMUX_VALID, + }, + [52] = { /* UART2 TX */ + .suspended = GPIOMUX_DRV_2MA | GPIOMUX_PULL_DOWN | + GPIOMUX_FUNC_2 | GPIOMUX_VALID, + }, +#endif +}; + static struct platform_device *devices[] __initdata = { #if defined(CONFIG_SERIAL_MSM) || defined(CONFIG_MSM_SERIAL_DEBUGGER) &msm_device_uart2, diff --git a/arch/arm/mach-msm/gpiomux-7x30.c b/arch/arm/mach-msm/gpiomux-7x30.c deleted file mode 100644 index 6ce41c5..0000000 --- a/arch/arm/mach-msm/gpiomux-7x30.c +++ /dev/null @@ -1,38 +0,0 @@ -/* Copyright (c) 2010, Code Aurora Forum. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA - * 02110-1301, USA. - */ -#include "gpiomux.h" - -struct msm_gpiomux_config msm_gpiomux_configs[GPIOMUX_NGPIOS] = { -#ifdef CONFIG_SERIAL_MSM_CONSOLE - [49] = { /* UART2 RFR */ - .suspended = GPIOMUX_DRV_2MA | GPIOMUX_PULL_DOWN | - GPIOMUX_FUNC_2 | GPIOMUX_VALID, - }, - [50] = { /* UART2 CTS */ - .suspended = GPIOMUX_DRV_2MA | GPIOMUX_PULL_DOWN | - GPIOMUX_FUNC_2 | GPIOMUX_VALID, - }, - [51] = { /* UART2 RX */ - .suspended = GPIOMUX_DRV_2MA | GPIOMUX_PULL_DOWN | - GPIOMUX_FUNC_2 | GPIOMUX_VALID, - }, - [52] = { /* UART2 TX */ - .suspended = GPIOMUX_DRV_2MA | GPIOMUX_PULL_DOWN | - GPIOMUX_FUNC_2 | GPIOMUX_VALID, - }, -#endif -}; -- cgit v0.10.2 From 48b63b6908a10add9ee383c7db24c37f99e5d324 Mon Sep 17 00:00:00 2001 From: Tejun Heo Date: Mon, 3 Jan 2011 13:49:43 +0000 Subject: video/msm_fb: use system_wq instead of dedicated workqueues With cmwq, there's no reason to use separate workqueues. Drop msmfb_info->resume_workqueue and use system_wq instead. Signed-off-by: Tejun Heo Cc: Stanislaw Gruszka Cc: linux-usb@vger.kernel.org Signed-off-by: David Brown diff --git a/drivers/video/msm/msm_fb.c b/drivers/video/msm/msm_fb.c index debe593..5436aeb 100644 --- a/drivers/video/msm/msm_fb.c +++ b/drivers/video/msm/msm_fb.c @@ -81,7 +81,6 @@ struct msmfb_info { spinlock_t update_lock; struct mutex panel_init_lock; wait_queue_head_t frame_wq; - struct workqueue_struct *resume_workqueue; struct work_struct resume_work; struct msmfb_callback dma_callback; struct msmfb_callback vsync_callback; @@ -111,7 +110,7 @@ static void msmfb_handle_dma_interrupt(struct msmfb_callback *callback) if (msmfb->sleeping == UPDATING && msmfb->frame_done == msmfb->update_frame) { DLOG(SUSPEND_RESUME, "full update completed\n"); - queue_work(msmfb->resume_workqueue, &msmfb->resume_work); + schedule_work(&msmfb->resume_work); } spin_unlock_irqrestore(&msmfb->update_lock, irq_flags); wake_up(&msmfb->frame_wq); @@ -559,12 +558,6 @@ static int msmfb_probe(struct platform_device *pdev) spin_lock_init(&msmfb->update_lock); mutex_init(&msmfb->panel_init_lock); init_waitqueue_head(&msmfb->frame_wq); - msmfb->resume_workqueue = create_workqueue("panel_on"); - if (msmfb->resume_workqueue == NULL) { - printk(KERN_ERR "failed to create panel_on workqueue\n"); - ret = -ENOMEM; - goto error_create_workqueue; - } INIT_WORK(&msmfb->resume_work, power_on_panel); msmfb->black = kzalloc(msmfb->fb->var.bits_per_pixel*msmfb->xres, GFP_KERNEL); @@ -589,8 +582,6 @@ static int msmfb_probe(struct platform_device *pdev) return 0; error_register_framebuffer: - destroy_workqueue(msmfb->resume_workqueue); -error_create_workqueue: iounmap(fb->screen_base); error_setup_fbmem: framebuffer_release(msmfb->fb); -- cgit v0.10.2 From c8e4e7b12632771ab59f2e27fe120764642d06d2 Mon Sep 17 00:00:00 2001 From: David Brown Date: Wed, 26 Jan 2011 16:14:23 -0800 Subject: msm: Remove broken register definition from trout Missed a register change with the clock cleanup on the MSM7x01 targets. Signed-off-by: David Brown diff --git a/arch/arm/mach-msm/io.c b/arch/arm/mach-msm/io.c index d8d9be5..cec6ed1 100644 --- a/arch/arm/mach-msm/io.c +++ b/arch/arm/mach-msm/io.c @@ -42,7 +42,6 @@ static struct map_desc msm_io_desc[] __initdata = { MSM_DEVICE(VIC), MSM_CHIP_DEVICE(CSR, MSM7X00), - MSM_DEVICE(GPT), MSM_DEVICE(DMOV), MSM_DEVICE(GPIO1), MSM_DEVICE(GPIO2), -- cgit v0.10.2 From 5c548add9899a1f8fcd47a58c4925c8ac4fc3027 Mon Sep 17 00:00:00 2001 From: David Brown Date: Wed, 26 Jan 2011 16:14:24 -0800 Subject: msm: Warning fix in trout gpio board file arch/arm/mach-msm/board-trout-gpio.c: In function 'trout_gpio_to_irq': arch/arm/mach-msm/board-trout-gpio.c:77: error: unused variable 'msm_gpio' Signed-off-by: David Brown diff --git a/arch/arm/mach-msm/board-trout-gpio.c b/arch/arm/mach-msm/board-trout-gpio.c index a604ec1..31117a4 100644 --- a/arch/arm/mach-msm/board-trout-gpio.c +++ b/arch/arm/mach-msm/board-trout-gpio.c @@ -74,8 +74,6 @@ static int msm_gpiolib_direction_output(struct gpio_chip *chip, static int trout_gpio_to_irq(struct gpio_chip *chip, unsigned offset) { - struct msm_gpio_chip *msm_gpio = to_msm_gpio_chip(chip); - return TROUT_GPIO_TO_INT(offset + chip->base); } -- cgit v0.10.2 From 437f629d4ea0a574b6102101fe4a51232a7cc105 Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Wed, 26 Jan 2011 16:20:52 -0800 Subject: msm: clock: Remove unused code and definitions This code is dead or otherwise useless so just remove it. Reviewed-by: Saravana Kannan Signed-off-by: Stephen Boyd Signed-off-by: David Brown diff --git a/arch/arm/mach-msm/board-msm8x60.c b/arch/arm/mach-msm/board-msm8x60.c index 9b5eb2b..b3c55f1 100644 --- a/arch/arm/mach-msm/board-msm8x60.c +++ b/arch/arm/mach-msm/board-msm8x60.c @@ -28,10 +28,6 @@ #include #include -unsigned long clk_get_max_axi_khz(void) -{ - return 0; -} static void __init msm8x60_map_io(void) { diff --git a/arch/arm/mach-msm/clock.c b/arch/arm/mach-msm/clock.c index 2069bfa..b67498d 100644 --- a/arch/arm/mach-msm/clock.c +++ b/arch/arm/mach-msm/clock.c @@ -37,13 +37,6 @@ struct clk *msm_clocks; unsigned msm_num_clocks; /* - * Bitmap of enabled clocks, excluding ACPU which is always - * enabled - */ -static DECLARE_BITMAP(clock_map_enabled, NR_CLKS); -static DEFINE_SPINLOCK(clock_map_lock); - -/* * Standard clock functions defined in include/linux/clk.h */ struct clk *clk_get(struct device *dev, const char *id) @@ -77,12 +70,8 @@ int clk_enable(struct clk *clk) unsigned long flags; spin_lock_irqsave(&clocks_lock, flags); clk->count++; - if (clk->count == 1) { + if (clk->count == 1) clk->ops->enable(clk->id); - spin_lock(&clock_map_lock); - clock_map_enabled[BIT_WORD(clk->id)] |= BIT_MASK(clk->id); - spin_unlock(&clock_map_lock); - } spin_unlock_irqrestore(&clocks_lock, flags); return 0; } @@ -94,12 +83,8 @@ void clk_disable(struct clk *clk) spin_lock_irqsave(&clocks_lock, flags); BUG_ON(clk->count == 0); clk->count--; - if (clk->count == 0) { + if (clk->count == 0) clk->ops->disable(clk->id); - spin_lock(&clock_map_lock); - clock_map_enabled[BIT_WORD(clk->id)] &= ~BIT_MASK(clk->id); - spin_unlock(&clock_map_lock); - } spin_unlock_irqrestore(&clocks_lock, flags); } EXPORT_SYMBOL(clk_disable); @@ -196,7 +181,6 @@ void __init msm_clock_init(struct clk *clock_tbl, unsigned num_clocks) { unsigned n; - spin_lock_init(&clocks_lock); mutex_lock(&clocks_mutex); msm_clocks = clock_tbl; msm_num_clocks = num_clocks; diff --git a/arch/arm/mach-msm/clock.h b/arch/arm/mach-msm/clock.h index c270b55..db9a77a 100644 --- a/arch/arm/mach-msm/clock.h +++ b/arch/arm/mach-msm/clock.h @@ -59,51 +59,9 @@ struct clk { struct device *dev; }; -#define A11S_CLK_CNTL_ADDR (MSM_CSR_BASE + 0x100) -#define A11S_CLK_SEL_ADDR (MSM_CSR_BASE + 0x104) -#define A11S_VDD_SVS_PLEVEL_ADDR (MSM_CSR_BASE + 0x124) - -#ifdef CONFIG_DEBUG_FS -#define CLOCK_DBG_NAME(x) .dbg_name = x, -#else -#define CLOCK_DBG_NAME(x) -#endif - -#define CLOCK(clk_name, clk_id, clk_dev, clk_flags) { \ - .name = clk_name, \ - .id = clk_id, \ - .flags = clk_flags, \ - .dev = clk_dev, \ - CLOCK_DBG_NAME(#clk_id) \ - } - #define OFF CLKFLAG_AUTO_OFF #define CLK_MIN CLKFLAG_MIN #define CLK_MAX CLKFLAG_MAX #define CLK_MINMAX (CLK_MIN | CLK_MAX) -#define NR_CLKS P_NR_CLKS - -enum { - PLL_0 = 0, - PLL_1, - PLL_2, - PLL_3, - PLL_4, - PLL_5, - PLL_6, - NUM_PLL -}; - -enum clkvote_client { - CLKVOTE_ACPUCLK = 0, - CLKVOTE_PMQOS, - CLKVOTE_MAX, -}; - -int msm_clock_require_tcxo(unsigned long *reason, int nbits); -int msm_clock_get_name(uint32_t id, char *name, uint32_t size); -int ebi1_clk_set_min_rate(enum clkvote_client client, unsigned long rate); -unsigned long clk_get_max_axi_khz(void); #endif - -- cgit v0.10.2 From ce1c80fbaa3b8e132d4e430cbf7cb4a9cd28b2d5 Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Wed, 26 Jan 2011 16:20:53 -0800 Subject: msm: clock: Remove 7x30 and pcom includes from clock.h clock.h includes clock-pcom.h and clock-7x30.h when it really doesn't need to. Remove the includes and fixup breakages. Reviewed-By: Saravana Kannan Signed-off-by: Stephen Boyd Signed-off-by: David Brown diff --git a/arch/arm/mach-msm/clock-pcom.c b/arch/arm/mach-msm/clock-pcom.c index a3b4562..8c4e867 100644 --- a/arch/arm/mach-msm/clock-pcom.c +++ b/arch/arm/mach-msm/clock-pcom.c @@ -20,6 +20,7 @@ #include "proc_comm.h" #include "clock.h" +#include "clock-pcom.h" /* * glue for the proc_comm interface diff --git a/arch/arm/mach-msm/clock.c b/arch/arm/mach-msm/clock.c index b67498d..8f71f8d 100644 --- a/arch/arm/mach-msm/clock.c +++ b/arch/arm/mach-msm/clock.c @@ -29,6 +29,7 @@ #include "clock.h" #include "proc_comm.h" #include "clock-7x30.h" +#include "clock-pcom.h" static DEFINE_MUTEX(clocks_mutex); static DEFINE_SPINLOCK(clocks_lock); diff --git a/arch/arm/mach-msm/clock.h b/arch/arm/mach-msm/clock.h index db9a77a..6a0cade 100644 --- a/arch/arm/mach-msm/clock.h +++ b/arch/arm/mach-msm/clock.h @@ -20,9 +20,6 @@ #include #include -#include "clock-pcom.h" -#include "clock-7x30.h" - #define CLKFLAG_INVERT 0x00000001 #define CLKFLAG_NOINVERT 0x00000002 #define CLKFLAG_NONEST 0x00000004 diff --git a/arch/arm/mach-msm/devices-msm7x00.c b/arch/arm/mach-msm/devices-msm7x00.c index fb548a8..0a47678 100644 --- a/arch/arm/mach-msm/devices-msm7x00.c +++ b/arch/arm/mach-msm/devices-msm7x00.c @@ -26,6 +26,7 @@ #include "clock.h" +#include "clock-pcom.h" #include static struct resource resources_uart1[] = { diff --git a/arch/arm/mach-msm/devices-msm7x30.c b/arch/arm/mach-msm/devices-msm7x30.c index 4e9a0ab..5dc64af 100644 --- a/arch/arm/mach-msm/devices-msm7x30.c +++ b/arch/arm/mach-msm/devices-msm7x30.c @@ -28,6 +28,7 @@ #include #include "clock-pcom.h" +#include "clock-7x30.h" #include diff --git a/arch/arm/mach-msm/devices-qsd8x50.c b/arch/arm/mach-msm/devices-qsd8x50.c index a4b798f..c08e48e 100644 --- a/arch/arm/mach-msm/devices-qsd8x50.c +++ b/arch/arm/mach-msm/devices-qsd8x50.c @@ -27,6 +27,7 @@ #include #include +#include "clock-pcom.h" static struct resource resources_uart3[] = { { -- cgit v0.10.2 From d64560fe3e9bf64b2050ceeb6b6946ba2a4efda0 Mon Sep 17 00:00:00 2001 From: Matt Wagantall Date: Wed, 26 Jan 2011 16:20:54 -0800 Subject: msm: clock: Move debugfs code from clock.c to clock-debug.c The clock debugfs code is large enough, and easy enough to separate, that it deserves its own file which is compiled only when CONFIG_DEBUG_FS is enabled. Also, cleanup header file #includes that are no longer required. Reviewed-by: Saravana Kannan Signed-off-by: Matt Wagantall Signed-off-by: Stephen Boyd Signed-off-by: David Brown diff --git a/arch/arm/mach-msm/Makefile b/arch/arm/mach-msm/Makefile index 0e5c9dc..c796441 100644 --- a/arch/arm/mach-msm/Makefile +++ b/arch/arm/mach-msm/Makefile @@ -1,4 +1,7 @@ obj-y += io.o idle.o timer.o +ifdef CONFIG_MSM_PROC_COMM +obj-$(CONFIG_DEBUG_FS) += clock-debug.o +endif obj-$(CONFIG_MSM_VIC) += irq-vic.o diff --git a/arch/arm/mach-msm/clock-debug.c b/arch/arm/mach-msm/clock-debug.c new file mode 100644 index 0000000..6f603ed --- /dev/null +++ b/arch/arm/mach-msm/clock-debug.c @@ -0,0 +1,133 @@ +/* + * Copyright (C) 2007 Google, Inc. + * Copyright (c) 2007-2010, Code Aurora Forum. All rights reserved. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include +#include +#include +#include +#include "clock.h" +#include "clock-pcom.h" + +static int clock_debug_rate_set(void *data, u64 val) +{ + struct clk *clock = data; + int ret; + + /* Only increases to max rate will succeed, but that's actually good + * for debugging purposes so we don't check for error. */ + if (clock->flags & CLK_MAX) + clk_set_max_rate(clock, val); + if (clock->flags & CLK_MIN) + ret = clk_set_min_rate(clock, val); + else + ret = clk_set_rate(clock, val); + if (ret != 0) + printk(KERN_ERR "clk_set%s_rate failed (%d)\n", + (clock->flags & CLK_MIN) ? "_min" : "", ret); + return ret; +} + +static int clock_debug_rate_get(void *data, u64 *val) +{ + struct clk *clock = data; + *val = clk_get_rate(clock); + return 0; +} + +DEFINE_SIMPLE_ATTRIBUTE(clock_rate_fops, clock_debug_rate_get, + clock_debug_rate_set, "%llu\n"); + +static int clock_debug_enable_set(void *data, u64 val) +{ + struct clk *clock = data; + int rc = 0; + + if (val) + rc = clock->ops->enable(clock->id); + else + clock->ops->disable(clock->id); + + return rc; +} + +static int clock_debug_enable_get(void *data, u64 *val) +{ + struct clk *clock = data; + + *val = clock->ops->is_enabled(clock->id); + + return 0; +} + +DEFINE_SIMPLE_ATTRIBUTE(clock_enable_fops, clock_debug_enable_get, + clock_debug_enable_set, "%llu\n"); + +static int clock_debug_local_get(void *data, u64 *val) +{ + struct clk *clock = data; + + *val = clock->ops != &clk_ops_pcom; + + return 0; +} + +DEFINE_SIMPLE_ATTRIBUTE(clock_local_fops, clock_debug_local_get, + NULL, "%llu\n"); + +static struct dentry *dent_rate, *dent_enable, *dent_local; + +int __init clock_debug_init(void) +{ + dent_rate = debugfs_create_dir("clk_rate", 0); + if (!dent_rate) + goto err; + + dent_enable = debugfs_create_dir("clk_enable", 0); + if (!dent_enable) + goto err; + + dent_local = debugfs_create_dir("clk_local", NULL); + if (!dent_local) + goto err; + + return 0; +err: + debugfs_remove(dent_local); + debugfs_remove(dent_enable); + debugfs_remove(dent_rate); + return -ENOMEM; +} + +int __init clock_debug_add(struct clk *clock) +{ + char temp[50], *ptr; + + if (!dent_rate || !dent_enable || !dent_local) + return -ENOMEM; + + strncpy(temp, clock->dbg_name, ARRAY_SIZE(temp)-1); + for (ptr = temp; *ptr; ptr++) + *ptr = tolower(*ptr); + + debugfs_create_file(temp, S_IRUGO | S_IWUSR, dent_rate, + clock, &clock_rate_fops); + debugfs_create_file(temp, S_IRUGO | S_IWUSR, dent_enable, + clock, &clock_enable_fops); + debugfs_create_file(temp, S_IRUGO, dent_local, + clock, &clock_local_fops); + + return 0; +} diff --git a/arch/arm/mach-msm/clock.c b/arch/arm/mach-msm/clock.c index 8f71f8d..8c2b4dd 100644 --- a/arch/arm/mach-msm/clock.c +++ b/arch/arm/mach-msm/clock.c @@ -15,16 +15,10 @@ */ #include -#include -#include #include #include -#include #include -#include -#include #include -#include #include "clock.h" #include "proc_comm.h" @@ -34,8 +28,6 @@ static DEFINE_MUTEX(clocks_mutex); static DEFINE_SPINLOCK(clocks_lock); static LIST_HEAD(clocks); -struct clk *msm_clocks; -unsigned msm_num_clocks; /* * Standard clock functions defined in include/linux/clk.h @@ -183,11 +175,9 @@ void __init msm_clock_init(struct clk *clock_tbl, unsigned num_clocks) unsigned n; mutex_lock(&clocks_mutex); - msm_clocks = clock_tbl; - msm_num_clocks = num_clocks; - for (n = 0; n < msm_num_clocks; n++) { - set_clock_ops(&msm_clocks[n]); - list_add_tail(&msm_clocks[n].list, &clocks); + for (n = 0; n < num_clocks; n++) { + set_clock_ops(&clock_tbl[n]); + list_add_tail(&clock_tbl[n].list, &clocks); } mutex_unlock(&clocks_mutex); @@ -196,115 +186,6 @@ void __init msm_clock_init(struct clk *clock_tbl, unsigned num_clocks) } -#if defined(CONFIG_DEBUG_FS) -static struct clk *msm_clock_get_nth(unsigned index) -{ - if (index < msm_num_clocks) - return msm_clocks + index; - else - return 0; -} - -static int clock_debug_rate_set(void *data, u64 val) -{ - struct clk *clock = data; - int ret; - - /* Only increases to max rate will succeed, but that's actually good - * for debugging purposes. So we don't check for error. */ - if (clock->flags & CLK_MAX) - clk_set_max_rate(clock, val); - if (clock->flags & CLK_MIN) - ret = clk_set_min_rate(clock, val); - else - ret = clk_set_rate(clock, val); - if (ret != 0) - printk(KERN_ERR "clk_set%s_rate failed (%d)\n", - (clock->flags & CLK_MIN) ? "_min" : "", ret); - return ret; -} - -static int clock_debug_rate_get(void *data, u64 *val) -{ - struct clk *clock = data; - *val = clk_get_rate(clock); - return 0; -} - -static int clock_debug_enable_set(void *data, u64 val) -{ - struct clk *clock = data; - int rc = 0; - - if (val) - rc = clock->ops->enable(clock->id); - else - clock->ops->disable(clock->id); - - return rc; -} - -static int clock_debug_enable_get(void *data, u64 *val) -{ - struct clk *clock = data; - - *val = clock->ops->is_enabled(clock->id); - - return 0; -} - -static int clock_debug_local_get(void *data, u64 *val) -{ - struct clk *clock = data; - - *val = clock->ops != &clk_ops_pcom; - - return 0; -} - -DEFINE_SIMPLE_ATTRIBUTE(clock_rate_fops, clock_debug_rate_get, - clock_debug_rate_set, "%llu\n"); -DEFINE_SIMPLE_ATTRIBUTE(clock_enable_fops, clock_debug_enable_get, - clock_debug_enable_set, "%llu\n"); -DEFINE_SIMPLE_ATTRIBUTE(clock_local_fops, clock_debug_local_get, - NULL, "%llu\n"); - -static int __init clock_debug_init(void) -{ - struct dentry *dent_rate, *dent_enable, *dent_local; - struct clk *clock; - unsigned n = 0; - char temp[50], *ptr; - - dent_rate = debugfs_create_dir("clk_rate", 0); - if (IS_ERR(dent_rate)) - return PTR_ERR(dent_rate); - - dent_enable = debugfs_create_dir("clk_enable", 0); - if (IS_ERR(dent_enable)) - return PTR_ERR(dent_enable); - - dent_local = debugfs_create_dir("clk_local", NULL); - if (IS_ERR(dent_local)) - return PTR_ERR(dent_local); - - while ((clock = msm_clock_get_nth(n++)) != 0) { - strncpy(temp, clock->dbg_name, ARRAY_SIZE(temp)-1); - for (ptr = temp; *ptr; ptr++) - *ptr = tolower(*ptr); - debugfs_create_file(temp, 0644, dent_rate, - clock, &clock_rate_fops); - debugfs_create_file(temp, 0644, dent_enable, - clock, &clock_enable_fops); - debugfs_create_file(temp, S_IRUGO, dent_local, - clock, &clock_local_fops); - } - return 0; -} - -device_initcall(clock_debug_init); -#endif - /* The bootloader and/or AMSS may have left various clocks enabled. * Disable any clocks that belong to us (CLKFLAG_AUTO_OFF) but have * not been explicitly enabled by a clk_enable() call. @@ -315,8 +196,10 @@ static int __init clock_late_init(void) struct clk *clk; unsigned count = 0; + clock_debug_init(); mutex_lock(&clocks_mutex); list_for_each_entry(clk, &clocks, list) { + clock_debug_add(clk); if (clk->flags & CLKFLAG_AUTO_OFF) { spin_lock_irqsave(&clocks_lock, flags); if (!clk->count) { diff --git a/arch/arm/mach-msm/clock.h b/arch/arm/mach-msm/clock.h index 6a0cade..70216b0 100644 --- a/arch/arm/mach-msm/clock.h +++ b/arch/arm/mach-msm/clock.h @@ -17,6 +17,7 @@ #ifndef __ARCH_ARM_MACH_MSM_CLOCK_H #define __ARCH_ARM_MACH_MSM_CLOCK_H +#include #include #include @@ -61,4 +62,12 @@ struct clk { #define CLK_MAX CLKFLAG_MAX #define CLK_MINMAX (CLK_MIN | CLK_MAX) +#ifdef CONFIG_DEBUG_FS +int __init clock_debug_init(void); +int __init clock_debug_add(struct clk *clock); +#else +static inline int __init clock_debug_init(void) { return 0; } +static inline int __init clock_debug_add(struct clk *clock) { return 0; } +#endif + #endif -- cgit v0.10.2 From 6e6d9b5bec5b27164126894c452853e4cac19b15 Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Wed, 26 Jan 2011 16:20:55 -0800 Subject: msm: clock: Invert debugfs directory layout There are currently 3 separate directories for clock debugging in debugfs: clk_enable, clk_rate, and clk_local. Each of these directories contains a list of clocks. This is rather annoying when you are focusing on one clock and want to enable/disable it and then check its rate. You either have to cd to the other directory or cat ../clk_rate/. Invert the layout so that there is one clock directory containing a directory for each clock. Inside each respective clock directory place an enable, rate, and is_local file relating to the clk_enable, clk_disable, and clk_local directories that exist today. Reviewed-by: Saravana Kannan Signed-off-by: Stephen Boyd Signed-off-by: David Brown diff --git a/arch/arm/mach-msm/clock-debug.c b/arch/arm/mach-msm/clock-debug.c index 6f603ed..b67b9e82 100644 --- a/arch/arm/mach-msm/clock-debug.c +++ b/arch/arm/mach-msm/clock-debug.c @@ -87,47 +87,45 @@ static int clock_debug_local_get(void *data, u64 *val) DEFINE_SIMPLE_ATTRIBUTE(clock_local_fops, clock_debug_local_get, NULL, "%llu\n"); -static struct dentry *dent_rate, *dent_enable, *dent_local; +static struct dentry *debugfs_base; int __init clock_debug_init(void) { - dent_rate = debugfs_create_dir("clk_rate", 0); - if (!dent_rate) - goto err; - - dent_enable = debugfs_create_dir("clk_enable", 0); - if (!dent_enable) - goto err; - - dent_local = debugfs_create_dir("clk_local", NULL); - if (!dent_local) - goto err; - + debugfs_base = debugfs_create_dir("clk", NULL); + if (!debugfs_base) + return -ENOMEM; return 0; -err: - debugfs_remove(dent_local); - debugfs_remove(dent_enable); - debugfs_remove(dent_rate); - return -ENOMEM; } int __init clock_debug_add(struct clk *clock) { char temp[50], *ptr; + struct dentry *clk_dir; - if (!dent_rate || !dent_enable || !dent_local) + if (!debugfs_base) return -ENOMEM; strncpy(temp, clock->dbg_name, ARRAY_SIZE(temp)-1); for (ptr = temp; *ptr; ptr++) *ptr = tolower(*ptr); - debugfs_create_file(temp, S_IRUGO | S_IWUSR, dent_rate, - clock, &clock_rate_fops); - debugfs_create_file(temp, S_IRUGO | S_IWUSR, dent_enable, - clock, &clock_enable_fops); - debugfs_create_file(temp, S_IRUGO, dent_local, - clock, &clock_local_fops); + clk_dir = debugfs_create_dir(temp, debugfs_base); + if (!clk_dir) + return -ENOMEM; + + if (!debugfs_create_file("rate", S_IRUGO | S_IWUSR, clk_dir, + clock, &clock_rate_fops)) + goto error; + if (!debugfs_create_file("enable", S_IRUGO | S_IWUSR, clk_dir, + clock, &clock_enable_fops)) + goto error; + + if (!debugfs_create_file("is_local", S_IRUGO, clk_dir, clock, + &clock_local_fops)) + goto error; return 0; +error: + debugfs_remove_recursive(clk_dir); + return -ENOMEM; } -- cgit v0.10.2 From f689ac98777b8ca7278c1099dfc2ebecde397523 Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Wed, 26 Jan 2011 16:20:56 -0800 Subject: msm: clock: Add support for more proc_comm clocks Add support for the ce, codec_ssbi, uart clocks, and i2c clocks. Reviewed-by: Saravana Kannan Signed-off-by: Stephen Boyd Signed-off-by: David Brown diff --git a/arch/arm/mach-msm/clock-pcom.h b/arch/arm/mach-msm/clock-pcom.h index 17d027b..2c813f1 100644 --- a/arch/arm/mach-msm/clock-pcom.h +++ b/arch/arm/mach-msm/clock-pcom.h @@ -132,8 +132,10 @@ #define P_CSI1_P_CLK 97 #define P_GSBI_CLK 98 #define P_GSBI_P_CLK 99 +#define P_CE_CLK 100 /* Crypto engine */ +#define P_CODEC_SSBI_CLK 101 -#define P_NR_CLKS 100 +#define P_NR_CLKS 102 struct clk_ops; extern struct clk_ops clk_ops_pcom; diff --git a/arch/arm/mach-msm/devices-msm7x30.c b/arch/arm/mach-msm/devices-msm7x30.c index 5dc64af..8bd73079 100644 --- a/arch/arm/mach-msm/devices-msm7x30.c +++ b/arch/arm/mach-msm/devices-msm7x30.c @@ -133,6 +133,8 @@ struct clk msm_clocks_7x30[] = { CLK_PCOM("adsp_clk", ADSP_CLK, NULL, 0), CLK_PCOM("cam_m_clk", CAM_M_CLK, NULL, 0), CLK_PCOM("camif_pad_pclk", CAMIF_PAD_P_CLK, NULL, OFF), + CLK_PCOM("ce_clk", CE_CLK, NULL, 0), + CLK_PCOM("codec_ssbi_clk", CODEC_SSBI_CLK, NULL, 0), CLK_PCOM("ebi1_clk", EBI1_CLK, NULL, CLK_MIN), CLK_PCOM("ecodec_clk", ECODEC_CLK, NULL, 0), CLK_PCOM("emdh_clk", EMDH_CLK, NULL, OFF | CLK_MINMAX), diff --git a/arch/arm/mach-msm/devices-qsd8x50.c b/arch/arm/mach-msm/devices-qsd8x50.c index c08e48e..4cbf89d 100644 --- a/arch/arm/mach-msm/devices-qsd8x50.c +++ b/arch/arm/mach-msm/devices-qsd8x50.c @@ -127,12 +127,14 @@ struct platform_device msm_device_hsusb_host = { struct clk msm_clocks_8x50[] = { CLK_PCOM("adm_clk", ADM_CLK, NULL, 0), + CLK_PCOM("ce_clk", CE_CLK, NULL, 0), CLK_PCOM("ebi1_clk", EBI1_CLK, NULL, CLK_MIN), CLK_PCOM("ebi2_clk", EBI2_CLK, NULL, 0), CLK_PCOM("ecodec_clk", ECODEC_CLK, NULL, 0), CLK_PCOM("emdh_clk", EMDH_CLK, NULL, OFF | CLK_MINMAX), CLK_PCOM("gp_clk", GP_CLK, NULL, 0), CLK_PCOM("grp_clk", GRP_3D_CLK, NULL, 0), + CLK_PCOM("i2c_clk", I2C_CLK, NULL, 0), CLK_PCOM("icodec_rx_clk", ICODEC_RX_CLK, NULL, 0), CLK_PCOM("icodec_tx_clk", ICODEC_TX_CLK, NULL, 0), CLK_PCOM("imem_clk", IMEM_CLK, NULL, OFF), @@ -150,7 +152,11 @@ struct clk msm_clocks_8x50[] = { CLK_PCOM("tsif_ref_clk", TSIF_REF_CLK, NULL, 0), CLK_PCOM("tv_dac_clk", TV_DAC_CLK, NULL, 0), CLK_PCOM("tv_enc_clk", TV_ENC_CLK, NULL, 0), + CLK_PCOM("uart_clk", UART1_CLK, NULL, OFF), + CLK_PCOM("uart_clk", UART2_CLK, NULL, 0), CLK_PCOM("uart_clk", UART3_CLK, &msm_device_uart3.dev, OFF), + CLK_PCOM("uartdm_clk", UART1DM_CLK, NULL, OFF), + CLK_PCOM("uartdm_clk", UART2DM_CLK, NULL, 0), CLK_PCOM("usb_hs_clk", USB_HS_CLK, NULL, OFF), CLK_PCOM("usb_hs_pclk", USB_HS_P_CLK, NULL, OFF), CLK_PCOM("usb_otg_clk", USB_OTG_CLK, NULL, 0), -- cgit v0.10.2 From 07a3cc4814f790354d4c7be2c9dc6143a714a07a Mon Sep 17 00:00:00 2001 From: Stepan Moskovchenko Date: Thu, 27 Jan 2011 12:13:22 -0800 Subject: msm: Clean up useless ifdefs Remove ifdefs that do nothing, either from having the code between them previously removed, or from having been accidentally added to the wrong file. Signed-off-by: Stepan Moskovchenko Signed-off-by: David Brown diff --git a/arch/arm/mach-msm/board-halibut.c b/arch/arm/mach-msm/board-halibut.c index 75dabb1..18a3c97 100644 --- a/arch/arm/mach-msm/board-halibut.c +++ b/arch/arm/mach-msm/board-halibut.c @@ -93,8 +93,6 @@ static void __init halibut_map_io(void) } MACHINE_START(HALIBUT, "Halibut Board (QCT SURF7200A)") -#ifdef CONFIG_MSM_DEBUG_UART -#endif .boot_params = 0x10000100, .fixup = halibut_fixup, .map_io = halibut_map_io, diff --git a/arch/arm/mach-msm/board-mahimahi.c b/arch/arm/mach-msm/board-mahimahi.c index ef3ebf2..7a9a03e 100644 --- a/arch/arm/mach-msm/board-mahimahi.c +++ b/arch/arm/mach-msm/board-mahimahi.c @@ -74,8 +74,6 @@ static void __init mahimahi_map_io(void) extern struct sys_timer msm_timer; MACHINE_START(MAHIMAHI, "mahimahi") -#ifdef CONFIG_MSM_DEBUG_UART -#endif .boot_params = 0x20000100, .fixup = mahimahi_fixup, .map_io = mahimahi_map_io, diff --git a/arch/arm/mach-msm/board-msm7x27.c b/arch/arm/mach-msm/board-msm7x27.c index e7a76ef..16d7580 100644 --- a/arch/arm/mach-msm/board-msm7x27.c +++ b/arch/arm/mach-msm/board-msm7x27.c @@ -130,8 +130,6 @@ static void __init msm7x2x_map_io(void) } MACHINE_START(MSM7X27_SURF, "QCT MSM7x27 SURF") -#ifdef CONFIG_MSM_DEBUG_UART -#endif .boot_params = PHYS_OFFSET + 0x100, .map_io = msm7x2x_map_io, .init_irq = msm7x2x_init_irq, @@ -140,8 +138,6 @@ MACHINE_START(MSM7X27_SURF, "QCT MSM7x27 SURF") MACHINE_END MACHINE_START(MSM7X27_FFA, "QCT MSM7x27 FFA") -#ifdef CONFIG_MSM_DEBUG_UART -#endif .boot_params = PHYS_OFFSET + 0x100, .map_io = msm7x2x_map_io, .init_irq = msm7x2x_init_irq, @@ -150,8 +146,6 @@ MACHINE_START(MSM7X27_FFA, "QCT MSM7x27 FFA") MACHINE_END MACHINE_START(MSM7X25_SURF, "QCT MSM7x25 SURF") -#ifdef CONFIG_MSM_DEBUG_UART -#endif .boot_params = PHYS_OFFSET + 0x100, .map_io = msm7x2x_map_io, .init_irq = msm7x2x_init_irq, @@ -160,8 +154,6 @@ MACHINE_START(MSM7X25_SURF, "QCT MSM7x25 SURF") MACHINE_END MACHINE_START(MSM7X25_FFA, "QCT MSM7x25 FFA") -#ifdef CONFIG_MSM_DEBUG_UART -#endif .boot_params = PHYS_OFFSET + 0x100, .map_io = msm7x2x_map_io, .init_irq = msm7x2x_init_irq, diff --git a/arch/arm/mach-msm/board-msm7x30.c b/arch/arm/mach-msm/board-msm7x30.c index 0707cc0..dc9fac1 100644 --- a/arch/arm/mach-msm/board-msm7x30.c +++ b/arch/arm/mach-msm/board-msm7x30.c @@ -105,8 +105,6 @@ static void __init msm7x30_map_io(void) } MACHINE_START(MSM7X30_SURF, "QCT MSM7X30 SURF") -#ifdef CONFIG_MSM_DEBUG_UART -#endif .boot_params = PHYS_OFFSET + 0x100, .map_io = msm7x30_map_io, .init_irq = msm7x30_init_irq, @@ -115,8 +113,6 @@ MACHINE_START(MSM7X30_SURF, "QCT MSM7X30 SURF") MACHINE_END MACHINE_START(MSM7X30_FFA, "QCT MSM7X30 FFA") -#ifdef CONFIG_MSM_DEBUG_UART -#endif .boot_params = PHYS_OFFSET + 0x100, .map_io = msm7x30_map_io, .init_irq = msm7x30_init_irq, @@ -125,8 +121,6 @@ MACHINE_START(MSM7X30_FFA, "QCT MSM7X30 FFA") MACHINE_END MACHINE_START(MSM7X30_FLUID, "QCT MSM7X30 FLUID") -#ifdef CONFIG_MSM_DEBUG_UART -#endif .boot_params = PHYS_OFFSET + 0x100, .map_io = msm7x30_map_io, .init_irq = msm7x30_init_irq, diff --git a/arch/arm/mach-msm/board-qsd8x50.c b/arch/arm/mach-msm/board-qsd8x50.c index 6dde818..3edc4de 100644 --- a/arch/arm/mach-msm/board-qsd8x50.c +++ b/arch/arm/mach-msm/board-qsd8x50.c @@ -116,8 +116,6 @@ static void __init qsd8x50_init(void) } MACHINE_START(QSD8X50_SURF, "QCT QSD8X50 SURF") -#ifdef CONFIG_MSM_DEBUG_UART -#endif .boot_params = PHYS_OFFSET + 0x100, .map_io = qsd8x50_map_io, .init_irq = qsd8x50_init_irq, @@ -126,8 +124,6 @@ MACHINE_START(QSD8X50_SURF, "QCT QSD8X50 SURF") MACHINE_END MACHINE_START(QSD8X50A_ST1_5, "QCT QSD8X50A ST1.5") -#ifdef CONFIG_MSM_DEBUG_UART -#endif .boot_params = PHYS_OFFSET + 0x100, .map_io = qsd8x50_map_io, .init_irq = qsd8x50_init_irq, diff --git a/arch/arm/mach-msm/board-sapphire.c b/arch/arm/mach-msm/board-sapphire.c index 8919ffb1..6781ca8 100644 --- a/arch/arm/mach-msm/board-sapphire.c +++ b/arch/arm/mach-msm/board-sapphire.c @@ -105,8 +105,6 @@ static void __init sapphire_map_io(void) MACHINE_START(SAPPHIRE, "sapphire") /* Maintainer: Brian Swetland */ -#ifdef CONFIG_MSM_DEBUG_UART -#endif .boot_params = PHYS_OFFSET + 0x100, .fixup = sapphire_fixup, .map_io = sapphire_map_io, diff --git a/arch/arm/mach-msm/board-trout.c b/arch/arm/mach-msm/board-trout.c index 73f1460..8448687 100644 --- a/arch/arm/mach-msm/board-trout.c +++ b/arch/arm/mach-msm/board-trout.c @@ -92,8 +92,6 @@ static void __init trout_map_io(void) } MACHINE_START(TROUT, "HTC Dream") -#ifdef CONFIG_MSM_DEBUG_UART -#endif .boot_params = 0x10000100, .fixup = trout_fixup, .map_io = trout_map_io, diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h b/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h index 1e75ed7..8f99d97 100644 --- a/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h +++ b/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h @@ -126,10 +126,4 @@ #define MSM_AD5_SIZE (SZ_1M*13) -#if defined(CONFIG_ARCH_MSM7X30) -#define MSM_GCC_BASE IOMEM(0xF8009000) -#define MSM_GCC_PHYS 0xC0182000 -#define MSM_GCC_SIZE SZ_4K -#endif - #endif -- cgit v0.10.2 From d056fca32354dd990ffbd90fd1da10eaec72aa87 Mon Sep 17 00:00:00 2001 From: Stepan Moskovchenko Date: Thu, 27 Jan 2011 12:12:07 -0800 Subject: msm: serial: Add MSM8960 serial support Add the device definitions and platform data to support the console serial port on MSM8960 Simulator and RUMI3 targets. Signed-off-by: Stepan Moskovchenko Signed-off-by: David Brown diff --git a/arch/arm/mach-msm/Makefile b/arch/arm/mach-msm/Makefile index c796441..ea8c74f 100644 --- a/arch/arm/mach-msm/Makefile +++ b/arch/arm/mach-msm/Makefile @@ -27,7 +27,7 @@ obj-$(CONFIG_MACH_HALIBUT) += board-halibut.o devices-msm7x00.o obj-$(CONFIG_ARCH_MSM7X30) += board-msm7x30.o devices-msm7x30.o obj-$(CONFIG_ARCH_QSD8X50) += board-qsd8x50.o devices-qsd8x50.o obj-$(CONFIG_ARCH_MSM8X60) += board-msm8x60.o -obj-$(CONFIG_ARCH_MSM8960) += board-msm8960.o +obj-$(CONFIG_ARCH_MSM8960) += board-msm8960.o devices-msm8960.o obj-$(CONFIG_ARCH_MSM7X30) += gpiomux-v1.o gpiomux.o obj-$(CONFIG_ARCH_QSD8X50) += gpiomux-8x50.o gpiomux-v1.o gpiomux.o diff --git a/arch/arm/mach-msm/board-msm8960.c b/arch/arm/mach-msm/board-msm8960.c index 2b09573..ef80f46 100644 --- a/arch/arm/mach-msm/board-msm8960.c +++ b/arch/arm/mach-msm/board-msm8960.c @@ -27,6 +27,8 @@ #include #include +#include "devices.h" + static void __init msm8960_map_io(void) { msm_map_msm8960_io(); @@ -54,15 +56,35 @@ static void __init msm8960_init_irq(void) } } +static struct platform_device *sim_devices[] __initdata = { + &msm8960_device_uart_gsbi2, +}; + +static struct platform_device *rumi3_devices[] __initdata = { + &msm8960_device_uart_gsbi5, +}; + +static void __init msm8960_sim_init(void) +{ + platform_add_devices(sim_devices, ARRAY_SIZE(sim_devices)); +} + +static void __init msm8960_rumi3_init(void) +{ + platform_add_devices(rumi3_devices, ARRAY_SIZE(rumi3_devices)); +} + MACHINE_START(MSM8960_SIM, "QCT MSM8960 SIMULATOR") .map_io = msm8960_map_io, .init_irq = msm8960_init_irq, .timer = &msm_timer, + .init_machine = msm8960_sim_init, MACHINE_END MACHINE_START(MSM8960_RUMI3, "QCT MSM8960 RUMI3") .map_io = msm8960_map_io, .init_irq = msm8960_init_irq, .timer = &msm_timer, + .init_machine = msm8960_rumi3_init, MACHINE_END diff --git a/arch/arm/mach-msm/devices-msm8960.c b/arch/arm/mach-msm/devices-msm8960.c new file mode 100644 index 0000000..d9e1f26 --- /dev/null +++ b/arch/arm/mach-msm/devices-msm8960.c @@ -0,0 +1,85 @@ +/* Copyright (c) 2011, Code Aurora Forum. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + */ + +#include +#include + +#include +#include +#include + +#include "devices.h" + +#define MSM_GSBI2_PHYS 0x16100000 +#define MSM_UART2DM_PHYS (MSM_GSBI2_PHYS + 0x40000) + +#define MSM_GSBI5_PHYS 0x16400000 +#define MSM_UART5DM_PHYS (MSM_GSBI5_PHYS + 0x40000) + +static struct resource resources_uart_gsbi2[] = { + { + .start = GSBI2_UARTDM_IRQ, + .end = GSBI2_UARTDM_IRQ, + .flags = IORESOURCE_IRQ, + }, + { + .start = MSM_UART2DM_PHYS, + .end = MSM_UART2DM_PHYS + PAGE_SIZE - 1, + .name = "uart_resource", + .flags = IORESOURCE_MEM, + }, + { + .start = MSM_GSBI2_PHYS, + .end = MSM_GSBI2_PHYS + PAGE_SIZE - 1, + .name = "gsbi_resource", + .flags = IORESOURCE_MEM, + }, +}; + +struct platform_device msm8960_device_uart_gsbi2 = { + .name = "msm_serial", + .id = 0, + .num_resources = ARRAY_SIZE(resources_uart_gsbi2), + .resource = resources_uart_gsbi2, +}; + +static struct resource resources_uart_gsbi5[] = { + { + .start = GSBI5_UARTDM_IRQ, + .end = GSBI5_UARTDM_IRQ, + .flags = IORESOURCE_IRQ, + }, + { + .start = MSM_UART5DM_PHYS, + .end = MSM_UART5DM_PHYS + PAGE_SIZE - 1, + .name = "uart_resource", + .flags = IORESOURCE_MEM, + }, + { + .start = MSM_GSBI5_PHYS, + .end = MSM_GSBI5_PHYS + PAGE_SIZE - 1, + .name = "gsbi_resource", + .flags = IORESOURCE_MEM, + }, +}; + +struct platform_device msm8960_device_uart_gsbi5 = { + .name = "msm_serial", + .id = 0, + .num_resources = ARRAY_SIZE(resources_uart_gsbi5), + .resource = resources_uart_gsbi5, +}; diff --git a/arch/arm/mach-msm/devices.h b/arch/arm/mach-msm/devices.h index 87c70bf..e2643b3 100644 --- a/arch/arm/mach-msm/devices.h +++ b/arch/arm/mach-msm/devices.h @@ -22,6 +22,9 @@ extern struct platform_device msm_device_uart1; extern struct platform_device msm_device_uart2; extern struct platform_device msm_device_uart3; +extern struct platform_device msm8960_device_uart_gsbi2; +extern struct platform_device msm8960_device_uart_gsbi5; + extern struct platform_device msm_device_sdc1; extern struct platform_device msm_device_sdc2; extern struct platform_device msm_device_sdc3; -- cgit v0.10.2 From 24f6173c44a3f921f4fc4b8afc1e3980cbba6528 Mon Sep 17 00:00:00 2001 From: Stepan Moskovchenko Date: Fri, 11 Feb 2011 12:28:16 -0800 Subject: msm: iommu: Create a Kconfig item for the IOMMU driver Break the IOMMU driver out as a Kconfig item. Initially it was decided to always build this in for 8x60, but this driver is not strictly necessary and should be optionally selectable. Signed-off-by: Stepan Moskovchenko Signed-off-by: David Brown diff --git a/arch/arm/mach-msm/Kconfig b/arch/arm/mach-msm/Kconfig index df9d74e..32b9d1f 100644 --- a/arch/arm/mach-msm/Kconfig +++ b/arch/arm/mach-msm/Kconfig @@ -45,7 +45,6 @@ config ARCH_MSM8X60 select CPU_V7 select MSM_V2_TLMM select MSM_GPIOMUX - select IOMMU_API select MSM_SCM if SMP config ARCH_MSM8960 @@ -149,6 +148,18 @@ config MACH_MSM8960_RUMI3 endmenu +config MSM_IOMMU + bool "MSM IOMMU Support" + depends on ARCH_MSM8X60 + select IOMMU_API + default n + help + Support for the IOMMUs found on certain Qualcomm SOCs. + These IOMMUs allow virtualization of the address space used by most + cores within the multimedia subsystem. + + If unsure, say N here. + config IOMMU_PGTABLES_L2 def_bool y depends on ARCH_MSM8X60 && MMU && SMP && CPU_DCACHE_DISABLE=n diff --git a/arch/arm/mach-msm/Makefile b/arch/arm/mach-msm/Makefile index ea8c74f..81f4811 100644 --- a/arch/arm/mach-msm/Makefile +++ b/arch/arm/mach-msm/Makefile @@ -4,11 +4,12 @@ obj-$(CONFIG_DEBUG_FS) += clock-debug.o endif obj-$(CONFIG_MSM_VIC) += irq-vic.o +obj-$(CONFIG_MSM_IOMMU) += iommu.o iommu_dev.o obj-$(CONFIG_ARCH_MSM7X00A) += dma.o irq.o acpuclock-arm11.o obj-$(CONFIG_ARCH_MSM7X30) += dma.o obj-$(CONFIG_ARCH_QSD8X50) += dma.o sirc.o -obj-$(CONFIG_ARCH_MSM8X60) += clock-dummy.o iommu.o iommu_dev.o devices-msm8x60-iommu.o +obj-$(CONFIG_ARCH_MSM8X60) += clock-dummy.o devices-msm8x60-iommu.o obj-$(CONFIG_ARCH_MSM8960) += clock-dummy.o obj-$(CONFIG_MSM_PROC_COMM) += proc_comm.o clock-pcom.o vreg.o -- cgit v0.10.2 From 69e213637538e749f6d22d2f426bcafa39eb5261 Mon Sep 17 00:00:00 2001 From: Stepan Moskovchenko Date: Fri, 11 Feb 2011 12:28:17 -0800 Subject: msm: iommu: Generalize platform data for multiple targets Make the IOMMU platform data target-independent in preparation for adding MSM8960 IOMMU support. The IOMMU configuration on MSM8x60 and MSM8960 is identical and the same platform data can be used for both. Signed-off-by: Stepan Moskovchenko Signed-off-by: David Brown diff --git a/arch/arm/mach-msm/Makefile b/arch/arm/mach-msm/Makefile index 81f4811..2099c97 100644 --- a/arch/arm/mach-msm/Makefile +++ b/arch/arm/mach-msm/Makefile @@ -4,12 +4,12 @@ obj-$(CONFIG_DEBUG_FS) += clock-debug.o endif obj-$(CONFIG_MSM_VIC) += irq-vic.o -obj-$(CONFIG_MSM_IOMMU) += iommu.o iommu_dev.o +obj-$(CONFIG_MSM_IOMMU) += iommu.o iommu_dev.o devices-iommu.o obj-$(CONFIG_ARCH_MSM7X00A) += dma.o irq.o acpuclock-arm11.o obj-$(CONFIG_ARCH_MSM7X30) += dma.o obj-$(CONFIG_ARCH_QSD8X50) += dma.o sirc.o -obj-$(CONFIG_ARCH_MSM8X60) += clock-dummy.o devices-msm8x60-iommu.o +obj-$(CONFIG_ARCH_MSM8X60) += clock-dummy.o obj-$(CONFIG_ARCH_MSM8960) += clock-dummy.o obj-$(CONFIG_MSM_PROC_COMM) += proc_comm.o clock-pcom.o vreg.o diff --git a/arch/arm/mach-msm/devices-iommu.c b/arch/arm/mach-msm/devices-iommu.c new file mode 100644 index 0000000..c0206b7 --- /dev/null +++ b/arch/arm/mach-msm/devices-iommu.c @@ -0,0 +1,904 @@ +/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + */ + +#include +#include +#include +#include +#include + +static struct resource msm_iommu_jpegd_resources[] = { + { + .start = 0x07300000, + .end = 0x07300000 + SZ_1M - 1, + .name = "physbase", + .flags = IORESOURCE_MEM, + }, + { + .name = "nonsecure_irq", + .start = SMMU_JPEGD_CB_SC_NON_SECURE_IRQ, + .end = SMMU_JPEGD_CB_SC_NON_SECURE_IRQ, + .flags = IORESOURCE_IRQ, + }, + { + .name = "secure_irq", + .start = SMMU_JPEGD_CB_SC_SECURE_IRQ, + .end = SMMU_JPEGD_CB_SC_SECURE_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct resource msm_iommu_vpe_resources[] = { + { + .start = 0x07400000, + .end = 0x07400000 + SZ_1M - 1, + .name = "physbase", + .flags = IORESOURCE_MEM, + }, + { + .name = "nonsecure_irq", + .start = SMMU_VPE_CB_SC_NON_SECURE_IRQ, + .end = SMMU_VPE_CB_SC_NON_SECURE_IRQ, + .flags = IORESOURCE_IRQ, + }, + { + .name = "secure_irq", + .start = SMMU_VPE_CB_SC_SECURE_IRQ, + .end = SMMU_VPE_CB_SC_SECURE_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct resource msm_iommu_mdp0_resources[] = { + { + .start = 0x07500000, + .end = 0x07500000 + SZ_1M - 1, + .name = "physbase", + .flags = IORESOURCE_MEM, + }, + { + .name = "nonsecure_irq", + .start = SMMU_MDP0_CB_SC_NON_SECURE_IRQ, + .end = SMMU_MDP0_CB_SC_NON_SECURE_IRQ, + .flags = IORESOURCE_IRQ, + }, + { + .name = "secure_irq", + .start = SMMU_MDP0_CB_SC_SECURE_IRQ, + .end = SMMU_MDP0_CB_SC_SECURE_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct resource msm_iommu_mdp1_resources[] = { + { + .start = 0x07600000, + .end = 0x07600000 + SZ_1M - 1, + .name = "physbase", + .flags = IORESOURCE_MEM, + }, + { + .name = "nonsecure_irq", + .start = SMMU_MDP1_CB_SC_NON_SECURE_IRQ, + .end = SMMU_MDP1_CB_SC_NON_SECURE_IRQ, + .flags = IORESOURCE_IRQ, + }, + { + .name = "secure_irq", + .start = SMMU_MDP1_CB_SC_SECURE_IRQ, + .end = SMMU_MDP1_CB_SC_SECURE_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct resource msm_iommu_rot_resources[] = { + { + .start = 0x07700000, + .end = 0x07700000 + SZ_1M - 1, + .name = "physbase", + .flags = IORESOURCE_MEM, + }, + { + .name = "nonsecure_irq", + .start = SMMU_ROT_CB_SC_NON_SECURE_IRQ, + .end = SMMU_ROT_CB_SC_NON_SECURE_IRQ, + .flags = IORESOURCE_IRQ, + }, + { + .name = "secure_irq", + .start = SMMU_ROT_CB_SC_SECURE_IRQ, + .end = SMMU_ROT_CB_SC_SECURE_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct resource msm_iommu_ijpeg_resources[] = { + { + .start = 0x07800000, + .end = 0x07800000 + SZ_1M - 1, + .name = "physbase", + .flags = IORESOURCE_MEM, + }, + { + .name = "nonsecure_irq", + .start = SMMU_IJPEG_CB_SC_NON_SECURE_IRQ, + .end = SMMU_IJPEG_CB_SC_NON_SECURE_IRQ, + .flags = IORESOURCE_IRQ, + }, + { + .name = "secure_irq", + .start = SMMU_IJPEG_CB_SC_SECURE_IRQ, + .end = SMMU_IJPEG_CB_SC_SECURE_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct resource msm_iommu_vfe_resources[] = { + { + .start = 0x07900000, + .end = 0x07900000 + SZ_1M - 1, + .name = "physbase", + .flags = IORESOURCE_MEM, + }, + { + .name = "nonsecure_irq", + .start = SMMU_VFE_CB_SC_NON_SECURE_IRQ, + .end = SMMU_VFE_CB_SC_NON_SECURE_IRQ, + .flags = IORESOURCE_IRQ, + }, + { + .name = "secure_irq", + .start = SMMU_VFE_CB_SC_SECURE_IRQ, + .end = SMMU_VFE_CB_SC_SECURE_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct resource msm_iommu_vcodec_a_resources[] = { + { + .start = 0x07A00000, + .end = 0x07A00000 + SZ_1M - 1, + .name = "physbase", + .flags = IORESOURCE_MEM, + }, + { + .name = "nonsecure_irq", + .start = SMMU_VCODEC_A_CB_SC_NON_SECURE_IRQ, + .end = SMMU_VCODEC_A_CB_SC_NON_SECURE_IRQ, + .flags = IORESOURCE_IRQ, + }, + { + .name = "secure_irq", + .start = SMMU_VCODEC_A_CB_SC_SECURE_IRQ, + .end = SMMU_VCODEC_A_CB_SC_SECURE_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct resource msm_iommu_vcodec_b_resources[] = { + { + .start = 0x07B00000, + .end = 0x07B00000 + SZ_1M - 1, + .name = "physbase", + .flags = IORESOURCE_MEM, + }, + { + .name = "nonsecure_irq", + .start = SMMU_VCODEC_B_CB_SC_NON_SECURE_IRQ, + .end = SMMU_VCODEC_B_CB_SC_NON_SECURE_IRQ, + .flags = IORESOURCE_IRQ, + }, + { + .name = "secure_irq", + .start = SMMU_VCODEC_B_CB_SC_SECURE_IRQ, + .end = SMMU_VCODEC_B_CB_SC_SECURE_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct resource msm_iommu_gfx3d_resources[] = { + { + .start = 0x07C00000, + .end = 0x07C00000 + SZ_1M - 1, + .name = "physbase", + .flags = IORESOURCE_MEM, + }, + { + .name = "nonsecure_irq", + .start = SMMU_GFX3D_CB_SC_NON_SECURE_IRQ, + .end = SMMU_GFX3D_CB_SC_NON_SECURE_IRQ, + .flags = IORESOURCE_IRQ, + }, + { + .name = "secure_irq", + .start = SMMU_GFX3D_CB_SC_SECURE_IRQ, + .end = SMMU_GFX3D_CB_SC_SECURE_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct resource msm_iommu_gfx2d0_resources[] = { + { + .start = 0x07D00000, + .end = 0x07D00000 + SZ_1M - 1, + .name = "physbase", + .flags = IORESOURCE_MEM, + }, + { + .name = "nonsecure_irq", + .start = SMMU_GFX2D0_CB_SC_NON_SECURE_IRQ, + .end = SMMU_GFX2D0_CB_SC_NON_SECURE_IRQ, + .flags = IORESOURCE_IRQ, + }, + { + .name = "secure_irq", + .start = SMMU_GFX2D0_CB_SC_SECURE_IRQ, + .end = SMMU_GFX2D0_CB_SC_SECURE_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct resource msm_iommu_gfx2d1_resources[] = { + { + .start = 0x07E00000, + .end = 0x07E00000 + SZ_1M - 1, + .name = "physbase", + .flags = IORESOURCE_MEM, + }, + { + .name = "nonsecure_irq", + .start = SMMU_GFX2D1_CB_SC_NON_SECURE_IRQ, + .end = SMMU_GFX2D1_CB_SC_NON_SECURE_IRQ, + .flags = IORESOURCE_IRQ, + }, + { + .name = "secure_irq", + .start = SMMU_GFX2D1_CB_SC_SECURE_IRQ, + .end = SMMU_GFX2D1_CB_SC_SECURE_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device msm_root_iommu_dev = { + .name = "msm_iommu", + .id = -1, +}; + +static struct msm_iommu_dev jpegd_iommu = { + .name = "jpegd", + .clk_rate = -1 +}; + +static struct msm_iommu_dev vpe_iommu = { + .name = "vpe" +}; + +static struct msm_iommu_dev mdp0_iommu = { + .name = "mdp0" +}; + +static struct msm_iommu_dev mdp1_iommu = { + .name = "mdp1" +}; + +static struct msm_iommu_dev rot_iommu = { + .name = "rot" +}; + +static struct msm_iommu_dev ijpeg_iommu = { + .name = "ijpeg" +}; + +static struct msm_iommu_dev vfe_iommu = { + .name = "vfe", + .clk_rate = -1 +}; + +static struct msm_iommu_dev vcodec_a_iommu = { + .name = "vcodec_a" +}; + +static struct msm_iommu_dev vcodec_b_iommu = { + .name = "vcodec_b" +}; + +static struct msm_iommu_dev gfx3d_iommu = { + .name = "gfx3d", + .clk_rate = 27000000 +}; + +static struct msm_iommu_dev gfx2d0_iommu = { + .name = "gfx2d0", + .clk_rate = 27000000 +}; + +static struct msm_iommu_dev gfx2d1_iommu = { + .name = "gfx2d1", + .clk_rate = 27000000 +}; + +static struct platform_device msm_device_iommu_jpegd = { + .name = "msm_iommu", + .id = 0, + .dev = { + .parent = &msm_root_iommu_dev.dev, + }, + .num_resources = ARRAY_SIZE(msm_iommu_jpegd_resources), + .resource = msm_iommu_jpegd_resources, +}; + +static struct platform_device msm_device_iommu_vpe = { + .name = "msm_iommu", + .id = 1, + .dev = { + .parent = &msm_root_iommu_dev.dev, + }, + .num_resources = ARRAY_SIZE(msm_iommu_vpe_resources), + .resource = msm_iommu_vpe_resources, +}; + +static struct platform_device msm_device_iommu_mdp0 = { + .name = "msm_iommu", + .id = 2, + .dev = { + .parent = &msm_root_iommu_dev.dev, + }, + .num_resources = ARRAY_SIZE(msm_iommu_mdp0_resources), + .resource = msm_iommu_mdp0_resources, +}; + +static struct platform_device msm_device_iommu_mdp1 = { + .name = "msm_iommu", + .id = 3, + .dev = { + .parent = &msm_root_iommu_dev.dev, + }, + .num_resources = ARRAY_SIZE(msm_iommu_mdp1_resources), + .resource = msm_iommu_mdp1_resources, +}; + +static struct platform_device msm_device_iommu_rot = { + .name = "msm_iommu", + .id = 4, + .dev = { + .parent = &msm_root_iommu_dev.dev, + }, + .num_resources = ARRAY_SIZE(msm_iommu_rot_resources), + .resource = msm_iommu_rot_resources, +}; + +static struct platform_device msm_device_iommu_ijpeg = { + .name = "msm_iommu", + .id = 5, + .dev = { + .parent = &msm_root_iommu_dev.dev, + }, + .num_resources = ARRAY_SIZE(msm_iommu_ijpeg_resources), + .resource = msm_iommu_ijpeg_resources, +}; + +static struct platform_device msm_device_iommu_vfe = { + .name = "msm_iommu", + .id = 6, + .dev = { + .parent = &msm_root_iommu_dev.dev, + }, + .num_resources = ARRAY_SIZE(msm_iommu_vfe_resources), + .resource = msm_iommu_vfe_resources, +}; + +static struct platform_device msm_device_iommu_vcodec_a = { + .name = "msm_iommu", + .id = 7, + .dev = { + .parent = &msm_root_iommu_dev.dev, + }, + .num_resources = ARRAY_SIZE(msm_iommu_vcodec_a_resources), + .resource = msm_iommu_vcodec_a_resources, +}; + +static struct platform_device msm_device_iommu_vcodec_b = { + .name = "msm_iommu", + .id = 8, + .dev = { + .parent = &msm_root_iommu_dev.dev, + }, + .num_resources = ARRAY_SIZE(msm_iommu_vcodec_b_resources), + .resource = msm_iommu_vcodec_b_resources, +}; + +static struct platform_device msm_device_iommu_gfx3d = { + .name = "msm_iommu", + .id = 9, + .dev = { + .parent = &msm_root_iommu_dev.dev, + }, + .num_resources = ARRAY_SIZE(msm_iommu_gfx3d_resources), + .resource = msm_iommu_gfx3d_resources, +}; + +static struct platform_device msm_device_iommu_gfx2d0 = { + .name = "msm_iommu", + .id = 10, + .dev = { + .parent = &msm_root_iommu_dev.dev, + }, + .num_resources = ARRAY_SIZE(msm_iommu_gfx2d0_resources), + .resource = msm_iommu_gfx2d0_resources, +}; + +struct platform_device msm_device_iommu_gfx2d1 = { + .name = "msm_iommu", + .id = 11, + .dev = { + .parent = &msm_root_iommu_dev.dev, + }, + .num_resources = ARRAY_SIZE(msm_iommu_gfx2d1_resources), + .resource = msm_iommu_gfx2d1_resources, +}; + +static struct msm_iommu_ctx_dev jpegd_src_ctx = { + .name = "jpegd_src", + .num = 0, + .mids = {0, -1} +}; + +static struct msm_iommu_ctx_dev jpegd_dst_ctx = { + .name = "jpegd_dst", + .num = 1, + .mids = {1, -1} +}; + +static struct msm_iommu_ctx_dev vpe_src_ctx = { + .name = "vpe_src", + .num = 0, + .mids = {0, -1} +}; + +static struct msm_iommu_ctx_dev vpe_dst_ctx = { + .name = "vpe_dst", + .num = 1, + .mids = {1, -1} +}; + +static struct msm_iommu_ctx_dev mdp_vg1_ctx = { + .name = "mdp_vg1", + .num = 0, + .mids = {0, 2, -1} +}; + +static struct msm_iommu_ctx_dev mdp_rgb1_ctx = { + .name = "mdp_rgb1", + .num = 1, + .mids = {1, 3, 4, 5, 6, 7, 8, 9, 10, -1} +}; + +static struct msm_iommu_ctx_dev mdp_vg2_ctx = { + .name = "mdp_vg2", + .num = 0, + .mids = {0, 2, -1} +}; + +static struct msm_iommu_ctx_dev mdp_rgb2_ctx = { + .name = "mdp_rgb2", + .num = 1, + .mids = {1, 3, 4, 5, 6, 7, 8, 9, 10, -1} +}; + +static struct msm_iommu_ctx_dev rot_src_ctx = { + .name = "rot_src", + .num = 0, + .mids = {0, -1} +}; + +static struct msm_iommu_ctx_dev rot_dst_ctx = { + .name = "rot_dst", + .num = 1, + .mids = {1, -1} +}; + +static struct msm_iommu_ctx_dev ijpeg_src_ctx = { + .name = "ijpeg_src", + .num = 0, + .mids = {0, -1} +}; + +static struct msm_iommu_ctx_dev ijpeg_dst_ctx = { + .name = "ijpeg_dst", + .num = 1, + .mids = {1, -1} +}; + +static struct msm_iommu_ctx_dev vfe_imgwr_ctx = { + .name = "vfe_imgwr", + .num = 0, + .mids = {2, 3, 4, 5, 6, 7, 8, -1} +}; + +static struct msm_iommu_ctx_dev vfe_misc_ctx = { + .name = "vfe_misc", + .num = 1, + .mids = {0, 1, 9, -1} +}; + +static struct msm_iommu_ctx_dev vcodec_a_stream_ctx = { + .name = "vcodec_a_stream", + .num = 0, + .mids = {2, 5, -1} +}; + +static struct msm_iommu_ctx_dev vcodec_a_mm1_ctx = { + .name = "vcodec_a_mm1", + .num = 1, + .mids = {0, 1, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, -1} +}; + +static struct msm_iommu_ctx_dev vcodec_b_mm2_ctx = { + .name = "vcodec_b_mm2", + .num = 0, + .mids = {0, 1, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, -1} +}; + +static struct msm_iommu_ctx_dev gfx3d_user_ctx = { + .name = "gfx3d_user", + .num = 0, + .mids = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, -1} +}; + +static struct msm_iommu_ctx_dev gfx3d_priv_ctx = { + .name = "gfx3d_priv", + .num = 1, + .mids = {16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, + 31, -1} +}; + +static struct msm_iommu_ctx_dev gfx2d0_2d0_ctx = { + .name = "gfx2d0_2d0", + .num = 0, + .mids = {0, 1, 2, 3, 4, 5, 6, 7, -1} +}; + +static struct msm_iommu_ctx_dev gfx2d1_2d1_ctx = { + .name = "gfx2d1_2d1", + .num = 0, + .mids = {0, 1, 2, 3, 4, 5, 6, 7, -1} +}; + +static struct platform_device msm_device_jpegd_src_ctx = { + .name = "msm_iommu_ctx", + .id = 0, + .dev = { + .parent = &msm_device_iommu_jpegd.dev, + }, +}; + +static struct platform_device msm_device_jpegd_dst_ctx = { + .name = "msm_iommu_ctx", + .id = 1, + .dev = { + .parent = &msm_device_iommu_jpegd.dev, + }, +}; + +static struct platform_device msm_device_vpe_src_ctx = { + .name = "msm_iommu_ctx", + .id = 2, + .dev = { + .parent = &msm_device_iommu_vpe.dev, + }, +}; + +static struct platform_device msm_device_vpe_dst_ctx = { + .name = "msm_iommu_ctx", + .id = 3, + .dev = { + .parent = &msm_device_iommu_vpe.dev, + }, +}; + +static struct platform_device msm_device_mdp_vg1_ctx = { + .name = "msm_iommu_ctx", + .id = 4, + .dev = { + .parent = &msm_device_iommu_mdp0.dev, + }, +}; + +static struct platform_device msm_device_mdp_rgb1_ctx = { + .name = "msm_iommu_ctx", + .id = 5, + .dev = { + .parent = &msm_device_iommu_mdp0.dev, + }, +}; + +static struct platform_device msm_device_mdp_vg2_ctx = { + .name = "msm_iommu_ctx", + .id = 6, + .dev = { + .parent = &msm_device_iommu_mdp1.dev, + }, +}; + +static struct platform_device msm_device_mdp_rgb2_ctx = { + .name = "msm_iommu_ctx", + .id = 7, + .dev = { + .parent = &msm_device_iommu_mdp1.dev, + }, +}; + +static struct platform_device msm_device_rot_src_ctx = { + .name = "msm_iommu_ctx", + .id = 8, + .dev = { + .parent = &msm_device_iommu_rot.dev, + }, +}; + +static struct platform_device msm_device_rot_dst_ctx = { + .name = "msm_iommu_ctx", + .id = 9, + .dev = { + .parent = &msm_device_iommu_rot.dev, + }, +}; + +static struct platform_device msm_device_ijpeg_src_ctx = { + .name = "msm_iommu_ctx", + .id = 10, + .dev = { + .parent = &msm_device_iommu_ijpeg.dev, + }, +}; + +static struct platform_device msm_device_ijpeg_dst_ctx = { + .name = "msm_iommu_ctx", + .id = 11, + .dev = { + .parent = &msm_device_iommu_ijpeg.dev, + }, +}; + +static struct platform_device msm_device_vfe_imgwr_ctx = { + .name = "msm_iommu_ctx", + .id = 12, + .dev = { + .parent = &msm_device_iommu_vfe.dev, + }, +}; + +static struct platform_device msm_device_vfe_misc_ctx = { + .name = "msm_iommu_ctx", + .id = 13, + .dev = { + .parent = &msm_device_iommu_vfe.dev, + }, +}; + +static struct platform_device msm_device_vcodec_a_stream_ctx = { + .name = "msm_iommu_ctx", + .id = 14, + .dev = { + .parent = &msm_device_iommu_vcodec_a.dev, + }, +}; + +static struct platform_device msm_device_vcodec_a_mm1_ctx = { + .name = "msm_iommu_ctx", + .id = 15, + .dev = { + .parent = &msm_device_iommu_vcodec_a.dev, + }, +}; + +static struct platform_device msm_device_vcodec_b_mm2_ctx = { + .name = "msm_iommu_ctx", + .id = 16, + .dev = { + .parent = &msm_device_iommu_vcodec_b.dev, + }, +}; + +static struct platform_device msm_device_gfx3d_user_ctx = { + .name = "msm_iommu_ctx", + .id = 17, + .dev = { + .parent = &msm_device_iommu_gfx3d.dev, + }, +}; + +static struct platform_device msm_device_gfx3d_priv_ctx = { + .name = "msm_iommu_ctx", + .id = 18, + .dev = { + .parent = &msm_device_iommu_gfx3d.dev, + }, +}; + +static struct platform_device msm_device_gfx2d0_2d0_ctx = { + .name = "msm_iommu_ctx", + .id = 19, + .dev = { + .parent = &msm_device_iommu_gfx2d0.dev, + }, +}; + +static struct platform_device msm_device_gfx2d1_2d1_ctx = { + .name = "msm_iommu_ctx", + .id = 20, + .dev = { + .parent = &msm_device_iommu_gfx2d1.dev, + }, +}; + +static struct platform_device *msm_iommu_devs[] = { + &msm_device_iommu_jpegd, + &msm_device_iommu_vpe, + &msm_device_iommu_mdp0, + &msm_device_iommu_mdp1, + &msm_device_iommu_rot, + &msm_device_iommu_ijpeg, + &msm_device_iommu_vfe, + &msm_device_iommu_vcodec_a, + &msm_device_iommu_vcodec_b, + &msm_device_iommu_gfx3d, + &msm_device_iommu_gfx2d0, + &msm_device_iommu_gfx2d1, +}; + +static struct msm_iommu_dev *msm_iommu_data[] = { + &jpegd_iommu, + &vpe_iommu, + &mdp0_iommu, + &mdp1_iommu, + &rot_iommu, + &ijpeg_iommu, + &vfe_iommu, + &vcodec_a_iommu, + &vcodec_b_iommu, + &gfx3d_iommu, + &gfx2d0_iommu, + &gfx2d1_iommu, +}; + +static struct platform_device *msm_iommu_ctx_devs[] = { + &msm_device_jpegd_src_ctx, + &msm_device_jpegd_dst_ctx, + &msm_device_vpe_src_ctx, + &msm_device_vpe_dst_ctx, + &msm_device_mdp_vg1_ctx, + &msm_device_mdp_rgb1_ctx, + &msm_device_mdp_vg2_ctx, + &msm_device_mdp_rgb2_ctx, + &msm_device_rot_src_ctx, + &msm_device_rot_dst_ctx, + &msm_device_ijpeg_src_ctx, + &msm_device_ijpeg_dst_ctx, + &msm_device_vfe_imgwr_ctx, + &msm_device_vfe_misc_ctx, + &msm_device_vcodec_a_stream_ctx, + &msm_device_vcodec_a_mm1_ctx, + &msm_device_vcodec_b_mm2_ctx, + &msm_device_gfx3d_user_ctx, + &msm_device_gfx3d_priv_ctx, + &msm_device_gfx2d0_2d0_ctx, + &msm_device_gfx2d1_2d1_ctx, +}; + +static struct msm_iommu_ctx_dev *msm_iommu_ctx_data[] = { + &jpegd_src_ctx, + &jpegd_dst_ctx, + &vpe_src_ctx, + &vpe_dst_ctx, + &mdp_vg1_ctx, + &mdp_rgb1_ctx, + &mdp_vg2_ctx, + &mdp_rgb2_ctx, + &rot_src_ctx, + &rot_dst_ctx, + &ijpeg_src_ctx, + &ijpeg_dst_ctx, + &vfe_imgwr_ctx, + &vfe_misc_ctx, + &vcodec_a_stream_ctx, + &vcodec_a_mm1_ctx, + &vcodec_b_mm2_ctx, + &gfx3d_user_ctx, + &gfx3d_priv_ctx, + &gfx2d0_2d0_ctx, + &gfx2d1_2d1_ctx, +}; + +static int __init msm8x60_iommu_init(void) +{ + int ret, i; + + ret = platform_device_register(&msm_root_iommu_dev); + if (ret != 0) { + pr_err("Failed to register root IOMMU device!\n"); + goto failure; + } + + for (i = 0; i < ARRAY_SIZE(msm_iommu_devs); i++) { + ret = platform_device_add_data(msm_iommu_devs[i], + msm_iommu_data[i], + sizeof(struct msm_iommu_dev)); + if (ret != 0) { + pr_err("platform_device_add_data failed, " + "i = %d\n", i); + goto failure_unwind; + } + + ret = platform_device_register(msm_iommu_devs[i]); + + if (ret != 0) { + pr_err("platform_device_register iommu failed, " + "i = %d\n", i); + goto failure_unwind; + } + } + + for (i = 0; i < ARRAY_SIZE(msm_iommu_ctx_devs); i++) { + ret = platform_device_add_data(msm_iommu_ctx_devs[i], + msm_iommu_ctx_data[i], + sizeof(*msm_iommu_ctx_devs[i])); + if (ret != 0) { + pr_err("platform_device_add_data iommu failed, " + "i = %d\n", i); + goto failure_unwind2; + } + + ret = platform_device_register(msm_iommu_ctx_devs[i]); + if (ret != 0) { + pr_err("platform_device_register ctx failed, " + "i = %d\n", i); + goto failure_unwind2; + } + } + return 0; + +failure_unwind2: + while (--i >= 0) + platform_device_unregister(msm_iommu_ctx_devs[i]); +failure_unwind: + while (--i >= 0) + platform_device_unregister(msm_iommu_devs[i]); + + platform_device_unregister(&msm_root_iommu_dev); +failure: + return ret; +} + +static void __exit msm8x60_iommu_exit(void) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(msm_iommu_ctx_devs); i++) + platform_device_unregister(msm_iommu_ctx_devs[i]); + + for (i = 0; i < ARRAY_SIZE(msm_iommu_devs); ++i) + platform_device_unregister(msm_iommu_devs[i]); + + platform_device_unregister(&msm_root_iommu_dev); +} + +subsys_initcall(msm8x60_iommu_init); +module_exit(msm8x60_iommu_exit); + +MODULE_LICENSE("GPL v2"); +MODULE_AUTHOR("Stepan Moskovchenko "); diff --git a/arch/arm/mach-msm/devices-msm8x60-iommu.c b/arch/arm/mach-msm/devices-msm8x60-iommu.c deleted file mode 100644 index f9e7bd3..0000000 --- a/arch/arm/mach-msm/devices-msm8x60-iommu.c +++ /dev/null @@ -1,906 +0,0 @@ -/* Copyright (c) 2010, Code Aurora Forum. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA - * 02110-1301, USA. - */ - -#include -#include -#include - -#include -#include -#include - -static struct resource msm_iommu_jpegd_resources[] = { - { - .start = MSM_IOMMU_JPEGD_PHYS, - .end = MSM_IOMMU_JPEGD_PHYS + MSM_IOMMU_JPEGD_SIZE - 1, - .name = "physbase", - .flags = IORESOURCE_MEM, - }, - { - .name = "nonsecure_irq", - .start = SMMU_JPEGD_CB_SC_NON_SECURE_IRQ, - .end = SMMU_JPEGD_CB_SC_NON_SECURE_IRQ, - .flags = IORESOURCE_IRQ, - }, - { - .name = "secure_irq", - .start = SMMU_JPEGD_CB_SC_SECURE_IRQ, - .end = SMMU_JPEGD_CB_SC_SECURE_IRQ, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct resource msm_iommu_vpe_resources[] = { - { - .start = MSM_IOMMU_VPE_PHYS, - .end = MSM_IOMMU_VPE_PHYS + MSM_IOMMU_VPE_SIZE - 1, - .name = "physbase", - .flags = IORESOURCE_MEM, - }, - { - .name = "nonsecure_irq", - .start = SMMU_VPE_CB_SC_NON_SECURE_IRQ, - .end = SMMU_VPE_CB_SC_NON_SECURE_IRQ, - .flags = IORESOURCE_IRQ, - }, - { - .name = "secure_irq", - .start = SMMU_VPE_CB_SC_SECURE_IRQ, - .end = SMMU_VPE_CB_SC_SECURE_IRQ, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct resource msm_iommu_mdp0_resources[] = { - { - .start = MSM_IOMMU_MDP0_PHYS, - .end = MSM_IOMMU_MDP0_PHYS + MSM_IOMMU_MDP0_SIZE - 1, - .name = "physbase", - .flags = IORESOURCE_MEM, - }, - { - .name = "nonsecure_irq", - .start = SMMU_MDP0_CB_SC_NON_SECURE_IRQ, - .end = SMMU_MDP0_CB_SC_NON_SECURE_IRQ, - .flags = IORESOURCE_IRQ, - }, - { - .name = "secure_irq", - .start = SMMU_MDP0_CB_SC_SECURE_IRQ, - .end = SMMU_MDP0_CB_SC_SECURE_IRQ, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct resource msm_iommu_mdp1_resources[] = { - { - .start = MSM_IOMMU_MDP1_PHYS, - .end = MSM_IOMMU_MDP1_PHYS + MSM_IOMMU_MDP1_SIZE - 1, - .name = "physbase", - .flags = IORESOURCE_MEM, - }, - { - .name = "nonsecure_irq", - .start = SMMU_MDP1_CB_SC_NON_SECURE_IRQ, - .end = SMMU_MDP1_CB_SC_NON_SECURE_IRQ, - .flags = IORESOURCE_IRQ, - }, - { - .name = "secure_irq", - .start = SMMU_MDP1_CB_SC_SECURE_IRQ, - .end = SMMU_MDP1_CB_SC_SECURE_IRQ, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct resource msm_iommu_rot_resources[] = { - { - .start = MSM_IOMMU_ROT_PHYS, - .end = MSM_IOMMU_ROT_PHYS + MSM_IOMMU_ROT_SIZE - 1, - .name = "physbase", - .flags = IORESOURCE_MEM, - }, - { - .name = "nonsecure_irq", - .start = SMMU_ROT_CB_SC_NON_SECURE_IRQ, - .end = SMMU_ROT_CB_SC_NON_SECURE_IRQ, - .flags = IORESOURCE_IRQ, - }, - { - .name = "secure_irq", - .start = SMMU_ROT_CB_SC_SECURE_IRQ, - .end = SMMU_ROT_CB_SC_SECURE_IRQ, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct resource msm_iommu_ijpeg_resources[] = { - { - .start = MSM_IOMMU_IJPEG_PHYS, - .end = MSM_IOMMU_IJPEG_PHYS + MSM_IOMMU_IJPEG_SIZE - 1, - .name = "physbase", - .flags = IORESOURCE_MEM, - }, - { - .name = "nonsecure_irq", - .start = SMMU_IJPEG_CB_SC_NON_SECURE_IRQ, - .end = SMMU_IJPEG_CB_SC_NON_SECURE_IRQ, - .flags = IORESOURCE_IRQ, - }, - { - .name = "secure_irq", - .start = SMMU_IJPEG_CB_SC_SECURE_IRQ, - .end = SMMU_IJPEG_CB_SC_SECURE_IRQ, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct resource msm_iommu_vfe_resources[] = { - { - .start = MSM_IOMMU_VFE_PHYS, - .end = MSM_IOMMU_VFE_PHYS + MSM_IOMMU_VFE_SIZE - 1, - .name = "physbase", - .flags = IORESOURCE_MEM, - }, - { - .name = "nonsecure_irq", - .start = SMMU_VFE_CB_SC_NON_SECURE_IRQ, - .end = SMMU_VFE_CB_SC_NON_SECURE_IRQ, - .flags = IORESOURCE_IRQ, - }, - { - .name = "secure_irq", - .start = SMMU_VFE_CB_SC_SECURE_IRQ, - .end = SMMU_VFE_CB_SC_SECURE_IRQ, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct resource msm_iommu_vcodec_a_resources[] = { - { - .start = MSM_IOMMU_VCODEC_A_PHYS, - .end = MSM_IOMMU_VCODEC_A_PHYS + MSM_IOMMU_VCODEC_A_SIZE - 1, - .name = "physbase", - .flags = IORESOURCE_MEM, - }, - { - .name = "nonsecure_irq", - .start = SMMU_VCODEC_A_CB_SC_NON_SECURE_IRQ, - .end = SMMU_VCODEC_A_CB_SC_NON_SECURE_IRQ, - .flags = IORESOURCE_IRQ, - }, - { - .name = "secure_irq", - .start = SMMU_VCODEC_A_CB_SC_SECURE_IRQ, - .end = SMMU_VCODEC_A_CB_SC_SECURE_IRQ, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct resource msm_iommu_vcodec_b_resources[] = { - { - .start = MSM_IOMMU_VCODEC_B_PHYS, - .end = MSM_IOMMU_VCODEC_B_PHYS + MSM_IOMMU_VCODEC_B_SIZE - 1, - .name = "physbase", - .flags = IORESOURCE_MEM, - }, - { - .name = "nonsecure_irq", - .start = SMMU_VCODEC_B_CB_SC_NON_SECURE_IRQ, - .end = SMMU_VCODEC_B_CB_SC_NON_SECURE_IRQ, - .flags = IORESOURCE_IRQ, - }, - { - .name = "secure_irq", - .start = SMMU_VCODEC_B_CB_SC_SECURE_IRQ, - .end = SMMU_VCODEC_B_CB_SC_SECURE_IRQ, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct resource msm_iommu_gfx3d_resources[] = { - { - .start = MSM_IOMMU_GFX3D_PHYS, - .end = MSM_IOMMU_GFX3D_PHYS + MSM_IOMMU_GFX3D_SIZE - 1, - .name = "physbase", - .flags = IORESOURCE_MEM, - }, - { - .name = "nonsecure_irq", - .start = SMMU_GFX3D_CB_SC_NON_SECURE_IRQ, - .end = SMMU_GFX3D_CB_SC_NON_SECURE_IRQ, - .flags = IORESOURCE_IRQ, - }, - { - .name = "secure_irq", - .start = SMMU_GFX3D_CB_SC_SECURE_IRQ, - .end = SMMU_GFX3D_CB_SC_SECURE_IRQ, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct resource msm_iommu_gfx2d0_resources[] = { - { - .start = MSM_IOMMU_GFX2D0_PHYS, - .end = MSM_IOMMU_GFX2D0_PHYS + MSM_IOMMU_GFX2D0_SIZE - 1, - .name = "physbase", - .flags = IORESOURCE_MEM, - }, - { - .name = "nonsecure_irq", - .start = SMMU_GFX2D0_CB_SC_NON_SECURE_IRQ, - .end = SMMU_GFX2D0_CB_SC_NON_SECURE_IRQ, - .flags = IORESOURCE_IRQ, - }, - { - .name = "secure_irq", - .start = SMMU_GFX2D0_CB_SC_SECURE_IRQ, - .end = SMMU_GFX2D0_CB_SC_SECURE_IRQ, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct resource msm_iommu_gfx2d1_resources[] = { - { - .start = MSM_IOMMU_GFX2D1_PHYS, - .end = MSM_IOMMU_GFX2D1_PHYS + MSM_IOMMU_GFX2D1_SIZE - 1, - .name = "physbase", - .flags = IORESOURCE_MEM, - }, - { - .name = "nonsecure_irq", - .start = SMMU_GFX2D1_CB_SC_NON_SECURE_IRQ, - .end = SMMU_GFX2D1_CB_SC_NON_SECURE_IRQ, - .flags = IORESOURCE_IRQ, - }, - { - .name = "secure_irq", - .start = SMMU_GFX2D1_CB_SC_SECURE_IRQ, - .end = SMMU_GFX2D1_CB_SC_SECURE_IRQ, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device msm_root_iommu_dev = { - .name = "msm_iommu", - .id = -1, -}; - -static struct msm_iommu_dev jpegd_iommu = { - .name = "jpegd", - .clk_rate = -1 -}; - -static struct msm_iommu_dev vpe_iommu = { - .name = "vpe" -}; - -static struct msm_iommu_dev mdp0_iommu = { - .name = "mdp0" -}; - -static struct msm_iommu_dev mdp1_iommu = { - .name = "mdp1" -}; - -static struct msm_iommu_dev rot_iommu = { - .name = "rot" -}; - -static struct msm_iommu_dev ijpeg_iommu = { - .name = "ijpeg" -}; - -static struct msm_iommu_dev vfe_iommu = { - .name = "vfe", - .clk_rate = -1 -}; - -static struct msm_iommu_dev vcodec_a_iommu = { - .name = "vcodec_a" -}; - -static struct msm_iommu_dev vcodec_b_iommu = { - .name = "vcodec_b" -}; - -static struct msm_iommu_dev gfx3d_iommu = { - .name = "gfx3d", - .clk_rate = 27000000 -}; - -static struct msm_iommu_dev gfx2d0_iommu = { - .name = "gfx2d0", - .clk_rate = 27000000 -}; - -static struct msm_iommu_dev gfx2d1_iommu = { - .name = "gfx2d1", - .clk_rate = 27000000 -}; - -static struct platform_device msm_device_iommu_jpegd = { - .name = "msm_iommu", - .id = 0, - .dev = { - .parent = &msm_root_iommu_dev.dev, - }, - .num_resources = ARRAY_SIZE(msm_iommu_jpegd_resources), - .resource = msm_iommu_jpegd_resources, -}; - -static struct platform_device msm_device_iommu_vpe = { - .name = "msm_iommu", - .id = 1, - .dev = { - .parent = &msm_root_iommu_dev.dev, - }, - .num_resources = ARRAY_SIZE(msm_iommu_vpe_resources), - .resource = msm_iommu_vpe_resources, -}; - -static struct platform_device msm_device_iommu_mdp0 = { - .name = "msm_iommu", - .id = 2, - .dev = { - .parent = &msm_root_iommu_dev.dev, - }, - .num_resources = ARRAY_SIZE(msm_iommu_mdp0_resources), - .resource = msm_iommu_mdp0_resources, -}; - -static struct platform_device msm_device_iommu_mdp1 = { - .name = "msm_iommu", - .id = 3, - .dev = { - .parent = &msm_root_iommu_dev.dev, - }, - .num_resources = ARRAY_SIZE(msm_iommu_mdp1_resources), - .resource = msm_iommu_mdp1_resources, -}; - -static struct platform_device msm_device_iommu_rot = { - .name = "msm_iommu", - .id = 4, - .dev = { - .parent = &msm_root_iommu_dev.dev, - }, - .num_resources = ARRAY_SIZE(msm_iommu_rot_resources), - .resource = msm_iommu_rot_resources, -}; - -static struct platform_device msm_device_iommu_ijpeg = { - .name = "msm_iommu", - .id = 5, - .dev = { - .parent = &msm_root_iommu_dev.dev, - }, - .num_resources = ARRAY_SIZE(msm_iommu_ijpeg_resources), - .resource = msm_iommu_ijpeg_resources, -}; - -static struct platform_device msm_device_iommu_vfe = { - .name = "msm_iommu", - .id = 6, - .dev = { - .parent = &msm_root_iommu_dev.dev, - }, - .num_resources = ARRAY_SIZE(msm_iommu_vfe_resources), - .resource = msm_iommu_vfe_resources, -}; - -static struct platform_device msm_device_iommu_vcodec_a = { - .name = "msm_iommu", - .id = 7, - .dev = { - .parent = &msm_root_iommu_dev.dev, - }, - .num_resources = ARRAY_SIZE(msm_iommu_vcodec_a_resources), - .resource = msm_iommu_vcodec_a_resources, -}; - -static struct platform_device msm_device_iommu_vcodec_b = { - .name = "msm_iommu", - .id = 8, - .dev = { - .parent = &msm_root_iommu_dev.dev, - }, - .num_resources = ARRAY_SIZE(msm_iommu_vcodec_b_resources), - .resource = msm_iommu_vcodec_b_resources, -}; - -static struct platform_device msm_device_iommu_gfx3d = { - .name = "msm_iommu", - .id = 9, - .dev = { - .parent = &msm_root_iommu_dev.dev, - }, - .num_resources = ARRAY_SIZE(msm_iommu_gfx3d_resources), - .resource = msm_iommu_gfx3d_resources, -}; - -static struct platform_device msm_device_iommu_gfx2d0 = { - .name = "msm_iommu", - .id = 10, - .dev = { - .parent = &msm_root_iommu_dev.dev, - }, - .num_resources = ARRAY_SIZE(msm_iommu_gfx2d0_resources), - .resource = msm_iommu_gfx2d0_resources, -}; - -struct platform_device msm_device_iommu_gfx2d1 = { - .name = "msm_iommu", - .id = 11, - .dev = { - .parent = &msm_root_iommu_dev.dev, - }, - .num_resources = ARRAY_SIZE(msm_iommu_gfx2d1_resources), - .resource = msm_iommu_gfx2d1_resources, -}; - -static struct msm_iommu_ctx_dev jpegd_src_ctx = { - .name = "jpegd_src", - .num = 0, - .mids = {0, -1} -}; - -static struct msm_iommu_ctx_dev jpegd_dst_ctx = { - .name = "jpegd_dst", - .num = 1, - .mids = {1, -1} -}; - -static struct msm_iommu_ctx_dev vpe_src_ctx = { - .name = "vpe_src", - .num = 0, - .mids = {0, -1} -}; - -static struct msm_iommu_ctx_dev vpe_dst_ctx = { - .name = "vpe_dst", - .num = 1, - .mids = {1, -1} -}; - -static struct msm_iommu_ctx_dev mdp_vg1_ctx = { - .name = "mdp_vg1", - .num = 0, - .mids = {0, 2, -1} -}; - -static struct msm_iommu_ctx_dev mdp_rgb1_ctx = { - .name = "mdp_rgb1", - .num = 1, - .mids = {1, 3, 4, 5, 6, 7, 8, 9, 10, -1} -}; - -static struct msm_iommu_ctx_dev mdp_vg2_ctx = { - .name = "mdp_vg2", - .num = 0, - .mids = {0, 2, -1} -}; - -static struct msm_iommu_ctx_dev mdp_rgb2_ctx = { - .name = "mdp_rgb2", - .num = 1, - .mids = {1, 3, 4, 5, 6, 7, 8, 9, 10, -1} -}; - -static struct msm_iommu_ctx_dev rot_src_ctx = { - .name = "rot_src", - .num = 0, - .mids = {0, -1} -}; - -static struct msm_iommu_ctx_dev rot_dst_ctx = { - .name = "rot_dst", - .num = 1, - .mids = {1, -1} -}; - -static struct msm_iommu_ctx_dev ijpeg_src_ctx = { - .name = "ijpeg_src", - .num = 0, - .mids = {0, -1} -}; - -static struct msm_iommu_ctx_dev ijpeg_dst_ctx = { - .name = "ijpeg_dst", - .num = 1, - .mids = {1, -1} -}; - -static struct msm_iommu_ctx_dev vfe_imgwr_ctx = { - .name = "vfe_imgwr", - .num = 0, - .mids = {2, 3, 4, 5, 6, 7, 8, -1} -}; - -static struct msm_iommu_ctx_dev vfe_misc_ctx = { - .name = "vfe_misc", - .num = 1, - .mids = {0, 1, 9, -1} -}; - -static struct msm_iommu_ctx_dev vcodec_a_stream_ctx = { - .name = "vcodec_a_stream", - .num = 0, - .mids = {2, 5, -1} -}; - -static struct msm_iommu_ctx_dev vcodec_a_mm1_ctx = { - .name = "vcodec_a_mm1", - .num = 1, - .mids = {0, 1, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, -1} -}; - -static struct msm_iommu_ctx_dev vcodec_b_mm2_ctx = { - .name = "vcodec_b_mm2", - .num = 0, - .mids = {0, 1, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, -1} -}; - -static struct msm_iommu_ctx_dev gfx3d_user_ctx = { - .name = "gfx3d_user", - .num = 0, - .mids = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, -1} -}; - -static struct msm_iommu_ctx_dev gfx3d_priv_ctx = { - .name = "gfx3d_priv", - .num = 1, - .mids = {16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, - 31, -1} -}; - -static struct msm_iommu_ctx_dev gfx2d0_2d0_ctx = { - .name = "gfx2d0_2d0", - .num = 0, - .mids = {0, 1, 2, 3, 4, 5, 6, 7, -1} -}; - -static struct msm_iommu_ctx_dev gfx2d1_2d1_ctx = { - .name = "gfx2d1_2d1", - .num = 0, - .mids = {0, 1, 2, 3, 4, 5, 6, 7, -1} -}; - -static struct platform_device msm_device_jpegd_src_ctx = { - .name = "msm_iommu_ctx", - .id = 0, - .dev = { - .parent = &msm_device_iommu_jpegd.dev, - }, -}; - -static struct platform_device msm_device_jpegd_dst_ctx = { - .name = "msm_iommu_ctx", - .id = 1, - .dev = { - .parent = &msm_device_iommu_jpegd.dev, - }, -}; - -static struct platform_device msm_device_vpe_src_ctx = { - .name = "msm_iommu_ctx", - .id = 2, - .dev = { - .parent = &msm_device_iommu_vpe.dev, - }, -}; - -static struct platform_device msm_device_vpe_dst_ctx = { - .name = "msm_iommu_ctx", - .id = 3, - .dev = { - .parent = &msm_device_iommu_vpe.dev, - }, -}; - -static struct platform_device msm_device_mdp_vg1_ctx = { - .name = "msm_iommu_ctx", - .id = 4, - .dev = { - .parent = &msm_device_iommu_mdp0.dev, - }, -}; - -static struct platform_device msm_device_mdp_rgb1_ctx = { - .name = "msm_iommu_ctx", - .id = 5, - .dev = { - .parent = &msm_device_iommu_mdp0.dev, - }, -}; - -static struct platform_device msm_device_mdp_vg2_ctx = { - .name = "msm_iommu_ctx", - .id = 6, - .dev = { - .parent = &msm_device_iommu_mdp1.dev, - }, -}; - -static struct platform_device msm_device_mdp_rgb2_ctx = { - .name = "msm_iommu_ctx", - .id = 7, - .dev = { - .parent = &msm_device_iommu_mdp1.dev, - }, -}; - -static struct platform_device msm_device_rot_src_ctx = { - .name = "msm_iommu_ctx", - .id = 8, - .dev = { - .parent = &msm_device_iommu_rot.dev, - }, -}; - -static struct platform_device msm_device_rot_dst_ctx = { - .name = "msm_iommu_ctx", - .id = 9, - .dev = { - .parent = &msm_device_iommu_rot.dev, - }, -}; - -static struct platform_device msm_device_ijpeg_src_ctx = { - .name = "msm_iommu_ctx", - .id = 10, - .dev = { - .parent = &msm_device_iommu_ijpeg.dev, - }, -}; - -static struct platform_device msm_device_ijpeg_dst_ctx = { - .name = "msm_iommu_ctx", - .id = 11, - .dev = { - .parent = &msm_device_iommu_ijpeg.dev, - }, -}; - -static struct platform_device msm_device_vfe_imgwr_ctx = { - .name = "msm_iommu_ctx", - .id = 12, - .dev = { - .parent = &msm_device_iommu_vfe.dev, - }, -}; - -static struct platform_device msm_device_vfe_misc_ctx = { - .name = "msm_iommu_ctx", - .id = 13, - .dev = { - .parent = &msm_device_iommu_vfe.dev, - }, -}; - -static struct platform_device msm_device_vcodec_a_stream_ctx = { - .name = "msm_iommu_ctx", - .id = 14, - .dev = { - .parent = &msm_device_iommu_vcodec_a.dev, - }, -}; - -static struct platform_device msm_device_vcodec_a_mm1_ctx = { - .name = "msm_iommu_ctx", - .id = 15, - .dev = { - .parent = &msm_device_iommu_vcodec_a.dev, - }, -}; - -static struct platform_device msm_device_vcodec_b_mm2_ctx = { - .name = "msm_iommu_ctx", - .id = 16, - .dev = { - .parent = &msm_device_iommu_vcodec_b.dev, - }, -}; - -static struct platform_device msm_device_gfx3d_user_ctx = { - .name = "msm_iommu_ctx", - .id = 17, - .dev = { - .parent = &msm_device_iommu_gfx3d.dev, - }, -}; - -static struct platform_device msm_device_gfx3d_priv_ctx = { - .name = "msm_iommu_ctx", - .id = 18, - .dev = { - .parent = &msm_device_iommu_gfx3d.dev, - }, -}; - -static struct platform_device msm_device_gfx2d0_2d0_ctx = { - .name = "msm_iommu_ctx", - .id = 19, - .dev = { - .parent = &msm_device_iommu_gfx2d0.dev, - }, -}; - -static struct platform_device msm_device_gfx2d1_2d1_ctx = { - .name = "msm_iommu_ctx", - .id = 20, - .dev = { - .parent = &msm_device_iommu_gfx2d1.dev, - }, -}; - -static struct platform_device *msm_iommu_devs[] = { - &msm_device_iommu_jpegd, - &msm_device_iommu_vpe, - &msm_device_iommu_mdp0, - &msm_device_iommu_mdp1, - &msm_device_iommu_rot, - &msm_device_iommu_ijpeg, - &msm_device_iommu_vfe, - &msm_device_iommu_vcodec_a, - &msm_device_iommu_vcodec_b, - &msm_device_iommu_gfx3d, - &msm_device_iommu_gfx2d0, - &msm_device_iommu_gfx2d1, -}; - -static struct msm_iommu_dev *msm_iommu_data[] = { - &jpegd_iommu, - &vpe_iommu, - &mdp0_iommu, - &mdp1_iommu, - &rot_iommu, - &ijpeg_iommu, - &vfe_iommu, - &vcodec_a_iommu, - &vcodec_b_iommu, - &gfx3d_iommu, - &gfx2d0_iommu, - &gfx2d1_iommu, -}; - -static struct platform_device *msm_iommu_ctx_devs[] = { - &msm_device_jpegd_src_ctx, - &msm_device_jpegd_dst_ctx, - &msm_device_vpe_src_ctx, - &msm_device_vpe_dst_ctx, - &msm_device_mdp_vg1_ctx, - &msm_device_mdp_rgb1_ctx, - &msm_device_mdp_vg2_ctx, - &msm_device_mdp_rgb2_ctx, - &msm_device_rot_src_ctx, - &msm_device_rot_dst_ctx, - &msm_device_ijpeg_src_ctx, - &msm_device_ijpeg_dst_ctx, - &msm_device_vfe_imgwr_ctx, - &msm_device_vfe_misc_ctx, - &msm_device_vcodec_a_stream_ctx, - &msm_device_vcodec_a_mm1_ctx, - &msm_device_vcodec_b_mm2_ctx, - &msm_device_gfx3d_user_ctx, - &msm_device_gfx3d_priv_ctx, - &msm_device_gfx2d0_2d0_ctx, - &msm_device_gfx2d1_2d1_ctx, -}; - -static struct msm_iommu_ctx_dev *msm_iommu_ctx_data[] = { - &jpegd_src_ctx, - &jpegd_dst_ctx, - &vpe_src_ctx, - &vpe_dst_ctx, - &mdp_vg1_ctx, - &mdp_rgb1_ctx, - &mdp_vg2_ctx, - &mdp_rgb2_ctx, - &rot_src_ctx, - &rot_dst_ctx, - &ijpeg_src_ctx, - &ijpeg_dst_ctx, - &vfe_imgwr_ctx, - &vfe_misc_ctx, - &vcodec_a_stream_ctx, - &vcodec_a_mm1_ctx, - &vcodec_b_mm2_ctx, - &gfx3d_user_ctx, - &gfx3d_priv_ctx, - &gfx2d0_2d0_ctx, - &gfx2d1_2d1_ctx, -}; - -static int __init msm8x60_iommu_init(void) -{ - int ret, i; - - ret = platform_device_register(&msm_root_iommu_dev); - if (ret != 0) { - pr_err("Failed to register root IOMMU device!\n"); - goto failure; - } - - for (i = 0; i < ARRAY_SIZE(msm_iommu_devs); i++) { - ret = platform_device_add_data(msm_iommu_devs[i], - msm_iommu_data[i], - sizeof(struct msm_iommu_dev)); - if (ret != 0) { - pr_err("platform_device_add_data failed, " - "i = %d\n", i); - goto failure_unwind; - } - - ret = platform_device_register(msm_iommu_devs[i]); - - if (ret != 0) { - pr_err("platform_device_register iommu failed, " - "i = %d\n", i); - goto failure_unwind; - } - } - - for (i = 0; i < ARRAY_SIZE(msm_iommu_ctx_devs); i++) { - ret = platform_device_add_data(msm_iommu_ctx_devs[i], - msm_iommu_ctx_data[i], - sizeof(*msm_iommu_ctx_devs[i])); - if (ret != 0) { - pr_err("platform_device_add_data iommu failed, " - "i = %d\n", i); - goto failure_unwind2; - } - - ret = platform_device_register(msm_iommu_ctx_devs[i]); - if (ret != 0) { - pr_err("platform_device_register ctx failed, " - "i = %d\n", i); - goto failure_unwind2; - } - } - return 0; - -failure_unwind2: - while (--i >= 0) - platform_device_unregister(msm_iommu_ctx_devs[i]); -failure_unwind: - while (--i >= 0) - platform_device_unregister(msm_iommu_devs[i]); - - platform_device_unregister(&msm_root_iommu_dev); -failure: - return ret; -} - -static void __exit msm8x60_iommu_exit(void) -{ - int i; - - for (i = 0; i < ARRAY_SIZE(msm_iommu_ctx_devs); i++) - platform_device_unregister(msm_iommu_ctx_devs[i]); - - for (i = 0; i < ARRAY_SIZE(msm_iommu_devs); ++i) - platform_device_unregister(msm_iommu_devs[i]); - - platform_device_unregister(&msm_root_iommu_dev); -} - -subsys_initcall(msm8x60_iommu_init); -module_exit(msm8x60_iommu_exit); - -MODULE_LICENSE("GPL v2"); -MODULE_AUTHOR("Stepan Moskovchenko "); diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h b/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h index 5bd18db..3b19b8f 100644 --- a/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h +++ b/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h @@ -62,40 +62,4 @@ #define MSM8X60_TMR0_PHYS 0x02040000 #define MSM8X60_TMR0_SIZE SZ_4K -#define MSM_IOMMU_JPEGD_PHYS 0x07300000 -#define MSM_IOMMU_JPEGD_SIZE SZ_1M - -#define MSM_IOMMU_VPE_PHYS 0x07400000 -#define MSM_IOMMU_VPE_SIZE SZ_1M - -#define MSM_IOMMU_MDP0_PHYS 0x07500000 -#define MSM_IOMMU_MDP0_SIZE SZ_1M - -#define MSM_IOMMU_MDP1_PHYS 0x07600000 -#define MSM_IOMMU_MDP1_SIZE SZ_1M - -#define MSM_IOMMU_ROT_PHYS 0x07700000 -#define MSM_IOMMU_ROT_SIZE SZ_1M - -#define MSM_IOMMU_IJPEG_PHYS 0x07800000 -#define MSM_IOMMU_IJPEG_SIZE SZ_1M - -#define MSM_IOMMU_VFE_PHYS 0x07900000 -#define MSM_IOMMU_VFE_SIZE SZ_1M - -#define MSM_IOMMU_VCODEC_A_PHYS 0x07A00000 -#define MSM_IOMMU_VCODEC_A_SIZE SZ_1M - -#define MSM_IOMMU_VCODEC_B_PHYS 0x07B00000 -#define MSM_IOMMU_VCODEC_B_SIZE SZ_1M - -#define MSM_IOMMU_GFX3D_PHYS 0x07C00000 -#define MSM_IOMMU_GFX3D_SIZE SZ_1M - -#define MSM_IOMMU_GFX2D0_PHYS 0x07D00000 -#define MSM_IOMMU_GFX2D0_SIZE SZ_1M - -#define MSM_IOMMU_GFX2D1_PHYS 0x07E00000 -#define MSM_IOMMU_GFX2D1_SIZE SZ_1M - #endif -- cgit v0.10.2 From 6499f0a8b3f44141431df79923fb8f1d8017e139 Mon Sep 17 00:00:00 2001 From: Stepan Moskovchenko Date: Fri, 11 Feb 2011 12:28:18 -0800 Subject: msm: iommu: Enable IOMMU support for MSM8960 Allow IOMMU to be selected for MSM8960 now that the platform data has been generalized. Signed-off-by: Stepan Moskovchenko Signed-off-by: David Brown diff --git a/arch/arm/mach-msm/Kconfig b/arch/arm/mach-msm/Kconfig index 32b9d1f..997c5bd 100644 --- a/arch/arm/mach-msm/Kconfig +++ b/arch/arm/mach-msm/Kconfig @@ -150,7 +150,7 @@ endmenu config MSM_IOMMU bool "MSM IOMMU Support" - depends on ARCH_MSM8X60 + depends on ARCH_MSM8X60 || ARCH_MSM8960 select IOMMU_API default n help -- cgit v0.10.2 From 3162aa2f1b55849651a05052d3e5f5e640ea44fa Mon Sep 17 00:00:00 2001 From: David Brown Date: Mon, 14 Feb 2011 16:15:26 -0800 Subject: msm: Use explicit GPLv2 licenses Replace a BSD-style license in Code Aurora Forum authored files with an explicit GPLv2. Signed-off-by: David Brown diff --git a/arch/arm/mach-msm/clock-7x30.h b/arch/arm/mach-msm/clock-7x30.h index e16f72f..da8e1c6 100644 --- a/arch/arm/mach-msm/clock-7x30.h +++ b/arch/arm/mach-msm/clock-7x30.h @@ -1,30 +1,13 @@ /* Copyright (c) 2009, Code Aurora Forum. All rights reserved. * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above - * copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided - * with the distribution. - * * Neither the name of Code Aurora Forum, Inc. nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS - * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR - * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE - * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN - * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. */ #ifndef __ARCH_ARM_MACH_MSM_CLOCK_7X30_H diff --git a/arch/arm/mach-msm/clock-pcom.h b/arch/arm/mach-msm/clock-pcom.h index 2c813f1..53dea61 100644 --- a/arch/arm/mach-msm/clock-pcom.h +++ b/arch/arm/mach-msm/clock-pcom.h @@ -1,30 +1,13 @@ /* Copyright (c) 2009, Code Aurora Forum. All rights reserved. * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above - * copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided - * with the distribution. - * * Neither the name of Code Aurora Forum, Inc. nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS - * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR - * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE - * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN - * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. */ #ifndef __ARCH_ARM_MACH_MSM_CLOCK_PCOM_H diff --git a/arch/arm/mach-msm/include/mach/clk.h b/arch/arm/mach-msm/include/mach/clk.h index c05ca40..e8d3842 100644 --- a/arch/arm/mach-msm/include/mach/clk.h +++ b/arch/arm/mach-msm/include/mach/clk.h @@ -1,30 +1,13 @@ /* Copyright (c) 2009, Code Aurora Forum. All rights reserved. * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above - * copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided - * with the distribution. - * * Neither the name of Code Aurora Forum, Inc. nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS - * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR - * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE - * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN - * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. */ #ifndef __MACH_CLK_H #define __MACH_CLK_H diff --git a/arch/arm/mach-msm/include/mach/irqs-7x30.h b/arch/arm/mach-msm/include/mach/irqs-7x30.h index 67c5396..1f15902 100644 --- a/arch/arm/mach-msm/include/mach/irqs-7x30.h +++ b/arch/arm/mach-msm/include/mach/irqs-7x30.h @@ -1,30 +1,13 @@ /* Copyright (c) 2009, Code Aurora Forum. All rights reserved. * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above - * copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided - * with the distribution. - * * Neither the name of Code Aurora Forum, Inc. nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS - * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR - * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE - * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN - * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. */ #ifndef __ASM_ARCH_MSM_IRQS_7X30_H diff --git a/arch/arm/mach-msm/include/mach/irqs-8960.h b/arch/arm/mach-msm/include/mach/irqs-8960.h index c7f083c..81ab2a6 100644 --- a/arch/arm/mach-msm/include/mach/irqs-8960.h +++ b/arch/arm/mach-msm/include/mach/irqs-8960.h @@ -1,29 +1,13 @@ /* Copyright (c) 2011 Code Aurora Forum. All rights reserved. * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Code Aurora nor - * the names of its contributors may be used to endorse or promote - * products derived from this software without specific prior written - * permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF - * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. */ #ifndef __ASM_ARCH_MSM_IRQS_8960_H diff --git a/arch/arm/mach-msm/include/mach/irqs-8x50.h b/arch/arm/mach-msm/include/mach/irqs-8x50.h index de3d8fe..26adbe0 100644 --- a/arch/arm/mach-msm/include/mach/irqs-8x50.h +++ b/arch/arm/mach-msm/include/mach/irqs-8x50.h @@ -1,30 +1,13 @@ /* Copyright (c) 2008-2009, Code Aurora Forum. All rights reserved. * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above - * copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided - * with the distribution. - * * Neither the name of Code Aurora Forum, Inc. nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS - * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR - * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE - * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN - * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. */ #ifndef __ASM_ARCH_MSM_IRQS_8XXX_H diff --git a/arch/arm/mach-msm/include/mach/sirc.h b/arch/arm/mach-msm/include/mach/sirc.h index 7281337..ef55868 100644 --- a/arch/arm/mach-msm/include/mach/sirc.h +++ b/arch/arm/mach-msm/include/mach/sirc.h @@ -1,30 +1,13 @@ /* Copyright (c) 2008-2009, Code Aurora Forum. All rights reserved. * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above - * copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided - * with the distribution. - * * Neither the name of Code Aurora Forum, Inc. nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS - * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR - * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE - * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN - * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. */ #ifndef __ASM_ARCH_MSM_SIRC_H diff --git a/arch/arm/mach-msm/include/mach/smp.h b/arch/arm/mach-msm/include/mach/smp.h index a95f7b9..3c01000e 100644 --- a/arch/arm/mach-msm/include/mach/smp.h +++ b/arch/arm/mach-msm/include/mach/smp.h @@ -1,29 +1,13 @@ /* Copyright (c) 2010, Code Aurora Forum. All rights reserved. * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Code Aurora nor - * the names of its contributors may be used to endorse or promote - * products derived from this software without specific prior written - * permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF - * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. */ #ifndef __ASM_ARCH_MSM_SMP_H diff --git a/arch/arm/mach-msm/scm-boot.h b/arch/arm/mach-msm/scm-boot.h index 68f9b61..7be32ff 100644 --- a/arch/arm/mach-msm/scm-boot.h +++ b/arch/arm/mach-msm/scm-boot.h @@ -1,29 +1,13 @@ /* Copyright (c) 2010, Code Aurora Forum. All rights reserved. * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above - * copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided - * with the distribution. - * * Neither the name of Code Aurora Forum, Inc. nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. * - * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS - * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR - * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE - * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN - * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. */ #ifndef __MACH_SCM_BOOT_H #define __MACH_SCM_BOOT_H diff --git a/arch/arm/mach-msm/scm.h b/arch/arm/mach-msm/scm.h index 261786b..00b31ea 100644 --- a/arch/arm/mach-msm/scm.h +++ b/arch/arm/mach-msm/scm.h @@ -1,29 +1,13 @@ /* Copyright (c) 2010, Code Aurora Forum. All rights reserved. * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above - * copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided - * with the distribution. - * * Neither the name of Code Aurora Forum, Inc. nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. * - * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS - * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR - * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE - * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN - * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. */ #ifndef __MACH_SCM_H #define __MACH_SCM_H -- cgit v0.10.2 From 0693a317b609a5d31d29e26c4f28ea079d5477f4 Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Fri, 18 Feb 2011 19:14:09 -0800 Subject: msm: headsmp.S: Fix section mismatch WARNING: vmlinux.o(.cpuinit.text+0xc80): Section mismatch in reference from the function boot_secondary() to the variable .init.text:msm_secondary_startup The function __cpuinit boot_secondary() references a variable __init msm_secondary_startup. If msm_secondary_startup is only used by boot_secondary then annotate msm_secondary_startup with a matching annotation. Signed-off-by: Stephen Boyd Signed-off-by: David Brown diff --git a/arch/arm/mach-msm/headsmp.S b/arch/arm/mach-msm/headsmp.S index d0c2143..0c631a9 100644 --- a/arch/arm/mach-msm/headsmp.S +++ b/arch/arm/mach-msm/headsmp.S @@ -11,7 +11,7 @@ #include #include - __INIT + __CPUINIT /* * MSM specific entry point for secondary CPUs. This provides -- cgit v0.10.2 From 2a52220c89e02423aa23e6b9fb6dc0c706465a82 Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Wed, 23 Feb 2011 09:37:41 -0800 Subject: msm: clock: Remove references to clk_ops_pcom Not all devices use proc_comm and determining if a clock is local vs. remote is fragile when done by comparing clk_ops pointers. Instead, implement an is_local() function for all clk_ops to determine if the clock is local. Doing this allows us to remove the last references to clk_ops_pcom from clock.c and compile it for targets with CONFIG_MSM_PROC_COMM=n. We don't need to set the clk_ops at runtime until 7x30 local clock detection comes in. Right now it's just complicating things so just set the ops pointer statically. Signed-off-by: Stephen Boyd Signed-off-by: David Brown diff --git a/arch/arm/mach-msm/Makefile b/arch/arm/mach-msm/Makefile index 2099c97..9519fd2 100644 --- a/arch/arm/mach-msm/Makefile +++ b/arch/arm/mach-msm/Makefile @@ -1,7 +1,6 @@ obj-y += io.o idle.o timer.o -ifdef CONFIG_MSM_PROC_COMM +obj-y += clock.o obj-$(CONFIG_DEBUG_FS) += clock-debug.o -endif obj-$(CONFIG_MSM_VIC) += irq-vic.o obj-$(CONFIG_MSM_IOMMU) += iommu.o iommu_dev.o devices-iommu.o @@ -9,11 +8,8 @@ obj-$(CONFIG_MSM_IOMMU) += iommu.o iommu_dev.o devices-iommu.o obj-$(CONFIG_ARCH_MSM7X00A) += dma.o irq.o acpuclock-arm11.o obj-$(CONFIG_ARCH_MSM7X30) += dma.o obj-$(CONFIG_ARCH_QSD8X50) += dma.o sirc.o -obj-$(CONFIG_ARCH_MSM8X60) += clock-dummy.o -obj-$(CONFIG_ARCH_MSM8960) += clock-dummy.o obj-$(CONFIG_MSM_PROC_COMM) += proc_comm.o clock-pcom.o vreg.o -obj-$(CONFIG_MSM_PROC_COMM) += clock.o obj-$(CONFIG_MSM_SMD) += smd.o smd_debug.o obj-$(CONFIG_MSM_SMD) += last_radio_log.o diff --git a/arch/arm/mach-msm/clock-7x30.h b/arch/arm/mach-msm/clock-7x30.h index da8e1c6..53622b3 100644 --- a/arch/arm/mach-msm/clock-7x30.h +++ b/arch/arm/mach-msm/clock-7x30.h @@ -145,6 +145,7 @@ extern int internal_pwr_rail_ctl_auto(unsigned rail_id, bool enable); .flags = clk_flags, \ .dev = clk_dev, \ .dbg_name = #l_id, \ + .ops = &clk_ops_pcom, \ } #endif diff --git a/arch/arm/mach-msm/clock-debug.c b/arch/arm/mach-msm/clock-debug.c index b67b9e82..4886404 100644 --- a/arch/arm/mach-msm/clock-debug.c +++ b/arch/arm/mach-msm/clock-debug.c @@ -19,7 +19,6 @@ #include #include #include "clock.h" -#include "clock-pcom.h" static int clock_debug_rate_set(void *data, u64 val) { @@ -79,7 +78,7 @@ static int clock_debug_local_get(void *data, u64 *val) { struct clk *clock = data; - *val = clock->ops != &clk_ops_pcom; + *val = clock->ops->is_local(clock->id); return 0; } diff --git a/arch/arm/mach-msm/clock-dummy.c b/arch/arm/mach-msm/clock-dummy.c deleted file mode 100644 index 1250d22..0000000 --- a/arch/arm/mach-msm/clock-dummy.c +++ /dev/null @@ -1,54 +0,0 @@ -/* Copyright (c) 2010, Code Aurora Forum. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA - * 02110-1301, USA. - * - */ -#include -#include -#include - -struct clk *clk_get(struct device *dev, const char *id) -{ - return ERR_PTR(-ENOENT); -} -EXPORT_SYMBOL(clk_get); - -int clk_enable(struct clk *clk) -{ - return -ENOENT; -} -EXPORT_SYMBOL(clk_enable); - -void clk_disable(struct clk *clk) -{ -} -EXPORT_SYMBOL(clk_disable); - -unsigned long clk_get_rate(struct clk *clk) -{ - return 0; -} -EXPORT_SYMBOL(clk_get_rate); - -int clk_set_rate(struct clk *clk, unsigned long rate) -{ - return -ENOENT; -} -EXPORT_SYMBOL(clk_set_rate); - -void clk_put(struct clk *clk) -{ -} -EXPORT_SYMBOL(clk_put); diff --git a/arch/arm/mach-msm/clock-pcom.c b/arch/arm/mach-msm/clock-pcom.c index 8c4e867..63b7113 100644 --- a/arch/arm/mach-msm/clock-pcom.c +++ b/arch/arm/mach-msm/clock-pcom.c @@ -117,6 +117,11 @@ long pc_clk_round_rate(unsigned id, unsigned rate) return rate; } +static bool pc_clk_is_local(unsigned id) +{ + return false; +} + struct clk_ops clk_ops_pcom = { .enable = pc_clk_enable, .disable = pc_clk_disable, @@ -129,4 +134,5 @@ struct clk_ops clk_ops_pcom = { .get_rate = pc_clk_get_rate, .is_enabled = pc_clk_is_enabled, .round_rate = pc_clk_round_rate, + .is_local = pc_clk_is_local, }; diff --git a/arch/arm/mach-msm/clock.c b/arch/arm/mach-msm/clock.c index 8c2b4dd..e00f6a0 100644 --- a/arch/arm/mach-msm/clock.c +++ b/arch/arm/mach-msm/clock.c @@ -21,9 +21,6 @@ #include #include "clock.h" -#include "proc_comm.h" -#include "clock-7x30.h" -#include "clock-pcom.h" static DEFINE_MUTEX(clocks_mutex); static DEFINE_SPINLOCK(clocks_lock); @@ -84,8 +81,6 @@ EXPORT_SYMBOL(clk_disable); int clk_reset(struct clk *clk, enum clk_reset_action action) { - if (!clk->ops->reset) - clk->ops->reset = &pc_clk_reset; return clk->ops->reset(clk->remote_id, action); } EXPORT_SYMBOL(clk_reset); @@ -162,23 +157,13 @@ EXPORT_SYMBOL(clk_set_flags); */ static struct clk *ebi1_clk; -static void __init set_clock_ops(struct clk *clk) -{ - if (!clk->ops) { - clk->ops = &clk_ops_pcom; - clk->id = clk->remote_id; - } -} - void __init msm_clock_init(struct clk *clock_tbl, unsigned num_clocks) { unsigned n; mutex_lock(&clocks_mutex); - for (n = 0; n < num_clocks; n++) { - set_clock_ops(&clock_tbl[n]); + for (n = 0; n < num_clocks; n++) list_add_tail(&clock_tbl[n].list, &clocks); - } mutex_unlock(&clocks_mutex); ebi1_clk = clk_get(NULL, "ebi1_clk"); diff --git a/arch/arm/mach-msm/clock.h b/arch/arm/mach-msm/clock.h index 70216b0..8d302c7 100644 --- a/arch/arm/mach-msm/clock.h +++ b/arch/arm/mach-msm/clock.h @@ -43,6 +43,7 @@ struct clk_ops { unsigned (*get_rate)(unsigned id); unsigned (*is_enabled)(unsigned id); long (*round_rate)(unsigned id, unsigned rate); + bool (*is_local)(unsigned id); }; struct clk { -- cgit v0.10.2 From bd32344a6baa8baac9c2b3e9c6c649cc4ed53920 Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Wed, 23 Feb 2011 09:37:42 -0800 Subject: msm: clock: Migrate to clkdev Migrating to clkdev has several advantages: * Less code in mach-msm/clock.c * A more robust clk_get() implementation * clk_add_alias() support * clk_get_sys() support In general, this will help board authors setup clock aliases and break the dependency on device pointers in the clock tables. Signed-off-by: Stephen Boyd Signed-off-by: David Brown diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 5cff165..4d26650 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -619,6 +619,7 @@ config ARCH_MSM select HAVE_CLK select GENERIC_CLOCKEVENTS select ARCH_REQUIRE_GPIOLIB + select CLKDEV_LOOKUP help Support for Qualcomm MSM/QSD based systems. This runs on the apps processor of the MSM/QSD and depends on a shared memory diff --git a/arch/arm/mach-msm/board-msm7x30.c b/arch/arm/mach-msm/board-msm7x30.c index dc9fac1..cf15889 100644 --- a/arch/arm/mach-msm/board-msm7x30.c +++ b/arch/arm/mach-msm/board-msm7x30.c @@ -23,6 +23,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/mach-msm/board-msm8960.c b/arch/arm/mach-msm/board-msm8960.c index ef80f46..1993721 100644 --- a/arch/arm/mach-msm/board-msm8960.c +++ b/arch/arm/mach-msm/board-msm8960.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/mach-msm/board-qsd8x50.c b/arch/arm/mach-msm/board-qsd8x50.c index b464d48..127ee6d 100644 --- a/arch/arm/mach-msm/board-qsd8x50.c +++ b/arch/arm/mach-msm/board-qsd8x50.c @@ -22,6 +22,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/mach-msm/board-trout.c b/arch/arm/mach-msm/board-trout.c index 8448687..8143867 100644 --- a/arch/arm/mach-msm/board-trout.c +++ b/arch/arm/mach-msm/board-trout.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/mach-msm/clock-7x30.h b/arch/arm/mach-msm/clock-7x30.h index 53622b3..1410445 100644 --- a/arch/arm/mach-msm/clock-7x30.h +++ b/arch/arm/mach-msm/clock-7x30.h @@ -130,23 +130,26 @@ void pll_disable(uint32_t pll); extern int internal_pwr_rail_ctl_auto(unsigned rail_id, bool enable); #define CLK_7X30(clk_name, clk_id, clk_dev, clk_flags) { \ - .name = clk_name, \ - .id = L_7X30_##clk_id, \ - .remote_id = P_##clk_id, \ - .flags = clk_flags, \ - .dev = clk_dev, \ - .dbg_name = #clk_id, \ + .con_id = clk_name, \ + .dev_id = clk_dev, \ + .clk = &(struct clk){ \ + .id = L_7X30_##clk_id, \ + .remote_id = P_##clk_id, \ + .flags = clk_flags, \ + .dbg_name = #clk_id, \ + }, \ } #define CLK_7X30S(clk_name, l_id, r_id, clk_dev, clk_flags) { \ - .name = clk_name, \ - .id = L_7X30_##l_id, \ - .remote_id = P_##r_id, \ - .flags = clk_flags, \ - .dev = clk_dev, \ - .dbg_name = #l_id, \ - .ops = &clk_ops_pcom, \ + .con_id = clk_name, \ + .dev_id = clk_dev, \ + .clk = &(struct clk){ \ + .id = L_7X30_##l_id, \ + .remote_id = P_##r_id, \ + .flags = clk_flags, \ + .dbg_name = #l_id, \ + .ops = &clk_ops_pcom, \ + }, \ } #endif - diff --git a/arch/arm/mach-msm/clock-pcom.h b/arch/arm/mach-msm/clock-pcom.h index 53dea61..974d003 100644 --- a/arch/arm/mach-msm/clock-pcom.h +++ b/arch/arm/mach-msm/clock-pcom.h @@ -126,13 +126,15 @@ extern struct clk_ops clk_ops_pcom; int pc_clk_reset(unsigned id, enum clk_reset_action action); #define CLK_PCOM(clk_name, clk_id, clk_dev, clk_flags) { \ - .name = clk_name, \ - .id = P_##clk_id, \ - .remote_id = P_##clk_id, \ - .ops = &clk_ops_pcom, \ - .flags = clk_flags, \ - .dev = clk_dev, \ - .dbg_name = #clk_id, \ + .con_id = clk_name, \ + .dev_id = clk_dev, \ + .clk = &(struct clk){ \ + .id = P_##clk_id, \ + .remote_id = P_##clk_id, \ + .ops = &clk_ops_pcom, \ + .flags = clk_flags, \ + .dbg_name = #clk_id, \ + }, \ } #endif diff --git a/arch/arm/mach-msm/clock.c b/arch/arm/mach-msm/clock.c index e00f6a0..22a5376 100644 --- a/arch/arm/mach-msm/clock.c +++ b/arch/arm/mach-msm/clock.c @@ -19,6 +19,11 @@ #include #include #include +#include +#include +#include +#include +#include #include "clock.h" @@ -29,32 +34,6 @@ static LIST_HEAD(clocks); /* * Standard clock functions defined in include/linux/clk.h */ -struct clk *clk_get(struct device *dev, const char *id) -{ - struct clk *clk; - - mutex_lock(&clocks_mutex); - - list_for_each_entry(clk, &clocks, list) - if (!strcmp(id, clk->name) && clk->dev == dev) - goto found_it; - - list_for_each_entry(clk, &clocks, list) - if (!strcmp(id, clk->name) && clk->dev == NULL) - goto found_it; - - clk = ERR_PTR(-ENOENT); -found_it: - mutex_unlock(&clocks_mutex); - return clk; -} -EXPORT_SYMBOL(clk_get); - -void clk_put(struct clk *clk) -{ -} -EXPORT_SYMBOL(clk_put); - int clk_enable(struct clk *clk) { unsigned long flags; @@ -157,13 +136,15 @@ EXPORT_SYMBOL(clk_set_flags); */ static struct clk *ebi1_clk; -void __init msm_clock_init(struct clk *clock_tbl, unsigned num_clocks) +void __init msm_clock_init(struct clk_lookup *clock_tbl, unsigned num_clocks) { unsigned n; mutex_lock(&clocks_mutex); - for (n = 0; n < num_clocks; n++) - list_add_tail(&clock_tbl[n].list, &clocks); + for (n = 0; n < num_clocks; n++) { + clkdev_add(&clock_tbl[n]); + list_add_tail(&clock_tbl[n].clk->list, &clocks); + } mutex_unlock(&clocks_mutex); ebi1_clk = clk_get(NULL, "ebi1_clk"); diff --git a/arch/arm/mach-msm/clock.h b/arch/arm/mach-msm/clock.h index 8d302c7..2c007f6 100644 --- a/arch/arm/mach-msm/clock.h +++ b/arch/arm/mach-msm/clock.h @@ -51,11 +51,9 @@ struct clk { uint32_t remote_id; uint32_t count; uint32_t flags; - const char *name; struct clk_ops *ops; const char *dbg_name; struct list_head list; - struct device *dev; }; #define OFF CLKFLAG_AUTO_OFF diff --git a/arch/arm/mach-msm/devices-msm7x00.c b/arch/arm/mach-msm/devices-msm7x00.c index ed62806..c4f5e26 100644 --- a/arch/arm/mach-msm/devices-msm7x00.c +++ b/arch/arm/mach-msm/devices-msm7x00.c @@ -15,6 +15,7 @@ #include #include +#include #include #include @@ -24,7 +25,6 @@ #include #include - #include "clock.h" #include "clock-pcom.h" #include @@ -418,7 +418,7 @@ struct platform_device msm_device_mdp = { .resource = resources_mdp, }; -struct clk msm_clocks_7x01a[] = { +struct clk_lookup msm_clocks_7x01a[] = { CLK_PCOM("adm_clk", ADM_CLK, NULL, 0), CLK_PCOM("adsp_clk", ADSP_CLK, NULL, 0), CLK_PCOM("ebi1_clk", EBI1_CLK, NULL, 0), @@ -427,7 +427,7 @@ struct clk msm_clocks_7x01a[] = { CLK_PCOM("emdh_clk", EMDH_CLK, NULL, OFF), CLK_PCOM("gp_clk", GP_CLK, NULL, 0), CLK_PCOM("grp_clk", GRP_3D_CLK, NULL, OFF), - CLK_PCOM("i2c_clk", I2C_CLK, &msm_device_i2c.dev, 0), + CLK_PCOM("i2c_clk", I2C_CLK, "msm_i2c.0", 0), CLK_PCOM("icodec_rx_clk", ICODEC_RX_CLK, NULL, 0), CLK_PCOM("icodec_tx_clk", ICODEC_TX_CLK, NULL, 0), CLK_PCOM("imem_clk", IMEM_CLK, NULL, OFF), @@ -437,25 +437,25 @@ struct clk msm_clocks_7x01a[] = { CLK_PCOM("pcm_clk", PCM_CLK, NULL, 0), CLK_PCOM("mddi_clk", PMDH_CLK, NULL, OFF | CLK_MINMAX), CLK_PCOM("sdac_clk", SDAC_CLK, NULL, OFF), - CLK_PCOM("sdc_clk", SDC1_CLK, &msm_device_sdc1.dev, OFF), - CLK_PCOM("sdc_pclk", SDC1_P_CLK, &msm_device_sdc1.dev, OFF), - CLK_PCOM("sdc_clk", SDC2_CLK, &msm_device_sdc2.dev, OFF), - CLK_PCOM("sdc_pclk", SDC2_P_CLK, &msm_device_sdc2.dev, OFF), - CLK_PCOM("sdc_clk", SDC3_CLK, &msm_device_sdc3.dev, OFF), - CLK_PCOM("sdc_pclk", SDC3_P_CLK, &msm_device_sdc3.dev, OFF), - CLK_PCOM("sdc_clk", SDC4_CLK, &msm_device_sdc4.dev, OFF), - CLK_PCOM("sdc_pclk", SDC4_P_CLK, &msm_device_sdc4.dev, OFF), + CLK_PCOM("sdc_clk", SDC1_CLK, "msm_sdcc.1", OFF), + CLK_PCOM("sdc_pclk", SDC1_P_CLK, "msm_sdcc.1", OFF), + CLK_PCOM("sdc_clk", SDC2_CLK, "msm_sdcc.2", OFF), + CLK_PCOM("sdc_pclk", SDC2_P_CLK, "msm_sdcc.2", OFF), + CLK_PCOM("sdc_clk", SDC3_CLK, "msm_sdcc.3", OFF), + CLK_PCOM("sdc_pclk", SDC3_P_CLK, "msm_sdcc.3", OFF), + CLK_PCOM("sdc_clk", SDC4_CLK, "msm_sdcc.4", OFF), + CLK_PCOM("sdc_pclk", SDC4_P_CLK, "msm_sdcc.4", OFF), CLK_PCOM("tsif_clk", TSIF_CLK, NULL, 0), CLK_PCOM("tsif_ref_clk", TSIF_REF_CLK, NULL, 0), CLK_PCOM("tv_dac_clk", TV_DAC_CLK, NULL, 0), CLK_PCOM("tv_enc_clk", TV_ENC_CLK, NULL, 0), - CLK_PCOM("uart_clk", UART1_CLK, &msm_device_uart1.dev, OFF), - CLK_PCOM("uart_clk", UART2_CLK, &msm_device_uart2.dev, 0), - CLK_PCOM("uart_clk", UART3_CLK, &msm_device_uart3.dev, OFF), + CLK_PCOM("uart_clk", UART1_CLK, "msm_serial.0", OFF), + CLK_PCOM("uart_clk", UART2_CLK, "msm_serial.1", 0), + CLK_PCOM("uart_clk", UART3_CLK, "msm_serial.2", OFF), CLK_PCOM("uart1dm_clk", UART1DM_CLK, NULL, OFF), CLK_PCOM("uart2dm_clk", UART2DM_CLK, NULL, 0), - CLK_PCOM("usb_hs_clk", USB_HS_CLK, &msm_device_hsusb.dev, OFF), - CLK_PCOM("usb_hs_pclk", USB_HS_P_CLK, &msm_device_hsusb.dev, OFF), + CLK_PCOM("usb_hs_clk", USB_HS_CLK, "msm_hsusb", OFF), + CLK_PCOM("usb_hs_pclk", USB_HS_P_CLK, "msm_hsusb", OFF), CLK_PCOM("usb_otg_clk", USB_OTG_CLK, NULL, 0), CLK_PCOM("vdc_clk", VDC_CLK, NULL, OFF ), CLK_PCOM("vfe_clk", VFE_CLK, NULL, OFF), diff --git a/arch/arm/mach-msm/devices-msm7x30.c b/arch/arm/mach-msm/devices-msm7x30.c index cd4343b..09b4f14 100644 --- a/arch/arm/mach-msm/devices-msm7x30.c +++ b/arch/arm/mach-msm/devices-msm7x30.c @@ -17,6 +17,7 @@ #include #include +#include #include #include #include @@ -129,7 +130,7 @@ struct platform_device msm_device_hsusb_host = { }, }; -struct clk msm_clocks_7x30[] = { +struct clk_lookup msm_clocks_7x30[] = { CLK_PCOM("adm_clk", ADM_CLK, NULL, 0), CLK_PCOM("adsp_clk", ADSP_CLK, NULL, 0), CLK_PCOM("cam_m_clk", CAM_M_CLK, NULL, 0), @@ -181,7 +182,7 @@ struct clk msm_clocks_7x30[] = { CLK_7X30S("tv_src_clk", TV_CLK, TV_ENC_CLK, NULL, 0), CLK_PCOM("tv_dac_clk", TV_DAC_CLK, NULL, 0), CLK_PCOM("tv_enc_clk", TV_ENC_CLK, NULL, 0), - CLK_PCOM("uart_clk", UART2_CLK, &msm_device_uart2.dev, 0), + CLK_PCOM("uart_clk", UART2_CLK, "msm_serial.1", 0), CLK_PCOM("usb_phy_clk", USB_PHY_CLK, NULL, 0), CLK_PCOM("usb_hs_clk", USB_HS_CLK, NULL, OFF), CLK_PCOM("usb_hs_pclk", USB_HS_P_CLK, NULL, OFF), diff --git a/arch/arm/mach-msm/devices-qsd8x50.c b/arch/arm/mach-msm/devices-qsd8x50.c index bd545f9..12d8deb 100644 --- a/arch/arm/mach-msm/devices-qsd8x50.c +++ b/arch/arm/mach-msm/devices-qsd8x50.c @@ -15,8 +15,9 @@ #include #include - +#include #include + #include #include #include @@ -314,7 +315,7 @@ int __init msm_add_sdcc(unsigned int controller, return platform_device_register(pdev); } -struct clk msm_clocks_8x50[] = { +struct clk_lookup msm_clocks_8x50[] = { CLK_PCOM("adm_clk", ADM_CLK, NULL, 0), CLK_PCOM("ce_clk", CE_CLK, NULL, 0), CLK_PCOM("ebi1_clk", EBI1_CLK, NULL, CLK_MIN), @@ -336,14 +337,14 @@ struct clk msm_clocks_8x50[] = { CLK_PCOM("pbus_clk", PBUS_CLK, NULL, CLK_MIN), CLK_PCOM("pcm_clk", PCM_CLK, NULL, 0), CLK_PCOM("sdac_clk", SDAC_CLK, NULL, OFF), - CLK_PCOM("sdc_clk", SDC1_CLK, &msm_device_sdc1.dev, OFF), - CLK_PCOM("sdc_pclk", SDC1_P_CLK, &msm_device_sdc1.dev, OFF), - CLK_PCOM("sdc_clk", SDC2_CLK, &msm_device_sdc2.dev, OFF), - CLK_PCOM("sdc_pclk", SDC2_P_CLK, &msm_device_sdc2.dev, OFF), - CLK_PCOM("sdc_clk", SDC3_CLK, &msm_device_sdc3.dev, OFF), - CLK_PCOM("sdc_pclk", SDC3_P_CLK, &msm_device_sdc3.dev, OFF), - CLK_PCOM("sdc_clk", SDC4_CLK, &msm_device_sdc4.dev, OFF), - CLK_PCOM("sdc_pclk", SDC4_P_CLK, &msm_device_sdc4.dev, OFF), + CLK_PCOM("sdc_clk", SDC1_CLK, "msm_sdcc.1", OFF), + CLK_PCOM("sdc_pclk", SDC1_P_CLK, "msm_sdcc.1", OFF), + CLK_PCOM("sdc_clk", SDC2_CLK, "msm_sdcc.2", OFF), + CLK_PCOM("sdc_pclk", SDC2_P_CLK, "msm_sdcc.2", OFF), + CLK_PCOM("sdc_clk", SDC3_CLK, "msm_sdcc.3", OFF), + CLK_PCOM("sdc_pclk", SDC3_P_CLK, "msm_sdcc.3", OFF), + CLK_PCOM("sdc_clk", SDC4_CLK, "msm_sdcc.4", OFF), + CLK_PCOM("sdc_pclk", SDC4_P_CLK, "msm_sdcc.4", OFF), CLK_PCOM("spi_clk", SPI_CLK, NULL, 0), CLK_PCOM("tsif_clk", TSIF_CLK, NULL, 0), CLK_PCOM("tsif_ref_clk", TSIF_REF_CLK, NULL, 0), @@ -351,7 +352,7 @@ struct clk msm_clocks_8x50[] = { CLK_PCOM("tv_enc_clk", TV_ENC_CLK, NULL, 0), CLK_PCOM("uart_clk", UART1_CLK, NULL, OFF), CLK_PCOM("uart_clk", UART2_CLK, NULL, 0), - CLK_PCOM("uart_clk", UART3_CLK, &msm_device_uart3.dev, OFF), + CLK_PCOM("uart_clk", UART3_CLK, "msm_serial.2", OFF), CLK_PCOM("uartdm_clk", UART1DM_CLK, NULL, OFF), CLK_PCOM("uartdm_clk", UART2DM_CLK, NULL, 0), CLK_PCOM("usb_hs_clk", USB_HS_CLK, NULL, OFF), diff --git a/arch/arm/mach-msm/devices.h b/arch/arm/mach-msm/devices.h index e2643b3..9545c19 100644 --- a/arch/arm/mach-msm/devices.h +++ b/arch/arm/mach-msm/devices.h @@ -16,6 +16,8 @@ #ifndef __ARCH_ARM_MACH_MSM_DEVICES_H #define __ARCH_ARM_MACH_MSM_DEVICES_H +#include + #include "clock.h" extern struct platform_device msm_device_uart1; @@ -44,13 +46,13 @@ extern struct platform_device msm_device_mddi0; extern struct platform_device msm_device_mddi1; extern struct platform_device msm_device_mdp; -extern struct clk msm_clocks_7x01a[]; +extern struct clk_lookup msm_clocks_7x01a[]; extern unsigned msm_num_clocks_7x01a; -extern struct clk msm_clocks_7x30[]; +extern struct clk_lookup msm_clocks_7x30[]; extern unsigned msm_num_clocks_7x30; -extern struct clk msm_clocks_8x50[]; +extern struct clk_lookup msm_clocks_8x50[]; extern unsigned msm_num_clocks_8x50; #endif diff --git a/arch/arm/mach-msm/include/mach/board.h b/arch/arm/mach-msm/include/mach/board.h index 6abf4a6..2ce8f1f 100644 --- a/arch/arm/mach-msm/include/mach/board.h +++ b/arch/arm/mach-msm/include/mach/board.h @@ -31,7 +31,7 @@ struct msm_acpu_clock_platform_data unsigned long wait_for_irq_khz; }; -struct clk; +struct clk_lookup; extern struct sys_timer msm_timer; @@ -41,7 +41,7 @@ void __init msm_add_devices(void); void __init msm_map_common_io(void); void __init msm_init_irq(void); void __init msm_init_gpio(void); -void __init msm_clock_init(struct clk *clock_tbl, unsigned num_clocks); +void __init msm_clock_init(struct clk_lookup *clock_tbl, unsigned num_clocks); void __init msm_acpu_clock_init(struct msm_acpu_clock_platform_data *); int __init msm_add_sdcc(unsigned int controller, struct msm_mmc_platform_data *plat, diff --git a/arch/arm/mach-msm/include/mach/clkdev.h b/arch/arm/mach-msm/include/mach/clkdev.h new file mode 100644 index 0000000..f87a57b --- /dev/null +++ b/arch/arm/mach-msm/include/mach/clkdev.h @@ -0,0 +1,19 @@ +/* Copyright (c) 2011, Code Aurora Forum. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#ifndef __ASM_ARCH_MSM_CLKDEV_H +#define __ASM_ARCH_MSM_CLKDEV_H + +struct clk; + +static inline int __clk_get(struct clk *clk) { return 1; } +static inline void __clk_put(struct clk *clk) { } +#endif -- cgit v0.10.2 From b0a679326ce90e65779178906df5b8b6180163d6 Mon Sep 17 00:00:00 2001 From: Dima Zavin Date: Wed, 2 Mar 2011 13:16:36 -0800 Subject: video: msmfb: Put the partial update magic value into the fix_screen struct. This can then be tested by userspace to see if the capability is supported. Userspace cannot rely on that value being left in var_screen, since userspace itself can change it. Signed-off-by: Dima Zavin Signed-off-by: Carl Vanderlip Signed-off-by: David Brown diff --git a/drivers/video/msm/msm_fb.c b/drivers/video/msm/msm_fb.c index 5436aeb..fe5efe5 100644 --- a/drivers/video/msm/msm_fb.c +++ b/drivers/video/msm/msm_fb.c @@ -469,6 +469,18 @@ static void setup_fb_info(struct msmfb_info *msmfb) fb_info->var.yoffset = 0; if (msmfb->panel->caps & MSMFB_CAP_PARTIAL_UPDATES) { + /* + * Set the param in the fixed screen, so userspace can't + * change it. This will be used to check for the + * capability. + */ + fb_info->fix.reserved[0] = 0x5444; + fb_info->fix.reserved[1] = 0x5055; + + /* + * This preloads the value so that if userspace doesn't + * change it, it will be a full update + */ fb_info->var.reserved[0] = 0x54445055; fb_info->var.reserved[1] = 0; fb_info->var.reserved[2] = (uint16_t)msmfb->xres | -- cgit v0.10.2 From a8d380f30a7d8cc507fd5cc84b2dc5ee2b2144d7 Mon Sep 17 00:00:00 2001 From: Dima Zavin Date: Wed, 2 Mar 2011 13:17:08 -0800 Subject: msm: mdp: Add support for RGBX 8888 image format. Signed-off-by: Dima Zavin Signed-off-by: Carl Vanderlip Signed-off-by: David Brown diff --git a/drivers/video/msm/mdp_hw.h b/drivers/video/msm/mdp_hw.h index 4e3deb4..9e1e92e 100644 --- a/drivers/video/msm/mdp_hw.h +++ b/drivers/video/msm/mdp_hw.h @@ -449,6 +449,7 @@ int mdp_ppp_blit(const struct mdp_info *mdp, struct mdp_blit_req *req, #define PPP_CFG_MDP_XRGB_8888(dir) PPP_CFG_MDP_ARGB_8888(dir) #define PPP_CFG_MDP_RGBA_8888(dir) PPP_CFG_MDP_ARGB_8888(dir) #define PPP_CFG_MDP_BGRA_8888(dir) PPP_CFG_MDP_ARGB_8888(dir) +#define PPP_CFG_MDP_RGBX_8888(dir) PPP_CFG_MDP_ARGB_8888(dir) #define PPP_CFG_MDP_Y_CBCR_H2V2(dir) (PPP_##dir##_C2R_8BIT | \ PPP_##dir##_C0G_8BIT | \ @@ -494,6 +495,8 @@ int mdp_ppp_blit(const struct mdp_info *mdp, struct mdp_blit_req *req, MDP_GET_PACK_PATTERN(CLR_ALPHA, CLR_B, CLR_G, CLR_R, 8) #define PPP_PACK_PATTERN_MDP_BGRA_8888 \ MDP_GET_PACK_PATTERN(CLR_ALPHA, CLR_R, CLR_G, CLR_B, 8) +#define PPP_PACK_PATTERN_MDP_RGBX_8888 \ + MDP_GET_PACK_PATTERN(CLR_ALPHA, CLR_B, CLR_G, CLR_R, 8) #define PPP_PACK_PATTERN_MDP_Y_CBCR_H2V1 \ MDP_GET_PACK_PATTERN(0, 0, CLR_CB, CLR_CR, 8) #define PPP_PACK_PATTERN_MDP_Y_CBCR_H2V2 PPP_PACK_PATTERN_MDP_Y_CBCR_H2V1 @@ -509,6 +512,7 @@ int mdp_ppp_blit(const struct mdp_info *mdp, struct mdp_blit_req *req, #define PPP_CHROMA_SAMP_MDP_ARGB_8888(dir) PPP_OP_##dir##_CHROMA_RGB #define PPP_CHROMA_SAMP_MDP_RGBA_8888(dir) PPP_OP_##dir##_CHROMA_RGB #define PPP_CHROMA_SAMP_MDP_BGRA_8888(dir) PPP_OP_##dir##_CHROMA_RGB +#define PPP_CHROMA_SAMP_MDP_RGBX_8888(dir) PPP_OP_##dir##_CHROMA_RGB #define PPP_CHROMA_SAMP_MDP_Y_CBCR_H2V1(dir) PPP_OP_##dir##_CHROMA_H2V1 #define PPP_CHROMA_SAMP_MDP_Y_CBCR_H2V2(dir) PPP_OP_##dir##_CHROMA_420 #define PPP_CHROMA_SAMP_MDP_Y_CRCB_H2V1(dir) PPP_OP_##dir##_CHROMA_H2V1 @@ -523,6 +527,7 @@ int mdp_ppp_blit(const struct mdp_info *mdp, struct mdp_blit_req *req, [MDP_ARGB_8888] = PPP_##name##_MDP_ARGB_8888,\ [MDP_RGBA_8888] = PPP_##name##_MDP_RGBA_8888,\ [MDP_BGRA_8888] = PPP_##name##_MDP_BGRA_8888,\ + [MDP_RGBX_8888] = PPP_##name##_MDP_RGBX_8888,\ [MDP_Y_CBCR_H2V1] = PPP_##name##_MDP_Y_CBCR_H2V1,\ [MDP_Y_CBCR_H2V2] = PPP_##name##_MDP_Y_CBCR_H2V2,\ [MDP_Y_CRCB_H2V1] = PPP_##name##_MDP_Y_CRCB_H2V1,\ @@ -536,6 +541,7 @@ int mdp_ppp_blit(const struct mdp_info *mdp, struct mdp_blit_req *req, [MDP_ARGB_8888] = PPP_##name##_MDP_ARGB_8888(dir),\ [MDP_RGBA_8888] = PPP_##name##_MDP_RGBA_8888(dir),\ [MDP_BGRA_8888] = PPP_##name##_MDP_BGRA_8888(dir),\ + [MDP_RGBX_8888] = PPP_##name##_MDP_RGBX_8888(dir),\ [MDP_Y_CBCR_H2V1] = PPP_##name##_MDP_Y_CBCR_H2V1(dir),\ [MDP_Y_CBCR_H2V2] = PPP_##name##_MDP_Y_CBCR_H2V2(dir),\ [MDP_Y_CRCB_H2V1] = PPP_##name##_MDP_Y_CRCB_H2V1(dir),\ @@ -547,7 +553,8 @@ int mdp_ppp_blit(const struct mdp_info *mdp, struct mdp_blit_req *req, (img == MDP_YCRYCB_H2V1)) #define IS_RGB(img) ((img == MDP_RGB_565) | (img == MDP_RGB_888) | \ (img == MDP_ARGB_8888) | (img == MDP_RGBA_8888) | \ - (img == MDP_XRGB_8888) | (img == MDP_BGRA_8888)) + (img == MDP_XRGB_8888) | (img == MDP_BGRA_8888) | \ + (img == MDP_RGBX_8888)) #define HAS_ALPHA(img) ((img == MDP_ARGB_8888) | (img == MDP_RGBA_8888) | \ (img == MDP_BGRA_8888)) diff --git a/drivers/video/msm/mdp_ppp.c b/drivers/video/msm/mdp_ppp.c index 4ff001f..2b6564e 100644 --- a/drivers/video/msm/mdp_ppp.c +++ b/drivers/video/msm/mdp_ppp.c @@ -69,6 +69,7 @@ static uint32_t bytes_per_pixel[] = { [MDP_ARGB_8888] = 4, [MDP_RGBA_8888] = 4, [MDP_BGRA_8888] = 4, + [MDP_RGBX_8888] = 4, [MDP_Y_CBCR_H2V1] = 1, [MDP_Y_CBCR_H2V2] = 1, [MDP_Y_CRCB_H2V1] = 1, diff --git a/include/linux/msm_mdp.h b/include/linux/msm_mdp.h index d11fe0f..fe722c1 100644 --- a/include/linux/msm_mdp.h +++ b/include/linux/msm_mdp.h @@ -32,6 +32,7 @@ enum { MDP_Y_CBCR_H2V1, /* Y and CrCb, pseduo planar w/ Cr is in MSB */ MDP_RGBA_8888, /* ARGB 888 */ MDP_BGRA_8888, /* ABGR 888 */ + MDP_RGBX_8888, /* RGBX 888 */ MDP_IMGTYPE_LIMIT /* Non valid image type after this enum */ }; -- cgit v0.10.2 From 5d55779a5d95acdaa1080f1a4806fd6d4984d1e4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Arve=20Hj=C3=B8nnev=C3=A5g?= Date: Wed, 2 Mar 2011 13:17:51 -0800 Subject: msm_fb: Fix framebuffer console MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Don't allow non panning updates to bypass the wait for the panel to turn on. Signed-off-by: Carl Vanderlip Signed-off-by: Arve Hjønnevåg Signed-off-by: David Brown diff --git a/drivers/video/msm/msm_fb.c b/drivers/video/msm/msm_fb.c index fe5efe5..ec35130 100644 --- a/drivers/video/msm/msm_fb.c +++ b/drivers/video/msm/msm_fb.c @@ -219,8 +219,8 @@ restart: sleeping = msmfb->sleeping; /* on a full update, if the last frame has not completed, wait for it */ - if (pan_display && (msmfb->frame_requested != msmfb->frame_done || - sleeping == UPDATING)) { + if ((pan_display && msmfb->frame_requested != msmfb->frame_done) || + sleeping == UPDATING) { int ret; spin_unlock_irqrestore(&msmfb->update_lock, irq_flags); ret = wait_event_interruptible_timeout(msmfb->frame_wq, -- cgit v0.10.2 From 8bec99b586e2aa285076c2057e72b70ab5c43175 Mon Sep 17 00:00:00 2001 From: Dima Zavin Date: Wed, 2 Mar 2011 13:18:19 -0800 Subject: msm: mdp: Set the correct pack pattern for XRGB/ARGB Signed-off-by: Dima Zavin Signed-off-by: Carl Vanderlip Signed-off-by: David Brown diff --git a/drivers/video/msm/mdp_hw.h b/drivers/video/msm/mdp_hw.h index 9e1e92e..d804774 100644 --- a/drivers/video/msm/mdp_hw.h +++ b/drivers/video/msm/mdp_hw.h @@ -489,7 +489,7 @@ int mdp_ppp_blit(const struct mdp_info *mdp, struct mdp_blit_req *req, MDP_GET_PACK_PATTERN(0, CLR_R, CLR_G, CLR_B, 8) #define PPP_PACK_PATTERN_MDP_RGB_888 PPP_PACK_PATTERN_MDP_RGB_565 #define PPP_PACK_PATTERN_MDP_XRGB_8888 \ - MDP_GET_PACK_PATTERN(CLR_ALPHA, CLR_R, CLR_G, CLR_B, 8) + MDP_GET_PACK_PATTERN(CLR_B, CLR_G, CLR_R, CLR_ALPHA, 8) #define PPP_PACK_PATTERN_MDP_ARGB_8888 PPP_PACK_PATTERN_MDP_XRGB_8888 #define PPP_PACK_PATTERN_MDP_RGBA_8888 \ MDP_GET_PACK_PATTERN(CLR_ALPHA, CLR_B, CLR_G, CLR_R, 8) -- cgit v0.10.2 From 41f3f5138a5ea71ee603f3d556953fce9aba3074 Mon Sep 17 00:00:00 2001 From: Stepan Moskovchenko Date: Thu, 24 Feb 2011 18:00:39 -0800 Subject: msm: iommu: Clock control for the IOMMU driver Add clock control to the IOMMU driver. The IOMMU bus clock (and potentially an AXI clock) need to be on to gain access to IOMMU registers. Actively control these clocks when needed instead of leaving them on. Signed-off-by: Stepan Moskovchenko Signed-off-by: David Brown diff --git a/arch/arm/mach-msm/include/mach/iommu.h b/arch/arm/mach-msm/include/mach/iommu.h index 296c0f1..8738a44 100644 --- a/arch/arm/mach-msm/include/mach/iommu.h +++ b/arch/arm/mach-msm/include/mach/iommu.h @@ -1,4 +1,4 @@ -/* Copyright (c) 2010, Code Aurora Forum. All rights reserved. +/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -19,6 +19,7 @@ #define MSM_IOMMU_H #include +#include /* Sharability attributes of MSM IOMMU mappings */ #define MSM_IOMMU_ATTR_NON_SH 0x0 @@ -74,13 +75,17 @@ struct msm_iommu_ctx_dev { * struct msm_iommu_drvdata - A single IOMMU hardware instance * @base: IOMMU config port base address (VA) * @irq: Interrupt number - * + * @clk: The bus clock for this IOMMU hardware instance + * @pclk: The clock for the IOMMU bus interconnect + * * A msm_iommu_drvdata holds the global driver data about a single piece * of an IOMMU hardware instance. */ struct msm_iommu_drvdata { void __iomem *base; int irq; + struct clk *clk; + struct clk *pclk; }; /** diff --git a/arch/arm/mach-msm/iommu.c b/arch/arm/mach-msm/iommu.c index e2d58e4..cde3cd0 100644 --- a/arch/arm/mach-msm/iommu.c +++ b/arch/arm/mach-msm/iommu.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2010, Code Aurora Forum. All rights reserved. +/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -26,6 +26,7 @@ #include #include #include +#include #include #include @@ -50,6 +51,30 @@ struct msm_priv { struct list_head list_attached; }; +static int __enable_clocks(struct msm_iommu_drvdata *drvdata) +{ + int ret; + + ret = clk_enable(drvdata->pclk); + if (ret) + goto fail; + + if (drvdata->clk) { + ret = clk_enable(drvdata->clk); + if (ret) + clk_disable(drvdata->pclk); + } +fail: + return ret; +} + +static void __disable_clocks(struct msm_iommu_drvdata *drvdata) +{ + if (drvdata->clk) + clk_disable(drvdata->clk); + clk_disable(drvdata->pclk); +} + static int __flush_iotlb(struct iommu_domain *domain) { struct msm_priv *priv = domain->priv; @@ -77,9 +102,16 @@ static int __flush_iotlb(struct iommu_domain *domain) BUG(); iommu_drvdata = dev_get_drvdata(ctx_drvdata->pdev->dev.parent); + BUG_ON(!iommu_drvdata); + + ret = __enable_clocks(iommu_drvdata); + if (ret) + goto fail; + SET_CTX_TLBIALL(iommu_drvdata->base, ctx_drvdata->num, 0); + __disable_clocks(iommu_drvdata); } - +fail: return ret; } @@ -265,9 +297,14 @@ static int msm_iommu_attach_dev(struct iommu_domain *domain, struct device *dev) goto fail; } + ret = __enable_clocks(iommu_drvdata); + if (ret) + goto fail; + __program_context(iommu_drvdata->base, ctx_dev->num, __pa(priv->pgtable)); + __disable_clocks(iommu_drvdata); list_add(&(ctx_drvdata->attached_elm), &priv->list_attached); ret = __flush_iotlb(domain); @@ -303,7 +340,12 @@ static void msm_iommu_detach_dev(struct iommu_domain *domain, if (ret) goto fail; + ret = __enable_clocks(iommu_drvdata); + if (ret) + goto fail; + __reset_context(iommu_drvdata->base, ctx_dev->num); + __disable_clocks(iommu_drvdata); list_del_init(&ctx_drvdata->attached_elm); fail: @@ -532,6 +574,10 @@ static phys_addr_t msm_iommu_iova_to_phys(struct iommu_domain *domain, base = iommu_drvdata->base; ctx = ctx_drvdata->num; + ret = __enable_clocks(iommu_drvdata); + if (ret) + goto fail; + /* Invalidate context TLB */ SET_CTX_TLBIALL(base, ctx, 0); SET_V2PPR_VA(base, ctx, va >> V2Pxx_VA_SHIFT); @@ -547,6 +593,7 @@ static phys_addr_t msm_iommu_iova_to_phys(struct iommu_domain *domain, if (GET_FAULT(base, ctx)) ret = 0; + __disable_clocks(iommu_drvdata); fail: spin_unlock_irqrestore(&msm_iommu_lock, flags); return ret; @@ -590,7 +637,7 @@ irqreturn_t msm_iommu_fault_handler(int irq, void *dev_id) struct msm_iommu_drvdata *drvdata = dev_id; void __iomem *base; unsigned int fsr; - int ncb, i; + int ncb, i, ret; spin_lock(&msm_iommu_lock); @@ -604,6 +651,10 @@ irqreturn_t msm_iommu_fault_handler(int irq, void *dev_id) pr_err("Unexpected IOMMU page fault!\n"); pr_err("base = %08x\n", (unsigned int) base); + ret = __enable_clocks(drvdata); + if (ret) + goto fail; + ncb = GET_NCB(base)+1; for (i = 0; i < ncb; i++) { fsr = GET_FSR(base, i); @@ -614,6 +665,7 @@ irqreturn_t msm_iommu_fault_handler(int irq, void *dev_id) SET_FSR(base, i, 0x4000000F); } } + __disable_clocks(drvdata); fail: spin_unlock(&msm_iommu_lock); return 0; -- cgit v0.10.2 From b61401adf38f56dbfdac91f31425edf60595ed30 Mon Sep 17 00:00:00 2001 From: Stepan Moskovchenko Date: Mon, 28 Feb 2011 16:03:02 -0800 Subject: msm: iommu: Rework clock logic and add IOMMU bus clock control Clean up the clock control code in the probe calls, and add support for controlling the clock for the IOMMU bus interconnect. With the (proper) clock driver in place, the clock control logic in the probe function can be made much cleaner since it does not have to deal with the placeholder driver anymore. Signed-off-by: Stepan Moskovchenko Reviewed-by: Trilok Soni Signed-off-by: David Brown diff --git a/arch/arm/mach-msm/devices-iommu.c b/arch/arm/mach-msm/devices-iommu.c index c0206b7..af97afe 100644 --- a/arch/arm/mach-msm/devices-iommu.c +++ b/arch/arm/mach-msm/devices-iommu.c @@ -280,7 +280,6 @@ static struct platform_device msm_root_iommu_dev = { static struct msm_iommu_dev jpegd_iommu = { .name = "jpegd", - .clk_rate = -1 }; static struct msm_iommu_dev vpe_iommu = { @@ -305,7 +304,6 @@ static struct msm_iommu_dev ijpeg_iommu = { static struct msm_iommu_dev vfe_iommu = { .name = "vfe", - .clk_rate = -1 }; static struct msm_iommu_dev vcodec_a_iommu = { @@ -318,17 +316,14 @@ static struct msm_iommu_dev vcodec_b_iommu = { static struct msm_iommu_dev gfx3d_iommu = { .name = "gfx3d", - .clk_rate = 27000000 }; static struct msm_iommu_dev gfx2d0_iommu = { .name = "gfx2d0", - .clk_rate = 27000000 }; static struct msm_iommu_dev gfx2d1_iommu = { .name = "gfx2d1", - .clk_rate = 27000000 }; static struct platform_device msm_device_iommu_jpegd = { diff --git a/arch/arm/mach-msm/include/mach/iommu.h b/arch/arm/mach-msm/include/mach/iommu.h index 8738a44..4dfe7ef 100644 --- a/arch/arm/mach-msm/include/mach/iommu.h +++ b/arch/arm/mach-msm/include/mach/iommu.h @@ -45,14 +45,9 @@ /** * struct msm_iommu_dev - a single IOMMU hardware instance * name Human-readable name given to this IOMMU HW instance - * clk_rate Rate to set for this IOMMU's clock, if applicable to this - * particular IOMMU. 0 means don't set a rate. - * -1 means it is an AXI clock with no valid rate - * */ struct msm_iommu_dev { const char *name; - int clk_rate; }; /** diff --git a/arch/arm/mach-msm/iommu_dev.c b/arch/arm/mach-msm/iommu_dev.c index b83c73b..79ade0b 100644 --- a/arch/arm/mach-msm/iommu_dev.c +++ b/arch/arm/mach-msm/iommu_dev.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2010, Code Aurora Forum. All rights reserved. +/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -29,6 +29,7 @@ #include #include +#include struct iommu_ctx_iter_data { /* input */ @@ -130,117 +131,134 @@ static int msm_iommu_probe(struct platform_device *pdev) { struct resource *r, *r2; struct clk *iommu_clk; + struct clk *iommu_pclk; struct msm_iommu_drvdata *drvdata; struct msm_iommu_dev *iommu_dev = pdev->dev.platform_data; void __iomem *regs_base; resource_size_t len; - int ret = 0, ncb, nm2v, irq; + int ret, ncb, nm2v, irq; - if (pdev->id != -1) { - drvdata = kzalloc(sizeof(*drvdata), GFP_KERNEL); + if (pdev->id == -1) { + msm_iommu_root_dev = pdev; + return 0; + } - if (!drvdata) { - ret = -ENOMEM; - goto fail; - } + drvdata = kzalloc(sizeof(*drvdata), GFP_KERNEL); - if (!iommu_dev) { - ret = -ENODEV; - goto fail; - } + if (!drvdata) { + ret = -ENOMEM; + goto fail; + } + + if (!iommu_dev) { + ret = -ENODEV; + goto fail; + } - if (iommu_dev->clk_rate != 0) { - iommu_clk = clk_get(&pdev->dev, "iommu_clk"); - - if (IS_ERR(iommu_clk)) { - ret = -ENODEV; - goto fail; - } - - if (iommu_dev->clk_rate > 0) { - ret = clk_set_rate(iommu_clk, - iommu_dev->clk_rate); - if (ret) { - clk_put(iommu_clk); - goto fail; - } - } - - ret = clk_enable(iommu_clk); - if (ret) { - clk_put(iommu_clk); - goto fail; - } + iommu_pclk = clk_get(NULL, "smmu_pclk"); + if (IS_ERR(iommu_pclk)) { + ret = -ENODEV; + goto fail; + } + + ret = clk_enable(iommu_pclk); + if (ret) + goto fail_enable; + + iommu_clk = clk_get(&pdev->dev, "iommu_clk"); + + if (!IS_ERR(iommu_clk)) { + if (clk_get_rate(iommu_clk) == 0) + clk_set_min_rate(iommu_clk, 1); + + ret = clk_enable(iommu_clk); + if (ret) { clk_put(iommu_clk); + goto fail_pclk; } + } else + iommu_clk = NULL; - r = platform_get_resource_byname(pdev, IORESOURCE_MEM, - "physbase"); - if (!r) { - ret = -ENODEV; - goto fail; - } + r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "physbase"); - len = r->end - r->start + 1; + if (!r) { + ret = -ENODEV; + goto fail_clk; + } - r2 = request_mem_region(r->start, len, r->name); - if (!r2) { - pr_err("Could not request memory region: " - "start=%p, len=%d\n", (void *) r->start, len); - ret = -EBUSY; - goto fail; - } + len = resource_size(r); - regs_base = ioremap(r2->start, len); + r2 = request_mem_region(r->start, len, r->name); + if (!r2) { + pr_err("Could not request memory region: start=%p, len=%d\n", + (void *) r->start, len); + ret = -EBUSY; + goto fail_clk; + } - if (!regs_base) { - pr_err("Could not ioremap: start=%p, len=%d\n", - (void *) r2->start, len); - ret = -EBUSY; - goto fail_mem; - } + regs_base = ioremap(r2->start, len); - irq = platform_get_irq_byname(pdev, "secure_irq"); - if (irq < 0) { - ret = -ENODEV; - goto fail_io; - } + if (!regs_base) { + pr_err("Could not ioremap: start=%p, len=%d\n", + (void *) r2->start, len); + ret = -EBUSY; + goto fail_mem; + } + + irq = platform_get_irq_byname(pdev, "secure_irq"); + if (irq < 0) { + ret = -ENODEV; + goto fail_io; + } - mb(); + mb(); - if (GET_IDR(regs_base) == 0) { - pr_err("Invalid IDR value detected\n"); - ret = -ENODEV; - goto fail_io; - } + if (GET_IDR(regs_base) == 0) { + pr_err("Invalid IDR value detected\n"); + ret = -ENODEV; + goto fail_io; + } - ret = request_irq(irq, msm_iommu_fault_handler, 0, - "msm_iommu_secure_irpt_handler", drvdata); - if (ret) { - pr_err("Request IRQ %d failed with ret=%d\n", irq, ret); - goto fail_io; - } + ret = request_irq(irq, msm_iommu_fault_handler, 0, + "msm_iommu_secure_irpt_handler", drvdata); + if (ret) { + pr_err("Request IRQ %d failed with ret=%d\n", irq, ret); + goto fail_io; + } - msm_iommu_reset(regs_base); - drvdata->base = regs_base; - drvdata->irq = irq; + msm_iommu_reset(regs_base); + drvdata->pclk = iommu_pclk; + drvdata->clk = iommu_clk; + drvdata->base = regs_base; + drvdata->irq = irq; - nm2v = GET_NM2VCBMT((unsigned long) regs_base); - ncb = GET_NCB((unsigned long) regs_base); + nm2v = GET_NM2VCBMT((unsigned long) regs_base); + ncb = GET_NCB((unsigned long) regs_base); - pr_info("device %s mapped at %p, irq %d with %d ctx banks\n", + pr_info("device %s mapped at %p, irq %d with %d ctx banks\n", iommu_dev->name, regs_base, irq, ncb+1); - platform_set_drvdata(pdev, drvdata); - } else - msm_iommu_root_dev = pdev; + platform_set_drvdata(pdev, drvdata); - return 0; + if (iommu_clk) + clk_disable(iommu_clk); + + clk_disable(iommu_pclk); + return 0; fail_io: iounmap(regs_base); fail_mem: release_mem_region(r->start, len); +fail_clk: + if (iommu_clk) { + clk_disable(iommu_clk); + clk_put(iommu_clk); + } +fail_pclk: + clk_disable(iommu_pclk); +fail_enable: + clk_put(iommu_pclk); fail: kfree(drvdata); return ret; @@ -252,7 +270,10 @@ static int msm_iommu_remove(struct platform_device *pdev) drv = platform_get_drvdata(pdev); if (drv) { - memset(drv, 0, sizeof(struct msm_iommu_drvdata)); + if (drv->clk) + clk_put(drv->clk); + clk_put(drv->pclk); + memset(drv, 0, sizeof(*drv)); kfree(drv); platform_set_drvdata(pdev, NULL); } @@ -264,7 +285,7 @@ static int msm_iommu_ctx_probe(struct platform_device *pdev) struct msm_iommu_ctx_dev *c = pdev->dev.platform_data; struct msm_iommu_drvdata *drvdata; struct msm_iommu_ctx_drvdata *ctx_drvdata = NULL; - int i, ret = 0; + int i, ret; if (!c || !pdev->dev.parent) { ret = -EINVAL; goto fail; @@ -288,6 +309,18 @@ static int msm_iommu_ctx_probe(struct platform_device *pdev) INIT_LIST_HEAD(&ctx_drvdata->attached_elm); platform_set_drvdata(pdev, ctx_drvdata); + ret = clk_enable(drvdata->pclk); + if (ret) + goto fail; + + if (drvdata->clk) { + ret = clk_enable(drvdata->clk); + if (ret) { + clk_disable(drvdata->pclk); + goto fail; + } + } + /* Program the M2V tables for this context */ for (i = 0; i < MAX_NUM_MIDS; i++) { int mid = c->mids[i]; @@ -310,8 +343,11 @@ static int msm_iommu_ctx_probe(struct platform_device *pdev) SET_NSCFG(drvdata->base, mid, 3); } - pr_info("context device %s with bank index %d\n", c->name, c->num); + if (drvdata->clk) + clk_disable(drvdata->clk); + clk_disable(drvdata->pclk); + dev_info(&pdev->dev, "context %s using bank %d\n", c->name, c->num); return 0; fail: kfree(ctx_drvdata); -- cgit v0.10.2 From 2e8c8ba98376459e73d03a285f5d3406b630ea2d Mon Sep 17 00:00:00 2001 From: Stepan Moskovchenko Date: Thu, 24 Feb 2011 18:00:41 -0800 Subject: msm: iommu: Use ASID tagging instead of VMID tagging Use ASID tags in the TLB instead of VMID tags in preparation for changes to the secure environment. Signed-off-by: Stepan Moskovchenko Signed-off-by: David Brown diff --git a/arch/arm/mach-msm/include/mach/iommu_hw-8xxx.h b/arch/arm/mach-msm/include/mach/iommu_hw-8xxx.h index c2c3da9..bbd397c 100644 --- a/arch/arm/mach-msm/include/mach/iommu_hw-8xxx.h +++ b/arch/arm/mach-msm/include/mach/iommu_hw-8xxx.h @@ -1,4 +1,4 @@ -/* Copyright (c) 2010, Code Aurora Forum. All rights reserved. +/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -68,6 +68,7 @@ do { \ #define FL_CACHEABLE (1 << 3) #define FL_TEX0 (1 << 12) #define FL_OFFSET(va) (((va) & 0xFFF00000) >> 20) +#define FL_NG (1 << 17) /* Second-level page table bits */ #define SL_BASE_MASK_LARGE 0xFFFF0000 @@ -81,6 +82,7 @@ do { \ #define SL_CACHEABLE (1 << 3) #define SL_TEX0 (1 << 6) #define SL_OFFSET(va) (((va) & 0xFF000) >> 12) +#define SL_NG (1 << 11) /* Memory type and cache policy attributes */ #define MT_SO 0 diff --git a/arch/arm/mach-msm/iommu.c b/arch/arm/mach-msm/iommu.c index cde3cd0..9c08740 100644 --- a/arch/arm/mach-msm/iommu.c +++ b/arch/arm/mach-msm/iommu.c @@ -137,7 +137,6 @@ static void __reset_context(void __iomem *base, int ctx) SET_TLBLKCR(base, ctx, 0); SET_PRRR(base, ctx, 0); SET_NMRR(base, ctx, 0); - SET_CONTEXTIDR(base, ctx, 0); } static void __program_context(void __iomem *base, int ctx, phys_addr_t pgtable) @@ -418,11 +417,11 @@ static int msm_iommu_map(struct iommu_domain *domain, unsigned long va, for (i = 0; i < 16; i++) *(fl_pte+i) = (pa & 0xFF000000) | FL_SUPERSECTION | FL_AP_READ | FL_AP_WRITE | FL_TYPE_SECT | - FL_SHARED | pgprot; + FL_SHARED | FL_NG | pgprot; } if (len == SZ_1M) - *fl_pte = (pa & 0xFFF00000) | FL_AP_READ | FL_AP_WRITE | + *fl_pte = (pa & 0xFFF00000) | FL_AP_READ | FL_AP_WRITE | FL_NG | FL_TYPE_SECT | FL_SHARED | pgprot; /* Need a 2nd level table */ @@ -447,7 +446,7 @@ static int msm_iommu_map(struct iommu_domain *domain, unsigned long va, if (len == SZ_4K) - *sl_pte = (pa & SL_BASE_MASK_SMALL) | SL_AP0 | SL_AP1 | + *sl_pte = (pa & SL_BASE_MASK_SMALL) | SL_AP0 | SL_AP1 | SL_NG | SL_SHARED | SL_TYPE_SMALL | pgprot; if (len == SZ_64K) { @@ -455,7 +454,7 @@ static int msm_iommu_map(struct iommu_domain *domain, unsigned long va, for (i = 0; i < 16; i++) *(sl_pte+i) = (pa & SL_BASE_MASK_LARGE) | SL_AP0 | - SL_AP1 | SL_SHARED | SL_TYPE_LARGE | pgprot; + SL_NG | SL_AP1 | SL_SHARED | SL_TYPE_LARGE | pgprot; } ret = __flush_iotlb(domain); diff --git a/arch/arm/mach-msm/iommu_dev.c b/arch/arm/mach-msm/iommu_dev.c index 79ade0b..0e240c9 100644 --- a/arch/arm/mach-msm/iommu_dev.c +++ b/arch/arm/mach-msm/iommu_dev.c @@ -330,14 +330,17 @@ static int msm_iommu_ctx_probe(struct platform_device *pdev) SET_M2VCBR_N(drvdata->base, mid, 0); SET_CBACR_N(drvdata->base, c->num, 0); - /* Set VMID = MID */ - SET_VMID(drvdata->base, mid, mid); + /* Set VMID = 0 */ + SET_VMID(drvdata->base, mid, 0); /* Set the context number for that MID to this context */ SET_CBNDX(drvdata->base, mid, c->num); - /* Set MID associated with this context bank */ - SET_CBVMID(drvdata->base, c->num, mid); + /* Set MID associated with this context bank to 0*/ + SET_CBVMID(drvdata->base, c->num, 0); + + /* Set the ASID for TLB tagging for this context */ + SET_CONTEXTIDR_ASID(drvdata->base, c->num, c->num); /* Set security bit override to be Non-secure */ SET_NSCFG(drvdata->base, mid, 3); -- cgit v0.10.2 From a43d8c101eb71bf4527dd7f36a34a5a502894f38 Mon Sep 17 00:00:00 2001 From: Stepan Moskovchenko Date: Thu, 24 Feb 2011 18:00:42 -0800 Subject: msm: iommu: Remove dependency on IDR Remove the depencency on the IOMMU IDR register, as it may not be accessible depending on the security configuraton. This involves moving the NCB field of IDR into the platform data. Signed-off-by: Stepan Moskovchenko Signed-off-by: David Brown diff --git a/arch/arm/mach-msm/devices-iommu.c b/arch/arm/mach-msm/devices-iommu.c index af97afe..24030d0 100644 --- a/arch/arm/mach-msm/devices-iommu.c +++ b/arch/arm/mach-msm/devices-iommu.c @@ -280,50 +280,62 @@ static struct platform_device msm_root_iommu_dev = { static struct msm_iommu_dev jpegd_iommu = { .name = "jpegd", + .ncb = 2, }; static struct msm_iommu_dev vpe_iommu = { - .name = "vpe" + .name = "vpe", + .ncb = 2, }; static struct msm_iommu_dev mdp0_iommu = { - .name = "mdp0" + .name = "mdp0", + .ncb = 2, }; static struct msm_iommu_dev mdp1_iommu = { - .name = "mdp1" + .name = "mdp1", + .ncb = 2, }; static struct msm_iommu_dev rot_iommu = { - .name = "rot" + .name = "rot", + .ncb = 2, }; static struct msm_iommu_dev ijpeg_iommu = { - .name = "ijpeg" + .name = "ijpeg", + .ncb = 2, }; static struct msm_iommu_dev vfe_iommu = { .name = "vfe", + .ncb = 2, }; static struct msm_iommu_dev vcodec_a_iommu = { - .name = "vcodec_a" + .name = "vcodec_a", + .ncb = 2, }; static struct msm_iommu_dev vcodec_b_iommu = { - .name = "vcodec_b" + .name = "vcodec_b", + .ncb = 2, }; static struct msm_iommu_dev gfx3d_iommu = { .name = "gfx3d", + .ncb = 3, }; static struct msm_iommu_dev gfx2d0_iommu = { .name = "gfx2d0", + .ncb = 2, }; static struct msm_iommu_dev gfx2d1_iommu = { .name = "gfx2d1", + .ncb = 2, }; static struct platform_device msm_device_iommu_jpegd = { diff --git a/arch/arm/mach-msm/include/mach/iommu.h b/arch/arm/mach-msm/include/mach/iommu.h index 4dfe7ef..5c7c955 100644 --- a/arch/arm/mach-msm/include/mach/iommu.h +++ b/arch/arm/mach-msm/include/mach/iommu.h @@ -45,9 +45,11 @@ /** * struct msm_iommu_dev - a single IOMMU hardware instance * name Human-readable name given to this IOMMU HW instance + * ncb Number of context banks present on this IOMMU HW instance */ struct msm_iommu_dev { const char *name; + int ncb; }; /** @@ -69,6 +71,7 @@ struct msm_iommu_ctx_dev { /** * struct msm_iommu_drvdata - A single IOMMU hardware instance * @base: IOMMU config port base address (VA) + * @ncb The number of contexts on this IOMMU * @irq: Interrupt number * @clk: The bus clock for this IOMMU hardware instance * @pclk: The clock for the IOMMU bus interconnect @@ -79,6 +82,7 @@ struct msm_iommu_ctx_dev { struct msm_iommu_drvdata { void __iomem *base; int irq; + int ncb; struct clk *clk; struct clk *pclk; }; diff --git a/arch/arm/mach-msm/iommu.c b/arch/arm/mach-msm/iommu.c index 9c08740..0146f519 100644 --- a/arch/arm/mach-msm/iommu.c +++ b/arch/arm/mach-msm/iommu.c @@ -636,7 +636,7 @@ irqreturn_t msm_iommu_fault_handler(int irq, void *dev_id) struct msm_iommu_drvdata *drvdata = dev_id; void __iomem *base; unsigned int fsr; - int ncb, i, ret; + int i, ret; spin_lock(&msm_iommu_lock); @@ -654,8 +654,7 @@ irqreturn_t msm_iommu_fault_handler(int irq, void *dev_id) if (ret) goto fail; - ncb = GET_NCB(base)+1; - for (i = 0; i < ncb; i++) { + for (i = 0; i < drvdata->ncb; i++) { fsr = GET_FSR(base, i); if (fsr) { pr_err("Fault occurred in context %d.\n", i); diff --git a/arch/arm/mach-msm/iommu_dev.c b/arch/arm/mach-msm/iommu_dev.c index 0e240c9..8e8fb07 100644 --- a/arch/arm/mach-msm/iommu_dev.c +++ b/arch/arm/mach-msm/iommu_dev.c @@ -85,9 +85,9 @@ fail: } EXPORT_SYMBOL(msm_iommu_get_ctx); -static void msm_iommu_reset(void __iomem *base) +static void msm_iommu_reset(void __iomem *base, int ncb) { - int ctx, ncb; + int ctx; SET_RPUE(base, 0); SET_RPUEIE(base, 0); @@ -100,7 +100,6 @@ static void msm_iommu_reset(void __iomem *base) SET_GLOBAL_TLBIALL(base, 0); SET_RPU_ACR(base, 0); SET_TLBLKCRWE(base, 1); - ncb = GET_NCB(base)+1; for (ctx = 0; ctx < ncb; ctx++) { SET_BPRCOSH(base, ctx, 0); @@ -136,7 +135,7 @@ static int msm_iommu_probe(struct platform_device *pdev) struct msm_iommu_dev *iommu_dev = pdev->dev.platform_data; void __iomem *regs_base; resource_size_t len; - int ret, ncb, nm2v, irq; + int ret, irq, par; if (pdev->id == -1) { msm_iommu_root_dev = pdev; @@ -211,10 +210,18 @@ static int msm_iommu_probe(struct platform_device *pdev) goto fail_io; } - mb(); + msm_iommu_reset(regs_base, iommu_dev->ncb); - if (GET_IDR(regs_base) == 0) { - pr_err("Invalid IDR value detected\n"); + SET_M(regs_base, 0, 1); + SET_PAR(regs_base, 0, 0); + SET_V2PCFG(regs_base, 0, 1); + SET_V2PPR(regs_base, 0, 0); + par = GET_PAR(regs_base, 0); + SET_V2PCFG(regs_base, 0, 0); + SET_M(regs_base, 0, 0); + + if (!par) { + pr_err("%s: Invalid PAR value detected\n", iommu_dev->name); ret = -ENODEV; goto fail_io; } @@ -226,17 +233,15 @@ static int msm_iommu_probe(struct platform_device *pdev) goto fail_io; } - msm_iommu_reset(regs_base); + drvdata->pclk = iommu_pclk; drvdata->clk = iommu_clk; drvdata->base = regs_base; drvdata->irq = irq; - - nm2v = GET_NM2VCBMT((unsigned long) regs_base); - ncb = GET_NCB((unsigned long) regs_base); + drvdata->ncb = iommu_dev->ncb; pr_info("device %s mapped at %p, irq %d with %d ctx banks\n", - iommu_dev->name, regs_base, irq, ncb+1); + iommu_dev->name, regs_base, irq, iommu_dev->ncb); platform_set_drvdata(pdev, drvdata); -- cgit v0.10.2 From b0e7808d548ea1d857216d31d63078411203a116 Mon Sep 17 00:00:00 2001 From: Stepan Moskovchenko Date: Mon, 28 Feb 2011 16:04:55 -0800 Subject: msm: iommu: Don't read from write-only registers Don't read from V2Pxx command registers when doing iova-to-phys operations. These registers are write-only and reading the value before modifying the VA bits is unnecessary. Signed-off-by: Stepan Moskovchenko Signed-off-by: David Brown diff --git a/arch/arm/mach-msm/include/mach/iommu_hw-8xxx.h b/arch/arm/mach-msm/include/mach/iommu_hw-8xxx.h index bbd397c..fc16010 100644 --- a/arch/arm/mach-msm/include/mach/iommu_hw-8xxx.h +++ b/arch/arm/mach-msm/include/mach/iommu_hw-8xxx.h @@ -625,20 +625,6 @@ do { \ #define SET_INDEX(b, c, v) SET_CONTEXT_FIELD(b, c, V2PSR, INDEX, v) -/* V2Pxx UW UR PW PR */ -#define SET_V2PUW_INDEX(b, c, v) SET_CONTEXT_FIELD(b, c, V2PUW, V2Pxx_INDEX, v) -#define SET_V2PUW_VA(b, c, v) SET_CONTEXT_FIELD(b, c, V2PUW, V2Pxx_VA, v) - -#define SET_V2PUR_INDEX(b, c, v) SET_CONTEXT_FIELD(b, c, V2PUR, V2Pxx_INDEX, v) -#define SET_V2PUR_VA(b, c, v) SET_CONTEXT_FIELD(b, c, V2PUR, V2Pxx_VA, v) - -#define SET_V2PPW_INDEX(b, c, v) SET_CONTEXT_FIELD(b, c, V2PPW, V2Pxx_INDEX, v) -#define SET_V2PPW_VA(b, c, v) SET_CONTEXT_FIELD(b, c, V2PPW, V2Pxx_VA, v) - -#define SET_V2PPR_INDEX(b, c, v) SET_CONTEXT_FIELD(b, c, V2PPR, V2Pxx_INDEX, v) -#define SET_V2PPR_VA(b, c, v) SET_CONTEXT_FIELD(b, c, V2PPR, V2Pxx_VA, v) - - /* Context Register getters */ /* ACTLR */ #define GET_CFERE(b, c) GET_CONTEXT_FIELD(b, c, ACTLR, CFERE) @@ -826,20 +812,6 @@ do { \ #define GET_INDEX(b, c) GET_CONTEXT_FIELD(b, c, V2PSR, INDEX) -/* V2Pxx UW UR PW PR */ -#define GET_V2PUW_INDEX(b, c) GET_CONTEXT_FIELD(b, c, V2PUW, V2Pxx_INDEX) -#define GET_V2PUW_VA(b, c) GET_CONTEXT_FIELD(b, c, V2PUW, V2Pxx_VA) - -#define GET_V2PUR_INDEX(b, c) GET_CONTEXT_FIELD(b, c, V2PUR, V2Pxx_INDEX) -#define GET_V2PUR_VA(b, c) GET_CONTEXT_FIELD(b, c, V2PUR, V2Pxx_VA) - -#define GET_V2PPW_INDEX(b, c) GET_CONTEXT_FIELD(b, c, V2PPW, V2Pxx_INDEX) -#define GET_V2PPW_VA(b, c) GET_CONTEXT_FIELD(b, c, V2PPW, V2Pxx_VA) - -#define GET_V2PPR_INDEX(b, c) GET_CONTEXT_FIELD(b, c, V2PPR, V2Pxx_INDEX) -#define GET_V2PPR_VA(b, c) GET_CONTEXT_FIELD(b, c, V2PPR, V2Pxx_VA) - - /* Global Registers */ #define M2VCBR_N (0xFF000) #define CBACR_N (0xFF800) diff --git a/arch/arm/mach-msm/iommu.c b/arch/arm/mach-msm/iommu.c index 0146f519..1a584e0 100644 --- a/arch/arm/mach-msm/iommu.c +++ b/arch/arm/mach-msm/iommu.c @@ -579,7 +579,7 @@ static phys_addr_t msm_iommu_iova_to_phys(struct iommu_domain *domain, /* Invalidate context TLB */ SET_CTX_TLBIALL(base, ctx, 0); - SET_V2PPR_VA(base, ctx, va >> V2Pxx_VA_SHIFT); + SET_V2PPR(base, ctx, va & V2Pxx_VA); par = GET_PAR(base, ctx); -- cgit v0.10.2 From c7831df3937f54bddc20128892a75373549516d0 Mon Sep 17 00:00:00 2001 From: Stepan Moskovchenko Date: Mon, 28 Feb 2011 16:04:56 -0800 Subject: msm: iommu: Enable HTW L2 redirection on MSM8960 Allow the MSM8960 IOMMU to access its page tables directly through the L2 cache. Signed-off-by: Stepan Moskovchenko Signed-off-by: David Brown diff --git a/arch/arm/mach-msm/Kconfig b/arch/arm/mach-msm/Kconfig index 997c5bd..1516896 100644 --- a/arch/arm/mach-msm/Kconfig +++ b/arch/arm/mach-msm/Kconfig @@ -162,7 +162,7 @@ config MSM_IOMMU config IOMMU_PGTABLES_L2 def_bool y - depends on ARCH_MSM8X60 && MMU && SMP && CPU_DCACHE_DISABLE=n + depends on MSM_IOMMU && MMU && SMP && CPU_DCACHE_DISABLE=n config MSM_DEBUG_UART int -- cgit v0.10.2 From 7e1a68abaef094d5927ffe76bce21d6d8aa87bcb Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Thu, 24 Feb 2011 10:44:42 -0800 Subject: msm: scm: Mark inline asm as volatile We don't want the compiler to remove these asm statements or reorder them in any way. Mark them as volatile to be sure. Signed-off-by: Stephen Boyd Acked-by: Will Deacon Signed-off-by: David Brown diff --git a/arch/arm/mach-msm/scm.c b/arch/arm/mach-msm/scm.c index f4b9bc9..ba57b5a 100644 --- a/arch/arm/mach-msm/scm.c +++ b/arch/arm/mach-msm/scm.c @@ -174,7 +174,7 @@ static u32 smc(u32 cmd_addr) register u32 r0 asm("r0") = 1; register u32 r1 asm("r1") = (u32)&context_id; register u32 r2 asm("r2") = cmd_addr; - asm( + asm volatile( __asmeq("%0", "r0") __asmeq("%1", "r0") __asmeq("%2", "r1") @@ -271,7 +271,7 @@ u32 scm_get_version(void) return version; mutex_lock(&scm_lock); - asm( + asm volatile( __asmeq("%0", "r1") __asmeq("%1", "r0") __asmeq("%2", "r1") -- cgit v0.10.2 From 98d4ded60bda17a9ffecd902b03deac52922b788 Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Thu, 24 Feb 2011 10:44:43 -0800 Subject: msm: scm: Fix improper register assignment Assign the registers used in the inline assembly immediately before the inline assembly block. This ensures the compiler doesn't optimize away dead register assignments when it shouldn't. Signed-off-by: Stephen Boyd Acked-by: Nicolas Pitre Signed-off-by: David Brown diff --git a/arch/arm/mach-msm/scm.c b/arch/arm/mach-msm/scm.c index ba57b5a..5eddf54 100644 --- a/arch/arm/mach-msm/scm.c +++ b/arch/arm/mach-msm/scm.c @@ -264,13 +264,16 @@ u32 scm_get_version(void) { int context_id; static u32 version = -1; - register u32 r0 asm("r0") = 0x1 << 8; - register u32 r1 asm("r1") = (u32)&context_id; + register u32 r0 asm("r0"); + register u32 r1 asm("r1"); if (version != -1) return version; mutex_lock(&scm_lock); + + r0 = 0x1 << 8; + r1 = (u32)&context_id; asm volatile( __asmeq("%0", "r1") __asmeq("%1", "r0") -- cgit v0.10.2 From 8e76a80960bf06c245160a484d5a363ca6b520bb Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Thu, 24 Feb 2011 10:44:44 -0800 Subject: msm: scm: Check for interruption immediately When we're interrupted on the secure side, we should just issue another smc instruction again instead of replaying the arguments to smc. Fix it. Signed-off-by: Stephen Boyd Signed-off-by: David Brown diff --git a/arch/arm/mach-msm/scm.c b/arch/arm/mach-msm/scm.c index 5eddf54..cfa808d 100644 --- a/arch/arm/mach-msm/scm.c +++ b/arch/arm/mach-msm/scm.c @@ -174,15 +174,18 @@ static u32 smc(u32 cmd_addr) register u32 r0 asm("r0") = 1; register u32 r1 asm("r1") = (u32)&context_id; register u32 r2 asm("r2") = cmd_addr; - asm volatile( - __asmeq("%0", "r0") - __asmeq("%1", "r0") - __asmeq("%2", "r1") - __asmeq("%3", "r2") - "smc #0 @ switch to secure world\n" - : "=r" (r0) - : "r" (r0), "r" (r1), "r" (r2) - : "r3"); + do { + asm volatile( + __asmeq("%0", "r0") + __asmeq("%1", "r0") + __asmeq("%2", "r1") + __asmeq("%3", "r2") + "smc #0 @ switch to secure world\n" + : "=r" (r0) + : "r" (r0), "r" (r1), "r" (r2) + : "r3"); + } while (r0 == SCM_INTERRUPTED); + return r0; } @@ -197,13 +200,9 @@ static int __scm_call(const struct scm_command *cmd) * side in the buffer. */ flush_cache_all(); - do { - ret = smc(cmd_addr); - if (ret < 0) { - ret = scm_remap_error(ret); - break; - } - } while (ret == SCM_INTERRUPTED); + ret = smc(cmd_addr); + if (ret < 0) + ret = scm_remap_error(ret); return ret; } @@ -274,14 +273,18 @@ u32 scm_get_version(void) r0 = 0x1 << 8; r1 = (u32)&context_id; - asm volatile( - __asmeq("%0", "r1") - __asmeq("%1", "r0") - __asmeq("%2", "r1") - "smc #0 @ switch to secure world\n" - : "=r" (r1) - : "r" (r0), "r" (r1) - : "r2", "r3"); + do { + asm volatile( + __asmeq("%0", "r0") + __asmeq("%1", "r1") + __asmeq("%2", "r0") + __asmeq("%3", "r1") + "smc #0 @ switch to secure world\n" + : "=r" (r0), "=r" (r1) + : "r" (r0), "r" (r1) + : "r2", "r3"); + } while (r0 == SCM_INTERRUPTED); + version = r1; mutex_unlock(&scm_lock); -- cgit v0.10.2