From 023e06dfa6882f500b9c86fd61f0b1913aa07f36 Mon Sep 17 00:00:00 2001 From: Hakjoo Kim Date: Sun, 15 Mar 2015 23:00:32 +0100 Subject: pinctrl: exynos: add exynos5410 SoC specific data MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add Samsung EXYNOS5410 SoC specific data to enable pinctrl support for all platforms based on EXYNOS5410. Signed-off-by: Hakjoo Kim [AF: Rebased onto Exynos5260, irq_chip consolidation, const'ification] Signed-off-by: Andreas Färber Acked-by: Tomasz Figa Tested-by: Pavel Fedin [k.kozlowski: Rebased on current v4.3] Signed-off-by: Krzysztof Kozlowski diff --git a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt index 9d2a995..6db16b9 100644 --- a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt @@ -17,6 +17,7 @@ Required Properties: - "samsung,exynos4x12-pinctrl": for Exynos4x12 compatible pin-controller. - "samsung,exynos5250-pinctrl": for Exynos5250 compatible pin-controller. - "samsung,exynos5260-pinctrl": for Exynos5260 compatible pin-controller. + - "samsung,exynos5410-pinctrl": for Exynos5410 compatible pin-controller. - "samsung,exynos5420-pinctrl": for Exynos5420 compatible pin-controller. - "samsung,exynos7-pinctrl": for Exynos7 compatible pin-controller. diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c b/drivers/pinctrl/samsung/pinctrl-exynos.c index 71ccf6a..16e2293 100644 --- a/drivers/pinctrl/samsung/pinctrl-exynos.c +++ b/drivers/pinctrl/samsung/pinctrl-exynos.c @@ -1150,6 +1150,109 @@ const struct samsung_pin_ctrl exynos5260_pin_ctrl[] __initconst = { }, }; +/* pin banks of exynos5410 pin-controller 0 */ +static const struct samsung_pin_bank_data exynos5410_pin_banks0[] __initconst = { + EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00), + EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04), + EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08), + EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c), + EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpb1", 0x10), + EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpb2", 0x14), + EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpb3", 0x18), + EXYNOS_PIN_BANK_EINTG(7, 0x0E0, "gpc0", 0x1c), + EXYNOS_PIN_BANK_EINTG(4, 0x100, "gpc3", 0x20), + EXYNOS_PIN_BANK_EINTG(7, 0x120, "gpc1", 0x24), + EXYNOS_PIN_BANK_EINTG(7, 0x140, "gpc2", 0x28), + EXYNOS_PIN_BANK_EINTN(2, 0x160, "gpm5"), + EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpd1", 0x2c), + EXYNOS_PIN_BANK_EINTG(8, 0x1A0, "gpe0", 0x30), + EXYNOS_PIN_BANK_EINTG(2, 0x1C0, "gpe1", 0x34), + EXYNOS_PIN_BANK_EINTG(6, 0x1E0, "gpf0", 0x38), + EXYNOS_PIN_BANK_EINTG(8, 0x200, "gpf1", 0x3c), + EXYNOS_PIN_BANK_EINTG(8, 0x220, "gpg0", 0x40), + EXYNOS_PIN_BANK_EINTG(8, 0x240, "gpg1", 0x44), + EXYNOS_PIN_BANK_EINTG(2, 0x260, "gpg2", 0x48), + EXYNOS_PIN_BANK_EINTG(4, 0x280, "gph0", 0x4c), + EXYNOS_PIN_BANK_EINTG(8, 0x2A0, "gph1", 0x50), + EXYNOS_PIN_BANK_EINTN(8, 0x2C0, "gpm7"), + EXYNOS_PIN_BANK_EINTN(6, 0x2E0, "gpy0"), + EXYNOS_PIN_BANK_EINTN(4, 0x300, "gpy1"), + EXYNOS_PIN_BANK_EINTN(6, 0x320, "gpy2"), + EXYNOS_PIN_BANK_EINTN(8, 0x340, "gpy3"), + EXYNOS_PIN_BANK_EINTN(8, 0x360, "gpy4"), + EXYNOS_PIN_BANK_EINTN(8, 0x380, "gpy5"), + EXYNOS_PIN_BANK_EINTN(8, 0x3A0, "gpy6"), + EXYNOS_PIN_BANK_EINTN(8, 0x3C0, "gpy7"), + EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00), + EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04), + EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08), + EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c), +}; + +/* pin banks of exynos5410 pin-controller 1 */ +static const struct samsung_pin_bank_data exynos5410_pin_banks1[] __initconst = { + EXYNOS_PIN_BANK_EINTG(5, 0x000, "gpj0", 0x00), + EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpj1", 0x04), + EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpj2", 0x08), + EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpj3", 0x0c), + EXYNOS_PIN_BANK_EINTG(2, 0x080, "gpj4", 0x10), + EXYNOS_PIN_BANK_EINTG(8, 0x0A0, "gpk0", 0x14), + EXYNOS_PIN_BANK_EINTG(8, 0x0C0, "gpk1", 0x18), + EXYNOS_PIN_BANK_EINTG(8, 0x0E0, "gpk2", 0x1c), + EXYNOS_PIN_BANK_EINTG(7, 0x100, "gpk3", 0x20), +}; + +/* pin banks of exynos5410 pin-controller 2 */ +static const struct samsung_pin_bank_data exynos5410_pin_banks2[] __initconst = { + EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpv0", 0x00), + EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpv1", 0x04), + EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpv2", 0x08), + EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpv3", 0x0c), + EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpv4", 0x10), +}; + +/* pin banks of exynos5410 pin-controller 3 */ +static const struct samsung_pin_bank_data exynos5410_pin_banks3[] __initconst = { + EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00), +}; + +/* + * Samsung pinctrl driver data for Exynos5410 SoC. Exynos5410 SoC includes + * four gpio/pin-mux/pinconfig controllers. + */ +const struct samsung_pin_ctrl exynos5410_pin_ctrl[] __initconst = { + { + /* pin-controller instance 0 data */ + .pin_banks = exynos5410_pin_banks0, + .nr_banks = ARRAY_SIZE(exynos5410_pin_banks0), + .eint_gpio_init = exynos_eint_gpio_init, + .eint_wkup_init = exynos_eint_wkup_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + }, { + /* pin-controller instance 1 data */ + .pin_banks = exynos5410_pin_banks1, + .nr_banks = ARRAY_SIZE(exynos5410_pin_banks1), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + }, { + /* pin-controller instance 2 data */ + .pin_banks = exynos5410_pin_banks2, + .nr_banks = ARRAY_SIZE(exynos5410_pin_banks2), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + }, { + /* pin-controller instance 3 data */ + .pin_banks = exynos5410_pin_banks3, + .nr_banks = ARRAY_SIZE(exynos5410_pin_banks3), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + }, +}; + /* pin banks of exynos5420 pin-controller 0 */ static const struct samsung_pin_bank_data exynos5420_pin_banks0[] __initconst = { EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpy7", 0x00), diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.c b/drivers/pinctrl/samsung/pinctrl-samsung.c index 3f622cc..48294e7 100644 --- a/drivers/pinctrl/samsung/pinctrl-samsung.c +++ b/drivers/pinctrl/samsung/pinctrl-samsung.c @@ -1222,6 +1222,8 @@ static const struct of_device_id samsung_pinctrl_dt_match[] = { .data = (void *)exynos5250_pin_ctrl }, { .compatible = "samsung,exynos5260-pinctrl", .data = (void *)exynos5260_pin_ctrl }, + { .compatible = "samsung,exynos5410-pinctrl", + .data = (void *)exynos5410_pin_ctrl }, { .compatible = "samsung,exynos5420-pinctrl", .data = (void *)exynos5420_pin_ctrl }, { .compatible = "samsung,exynos5433-pinctrl", diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.h b/drivers/pinctrl/samsung/pinctrl-samsung.h index c1239ff..cd31bfa 100644 --- a/drivers/pinctrl/samsung/pinctrl-samsung.h +++ b/drivers/pinctrl/samsung/pinctrl-samsung.h @@ -270,6 +270,7 @@ extern const struct samsung_pin_ctrl exynos4x12_pin_ctrl[]; extern const struct samsung_pin_ctrl exynos4415_pin_ctrl[]; extern const struct samsung_pin_ctrl exynos5250_pin_ctrl[]; extern const struct samsung_pin_ctrl exynos5260_pin_ctrl[]; +extern const struct samsung_pin_ctrl exynos5410_pin_ctrl[]; extern const struct samsung_pin_ctrl exynos5420_pin_ctrl[]; extern const struct samsung_pin_ctrl exynos5433_pin_ctrl[]; extern const struct samsung_pin_ctrl exynos7_pin_ctrl[]; -- cgit v0.10.2 From f10a2585811ebd503ddf8ebcc9a32166c7b4b05f Mon Sep 17 00:00:00 2001 From: Markus Elfring Date: Thu, 5 Nov 2015 17:10:22 +0100 Subject: pinctrl: Delete unnecessary checks The pinctrl_unregister() function tests whether its argument is NULL and then returns immediately. Thus the test around the call is not needed. This issue was detected by using the Coccinelle software. Signed-off-by: Markus Elfring Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/bcm/pinctrl-cygnus-gpio.c b/drivers/pinctrl/bcm/pinctrl-cygnus-gpio.c index 12a48f4..663ad0a 100644 --- a/drivers/pinctrl/bcm/pinctrl-cygnus-gpio.c +++ b/drivers/pinctrl/bcm/pinctrl-cygnus-gpio.c @@ -638,8 +638,7 @@ static int cygnus_gpio_register_pinconf(struct cygnus_gpio *chip) static void cygnus_gpio_unregister_pinconf(struct cygnus_gpio *chip) { - if (chip->pctl) - pinctrl_unregister(chip->pctl); + pinctrl_unregister(chip->pctl); } struct cygnus_gpio_data { diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c index ef04b96..d24e5f1 100644 --- a/drivers/pinctrl/pinctrl-single.c +++ b/drivers/pinctrl/pinctrl-single.c @@ -1484,10 +1484,7 @@ static void pcs_irq_free(struct pcs_device *pcs) static void pcs_free_resources(struct pcs_device *pcs) { pcs_irq_free(pcs); - - if (pcs->pctl) - pinctrl_unregister(pcs->pctl); - + pinctrl_unregister(pcs->pctl); pcs_free_funcs(pcs); pcs_free_pingroups(pcs); } -- cgit v0.10.2 From b04a23b05609b35365127ad8906c55866eb47fe7 Mon Sep 17 00:00:00 2001 From: Hongzhou Yang Date: Tue, 17 Nov 2015 14:33:41 -0800 Subject: pinctrl: mediatek: fix a memleak when do dt maps. configs will kmemdup to dup_configs in pictrl util function. So configs need to be freed. Signed-off-by: Hongzhou Yang Reviewed-by: Daniel Kurtz Reviewed-by: Matthias Brugger Reviewed-by: Yingjoe Chen Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c index f307f1d..3bb4a2a 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c @@ -509,6 +509,9 @@ static int mtk_pctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev, err = pinconf_generic_parse_dt_config(node, pctldev, &configs, &num_configs); + if (err) + return err; + if (num_configs) has_config = 1; @@ -520,21 +523,23 @@ static int mtk_pctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev, if (has_config && num_pins >= 1) maps_per_pin++; - if (!num_pins || !maps_per_pin) - return -EINVAL; + if (!num_pins || !maps_per_pin) { + err = -EINVAL; + goto exit; + } reserve = num_pins * maps_per_pin; err = pinctrl_utils_reserve_map(pctldev, map, reserved_maps, num_maps, reserve); if (err < 0) - goto fail; + goto exit; for (i = 0; i < num_pins; i++) { err = of_property_read_u32_index(node, "pinmux", i, &pinfunc); if (err) - goto fail; + goto exit; pin = MTK_GET_PIN_NO(pinfunc); func = MTK_GET_PIN_FUNC(pinfunc); @@ -543,20 +548,21 @@ static int mtk_pctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev, func >= ARRAY_SIZE(mtk_gpio_functions)) { dev_err(pctl->dev, "invalid pins value.\n"); err = -EINVAL; - goto fail; + goto exit; } grp = mtk_pctrl_find_group_by_pin(pctl, pin); if (!grp) { dev_err(pctl->dev, "unable to match pin %d to group\n", pin); - return -EINVAL; + err = -EINVAL; + goto exit; } err = mtk_pctrl_dt_node_to_map_func(pctl, pin, func, grp, map, reserved_maps, num_maps); if (err < 0) - goto fail; + goto exit; if (has_config) { err = pinctrl_utils_add_map_configs(pctldev, map, @@ -564,13 +570,14 @@ static int mtk_pctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev, configs, num_configs, PIN_MAP_TYPE_CONFIGS_GROUP); if (err < 0) - goto fail; + goto exit; } } - return 0; + err = 0; -fail: +exit: + kfree(configs); return err; } -- cgit v0.10.2 From 2652df631cbe9bd4bb0f3c9dcc284e0f099dbbf1 Mon Sep 17 00:00:00 2001 From: Pramod Kumar Date: Thu, 19 Nov 2015 09:22:13 +0530 Subject: dt-binding: Add ngpios property to GPIO controller node Add ngpios property to the gpio controller's DT node so that controller driver extracts total number of in-use gpio lines from DT and removes dependency on driver. Signed-off-by: Pramod Kumar Reviewed-by: Ray Jui Reviewed-by: Scott Branden Acked-by: Rob Herring Signed-off-by: Linus Walleij diff --git a/Documentation/devicetree/bindings/pinctrl/brcm,cygnus-gpio.txt b/Documentation/devicetree/bindings/pinctrl/brcm,cygnus-gpio.txt index 16589fb6..8b1e5d1 100644 --- a/Documentation/devicetree/bindings/pinctrl/brcm,cygnus-gpio.txt +++ b/Documentation/devicetree/bindings/pinctrl/brcm,cygnus-gpio.txt @@ -10,6 +10,9 @@ Required properties: Define the base and range of the I/O address space that contains the Cygnus GPIO/PINCONF controller registers +- ngpios: + Total number of in-use slots in GPIO controller + - #gpio-cells: Must be two. The first cell is the GPIO pin number (within the controller's pin space) and the second cell is used for the following: @@ -57,6 +60,7 @@ Example: compatible = "brcm,cygnus-ccm-gpio"; reg = <0x1800a000 0x50>, <0x0301d164 0x20>; + ngpios = <24>; #gpio-cells = <2>; gpio-controller; interrupts = ; @@ -78,6 +82,7 @@ Example: gpio_asiu: gpio@180a5000 { compatible = "brcm,cygnus-asiu-gpio"; reg = <0x180a5000 0x668>; + ngpios = <146>; #gpio-cells = <2>; gpio-controller; interrupts = ; -- cgit v0.10.2 From e1aaaf3ff311ce03401965a38b33aceac4e51951 Mon Sep 17 00:00:00 2001 From: Pramod Kumar Date: Thu, 19 Nov 2015 09:22:15 +0530 Subject: pinctrl: use ngpios propety from DT Since identical hardware is used in several instances and every instance will have different in-use pins. Hence extracting this number from DT via "ngpios" property. Signed-off-by: Pramod Kumar Reviewed-by: Ray Jui Reviewed-by: Scott Branden Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/bcm/pinctrl-cygnus-gpio.c b/drivers/pinctrl/bcm/pinctrl-cygnus-gpio.c index 663ad0a..f19283a 100644 --- a/drivers/pinctrl/bcm/pinctrl-cygnus-gpio.c +++ b/drivers/pinctrl/bcm/pinctrl-cygnus-gpio.c @@ -641,35 +641,11 @@ static void cygnus_gpio_unregister_pinconf(struct cygnus_gpio *chip) pinctrl_unregister(chip->pctl); } -struct cygnus_gpio_data { - unsigned num_gpios; -}; - -static const struct cygnus_gpio_data cygnus_cmm_gpio_data = { - .num_gpios = 24, -}; - -static const struct cygnus_gpio_data cygnus_asiu_gpio_data = { - .num_gpios = 146, -}; - -static const struct cygnus_gpio_data cygnus_crmu_gpio_data = { - .num_gpios = 6, -}; - static const struct of_device_id cygnus_gpio_of_match[] = { - { - .compatible = "brcm,cygnus-ccm-gpio", - .data = &cygnus_cmm_gpio_data, - }, - { - .compatible = "brcm,cygnus-asiu-gpio", - .data = &cygnus_asiu_gpio_data, - }, - { - .compatible = "brcm,cygnus-crmu-gpio", - .data = &cygnus_crmu_gpio_data, - } + { .compatible = "brcm,cygnus-ccm-gpio" }, + { .compatible = "brcm,cygnus-asiu-gpio" }, + { .compatible = "brcm,cygnus-crmu-gpio" }, + { } }; static int cygnus_gpio_probe(struct platform_device *pdev) @@ -680,14 +656,6 @@ static int cygnus_gpio_probe(struct platform_device *pdev) struct gpio_chip *gc; u32 ngpios; int irq, ret; - const struct of_device_id *match; - const struct cygnus_gpio_data *gpio_data; - - match = of_match_device(cygnus_gpio_of_match, dev); - if (!match) - return -ENODEV; - gpio_data = match->data; - ngpios = gpio_data->num_gpios; chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); if (!chip) @@ -712,6 +680,11 @@ static int cygnus_gpio_probe(struct platform_device *pdev) } } + if (of_property_read_u32(dev->of_node, "ngpios", &ngpios)) { + dev_err(&pdev->dev, "missing ngpios DT property\n"); + return -ENODEV; + } + spin_lock_init(&chip->lock); gc = &chip->gc; -- cgit v0.10.2 From 462de629942212d90e6c915eca3eaebb45b647a3 Mon Sep 17 00:00:00 2001 From: Pramod Kumar Date: Thu, 19 Nov 2015 09:22:16 +0530 Subject: pinctrl: Add new compatible string to GPIO controller driver This compatible string should be used for all new iproc based future SoCs having the same GPIO controller hardware. Signed-off-by: Pramod Kumar Reviewed-by: Ray Jui Reviewed-by: Scott Branden Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/bcm/pinctrl-cygnus-gpio.c b/drivers/pinctrl/bcm/pinctrl-cygnus-gpio.c index f19283a..f60ec8e 100644 --- a/drivers/pinctrl/bcm/pinctrl-cygnus-gpio.c +++ b/drivers/pinctrl/bcm/pinctrl-cygnus-gpio.c @@ -645,6 +645,7 @@ static const struct of_device_id cygnus_gpio_of_match[] = { { .compatible = "brcm,cygnus-ccm-gpio" }, { .compatible = "brcm,cygnus-asiu-gpio" }, { .compatible = "brcm,cygnus-crmu-gpio" }, + { .compatible = "brcm,iproc-gpio" }, { } }; -- cgit v0.10.2 From afc8c78d179d36b85b648dca865e56040afc5f2d Mon Sep 17 00:00:00 2001 From: Pramod Kumar Date: Thu, 19 Nov 2015 09:22:17 +0530 Subject: gpio: Rename func/macro/var to IP-block,iproc Change functions, macros and variables name from cygnus to IP block, iproc, so that it could be used in all iproc based future SoCs having same GPIO controller block. Signed-off-by: Pramod Kumar Reviewed-by: Ray Jui Reviewed-by: Scott Branden Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/bcm/pinctrl-cygnus-gpio.c b/drivers/pinctrl/bcm/pinctrl-cygnus-gpio.c index f60ec8e..fa66c3e 100644 --- a/drivers/pinctrl/bcm/pinctrl-cygnus-gpio.c +++ b/drivers/pinctrl/bcm/pinctrl-cygnus-gpio.c @@ -10,14 +10,16 @@ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * - * This file contains the Broadcom Cygnus GPIO driver that supports 3 - * GPIO controllers on Cygnus including the ASIU GPIO controller, the + * This file contains the Broadcom Iproc GPIO driver that supports 3 + * GPIO controllers on Iproc including the ASIU GPIO controller, the * chipCommonG GPIO controller, and the always-on GPIO controller. Basic * PINCONF such as bias pull up/down, and drive strength are also supported * in this driver. * - * Pins from the ASIU GPIO can be individually muxed to GPIO function, - * through the interaction with the Cygnus IOMUX controller + * It provides the functionality where pins from the GPIO can be + * individually muxed to GPIO function, if individual pad + * configuration is supported, through the interaction with respective + * SoCs IOMUX controller. */ #include @@ -34,42 +36,42 @@ #include "../pinctrl-utils.h" -#define CYGNUS_GPIO_DATA_IN_OFFSET 0x00 -#define CYGNUS_GPIO_DATA_OUT_OFFSET 0x04 -#define CYGNUS_GPIO_OUT_EN_OFFSET 0x08 -#define CYGNUS_GPIO_INT_TYPE_OFFSET 0x0c -#define CYGNUS_GPIO_INT_DE_OFFSET 0x10 -#define CYGNUS_GPIO_INT_EDGE_OFFSET 0x14 -#define CYGNUS_GPIO_INT_MSK_OFFSET 0x18 -#define CYGNUS_GPIO_INT_STAT_OFFSET 0x1c -#define CYGNUS_GPIO_INT_MSTAT_OFFSET 0x20 -#define CYGNUS_GPIO_INT_CLR_OFFSET 0x24 -#define CYGNUS_GPIO_PAD_RES_OFFSET 0x34 -#define CYGNUS_GPIO_RES_EN_OFFSET 0x38 +#define IPROC_GPIO_DATA_IN_OFFSET 0x00 +#define IPROC_GPIO_DATA_OUT_OFFSET 0x04 +#define IPROC_GPIO_OUT_EN_OFFSET 0x08 +#define IPROC_GPIO_INT_TYPE_OFFSET 0x0c +#define IPROC_GPIO_INT_DE_OFFSET 0x10 +#define IPROC_GPIO_INT_EDGE_OFFSET 0x14 +#define IPROC_GPIO_INT_MSK_OFFSET 0x18 +#define IPROC_GPIO_INT_STAT_OFFSET 0x1c +#define IPROC_GPIO_INT_MSTAT_OFFSET 0x20 +#define IPROC_GPIO_INT_CLR_OFFSET 0x24 +#define IPROC_GPIO_PAD_RES_OFFSET 0x34 +#define IPROC_GPIO_RES_EN_OFFSET 0x38 /* drive strength control for ASIU GPIO */ -#define CYGNUS_GPIO_ASIU_DRV0_CTRL_OFFSET 0x58 +#define IPROC_GPIO_ASIU_DRV0_CTRL_OFFSET 0x58 /* drive strength control for CCM/CRMU (AON) GPIO */ -#define CYGNUS_GPIO_DRV0_CTRL_OFFSET 0x00 +#define IPROC_GPIO_DRV0_CTRL_OFFSET 0x00 #define GPIO_BANK_SIZE 0x200 #define NGPIOS_PER_BANK 32 #define GPIO_BANK(pin) ((pin) / NGPIOS_PER_BANK) -#define CYGNUS_GPIO_REG(pin, reg) (GPIO_BANK(pin) * GPIO_BANK_SIZE + (reg)) -#define CYGNUS_GPIO_SHIFT(pin) ((pin) % NGPIOS_PER_BANK) +#define IPROC_GPIO_REG(pin, reg) (GPIO_BANK(pin) * GPIO_BANK_SIZE + (reg)) +#define IPROC_GPIO_SHIFT(pin) ((pin) % NGPIOS_PER_BANK) #define GPIO_DRV_STRENGTH_BIT_SHIFT 20 #define GPIO_DRV_STRENGTH_BITS 3 #define GPIO_DRV_STRENGTH_BIT_MASK ((1 << GPIO_DRV_STRENGTH_BITS) - 1) /* - * Cygnus GPIO core + * Iproc GPIO core * * @dev: pointer to device - * @base: I/O register base for Cygnus GPIO controller - * @io_ctrl: I/O register base for certain type of Cygnus GPIO controller that + * @base: I/O register base for Iproc GPIO controller + * @io_ctrl: I/O register base for certain type of Iproc GPIO controller that * has the PINCONF support implemented outside of the GPIO block * @lock: lock to protect access to I/O registers * @gc: GPIO chip @@ -79,7 +81,7 @@ * @pctl: pointer to pinctrl_dev * @pctldesc: pinctrl descriptor */ -struct cygnus_gpio { +struct iproc_gpio { struct device *dev; void __iomem *base; @@ -96,33 +98,33 @@ struct cygnus_gpio { struct pinctrl_desc pctldesc; }; -static inline struct cygnus_gpio *to_cygnus_gpio(struct gpio_chip *gc) +static inline struct iproc_gpio *to_iproc_gpio(struct gpio_chip *gc) { - return container_of(gc, struct cygnus_gpio, gc); + return container_of(gc, struct iproc_gpio, gc); } /* * Mapping from PINCONF pins to GPIO pins is 1-to-1 */ -static inline unsigned cygnus_pin_to_gpio(unsigned pin) +static inline unsigned iproc_pin_to_gpio(unsigned pin) { return pin; } /** - * cygnus_set_bit - set or clear one bit (corresponding to the GPIO pin) in a - * Cygnus GPIO register + * iproc_set_bit - set or clear one bit (corresponding to the GPIO pin) in a + * Iproc GPIO register * - * @cygnus_gpio: Cygnus GPIO device + * @iproc_gpio: Iproc GPIO device * @reg: register offset * @gpio: GPIO pin * @set: set or clear */ -static inline void cygnus_set_bit(struct cygnus_gpio *chip, unsigned int reg, +static inline void iproc_set_bit(struct iproc_gpio *chip, unsigned int reg, unsigned gpio, bool set) { - unsigned int offset = CYGNUS_GPIO_REG(gpio, reg); - unsigned int shift = CYGNUS_GPIO_SHIFT(gpio); + unsigned int offset = IPROC_GPIO_REG(gpio, reg); + unsigned int shift = IPROC_GPIO_SHIFT(gpio); u32 val; val = readl(chip->base + offset); @@ -133,19 +135,19 @@ static inline void cygnus_set_bit(struct cygnus_gpio *chip, unsigned int reg, writel(val, chip->base + offset); } -static inline bool cygnus_get_bit(struct cygnus_gpio *chip, unsigned int reg, +static inline bool iproc_get_bit(struct iproc_gpio *chip, unsigned int reg, unsigned gpio) { - unsigned int offset = CYGNUS_GPIO_REG(gpio, reg); - unsigned int shift = CYGNUS_GPIO_SHIFT(gpio); + unsigned int offset = IPROC_GPIO_REG(gpio, reg); + unsigned int shift = IPROC_GPIO_SHIFT(gpio); return !!(readl(chip->base + offset) & BIT(shift)); } -static void cygnus_gpio_irq_handler(struct irq_desc *desc) +static void iproc_gpio_irq_handler(struct irq_desc *desc) { struct gpio_chip *gc = irq_desc_get_handler_data(desc); - struct cygnus_gpio *chip = to_cygnus_gpio(gc); + struct iproc_gpio *chip = to_iproc_gpio(gc); struct irq_chip *irq_chip = irq_desc_get_chip(desc); int i, bit; @@ -154,7 +156,7 @@ static void cygnus_gpio_irq_handler(struct irq_desc *desc) /* go through the entire GPIO banks and handle all interrupts */ for (i = 0; i < chip->num_banks; i++) { unsigned long val = readl(chip->base + (i * GPIO_BANK_SIZE) + - CYGNUS_GPIO_INT_MSTAT_OFFSET); + IPROC_GPIO_INT_MSTAT_OFFSET); for_each_set_bit(bit, &val, NGPIOS_PER_BANK) { unsigned pin = NGPIOS_PER_BANK * i + bit; @@ -165,7 +167,7 @@ static void cygnus_gpio_irq_handler(struct irq_desc *desc) * handler, so we do not leave any window */ writel(BIT(bit), chip->base + (i * GPIO_BANK_SIZE) + - CYGNUS_GPIO_INT_CLR_OFFSET); + IPROC_GPIO_INT_CLR_OFFSET); generic_handle_irq(child_irq); } @@ -175,60 +177,60 @@ static void cygnus_gpio_irq_handler(struct irq_desc *desc) } -static void cygnus_gpio_irq_ack(struct irq_data *d) +static void iproc_gpio_irq_ack(struct irq_data *d) { struct gpio_chip *gc = irq_data_get_irq_chip_data(d); - struct cygnus_gpio *chip = to_cygnus_gpio(gc); + struct iproc_gpio *chip = to_iproc_gpio(gc); unsigned gpio = d->hwirq; - unsigned int offset = CYGNUS_GPIO_REG(gpio, - CYGNUS_GPIO_INT_CLR_OFFSET); - unsigned int shift = CYGNUS_GPIO_SHIFT(gpio); + unsigned int offset = IPROC_GPIO_REG(gpio, + IPROC_GPIO_INT_CLR_OFFSET); + unsigned int shift = IPROC_GPIO_SHIFT(gpio); u32 val = BIT(shift); writel(val, chip->base + offset); } /** - * cygnus_gpio_irq_set_mask - mask/unmask a GPIO interrupt + * iproc_gpio_irq_set_mask - mask/unmask a GPIO interrupt * * @d: IRQ chip data * @unmask: mask/unmask GPIO interrupt */ -static void cygnus_gpio_irq_set_mask(struct irq_data *d, bool unmask) +static void iproc_gpio_irq_set_mask(struct irq_data *d, bool unmask) { struct gpio_chip *gc = irq_data_get_irq_chip_data(d); - struct cygnus_gpio *chip = to_cygnus_gpio(gc); + struct iproc_gpio *chip = to_iproc_gpio(gc); unsigned gpio = d->hwirq; - cygnus_set_bit(chip, CYGNUS_GPIO_INT_MSK_OFFSET, gpio, unmask); + iproc_set_bit(chip, IPROC_GPIO_INT_MSK_OFFSET, gpio, unmask); } -static void cygnus_gpio_irq_mask(struct irq_data *d) +static void iproc_gpio_irq_mask(struct irq_data *d) { struct gpio_chip *gc = irq_data_get_irq_chip_data(d); - struct cygnus_gpio *chip = to_cygnus_gpio(gc); + struct iproc_gpio *chip = to_iproc_gpio(gc); unsigned long flags; spin_lock_irqsave(&chip->lock, flags); - cygnus_gpio_irq_set_mask(d, false); + iproc_gpio_irq_set_mask(d, false); spin_unlock_irqrestore(&chip->lock, flags); } -static void cygnus_gpio_irq_unmask(struct irq_data *d) +static void iproc_gpio_irq_unmask(struct irq_data *d) { struct gpio_chip *gc = irq_data_get_irq_chip_data(d); - struct cygnus_gpio *chip = to_cygnus_gpio(gc); + struct iproc_gpio *chip = to_iproc_gpio(gc); unsigned long flags; spin_lock_irqsave(&chip->lock, flags); - cygnus_gpio_irq_set_mask(d, true); + iproc_gpio_irq_set_mask(d, true); spin_unlock_irqrestore(&chip->lock, flags); } -static int cygnus_gpio_irq_set_type(struct irq_data *d, unsigned int type) +static int iproc_gpio_irq_set_type(struct irq_data *d, unsigned int type) { struct gpio_chip *gc = irq_data_get_irq_chip_data(d); - struct cygnus_gpio *chip = to_cygnus_gpio(gc); + struct iproc_gpio *chip = to_iproc_gpio(gc); unsigned gpio = d->hwirq; bool level_triggered = false; bool dual_edge = false; @@ -263,10 +265,10 @@ static int cygnus_gpio_irq_set_type(struct irq_data *d, unsigned int type) } spin_lock_irqsave(&chip->lock, flags); - cygnus_set_bit(chip, CYGNUS_GPIO_INT_TYPE_OFFSET, gpio, + iproc_set_bit(chip, IPROC_GPIO_INT_TYPE_OFFSET, gpio, level_triggered); - cygnus_set_bit(chip, CYGNUS_GPIO_INT_DE_OFFSET, gpio, dual_edge); - cygnus_set_bit(chip, CYGNUS_GPIO_INT_EDGE_OFFSET, gpio, + iproc_set_bit(chip, IPROC_GPIO_INT_DE_OFFSET, gpio, dual_edge); + iproc_set_bit(chip, IPROC_GPIO_INT_EDGE_OFFSET, gpio, rising_or_high); spin_unlock_irqrestore(&chip->lock, flags); @@ -277,32 +279,32 @@ static int cygnus_gpio_irq_set_type(struct irq_data *d, unsigned int type) return 0; } -static struct irq_chip cygnus_gpio_irq_chip = { - .name = "bcm-cygnus-gpio", - .irq_ack = cygnus_gpio_irq_ack, - .irq_mask = cygnus_gpio_irq_mask, - .irq_unmask = cygnus_gpio_irq_unmask, - .irq_set_type = cygnus_gpio_irq_set_type, +static struct irq_chip iproc_gpio_irq_chip = { + .name = "bcm-iproc-gpio", + .irq_ack = iproc_gpio_irq_ack, + .irq_mask = iproc_gpio_irq_mask, + .irq_unmask = iproc_gpio_irq_unmask, + .irq_set_type = iproc_gpio_irq_set_type, }; /* - * Request the Cygnus IOMUX pinmux controller to mux individual pins to GPIO + * Request the Iproc IOMUX pinmux controller to mux individual pins to GPIO */ -static int cygnus_gpio_request(struct gpio_chip *gc, unsigned offset) +static int iproc_gpio_request(struct gpio_chip *gc, unsigned offset) { - struct cygnus_gpio *chip = to_cygnus_gpio(gc); + struct iproc_gpio *chip = to_iproc_gpio(gc); unsigned gpio = gc->base + offset; - /* not all Cygnus GPIO pins can be muxed individually */ + /* not all Iproc GPIO pins can be muxed individually */ if (!chip->pinmux_is_supported) return 0; return pinctrl_request_gpio(gpio); } -static void cygnus_gpio_free(struct gpio_chip *gc, unsigned offset) +static void iproc_gpio_free(struct gpio_chip *gc, unsigned offset) { - struct cygnus_gpio *chip = to_cygnus_gpio(gc); + struct iproc_gpio *chip = to_iproc_gpio(gc); unsigned gpio = gc->base + offset; if (!chip->pinmux_is_supported) @@ -311,13 +313,13 @@ static void cygnus_gpio_free(struct gpio_chip *gc, unsigned offset) pinctrl_free_gpio(gpio); } -static int cygnus_gpio_direction_input(struct gpio_chip *gc, unsigned gpio) +static int iproc_gpio_direction_input(struct gpio_chip *gc, unsigned gpio) { - struct cygnus_gpio *chip = to_cygnus_gpio(gc); + struct iproc_gpio *chip = to_iproc_gpio(gc); unsigned long flags; spin_lock_irqsave(&chip->lock, flags); - cygnus_set_bit(chip, CYGNUS_GPIO_OUT_EN_OFFSET, gpio, false); + iproc_set_bit(chip, IPROC_GPIO_OUT_EN_OFFSET, gpio, false); spin_unlock_irqrestore(&chip->lock, flags); dev_dbg(chip->dev, "gpio:%u set input\n", gpio); @@ -325,15 +327,15 @@ static int cygnus_gpio_direction_input(struct gpio_chip *gc, unsigned gpio) return 0; } -static int cygnus_gpio_direction_output(struct gpio_chip *gc, unsigned gpio, +static int iproc_gpio_direction_output(struct gpio_chip *gc, unsigned gpio, int val) { - struct cygnus_gpio *chip = to_cygnus_gpio(gc); + struct iproc_gpio *chip = to_iproc_gpio(gc); unsigned long flags; spin_lock_irqsave(&chip->lock, flags); - cygnus_set_bit(chip, CYGNUS_GPIO_OUT_EN_OFFSET, gpio, true); - cygnus_set_bit(chip, CYGNUS_GPIO_DATA_OUT_OFFSET, gpio, !!(val)); + iproc_set_bit(chip, IPROC_GPIO_OUT_EN_OFFSET, gpio, true); + iproc_set_bit(chip, IPROC_GPIO_DATA_OUT_OFFSET, gpio, !!(val)); spin_unlock_irqrestore(&chip->lock, flags); dev_dbg(chip->dev, "gpio:%u set output, value:%d\n", gpio, val); @@ -341,29 +343,29 @@ static int cygnus_gpio_direction_output(struct gpio_chip *gc, unsigned gpio, return 0; } -static void cygnus_gpio_set(struct gpio_chip *gc, unsigned gpio, int val) +static void iproc_gpio_set(struct gpio_chip *gc, unsigned gpio, int val) { - struct cygnus_gpio *chip = to_cygnus_gpio(gc); + struct iproc_gpio *chip = to_iproc_gpio(gc); unsigned long flags; spin_lock_irqsave(&chip->lock, flags); - cygnus_set_bit(chip, CYGNUS_GPIO_DATA_OUT_OFFSET, gpio, !!(val)); + iproc_set_bit(chip, IPROC_GPIO_DATA_OUT_OFFSET, gpio, !!(val)); spin_unlock_irqrestore(&chip->lock, flags); dev_dbg(chip->dev, "gpio:%u set, value:%d\n", gpio, val); } -static int cygnus_gpio_get(struct gpio_chip *gc, unsigned gpio) +static int iproc_gpio_get(struct gpio_chip *gc, unsigned gpio) { - struct cygnus_gpio *chip = to_cygnus_gpio(gc); - unsigned int offset = CYGNUS_GPIO_REG(gpio, - CYGNUS_GPIO_DATA_IN_OFFSET); - unsigned int shift = CYGNUS_GPIO_SHIFT(gpio); + struct iproc_gpio *chip = to_iproc_gpio(gc); + unsigned int offset = IPROC_GPIO_REG(gpio, + IPROC_GPIO_DATA_IN_OFFSET); + unsigned int shift = IPROC_GPIO_SHIFT(gpio); return !!(readl(chip->base + offset) & BIT(shift)); } -static int cygnus_get_groups_count(struct pinctrl_dev *pctldev) +static int iproc_get_groups_count(struct pinctrl_dev *pctldev) { return 1; } @@ -372,20 +374,20 @@ static int cygnus_get_groups_count(struct pinctrl_dev *pctldev) * Only one group: "gpio_grp", since this local pinctrl device only performs * GPIO specific PINCONF configurations */ -static const char *cygnus_get_group_name(struct pinctrl_dev *pctldev, +static const char *iproc_get_group_name(struct pinctrl_dev *pctldev, unsigned selector) { return "gpio_grp"; } -static const struct pinctrl_ops cygnus_pctrl_ops = { - .get_groups_count = cygnus_get_groups_count, - .get_group_name = cygnus_get_group_name, +static const struct pinctrl_ops iproc_pctrl_ops = { + .get_groups_count = iproc_get_groups_count, + .get_group_name = iproc_get_group_name, .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, .dt_free_map = pinctrl_utils_dt_free_map, }; -static int cygnus_gpio_set_pull(struct cygnus_gpio *chip, unsigned gpio, +static int iproc_gpio_set_pull(struct iproc_gpio *chip, unsigned gpio, bool disable, bool pull_up) { unsigned long flags; @@ -393,11 +395,11 @@ static int cygnus_gpio_set_pull(struct cygnus_gpio *chip, unsigned gpio, spin_lock_irqsave(&chip->lock, flags); if (disable) { - cygnus_set_bit(chip, CYGNUS_GPIO_RES_EN_OFFSET, gpio, false); + iproc_set_bit(chip, IPROC_GPIO_RES_EN_OFFSET, gpio, false); } else { - cygnus_set_bit(chip, CYGNUS_GPIO_PAD_RES_OFFSET, gpio, + iproc_set_bit(chip, IPROC_GPIO_PAD_RES_OFFSET, gpio, pull_up); - cygnus_set_bit(chip, CYGNUS_GPIO_RES_EN_OFFSET, gpio, true); + iproc_set_bit(chip, IPROC_GPIO_RES_EN_OFFSET, gpio, true); } spin_unlock_irqrestore(&chip->lock, flags); @@ -407,18 +409,18 @@ static int cygnus_gpio_set_pull(struct cygnus_gpio *chip, unsigned gpio, return 0; } -static void cygnus_gpio_get_pull(struct cygnus_gpio *chip, unsigned gpio, +static void iproc_gpio_get_pull(struct iproc_gpio *chip, unsigned gpio, bool *disable, bool *pull_up) { unsigned long flags; spin_lock_irqsave(&chip->lock, flags); - *disable = !cygnus_get_bit(chip, CYGNUS_GPIO_RES_EN_OFFSET, gpio); - *pull_up = cygnus_get_bit(chip, CYGNUS_GPIO_PAD_RES_OFFSET, gpio); + *disable = !iproc_get_bit(chip, IPROC_GPIO_RES_EN_OFFSET, gpio); + *pull_up = iproc_get_bit(chip, IPROC_GPIO_PAD_RES_OFFSET, gpio); spin_unlock_irqrestore(&chip->lock, flags); } -static int cygnus_gpio_set_strength(struct cygnus_gpio *chip, unsigned gpio, +static int iproc_gpio_set_strength(struct iproc_gpio *chip, unsigned gpio, unsigned strength) { void __iomem *base; @@ -432,14 +434,14 @@ static int cygnus_gpio_set_strength(struct cygnus_gpio *chip, unsigned gpio, if (chip->io_ctrl) { base = chip->io_ctrl; - offset = CYGNUS_GPIO_DRV0_CTRL_OFFSET; + offset = IPROC_GPIO_DRV0_CTRL_OFFSET; } else { base = chip->base; - offset = CYGNUS_GPIO_REG(gpio, - CYGNUS_GPIO_ASIU_DRV0_CTRL_OFFSET); + offset = IPROC_GPIO_REG(gpio, + IPROC_GPIO_ASIU_DRV0_CTRL_OFFSET); } - shift = CYGNUS_GPIO_SHIFT(gpio); + shift = IPROC_GPIO_SHIFT(gpio); dev_dbg(chip->dev, "gpio:%u set drive strength:%d mA\n", gpio, strength); @@ -458,7 +460,7 @@ static int cygnus_gpio_set_strength(struct cygnus_gpio *chip, unsigned gpio, return 0; } -static int cygnus_gpio_get_strength(struct cygnus_gpio *chip, unsigned gpio, +static int iproc_gpio_get_strength(struct iproc_gpio *chip, unsigned gpio, u16 *strength) { void __iomem *base; @@ -468,14 +470,14 @@ static int cygnus_gpio_get_strength(struct cygnus_gpio *chip, unsigned gpio, if (chip->io_ctrl) { base = chip->io_ctrl; - offset = CYGNUS_GPIO_DRV0_CTRL_OFFSET; + offset = IPROC_GPIO_DRV0_CTRL_OFFSET; } else { base = chip->base; - offset = CYGNUS_GPIO_REG(gpio, - CYGNUS_GPIO_ASIU_DRV0_CTRL_OFFSET); + offset = IPROC_GPIO_REG(gpio, + IPROC_GPIO_ASIU_DRV0_CTRL_OFFSET); } - shift = CYGNUS_GPIO_SHIFT(gpio); + shift = IPROC_GPIO_SHIFT(gpio); spin_lock_irqsave(&chip->lock, flags); *strength = 0; @@ -493,40 +495,40 @@ static int cygnus_gpio_get_strength(struct cygnus_gpio *chip, unsigned gpio, return 0; } -static int cygnus_pin_config_get(struct pinctrl_dev *pctldev, unsigned pin, +static int iproc_pin_config_get(struct pinctrl_dev *pctldev, unsigned pin, unsigned long *config) { - struct cygnus_gpio *chip = pinctrl_dev_get_drvdata(pctldev); + struct iproc_gpio *chip = pinctrl_dev_get_drvdata(pctldev); enum pin_config_param param = pinconf_to_config_param(*config); - unsigned gpio = cygnus_pin_to_gpio(pin); + unsigned gpio = iproc_pin_to_gpio(pin); u16 arg; bool disable, pull_up; int ret; switch (param) { case PIN_CONFIG_BIAS_DISABLE: - cygnus_gpio_get_pull(chip, gpio, &disable, &pull_up); + iproc_gpio_get_pull(chip, gpio, &disable, &pull_up); if (disable) return 0; else return -EINVAL; case PIN_CONFIG_BIAS_PULL_UP: - cygnus_gpio_get_pull(chip, gpio, &disable, &pull_up); + iproc_gpio_get_pull(chip, gpio, &disable, &pull_up); if (!disable && pull_up) return 0; else return -EINVAL; case PIN_CONFIG_BIAS_PULL_DOWN: - cygnus_gpio_get_pull(chip, gpio, &disable, &pull_up); + iproc_gpio_get_pull(chip, gpio, &disable, &pull_up); if (!disable && !pull_up) return 0; else return -EINVAL; case PIN_CONFIG_DRIVE_STRENGTH: - ret = cygnus_gpio_get_strength(chip, gpio, &arg); + ret = iproc_gpio_get_strength(chip, gpio, &arg); if (ret) return ret; else @@ -541,13 +543,13 @@ static int cygnus_pin_config_get(struct pinctrl_dev *pctldev, unsigned pin, return -ENOTSUPP; } -static int cygnus_pin_config_set(struct pinctrl_dev *pctldev, unsigned pin, +static int iproc_pin_config_set(struct pinctrl_dev *pctldev, unsigned pin, unsigned long *configs, unsigned num_configs) { - struct cygnus_gpio *chip = pinctrl_dev_get_drvdata(pctldev); + struct iproc_gpio *chip = pinctrl_dev_get_drvdata(pctldev); enum pin_config_param param; u16 arg; - unsigned i, gpio = cygnus_pin_to_gpio(pin); + unsigned i, gpio = iproc_pin_to_gpio(pin); int ret = -ENOTSUPP; for (i = 0; i < num_configs; i++) { @@ -556,25 +558,25 @@ static int cygnus_pin_config_set(struct pinctrl_dev *pctldev, unsigned pin, switch (param) { case PIN_CONFIG_BIAS_DISABLE: - ret = cygnus_gpio_set_pull(chip, gpio, true, false); + ret = iproc_gpio_set_pull(chip, gpio, true, false); if (ret < 0) goto out; break; case PIN_CONFIG_BIAS_PULL_UP: - ret = cygnus_gpio_set_pull(chip, gpio, false, true); + ret = iproc_gpio_set_pull(chip, gpio, false, true); if (ret < 0) goto out; break; case PIN_CONFIG_BIAS_PULL_DOWN: - ret = cygnus_gpio_set_pull(chip, gpio, false, false); + ret = iproc_gpio_set_pull(chip, gpio, false, false); if (ret < 0) goto out; break; case PIN_CONFIG_DRIVE_STRENGTH: - ret = cygnus_gpio_set_strength(chip, gpio, arg); + ret = iproc_gpio_set_strength(chip, gpio, arg); if (ret < 0) goto out; break; @@ -589,20 +591,20 @@ out: return ret; } -static const struct pinconf_ops cygnus_pconf_ops = { +static const struct pinconf_ops iproc_pconf_ops = { .is_generic = true, - .pin_config_get = cygnus_pin_config_get, - .pin_config_set = cygnus_pin_config_set, + .pin_config_get = iproc_pin_config_get, + .pin_config_set = iproc_pin_config_set, }; /* - * Cygnus GPIO controller supports some PINCONF related configurations such as + * Iproc GPIO controller supports some PINCONF related configurations such as * pull up, pull down, and drive strength, when the pin is configured to GPIO * * Here a local pinctrl device is created with simple 1-to-1 pin mapping to the * local GPIO pins */ -static int cygnus_gpio_register_pinconf(struct cygnus_gpio *chip) +static int iproc_gpio_register_pinconf(struct iproc_gpio *chip) { struct pinctrl_desc *pctldesc = &chip->pctldesc; struct pinctrl_pin_desc *pins; @@ -622,10 +624,10 @@ static int cygnus_gpio_register_pinconf(struct cygnus_gpio *chip) } pctldesc->name = dev_name(chip->dev); - pctldesc->pctlops = &cygnus_pctrl_ops; + pctldesc->pctlops = &iproc_pctrl_ops; pctldesc->pins = pins; pctldesc->npins = gc->ngpio; - pctldesc->confops = &cygnus_pconf_ops; + pctldesc->confops = &iproc_pconf_ops; chip->pctl = pinctrl_register(pctldesc, chip->dev, chip); if (IS_ERR(chip->pctl)) { @@ -636,12 +638,12 @@ static int cygnus_gpio_register_pinconf(struct cygnus_gpio *chip) return 0; } -static void cygnus_gpio_unregister_pinconf(struct cygnus_gpio *chip) +static void iproc_gpio_unregister_pinconf(struct cygnus_gpio *chip) { pinctrl_unregister(chip->pctl); } -static const struct of_device_id cygnus_gpio_of_match[] = { +static const struct of_device_id iproc_gpio_of_match[] = { { .compatible = "brcm,cygnus-ccm-gpio" }, { .compatible = "brcm,cygnus-asiu-gpio" }, { .compatible = "brcm,cygnus-crmu-gpio" }, @@ -649,11 +651,11 @@ static const struct of_device_id cygnus_gpio_of_match[] = { { } }; -static int cygnus_gpio_probe(struct platform_device *pdev) +static int iproc_gpio_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; struct resource *res; - struct cygnus_gpio *chip; + struct iproc_gpio *chip; struct gpio_chip *gc; u32 ngpios; int irq, ret; @@ -695,12 +697,12 @@ static int cygnus_gpio_probe(struct platform_device *pdev) gc->label = dev_name(dev); gc->dev = dev; gc->of_node = dev->of_node; - gc->request = cygnus_gpio_request; - gc->free = cygnus_gpio_free; - gc->direction_input = cygnus_gpio_direction_input; - gc->direction_output = cygnus_gpio_direction_output; - gc->set = cygnus_gpio_set; - gc->get = cygnus_gpio_get; + gc->request = iproc_gpio_request; + gc->free = iproc_gpio_free; + gc->direction_input = iproc_gpio_direction_input; + gc->direction_output = iproc_gpio_direction_output; + gc->set = iproc_gpio_set; + gc->get = iproc_gpio_get; chip->pinmux_is_supported = of_property_read_bool(dev->of_node, "gpio-ranges"); @@ -711,7 +713,7 @@ static int cygnus_gpio_probe(struct platform_device *pdev) return ret; } - ret = cygnus_gpio_register_pinconf(chip); + ret = iproc_gpio_register_pinconf(chip); if (ret) { dev_err(dev, "unable to register pinconf\n"); goto err_rm_gpiochip; @@ -720,21 +722,21 @@ static int cygnus_gpio_probe(struct platform_device *pdev) /* optional GPIO interrupt support */ irq = platform_get_irq(pdev, 0); if (irq) { - ret = gpiochip_irqchip_add(gc, &cygnus_gpio_irq_chip, 0, + ret = gpiochip_irqchip_add(gc, &iproc_gpio_irq_chip, 0, handle_simple_irq, IRQ_TYPE_NONE); if (ret) { dev_err(dev, "no GPIO irqchip\n"); goto err_unregister_pinconf; } - gpiochip_set_chained_irqchip(gc, &cygnus_gpio_irq_chip, irq, - cygnus_gpio_irq_handler); + gpiochip_set_chained_irqchip(gc, &iproc_gpio_irq_chip, irq, + iproc_gpio_irq_handler); } return 0; err_unregister_pinconf: - cygnus_gpio_unregister_pinconf(chip); + iproc_gpio_unregister_pinconf(chip); err_rm_gpiochip: gpiochip_remove(gc); @@ -742,16 +744,16 @@ err_rm_gpiochip: return ret; } -static struct platform_driver cygnus_gpio_driver = { +static struct platform_driver iproc_gpio_driver = { .driver = { - .name = "cygnus-gpio", - .of_match_table = cygnus_gpio_of_match, + .name = "iproc-gpio", + .of_match_table = iproc_gpio_of_match, }, - .probe = cygnus_gpio_probe, + .probe = iproc_gpio_probe, }; -static int __init cygnus_gpio_init(void) +static int __init iproc_gpio_init(void) { - return platform_driver_probe(&cygnus_gpio_driver, cygnus_gpio_probe); + return platform_driver_probe(&iproc_gpio_driver, iproc_gpio_probe); } -arch_initcall_sync(cygnus_gpio_init); +arch_initcall_sync(iproc_gpio_init); -- cgit v0.10.2 From 604b25793b85a5ca2fc949b9b7202bb8a83ccb95 Mon Sep 17 00:00:00 2001 From: Pramod Kumar Date: Thu, 19 Nov 2015 09:22:18 +0530 Subject: Documentation: Rename gpio controller name from cygnus to iproc Renamed gpio controller's driver name from cygnus to iproc to make it more generic so that all iProc based SoCs having the same gpio controller could use this. Signed-off-by: Pramod Kumar Reviewed-by: Ray Jui Reviewed-by: Scott Branden Acked-by: Rob Herring Signed-off-by: Linus Walleij diff --git a/Documentation/devicetree/bindings/pinctrl/brcm,cygnus-gpio.txt b/Documentation/devicetree/bindings/pinctrl/brcm,cygnus-gpio.txt deleted file mode 100644 index 8b1e5d1..0000000 --- a/Documentation/devicetree/bindings/pinctrl/brcm,cygnus-gpio.txt +++ /dev/null @@ -1,109 +0,0 @@ -Broadcom Cygnus GPIO/PINCONF Controller - -Required properties: - -- compatible: - Must be "brcm,cygnus-ccm-gpio", "brcm,cygnus-asiu-gpio", - "brcm,cygnus-crmu-gpio" or "brcm,iproc-gpio" - -- reg: - Define the base and range of the I/O address space that contains the Cygnus -GPIO/PINCONF controller registers - -- ngpios: - Total number of in-use slots in GPIO controller - -- #gpio-cells: - Must be two. The first cell is the GPIO pin number (within the -controller's pin space) and the second cell is used for the following: - bit[0]: polarity (0 for active high and 1 for active low) - -- gpio-controller: - Specifies that the node is a GPIO controller - -Optional properties: - -- interrupts: - Interrupt ID - -- interrupt-controller: - Specifies that the node is an interrupt controller - -- gpio-ranges: - Specifies the mapping between gpio controller and pin-controllers pins. - This requires 4 fields in cells defined as - - 1. Phandle of pin-controller. - 2. GPIO base pin offset. - 3 Pin-control base pin offset. - 4. number of gpio pins which are linearly mapped from pin base. - -Supported generic PINCONF properties in child nodes: - -- pins: - The list of pins (within the controller's own pin space) that properties -in the node apply to. Pin names are "gpio-" - -- bias-disable: - Disable pin bias - -- bias-pull-up: - Enable internal pull up resistor - -- bias-pull-down: - Enable internal pull down resistor - -- drive-strength: - Valid drive strength values include 2, 4, 6, 8, 10, 12, 14, 16 (mA) - -Example: - gpio_ccm: gpio@1800a000 { - compatible = "brcm,cygnus-ccm-gpio"; - reg = <0x1800a000 0x50>, - <0x0301d164 0x20>; - ngpios = <24>; - #gpio-cells = <2>; - gpio-controller; - interrupts = ; - interrupt-controller; - - touch_pins: touch_pins { - pwr: pwr { - pins = "gpio-0"; - drive-strength = <16>; - }; - - event: event { - pins = "gpio-1"; - bias-pull-up; - }; - }; - }; - - gpio_asiu: gpio@180a5000 { - compatible = "brcm,cygnus-asiu-gpio"; - reg = <0x180a5000 0x668>; - ngpios = <146>; - #gpio-cells = <2>; - gpio-controller; - interrupts = ; - interrupt-controller; - gpio-ranges = <&pinctrl 0 42 1>, - <&pinctrl 1 44 3>; - }; - - /* - * Touchscreen that uses the CCM GPIO 0 and 1 - */ - tsc { - ... - ... - gpio-pwr = <&gpio_ccm 0 0>; - gpio-event = <&gpio_ccm 1 0>; - }; - - /* Bluetooth that uses the ASIU GPIO 5, with polarity inverted */ - bluetooth { - ... - ... - bcm,rfkill-bank-sel = <&gpio_asiu 5 1> - } diff --git a/Documentation/devicetree/bindings/pinctrl/brcm,iproc-gpio.txt b/Documentation/devicetree/bindings/pinctrl/brcm,iproc-gpio.txt new file mode 100644 index 0000000..e427792 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/brcm,iproc-gpio.txt @@ -0,0 +1,109 @@ +Broadcom iProc GPIO/PINCONF Controller + +Required properties: + +- compatible: + Must be "brcm,cygnus-ccm-gpio", "brcm,cygnus-asiu-gpio", + "brcm,cygnus-crmu-gpio" or "brcm,iproc-gpio" + +- reg: + Define the base and range of the I/O address space that contains SoC +GPIO/PINCONF controller registers + +- ngpios: + Total number of in-use slots in GPIO controller + +- #gpio-cells: + Must be two. The first cell is the GPIO pin number (within the +controller's pin space) and the second cell is used for the following: + bit[0]: polarity (0 for active high and 1 for active low) + +- gpio-controller: + Specifies that the node is a GPIO controller + +Optional properties: + +- interrupts: + Interrupt ID + +- interrupt-controller: + Specifies that the node is an interrupt controller + +- gpio-ranges: + Specifies the mapping between gpio controller and pin-controllers pins. + This requires 4 fields in cells defined as - + 1. Phandle of pin-controller. + 2. GPIO base pin offset. + 3 Pin-control base pin offset. + 4. number of gpio pins which are linearly mapped from pin base. + +Supported generic PINCONF properties in child nodes: + +- pins: + The list of pins (within the controller's own pin space) that properties +in the node apply to. Pin names are "gpio-" + +- bias-disable: + Disable pin bias + +- bias-pull-up: + Enable internal pull up resistor + +- bias-pull-down: + Enable internal pull down resistor + +- drive-strength: + Valid drive strength values include 2, 4, 6, 8, 10, 12, 14, 16 (mA) + +Example: + gpio_ccm: gpio@1800a000 { + compatible = "brcm,cygnus-ccm-gpio"; + reg = <0x1800a000 0x50>, + <0x0301d164 0x20>; + ngpios = <24>; + #gpio-cells = <2>; + gpio-controller; + interrupts = ; + interrupt-controller; + + touch_pins: touch_pins { + pwr: pwr { + pins = "gpio-0"; + drive-strength = <16>; + }; + + event: event { + pins = "gpio-1"; + bias-pull-up; + }; + }; + }; + + gpio_asiu: gpio@180a5000 { + compatible = "brcm,cygnus-asiu-gpio"; + reg = <0x180a5000 0x668>; + ngpios = <146>; + #gpio-cells = <2>; + gpio-controller; + interrupts = ; + interrupt-controller; + gpio-ranges = <&pinctrl 0 42 1>, + <&pinctrl 1 44 3>; + }; + + /* + * Touchscreen that uses the CCM GPIO 0 and 1 + */ + tsc { + ... + ... + gpio-pwr = <&gpio_ccm 0 0>; + gpio-event = <&gpio_ccm 1 0>; + }; + + /* Bluetooth that uses the ASIU GPIO 5, with polarity inverted */ + bluetooth { + ... + ... + bcm,rfkill-bank-sel = <&gpio_asiu 5 1> + } -- cgit v0.10.2 From 616043d58a89c0966e479a83f64ba8c0ab3e657e Mon Sep 17 00:00:00 2001 From: Pramod Kumar Date: Thu, 19 Nov 2015 09:22:19 +0530 Subject: pinctrl: Rename gpio driver from cygnus to iproc Rename gpio driver file name from pinctrl-cygnus-gpio.c to pinctrl-iproc-gpio.c to make it more generic so that all iproc based future SoCs using the same gpio block could use this driver. Signed-off-by: Pramod Kumar Reviewed-by: Ray Jui Reviewed-by: Scott Branden Acked-by: Rob Herring Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/bcm/Kconfig b/drivers/pinctrl/bcm/Kconfig index cd11d4d..5949547 100644 --- a/drivers/pinctrl/bcm/Kconfig +++ b/drivers/pinctrl/bcm/Kconfig @@ -20,27 +20,41 @@ config PINCTRL_BCM2835 select PINMUX select PINCONF -config PINCTRL_CYGNUS_GPIO - bool "Broadcom Cygnus GPIO (with PINCONF) driver" - depends on OF_GPIO && ARCH_BCM_CYGNUS +config PINCTRL_IPROC_GPIO + bool "Broadcom iProc GPIO (with PINCONF) driver" + depends on OF_GPIO && (ARCH_BCM_IPROC || COMPILE_TEST) select GPIOLIB_IRQCHIP select PINCONF select GENERIC_PINCONF - default ARCH_BCM_CYGNUS + default ARCH_BCM_IPROC help - Say yes here to enable the Broadcom Cygnus GPIO driver. + Say yes here to enable the Broadcom iProc GPIO driver. + + The Broadcom iProc based SoCs- Cygnus, NS2, NSP and Stingray, use + same GPIO Controller IP hence this driver could be used for all. The Broadcom Cygnus SoC has 3 GPIO controllers including the ASIU GPIO controller (ASIU), the chipCommonG GPIO controller (CCM), and the always-ON GPIO controller (CRMU/AON). All 3 GPIO controllers are supported by this driver. - All 3 Cygnus GPIO controllers support basic PINCONF functions such + The Broadcom NSP has two GPIO controllers including the ChipcommonA + GPIO, the ChipcommonB GPIO. Later controller is supported by this + driver. + + The Broadcom NS2 has two GPIO controller including the CRMU GPIO, + the ChipcommonG GPIO. Both controllers are supported by this driver. + + The Broadcom Stingray GPIO controllers are supported by this driver. + + All above SoCs GPIO controllers support basic PINCONF functions such as bias pull up, pull down, and drive strength configurations, when these pins are muxed to GPIO. - Pins from the ASIU GPIO can be individually muxed to GPIO function, - through interaction with the Cygnus IOMUX controller. + It provides the framework where pins from the individual GPIO can be + individually muxed to GPIO function, through interaction with the + SoCs IOMUX controller. This features could be used only on SoCs which + support individual pin muxing. config PINCTRL_CYGNUS_MUX bool "Broadcom Cygnus IOMUX driver" diff --git a/drivers/pinctrl/bcm/Makefile b/drivers/pinctrl/bcm/Makefile index 2b2f70e..9ac6370 100644 --- a/drivers/pinctrl/bcm/Makefile +++ b/drivers/pinctrl/bcm/Makefile @@ -2,5 +2,5 @@ obj-$(CONFIG_PINCTRL_BCM281XX) += pinctrl-bcm281xx.o obj-$(CONFIG_PINCTRL_BCM2835) += pinctrl-bcm2835.o -obj-$(CONFIG_PINCTRL_CYGNUS_GPIO) += pinctrl-cygnus-gpio.o +obj-$(CONFIG_PINCTRL_IPROC_GPIO) += pinctrl-iproc-gpio.o obj-$(CONFIG_PINCTRL_CYGNUS_MUX) += pinctrl-cygnus-mux.o diff --git a/drivers/pinctrl/bcm/pinctrl-cygnus-gpio.c b/drivers/pinctrl/bcm/pinctrl-cygnus-gpio.c deleted file mode 100644 index fa66c3e..0000000 --- a/drivers/pinctrl/bcm/pinctrl-cygnus-gpio.c +++ /dev/null @@ -1,759 +0,0 @@ -/* - * Copyright (C) 2014-2015 Broadcom Corporation - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation version 2. - * - * This program is distributed "as is" WITHOUT ANY WARRANTY of any - * kind, whether express or implied; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * This file contains the Broadcom Iproc GPIO driver that supports 3 - * GPIO controllers on Iproc including the ASIU GPIO controller, the - * chipCommonG GPIO controller, and the always-on GPIO controller. Basic - * PINCONF such as bias pull up/down, and drive strength are also supported - * in this driver. - * - * It provides the functionality where pins from the GPIO can be - * individually muxed to GPIO function, if individual pad - * configuration is supported, through the interaction with respective - * SoCs IOMUX controller. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "../pinctrl-utils.h" - -#define IPROC_GPIO_DATA_IN_OFFSET 0x00 -#define IPROC_GPIO_DATA_OUT_OFFSET 0x04 -#define IPROC_GPIO_OUT_EN_OFFSET 0x08 -#define IPROC_GPIO_INT_TYPE_OFFSET 0x0c -#define IPROC_GPIO_INT_DE_OFFSET 0x10 -#define IPROC_GPIO_INT_EDGE_OFFSET 0x14 -#define IPROC_GPIO_INT_MSK_OFFSET 0x18 -#define IPROC_GPIO_INT_STAT_OFFSET 0x1c -#define IPROC_GPIO_INT_MSTAT_OFFSET 0x20 -#define IPROC_GPIO_INT_CLR_OFFSET 0x24 -#define IPROC_GPIO_PAD_RES_OFFSET 0x34 -#define IPROC_GPIO_RES_EN_OFFSET 0x38 - -/* drive strength control for ASIU GPIO */ -#define IPROC_GPIO_ASIU_DRV0_CTRL_OFFSET 0x58 - -/* drive strength control for CCM/CRMU (AON) GPIO */ -#define IPROC_GPIO_DRV0_CTRL_OFFSET 0x00 - -#define GPIO_BANK_SIZE 0x200 -#define NGPIOS_PER_BANK 32 -#define GPIO_BANK(pin) ((pin) / NGPIOS_PER_BANK) - -#define IPROC_GPIO_REG(pin, reg) (GPIO_BANK(pin) * GPIO_BANK_SIZE + (reg)) -#define IPROC_GPIO_SHIFT(pin) ((pin) % NGPIOS_PER_BANK) - -#define GPIO_DRV_STRENGTH_BIT_SHIFT 20 -#define GPIO_DRV_STRENGTH_BITS 3 -#define GPIO_DRV_STRENGTH_BIT_MASK ((1 << GPIO_DRV_STRENGTH_BITS) - 1) - -/* - * Iproc GPIO core - * - * @dev: pointer to device - * @base: I/O register base for Iproc GPIO controller - * @io_ctrl: I/O register base for certain type of Iproc GPIO controller that - * has the PINCONF support implemented outside of the GPIO block - * @lock: lock to protect access to I/O registers - * @gc: GPIO chip - * @num_banks: number of GPIO banks, each bank supports up to 32 GPIOs - * @pinmux_is_supported: flag to indicate this GPIO controller contains pins - * that can be individually muxed to GPIO - * @pctl: pointer to pinctrl_dev - * @pctldesc: pinctrl descriptor - */ -struct iproc_gpio { - struct device *dev; - - void __iomem *base; - void __iomem *io_ctrl; - - spinlock_t lock; - - struct gpio_chip gc; - unsigned num_banks; - - bool pinmux_is_supported; - - struct pinctrl_dev *pctl; - struct pinctrl_desc pctldesc; -}; - -static inline struct iproc_gpio *to_iproc_gpio(struct gpio_chip *gc) -{ - return container_of(gc, struct iproc_gpio, gc); -} - -/* - * Mapping from PINCONF pins to GPIO pins is 1-to-1 - */ -static inline unsigned iproc_pin_to_gpio(unsigned pin) -{ - return pin; -} - -/** - * iproc_set_bit - set or clear one bit (corresponding to the GPIO pin) in a - * Iproc GPIO register - * - * @iproc_gpio: Iproc GPIO device - * @reg: register offset - * @gpio: GPIO pin - * @set: set or clear - */ -static inline void iproc_set_bit(struct iproc_gpio *chip, unsigned int reg, - unsigned gpio, bool set) -{ - unsigned int offset = IPROC_GPIO_REG(gpio, reg); - unsigned int shift = IPROC_GPIO_SHIFT(gpio); - u32 val; - - val = readl(chip->base + offset); - if (set) - val |= BIT(shift); - else - val &= ~BIT(shift); - writel(val, chip->base + offset); -} - -static inline bool iproc_get_bit(struct iproc_gpio *chip, unsigned int reg, - unsigned gpio) -{ - unsigned int offset = IPROC_GPIO_REG(gpio, reg); - unsigned int shift = IPROC_GPIO_SHIFT(gpio); - - return !!(readl(chip->base + offset) & BIT(shift)); -} - -static void iproc_gpio_irq_handler(struct irq_desc *desc) -{ - struct gpio_chip *gc = irq_desc_get_handler_data(desc); - struct iproc_gpio *chip = to_iproc_gpio(gc); - struct irq_chip *irq_chip = irq_desc_get_chip(desc); - int i, bit; - - chained_irq_enter(irq_chip, desc); - - /* go through the entire GPIO banks and handle all interrupts */ - for (i = 0; i < chip->num_banks; i++) { - unsigned long val = readl(chip->base + (i * GPIO_BANK_SIZE) + - IPROC_GPIO_INT_MSTAT_OFFSET); - - for_each_set_bit(bit, &val, NGPIOS_PER_BANK) { - unsigned pin = NGPIOS_PER_BANK * i + bit; - int child_irq = irq_find_mapping(gc->irqdomain, pin); - - /* - * Clear the interrupt before invoking the - * handler, so we do not leave any window - */ - writel(BIT(bit), chip->base + (i * GPIO_BANK_SIZE) + - IPROC_GPIO_INT_CLR_OFFSET); - - generic_handle_irq(child_irq); - } - } - - chained_irq_exit(irq_chip, desc); -} - - -static void iproc_gpio_irq_ack(struct irq_data *d) -{ - struct gpio_chip *gc = irq_data_get_irq_chip_data(d); - struct iproc_gpio *chip = to_iproc_gpio(gc); - unsigned gpio = d->hwirq; - unsigned int offset = IPROC_GPIO_REG(gpio, - IPROC_GPIO_INT_CLR_OFFSET); - unsigned int shift = IPROC_GPIO_SHIFT(gpio); - u32 val = BIT(shift); - - writel(val, chip->base + offset); -} - -/** - * iproc_gpio_irq_set_mask - mask/unmask a GPIO interrupt - * - * @d: IRQ chip data - * @unmask: mask/unmask GPIO interrupt - */ -static void iproc_gpio_irq_set_mask(struct irq_data *d, bool unmask) -{ - struct gpio_chip *gc = irq_data_get_irq_chip_data(d); - struct iproc_gpio *chip = to_iproc_gpio(gc); - unsigned gpio = d->hwirq; - - iproc_set_bit(chip, IPROC_GPIO_INT_MSK_OFFSET, gpio, unmask); -} - -static void iproc_gpio_irq_mask(struct irq_data *d) -{ - struct gpio_chip *gc = irq_data_get_irq_chip_data(d); - struct iproc_gpio *chip = to_iproc_gpio(gc); - unsigned long flags; - - spin_lock_irqsave(&chip->lock, flags); - iproc_gpio_irq_set_mask(d, false); - spin_unlock_irqrestore(&chip->lock, flags); -} - -static void iproc_gpio_irq_unmask(struct irq_data *d) -{ - struct gpio_chip *gc = irq_data_get_irq_chip_data(d); - struct iproc_gpio *chip = to_iproc_gpio(gc); - unsigned long flags; - - spin_lock_irqsave(&chip->lock, flags); - iproc_gpio_irq_set_mask(d, true); - spin_unlock_irqrestore(&chip->lock, flags); -} - -static int iproc_gpio_irq_set_type(struct irq_data *d, unsigned int type) -{ - struct gpio_chip *gc = irq_data_get_irq_chip_data(d); - struct iproc_gpio *chip = to_iproc_gpio(gc); - unsigned gpio = d->hwirq; - bool level_triggered = false; - bool dual_edge = false; - bool rising_or_high = false; - unsigned long flags; - - switch (type & IRQ_TYPE_SENSE_MASK) { - case IRQ_TYPE_EDGE_RISING: - rising_or_high = true; - break; - - case IRQ_TYPE_EDGE_FALLING: - break; - - case IRQ_TYPE_EDGE_BOTH: - dual_edge = true; - break; - - case IRQ_TYPE_LEVEL_HIGH: - level_triggered = true; - rising_or_high = true; - break; - - case IRQ_TYPE_LEVEL_LOW: - level_triggered = true; - break; - - default: - dev_err(chip->dev, "invalid GPIO IRQ type 0x%x\n", - type); - return -EINVAL; - } - - spin_lock_irqsave(&chip->lock, flags); - iproc_set_bit(chip, IPROC_GPIO_INT_TYPE_OFFSET, gpio, - level_triggered); - iproc_set_bit(chip, IPROC_GPIO_INT_DE_OFFSET, gpio, dual_edge); - iproc_set_bit(chip, IPROC_GPIO_INT_EDGE_OFFSET, gpio, - rising_or_high); - spin_unlock_irqrestore(&chip->lock, flags); - - dev_dbg(chip->dev, - "gpio:%u level_triggered:%d dual_edge:%d rising_or_high:%d\n", - gpio, level_triggered, dual_edge, rising_or_high); - - return 0; -} - -static struct irq_chip iproc_gpio_irq_chip = { - .name = "bcm-iproc-gpio", - .irq_ack = iproc_gpio_irq_ack, - .irq_mask = iproc_gpio_irq_mask, - .irq_unmask = iproc_gpio_irq_unmask, - .irq_set_type = iproc_gpio_irq_set_type, -}; - -/* - * Request the Iproc IOMUX pinmux controller to mux individual pins to GPIO - */ -static int iproc_gpio_request(struct gpio_chip *gc, unsigned offset) -{ - struct iproc_gpio *chip = to_iproc_gpio(gc); - unsigned gpio = gc->base + offset; - - /* not all Iproc GPIO pins can be muxed individually */ - if (!chip->pinmux_is_supported) - return 0; - - return pinctrl_request_gpio(gpio); -} - -static void iproc_gpio_free(struct gpio_chip *gc, unsigned offset) -{ - struct iproc_gpio *chip = to_iproc_gpio(gc); - unsigned gpio = gc->base + offset; - - if (!chip->pinmux_is_supported) - return; - - pinctrl_free_gpio(gpio); -} - -static int iproc_gpio_direction_input(struct gpio_chip *gc, unsigned gpio) -{ - struct iproc_gpio *chip = to_iproc_gpio(gc); - unsigned long flags; - - spin_lock_irqsave(&chip->lock, flags); - iproc_set_bit(chip, IPROC_GPIO_OUT_EN_OFFSET, gpio, false); - spin_unlock_irqrestore(&chip->lock, flags); - - dev_dbg(chip->dev, "gpio:%u set input\n", gpio); - - return 0; -} - -static int iproc_gpio_direction_output(struct gpio_chip *gc, unsigned gpio, - int val) -{ - struct iproc_gpio *chip = to_iproc_gpio(gc); - unsigned long flags; - - spin_lock_irqsave(&chip->lock, flags); - iproc_set_bit(chip, IPROC_GPIO_OUT_EN_OFFSET, gpio, true); - iproc_set_bit(chip, IPROC_GPIO_DATA_OUT_OFFSET, gpio, !!(val)); - spin_unlock_irqrestore(&chip->lock, flags); - - dev_dbg(chip->dev, "gpio:%u set output, value:%d\n", gpio, val); - - return 0; -} - -static void iproc_gpio_set(struct gpio_chip *gc, unsigned gpio, int val) -{ - struct iproc_gpio *chip = to_iproc_gpio(gc); - unsigned long flags; - - spin_lock_irqsave(&chip->lock, flags); - iproc_set_bit(chip, IPROC_GPIO_DATA_OUT_OFFSET, gpio, !!(val)); - spin_unlock_irqrestore(&chip->lock, flags); - - dev_dbg(chip->dev, "gpio:%u set, value:%d\n", gpio, val); -} - -static int iproc_gpio_get(struct gpio_chip *gc, unsigned gpio) -{ - struct iproc_gpio *chip = to_iproc_gpio(gc); - unsigned int offset = IPROC_GPIO_REG(gpio, - IPROC_GPIO_DATA_IN_OFFSET); - unsigned int shift = IPROC_GPIO_SHIFT(gpio); - - return !!(readl(chip->base + offset) & BIT(shift)); -} - -static int iproc_get_groups_count(struct pinctrl_dev *pctldev) -{ - return 1; -} - -/* - * Only one group: "gpio_grp", since this local pinctrl device only performs - * GPIO specific PINCONF configurations - */ -static const char *iproc_get_group_name(struct pinctrl_dev *pctldev, - unsigned selector) -{ - return "gpio_grp"; -} - -static const struct pinctrl_ops iproc_pctrl_ops = { - .get_groups_count = iproc_get_groups_count, - .get_group_name = iproc_get_group_name, - .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, - .dt_free_map = pinctrl_utils_dt_free_map, -}; - -static int iproc_gpio_set_pull(struct iproc_gpio *chip, unsigned gpio, - bool disable, bool pull_up) -{ - unsigned long flags; - - spin_lock_irqsave(&chip->lock, flags); - - if (disable) { - iproc_set_bit(chip, IPROC_GPIO_RES_EN_OFFSET, gpio, false); - } else { - iproc_set_bit(chip, IPROC_GPIO_PAD_RES_OFFSET, gpio, - pull_up); - iproc_set_bit(chip, IPROC_GPIO_RES_EN_OFFSET, gpio, true); - } - - spin_unlock_irqrestore(&chip->lock, flags); - - dev_dbg(chip->dev, "gpio:%u set pullup:%d\n", gpio, pull_up); - - return 0; -} - -static void iproc_gpio_get_pull(struct iproc_gpio *chip, unsigned gpio, - bool *disable, bool *pull_up) -{ - unsigned long flags; - - spin_lock_irqsave(&chip->lock, flags); - *disable = !iproc_get_bit(chip, IPROC_GPIO_RES_EN_OFFSET, gpio); - *pull_up = iproc_get_bit(chip, IPROC_GPIO_PAD_RES_OFFSET, gpio); - spin_unlock_irqrestore(&chip->lock, flags); -} - -static int iproc_gpio_set_strength(struct iproc_gpio *chip, unsigned gpio, - unsigned strength) -{ - void __iomem *base; - unsigned int i, offset, shift; - u32 val; - unsigned long flags; - - /* make sure drive strength is supported */ - if (strength < 2 || strength > 16 || (strength % 2)) - return -ENOTSUPP; - - if (chip->io_ctrl) { - base = chip->io_ctrl; - offset = IPROC_GPIO_DRV0_CTRL_OFFSET; - } else { - base = chip->base; - offset = IPROC_GPIO_REG(gpio, - IPROC_GPIO_ASIU_DRV0_CTRL_OFFSET); - } - - shift = IPROC_GPIO_SHIFT(gpio); - - dev_dbg(chip->dev, "gpio:%u set drive strength:%d mA\n", gpio, - strength); - - spin_lock_irqsave(&chip->lock, flags); - strength = (strength / 2) - 1; - for (i = 0; i < GPIO_DRV_STRENGTH_BITS; i++) { - val = readl(base + offset); - val &= ~BIT(shift); - val |= ((strength >> i) & 0x1) << shift; - writel(val, base + offset); - offset += 4; - } - spin_unlock_irqrestore(&chip->lock, flags); - - return 0; -} - -static int iproc_gpio_get_strength(struct iproc_gpio *chip, unsigned gpio, - u16 *strength) -{ - void __iomem *base; - unsigned int i, offset, shift; - u32 val; - unsigned long flags; - - if (chip->io_ctrl) { - base = chip->io_ctrl; - offset = IPROC_GPIO_DRV0_CTRL_OFFSET; - } else { - base = chip->base; - offset = IPROC_GPIO_REG(gpio, - IPROC_GPIO_ASIU_DRV0_CTRL_OFFSET); - } - - shift = IPROC_GPIO_SHIFT(gpio); - - spin_lock_irqsave(&chip->lock, flags); - *strength = 0; - for (i = 0; i < GPIO_DRV_STRENGTH_BITS; i++) { - val = readl(base + offset) & BIT(shift); - val >>= shift; - *strength += (val << i); - offset += 4; - } - - /* convert to mA */ - *strength = (*strength + 1) * 2; - spin_unlock_irqrestore(&chip->lock, flags); - - return 0; -} - -static int iproc_pin_config_get(struct pinctrl_dev *pctldev, unsigned pin, - unsigned long *config) -{ - struct iproc_gpio *chip = pinctrl_dev_get_drvdata(pctldev); - enum pin_config_param param = pinconf_to_config_param(*config); - unsigned gpio = iproc_pin_to_gpio(pin); - u16 arg; - bool disable, pull_up; - int ret; - - switch (param) { - case PIN_CONFIG_BIAS_DISABLE: - iproc_gpio_get_pull(chip, gpio, &disable, &pull_up); - if (disable) - return 0; - else - return -EINVAL; - - case PIN_CONFIG_BIAS_PULL_UP: - iproc_gpio_get_pull(chip, gpio, &disable, &pull_up); - if (!disable && pull_up) - return 0; - else - return -EINVAL; - - case PIN_CONFIG_BIAS_PULL_DOWN: - iproc_gpio_get_pull(chip, gpio, &disable, &pull_up); - if (!disable && !pull_up) - return 0; - else - return -EINVAL; - - case PIN_CONFIG_DRIVE_STRENGTH: - ret = iproc_gpio_get_strength(chip, gpio, &arg); - if (ret) - return ret; - else - *config = pinconf_to_config_packed(param, arg); - - return 0; - - default: - return -ENOTSUPP; - } - - return -ENOTSUPP; -} - -static int iproc_pin_config_set(struct pinctrl_dev *pctldev, unsigned pin, - unsigned long *configs, unsigned num_configs) -{ - struct iproc_gpio *chip = pinctrl_dev_get_drvdata(pctldev); - enum pin_config_param param; - u16 arg; - unsigned i, gpio = iproc_pin_to_gpio(pin); - int ret = -ENOTSUPP; - - for (i = 0; i < num_configs; i++) { - param = pinconf_to_config_param(configs[i]); - arg = pinconf_to_config_argument(configs[i]); - - switch (param) { - case PIN_CONFIG_BIAS_DISABLE: - ret = iproc_gpio_set_pull(chip, gpio, true, false); - if (ret < 0) - goto out; - break; - - case PIN_CONFIG_BIAS_PULL_UP: - ret = iproc_gpio_set_pull(chip, gpio, false, true); - if (ret < 0) - goto out; - break; - - case PIN_CONFIG_BIAS_PULL_DOWN: - ret = iproc_gpio_set_pull(chip, gpio, false, false); - if (ret < 0) - goto out; - break; - - case PIN_CONFIG_DRIVE_STRENGTH: - ret = iproc_gpio_set_strength(chip, gpio, arg); - if (ret < 0) - goto out; - break; - - default: - dev_err(chip->dev, "invalid configuration\n"); - return -ENOTSUPP; - } - } /* for each config */ - -out: - return ret; -} - -static const struct pinconf_ops iproc_pconf_ops = { - .is_generic = true, - .pin_config_get = iproc_pin_config_get, - .pin_config_set = iproc_pin_config_set, -}; - -/* - * Iproc GPIO controller supports some PINCONF related configurations such as - * pull up, pull down, and drive strength, when the pin is configured to GPIO - * - * Here a local pinctrl device is created with simple 1-to-1 pin mapping to the - * local GPIO pins - */ -static int iproc_gpio_register_pinconf(struct iproc_gpio *chip) -{ - struct pinctrl_desc *pctldesc = &chip->pctldesc; - struct pinctrl_pin_desc *pins; - struct gpio_chip *gc = &chip->gc; - int i; - - pins = devm_kcalloc(chip->dev, gc->ngpio, sizeof(*pins), GFP_KERNEL); - if (!pins) - return -ENOMEM; - - for (i = 0; i < gc->ngpio; i++) { - pins[i].number = i; - pins[i].name = devm_kasprintf(chip->dev, GFP_KERNEL, - "gpio-%d", i); - if (!pins[i].name) - return -ENOMEM; - } - - pctldesc->name = dev_name(chip->dev); - pctldesc->pctlops = &iproc_pctrl_ops; - pctldesc->pins = pins; - pctldesc->npins = gc->ngpio; - pctldesc->confops = &iproc_pconf_ops; - - chip->pctl = pinctrl_register(pctldesc, chip->dev, chip); - if (IS_ERR(chip->pctl)) { - dev_err(chip->dev, "unable to register pinctrl device\n"); - return PTR_ERR(chip->pctl); - } - - return 0; -} - -static void iproc_gpio_unregister_pinconf(struct cygnus_gpio *chip) -{ - pinctrl_unregister(chip->pctl); -} - -static const struct of_device_id iproc_gpio_of_match[] = { - { .compatible = "brcm,cygnus-ccm-gpio" }, - { .compatible = "brcm,cygnus-asiu-gpio" }, - { .compatible = "brcm,cygnus-crmu-gpio" }, - { .compatible = "brcm,iproc-gpio" }, - { } -}; - -static int iproc_gpio_probe(struct platform_device *pdev) -{ - struct device *dev = &pdev->dev; - struct resource *res; - struct iproc_gpio *chip; - struct gpio_chip *gc; - u32 ngpios; - int irq, ret; - - chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); - if (!chip) - return -ENOMEM; - - chip->dev = dev; - platform_set_drvdata(pdev, chip); - - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - chip->base = devm_ioremap_resource(dev, res); - if (IS_ERR(chip->base)) { - dev_err(dev, "unable to map I/O memory\n"); - return PTR_ERR(chip->base); - } - - res = platform_get_resource(pdev, IORESOURCE_MEM, 1); - if (res) { - chip->io_ctrl = devm_ioremap_resource(dev, res); - if (IS_ERR(chip->io_ctrl)) { - dev_err(dev, "unable to map I/O memory\n"); - return PTR_ERR(chip->io_ctrl); - } - } - - if (of_property_read_u32(dev->of_node, "ngpios", &ngpios)) { - dev_err(&pdev->dev, "missing ngpios DT property\n"); - return -ENODEV; - } - - spin_lock_init(&chip->lock); - - gc = &chip->gc; - gc->base = -1; - gc->ngpio = ngpios; - chip->num_banks = (ngpios + NGPIOS_PER_BANK - 1) / NGPIOS_PER_BANK; - gc->label = dev_name(dev); - gc->dev = dev; - gc->of_node = dev->of_node; - gc->request = iproc_gpio_request; - gc->free = iproc_gpio_free; - gc->direction_input = iproc_gpio_direction_input; - gc->direction_output = iproc_gpio_direction_output; - gc->set = iproc_gpio_set; - gc->get = iproc_gpio_get; - - chip->pinmux_is_supported = of_property_read_bool(dev->of_node, - "gpio-ranges"); - - ret = gpiochip_add(gc); - if (ret < 0) { - dev_err(dev, "unable to add GPIO chip\n"); - return ret; - } - - ret = iproc_gpio_register_pinconf(chip); - if (ret) { - dev_err(dev, "unable to register pinconf\n"); - goto err_rm_gpiochip; - } - - /* optional GPIO interrupt support */ - irq = platform_get_irq(pdev, 0); - if (irq) { - ret = gpiochip_irqchip_add(gc, &iproc_gpio_irq_chip, 0, - handle_simple_irq, IRQ_TYPE_NONE); - if (ret) { - dev_err(dev, "no GPIO irqchip\n"); - goto err_unregister_pinconf; - } - - gpiochip_set_chained_irqchip(gc, &iproc_gpio_irq_chip, irq, - iproc_gpio_irq_handler); - } - - return 0; - -err_unregister_pinconf: - iproc_gpio_unregister_pinconf(chip); - -err_rm_gpiochip: - gpiochip_remove(gc); - - return ret; -} - -static struct platform_driver iproc_gpio_driver = { - .driver = { - .name = "iproc-gpio", - .of_match_table = iproc_gpio_of_match, - }, - .probe = iproc_gpio_probe, -}; - -static int __init iproc_gpio_init(void) -{ - return platform_driver_probe(&iproc_gpio_driver, iproc_gpio_probe); -} -arch_initcall_sync(iproc_gpio_init); diff --git a/drivers/pinctrl/bcm/pinctrl-iproc-gpio.c b/drivers/pinctrl/bcm/pinctrl-iproc-gpio.c new file mode 100644 index 0000000..525ea13 --- /dev/null +++ b/drivers/pinctrl/bcm/pinctrl-iproc-gpio.c @@ -0,0 +1,758 @@ +/* + * Copyright (C) 2014-2015 Broadcom Corporation + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * This file contains the Broadcom Iproc GPIO driver that supports 3 + * GPIO controllers on Iproc including the ASIU GPIO controller, the + * chipCommonG GPIO controller, and the always-on GPIO controller. Basic + * PINCONF such as bias pull up/down, and drive strength are also supported + * in this driver. + * + * It provides the functionality where pins from the GPIO can be + * individually muxed to GPIO function, if individual pad + * configuration is supported, through the interaction with respective + * SoCs IOMUX controller. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../pinctrl-utils.h" + +#define IPROC_GPIO_DATA_IN_OFFSET 0x00 +#define IPROC_GPIO_DATA_OUT_OFFSET 0x04 +#define IPROC_GPIO_OUT_EN_OFFSET 0x08 +#define IPROC_GPIO_INT_TYPE_OFFSET 0x0c +#define IPROC_GPIO_INT_DE_OFFSET 0x10 +#define IPROC_GPIO_INT_EDGE_OFFSET 0x14 +#define IPROC_GPIO_INT_MSK_OFFSET 0x18 +#define IPROC_GPIO_INT_STAT_OFFSET 0x1c +#define IPROC_GPIO_INT_MSTAT_OFFSET 0x20 +#define IPROC_GPIO_INT_CLR_OFFSET 0x24 +#define IPROC_GPIO_PAD_RES_OFFSET 0x34 +#define IPROC_GPIO_RES_EN_OFFSET 0x38 + +/* drive strength control for ASIU GPIO */ +#define IPROC_GPIO_ASIU_DRV0_CTRL_OFFSET 0x58 + +/* drive strength control for CCM/CRMU (AON) GPIO */ +#define IPROC_GPIO_DRV0_CTRL_OFFSET 0x00 + +#define GPIO_BANK_SIZE 0x200 +#define NGPIOS_PER_BANK 32 +#define GPIO_BANK(pin) ((pin) / NGPIOS_PER_BANK) + +#define IPROC_GPIO_REG(pin, reg) (GPIO_BANK(pin) * GPIO_BANK_SIZE + (reg)) +#define IPROC_GPIO_SHIFT(pin) ((pin) % NGPIOS_PER_BANK) + +#define GPIO_DRV_STRENGTH_BIT_SHIFT 20 +#define GPIO_DRV_STRENGTH_BITS 3 +#define GPIO_DRV_STRENGTH_BIT_MASK ((1 << GPIO_DRV_STRENGTH_BITS) - 1) + +/* + * Iproc GPIO core + * + * @dev: pointer to device + * @base: I/O register base for Iproc GPIO controller + * @io_ctrl: I/O register base for certain type of Iproc GPIO controller that + * has the PINCONF support implemented outside of the GPIO block + * @lock: lock to protect access to I/O registers + * @gc: GPIO chip + * @num_banks: number of GPIO banks, each bank supports up to 32 GPIOs + * @pinmux_is_supported: flag to indicate this GPIO controller contains pins + * that can be individually muxed to GPIO + * @pctl: pointer to pinctrl_dev + * @pctldesc: pinctrl descriptor + */ +struct iproc_gpio { + struct device *dev; + + void __iomem *base; + void __iomem *io_ctrl; + + spinlock_t lock; + + struct gpio_chip gc; + unsigned num_banks; + + bool pinmux_is_supported; + + struct pinctrl_dev *pctl; + struct pinctrl_desc pctldesc; +}; + +static inline struct iproc_gpio *to_iproc_gpio(struct gpio_chip *gc) +{ + return container_of(gc, struct iproc_gpio, gc); +} + +/* + * Mapping from PINCONF pins to GPIO pins is 1-to-1 + */ +static inline unsigned iproc_pin_to_gpio(unsigned pin) +{ + return pin; +} + +/** + * iproc_set_bit - set or clear one bit (corresponding to the GPIO pin) in a + * Iproc GPIO register + * + * @iproc_gpio: Iproc GPIO device + * @reg: register offset + * @gpio: GPIO pin + * @set: set or clear + */ +static inline void iproc_set_bit(struct iproc_gpio *chip, unsigned int reg, + unsigned gpio, bool set) +{ + unsigned int offset = IPROC_GPIO_REG(gpio, reg); + unsigned int shift = IPROC_GPIO_SHIFT(gpio); + u32 val; + + val = readl(chip->base + offset); + if (set) + val |= BIT(shift); + else + val &= ~BIT(shift); + writel(val, chip->base + offset); +} + +static inline bool iproc_get_bit(struct iproc_gpio *chip, unsigned int reg, + unsigned gpio) +{ + unsigned int offset = IPROC_GPIO_REG(gpio, reg); + unsigned int shift = IPROC_GPIO_SHIFT(gpio); + + return !!(readl(chip->base + offset) & BIT(shift)); +} + +static void iproc_gpio_irq_handler(struct irq_desc *desc) +{ + struct gpio_chip *gc = irq_desc_get_handler_data(desc); + struct iproc_gpio *chip = to_iproc_gpio(gc); + struct irq_chip *irq_chip = irq_desc_get_chip(desc); + int i, bit; + + chained_irq_enter(irq_chip, desc); + + /* go through the entire GPIO banks and handle all interrupts */ + for (i = 0; i < chip->num_banks; i++) { + unsigned long val = readl(chip->base + (i * GPIO_BANK_SIZE) + + IPROC_GPIO_INT_MSTAT_OFFSET); + + for_each_set_bit(bit, &val, NGPIOS_PER_BANK) { + unsigned pin = NGPIOS_PER_BANK * i + bit; + int child_irq = irq_find_mapping(gc->irqdomain, pin); + + /* + * Clear the interrupt before invoking the + * handler, so we do not leave any window + */ + writel(BIT(bit), chip->base + (i * GPIO_BANK_SIZE) + + IPROC_GPIO_INT_CLR_OFFSET); + + generic_handle_irq(child_irq); + } + } + + chained_irq_exit(irq_chip, desc); +} + + +static void iproc_gpio_irq_ack(struct irq_data *d) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct iproc_gpio *chip = to_iproc_gpio(gc); + unsigned gpio = d->hwirq; + unsigned int offset = IPROC_GPIO_REG(gpio, + IPROC_GPIO_INT_CLR_OFFSET); + unsigned int shift = IPROC_GPIO_SHIFT(gpio); + u32 val = BIT(shift); + + writel(val, chip->base + offset); +} + +/** + * iproc_gpio_irq_set_mask - mask/unmask a GPIO interrupt + * + * @d: IRQ chip data + * @unmask: mask/unmask GPIO interrupt + */ +static void iproc_gpio_irq_set_mask(struct irq_data *d, bool unmask) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct iproc_gpio *chip = to_iproc_gpio(gc); + unsigned gpio = d->hwirq; + + iproc_set_bit(chip, IPROC_GPIO_INT_MSK_OFFSET, gpio, unmask); +} + +static void iproc_gpio_irq_mask(struct irq_data *d) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct iproc_gpio *chip = to_iproc_gpio(gc); + unsigned long flags; + + spin_lock_irqsave(&chip->lock, flags); + iproc_gpio_irq_set_mask(d, false); + spin_unlock_irqrestore(&chip->lock, flags); +} + +static void iproc_gpio_irq_unmask(struct irq_data *d) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct iproc_gpio *chip = to_iproc_gpio(gc); + unsigned long flags; + + spin_lock_irqsave(&chip->lock, flags); + iproc_gpio_irq_set_mask(d, true); + spin_unlock_irqrestore(&chip->lock, flags); +} + +static int iproc_gpio_irq_set_type(struct irq_data *d, unsigned int type) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct iproc_gpio *chip = to_iproc_gpio(gc); + unsigned gpio = d->hwirq; + bool level_triggered = false; + bool dual_edge = false; + bool rising_or_high = false; + unsigned long flags; + + switch (type & IRQ_TYPE_SENSE_MASK) { + case IRQ_TYPE_EDGE_RISING: + rising_or_high = true; + break; + + case IRQ_TYPE_EDGE_FALLING: + break; + + case IRQ_TYPE_EDGE_BOTH: + dual_edge = true; + break; + + case IRQ_TYPE_LEVEL_HIGH: + level_triggered = true; + rising_or_high = true; + break; + + case IRQ_TYPE_LEVEL_LOW: + level_triggered = true; + break; + + default: + dev_err(chip->dev, "invalid GPIO IRQ type 0x%x\n", + type); + return -EINVAL; + } + + spin_lock_irqsave(&chip->lock, flags); + iproc_set_bit(chip, IPROC_GPIO_INT_TYPE_OFFSET, gpio, + level_triggered); + iproc_set_bit(chip, IPROC_GPIO_INT_DE_OFFSET, gpio, dual_edge); + iproc_set_bit(chip, IPROC_GPIO_INT_EDGE_OFFSET, gpio, + rising_or_high); + spin_unlock_irqrestore(&chip->lock, flags); + + dev_dbg(chip->dev, + "gpio:%u level_triggered:%d dual_edge:%d rising_or_high:%d\n", + gpio, level_triggered, dual_edge, rising_or_high); + + return 0; +} + +static struct irq_chip iproc_gpio_irq_chip = { + .name = "bcm-iproc-gpio", + .irq_ack = iproc_gpio_irq_ack, + .irq_mask = iproc_gpio_irq_mask, + .irq_unmask = iproc_gpio_irq_unmask, + .irq_set_type = iproc_gpio_irq_set_type, +}; + +/* + * Request the Iproc IOMUX pinmux controller to mux individual pins to GPIO + */ +static int iproc_gpio_request(struct gpio_chip *gc, unsigned offset) +{ + struct iproc_gpio *chip = to_iproc_gpio(gc); + unsigned gpio = gc->base + offset; + + /* not all Iproc GPIO pins can be muxed individually */ + if (!chip->pinmux_is_supported) + return 0; + + return pinctrl_request_gpio(gpio); +} + +static void iproc_gpio_free(struct gpio_chip *gc, unsigned offset) +{ + struct iproc_gpio *chip = to_iproc_gpio(gc); + unsigned gpio = gc->base + offset; + + if (!chip->pinmux_is_supported) + return; + + pinctrl_free_gpio(gpio); +} + +static int iproc_gpio_direction_input(struct gpio_chip *gc, unsigned gpio) +{ + struct iproc_gpio *chip = to_iproc_gpio(gc); + unsigned long flags; + + spin_lock_irqsave(&chip->lock, flags); + iproc_set_bit(chip, IPROC_GPIO_OUT_EN_OFFSET, gpio, false); + spin_unlock_irqrestore(&chip->lock, flags); + + dev_dbg(chip->dev, "gpio:%u set input\n", gpio); + + return 0; +} + +static int iproc_gpio_direction_output(struct gpio_chip *gc, unsigned gpio, + int val) +{ + struct iproc_gpio *chip = to_iproc_gpio(gc); + unsigned long flags; + + spin_lock_irqsave(&chip->lock, flags); + iproc_set_bit(chip, IPROC_GPIO_OUT_EN_OFFSET, gpio, true); + iproc_set_bit(chip, IPROC_GPIO_DATA_OUT_OFFSET, gpio, !!(val)); + spin_unlock_irqrestore(&chip->lock, flags); + + dev_dbg(chip->dev, "gpio:%u set output, value:%d\n", gpio, val); + + return 0; +} + +static void iproc_gpio_set(struct gpio_chip *gc, unsigned gpio, int val) +{ + struct iproc_gpio *chip = to_iproc_gpio(gc); + unsigned long flags; + + spin_lock_irqsave(&chip->lock, flags); + iproc_set_bit(chip, IPROC_GPIO_DATA_OUT_OFFSET, gpio, !!(val)); + spin_unlock_irqrestore(&chip->lock, flags); + + dev_dbg(chip->dev, "gpio:%u set, value:%d\n", gpio, val); +} + +static int iproc_gpio_get(struct gpio_chip *gc, unsigned gpio) +{ + struct iproc_gpio *chip = to_iproc_gpio(gc); + unsigned int offset = IPROC_GPIO_REG(gpio, + IPROC_GPIO_DATA_IN_OFFSET); + unsigned int shift = IPROC_GPIO_SHIFT(gpio); + + return !!(readl(chip->base + offset) & BIT(shift)); +} + +static int iproc_get_groups_count(struct pinctrl_dev *pctldev) +{ + return 1; +} + +/* + * Only one group: "gpio_grp", since this local pinctrl device only performs + * GPIO specific PINCONF configurations + */ +static const char *iproc_get_group_name(struct pinctrl_dev *pctldev, + unsigned selector) +{ + return "gpio_grp"; +} + +static const struct pinctrl_ops iproc_pctrl_ops = { + .get_groups_count = iproc_get_groups_count, + .get_group_name = iproc_get_group_name, + .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, + .dt_free_map = pinctrl_utils_dt_free_map, +}; + +static int iproc_gpio_set_pull(struct iproc_gpio *chip, unsigned gpio, + bool disable, bool pull_up) +{ + unsigned long flags; + + spin_lock_irqsave(&chip->lock, flags); + + if (disable) { + iproc_set_bit(chip, IPROC_GPIO_RES_EN_OFFSET, gpio, false); + } else { + iproc_set_bit(chip, IPROC_GPIO_PAD_RES_OFFSET, gpio, + pull_up); + iproc_set_bit(chip, IPROC_GPIO_RES_EN_OFFSET, gpio, true); + } + + spin_unlock_irqrestore(&chip->lock, flags); + + dev_dbg(chip->dev, "gpio:%u set pullup:%d\n", gpio, pull_up); + + return 0; +} + +static void iproc_gpio_get_pull(struct iproc_gpio *chip, unsigned gpio, + bool *disable, bool *pull_up) +{ + unsigned long flags; + + spin_lock_irqsave(&chip->lock, flags); + *disable = !iproc_get_bit(chip, IPROC_GPIO_RES_EN_OFFSET, gpio); + *pull_up = iproc_get_bit(chip, IPROC_GPIO_PAD_RES_OFFSET, gpio); + spin_unlock_irqrestore(&chip->lock, flags); +} + +static int iproc_gpio_set_strength(struct iproc_gpio *chip, unsigned gpio, + unsigned strength) +{ + void __iomem *base; + unsigned int i, offset, shift; + u32 val; + unsigned long flags; + + /* make sure drive strength is supported */ + if (strength < 2 || strength > 16 || (strength % 2)) + return -ENOTSUPP; + + if (chip->io_ctrl) { + base = chip->io_ctrl; + offset = IPROC_GPIO_DRV0_CTRL_OFFSET; + } else { + base = chip->base; + offset = IPROC_GPIO_REG(gpio, + IPROC_GPIO_ASIU_DRV0_CTRL_OFFSET); + } + + shift = IPROC_GPIO_SHIFT(gpio); + + dev_dbg(chip->dev, "gpio:%u set drive strength:%d mA\n", gpio, + strength); + + spin_lock_irqsave(&chip->lock, flags); + strength = (strength / 2) - 1; + for (i = 0; i < GPIO_DRV_STRENGTH_BITS; i++) { + val = readl(base + offset); + val &= ~BIT(shift); + val |= ((strength >> i) & 0x1) << shift; + writel(val, base + offset); + offset += 4; + } + spin_unlock_irqrestore(&chip->lock, flags); + + return 0; +} + +static int iproc_gpio_get_strength(struct iproc_gpio *chip, unsigned gpio, + u16 *strength) +{ + void __iomem *base; + unsigned int i, offset, shift; + u32 val; + unsigned long flags; + + if (chip->io_ctrl) { + base = chip->io_ctrl; + offset = IPROC_GPIO_DRV0_CTRL_OFFSET; + } else { + base = chip->base; + offset = IPROC_GPIO_REG(gpio, + IPROC_GPIO_ASIU_DRV0_CTRL_OFFSET); + } + + shift = IPROC_GPIO_SHIFT(gpio); + + spin_lock_irqsave(&chip->lock, flags); + *strength = 0; + for (i = 0; i < GPIO_DRV_STRENGTH_BITS; i++) { + val = readl(base + offset) & BIT(shift); + val >>= shift; + *strength += (val << i); + offset += 4; + } + + /* convert to mA */ + *strength = (*strength + 1) * 2; + spin_unlock_irqrestore(&chip->lock, flags); + + return 0; +} + +static int iproc_pin_config_get(struct pinctrl_dev *pctldev, unsigned pin, + unsigned long *config) +{ + struct iproc_gpio *chip = pinctrl_dev_get_drvdata(pctldev); + enum pin_config_param param = pinconf_to_config_param(*config); + unsigned gpio = iproc_pin_to_gpio(pin); + u16 arg; + bool disable, pull_up; + int ret; + + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + iproc_gpio_get_pull(chip, gpio, &disable, &pull_up); + if (disable) + return 0; + else + return -EINVAL; + + case PIN_CONFIG_BIAS_PULL_UP: + iproc_gpio_get_pull(chip, gpio, &disable, &pull_up); + if (!disable && pull_up) + return 0; + else + return -EINVAL; + + case PIN_CONFIG_BIAS_PULL_DOWN: + iproc_gpio_get_pull(chip, gpio, &disable, &pull_up); + if (!disable && !pull_up) + return 0; + else + return -EINVAL; + + case PIN_CONFIG_DRIVE_STRENGTH: + ret = iproc_gpio_get_strength(chip, gpio, &arg); + if (ret) + return ret; + *config = pinconf_to_config_packed(param, arg); + + return 0; + + default: + return -ENOTSUPP; + } + + return -ENOTSUPP; +} + +static int iproc_pin_config_set(struct pinctrl_dev *pctldev, unsigned pin, + unsigned long *configs, unsigned num_configs) +{ + struct iproc_gpio *chip = pinctrl_dev_get_drvdata(pctldev); + enum pin_config_param param; + u16 arg; + unsigned i, gpio = iproc_pin_to_gpio(pin); + int ret = -ENOTSUPP; + + for (i = 0; i < num_configs; i++) { + param = pinconf_to_config_param(configs[i]); + arg = pinconf_to_config_argument(configs[i]); + + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + ret = iproc_gpio_set_pull(chip, gpio, true, false); + if (ret < 0) + goto out; + break; + + case PIN_CONFIG_BIAS_PULL_UP: + ret = iproc_gpio_set_pull(chip, gpio, false, true); + if (ret < 0) + goto out; + break; + + case PIN_CONFIG_BIAS_PULL_DOWN: + ret = iproc_gpio_set_pull(chip, gpio, false, false); + if (ret < 0) + goto out; + break; + + case PIN_CONFIG_DRIVE_STRENGTH: + ret = iproc_gpio_set_strength(chip, gpio, arg); + if (ret < 0) + goto out; + break; + + default: + dev_err(chip->dev, "invalid configuration\n"); + return -ENOTSUPP; + } + } /* for each config */ + +out: + return ret; +} + +static const struct pinconf_ops iproc_pconf_ops = { + .is_generic = true, + .pin_config_get = iproc_pin_config_get, + .pin_config_set = iproc_pin_config_set, +}; + +/* + * Iproc GPIO controller supports some PINCONF related configurations such as + * pull up, pull down, and drive strength, when the pin is configured to GPIO + * + * Here a local pinctrl device is created with simple 1-to-1 pin mapping to the + * local GPIO pins + */ +static int iproc_gpio_register_pinconf(struct iproc_gpio *chip) +{ + struct pinctrl_desc *pctldesc = &chip->pctldesc; + struct pinctrl_pin_desc *pins; + struct gpio_chip *gc = &chip->gc; + int i; + + pins = devm_kcalloc(chip->dev, gc->ngpio, sizeof(*pins), GFP_KERNEL); + if (!pins) + return -ENOMEM; + + for (i = 0; i < gc->ngpio; i++) { + pins[i].number = i; + pins[i].name = devm_kasprintf(chip->dev, GFP_KERNEL, + "gpio-%d", i); + if (!pins[i].name) + return -ENOMEM; + } + + pctldesc->name = dev_name(chip->dev); + pctldesc->pctlops = &iproc_pctrl_ops; + pctldesc->pins = pins; + pctldesc->npins = gc->ngpio; + pctldesc->confops = &iproc_pconf_ops; + + chip->pctl = pinctrl_register(pctldesc, chip->dev, chip); + if (IS_ERR(chip->pctl)) { + dev_err(chip->dev, "unable to register pinctrl device\n"); + return PTR_ERR(chip->pctl); + } + + return 0; +} + +static void iproc_gpio_unregister_pinconf(struct cygnus_gpio *chip) +{ + pinctrl_unregister(chip->pctl); +} + +static const struct of_device_id iproc_gpio_of_match[] = { + { .compatible = "brcm,cygnus-ccm-gpio" }, + { .compatible = "brcm,cygnus-asiu-gpio" }, + { .compatible = "brcm,cygnus-crmu-gpio" }, + { .compatible = "brcm,iproc-gpio" }, + { } +}; + +static int iproc_gpio_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct resource *res; + struct iproc_gpio *chip; + struct gpio_chip *gc; + u32 ngpios; + int irq, ret; + + chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); + if (!chip) + return -ENOMEM; + + chip->dev = dev; + platform_set_drvdata(pdev, chip); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + chip->base = devm_ioremap_resource(dev, res); + if (IS_ERR(chip->base)) { + dev_err(dev, "unable to map I/O memory\n"); + return PTR_ERR(chip->base); + } + + res = platform_get_resource(pdev, IORESOURCE_MEM, 1); + if (res) { + chip->io_ctrl = devm_ioremap_resource(dev, res); + if (IS_ERR(chip->io_ctrl)) { + dev_err(dev, "unable to map I/O memory\n"); + return PTR_ERR(chip->io_ctrl); + } + } + + if (of_property_read_u32(dev->of_node, "ngpios", &ngpios)) { + dev_err(&pdev->dev, "missing ngpios DT property\n"); + return -ENODEV; + } + + spin_lock_init(&chip->lock); + + gc = &chip->gc; + gc->base = -1; + gc->ngpio = ngpios; + chip->num_banks = (ngpios + NGPIOS_PER_BANK - 1) / NGPIOS_PER_BANK; + gc->label = dev_name(dev); + gc->dev = dev; + gc->of_node = dev->of_node; + gc->request = iproc_gpio_request; + gc->free = iproc_gpio_free; + gc->direction_input = iproc_gpio_direction_input; + gc->direction_output = iproc_gpio_direction_output; + gc->set = iproc_gpio_set; + gc->get = iproc_gpio_get; + + chip->pinmux_is_supported = of_property_read_bool(dev->of_node, + "gpio-ranges"); + + ret = gpiochip_add(gc); + if (ret < 0) { + dev_err(dev, "unable to add GPIO chip\n"); + return ret; + } + + ret = iproc_gpio_register_pinconf(chip); + if (ret) { + dev_err(dev, "unable to register pinconf\n"); + goto err_rm_gpiochip; + } + + /* optional GPIO interrupt support */ + irq = platform_get_irq(pdev, 0); + if (irq) { + ret = gpiochip_irqchip_add(gc, &iproc_gpio_irq_chip, 0, + handle_simple_irq, IRQ_TYPE_NONE); + if (ret) { + dev_err(dev, "no GPIO irqchip\n"); + goto err_unregister_pinconf; + } + + gpiochip_set_chained_irqchip(gc, &iproc_gpio_irq_chip, irq, + iproc_gpio_irq_handler); + } + + return 0; + +err_unregister_pinconf: + iproc_gpio_unregister_pinconf(chip); + +err_rm_gpiochip: + gpiochip_remove(gc); + + return ret; +} + +static struct platform_driver iproc_gpio_driver = { + .driver = { + .name = "iproc-gpio", + .of_match_table = iproc_gpio_of_match, + }, + .probe = iproc_gpio_probe, +}; + +static int __init iproc_gpio_init(void) +{ + return platform_driver_probe(&iproc_gpio_driver, iproc_gpio_probe); +} +arch_initcall_sync(iproc_gpio_init); -- cgit v0.10.2 From 32844138e31347fc0f61d3bf2d7b9c4583f189e3 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Wed, 18 Nov 2015 16:21:17 +0100 Subject: pinctrl: at91-pio4: use %pr format string for resource resource_size_t may be defined as 32 or 64 bit depending on configuration, so it cannot be printed using the normal format strings, as gcc correctly warns: pinctrl-at91-pio4.c: In function 'atmel_pinctrl_probe': pinctrl-at91-pio4.c:1003:41: warning: format '%u' expects argument of type 'unsigned int', but argument 5 has type 'resource_size_t {aka long long unsigned int}' [-Wformat=] dev_dbg(dev, "bank %i: hwirq=%u\n", i, res->start); This changes the format string to use the special "%pr" format string that prints a resource, and changes the arguments so we the resource structure directly. Signed-off-by: Arnd Bergmann Acked-by: Ludovic Desroches Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/pinctrl-at91-pio4.c b/drivers/pinctrl/pinctrl-at91-pio4.c index 33edd07..abdc16e 100644 --- a/drivers/pinctrl/pinctrl-at91-pio4.c +++ b/drivers/pinctrl/pinctrl-at91-pio4.c @@ -1000,7 +1000,7 @@ static int atmel_pinctrl_probe(struct platform_device *pdev) atmel_pioctrl->irqs[i] = res->start; irq_set_chained_handler(res->start, atmel_gpio_irq_handler); irq_set_handler_data(res->start, atmel_pioctrl); - dev_dbg(dev, "bank %i: hwirq=%u\n", i, res->start); + dev_dbg(dev, "bank %i: irq=%pr\n", i, res); } atmel_pioctrl->irq_domain = irq_domain_add_linear(dev->of_node, -- cgit v0.10.2 From bf714d3780b599731eb18f6a6a3fb67bac38ec21 Mon Sep 17 00:00:00 2001 From: Martin Schiller Date: Thu, 26 Nov 2015 11:00:06 +0100 Subject: pinctrl/lantiq: updating devicetree binding description This patch adds the new dedicated "lantiq,-pinctrl" compatible strings to the devicetree bindings Documentation, where is one of "ase", "danube", "xrx100", "xrx200" or "xrx300" and marks the "lantiq,pinctrl-xway", "lantiq,pinctrl-ase" and "lantiq,pinctrl-xr9" compatible strings as DEPRECATED. Signed-off-by: Martin Schiller Acked-by: Rob Herring Signed-off-by: Linus Walleij diff --git a/Documentation/devicetree/bindings/pinctrl/lantiq,pinctrl-xway.txt b/Documentation/devicetree/bindings/pinctrl/lantiq,pinctrl-xway.txt index e89b467..8e5216b 100644 --- a/Documentation/devicetree/bindings/pinctrl/lantiq,pinctrl-xway.txt +++ b/Documentation/devicetree/bindings/pinctrl/lantiq,pinctrl-xway.txt @@ -1,7 +1,16 @@ Lantiq XWAY pinmux controller Required properties: -- compatible: "lantiq,pinctrl-xway" or "lantiq,pinctrl-xr9" +- compatible: "lantiq,pinctrl-xway", (DEPRECATED: Use "lantiq,pinctrl-danube") + "lantiq,pinctrl-xr9", (DEPRECATED: Use "lantiq,xrx100-pinctrl" or + "lantiq,xrx200-pinctrl") + "lantiq,pinctrl-ase", (DEPRECATED: Use "lantiq,ase-pinctrl") + "lantiq,-pinctrl", where is: + "ase" (XWAY AMAZON Family) + "danube" (XWAY DANUBE Family) + "xrx100" (XWAY xRX100 Family) + "xrx200" (XWAY xRX200 Family) + "xrx300" (XWAY xRX300 Family) - reg: Should contain the physical address and length of the gpio/pinmux register range @@ -36,19 +45,87 @@ Required subnode-properties: Valid values for group and function names: +XWAY: (DEPRECATED: Use DANUBE) mux groups: exin0, exin1, exin2, jtag, ebu a23, ebu a24, ebu a25, ebu clk, ebu cs1, ebu wait, nand ale, nand cs1, nand cle, spi, spi_cs1, spi_cs2, spi_cs3, - spi_cs4, spi_cs5, spi_cs6, asc0, asc0 cts rts, stp, nmi , gpt1, gpt2, + spi_cs4, spi_cs5, spi_cs6, asc0, asc0 cts rts, stp, nmi, gpt1, gpt2, gpt3, clkout0, clkout1, clkout2, clkout3, gnt1, gnt2, gnt3, req1, req2, req3 - additional mux groups (XR9 only): - mdio, nand rdy, nand rd, exin3, exin4, gnt4, req4 + functions: + spi, asc, cgu, jtag, exin, stp, gpt, nmi, pci, ebu + +XR9: ( DEPRECATED: Use xRX100/xRX200) + mux groups: + exin0, exin1, exin2, exin3, exin4, jtag, ebu a23, ebu a24, ebu a25, + ebu clk, ebu cs1, ebu wait, nand ale, nand cs1, nand cle, nand rdy, + nand rd, spi, spi_cs1, spi_cs2, spi_cs3, spi_cs4, spi_cs5, spi_cs6, + asc0, asc0 cts rts, stp, nmi, gpt1, gpt2, gpt3, clkout0, clkout1, + clkout2, clkout3, gnt1, gnt2, gnt3, gnt4, req1, req2, req3, req4, mdio, + gphy0 led0, gphy0 led1, gphy0 led2, gphy1 led0, gphy1 led1, gphy1 led2 + + functions: + spi, asc, cgu, jtag, exin, stp, gpt, nmi, pci, ebu, mdio, gphy + +AMAZON: + mux groups: + exin0, exin1, exin2, jtag, spi_di, spi_do, spi_clk, spi_cs1, spi_cs2, + spi_cs3, spi_cs4, spi_cs5, spi_cs6, asc, stp, gpt1, gpt2, gpt3, clkout0, + clkout1, clkout2, mdio, dfe led0, dfe led1, ephy led0, ephy led1, ephy led2 + + functions: + spi, asc, cgu, jtag, exin, stp, gpt, mdio, ephy, dfe + +DANUBE: + mux groups: + exin0, exin1, exin2, jtag, ebu a23, ebu a24, ebu a25, ebu clk, ebu cs1, + ebu wait, nand ale, nand cs1, nand cle, spi_di, spi_do, spi_clk, spi_cs1, + spi_cs2, spi_cs3, spi_cs4, spi_cs5, spi_cs6, asc0, asc0 cts rts, stp, nmi, + gpt1, gpt2, gpt3, clkout0, clkout1, clkout2, clkout3, gnt1, gnt2, gnt3, + req1, req2, req3, dfe led0, dfe led1 functions: - spi, asc, cgu, jtag, exin, stp, gpt, nmi, pci, ebu, mdio + spi, asc, cgu, jtag, exin, stp, gpt, nmi, pci, ebu, dfe +xRX100: + mux groups: + exin0, exin1, exin2, exin3, exin4, ebu a23, ebu a24, ebu a25, ebu clk, + ebu cs1, ebu wait, nand ale, nand cs1, nand cle, nand rdy, nand rd, + spi_di, spi_do, spi_clk, spi_cs1, spi_cs2, spi_cs3, spi_cs4, spi_cs5, + spi_cs6, asc0, asc0 cts rts, stp, nmi, gpt1, gpt2, gpt3, clkout0, clkout1, + clkout2, clkout3, gnt1, gnt2, gnt3, gnt4, req1, req2, req3, req4, mdio, + dfe led0, dfe led1 + + functions: + spi, asc, cgu, exin, stp, gpt, nmi, pci, ebu, mdio, dfe + +xRX200: + mux groups: + exin0, exin1, exin2, exin3, exin4, ebu a23, ebu a24, ebu a25, ebu clk, + ebu cs1, ebu wait, nand ale, nand cs1, nand cle, nand rdy, nand rd, + spi_di, spi_do, spi_clk, spi_cs1, spi_cs2, spi_cs3, spi_cs4, spi_cs5, + spi_cs6, usif uart_rx, usif uart_tx, usif uart_rts, usif uart_cts, + usif uart_dtr, usif uart_dsr, usif uart_dcd, usif uart_ri, usif spi_di, + usif spi_do, usif spi_clk, usif spi_cs0, usif spi_cs1, usif spi_cs2, + stp, nmi, gpt1, gpt2, gpt3, clkout0, clkout1, clkout2, clkout3, gnt1, + gnt2, gnt3, gnt4, req1, req2, req3, req4, mdio, dfe led0, dfe led1, + gphy0 led0, gphy0 led1, gphy0 led2, gphy1 led0, gphy1 led1, gphy1 led2 + + functions: + spi, usif, cgu, exin, stp, gpt, nmi, pci, ebu, mdio, dfe, gphy + +xRX300: + mux groups: + exin0, exin1, exin2, exin4, nand ale, nand cs0, nand cs1, nand cle, + nand rdy, nand rd, nand_d0, nand_d1, nand_d2, nand_d3, nand_d4, nand_d5, + nand_d6, nand_d7, nand_d1, nand wr, nand wp, nand se, spi_di, spi_do, + spi_clk, spi_cs1, spi_cs4, spi_cs6, usif uart_rx, usif uart_tx, + usif spi_di, usif spi_do, usif spi_clk, usif spi_cs0, stp, clkout2, + mdio, dfe led0, dfe led1, ephy0 led0, ephy0 led1, ephy1 led0, ephy1 led1 + + functions: + spi, usif, cgu, exin, stp, ebu, mdio, dfe, ephy Definition of pin configurations: @@ -62,15 +139,32 @@ Optional subnode-properties: 0: none, 1: down, 2: up. - lantiq,open-drain: Boolean, enables open-drain on the defined pin. -Valid values for XWAY pin names: +Valid values for XWAY pin names: (DEPRECATED: Use DANUBE) Pinconf pins can be referenced via the names io0-io31. -Valid values for XR9 pin names: +Valid values for XR9 pin names: (DEPRECATED: Use xrX100/xRX200) Pinconf pins can be referenced via the names io0-io55. +Valid values for AMAZON pin names: + Pinconf pins can be referenced via the names io0-io31. + +Valid values for DANUBE pin names: + Pinconf pins can be referenced via the names io0-io31. + +Valid values for xRX100 pin names: + Pinconf pins can be referenced via the names io0-io55. + +Valid values for xRX200 pin names: + Pinconf pins can be referenced via the names io0-io49. + +Valid values for xRX300 pin names: + Pinconf pins can be referenced via the names io0-io1,io3-io6,io8-io11, + io13-io19,io23-io27,io34-io36, + io42-io43,io48-io61. + Example: gpio: pinmux@E100B10 { - compatible = "lantiq,pinctrl-xway"; + compatible = "lantiq,danube-pinctrl"; pinctrl-names = "default"; pinctrl-0 = <&state_default>; -- cgit v0.10.2 From be14811c03cf20c793fd176a347625335110b0e6 Mon Sep 17 00:00:00 2001 From: Martin Schiller Date: Thu, 26 Nov 2015 11:00:07 +0100 Subject: pinctrl/lantiq: introduce new dedicated devicetree bindings This patch introduces new dedicated "lantiq,-pinctrl" devicetree bindings, where is one of "ase", "danube", "xrx100", "xrx200" or "xrx300" and marks the "lantiq,pinctrl-xway", "lantiq,pinctrl-ase" and "lantiq,pinctrl-xr9" bindings as DEPRECATED. Based on the newest Lantiq Hardware Description it turend out, that there are some differences in the GPIO alternative functions of the Danube, xRX100 and xRX200 families, which makes it impossible to use only one xway_mfp table. This patch also adds support for the xRX300 family. Signed-off-by: Martin Schiller Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/pinctrl-lantiq.h b/drivers/pinctrl/pinctrl-lantiq.h index eb89ba0..e137d13 100644 --- a/drivers/pinctrl/pinctrl-lantiq.h +++ b/drivers/pinctrl/pinctrl-lantiq.h @@ -162,6 +162,14 @@ enum ltq_pin { GPIO53, GPIO54, GPIO55, + GPIO56, + GPIO57, + GPIO58, + GPIO59, + GPIO60, /* 60 */ + GPIO61, + GPIO62, + GPIO63, GPIO64, GPIO65, diff --git a/drivers/pinctrl/pinctrl-xway.c b/drivers/pinctrl/pinctrl-xway.c index ae724bd..a064962 100644 --- a/drivers/pinctrl/pinctrl-xway.c +++ b/drivers/pinctrl/pinctrl-xway.c @@ -7,6 +7,7 @@ * publishhed by the Free Software Foundation. * * Copyright (C) 2012 John Crispin + * Copyright (C) 2015 Martin Schiller */ #include @@ -24,7 +25,7 @@ #include -/* we have 3 1/2 banks of 16 bit each */ +/* we have up to 4 banks of 16 bit each */ #define PINS 16 #define PORT3 3 #define PORT(x) (x / PINS) @@ -35,7 +36,7 @@ #define MUX_ALT1 0x2 /* - * each bank has this offset apart from the 1/2 bank that is mixed into the + * each bank has this offset apart from the 4th bank that is mixed into the * other 3 ranges */ #define REG_OFF 0x30 @@ -51,7 +52,7 @@ #define GPIO_PUDSEL(p) (GPIO_BASE(p) + 0x1c) #define GPIO_PUDEN(p) (GPIO_BASE(p) + 0x20) -/* the 1/2 port needs special offsets for some registers */ +/* the 4th port needs special offsets for some registers */ #define GPIO3_OD (GPIO_BASE(0) + 0x24) #define GPIO3_PUDSEL (GPIO_BASE(0) + 0x28) #define GPIO3_PUDEN (GPIO_BASE(0) + 0x2C) @@ -80,17 +81,18 @@ #define FUNC_MUX(f, m) \ { .func = f, .mux = XWAY_MUX_##m, } -#define XWAY_MAX_PIN 32 -#define XR9_MAX_PIN 56 - enum xway_mux { XWAY_MUX_GPIO = 0, XWAY_MUX_SPI, XWAY_MUX_ASC, + XWAY_MUX_USIF, XWAY_MUX_PCI, + XWAY_MUX_CBUS, XWAY_MUX_CGU, XWAY_MUX_EBU, + XWAY_MUX_EBU2, XWAY_MUX_JTAG, + XWAY_MUX_MCD, XWAY_MUX_EXIN, XWAY_MUX_TDM, XWAY_MUX_STP, @@ -103,9 +105,15 @@ enum xway_mux { XWAY_MUX_DFE, XWAY_MUX_SDIO, XWAY_MUX_GPHY, + XWAY_MUX_SSI, + XWAY_MUX_WIFI, XWAY_MUX_NONE = 0xffff, }; +/* --------- DEPRECATED: xr9 related code --------- */ +/* ---------- use xrx100/xrx200 instead ---------- */ +#define XR9_MAX_PIN 56 + static const struct ltq_mfp_pin xway_mfp[] = { /* pin f0 f1 f2 f3 */ MFP_XWAY(GPIO0, GPIO, EXIN, NONE, TDM), @@ -113,7 +121,7 @@ static const struct ltq_mfp_pin xway_mfp[] = { MFP_XWAY(GPIO2, GPIO, CGU, EXIN, GPHY), MFP_XWAY(GPIO3, GPIO, CGU, NONE, PCI), MFP_XWAY(GPIO4, GPIO, STP, NONE, ASC), - MFP_XWAY(GPIO5, GPIO, STP, NONE, GPHY), + MFP_XWAY(GPIO5, GPIO, STP, GPHY, NONE), MFP_XWAY(GPIO6, GPIO, STP, GPT, ASC), MFP_XWAY(GPIO7, GPIO, CGU, PCI, GPHY), MFP_XWAY(GPIO8, GPIO, CGU, NMI, NONE), @@ -152,7 +160,7 @@ static const struct ltq_mfp_pin xway_mfp[] = { MFP_XWAY(GPIO41, GPIO, NONE, NONE, NONE), MFP_XWAY(GPIO42, GPIO, MDIO, NONE, NONE), MFP_XWAY(GPIO43, GPIO, MDIO, NONE, NONE), - MFP_XWAY(GPIO44, GPIO, NONE, GPHY, SIN), + MFP_XWAY(GPIO44, GPIO, NONE, SIN, GPHY), MFP_XWAY(GPIO45, GPIO, NONE, GPHY, SIN), MFP_XWAY(GPIO46, GPIO, NONE, NONE, EXIN), MFP_XWAY(GPIO47, GPIO, NONE, GPHY, SIN), @@ -166,42 +174,6 @@ static const struct ltq_mfp_pin xway_mfp[] = { MFP_XWAY(GPIO55, GPIO, NONE, NONE, NONE), }; -static const struct ltq_mfp_pin ase_mfp[] = { - /* pin f0 f1 f2 f3 */ - MFP_XWAY(GPIO0, GPIO, EXIN, MII, TDM), - MFP_XWAY(GPIO1, GPIO, STP, DFE, EBU), - MFP_XWAY(GPIO2, GPIO, STP, DFE, EPHY), - MFP_XWAY(GPIO3, GPIO, STP, EPHY, EBU), - MFP_XWAY(GPIO4, GPIO, GPT, EPHY, MII), - MFP_XWAY(GPIO5, GPIO, MII, ASC, GPT), - MFP_XWAY(GPIO6, GPIO, MII, ASC, EXIN), - MFP_XWAY(GPIO7, GPIO, SPI, MII, JTAG), - MFP_XWAY(GPIO8, GPIO, SPI, MII, JTAG), - MFP_XWAY(GPIO9, GPIO, SPI, MII, JTAG), - MFP_XWAY(GPIO10, GPIO, SPI, MII, JTAG), - MFP_XWAY(GPIO11, GPIO, EBU, CGU, JTAG), - MFP_XWAY(GPIO12, GPIO, EBU, MII, SDIO), - MFP_XWAY(GPIO13, GPIO, EBU, MII, CGU), - MFP_XWAY(GPIO14, GPIO, EBU, SPI, CGU), - MFP_XWAY(GPIO15, GPIO, EBU, SPI, SDIO), - MFP_XWAY(GPIO16, GPIO, NONE, NONE, NONE), - MFP_XWAY(GPIO17, GPIO, NONE, NONE, NONE), - MFP_XWAY(GPIO18, GPIO, NONE, NONE, NONE), - MFP_XWAY(GPIO19, GPIO, EBU, MII, SDIO), - MFP_XWAY(GPIO20, GPIO, EBU, MII, SDIO), - MFP_XWAY(GPIO21, GPIO, EBU, MII, SDIO), - MFP_XWAY(GPIO22, GPIO, EBU, MII, CGU), - MFP_XWAY(GPIO23, GPIO, EBU, MII, CGU), - MFP_XWAY(GPIO24, GPIO, EBU, NONE, MII), - MFP_XWAY(GPIO25, GPIO, EBU, MII, GPT), - MFP_XWAY(GPIO26, GPIO, EBU, MII, SDIO), - MFP_XWAY(GPIO27, GPIO, EBU, NONE, MII), - MFP_XWAY(GPIO28, GPIO, MII, EBU, SDIO), - MFP_XWAY(GPIO29, GPIO, EBU, MII, EXIN), - MFP_XWAY(GPIO30, GPIO, NONE, NONE, NONE), - MFP_XWAY(GPIO31, GPIO, NONE, NONE, NONE), -}; - static const unsigned pins_jtag[] = {GPIO15, GPIO16, GPIO17, GPIO19, GPIO35}; static const unsigned pins_asc0[] = {GPIO11, GPIO12}; static const unsigned pins_asc0_cts_rts[] = {GPIO9, GPIO10}; @@ -231,6 +203,8 @@ static const unsigned pins_nand_cle[] = {GPIO24}; static const unsigned pins_nand_rdy[] = {GPIO48}; static const unsigned pins_nand_rd[] = {GPIO49}; +static const unsigned xway_exin_pin_map[] = {GPIO0, GPIO1, GPIO2, GPIO39, GPIO46, GPIO9}; + static const unsigned pins_exin0[] = {GPIO0}; static const unsigned pins_exin1[] = {GPIO1}; static const unsigned pins_exin2[] = {GPIO2}; @@ -240,7 +214,7 @@ static const unsigned pins_exin5[] = {GPIO9}; static const unsigned pins_spi[] = {GPIO16, GPIO17, GPIO18}; static const unsigned pins_spi_cs1[] = {GPIO15}; -static const unsigned pins_spi_cs2[] = {GPIO21}; +static const unsigned pins_spi_cs2[] = {GPIO22}; static const unsigned pins_spi_cs3[] = {GPIO13}; static const unsigned pins_spi_cs4[] = {GPIO10}; static const unsigned pins_spi_cs5[] = {GPIO9}; @@ -264,25 +238,6 @@ static const unsigned pins_pci_req2[] = {GPIO31}; static const unsigned pins_pci_req3[] = {GPIO3}; static const unsigned pins_pci_req4[] = {GPIO37}; -static const unsigned ase_pins_jtag[] = {GPIO7, GPIO8, GPIO9, GPIO10, GPIO11}; -static const unsigned ase_pins_asc[] = {GPIO5, GPIO6}; -static const unsigned ase_pins_stp[] = {GPIO1, GPIO2, GPIO3}; -static const unsigned ase_pins_ephy[] = {GPIO2, GPIO3, GPIO4}; -static const unsigned ase_pins_dfe[] = {GPIO1, GPIO2}; - -static const unsigned ase_pins_spi[] = {GPIO8, GPIO9, GPIO10}; -static const unsigned ase_pins_spi_cs1[] = {GPIO7}; -static const unsigned ase_pins_spi_cs2[] = {GPIO15}; -static const unsigned ase_pins_spi_cs3[] = {GPIO14}; - -static const unsigned ase_pins_exin0[] = {GPIO6}; -static const unsigned ase_pins_exin1[] = {GPIO29}; -static const unsigned ase_pins_exin2[] = {GPIO0}; - -static const unsigned ase_pins_gpt1[] = {GPIO5}; -static const unsigned ase_pins_gpt2[] = {GPIO4}; -static const unsigned ase_pins_gpt3[] = {GPIO25}; - static const struct ltq_pin_group xway_grps[] = { GRP_MUX("exin0", EXIN, pins_exin0), GRP_MUX("exin1", EXIN, pins_exin1), @@ -338,24 +293,6 @@ static const struct ltq_pin_group xway_grps[] = { GRP_MUX("gphy1 led2", GPHY, pins_gphy1_led2), }; -static const struct ltq_pin_group ase_grps[] = { - GRP_MUX("exin0", EXIN, ase_pins_exin0), - GRP_MUX("exin1", EXIN, ase_pins_exin1), - GRP_MUX("exin2", EXIN, ase_pins_exin2), - GRP_MUX("jtag", JTAG, ase_pins_jtag), - GRP_MUX("stp", STP, ase_pins_stp), - GRP_MUX("asc", ASC, ase_pins_asc), - GRP_MUX("gpt1", GPT, ase_pins_gpt1), - GRP_MUX("gpt2", GPT, ase_pins_gpt2), - GRP_MUX("gpt3", GPT, ase_pins_gpt3), - GRP_MUX("ephy", EPHY, ase_pins_ephy), - GRP_MUX("dfe", DFE, ase_pins_dfe), - GRP_MUX("spi", SPI, ase_pins_spi), - GRP_MUX("spi_cs1", SPI, ase_pins_spi_cs1), - GRP_MUX("spi_cs2", SPI, ase_pins_spi_cs2), - GRP_MUX("spi_cs3", SPI, ase_pins_spi_cs3), -}; - static const char * const xway_pci_grps[] = {"gnt1", "gnt2", "gnt3", "req1", "req2", "req3"}; @@ -395,30 +332,6 @@ static const char * const xrx_pci_grps[] = {"gnt1", "gnt2", "req1", "req2", "req3", "req4"}; -/* ase */ -static const char * const ase_exin_grps[] = {"exin0", "exin1", "exin2"}; -static const char * const ase_gpt_grps[] = {"gpt1", "gpt2", "gpt3"}; -static const char * const ase_dfe_grps[] = {"dfe"}; -static const char * const ase_ephy_grps[] = {"ephy"}; -static const char * const ase_asc_grps[] = {"asc"}; -static const char * const ase_jtag_grps[] = {"jtag"}; -static const char * const ase_stp_grps[] = {"stp"}; -static const char * const ase_spi_grps[] = {"spi", "spi_cs1", - "spi_cs2", "spi_cs3"}; - -static const struct ltq_pmx_func danube_funcs[] = { - {"spi", ARRAY_AND_SIZE(xway_spi_grps)}, - {"asc", ARRAY_AND_SIZE(xway_asc_grps)}, - {"cgu", ARRAY_AND_SIZE(xway_cgu_grps)}, - {"jtag", ARRAY_AND_SIZE(xway_jtag_grps)}, - {"exin", ARRAY_AND_SIZE(xway_exin_grps)}, - {"stp", ARRAY_AND_SIZE(xway_stp_grps)}, - {"gpt", ARRAY_AND_SIZE(xway_gpt_grps)}, - {"nmi", ARRAY_AND_SIZE(xway_nmi_grps)}, - {"pci", ARRAY_AND_SIZE(xway_pci_grps)}, - {"ebu", ARRAY_AND_SIZE(xway_ebu_grps)}, -}; - static const struct ltq_pmx_func xrx_funcs[] = { {"spi", ARRAY_AND_SIZE(xway_spi_grps)}, {"asc", ARRAY_AND_SIZE(xway_asc_grps)}, @@ -434,17 +347,991 @@ static const struct ltq_pmx_func xrx_funcs[] = { {"gphy", ARRAY_AND_SIZE(xrx_gphy_grps)}, }; +/* --------- ase related code --------- */ +#define ASE_MAX_PIN 32 + +static const struct ltq_mfp_pin ase_mfp[] = { + /* pin f0 f1 f2 f3 */ + MFP_XWAY(GPIO0, GPIO, EXIN, MII, TDM), + MFP_XWAY(GPIO1, GPIO, STP, DFE, EBU), + MFP_XWAY(GPIO2, GPIO, STP, DFE, EPHY), + MFP_XWAY(GPIO3, GPIO, STP, EPHY, EBU), + MFP_XWAY(GPIO4, GPIO, GPT, EPHY, MII), + MFP_XWAY(GPIO5, GPIO, MII, ASC, GPT), + MFP_XWAY(GPIO6, GPIO, MII, ASC, EXIN), + MFP_XWAY(GPIO7, GPIO, SPI, MII, JTAG), + MFP_XWAY(GPIO8, GPIO, SPI, MII, JTAG), + MFP_XWAY(GPIO9, GPIO, SPI, MII, JTAG), + MFP_XWAY(GPIO10, GPIO, SPI, MII, JTAG), + MFP_XWAY(GPIO11, GPIO, EBU, CGU, JTAG), + MFP_XWAY(GPIO12, GPIO, EBU, MII, SDIO), + MFP_XWAY(GPIO13, GPIO, EBU, MII, CGU), + MFP_XWAY(GPIO14, GPIO, EBU, SPI, CGU), + MFP_XWAY(GPIO15, GPIO, EBU, SPI, SDIO), + MFP_XWAY(GPIO16, GPIO, NONE, NONE, NONE), + MFP_XWAY(GPIO17, GPIO, NONE, NONE, NONE), + MFP_XWAY(GPIO18, GPIO, NONE, NONE, NONE), + MFP_XWAY(GPIO19, GPIO, EBU, MII, SDIO), + MFP_XWAY(GPIO20, GPIO, EBU, MII, SDIO), + MFP_XWAY(GPIO21, GPIO, EBU, MII, EBU2), + MFP_XWAY(GPIO22, GPIO, EBU, MII, CGU), + MFP_XWAY(GPIO23, GPIO, EBU, MII, CGU), + MFP_XWAY(GPIO24, GPIO, EBU, EBU2, MDIO), + MFP_XWAY(GPIO25, GPIO, EBU, MII, GPT), + MFP_XWAY(GPIO26, GPIO, EBU, MII, SDIO), + MFP_XWAY(GPIO27, GPIO, EBU, NONE, MDIO), + MFP_XWAY(GPIO28, GPIO, MII, EBU, SDIO), + MFP_XWAY(GPIO29, GPIO, EBU, MII, EXIN), + MFP_XWAY(GPIO30, GPIO, NONE, NONE, NONE), + MFP_XWAY(GPIO31, GPIO, NONE, NONE, NONE), +}; + +static const unsigned ase_exin_pin_map[] = {GPIO6, GPIO29, GPIO0}; + +static const unsigned ase_pins_exin0[] = {GPIO6}; +static const unsigned ase_pins_exin1[] = {GPIO29}; +static const unsigned ase_pins_exin2[] = {GPIO0}; + +static const unsigned ase_pins_jtag[] = {GPIO7, GPIO8, GPIO9, GPIO10, GPIO11}; +static const unsigned ase_pins_asc[] = {GPIO5, GPIO6}; +static const unsigned ase_pins_stp[] = {GPIO1, GPIO2, GPIO3}; +static const unsigned ase_pins_mdio[] = {GPIO24, GPIO27}; +static const unsigned ase_pins_ephy_led0[] = {GPIO2}; +static const unsigned ase_pins_ephy_led1[] = {GPIO3}; +static const unsigned ase_pins_ephy_led2[] = {GPIO4}; +static const unsigned ase_pins_dfe_led0[] = {GPIO1}; +static const unsigned ase_pins_dfe_led1[] = {GPIO2}; + +static const unsigned ase_pins_spi[] = {GPIO8, GPIO9, GPIO10}; /* DEPRECATED */ +static const unsigned ase_pins_spi_di[] = {GPIO8}; +static const unsigned ase_pins_spi_do[] = {GPIO9}; +static const unsigned ase_pins_spi_clk[] = {GPIO10}; +static const unsigned ase_pins_spi_cs1[] = {GPIO7}; +static const unsigned ase_pins_spi_cs2[] = {GPIO15}; +static const unsigned ase_pins_spi_cs3[] = {GPIO14}; + +static const unsigned ase_pins_gpt1[] = {GPIO5}; +static const unsigned ase_pins_gpt2[] = {GPIO4}; +static const unsigned ase_pins_gpt3[] = {GPIO25}; + +static const unsigned ase_pins_clkout0[] = {GPIO23}; +static const unsigned ase_pins_clkout1[] = {GPIO22}; +static const unsigned ase_pins_clkout2[] = {GPIO14}; + +static const struct ltq_pin_group ase_grps[] = { + GRP_MUX("exin0", EXIN, ase_pins_exin0), + GRP_MUX("exin1", EXIN, ase_pins_exin1), + GRP_MUX("exin2", EXIN, ase_pins_exin2), + GRP_MUX("jtag", JTAG, ase_pins_jtag), + GRP_MUX("spi", SPI, ase_pins_spi), /* DEPRECATED */ + GRP_MUX("spi_di", SPI, ase_pins_spi_di), + GRP_MUX("spi_do", SPI, ase_pins_spi_do), + GRP_MUX("spi_clk", SPI, ase_pins_spi_clk), + GRP_MUX("spi_cs1", SPI, ase_pins_spi_cs1), + GRP_MUX("spi_cs2", SPI, ase_pins_spi_cs2), + GRP_MUX("spi_cs3", SPI, ase_pins_spi_cs3), + GRP_MUX("asc", ASC, ase_pins_asc), + GRP_MUX("stp", STP, ase_pins_stp), + GRP_MUX("gpt1", GPT, ase_pins_gpt1), + GRP_MUX("gpt2", GPT, ase_pins_gpt2), + GRP_MUX("gpt3", GPT, ase_pins_gpt3), + GRP_MUX("clkout0", CGU, ase_pins_clkout0), + GRP_MUX("clkout1", CGU, ase_pins_clkout1), + GRP_MUX("clkout2", CGU, ase_pins_clkout2), + GRP_MUX("mdio", MDIO, ase_pins_mdio), + GRP_MUX("dfe led0", DFE, ase_pins_dfe_led0), + GRP_MUX("dfe led1", DFE, ase_pins_dfe_led1), + GRP_MUX("ephy led0", EPHY, ase_pins_ephy_led0), + GRP_MUX("ephy led1", EPHY, ase_pins_ephy_led1), + GRP_MUX("ephy led2", EPHY, ase_pins_ephy_led2), +}; + +static const char * const ase_exin_grps[] = {"exin0", "exin1", "exin2"}; +static const char * const ase_gpt_grps[] = {"gpt1", "gpt2", "gpt3"}; +static const char * const ase_cgu_grps[] = {"clkout0", "clkout1", + "clkout2"}; +static const char * const ase_mdio_grps[] = {"mdio"}; +static const char * const ase_dfe_grps[] = {"dfe led0", "dfe led1"}; +static const char * const ase_ephy_grps[] = {"ephy led0", "ephy led1", + "ephy led2"}; +static const char * const ase_asc_grps[] = {"asc"}; +static const char * const ase_jtag_grps[] = {"jtag"}; +static const char * const ase_stp_grps[] = {"stp"}; +static const char * const ase_spi_grps[] = {"spi", /* DEPRECATED */ + "spi_di", "spi_do", + "spi_clk", "spi_cs1", + "spi_cs2", "spi_cs3"}; + static const struct ltq_pmx_func ase_funcs[] = { {"spi", ARRAY_AND_SIZE(ase_spi_grps)}, {"asc", ARRAY_AND_SIZE(ase_asc_grps)}, + {"cgu", ARRAY_AND_SIZE(ase_cgu_grps)}, {"jtag", ARRAY_AND_SIZE(ase_jtag_grps)}, {"exin", ARRAY_AND_SIZE(ase_exin_grps)}, {"stp", ARRAY_AND_SIZE(ase_stp_grps)}, {"gpt", ARRAY_AND_SIZE(ase_gpt_grps)}, + {"mdio", ARRAY_AND_SIZE(ase_mdio_grps)}, {"ephy", ARRAY_AND_SIZE(ase_ephy_grps)}, {"dfe", ARRAY_AND_SIZE(ase_dfe_grps)}, }; +/* --------- danube related code --------- */ +#define DANUBE_MAX_PIN 32 + +static const struct ltq_mfp_pin danube_mfp[] = { + /* pin f0 f1 f2 f3 */ + MFP_XWAY(GPIO0, GPIO, EXIN, SDIO, TDM), + MFP_XWAY(GPIO1, GPIO, EXIN, CBUS, MII), + MFP_XWAY(GPIO2, GPIO, CGU, EXIN, MII), + MFP_XWAY(GPIO3, GPIO, CGU, SDIO, PCI), + MFP_XWAY(GPIO4, GPIO, STP, DFE, ASC), + MFP_XWAY(GPIO5, GPIO, STP, MII, DFE), + MFP_XWAY(GPIO6, GPIO, STP, GPT, ASC), + MFP_XWAY(GPIO7, GPIO, CGU, CBUS, MII), + MFP_XWAY(GPIO8, GPIO, CGU, NMI, MII), + MFP_XWAY(GPIO9, GPIO, ASC, SPI, MII), + MFP_XWAY(GPIO10, GPIO, ASC, SPI, MII), + MFP_XWAY(GPIO11, GPIO, ASC, CBUS, SPI), + MFP_XWAY(GPIO12, GPIO, ASC, CBUS, MCD), + MFP_XWAY(GPIO13, GPIO, EBU, SPI, MII), + MFP_XWAY(GPIO14, GPIO, CGU, CBUS, MII), + MFP_XWAY(GPIO15, GPIO, SPI, SDIO, JTAG), + MFP_XWAY(GPIO16, GPIO, SPI, SDIO, JTAG), + MFP_XWAY(GPIO17, GPIO, SPI, SDIO, JTAG), + MFP_XWAY(GPIO18, GPIO, SPI, SDIO, JTAG), + MFP_XWAY(GPIO19, GPIO, PCI, SDIO, MII), + MFP_XWAY(GPIO20, GPIO, JTAG, SDIO, MII), + MFP_XWAY(GPIO21, GPIO, PCI, EBU, GPT), + MFP_XWAY(GPIO22, GPIO, SPI, MCD, MII), + MFP_XWAY(GPIO23, GPIO, EBU, PCI, STP), + MFP_XWAY(GPIO24, GPIO, EBU, TDM, PCI), + MFP_XWAY(GPIO25, GPIO, TDM, SDIO, ASC), + MFP_XWAY(GPIO26, GPIO, EBU, TDM, SDIO), + MFP_XWAY(GPIO27, GPIO, TDM, SDIO, ASC), + MFP_XWAY(GPIO28, GPIO, GPT, MII, SDIO), + MFP_XWAY(GPIO29, GPIO, PCI, CBUS, MII), + MFP_XWAY(GPIO30, GPIO, PCI, CBUS, MII), + MFP_XWAY(GPIO31, GPIO, EBU, PCI, MII), +}; + +static const unsigned danube_exin_pin_map[] = {GPIO0, GPIO1, GPIO2}; + +static const unsigned danube_pins_exin0[] = {GPIO0}; +static const unsigned danube_pins_exin1[] = {GPIO1}; +static const unsigned danube_pins_exin2[] = {GPIO2}; + +static const unsigned danube_pins_jtag[] = {GPIO15, GPIO16, GPIO17, GPIO18, GPIO20}; +static const unsigned danube_pins_asc0[] = {GPIO11, GPIO12}; +static const unsigned danube_pins_asc0_cts_rts[] = {GPIO9, GPIO10}; +static const unsigned danube_pins_stp[] = {GPIO4, GPIO5, GPIO6}; +static const unsigned danube_pins_nmi[] = {GPIO8}; + +static const unsigned danube_pins_dfe_led0[] = {GPIO4}; +static const unsigned danube_pins_dfe_led1[] = {GPIO5}; + +static const unsigned danube_pins_ebu_a24[] = {GPIO13}; +static const unsigned danube_pins_ebu_clk[] = {GPIO21}; +static const unsigned danube_pins_ebu_cs1[] = {GPIO23}; +static const unsigned danube_pins_ebu_a23[] = {GPIO24}; +static const unsigned danube_pins_ebu_wait[] = {GPIO26}; +static const unsigned danube_pins_ebu_a25[] = {GPIO31}; + +static const unsigned danube_pins_nand_ale[] = {GPIO13}; +static const unsigned danube_pins_nand_cs1[] = {GPIO23}; +static const unsigned danube_pins_nand_cle[] = {GPIO24}; + +static const unsigned danube_pins_spi[] = {GPIO16, GPIO17, GPIO18}; /* DEPRECATED */ +static const unsigned danube_pins_spi_di[] = {GPIO16}; +static const unsigned danube_pins_spi_do[] = {GPIO17}; +static const unsigned danube_pins_spi_clk[] = {GPIO18}; +static const unsigned danube_pins_spi_cs1[] = {GPIO15}; +static const unsigned danube_pins_spi_cs2[] = {GPIO21}; +static const unsigned danube_pins_spi_cs3[] = {GPIO13}; +static const unsigned danube_pins_spi_cs4[] = {GPIO10}; +static const unsigned danube_pins_spi_cs5[] = {GPIO9}; +static const unsigned danube_pins_spi_cs6[] = {GPIO11}; + +static const unsigned danube_pins_gpt1[] = {GPIO28}; +static const unsigned danube_pins_gpt2[] = {GPIO21}; +static const unsigned danube_pins_gpt3[] = {GPIO6}; + +static const unsigned danube_pins_clkout0[] = {GPIO8}; +static const unsigned danube_pins_clkout1[] = {GPIO7}; +static const unsigned danube_pins_clkout2[] = {GPIO3}; +static const unsigned danube_pins_clkout3[] = {GPIO2}; + +static const unsigned danube_pins_pci_gnt1[] = {GPIO30}; +static const unsigned danube_pins_pci_gnt2[] = {GPIO23}; +static const unsigned danube_pins_pci_gnt3[] = {GPIO19}; +static const unsigned danube_pins_pci_req1[] = {GPIO29}; +static const unsigned danube_pins_pci_req2[] = {GPIO31}; +static const unsigned danube_pins_pci_req3[] = {GPIO3}; + +static const struct ltq_pin_group danube_grps[] = { + GRP_MUX("exin0", EXIN, danube_pins_exin0), + GRP_MUX("exin1", EXIN, danube_pins_exin1), + GRP_MUX("exin2", EXIN, danube_pins_exin2), + GRP_MUX("jtag", JTAG, danube_pins_jtag), + GRP_MUX("ebu a23", EBU, danube_pins_ebu_a23), + GRP_MUX("ebu a24", EBU, danube_pins_ebu_a24), + GRP_MUX("ebu a25", EBU, danube_pins_ebu_a25), + GRP_MUX("ebu clk", EBU, danube_pins_ebu_clk), + GRP_MUX("ebu cs1", EBU, danube_pins_ebu_cs1), + GRP_MUX("ebu wait", EBU, danube_pins_ebu_wait), + GRP_MUX("nand ale", EBU, danube_pins_nand_ale), + GRP_MUX("nand cs1", EBU, danube_pins_nand_cs1), + GRP_MUX("nand cle", EBU, danube_pins_nand_cle), + GRP_MUX("spi", SPI, danube_pins_spi), /* DEPRECATED */ + GRP_MUX("spi_di", SPI, danube_pins_spi_di), + GRP_MUX("spi_do", SPI, danube_pins_spi_do), + GRP_MUX("spi_clk", SPI, danube_pins_spi_clk), + GRP_MUX("spi_cs1", SPI, danube_pins_spi_cs1), + GRP_MUX("spi_cs2", SPI, danube_pins_spi_cs2), + GRP_MUX("spi_cs3", SPI, danube_pins_spi_cs3), + GRP_MUX("spi_cs4", SPI, danube_pins_spi_cs4), + GRP_MUX("spi_cs5", SPI, danube_pins_spi_cs5), + GRP_MUX("spi_cs6", SPI, danube_pins_spi_cs6), + GRP_MUX("asc0", ASC, danube_pins_asc0), + GRP_MUX("asc0 cts rts", ASC, danube_pins_asc0_cts_rts), + GRP_MUX("stp", STP, danube_pins_stp), + GRP_MUX("nmi", NMI, danube_pins_nmi), + GRP_MUX("gpt1", GPT, danube_pins_gpt1), + GRP_MUX("gpt2", GPT, danube_pins_gpt2), + GRP_MUX("gpt3", GPT, danube_pins_gpt3), + GRP_MUX("clkout0", CGU, danube_pins_clkout0), + GRP_MUX("clkout1", CGU, danube_pins_clkout1), + GRP_MUX("clkout2", CGU, danube_pins_clkout2), + GRP_MUX("clkout3", CGU, danube_pins_clkout3), + GRP_MUX("gnt1", PCI, danube_pins_pci_gnt1), + GRP_MUX("gnt2", PCI, danube_pins_pci_gnt2), + GRP_MUX("gnt3", PCI, danube_pins_pci_gnt3), + GRP_MUX("req1", PCI, danube_pins_pci_req1), + GRP_MUX("req2", PCI, danube_pins_pci_req2), + GRP_MUX("req3", PCI, danube_pins_pci_req3), + GRP_MUX("dfe led0", DFE, danube_pins_dfe_led0), + GRP_MUX("dfe led1", DFE, danube_pins_dfe_led1), +}; + +static const char * const danube_pci_grps[] = {"gnt1", "gnt2", + "gnt3", "req1", + "req2", "req3"}; +static const char * const danube_spi_grps[] = {"spi", /* DEPRECATED */ + "spi_di", "spi_do", + "spi_clk", "spi_cs1", + "spi_cs2", "spi_cs3", + "spi_cs4", "spi_cs5", + "spi_cs6"}; +static const char * const danube_cgu_grps[] = {"clkout0", "clkout1", + "clkout2", "clkout3"}; +static const char * const danube_ebu_grps[] = {"ebu a23", "ebu a24", + "ebu a25", "ebu cs1", + "ebu wait", "ebu clk", + "nand ale", "nand cs1", + "nand cle"}; +static const char * const danube_dfe_grps[] = {"dfe led0", "dfe led1"}; +static const char * const danube_exin_grps[] = {"exin0", "exin1", "exin2"}; +static const char * const danube_gpt_grps[] = {"gpt1", "gpt2", "gpt3"}; +static const char * const danube_asc_grps[] = {"asc0", "asc0 cts rts"}; +static const char * const danube_jtag_grps[] = {"jtag"}; +static const char * const danube_stp_grps[] = {"stp"}; +static const char * const danube_nmi_grps[] = {"nmi"}; + +static const struct ltq_pmx_func danube_funcs[] = { + {"spi", ARRAY_AND_SIZE(danube_spi_grps)}, + {"asc", ARRAY_AND_SIZE(danube_asc_grps)}, + {"cgu", ARRAY_AND_SIZE(danube_cgu_grps)}, + {"jtag", ARRAY_AND_SIZE(danube_jtag_grps)}, + {"exin", ARRAY_AND_SIZE(danube_exin_grps)}, + {"stp", ARRAY_AND_SIZE(danube_stp_grps)}, + {"gpt", ARRAY_AND_SIZE(danube_gpt_grps)}, + {"nmi", ARRAY_AND_SIZE(danube_nmi_grps)}, + {"pci", ARRAY_AND_SIZE(danube_pci_grps)}, + {"ebu", ARRAY_AND_SIZE(danube_ebu_grps)}, + {"dfe", ARRAY_AND_SIZE(danube_dfe_grps)}, +}; + +/* --------- xrx100 related code --------- */ +#define XRX100_MAX_PIN 56 + +static const struct ltq_mfp_pin xrx100_mfp[] = { + /* pin f0 f1 f2 f3 */ + MFP_XWAY(GPIO0, GPIO, EXIN, SDIO, TDM), + MFP_XWAY(GPIO1, GPIO, EXIN, CBUS, SIN), + MFP_XWAY(GPIO2, GPIO, CGU, EXIN, NONE), + MFP_XWAY(GPIO3, GPIO, CGU, SDIO, PCI), + MFP_XWAY(GPIO4, GPIO, STP, DFE, ASC), + MFP_XWAY(GPIO5, GPIO, STP, NONE, DFE), + MFP_XWAY(GPIO6, GPIO, STP, GPT, ASC), + MFP_XWAY(GPIO7, GPIO, CGU, CBUS, NONE), + MFP_XWAY(GPIO8, GPIO, CGU, NMI, NONE), + MFP_XWAY(GPIO9, GPIO, ASC, SPI, EXIN), + MFP_XWAY(GPIO10, GPIO, ASC, SPI, EXIN), + MFP_XWAY(GPIO11, GPIO, ASC, CBUS, SPI), + MFP_XWAY(GPIO12, GPIO, ASC, CBUS, MCD), + MFP_XWAY(GPIO13, GPIO, EBU, SPI, NONE), + MFP_XWAY(GPIO14, GPIO, CGU, NONE, NONE), + MFP_XWAY(GPIO15, GPIO, SPI, SDIO, MCD), + MFP_XWAY(GPIO16, GPIO, SPI, SDIO, NONE), + MFP_XWAY(GPIO17, GPIO, SPI, SDIO, NONE), + MFP_XWAY(GPIO18, GPIO, SPI, SDIO, NONE), + MFP_XWAY(GPIO19, GPIO, PCI, SDIO, CGU), + MFP_XWAY(GPIO20, GPIO, NONE, SDIO, EBU), + MFP_XWAY(GPIO21, GPIO, PCI, EBU, GPT), + MFP_XWAY(GPIO22, GPIO, SPI, NONE, EBU), + MFP_XWAY(GPIO23, GPIO, EBU, PCI, STP), + MFP_XWAY(GPIO24, GPIO, EBU, TDM, PCI), + MFP_XWAY(GPIO25, GPIO, TDM, SDIO, ASC), + MFP_XWAY(GPIO26, GPIO, EBU, TDM, SDIO), + MFP_XWAY(GPIO27, GPIO, TDM, SDIO, ASC), + MFP_XWAY(GPIO28, GPIO, GPT, NONE, SDIO), + MFP_XWAY(GPIO29, GPIO, PCI, CBUS, NONE), + MFP_XWAY(GPIO30, GPIO, PCI, CBUS, NONE), + MFP_XWAY(GPIO31, GPIO, EBU, PCI, NONE), + MFP_XWAY(GPIO32, GPIO, MII, NONE, EBU), + MFP_XWAY(GPIO33, GPIO, MII, NONE, EBU), + MFP_XWAY(GPIO34, GPIO, SIN, SSI, NONE), + MFP_XWAY(GPIO35, GPIO, SIN, SSI, NONE), + MFP_XWAY(GPIO36, GPIO, SIN, SSI, NONE), + MFP_XWAY(GPIO37, GPIO, PCI, NONE, NONE), + MFP_XWAY(GPIO38, GPIO, PCI, NONE, NONE), + MFP_XWAY(GPIO39, GPIO, NONE, EXIN, NONE), + MFP_XWAY(GPIO40, GPIO, MII, TDM, NONE), + MFP_XWAY(GPIO41, GPIO, MII, TDM, NONE), + MFP_XWAY(GPIO42, GPIO, MDIO, NONE, NONE), + MFP_XWAY(GPIO43, GPIO, MDIO, NONE, NONE), + MFP_XWAY(GPIO44, GPIO, MII, SIN, NONE), + MFP_XWAY(GPIO45, GPIO, MII, NONE, SIN), + MFP_XWAY(GPIO46, GPIO, MII, NONE, EXIN), + MFP_XWAY(GPIO47, GPIO, MII, NONE, SIN), + MFP_XWAY(GPIO48, GPIO, EBU, NONE, NONE), + MFP_XWAY(GPIO49, GPIO, EBU, NONE, NONE), + MFP_XWAY(GPIO50, GPIO, NONE, NONE, NONE), + MFP_XWAY(GPIO51, GPIO, NONE, NONE, NONE), + MFP_XWAY(GPIO52, GPIO, NONE, NONE, NONE), + MFP_XWAY(GPIO53, GPIO, NONE, NONE, NONE), + MFP_XWAY(GPIO54, GPIO, NONE, NONE, NONE), + MFP_XWAY(GPIO55, GPIO, NONE, NONE, NONE), +}; + +static const unsigned xrx100_exin_pin_map[] = {GPIO0, GPIO1, GPIO2, GPIO39, GPIO10, GPIO9}; + +static const unsigned xrx100_pins_exin0[] = {GPIO0}; +static const unsigned xrx100_pins_exin1[] = {GPIO1}; +static const unsigned xrx100_pins_exin2[] = {GPIO2}; +static const unsigned xrx100_pins_exin3[] = {GPIO39}; +static const unsigned xrx100_pins_exin4[] = {GPIO10}; +static const unsigned xrx100_pins_exin5[] = {GPIO9}; + +static const unsigned xrx100_pins_asc0[] = {GPIO11, GPIO12}; +static const unsigned xrx100_pins_asc0_cts_rts[] = {GPIO9, GPIO10}; +static const unsigned xrx100_pins_stp[] = {GPIO4, GPIO5, GPIO6}; +static const unsigned xrx100_pins_nmi[] = {GPIO8}; +static const unsigned xrx100_pins_mdio[] = {GPIO42, GPIO43}; + +static const unsigned xrx100_pins_dfe_led0[] = {GPIO4}; +static const unsigned xrx100_pins_dfe_led1[] = {GPIO5}; + +static const unsigned xrx100_pins_ebu_a24[] = {GPIO13}; +static const unsigned xrx100_pins_ebu_clk[] = {GPIO21}; +static const unsigned xrx100_pins_ebu_cs1[] = {GPIO23}; +static const unsigned xrx100_pins_ebu_a23[] = {GPIO24}; +static const unsigned xrx100_pins_ebu_wait[] = {GPIO26}; +static const unsigned xrx100_pins_ebu_a25[] = {GPIO31}; + +static const unsigned xrx100_pins_nand_ale[] = {GPIO13}; +static const unsigned xrx100_pins_nand_cs1[] = {GPIO23}; +static const unsigned xrx100_pins_nand_cle[] = {GPIO24}; +static const unsigned xrx100_pins_nand_rdy[] = {GPIO48}; +static const unsigned xrx100_pins_nand_rd[] = {GPIO49}; + +static const unsigned xrx100_pins_spi_di[] = {GPIO16}; +static const unsigned xrx100_pins_spi_do[] = {GPIO17}; +static const unsigned xrx100_pins_spi_clk[] = {GPIO18}; +static const unsigned xrx100_pins_spi_cs1[] = {GPIO15}; +static const unsigned xrx100_pins_spi_cs2[] = {GPIO22}; +static const unsigned xrx100_pins_spi_cs3[] = {GPIO13}; +static const unsigned xrx100_pins_spi_cs4[] = {GPIO10}; +static const unsigned xrx100_pins_spi_cs5[] = {GPIO9}; +static const unsigned xrx100_pins_spi_cs6[] = {GPIO11}; + +static const unsigned xrx100_pins_gpt1[] = {GPIO28}; +static const unsigned xrx100_pins_gpt2[] = {GPIO21}; +static const unsigned xrx100_pins_gpt3[] = {GPIO6}; + +static const unsigned xrx100_pins_clkout0[] = {GPIO8}; +static const unsigned xrx100_pins_clkout1[] = {GPIO7}; +static const unsigned xrx100_pins_clkout2[] = {GPIO3}; +static const unsigned xrx100_pins_clkout3[] = {GPIO2}; + +static const unsigned xrx100_pins_pci_gnt1[] = {GPIO30}; +static const unsigned xrx100_pins_pci_gnt2[] = {GPIO23}; +static const unsigned xrx100_pins_pci_gnt3[] = {GPIO19}; +static const unsigned xrx100_pins_pci_gnt4[] = {GPIO38}; +static const unsigned xrx100_pins_pci_req1[] = {GPIO29}; +static const unsigned xrx100_pins_pci_req2[] = {GPIO31}; +static const unsigned xrx100_pins_pci_req3[] = {GPIO3}; +static const unsigned xrx100_pins_pci_req4[] = {GPIO37}; + +static const struct ltq_pin_group xrx100_grps[] = { + GRP_MUX("exin0", EXIN, xrx100_pins_exin0), + GRP_MUX("exin1", EXIN, xrx100_pins_exin1), + GRP_MUX("exin2", EXIN, xrx100_pins_exin2), + GRP_MUX("exin3", EXIN, xrx100_pins_exin3), + GRP_MUX("exin4", EXIN, xrx100_pins_exin4), + GRP_MUX("exin5", EXIN, xrx100_pins_exin5), + GRP_MUX("ebu a23", EBU, xrx100_pins_ebu_a23), + GRP_MUX("ebu a24", EBU, xrx100_pins_ebu_a24), + GRP_MUX("ebu a25", EBU, xrx100_pins_ebu_a25), + GRP_MUX("ebu clk", EBU, xrx100_pins_ebu_clk), + GRP_MUX("ebu cs1", EBU, xrx100_pins_ebu_cs1), + GRP_MUX("ebu wait", EBU, xrx100_pins_ebu_wait), + GRP_MUX("nand ale", EBU, xrx100_pins_nand_ale), + GRP_MUX("nand cs1", EBU, xrx100_pins_nand_cs1), + GRP_MUX("nand cle", EBU, xrx100_pins_nand_cle), + GRP_MUX("nand rdy", EBU, xrx100_pins_nand_rdy), + GRP_MUX("nand rd", EBU, xrx100_pins_nand_rd), + GRP_MUX("spi_di", SPI, xrx100_pins_spi_di), + GRP_MUX("spi_do", SPI, xrx100_pins_spi_do), + GRP_MUX("spi_clk", SPI, xrx100_pins_spi_clk), + GRP_MUX("spi_cs1", SPI, xrx100_pins_spi_cs1), + GRP_MUX("spi_cs2", SPI, xrx100_pins_spi_cs2), + GRP_MUX("spi_cs3", SPI, xrx100_pins_spi_cs3), + GRP_MUX("spi_cs4", SPI, xrx100_pins_spi_cs4), + GRP_MUX("spi_cs5", SPI, xrx100_pins_spi_cs5), + GRP_MUX("spi_cs6", SPI, xrx100_pins_spi_cs6), + GRP_MUX("asc0", ASC, xrx100_pins_asc0), + GRP_MUX("asc0 cts rts", ASC, xrx100_pins_asc0_cts_rts), + GRP_MUX("stp", STP, xrx100_pins_stp), + GRP_MUX("nmi", NMI, xrx100_pins_nmi), + GRP_MUX("gpt1", GPT, xrx100_pins_gpt1), + GRP_MUX("gpt2", GPT, xrx100_pins_gpt2), + GRP_MUX("gpt3", GPT, xrx100_pins_gpt3), + GRP_MUX("clkout0", CGU, xrx100_pins_clkout0), + GRP_MUX("clkout1", CGU, xrx100_pins_clkout1), + GRP_MUX("clkout2", CGU, xrx100_pins_clkout2), + GRP_MUX("clkout3", CGU, xrx100_pins_clkout3), + GRP_MUX("gnt1", PCI, xrx100_pins_pci_gnt1), + GRP_MUX("gnt2", PCI, xrx100_pins_pci_gnt2), + GRP_MUX("gnt3", PCI, xrx100_pins_pci_gnt3), + GRP_MUX("gnt4", PCI, xrx100_pins_pci_gnt4), + GRP_MUX("req1", PCI, xrx100_pins_pci_req1), + GRP_MUX("req2", PCI, xrx100_pins_pci_req2), + GRP_MUX("req3", PCI, xrx100_pins_pci_req3), + GRP_MUX("req4", PCI, xrx100_pins_pci_req4), + GRP_MUX("mdio", MDIO, xrx100_pins_mdio), + GRP_MUX("dfe led0", DFE, xrx100_pins_dfe_led0), + GRP_MUX("dfe led1", DFE, xrx100_pins_dfe_led1), +}; + +static const char * const xrx100_pci_grps[] = {"gnt1", "gnt2", + "gnt3", "gnt4", + "req1", "req2", + "req3", "req4"}; +static const char * const xrx100_spi_grps[] = {"spi_di", "spi_do", + "spi_clk", "spi_cs1", + "spi_cs2", "spi_cs3", + "spi_cs4", "spi_cs5", + "spi_cs6"}; +static const char * const xrx100_cgu_grps[] = {"clkout0", "clkout1", + "clkout2", "clkout3"}; +static const char * const xrx100_ebu_grps[] = {"ebu a23", "ebu a24", + "ebu a25", "ebu cs1", + "ebu wait", "ebu clk", + "nand ale", "nand cs1", + "nand cle", "nand rdy", + "nand rd"}; +static const char * const xrx100_exin_grps[] = {"exin0", "exin1", "exin2", + "exin3", "exin4", "exin5"}; +static const char * const xrx100_gpt_grps[] = {"gpt1", "gpt2", "gpt3"}; +static const char * const xrx100_asc_grps[] = {"asc0", "asc0 cts rts"}; +static const char * const xrx100_stp_grps[] = {"stp"}; +static const char * const xrx100_nmi_grps[] = {"nmi"}; +static const char * const xrx100_mdio_grps[] = {"mdio"}; +static const char * const xrx100_dfe_grps[] = {"dfe led0", "dfe led1"}; + +static const struct ltq_pmx_func xrx100_funcs[] = { + {"spi", ARRAY_AND_SIZE(xrx100_spi_grps)}, + {"asc", ARRAY_AND_SIZE(xrx100_asc_grps)}, + {"cgu", ARRAY_AND_SIZE(xrx100_cgu_grps)}, + {"exin", ARRAY_AND_SIZE(xrx100_exin_grps)}, + {"stp", ARRAY_AND_SIZE(xrx100_stp_grps)}, + {"gpt", ARRAY_AND_SIZE(xrx100_gpt_grps)}, + {"nmi", ARRAY_AND_SIZE(xrx100_nmi_grps)}, + {"pci", ARRAY_AND_SIZE(xrx100_pci_grps)}, + {"ebu", ARRAY_AND_SIZE(xrx100_ebu_grps)}, + {"mdio", ARRAY_AND_SIZE(xrx100_mdio_grps)}, + {"dfe", ARRAY_AND_SIZE(xrx100_dfe_grps)}, +}; + +/* --------- xrx200 related code --------- */ +#define XRX200_MAX_PIN 50 + +static const struct ltq_mfp_pin xrx200_mfp[] = { + /* pin f0 f1 f2 f3 */ + MFP_XWAY(GPIO0, GPIO, EXIN, SDIO, TDM), + MFP_XWAY(GPIO1, GPIO, EXIN, CBUS, SIN), + MFP_XWAY(GPIO2, GPIO, CGU, EXIN, GPHY), + MFP_XWAY(GPIO3, GPIO, CGU, SDIO, PCI), + MFP_XWAY(GPIO4, GPIO, STP, DFE, USIF), + MFP_XWAY(GPIO5, GPIO, STP, GPHY, DFE), + MFP_XWAY(GPIO6, GPIO, STP, GPT, USIF), + MFP_XWAY(GPIO7, GPIO, CGU, CBUS, GPHY), + MFP_XWAY(GPIO8, GPIO, CGU, NMI, NONE), + MFP_XWAY(GPIO9, GPIO, USIF, SPI, EXIN), + MFP_XWAY(GPIO10, GPIO, USIF, SPI, EXIN), + MFP_XWAY(GPIO11, GPIO, USIF, CBUS, SPI), + MFP_XWAY(GPIO12, GPIO, USIF, CBUS, MCD), + MFP_XWAY(GPIO13, GPIO, EBU, SPI, NONE), + MFP_XWAY(GPIO14, GPIO, CGU, CBUS, USIF), + MFP_XWAY(GPIO15, GPIO, SPI, SDIO, MCD), + MFP_XWAY(GPIO16, GPIO, SPI, SDIO, NONE), + MFP_XWAY(GPIO17, GPIO, SPI, SDIO, NONE), + MFP_XWAY(GPIO18, GPIO, SPI, SDIO, NONE), + MFP_XWAY(GPIO19, GPIO, PCI, SDIO, CGU), + MFP_XWAY(GPIO20, GPIO, NONE, SDIO, EBU), + MFP_XWAY(GPIO21, GPIO, PCI, EBU, GPT), + MFP_XWAY(GPIO22, GPIO, SPI, CGU, EBU), + MFP_XWAY(GPIO23, GPIO, EBU, PCI, STP), + MFP_XWAY(GPIO24, GPIO, EBU, TDM, PCI), + MFP_XWAY(GPIO25, GPIO, TDM, SDIO, USIF), + MFP_XWAY(GPIO26, GPIO, EBU, TDM, SDIO), + MFP_XWAY(GPIO27, GPIO, TDM, SDIO, USIF), + MFP_XWAY(GPIO28, GPIO, GPT, PCI, SDIO), + MFP_XWAY(GPIO29, GPIO, PCI, CBUS, EXIN), + MFP_XWAY(GPIO30, GPIO, PCI, CBUS, NONE), + MFP_XWAY(GPIO31, GPIO, EBU, PCI, NONE), + MFP_XWAY(GPIO32, GPIO, MII, NONE, EBU), + MFP_XWAY(GPIO33, GPIO, MII, NONE, EBU), + MFP_XWAY(GPIO34, GPIO, SIN, SSI, NONE), + MFP_XWAY(GPIO35, GPIO, SIN, SSI, NONE), + MFP_XWAY(GPIO36, GPIO, SIN, SSI, EXIN), + MFP_XWAY(GPIO37, GPIO, USIF, NONE, PCI), + MFP_XWAY(GPIO38, GPIO, PCI, USIF, NONE), + MFP_XWAY(GPIO39, GPIO, USIF, EXIN, NONE), + MFP_XWAY(GPIO40, GPIO, MII, TDM, NONE), + MFP_XWAY(GPIO41, GPIO, MII, TDM, NONE), + MFP_XWAY(GPIO42, GPIO, MDIO, NONE, NONE), + MFP_XWAY(GPIO43, GPIO, MDIO, NONE, NONE), + MFP_XWAY(GPIO44, GPIO, MII, SIN, GPHY), + MFP_XWAY(GPIO45, GPIO, MII, GPHY, SIN), + MFP_XWAY(GPIO46, GPIO, MII, NONE, EXIN), + MFP_XWAY(GPIO47, GPIO, MII, GPHY, SIN), + MFP_XWAY(GPIO48, GPIO, EBU, NONE, NONE), + MFP_XWAY(GPIO49, GPIO, EBU, NONE, NONE), +}; + +static const unsigned xrx200_exin_pin_map[] = {GPIO0, GPIO1, GPIO2, GPIO39, GPIO10, GPIO9}; + +static const unsigned xrx200_pins_exin0[] = {GPIO0}; +static const unsigned xrx200_pins_exin1[] = {GPIO1}; +static const unsigned xrx200_pins_exin2[] = {GPIO2}; +static const unsigned xrx200_pins_exin3[] = {GPIO39}; +static const unsigned xrx200_pins_exin4[] = {GPIO10}; +static const unsigned xrx200_pins_exin5[] = {GPIO9}; + +static const unsigned xrx200_pins_usif_uart_rx[] = {GPIO11}; +static const unsigned xrx200_pins_usif_uart_tx[] = {GPIO12}; +static const unsigned xrx200_pins_usif_uart_rts[] = {GPIO9}; +static const unsigned xrx200_pins_usif_uart_cts[] = {GPIO10}; +static const unsigned xrx200_pins_usif_uart_dtr[] = {GPIO4}; +static const unsigned xrx200_pins_usif_uart_dsr[] = {GPIO6}; +static const unsigned xrx200_pins_usif_uart_dcd[] = {GPIO25}; +static const unsigned xrx200_pins_usif_uart_ri[] = {GPIO27}; + +static const unsigned xrx200_pins_usif_spi_di[] = {GPIO11}; +static const unsigned xrx200_pins_usif_spi_do[] = {GPIO12}; +static const unsigned xrx200_pins_usif_spi_clk[] = {GPIO38}; +static const unsigned xrx200_pins_usif_spi_cs0[] = {GPIO37}; +static const unsigned xrx200_pins_usif_spi_cs1[] = {GPIO39}; +static const unsigned xrx200_pins_usif_spi_cs2[] = {GPIO14}; + +static const unsigned xrx200_pins_stp[] = {GPIO4, GPIO5, GPIO6}; +static const unsigned xrx200_pins_nmi[] = {GPIO8}; +static const unsigned xrx200_pins_mdio[] = {GPIO42, GPIO43}; + +static const unsigned xrx200_pins_dfe_led0[] = {GPIO4}; +static const unsigned xrx200_pins_dfe_led1[] = {GPIO5}; + +static const unsigned xrx200_pins_gphy0_led0[] = {GPIO5}; +static const unsigned xrx200_pins_gphy0_led1[] = {GPIO7}; +static const unsigned xrx200_pins_gphy0_led2[] = {GPIO2}; +static const unsigned xrx200_pins_gphy1_led0[] = {GPIO44}; +static const unsigned xrx200_pins_gphy1_led1[] = {GPIO45}; +static const unsigned xrx200_pins_gphy1_led2[] = {GPIO47}; + +static const unsigned xrx200_pins_ebu_a24[] = {GPIO13}; +static const unsigned xrx200_pins_ebu_clk[] = {GPIO21}; +static const unsigned xrx200_pins_ebu_cs1[] = {GPIO23}; +static const unsigned xrx200_pins_ebu_a23[] = {GPIO24}; +static const unsigned xrx200_pins_ebu_wait[] = {GPIO26}; +static const unsigned xrx200_pins_ebu_a25[] = {GPIO31}; + +static const unsigned xrx200_pins_nand_ale[] = {GPIO13}; +static const unsigned xrx200_pins_nand_cs1[] = {GPIO23}; +static const unsigned xrx200_pins_nand_cle[] = {GPIO24}; +static const unsigned xrx200_pins_nand_rdy[] = {GPIO48}; +static const unsigned xrx200_pins_nand_rd[] = {GPIO49}; + +static const unsigned xrx200_pins_spi_di[] = {GPIO16}; +static const unsigned xrx200_pins_spi_do[] = {GPIO17}; +static const unsigned xrx200_pins_spi_clk[] = {GPIO18}; +static const unsigned xrx200_pins_spi_cs1[] = {GPIO15}; +static const unsigned xrx200_pins_spi_cs2[] = {GPIO22}; +static const unsigned xrx200_pins_spi_cs3[] = {GPIO13}; +static const unsigned xrx200_pins_spi_cs4[] = {GPIO10}; +static const unsigned xrx200_pins_spi_cs5[] = {GPIO9}; +static const unsigned xrx200_pins_spi_cs6[] = {GPIO11}; + +static const unsigned xrx200_pins_gpt1[] = {GPIO28}; +static const unsigned xrx200_pins_gpt2[] = {GPIO21}; +static const unsigned xrx200_pins_gpt3[] = {GPIO6}; + +static const unsigned xrx200_pins_clkout0[] = {GPIO8}; +static const unsigned xrx200_pins_clkout1[] = {GPIO7}; +static const unsigned xrx200_pins_clkout2[] = {GPIO3}; +static const unsigned xrx200_pins_clkout3[] = {GPIO2}; + +static const unsigned xrx200_pins_pci_gnt1[] = {GPIO28}; +static const unsigned xrx200_pins_pci_gnt2[] = {GPIO23}; +static const unsigned xrx200_pins_pci_gnt3[] = {GPIO19}; +static const unsigned xrx200_pins_pci_gnt4[] = {GPIO38}; +static const unsigned xrx200_pins_pci_req1[] = {GPIO29}; +static const unsigned xrx200_pins_pci_req2[] = {GPIO31}; +static const unsigned xrx200_pins_pci_req3[] = {GPIO3}; +static const unsigned xrx200_pins_pci_req4[] = {GPIO37}; + +static const struct ltq_pin_group xrx200_grps[] = { + GRP_MUX("exin0", EXIN, xrx200_pins_exin0), + GRP_MUX("exin1", EXIN, xrx200_pins_exin1), + GRP_MUX("exin2", EXIN, xrx200_pins_exin2), + GRP_MUX("exin3", EXIN, xrx200_pins_exin3), + GRP_MUX("exin4", EXIN, xrx200_pins_exin4), + GRP_MUX("exin5", EXIN, xrx200_pins_exin5), + GRP_MUX("ebu a23", EBU, xrx200_pins_ebu_a23), + GRP_MUX("ebu a24", EBU, xrx200_pins_ebu_a24), + GRP_MUX("ebu a25", EBU, xrx200_pins_ebu_a25), + GRP_MUX("ebu clk", EBU, xrx200_pins_ebu_clk), + GRP_MUX("ebu cs1", EBU, xrx200_pins_ebu_cs1), + GRP_MUX("ebu wait", EBU, xrx200_pins_ebu_wait), + GRP_MUX("nand ale", EBU, xrx200_pins_nand_ale), + GRP_MUX("nand cs1", EBU, xrx200_pins_nand_cs1), + GRP_MUX("nand cle", EBU, xrx200_pins_nand_cle), + GRP_MUX("nand rdy", EBU, xrx200_pins_nand_rdy), + GRP_MUX("nand rd", EBU, xrx200_pins_nand_rd), + GRP_MUX("spi_di", SPI, xrx200_pins_spi_di), + GRP_MUX("spi_do", SPI, xrx200_pins_spi_do), + GRP_MUX("spi_clk", SPI, xrx200_pins_spi_clk), + GRP_MUX("spi_cs1", SPI, xrx200_pins_spi_cs1), + GRP_MUX("spi_cs2", SPI, xrx200_pins_spi_cs2), + GRP_MUX("spi_cs3", SPI, xrx200_pins_spi_cs3), + GRP_MUX("spi_cs4", SPI, xrx200_pins_spi_cs4), + GRP_MUX("spi_cs5", SPI, xrx200_pins_spi_cs5), + GRP_MUX("spi_cs6", SPI, xrx200_pins_spi_cs6), + GRP_MUX("usif uart_rx", USIF, xrx200_pins_usif_uart_rx), + GRP_MUX("usif uart_rx", USIF, xrx200_pins_usif_uart_tx), + GRP_MUX("usif uart_rts", USIF, xrx200_pins_usif_uart_rts), + GRP_MUX("usif uart_cts", USIF, xrx200_pins_usif_uart_cts), + GRP_MUX("usif uart_dtr", USIF, xrx200_pins_usif_uart_dtr), + GRP_MUX("usif uart_dsr", USIF, xrx200_pins_usif_uart_dsr), + GRP_MUX("usif uart_dcd", USIF, xrx200_pins_usif_uart_dcd), + GRP_MUX("usif uart_ri", USIF, xrx200_pins_usif_uart_ri), + GRP_MUX("usif spi_di", USIF, xrx200_pins_usif_spi_di), + GRP_MUX("usif spi_do", USIF, xrx200_pins_usif_spi_do), + GRP_MUX("usif spi_clk", USIF, xrx200_pins_usif_spi_clk), + GRP_MUX("usif spi_cs0", USIF, xrx200_pins_usif_spi_cs0), + GRP_MUX("usif spi_cs1", USIF, xrx200_pins_usif_spi_cs1), + GRP_MUX("usif spi_cs2", USIF, xrx200_pins_usif_spi_cs2), + GRP_MUX("stp", STP, xrx200_pins_stp), + GRP_MUX("nmi", NMI, xrx200_pins_nmi), + GRP_MUX("gpt1", GPT, xrx200_pins_gpt1), + GRP_MUX("gpt2", GPT, xrx200_pins_gpt2), + GRP_MUX("gpt3", GPT, xrx200_pins_gpt3), + GRP_MUX("clkout0", CGU, xrx200_pins_clkout0), + GRP_MUX("clkout1", CGU, xrx200_pins_clkout1), + GRP_MUX("clkout2", CGU, xrx200_pins_clkout2), + GRP_MUX("clkout3", CGU, xrx200_pins_clkout3), + GRP_MUX("gnt1", PCI, xrx200_pins_pci_gnt1), + GRP_MUX("gnt2", PCI, xrx200_pins_pci_gnt2), + GRP_MUX("gnt3", PCI, xrx200_pins_pci_gnt3), + GRP_MUX("gnt4", PCI, xrx200_pins_pci_gnt4), + GRP_MUX("req1", PCI, xrx200_pins_pci_req1), + GRP_MUX("req2", PCI, xrx200_pins_pci_req2), + GRP_MUX("req3", PCI, xrx200_pins_pci_req3), + GRP_MUX("req4", PCI, xrx200_pins_pci_req4), + GRP_MUX("mdio", MDIO, xrx200_pins_mdio), + GRP_MUX("dfe led0", DFE, xrx200_pins_dfe_led0), + GRP_MUX("dfe led1", DFE, xrx200_pins_dfe_led1), + GRP_MUX("gphy0 led0", GPHY, xrx200_pins_gphy0_led0), + GRP_MUX("gphy0 led1", GPHY, xrx200_pins_gphy0_led1), + GRP_MUX("gphy0 led2", GPHY, xrx200_pins_gphy0_led2), + GRP_MUX("gphy1 led0", GPHY, xrx200_pins_gphy1_led0), + GRP_MUX("gphy1 led1", GPHY, xrx200_pins_gphy1_led1), + GRP_MUX("gphy1 led2", GPHY, xrx200_pins_gphy1_led2), +}; + +static const char * const xrx200_pci_grps[] = {"gnt1", "gnt2", + "gnt3", "gnt4", + "req1", "req2", + "req3", "req4"}; +static const char * const xrx200_spi_grps[] = {"spi_di", "spi_do", + "spi_clk", "spi_cs1", + "spi_cs2", "spi_cs3", + "spi_cs4", "spi_cs5", + "spi_cs6"}; +static const char * const xrx200_cgu_grps[] = {"clkout0", "clkout1", + "clkout2", "clkout3"}; +static const char * const xrx200_ebu_grps[] = {"ebu a23", "ebu a24", + "ebu a25", "ebu cs1", + "ebu wait", "ebu clk", + "nand ale", "nand cs1", + "nand cle", "nand rdy", + "nand rd"}; +static const char * const xrx200_exin_grps[] = {"exin0", "exin1", "exin2", + "exin3", "exin4", "exin5"}; +static const char * const xrx200_gpt_grps[] = {"gpt1", "gpt2", "gpt3"}; +static const char * const xrx200_usif_grps[] = {"usif uart_rx", "usif uart_tx", + "usif uart_rts", "usif uart_cts", + "usif uart_dtr", "usif uart_dsr", + "usif uart_dcd", "usif uart_ri", + "usif spi_di", "usif spi_do", + "usif spi_clk", "usif spi_cs0", + "usif spi_cs1", "usif spi_cs2"}; +static const char * const xrx200_stp_grps[] = {"stp"}; +static const char * const xrx200_nmi_grps[] = {"nmi"}; +static const char * const xrx200_mdio_grps[] = {"mdio"}; +static const char * const xrx200_dfe_grps[] = {"dfe led0", "dfe led1"}; +static const char * const xrx200_gphy_grps[] = {"gphy0 led0", "gphy0 led1", + "gphy0 led2", "gphy1 led0", + "gphy1 led1", "gphy1 led2"}; + +static const struct ltq_pmx_func xrx200_funcs[] = { + {"spi", ARRAY_AND_SIZE(xrx200_spi_grps)}, + {"usif", ARRAY_AND_SIZE(xrx200_usif_grps)}, + {"cgu", ARRAY_AND_SIZE(xrx200_cgu_grps)}, + {"exin", ARRAY_AND_SIZE(xrx200_exin_grps)}, + {"stp", ARRAY_AND_SIZE(xrx200_stp_grps)}, + {"gpt", ARRAY_AND_SIZE(xrx200_gpt_grps)}, + {"nmi", ARRAY_AND_SIZE(xrx200_nmi_grps)}, + {"pci", ARRAY_AND_SIZE(xrx200_pci_grps)}, + {"ebu", ARRAY_AND_SIZE(xrx200_ebu_grps)}, + {"mdio", ARRAY_AND_SIZE(xrx200_mdio_grps)}, + {"dfe", ARRAY_AND_SIZE(xrx200_dfe_grps)}, + {"gphy", ARRAY_AND_SIZE(xrx200_gphy_grps)}, +}; + +/* --------- xrx300 related code --------- */ +#define XRX300_MAX_PIN 64 + +static const struct ltq_mfp_pin xrx300_mfp[] = { + /* pin f0 f1 f2 f3 */ + MFP_XWAY(GPIO0, GPIO, EXIN, EPHY, NONE), + MFP_XWAY(GPIO1, GPIO, NONE, EXIN, NONE), + MFP_XWAY(GPIO2, NONE, NONE, NONE, NONE), + MFP_XWAY(GPIO3, GPIO, CGU, NONE, NONE), + MFP_XWAY(GPIO4, GPIO, STP, DFE, NONE), + MFP_XWAY(GPIO5, GPIO, STP, EPHY, DFE), + MFP_XWAY(GPIO6, GPIO, STP, NONE, NONE), + MFP_XWAY(GPIO7, NONE, NONE, NONE, NONE), + MFP_XWAY(GPIO8, GPIO, CGU, GPHY, EPHY), + MFP_XWAY(GPIO9, GPIO, WIFI, NONE, EXIN), + MFP_XWAY(GPIO10, GPIO, USIF, SPI, EXIN), + MFP_XWAY(GPIO11, GPIO, USIF, WIFI, SPI), + MFP_XWAY(GPIO12, NONE, NONE, NONE, NONE), + MFP_XWAY(GPIO13, GPIO, EBU, NONE, NONE), + MFP_XWAY(GPIO14, GPIO, CGU, USIF, EPHY), + MFP_XWAY(GPIO15, GPIO, SPI, NONE, MCD), + MFP_XWAY(GPIO16, GPIO, SPI, EXIN, NONE), + MFP_XWAY(GPIO17, GPIO, SPI, NONE, NONE), + MFP_XWAY(GPIO18, GPIO, SPI, NONE, NONE), + MFP_XWAY(GPIO19, GPIO, USIF, NONE, EPHY), + MFP_XWAY(GPIO20, NONE, NONE, NONE, NONE), + MFP_XWAY(GPIO21, NONE, NONE, NONE, NONE), + MFP_XWAY(GPIO22, NONE, NONE, NONE, NONE), + MFP_XWAY(GPIO23, GPIO, EBU, NONE, NONE), + MFP_XWAY(GPIO24, GPIO, EBU, NONE, NONE), + MFP_XWAY(GPIO25, GPIO, TDM, NONE, NONE), + MFP_XWAY(GPIO26, GPIO, TDM, NONE, NONE), + MFP_XWAY(GPIO27, GPIO, TDM, NONE, NONE), + MFP_XWAY(GPIO28, NONE, NONE, NONE, NONE), + MFP_XWAY(GPIO29, NONE, NONE, NONE, NONE), + MFP_XWAY(GPIO30, NONE, NONE, NONE, NONE), + MFP_XWAY(GPIO31, NONE, NONE, NONE, NONE), + MFP_XWAY(GPIO32, NONE, NONE, NONE, NONE), + MFP_XWAY(GPIO33, NONE, NONE, NONE, NONE), + MFP_XWAY(GPIO34, GPIO, NONE, SSI, NONE), + MFP_XWAY(GPIO35, GPIO, NONE, SSI, NONE), + MFP_XWAY(GPIO36, GPIO, NONE, SSI, NONE), + MFP_XWAY(GPIO37, NONE, NONE, NONE, NONE), + MFP_XWAY(GPIO38, NONE, NONE, NONE, NONE), + MFP_XWAY(GPIO39, NONE, NONE, NONE, NONE), + MFP_XWAY(GPIO40, NONE, NONE, NONE, NONE), + MFP_XWAY(GPIO41, NONE, NONE, NONE, NONE), + MFP_XWAY(GPIO42, GPIO, MDIO, NONE, NONE), + MFP_XWAY(GPIO43, GPIO, MDIO, NONE, NONE), + MFP_XWAY(GPIO44, NONE, NONE, NONE, NONE), + MFP_XWAY(GPIO45, NONE, NONE, NONE, NONE), + MFP_XWAY(GPIO46, NONE, NONE, NONE, NONE), + MFP_XWAY(GPIO47, NONE, NONE, NONE, NONE), + MFP_XWAY(GPIO48, GPIO, EBU, NONE, NONE), + MFP_XWAY(GPIO49, GPIO, EBU, NONE, NONE), + MFP_XWAY(GPIO50, GPIO, EBU, NONE, NONE), + MFP_XWAY(GPIO51, GPIO, EBU, NONE, NONE), + MFP_XWAY(GPIO52, GPIO, EBU, NONE, NONE), + MFP_XWAY(GPIO53, GPIO, EBU, NONE, NONE), + MFP_XWAY(GPIO54, GPIO, EBU, NONE, NONE), + MFP_XWAY(GPIO55, GPIO, EBU, NONE, NONE), + MFP_XWAY(GPIO56, GPIO, EBU, NONE, NONE), + MFP_XWAY(GPIO57, GPIO, EBU, NONE, NONE), + MFP_XWAY(GPIO58, GPIO, EBU, TDM, NONE), + MFP_XWAY(GPIO59, GPIO, EBU, NONE, NONE), + MFP_XWAY(GPIO60, GPIO, EBU, NONE, NONE), + MFP_XWAY(GPIO61, GPIO, EBU, NONE, NONE), + MFP_XWAY(GPIO62, NONE, NONE, NONE, NONE), + MFP_XWAY(GPIO63, NONE, NONE, NONE, NONE), +}; + +static const unsigned xrx300_exin_pin_map[] = {GPIO0, GPIO1, GPIO16, GPIO10, GPIO9}; + +static const unsigned xrx300_pins_exin0[] = {GPIO0}; +static const unsigned xrx300_pins_exin1[] = {GPIO1}; +static const unsigned xrx300_pins_exin2[] = {GPIO16}; +/* EXIN3 is not available on xrX300 */ +static const unsigned xrx300_pins_exin4[] = {GPIO10}; +static const unsigned xrx300_pins_exin5[] = {GPIO9}; + +static const unsigned xrx300_pins_usif_uart_rx[] = {GPIO11}; +static const unsigned xrx300_pins_usif_uart_tx[] = {GPIO10}; + +static const unsigned xrx300_pins_usif_spi_di[] = {GPIO11}; +static const unsigned xrx300_pins_usif_spi_do[] = {GPIO10}; +static const unsigned xrx300_pins_usif_spi_clk[] = {GPIO19}; +static const unsigned xrx300_pins_usif_spi_cs0[] = {GPIO14}; + +static const unsigned xrx300_pins_stp[] = {GPIO4, GPIO5, GPIO6}; +static const unsigned xrx300_pins_mdio[] = {GPIO42, GPIO43}; + +static const unsigned xrx300_pins_dfe_led0[] = {GPIO4}; +static const unsigned xrx300_pins_dfe_led1[] = {GPIO5}; + +static const unsigned xrx300_pins_ephy0_led0[] = {GPIO5}; +static const unsigned xrx300_pins_ephy0_led1[] = {GPIO8}; +static const unsigned xrx300_pins_ephy1_led0[] = {GPIO14}; +static const unsigned xrx300_pins_ephy1_led1[] = {GPIO19}; + +static const unsigned xrx300_pins_nand_ale[] = {GPIO13}; +static const unsigned xrx300_pins_nand_cs1[] = {GPIO23}; +static const unsigned xrx300_pins_nand_cle[] = {GPIO24}; +static const unsigned xrx300_pins_nand_rdy[] = {GPIO48}; +static const unsigned xrx300_pins_nand_rd[] = {GPIO49}; +static const unsigned xrx300_pins_nand_d1[] = {GPIO50}; +static const unsigned xrx300_pins_nand_d0[] = {GPIO51}; +static const unsigned xrx300_pins_nand_d2[] = {GPIO52}; +static const unsigned xrx300_pins_nand_d7[] = {GPIO53}; +static const unsigned xrx300_pins_nand_d6[] = {GPIO54}; +static const unsigned xrx300_pins_nand_d5[] = {GPIO55}; +static const unsigned xrx300_pins_nand_d4[] = {GPIO56}; +static const unsigned xrx300_pins_nand_d3[] = {GPIO57}; +static const unsigned xrx300_pins_nand_cs0[] = {GPIO58}; +static const unsigned xrx300_pins_nand_wr[] = {GPIO59}; +static const unsigned xrx300_pins_nand_wp[] = {GPIO60}; +static const unsigned xrx300_pins_nand_se[] = {GPIO61}; + +static const unsigned xrx300_pins_spi_di[] = {GPIO16}; +static const unsigned xrx300_pins_spi_do[] = {GPIO17}; +static const unsigned xrx300_pins_spi_clk[] = {GPIO18}; +static const unsigned xrx300_pins_spi_cs1[] = {GPIO15}; +/* SPI_CS2 is not available on xrX300 */ +/* SPI_CS3 is not available on xrX300 */ +static const unsigned xrx300_pins_spi_cs4[] = {GPIO10}; +/* SPI_CS5 is not available on xrX300 */ +static const unsigned xrx300_pins_spi_cs6[] = {GPIO11}; + +/* CLKOUT0 is not available on xrX300 */ +/* CLKOUT1 is not available on xrX300 */ +static const unsigned xrx300_pins_clkout2[] = {GPIO3}; + +static const struct ltq_pin_group xrx300_grps[] = { + GRP_MUX("exin0", EXIN, xrx300_pins_exin0), + GRP_MUX("exin1", EXIN, xrx300_pins_exin1), + GRP_MUX("exin2", EXIN, xrx300_pins_exin2), + GRP_MUX("exin4", EXIN, xrx300_pins_exin4), + GRP_MUX("exin5", EXIN, xrx300_pins_exin5), + GRP_MUX("nand ale", EBU, xrx300_pins_nand_ale), + GRP_MUX("nand cs1", EBU, xrx300_pins_nand_cs1), + GRP_MUX("nand cle", EBU, xrx300_pins_nand_cle), + GRP_MUX("nand rdy", EBU, xrx300_pins_nand_rdy), + GRP_MUX("nand rd", EBU, xrx300_pins_nand_rd), + GRP_MUX("nand d1", EBU, xrx300_pins_nand_d1), + GRP_MUX("nand d0", EBU, xrx300_pins_nand_d0), + GRP_MUX("nand d2", EBU, xrx300_pins_nand_d2), + GRP_MUX("nand d7", EBU, xrx300_pins_nand_d7), + GRP_MUX("nand d6", EBU, xrx300_pins_nand_d6), + GRP_MUX("nand d5", EBU, xrx300_pins_nand_d5), + GRP_MUX("nand d4", EBU, xrx300_pins_nand_d4), + GRP_MUX("nand d3", EBU, xrx300_pins_nand_d3), + GRP_MUX("nand cs0", EBU, xrx300_pins_nand_cs0), + GRP_MUX("nand wr", EBU, xrx300_pins_nand_wr), + GRP_MUX("nand wp", EBU, xrx300_pins_nand_wp), + GRP_MUX("nand se", EBU, xrx300_pins_nand_se), + GRP_MUX("spi_di", SPI, xrx300_pins_spi_di), + GRP_MUX("spi_do", SPI, xrx300_pins_spi_do), + GRP_MUX("spi_clk", SPI, xrx300_pins_spi_clk), + GRP_MUX("spi_cs1", SPI, xrx300_pins_spi_cs1), + GRP_MUX("spi_cs4", SPI, xrx300_pins_spi_cs4), + GRP_MUX("spi_cs6", SPI, xrx300_pins_spi_cs6), + GRP_MUX("usif uart_rx", USIF, xrx300_pins_usif_uart_rx), + GRP_MUX("usif uart_tx", USIF, xrx300_pins_usif_uart_tx), + GRP_MUX("usif spi_di", USIF, xrx300_pins_usif_spi_di), + GRP_MUX("usif spi_do", USIF, xrx300_pins_usif_spi_do), + GRP_MUX("usif spi_clk", USIF, xrx300_pins_usif_spi_clk), + GRP_MUX("usif spi_cs0", USIF, xrx300_pins_usif_spi_cs0), + GRP_MUX("stp", STP, xrx300_pins_stp), + GRP_MUX("clkout2", CGU, xrx300_pins_clkout2), + GRP_MUX("mdio", MDIO, xrx300_pins_mdio), + GRP_MUX("dfe led0", DFE, xrx300_pins_dfe_led0), + GRP_MUX("dfe led1", DFE, xrx300_pins_dfe_led1), + GRP_MUX("ephy0 led0", GPHY, xrx300_pins_ephy0_led0), + GRP_MUX("ephy0 led1", GPHY, xrx300_pins_ephy0_led1), + GRP_MUX("ephy1 led0", GPHY, xrx300_pins_ephy1_led0), + GRP_MUX("ephy1 led1", GPHY, xrx300_pins_ephy1_led1), +}; + +static const char * const xrx300_spi_grps[] = {"spi_di", "spi_do", + "spi_clk", "spi_cs1", + "spi_cs4", "spi_cs6"}; +static const char * const xrx300_cgu_grps[] = {"clkout2"}; +static const char * const xrx300_ebu_grps[] = {"nand ale", "nand cs1", + "nand cle", "nand rdy", + "nand rd", "nand d1", + "nand d0", "nand d2", + "nand d7", "nand d6", + "nand d5", "nand d4", + "nand d3", "nand cs0", + "nand wr", "nand wp", + "nand se"}; +static const char * const xrx300_exin_grps[] = {"exin0", "exin1", "exin2", + "exin4", "exin5"}; +static const char * const xrx300_usif_grps[] = {"usif uart_rx", "usif uart_tx", + "usif spi_di", "usif spi_do", + "usif spi_clk", "usif spi_cs0"}; +static const char * const xrx300_stp_grps[] = {"stp"}; +static const char * const xrx300_mdio_grps[] = {"mdio"}; +static const char * const xrx300_dfe_grps[] = {"dfe led0", "dfe led1"}; +static const char * const xrx300_gphy_grps[] = {"ephy0 led0", "ephy0 led1", + "ephy1 led0", "ephy1 led1"}; + +static const struct ltq_pmx_func xrx300_funcs[] = { + {"spi", ARRAY_AND_SIZE(xrx300_spi_grps)}, + {"usif", ARRAY_AND_SIZE(xrx300_usif_grps)}, + {"cgu", ARRAY_AND_SIZE(xrx300_cgu_grps)}, + {"exin", ARRAY_AND_SIZE(xrx300_exin_grps)}, + {"stp", ARRAY_AND_SIZE(xrx300_stp_grps)}, + {"ebu", ARRAY_AND_SIZE(xrx300_ebu_grps)}, + {"mdio", ARRAY_AND_SIZE(xrx300_mdio_grps)}, + {"dfe", ARRAY_AND_SIZE(xrx300_dfe_grps)}, + {"ephy", ARRAY_AND_SIZE(xrx300_gphy_grps)}, +}; + /* --------- pinconf related code --------- */ static int xway_pinconf_get(struct pinctrl_dev *pctldev, unsigned pin, @@ -695,10 +1582,7 @@ static struct gpio_chip xway_chip = { /* --------- register the pinctrl layer --------- */ -static const unsigned xway_exin_pin_map[] = {GPIO0, GPIO1, GPIO2, GPIO39, GPIO46, GPIO9}; -static const unsigned ase_exin_pins_map[] = {GPIO6, GPIO29, GPIO0}; - -static struct pinctrl_xway_soc { +struct pinctrl_xway_soc { int pin_count; const struct ltq_mfp_pin *mfp; const struct ltq_pin_group *grps; @@ -707,22 +1591,54 @@ static struct pinctrl_xway_soc { unsigned int num_funcs; const unsigned *exin; unsigned int num_exin; -} soc_cfg[] = { - /* legacy xway */ - {XWAY_MAX_PIN, xway_mfp, - xway_grps, ARRAY_SIZE(xway_grps), - danube_funcs, ARRAY_SIZE(danube_funcs), - xway_exin_pin_map, 3}, - /* xway xr9 series */ - {XR9_MAX_PIN, xway_mfp, - xway_grps, ARRAY_SIZE(xway_grps), - xrx_funcs, ARRAY_SIZE(xrx_funcs), - xway_exin_pin_map, 6}, - /* xway ase series */ - {XWAY_MAX_PIN, ase_mfp, - ase_grps, ARRAY_SIZE(ase_grps), - ase_funcs, ARRAY_SIZE(ase_funcs), - ase_exin_pins_map, 3}, +}; + +/* xway xr9 series (DEPRECATED: Use XWAY xRX100/xRX200 Family) */ +static struct pinctrl_xway_soc xr9_pinctrl = { + XR9_MAX_PIN, xway_mfp, + xway_grps, ARRAY_SIZE(xway_grps), + xrx_funcs, ARRAY_SIZE(xrx_funcs), + xway_exin_pin_map, 6 +}; + +/* XWAY AMAZON Family */ +static struct pinctrl_xway_soc ase_pinctrl = { + ASE_MAX_PIN, ase_mfp, + ase_grps, ARRAY_SIZE(ase_grps), + ase_funcs, ARRAY_SIZE(ase_funcs), + ase_exin_pin_map, 3 +}; + +/* XWAY DANUBE Family */ +static struct pinctrl_xway_soc danube_pinctrl = { + DANUBE_MAX_PIN, danube_mfp, + danube_grps, ARRAY_SIZE(danube_grps), + danube_funcs, ARRAY_SIZE(danube_funcs), + danube_exin_pin_map, 3 +}; + +/* XWAY xRX100 Family */ +static struct pinctrl_xway_soc xrx100_pinctrl = { + XRX100_MAX_PIN, xrx100_mfp, + xrx100_grps, ARRAY_SIZE(xrx100_grps), + xrx100_funcs, ARRAY_SIZE(xrx100_funcs), + xrx100_exin_pin_map, 6 +}; + +/* XWAY xRX200 Family */ +static struct pinctrl_xway_soc xrx200_pinctrl = { + XRX200_MAX_PIN, xrx200_mfp, + xrx200_grps, ARRAY_SIZE(xrx200_grps), + xrx200_funcs, ARRAY_SIZE(xrx200_funcs), + xrx200_exin_pin_map, 6 +}; + +/* XWAY xRX300 Family */ +static struct pinctrl_xway_soc xrx300_pinctrl = { + XRX300_MAX_PIN, xrx300_mfp, + xrx300_grps, ARRAY_SIZE(xrx300_grps), + xrx300_funcs, ARRAY_SIZE(xrx300_funcs), + xrx300_exin_pin_map, 5 }; static struct pinctrl_gpio_range xway_gpio_range = { @@ -731,9 +1647,14 @@ static struct pinctrl_gpio_range xway_gpio_range = { }; static const struct of_device_id xway_match[] = { - { .compatible = "lantiq,pinctrl-xway", .data = &soc_cfg[0]}, - { .compatible = "lantiq,pinctrl-xr9", .data = &soc_cfg[1]}, - { .compatible = "lantiq,pinctrl-ase", .data = &soc_cfg[2]}, + { .compatible = "lantiq,pinctrl-xway", .data = &danube_pinctrl}, /*DEPRECATED*/ + { .compatible = "lantiq,pinctrl-xr9", .data = &xr9_pinctrl}, /*DEPRECATED*/ + { .compatible = "lantiq,pinctrl-ase", .data = &ase_pinctrl}, /*DEPRECATED*/ + { .compatible = "lantiq,ase-pinctrl", .data = &ase_pinctrl}, + { .compatible = "lantiq,danube-pinctrl", .data = &danube_pinctrl}, + { .compatible = "lantiq,xrx100-pinctrl", .data = &xrx100_pinctrl}, + { .compatible = "lantiq,xrx200-pinctrl", .data = &xrx200_pinctrl}, + { .compatible = "lantiq,xrx300-pinctrl", .data = &xrx300_pinctrl}, {}, }; MODULE_DEVICE_TABLE(of, xway_match); @@ -755,7 +1676,7 @@ static int pinmux_xway_probe(struct platform_device *pdev) if (match) xway_soc = (const struct pinctrl_xway_soc *) match->data; else - xway_soc = &soc_cfg[0]; + xway_soc = &danube_pinctrl; /* find out how many pads we have */ xway_chip.ngpio = xway_soc->pin_count; -- cgit v0.10.2 From 57b588c950b7e04e0f22393ad439299ba4fda9c3 Mon Sep 17 00:00:00 2001 From: John Crispin Date: Thu, 26 Nov 2015 11:00:09 +0100 Subject: pinctrl/lantiq: Fix GPIO Setup of GPIO Port3 Some special handling of GPIO Port 3 is needed because of some hardware thingofabob. Signed-off-by: John Crispin Signed-off-by: Martin Schiller Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/pinctrl-xway.c b/drivers/pinctrl/pinctrl-xway.c index a064962..b78baaa 100644 --- a/drivers/pinctrl/pinctrl-xway.c +++ b/drivers/pinctrl/pinctrl-xway.c @@ -1563,6 +1563,10 @@ static int xway_gpio_dir_out(struct gpio_chip *chip, unsigned int pin, int val) { struct ltq_pinmux_info *info = dev_get_drvdata(chip->dev); + if (PORT(pin) == PORT3) + gpio_setbit(info->membase[0], GPIO3_OD, PORT_PIN(pin)); + else + gpio_setbit(info->membase[0], GPIO_OD(pin), PORT_PIN(pin)); gpio_setbit(info->membase[0], GPIO_DIR(pin), PORT_PIN(pin)); xway_gpio_set(chip, pin, val); -- cgit v0.10.2 From dcd803bebcfc0fae9c2d3d5063210e9225fe4b1b Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 20 Oct 2015 19:33:00 +0200 Subject: pinctrl: sh-pfc: Add PINMUX_SINGLE() Add a macro to describe a pinmux configuration for a single-function pin. Signed-off-by: Geert Uytterhoeven Acked-by: Kuninori Morimoto Acked-by: Laurent Pinchart diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h index 7b373d43..fb2de52 100644 --- a/drivers/pinctrl/sh-pfc/sh_pfc.h +++ b/drivers/pinctrl/sh-pfc/sh_pfc.h @@ -199,6 +199,14 @@ struct sh_pfc_soc_info { PINMUX_DATA(fn##_MARK, FN_##ms, FN_##ipsr, FN_##fn) /* + * Describe a pinmux configuration for a single-function pin with GPIO + * capability. + * - fn: Function name + */ +#define PINMUX_SINGLE(fn) \ + PINMUX_DATA(fn##_MARK, FN_##fn) + +/* * GP port style (32 ports banks) */ -- cgit v0.10.2 From 01af9ecbd7bd7d688c54d73a7fa8f7e10ab29d8c Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 20 Oct 2015 19:34:41 +0200 Subject: pinctrl: sh-pfc: r8a7790: Use PINMUX_SINGLE() instead of raw PINMUX_DATA() Signed-off-by: Geert Uytterhoeven Acked-by: Kuninori Morimoto Acked-by: Laurent Pinchart diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c index d9924b0..1acad99 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c @@ -806,15 +806,15 @@ enum { static const u16 pinmux_data[] = { PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */ - PINMUX_DATA(VI1_DATA7_VI1_B7_MARK, FN_VI1_DATA7_VI1_B7), - PINMUX_DATA(USB0_PWEN_MARK, FN_USB0_PWEN), - PINMUX_DATA(USB0_OVC_VBUS_MARK, FN_USB0_OVC_VBUS), - PINMUX_DATA(USB2_PWEN_MARK, FN_USB2_PWEN), - PINMUX_DATA(USB2_OVC_MARK, FN_USB2_OVC), - PINMUX_DATA(AVS1_MARK, FN_AVS1), - PINMUX_DATA(AVS2_MARK, FN_AVS2), - PINMUX_DATA(DU_DOTCLKIN0_MARK, FN_DU_DOTCLKIN0), - PINMUX_DATA(DU_DOTCLKIN2_MARK, FN_DU_DOTCLKIN2), + PINMUX_SINGLE(VI1_DATA7_VI1_B7), + PINMUX_SINGLE(USB0_PWEN), + PINMUX_SINGLE(USB0_OVC_VBUS), + PINMUX_SINGLE(USB2_PWEN), + PINMUX_SINGLE(USB2_OVC), + PINMUX_SINGLE(AVS1), + PINMUX_SINGLE(AVS2), + PINMUX_SINGLE(DU_DOTCLKIN0), + PINMUX_SINGLE(DU_DOTCLKIN2), PINMUX_IPSR_DATA(IP0_2_0, D0), PINMUX_IPSR_MSEL(IP0_2_0, MSIOF3_SCK_B, SEL_SOF3_1), -- cgit v0.10.2 From bc3341ddaea26756c76965a7e0e95c6a8e01c857 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 20 Oct 2015 19:34:56 +0200 Subject: pinctrl: sh-pfc: r8a7791: Use PINMUX_SINGLE() instead of raw PINMUX_DATA() Signed-off-by: Geert Uytterhoeven Acked-by: Kuninori Morimoto Acked-by: Laurent Pinchart diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c index 87a4f44..ebadd28 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c @@ -787,23 +787,23 @@ enum { static const u16 pinmux_data[] = { PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */ - PINMUX_DATA(EX_CS0_N_MARK, FN_EX_CS0_N), - PINMUX_DATA(RD_N_MARK, FN_RD_N), - PINMUX_DATA(AUDIO_CLKA_MARK, FN_AUDIO_CLKA), - PINMUX_DATA(VI0_CLK_MARK, FN_VI0_CLK), - PINMUX_DATA(VI0_DATA0_VI0_B0_MARK, FN_VI0_DATA0_VI0_B0), - PINMUX_DATA(VI0_DATA1_VI0_B1_MARK, FN_VI0_DATA1_VI0_B1), - PINMUX_DATA(VI0_DATA2_VI0_B2_MARK, FN_VI0_DATA2_VI0_B2), - PINMUX_DATA(VI0_DATA4_VI0_B4_MARK, FN_VI0_DATA4_VI0_B4), - PINMUX_DATA(VI0_DATA5_VI0_B5_MARK, FN_VI0_DATA5_VI0_B5), - PINMUX_DATA(VI0_DATA6_VI0_B6_MARK, FN_VI0_DATA6_VI0_B6), - PINMUX_DATA(VI0_DATA7_VI0_B7_MARK, FN_VI0_DATA7_VI0_B7), - PINMUX_DATA(USB0_PWEN_MARK, FN_USB0_PWEN), - PINMUX_DATA(USB0_OVC_MARK, FN_USB0_OVC), - PINMUX_DATA(USB1_PWEN_MARK, FN_USB1_PWEN), - PINMUX_DATA(USB1_OVC_MARK, FN_USB1_OVC), - PINMUX_DATA(DU0_DOTCLKIN_MARK, FN_DU0_DOTCLKIN), - PINMUX_DATA(SD1_CLK_MARK, FN_SD1_CLK), + PINMUX_SINGLE(EX_CS0_N), + PINMUX_SINGLE(RD_N), + PINMUX_SINGLE(AUDIO_CLKA), + PINMUX_SINGLE(VI0_CLK), + PINMUX_SINGLE(VI0_DATA0_VI0_B0), + PINMUX_SINGLE(VI0_DATA1_VI0_B1), + PINMUX_SINGLE(VI0_DATA2_VI0_B2), + PINMUX_SINGLE(VI0_DATA4_VI0_B4), + PINMUX_SINGLE(VI0_DATA5_VI0_B5), + PINMUX_SINGLE(VI0_DATA6_VI0_B6), + PINMUX_SINGLE(VI0_DATA7_VI0_B7), + PINMUX_SINGLE(USB0_PWEN), + PINMUX_SINGLE(USB0_OVC), + PINMUX_SINGLE(USB1_PWEN), + PINMUX_SINGLE(USB1_OVC), + PINMUX_SINGLE(DU0_DOTCLKIN), + PINMUX_SINGLE(SD1_CLK), /* IPSR0 */ PINMUX_IPSR_DATA(IP0_0, D0), -- cgit v0.10.2 From 61a483ff80e19846de5ab9c9ccadd11f3c11f982 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 20 Oct 2015 19:35:02 +0200 Subject: pinctrl: sh-pfc: r8a7794: Use PINMUX_SINGLE() instead of raw PINMUX_DATA() Signed-off-by: Geert Uytterhoeven Acked-by: Kuninori Morimoto Acked-by: Laurent Pinchart diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7794.c b/drivers/pinctrl/sh-pfc/pfc-r8a7794.c index 086f679..3324ee7 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7794.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7794.c @@ -618,28 +618,28 @@ enum { static const u16 pinmux_data[] = { PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */ - PINMUX_DATA(A2_MARK, FN_A2), - PINMUX_DATA(WE0_N_MARK, FN_WE0_N), - PINMUX_DATA(WE1_N_MARK, FN_WE1_N), - PINMUX_DATA(DACK0_MARK, FN_DACK0), - PINMUX_DATA(USB0_PWEN_MARK, FN_USB0_PWEN), - PINMUX_DATA(USB0_OVC_MARK, FN_USB0_OVC), - PINMUX_DATA(USB1_PWEN_MARK, FN_USB1_PWEN), - PINMUX_DATA(USB1_OVC_MARK, FN_USB1_OVC), - PINMUX_DATA(SD0_CLK_MARK, FN_SD0_CLK), - PINMUX_DATA(SD0_CMD_MARK, FN_SD0_CMD), - PINMUX_DATA(SD0_DATA0_MARK, FN_SD0_DATA0), - PINMUX_DATA(SD0_DATA1_MARK, FN_SD0_DATA1), - PINMUX_DATA(SD0_DATA2_MARK, FN_SD0_DATA2), - PINMUX_DATA(SD0_DATA3_MARK, FN_SD0_DATA3), - PINMUX_DATA(SD0_CD_MARK, FN_SD0_CD), - PINMUX_DATA(SD0_WP_MARK, FN_SD0_WP), - PINMUX_DATA(SD1_CLK_MARK, FN_SD1_CLK), - PINMUX_DATA(SD1_CMD_MARK, FN_SD1_CMD), - PINMUX_DATA(SD1_DATA0_MARK, FN_SD1_DATA0), - PINMUX_DATA(SD1_DATA1_MARK, FN_SD1_DATA1), - PINMUX_DATA(SD1_DATA2_MARK, FN_SD1_DATA2), - PINMUX_DATA(SD1_DATA3_MARK, FN_SD1_DATA3), + PINMUX_SINGLE(A2), + PINMUX_SINGLE(WE0_N), + PINMUX_SINGLE(WE1_N), + PINMUX_SINGLE(DACK0), + PINMUX_SINGLE(USB0_PWEN), + PINMUX_SINGLE(USB0_OVC), + PINMUX_SINGLE(USB1_PWEN), + PINMUX_SINGLE(USB1_OVC), + PINMUX_SINGLE(SD0_CLK), + PINMUX_SINGLE(SD0_CMD), + PINMUX_SINGLE(SD0_DATA0), + PINMUX_SINGLE(SD0_DATA1), + PINMUX_SINGLE(SD0_DATA2), + PINMUX_SINGLE(SD0_DATA3), + PINMUX_SINGLE(SD0_CD), + PINMUX_SINGLE(SD0_WP), + PINMUX_SINGLE(SD1_CLK), + PINMUX_SINGLE(SD1_CMD), + PINMUX_SINGLE(SD1_DATA0), + PINMUX_SINGLE(SD1_DATA1), + PINMUX_SINGLE(SD1_DATA2), + PINMUX_SINGLE(SD1_DATA3), /* IPSR0 */ PINMUX_IPSR_DATA(IP0_0, SD1_CD), -- cgit v0.10.2 From b8856085c3184d0360b018af2a94a9d414a9214d Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 28 Oct 2015 10:17:55 +0100 Subject: pinctrl: sh-pfc: r8a7795: Make PORT_GP_x() macros consistent On r8a7795, PORT_GP_x() is a macro for defining GPIOs 0..x. In all other sh-pfc code, PORT_GP_x() is a macro for defining GPIOs 0..(x-1). Make the r8a7795 macro definitions consistent with the rest of the sh-pfc codebase. Signed-off-by: Geert Uytterhoeven Acked-by: Linus Walleij Acked-by: Laurent Pinchart diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c index 7ddb2ad..29d001b 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c @@ -13,12 +13,12 @@ #include "core.h" #include "sh_pfc.h" -#define PORT_GP_3(bank, fn, sfx) \ +#define PORT_GP_4(bank, fn, sfx) \ PORT_GP_1(bank, 0, fn, sfx), PORT_GP_1(bank, 1, fn, sfx), \ PORT_GP_1(bank, 2, fn, sfx), PORT_GP_1(bank, 3, fn, sfx) -#define PORT_GP_14(bank, fn, sfx) \ - PORT_GP_3(bank, fn, sfx), \ +#define PORT_GP_15(bank, fn, sfx) \ + PORT_GP_4(bank, fn, sfx), \ PORT_GP_1(bank, 4, fn, sfx), PORT_GP_1(bank, 5, fn, sfx), \ PORT_GP_1(bank, 6, fn, sfx), PORT_GP_1(bank, 7, fn, sfx), \ PORT_GP_1(bank, 8, fn, sfx), PORT_GP_1(bank, 9, fn, sfx), \ @@ -26,33 +26,33 @@ PORT_GP_1(bank, 12, fn, sfx), PORT_GP_1(bank, 13, fn, sfx), \ PORT_GP_1(bank, 14, fn, sfx) -#define PORT_GP_15(bank, fn, sfx) \ - PORT_GP_14(bank, fn, sfx), PORT_GP_1(bank, 15, fn, sfx) +#define PORT_GP_16(bank, fn, sfx) \ + PORT_GP_15(bank, fn, sfx), PORT_GP_1(bank, 15, fn, sfx) -#define PORT_GP_17(bank, fn, sfx) \ - PORT_GP_15(bank, fn, sfx), \ +#define PORT_GP_18(bank, fn, sfx) \ + PORT_GP_16(bank, fn, sfx), \ PORT_GP_1(bank, 16, fn, sfx), PORT_GP_1(bank, 17, fn, sfx) -#define PORT_GP_25(bank, fn, sfx) \ - PORT_GP_17(bank, fn, sfx), \ +#define PORT_GP_26(bank, fn, sfx) \ + PORT_GP_18(bank, fn, sfx), \ PORT_GP_1(bank, 18, fn, sfx), PORT_GP_1(bank, 19, fn, sfx), \ PORT_GP_1(bank, 20, fn, sfx), PORT_GP_1(bank, 21, fn, sfx), \ PORT_GP_1(bank, 22, fn, sfx), PORT_GP_1(bank, 23, fn, sfx), \ PORT_GP_1(bank, 24, fn, sfx), PORT_GP_1(bank, 25, fn, sfx) -#define PORT_GP_27(bank, fn, sfx) \ - PORT_GP_25(bank, fn, sfx), \ +#define PORT_GP_28(bank, fn, sfx) \ + PORT_GP_26(bank, fn, sfx), \ PORT_GP_1(bank, 26, fn, sfx), PORT_GP_1(bank, 27, fn, sfx) #define CPU_ALL_PORT(fn, sfx) \ - PORT_GP_15(0, fn, sfx), \ - PORT_GP_27(1, fn, sfx), \ - PORT_GP_14(2, fn, sfx), \ - PORT_GP_15(3, fn, sfx), \ - PORT_GP_17(4, fn, sfx), \ - PORT_GP_25(5, fn, sfx), \ + PORT_GP_16(0, fn, sfx), \ + PORT_GP_28(1, fn, sfx), \ + PORT_GP_15(2, fn, sfx), \ + PORT_GP_16(3, fn, sfx), \ + PORT_GP_18(4, fn, sfx), \ + PORT_GP_26(5, fn, sfx), \ PORT_GP_32(6, fn, sfx), \ - PORT_GP_3(7, fn, sfx) + PORT_GP_4(7, fn, sfx) /* * F_() : just information * FM() : macro for FN_xxx / xxx_MARK -- cgit v0.10.2 From fd1aa743b070d79bf08ba3f1f96d8c660f48944d Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 9 Nov 2015 09:56:21 +0100 Subject: pinctrl: sh-pfc: r8a7795: Rename SEL_SCIF to SEL_SATA Cfr. Manual Errata for Rev 0.50 of the R-Car Gen3 datasheet. This has no user-visible impact. Signed-off-by: Geert Uytterhoeven Acked-by: Linus Walleij diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c index 29d001b..bb5f37c 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c @@ -495,7 +495,7 @@ FM(IP16_31_28) IP16_31_28 #define MOD_SEL1_13 FM(SEL_SCIF3_0) FM(SEL_SCIF3_1) #define MOD_SEL1_12 FM(SEL_SCIF2_0) FM(SEL_SCIF2_1) #define MOD_SEL1_11 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1) -#define MOD_SEL1_10 FM(SEL_SCIF_0) FM(SEL_SCIF_1) +#define MOD_SEL1_10 FM(SEL_SATA_0) FM(SEL_SATA_1) #define MOD_SEL1_9 FM(SEL_REMOCON_0) FM(SEL_REMOCON_1) #define MOD_SEL1_6 FM(SEL_RCAN0_0) FM(SEL_RCAN0_1) #define MOD_SEL1_5 FM(SEL_PWM6_0) FM(SEL_PWM6_1) @@ -1033,7 +1033,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_DATA(IP9_19_16, SD2_DAT3), PINMUX_IPSR_DATA(IP9_23_20, SD2_DS), - PINMUX_IPSR_MSEL(IP9_23_20, SATA_DEVSLP_B, SEL_SCIF_1), + PINMUX_IPSR_MSEL(IP9_23_20, SATA_DEVSLP_B, SEL_SATA_1), PINMUX_IPSR_DATA(IP9_27_24, SD3_DAT4), PINMUX_IPSR_MSEL(IP9_27_24, SD2_CD_A, SEL_SDHI2_0), @@ -1293,7 +1293,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_DATA(IP15_11_8, SSI_SDATA6), PINMUX_IPSR_MSEL(IP15_11_8, SIM0_CLK_D, SEL_SIMCARD_3), - PINMUX_IPSR_MSEL(IP15_11_8, SATA_DEVSLP_A, SEL_SCIF_0), + PINMUX_IPSR_MSEL(IP15_11_8, SATA_DEVSLP_A, SEL_SATA_0), PINMUX_IPSR_DATA(IP15_15_12, SSI_SCK78), PINMUX_IPSR_MSEL(IP15_15_12, HRX2_B, SEL_HSCIF2_1), -- cgit v0.10.2 From a56069c46c102710721e003e2423ca377d99687b Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 26 Aug 2015 19:35:58 +0200 Subject: pinctrl: sh-pfc: r8a7795: Add HSCIF pins, groups, and functions Signed-off-by: Geert Uytterhoeven Acked-by: Linus Walleij diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c index bb5f37c..bb28d73 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c @@ -1612,6 +1612,191 @@ static const unsigned int avb_avtp_capture_b_mux[] = { AVB_AVTP_CAPTURE_B_MARK, }; +/* - HSCIF0 ----------------------------------------------------------------- */ +static const unsigned int hscif0_data_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14), +}; +static const unsigned int hscif0_data_mux[] = { + HRX0_MARK, HTX0_MARK, +}; +static const unsigned int hscif0_clk_pins[] = { + /* SCK */ + RCAR_GP_PIN(5, 12), +}; +static const unsigned int hscif0_clk_mux[] = { + HSCK0_MARK, +}; +static const unsigned int hscif0_ctrl_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 15), +}; +static const unsigned int hscif0_ctrl_mux[] = { + HRTS0_N_MARK, HCTS0_N_MARK, +}; +/* - HSCIF1 ----------------------------------------------------------------- */ +static const unsigned int hscif1_data_a_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6), +}; +static const unsigned int hscif1_data_a_mux[] = { + HRX1_A_MARK, HTX1_A_MARK, +}; +static const unsigned int hscif1_clk_a_pins[] = { + /* SCK */ + RCAR_GP_PIN(6, 21), +}; +static const unsigned int hscif1_clk_a_mux[] = { + HSCK1_A_MARK, +}; +static const unsigned int hscif1_ctrl_a_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7), +}; +static const unsigned int hscif1_ctrl_a_mux[] = { + HRTS1_N_A_MARK, HCTS1_N_A_MARK, +}; + +static const unsigned int hscif1_data_b_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2), +}; +static const unsigned int hscif1_data_b_mux[] = { + HRX1_B_MARK, HTX1_B_MARK, +}; +static const unsigned int hscif1_clk_b_pins[] = { + /* SCK */ + RCAR_GP_PIN(5, 0), +}; +static const unsigned int hscif1_clk_b_mux[] = { + HSCK1_B_MARK, +}; +static const unsigned int hscif1_ctrl_b_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3), +}; +static const unsigned int hscif1_ctrl_b_mux[] = { + HRTS1_N_B_MARK, HCTS1_N_B_MARK, +}; +/* - HSCIF2 ----------------------------------------------------------------- */ +static const unsigned int hscif2_data_a_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9), +}; +static const unsigned int hscif2_data_a_mux[] = { + HRX2_A_MARK, HTX2_A_MARK, +}; +static const unsigned int hscif2_clk_a_pins[] = { + /* SCK */ + RCAR_GP_PIN(6, 10), +}; +static const unsigned int hscif2_clk_a_mux[] = { + HSCK2_A_MARK, +}; +static const unsigned int hscif2_ctrl_a_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6), +}; +static const unsigned int hscif2_ctrl_a_mux[] = { + HRTS2_N_A_MARK, HCTS2_N_A_MARK, +}; + +static const unsigned int hscif2_data_b_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18), +}; +static const unsigned int hscif2_data_b_mux[] = { + HRX2_B_MARK, HTX2_B_MARK, +}; +static const unsigned int hscif2_clk_b_pins[] = { + /* SCK */ + RCAR_GP_PIN(6, 21), +}; +static const unsigned int hscif2_clk_b_mux[] = { + HSCK1_B_MARK, +}; +static const unsigned int hscif2_ctrl_b_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 19), +}; +static const unsigned int hscif2_ctrl_b_mux[] = { + HRTS2_N_B_MARK, HCTS2_N_B_MARK, +}; +/* - HSCIF3 ----------------------------------------------------------------- */ +static const unsigned int hscif3_data_a_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24), +}; +static const unsigned int hscif3_data_a_mux[] = { + HRX3_A_MARK, HTX3_A_MARK, +}; +static const unsigned int hscif3_clk_pins[] = { + /* SCK */ + RCAR_GP_PIN(1, 22), +}; +static const unsigned int hscif3_clk_mux[] = { + HSCK3_MARK, +}; +static const unsigned int hscif3_ctrl_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25), +}; +static const unsigned int hscif3_ctrl_mux[] = { + HRTS3_N_MARK, HCTS3_N_MARK, +}; + +static const unsigned int hscif3_data_b_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), +}; +static const unsigned int hscif3_data_b_mux[] = { + HRX3_B_MARK, HTX3_B_MARK, +}; +static const unsigned int hscif3_data_c_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), +}; +static const unsigned int hscif3_data_c_mux[] = { + HRX3_C_MARK, HTX3_C_MARK, +}; +static const unsigned int hscif3_data_d_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), +}; +static const unsigned int hscif3_data_d_mux[] = { + HRX3_D_MARK, HTX3_D_MARK, +}; +/* - HSCIF4 ----------------------------------------------------------------- */ +static const unsigned int hscif4_data_a_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13), +}; +static const unsigned int hscif4_data_a_mux[] = { + HRX4_A_MARK, HTX4_A_MARK, +}; +static const unsigned int hscif4_clk_pins[] = { + /* SCK */ + RCAR_GP_PIN(1, 11), +}; +static const unsigned int hscif4_clk_mux[] = { + HSCK4_MARK, +}; +static const unsigned int hscif4_ctrl_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), +}; +static const unsigned int hscif4_ctrl_mux[] = { + HRTS4_N_MARK, HCTS3_N_MARK, +}; + +static const unsigned int hscif4_data_b_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11), +}; +static const unsigned int hscif4_data_b_mux[] = { + HRX4_B_MARK, HTX4_B_MARK, +}; + /* - I2C -------------------------------------------------------------------- */ static const unsigned int i2c1_a_pins[] = { /* SDA, SCL */ @@ -2050,6 +2235,31 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(avb_avtp_capture_a), SH_PFC_PIN_GROUP(avb_avtp_match_b), SH_PFC_PIN_GROUP(avb_avtp_capture_b), + SH_PFC_PIN_GROUP(hscif0_data), + SH_PFC_PIN_GROUP(hscif0_clk), + SH_PFC_PIN_GROUP(hscif0_ctrl), + SH_PFC_PIN_GROUP(hscif1_data_a), + SH_PFC_PIN_GROUP(hscif1_clk_a), + SH_PFC_PIN_GROUP(hscif1_ctrl_a), + SH_PFC_PIN_GROUP(hscif1_data_b), + SH_PFC_PIN_GROUP(hscif1_clk_b), + SH_PFC_PIN_GROUP(hscif1_ctrl_b), + SH_PFC_PIN_GROUP(hscif2_data_a), + SH_PFC_PIN_GROUP(hscif2_clk_a), + SH_PFC_PIN_GROUP(hscif2_ctrl_a), + SH_PFC_PIN_GROUP(hscif2_data_b), + SH_PFC_PIN_GROUP(hscif2_clk_b), + SH_PFC_PIN_GROUP(hscif2_ctrl_b), + SH_PFC_PIN_GROUP(hscif3_data_a), + SH_PFC_PIN_GROUP(hscif3_clk), + SH_PFC_PIN_GROUP(hscif3_ctrl), + SH_PFC_PIN_GROUP(hscif3_data_b), + SH_PFC_PIN_GROUP(hscif3_data_c), + SH_PFC_PIN_GROUP(hscif3_data_d), + SH_PFC_PIN_GROUP(hscif4_data_a), + SH_PFC_PIN_GROUP(hscif4_clk), + SH_PFC_PIN_GROUP(hscif4_ctrl), + SH_PFC_PIN_GROUP(hscif4_data_b), SH_PFC_PIN_GROUP(i2c1_a), SH_PFC_PIN_GROUP(i2c1_b), SH_PFC_PIN_GROUP(i2c2_a), @@ -2141,6 +2351,46 @@ static const char * const avb_groups[] = { "avb_avtp_capture_b", }; +static const char * const hscif0_groups[] = { + "hscif0_data", + "hscif0_clk", + "hscif0_ctrl", +}; + +static const char * const hscif1_groups[] = { + "hscif1_data_a", + "hscif1_clk_a", + "hscif1_ctrl_a", + "hscif1_data_b", + "hscif1_clk_b", + "hscif1_ctrl_b", +}; + +static const char * const hscif2_groups[] = { + "hscif2_data_a", + "hscif2_clk_a", + "hscif2_ctrl_a", + "hscif2_data_b", + "hscif2_clk_b", + "hscif2_ctrl_b", +}; + +static const char * const hscif3_groups[] = { + "hscif3_data_a", + "hscif3_clk", + "hscif3_ctrl", + "hscif3_data_b", + "hscif3_data_c", + "hscif3_data_d", +}; + +static const char * const hscif4_groups[] = { + "hscif4_data_a", + "hscif4_clk", + "hscif4_ctrl", + "hscif4_data_b", +}; + static const char * const i2c1_groups[] = { "i2c1_a", "i2c1_b", @@ -2231,6 +2481,11 @@ static const char * const ssi_groups[] = { static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(audio_clk), SH_PFC_FUNCTION(avb), + SH_PFC_FUNCTION(hscif0), + SH_PFC_FUNCTION(hscif1), + SH_PFC_FUNCTION(hscif2), + SH_PFC_FUNCTION(hscif3), + SH_PFC_FUNCTION(hscif4), SH_PFC_FUNCTION(i2c1), SH_PFC_FUNCTION(i2c2), SH_PFC_FUNCTION(i2c6), -- cgit v0.10.2 From 2d24fe675ae1824402987fbf626ce34c461760bb Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Wed, 11 Nov 2015 14:29:59 +0900 Subject: pinctrl: sh-pfc: Share/reuse same PORT_GP_x() macros Many SoC needs each PORT_GP_x() macros, but we can share/reuse same one. Signed-off-by: Kuninori Morimoto Acked-by: Laurent Pinchart Signed-off-by: Geert Uytterhoeven diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c index ed4e078..7293e37 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c @@ -23,13 +23,6 @@ #include "sh_pfc.h" -#define PORT_GP_9(bank, fn, sfx) \ - PORT_GP_1(bank, 0, fn, sfx), PORT_GP_1(bank, 1, fn, sfx), \ - PORT_GP_1(bank, 2, fn, sfx), PORT_GP_1(bank, 3, fn, sfx), \ - PORT_GP_1(bank, 4, fn, sfx), PORT_GP_1(bank, 5, fn, sfx), \ - PORT_GP_1(bank, 6, fn, sfx), PORT_GP_1(bank, 7, fn, sfx), \ - PORT_GP_1(bank, 8, fn, sfx) - #define CPU_ALL_PORT(fn, sfx) \ PORT_GP_32(0, fn, sfx), \ PORT_GP_32(1, fn, sfx), \ diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c index 1acad99..d99a5bc 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c @@ -26,23 +26,6 @@ #include "core.h" #include "sh_pfc.h" -#define PORT_GP_30(bank, fn, sfx) \ - PORT_GP_1(bank, 0, fn, sfx), PORT_GP_1(bank, 1, fn, sfx), \ - PORT_GP_1(bank, 2, fn, sfx), PORT_GP_1(bank, 3, fn, sfx), \ - PORT_GP_1(bank, 4, fn, sfx), PORT_GP_1(bank, 5, fn, sfx), \ - PORT_GP_1(bank, 6, fn, sfx), PORT_GP_1(bank, 7, fn, sfx), \ - PORT_GP_1(bank, 8, fn, sfx), PORT_GP_1(bank, 9, fn, sfx), \ - PORT_GP_1(bank, 10, fn, sfx), PORT_GP_1(bank, 11, fn, sfx), \ - PORT_GP_1(bank, 12, fn, sfx), PORT_GP_1(bank, 13, fn, sfx), \ - PORT_GP_1(bank, 14, fn, sfx), PORT_GP_1(bank, 15, fn, sfx), \ - PORT_GP_1(bank, 16, fn, sfx), PORT_GP_1(bank, 17, fn, sfx), \ - PORT_GP_1(bank, 18, fn, sfx), PORT_GP_1(bank, 19, fn, sfx), \ - PORT_GP_1(bank, 20, fn, sfx), PORT_GP_1(bank, 21, fn, sfx), \ - PORT_GP_1(bank, 22, fn, sfx), PORT_GP_1(bank, 23, fn, sfx), \ - PORT_GP_1(bank, 24, fn, sfx), PORT_GP_1(bank, 25, fn, sfx), \ - PORT_GP_1(bank, 26, fn, sfx), PORT_GP_1(bank, 27, fn, sfx), \ - PORT_GP_1(bank, 28, fn, sfx), PORT_GP_1(bank, 29, fn, sfx) - #define CPU_ALL_PORT(fn, sfx) \ PORT_GP_32(0, fn, sfx), \ PORT_GP_30(1, fn, sfx), \ diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c index ebadd28..10a9673 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c @@ -13,21 +13,6 @@ #include "core.h" #include "sh_pfc.h" -#define PORT_GP_26(bank, fn, sfx) \ - PORT_GP_1(bank, 0, fn, sfx), PORT_GP_1(bank, 1, fn, sfx), \ - PORT_GP_1(bank, 2, fn, sfx), PORT_GP_1(bank, 3, fn, sfx), \ - PORT_GP_1(bank, 4, fn, sfx), PORT_GP_1(bank, 5, fn, sfx), \ - PORT_GP_1(bank, 6, fn, sfx), PORT_GP_1(bank, 7, fn, sfx), \ - PORT_GP_1(bank, 8, fn, sfx), PORT_GP_1(bank, 9, fn, sfx), \ - PORT_GP_1(bank, 10, fn, sfx), PORT_GP_1(bank, 11, fn, sfx), \ - PORT_GP_1(bank, 12, fn, sfx), PORT_GP_1(bank, 13, fn, sfx), \ - PORT_GP_1(bank, 14, fn, sfx), PORT_GP_1(bank, 15, fn, sfx), \ - PORT_GP_1(bank, 16, fn, sfx), PORT_GP_1(bank, 17, fn, sfx), \ - PORT_GP_1(bank, 18, fn, sfx), PORT_GP_1(bank, 19, fn, sfx), \ - PORT_GP_1(bank, 20, fn, sfx), PORT_GP_1(bank, 21, fn, sfx), \ - PORT_GP_1(bank, 22, fn, sfx), PORT_GP_1(bank, 23, fn, sfx), \ - PORT_GP_1(bank, 24, fn, sfx), PORT_GP_1(bank, 25, fn, sfx) - #define CPU_ALL_PORT(fn, sfx) \ PORT_GP_32(0, fn, sfx), \ PORT_GP_26(1, fn, sfx), \ diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7794.c b/drivers/pinctrl/sh-pfc/pfc-r8a7794.c index 3324ee7..10995fa 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7794.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7794.c @@ -15,25 +15,6 @@ #include "core.h" #include "sh_pfc.h" -#define PORT_GP_26(bank, fn, sfx) \ - PORT_GP_1(bank, 0, fn, sfx), PORT_GP_1(bank, 1, fn, sfx), \ - PORT_GP_1(bank, 2, fn, sfx), PORT_GP_1(bank, 3, fn, sfx), \ - PORT_GP_1(bank, 4, fn, sfx), PORT_GP_1(bank, 5, fn, sfx), \ - PORT_GP_1(bank, 6, fn, sfx), PORT_GP_1(bank, 7, fn, sfx), \ - PORT_GP_1(bank, 8, fn, sfx), PORT_GP_1(bank, 9, fn, sfx), \ - PORT_GP_1(bank, 10, fn, sfx), PORT_GP_1(bank, 11, fn, sfx), \ - PORT_GP_1(bank, 12, fn, sfx), PORT_GP_1(bank, 13, fn, sfx), \ - PORT_GP_1(bank, 14, fn, sfx), PORT_GP_1(bank, 15, fn, sfx), \ - PORT_GP_1(bank, 16, fn, sfx), PORT_GP_1(bank, 17, fn, sfx), \ - PORT_GP_1(bank, 18, fn, sfx), PORT_GP_1(bank, 19, fn, sfx), \ - PORT_GP_1(bank, 20, fn, sfx), PORT_GP_1(bank, 21, fn, sfx), \ - PORT_GP_1(bank, 22, fn, sfx), PORT_GP_1(bank, 23, fn, sfx), \ - PORT_GP_1(bank, 24, fn, sfx), PORT_GP_1(bank, 25, fn, sfx) - -#define PORT_GP_28(bank, fn, sfx) \ - PORT_GP_26(bank, fn, sfx), \ - PORT_GP_1(bank, 26, fn, sfx), PORT_GP_1(bank, 27, fn, sfx) - #define CPU_ALL_PORT(fn, sfx) \ PORT_GP_32(0, fn, sfx), \ PORT_GP_26(1, fn, sfx), \ diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c index bb28d73..79984b3 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c @@ -13,37 +13,6 @@ #include "core.h" #include "sh_pfc.h" -#define PORT_GP_4(bank, fn, sfx) \ - PORT_GP_1(bank, 0, fn, sfx), PORT_GP_1(bank, 1, fn, sfx), \ - PORT_GP_1(bank, 2, fn, sfx), PORT_GP_1(bank, 3, fn, sfx) - -#define PORT_GP_15(bank, fn, sfx) \ - PORT_GP_4(bank, fn, sfx), \ - PORT_GP_1(bank, 4, fn, sfx), PORT_GP_1(bank, 5, fn, sfx), \ - PORT_GP_1(bank, 6, fn, sfx), PORT_GP_1(bank, 7, fn, sfx), \ - PORT_GP_1(bank, 8, fn, sfx), PORT_GP_1(bank, 9, fn, sfx), \ - PORT_GP_1(bank, 10, fn, sfx), PORT_GP_1(bank, 11, fn, sfx), \ - PORT_GP_1(bank, 12, fn, sfx), PORT_GP_1(bank, 13, fn, sfx), \ - PORT_GP_1(bank, 14, fn, sfx) - -#define PORT_GP_16(bank, fn, sfx) \ - PORT_GP_15(bank, fn, sfx), PORT_GP_1(bank, 15, fn, sfx) - -#define PORT_GP_18(bank, fn, sfx) \ - PORT_GP_16(bank, fn, sfx), \ - PORT_GP_1(bank, 16, fn, sfx), PORT_GP_1(bank, 17, fn, sfx) - -#define PORT_GP_26(bank, fn, sfx) \ - PORT_GP_18(bank, fn, sfx), \ - PORT_GP_1(bank, 18, fn, sfx), PORT_GP_1(bank, 19, fn, sfx), \ - PORT_GP_1(bank, 20, fn, sfx), PORT_GP_1(bank, 21, fn, sfx), \ - PORT_GP_1(bank, 22, fn, sfx), PORT_GP_1(bank, 23, fn, sfx), \ - PORT_GP_1(bank, 24, fn, sfx), PORT_GP_1(bank, 25, fn, sfx) - -#define PORT_GP_28(bank, fn, sfx) \ - PORT_GP_26(bank, fn, sfx), \ - PORT_GP_1(bank, 26, fn, sfx), PORT_GP_1(bank, 27, fn, sfx) - #define CPU_ALL_PORT(fn, sfx) \ PORT_GP_16(0, fn, sfx), \ PORT_GP_28(1, fn, sfx), \ diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7734.c b/drivers/pinctrl/sh-pfc/pfc-sh7734.c index e7deb51..9d66865 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh7734.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh7734.c @@ -14,14 +14,6 @@ #include "sh_pfc.h" -#define PORT_GP_12(bank, fn, sfx) \ - PORT_GP_1(bank, 0, fn, sfx), PORT_GP_1(bank, 1, fn, sfx), \ - PORT_GP_1(bank, 2, fn, sfx), PORT_GP_1(bank, 3, fn, sfx), \ - PORT_GP_1(bank, 4, fn, sfx), PORT_GP_1(bank, 5, fn, sfx), \ - PORT_GP_1(bank, 6, fn, sfx), PORT_GP_1(bank, 7, fn, sfx), \ - PORT_GP_1(bank, 8, fn, sfx), PORT_GP_1(bank, 9, fn, sfx), \ - PORT_GP_1(bank, 10, fn, sfx), PORT_GP_1(bank, 11, fn, sfx) - #define CPU_ALL_PORT(fn, sfx) \ PORT_GP_32(0, fn, sfx), \ PORT_GP_32(1, fn, sfx), \ diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h index fb2de52..2123ab4 100644 --- a/drivers/pinctrl/sh-pfc/sh_pfc.h +++ b/drivers/pinctrl/sh-pfc/sh_pfc.h @@ -213,22 +213,68 @@ struct sh_pfc_soc_info { #define PORT_GP_CFG_1(bank, pin, fn, sfx, cfg) fn(bank, pin, GP_##bank##_##pin, sfx, cfg) #define PORT_GP_1(bank, pin, fn, sfx) PORT_GP_CFG_1(bank, pin, fn, sfx, 0) -#define PORT_GP_CFG_32(bank, fn, sfx, cfg) \ +#define PORT_GP_CFG_4(bank, fn, sfx, cfg) \ PORT_GP_CFG_1(bank, 0, fn, sfx, cfg), PORT_GP_CFG_1(bank, 1, fn, sfx, cfg), \ - PORT_GP_CFG_1(bank, 2, fn, sfx, cfg), PORT_GP_CFG_1(bank, 3, fn, sfx, cfg), \ + PORT_GP_CFG_1(bank, 2, fn, sfx, cfg), PORT_GP_CFG_1(bank, 3, fn, sfx, cfg) +#define PORT_GP_4(bank, fn, sfx) PORT_GP_CFG_4(bank, fn, sfx, 0) + +#define PORT_GP_CFG_8(bank, fn, sfx, cfg) \ + PORT_GP_CFG_4(bank, fn, sfx, cfg), \ PORT_GP_CFG_1(bank, 4, fn, sfx, cfg), PORT_GP_CFG_1(bank, 5, fn, sfx, cfg), \ - PORT_GP_CFG_1(bank, 6, fn, sfx, cfg), PORT_GP_CFG_1(bank, 7, fn, sfx, cfg), \ + PORT_GP_CFG_1(bank, 6, fn, sfx, cfg), PORT_GP_CFG_1(bank, 7, fn, sfx, cfg) +#define PORT_GP_8(bank, fn, sfx) PORT_GP_CFG_8(bank, fn, sfx, 0) + +#define PORT_GP_CFG_9(bank, fn, sfx, cfg) \ + PORT_GP_CFG_8(bank, fn, sfx, cfg), \ + PORT_GP_CFG_1(bank, 8, fn, sfx, cfg) +#define PORT_GP_9(bank, fn, sfx) PORT_GP_CFG_9(bank, fn, sfx, 0) + +#define PORT_GP_CFG_12(bank, fn, sfx, cfg) \ + PORT_GP_CFG_8(bank, fn, sfx, cfg), \ PORT_GP_CFG_1(bank, 8, fn, sfx, cfg), PORT_GP_CFG_1(bank, 9, fn, sfx, cfg), \ - PORT_GP_CFG_1(bank, 10, fn, sfx, cfg), PORT_GP_CFG_1(bank, 11, fn, sfx, cfg), \ - PORT_GP_CFG_1(bank, 12, fn, sfx, cfg), PORT_GP_CFG_1(bank, 13, fn, sfx, cfg), \ - PORT_GP_CFG_1(bank, 14, fn, sfx, cfg), PORT_GP_CFG_1(bank, 15, fn, sfx, cfg), \ - PORT_GP_CFG_1(bank, 16, fn, sfx, cfg), PORT_GP_CFG_1(bank, 17, fn, sfx, cfg), \ + PORT_GP_CFG_1(bank, 10, fn, sfx, cfg), PORT_GP_CFG_1(bank, 11, fn, sfx, cfg) +#define PORT_GP_12(bank, fn, sfx) PORT_GP_CFG_12(bank, fn, sfx, 0) + +#define PORT_GP_CFG_14(bank, fn, sfx, cfg) \ + PORT_GP_CFG_12(bank, fn, sfx, cfg), \ + PORT_GP_CFG_1(bank, 12, fn, sfx, cfg), PORT_GP_CFG_1(bank, 13, fn, sfx, cfg) +#define PORT_GP_14(bank, fn, sfx) PORT_GP_CFG_14(bank, fn, sfx, 0) + +#define PORT_GP_CFG_15(bank, fn, sfx, cfg) \ + PORT_GP_CFG_14(bank, fn, sfx, cfg), \ + PORT_GP_CFG_1(bank, 14, fn, sfx, cfg) +#define PORT_GP_15(bank, fn, sfx) PORT_GP_CFG_15(bank, fn, sfx, 0) + +#define PORT_GP_CFG_16(bank, fn, sfx, cfg) \ + PORT_GP_CFG_14(bank, fn, sfx, cfg), \ + PORT_GP_CFG_1(bank, 14, fn, sfx, cfg), PORT_GP_CFG_1(bank, 15, fn, sfx, cfg) +#define PORT_GP_16(bank, fn, sfx) PORT_GP_CFG_16(bank, fn, sfx, 0) + +#define PORT_GP_CFG_18(bank, fn, sfx, cfg) \ + PORT_GP_CFG_16(bank, fn, sfx, cfg), \ + PORT_GP_CFG_1(bank, 16, fn, sfx, cfg), PORT_GP_CFG_1(bank, 17, fn, sfx, cfg) +#define PORT_GP_18(bank, fn, sfx) PORT_GP_CFG_18(bank, fn, sfx, 0) + +#define PORT_GP_CFG_26(bank, fn, sfx, cfg) \ + PORT_GP_CFG_18(bank, fn, sfx, cfg), \ PORT_GP_CFG_1(bank, 18, fn, sfx, cfg), PORT_GP_CFG_1(bank, 19, fn, sfx, cfg), \ PORT_GP_CFG_1(bank, 20, fn, sfx, cfg), PORT_GP_CFG_1(bank, 21, fn, sfx, cfg), \ PORT_GP_CFG_1(bank, 22, fn, sfx, cfg), PORT_GP_CFG_1(bank, 23, fn, sfx, cfg), \ - PORT_GP_CFG_1(bank, 24, fn, sfx, cfg), PORT_GP_CFG_1(bank, 25, fn, sfx, cfg), \ - PORT_GP_CFG_1(bank, 26, fn, sfx, cfg), PORT_GP_CFG_1(bank, 27, fn, sfx, cfg), \ - PORT_GP_CFG_1(bank, 28, fn, sfx, cfg), PORT_GP_CFG_1(bank, 29, fn, sfx, cfg), \ + PORT_GP_CFG_1(bank, 24, fn, sfx, cfg), PORT_GP_CFG_1(bank, 25, fn, sfx, cfg) +#define PORT_GP_26(bank, fn, sfx) PORT_GP_CFG_26(bank, fn, sfx, 0) + +#define PORT_GP_CFG_28(bank, fn, sfx, cfg) \ + PORT_GP_CFG_26(bank, fn, sfx, cfg), \ + PORT_GP_CFG_1(bank, 26, fn, sfx, cfg), PORT_GP_CFG_1(bank, 27, fn, sfx, cfg) +#define PORT_GP_28(bank, fn, sfx) PORT_GP_CFG_28(bank, fn, sfx, 0) + +#define PORT_GP_CFG_30(bank, fn, sfx, cfg) \ + PORT_GP_CFG_28(bank, fn, sfx, cfg), \ + PORT_GP_CFG_1(bank, 28, fn, sfx, cfg), PORT_GP_CFG_1(bank, 29, fn, sfx, cfg) +#define PORT_GP_30(bank, fn, sfx) PORT_GP_CFG_30(bank, fn, sfx, 0) + +#define PORT_GP_CFG_32(bank, fn, sfx, cfg) \ + PORT_GP_CFG_30(bank, fn, sfx, cfg), \ PORT_GP_CFG_1(bank, 30, fn, sfx, cfg), PORT_GP_CFG_1(bank, 31, fn, sfx, cfg) #define PORT_GP_32(bank, fn, sfx) PORT_GP_CFG_32(bank, fn, sfx, 0) -- cgit v0.10.2 From beee39099b9041c8bcb50e771d0cc6aea4e79e45 Mon Sep 17 00:00:00 2001 From: Timur Tabi Date: Tue, 10 Nov 2015 09:57:10 -0600 Subject: pinctrl: qcom: qdf2xxx: improve error checking and reporting MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The driver doesn't report an error message if the ACPI tables are missing the num-gpios property (which indicates how many GPIOs there are on this SOC), and it didn't check to ensure that the mallocs didn't fail. Signed-off-by: Timur Tabi Reviewed-by: Björn Andersson Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/qcom/pinctrl-qdf2xxx.c b/drivers/pinctrl/qcom/pinctrl-qdf2xxx.c index e9ff3bc..f448534 100644 --- a/drivers/pinctrl/qcom/pinctrl-qdf2xxx.c +++ b/drivers/pinctrl/qcom/pinctrl-qdf2xxx.c @@ -32,6 +32,9 @@ static struct msm_pinctrl_soc_data qdf2xxx_pinctrl; +/* A reasonable limit to the number of GPIOS */ +#define MAX_GPIOS 256 + static int qdf2xxx_pinctrl_probe(struct platform_device *pdev) { struct pinctrl_pin_desc *pins; @@ -42,11 +45,13 @@ static int qdf2xxx_pinctrl_probe(struct platform_device *pdev) /* Query the number of GPIOs from ACPI */ ret = device_property_read_u32(&pdev->dev, "num-gpios", &num_gpios); - if (ret < 0) + if (ret < 0) { + dev_warn(&pdev->dev, "missing num-gpios property\n"); return ret; + } - if (!num_gpios) { - dev_warn(&pdev->dev, "missing num-gpios property\n"); + if (!num_gpios || num_gpios > MAX_GPIOS) { + dev_warn(&pdev->dev, "invalid num-gpios property\n"); return -ENODEV; } @@ -55,6 +60,9 @@ static int qdf2xxx_pinctrl_probe(struct platform_device *pdev) groups = devm_kcalloc(&pdev->dev, num_gpios, sizeof(struct msm_pingroup), GFP_KERNEL); + if (!pins || !groups) + return -ENOMEM; + for (i = 0; i < num_gpios; i++) { pins[i].number = i; -- cgit v0.10.2 From ab4256cfeab91569e1d96e7f0014538fe0845259 Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Wed, 18 Nov 2015 11:33:17 -0800 Subject: pinctrl: qcom: pmic-gpio/mpp: of_irq_count() == npins MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The number of interrupts is always equal to the number of pins provided by the PMIC gpio and MPP hardware blocks. Count the number of irqs to figure out the number of pins instead of adding more compatible strings or doing math on the reg property. This should make the code more generic and ease the number of changes we have to make to the driver for each new pmic revision. Cc: Ivan T. Ivanov Signed-off-by: Stephen Boyd Reviewed-by: Andy Gross Reviewed-by: Björn Andersson Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c b/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c index 6c42ca1..543cdd6 100644 --- a/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c +++ b/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -693,16 +694,15 @@ static int pmic_gpio_probe(struct platform_device *pdev) struct pmic_gpio_pad *pad, *pads; struct pmic_gpio_state *state; int ret, npins, i; - u32 res[2]; + u32 reg; - ret = of_property_read_u32_array(dev->of_node, "reg", res, 2); + ret = of_property_read_u32(dev->of_node, "reg", ®); if (ret < 0) { - dev_err(dev, "missing base address and/or range"); + dev_err(dev, "missing base address"); return ret; } - npins = res[1] / PMIC_GPIO_ADDRESS_RANGE; - + npins = of_irq_count(dev->of_node); if (!npins) return -EINVAL; @@ -752,7 +752,7 @@ static int pmic_gpio_probe(struct platform_device *pdev) if (pad->irq < 0) return pad->irq; - pad->base = res[0] + i * PMIC_GPIO_ADDRESS_RANGE; + pad->base = reg + i * PMIC_GPIO_ADDRESS_RANGE; ret = pmic_gpio_populate(state, pad); if (ret < 0) diff --git a/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c b/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c index 9ce0e30..d778fb9 100644 --- a/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c +++ b/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -795,15 +796,15 @@ static int pmic_mpp_probe(struct platform_device *pdev) struct pmic_mpp_pad *pad, *pads; struct pmic_mpp_state *state; int ret, npins, i; - u32 res[2]; + u32 reg; - ret = of_property_read_u32_array(dev->of_node, "reg", res, 2); + ret = of_property_read_u32(dev->of_node, "reg", ®); if (ret < 0) { - dev_err(dev, "missing base address and/or range"); + dev_err(dev, "missing base address"); return ret; } - npins = res[1] / PMIC_MPP_ADDRESS_RANGE; + npins = of_irq_count(dev->of_node); if (!npins) return -EINVAL; @@ -854,7 +855,7 @@ static int pmic_mpp_probe(struct platform_device *pdev) if (pad->irq < 0) return pad->irq; - pad->base = res[0] + i * PMIC_MPP_ADDRESS_RANGE; + pad->base = reg + i * PMIC_MPP_ADDRESS_RANGE; ret = pmic_mpp_populate(state, pad); if (ret < 0) diff --git a/drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c b/drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c index d809c9e..78fa228 100644 --- a/drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c +++ b/drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c @@ -23,6 +23,7 @@ #include #include #include +#include #include @@ -650,11 +651,12 @@ static int pm8xxx_pin_populate(struct pm8xxx_gpio *pctrl, } static const struct of_device_id pm8xxx_gpio_of_match[] = { - { .compatible = "qcom,pm8018-gpio", .data = (void *)6 }, - { .compatible = "qcom,pm8038-gpio", .data = (void *)12 }, - { .compatible = "qcom,pm8058-gpio", .data = (void *)40 }, - { .compatible = "qcom,pm8917-gpio", .data = (void *)38 }, - { .compatible = "qcom,pm8921-gpio", .data = (void *)44 }, + { .compatible = "qcom,pm8018-gpio" }, + { .compatible = "qcom,pm8038-gpio" }, + { .compatible = "qcom,pm8058-gpio" }, + { .compatible = "qcom,pm8917-gpio" }, + { .compatible = "qcom,pm8921-gpio" }, + { .compatible = "qcom,ssbi-gpio" }, { }, }; MODULE_DEVICE_TABLE(of, pm8xxx_gpio_of_match); @@ -672,7 +674,9 @@ static int pm8xxx_gpio_probe(struct platform_device *pdev) return -ENOMEM; pctrl->dev = &pdev->dev; - pctrl->npins = (unsigned)of_device_get_match_data(&pdev->dev); + pctrl->npins = of_irq_count(pdev->dev.of_node); + if (!pctrl->npins) + return -EINVAL; pctrl->regmap = dev_get_regmap(pdev->dev.parent, NULL); if (!pctrl->regmap) { diff --git a/drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c b/drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c index 8982027..0831063 100644 --- a/drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c +++ b/drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c @@ -23,6 +23,7 @@ #include #include #include +#include #include @@ -741,11 +742,12 @@ static int pm8xxx_pin_populate(struct pm8xxx_mpp *pctrl, } static const struct of_device_id pm8xxx_mpp_of_match[] = { - { .compatible = "qcom,pm8018-mpp", .data = (void *)6 }, - { .compatible = "qcom,pm8038-mpp", .data = (void *)6 }, - { .compatible = "qcom,pm8917-mpp", .data = (void *)10 }, - { .compatible = "qcom,pm8821-mpp", .data = (void *)4 }, - { .compatible = "qcom,pm8921-mpp", .data = (void *)12 }, + { .compatible = "qcom,pm8018-mpp" }, + { .compatible = "qcom,pm8038-mpp" }, + { .compatible = "qcom,pm8917-mpp" }, + { .compatible = "qcom,pm8821-mpp" }, + { .compatible = "qcom,pm8921-mpp" }, + { .compatible = "qcom,ssbi-mpp" }, { }, }; MODULE_DEVICE_TABLE(of, pm8xxx_mpp_of_match); @@ -763,7 +765,9 @@ static int pm8xxx_mpp_probe(struct platform_device *pdev) return -ENOMEM; pctrl->dev = &pdev->dev; - pctrl->npins = (unsigned)of_device_get_match_data(&pdev->dev); + pctrl->npins = of_irq_count(pdev->dev.of_node); + if (!pctrl->npins) + return -EINVAL; pctrl->regmap = dev_get_regmap(pdev->dev.parent, NULL); if (!pctrl->regmap) { -- cgit v0.10.2 From d1b49b68609c673f70a6da4858cc16d7749df6a3 Mon Sep 17 00:00:00 2001 From: Joonwoo Park Date: Tue, 17 Nov 2015 16:35:46 -0800 Subject: pinctrl: qcom: Add msm8996 pinctrl driver MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add initial pinctrl driver to support pin configuration with pinctrl framework for msm8996. Cc: Signed-off-by: Joonwoo Park [sboyd@codeaurora.org: Remove duplicate entries and enums] Signed-off-by: Stephen Boyd Acked-by: Rob Herring Acked-by: Björn Andersson Signed-off-by: Linus Walleij diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,msm8996-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/qcom,msm8996-pinctrl.txt new file mode 100644 index 0000000..e312a71 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,msm8996-pinctrl.txt @@ -0,0 +1,199 @@ +Qualcomm MSM8996 TLMM block + +This binding describes the Top Level Mode Multiplexer block found in the +MSM8996 platform. + +- compatible: + Usage: required + Value type: + Definition: must be "qcom,msm8996-pinctrl" + +- reg: + Usage: required + Value type: + Definition: the base address and size of the TLMM register space. + +- interrupts: + Usage: required + Value type: + Definition: should specify the TLMM summary IRQ. + +- interrupt-controller: + Usage: required + Value type: + Definition: identifies this node as an interrupt controller + +- #interrupt-cells: + Usage: required + Value type: + Definition: must be 2. Specifying the pin number and flags, as defined + in + +- gpio-controller: + Usage: required + Value type: + Definition: identifies this node as a gpio controller + +- #gpio-cells: + Usage: required + Value type: + Definition: must be 2. Specifying the pin number and flags, as defined + in + +Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for +a general description of GPIO and interrupt bindings. + +Please refer to pinctrl-bindings.txt in this directory for details of the +common pinctrl bindings used by client devices, including the meaning of the +phrase "pin configuration node". + +The pin configuration nodes act as a container for an arbitrary number of +subnodes. Each of these subnodes represents some desired configuration for a +pin, a group, or a list of pins or groups. This configuration can include the +mux function to select on those pin(s)/group(s), and various pin configuration +parameters, such as pull-up, drive strength, etc. + + +PIN CONFIGURATION NODES: + +The name of each subnode is not important; all subnodes should be enumerated +and processed purely based on their content. + +Each subnode only affects those parameters that are explicitly listed. In +other words, a subnode that lists a mux function but no pin configuration +parameters implies no information about any pin configuration parameters. +Similarly, a pin subnode that describes a pullup parameter implies no +information about e.g. the mux function. + + +The following generic properties as defined in pinctrl-bindings.txt are valid +to specify in a pin configuration subnode: + +- pins: + Usage: required + Value type: + Definition: List of gpio pins affected by the properties specified in + this subnode. + + Valid pins are: + gpio0-gpio149 + Supports mux, bias and drive-strength + + sdc1_clk, sdc1_cmd, sdc1_data sdc2_clk, sdc2_cmd, + sdc2_data sdc1_rclk + Supports bias and drive-strength + +- function: + Usage: required + Value type: + Definition: Specify the alternative function to be configured for the + specified pins. Functions are only valid for gpio pins. + Valid values are: + + blsp_uart1, blsp_spi1, blsp_i2c1, blsp_uim1, atest_tsens, + bimc_dte1, dac_calib0, blsp_spi8, blsp_uart8, blsp_uim8, + qdss_cti_trig_out_b, bimc_dte0, dac_calib1, qdss_cti_trig_in_b, + dac_calib2, atest_tsens2, atest_usb1, blsp_spi10, blsp_uart10, + blsp_uim10, atest_bbrx1, atest_usb13, atest_bbrx0, atest_usb12, + mdp_vsync, edp_lcd, blsp_i2c10, atest_gpsadc1, atest_usb11, + atest_gpsadc0, edp_hot, atest_usb10, m_voc, dac_gpio, atest_char, + cam_mclk, pll_bypassnl, qdss_stm7, blsp_i2c8, qdss_tracedata_b, + pll_reset, qdss_stm6, qdss_stm5, qdss_stm4, atest_usb2, cci_i2c, + qdss_stm3, dac_calib3, atest_usb23, atest_char3, dac_calib4, + qdss_stm2, atest_usb22, atest_char2, qdss_stm1, dac_calib5, + atest_usb21, atest_char1, dbg_out, qdss_stm0, dac_calib6, + atest_usb20, atest_char0, dac_calib10, qdss_stm10, + qdss_cti_trig_in_a, cci_timer4, blsp_spi6, blsp_uart6, blsp_uim6, + blsp2_spi, qdss_stm9, qdss_cti_trig_out_a, dac_calib11, + qdss_stm8, cci_timer0, qdss_stm13, dac_calib7, cci_timer1, + qdss_stm12, dac_calib8, cci_timer2, blsp1_spi, qdss_stm11, + dac_calib9, cci_timer3, cci_async, dac_calib12, blsp_i2c6, + qdss_tracectl_a, dac_calib13, qdss_traceclk_a, dac_calib14, + dac_calib15, hdmi_rcv, dac_calib16, hdmi_cec, pwr_modem, + dac_calib17, hdmi_ddc, pwr_nav, dac_calib18, pwr_crypto, + dac_calib19, hdmi_hot, dac_calib20, dac_calib21, pci_e0, + dac_calib22, dac_calib23, dac_calib24, tsif1_sync, dac_calib25, + sd_write, tsif1_error, blsp_spi2, blsp_uart2, blsp_uim2, + qdss_cti, blsp_i2c2, blsp_spi3, blsp_uart3, blsp_uim3, blsp_i2c3, + uim3, blsp_spi9, blsp_uart9, blsp_uim9, blsp10_spi, blsp_i2c9, + blsp_spi7, blsp_uart7, blsp_uim7, qdss_tracedata_a, blsp_i2c7, + qua_mi2s, gcc_gp1_clk_a, ssc_irq, uim4, blsp_spi11, blsp_uart11, + blsp_uim11, gcc_gp2_clk_a, gcc_gp3_clk_a, blsp_i2c11, cri_trng0, + cri_trng1, cri_trng, qdss_stm18, pri_mi2s, qdss_stm17, blsp_spi4, + blsp_uart4, blsp_uim4, qdss_stm16, qdss_stm15, blsp_i2c4, + qdss_stm14, dac_calib26, spkr_i2s, audio_ref, lpass_slimbus, + isense_dbg, tsense_pwm1, tsense_pwm2, btfm_slimbus, ter_mi2s, + qdss_stm22, qdss_stm21, qdss_stm20, qdss_stm19, gcc_gp1_clk_b, + sec_mi2s, blsp_spi5, blsp_uart5, blsp_uim5, gcc_gp2_clk_b, + gcc_gp3_clk_b, blsp_i2c5, blsp_spi12, blsp_uart12, blsp_uim12, + qdss_stm25, qdss_stm31, blsp_i2c12, qdss_stm30, qdss_stm29, + tsif1_clk, qdss_stm28, tsif1_en, tsif1_data, sdc4_cmd, qdss_stm27, + qdss_traceclk_b, tsif2_error, sdc43, vfr_1, qdss_stm26, tsif2_clk, + sdc4_clk, qdss_stm24, tsif2_en, sdc42, qdss_stm23, qdss_tracectl_b, + sd_card, tsif2_data, sdc41, tsif2_sync, sdc40, mdp_vsync_p_b, + ldo_en, mdp_vsync_s_b, ldo_update, blsp11_uart_tx_b, blsp11_uart_rx_b, + blsp11_i2c_sda_b, prng_rosc, blsp11_i2c_scl_b, uim2, uim1, uim_batt, + pci_e2, pa_indicator, adsp_ext, ddr_bist, qdss_tracedata_11, + qdss_tracedata_12, modem_tsync, nav_dr, nav_pps, pci_e1, gsm_tx, + qspi_cs, ssbi2, ssbi1, mss_lte, qspi_clk, qspi0, qspi1, qspi2, qspi3, + gpio + +- bias-disable: + Usage: optional + Value type: + Definition: The specified pins should be configued as no pull. + +- bias-pull-down: + Usage: optional + Value type: + Definition: The specified pins should be configued as pull down. + +- bias-pull-up: + Usage: optional + Value type: + Definition: The specified pins should be configued as pull up. + +- output-high: + Usage: optional + Value type: + Definition: The specified pins are configured in output mode, driven + high. + Not valid for sdc pins. + +- output-low: + Usage: optional + Value type: + Definition: The specified pins are configured in output mode, driven + low. + Not valid for sdc pins. + +- drive-strength: + Usage: optional + Value type: + Definition: Selects the drive strength for the specified pins, in mA. + Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16 + +Example: + + tlmm: pinctrl@01010000 { + compatible = "qcom,msm8996-pinctrl"; + reg = <0x01010000 0x300000>; + interrupts = <0 208 0>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + + uart_console_active: uart_console_active { + mux { + pins = "gpio4", "gpio5"; + function = "blsp_uart8"; + }; + + config { + pins = "gpio4", "gpio5"; + drive-strength = <2>; + bias-disable; + }; + }; + }; diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig index 383263a..eeac8cb 100644 --- a/drivers/pinctrl/qcom/Kconfig +++ b/drivers/pinctrl/qcom/Kconfig @@ -63,6 +63,14 @@ config PINCTRL_MSM8916 This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm TLMM block found on the Qualcomm 8916 platform. +config PINCTRL_MSM8996 + tristate "Qualcomm MSM8996 pin controller driver" + depends on GPIOLIB && OF + select PINCTRL_MSM + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm TLMM block found in the Qualcomm MSM8996 platform. + config PINCTRL_QDF2XXX tristate "Qualcomm Technologies QDF2xxx pin controller driver" depends on GPIOLIB && ACPI diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile index 13b190e..dfb50a9 100644 --- a/drivers/pinctrl/qcom/Makefile +++ b/drivers/pinctrl/qcom/Makefile @@ -7,6 +7,7 @@ obj-$(CONFIG_PINCTRL_MSM8660) += pinctrl-msm8660.o obj-$(CONFIG_PINCTRL_MSM8960) += pinctrl-msm8960.o obj-$(CONFIG_PINCTRL_MSM8X74) += pinctrl-msm8x74.o obj-$(CONFIG_PINCTRL_MSM8916) += pinctrl-msm8916.o +obj-$(CONFIG_PINCTRL_MSM8996) += pinctrl-msm8996.o obj-$(CONFIG_PINCTRL_QDF2XXX) += pinctrl-qdf2xxx.o obj-$(CONFIG_PINCTRL_QCOM_SPMI_PMIC) += pinctrl-spmi-gpio.o obj-$(CONFIG_PINCTRL_QCOM_SPMI_PMIC) += pinctrl-spmi-mpp.o diff --git a/drivers/pinctrl/qcom/pinctrl-msm8996.c b/drivers/pinctrl/qcom/pinctrl-msm8996.c new file mode 100644 index 0000000..c257927 --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-msm8996.c @@ -0,0 +1,1942 @@ +/* + * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include + +#include "pinctrl-msm.h" + +#define FUNCTION(fname) \ + [msm_mux_##fname] = { \ + .name = #fname, \ + .groups = fname##_groups, \ + .ngroups = ARRAY_SIZE(fname##_groups), \ + } + +#define REG_BASE 0x0 +#define REG_SIZE 0x1000 +#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ + { \ + .name = "gpio" #id, \ + .pins = gpio##id##_pins, \ + .npins = (unsigned)ARRAY_SIZE(gpio##id##_pins), \ + .funcs = (int[]){ \ + msm_mux_gpio, /* gpio mode */ \ + msm_mux_##f1, \ + msm_mux_##f2, \ + msm_mux_##f3, \ + msm_mux_##f4, \ + msm_mux_##f5, \ + msm_mux_##f6, \ + msm_mux_##f7, \ + msm_mux_##f8, \ + msm_mux_##f9 \ + }, \ + .nfuncs = 10, \ + .ctl_reg = REG_BASE + REG_SIZE * id, \ + .io_reg = REG_BASE + 0x4 + REG_SIZE * id, \ + .intr_cfg_reg = REG_BASE + 0x8 + REG_SIZE * id, \ + .intr_status_reg = REG_BASE + 0xc + REG_SIZE * id, \ + .intr_target_reg = REG_BASE + 0x8 + REG_SIZE * id, \ + .mux_bit = 2, \ + .pull_bit = 0, \ + .drv_bit = 6, \ + .oe_bit = 9, \ + .in_bit = 0, \ + .out_bit = 1, \ + .intr_enable_bit = 0, \ + .intr_status_bit = 0, \ + .intr_target_bit = 5, \ + .intr_target_kpss_val = 3, \ + .intr_raw_status_bit = 4, \ + .intr_polarity_bit = 1, \ + .intr_detection_bit = 2, \ + .intr_detection_width = 2, \ + } + +#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \ + { \ + .name = #pg_name, \ + .pins = pg_name##_pins, \ + .npins = (unsigned)ARRAY_SIZE(pg_name##_pins), \ + .ctl_reg = ctl, \ + .io_reg = 0, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .mux_bit = -1, \ + .pull_bit = pull, \ + .drv_bit = drv, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = -1, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } +static const struct pinctrl_pin_desc msm8996_pins[] = { + PINCTRL_PIN(0, "GPIO_0"), + PINCTRL_PIN(1, "GPIO_1"), + PINCTRL_PIN(2, "GPIO_2"), + PINCTRL_PIN(3, "GPIO_3"), + PINCTRL_PIN(4, "GPIO_4"), + PINCTRL_PIN(5, "GPIO_5"), + PINCTRL_PIN(6, "GPIO_6"), + PINCTRL_PIN(7, "GPIO_7"), + PINCTRL_PIN(8, "GPIO_8"), + PINCTRL_PIN(9, "GPIO_9"), + PINCTRL_PIN(10, "GPIO_10"), + PINCTRL_PIN(11, "GPIO_11"), + PINCTRL_PIN(12, "GPIO_12"), + PINCTRL_PIN(13, "GPIO_13"), + PINCTRL_PIN(14, "GPIO_14"), + PINCTRL_PIN(15, "GPIO_15"), + PINCTRL_PIN(16, "GPIO_16"), + PINCTRL_PIN(17, "GPIO_17"), + PINCTRL_PIN(18, "GPIO_18"), + PINCTRL_PIN(19, "GPIO_19"), + PINCTRL_PIN(20, "GPIO_20"), + PINCTRL_PIN(21, "GPIO_21"), + PINCTRL_PIN(22, "GPIO_22"), + PINCTRL_PIN(23, "GPIO_23"), + PINCTRL_PIN(24, "GPIO_24"), + PINCTRL_PIN(25, "GPIO_25"), + PINCTRL_PIN(26, "GPIO_26"), + PINCTRL_PIN(27, "GPIO_27"), + PINCTRL_PIN(28, "GPIO_28"), + PINCTRL_PIN(29, "GPIO_29"), + PINCTRL_PIN(30, "GPIO_30"), + PINCTRL_PIN(31, "GPIO_31"), + PINCTRL_PIN(32, "GPIO_32"), + PINCTRL_PIN(33, "GPIO_33"), + PINCTRL_PIN(34, "GPIO_34"), + PINCTRL_PIN(35, "GPIO_35"), + PINCTRL_PIN(36, "GPIO_36"), + PINCTRL_PIN(37, "GPIO_37"), + PINCTRL_PIN(38, "GPIO_38"), + PINCTRL_PIN(39, "GPIO_39"), + PINCTRL_PIN(40, "GPIO_40"), + PINCTRL_PIN(41, "GPIO_41"), + PINCTRL_PIN(42, "GPIO_42"), + PINCTRL_PIN(43, "GPIO_43"), + PINCTRL_PIN(44, "GPIO_44"), + PINCTRL_PIN(45, "GPIO_45"), + PINCTRL_PIN(46, "GPIO_46"), + PINCTRL_PIN(47, "GPIO_47"), + PINCTRL_PIN(48, "GPIO_48"), + PINCTRL_PIN(49, "GPIO_49"), + PINCTRL_PIN(50, "GPIO_50"), + PINCTRL_PIN(51, "GPIO_51"), + PINCTRL_PIN(52, "GPIO_52"), + PINCTRL_PIN(53, "GPIO_53"), + PINCTRL_PIN(54, "GPIO_54"), + PINCTRL_PIN(55, "GPIO_55"), + PINCTRL_PIN(56, "GPIO_56"), + PINCTRL_PIN(57, "GPIO_57"), + PINCTRL_PIN(58, "GPIO_58"), + PINCTRL_PIN(59, "GPIO_59"), + PINCTRL_PIN(60, "GPIO_60"), + PINCTRL_PIN(61, "GPIO_61"), + PINCTRL_PIN(62, "GPIO_62"), + PINCTRL_PIN(63, "GPIO_63"), + PINCTRL_PIN(64, "GPIO_64"), + PINCTRL_PIN(65, "GPIO_65"), + PINCTRL_PIN(66, "GPIO_66"), + PINCTRL_PIN(67, "GPIO_67"), + PINCTRL_PIN(68, "GPIO_68"), + PINCTRL_PIN(69, "GPIO_69"), + PINCTRL_PIN(70, "GPIO_70"), + PINCTRL_PIN(71, "GPIO_71"), + PINCTRL_PIN(72, "GPIO_72"), + PINCTRL_PIN(73, "GPIO_73"), + PINCTRL_PIN(74, "GPIO_74"), + PINCTRL_PIN(75, "GPIO_75"), + PINCTRL_PIN(76, "GPIO_76"), + PINCTRL_PIN(77, "GPIO_77"), + PINCTRL_PIN(78, "GPIO_78"), + PINCTRL_PIN(79, "GPIO_79"), + PINCTRL_PIN(80, "GPIO_80"), + PINCTRL_PIN(81, "GPIO_81"), + PINCTRL_PIN(82, "GPIO_82"), + PINCTRL_PIN(83, "GPIO_83"), + PINCTRL_PIN(84, "GPIO_84"), + PINCTRL_PIN(85, "GPIO_85"), + PINCTRL_PIN(86, "GPIO_86"), + PINCTRL_PIN(87, "GPIO_87"), + PINCTRL_PIN(88, "GPIO_88"), + PINCTRL_PIN(89, "GPIO_89"), + PINCTRL_PIN(90, "GPIO_90"), + PINCTRL_PIN(91, "GPIO_91"), + PINCTRL_PIN(92, "GPIO_92"), + PINCTRL_PIN(93, "GPIO_93"), + PINCTRL_PIN(94, "GPIO_94"), + PINCTRL_PIN(95, "GPIO_95"), + PINCTRL_PIN(96, "GPIO_96"), + PINCTRL_PIN(97, "GPIO_97"), + PINCTRL_PIN(98, "GPIO_98"), + PINCTRL_PIN(99, "GPIO_99"), + PINCTRL_PIN(100, "GPIO_100"), + PINCTRL_PIN(101, "GPIO_101"), + PINCTRL_PIN(102, "GPIO_102"), + PINCTRL_PIN(103, "GPIO_103"), + PINCTRL_PIN(104, "GPIO_104"), + PINCTRL_PIN(105, "GPIO_105"), + PINCTRL_PIN(106, "GPIO_106"), + PINCTRL_PIN(107, "GPIO_107"), + PINCTRL_PIN(108, "GPIO_108"), + PINCTRL_PIN(109, "GPIO_109"), + PINCTRL_PIN(110, "GPIO_110"), + PINCTRL_PIN(111, "GPIO_111"), + PINCTRL_PIN(112, "GPIO_112"), + PINCTRL_PIN(113, "GPIO_113"), + PINCTRL_PIN(114, "GPIO_114"), + PINCTRL_PIN(115, "GPIO_115"), + PINCTRL_PIN(116, "GPIO_116"), + PINCTRL_PIN(117, "GPIO_117"), + PINCTRL_PIN(118, "GPIO_118"), + PINCTRL_PIN(119, "GPIO_119"), + PINCTRL_PIN(120, "GPIO_120"), + PINCTRL_PIN(121, "GPIO_121"), + PINCTRL_PIN(122, "GPIO_122"), + PINCTRL_PIN(123, "GPIO_123"), + PINCTRL_PIN(124, "GPIO_124"), + PINCTRL_PIN(125, "GPIO_125"), + PINCTRL_PIN(126, "GPIO_126"), + PINCTRL_PIN(127, "GPIO_127"), + PINCTRL_PIN(128, "GPIO_128"), + PINCTRL_PIN(129, "GPIO_129"), + PINCTRL_PIN(130, "GPIO_130"), + PINCTRL_PIN(131, "GPIO_131"), + PINCTRL_PIN(132, "GPIO_132"), + PINCTRL_PIN(133, "GPIO_133"), + PINCTRL_PIN(134, "GPIO_134"), + PINCTRL_PIN(135, "GPIO_135"), + PINCTRL_PIN(136, "GPIO_136"), + PINCTRL_PIN(137, "GPIO_137"), + PINCTRL_PIN(138, "GPIO_138"), + PINCTRL_PIN(139, "GPIO_139"), + PINCTRL_PIN(140, "GPIO_140"), + PINCTRL_PIN(141, "GPIO_141"), + PINCTRL_PIN(142, "GPIO_142"), + PINCTRL_PIN(143, "GPIO_143"), + PINCTRL_PIN(144, "GPIO_144"), + PINCTRL_PIN(145, "GPIO_145"), + PINCTRL_PIN(146, "GPIO_146"), + PINCTRL_PIN(147, "GPIO_147"), + PINCTRL_PIN(148, "GPIO_148"), + PINCTRL_PIN(149, "GPIO_149"), + PINCTRL_PIN(150, "SDC1_CLK"), + PINCTRL_PIN(151, "SDC1_CMD"), + PINCTRL_PIN(152, "SDC1_DATA"), + PINCTRL_PIN(153, "SDC2_CLK"), + PINCTRL_PIN(154, "SDC2_CMD"), + PINCTRL_PIN(155, "SDC2_DATA"), + PINCTRL_PIN(156, "SDC1_RCLK"), +}; + +#define DECLARE_MSM_GPIO_PINS(pin) \ + static const unsigned int gpio##pin##_pins[] = { pin } +DECLARE_MSM_GPIO_PINS(0); +DECLARE_MSM_GPIO_PINS(1); +DECLARE_MSM_GPIO_PINS(2); +DECLARE_MSM_GPIO_PINS(3); +DECLARE_MSM_GPIO_PINS(4); +DECLARE_MSM_GPIO_PINS(5); +DECLARE_MSM_GPIO_PINS(6); +DECLARE_MSM_GPIO_PINS(7); +DECLARE_MSM_GPIO_PINS(8); +DECLARE_MSM_GPIO_PINS(9); +DECLARE_MSM_GPIO_PINS(10); +DECLARE_MSM_GPIO_PINS(11); +DECLARE_MSM_GPIO_PINS(12); +DECLARE_MSM_GPIO_PINS(13); +DECLARE_MSM_GPIO_PINS(14); +DECLARE_MSM_GPIO_PINS(15); +DECLARE_MSM_GPIO_PINS(16); +DECLARE_MSM_GPIO_PINS(17); +DECLARE_MSM_GPIO_PINS(18); +DECLARE_MSM_GPIO_PINS(19); +DECLARE_MSM_GPIO_PINS(20); +DECLARE_MSM_GPIO_PINS(21); +DECLARE_MSM_GPIO_PINS(22); +DECLARE_MSM_GPIO_PINS(23); +DECLARE_MSM_GPIO_PINS(24); +DECLARE_MSM_GPIO_PINS(25); +DECLARE_MSM_GPIO_PINS(26); +DECLARE_MSM_GPIO_PINS(27); +DECLARE_MSM_GPIO_PINS(28); +DECLARE_MSM_GPIO_PINS(29); +DECLARE_MSM_GPIO_PINS(30); +DECLARE_MSM_GPIO_PINS(31); +DECLARE_MSM_GPIO_PINS(32); +DECLARE_MSM_GPIO_PINS(33); +DECLARE_MSM_GPIO_PINS(34); +DECLARE_MSM_GPIO_PINS(35); +DECLARE_MSM_GPIO_PINS(36); +DECLARE_MSM_GPIO_PINS(37); +DECLARE_MSM_GPIO_PINS(38); +DECLARE_MSM_GPIO_PINS(39); +DECLARE_MSM_GPIO_PINS(40); +DECLARE_MSM_GPIO_PINS(41); +DECLARE_MSM_GPIO_PINS(42); +DECLARE_MSM_GPIO_PINS(43); +DECLARE_MSM_GPIO_PINS(44); +DECLARE_MSM_GPIO_PINS(45); +DECLARE_MSM_GPIO_PINS(46); +DECLARE_MSM_GPIO_PINS(47); +DECLARE_MSM_GPIO_PINS(48); +DECLARE_MSM_GPIO_PINS(49); +DECLARE_MSM_GPIO_PINS(50); +DECLARE_MSM_GPIO_PINS(51); +DECLARE_MSM_GPIO_PINS(52); +DECLARE_MSM_GPIO_PINS(53); +DECLARE_MSM_GPIO_PINS(54); +DECLARE_MSM_GPIO_PINS(55); +DECLARE_MSM_GPIO_PINS(56); +DECLARE_MSM_GPIO_PINS(57); +DECLARE_MSM_GPIO_PINS(58); +DECLARE_MSM_GPIO_PINS(59); +DECLARE_MSM_GPIO_PINS(60); +DECLARE_MSM_GPIO_PINS(61); +DECLARE_MSM_GPIO_PINS(62); +DECLARE_MSM_GPIO_PINS(63); +DECLARE_MSM_GPIO_PINS(64); +DECLARE_MSM_GPIO_PINS(65); +DECLARE_MSM_GPIO_PINS(66); +DECLARE_MSM_GPIO_PINS(67); +DECLARE_MSM_GPIO_PINS(68); +DECLARE_MSM_GPIO_PINS(69); +DECLARE_MSM_GPIO_PINS(70); +DECLARE_MSM_GPIO_PINS(71); +DECLARE_MSM_GPIO_PINS(72); +DECLARE_MSM_GPIO_PINS(73); +DECLARE_MSM_GPIO_PINS(74); +DECLARE_MSM_GPIO_PINS(75); +DECLARE_MSM_GPIO_PINS(76); +DECLARE_MSM_GPIO_PINS(77); +DECLARE_MSM_GPIO_PINS(78); +DECLARE_MSM_GPIO_PINS(79); +DECLARE_MSM_GPIO_PINS(80); +DECLARE_MSM_GPIO_PINS(81); +DECLARE_MSM_GPIO_PINS(82); +DECLARE_MSM_GPIO_PINS(83); +DECLARE_MSM_GPIO_PINS(84); +DECLARE_MSM_GPIO_PINS(85); +DECLARE_MSM_GPIO_PINS(86); +DECLARE_MSM_GPIO_PINS(87); +DECLARE_MSM_GPIO_PINS(88); +DECLARE_MSM_GPIO_PINS(89); +DECLARE_MSM_GPIO_PINS(90); +DECLARE_MSM_GPIO_PINS(91); +DECLARE_MSM_GPIO_PINS(92); +DECLARE_MSM_GPIO_PINS(93); +DECLARE_MSM_GPIO_PINS(94); +DECLARE_MSM_GPIO_PINS(95); +DECLARE_MSM_GPIO_PINS(96); +DECLARE_MSM_GPIO_PINS(97); +DECLARE_MSM_GPIO_PINS(98); +DECLARE_MSM_GPIO_PINS(99); +DECLARE_MSM_GPIO_PINS(100); +DECLARE_MSM_GPIO_PINS(101); +DECLARE_MSM_GPIO_PINS(102); +DECLARE_MSM_GPIO_PINS(103); +DECLARE_MSM_GPIO_PINS(104); +DECLARE_MSM_GPIO_PINS(105); +DECLARE_MSM_GPIO_PINS(106); +DECLARE_MSM_GPIO_PINS(107); +DECLARE_MSM_GPIO_PINS(108); +DECLARE_MSM_GPIO_PINS(109); +DECLARE_MSM_GPIO_PINS(110); +DECLARE_MSM_GPIO_PINS(111); +DECLARE_MSM_GPIO_PINS(112); +DECLARE_MSM_GPIO_PINS(113); +DECLARE_MSM_GPIO_PINS(114); +DECLARE_MSM_GPIO_PINS(115); +DECLARE_MSM_GPIO_PINS(116); +DECLARE_MSM_GPIO_PINS(117); +DECLARE_MSM_GPIO_PINS(118); +DECLARE_MSM_GPIO_PINS(119); +DECLARE_MSM_GPIO_PINS(120); +DECLARE_MSM_GPIO_PINS(121); +DECLARE_MSM_GPIO_PINS(122); +DECLARE_MSM_GPIO_PINS(123); +DECLARE_MSM_GPIO_PINS(124); +DECLARE_MSM_GPIO_PINS(125); +DECLARE_MSM_GPIO_PINS(126); +DECLARE_MSM_GPIO_PINS(127); +DECLARE_MSM_GPIO_PINS(128); +DECLARE_MSM_GPIO_PINS(129); +DECLARE_MSM_GPIO_PINS(130); +DECLARE_MSM_GPIO_PINS(131); +DECLARE_MSM_GPIO_PINS(132); +DECLARE_MSM_GPIO_PINS(133); +DECLARE_MSM_GPIO_PINS(134); +DECLARE_MSM_GPIO_PINS(135); +DECLARE_MSM_GPIO_PINS(136); +DECLARE_MSM_GPIO_PINS(137); +DECLARE_MSM_GPIO_PINS(138); +DECLARE_MSM_GPIO_PINS(139); +DECLARE_MSM_GPIO_PINS(140); +DECLARE_MSM_GPIO_PINS(141); +DECLARE_MSM_GPIO_PINS(142); +DECLARE_MSM_GPIO_PINS(143); +DECLARE_MSM_GPIO_PINS(144); +DECLARE_MSM_GPIO_PINS(145); +DECLARE_MSM_GPIO_PINS(146); +DECLARE_MSM_GPIO_PINS(147); +DECLARE_MSM_GPIO_PINS(148); +DECLARE_MSM_GPIO_PINS(149); + +static const unsigned int sdc1_clk_pins[] = { 150 }; +static const unsigned int sdc1_cmd_pins[] = { 151 }; +static const unsigned int sdc1_data_pins[] = { 152 }; +static const unsigned int sdc2_clk_pins[] = { 153 }; +static const unsigned int sdc2_cmd_pins[] = { 154 }; +static const unsigned int sdc2_data_pins[] = { 155 }; +static const unsigned int sdc1_rclk_pins[] = { 156 }; + +enum msm8996_functions { + msm_mux_adsp_ext, + msm_mux_atest_bbrx0, + msm_mux_atest_bbrx1, + msm_mux_atest_char, + msm_mux_atest_char0, + msm_mux_atest_char1, + msm_mux_atest_char2, + msm_mux_atest_char3, + msm_mux_atest_gpsadc0, + msm_mux_atest_gpsadc1, + msm_mux_atest_tsens, + msm_mux_atest_tsens2, + msm_mux_atest_usb1, + msm_mux_atest_usb10, + msm_mux_atest_usb11, + msm_mux_atest_usb12, + msm_mux_atest_usb13, + msm_mux_atest_usb2, + msm_mux_atest_usb20, + msm_mux_atest_usb21, + msm_mux_atest_usb22, + msm_mux_atest_usb23, + msm_mux_audio_ref, + msm_mux_bimc_dte0, + msm_mux_bimc_dte1, + msm_mux_blsp10_spi, + msm_mux_blsp11_i2c_scl_b, + msm_mux_blsp11_i2c_sda_b, + msm_mux_blsp11_uart_rx_b, + msm_mux_blsp11_uart_tx_b, + msm_mux_blsp1_spi, + msm_mux_blsp2_spi, + msm_mux_blsp_i2c1, + msm_mux_blsp_i2c10, + msm_mux_blsp_i2c11, + msm_mux_blsp_i2c12, + msm_mux_blsp_i2c2, + msm_mux_blsp_i2c3, + msm_mux_blsp_i2c4, + msm_mux_blsp_i2c5, + msm_mux_blsp_i2c6, + msm_mux_blsp_i2c7, + msm_mux_blsp_i2c8, + msm_mux_blsp_i2c9, + msm_mux_blsp_spi1, + msm_mux_blsp_spi10, + msm_mux_blsp_spi11, + msm_mux_blsp_spi12, + msm_mux_blsp_spi2, + msm_mux_blsp_spi3, + msm_mux_blsp_spi4, + msm_mux_blsp_spi5, + msm_mux_blsp_spi6, + msm_mux_blsp_spi7, + msm_mux_blsp_spi8, + msm_mux_blsp_spi9, + msm_mux_blsp_uart1, + msm_mux_blsp_uart10, + msm_mux_blsp_uart11, + msm_mux_blsp_uart12, + msm_mux_blsp_uart2, + msm_mux_blsp_uart3, + msm_mux_blsp_uart4, + msm_mux_blsp_uart5, + msm_mux_blsp_uart6, + msm_mux_blsp_uart7, + msm_mux_blsp_uart8, + msm_mux_blsp_uart9, + msm_mux_blsp_uim1, + msm_mux_blsp_uim10, + msm_mux_blsp_uim11, + msm_mux_blsp_uim12, + msm_mux_blsp_uim2, + msm_mux_blsp_uim3, + msm_mux_blsp_uim4, + msm_mux_blsp_uim5, + msm_mux_blsp_uim6, + msm_mux_blsp_uim7, + msm_mux_blsp_uim8, + msm_mux_blsp_uim9, + msm_mux_btfm_slimbus, + msm_mux_cam_mclk, + msm_mux_cci_async, + msm_mux_cci_i2c, + msm_mux_cci_timer0, + msm_mux_cci_timer1, + msm_mux_cci_timer2, + msm_mux_cci_timer3, + msm_mux_cci_timer4, + msm_mux_cri_trng, + msm_mux_cri_trng0, + msm_mux_cri_trng1, + msm_mux_dac_calib0, + msm_mux_dac_calib1, + msm_mux_dac_calib10, + msm_mux_dac_calib11, + msm_mux_dac_calib12, + msm_mux_dac_calib13, + msm_mux_dac_calib14, + msm_mux_dac_calib15, + msm_mux_dac_calib16, + msm_mux_dac_calib17, + msm_mux_dac_calib18, + msm_mux_dac_calib19, + msm_mux_dac_calib2, + msm_mux_dac_calib20, + msm_mux_dac_calib21, + msm_mux_dac_calib22, + msm_mux_dac_calib23, + msm_mux_dac_calib24, + msm_mux_dac_calib25, + msm_mux_dac_calib26, + msm_mux_dac_calib3, + msm_mux_dac_calib4, + msm_mux_dac_calib5, + msm_mux_dac_calib6, + msm_mux_dac_calib7, + msm_mux_dac_calib8, + msm_mux_dac_calib9, + msm_mux_dac_gpio, + msm_mux_dbg_out, + msm_mux_ddr_bist, + msm_mux_edp_hot, + msm_mux_edp_lcd, + msm_mux_gcc_gp1_clk_a, + msm_mux_gcc_gp1_clk_b, + msm_mux_gcc_gp2_clk_a, + msm_mux_gcc_gp2_clk_b, + msm_mux_gcc_gp3_clk_a, + msm_mux_gcc_gp3_clk_b, + msm_mux_gsm_tx, + msm_mux_hdmi_cec, + msm_mux_hdmi_ddc, + msm_mux_hdmi_hot, + msm_mux_hdmi_rcv, + msm_mux_isense_dbg, + msm_mux_ldo_en, + msm_mux_ldo_update, + msm_mux_lpass_slimbus, + msm_mux_m_voc, + msm_mux_mdp_vsync, + msm_mux_mdp_vsync_p_b, + msm_mux_mdp_vsync_s_b, + msm_mux_modem_tsync, + msm_mux_mss_lte, + msm_mux_nav_dr, + msm_mux_nav_pps, + msm_mux_pa_indicator, + msm_mux_pci_e0, + msm_mux_pci_e1, + msm_mux_pci_e2, + msm_mux_pll_bypassnl, + msm_mux_pll_reset, + msm_mux_pri_mi2s, + msm_mux_prng_rosc, + msm_mux_pwr_crypto, + msm_mux_pwr_modem, + msm_mux_pwr_nav, + msm_mux_qdss_cti, + msm_mux_qdss_cti_trig_in_a, + msm_mux_qdss_cti_trig_in_b, + msm_mux_qdss_cti_trig_out_a, + msm_mux_qdss_cti_trig_out_b, + msm_mux_qdss_stm0, + msm_mux_qdss_stm1, + msm_mux_qdss_stm10, + msm_mux_qdss_stm11, + msm_mux_qdss_stm12, + msm_mux_qdss_stm13, + msm_mux_qdss_stm14, + msm_mux_qdss_stm15, + msm_mux_qdss_stm16, + msm_mux_qdss_stm17, + msm_mux_qdss_stm18, + msm_mux_qdss_stm19, + msm_mux_qdss_stm2, + msm_mux_qdss_stm20, + msm_mux_qdss_stm21, + msm_mux_qdss_stm22, + msm_mux_qdss_stm23, + msm_mux_qdss_stm24, + msm_mux_qdss_stm25, + msm_mux_qdss_stm26, + msm_mux_qdss_stm27, + msm_mux_qdss_stm28, + msm_mux_qdss_stm29, + msm_mux_qdss_stm3, + msm_mux_qdss_stm30, + msm_mux_qdss_stm31, + msm_mux_qdss_stm4, + msm_mux_qdss_stm5, + msm_mux_qdss_stm6, + msm_mux_qdss_stm7, + msm_mux_qdss_stm8, + msm_mux_qdss_stm9, + msm_mux_qdss_traceclk_a, + msm_mux_qdss_traceclk_b, + msm_mux_qdss_tracectl_a, + msm_mux_qdss_tracectl_b, + msm_mux_qdss_tracedata_11, + msm_mux_qdss_tracedata_12, + msm_mux_qdss_tracedata_a, + msm_mux_qdss_tracedata_b, + msm_mux_qspi0, + msm_mux_qspi1, + msm_mux_qspi2, + msm_mux_qspi3, + msm_mux_qspi_clk, + msm_mux_qspi_cs, + msm_mux_qua_mi2s, + msm_mux_sd_card, + msm_mux_sd_write, + msm_mux_sdc40, + msm_mux_sdc41, + msm_mux_sdc42, + msm_mux_sdc43, + msm_mux_sdc4_clk, + msm_mux_sdc4_cmd, + msm_mux_sec_mi2s, + msm_mux_spkr_i2s, + msm_mux_ssbi1, + msm_mux_ssbi2, + msm_mux_ssc_irq, + msm_mux_ter_mi2s, + msm_mux_tsense_pwm1, + msm_mux_tsense_pwm2, + msm_mux_tsif1_clk, + msm_mux_tsif1_data, + msm_mux_tsif1_en, + msm_mux_tsif1_error, + msm_mux_tsif1_sync, + msm_mux_tsif2_clk, + msm_mux_tsif2_data, + msm_mux_tsif2_en, + msm_mux_tsif2_error, + msm_mux_tsif2_sync, + msm_mux_uim1, + msm_mux_uim2, + msm_mux_uim3, + msm_mux_uim4, + msm_mux_uim_batt, + msm_mux_vfr_1, + msm_mux_gpio, + msm_mux_NA, +}; + +static const char * const gpio_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", + "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", + "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", + "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", + "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", + "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", + "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49", + "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56", + "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", + "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70", + "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77", + "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84", + "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91", + "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98", + "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104", + "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110", + "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio116", + "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", "gpio122", + "gpio123", "gpio124", "gpio125", "gpio126", "gpio127", "gpio128", + "gpio129", "gpio130", "gpio131", "gpio132", "gpio133", "gpio134", + "gpio135", "gpio136", "gpio137", "gpio138", "gpio139", "gpio140", + "gpio141", "gpio142", "gpio143", "gpio144", "gpio145", "gpio146", + "gpio147", "gpio148", "gpio149" +}; + + +static const char * const blsp_uart1_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", +}; +static const char * const blsp_spi1_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", +}; +static const char * const blsp_i2c1_groups[] = { + "gpio2", "gpio3", +}; +static const char * const blsp_uim1_groups[] = { + "gpio0", "gpio1", +}; +static const char * const atest_tsens_groups[] = { + "gpio3", +}; +static const char * const bimc_dte1_groups[] = { + "gpio3", "gpio5", +}; +static const char * const blsp_spi8_groups[] = { + "gpio4", "gpio5", "gpio6", "gpio7", +}; +static const char * const blsp_uart8_groups[] = { + "gpio4", "gpio5", "gpio6", "gpio7", +}; +static const char * const blsp_uim8_groups[] = { + "gpio4", "gpio5", +}; +static const char * const qdss_cti_trig_out_b_groups[] = { + "gpio4", +}; +static const char * const dac_calib0_groups[] = { + "gpio4", "gpio41", +}; +static const char * const bimc_dte0_groups[] = { + "gpio4", "gpio6", +}; +static const char * const qdss_cti_trig_in_b_groups[] = { + "gpio5", +}; +static const char * const dac_calib1_groups[] = { + "gpio5", "gpio42", +}; +static const char * const dac_calib2_groups[] = { + "gpio6", "gpio43", +}; +static const char * const atest_tsens2_groups[] = { + "gpio7", +}; +static const char * const blsp_spi10_groups[] = { + "gpio8", "gpio9", "gpio10", "gpio11", +}; +static const char * const blsp_uart10_groups[] = { + "gpio8", "gpio9", "gpio10", "gpio11", +}; +static const char * const blsp_uim10_groups[] = { + "gpio8", "gpio9", +}; +static const char * const atest_bbrx1_groups[] = { + "gpio8", +}; +static const char * const atest_usb12_groups[] = { + "gpio9", +}; +static const char * const mdp_vsync_groups[] = { + "gpio10", "gpio11", "gpio12", +}; +static const char * const edp_lcd_groups[] = { + "gpio10", +}; +static const char * const blsp_i2c10_groups[] = { + "gpio10", "gpio11", +}; +static const char * const atest_usb11_groups[] = { + "gpio10", +}; +static const char * const atest_gpsadc0_groups[] = { + "gpio11", +}; +static const char * const edp_hot_groups[] = { + "gpio11", +}; +static const char * const atest_usb10_groups[] = { + "gpio11", +}; +static const char * const m_voc_groups[] = { + "gpio12", +}; +static const char * const dac_gpio_groups[] = { + "gpio12", +}; +static const char * const atest_char_groups[] = { + "gpio12", +}; +static const char * const cam_mclk_groups[] = { + "gpio13", "gpio14", "gpio15", "gpio16", +}; +static const char * const pll_bypassnl_groups[] = { + "gpio13", +}; +static const char * const qdss_stm7_groups[] = { + "gpio13", +}; +static const char * const blsp_i2c8_groups[] = { + "gpio6", "gpio7", +}; +static const char * const atest_usb1_groups[] = { + "gpio7", +}; +static const char * const atest_usb13_groups[] = { + "gpio8", +}; +static const char * const atest_bbrx0_groups[] = { + "gpio9", +}; +static const char * const atest_gpsadc1_groups[] = { + "gpio10", +}; +static const char * const qdss_tracedata_b_groups[] = { + "gpio13", "gpio14", "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", + "gpio21", "gpio22", "gpio23", "gpio26", "gpio29", "gpio57", "gpio58", + "gpio92", "gpio93", +}; +static const char * const pll_reset_groups[] = { + "gpio14", +}; +static const char * const qdss_stm6_groups[] = { + "gpio14", +}; +static const char * const qdss_stm5_groups[] = { + "gpio15", +}; +static const char * const qdss_stm4_groups[] = { + "gpio16", +}; +static const char * const atest_usb2_groups[] = { + "gpio16", +}; +static const char * const dac_calib3_groups[] = { + "gpio17", "gpio44", +}; +static const char * const cci_i2c_groups[] = { + "gpio17", "gpio18", "gpio19", "gpio20", +}; +static const char * const qdss_stm3_groups[] = { + "gpio17", +}; +static const char * const atest_usb23_groups[] = { + "gpio17", +}; +static const char * const atest_char3_groups[] = { + "gpio17", +}; +static const char * const dac_calib4_groups[] = { + "gpio18", "gpio45", +}; +static const char * const qdss_stm2_groups[] = { + "gpio18", +}; +static const char * const atest_usb22_groups[] = { + "gpio18", +}; +static const char * const atest_char2_groups[] = { + "gpio18", +}; +static const char * const dac_calib5_groups[] = { + "gpio19", "gpio46", +}; +static const char * const qdss_stm1_groups[] = { + "gpio19", +}; +static const char * const atest_usb21_groups[] = { + "gpio19", +}; +static const char * const atest_char1_groups[] = { + "gpio19", +}; +static const char * const dac_calib6_groups[] = { + "gpio20", "gpio47", +}; +static const char * const dbg_out_groups[] = { + "gpio20", +}; +static const char * const qdss_stm0_groups[] = { + "gpio20", +}; +static const char * const atest_usb20_groups[] = { + "gpio20", +}; +static const char * const atest_char0_groups[] = { + "gpio20", +}; +static const char * const dac_calib7_groups[] = { + "gpio21", "gpio48", +}; +static const char * const cci_timer0_groups[] = { + "gpio21", +}; +static const char * const qdss_stm13_groups[] = { + "gpio21", +}; +static const char * const dac_calib8_groups[] = { + "gpio22", "gpio49", +}; +static const char * const cci_timer1_groups[] = { + "gpio22", +}; +static const char * const qdss_stm12_groups[] = { + "gpio22", +}; +static const char * const dac_calib9_groups[] = { + "gpio23", "gpio50", +}; +static const char * const cci_timer2_groups[] = { + "gpio23", +}; +static const char * const qdss_stm11_groups[] = { + "gpio23", +}; +static const char * const dac_calib10_groups[] = { + "gpio24", "gpio51", +}; +static const char * const cci_timer3_groups[] = { + "gpio24", +}; +static const char * const cci_async_groups[] = { + "gpio24", "gpio25", "gpio26", +}; +static const char * const blsp1_spi_groups[] = { + "gpio24", "gpio27", "gpio28", "gpio90", +}; +static const char * const qdss_stm10_groups[] = { + "gpio24", +}; +static const char * const qdss_cti_trig_in_a_groups[] = { + "gpio24", +}; +static const char * const dac_calib11_groups[] = { + "gpio25", "gpio52", +}; +static const char * const cci_timer4_groups[] = { + "gpio25", +}; +static const char * const blsp_spi6_groups[] = { + "gpio25", "gpio26", "gpio27", "gpio28", +}; +static const char * const blsp_uart6_groups[] = { + "gpio25", "gpio26", "gpio27", "gpio28", +}; +static const char * const blsp_uim6_groups[] = { + "gpio25", "gpio26", +}; +static const char * const blsp2_spi_groups[] = { + "gpio25", "gpio29", "gpio30", +}; +static const char * const qdss_stm9_groups[] = { + "gpio25", +}; +static const char * const qdss_cti_trig_out_a_groups[] = { + "gpio25", +}; +static const char * const dac_calib12_groups[] = { + "gpio26", "gpio53", +}; +static const char * const qdss_stm8_groups[] = { + "gpio26", +}; +static const char * const dac_calib13_groups[] = { + "gpio27", "gpio54", +}; +static const char * const blsp_i2c6_groups[] = { + "gpio27", "gpio28", +}; +static const char * const qdss_tracectl_a_groups[] = { + "gpio27", +}; +static const char * const dac_calib14_groups[] = { + "gpio28", "gpio55", +}; +static const char * const qdss_traceclk_a_groups[] = { + "gpio28", +}; +static const char * const dac_calib15_groups[] = { + "gpio29", "gpio56", +}; +static const char * const dac_calib16_groups[] = { + "gpio30", "gpio57", +}; +static const char * const hdmi_rcv_groups[] = { + "gpio30", +}; +static const char * const dac_calib17_groups[] = { + "gpio31", "gpio58", +}; +static const char * const pwr_modem_groups[] = { + "gpio31", +}; +static const char * const hdmi_cec_groups[] = { + "gpio31", +}; +static const char * const pwr_nav_groups[] = { + "gpio32", +}; +static const char * const dac_calib18_groups[] = { + "gpio32", "gpio59", +}; +static const char * const hdmi_ddc_groups[] = { + "gpio32", "gpio33", +}; +static const char * const pwr_crypto_groups[] = { + "gpio33", +}; +static const char * const dac_calib19_groups[] = { + "gpio33", "gpio60", +}; +static const char * const dac_calib20_groups[] = { + "gpio34", "gpio61", +}; +static const char * const hdmi_hot_groups[] = { + "gpio34", +}; +static const char * const dac_calib21_groups[] = { + "gpio35", "gpio62", +}; +static const char * const pci_e0_groups[] = { + "gpio35", "gpio36", +}; +static const char * const dac_calib22_groups[] = { + "gpio36", "gpio63", +}; +static const char * const dac_calib23_groups[] = { + "gpio37", "gpio64", +}; +static const char * const blsp_i2c2_groups[] = { + "gpio43", "gpio44", +}; +static const char * const blsp_spi3_groups[] = { + "gpio45", "gpio46", "gpio47", "gpio48", +}; +static const char * const blsp_uart3_groups[] = { + "gpio45", "gpio46", "gpio47", "gpio48", +}; +static const char * const blsp_uim3_groups[] = { + "gpio45", "gpio46", +}; +static const char * const blsp_i2c3_groups[] = { + "gpio47", "gpio48", +}; +static const char * const dac_calib24_groups[] = { + "gpio38", "gpio65", +}; +static const char * const dac_calib25_groups[] = { + "gpio39", "gpio66", +}; +static const char * const tsif1_sync_groups[] = { + "gpio39", +}; +static const char * const sd_write_groups[] = { + "gpio40", +}; +static const char * const tsif1_error_groups[] = { + "gpio40", +}; +static const char * const blsp_spi2_groups[] = { + "gpio41", "gpio42", "gpio43", "gpio44", +}; +static const char * const blsp_uart2_groups[] = { + "gpio41", "gpio42", "gpio43", "gpio44", +}; +static const char * const blsp_uim2_groups[] = { + "gpio41", "gpio42", +}; +static const char * const qdss_cti_groups[] = { + "gpio41", "gpio42", "gpio100", "gpio101", +}; +static const char * const uim3_groups[] = { + "gpio49", "gpio50", "gpio51", "gpio52", +}; +static const char * const blsp_spi9_groups[] = { + "gpio49", "gpio50", "gpio51", "gpio52", +}; +static const char * const blsp_uart9_groups[] = { + "gpio49", "gpio50", "gpio51", "gpio52", +}; +static const char * const blsp_uim9_groups[] = { + "gpio49", "gpio50", +}; +static const char * const blsp10_spi_groups[] = { + "gpio49", "gpio50", "gpio51", "gpio52", "gpio88", +}; +static const char * const blsp_i2c9_groups[] = { + "gpio51", "gpio52", +}; +static const char * const blsp_spi7_groups[] = { + "gpio53", "gpio54", "gpio55", "gpio56", +}; +static const char * const blsp_uart7_groups[] = { + "gpio53", "gpio54", "gpio55", "gpio56", +}; +static const char * const blsp_uim7_groups[] = { + "gpio53", "gpio54", +}; +static const char * const qdss_tracedata_a_groups[] = { + "gpio53", "gpio54", "gpio63", "gpio64", "gpio65", "gpio66", "gpio67", + "gpio74", "gpio75", "gpio76", "gpio77", "gpio85", "gpio86", "gpio87", + "gpio89", "gpio90", +}; +static const char * const blsp_i2c7_groups[] = { + "gpio55", "gpio56", +}; +static const char * const qua_mi2s_groups[] = { + "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", +}; +static const char * const gcc_gp1_clk_a_groups[] = { + "gpio57", +}; +static const char * const uim4_groups[] = { + "gpio58", "gpio59", "gpio60", "gpio61", +}; +static const char * const blsp_spi11_groups[] = { + "gpio58", "gpio59", "gpio60", "gpio61", +}; +static const char * const blsp_uart11_groups[] = { + "gpio58", "gpio59", "gpio60", "gpio61", +}; +static const char * const blsp_uim11_groups[] = { + "gpio58", "gpio59", +}; +static const char * const gcc_gp2_clk_a_groups[] = { + "gpio58", +}; +static const char * const gcc_gp3_clk_a_groups[] = { + "gpio59", +}; +static const char * const blsp_i2c11_groups[] = { + "gpio60", "gpio61", +}; +static const char * const cri_trng0_groups[] = { + "gpio60", +}; +static const char * const cri_trng1_groups[] = { + "gpio61", +}; +static const char * const cri_trng_groups[] = { + "gpio62", +}; +static const char * const qdss_stm18_groups[] = { + "gpio63", +}; +static const char * const pri_mi2s_groups[] = { + "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", +}; +static const char * const qdss_stm17_groups[] = { + "gpio64", +}; +static const char * const blsp_spi4_groups[] = { + "gpio65", "gpio66", "gpio67", "gpio68", +}; +static const char * const blsp_uart4_groups[] = { + "gpio65", "gpio66", "gpio67", "gpio68", +}; +static const char * const blsp_uim4_groups[] = { + "gpio65", "gpio66", +}; +static const char * const qdss_stm16_groups[] = { + "gpio65", +}; +static const char * const qdss_stm15_groups[] = { + "gpio66", +}; +static const char * const dac_calib26_groups[] = { + "gpio67", +}; +static const char * const blsp_i2c4_groups[] = { + "gpio67", "gpio68", +}; +static const char * const qdss_stm14_groups[] = { + "gpio67", +}; +static const char * const spkr_i2s_groups[] = { + "gpio69", "gpio70", "gpio71", "gpio72", +}; +static const char * const audio_ref_groups[] = { + "gpio69", +}; +static const char * const lpass_slimbus_groups[] = { + "gpio70", "gpio71", "gpio72", +}; +static const char * const isense_dbg_groups[] = { + "gpio70", +}; +static const char * const tsense_pwm1_groups[] = { + "gpio71", +}; +static const char * const tsense_pwm2_groups[] = { + "gpio71", +}; +static const char * const btfm_slimbus_groups[] = { + "gpio73", "gpio74", +}; +static const char * const ter_mi2s_groups[] = { + "gpio74", "gpio75", "gpio76", "gpio77", "gpio78", +}; +static const char * const qdss_stm22_groups[] = { + "gpio74", +}; +static const char * const qdss_stm21_groups[] = { + "gpio75", +}; +static const char * const qdss_stm20_groups[] = { + "gpio76", +}; +static const char * const qdss_stm19_groups[] = { + "gpio77", +}; +static const char * const ssc_irq_groups[] = { + "gpio78", "gpio79", "gpio80", "gpio117", "gpio118", "gpio119", + "gpio120", "gpio121", "gpio122", "gpio123", "gpio124", "gpio125", +}; +static const char * const gcc_gp1_clk_b_groups[] = { + "gpio78", +}; +static const char * const sec_mi2s_groups[] = { + "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", +}; +static const char * const blsp_spi5_groups[] = { + "gpio81", "gpio82", "gpio83", "gpio84", +}; +static const char * const blsp_uart5_groups[] = { + "gpio81", "gpio82", "gpio83", "gpio84", +}; +static const char * const blsp_uim5_groups[] = { + "gpio81", "gpio82", +}; +static const char * const gcc_gp2_clk_b_groups[] = { + "gpio81", +}; +static const char * const gcc_gp3_clk_b_groups[] = { + "gpio82", +}; +static const char * const blsp_i2c5_groups[] = { + "gpio83", "gpio84", +}; +static const char * const blsp_spi12_groups[] = { + "gpio85", "gpio86", "gpio87", "gpio88", +}; +static const char * const blsp_uart12_groups[] = { + "gpio85", "gpio86", "gpio87", "gpio88", +}; +static const char * const blsp_uim12_groups[] = { + "gpio85", "gpio86", +}; +static const char * const qdss_stm25_groups[] = { + "gpio85", +}; +static const char * const qdss_stm31_groups[] = { + "gpio86", +}; +static const char * const blsp_i2c12_groups[] = { + "gpio87", "gpio88", +}; +static const char * const qdss_stm30_groups[] = { + "gpio87", +}; +static const char * const qdss_stm29_groups[] = { + "gpio88", +}; +static const char * const tsif1_clk_groups[] = { + "gpio89", +}; +static const char * const qdss_stm28_groups[] = { + "gpio89", +}; +static const char * const tsif1_en_groups[] = { + "gpio90", +}; +static const char * const tsif1_data_groups[] = { + "gpio91", +}; +static const char * const sdc4_cmd_groups[] = { + "gpio91", +}; +static const char * const qdss_stm27_groups[] = { + "gpio91", +}; +static const char * const qdss_traceclk_b_groups[] = { + "gpio91", +}; +static const char * const tsif2_error_groups[] = { + "gpio92", +}; +static const char * const sdc43_groups[] = { + "gpio92", +}; +static const char * const vfr_1_groups[] = { + "gpio92", +}; +static const char * const qdss_stm26_groups[] = { + "gpio92", +}; +static const char * const tsif2_clk_groups[] = { + "gpio93", +}; +static const char * const sdc4_clk_groups[] = { + "gpio93", +}; +static const char * const qdss_stm24_groups[] = { + "gpio93", +}; +static const char * const tsif2_en_groups[] = { + "gpio94", +}; +static const char * const sdc42_groups[] = { + "gpio94", +}; +static const char * const qdss_stm23_groups[] = { + "gpio94", +}; +static const char * const qdss_tracectl_b_groups[] = { + "gpio94", +}; +static const char * const sd_card_groups[] = { + "gpio95", +}; +static const char * const tsif2_data_groups[] = { + "gpio95", +}; +static const char * const sdc41_groups[] = { + "gpio95", +}; +static const char * const tsif2_sync_groups[] = { + "gpio96", +}; +static const char * const sdc40_groups[] = { + "gpio96", +}; +static const char * const mdp_vsync_p_b_groups[] = { + "gpio97", +}; +static const char * const ldo_en_groups[] = { + "gpio97", +}; +static const char * const mdp_vsync_s_b_groups[] = { + "gpio98", +}; +static const char * const ldo_update_groups[] = { + "gpio98", +}; +static const char * const blsp11_uart_tx_b_groups[] = { + "gpio100", +}; +static const char * const blsp11_uart_rx_b_groups[] = { + "gpio101", +}; +static const char * const blsp11_i2c_sda_b_groups[] = { + "gpio102", +}; +static const char * const prng_rosc_groups[] = { + "gpio102", +}; +static const char * const blsp11_i2c_scl_b_groups[] = { + "gpio103", +}; +static const char * const uim2_groups[] = { + "gpio105", "gpio106", "gpio107", "gpio108", +}; +static const char * const uim1_groups[] = { + "gpio109", "gpio110", "gpio111", "gpio112", +}; +static const char * const uim_batt_groups[] = { + "gpio113", +}; +static const char * const pci_e2_groups[] = { + "gpio114", "gpio115", "gpio116", +}; +static const char * const pa_indicator_groups[] = { + "gpio116", +}; +static const char * const adsp_ext_groups[] = { + "gpio118", +}; +static const char * const ddr_bist_groups[] = { + "gpio121", "gpio122", "gpio123", "gpio124", +}; +static const char * const qdss_tracedata_11_groups[] = { + "gpio123", +}; +static const char * const qdss_tracedata_12_groups[] = { + "gpio124", +}; +static const char * const modem_tsync_groups[] = { + "gpio128", +}; +static const char * const nav_dr_groups[] = { + "gpio128", +}; +static const char * const nav_pps_groups[] = { + "gpio128", +}; +static const char * const pci_e1_groups[] = { + "gpio130", "gpio131", "gpio132", +}; +static const char * const gsm_tx_groups[] = { + "gpio134", "gpio135", +}; +static const char * const qspi_cs_groups[] = { + "gpio138", "gpio141", +}; +static const char * const ssbi2_groups[] = { + "gpio139", +}; +static const char * const ssbi1_groups[] = { + "gpio140", +}; +static const char * const mss_lte_groups[] = { + "gpio144", "gpio145", +}; +static const char * const qspi_clk_groups[] = { + "gpio145", +}; +static const char * const qspi0_groups[] = { + "gpio146", +}; +static const char * const qspi1_groups[] = { + "gpio147", +}; +static const char * const qspi2_groups[] = { + "gpio148", +}; +static const char * const qspi3_groups[] = { + "gpio149", +}; + +static const struct msm_function msm8996_functions[] = { + FUNCTION(adsp_ext), + FUNCTION(atest_bbrx0), + FUNCTION(atest_bbrx1), + FUNCTION(atest_char), + FUNCTION(atest_char0), + FUNCTION(atest_char1), + FUNCTION(atest_char2), + FUNCTION(atest_char3), + FUNCTION(atest_gpsadc0), + FUNCTION(atest_gpsadc1), + FUNCTION(atest_tsens), + FUNCTION(atest_tsens2), + FUNCTION(atest_usb1), + FUNCTION(atest_usb10), + FUNCTION(atest_usb11), + FUNCTION(atest_usb12), + FUNCTION(atest_usb13), + FUNCTION(atest_usb2), + FUNCTION(atest_usb20), + FUNCTION(atest_usb21), + FUNCTION(atest_usb22), + FUNCTION(atest_usb23), + FUNCTION(audio_ref), + FUNCTION(bimc_dte0), + FUNCTION(bimc_dte1), + FUNCTION(blsp10_spi), + FUNCTION(blsp11_i2c_scl_b), + FUNCTION(blsp11_i2c_sda_b), + FUNCTION(blsp11_uart_rx_b), + FUNCTION(blsp11_uart_tx_b), + FUNCTION(blsp1_spi), + FUNCTION(blsp2_spi), + FUNCTION(blsp_i2c1), + FUNCTION(blsp_i2c10), + FUNCTION(blsp_i2c11), + FUNCTION(blsp_i2c12), + FUNCTION(blsp_i2c2), + FUNCTION(blsp_i2c3), + FUNCTION(blsp_i2c4), + FUNCTION(blsp_i2c5), + FUNCTION(blsp_i2c6), + FUNCTION(blsp_i2c7), + FUNCTION(blsp_i2c8), + FUNCTION(blsp_i2c9), + FUNCTION(blsp_spi1), + FUNCTION(blsp_spi10), + FUNCTION(blsp_spi11), + FUNCTION(blsp_spi12), + FUNCTION(blsp_spi2), + FUNCTION(blsp_spi3), + FUNCTION(blsp_spi4), + FUNCTION(blsp_spi5), + FUNCTION(blsp_spi6), + FUNCTION(blsp_spi7), + FUNCTION(blsp_spi8), + FUNCTION(blsp_spi9), + FUNCTION(blsp_uart1), + FUNCTION(blsp_uart10), + FUNCTION(blsp_uart11), + FUNCTION(blsp_uart12), + FUNCTION(blsp_uart2), + FUNCTION(blsp_uart3), + FUNCTION(blsp_uart4), + FUNCTION(blsp_uart5), + FUNCTION(blsp_uart6), + FUNCTION(blsp_uart7), + FUNCTION(blsp_uart8), + FUNCTION(blsp_uart9), + FUNCTION(blsp_uim1), + FUNCTION(blsp_uim10), + FUNCTION(blsp_uim11), + FUNCTION(blsp_uim12), + FUNCTION(blsp_uim2), + FUNCTION(blsp_uim3), + FUNCTION(blsp_uim4), + FUNCTION(blsp_uim5), + FUNCTION(blsp_uim6), + FUNCTION(blsp_uim7), + FUNCTION(blsp_uim8), + FUNCTION(blsp_uim9), + FUNCTION(btfm_slimbus), + FUNCTION(cam_mclk), + FUNCTION(cci_async), + FUNCTION(cci_i2c), + FUNCTION(cci_timer0), + FUNCTION(cci_timer1), + FUNCTION(cci_timer2), + FUNCTION(cci_timer3), + FUNCTION(cci_timer4), + FUNCTION(cri_trng), + FUNCTION(cri_trng0), + FUNCTION(cri_trng1), + FUNCTION(dac_calib0), + FUNCTION(dac_calib1), + FUNCTION(dac_calib10), + FUNCTION(dac_calib11), + FUNCTION(dac_calib12), + FUNCTION(dac_calib13), + FUNCTION(dac_calib14), + FUNCTION(dac_calib15), + FUNCTION(dac_calib16), + FUNCTION(dac_calib17), + FUNCTION(dac_calib18), + FUNCTION(dac_calib19), + FUNCTION(dac_calib2), + FUNCTION(dac_calib20), + FUNCTION(dac_calib21), + FUNCTION(dac_calib22), + FUNCTION(dac_calib23), + FUNCTION(dac_calib24), + FUNCTION(dac_calib25), + FUNCTION(dac_calib26), + FUNCTION(dac_calib3), + FUNCTION(dac_calib4), + FUNCTION(dac_calib5), + FUNCTION(dac_calib6), + FUNCTION(dac_calib7), + FUNCTION(dac_calib8), + FUNCTION(dac_calib9), + FUNCTION(dac_gpio), + FUNCTION(dbg_out), + FUNCTION(ddr_bist), + FUNCTION(edp_hot), + FUNCTION(edp_lcd), + FUNCTION(gcc_gp1_clk_a), + FUNCTION(gcc_gp1_clk_b), + FUNCTION(gcc_gp2_clk_a), + FUNCTION(gcc_gp2_clk_b), + FUNCTION(gcc_gp3_clk_a), + FUNCTION(gcc_gp3_clk_b), + FUNCTION(gpio), + FUNCTION(gsm_tx), + FUNCTION(hdmi_cec), + FUNCTION(hdmi_ddc), + FUNCTION(hdmi_hot), + FUNCTION(hdmi_rcv), + FUNCTION(isense_dbg), + FUNCTION(ldo_en), + FUNCTION(ldo_update), + FUNCTION(lpass_slimbus), + FUNCTION(m_voc), + FUNCTION(mdp_vsync), + FUNCTION(mdp_vsync_p_b), + FUNCTION(mdp_vsync_s_b), + FUNCTION(modem_tsync), + FUNCTION(mss_lte), + FUNCTION(nav_dr), + FUNCTION(nav_pps), + FUNCTION(pa_indicator), + FUNCTION(pci_e0), + FUNCTION(pci_e1), + FUNCTION(pci_e2), + FUNCTION(pll_bypassnl), + FUNCTION(pll_reset), + FUNCTION(pri_mi2s), + FUNCTION(prng_rosc), + FUNCTION(pwr_crypto), + FUNCTION(pwr_modem), + FUNCTION(pwr_nav), + FUNCTION(qdss_cti), + FUNCTION(qdss_cti_trig_in_a), + FUNCTION(qdss_cti_trig_in_b), + FUNCTION(qdss_cti_trig_out_a), + FUNCTION(qdss_cti_trig_out_b), + FUNCTION(qdss_stm0), + FUNCTION(qdss_stm1), + FUNCTION(qdss_stm10), + FUNCTION(qdss_stm11), + FUNCTION(qdss_stm12), + FUNCTION(qdss_stm13), + FUNCTION(qdss_stm14), + FUNCTION(qdss_stm15), + FUNCTION(qdss_stm16), + FUNCTION(qdss_stm17), + FUNCTION(qdss_stm18), + FUNCTION(qdss_stm19), + FUNCTION(qdss_stm2), + FUNCTION(qdss_stm20), + FUNCTION(qdss_stm21), + FUNCTION(qdss_stm22), + FUNCTION(qdss_stm23), + FUNCTION(qdss_stm24), + FUNCTION(qdss_stm25), + FUNCTION(qdss_stm26), + FUNCTION(qdss_stm27), + FUNCTION(qdss_stm28), + FUNCTION(qdss_stm29), + FUNCTION(qdss_stm3), + FUNCTION(qdss_stm30), + FUNCTION(qdss_stm31), + FUNCTION(qdss_stm4), + FUNCTION(qdss_stm5), + FUNCTION(qdss_stm6), + FUNCTION(qdss_stm7), + FUNCTION(qdss_stm8), + FUNCTION(qdss_stm9), + FUNCTION(qdss_traceclk_a), + FUNCTION(qdss_traceclk_b), + FUNCTION(qdss_tracectl_a), + FUNCTION(qdss_tracectl_b), + FUNCTION(qdss_tracedata_11), + FUNCTION(qdss_tracedata_12), + FUNCTION(qdss_tracedata_a), + FUNCTION(qdss_tracedata_b), + FUNCTION(qspi0), + FUNCTION(qspi1), + FUNCTION(qspi2), + FUNCTION(qspi3), + FUNCTION(qspi_clk), + FUNCTION(qspi_cs), + FUNCTION(qua_mi2s), + FUNCTION(sd_card), + FUNCTION(sd_write), + FUNCTION(sdc40), + FUNCTION(sdc41), + FUNCTION(sdc42), + FUNCTION(sdc43), + FUNCTION(sdc4_clk), + FUNCTION(sdc4_cmd), + FUNCTION(sec_mi2s), + FUNCTION(spkr_i2s), + FUNCTION(ssbi1), + FUNCTION(ssbi2), + FUNCTION(ssc_irq), + FUNCTION(ter_mi2s), + FUNCTION(tsense_pwm1), + FUNCTION(tsense_pwm2), + FUNCTION(tsif1_clk), + FUNCTION(tsif1_data), + FUNCTION(tsif1_en), + FUNCTION(tsif1_error), + FUNCTION(tsif1_sync), + FUNCTION(tsif2_clk), + FUNCTION(tsif2_data), + FUNCTION(tsif2_en), + FUNCTION(tsif2_error), + FUNCTION(tsif2_sync), + FUNCTION(uim1), + FUNCTION(uim2), + FUNCTION(uim3), + FUNCTION(uim4), + FUNCTION(uim_batt), + FUNCTION(vfr_1), +}; + +static const struct msm_pingroup msm8996_groups[] = { + PINGROUP(0, blsp_spi1, blsp_uart1, blsp_uim1, NA, NA, NA, NA, NA, NA), + PINGROUP(1, blsp_spi1, blsp_uart1, blsp_uim1, NA, NA, NA, NA, NA, NA), + PINGROUP(2, blsp_spi1, blsp_uart1, blsp_i2c1, NA, NA, NA, NA, NA, NA), + PINGROUP(3, blsp_spi1, blsp_uart1, blsp_i2c1, NA, atest_tsens, + bimc_dte1, NA, NA, NA), + PINGROUP(4, blsp_spi8, blsp_uart8, blsp_uim8, NA, qdss_cti_trig_out_b, + dac_calib0, bimc_dte0, NA, NA), + PINGROUP(5, blsp_spi8, blsp_uart8, blsp_uim8, NA, qdss_cti_trig_in_b, + dac_calib1, bimc_dte1, NA, NA), + PINGROUP(6, blsp_spi8, blsp_uart8, blsp_i2c8, NA, dac_calib2, + bimc_dte0, NA, NA, NA), + PINGROUP(7, blsp_spi8, blsp_uart8, blsp_i2c8, NA, atest_tsens2, + atest_usb1, NA, NA, NA), + PINGROUP(8, blsp_spi10, blsp_uart10, blsp_uim10, NA, atest_bbrx1, + atest_usb13, NA, NA, NA), + PINGROUP(9, blsp_spi10, blsp_uart10, blsp_uim10, atest_bbrx0, + atest_usb12, NA, NA, NA, NA), + PINGROUP(10, mdp_vsync, blsp_spi10, blsp_uart10, blsp_i2c10, + atest_gpsadc1, atest_usb11, NA, NA, NA), + PINGROUP(11, mdp_vsync, blsp_spi10, blsp_uart10, blsp_i2c10, + atest_gpsadc0, atest_usb10, NA, NA, NA), + PINGROUP(12, mdp_vsync, m_voc, dac_gpio, atest_char, NA, NA, NA, NA, + NA), + PINGROUP(13, cam_mclk, pll_bypassnl, qdss_stm7, qdss_tracedata_b, NA, + NA, NA, NA, NA), + PINGROUP(14, cam_mclk, pll_reset, qdss_stm6, qdss_tracedata_b, NA, NA, + NA, NA, NA), + PINGROUP(15, cam_mclk, qdss_stm5, qdss_tracedata_b, NA, NA, NA, NA, NA, + NA), + PINGROUP(16, cam_mclk, qdss_stm4, qdss_tracedata_b, NA, atest_usb2, NA, + NA, NA, NA), + PINGROUP(17, cci_i2c, qdss_stm3, qdss_tracedata_b, dac_calib3, + atest_usb23, atest_char3, NA, NA, NA), + PINGROUP(18, cci_i2c, qdss_stm2, qdss_tracedata_b, dac_calib4, + atest_usb22, atest_char2, NA, NA, NA), + PINGROUP(19, cci_i2c, qdss_stm1, qdss_tracedata_b, dac_calib5, + atest_usb21, atest_char1, NA, NA, NA), + PINGROUP(20, cci_i2c, dbg_out, qdss_stm0, dac_calib6, atest_usb20, + atest_char0, NA, NA, NA), + PINGROUP(21, cci_timer0, qdss_stm13, qdss_tracedata_b, dac_calib7, NA, + NA, NA, NA, NA), + PINGROUP(22, cci_timer1, qdss_stm12, qdss_tracedata_b, dac_calib8, NA, + NA, NA, NA, NA), + PINGROUP(23, cci_timer2, blsp1_spi, qdss_stm11, qdss_tracedata_b, + dac_calib9, NA, NA, NA, NA), + PINGROUP(24, cci_timer3, cci_async, blsp1_spi, qdss_stm10, + qdss_cti_trig_in_a, dac_calib10, NA, NA, NA), + PINGROUP(25, cci_timer4, cci_async, blsp_spi6, blsp_uart6, blsp_uim6, + blsp2_spi, qdss_stm9, qdss_cti_trig_out_a, dac_calib11), + PINGROUP(26, cci_async, blsp_spi6, blsp_uart6, blsp_uim6, qdss_stm8, + qdss_tracedata_b, dac_calib12, NA, NA), + PINGROUP(27, blsp_spi6, blsp_uart6, blsp_i2c6, blsp1_spi, + qdss_tracectl_a, dac_calib13, NA, NA, NA), + PINGROUP(28, blsp_spi6, blsp_uart6, blsp_i2c6, blsp1_spi, + qdss_traceclk_a, dac_calib14, NA, NA, NA), + PINGROUP(29, blsp2_spi, NA, qdss_tracedata_b, dac_calib15, NA, NA, NA, + NA, NA), + PINGROUP(30, hdmi_rcv, blsp2_spi, dac_calib16, NA, NA, NA, NA, NA, NA), + PINGROUP(31, hdmi_cec, pwr_modem, dac_calib17, NA, NA, NA, NA, NA, NA), + PINGROUP(32, hdmi_ddc, pwr_nav, NA, dac_calib18, NA, NA, NA, NA, NA), + PINGROUP(33, hdmi_ddc, pwr_crypto, NA, dac_calib19, NA, NA, NA, NA, NA), + PINGROUP(34, hdmi_hot, NA, dac_calib20, NA, NA, NA, NA, NA, NA), + PINGROUP(35, pci_e0, NA, dac_calib21, NA, NA, NA, NA, NA, NA), + PINGROUP(36, pci_e0, NA, dac_calib22, NA, NA, NA, NA, NA, NA), + PINGROUP(37, NA, dac_calib23, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(38, NA, dac_calib24, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(39, tsif1_sync, NA, dac_calib25, NA, NA, NA, NA, NA, NA), + PINGROUP(40, sd_write, tsif1_error, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(41, blsp_spi2, blsp_uart2, blsp_uim2, NA, qdss_cti, + dac_calib0, NA, NA, NA), + PINGROUP(42, blsp_spi2, blsp_uart2, blsp_uim2, NA, qdss_cti, + dac_calib1, NA, NA, NA), + PINGROUP(43, blsp_spi2, blsp_uart2, blsp_i2c2, NA, dac_calib2, NA, NA, + NA, NA), + PINGROUP(44, blsp_spi2, blsp_uart2, blsp_i2c2, NA, dac_calib3, NA, NA, + NA, NA), + PINGROUP(45, blsp_spi3, blsp_uart3, blsp_uim3, NA, dac_calib4, NA, NA, + NA, NA), + PINGROUP(46, blsp_spi3, blsp_uart3, blsp_uim3, NA, dac_calib5, NA, NA, + NA, NA), + PINGROUP(47, blsp_spi3, blsp_uart3, blsp_i2c3, dac_calib6, NA, NA, NA, + NA, NA), + PINGROUP(48, blsp_spi3, blsp_uart3, blsp_i2c3, dac_calib7, NA, NA, NA, + NA, NA), + PINGROUP(49, uim3, blsp_spi9, blsp_uart9, blsp_uim9, blsp10_spi, + dac_calib8, NA, NA, NA), + PINGROUP(50, uim3, blsp_spi9, blsp_uart9, blsp_uim9, blsp10_spi, + dac_calib9, NA, NA, NA), + PINGROUP(51, uim3, blsp_spi9, blsp_uart9, blsp_i2c9, blsp10_spi, + dac_calib10, NA, NA, NA), + PINGROUP(52, uim3, blsp_spi9, blsp_uart9, blsp_i2c9, + blsp10_spi, dac_calib11, NA, NA, NA), + PINGROUP(53, blsp_spi7, blsp_uart7, blsp_uim7, NA, qdss_tracedata_a, + dac_calib12, NA, NA, NA), + PINGROUP(54, blsp_spi7, blsp_uart7, blsp_uim7, NA, NA, + qdss_tracedata_a, dac_calib13, NA, NA), + PINGROUP(55, blsp_spi7, blsp_uart7, blsp_i2c7, NA, dac_calib14, NA, NA, + NA, NA), + PINGROUP(56, blsp_spi7, blsp_uart7, blsp_i2c7, NA, dac_calib15, NA, NA, + NA, NA), + PINGROUP(57, qua_mi2s, gcc_gp1_clk_a, NA, qdss_tracedata_b, + dac_calib16, NA, NA, NA, NA), + PINGROUP(58, qua_mi2s, uim4, blsp_spi11, blsp_uart11, blsp_uim11, + gcc_gp2_clk_a, NA, qdss_tracedata_b, dac_calib17), + PINGROUP(59, qua_mi2s, uim4, blsp_spi11, blsp_uart11, blsp_uim11, + gcc_gp3_clk_a, NA, dac_calib18, NA), + PINGROUP(60, qua_mi2s, uim4, blsp_spi11, blsp_uart11, blsp_i2c11, + cri_trng0, NA, dac_calib19, NA), + PINGROUP(61, qua_mi2s, uim4, blsp_spi11, blsp_uart11, + blsp_i2c11, cri_trng1, NA, dac_calib20, NA), + PINGROUP(62, qua_mi2s, cri_trng, NA, dac_calib21, NA, NA, NA, NA, NA), + PINGROUP(63, qua_mi2s, NA, NA, qdss_stm18, qdss_tracedata_a, + dac_calib22, NA, NA, NA), + PINGROUP(64, pri_mi2s, NA, qdss_stm17, qdss_tracedata_a, dac_calib23, + NA, NA, NA, NA), + PINGROUP(65, pri_mi2s, blsp_spi4, blsp_uart4, blsp_uim4, NA, + qdss_stm16, qdss_tracedata_a, dac_calib24, NA), + PINGROUP(66, pri_mi2s, blsp_spi4, blsp_uart4, blsp_uim4, NA, + qdss_stm15, qdss_tracedata_a, dac_calib25, NA), + PINGROUP(67, pri_mi2s, blsp_spi4, blsp_uart4, blsp_i2c4, qdss_stm14, + qdss_tracedata_a, dac_calib26, NA, NA), + PINGROUP(68, pri_mi2s, blsp_spi4, blsp_uart4, blsp_i2c4, NA, NA, NA, + NA, NA), + PINGROUP(69, spkr_i2s, audio_ref, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(70, lpass_slimbus, spkr_i2s, isense_dbg, NA, NA, NA, NA, NA, + NA), + PINGROUP(71, lpass_slimbus, spkr_i2s, tsense_pwm1, tsense_pwm2, NA, NA, + NA, NA, NA), + PINGROUP(72, lpass_slimbus, spkr_i2s, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(73, btfm_slimbus, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(74, btfm_slimbus, ter_mi2s, qdss_stm22, qdss_tracedata_a, NA, + NA, NA, NA, NA), + PINGROUP(75, ter_mi2s, qdss_stm21, qdss_tracedata_a, NA, NA, NA, NA, + NA, NA), + PINGROUP(76, ter_mi2s, qdss_stm20, qdss_tracedata_a, NA, NA, NA, NA, + NA, NA), + PINGROUP(77, ter_mi2s, qdss_stm19, qdss_tracedata_a, NA, NA, NA, NA, + NA, NA), + PINGROUP(78, ter_mi2s, gcc_gp1_clk_b, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(79, sec_mi2s, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(80, sec_mi2s, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(81, sec_mi2s, blsp_spi5, blsp_uart5, blsp_uim5, gcc_gp2_clk_b, + NA, NA, NA, NA), + PINGROUP(82, sec_mi2s, blsp_spi5, blsp_uart5, blsp_uim5, gcc_gp3_clk_b, + NA, NA, NA, NA), + PINGROUP(83, sec_mi2s, blsp_spi5, blsp_uart5, blsp_i2c5, NA, NA, NA, + NA, NA), + PINGROUP(84, blsp_spi5, blsp_uart5, blsp_i2c5, NA, NA, NA, NA, NA, NA), + PINGROUP(85, blsp_spi12, blsp_uart12, blsp_uim12, NA, qdss_stm25, + qdss_tracedata_a, NA, NA, NA), + PINGROUP(86, blsp_spi12, blsp_uart12, blsp_uim12, NA, NA, qdss_stm31, + qdss_tracedata_a, NA, NA), + PINGROUP(87, blsp_spi12, blsp_uart12, blsp_i2c12, NA, qdss_stm30, + qdss_tracedata_a, NA, NA, NA), + PINGROUP(88, blsp_spi12, blsp_uart12, blsp_i2c12, blsp10_spi, NA, + qdss_stm29, NA, NA, NA), + PINGROUP(89, tsif1_clk, qdss_stm28, qdss_tracedata_a, NA, NA, NA, NA, + NA, NA), + PINGROUP(90, tsif1_en, blsp1_spi, qdss_tracedata_a, NA, NA, NA, NA, NA, + NA), + PINGROUP(91, tsif1_data, sdc4_cmd, qdss_stm27, qdss_traceclk_b, NA, NA, + NA, NA, NA), + PINGROUP(92, tsif2_error, sdc43, vfr_1, qdss_stm26, qdss_tracedata_b, + NA, NA, NA, NA), + PINGROUP(93, tsif2_clk, sdc4_clk, NA, qdss_stm24, qdss_tracedata_b, NA, + NA, NA, NA), + PINGROUP(94, tsif2_en, sdc42, NA, qdss_stm23, qdss_tracectl_b, NA, NA, + NA, NA), + PINGROUP(95, tsif2_data, sdc41, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(96, tsif2_sync, sdc40, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(97, NA, NA, mdp_vsync_p_b, ldo_en, NA, NA, NA, NA, NA), + PINGROUP(98, NA, NA, mdp_vsync_s_b, ldo_update, NA, NA, NA, NA, NA), + PINGROUP(99, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(100, NA, NA, blsp11_uart_tx_b, qdss_cti, NA, NA, NA, NA, NA), + PINGROUP(101, NA, blsp11_uart_rx_b, qdss_cti, NA, NA, NA, NA, NA, NA), + PINGROUP(102, NA, blsp11_i2c_sda_b, prng_rosc, NA, NA, NA, NA, NA, NA), + PINGROUP(103, NA, blsp11_i2c_scl_b, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(104, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(105, uim2, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(106, uim2, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(107, uim2, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(108, uim2, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(109, uim1, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(110, uim1, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(111, uim1, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(112, uim1, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(113, uim_batt, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(114, NA, pci_e2, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(115, NA, pci_e2, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(116, NA, pa_indicator, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(117, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(118, adsp_ext, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(119, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(120, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(121, ddr_bist, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(122, ddr_bist, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(123, ddr_bist, qdss_tracedata_11, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(124, ddr_bist, qdss_tracedata_12, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(125, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(126, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(127, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(128, NA, modem_tsync, nav_dr, nav_pps, NA, NA, NA, NA, NA), + PINGROUP(129, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(130, pci_e1, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(131, pci_e1, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(132, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(133, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(134, gsm_tx, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(135, gsm_tx, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(136, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(137, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(138, NA, qspi_cs, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(139, NA, ssbi2, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(140, NA, ssbi1, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(141, NA, qspi_cs, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(142, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(143, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(144, mss_lte, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(145, mss_lte, qspi_clk, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(146, NA, qspi0, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(147, NA, qspi1, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(148, NA, qspi2, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(149, NA, qspi3, NA, NA, NA, NA, NA, NA, NA), + SDC_QDSD_PINGROUP(sdc1_clk, 0x12c000, 13, 6), + SDC_QDSD_PINGROUP(sdc1_cmd, 0x12c000, 11, 3), + SDC_QDSD_PINGROUP(sdc1_data, 0x12c000, 9, 0), + SDC_QDSD_PINGROUP(sdc2_clk, 0x12d000, 14, 6), + SDC_QDSD_PINGROUP(sdc2_cmd, 0x12d000, 11, 3), + SDC_QDSD_PINGROUP(sdc2_data, 0x12d000, 9, 0), + SDC_QDSD_PINGROUP(sdc1_rclk, 0x12c000, 15, 0), +}; + +static const struct msm_pinctrl_soc_data msm8996_pinctrl = { + .pins = msm8996_pins, + .npins = ARRAY_SIZE(msm8996_pins), + .functions = msm8996_functions, + .nfunctions = ARRAY_SIZE(msm8996_functions), + .groups = msm8996_groups, + .ngroups = ARRAY_SIZE(msm8996_groups), + .ngpios = 150, +}; + +static int msm8996_pinctrl_probe(struct platform_device *pdev) +{ + return msm_pinctrl_probe(pdev, &msm8996_pinctrl); +} + +static const struct of_device_id msm8996_pinctrl_of_match[] = { + { .compatible = "qcom,msm8996-pinctrl", }, + { } +}; + +static struct platform_driver msm8996_pinctrl_driver = { + .driver = { + .name = "msm8996-pinctrl", + .of_match_table = msm8996_pinctrl_of_match, + }, + .probe = msm8996_pinctrl_probe, + .remove = msm_pinctrl_remove, +}; + +static int __init msm8996_pinctrl_init(void) +{ + return platform_driver_register(&msm8996_pinctrl_driver); +} +arch_initcall(msm8996_pinctrl_init); + +static void __exit msm8996_pinctrl_exit(void) +{ + platform_driver_unregister(&msm8996_pinctrl_driver); +} +module_exit(msm8996_pinctrl_exit); + +MODULE_DESCRIPTION("Qualcomm msm8996 pinctrl driver"); +MODULE_LICENSE("GPL v2"); +MODULE_DEVICE_TABLE(of, msm8996_pinctrl_of_match); -- cgit v0.10.2 From 016c2f4d2013817e10e30251cc5aadbc26a4c919 Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Tue, 17 Nov 2015 16:52:32 -0800 Subject: pinctrl: qcom: spmi-gpio: Add pm8994 gpio support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Update the binding and driver for pm8994-gpio devices. Cc: Cc: "Ivan T. Ivanov" Signed-off-by: Stephen Boyd Acked-by: Rob Herring Acked-by: Björn Andersson Signed-off-by: Linus Walleij diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.txt b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.txt index 1ae63c0..a90c812 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.txt +++ b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.txt @@ -14,6 +14,7 @@ PMIC's from Qualcomm. "qcom,pm8917-gpio" "qcom,pm8921-gpio" "qcom,pm8941-gpio" + "qcom,pm8994-gpio" "qcom,pma8084-gpio" - reg: @@ -79,6 +80,7 @@ to specify in a pin configuration subnode: gpio1-gpio38 for pm8917 gpio1-gpio44 for pm8921 gpio1-gpio36 for pm8941 + gpio1-gpio22 for pm8994 gpio1-gpio22 for pma8084 - function: diff --git a/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c b/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c index 543cdd6..4eea62a 100644 --- a/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c +++ b/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c @@ -804,6 +804,7 @@ static int pmic_gpio_remove(struct platform_device *pdev) static const struct of_device_id pmic_gpio_of_match[] = { { .compatible = "qcom,pm8916-gpio" }, /* 4 GPIO's */ { .compatible = "qcom,pm8941-gpio" }, /* 36 GPIO's */ + { .compatible = "qcom,pm8994-gpio" }, /* 22 GPIO's */ { .compatible = "qcom,pma8084-gpio" }, /* 22 GPIO's */ { }, }; -- cgit v0.10.2 From eb9610f3d48081528f0d0e35e29b28ad1de6dac6 Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Tue, 17 Nov 2015 16:52:33 -0800 Subject: pinctrl: qcom: spmi-mpp: Add pm8994 mpp support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Update the driver and binding for pm8994-mpp devices. Cc: Cc: "Ivan T. Ivanov" Signed-off-by: Stephen Boyd Acked-by: Rob Herring Acked-by: Björn Andersson Signed-off-by: Linus Walleij diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.txt b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.txt index d7803a2..d74e631 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.txt +++ b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.txt @@ -15,6 +15,7 @@ of PMIC's from Qualcomm. "qcom,pm8917-mpp", "qcom,pm8921-mpp", "qcom,pm8941-mpp", + "qcom,pm8994-mpp", "qcom,pma8084-mpp", - reg: diff --git a/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c b/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c index d778fb9..8841bb7 100644 --- a/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c +++ b/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c @@ -908,6 +908,7 @@ static const struct of_device_id pmic_mpp_of_match[] = { { .compatible = "qcom,pm8841-mpp" }, /* 4 MPP's */ { .compatible = "qcom,pm8916-mpp" }, /* 4 MPP's */ { .compatible = "qcom,pm8941-mpp" }, /* 8 MPP's */ + { .compatible = "qcom,pm8994-mpp" }, /* 8 MPP's */ { .compatible = "qcom,pma8084-mpp" }, /* 8 MPP's */ { }, }; -- cgit v0.10.2 From b9a4e155458c73f125a248c963665a8df982496f Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Tue, 24 Nov 2015 15:00:45 +0900 Subject: pinctrl: uniphier: rework UniPhier pinctrl entries in Kconfig There is a plan to support more pinctrl drivers for this SoC family. Move the driver entries into a sub menu by using "menuconfig". Also, add the missing dependency "depends on OF && MFD_SYSCON". Signed-off-by: Masahiro Yamada Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/uniphier/Kconfig b/drivers/pinctrl/uniphier/Kconfig index ad90707..7abd614 100644 --- a/drivers/pinctrl/uniphier/Kconfig +++ b/drivers/pinctrl/uniphier/Kconfig @@ -1,32 +1,35 @@ -if ARCH_UNIPHIER - -config PINCTRL_UNIPHIER - bool +menuconfig PINCTRL_UNIPHIER + bool "UniPhier SoC pinctrl drivers" + depends on ARCH_UNIPHIER + depends on OF && MFD_SYSCON + default y select PINMUX select GENERIC_PINCONF +if PINCTRL_UNIPHIER + config PINCTRL_UNIPHIER_PH1_LD4 tristate "UniPhier PH1-LD4 SoC pinctrl driver" - select PINCTRL_UNIPHIER + default y config PINCTRL_UNIPHIER_PH1_PRO4 tristate "UniPhier PH1-Pro4 SoC pinctrl driver" - select PINCTRL_UNIPHIER + default y config PINCTRL_UNIPHIER_PH1_SLD8 tristate "UniPhier PH1-sLD8 SoC pinctrl driver" - select PINCTRL_UNIPHIER + default y config PINCTRL_UNIPHIER_PH1_PRO5 tristate "UniPhier PH1-Pro5 SoC pinctrl driver" - select PINCTRL_UNIPHIER + default y config PINCTRL_UNIPHIER_PROXSTREAM2 tristate "UniPhier ProXstream2 SoC pinctrl driver" - select PINCTRL_UNIPHIER + default y config PINCTRL_UNIPHIER_PH1_LD6B tristate "UniPhier PH1-LD6b SoC pinctrl driver" - select PINCTRL_UNIPHIER + default y endif -- cgit v0.10.2 From 1bcb2021d58f2be51a43589faf38355fc6b1ee4f Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Tue, 24 Nov 2015 20:45:22 +0900 Subject: pinctrl: berlin: guard sub-directory with CONFIG_PINCTRL_BERLIN CONFIG_PINCTRL_BERLIN is more suitable than CONFIG_ARCH_BERLIN to guard the drivers/pinctrl/berlin/ directory. Signed-off-by: Masahiro Yamada Acked-by: Jisheng Zhang Acked-by: Sebastian Hesselbarth Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index 738cb49..17c0206 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -41,7 +41,7 @@ obj-$(CONFIG_PINCTRL_ST) += pinctrl-st.o obj-$(CONFIG_PINCTRL_ZYNQ) += pinctrl-zynq.o obj-$(CONFIG_ARCH_BCM) += bcm/ -obj-$(CONFIG_ARCH_BERLIN) += berlin/ +obj-$(CONFIG_PINCTRL_BERLIN) += berlin/ obj-y += freescale/ obj-$(CONFIG_X86) += intel/ obj-$(CONFIG_PLAT_ORION) += mvebu/ diff --git a/drivers/pinctrl/berlin/Makefile b/drivers/pinctrl/berlin/Makefile index 06f9402..6f641ce 100644 --- a/drivers/pinctrl/berlin/Makefile +++ b/drivers/pinctrl/berlin/Makefile @@ -1,4 +1,4 @@ -obj-$(CONFIG_PINCTRL_BERLIN) += berlin.o +obj-y += berlin.o obj-$(CONFIG_PINCTRL_BERLIN_BG2) += berlin-bg2.o obj-$(CONFIG_PINCTRL_BERLIN_BG2CD) += berlin-bg2cd.o obj-$(CONFIG_PINCTRL_BERLIN_BG2Q) += berlin-bg2q.o -- cgit v0.10.2 From 973bbcfa1707b1e883ebed7ce5a30b21df8c85c0 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Tue, 24 Nov 2015 20:45:23 +0900 Subject: pinctrl: mvebu: guard sub-directory with CONFIG_PINCTRL_MVEBU CONFIG_PINCTRL_MVEBU is more suitable than CONFIG_PLAT_ORION to guard the drivers/pinctrl/mvebu/ directory. Signed-off-by: Masahiro Yamada Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index 17c0206..cdc4a61 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -44,7 +44,7 @@ obj-$(CONFIG_ARCH_BCM) += bcm/ obj-$(CONFIG_PINCTRL_BERLIN) += berlin/ obj-y += freescale/ obj-$(CONFIG_X86) += intel/ -obj-$(CONFIG_PLAT_ORION) += mvebu/ +obj-$(CONFIG_PINCTRL_MVEBU) += mvebu/ obj-y += nomadik/ obj-$(CONFIG_ARCH_QCOM) += qcom/ obj-$(CONFIG_PINCTRL_SAMSUNG) += samsung/ diff --git a/drivers/pinctrl/mvebu/Makefile b/drivers/pinctrl/mvebu/Makefile index 554d8af..18270cd 100644 --- a/drivers/pinctrl/mvebu/Makefile +++ b/drivers/pinctrl/mvebu/Makefile @@ -1,4 +1,4 @@ -obj-$(CONFIG_PINCTRL_MVEBU) += pinctrl-mvebu.o +obj-y += pinctrl-mvebu.o obj-$(CONFIG_PINCTRL_DOVE) += pinctrl-dove.o obj-$(CONFIG_PINCTRL_KIRKWOOD) += pinctrl-kirkwood.o obj-$(CONFIG_PINCTRL_ARMADA_370) += pinctrl-armada-370.o -- cgit v0.10.2 From 2f9c2424f6bf12260e0fa551edda82b63d0808aa Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Tue, 24 Nov 2015 20:45:24 +0900 Subject: pinctrl: spear: guard sub-directory with CONFIG_PINCTRL_SPEAR CONFIG_PINCTRL_SPEAR is more suitable than CONFIG_PLAT_SPEAR to guard the drivers/pinctrl/spear/ directory. Signed-off-by: Masahiro Yamada Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index cdc4a61..22a02f3 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -49,7 +49,7 @@ obj-y += nomadik/ obj-$(CONFIG_ARCH_QCOM) += qcom/ obj-$(CONFIG_PINCTRL_SAMSUNG) += samsung/ obj-$(CONFIG_PINCTRL_SH_PFC) += sh-pfc/ -obj-$(CONFIG_PLAT_SPEAR) += spear/ +obj-$(CONFIG_PINCTRL_SPEAR) += spear/ obj-$(CONFIG_ARCH_SUNXI) += sunxi/ obj-$(CONFIG_PINCTRL_UNIPHIER) += uniphier/ obj-$(CONFIG_ARCH_VT8500) += vt8500/ diff --git a/drivers/pinctrl/spear/Makefile b/drivers/pinctrl/spear/Makefile index 0e400eb..37b8412 100644 --- a/drivers/pinctrl/spear/Makefile +++ b/drivers/pinctrl/spear/Makefile @@ -1,7 +1,7 @@ # SPEAr pinmux support obj-$(CONFIG_PINCTRL_SPEAR_PLGPIO) += pinctrl-plgpio.o -obj-$(CONFIG_PINCTRL_SPEAR) += pinctrl-spear.o +obj-y += pinctrl-spear.o obj-$(CONFIG_PINCTRL_SPEAR3XX) += pinctrl-spear3xx.o obj-$(CONFIG_PINCTRL_SPEAR300) += pinctrl-spear300.o obj-$(CONFIG_PINCTRL_SPEAR310) += pinctrl-spear310.o -- cgit v0.10.2 From 485dba27e9710fd03e7b35df4d7c4c562286f20e Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Mon, 30 Nov 2015 16:57:35 +0900 Subject: pinctrl: fix a typo in Kconfig Signed-off-by: Masahiro Yamada Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index b422e4e..eb434d4 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -246,7 +246,7 @@ config PINCTRL_ZYNQ select PINMUX select GENERIC_PINCONF help - This selectes the pinctrl driver for Xilinx Zynq. + This selects the pinctrl driver for Xilinx Zynq. source "drivers/pinctrl/bcm/Kconfig" source "drivers/pinctrl/berlin/Kconfig" -- cgit v0.10.2 From d9ac5e25f1335bb16c638736bf25146a550eb394 Mon Sep 17 00:00:00 2001 From: Yingjoe Chen Date: Wed, 25 Nov 2015 20:13:23 +0800 Subject: pinctrl: update document for pinconf_generic_parse_dt_config The returned configs from pinconf_generic_parse_dt_config() is duplicated from original. Make it clear it must be freed when no longer necessary. Signed-off-by: Yingjoe Chen Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/pinconf-generic.c b/drivers/pinctrl/pinconf-generic.c index 099a344..79e6159 100644 --- a/drivers/pinctrl/pinconf-generic.c +++ b/drivers/pinctrl/pinconf-generic.c @@ -220,6 +220,7 @@ static void parse_dt_cfg(struct device_node *np, * parse the config properties into generic pinconfig values. * @np: node containing the pinconfig properties * @configs: array with nconfigs entries containing the generic pinconf values + * must be freed when no longer necessary. * @nconfigs: umber of configurations */ int pinconf_generic_parse_dt_config(struct device_node *np, -- cgit v0.10.2 From c5cdcba3d54b9bd2443bd0afe9f4828f802a944f Mon Sep 17 00:00:00 2001 From: Qipeng Zha Date: Thu, 26 Nov 2015 01:09:51 +0800 Subject: pinctrl: intel: fix bug of register offset calculation The group size for registers PADCFGLOCK, HOSTSW_OWN, GPI_IS, GPI_IE, are not 24 for Broxton, Add a parameter to allow different platform to set correct value. Signed-off-by: Qi Zheng Signed-off-by: Qipeng Zha Acked-by: Mika Westerberg Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/intel/pinctrl-broxton.c b/drivers/pinctrl/intel/pinctrl-broxton.c index e42d5d4..5979d38 100644 --- a/drivers/pinctrl/intel/pinctrl-broxton.c +++ b/drivers/pinctrl/intel/pinctrl-broxton.c @@ -28,6 +28,7 @@ .padcfglock_offset = BXT_PADCFGLOCK, \ .hostown_offset = BXT_HOSTSW_OWN, \ .ie_offset = BXT_GPI_IE, \ + .gpp_size = 32, \ .pin_base = (s), \ .npins = ((e) - (s) + 1), \ } diff --git a/drivers/pinctrl/intel/pinctrl-intel.c b/drivers/pinctrl/intel/pinctrl-intel.c index 392e28d..06004d8 100644 --- a/drivers/pinctrl/intel/pinctrl-intel.c +++ b/drivers/pinctrl/intel/pinctrl-intel.c @@ -25,9 +25,6 @@ #include "pinctrl-intel.h" -/* Maximum number of pads in each group */ -#define NPADS_IN_GPP 24 - /* Offset from regs */ #define PADBAR 0x00c #define GPI_IS 0x100 @@ -173,11 +170,11 @@ static bool intel_pad_acpi_mode(struct intel_pinctrl *pctrl, unsigned pin) return false; padno = pin_to_padno(community, pin); - gpp = padno / NPADS_IN_GPP; + gpp = padno / community->gpp_size; offset = community->hostown_offset + gpp * 4; hostown = community->regs + offset; - return !(readl(hostown) & BIT(padno % NPADS_IN_GPP)); + return !(readl(hostown) & BIT(padno % community->gpp_size)); } static bool intel_pad_locked(struct intel_pinctrl *pctrl, unsigned pin) @@ -193,7 +190,7 @@ static bool intel_pad_locked(struct intel_pinctrl *pctrl, unsigned pin) return false; padno = pin_to_padno(community, pin); - gpp = padno / NPADS_IN_GPP; + gpp = padno / community->gpp_size; /* * If PADCFGLOCK and PADCFGLOCKTX bits are both clear for this pad, @@ -202,12 +199,12 @@ static bool intel_pad_locked(struct intel_pinctrl *pctrl, unsigned pin) */ offset = community->padcfglock_offset + gpp * 8; value = readl(community->regs + offset); - if (value & BIT(pin % NPADS_IN_GPP)) + if (value & BIT(pin % community->gpp_size)) return true; offset = community->padcfglock_offset + 4 + gpp * 8; value = readl(community->regs + offset); - if (value & BIT(pin % NPADS_IN_GPP)) + if (value & BIT(pin % community->gpp_size)) return true; return false; @@ -663,8 +660,8 @@ static void intel_gpio_irq_ack(struct irq_data *d) community = intel_get_community(pctrl, pin); if (community) { unsigned padno = pin_to_padno(community, pin); - unsigned gpp_offset = padno % NPADS_IN_GPP; - unsigned gpp = padno / NPADS_IN_GPP; + unsigned gpp_offset = padno % community->gpp_size; + unsigned gpp = padno / community->gpp_size; writel(BIT(gpp_offset), community->regs + GPI_IS + gpp * 4); } @@ -685,8 +682,8 @@ static void intel_gpio_irq_mask_unmask(struct irq_data *d, bool mask) community = intel_get_community(pctrl, pin); if (community) { unsigned padno = pin_to_padno(community, pin); - unsigned gpp_offset = padno % NPADS_IN_GPP; - unsigned gpp = padno / NPADS_IN_GPP; + unsigned gpp_offset = padno % community->gpp_size; + unsigned gpp = padno / community->gpp_size; void __iomem *reg; u32 value; @@ -780,8 +777,8 @@ static int intel_gpio_irq_wake(struct irq_data *d, unsigned int on) return -EINVAL; padno = pin_to_padno(community, pin); - gpp = padno / NPADS_IN_GPP; - gpp_offset = padno % NPADS_IN_GPP; + gpp = padno / community->gpp_size; + gpp_offset = padno % community->gpp_size; /* Clear the existing wake status */ writel(BIT(gpp_offset), community->regs + GPI_GPE_STS + gpp * 4); @@ -819,14 +816,14 @@ static irqreturn_t intel_gpio_community_irq_handler(struct intel_pinctrl *pctrl, /* Only interrupts that are enabled */ pending &= enabled; - for_each_set_bit(gpp_offset, &pending, NPADS_IN_GPP) { + for_each_set_bit(gpp_offset, &pending, community->gpp_size) { unsigned padno, irq; /* * The last group in community can have less pins * than NPADS_IN_GPP. */ - padno = gpp_offset + gpp * NPADS_IN_GPP; + padno = gpp_offset + gpp * community->gpp_size; if (padno >= community->npins) break; @@ -1002,7 +999,8 @@ int intel_pinctrl_probe(struct platform_device *pdev, community->regs = regs; community->pad_regs = regs + padbar; - community->ngpps = DIV_ROUND_UP(community->npins, NPADS_IN_GPP); + community->ngpps = DIV_ROUND_UP(community->npins, + community->gpp_size); } irq = platform_get_irq(pdev, 0); diff --git a/drivers/pinctrl/intel/pinctrl-intel.h b/drivers/pinctrl/intel/pinctrl-intel.h index 4ec8b57..b602157 100644 --- a/drivers/pinctrl/intel/pinctrl-intel.h +++ b/drivers/pinctrl/intel/pinctrl-intel.h @@ -55,6 +55,8 @@ struct intel_function { * ACPI). * @ie_offset: Register offset of GPI_IE from @regs. * @pin_base: Starting pin of pins in this community + * @gpp_size: Maximum number of pads in each group, such as PADCFGLOCK, + * HOSTSW_OWN, GPI_IS, GPI_IE, etc. * @npins: Number of pins in this community * @regs: Community specific common registers (reserved for core driver) * @pad_regs: Community specific pad registers (reserved for core driver) @@ -68,6 +70,7 @@ struct intel_community { unsigned hostown_offset; unsigned ie_offset; unsigned pin_base; + unsigned gpp_size; size_t npins; void __iomem *regs; void __iomem *pad_regs; diff --git a/drivers/pinctrl/intel/pinctrl-sunrisepoint.c b/drivers/pinctrl/intel/pinctrl-sunrisepoint.c index 1de9ae5..c725a53 100644 --- a/drivers/pinctrl/intel/pinctrl-sunrisepoint.c +++ b/drivers/pinctrl/intel/pinctrl-sunrisepoint.c @@ -30,6 +30,7 @@ .padcfglock_offset = SPT_PADCFGLOCK, \ .hostown_offset = SPT_HOSTSW_OWN, \ .ie_offset = SPT_GPI_IE, \ + .gpp_size = 24, \ .pin_base = (s), \ .npins = ((e) - (s) + 1), \ } -- cgit v0.10.2 From d81d8717c6c0f22c61c6e05ac3c6409b5021999c Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 25 Nov 2015 11:25:01 +0100 Subject: pinctrl: sh-pfc: emev2: Use PINMUX_SINGLE() instead of raw PINMUX_DATA() Signed-off-by: Geert Uytterhoeven diff --git a/drivers/pinctrl/sh-pfc/pfc-emev2.c b/drivers/pinctrl/sh-pfc/pfc-emev2.c index 02118ab..a3a4b67 100644 --- a/drivers/pinctrl/sh-pfc/pfc-emev2.c +++ b/drivers/pinctrl/sh-pfc/pfc-emev2.c @@ -258,18 +258,18 @@ static const u16 pinmux_data[] = { /* GPSR0 */ /* V9 */ - PINMUX_DATA(JT_SEL_MARK, FN_JT_SEL), + PINMUX_SINGLE(JT_SEL), /* U9 */ - PINMUX_DATA(ERR_RST_REQB_MARK, FN_ERR_RST_REQB), + PINMUX_SINGLE(ERR_RST_REQB), /* V8 */ - PINMUX_DATA(REF_CLKO_MARK, FN_REF_CLKO), + PINMUX_SINGLE(REF_CLKO), /* U8 */ - PINMUX_DATA(EXT_CLKI_MARK, FN_EXT_CLKI), + PINMUX_SINGLE(EXT_CLKI), /* B22*/ PINMUX_IPSR_NOFN(LCD3_1_0_PORT18, LCD3_PXCLK, SEL_LCD3_1_0_00), PINMUX_IPSR_NOFN(LCD3_1_0_PORT18, YUV3_CLK_O, SEL_LCD3_1_0_01), /* C21 */ - PINMUX_DATA(LCD3_PXCLKB_MARK, FN_LCD3_PXCLKB), + PINMUX_SINGLE(LCD3_PXCLKB), /* A21 */ PINMUX_IPSR_NOFN(LCD3_1_0_PORT20, LCD3_CLK_I, SEL_LCD3_1_0_00), PINMUX_IPSR_NOFN(LCD3_1_0_PORT20, YUV3_CLK_I, SEL_LCD3_1_0_01), @@ -285,17 +285,17 @@ static const u16 pinmux_data[] = { /* GPSR1 */ /* A20 */ - PINMUX_DATA(LCD3_R0_MARK, FN_LCD3_R0), + PINMUX_SINGLE(LCD3_R0), /* B20 */ - PINMUX_DATA(LCD3_R1_MARK, FN_LCD3_R1), + PINMUX_SINGLE(LCD3_R1), /* A19 */ - PINMUX_DATA(LCD3_R2_MARK, FN_LCD3_R2), + PINMUX_SINGLE(LCD3_R2), /* B19 */ - PINMUX_DATA(LCD3_R3_MARK, FN_LCD3_R3), + PINMUX_SINGLE(LCD3_R3), /* C19 */ - PINMUX_DATA(LCD3_R4_MARK, FN_LCD3_R4), + PINMUX_SINGLE(LCD3_R4), /* B18 */ - PINMUX_DATA(LCD3_R5_MARK, FN_LCD3_R5), + PINMUX_SINGLE(LCD3_R5), /* C18 */ PINMUX_IPSR_NOFN(LCD3_9_8_PORT38, LCD3_R6, SEL_LCD3_9_8_00), PINMUX_IPSR_NOFN(LCD3_9_8_PORT38, TP33_CLK, SEL_LCD3_9_8_10), @@ -367,9 +367,9 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, YUV3_D15, SEL_LCD3_11_10_01), PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, TP33_DATA15, SEL_LCD3_11_10_10), /* AA9 */ - PINMUX_DATA(IIC0_SCL_MARK, FN_IIC0_SCL), + PINMUX_SINGLE(IIC0_SCL), /* AA8 */ - PINMUX_DATA(IIC0_SDA_MARK, FN_IIC0_SDA), + PINMUX_SINGLE(IIC0_SDA), /* Y9 */ PINMUX_IPSR_NOFN(IIC_1_0_PORT46, IIC1_SCL, SEL_IIC_1_0_00), PINMUX_IPSR_NOFN(IIC_1_0_PORT46, UART3_RX, SEL_IIC_1_0_01), @@ -377,51 +377,51 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_NOFN(IIC_1_0_PORT47, IIC1_SDA, SEL_IIC_1_0_00), PINMUX_IPSR_NOFN(IIC_1_0_PORT47, UART3_TX, SEL_IIC_1_0_01), /* AC19 */ - PINMUX_DATA(SD_CKI_MARK, FN_SD_CKI), + PINMUX_SINGLE(SD_CKI), /* AB18 */ - PINMUX_DATA(SDI0_CKO_MARK, FN_SDI0_CKO), + PINMUX_SINGLE(SDI0_CKO), /* AC18 */ - PINMUX_DATA(SDI0_CKI_MARK, FN_SDI0_CKI), + PINMUX_SINGLE(SDI0_CKI), /* Y12 */ - PINMUX_DATA(SDI0_CMD_MARK, FN_SDI0_CMD), + PINMUX_SINGLE(SDI0_CMD), /* AA13 */ - PINMUX_DATA(SDI0_DATA0_MARK, FN_SDI0_DATA0), + PINMUX_SINGLE(SDI0_DATA0), /* Y13 */ - PINMUX_DATA(SDI0_DATA1_MARK, FN_SDI0_DATA1), + PINMUX_SINGLE(SDI0_DATA1), /* AA14 */ - PINMUX_DATA(SDI0_DATA2_MARK, FN_SDI0_DATA2), + PINMUX_SINGLE(SDI0_DATA2), /* Y14 */ - PINMUX_DATA(SDI0_DATA3_MARK, FN_SDI0_DATA3), + PINMUX_SINGLE(SDI0_DATA3), /* AA15 */ - PINMUX_DATA(SDI0_DATA4_MARK, FN_SDI0_DATA4), + PINMUX_SINGLE(SDI0_DATA4), /* Y15 */ - PINMUX_DATA(SDI0_DATA5_MARK, FN_SDI0_DATA5), + PINMUX_SINGLE(SDI0_DATA5), /* AA16 */ - PINMUX_DATA(SDI0_DATA6_MARK, FN_SDI0_DATA6), + PINMUX_SINGLE(SDI0_DATA6), /* Y16 */ - PINMUX_DATA(SDI0_DATA7_MARK, FN_SDI0_DATA7), + PINMUX_SINGLE(SDI0_DATA7), /* AB22 */ - PINMUX_DATA(SDI1_CKO_MARK, FN_SDI1_CKO), + PINMUX_SINGLE(SDI1_CKO), /* AA23 */ - PINMUX_DATA(SDI1_CKI_MARK, FN_SDI1_CKI), + PINMUX_SINGLE(SDI1_CKI), /* AC21 */ - PINMUX_DATA(SDI1_CMD_MARK, FN_SDI1_CMD), + PINMUX_SINGLE(SDI1_CMD), /* GPSR2 */ /* AB21 */ - PINMUX_DATA(SDI1_DATA0_MARK, FN_SDI1_DATA0), + PINMUX_SINGLE(SDI1_DATA0), /* AB20 */ - PINMUX_DATA(SDI1_DATA1_MARK, FN_SDI1_DATA1), + PINMUX_SINGLE(SDI1_DATA1), /* AB19 */ - PINMUX_DATA(SDI1_DATA2_MARK, FN_SDI1_DATA2), + PINMUX_SINGLE(SDI1_DATA2), /* AA19 */ - PINMUX_DATA(SDI1_DATA3_MARK, FN_SDI1_DATA3), + PINMUX_SINGLE(SDI1_DATA3), /* J23 */ - PINMUX_DATA(AB_CLK_MARK, FN_AB_CLK), + PINMUX_SINGLE(AB_CLK), /* D21 */ - PINMUX_DATA(AB_CSB0_MARK, FN_AB_CSB0), + PINMUX_SINGLE(AB_CSB0), /* E21 */ - PINMUX_DATA(AB_CSB1_MARK, FN_AB_CSB1), + PINMUX_SINGLE(AB_CSB1), /* F20 */ PINMUX_IPSR_NOFN(AB_1_0_PORT71, AB_CSB2, SEL_AB_1_0_00), PINMUX_IPSR_NOFN(AB_1_0_PORT71, CF_CSB0, SEL_AB_1_0_10), @@ -514,7 +514,7 @@ static const u16 pinmux_data[] = { /* GPSR3 */ /* M21 */ - PINMUX_DATA(AB_A20_MARK, FN_AB_A20), + PINMUX_SINGLE(AB_A20), /* N21 */ PINMUX_IPSR_NOFN(AB_9_8_PORT97, AB_A21, SEL_AB_9_8_00), PINMUX_IPSR_NOFN(AB_9_8_PORT97, SDI2_CKO, SEL_AB_9_8_01), @@ -541,13 +541,13 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_NOFN(AB_13_12_PORT104, AB_A28, SEL_AB_13_12_00), PINMUX_IPSR_NOFN(AB_13_12_PORT104, AB_BEN1, SEL_AB_13_12_10), /* B8 */ - PINMUX_DATA(USI0_CS1_MARK, FN_USI0_CS1), + PINMUX_SINGLE(USI0_CS1), /* B9 */ - PINMUX_DATA(USI0_CS2_MARK, FN_USI0_CS2), + PINMUX_SINGLE(USI0_CS2), /* C10 */ - PINMUX_DATA(USI1_DI_MARK, FN_USI1_DI), + PINMUX_SINGLE(USI1_DI), /* D10 */ - PINMUX_DATA(USI1_DO_MARK, FN_USI1_DO), + PINMUX_SINGLE(USI1_DO), /* AB5 */ PINMUX_IPSR_NOFN(USI_1_0_PORT109, USI2_CLK, SEL_USI_1_0_00), PINMUX_IPSR_NOFN(USI_1_0_PORT109, DTV_BCLK_B, SEL_USI_1_0_01), @@ -587,49 +587,49 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_NOFN(USI_9_8_PORT121, PWM1, SEL_USI_9_8_00), PINMUX_IPSR_NOFN(USI_9_8_PORT121, USI4_DO, SEL_USI_9_8_01), /* V20 */ - PINMUX_DATA(NTSC_CLK_MARK, FN_NTSC_CLK), + PINMUX_SINGLE(NTSC_CLK), /* P20 */ - PINMUX_DATA(NTSC_DATA0_MARK, FN_NTSC_DATA0), + PINMUX_SINGLE(NTSC_DATA0), /* P18 */ - PINMUX_DATA(NTSC_DATA1_MARK, FN_NTSC_DATA1), + PINMUX_SINGLE(NTSC_DATA1), /* R20 */ - PINMUX_DATA(NTSC_DATA2_MARK, FN_NTSC_DATA2), + PINMUX_SINGLE(NTSC_DATA2), /* R18 */ - PINMUX_DATA(NTSC_DATA3_MARK, FN_NTSC_DATA3), + PINMUX_SINGLE(NTSC_DATA3), /* T20 */ - PINMUX_DATA(NTSC_DATA4_MARK, FN_NTSC_DATA4), + PINMUX_SINGLE(NTSC_DATA4), /* GPRS3 */ /* T18 */ - PINMUX_DATA(NTSC_DATA5_MARK, FN_NTSC_DATA5), + PINMUX_SINGLE(NTSC_DATA5), /* U20 */ - PINMUX_DATA(NTSC_DATA6_MARK, FN_NTSC_DATA6), + PINMUX_SINGLE(NTSC_DATA6), /* U18 */ - PINMUX_DATA(NTSC_DATA7_MARK, FN_NTSC_DATA7), + PINMUX_SINGLE(NTSC_DATA7), /* W23 */ - PINMUX_DATA(CAM_CLKO_MARK, FN_CAM_CLKO), + PINMUX_SINGLE(CAM_CLKO), /* Y23 */ - PINMUX_DATA(CAM_CLKI_MARK, FN_CAM_CLKI), + PINMUX_SINGLE(CAM_CLKI), /* W22 */ - PINMUX_DATA(CAM_VS_MARK, FN_CAM_VS), + PINMUX_SINGLE(CAM_VS), /* V21 */ - PINMUX_DATA(CAM_HS_MARK, FN_CAM_HS), + PINMUX_SINGLE(CAM_HS), /* T21 */ - PINMUX_DATA(CAM_YUV0_MARK, FN_CAM_YUV0), + PINMUX_SINGLE(CAM_YUV0), /* T22 */ - PINMUX_DATA(CAM_YUV1_MARK, FN_CAM_YUV1), + PINMUX_SINGLE(CAM_YUV1), /* T23 */ - PINMUX_DATA(CAM_YUV2_MARK, FN_CAM_YUV2), + PINMUX_SINGLE(CAM_YUV2), /* U21 */ - PINMUX_DATA(CAM_YUV3_MARK, FN_CAM_YUV3), + PINMUX_SINGLE(CAM_YUV3), /* U22 */ - PINMUX_DATA(CAM_YUV4_MARK, FN_CAM_YUV4), + PINMUX_SINGLE(CAM_YUV4), /* U23 */ - PINMUX_DATA(CAM_YUV5_MARK, FN_CAM_YUV5), + PINMUX_SINGLE(CAM_YUV5), /* V22 */ - PINMUX_DATA(CAM_YUV6_MARK, FN_CAM_YUV6), + PINMUX_SINGLE(CAM_YUV6), /* V23 */ - PINMUX_DATA(CAM_YUV7_MARK, FN_CAM_YUV7), + PINMUX_SINGLE(CAM_YUV7), /* K22 */ PINMUX_IPSR_NOFN(HSI_1_0_PORT143, USI5_CLK_B, SEL_HSI_1_0_01), /* K23 */ @@ -647,17 +647,17 @@ static const u16 pinmux_data[] = { /* M22 */ PINMUX_IPSR_NOFN(HSI_1_0_PORT150, USI5_DI_B, SEL_HSI_1_0_01), /* D13 */ - PINMUX_DATA(JT_TDO_MARK, FN_JT_TDO), + PINMUX_SINGLE(JT_TDO), /* F13 */ - PINMUX_DATA(JT_TDOEN_MARK, FN_JT_TDOEN), + PINMUX_SINGLE(JT_TDOEN), /* AA12 */ - PINMUX_DATA(USB_VBUS_MARK, FN_USB_VBUS), + PINMUX_SINGLE(USB_VBUS), /* A12 */ - PINMUX_DATA(LOWPWR_MARK, FN_LOWPWR), + PINMUX_SINGLE(LOWPWR), /* Y11 */ - PINMUX_DATA(UART1_RX_MARK, FN_UART1_RX), + PINMUX_SINGLE(UART1_RX), /* Y10 */ - PINMUX_DATA(UART1_TX_MARK, FN_UART1_TX), + PINMUX_SINGLE(UART1_TX), /* AA10 */ PINMUX_IPSR_NOFN(UART_1_0_PORT157, UART1_CTSB, SEL_UART_1_0_00), PINMUX_IPSR_NOFN(UART_1_0_PORT157, UART2_RX, SEL_UART_1_0_01), -- cgit v0.10.2 From 79e72c535cea93dd86f9b2ace61bbcbf9eeff243 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 25 Nov 2015 11:25:29 +0100 Subject: pinctrl: sh-pfc: r8a7778: Use PINMUX_SINGLE() instead of raw PINMUX_DATA() Signed-off-by: Geert Uytterhoeven diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7778.c b/drivers/pinctrl/sh-pfc/pfc-r8a7778.c index bbd35dc..ad09a67 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7778.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7778.c @@ -548,17 +548,17 @@ enum { static const u16 pinmux_data[] = { PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */ - PINMUX_DATA(PENC0_MARK, FN_PENC0), - PINMUX_DATA(PENC1_MARK, FN_PENC1), - PINMUX_DATA(A1_MARK, FN_A1), - PINMUX_DATA(A2_MARK, FN_A2), - PINMUX_DATA(A3_MARK, FN_A3), - PINMUX_DATA(WE0_MARK, FN_WE0), - PINMUX_DATA(AUDIO_CLKA_MARK, FN_AUDIO_CLKA), - PINMUX_DATA(AUDIO_CLKB_MARK, FN_AUDIO_CLKB), - PINMUX_DATA(SSI_SCK34_MARK, FN_SSI_SCK34), - PINMUX_DATA(AVS1_MARK, FN_AVS1), - PINMUX_DATA(AVS2_MARK, FN_AVS2), + PINMUX_SINGLE(PENC0), + PINMUX_SINGLE(PENC1), + PINMUX_SINGLE(A1), + PINMUX_SINGLE(A2), + PINMUX_SINGLE(A3), + PINMUX_SINGLE(WE0), + PINMUX_SINGLE(AUDIO_CLKA), + PINMUX_SINGLE(AUDIO_CLKB), + PINMUX_SINGLE(SSI_SCK34), + PINMUX_SINGLE(AVS1), + PINMUX_SINGLE(AVS2), /* IPSR0 */ PINMUX_IPSR_DATA(IP0_1_0, PRESETOUT), -- cgit v0.10.2 From ab2d12cbe9d0369f94bc55bc659b2d2d9f3c15db Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 25 Nov 2015 11:25:35 +0100 Subject: pinctrl: sh-pfc: r8a7779: Use PINMUX_SINGLE() instead of raw PINMUX_DATA() Signed-off-by: Geert Uytterhoeven diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c index 7293e37..afc5d80 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c @@ -602,14 +602,14 @@ enum { static const u16 pinmux_data[] = { PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */ - PINMUX_DATA(AVS1_MARK, FN_AVS1), - PINMUX_DATA(AVS1_MARK, FN_AVS1), - PINMUX_DATA(A17_MARK, FN_A17), - PINMUX_DATA(A18_MARK, FN_A18), - PINMUX_DATA(A19_MARK, FN_A19), - - PINMUX_DATA(USB_PENC0_MARK, FN_USB_PENC0), - PINMUX_DATA(USB_PENC1_MARK, FN_USB_PENC1), + PINMUX_SINGLE(AVS1), + PINMUX_SINGLE(AVS1), + PINMUX_SINGLE(A17), + PINMUX_SINGLE(A18), + PINMUX_SINGLE(A19), + + PINMUX_SINGLE(USB_PENC0), + PINMUX_SINGLE(USB_PENC1), PINMUX_IPSR_DATA(IP0_2_0, USB_PENC2), PINMUX_IPSR_MSEL(IP0_2_0, SCK0, SEL_SCIF0_0), -- cgit v0.10.2 From 8795841bd606fbf1a63f66c51c07de39c44c4f34 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 25 Nov 2015 13:45:02 +0100 Subject: pinctrl: sh-pfc: sh7734: Use PINMUX_SINGLE() instead of raw PINMUX_DATA() Signed-off-by: Geert Uytterhoeven diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7734.c b/drivers/pinctrl/sh-pfc/pfc-sh7734.c index 9d66865..20373a9 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh7734.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh7734.c @@ -577,15 +577,18 @@ enum { static const u16 pinmux_data[] = { PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */ - PINMUX_DATA(CLKOUT_MARK, FN_CLKOUT), - PINMUX_DATA(BS_MARK, FN_BS), PINMUX_DATA(CS0_MARK, FN_CS0), - PINMUX_DATA(EX_CS0_MARK, FN_EX_CS0), - PINMUX_DATA(RD_MARK, FN_RD), PINMUX_DATA(WE0_MARK, FN_WE0), - PINMUX_DATA(WE1_MARK, FN_WE1), - PINMUX_DATA(SCL0_MARK, FN_SCL0), PINMUX_DATA(PENC0_MARK, FN_PENC0), - PINMUX_DATA(USB_OVC0_MARK, FN_USB_OVC0), - PINMUX_DATA(IRQ2_B_MARK, FN_IRQ2_B), - PINMUX_DATA(IRQ3_B_MARK, FN_IRQ3_B), + PINMUX_SINGLE(CLKOUT), + PINMUX_SINGLE(BS), + PINMUX_SINGLE(CS0), + PINMUX_SINGLE(EX_CS0), + PINMUX_SINGLE(RD), + PINMUX_SINGLE(WE0), + PINMUX_SINGLE(WE1), + PINMUX_SINGLE(SCL0), + PINMUX_SINGLE(PENC0), + PINMUX_SINGLE(USB_OVC0), + PINMUX_SINGLE(IRQ2_B), + PINMUX_SINGLE(IRQ3_B), /* IPSR0 */ PINMUX_IPSR_DATA(IP0_1_0, A0), -- cgit v0.10.2 From 8d4df57378e51ac15da0276a0a3b20368729fe2a Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 2 Sep 2015 20:37:55 +0200 Subject: pinctrl: sh-pfc: r8a7795: Add pinmux data for single-function pins Pins that (1) can be configured as either GPIO or a single peripheral function, and (2) that don't need configuration in an IPSRx register, should still be listed in the pinmux_data[] array. Else selecting the peripheral function fails with e.g.: sh-pfc e6060000.pfc: cannot locate data/mark enum_id for mark 1281 (mark 1281 is MSIOF0_SCK_MARK). Signed-off-by: Geert Uytterhoeven diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c index 79984b3..022ba91 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c @@ -549,6 +549,25 @@ enum { static const u16 pinmux_data[] = { PINMUX_DATA_GP_ALL(), + PINMUX_SINGLE(AVS1), + PINMUX_SINGLE(AVS2), + PINMUX_SINGLE(HDMI0_CEC), + PINMUX_SINGLE(HDMI1_CEC), + PINMUX_SINGLE(MSIOF0_RXD), + PINMUX_SINGLE(MSIOF0_SCK), + PINMUX_SINGLE(MSIOF0_TXD), + PINMUX_SINGLE(SD2_CMD), + PINMUX_SINGLE(SD3_CLK), + PINMUX_SINGLE(SD3_CMD), + PINMUX_SINGLE(SD3_DAT0), + PINMUX_SINGLE(SD3_DAT1), + PINMUX_SINGLE(SD3_DAT2), + PINMUX_SINGLE(SD3_DAT3), + PINMUX_SINGLE(SD3_DS), + PINMUX_SINGLE(SSI_SCK5), + PINMUX_SINGLE(SSI_SDATA5), + PINMUX_SINGLE(SSI_WS5), + /* IPSR0 */ PINMUX_IPSR_DATA(IP0_3_0, AVB_MDC), PINMUX_IPSR_MSEL(IP0_3_0, MSIOF2_SS2_C, SEL_MSIOF2_2), -- cgit v0.10.2 From e7419b81ff83eafca19629b383540d5d2d0f975c Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 2 Sep 2015 16:51:54 +0200 Subject: pinctrl: sh-pfc: r8a7795: Add MSIOF pins, groups, and functions Extracted from a big patch by Takeshi Kihara. Signed-off-by: Takeshi Kihara [geert: Correct MSIOF3 TXD_A/RXD_A pins] Signed-off-by: Geert Uytterhoeven diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c index 022ba91..b9ef8ed 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c @@ -1836,6 +1836,662 @@ static const unsigned int i2c6_c_mux[] = { SDA6_C_MARK, SCL6_C_MARK, }; +/* - MSIOF0 ----------------------------------------------------------------- */ +static const unsigned int msiof0_clk_pins[] = { + /* SCK */ + RCAR_GP_PIN(5, 17), +}; +static const unsigned int msiof0_clk_mux[] = { + MSIOF0_SCK_MARK, +}; +static const unsigned int msiof0_sync_pins[] = { + /* SYNC */ + RCAR_GP_PIN(5, 18), +}; +static const unsigned int msiof0_sync_mux[] = { + MSIOF0_SYNC_MARK, +}; +static const unsigned int msiof0_ss1_pins[] = { + /* SS1 */ + RCAR_GP_PIN(5, 19), +}; +static const unsigned int msiof0_ss1_mux[] = { + MSIOF0_SS1_MARK, +}; +static const unsigned int msiof0_ss2_pins[] = { + /* SS2 */ + RCAR_GP_PIN(5, 21), +}; +static const unsigned int msiof0_ss2_mux[] = { + MSIOF0_SS2_MARK, +}; +static const unsigned int msiof0_txd_pins[] = { + /* TXD */ + RCAR_GP_PIN(5, 20), +}; +static const unsigned int msiof0_txd_mux[] = { + MSIOF0_TXD_MARK, +}; +static const unsigned int msiof0_rxd_pins[] = { + /* RXD */ + RCAR_GP_PIN(5, 22), +}; +static const unsigned int msiof0_rxd_mux[] = { + MSIOF0_RXD_MARK, +}; +/* - MSIOF1 ----------------------------------------------------------------- */ +static const unsigned int msiof1_clk_a_pins[] = { + /* SCK */ + RCAR_GP_PIN(6, 8), +}; +static const unsigned int msiof1_clk_a_mux[] = { + MSIOF1_SCK_A_MARK, +}; +static const unsigned int msiof1_sync_a_pins[] = { + /* SYNC */ + RCAR_GP_PIN(6, 9), +}; +static const unsigned int msiof1_sync_a_mux[] = { + MSIOF1_SYNC_A_MARK, +}; +static const unsigned int msiof1_ss1_a_pins[] = { + /* SS1 */ + RCAR_GP_PIN(6, 5), +}; +static const unsigned int msiof1_ss1_a_mux[] = { + MSIOF1_SS1_A_MARK, +}; +static const unsigned int msiof1_ss2_a_pins[] = { + /* SS2 */ + RCAR_GP_PIN(6, 6), +}; +static const unsigned int msiof1_ss2_a_mux[] = { + MSIOF1_SS2_A_MARK, +}; +static const unsigned int msiof1_txd_a_pins[] = { + /* TXD */ + RCAR_GP_PIN(6, 7), +}; +static const unsigned int msiof1_txd_a_mux[] = { + MSIOF1_TXD_A_MARK, +}; +static const unsigned int msiof1_rxd_a_pins[] = { + /* RXD */ + RCAR_GP_PIN(6, 10), +}; +static const unsigned int msiof1_rxd_a_mux[] = { + MSIOF1_RXD_A_MARK, +}; +static const unsigned int msiof1_clk_b_pins[] = { + /* SCK */ + RCAR_GP_PIN(5, 9), +}; +static const unsigned int msiof1_clk_b_mux[] = { + MSIOF1_SCK_B_MARK, +}; +static const unsigned int msiof1_sync_b_pins[] = { + /* SYNC */ + RCAR_GP_PIN(5, 3), +}; +static const unsigned int msiof1_sync_b_mux[] = { + MSIOF1_SYNC_B_MARK, +}; +static const unsigned int msiof1_ss1_b_pins[] = { + /* SS1 */ + RCAR_GP_PIN(5, 4), +}; +static const unsigned int msiof1_ss1_b_mux[] = { + MSIOF1_SS1_B_MARK, +}; +static const unsigned int msiof1_ss2_b_pins[] = { + /* SS2 */ + RCAR_GP_PIN(5, 0), +}; +static const unsigned int msiof1_ss2_b_mux[] = { + MSIOF1_SS2_B_MARK, +}; +static const unsigned int msiof1_txd_b_pins[] = { + /* TXD */ + RCAR_GP_PIN(5, 8), +}; +static const unsigned int msiof1_txd_b_mux[] = { + MSIOF1_TXD_B_MARK, +}; +static const unsigned int msiof1_rxd_b_pins[] = { + /* RXD */ + RCAR_GP_PIN(5, 7), +}; +static const unsigned int msiof1_rxd_b_mux[] = { + MSIOF1_RXD_B_MARK, +}; +static const unsigned int msiof1_clk_c_pins[] = { + /* SCK */ + RCAR_GP_PIN(6, 17), +}; +static const unsigned int msiof1_clk_c_mux[] = { + MSIOF1_SCK_C_MARK, +}; +static const unsigned int msiof1_sync_c_pins[] = { + /* SYNC */ + RCAR_GP_PIN(6, 18), +}; +static const unsigned int msiof1_sync_c_mux[] = { + MSIOF1_SYNC_C_MARK, +}; +static const unsigned int msiof1_ss1_c_pins[] = { + /* SS1 */ + RCAR_GP_PIN(6, 21), +}; +static const unsigned int msiof1_ss1_c_mux[] = { + MSIOF1_SS1_C_MARK, +}; +static const unsigned int msiof1_ss2_c_pins[] = { + /* SS2 */ + RCAR_GP_PIN(6, 27), +}; +static const unsigned int msiof1_ss2_c_mux[] = { + MSIOF1_SS2_C_MARK, +}; +static const unsigned int msiof1_txd_c_pins[] = { + /* TXD */ + RCAR_GP_PIN(6, 20), +}; +static const unsigned int msiof1_txd_c_mux[] = { + MSIOF1_TXD_C_MARK, +}; +static const unsigned int msiof1_rxd_c_pins[] = { + /* RXD */ + RCAR_GP_PIN(6, 19), +}; +static const unsigned int msiof1_rxd_c_mux[] = { + MSIOF1_RXD_C_MARK, +}; +static const unsigned int msiof1_clk_d_pins[] = { + /* SCK */ + RCAR_GP_PIN(5, 12), +}; +static const unsigned int msiof1_clk_d_mux[] = { + MSIOF1_SCK_D_MARK, +}; +static const unsigned int msiof1_sync_d_pins[] = { + /* SYNC */ + RCAR_GP_PIN(5, 15), +}; +static const unsigned int msiof1_sync_d_mux[] = { + MSIOF1_SYNC_D_MARK, +}; +static const unsigned int msiof1_ss1_d_pins[] = { + /* SS1 */ + RCAR_GP_PIN(5, 16), +}; +static const unsigned int msiof1_ss1_d_mux[] = { + MSIOF1_SS1_D_MARK, +}; +static const unsigned int msiof1_ss2_d_pins[] = { + /* SS2 */ + RCAR_GP_PIN(5, 21), +}; +static const unsigned int msiof1_ss2_d_mux[] = { + MSIOF1_SS2_D_MARK, +}; +static const unsigned int msiof1_txd_d_pins[] = { + /* TXD */ + RCAR_GP_PIN(5, 14), +}; +static const unsigned int msiof1_txd_d_mux[] = { + MSIOF1_TXD_D_MARK, +}; +static const unsigned int msiof1_rxd_d_pins[] = { + /* RXD */ + RCAR_GP_PIN(5, 13), +}; +static const unsigned int msiof1_rxd_d_mux[] = { + MSIOF1_RXD_D_MARK, +}; +static const unsigned int msiof1_clk_e_pins[] = { + /* SCK */ + RCAR_GP_PIN(3, 0), +}; +static const unsigned int msiof1_clk_e_mux[] = { + MSIOF1_SCK_E_MARK, +}; +static const unsigned int msiof1_sync_e_pins[] = { + /* SYNC */ + RCAR_GP_PIN(3, 1), +}; +static const unsigned int msiof1_sync_e_mux[] = { + MSIOF1_SYNC_E_MARK, +}; +static const unsigned int msiof1_ss1_e_pins[] = { + /* SS1 */ + RCAR_GP_PIN(3, 4), +}; +static const unsigned int msiof1_ss1_e_mux[] = { + MSIOF1_SS1_E_MARK, +}; +static const unsigned int msiof1_ss2_e_pins[] = { + /* SS2 */ + RCAR_GP_PIN(3, 5), +}; +static const unsigned int msiof1_ss2_e_mux[] = { + MSIOF1_SS2_E_MARK, +}; +static const unsigned int msiof1_txd_e_pins[] = { + /* TXD */ + RCAR_GP_PIN(3, 3), +}; +static const unsigned int msiof1_txd_e_mux[] = { + MSIOF1_TXD_E_MARK, +}; +static const unsigned int msiof1_rxd_e_pins[] = { + /* RXD */ + RCAR_GP_PIN(3, 2), +}; +static const unsigned int msiof1_rxd_e_mux[] = { + MSIOF1_RXD_E_MARK, +}; +static const unsigned int msiof1_clk_f_pins[] = { + /* SCK */ + RCAR_GP_PIN(5, 23), +}; +static const unsigned int msiof1_clk_f_mux[] = { + MSIOF1_SCK_F_MARK, +}; +static const unsigned int msiof1_sync_f_pins[] = { + /* SYNC */ + RCAR_GP_PIN(5, 24), +}; +static const unsigned int msiof1_sync_f_mux[] = { + MSIOF1_SYNC_F_MARK, +}; +static const unsigned int msiof1_ss1_f_pins[] = { + /* SS1 */ + RCAR_GP_PIN(6, 1), +}; +static const unsigned int msiof1_ss1_f_mux[] = { + MSIOF1_SS1_F_MARK, +}; +static const unsigned int msiof1_ss2_f_pins[] = { + /* SS2 */ + RCAR_GP_PIN(6, 2), +}; +static const unsigned int msiof1_ss2_f_mux[] = { + MSIOF1_SS2_F_MARK, +}; +static const unsigned int msiof1_txd_f_pins[] = { + /* TXD */ + RCAR_GP_PIN(6, 0), +}; +static const unsigned int msiof1_txd_f_mux[] = { + MSIOF1_TXD_F_MARK, +}; +static const unsigned int msiof1_rxd_f_pins[] = { + /* RXD */ + RCAR_GP_PIN(5, 25), +}; +static const unsigned int msiof1_rxd_f_mux[] = { + MSIOF1_RXD_F_MARK, +}; +static const unsigned int msiof1_clk_g_pins[] = { + /* SCK */ + RCAR_GP_PIN(3, 6), +}; +static const unsigned int msiof1_clk_g_mux[] = { + MSIOF1_SCK_G_MARK, +}; +static const unsigned int msiof1_sync_g_pins[] = { + /* SYNC */ + RCAR_GP_PIN(3, 7), +}; +static const unsigned int msiof1_sync_g_mux[] = { + MSIOF1_SYNC_G_MARK, +}; +static const unsigned int msiof1_ss1_g_pins[] = { + /* SS1 */ + RCAR_GP_PIN(3, 10), +}; +static const unsigned int msiof1_ss1_g_mux[] = { + MSIOF1_SS1_G_MARK, +}; +static const unsigned int msiof1_ss2_g_pins[] = { + /* SS2 */ + RCAR_GP_PIN(3, 11), +}; +static const unsigned int msiof1_ss2_g_mux[] = { + MSIOF1_SS2_G_MARK, +}; +static const unsigned int msiof1_txd_g_pins[] = { + /* TXD */ + RCAR_GP_PIN(3, 9), +}; +static const unsigned int msiof1_txd_g_mux[] = { + MSIOF1_TXD_G_MARK, +}; +static const unsigned int msiof1_rxd_g_pins[] = { + /* RXD */ + RCAR_GP_PIN(3, 8), +}; +static const unsigned int msiof1_rxd_g_mux[] = { + MSIOF1_RXD_G_MARK, +}; +/* - MSIOF2 ----------------------------------------------------------------- */ +static const unsigned int msiof2_clk_a_pins[] = { + /* SCK */ + RCAR_GP_PIN(1, 9), +}; +static const unsigned int msiof2_clk_a_mux[] = { + MSIOF2_SCK_A_MARK, +}; +static const unsigned int msiof2_sync_a_pins[] = { + /* SYNC */ + RCAR_GP_PIN(1, 8), +}; +static const unsigned int msiof2_sync_a_mux[] = { + MSIOF2_SYNC_A_MARK, +}; +static const unsigned int msiof2_ss1_a_pins[] = { + /* SS1 */ + RCAR_GP_PIN(1, 6), +}; +static const unsigned int msiof2_ss1_a_mux[] = { + MSIOF2_SS1_A_MARK, +}; +static const unsigned int msiof2_ss2_a_pins[] = { + /* SS2 */ + RCAR_GP_PIN(1, 7), +}; +static const unsigned int msiof2_ss2_a_mux[] = { + MSIOF2_SS2_A_MARK, +}; +static const unsigned int msiof2_txd_a_pins[] = { + /* TXD */ + RCAR_GP_PIN(1, 11), +}; +static const unsigned int msiof2_txd_a_mux[] = { + MSIOF2_TXD_A_MARK, +}; +static const unsigned int msiof2_rxd_a_pins[] = { + /* RXD */ + RCAR_GP_PIN(1, 10), +}; +static const unsigned int msiof2_rxd_a_mux[] = { + MSIOF2_RXD_A_MARK, +}; +static const unsigned int msiof2_clk_b_pins[] = { + /* SCK */ + RCAR_GP_PIN(0, 4), +}; +static const unsigned int msiof2_clk_b_mux[] = { + MSIOF2_SCK_B_MARK, +}; +static const unsigned int msiof2_sync_b_pins[] = { + /* SYNC */ + RCAR_GP_PIN(0, 5), +}; +static const unsigned int msiof2_sync_b_mux[] = { + MSIOF2_SYNC_B_MARK, +}; +static const unsigned int msiof2_ss1_b_pins[] = { + /* SS1 */ + RCAR_GP_PIN(0, 0), +}; +static const unsigned int msiof2_ss1_b_mux[] = { + MSIOF2_SS1_B_MARK, +}; +static const unsigned int msiof2_ss2_b_pins[] = { + /* SS2 */ + RCAR_GP_PIN(0, 1), +}; +static const unsigned int msiof2_ss2_b_mux[] = { + MSIOF2_SS2_B_MARK, +}; +static const unsigned int msiof2_txd_b_pins[] = { + /* TXD */ + RCAR_GP_PIN(0, 7), +}; +static const unsigned int msiof2_txd_b_mux[] = { + MSIOF2_TXD_B_MARK, +}; +static const unsigned int msiof2_rxd_b_pins[] = { + /* RXD */ + RCAR_GP_PIN(0, 6), +}; +static const unsigned int msiof2_rxd_b_mux[] = { + MSIOF2_RXD_B_MARK, +}; +static const unsigned int msiof2_clk_c_pins[] = { + /* SCK */ + RCAR_GP_PIN(2, 12), +}; +static const unsigned int msiof2_clk_c_mux[] = { + MSIOF2_SCK_C_MARK, +}; +static const unsigned int msiof2_sync_c_pins[] = { + /* SYNC */ + RCAR_GP_PIN(2, 11), +}; +static const unsigned int msiof2_sync_c_mux[] = { + MSIOF2_SYNC_C_MARK, +}; +static const unsigned int msiof2_ss1_c_pins[] = { + /* SS1 */ + RCAR_GP_PIN(2, 10), +}; +static const unsigned int msiof2_ss1_c_mux[] = { + MSIOF2_SS1_C_MARK, +}; +static const unsigned int msiof2_ss2_c_pins[] = { + /* SS2 */ + RCAR_GP_PIN(2, 9), +}; +static const unsigned int msiof2_ss2_c_mux[] = { + MSIOF2_SS2_C_MARK, +}; +static const unsigned int msiof2_txd_c_pins[] = { + /* TXD */ + RCAR_GP_PIN(2, 14), +}; +static const unsigned int msiof2_txd_c_mux[] = { + MSIOF2_TXD_C_MARK, +}; +static const unsigned int msiof2_rxd_c_pins[] = { + /* RXD */ + RCAR_GP_PIN(2, 13), +}; +static const unsigned int msiof2_rxd_c_mux[] = { + MSIOF2_RXD_C_MARK, +}; +static const unsigned int msiof2_clk_d_pins[] = { + /* SCK */ + RCAR_GP_PIN(0, 8), +}; +static const unsigned int msiof2_clk_d_mux[] = { + MSIOF2_SCK_D_MARK, +}; +static const unsigned int msiof2_sync_d_pins[] = { + /* SYNC */ + RCAR_GP_PIN(0, 9), +}; +static const unsigned int msiof2_sync_d_mux[] = { + MSIOF2_SYNC_D_MARK, +}; +static const unsigned int msiof2_ss1_d_pins[] = { + /* SS1 */ + RCAR_GP_PIN(0, 12), +}; +static const unsigned int msiof2_ss1_d_mux[] = { + MSIOF2_SS1_D_MARK, +}; +static const unsigned int msiof2_ss2_d_pins[] = { + /* SS2 */ + RCAR_GP_PIN(0, 13), +}; +static const unsigned int msiof2_ss2_d_mux[] = { + MSIOF2_SS2_D_MARK, +}; +static const unsigned int msiof2_txd_d_pins[] = { + /* TXD */ + RCAR_GP_PIN(0, 11), +}; +static const unsigned int msiof2_txd_d_mux[] = { + MSIOF2_TXD_D_MARK, +}; +static const unsigned int msiof2_rxd_d_pins[] = { + /* RXD */ + RCAR_GP_PIN(0, 10), +}; +static const unsigned int msiof2_rxd_d_mux[] = { + MSIOF2_RXD_D_MARK, +}; +/* - MSIOF3 ----------------------------------------------------------------- */ +static const unsigned int msiof3_clk_a_pins[] = { + /* SCK */ + RCAR_GP_PIN(0, 0), +}; +static const unsigned int msiof3_clk_a_mux[] = { + MSIOF3_SCK_A_MARK, +}; +static const unsigned int msiof3_sync_a_pins[] = { + /* SYNC */ + RCAR_GP_PIN(0, 1), +}; +static const unsigned int msiof3_sync_a_mux[] = { + MSIOF3_SYNC_A_MARK, +}; +static const unsigned int msiof3_ss1_a_pins[] = { + /* SS1 */ + RCAR_GP_PIN(0, 14), +}; +static const unsigned int msiof3_ss1_a_mux[] = { + MSIOF3_SS1_A_MARK, +}; +static const unsigned int msiof3_ss2_a_pins[] = { + /* SS2 */ + RCAR_GP_PIN(0, 15), +}; +static const unsigned int msiof3_ss2_a_mux[] = { + MSIOF3_SS2_A_MARK, +}; +static const unsigned int msiof3_txd_a_pins[] = { + /* TXD */ + RCAR_GP_PIN(0, 3), +}; +static const unsigned int msiof3_txd_a_mux[] = { + MSIOF3_TXD_A_MARK, +}; +static const unsigned int msiof3_rxd_a_pins[] = { + /* RXD */ + RCAR_GP_PIN(0, 2), +}; +static const unsigned int msiof3_rxd_a_mux[] = { + MSIOF3_RXD_A_MARK, +}; +static const unsigned int msiof3_clk_b_pins[] = { + /* SCK */ + RCAR_GP_PIN(1, 2), +}; +static const unsigned int msiof3_clk_b_mux[] = { + MSIOF3_SCK_B_MARK, +}; +static const unsigned int msiof3_sync_b_pins[] = { + /* SYNC */ + RCAR_GP_PIN(1, 0), +}; +static const unsigned int msiof3_sync_b_mux[] = { + MSIOF3_SYNC_B_MARK, +}; +static const unsigned int msiof3_ss1_b_pins[] = { + /* SS1 */ + RCAR_GP_PIN(1, 4), +}; +static const unsigned int msiof3_ss1_b_mux[] = { + MSIOF3_SS1_B_MARK, +}; +static const unsigned int msiof3_ss2_b_pins[] = { + /* SS2 */ + RCAR_GP_PIN(1, 5), +}; +static const unsigned int msiof3_ss2_b_mux[] = { + MSIOF3_SS2_B_MARK, +}; +static const unsigned int msiof3_txd_b_pins[] = { + /* TXD */ + RCAR_GP_PIN(1, 1), +}; +static const unsigned int msiof3_txd_b_mux[] = { + MSIOF3_TXD_B_MARK, +}; +static const unsigned int msiof3_rxd_b_pins[] = { + /* RXD */ + RCAR_GP_PIN(1, 3), +}; +static const unsigned int msiof3_rxd_b_mux[] = { + MSIOF3_RXD_B_MARK, +}; +static const unsigned int msiof3_clk_c_pins[] = { + /* SCK */ + RCAR_GP_PIN(1, 12), +}; +static const unsigned int msiof3_clk_c_mux[] = { + MSIOF3_SCK_C_MARK, +}; +static const unsigned int msiof3_sync_c_pins[] = { + /* SYNC */ + RCAR_GP_PIN(1, 13), +}; +static const unsigned int msiof3_sync_c_mux[] = { + MSIOF3_SYNC_C_MARK, +}; +static const unsigned int msiof3_txd_c_pins[] = { + /* TXD */ + RCAR_GP_PIN(1, 15), +}; +static const unsigned int msiof3_txd_c_mux[] = { + MSIOF3_TXD_C_MARK, +}; +static const unsigned int msiof3_rxd_c_pins[] = { + /* RXD */ + RCAR_GP_PIN(1, 14), +}; +static const unsigned int msiof3_rxd_c_mux[] = { + MSIOF3_RXD_C_MARK, +}; +static const unsigned int msiof3_clk_d_pins[] = { + /* SCK */ + RCAR_GP_PIN(1, 22), +}; +static const unsigned int msiof3_clk_d_mux[] = { + MSIOF3_SCK_D_MARK, +}; +static const unsigned int msiof3_sync_d_pins[] = { + /* SYNC */ + RCAR_GP_PIN(1, 23), +}; +static const unsigned int msiof3_sync_d_mux[] = { + MSIOF3_SYNC_D_MARK, +}; +static const unsigned int msiof3_ss1_d_pins[] = { + /* SS1 */ + RCAR_GP_PIN(1, 26), +}; +static const unsigned int msiof3_ss1_d_mux[] = { + MSIOF3_SS1_D_MARK, +}; +static const unsigned int msiof3_txd_d_pins[] = { + /* TXD */ + RCAR_GP_PIN(1, 25), +}; +static const unsigned int msiof3_txd_d_mux[] = { + MSIOF3_TXD_D_MARK, +}; +static const unsigned int msiof3_rxd_d_pins[] = { + /* RXD */ + RCAR_GP_PIN(1, 24), +}; +static const unsigned int msiof3_rxd_d_mux[] = { + MSIOF3_RXD_D_MARK, +}; + /* - SCIF0 ------------------------------------------------------------------ */ static const unsigned int scif0_data_pins[] = { /* RX, TX */ @@ -2255,6 +2911,99 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(i2c6_a), SH_PFC_PIN_GROUP(i2c6_b), SH_PFC_PIN_GROUP(i2c6_c), + SH_PFC_PIN_GROUP(msiof0_clk), + SH_PFC_PIN_GROUP(msiof0_sync), + SH_PFC_PIN_GROUP(msiof0_ss1), + SH_PFC_PIN_GROUP(msiof0_ss2), + SH_PFC_PIN_GROUP(msiof0_txd), + SH_PFC_PIN_GROUP(msiof0_rxd), + SH_PFC_PIN_GROUP(msiof1_clk_a), + SH_PFC_PIN_GROUP(msiof1_sync_a), + SH_PFC_PIN_GROUP(msiof1_ss1_a), + SH_PFC_PIN_GROUP(msiof1_ss2_a), + SH_PFC_PIN_GROUP(msiof1_txd_a), + SH_PFC_PIN_GROUP(msiof1_rxd_a), + SH_PFC_PIN_GROUP(msiof1_clk_b), + SH_PFC_PIN_GROUP(msiof1_sync_b), + SH_PFC_PIN_GROUP(msiof1_ss1_b), + SH_PFC_PIN_GROUP(msiof1_ss2_b), + SH_PFC_PIN_GROUP(msiof1_txd_b), + SH_PFC_PIN_GROUP(msiof1_rxd_b), + SH_PFC_PIN_GROUP(msiof1_clk_c), + SH_PFC_PIN_GROUP(msiof1_sync_c), + SH_PFC_PIN_GROUP(msiof1_ss1_c), + SH_PFC_PIN_GROUP(msiof1_ss2_c), + SH_PFC_PIN_GROUP(msiof1_txd_c), + SH_PFC_PIN_GROUP(msiof1_rxd_c), + SH_PFC_PIN_GROUP(msiof1_clk_d), + SH_PFC_PIN_GROUP(msiof1_sync_d), + SH_PFC_PIN_GROUP(msiof1_ss1_d), + SH_PFC_PIN_GROUP(msiof1_ss2_d), + SH_PFC_PIN_GROUP(msiof1_txd_d), + SH_PFC_PIN_GROUP(msiof1_rxd_d), + SH_PFC_PIN_GROUP(msiof1_clk_e), + SH_PFC_PIN_GROUP(msiof1_sync_e), + SH_PFC_PIN_GROUP(msiof1_ss1_e), + SH_PFC_PIN_GROUP(msiof1_ss2_e), + SH_PFC_PIN_GROUP(msiof1_txd_e), + SH_PFC_PIN_GROUP(msiof1_rxd_e), + SH_PFC_PIN_GROUP(msiof1_clk_f), + SH_PFC_PIN_GROUP(msiof1_sync_f), + SH_PFC_PIN_GROUP(msiof1_ss1_f), + SH_PFC_PIN_GROUP(msiof1_ss2_f), + SH_PFC_PIN_GROUP(msiof1_txd_f), + SH_PFC_PIN_GROUP(msiof1_rxd_f), + SH_PFC_PIN_GROUP(msiof1_clk_g), + SH_PFC_PIN_GROUP(msiof1_sync_g), + SH_PFC_PIN_GROUP(msiof1_ss1_g), + SH_PFC_PIN_GROUP(msiof1_ss2_g), + SH_PFC_PIN_GROUP(msiof1_txd_g), + SH_PFC_PIN_GROUP(msiof1_rxd_g), + SH_PFC_PIN_GROUP(msiof2_clk_a), + SH_PFC_PIN_GROUP(msiof2_sync_a), + SH_PFC_PIN_GROUP(msiof2_ss1_a), + SH_PFC_PIN_GROUP(msiof2_ss2_a), + SH_PFC_PIN_GROUP(msiof2_txd_a), + SH_PFC_PIN_GROUP(msiof2_rxd_a), + SH_PFC_PIN_GROUP(msiof2_clk_b), + SH_PFC_PIN_GROUP(msiof2_sync_b), + SH_PFC_PIN_GROUP(msiof2_ss1_b), + SH_PFC_PIN_GROUP(msiof2_ss2_b), + SH_PFC_PIN_GROUP(msiof2_txd_b), + SH_PFC_PIN_GROUP(msiof2_rxd_b), + SH_PFC_PIN_GROUP(msiof2_clk_c), + SH_PFC_PIN_GROUP(msiof2_sync_c), + SH_PFC_PIN_GROUP(msiof2_ss1_c), + SH_PFC_PIN_GROUP(msiof2_ss2_c), + SH_PFC_PIN_GROUP(msiof2_txd_c), + SH_PFC_PIN_GROUP(msiof2_rxd_c), + SH_PFC_PIN_GROUP(msiof2_clk_d), + SH_PFC_PIN_GROUP(msiof2_sync_d), + SH_PFC_PIN_GROUP(msiof2_ss1_d), + SH_PFC_PIN_GROUP(msiof2_ss2_d), + SH_PFC_PIN_GROUP(msiof2_txd_d), + SH_PFC_PIN_GROUP(msiof2_rxd_d), + SH_PFC_PIN_GROUP(msiof3_clk_a), + SH_PFC_PIN_GROUP(msiof3_sync_a), + SH_PFC_PIN_GROUP(msiof3_ss1_a), + SH_PFC_PIN_GROUP(msiof3_ss2_a), + SH_PFC_PIN_GROUP(msiof3_txd_a), + SH_PFC_PIN_GROUP(msiof3_rxd_a), + SH_PFC_PIN_GROUP(msiof3_clk_b), + SH_PFC_PIN_GROUP(msiof3_sync_b), + SH_PFC_PIN_GROUP(msiof3_ss1_b), + SH_PFC_PIN_GROUP(msiof3_ss2_b), + SH_PFC_PIN_GROUP(msiof3_txd_b), + SH_PFC_PIN_GROUP(msiof3_rxd_b), + SH_PFC_PIN_GROUP(msiof3_clk_c), + SH_PFC_PIN_GROUP(msiof3_sync_c), + SH_PFC_PIN_GROUP(msiof3_txd_c), + SH_PFC_PIN_GROUP(msiof3_rxd_c), + SH_PFC_PIN_GROUP(msiof3_clk_d), + SH_PFC_PIN_GROUP(msiof3_sync_d), + SH_PFC_PIN_GROUP(msiof3_ss1_d), + SH_PFC_PIN_GROUP(msiof3_txd_d), + SH_PFC_PIN_GROUP(msiof3_rxd_d), SH_PFC_PIN_GROUP(scif0_data), SH_PFC_PIN_GROUP(scif0_clk), SH_PFC_PIN_GROUP(scif0_ctrl), @@ -2395,6 +3144,111 @@ static const char * const i2c6_groups[] = { "i2c6_c", }; +static const char * const msiof0_groups[] = { + "msiof0_clk", + "msiof0_sync", + "msiof0_ss1", + "msiof0_ss2", + "msiof0_txd", + "msiof0_rxd", +}; + +static const char * const msiof1_groups[] = { + "msiof1_clk_a", + "msiof1_sync_a", + "msiof1_ss1_a", + "msiof1_ss2_a", + "msiof1_txd_a", + "msiof1_rxd_a", + "msiof1_clk_b", + "msiof1_sync_b", + "msiof1_ss1_b", + "msiof1_ss2_b", + "msiof1_txd_b", + "msiof1_rxd_b", + "msiof1_clk_c", + "msiof1_sync_c", + "msiof1_ss1_c", + "msiof1_ss2_c", + "msiof1_txd_c", + "msiof1_rxd_c", + "msiof1_clk_d", + "msiof1_sync_d", + "msiof1_ss1_d", + "msiof1_ss2_d", + "msiof1_txd_d", + "msiof1_rxd_d", + "msiof1_clk_e", + "msiof1_sync_e", + "msiof1_ss1_e", + "msiof1_ss2_e", + "msiof1_txd_e", + "msiof1_rxd_e", + "msiof1_clk_f", + "msiof1_sync_f", + "msiof1_ss1_f", + "msiof1_ss2_f", + "msiof1_txd_f", + "msiof1_rxd_f", + "msiof1_clk_g", + "msiof1_sync_g", + "msiof1_ss1_g", + "msiof1_ss2_g", + "msiof1_txd_g", + "msiof1_rxd_g", +}; + +static const char * const msiof2_groups[] = { + "msiof2_clk_a", + "msiof2_sync_a", + "msiof2_ss1_a", + "msiof2_ss2_a", + "msiof2_txd_a", + "msiof2_rxd_a", + "msiof2_clk_b", + "msiof2_sync_b", + "msiof2_ss1_b", + "msiof2_ss2_b", + "msiof2_txd_b", + "msiof2_rxd_b", + "msiof2_clk_c", + "msiof2_sync_c", + "msiof2_ss1_c", + "msiof2_ss2_c", + "msiof2_txd_c", + "msiof2_rxd_c", + "msiof2_clk_d", + "msiof2_sync_d", + "msiof2_ss1_d", + "msiof2_ss2_d", + "msiof2_txd_d", + "msiof2_rxd_d", +}; + +static const char * const msiof3_groups[] = { + "msiof3_clk_a", + "msiof3_sync_a", + "msiof3_ss1_a", + "msiof3_ss2_a", + "msiof3_txd_a", + "msiof3_rxd_a", + "msiof3_clk_b", + "msiof3_sync_b", + "msiof3_ss1_b", + "msiof3_ss2_b", + "msiof3_txd_b", + "msiof3_rxd_b", + "msiof3_clk_c", + "msiof3_sync_c", + "msiof3_txd_c", + "msiof3_rxd_c", + "msiof3_clk_d", + "msiof3_sync_d", + "msiof3_ss1_d", + "msiof3_txd_d", + "msiof3_rxd_d", +}; + static const char * const scif0_groups[] = { "scif0_data", "scif0_clk", @@ -2477,6 +3331,10 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(i2c1), SH_PFC_FUNCTION(i2c2), SH_PFC_FUNCTION(i2c6), + SH_PFC_FUNCTION(msiof0), + SH_PFC_FUNCTION(msiof1), + SH_PFC_FUNCTION(msiof2), + SH_PFC_FUNCTION(msiof3), SH_PFC_FUNCTION(scif0), SH_PFC_FUNCTION(scif1), SH_PFC_FUNCTION(scif2), -- cgit v0.10.2 From 188289ad90bfde1bdbed962cbadaa016a2acfbf1 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 30 Nov 2015 14:54:50 +0100 Subject: pinctrl: sh-pfc: emev2: Correct comment for CFI data pins The 8 data pins of the Compact Flash Interface are numbered 0..7, not 0..8. Signed-off-by: Geert Uytterhoeven diff --git a/drivers/pinctrl/sh-pfc/pfc-emev2.c b/drivers/pinctrl/sh-pfc/pfc-emev2.c index a3a4b67..1cbbe04 100644 --- a/drivers/pinctrl/sh-pfc/pfc-emev2.c +++ b/drivers/pinctrl/sh-pfc/pfc-emev2.c @@ -749,7 +749,7 @@ static const unsigned int cf_ctrl_mux[] = { }; static const unsigned int cf_data8_pins[] = { - /* CF_D[0:8] */ + /* CF_D[0:7] */ 77, 78, 79, 80, 81, 82, 83, 84, }; -- cgit v0.10.2 From 944e798890e10c27c520d422c4d0562ddf47890c Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 30 Nov 2015 14:54:13 +0100 Subject: pinctrl: sh-pfc: r8a7740: Correct comment for LCD1 data pins The 12 data pins of LCD1 are numbered 0..11, not 0..12. Signed-off-by: Geert Uytterhoeven diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c index 279e9dd..7f7c8a6e 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c @@ -2214,7 +2214,7 @@ static const unsigned int lcd1_data9_mux[] = { LCD1_D8_MARK, }; static const unsigned int lcd1_data12_pins[] = { - /* D[0:12] */ + /* D[0:11] */ 4, 3, 2, 1, 0, 91, 92, 23, 93, 94, 21, 201, }; -- cgit v0.10.2 From b363d81972fc57427ec799754e16bf31bd1cb95b Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 26 Nov 2015 14:17:11 +0100 Subject: pinctrl: sh-pfc: sh73a0: Correct comment for LCD2 data pins The 12 data pins of LCD2 are numbered 0..11, not 0..12. Signed-off-by: Geert Uytterhoeven diff --git a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c index 6a69c8c..54c8049 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c @@ -2059,7 +2059,7 @@ static const unsigned int lcd2_data9_mux[] = { LCD2D8_MARK, }; static const unsigned int lcd2_data12_pins[] = { - /* D[0:12] */ + /* D[0:11] */ 128, 129, 142, 143, 144, 145, 138, 139, 140, 141, 130, 131, }; -- cgit v0.10.2 From ae9335dc0c1d777c06f8c9eb59d4b718523fbc55 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 26 Nov 2015 14:18:42 +0100 Subject: pinctrl: sh-pfc: sh73a0: Add MSIOF support Add pins, groups, and a function for the 4 MSIOF devices. Note that the pin function name of MSIOF3 is named BBIF1. Signed-off-by: Geert Uytterhoeven diff --git a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c index 54c8049..d25e6f6 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c @@ -2198,6 +2198,420 @@ static const unsigned int mmc0_ctrl_1_pins[] = { static const unsigned int mmc0_ctrl_1_mux[] = { MMCCMD1_MARK, MMCCLK1_MARK, }; +/* - MSIOF0 ----------------------------------------------------------------- */ +static const unsigned int msiof0_rsck_pins[] = { + /* RSCK */ + 66, +}; +static const unsigned int msiof0_rsck_mux[] = { + MSIOF0_RSCK_MARK, +}; +static const unsigned int msiof0_tsck_pins[] = { + /* TSCK */ + 64, +}; +static const unsigned int msiof0_tsck_mux[] = { + MSIOF0_TSCK_MARK, +}; +static const unsigned int msiof0_rsync_pins[] = { + /* RSYNC */ + 67, +}; +static const unsigned int msiof0_rsync_mux[] = { + MSIOF0_RSYNC_MARK, +}; +static const unsigned int msiof0_tsync_pins[] = { + /* TSYNC */ + 63, +}; +static const unsigned int msiof0_tsync_mux[] = { + MSIOF0_TSYNC_MARK, +}; +static const unsigned int msiof0_ss1_pins[] = { + /* SS1 */ + 62, +}; +static const unsigned int msiof0_ss1_mux[] = { + MSIOF0_SS1_MARK, +}; +static const unsigned int msiof0_ss2_pins[] = { + /* SS2 */ + 71, +}; +static const unsigned int msiof0_ss2_mux[] = { + MSIOF0_SS2_MARK, +}; +static const unsigned int msiof0_rxd_pins[] = { + /* RXD */ + 70, +}; +static const unsigned int msiof0_rxd_mux[] = { + MSIOF0_RXD_MARK, +}; +static const unsigned int msiof0_txd_pins[] = { + /* TXD */ + 65, +}; +static const unsigned int msiof0_txd_mux[] = { + MSIOF0_TXD_MARK, +}; +static const unsigned int msiof0_mck0_pins[] = { + /* MSCK0 */ + 68, +}; +static const unsigned int msiof0_mck0_mux[] = { + MSIOF0_MCK0_MARK, +}; + +static const unsigned int msiof0_mck1_pins[] = { + /* MSCK1 */ + 69, +}; +static const unsigned int msiof0_mck1_mux[] = { + MSIOF0_MCK1_MARK, +}; + +static const unsigned int msiof0l_rsck_pins[] = { + /* RSCK */ + 214, +}; +static const unsigned int msiof0l_rsck_mux[] = { + MSIOF0L_RSCK_MARK, +}; +static const unsigned int msiof0l_tsck_pins[] = { + /* TSCK */ + 219, +}; +static const unsigned int msiof0l_tsck_mux[] = { + MSIOF0L_TSCK_MARK, +}; +static const unsigned int msiof0l_rsync_pins[] = { + /* RSYNC */ + 215, +}; +static const unsigned int msiof0l_rsync_mux[] = { + MSIOF0L_RSYNC_MARK, +}; +static const unsigned int msiof0l_tsync_pins[] = { + /* TSYNC */ + 217, +}; +static const unsigned int msiof0l_tsync_mux[] = { + MSIOF0L_TSYNC_MARK, +}; +static const unsigned int msiof0l_ss1_a_pins[] = { + /* SS1 */ + 207, +}; +static const unsigned int msiof0l_ss1_a_mux[] = { + PORT207_MSIOF0L_SS1_MARK, +}; +static const unsigned int msiof0l_ss1_b_pins[] = { + /* SS1 */ + 210, +}; +static const unsigned int msiof0l_ss1_b_mux[] = { + PORT210_MSIOF0L_SS1_MARK, +}; +static const unsigned int msiof0l_ss2_a_pins[] = { + /* SS2 */ + 208, +}; +static const unsigned int msiof0l_ss2_a_mux[] = { + PORT208_MSIOF0L_SS2_MARK, +}; +static const unsigned int msiof0l_ss2_b_pins[] = { + /* SS2 */ + 211, +}; +static const unsigned int msiof0l_ss2_b_mux[] = { + PORT211_MSIOF0L_SS2_MARK, +}; +static const unsigned int msiof0l_rxd_pins[] = { + /* RXD */ + 221, +}; +static const unsigned int msiof0l_rxd_mux[] = { + MSIOF0L_RXD_MARK, +}; +static const unsigned int msiof0l_txd_pins[] = { + /* TXD */ + 222, +}; +static const unsigned int msiof0l_txd_mux[] = { + MSIOF0L_TXD_MARK, +}; +static const unsigned int msiof0l_mck0_pins[] = { + /* MSCK0 */ + 212, +}; +static const unsigned int msiof0l_mck0_mux[] = { + MSIOF0L_MCK0_MARK, +}; +static const unsigned int msiof0l_mck1_pins[] = { + /* MSCK1 */ + 213, +}; +static const unsigned int msiof0l_mck1_mux[] = { + MSIOF0L_MCK1_MARK, +}; +/* - MSIOF1 ----------------------------------------------------------------- */ +static const unsigned int msiof1_rsck_pins[] = { + /* RSCK */ + 234, +}; +static const unsigned int msiof1_rsck_mux[] = { + MSIOF1_RSCK_MARK, +}; +static const unsigned int msiof1_tsck_pins[] = { + /* TSCK */ + 232, +}; +static const unsigned int msiof1_tsck_mux[] = { + MSIOF1_TSCK_MARK, +}; +static const unsigned int msiof1_rsync_pins[] = { + /* RSYNC */ + 235, +}; +static const unsigned int msiof1_rsync_mux[] = { + MSIOF1_RSYNC_MARK, +}; +static const unsigned int msiof1_tsync_pins[] = { + /* TSYNC */ + 231, +}; +static const unsigned int msiof1_tsync_mux[] = { + MSIOF1_TSYNC_MARK, +}; +static const unsigned int msiof1_ss1_pins[] = { + /* SS1 */ + 238, +}; +static const unsigned int msiof1_ss1_mux[] = { + MSIOF1_SS1_MARK, +}; +static const unsigned int msiof1_ss2_pins[] = { + /* SS2 */ + 239, +}; +static const unsigned int msiof1_ss2_mux[] = { + MSIOF1_SS2_MARK, +}; +static const unsigned int msiof1_rxd_pins[] = { + /* RXD */ + 233, +}; +static const unsigned int msiof1_rxd_mux[] = { + MSIOF1_RXD_MARK, +}; +static const unsigned int msiof1_txd_pins[] = { + /* TXD */ + 230, +}; +static const unsigned int msiof1_txd_mux[] = { + MSIOF1_TXD_MARK, +}; +static const unsigned int msiof1_mck0_pins[] = { + /* MSCK0 */ + 236, +}; +static const unsigned int msiof1_mck0_mux[] = { + MSIOF1_MCK0_MARK, +}; +static const unsigned int msiof1_mck1_pins[] = { + /* MSCK1 */ + 237, +}; +static const unsigned int msiof1_mck1_mux[] = { + MSIOF1_MCK1_MARK, +}; +/* - MSIOF2 ----------------------------------------------------------------- */ +static const unsigned int msiof2_rsck_pins[] = { + /* RSCK */ + 151, +}; +static const unsigned int msiof2_rsck_mux[] = { + MSIOF2_RSCK_MARK, +}; +static const unsigned int msiof2_tsck_pins[] = { + /* TSCK */ + 135, +}; +static const unsigned int msiof2_tsck_mux[] = { + MSIOF2_TSCK_MARK, +}; +static const unsigned int msiof2_rsync_pins[] = { + /* RSYNC */ + 152, +}; +static const unsigned int msiof2_rsync_mux[] = { + MSIOF2_RSYNC_MARK, +}; +static const unsigned int msiof2_tsync_pins[] = { + /* TSYNC */ + 133, +}; +static const unsigned int msiof2_tsync_mux[] = { + MSIOF2_TSYNC_MARK, +}; +static const unsigned int msiof2_ss1_a_pins[] = { + /* SS1 */ + 131, +}; +static const unsigned int msiof2_ss1_a_mux[] = { + PORT131_MSIOF2_SS1_MARK, +}; +static const unsigned int msiof2_ss1_b_pins[] = { + /* SS1 */ + 153, +}; +static const unsigned int msiof2_ss1_b_mux[] = { + PORT153_MSIOF2_SS1_MARK, +}; +static const unsigned int msiof2_ss2_a_pins[] = { + /* SS2 */ + 132, +}; +static const unsigned int msiof2_ss2_a_mux[] = { + PORT132_MSIOF2_SS2_MARK, +}; +static const unsigned int msiof2_ss2_b_pins[] = { + /* SS2 */ + 156, +}; +static const unsigned int msiof2_ss2_b_mux[] = { + PORT156_MSIOF2_SS2_MARK, +}; +static const unsigned int msiof2_rxd_a_pins[] = { + /* RXD */ + 130, +}; +static const unsigned int msiof2_rxd_a_mux[] = { + PORT130_MSIOF2_RXD_MARK, +}; +static const unsigned int msiof2_rxd_b_pins[] = { + /* RXD */ + 157, +}; +static const unsigned int msiof2_rxd_b_mux[] = { + PORT157_MSIOF2_RXD_MARK, +}; +static const unsigned int msiof2_txd_pins[] = { + /* TXD */ + 134, +}; +static const unsigned int msiof2_txd_mux[] = { + MSIOF2_TXD_MARK, +}; +static const unsigned int msiof2_mck0_pins[] = { + /* MSCK0 */ + 154, +}; +static const unsigned int msiof2_mck0_mux[] = { + MSIOF2_MCK0_MARK, +}; +static const unsigned int msiof2_mck1_pins[] = { + /* MSCK1 */ + 155, +}; +static const unsigned int msiof2_mck1_mux[] = { + MSIOF2_MCK1_MARK, +}; + +static const unsigned int msiof2r_tsck_pins[] = { + /* TSCK */ + 248, +}; +static const unsigned int msiof2r_tsck_mux[] = { + MSIOF2R_TSCK_MARK, +}; +static const unsigned int msiof2r_tsync_pins[] = { + /* TSYNC */ + 249, +}; +static const unsigned int msiof2r_tsync_mux[] = { + MSIOF2R_TSYNC_MARK, +}; +static const unsigned int msiof2r_rxd_pins[] = { + /* RXD */ + 244, +}; +static const unsigned int msiof2r_rxd_mux[] = { + MSIOF2R_RXD_MARK, +}; +static const unsigned int msiof2r_txd_pins[] = { + /* TXD */ + 245, +}; +static const unsigned int msiof2r_txd_mux[] = { + MSIOF2R_TXD_MARK, +}; +/* - MSIOF3 (Pin function name of MSIOF3 is named BBIF1) -------------------- */ +static const unsigned int msiof3_rsck_pins[] = { + /* RSCK */ + 115, +}; +static const unsigned int msiof3_rsck_mux[] = { + BBIF1_RSCK_MARK, +}; +static const unsigned int msiof3_tsck_pins[] = { + /* TSCK */ + 112, +}; +static const unsigned int msiof3_tsck_mux[] = { + BBIF1_TSCK_MARK, +}; +static const unsigned int msiof3_rsync_pins[] = { + /* RSYNC */ + 116, +}; +static const unsigned int msiof3_rsync_mux[] = { + BBIF1_RSYNC_MARK, +}; +static const unsigned int msiof3_tsync_pins[] = { + /* TSYNC */ + 113, +}; +static const unsigned int msiof3_tsync_mux[] = { + BBIF1_TSYNC_MARK, +}; +static const unsigned int msiof3_ss1_pins[] = { + /* SS1 */ + 117, +}; +static const unsigned int msiof3_ss1_mux[] = { + BBIF1_SS1_MARK, +}; +static const unsigned int msiof3_ss2_pins[] = { + /* SS2 */ + 109, +}; +static const unsigned int msiof3_ss2_mux[] = { + BBIF1_SS2_MARK, +}; +static const unsigned int msiof3_rxd_pins[] = { + /* RXD */ + 111, +}; +static const unsigned int msiof3_rxd_mux[] = { + BBIF1_RXD_MARK, +}; +static const unsigned int msiof3_txd_pins[] = { + /* TXD */ + 114, +}; +static const unsigned int msiof3_txd_mux[] = { + BBIF1_TXD_MARK, +}; +static const unsigned int msiof3_flow_pins[] = { + /* FLOW */ + 117, +}; +static const unsigned int msiof3_flow_mux[] = { + BBIF1_FLOW_MARK, +}; + /* - SCIFA0 ----------------------------------------------------------------- */ static const unsigned int scifa0_data_pins[] = { /* RXD, TXD */ @@ -2782,6 +3196,64 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(mmc0_data4_1), SH_PFC_PIN_GROUP(mmc0_data8_1), SH_PFC_PIN_GROUP(mmc0_ctrl_1), + SH_PFC_PIN_GROUP(msiof0_rsck), + SH_PFC_PIN_GROUP(msiof0_tsck), + SH_PFC_PIN_GROUP(msiof0_rsync), + SH_PFC_PIN_GROUP(msiof0_tsync), + SH_PFC_PIN_GROUP(msiof0_ss1), + SH_PFC_PIN_GROUP(msiof0_ss2), + SH_PFC_PIN_GROUP(msiof0_rxd), + SH_PFC_PIN_GROUP(msiof0_txd), + SH_PFC_PIN_GROUP(msiof0_mck0), + SH_PFC_PIN_GROUP(msiof0_mck1), + SH_PFC_PIN_GROUP(msiof0l_rsck), + SH_PFC_PIN_GROUP(msiof0l_tsck), + SH_PFC_PIN_GROUP(msiof0l_rsync), + SH_PFC_PIN_GROUP(msiof0l_tsync), + SH_PFC_PIN_GROUP(msiof0l_ss1_a), + SH_PFC_PIN_GROUP(msiof0l_ss1_b), + SH_PFC_PIN_GROUP(msiof0l_ss2_a), + SH_PFC_PIN_GROUP(msiof0l_ss2_b), + SH_PFC_PIN_GROUP(msiof0l_rxd), + SH_PFC_PIN_GROUP(msiof0l_txd), + SH_PFC_PIN_GROUP(msiof0l_mck0), + SH_PFC_PIN_GROUP(msiof0l_mck1), + SH_PFC_PIN_GROUP(msiof1_rsck), + SH_PFC_PIN_GROUP(msiof1_tsck), + SH_PFC_PIN_GROUP(msiof1_rsync), + SH_PFC_PIN_GROUP(msiof1_tsync), + SH_PFC_PIN_GROUP(msiof1_ss1), + SH_PFC_PIN_GROUP(msiof1_ss2), + SH_PFC_PIN_GROUP(msiof1_rxd), + SH_PFC_PIN_GROUP(msiof1_txd), + SH_PFC_PIN_GROUP(msiof1_mck0), + SH_PFC_PIN_GROUP(msiof1_mck1), + SH_PFC_PIN_GROUP(msiof2_rsck), + SH_PFC_PIN_GROUP(msiof2_tsck), + SH_PFC_PIN_GROUP(msiof2_rsync), + SH_PFC_PIN_GROUP(msiof2_tsync), + SH_PFC_PIN_GROUP(msiof2_ss1_a), + SH_PFC_PIN_GROUP(msiof2_ss1_b), + SH_PFC_PIN_GROUP(msiof2_ss2_a), + SH_PFC_PIN_GROUP(msiof2_ss2_b), + SH_PFC_PIN_GROUP(msiof2_rxd_a), + SH_PFC_PIN_GROUP(msiof2_rxd_b), + SH_PFC_PIN_GROUP(msiof2_txd), + SH_PFC_PIN_GROUP(msiof2_mck0), + SH_PFC_PIN_GROUP(msiof2_mck1), + SH_PFC_PIN_GROUP(msiof2r_tsck), + SH_PFC_PIN_GROUP(msiof2r_tsync), + SH_PFC_PIN_GROUP(msiof2r_rxd), + SH_PFC_PIN_GROUP(msiof2r_txd), + SH_PFC_PIN_GROUP(msiof3_rsck), + SH_PFC_PIN_GROUP(msiof3_tsck), + SH_PFC_PIN_GROUP(msiof3_rsync), + SH_PFC_PIN_GROUP(msiof3_tsync), + SH_PFC_PIN_GROUP(msiof3_ss1), + SH_PFC_PIN_GROUP(msiof3_ss2), + SH_PFC_PIN_GROUP(msiof3_rxd), + SH_PFC_PIN_GROUP(msiof3_txd), + SH_PFC_PIN_GROUP(msiof3_flow), SH_PFC_PIN_GROUP(scifa0_data), SH_PFC_PIN_GROUP(scifa0_clk), SH_PFC_PIN_GROUP(scifa0_ctrl), @@ -2982,6 +3454,76 @@ static const char * const mmc0_groups[] = { "mmc0_ctrl_1", }; +static const char * const msiof0_groups[] = { + "msiof0_rsck", + "msiof0_tsck", + "msiof0_rsync", + "msiof0_tsync", + "msiof0_ss1", + "msiof0_ss2", + "msiof0_rxd", + "msiof0_txd", + "msiof0_mck0", + "msiof0_mck1", + "msiof0l_rsck", + "msiof0l_tsck", + "msiof0l_rsync", + "msiof0l_tsync", + "msiof0l_ss1_a", + "msiof0l_ss1_b", + "msiof0l_ss2_a", + "msiof0l_ss2_b", + "msiof0l_rxd", + "msiof0l_txd", + "msiof0l_mck0", + "msiof0l_mck1", +}; + +static const char * const msiof1_groups[] = { + "msiof1_rsck", + "msiof1_tsck", + "msiof1_rsync", + "msiof1_tsync", + "msiof1_ss1", + "msiof1_ss2", + "msiof1_rxd", + "msiof1_txd", + "msiof1_mck0", + "msiof1_mck1", +}; + +static const char * const msiof2_groups[] = { + "msiof2_rsck", + "msiof2_tsck", + "msiof2_rsync", + "msiof2_tsync", + "msiof2_ss1_a", + "msiof2_ss1_b", + "msiof2_ss2_a", + "msiof2_ss2_b", + "msiof2_rxd_a", + "msiof2_rxd_b", + "msiof2_txd", + "msiof2_mck0", + "msiof2_mck1", + "msiof2r_tsck", + "msiof2r_tsync", + "msiof2r_rxd", + "msiof2r_txd", +}; + +static const char * const msiof3_groups[] = { + "msiof3_rsck", + "msiof3_tsck", + "msiof3_rsync", + "msiof3_tsync", + "msiof3_ss1", + "msiof3_ss2", + "msiof3_rxd", + "msiof3_txd", + "msiof3_flow", +}; + static const char * const scifa0_groups[] = { "scifa0_data", "scifa0_clk", @@ -3116,6 +3658,10 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(lcd), SH_PFC_FUNCTION(lcd2), SH_PFC_FUNCTION(mmc0), + SH_PFC_FUNCTION(msiof0), + SH_PFC_FUNCTION(msiof1), + SH_PFC_FUNCTION(msiof2), + SH_PFC_FUNCTION(msiof3), SH_PFC_FUNCTION(scifa0), SH_PFC_FUNCTION(scifa1), SH_PFC_FUNCTION(scifa2), -- cgit v0.10.2 From a4c8a6d2f6ed3686ce0cc789ed9213f579ebd4ad Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 26 Oct 2015 09:53:28 +0100 Subject: pinctrl: sh-pfc: r8a7791: Add SCIF_CLK support Add pins, groups, and a function for SCIF_CLK, which is the external clock source for the Baud Rate Generator for External Clock (BRG) on (H)SCIF. Signed-off-by: Geert Uytterhoeven Acked-by: Linus Walleij diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c index 10a9673..c508ae4 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c @@ -3587,6 +3587,23 @@ static const unsigned int scifb2_data_d_pins[] = { static const unsigned int scifb2_data_d_mux[] = { SCIFB2_RXD_D_MARK, SCIFB2_TXD_D_MARK, }; + +/* - SCIF Clock ------------------------------------------------------------- */ +static const unsigned int scif_clk_pins[] = { + /* SCIF_CLK */ + RCAR_GP_PIN(2, 29), +}; +static const unsigned int scif_clk_mux[] = { + SCIF_CLK_MARK, +}; +static const unsigned int scif_clk_b_pins[] = { + /* SCIF_CLK */ + RCAR_GP_PIN(7, 19), +}; +static const unsigned int scif_clk_b_mux[] = { + SCIF_CLK_B_MARK, +}; + /* - SDHI0 ------------------------------------------------------------------ */ static const unsigned int sdhi0_data1_pins[] = { /* D0 */ @@ -4495,6 +4512,8 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(scifb2_data_c), SH_PFC_PIN_GROUP(scifb2_clk_c), SH_PFC_PIN_GROUP(scifb2_data_d), + SH_PFC_PIN_GROUP(scif_clk), + SH_PFC_PIN_GROUP(scif_clk_b), SH_PFC_PIN_GROUP(sdhi0_data1), SH_PFC_PIN_GROUP(sdhi0_data4), SH_PFC_PIN_GROUP(sdhi0_ctrl), @@ -4961,6 +4980,11 @@ static const char * const scifb2_groups[] = { "scifb2_data_d", }; +static const char * const scif_clk_groups[] = { + "scif_clk", + "scif_clk_b", +}; + static const char * const sdhi0_groups[] = { "sdhi0_data1", "sdhi0_data4", @@ -5111,6 +5135,7 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(scifb0), SH_PFC_FUNCTION(scifb1), SH_PFC_FUNCTION(scifb2), + SH_PFC_FUNCTION(scif_clk), SH_PFC_FUNCTION(sdhi0), SH_PFC_FUNCTION(sdhi1), SH_PFC_FUNCTION(sdhi2), -- cgit v0.10.2 From f27200f9dce59ce5063bf722ef6ccedd34e4357b Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 16 Nov 2015 21:53:37 +0100 Subject: pinctrl: sh-pfc: r8a7795: Add SCIF_CLK support Add pins, groups, and a function for SCIF_CLK, which is the external clock source for the Baud Rate Generator for External Clock (BRG) on (H)SCIF. Signed-off-by: Geert Uytterhoeven Acked-by: Linus Walleij diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c index b9ef8ed..35e0172 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c @@ -2675,6 +2675,22 @@ static const unsigned int scif5_clk_mux[] = { SCK5_MARK, }; +/* - SCIF Clock ------------------------------------------------------------- */ +static const unsigned int scif_clk_a_pins[] = { + /* SCIF_CLK */ + RCAR_GP_PIN(6, 23), +}; +static const unsigned int scif_clk_a_mux[] = { + SCIF_CLK_A_MARK, +}; +static const unsigned int scif_clk_b_pins[] = { + /* SCIF_CLK */ + RCAR_GP_PIN(5, 9), +}; +static const unsigned int scif_clk_b_mux[] = { + SCIF_CLK_B_MARK, +}; + /* - SSI -------------------------------------------------------------------- */ static const unsigned int ssi0_data_pins[] = { /* SDATA */ @@ -3029,6 +3045,8 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(scif4_ctrl_c), SH_PFC_PIN_GROUP(scif5_data), SH_PFC_PIN_GROUP(scif5_clk), + SH_PFC_PIN_GROUP(scif_clk_a), + SH_PFC_PIN_GROUP(scif_clk_b), SH_PFC_PIN_GROUP(ssi0_data), SH_PFC_PIN_GROUP(ssi01239_ctrl), SH_PFC_PIN_GROUP(ssi1_data_a), @@ -3292,6 +3310,11 @@ static const char * const scif5_groups[] = { "scif5_clk", }; +static const char * const scif_clk_groups[] = { + "scif_clk_a", + "scif_clk_b", +}; + static const char * const ssi_groups[] = { "ssi0_data", "ssi01239_ctrl", @@ -3341,6 +3364,7 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(scif3), SH_PFC_FUNCTION(scif4), SH_PFC_FUNCTION(scif5), + SH_PFC_FUNCTION(scif_clk), SH_PFC_FUNCTION(ssi), }; -- cgit v0.10.2 From 0581b16b184031e767f64d20a93f65433d678685 Mon Sep 17 00:00:00 2001 From: Sebastian Hesselbarth Date: Sat, 28 Nov 2015 11:26:49 +0100 Subject: pinctrl: mvebu: complain about missing group after checking variant Common MVEBU pinctrl driver core gets an array of controls to modify a specific set of registers and an array of modes for each pingroup from each of the different SoC families of MVEBU. Some SoC families comprise different variants that differ in available pingroups and also controls, but to ease driver development, we can pass a variant mask to disable specific pingroups for some variants. However, controls are limited to the true number of pinctrl groups avaiable on a variant. Now, when pinctrl core driver parses over above arrays, it tries to match modes with available controls and complains about missing controls for modes that are passed to the core but actually are not avaiable on a variant with: kirkwood-pinctrl f1010000.pin-controller: unknown pinctrl group 36 This warning is a false-positive and annoying, so move the warning after we checked the variant mask for each mode setting. Also, if there is no supported setting for this variant, do not complain at all. Signed-off-by: Sebastian Hesselbarth Reported-by: Linus Walleij Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/mvebu/pinctrl-mvebu.c b/drivers/pinctrl/mvebu/pinctrl-mvebu.c index 77d2221..e4d4738 100644 --- a/drivers/pinctrl/mvebu/pinctrl-mvebu.c +++ b/drivers/pinctrl/mvebu/pinctrl-mvebu.c @@ -663,28 +663,20 @@ int mvebu_pinctrl_probe(struct platform_device *pdev) /* assign mpp modes to groups */ for (n = 0; n < soc->nmodes; n++) { struct mvebu_mpp_mode *mode = &soc->modes[n]; - struct mvebu_pinctrl_group *grp = - mvebu_pinctrl_find_group_by_pid(pctl, mode->pid); + struct mvebu_mpp_ctrl_setting *set = &mode->settings[0]; + struct mvebu_pinctrl_group *grp; unsigned num_settings; - if (!grp) { - dev_warn(&pdev->dev, "unknown pinctrl group %d\n", - mode->pid); - continue; - } - - for (num_settings = 0; ;) { - struct mvebu_mpp_ctrl_setting *set = - &mode->settings[num_settings]; - + for (num_settings = 0; ; set++) { if (!set->name) break; - num_settings++; /* skip unsupported settings for this variant */ if (pctl->variant && !(pctl->variant & set->variant)) continue; + num_settings++; + /* find gpio/gpo/gpi settings */ if (strcmp(set->name, "gpio") == 0) set->flags = MVEBU_SETTING_GPI | @@ -695,6 +687,17 @@ int mvebu_pinctrl_probe(struct platform_device *pdev) set->flags = MVEBU_SETTING_GPI; } + /* skip modes with no settings for this variant */ + if (!num_settings) + continue; + + grp = mvebu_pinctrl_find_group_by_pid(pctl, mode->pid); + if (!grp) { + dev_warn(&pdev->dev, "unknown pinctrl group %d\n", + mode->pid); + continue; + } + grp->settings = mode->settings; grp->num_settings = num_settings; } -- cgit v0.10.2 From 1403ead9ea0fda604e28ed861d5c25fdbc8d0dbc Mon Sep 17 00:00:00 2001 From: Robert Jarzmik Date: Sat, 21 Nov 2015 19:04:48 +0100 Subject: MAINTAINERS: add to pxa files pinctrl Add the pinctrl pxa drivers to the pxa maintained files. Signed-off-by: Robert Jarzmik Signed-off-by: Linus Walleij diff --git a/MAINTAINERS b/MAINTAINERS index e9caa4b..9bca217 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -8613,6 +8613,7 @@ S: Maintained F: arch/arm/mach-pxa/ F: drivers/dma/pxa* F: drivers/pcmcia/pxa2xx* +F: drivers/pinctrl/pxa/ F: drivers/spi/spi-pxa2xx* F: drivers/usb/gadget/udc/pxa2* F: include/sound/pxa2xx-lib.h -- cgit v0.10.2 From 73317712d9277407b726917de7c4e6d5a4b7df99 Mon Sep 17 00:00:00 2001 From: Robert Jarzmik Date: Sat, 21 Nov 2015 19:04:49 +0100 Subject: pinctrl: pxa: pxa2xx: add pin control skeleton Add a pincontrol driver for pxa2xx architecture, encompassing all pxa25x and pxa27x variants. This is only the pin muxing part of the driver. One specific consideration is also the memory space (MMIO), which is intertwined with the GPIO registers. To make things worse, the GPIO direction register also affect pin muxing, as it chooses the "kind" of pin, ie. the 4 output functions or 4 input functions. The mapping between pinctrl notions and PXA Technical Reference Manual is as follows : - a pin is obviously a pin - a group is also a pin, ie. group P101 is the pin 101 - a mux function is an alternate function (ie. gpio-in, gpio-out, MMCLK, BTRTS, etc ...) The individual architecture (pxa27x, pxa25x) instantiate a pin control by providing a table of pins, each pin being provided a list of PXA_FUNCTION (alternate functions). Signed-off-by: Robert Jarzmik Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/pxa/Kconfig b/drivers/pinctrl/pxa/Kconfig new file mode 100644 index 0000000..13e24d7 --- /dev/null +++ b/drivers/pinctrl/pxa/Kconfig @@ -0,0 +1,9 @@ +if (ARCH_PXA || COMPILE_TEST) + +config PINCTRL_PXA + bool + select PINMUX + select PINCONF + select GENERIC_PINCONF + +endif diff --git a/drivers/pinctrl/pxa/pinctrl-pxa2xx.c b/drivers/pinctrl/pxa/pinctrl-pxa2xx.c new file mode 100644 index 0000000..baded1a --- /dev/null +++ b/drivers/pinctrl/pxa/pinctrl-pxa2xx.c @@ -0,0 +1,252 @@ +/* + * Marvell PXA2xx family pin control + * + * Copyright (C) 2015 Robert Jarzmik + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../pinctrl-utils.h" +#include "pinctrl-pxa2xx.h" + +static int pxa2xx_pctrl_get_groups_count(struct pinctrl_dev *pctldev) +{ + struct pxa_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); + + return pctl->ngroups; +} + +static const char *pxa2xx_pctrl_get_group_name(struct pinctrl_dev *pctldev, + unsigned tgroup) +{ + struct pxa_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); + struct pxa_pinctrl_group *group = pctl->groups + tgroup; + + return group->name; +} + +static int pxa2xx_pctrl_get_group_pins(struct pinctrl_dev *pctldev, + unsigned tgroup, + const unsigned **pins, + unsigned *num_pins) +{ + struct pxa_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); + struct pxa_pinctrl_group *group = pctl->groups + tgroup; + + *pins = (unsigned *)&group->pin; + *num_pins = 1; + + return 0; +} + +static const struct pinctrl_ops pxa2xx_pctl_ops = { +#ifdef CONFIG_OF + .dt_node_to_map = pinconf_generic_dt_node_to_map_all, + .dt_free_map = pinctrl_utils_dt_free_map, +#endif + .get_groups_count = pxa2xx_pctrl_get_groups_count, + .get_group_name = pxa2xx_pctrl_get_group_name, + .get_group_pins = pxa2xx_pctrl_get_group_pins, +}; + +static struct pinctrl_desc pxa2xx_pinctrl_desc = { + .pctlops = &pxa2xx_pctl_ops, +}; + +static const struct pxa_pinctrl_function * +pxa2xx_find_function(struct pxa_pinctrl *pctl, const char *fname, + const struct pxa_pinctrl_function *functions) +{ + const struct pxa_pinctrl_function *func; + + for (func = functions; func->name; func++) + if (!strcmp(fname, func->name)) + return func; + + return NULL; +} + +static int pxa2xx_build_functions(struct pxa_pinctrl *pctl) +{ + int i; + struct pxa_pinctrl_function *functions; + struct pxa_desc_function *df; + + /* + * Each pin can have at most 6 alternate functions, and 2 gpio functions + * which are common to each pin. As there are more than 2 pins without + * alternate function, 6 * npins is an absolute high limit of the number + * of functions. + */ + functions = devm_kcalloc(pctl->dev, pctl->npins * 6, + sizeof(*functions), GFP_KERNEL); + if (!functions) + return -ENOMEM; + + for (i = 0; i < pctl->npins; i++) + for (df = pctl->ppins[i].functions; df->name; df++) + if (!pxa2xx_find_function(pctl, df->name, functions)) + (functions + pctl->nfuncs++)->name = df->name; + pctl->functions = devm_kmemdup(pctl->dev, functions, + pctl->nfuncs * sizeof(*functions), + GFP_KERNEL); + if (!pctl->functions) + return -ENOMEM; + + kfree(functions); + return 0; +} + +static int pxa2xx_build_groups(struct pxa_pinctrl *pctl) +{ + int i, j, ngroups; + struct pxa_pinctrl_function *func; + struct pxa_desc_function *df; + char **gtmp; + + gtmp = devm_kmalloc_array(pctl->dev, pctl->npins, sizeof(*gtmp), + GFP_KERNEL); + if (!gtmp) + return -ENOMEM; + + for (i = 0; i < pctl->nfuncs; i++) { + ngroups = 0; + for (j = 0; j < pctl->npins; j++) + for (df = pctl->ppins[j].functions; df->name; + df++) + if (!strcmp(pctl->functions[i].name, + df->name)) + gtmp[ngroups++] = (char *) + pctl->ppins[j].pin.name; + func = pctl->functions + i; + func->ngroups = ngroups; + func->groups = + devm_kmalloc_array(pctl->dev, ngroups, + sizeof(char *), GFP_KERNEL); + if (!func->groups) + return -ENOMEM; + + memcpy(func->groups, gtmp, ngroups * sizeof(*gtmp)); + } + + kfree(gtmp); + return 0; +} + +static int pxa2xx_build_state(struct pxa_pinctrl *pctl, + const struct pxa_desc_pin *ppins, int npins) +{ + struct pxa_pinctrl_group *group; + struct pinctrl_pin_desc *pins; + int ret, i; + + pctl->npins = npins; + pctl->ppins = ppins; + pctl->ngroups = npins; + + pctl->desc.npins = npins; + pins = devm_kcalloc(pctl->dev, npins, sizeof(*pins), GFP_KERNEL); + if (!pins) + return -ENOMEM; + + pctl->desc.pins = pins; + for (i = 0; i < npins; i++) + pins[i] = ppins[i].pin; + + pctl->groups = devm_kmalloc_array(pctl->dev, pctl->ngroups, + sizeof(*pctl->groups), GFP_KERNEL); + if (!pctl->groups) + return -ENOMEM; + + for (i = 0; i < npins; i++) { + group = pctl->groups + i; + group->name = ppins[i].pin.name; + group->pin = ppins[i].pin.number; + } + + ret = pxa2xx_build_functions(pctl); + if (ret) + return ret; + + ret = pxa2xx_build_groups(pctl); + if (ret) + return ret; + + return 0; +} + +int pxa2xx_pinctrl_init(struct platform_device *pdev, + const struct pxa_desc_pin *ppins, int npins, + void __iomem *base_gafr[], void __iomem *base_gpdr[], + void __iomem *base_pgsr[]) +{ + struct pxa_pinctrl *pctl; + int ret, i, maxpin = 0; + + for (i = 0; i < npins; i++) + maxpin = max_t(int, ppins[i].pin.number, maxpin); + + pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL); + if (!pctl) + return -ENOMEM; + pctl->base_gafr = devm_kcalloc(&pdev->dev, roundup(maxpin, 16), + sizeof(*pctl->base_gafr), GFP_KERNEL); + pctl->base_gpdr = devm_kcalloc(&pdev->dev, roundup(maxpin, 32), + sizeof(*pctl->base_gpdr), GFP_KERNEL); + pctl->base_pgsr = devm_kcalloc(&pdev->dev, roundup(maxpin, 32), + sizeof(*pctl->base_pgsr), GFP_KERNEL); + if (!pctl->base_gafr || !pctl->base_gpdr || !pctl->base_pgsr) + return -ENOMEM; + + platform_set_drvdata(pdev, pctl); + spin_lock_init(&pctl->lock); + + pctl->dev = &pdev->dev; + pctl->desc = pxa2xx_pinctrl_desc; + pctl->desc.name = dev_name(&pdev->dev); + pctl->desc.owner = THIS_MODULE; + + for (i = 0; i < roundup(maxpin, 16); i += 16) + pctl->base_gafr[i / 16] = base_gafr[i / 16]; + for (i = 0; i < roundup(maxpin, 32); i += 32) { + pctl->base_gpdr[i / 32] = base_gpdr[i / 32]; + pctl->base_pgsr[i / 32] = base_pgsr[i / 32]; + } + + ret = pxa2xx_build_state(pctl, ppins, npins); + if (ret) + return ret; + + pctl->pctl_dev = pinctrl_register(&pctl->desc, &pdev->dev, pctl); + if (IS_ERR(pctl->pctl_dev)) { + dev_err(&pdev->dev, "couldn't register pinctrl driver\n"); + return PTR_ERR(pctl->pctl_dev); + } + + dev_info(&pdev->dev, "initialized pxa2xx pinctrl driver\n"); + + return 0; +} + +int pxa2xx_pinctrl_exit(struct platform_device *pdev) +{ + struct pxa_pinctrl *pctl = platform_get_drvdata(pdev); + + pinctrl_unregister(pctl->pctl_dev); + return 0; +} diff --git a/drivers/pinctrl/pxa/pinctrl-pxa2xx.h b/drivers/pinctrl/pxa/pinctrl-pxa2xx.h new file mode 100644 index 0000000..8be1e0b --- /dev/null +++ b/drivers/pinctrl/pxa/pinctrl-pxa2xx.h @@ -0,0 +1,92 @@ +/* + * Marvell PXA2xx family pin control + * + * Copyright (C) 2015 Robert Jarzmik + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + */ + +#ifndef __PINCTRL_PXA_H +#define __PINCTRL_PXA_H + +#define PXA_FUNCTION(_dir, _af, _name) \ + { \ + .name = _name, \ + .muxval = (_dir | (_af << 1)), \ + } + +#define PXA_PIN(_pin, funcs...) \ + { \ + .pin = _pin, \ + .functions = (struct pxa_desc_function[]){ \ + funcs, { } }, \ + } + +#define PXA_GPIO_PIN(_pin, funcs...) \ + { \ + .pin = _pin, \ + .functions = (struct pxa_desc_function[]){ \ + PXA_FUNCTION(0, 0, "gpio_in"), \ + PXA_FUNCTION(1, 0, "gpio_out"), \ + funcs, { } }, \ + } + +#define PXA_GPIO_ONLY_PIN(_pin) \ + { \ + .pin = _pin, \ + .functions = (struct pxa_desc_function[]){ \ + PXA_FUNCTION(0, 0, "gpio_in"), \ + PXA_FUNCTION(1, 0, "gpio_out"), \ + { } }, \ + } + +#define PXA_PINCTRL_PIN(pin) \ + PINCTRL_PIN(pin, "P" #pin) + +struct pxa_desc_function { + const char *name; + u8 muxval; +}; + +struct pxa_desc_pin { + struct pinctrl_pin_desc pin; + struct pxa_desc_function *functions; +}; + +struct pxa_pinctrl_group { + const char *name; + unsigned pin; +}; + +struct pxa_pinctrl_function { + const char *name; + const char **groups; + unsigned ngroups; +}; + +struct pxa_pinctrl { + spinlock_t lock; + void __iomem **base_gafr; + void __iomem **base_gpdr; + void __iomem **base_pgsr; + struct device *dev; + struct pinctrl_desc desc; + struct pinctrl_dev *pctl_dev; + unsigned npins; + const struct pxa_desc_pin *ppins; + unsigned ngroups; + struct pxa_pinctrl_group *groups; + unsigned nfuncs; + struct pxa_pinctrl_function *functions; + char *name; +}; + +int pxa2xx_pinctrl_init(struct platform_device *pdev, + const struct pxa_desc_pin *ppins, int npins, + void __iomem *base_gafr[], void __iomem *base_gpdr[], + void __iomem *base_gpsr[]); + +#endif /* __PINCTRL_PXA_H */ -- cgit v0.10.2 From d530ef9b88e5162a1972050994264d66ca884f3f Mon Sep 17 00:00:00 2001 From: Robert Jarzmik Date: Sat, 21 Nov 2015 19:04:50 +0100 Subject: pinctrl: pxa: pxa2xx: add pin muxing The driver is inspired from the sunxi driver. The pxa architecture specificities leading to the driver are : - each pin has 8 possible alternate functions - 4 of these are output kind - 4 of these are input kind - there is always a "gpio input" and "gpio output" function - the function matrix is very scattered : - some functions can be found on 5 different pads - the number of functions is greater than the number of pins - there is no "topology" grouping of pins (such as all SPI in one corner of the die) Signed-off-by: Robert Jarzmik Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/pxa/pinctrl-pxa2xx.c b/drivers/pinctrl/pxa/pinctrl-pxa2xx.c index baded1a..a4ba824 100644 --- a/drivers/pinctrl/pxa/pinctrl-pxa2xx.c +++ b/drivers/pinctrl/pxa/pinctrl-pxa2xx.c @@ -64,8 +64,129 @@ static const struct pinctrl_ops pxa2xx_pctl_ops = { .get_group_pins = pxa2xx_pctrl_get_group_pins, }; +static struct pxa_desc_function * +pxa_desc_by_func_group(struct pxa_pinctrl *pctl, const char *pin_name, + const char *func_name) +{ + int i; + struct pxa_desc_function *df; + + for (i = 0; i < pctl->npins; i++) { + const struct pxa_desc_pin *pin = pctl->ppins + i; + + if (!strcmp(pin->pin.name, pin_name)) + for (df = pin->functions; df->name; df++) + if (!strcmp(df->name, func_name)) + return df; + } + + return NULL; +} + +static int pxa2xx_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, + unsigned pin, + bool input) +{ + struct pxa_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); + unsigned long flags; + uint32_t val; + void __iomem *gpdr; + + gpdr = pctl->base_gpdr[pin / 32]; + dev_dbg(pctl->dev, "set_direction(pin=%d): dir=%d\n", + pin, !input); + + spin_lock_irqsave(&pctl->lock, flags); + + val = readl_relaxed(gpdr); + val = (val & ~BIT(pin % 32)) | (input ? 0 : BIT(pin % 32)); + writel_relaxed(val, gpdr); + + spin_unlock_irqrestore(&pctl->lock, flags); + + return 0; +} + +static const char *pxa2xx_pmx_get_func_name(struct pinctrl_dev *pctldev, + unsigned function) +{ + struct pxa_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); + struct pxa_pinctrl_function *pf = pctl->functions + function; + + return pf->name; +} + +static int pxa2xx_get_functions_count(struct pinctrl_dev *pctldev) +{ + struct pxa_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); + + return pctl->nfuncs; +} + +static int pxa2xx_pmx_get_func_groups(struct pinctrl_dev *pctldev, + unsigned function, + const char * const **groups, + unsigned * const num_groups) +{ + struct pxa_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); + struct pxa_pinctrl_function *pf = pctl->functions + function; + + *groups = pf->groups; + *num_groups = pf->ngroups; + + return 0; +} + +static int pxa2xx_pmx_set_mux(struct pinctrl_dev *pctldev, unsigned function, + unsigned tgroup) +{ + struct pxa_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); + struct pxa_pinctrl_group *group = pctl->groups + tgroup; + struct pxa_desc_function *df; + int pin, shift; + unsigned long flags; + void __iomem *gafr, *gpdr; + u32 val; + + + df = pxa_desc_by_func_group(pctl, group->name, + (pctl->functions + function)->name); + if (!df) + return -EINVAL; + + pin = group->pin; + gafr = pctl->base_gafr[pin / 16]; + gpdr = pctl->base_gpdr[pin / 32]; + shift = (pin % 16) << 1; + dev_dbg(pctl->dev, "set_mux(pin=%d): af=%d dir=%d\n", + pin, df->muxval >> 1, df->muxval & 0x1); + + spin_lock_irqsave(&pctl->lock, flags); + + val = readl_relaxed(gafr); + val = (val & ~(0x3 << shift)) | ((df->muxval >> 1) << shift); + writel_relaxed(val, gafr); + + val = readl_relaxed(gpdr); + val = (val & ~BIT(pin % 32)) | ((df->muxval & 1) ? BIT(pin % 32) : 0); + writel_relaxed(val, gpdr); + + spin_unlock_irqrestore(&pctl->lock, flags); + + return 0; +} +static const struct pinmux_ops pxa2xx_pinmux_ops = { + .get_functions_count = pxa2xx_get_functions_count, + .get_function_name = pxa2xx_pmx_get_func_name, + .get_function_groups = pxa2xx_pmx_get_func_groups, + .set_mux = pxa2xx_pmx_set_mux, + .gpio_set_direction = pxa2xx_pmx_gpio_set_direction, +}; + static struct pinctrl_desc pxa2xx_pinctrl_desc = { .pctlops = &pxa2xx_pctl_ops, + .pmxops = &pxa2xx_pinmux_ops, }; static const struct pxa_pinctrl_function * -- cgit v0.10.2 From aedf08b664b71ecf0b35891eb6c83e26b888342a Mon Sep 17 00:00:00 2001 From: Robert Jarzmik Date: Sat, 21 Nov 2015 19:04:51 +0100 Subject: pinctrl: pxa: pxa2xx: add pin configuration support Add pin configuration for pxa2xx architectures. PXA doesn't provide any bias, push, pull capabilities. The only capability is to set a state for the pins when the platform enter sleep or deep sleep mode. The state of a pin is set by : - whether the GPIO direction was input or output - if it is output, a register set programs whether the pin should be held to ground or VccIO Signed-off-by: Robert Jarzmik Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/pxa/pinctrl-pxa2xx.c b/drivers/pinctrl/pxa/pinctrl-pxa2xx.c index a4ba824..e019144 100644 --- a/drivers/pinctrl/pxa/pinctrl-pxa2xx.c +++ b/drivers/pinctrl/pxa/pinctrl-pxa2xx.c @@ -184,7 +184,70 @@ static const struct pinmux_ops pxa2xx_pinmux_ops = { .gpio_set_direction = pxa2xx_pmx_gpio_set_direction, }; +static int pxa2xx_pconf_group_get(struct pinctrl_dev *pctldev, + unsigned group, + unsigned long *config) +{ + struct pxa_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); + struct pxa_pinctrl_group *g = pctl->groups + group; + unsigned long flags; + unsigned pin = g->pin; + void __iomem *pgsr = pctl->base_pgsr[pin / 32]; + u32 val; + + spin_lock_irqsave(&pctl->lock, flags); + val = readl_relaxed(pgsr) & BIT(pin % 32); + *config = val ? PIN_CONFIG_LOW_POWER_MODE : 0; + spin_unlock_irqrestore(&pctl->lock, flags); + + dev_dbg(pctl->dev, "get sleep gpio state(pin=%d) %d\n", + pin, !!val); + return 0; +} + +static int pxa2xx_pconf_group_set(struct pinctrl_dev *pctldev, + unsigned group, + unsigned long *configs, + unsigned num_configs) +{ + struct pxa_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); + struct pxa_pinctrl_group *g = pctl->groups + group; + unsigned long flags; + unsigned pin = g->pin; + void __iomem *pgsr = pctl->base_pgsr[pin / 32]; + int i, is_set = 0; + u32 val; + + for (i = 0; i < num_configs; i++) { + switch (pinconf_to_config_param(configs[i])) { + case PIN_CONFIG_LOW_POWER_MODE: + is_set = pinconf_to_config_argument(configs[i]); + break; + default: + return -EINVAL; + } + } + + dev_dbg(pctl->dev, "set sleep gpio state(pin=%d) %d\n", + pin, is_set); + + spin_lock_irqsave(&pctl->lock, flags); + val = readl_relaxed(pgsr); + val = (val & ~BIT(pin % 32)) | (is_set ? BIT(pin % 32) : 0); + writel_relaxed(val, pgsr); + spin_unlock_irqrestore(&pctl->lock, flags); + + return 0; +} + +static const struct pinconf_ops pxa2xx_pconf_ops = { + .pin_config_group_get = pxa2xx_pconf_group_get, + .pin_config_group_set = pxa2xx_pconf_group_set, + .is_generic = true, +}; + static struct pinctrl_desc pxa2xx_pinctrl_desc = { + .confops = &pxa2xx_pconf_ops, .pctlops = &pxa2xx_pctl_ops, .pmxops = &pxa2xx_pinmux_ops, }; -- cgit v0.10.2 From d0e3096859eee425397c7a93b93ddeaa140b997d Mon Sep 17 00:00:00 2001 From: Robert Jarzmik Date: Sat, 21 Nov 2015 19:04:52 +0100 Subject: pinctrl: pxa: add pxa27x architecture Add the pxa27x architecture, which is a pxa2xx with 128 pins. The registers spacing, and pins logic is common to pxa2xx, only the pins and their alternate function are specific to pxa27x. Signed-off-by: Robert Jarzmik Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/pxa/Kconfig b/drivers/pinctrl/pxa/Kconfig index 13e24d7..990667f 100644 --- a/drivers/pinctrl/pxa/Kconfig +++ b/drivers/pinctrl/pxa/Kconfig @@ -6,4 +6,12 @@ config PINCTRL_PXA select PINCONF select GENERIC_PINCONF +config PINCTRL_PXA27X + tristate "Marvell PXA27x pin controller driver" + select PINCTRL_PXA + default y if PXA27x + help + This is the pinctrl, pinmux, pinconf driver for the Marvell + PXA2xx block found in the pxa25x and pxa27x platforms. + endif diff --git a/drivers/pinctrl/pxa/Makefile b/drivers/pinctrl/pxa/Makefile new file mode 100644 index 0000000..f1d56af --- /dev/null +++ b/drivers/pinctrl/pxa/Makefile @@ -0,0 +1,2 @@ +# Marvell PXA pin control drivers +obj-$(CONFIG_PINCTRL_PXA27X) += pinctrl-pxa2xx.o pinctrl-pxa27x.o diff --git a/drivers/pinctrl/pxa/pinctrl-pxa27x.c b/drivers/pinctrl/pxa/pinctrl-pxa27x.c new file mode 100644 index 0000000..2e2c370 --- /dev/null +++ b/drivers/pinctrl/pxa/pinctrl-pxa27x.c @@ -0,0 +1,566 @@ +/* + * Marvell PXA27x family pin control + * + * Copyright (C) 2015 Robert Jarzmik + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + */ +#include +#include +#include +#include +#include + +#include "pinctrl-pxa2xx.h" + +static const struct pxa_desc_pin pxa27x_pins[] = { + PXA_GPIO_ONLY_PIN(PXA_PINCTRL_PIN(0)), + PXA_GPIO_ONLY_PIN(PXA_PINCTRL_PIN(1)), + PXA_GPIO_PIN(PXA_PINCTRL_PIN(9), + PXA_FUNCTION(0, 3, "FFCTS"), + PXA_FUNCTION(1, 1, "HZ_CLK"), + PXA_FUNCTION(1, 3, "CHOUT<0>")), + PXA_GPIO_PIN(PXA_PINCTRL_PIN(10), + PXA_FUNCTION(0, 1, "FFDCD"), + PXA_FUNCTION(0, 3, "USB_P3_5"), + PXA_FUNCTION(1, 1, "HZ_CLK"), + PXA_FUNCTION(1, 3, "CHOUT<1>")), + PXA_GPIO_PIN(PXA_PINCTRL_PIN(11), + PXA_FUNCTION(0, 1, "EXT_SYNC<0>"), + PXA_FUNCTION(0, 2, "SSPRXD2"), + PXA_FUNCTION(0, 3, "USB_P3_1"), + PXA_FUNCTION(1, 1, "CHOUT<0>"), + PXA_FUNCTION(1, 1, "PWM_OUT<2>"), + PXA_FUNCTION(1, 3, "48_MHz")), + PXA_GPIO_PIN(PXA_PINCTRL_PIN(12), + PXA_FUNCTION(0, 1, "EXT_SYNC<1>"), + PXA_FUNCTION(0, 2, "CIF_DD<7>"), + PXA_FUNCTION(1, 1, "CHOUT<1>"), + PXA_FUNCTION(1, 1, "PWM_OUT<3>"), + PXA_FUNCTION(1, 3, "48_MHz")), + PXA_GPIO_PIN(PXA_PINCTRL_PIN(13), + PXA_FUNCTION(0, 1, "CLK_EXT"), + PXA_FUNCTION(0, 2, "KP_DKIN<7>"), + PXA_FUNCTION(0, 3, "KP_MKIN<7>"), + PXA_FUNCTION(1, 1, "SSPTXD2")), + PXA_GPIO_PIN(PXA_PINCTRL_PIN(14), + PXA_FUNCTION(0, 1, "L_VSYNC"), + PXA_FUNCTION(0, 2, "SSPSFRM2"), + PXA_FUNCTION(1, 1, "SSPSFRM2"), + PXA_FUNCTION(1, 3, "UCLK")), + PXA_GPIO_ONLY_PIN(PXA_PINCTRL_PIN(15)), + PXA_GPIO_PIN(PXA_PINCTRL_PIN(16), + PXA_FUNCTION(0, 1, "KP_MKIN<5>"), + PXA_FUNCTION(1, 2, "PWM_OUT<0>"), + PXA_FUNCTION(1, 3, "FFTXD")), + PXA_GPIO_PIN(PXA_PINCTRL_PIN(17), + PXA_FUNCTION(0, 1, "KP_MKIN<6>"), + PXA_FUNCTION(0, 2, "CIF_DD<6>"), + PXA_FUNCTION(1, 2, "PWM_OUT<1>")), + PXA_GPIO_PIN(PXA_PINCTRL_PIN(18), + PXA_FUNCTION(0, 1, "RDY")), + PXA_GPIO_PIN(PXA_PINCTRL_PIN(19), + PXA_FUNCTION(0, 1, "SSPSCLK2"), + PXA_FUNCTION(0, 3, "FFRXD"), + PXA_FUNCTION(1, 1, "SSPSCLK2"), + PXA_FUNCTION(1, 2, "L_CS"), + PXA_FUNCTION(1, 3, "nURST")), + PXA_GPIO_PIN(PXA_PINCTRL_PIN(20), + PXA_FUNCTION(0, 1, "DREQ<0>"), + PXA_FUNCTION(0, 2, "MBREQ"), + PXA_FUNCTION(1, 1, "nSDCS<2>")), + PXA_GPIO_PIN(PXA_PINCTRL_PIN(21), + PXA_FUNCTION(1, 1, "nSDCS<3>"), + PXA_FUNCTION(1, 2, "DVAL<0>"), + PXA_FUNCTION(1, 3, "MBGNT")), + PXA_GPIO_PIN(PXA_PINCTRL_PIN(22), + PXA_FUNCTION(0, 1, "SSPEXTCLK2"), + PXA_FUNCTION(0, 2, "SSPSCLKEN2"), + PXA_FUNCTION(0, 3, "SSPSCLK2"), + PXA_FUNCTION(1, 1, "KP_MKOUT<7>"), + PXA_FUNCTION(1, 2, "SSPSYSCLK2"), + PXA_FUNCTION(1, 3, "SSPSCLK2")), + PXA_GPIO_PIN(PXA_PINCTRL_PIN(23), + PXA_FUNCTION(0, 2, "SSPSCLK"), + PXA_FUNCTION(1, 1, "CIF_MCLK"), + PXA_FUNCTION(1, 1, "SSPSCLK")), + PXA_GPIO_PIN(PXA_PINCTRL_PIN(24), + PXA_FUNCTION(0, 1, "CIF_FV"), + PXA_FUNCTION(0, 2, "SSPSFRM"), + PXA_FUNCTION(1, 1, "CIF_FV"), + PXA_FUNCTION(1, 2, "SSPSFRM")), + PXA_GPIO_PIN(PXA_PINCTRL_PIN(25), + PXA_FUNCTION(0, 1, "CIF_LV"), + PXA_FUNCTION(1, 1, "CIF_LV"), + PXA_FUNCTION(1, 2, "SSPTXD")), + PXA_GPIO_PIN(PXA_PINCTRL_PIN(26), + PXA_FUNCTION(0, 1, "SSPRXD"), + PXA_FUNCTION(0, 2, "CIF_PCLK"), + PXA_FUNCTION(0, 3, "FFCTS")), + PXA_GPIO_PIN(PXA_PINCTRL_PIN(27), + PXA_FUNCTION(0, 1, "SSPEXTCLK"), + PXA_FUNCTION(0, 2, "SSPSCLKEN"), + PXA_FUNCTION(0, 3, "CIF_DD<0>"), + PXA_FUNCTION(1, 1, "SSPSYSCLK"), + PXA_FUNCTION(1, 3, "FFRTS")), + PXA_GPIO_PIN(PXA_PINCTRL_PIN(28), + PXA_FUNCTION(0, 1, "AC97_BITCLK"), + PXA_FUNCTION(0, 2, "I2S_BITCLK"), + PXA_FUNCTION(0, 3, "SSPSFRM"), + PXA_FUNCTION(1, 1, "I2S_BITCLK"), + PXA_FUNCTION(1, 3, "SSPSFRM")), + PXA_GPIO_PIN(PXA_PINCTRL_PIN(29), + PXA_FUNCTION(0, 1, "AC97_SDATA_IN_0"), + PXA_FUNCTION(0, 2, "I2S_SDATA_IN"), + PXA_FUNCTION(0, 3, "SSPSCLK"), + PXA_FUNCTION(1, 1, "SSPRXD2"), + PXA_FUNCTION(1, 3, "SSPSCLK")), + PXA_GPIO_PIN(PXA_PINCTRL_PIN(30), + PXA_FUNCTION(1, 1, "I2S_SDATA_OUT"), + PXA_FUNCTION(1, 2, "AC97_SDATA_OUT"), + PXA_FUNCTION(1, 3, "USB_P3_2")), + PXA_GPIO_PIN(PXA_PINCTRL_PIN(31), + PXA_FUNCTION(1, 1, "I2S_SYNC"), + PXA_FUNCTION(1, 2, "AC97_SYNC"), + PXA_FUNCTION(1, 3, "USB_P3_6")), + PXA_GPIO_PIN(PXA_PINCTRL_PIN(32), + PXA_FUNCTION(1, 1, "MSSCLK"), + PXA_FUNCTION(1, 2, "MMCLK")), + PXA_GPIO_PIN(PXA_PINCTRL_PIN(33), + PXA_FUNCTION(0, 1, "FFRXD"), + PXA_FUNCTION(0, 2, "FFDSR"), + PXA_FUNCTION(1, 1, "DVAL<1>"), + PXA_FUNCTION(1, 2, "nCS<5>"), + PXA_FUNCTION(1, 3, "MBGNT")), + PXA_GPIO_PIN(PXA_PINCTRL_PIN(34), + PXA_FUNCTION(0, 1, "FFRXD"), + PXA_FUNCTION(0, 2, "KP_MKIN<3>"), + PXA_FUNCTION(0, 3, "SSPSCLK3"), + PXA_FUNCTION(1, 1, "USB_P2_2"), + PXA_FUNCTION(1, 3, "SSPSCLK3")), + PXA_GPIO_PIN(PXA_PINCTRL_PIN(35), + PXA_FUNCTION(0, 1, "FFCTS"), + PXA_FUNCTION(0, 2, "USB_P2_1"), + PXA_FUNCTION(0, 3, "SSPSFRM3"), + PXA_FUNCTION(1, 2, "KP_MKOUT<6>"), + PXA_FUNCTION(1, 3, "SSPTXD3")), + PXA_GPIO_PIN(PXA_PINCTRL_PIN(36), + PXA_FUNCTION(0, 1, "FFDCD"), + PXA_FUNCTION(0, 2, "SSPSCLK2"), + PXA_FUNCTION(0, 3, "KP_MKIN<7>"), + PXA_FUNCTION(1, 1, "USB_P2_4"), + PXA_FUNCTION(1, 2, "SSPSCLK2")), + PXA_GPIO_PIN(PXA_PINCTRL_PIN(37), + PXA_FUNCTION(0, 1, "FFDSR"), + PXA_FUNCTION(0, 2, "SSPSFRM2"), + PXA_FUNCTION(0, 3, "KP_MKIN<3>"), + PXA_FUNCTION(1, 1, "USB_P2_8"), + PXA_FUNCTION(1, 2, "SSPSFRM2"), + PXA_FUNCTION(1, 3, "FFTXD")), + PXA_GPIO_PIN(PXA_PINCTRL_PIN(38), + PXA_FUNCTION(0, 1, "FFRI"), + PXA_FUNCTION(0, 2, "KP_MKIN<4>"), + PXA_FUNCTION(0, 3, "USB_P2_3"), + PXA_FUNCTION(1, 1, "SSPTXD3"), + PXA_FUNCTION(1, 2, "SSPTXD2"), + PXA_FUNCTION(1, 3, "PWM_OUT<0>")), + PXA_GPIO_PIN(PXA_PINCTRL_PIN(39), + PXA_FUNCTION(0, 1, "KP_MKIN<4>"), + PXA_FUNCTION(0, 3, "SSPSFRM3"), + PXA_FUNCTION(1, 1, "USB_P2_6"), + PXA_FUNCTION(1, 2, "FFTXD"), + PXA_FUNCTION(1, 3, "SSPSFRM3")), + PXA_GPIO_PIN(PXA_PINCTRL_PIN(40), + PXA_FUNCTION(0, 1, "SSPRXD2"), + PXA_FUNCTION(0, 3, "USB_P2_5"), + PXA_FUNCTION(1, 1, "KP_MKOUT<6>"), + PXA_FUNCTION(1, 2, "FFDTR"), + PXA_FUNCTION(1, 3, "SSPSCLK3")), + PXA_GPIO_PIN(PXA_PINCTRL_PIN(41), + PXA_FUNCTION(0, 1, "FFRXD"), + PXA_FUNCTION(0, 2, "USB_P2_7"), + PXA_FUNCTION(0, 3, "SSPRXD3"), + PXA_FUNCTION(1, 1, "KP_MKOUT<7>"), + PXA_FUNCTION(1, 2, "FFRTS")), + PXA_GPIO_PIN(PXA_PINCTRL_PIN(42), + PXA_FUNCTION(0, 1, "BTRXD"), + PXA_FUNCTION(0, 2, "ICP_RXD"), + PXA_FUNCTION(1, 3, "CIF_MCLK")), + PXA_GPIO_PIN(PXA_PINCTRL_PIN(43), + PXA_FUNCTION(0, 3, "CIF_FV"), + PXA_FUNCTION(1, 1, "ICP_TXD"), + PXA_FUNCTION(1, 2, "BTTXD"), + PXA_FUNCTION(1, 3, "CIF_FV")), + PXA_GPIO_PIN(PXA_PINCTRL_PIN(44), + PXA_FUNCTION(0, 1, "BTCTS"), + PXA_FUNCTION(0, 3, "CIF_LV"), + PXA_FUNCTION(1, 3, "CIF_LV")), + PXA_GPIO_PIN(PXA_PINCTRL_PIN(45), + PXA_FUNCTION(0, 3, "CIF_PCLK"), + PXA_FUNCTION(1, 1, "AC97_SYSCLK"), + PXA_FUNCTION(1, 2, "BTRTS"), + PXA_FUNCTION(1, 3, "SSPSYSCLK3")), + PXA_GPIO_PIN(PXA_PINCTRL_PIN(46), + PXA_FUNCTION(0, 1, "ICP_RXD"), + PXA_FUNCTION(0, 2, "STD_RXD"), + PXA_FUNCTION(1, 2, "PWM_OUT<2>")), + PXA_GPIO_PIN(PXA_PINCTRL_PIN(47), + PXA_FUNCTION(0, 1, "CIF_DD<0>"), + PXA_FUNCTION(1, 1, "STD_TXD"), + PXA_FUNCTION(1, 2, "ICP_TXD"), + PXA_FUNCTION(1, 3, "PWM_OUT<3>")), + PXA_GPIO_PIN(PXA_PINCTRL_PIN(48), + PXA_FUNCTION(0, 1, "CIF_DD<5>"), + PXA_FUNCTION(1, 1, "BB_OB_DAT<1>"), + PXA_FUNCTION(1, 2, "nPOE")), + PXA_GPIO_PIN(PXA_PINCTRL_PIN(49), + PXA_FUNCTION(1, 2, "nPWE")), + PXA_GPIO_PIN(PXA_PINCTRL_PIN(50), + PXA_FUNCTION(0, 1, "CIF_DD<3>"), + PXA_FUNCTION(0, 3, "SSPSCLK2"), + PXA_FUNCTION(1, 1, "BB_OB_DAT<2>"), + PXA_FUNCTION(1, 2, "nPIOR"), + PXA_FUNCTION(1, 3, "SSPSCLK2")), + PXA_GPIO_PIN(PXA_PINCTRL_PIN(51), + PXA_FUNCTION(0, 1, "CIF_DD<2>"), + PXA_FUNCTION(1, 1, "BB_OB_DAT<3>"), + PXA_FUNCTION(1, 2, "nPIOW")), + PXA_GPIO_PIN(PXA_PINCTRL_PIN(52), + PXA_FUNCTION(0, 1, "CIF_DD<4>"), + PXA_FUNCTION(0, 2, "SSPSCLK3"), + PXA_FUNCTION(1, 1, "BB_OB_CLK"), + PXA_FUNCTION(1, 2, "SSPSCLK3")), + PXA_GPIO_PIN(PXA_PINCTRL_PIN(53), + PXA_FUNCTION(0, 1, "FFRXD"), + PXA_FUNCTION(0, 2, "USB_P2_3"), + PXA_FUNCTION(1, 1, "BB_OB_STB"), + PXA_FUNCTION(1, 2, "CIF_MCLK"), + PXA_FUNCTION(1, 3, "SSPSYSCLK")), + PXA_GPIO_PIN(PXA_PINCTRL_PIN(54), + PXA_FUNCTION(0, 2, "BB_OB_WAIT"), + PXA_FUNCTION(0, 3, "CIF_PCLK"), + PXA_FUNCTION(1, 2, "nPCE<2>")), + PXA_GPIO_PIN(PXA_PINCTRL_PIN(55), + PXA_FUNCTION(0, 1, "CIF_DD<1>"), + PXA_FUNCTION(0, 2, "BB_IB_DAT<1>"), + PXA_FUNCTION(1, 2, "nPREG")), + PXA_GPIO_PIN(PXA_PINCTRL_PIN(56), + PXA_FUNCTION(0, 1, "nPWAIT"), + PXA_FUNCTION(0, 2, "BB_IB_DAT<2>"), + PXA_FUNCTION(1, 1, "USB_P3_4")), + PXA_GPIO_PIN(PXA_PINCTRL_PIN(57), + PXA_FUNCTION(0, 1, "nIOS16"), + PXA_FUNCTION(0, 2, "BB_IB_DAT<3>"), + PXA_FUNCTION(1, 3, "SSPTXD")), + PXA_GPIO_PIN(PXA_PINCTRL_PIN(58), + PXA_FUNCTION(0, 2, "LDD<0>"), + PXA_FUNCTION(1, 2, "LDD<0>")), + PXA_GPIO_PIN(PXA_PINCTRL_PIN(59), + PXA_FUNCTION(0, 2, "LDD<1>"), + PXA_FUNCTION(1, 2, "LDD<1>")), + PXA_GPIO_PIN(PXA_PINCTRL_PIN(60), + PXA_FUNCTION(0, 2, "LDD<2>"), + PXA_FUNCTION(1, 2, "LDD<2>")), + PXA_GPIO_PIN(PXA_PINCTRL_PIN(61), + PXA_FUNCTION(0, 2, "LDD<3>"), + PXA_FUNCTION(1, 2, "LDD<3>")), + PXA_GPIO_PIN(PXA_PINCTRL_PIN(62), + PXA_FUNCTION(0, 2, "LDD<4>"), + PXA_FUNCTION(1, 2, "LDD<4>")), + PXA_GPIO_PIN(PXA_PINCTRL_PIN(63), + PXA_FUNCTION(0, 2, "LDD<5>"), + PXA_FUNCTION(1, 2, "LDD<5>")), + PXA_GPIO_PIN(PXA_PINCTRL_PIN(64), + PXA_FUNCTION(0, 2, "LDD<6>"), + PXA_FUNCTION(1, 2, "LDD<6>")), + PXA_GPIO_PIN(PXA_PINCTRL_PIN(65), + PXA_FUNCTION(0, 2, "LDD<7>"), + PXA_FUNCTION(1, 2, "LDD<7>")), + PXA_GPIO_PIN(PXA_PINCTRL_PIN(66), + PXA_FUNCTION(0, 2, "LDD<8>"), + PXA_FUNCTION(1, 2, "LDD<8>")), + PXA_GPIO_PIN(PXA_PINCTRL_PIN(67), + PXA_FUNCTION(0, 2, "LDD<9>"), + PXA_FUNCTION(1, 2, "LDD<9>")), + PXA_GPIO_PIN(PXA_PINCTRL_PIN(68), + PXA_FUNCTION(0, 2, "LDD<10>"), + PXA_FUNCTION(1, 2, "LDD<10>")), + PXA_GPIO_PIN(PXA_PINCTRL_PIN(69), + PXA_FUNCTION(0, 2, "LDD<11>"), + PXA_FUNCTION(1, 2, "LDD<11>")), + PXA_GPIO_PIN(PXA_PINCTRL_PIN(70), + PXA_FUNCTION(0, 2, "LDD<12>"), + PXA_FUNCTION(1, 2, "LDD<12>")), + PXA_GPIO_PIN(PXA_PINCTRL_PIN(71), + PXA_FUNCTION(0, 2, "LDD<13>"), + PXA_FUNCTION(1, 2, "LDD<13>")), + PXA_GPIO_PIN(PXA_PINCTRL_PIN(72), + PXA_FUNCTION(0, 2, "LDD<14>"), + PXA_FUNCTION(1, 2, "LDD<14>")), + PXA_GPIO_PIN(PXA_PINCTRL_PIN(73), + PXA_FUNCTION(0, 2, "LDD<15>"), + PXA_FUNCTION(1, 2, "LDD<15>")), + PXA_GPIO_PIN(PXA_PINCTRL_PIN(74), + PXA_FUNCTION(1, 2, "L_FCLK_RD")), + PXA_GPIO_PIN(PXA_PINCTRL_PIN(75), + PXA_FUNCTION(1, 2, "L_LCLK_A0")), + PXA_GPIO_PIN(PXA_PINCTRL_PIN(76), + PXA_FUNCTION(1, 2, "L_PCLK_WR")), + PXA_GPIO_PIN(PXA_PINCTRL_PIN(77), + PXA_FUNCTION(1, 2, "L_BIAS")), + PXA_GPIO_PIN(PXA_PINCTRL_PIN(78), + PXA_FUNCTION(1, 1, "nPCE<2>"), + PXA_FUNCTION(1, 2, "nCS<2>")), + PXA_GPIO_PIN(PXA_PINCTRL_PIN(79), + PXA_FUNCTION(1, 1, "PSKTSEL"), + PXA_FUNCTION(1, 2, "nCS<3>"), + PXA_FUNCTION(1, 3, "PWM_OUT<2>")), + PXA_GPIO_PIN(PXA_PINCTRL_PIN(80), + PXA_FUNCTION(0, 1, "DREQ<1>"), + PXA_FUNCTION(0, 2, "MBREQ"), + PXA_FUNCTION(1, 2, "nCS<4>"), + PXA_FUNCTION(1, 3, "PWM_OUT<3>")), + PXA_GPIO_PIN(PXA_PINCTRL_PIN(81), + PXA_FUNCTION(0, 2, "CIF_DD<0>"), + PXA_FUNCTION(1, 1, "SSPTXD3"), + PXA_FUNCTION(1, 2, "BB_OB_DAT<0>")), + PXA_GPIO_PIN(PXA_PINCTRL_PIN(82), + PXA_FUNCTION(0, 1, "SSPRXD3"), + PXA_FUNCTION(0, 2, "BB_IB_DAT<0>"), + PXA_FUNCTION(0, 3, "CIF_DD<5>"), + PXA_FUNCTION(1, 3, "FFDTR")), + PXA_GPIO_PIN(PXA_PINCTRL_PIN(83), + PXA_FUNCTION(0, 1, "SSPSFRM3"), + PXA_FUNCTION(0, 2, "BB_IB_CLK"), + PXA_FUNCTION(0, 3, "CIF_DD<5>"), + PXA_FUNCTION(1, 1, "SSPSFRM3"), + PXA_FUNCTION(1, 2, "FFTXD"), + PXA_FUNCTION(1, 3, "FFRTS")), + PXA_GPIO_PIN(PXA_PINCTRL_PIN(84), + PXA_FUNCTION(0, 1, "SSPCLK3"), + PXA_FUNCTION(0, 2, "BB_IB_STB"), + PXA_FUNCTION(0, 3, "CIF_FV"), + PXA_FUNCTION(1, 1, "SSPCLK3"), + PXA_FUNCTION(1, 3, "CIF_FV")), + PXA_GPIO_PIN(PXA_PINCTRL_PIN(85), + PXA_FUNCTION(0, 1, "FFRXD"), + PXA_FUNCTION(0, 2, "DREQ<2>"), + PXA_FUNCTION(0, 3, "CIF_LV"), + PXA_FUNCTION(1, 1, "nPCE<1>"), + PXA_FUNCTION(1, 2, "BB_IB_WAIT"), + PXA_FUNCTION(1, 3, "CIF_LV")), + PXA_GPIO_PIN(PXA_PINCTRL_PIN(86), + PXA_FUNCTION(0, 1, "SSPRXD2"), + PXA_FUNCTION(0, 2, "LDD<16>"), + PXA_FUNCTION(0, 3, "USB_P3_5"), + PXA_FUNCTION(1, 1, "nPCE<1>"), + PXA_FUNCTION(1, 2, "LDD<16>")), + PXA_GPIO_PIN(PXA_PINCTRL_PIN(87), + PXA_FUNCTION(0, 1, "nPCE<2>"), + PXA_FUNCTION(0, 2, "LDD<17>"), + PXA_FUNCTION(0, 3, "USB_P3_1"), + PXA_FUNCTION(1, 1, "SSPTXD2"), + PXA_FUNCTION(1, 2, "LDD<17>"), + PXA_FUNCTION(1, 3, "SSPSFRM2")), + PXA_GPIO_PIN(PXA_PINCTRL_PIN(88), + PXA_FUNCTION(0, 1, "USBHPWR<1>"), + PXA_FUNCTION(0, 2, "SSPRXD2"), + PXA_FUNCTION(0, 3, "SSPSFRM2"), + PXA_FUNCTION(1, 2, "SSPTXD2"), + PXA_FUNCTION(1, 3, "SSPSFRM2")), + PXA_GPIO_PIN(PXA_PINCTRL_PIN(89), + PXA_FUNCTION(0, 1, "SSPRXD3"), + PXA_FUNCTION(0, 3, "FFRI"), + PXA_FUNCTION(1, 1, "AC97_SYSCLK"), + PXA_FUNCTION(1, 2, "USBHPEN<1>"), + PXA_FUNCTION(1, 3, "SSPTXD2")), + PXA_GPIO_PIN(PXA_PINCTRL_PIN(90), + PXA_FUNCTION(0, 1, "KP_MKIN<5>"), + PXA_FUNCTION(0, 3, "USB_P3_5"), + PXA_FUNCTION(1, 1, "CIF_DD<4>"), + PXA_FUNCTION(1, 2, "nURST")), + PXA_GPIO_PIN(PXA_PINCTRL_PIN(91), + PXA_FUNCTION(0, 1, "KP_MKIN<6>"), + PXA_FUNCTION(0, 3, "USB_P3_1"), + PXA_FUNCTION(1, 1, "CIF_DD<5>"), + PXA_FUNCTION(1, 2, "UCLK")), + PXA_GPIO_PIN(PXA_PINCTRL_PIN(92), + PXA_FUNCTION(0, 1, "MMDAT<0>"), + PXA_FUNCTION(1, 1, "MMDAT<0>"), + PXA_FUNCTION(1, 2, "MSBS")), + PXA_GPIO_PIN(PXA_PINCTRL_PIN(93), + PXA_FUNCTION(0, 1, "KP_DKIN<0>"), + PXA_FUNCTION(0, 2, "CIF_DD<6>"), + PXA_FUNCTION(1, 1, "AC97_SDATA_OUT")), + PXA_GPIO_PIN(PXA_PINCTRL_PIN(94), + PXA_FUNCTION(0, 1, "KP_DKIN<1>"), + PXA_FUNCTION(0, 2, "CIF_DD<5>"), + PXA_FUNCTION(1, 1, "AC97_SYNC")), + PXA_GPIO_PIN(PXA_PINCTRL_PIN(95), + PXA_FUNCTION(0, 1, "KP_DKIN<2>"), + PXA_FUNCTION(0, 2, "CIF_DD<4>"), + PXA_FUNCTION(0, 3, "KP_MKIN<6>"), + PXA_FUNCTION(1, 1, "AC97_RESET_n")), + PXA_GPIO_PIN(PXA_PINCTRL_PIN(96), + PXA_FUNCTION(0, 1, "KP_DKIN<3>"), + PXA_FUNCTION(0, 2, "MBREQ"), + PXA_FUNCTION(0, 3, "FFRXD"), + PXA_FUNCTION(1, 2, "DVAL<1>"), + PXA_FUNCTION(1, 3, "KP_MKOUT<6>")), + PXA_GPIO_PIN(PXA_PINCTRL_PIN(97), + PXA_FUNCTION(0, 1, "KP_DKIN<4>"), + PXA_FUNCTION(0, 2, "DREQ<1>"), + PXA_FUNCTION(0, 3, "KP_MKIN<3>"), + PXA_FUNCTION(1, 2, "MBGNT")), + PXA_GPIO_PIN(PXA_PINCTRL_PIN(98), + PXA_FUNCTION(0, 1, "KP_DKIN<5>"), + PXA_FUNCTION(0, 2, "CIF_DD<0>"), + PXA_FUNCTION(0, 3, "KP_MKIN<4>"), + PXA_FUNCTION(1, 1, "AC97_SYSCLK"), + PXA_FUNCTION(1, 3, "FFRTS")), + PXA_GPIO_PIN(PXA_PINCTRL_PIN(99), + PXA_FUNCTION(0, 1, "KP_DKIN<6>"), + PXA_FUNCTION(0, 2, "AC97_SDATA_IN_1"), + PXA_FUNCTION(0, 3, "KP_MKIN<5>"), + PXA_FUNCTION(1, 3, "FFTXD")), + PXA_GPIO_PIN(PXA_PINCTRL_PIN(100), + PXA_FUNCTION(0, 1, "KP_MKIN<0>"), + PXA_FUNCTION(0, 2, "DREQ<2>"), + PXA_FUNCTION(0, 3, "FFCTS")), + PXA_GPIO_PIN(PXA_PINCTRL_PIN(101), + PXA_FUNCTION(0, 1, "KP_MKIN<1>")), + PXA_GPIO_PIN(PXA_PINCTRL_PIN(102), + PXA_FUNCTION(0, 1, "KP_MKIN<2>"), + PXA_FUNCTION(0, 3, "FFRXD"), + PXA_FUNCTION(1, 1, "nPCE<1>")), + PXA_GPIO_PIN(PXA_PINCTRL_PIN(103), + PXA_FUNCTION(0, 1, "CIF_DD<3>"), + PXA_FUNCTION(1, 2, "KP_MKOUT<0>")), + PXA_GPIO_PIN(PXA_PINCTRL_PIN(104), + PXA_FUNCTION(0, 1, "CIF_DD<2>"), + PXA_FUNCTION(1, 1, "PSKTSEL"), + PXA_FUNCTION(1, 2, "KP_MKOUT<1>")), + PXA_GPIO_PIN(PXA_PINCTRL_PIN(105), + PXA_FUNCTION(0, 1, "CIF_DD<1>"), + PXA_FUNCTION(1, 1, "nPCE<2>"), + PXA_FUNCTION(1, 2, "KP_MKOUT<2>")), + PXA_GPIO_PIN(PXA_PINCTRL_PIN(106), + PXA_FUNCTION(0, 1, "CIF_DD<9>"), + PXA_FUNCTION(1, 2, "KP_MKOUT<3>")), + PXA_GPIO_PIN(PXA_PINCTRL_PIN(107), + PXA_FUNCTION(0, 1, "CIF_DD<8>"), + PXA_FUNCTION(1, 2, "KP_MKOUT<4>")), + PXA_GPIO_PIN(PXA_PINCTRL_PIN(108), + PXA_FUNCTION(0, 1, "CIF_DD<7>"), + PXA_FUNCTION(1, 1, "CHOUT<0>"), + PXA_FUNCTION(1, 2, "KP_MKOUT<5>")), + PXA_GPIO_PIN(PXA_PINCTRL_PIN(109), + PXA_FUNCTION(0, 1, "MMDAT<1>"), + PXA_FUNCTION(0, 2, "MSSDIO"), + PXA_FUNCTION(1, 1, "MMDAT<1>"), + PXA_FUNCTION(1, 2, "MSSDIO")), + PXA_GPIO_PIN(PXA_PINCTRL_PIN(110), + PXA_FUNCTION(0, 1, "MMDAT<2>"), + PXA_FUNCTION(1, 1, "MMDAT<2>")), + PXA_GPIO_PIN(PXA_PINCTRL_PIN(111), + PXA_FUNCTION(0, 1, "MMDAT<3>"), + PXA_FUNCTION(1, 1, "MMDAT<3>")), + PXA_GPIO_PIN(PXA_PINCTRL_PIN(112), + PXA_FUNCTION(0, 1, "MMCMD"), + PXA_FUNCTION(0, 2, "nMSINS"), + PXA_FUNCTION(1, 1, "MMCMD")), + PXA_GPIO_PIN(PXA_PINCTRL_PIN(113), + PXA_FUNCTION(0, 3, "USB_P3_3"), + PXA_FUNCTION(1, 1, "I2S_SYSCLK"), + PXA_FUNCTION(1, 2, "AC97_RESET_n")), + PXA_GPIO_PIN(PXA_PINCTRL_PIN(114), + PXA_FUNCTION(0, 1, "CIF_DD<1>"), + PXA_FUNCTION(1, 1, "UEN"), + PXA_FUNCTION(1, 2, "UVS0")), + PXA_GPIO_PIN(PXA_PINCTRL_PIN(115), + PXA_FUNCTION(0, 1, "DREQ<0>"), + PXA_FUNCTION(0, 2, "CIF_DD<3>"), + PXA_FUNCTION(0, 3, "MBREQ"), + PXA_FUNCTION(1, 1, "UEN"), + PXA_FUNCTION(1, 2, "nUVS1"), + PXA_FUNCTION(1, 3, "PWM_OUT<1>")), + PXA_GPIO_PIN(PXA_PINCTRL_PIN(116), + PXA_FUNCTION(0, 1, "CIF_DD<2>"), + PXA_FUNCTION(0, 2, "AC97_SDATA_IN_0"), + PXA_FUNCTION(0, 3, "UDET"), + PXA_FUNCTION(1, 1, "DVAL<0>"), + PXA_FUNCTION(1, 2, "nUVS2"), + PXA_FUNCTION(1, 3, "MBGNT")), + PXA_GPIO_PIN(PXA_PINCTRL_PIN(117), + PXA_FUNCTION(0, 1, "SCL"), + PXA_FUNCTION(1, 1, "SCL")), + PXA_GPIO_PIN(PXA_PINCTRL_PIN(118), + PXA_FUNCTION(0, 1, "SDA"), + PXA_FUNCTION(1, 1, "SDA")), + PXA_GPIO_PIN(PXA_PINCTRL_PIN(119), + PXA_FUNCTION(0, 1, "USBHPWR<2>")), + PXA_GPIO_PIN(PXA_PINCTRL_PIN(120), + PXA_FUNCTION(1, 2, "USBHPEN<2>")), +}; + +static int pxa27x_pinctrl_probe(struct platform_device *pdev) +{ + int ret, i; + void __iomem *base_af[8]; + void __iomem *base_dir[4]; + void __iomem *base_sleep[4]; + struct resource *res; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + base_af[0] = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(base_af[0])) + return PTR_ERR(base_af[0]); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 1); + base_dir[0] = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(base_dir[0])) + return PTR_ERR(base_dir[0]); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 2); + base_dir[3] = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(base_dir[3])) + return PTR_ERR(base_dir[3]); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 3); + base_sleep[0] = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(base_sleep[0])) + return PTR_ERR(base_sleep[0]); + + for (i = 0; i < ARRAY_SIZE(base_af); i++) + base_af[i] = base_af[0] + sizeof(base_af[0]) * i; + for (i = 0; i < 3; i++) + base_dir[i] = base_dir[0] + sizeof(base_dir[0]) * i; + for (i = 0; i < ARRAY_SIZE(base_sleep); i++) + base_sleep[i] = base_sleep[0] + sizeof(base_af[0]) * i; + + ret = pxa2xx_pinctrl_init(pdev, pxa27x_pins, ARRAY_SIZE(pxa27x_pins), + base_af, base_dir, base_sleep); + return ret; +} + +static const struct of_device_id pxa27x_pinctrl_match[] = { + { .compatible = "marvell,pxa27x-pinctrl", }, + {} +}; +MODULE_DEVICE_TABLE(of, pxa27x_pinctrl_match); + +static struct platform_driver pxa27x_pinctrl_driver = { + .probe = pxa27x_pinctrl_probe, + .driver = { + .name = "pxa27x-pinctrl", + .of_match_table = pxa27x_pinctrl_match, + }, +}; +module_platform_driver(pxa27x_pinctrl_driver); + +MODULE_AUTHOR("Robert Jarzmik "); +MODULE_DESCRIPTION("Marvell PXA27x pinctrl driver"); +MODULE_LICENSE("GPL v2"); -- cgit v0.10.2 From 4b15ec9d42b2004d7114e6714a27b60ba4f27b57 Mon Sep 17 00:00:00 2001 From: Robert Jarzmik Date: Sat, 21 Nov 2015 19:04:53 +0100 Subject: pinctrl: activate pxa architecture As the pxa architecture, at least for pxa27x, supports pin control, activate it in the pinctrl tree. Signed-off-by: Robert Jarzmik Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index eb434d4..2b80a79 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -254,6 +254,7 @@ source "drivers/pinctrl/freescale/Kconfig" source "drivers/pinctrl/intel/Kconfig" source "drivers/pinctrl/mvebu/Kconfig" source "drivers/pinctrl/nomadik/Kconfig" +source "drivers/pinctrl/pxa/Kconfig" source "drivers/pinctrl/qcom/Kconfig" source "drivers/pinctrl/samsung/Kconfig" source "drivers/pinctrl/sh-pfc/Kconfig" diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index 22a02f3..bf1b5ca 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -46,6 +46,7 @@ obj-y += freescale/ obj-$(CONFIG_X86) += intel/ obj-$(CONFIG_PINCTRL_MVEBU) += mvebu/ obj-y += nomadik/ +obj-$(CONFIG_ARCH_PXA) += pxa/ obj-$(CONFIG_ARCH_QCOM) += qcom/ obj-$(CONFIG_PINCTRL_SAMSUNG) += samsung/ obj-$(CONFIG_PINCTRL_SH_PFC) += sh-pfc/ -- cgit v0.10.2 From 80d71b616d7294ad65c4b4cf43dd734bc82b4fcf Mon Sep 17 00:00:00 2001 From: Wei Chen Date: Mon, 30 Nov 2015 06:05:53 +0000 Subject: pinctrl: atlas7: add cs line for atlas7 nand The nand in atlas7 has two chip select line. But in most time, the nand only has one chip, so only one chip select line is enough. The nand driver select this new pin group can free one chip select line for other modules to avoid pin conflict. Signed-off-by: Wei Chen Signed-off-by: Barry Song Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/sirf/pinctrl-atlas7.c b/drivers/pinctrl/sirf/pinctrl-atlas7.c index 829018c..30db524 100644 --- a/drivers/pinctrl/sirf/pinctrl-atlas7.c +++ b/drivers/pinctrl/sirf/pinctrl-atlas7.c @@ -889,6 +889,8 @@ static const unsigned int nd_df_pins[] = { 44, 43, 42, 41, 40, 39, 38, 37, 47, 46, 52, 51, 45, 49, 50, 48, 124, }; static const unsigned int nd_df_nowp_pins[] = { 44, 43, 42, 41, 40, 39, 38, 37, 47, 46, 52, 51, 45, 49, 50, 48, }; +static const unsigned int nd_df_nocs_pins[] = { 44, 43, 42, 41, 40, 39, 38, + 37, 47, 46, 52, 45, 49, 50, 48, 124, }; static const unsigned int ps_pins[] = { 120, 119, 121, }; static const unsigned int pwc_core_on_pins[] = { 8, }; static const unsigned int pwc_ext_on_pins[] = { 6, }; @@ -1144,6 +1146,7 @@ struct atlas7_pin_group altas7_pin_groups[] = { GROUP("lvds_analog_grp", lvds_analog_pins), GROUP("nd_df_grp", nd_df_pins), GROUP("nd_df_nowp_grp", nd_df_nowp_pins), + GROUP("nd_df_nocs_grp", nd_df_nocs_pins), GROUP("ps_grp", ps_pins), GROUP("pwc_core_on_grp", pwc_core_on_pins), GROUP("pwc_ext_on_grp", pwc_ext_on_pins), @@ -1423,6 +1426,7 @@ static const char * const lr_lcdrom_grp[] = { "lr_lcdrom_grp", }; static const char * const lvds_analog_grp[] = { "lvds_analog_grp", }; static const char * const nd_df_grp[] = { "nd_df_grp", }; static const char * const nd_df_nowp_grp[] = { "nd_df_nowp_grp", }; +static const char * const nd_df_nocs_grp[] = { "nd_df_nocs_grp", }; static const char * const ps_grp[] = { "ps_grp", }; static const char * const pwc_core_on_grp[] = { "pwc_core_on_grp", }; static const char * const pwc_ext_on_grp[] = { "pwc_ext_on_grp", }; @@ -3223,6 +3227,30 @@ static struct atlas7_grp_mux nd_df_nowp_grp_mux = { .pad_mux_list = nd_df_nowp_grp_pad_mux, }; +static struct atlas7_pad_mux nd_df_nocs_grp_pad_mux[] = { + MUX(1, 44, 1, N, N, N, N), + MUX(1, 43, 1, N, N, N, N), + MUX(1, 42, 1, N, N, N, N), + MUX(1, 41, 1, N, N, N, N), + MUX(1, 40, 1, N, N, N, N), + MUX(1, 39, 1, N, N, N, N), + MUX(1, 38, 1, N, N, N, N), + MUX(1, 37, 1, N, N, N, N), + MUX(1, 47, 1, N, N, N, N), + MUX(1, 46, 1, N, N, N, N), + MUX(1, 52, 1, N, N, N, N), + MUX(1, 45, 1, N, N, N, N), + MUX(1, 49, 1, N, N, N, N), + MUX(1, 50, 1, N, N, N, N), + MUX(1, 48, 1, N, N, N, N), + MUX(1, 124, 4, N, N, N, N), +}; + +static struct atlas7_grp_mux nd_df_nocs_grp_mux = { + .pad_mux_count = ARRAY_SIZE(nd_df_nocs_grp_pad_mux), + .pad_mux_list = nd_df_nocs_grp_pad_mux, +}; + static struct atlas7_pad_mux ps_grp_pad_mux[] = { MUX(1, 120, 2, N, N, N, N), MUX(1, 119, 2, N, N, N, N), @@ -4600,6 +4628,7 @@ static struct atlas7_pmx_func atlas7_pmx_functions[] = { FUNCTION("lvds_analog", lvds_analog_grp, &lvds_analog_grp_mux), FUNCTION("nd_df", nd_df_grp, &nd_df_grp_mux), FUNCTION("nd_df_nowp", nd_df_nowp_grp, &nd_df_nowp_grp_mux), + FUNCTION("nd_df_nocs", nd_df_nocs_grp, &nd_df_nocs_grp_mux), FUNCTION("ps", ps_grp, &ps_grp_mux), FUNCTION("pwc_core_on", pwc_core_on_grp, &pwc_core_on_grp_mux), FUNCTION("pwc_ext_on", pwc_ext_on_grp, &pwc_ext_on_grp_mux), -- cgit v0.10.2 From 6d985333a1e05ba6b8cdd6f6f4e08992a06e9bc0 Mon Sep 17 00:00:00 2001 From: Yonghui Zhang Date: Mon, 30 Nov 2015 06:05:54 +0000 Subject: pinctrl: altas7: add sd9 function mux support The sd9 pin mux with sd3 and it is selected by SYS2PCI_SDIO9SEL. This makes the codes ugly since the register is not in pinctrl module. Signed-off-by: Yonghui Zhang Signed-off-by: Barry Song Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/sirf/pinctrl-atlas7.c b/drivers/pinctrl/sirf/pinctrl-atlas7.c index 30db524..47c63c5 100644 --- a/drivers/pinctrl/sirf/pinctrl-atlas7.c +++ b/drivers/pinctrl/sirf/pinctrl-atlas7.c @@ -161,6 +161,9 @@ enum altas7_pad_type { #define IN_DISABLE_VAL_1_REG_SET 0x0A88 #define IN_DISABLE_VAL_1_REG_CLR 0x0A8C +/* Offset of the SDIO9SEL*/ +#define SYS2PCI_SDIO9SEL 0x14 + struct dt_params { const char *property; int value; @@ -370,6 +373,7 @@ struct atlas7_pmx { struct pinctrl_desc pctl_desc; struct atlas7_pinctrl_data *pctl_data; void __iomem *regs[ATLAS7_PINCTRL_REG_BANKS]; + void __iomem *sys2pci_base; u32 status_ds[NUM_OF_IN_DISABLE_REG]; u32 status_dsv[NUM_OF_IN_DISABLE_REG]; struct atlas7_pad_status sleep_data[ATLAS7_PINCTRL_TOTAL_PINS]; @@ -946,7 +950,7 @@ static const unsigned int sd2_cdb_pins0[] = { 124, }; static const unsigned int sd2_cdb_pins1[] = { 161, }; static const unsigned int sd2_wpb_pins0[] = { 123, }; static const unsigned int sd2_wpb_pins1[] = { 163, }; -static const unsigned int sd3_pins[] = { 85, 86, 87, 88, 89, 90, }; +static const unsigned int sd3_9_pins[] = { 85, 86, 87, 88, 89, 90, }; static const unsigned int sd5_pins[] = { 91, 92, 93, 94, 95, 96, }; static const unsigned int sd6_pins0[] = { 79, 78, 74, 75, 76, 77, }; static const unsigned int sd6_pins1[] = { 101, 99, 100, 110, 109, 111, }; @@ -1199,7 +1203,7 @@ struct atlas7_pin_group altas7_pin_groups[] = { GROUP("sd2_cdb_grp1", sd2_cdb_pins1), GROUP("sd2_wpb_grp0", sd2_wpb_pins0), GROUP("sd2_wpb_grp1", sd2_wpb_pins1), - GROUP("sd3_grp", sd3_pins), + GROUP("sd3_9_grp", sd3_9_pins), GROUP("sd5_grp", sd5_pins), GROUP("sd6_grp0", sd6_pins0), GROUP("sd6_grp1", sd6_pins1), @@ -1482,7 +1486,7 @@ static const char * const sd2_cdb_grp0[] = { "sd2_cdb_grp0", }; static const char * const sd2_cdb_grp1[] = { "sd2_cdb_grp1", }; static const char * const sd2_wpb_grp0[] = { "sd2_wpb_grp0", }; static const char * const sd2_wpb_grp1[] = { "sd2_wpb_grp1", }; -static const char * const sd3_grp[] = { "sd3_grp", }; +static const char * const sd3_9_grp[] = { "sd3_9_grp", }; static const char * const sd5_grp[] = { "sd5_grp", }; static const char * const sd6_grp0[] = { "sd6_grp0", }; static const char * const sd6_grp1[] = { "sd6_grp1", }; @@ -3771,7 +3775,7 @@ static struct atlas7_grp_mux sd2_wpb_grp1_mux = { .pad_mux_list = sd2_wpb_grp1_pad_mux, }; -static struct atlas7_pad_mux sd3_grp_pad_mux[] = { +static struct atlas7_pad_mux sd3_9_grp_pad_mux[] = { MUX(1, 85, 1, N, N, N, N), MUX(1, 86, 1, N, N, N, N), MUX(1, 87, 1, N, N, N, N), @@ -3780,9 +3784,9 @@ static struct atlas7_pad_mux sd3_grp_pad_mux[] = { MUX(1, 90, 1, N, N, N, N), }; -static struct atlas7_grp_mux sd3_grp_mux = { - .pad_mux_count = ARRAY_SIZE(sd3_grp_pad_mux), - .pad_mux_list = sd3_grp_pad_mux, +static struct atlas7_grp_mux sd3_9_grp_mux = { + .pad_mux_count = ARRAY_SIZE(sd3_9_grp_pad_mux), + .pad_mux_list = sd3_9_grp_pad_mux, }; static struct atlas7_pad_mux sd5_grp_pad_mux[] = { @@ -4715,10 +4719,11 @@ static struct atlas7_pmx_func atlas7_pmx_functions[] = { FUNCTION("sd2_cdb_m1", sd2_cdb_grp1, &sd2_cdb_grp1_mux), FUNCTION("sd2_wpb_m0", sd2_wpb_grp0, &sd2_wpb_grp0_mux), FUNCTION("sd2_wpb_m1", sd2_wpb_grp1, &sd2_wpb_grp1_mux), - FUNCTION("sd3", sd3_grp, &sd3_grp_mux), + FUNCTION("sd3", sd3_9_grp, &sd3_9_grp_mux), FUNCTION("sd5", sd5_grp, &sd5_grp_mux), FUNCTION("sd6_m0", sd6_grp0, &sd6_grp0_mux), FUNCTION("sd6_m1", sd6_grp1, &sd6_grp1_mux), + FUNCTION("sd9", sd3_9_grp, &sd3_9_grp_mux), FUNCTION("sp0_ext_ldo_on", sp0_ext_ldo_on_grp, &sp0_ext_ldo_on_grp_mux), @@ -5126,6 +5131,14 @@ static int atlas7_pmx_set_mux(struct pinctrl_dev *pctldev, pr_debug("PMX DUMP ### Function:[%s] Group:[%s] #### START >>>\n", pmx_func->name, pin_grp->name); + /* the sd3 and sd9 pin select by SYS2PCI_SDIO9SEL register */ + if (pin_grp->pins == (unsigned int *)&sd3_9_pins) { + if (!strcmp(pmx_func->name, "sd9")) + writel(1, pmx->sys2pci_base + SYS2PCI_SDIO9SEL); + else + writel(0, pmx->sys2pci_base + SYS2PCI_SDIO9SEL); + } + grp_mux = pmx_func->grpmux; for (idx = 0; idx < grp_mux->pad_mux_count; idx++) { @@ -5414,12 +5427,27 @@ static int atlas7_pinmux_probe(struct platform_device *pdev) struct atlas7_pmx *pmx; struct device_node *np = pdev->dev.of_node; u32 banks = ATLAS7_PINCTRL_REG_BANKS; + struct device_node *sys2pci_np; + struct resource res; /* Create state holders etc for this driver */ pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL); if (!pmx) return -ENOMEM; + /* The sd3 and sd9 shared all pins, and the function select by + * SYS2PCI_SDIO9SEL register + */ + sys2pci_np = of_find_node_by_name(NULL, "sys2pci"); + if (!sys2pci_np) + return -EINVAL; + ret = of_address_to_resource(sys2pci_np, 0, &res); + if (ret) + return ret; + pmx->sys2pci_base = devm_ioremap_resource(&pdev->dev, &res); + if (IS_ERR(pmx->sys2pci_base)) + return -ENOMEM; + pmx->dev = &pdev->dev; pmx->pctl_data = &atlas7_ioc_data; -- cgit v0.10.2 From d166629cdf73a60f5fe8646bfe96dfd39c5ba660 Mon Sep 17 00:00:00 2001 From: Wei Chen Date: Mon, 30 Nov 2015 06:05:55 +0000 Subject: pinctrl: atlas7: adjust pin groups of atlas7 nanddisk Remove write-protect and chip-selector pins from nand pin group. And then create two separate pin groups for these two pin. So the nand driver can choose correct pin groups as board desgin: For example: 1. nand without wp&cs: nand@17050000 { pinctrl-0 = <&nd_df_basic_pmx>; }; 2. nand with wp nand@17050000 { pinctrl-0 = <&nd_df_basic_pmx &nd_df_wp_pmx>; }; 3. nand with cs: nand@17050000 { pinctrl-0 = <&nd_df_basic_pmx &nd_df_cs_pmx>; }; 4. nand with wp&cs: nand@17050000 { pinctrl-0 = <&nd_df_basic_pmx &nd_df_wp_pmx &nd_df_cs_pmx>; }; Signed-off-by: Wei Chen Signed-off-by: Barry Song Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/sirf/pinctrl-atlas7.c b/drivers/pinctrl/sirf/pinctrl-atlas7.c index 47c63c5..f73eff5 100644 --- a/drivers/pinctrl/sirf/pinctrl-atlas7.c +++ b/drivers/pinctrl/sirf/pinctrl-atlas7.c @@ -889,12 +889,10 @@ static const unsigned int lr_lcdrom_pins[] = { 73, 54, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 56, 53, 55, }; static const unsigned int lvds_analog_pins[] = { 149, 150, 151, 152, 153, 154, 155, 156, 157, 158, }; -static const unsigned int nd_df_pins[] = { 44, 43, 42, 41, 40, 39, 38, 37, - 47, 46, 52, 51, 45, 49, 50, 48, 124, }; -static const unsigned int nd_df_nowp_pins[] = { 44, 43, 42, 41, 40, 39, 38, - 37, 47, 46, 52, 51, 45, 49, 50, 48, }; -static const unsigned int nd_df_nocs_pins[] = { 44, 43, 42, 41, 40, 39, 38, - 37, 47, 46, 52, 45, 49, 50, 48, 124, }; +static const unsigned int nd_df_basic_pins[] = { 44, 43, 42, 41, 40, 39, 38, + 37, 47, 46, 52, 45, 49, 50, 48, }; +static const unsigned int nd_df_wp_pins[] = { 124, }; +static const unsigned int nd_df_cs_pins[] = { 51, }; static const unsigned int ps_pins[] = { 120, 119, 121, }; static const unsigned int pwc_core_on_pins[] = { 8, }; static const unsigned int pwc_ext_on_pins[] = { 6, }; @@ -1148,9 +1146,9 @@ struct atlas7_pin_group altas7_pin_groups[] = { GROUP("ld_ldd_lck_grp", ld_ldd_lck_pins), GROUP("lr_lcdrom_grp", lr_lcdrom_pins), GROUP("lvds_analog_grp", lvds_analog_pins), - GROUP("nd_df_grp", nd_df_pins), - GROUP("nd_df_nowp_grp", nd_df_nowp_pins), - GROUP("nd_df_nocs_grp", nd_df_nocs_pins), + GROUP("nd_df_basic_grp", nd_df_basic_pins), + GROUP("nd_df_wp_grp", nd_df_wp_pins), + GROUP("nd_df_cs_grp", nd_df_cs_pins), GROUP("ps_grp", ps_pins), GROUP("pwc_core_on_grp", pwc_core_on_pins), GROUP("pwc_ext_on_grp", pwc_ext_on_pins), @@ -1428,9 +1426,9 @@ static const char * const ld_ldd_fck_grp[] = { "ld_ldd_fck_grp", }; static const char * const ld_ldd_lck_grp[] = { "ld_ldd_lck_grp", }; static const char * const lr_lcdrom_grp[] = { "lr_lcdrom_grp", }; static const char * const lvds_analog_grp[] = { "lvds_analog_grp", }; -static const char * const nd_df_grp[] = { "nd_df_grp", }; -static const char * const nd_df_nowp_grp[] = { "nd_df_nowp_grp", }; -static const char * const nd_df_nocs_grp[] = { "nd_df_nocs_grp", }; +static const char * const nd_df_basic_grp[] = { "nd_df_basic_grp", }; +static const char * const nd_df_wp_grp[] = { "nd_df_wp_grp", }; +static const char * const nd_df_cs_grp[] = { "nd_df_cs_grp", }; static const char * const ps_grp[] = { "ps_grp", }; static const char * const pwc_core_on_grp[] = { "pwc_core_on_grp", }; static const char * const pwc_ext_on_grp[] = { "pwc_ext_on_grp", }; @@ -3182,7 +3180,7 @@ static struct atlas7_grp_mux lvds_analog_grp_mux = { .pad_mux_list = lvds_analog_grp_pad_mux, }; -static struct atlas7_pad_mux nd_df_grp_pad_mux[] = { +static struct atlas7_pad_mux nd_df_basic_grp_pad_mux[] = { MUX(1, 44, 1, N, N, N, N), MUX(1, 43, 1, N, N, N, N), MUX(1, 42, 1, N, N, N, N), @@ -3194,65 +3192,33 @@ static struct atlas7_pad_mux nd_df_grp_pad_mux[] = { MUX(1, 47, 1, N, N, N, N), MUX(1, 46, 1, N, N, N, N), MUX(1, 52, 1, N, N, N, N), - MUX(1, 51, 1, N, N, N, N), MUX(1, 45, 1, N, N, N, N), MUX(1, 49, 1, N, N, N, N), MUX(1, 50, 1, N, N, N, N), MUX(1, 48, 1, N, N, N, N), - MUX(1, 124, 4, N, N, N, N), }; -static struct atlas7_grp_mux nd_df_grp_mux = { - .pad_mux_count = ARRAY_SIZE(nd_df_grp_pad_mux), - .pad_mux_list = nd_df_grp_pad_mux, +static struct atlas7_grp_mux nd_df_basic_grp_mux = { + .pad_mux_count = ARRAY_SIZE(nd_df_basic_grp_pad_mux), + .pad_mux_list = nd_df_basic_grp_pad_mux, }; -static struct atlas7_pad_mux nd_df_nowp_grp_pad_mux[] = { - MUX(1, 44, 1, N, N, N, N), - MUX(1, 43, 1, N, N, N, N), - MUX(1, 42, 1, N, N, N, N), - MUX(1, 41, 1, N, N, N, N), - MUX(1, 40, 1, N, N, N, N), - MUX(1, 39, 1, N, N, N, N), - MUX(1, 38, 1, N, N, N, N), - MUX(1, 37, 1, N, N, N, N), - MUX(1, 47, 1, N, N, N, N), - MUX(1, 46, 1, N, N, N, N), - MUX(1, 52, 1, N, N, N, N), - MUX(1, 51, 1, N, N, N, N), - MUX(1, 45, 1, N, N, N, N), - MUX(1, 49, 1, N, N, N, N), - MUX(1, 50, 1, N, N, N, N), - MUX(1, 48, 1, N, N, N, N), +static struct atlas7_pad_mux nd_df_wp_grp_pad_mux[] = { + MUX(1, 124, 4, N, N, N, N), }; -static struct atlas7_grp_mux nd_df_nowp_grp_mux = { - .pad_mux_count = ARRAY_SIZE(nd_df_nowp_grp_pad_mux), - .pad_mux_list = nd_df_nowp_grp_pad_mux, +static struct atlas7_grp_mux nd_df_wp_grp_mux = { + .pad_mux_count = ARRAY_SIZE(nd_df_wp_grp_pad_mux), + .pad_mux_list = nd_df_wp_grp_pad_mux, }; -static struct atlas7_pad_mux nd_df_nocs_grp_pad_mux[] = { - MUX(1, 44, 1, N, N, N, N), - MUX(1, 43, 1, N, N, N, N), - MUX(1, 42, 1, N, N, N, N), - MUX(1, 41, 1, N, N, N, N), - MUX(1, 40, 1, N, N, N, N), - MUX(1, 39, 1, N, N, N, N), - MUX(1, 38, 1, N, N, N, N), - MUX(1, 37, 1, N, N, N, N), - MUX(1, 47, 1, N, N, N, N), - MUX(1, 46, 1, N, N, N, N), - MUX(1, 52, 1, N, N, N, N), - MUX(1, 45, 1, N, N, N, N), - MUX(1, 49, 1, N, N, N, N), - MUX(1, 50, 1, N, N, N, N), - MUX(1, 48, 1, N, N, N, N), - MUX(1, 124, 4, N, N, N, N), +static struct atlas7_pad_mux nd_df_cs_grp_pad_mux[] = { + MUX(1, 51, 1, N, N, N, N), }; -static struct atlas7_grp_mux nd_df_nocs_grp_mux = { - .pad_mux_count = ARRAY_SIZE(nd_df_nocs_grp_pad_mux), - .pad_mux_list = nd_df_nocs_grp_pad_mux, +static struct atlas7_grp_mux nd_df_cs_grp_mux = { + .pad_mux_count = ARRAY_SIZE(nd_df_cs_grp_pad_mux), + .pad_mux_list = nd_df_cs_grp_pad_mux, }; static struct atlas7_pad_mux ps_grp_pad_mux[] = { @@ -4630,9 +4596,9 @@ static struct atlas7_pmx_func atlas7_pmx_functions[] = { FUNCTION("ld_ldd_lck", ld_ldd_lck_grp, &ld_ldd_lck_grp_mux), FUNCTION("lr_lcdrom", lr_lcdrom_grp, &lr_lcdrom_grp_mux), FUNCTION("lvds_analog", lvds_analog_grp, &lvds_analog_grp_mux), - FUNCTION("nd_df", nd_df_grp, &nd_df_grp_mux), - FUNCTION("nd_df_nowp", nd_df_nowp_grp, &nd_df_nowp_grp_mux), - FUNCTION("nd_df_nocs", nd_df_nocs_grp, &nd_df_nocs_grp_mux), + FUNCTION("nd_df_basic", nd_df_basic_grp, &nd_df_basic_grp_mux), + FUNCTION("nd_df_wp", nd_df_wp_grp, &nd_df_wp_grp_mux), + FUNCTION("nd_df_cs", nd_df_cs_grp, &nd_df_cs_grp_mux), FUNCTION("ps", ps_grp, &ps_grp_mux), FUNCTION("pwc_core_on", pwc_core_on_grp, &pwc_core_on_grp_mux), FUNCTION("pwc_ext_on", pwc_ext_on_grp, &pwc_ext_on_grp_mux), -- cgit v0.10.2 From 5238bba81f6ccd17ce0ddf7df393d9c5d4f1b307 Mon Sep 17 00:00:00 2001 From: Wei Chen Date: Mon, 30 Nov 2015 06:05:56 +0000 Subject: pinctrl: atlas7: adjust vip pin groups for atlas7 The vip low 8bit mode and vip high 8 bit mode pin groups had missed 3 pins:vip_vsync, vip_hsync and vip_pxclk. Without these 3 pins, the vip could not work properly. Now we add these 3 pins into these two pin groups. Signed-off-by: Wei Chen Signed-off-by: Barry Song Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/sirf/pinctrl-atlas7.c b/drivers/pinctrl/sirf/pinctrl-atlas7.c index f73eff5..fc9c3f7 100644 --- a/drivers/pinctrl/sirf/pinctrl-atlas7.c +++ b/drivers/pinctrl/sirf/pinctrl-atlas7.c @@ -1002,9 +1002,9 @@ static const unsigned int vi_vip1_ext_pins[] = { 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 108, 103, 104, 105, 106, 107, 102, 97, 98, 99, 100, }; static const unsigned int vi_vip1_low8bit_pins[] = { 74, 75, 76, 77, 78, 79, - 80, 81, }; -static const unsigned int vi_vip1_high8bit_pins[] = { 82, 83, 84, 108, 103, - 104, 105, 106, }; + 80, 81, 82, 83, 84, }; +static const unsigned int vi_vip1_high8bit_pins[] = { 82, 83, 84, 103, 104, + 105, 106, 107, 102, 97, 98, }; /* definition of pin group table */ struct atlas7_pin_group altas7_pin_groups[] = { @@ -4294,6 +4294,9 @@ static struct atlas7_pad_mux vi_vip1_low8bit_grp_pad_mux[] = { MUX(1, 79, 1, N, N, N, N), MUX(1, 80, 1, N, N, N, N), MUX(1, 81, 1, N, N, N, N), + MUX(1, 82, 1, N, N, N, N), + MUX(1, 83, 1, N, N, N, N), + MUX(1, 84, 1, N, N, N, N), }; static struct atlas7_grp_mux vi_vip1_low8bit_grp_mux = { @@ -4305,11 +4308,14 @@ static struct atlas7_pad_mux vi_vip1_high8bit_grp_pad_mux[] = { MUX(1, 82, 1, N, N, N, N), MUX(1, 83, 1, N, N, N, N), MUX(1, 84, 1, N, N, N, N), - MUX(1, 108, 2, N, N, N, N), MUX(1, 103, 2, N, N, N, N), MUX(1, 104, 2, N, N, N, N), MUX(1, 105, 2, N, N, N, N), MUX(1, 106, 2, N, N, N, N), + MUX(1, 107, 2, N, N, N, N), + MUX(1, 102, 2, N, N, N, N), + MUX(1, 97, 2, N, N, N, N), + MUX(1, 98, 2, N, N, N, N), }; static struct atlas7_grp_mux vi_vip1_high8bit_grp_mux = { -- cgit v0.10.2 From df8801a0739664b48f8c47b276e989b2c6d8bced Mon Sep 17 00:00:00 2001 From: Guoying Zhang Date: Mon, 30 Nov 2015 06:05:57 +0000 Subject: pinctrl: atlas7: add pulse conter pin group without direction pin DR needs use the pulse counter direction pin as common gpio function. Signed-off-by: Guoying Zhang Signed-off-by: Barry Song Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/sirf/pinctrl-atlas7.c b/drivers/pinctrl/sirf/pinctrl-atlas7.c index fc9c3f7..053d98e 100644 --- a/drivers/pinctrl/sirf/pinctrl-atlas7.c +++ b/drivers/pinctrl/sirf/pinctrl-atlas7.c @@ -894,6 +894,7 @@ static const unsigned int nd_df_basic_pins[] = { 44, 43, 42, 41, 40, 39, 38, static const unsigned int nd_df_wp_pins[] = { 124, }; static const unsigned int nd_df_cs_pins[] = { 51, }; static const unsigned int ps_pins[] = { 120, 119, 121, }; +static const unsigned int ps_no_dir_pins[] = { 119, }; static const unsigned int pwc_core_on_pins[] = { 8, }; static const unsigned int pwc_ext_on_pins[] = { 6, }; static const unsigned int pwc_gpio3_clk_pins[] = { 3, }; @@ -1150,6 +1151,7 @@ struct atlas7_pin_group altas7_pin_groups[] = { GROUP("nd_df_wp_grp", nd_df_wp_pins), GROUP("nd_df_cs_grp", nd_df_cs_pins), GROUP("ps_grp", ps_pins), + GROUP("ps_no_dir_grp", ps_no_dir_pins), GROUP("pwc_core_on_grp", pwc_core_on_pins), GROUP("pwc_ext_on_grp", pwc_ext_on_pins), GROUP("pwc_gpio3_clk_grp", pwc_gpio3_clk_pins), @@ -1430,6 +1432,7 @@ static const char * const nd_df_basic_grp[] = { "nd_df_basic_grp", }; static const char * const nd_df_wp_grp[] = { "nd_df_wp_grp", }; static const char * const nd_df_cs_grp[] = { "nd_df_cs_grp", }; static const char * const ps_grp[] = { "ps_grp", }; +static const char * const ps_no_dir_grp[] = { "ps_no_dir_grp", }; static const char * const pwc_core_on_grp[] = { "pwc_core_on_grp", }; static const char * const pwc_ext_on_grp[] = { "pwc_ext_on_grp", }; static const char * const pwc_gpio3_clk_grp[] = { "pwc_gpio3_clk_grp", }; @@ -3232,6 +3235,15 @@ static struct atlas7_grp_mux ps_grp_mux = { .pad_mux_list = ps_grp_pad_mux, }; +static struct atlas7_pad_mux ps_no_dir_grp_pad_mux[] = { + MUX(1, 119, 2, N, N, N, N), +}; + +static struct atlas7_grp_mux ps_no_dir_grp_mux = { + .pad_mux_count = ARRAY_SIZE(ps_no_dir_grp_pad_mux), + .pad_mux_list = ps_no_dir_grp_pad_mux, +}; + static struct atlas7_pad_mux pwc_core_on_grp_pad_mux[] = { MUX(0, 8, 1, N, N, N, N), }; @@ -4606,6 +4618,7 @@ static struct atlas7_pmx_func atlas7_pmx_functions[] = { FUNCTION("nd_df_wp", nd_df_wp_grp, &nd_df_wp_grp_mux), FUNCTION("nd_df_cs", nd_df_cs_grp, &nd_df_cs_grp_mux), FUNCTION("ps", ps_grp, &ps_grp_mux), + FUNCTION("ps_no_dir", ps_no_dir_grp, &ps_no_dir_grp_mux), FUNCTION("pwc_core_on", pwc_core_on_grp, &pwc_core_on_grp_mux), FUNCTION("pwc_ext_on", pwc_ext_on_grp, &pwc_ext_on_grp_mux), FUNCTION("pwc_gpio3_clk", pwc_gpio3_clk_grp, &pwc_gpio3_clk_grp_mux), -- cgit v0.10.2 From e43d2b75297e9a5d3fc154f28c8be95b9694b29b Mon Sep 17 00:00:00 2001 From: Ludovic Desroches Date: Tue, 1 Dec 2015 15:19:02 +0100 Subject: pinctrl: at91-pio4: fix memleak after using dt map configs is allocated by pinconf_generic_parse_dt_config(), pinctrl_utils_add_map_configs() duplicates configs so it can and has to be freed to prevent memory leaks. Signed-off-by: Ludovic Desroches Reported-by: Yingjoe Chen Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/pinctrl-at91-pio4.c b/drivers/pinctrl/pinctrl-at91-pio4.c index abdc16e..d5bdceb 100644 --- a/drivers/pinctrl/pinctrl-at91-pio4.c +++ b/drivers/pinctrl/pinctrl-at91-pio4.c @@ -500,7 +500,8 @@ static int atmel_pctl_dt_subnode_to_map(struct pinctrl_dev *pctldev, if (!num_pins) { dev_err(pctldev->dev, "no pins found in node %s\n", of_node_full_name(np)); - return -EINVAL; + ret = -EINVAL; + goto exit; } /* @@ -514,19 +515,19 @@ static int atmel_pctl_dt_subnode_to_map(struct pinctrl_dev *pctldev, ret = pinctrl_utils_reserve_map(pctldev, map, reserved_maps, num_maps, reserve); if (ret < 0) - return ret; + goto exit; for (i = 0; i < num_pins; i++) { const char *group, *func; ret = of_property_read_u32_index(np, "pinmux", i, &pinfunc); if (ret) - return ret; + goto exit; ret = atmel_pctl_xlate_pinfunc(pctldev, np, pinfunc, &group, &func); if (ret) - return ret; + goto exit; pinctrl_utils_add_map_mux(pctldev, map, reserved_maps, num_maps, group, func); @@ -537,11 +538,13 @@ static int atmel_pctl_dt_subnode_to_map(struct pinctrl_dev *pctldev, configs, num_configs, PIN_MAP_TYPE_CONFIGS_GROUP); if (ret < 0) - return ret; + goto exit; } } - return 0; +exit: + kfree(configs); + return ret; } static int atmel_pctl_dt_node_to_map(struct pinctrl_dev *pctldev, -- cgit v0.10.2 From bb37baeaafa699055eb1bf2242e3a4868bfdd18b Mon Sep 17 00:00:00 2001 From: Yendapally Reddy Dhananjaya Reddy Date: Fri, 4 Dec 2015 12:10:57 -0500 Subject: pinctrl: Broadcom NSP GPIO-a device tree bindings Device tree binding documentation for Broadcom NSP GPIO-a Signed-off-by: Yendapally Reddy Dhananjaya Reddy Signed-off-by: Linus Walleij diff --git a/Documentation/devicetree/bindings/pinctrl/brcm,nsp-gpio.txt b/Documentation/devicetree/bindings/pinctrl/brcm,nsp-gpio.txt new file mode 100644 index 0000000..0844168 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/brcm,nsp-gpio.txt @@ -0,0 +1,80 @@ +Broadcom Northstar plus (NSP) GPIO/PINCONF Controller + +Required properties: +- compatible: + Must be "brcm,nsp-gpio-a" + +- reg: + Should contain the register physical address and length for each of + GPIO base, IO control registers + +- #gpio-cells: + Must be two. The first cell is the GPIO pin number (within the + controller's pin space) and the second cell is used for the following: + bit[0]: polarity (0 for active high and 1 for active low) + +- gpio-controller: + Specifies that the node is a GPIO controller + +- ngpios: + Number of gpios supported (58x25 supports 32 and 58x23 supports 24) + +Optional properties: +- interrupts: + Interrupt ID + +- interrupt-controller: + Specifies that the node is an interrupt controller + +- gpio-ranges: + Specifies the mapping between gpio controller and pin-controllers pins. + This requires 4 fields in cells defined as - + 1. Phandle of pin-controller. + 2. GPIO base pin offset. + 3 Pin-control base pin offset. + 4. number of gpio pins which are linearly mapped from pin base. + +Supported generic PINCONF properties in child nodes: +- pins: + The list of pins (within the controller's own pin space) that properties + in the node apply to. Pin names are "gpio-" + +- bias-disable: + Disable pin bias + +- bias-pull-up: + Enable internal pull up resistor + +- bias-pull-down: + Enable internal pull down resistor + +- drive-strength: + Valid drive strength values include 2, 4, 6, 8, 10, 12, 14, 16 (mA) + +Example: + + gpioa: gpio@18000020 { + compatible = "brcm,nsp-gpio-a"; + reg = <0x18000020 0x100>, + <0x1803f1c4 0x1c>; + #gpio-cells = <2>; + gpio-controller; + ngpios = <32>; + gpio-ranges = <&pinctrl 0 0 31>; + interrupt-controller; + interrupts = ; + + /* Hog a few default settings */ + pinctrl-names = "default"; + pinctrl-0 = <&led>; + led: led { + pins = "gpio-1"; + bias-pull-up; + }; + + pwr: pwr { + gpio-hog; + gpios = <3 1>; + output-high; + }; + }; -- cgit v0.10.2 From 8bfcbbbcabe02310885a26ebd02550a928c306ca Mon Sep 17 00:00:00 2001 From: Yendapally Reddy Dhananjaya Reddy Date: Fri, 4 Dec 2015 12:11:42 -0500 Subject: pinctrl: nsp: add gpio-a driver support for Broadcom NSP SoC This adds the initial support of the Broadcom NSP gpio-a driver. Signed-off-by: Yendapally Reddy Dhananjaya Reddy Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/bcm/Kconfig b/drivers/pinctrl/bcm/Kconfig index cd11d4d..1a8c837 100644 --- a/drivers/pinctrl/bcm/Kconfig +++ b/drivers/pinctrl/bcm/Kconfig @@ -54,3 +54,20 @@ config PINCTRL_CYGNUS_MUX The Broadcom Cygnus IOMUX driver supports group based IOMUX configuration, with the exception that certain individual pins can be overrided to GPIO function + +config PINCTRL_NSP_GPIO + bool "Broadcom NSP GPIO (with PINCONF) driver" + depends on OF_GPIO && (ARCH_BCM_NSP || COMPILE_TEST) + select GPIOLIB_IRQCHIP + select PINCONF + select GENERIC_PINCONF + default ARCH_BCM_NSP + help + Say yes here to enable the Broadcom NSP GPIO driver. + + The Broadcom Northstar Plus SoC ChipcommonA GPIO controller is + supported by this driver. + + The ChipcommonA GPIO controller support basic PINCONF functions such + as bias pull up, pull down, and drive strength configurations, when + these pins are muxed to GPIO. diff --git a/drivers/pinctrl/bcm/Makefile b/drivers/pinctrl/bcm/Makefile index 2b2f70e..2fb1ed8 100644 --- a/drivers/pinctrl/bcm/Makefile +++ b/drivers/pinctrl/bcm/Makefile @@ -4,3 +4,4 @@ obj-$(CONFIG_PINCTRL_BCM281XX) += pinctrl-bcm281xx.o obj-$(CONFIG_PINCTRL_BCM2835) += pinctrl-bcm2835.o obj-$(CONFIG_PINCTRL_CYGNUS_GPIO) += pinctrl-cygnus-gpio.o obj-$(CONFIG_PINCTRL_CYGNUS_MUX) += pinctrl-cygnus-mux.o +obj-$(CONFIG_PINCTRL_NSP_GPIO) += pinctrl-nsp-gpio.o diff --git a/drivers/pinctrl/bcm/pinctrl-nsp-gpio.c b/drivers/pinctrl/bcm/pinctrl-nsp-gpio.c new file mode 100644 index 0000000..06b7aaf --- /dev/null +++ b/drivers/pinctrl/bcm/pinctrl-nsp-gpio.c @@ -0,0 +1,749 @@ +/* + * Copyright (C) 2015 Broadcom Corporation + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * This file contains the Broadcom Northstar Plus (NSP) GPIO driver that + * supports the chipCommonA GPIO controller. Basic PINCONF such as bias, + * pull up/down, slew and drive strength are also supported in this driver. + * + * Pins from the chipCommonA GPIO can be individually muxed to GPIO function, + * through the interaction with the NSP IOMUX controller. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../pinctrl-utils.h" + +#define NSP_CHIP_A_INT_STATUS 0x00 +#define NSP_CHIP_A_INT_MASK 0x04 +#define NSP_GPIO_DATA_IN 0x40 +#define NSP_GPIO_DATA_OUT 0x44 +#define NSP_GPIO_OUT_EN 0x48 +#define NSP_GPIO_INT_POLARITY 0x50 +#define NSP_GPIO_INT_MASK 0x54 +#define NSP_GPIO_EVENT 0x58 +#define NSP_GPIO_EVENT_INT_MASK 0x5c +#define NSP_GPIO_EVENT_INT_POLARITY 0x64 +#define NSP_CHIP_A_GPIO_INT_BIT 0x01 + +/* I/O parameters offset for chipcommon A GPIO */ +#define NSP_GPIO_DRV_CTRL 0x00 +#define NSP_GPIO_HYSTERESIS_EN 0x10 +#define NSP_GPIO_SLEW_RATE_EN 0x14 +#define NSP_PULL_UP_EN 0x18 +#define NSP_PULL_DOWN_EN 0x1c +#define GPIO_DRV_STRENGTH_BITS 0x03 + +/* + * nsp GPIO core + * + * @dev: pointer to device + * @base: I/O register base for nsp GPIO controller + * @io_ctrl: I/O register base for PINCONF support outside the GPIO block + * @gc: GPIO chip + * @pctl: pointer to pinctrl_dev + * @pctldesc: pinctrl descriptor + * @irq_domain: pointer to irq domain + * @lock: lock to protect access to I/O registers + */ +struct nsp_gpio { + struct device *dev; + void __iomem *base; + void __iomem *io_ctrl; + struct gpio_chip gc; + struct pinctrl_dev *pctl; + struct pinctrl_desc pctldesc; + struct irq_domain *irq_domain; + spinlock_t lock; +}; + +enum base_type { + REG, + IO_CTRL +}; + +static inline struct nsp_gpio *to_nsp_gpio(struct gpio_chip *gc) +{ + return container_of(gc, struct nsp_gpio, gc); +} + +/* + * Mapping from PINCONF pins to GPIO pins is 1-to-1 + */ +static inline unsigned nsp_pin_to_gpio(unsigned pin) +{ + return pin; +} + +/* + * nsp_set_bit - set or clear one bit (corresponding to the GPIO pin) in a + * nsp GPIO register + * + * @nsp_gpio: nsp GPIO device + * @base_type: reg base to modify + * @reg: register offset + * @gpio: GPIO pin + * @set: set or clear + */ +static inline void nsp_set_bit(struct nsp_gpio *chip, enum base_type address, + unsigned int reg, unsigned gpio, bool set) +{ + u32 val; + void __iomem *base_address; + + if (address == IO_CTRL) + base_address = chip->io_ctrl; + else + base_address = chip->base; + + val = readl(base_address + reg); + if (set) + val |= BIT(gpio); + else + val &= ~BIT(gpio); + + writel(val, base_address + reg); +} + +/* + * nsp_get_bit - get one bit (corresponding to the GPIO pin) in a + * nsp GPIO register + */ +static inline bool nsp_get_bit(struct nsp_gpio *chip, enum base_type address, + unsigned int reg, unsigned gpio) +{ + if (address == IO_CTRL) + return !!(readl(chip->io_ctrl + reg) & BIT(gpio)); + else + return !!(readl(chip->base + reg) & BIT(gpio)); +} + +static irqreturn_t nsp_gpio_irq_handler(int irq, void *data) +{ + struct nsp_gpio *chip = (struct nsp_gpio *)data; + struct gpio_chip gc = chip->gc; + int bit; + unsigned long int_bits = 0; + u32 int_status; + + /* go through the entire GPIOs and handle all interrupts */ + int_status = readl(chip->base + NSP_CHIP_A_INT_STATUS); + if (int_status & NSP_CHIP_A_GPIO_INT_BIT) { + unsigned int event, level; + + /* Get level and edge interrupts */ + event = readl(chip->base + NSP_GPIO_EVENT_INT_MASK) & + readl(chip->base + NSP_GPIO_EVENT); + level = readl(chip->base + NSP_GPIO_DATA_IN) ^ + readl(chip->base + NSP_GPIO_INT_POLARITY); + level &= readl(chip->base + NSP_GPIO_INT_MASK); + int_bits = level | event; + + for_each_set_bit(bit, &int_bits, gc.ngpio) { + /* + * Clear the interrupt before invoking the + * handler, so we do not leave any window + */ + writel(BIT(bit), chip->base + NSP_GPIO_EVENT); + generic_handle_irq( + irq_linear_revmap(chip->irq_domain, bit)); + } + } + + return int_bits ? IRQ_HANDLED : IRQ_NONE; +} + +static void nsp_gpio_irq_ack(struct irq_data *d) +{ + struct nsp_gpio *chip = irq_data_get_irq_chip_data(d); + unsigned gpio = d->hwirq; + u32 val = BIT(gpio); + u32 trigger_type; + + trigger_type = irq_get_trigger_type(d->irq); + if (trigger_type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) + nsp_set_bit(chip, REG, NSP_GPIO_EVENT, gpio, val); +} + +/* + * nsp_gpio_irq_set_mask - mask/unmask a GPIO interrupt + * + * @d: IRQ chip data + * @unmask: mask/unmask GPIO interrupt + */ +static void nsp_gpio_irq_set_mask(struct irq_data *d, bool unmask) +{ + struct nsp_gpio *chip = irq_data_get_irq_chip_data(d); + unsigned gpio = d->hwirq; + u32 trigger_type; + + trigger_type = irq_get_trigger_type(d->irq); + if (trigger_type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) + nsp_set_bit(chip, REG, NSP_GPIO_EVENT_INT_MASK, gpio, unmask); + else + nsp_set_bit(chip, REG, NSP_GPIO_INT_MASK, gpio, unmask); +} + +static void nsp_gpio_irq_mask(struct irq_data *d) +{ + struct nsp_gpio *chip = irq_data_get_irq_chip_data(d); + unsigned long flags; + + spin_lock_irqsave(&chip->lock, flags); + nsp_gpio_irq_set_mask(d, false); + spin_unlock_irqrestore(&chip->lock, flags); +} + +static void nsp_gpio_irq_unmask(struct irq_data *d) +{ + struct nsp_gpio *chip = irq_data_get_irq_chip_data(d); + unsigned long flags; + + spin_lock_irqsave(&chip->lock, flags); + nsp_gpio_irq_set_mask(d, true); + spin_unlock_irqrestore(&chip->lock, flags); +} + +static int nsp_gpio_irq_set_type(struct irq_data *d, unsigned int type) +{ + struct nsp_gpio *chip = irq_data_get_irq_chip_data(d); + unsigned gpio = d->hwirq; + bool level_low; + bool falling; + unsigned long flags; + + spin_lock_irqsave(&chip->lock, flags); + falling = nsp_get_bit(chip, REG, NSP_GPIO_EVENT_INT_POLARITY, gpio); + level_low = nsp_get_bit(chip, REG, NSP_GPIO_INT_POLARITY, gpio); + + switch (type & IRQ_TYPE_SENSE_MASK) { + case IRQ_TYPE_EDGE_RISING: + falling = false; + break; + + case IRQ_TYPE_EDGE_FALLING: + falling = true; + break; + + case IRQ_TYPE_LEVEL_HIGH: + level_low = false; + break; + + case IRQ_TYPE_LEVEL_LOW: + level_low = true; + break; + + default: + dev_err(chip->dev, "invalid GPIO IRQ type 0x%x\n", + type); + spin_unlock_irqrestore(&chip->lock, flags); + return -EINVAL; + } + + nsp_set_bit(chip, REG, NSP_GPIO_EVENT_INT_POLARITY, gpio, falling); + nsp_set_bit(chip, REG, NSP_GPIO_INT_POLARITY, gpio, level_low); + spin_unlock_irqrestore(&chip->lock, flags); + + dev_dbg(chip->dev, "gpio:%u level_low:%s falling:%s\n", gpio, + level_low ? "true" : "false", falling ? "true" : "false"); + return 0; +} + +static struct irq_chip nsp_gpio_irq_chip = { + .name = "gpio-a", + .irq_enable = nsp_gpio_irq_unmask, + .irq_disable = nsp_gpio_irq_mask, + .irq_ack = nsp_gpio_irq_ack, + .irq_mask = nsp_gpio_irq_mask, + .irq_unmask = nsp_gpio_irq_unmask, + .irq_set_type = nsp_gpio_irq_set_type, +}; + +/* + * Request the nsp IOMUX pinmux controller to mux individual pins to GPIO + */ +static int nsp_gpio_request(struct gpio_chip *gc, unsigned offset) +{ + unsigned gpio = gc->base + offset; + + return pinctrl_request_gpio(gpio); +} + +static void nsp_gpio_free(struct gpio_chip *gc, unsigned offset) +{ + unsigned gpio = gc->base + offset; + + pinctrl_free_gpio(gpio); +} + +static int nsp_gpio_direction_input(struct gpio_chip *gc, unsigned gpio) +{ + struct nsp_gpio *chip = to_nsp_gpio(gc); + unsigned long flags; + + spin_lock_irqsave(&chip->lock, flags); + nsp_set_bit(chip, REG, NSP_GPIO_OUT_EN, gpio, false); + spin_unlock_irqrestore(&chip->lock, flags); + + dev_dbg(chip->dev, "gpio:%u set input\n", gpio); + return 0; +} + +static int nsp_gpio_direction_output(struct gpio_chip *gc, unsigned gpio, + int val) +{ + struct nsp_gpio *chip = to_nsp_gpio(gc); + unsigned long flags; + + spin_lock_irqsave(&chip->lock, flags); + nsp_set_bit(chip, REG, NSP_GPIO_OUT_EN, gpio, true); + nsp_set_bit(chip, REG, NSP_GPIO_DATA_OUT, gpio, !!(val)); + spin_unlock_irqrestore(&chip->lock, flags); + + dev_dbg(chip->dev, "gpio:%u set output, value:%d\n", gpio, val); + return 0; +} + +static void nsp_gpio_set(struct gpio_chip *gc, unsigned gpio, int val) +{ + struct nsp_gpio *chip = to_nsp_gpio(gc); + unsigned long flags; + + spin_lock_irqsave(&chip->lock, flags); + nsp_set_bit(chip, REG, NSP_GPIO_DATA_OUT, gpio, !!(val)); + spin_unlock_irqrestore(&chip->lock, flags); + + dev_dbg(chip->dev, "gpio:%u set, value:%d\n", gpio, val); +} + +static int nsp_gpio_get(struct gpio_chip *gc, unsigned gpio) +{ + struct nsp_gpio *chip = to_nsp_gpio(gc); + + return !!(readl(chip->base + NSP_GPIO_DATA_IN) & BIT(gpio)); +} + +static int nsp_gpio_to_irq(struct gpio_chip *gc, unsigned offset) +{ + struct nsp_gpio *chip = to_nsp_gpio(gc); + + return irq_linear_revmap(chip->irq_domain, offset); +} + +static int nsp_get_groups_count(struct pinctrl_dev *pctldev) +{ + return 1; +} + +/* + * Only one group: "gpio_grp", since this local pinctrl device only performs + * GPIO specific PINCONF configurations + */ +static const char *nsp_get_group_name(struct pinctrl_dev *pctldev, + unsigned selector) +{ + return "gpio_grp"; +} + +static const struct pinctrl_ops nsp_pctrl_ops = { + .get_groups_count = nsp_get_groups_count, + .get_group_name = nsp_get_group_name, + .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, + .dt_free_map = pinctrl_utils_dt_free_map, +}; + +static int nsp_gpio_set_slew(struct nsp_gpio *chip, unsigned gpio, u16 slew) +{ + if (slew) + nsp_set_bit(chip, IO_CTRL, NSP_GPIO_SLEW_RATE_EN, gpio, true); + else + nsp_set_bit(chip, IO_CTRL, NSP_GPIO_SLEW_RATE_EN, gpio, false); + + return 0; +} + +static int nsp_gpio_set_pull(struct nsp_gpio *chip, unsigned gpio, + bool pull_up, bool pull_down) +{ + unsigned long flags; + + spin_lock_irqsave(&chip->lock, flags); + nsp_set_bit(chip, IO_CTRL, NSP_PULL_DOWN_EN, gpio, pull_down); + nsp_set_bit(chip, IO_CTRL, NSP_PULL_UP_EN, gpio, pull_up); + spin_unlock_irqrestore(&chip->lock, flags); + + dev_dbg(chip->dev, "gpio:%u set pullup:%d pulldown: %d\n", + gpio, pull_up, pull_down); + return 0; +} + +static void nsp_gpio_get_pull(struct nsp_gpio *chip, unsigned gpio, + bool *pull_up, bool *pull_down) +{ + unsigned long flags; + + spin_lock_irqsave(&chip->lock, flags); + *pull_up = nsp_get_bit(chip, IO_CTRL, NSP_PULL_UP_EN, gpio); + *pull_down = nsp_get_bit(chip, IO_CTRL, NSP_PULL_DOWN_EN, gpio); + spin_unlock_irqrestore(&chip->lock, flags); +} + +static int nsp_gpio_set_strength(struct nsp_gpio *chip, unsigned gpio, + u16 strength) +{ + u32 offset, shift, i; + u32 val; + unsigned long flags; + + /* make sure drive strength is supported */ + if (strength < 2 || strength > 16 || (strength % 2)) + return -ENOTSUPP; + + shift = gpio; + offset = NSP_GPIO_DRV_CTRL; + dev_dbg(chip->dev, "gpio:%u set drive strength:%d mA\n", gpio, + strength); + spin_lock_irqsave(&chip->lock, flags); + strength = (strength / 2) - 1; + for (i = GPIO_DRV_STRENGTH_BITS; i > 0; i--) { + val = readl(chip->io_ctrl + offset); + val &= ~BIT(shift); + val |= ((strength >> (i-1)) & 0x1) << shift; + writel(val, chip->io_ctrl + offset); + offset += 4; + } + spin_unlock_irqrestore(&chip->lock, flags); + + return 0; +} + +static int nsp_gpio_get_strength(struct nsp_gpio *chip, unsigned gpio, + u16 *strength) +{ + unsigned int i, offset, shift; + u32 val; + unsigned long flags; + + offset = NSP_GPIO_DRV_CTRL; + shift = gpio; + + spin_lock_irqsave(&chip->lock, flags); + *strength = 0; + for (i = (GPIO_DRV_STRENGTH_BITS - 1); i >= 0; i--) { + val = readl(chip->io_ctrl + offset) & BIT(shift); + val >>= shift; + *strength += (val << i); + offset += 4; + } + + /* convert to mA */ + *strength = (*strength + 1) * 2; + spin_unlock_irqrestore(&chip->lock, flags); + + return 0; +} + +int nsp_pin_config_group_get(struct pinctrl_dev *pctldev, unsigned selector, + unsigned long *config) +{ + return 0; +} + +int nsp_pin_config_group_set(struct pinctrl_dev *pctldev, unsigned selector, + unsigned long *configs, unsigned num_configs) +{ + return 0; +} + +static int nsp_pin_config_get(struct pinctrl_dev *pctldev, unsigned pin, + unsigned long *config) +{ + struct nsp_gpio *chip = pinctrl_dev_get_drvdata(pctldev); + enum pin_config_param param = pinconf_to_config_param(*config); + unsigned int gpio; + u16 arg = 0; + bool pull_up, pull_down; + int ret; + + gpio = nsp_pin_to_gpio(pin); + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + nsp_gpio_get_pull(chip, gpio, &pull_up, &pull_down); + if ((pull_up == false) && (pull_down == false)) + return 0; + else + return -EINVAL; + + case PIN_CONFIG_BIAS_PULL_UP: + nsp_gpio_get_pull(chip, gpio, &pull_up, &pull_down); + if (pull_up) + return 0; + else + return -EINVAL; + + case PIN_CONFIG_BIAS_PULL_DOWN: + nsp_gpio_get_pull(chip, gpio, &pull_up, &pull_down); + if (pull_down) + return 0; + else + return -EINVAL; + + case PIN_CONFIG_DRIVE_STRENGTH: + ret = nsp_gpio_get_strength(chip, gpio, &arg); + if (ret) + return ret; + *config = pinconf_to_config_packed(param, arg); + return 0; + + default: + return -ENOTSUPP; + } +} + +static int nsp_pin_config_set(struct pinctrl_dev *pctldev, unsigned pin, + unsigned long *configs, unsigned num_configs) +{ + struct nsp_gpio *chip = pinctrl_dev_get_drvdata(pctldev); + enum pin_config_param param; + u16 arg; + unsigned int i, gpio; + int ret = -ENOTSUPP; + + gpio = nsp_pin_to_gpio(pin); + for (i = 0; i < num_configs; i++) { + param = pinconf_to_config_param(configs[i]); + arg = pinconf_to_config_argument(configs[i]); + + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + ret = nsp_gpio_set_pull(chip, gpio, false, false); + if (ret < 0) + goto out; + break; + + case PIN_CONFIG_BIAS_PULL_UP: + ret = nsp_gpio_set_pull(chip, gpio, true, false); + if (ret < 0) + goto out; + break; + + case PIN_CONFIG_BIAS_PULL_DOWN: + ret = nsp_gpio_set_pull(chip, gpio, false, true); + if (ret < 0) + goto out; + break; + + case PIN_CONFIG_DRIVE_STRENGTH: + ret = nsp_gpio_set_strength(chip, gpio, arg); + if (ret < 0) + goto out; + break; + + case PIN_CONFIG_SLEW_RATE: + ret = nsp_gpio_set_slew(chip, gpio, arg); + if (ret < 0) + goto out; + break; + + default: + dev_err(chip->dev, "invalid configuration\n"); + return -ENOTSUPP; + } + } + +out: + return ret; +} + +static const struct pinconf_ops nsp_pconf_ops = { + .is_generic = true, + .pin_config_get = nsp_pin_config_get, + .pin_config_set = nsp_pin_config_set, + .pin_config_group_get = nsp_pin_config_group_get, + .pin_config_group_set = nsp_pin_config_group_set, +}; + +/* + * NSP GPIO controller supports some PINCONF related configurations such as + * pull up, pull down, slew and drive strength, when the pin is configured + * to GPIO. + * + * Here a local pinctrl device is created with simple 1-to-1 pin mapping to the + * local GPIO pins + */ +static int nsp_gpio_register_pinconf(struct nsp_gpio *chip) +{ + struct pinctrl_desc *pctldesc = &chip->pctldesc; + struct pinctrl_pin_desc *pins; + struct gpio_chip *gc = &chip->gc; + int i; + + pins = devm_kcalloc(chip->dev, gc->ngpio, sizeof(*pins), GFP_KERNEL); + if (!pins) + return -ENOMEM; + for (i = 0; i < gc->ngpio; i++) { + pins[i].number = i; + pins[i].name = devm_kasprintf(chip->dev, GFP_KERNEL, + "gpio-%d", i); + if (!pins[i].name) + return -ENOMEM; + } + pctldesc->name = dev_name(chip->dev); + pctldesc->pctlops = &nsp_pctrl_ops; + pctldesc->pins = pins; + pctldesc->npins = gc->ngpio; + pctldesc->confops = &nsp_pconf_ops; + + chip->pctl = pinctrl_register(pctldesc, chip->dev, chip); + if (IS_ERR(chip->pctl)) { + dev_err(chip->dev, "unable to register pinctrl device\n"); + return PTR_ERR(chip->pctl); + } + + return 0; +} + +static const struct of_device_id nsp_gpio_of_match[] = { + {.compatible = "brcm,nsp-gpio-a",}, + {} +}; + +static int nsp_gpio_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct resource *res; + struct nsp_gpio *chip; + struct gpio_chip *gc; + u32 val, count; + int irq, ret; + + if (of_property_read_u32(pdev->dev.of_node, "ngpios", &val)) { + dev_err(&pdev->dev, "Missing ngpios OF property\n"); + return -ENODEV; + } + + chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); + if (!chip) + return -ENOMEM; + + chip->dev = dev; + platform_set_drvdata(pdev, chip); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + chip->base = devm_ioremap_resource(dev, res); + if (IS_ERR(chip->base)) { + dev_err(dev, "unable to map I/O memory\n"); + return PTR_ERR(chip->base); + } + + res = platform_get_resource(pdev, IORESOURCE_MEM, 1); + chip->io_ctrl = devm_ioremap_resource(dev, res); + if (IS_ERR(chip->io_ctrl)) { + dev_err(dev, "unable to map I/O memory\n"); + return PTR_ERR(chip->io_ctrl); + } + + spin_lock_init(&chip->lock); + gc = &chip->gc; + gc->base = -1; + gc->can_sleep = false; + gc->ngpio = val; + gc->label = dev_name(dev); + gc->dev = dev; + gc->of_node = dev->of_node; + gc->request = nsp_gpio_request; + gc->free = nsp_gpio_free; + gc->direction_input = nsp_gpio_direction_input; + gc->direction_output = nsp_gpio_direction_output; + gc->set = nsp_gpio_set; + gc->get = nsp_gpio_get; + gc->to_irq = nsp_gpio_to_irq; + + /* optional GPIO interrupt support */ + irq = platform_get_irq(pdev, 0); + if (irq > 0) { + /* Create irq domain so that each pin can be assigned an IRQ.*/ + chip->irq_domain = irq_domain_add_linear(gc->of_node, gc->ngpio, + &irq_domain_simple_ops, + chip); + if (!chip->irq_domain) { + dev_err(&pdev->dev, "Couldn't allocate IRQ domain\n"); + return -ENXIO; + } + + /* Map each gpio to an IRQ and set the handler for gpiolib. */ + for (count = 0; count < gc->ngpio; count++) { + int irq = irq_create_mapping(chip->irq_domain, count); + + irq_set_chip_and_handler(irq, &nsp_gpio_irq_chip, + handle_simple_irq); + set_irq_flags(irq, IRQF_VALID); + irq_set_chip_data(irq, chip); + } + + /* Install ISR for this GPIO controller. */ + ret = devm_request_irq(&pdev->dev, irq, nsp_gpio_irq_handler, + IRQF_SHARED, "gpio-a", chip); + if (ret) { + dev_err(&pdev->dev, "Unable to request IRQ%d: %d\n", + irq, ret); + goto err_rm_gpiochip; + } + + val = readl(chip->base + NSP_CHIP_A_INT_MASK); + val = val | NSP_CHIP_A_GPIO_INT_BIT; + writel(val, (chip->base + NSP_CHIP_A_INT_MASK)); + } + + ret = gpiochip_add(gc); + if (ret < 0) { + dev_err(dev, "unable to add GPIO chip\n"); + return ret; + } + + ret = nsp_gpio_register_pinconf(chip); + if (ret) { + dev_err(dev, "unable to register pinconf\n"); + goto err_rm_gpiochip; + } + + return 0; + +err_rm_gpiochip: + gpiochip_remove(gc); + + return ret; +} + +static struct platform_driver nsp_gpio_driver = { + .driver = { + .name = "nsp-gpio-a", + .of_match_table = nsp_gpio_of_match, + }, + .probe = nsp_gpio_probe, +}; + +static int __init nsp_gpio_init(void) +{ + return platform_driver_probe(&nsp_gpio_driver, nsp_gpio_probe); +} +arch_initcall_sync(nsp_gpio_init); -- cgit v0.10.2 From 588047686fe9e4a4da85ca6dd92a220a8fb45ce5 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Thu, 10 Dec 2015 23:04:45 +0100 Subject: Revert "pinctrl: intel: fix bug of register offset calculation" This reverts commit c5cdcba3d54b9bd2443bd0afe9f4828f802a944f. diff --git a/drivers/pinctrl/intel/pinctrl-broxton.c b/drivers/pinctrl/intel/pinctrl-broxton.c index 5979d38..e42d5d4 100644 --- a/drivers/pinctrl/intel/pinctrl-broxton.c +++ b/drivers/pinctrl/intel/pinctrl-broxton.c @@ -28,7 +28,6 @@ .padcfglock_offset = BXT_PADCFGLOCK, \ .hostown_offset = BXT_HOSTSW_OWN, \ .ie_offset = BXT_GPI_IE, \ - .gpp_size = 32, \ .pin_base = (s), \ .npins = ((e) - (s) + 1), \ } diff --git a/drivers/pinctrl/intel/pinctrl-intel.c b/drivers/pinctrl/intel/pinctrl-intel.c index 06004d8..392e28d 100644 --- a/drivers/pinctrl/intel/pinctrl-intel.c +++ b/drivers/pinctrl/intel/pinctrl-intel.c @@ -25,6 +25,9 @@ #include "pinctrl-intel.h" +/* Maximum number of pads in each group */ +#define NPADS_IN_GPP 24 + /* Offset from regs */ #define PADBAR 0x00c #define GPI_IS 0x100 @@ -170,11 +173,11 @@ static bool intel_pad_acpi_mode(struct intel_pinctrl *pctrl, unsigned pin) return false; padno = pin_to_padno(community, pin); - gpp = padno / community->gpp_size; + gpp = padno / NPADS_IN_GPP; offset = community->hostown_offset + gpp * 4; hostown = community->regs + offset; - return !(readl(hostown) & BIT(padno % community->gpp_size)); + return !(readl(hostown) & BIT(padno % NPADS_IN_GPP)); } static bool intel_pad_locked(struct intel_pinctrl *pctrl, unsigned pin) @@ -190,7 +193,7 @@ static bool intel_pad_locked(struct intel_pinctrl *pctrl, unsigned pin) return false; padno = pin_to_padno(community, pin); - gpp = padno / community->gpp_size; + gpp = padno / NPADS_IN_GPP; /* * If PADCFGLOCK and PADCFGLOCKTX bits are both clear for this pad, @@ -199,12 +202,12 @@ static bool intel_pad_locked(struct intel_pinctrl *pctrl, unsigned pin) */ offset = community->padcfglock_offset + gpp * 8; value = readl(community->regs + offset); - if (value & BIT(pin % community->gpp_size)) + if (value & BIT(pin % NPADS_IN_GPP)) return true; offset = community->padcfglock_offset + 4 + gpp * 8; value = readl(community->regs + offset); - if (value & BIT(pin % community->gpp_size)) + if (value & BIT(pin % NPADS_IN_GPP)) return true; return false; @@ -660,8 +663,8 @@ static void intel_gpio_irq_ack(struct irq_data *d) community = intel_get_community(pctrl, pin); if (community) { unsigned padno = pin_to_padno(community, pin); - unsigned gpp_offset = padno % community->gpp_size; - unsigned gpp = padno / community->gpp_size; + unsigned gpp_offset = padno % NPADS_IN_GPP; + unsigned gpp = padno / NPADS_IN_GPP; writel(BIT(gpp_offset), community->regs + GPI_IS + gpp * 4); } @@ -682,8 +685,8 @@ static void intel_gpio_irq_mask_unmask(struct irq_data *d, bool mask) community = intel_get_community(pctrl, pin); if (community) { unsigned padno = pin_to_padno(community, pin); - unsigned gpp_offset = padno % community->gpp_size; - unsigned gpp = padno / community->gpp_size; + unsigned gpp_offset = padno % NPADS_IN_GPP; + unsigned gpp = padno / NPADS_IN_GPP; void __iomem *reg; u32 value; @@ -777,8 +780,8 @@ static int intel_gpio_irq_wake(struct irq_data *d, unsigned int on) return -EINVAL; padno = pin_to_padno(community, pin); - gpp = padno / community->gpp_size; - gpp_offset = padno % community->gpp_size; + gpp = padno / NPADS_IN_GPP; + gpp_offset = padno % NPADS_IN_GPP; /* Clear the existing wake status */ writel(BIT(gpp_offset), community->regs + GPI_GPE_STS + gpp * 4); @@ -816,14 +819,14 @@ static irqreturn_t intel_gpio_community_irq_handler(struct intel_pinctrl *pctrl, /* Only interrupts that are enabled */ pending &= enabled; - for_each_set_bit(gpp_offset, &pending, community->gpp_size) { + for_each_set_bit(gpp_offset, &pending, NPADS_IN_GPP) { unsigned padno, irq; /* * The last group in community can have less pins * than NPADS_IN_GPP. */ - padno = gpp_offset + gpp * community->gpp_size; + padno = gpp_offset + gpp * NPADS_IN_GPP; if (padno >= community->npins) break; @@ -999,8 +1002,7 @@ int intel_pinctrl_probe(struct platform_device *pdev, community->regs = regs; community->pad_regs = regs + padbar; - community->ngpps = DIV_ROUND_UP(community->npins, - community->gpp_size); + community->ngpps = DIV_ROUND_UP(community->npins, NPADS_IN_GPP); } irq = platform_get_irq(pdev, 0); diff --git a/drivers/pinctrl/intel/pinctrl-intel.h b/drivers/pinctrl/intel/pinctrl-intel.h index b602157..4ec8b57 100644 --- a/drivers/pinctrl/intel/pinctrl-intel.h +++ b/drivers/pinctrl/intel/pinctrl-intel.h @@ -55,8 +55,6 @@ struct intel_function { * ACPI). * @ie_offset: Register offset of GPI_IE from @regs. * @pin_base: Starting pin of pins in this community - * @gpp_size: Maximum number of pads in each group, such as PADCFGLOCK, - * HOSTSW_OWN, GPI_IS, GPI_IE, etc. * @npins: Number of pins in this community * @regs: Community specific common registers (reserved for core driver) * @pad_regs: Community specific pad registers (reserved for core driver) @@ -70,7 +68,6 @@ struct intel_community { unsigned hostown_offset; unsigned ie_offset; unsigned pin_base; - unsigned gpp_size; size_t npins; void __iomem *regs; void __iomem *pad_regs; diff --git a/drivers/pinctrl/intel/pinctrl-sunrisepoint.c b/drivers/pinctrl/intel/pinctrl-sunrisepoint.c index c725a53..1de9ae5 100644 --- a/drivers/pinctrl/intel/pinctrl-sunrisepoint.c +++ b/drivers/pinctrl/intel/pinctrl-sunrisepoint.c @@ -30,7 +30,6 @@ .padcfglock_offset = SPT_PADCFGLOCK, \ .hostown_offset = SPT_HOSTSW_OWN, \ .ie_offset = SPT_GPI_IE, \ - .gpp_size = 24, \ .pin_base = (s), \ .npins = ((e) - (s) + 1), \ } -- cgit v0.10.2 From 9b0ee474cfdbce235f63e179d018e28673163075 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Wed, 2 Dec 2015 17:31:54 +0100 Subject: pinctrl: adi2: Use platform_register/unregister_drivers() These new helpers simplify implementing multi-driver modules and properly handle failure to register one driver by unregistering all previously registered drivers. Signed-off-by: Thierry Reding Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/pinctrl-adi2.c b/drivers/pinctrl/pinctrl-adi2.c index fd342df..8e9e8ea 100644 --- a/drivers/pinctrl/pinctrl-adi2.c +++ b/drivers/pinctrl/pinctrl-adi2.c @@ -1102,32 +1102,24 @@ static struct platform_driver adi_gpio_driver = { }, }; +static struct platform_driver * const drivers[] = { + &adi_pinctrl_driver, + &adi_gpio_pint_driver, + &adi_gpio_driver, +}; + static int __init adi_pinctrl_setup(void) { int ret; - ret = platform_driver_register(&adi_pinctrl_driver); + ret = platform_register_drivers(drivers, ARRAY_SIZE(drivers)); if (ret) return ret; - ret = platform_driver_register(&adi_gpio_pint_driver); - if (ret) - goto pint_error; - - ret = platform_driver_register(&adi_gpio_driver); - if (ret) - goto gpio_error; - #ifdef CONFIG_PM register_syscore_ops(&gpio_pm_syscore_ops); #endif - return ret; -gpio_error: - platform_driver_unregister(&adi_gpio_pint_driver); -pint_error: - platform_driver_unregister(&adi_pinctrl_driver); - - return ret; + return 0; } arch_initcall(adi_pinctrl_setup); -- cgit v0.10.2 From bab7f5a4019b6ca410acdf8730b924b989049423 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Wed, 2 Dec 2015 17:31:55 +0100 Subject: pinctrl: at91: Use platform_register/unregister_drivers() These new helpers simplify implementing multi-driver modules and properly handle failure to register one driver by unregistering all previously registered drivers. Signed-off-by: Thierry Reding Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c index 0d2fc0c..47b625b 100644 --- a/drivers/pinctrl/pinctrl-at91.c +++ b/drivers/pinctrl/pinctrl-at91.c @@ -1828,20 +1828,20 @@ static struct platform_driver at91_pinctrl_driver = { .remove = at91_pinctrl_remove, }; +static struct platform_driver * const drivers[] = { + &at91_gpio_driver, + &at91_pinctrl_driver, +}; + static int __init at91_pinctrl_init(void) { - int ret; - - ret = platform_driver_register(&at91_gpio_driver); - if (ret) - return ret; - return platform_driver_register(&at91_pinctrl_driver); + return platform_register_drivers(drivers, ARRAY_SIZE(drivers)); } arch_initcall(at91_pinctrl_init); static void __exit at91_pinctrl_exit(void) { - platform_driver_unregister(&at91_pinctrl_driver); + platform_unregister_drivers(drivers, ARRAY_SIZE(drivers)); } module_exit(at91_pinctrl_exit); -- cgit v0.10.2 From 652da8248ebad205fbd59fc7fed6e8d5baef4472 Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Tue, 1 Dec 2015 17:41:30 -0800 Subject: pinctrl: bcm: Default PINCTRL_BCM281XX to y for ARCH_BCM_MOBILE This driver is mandatory for proper operation on the platforms covered by the ARCH_BCM_MOBILE Kconfig symbol, make sure we do that driver on for these platforms. Signed-off-by: Florian Fainelli Reviewed-by: Ray Jui Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/bcm/Kconfig b/drivers/pinctrl/bcm/Kconfig index a99ca6a..2cc7438 100644 --- a/drivers/pinctrl/bcm/Kconfig +++ b/drivers/pinctrl/bcm/Kconfig @@ -9,6 +9,7 @@ config PINCTRL_BCM281XX select PINCONF select GENERIC_PINCONF select REGMAP_MMIO + default ARCH_BCM_MOBILE help Say Y here to support Broadcom BCM281xx pinctrl driver, which is used for the BCM281xx SoC family, including BCM11130, BCM11140, BCM11351, -- cgit v0.10.2 From e87623cb3b879b73e807c340d61f1dfc270b5cc6 Mon Sep 17 00:00:00 2001 From: Jens Kuske Date: Fri, 4 Dec 2015 22:24:41 +0100 Subject: pinctrl: sunxi: Add H3 PIO controller support The H3 uses the same pin controller as previous SoC's from Allwinner. Add support for the pins controlled by the main PIO controller. Signed-off-by: Jens Kuske Acked-by: Rob Herring Acked-by: Maxime Ripard Signed-off-by: Linus Walleij diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt index b321b26..e6ba602 100644 --- a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt @@ -18,6 +18,7 @@ Required properties: "allwinner,sun8i-a23-r-pinctrl" "allwinner,sun8i-a33-pinctrl" "allwinner,sun8i-a83t-pinctrl" + "allwinner,sun8i-h3-pinctrl" - reg: Should contain the register physical address and length for the pin controller. diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig index e68fd95..89ab7f5 100644 --- a/drivers/pinctrl/sunxi/Kconfig +++ b/drivers/pinctrl/sunxi/Kconfig @@ -51,6 +51,10 @@ config PINCTRL_SUN8I_A23_R depends on RESET_CONTROLLER select PINCTRL_SUNXI_COMMON +config PINCTRL_SUN8I_H3 + def_bool MACH_SUN8I + select PINCTRL_SUNXI_COMMON + config PINCTRL_SUN9I_A80 def_bool MACH_SUN9I select PINCTRL_SUNXI_COMMON diff --git a/drivers/pinctrl/sunxi/Makefile b/drivers/pinctrl/sunxi/Makefile index e080290..6bd818e 100644 --- a/drivers/pinctrl/sunxi/Makefile +++ b/drivers/pinctrl/sunxi/Makefile @@ -13,4 +13,5 @@ obj-$(CONFIG_PINCTRL_SUN8I_A23) += pinctrl-sun8i-a23.o obj-$(CONFIG_PINCTRL_SUN8I_A23_R) += pinctrl-sun8i-a23-r.o obj-$(CONFIG_PINCTRL_SUN8I_A33) += pinctrl-sun8i-a33.o obj-$(CONFIG_PINCTRL_SUN8I_A83T) += pinctrl-sun8i-a83t.o +obj-$(CONFIG_PINCTRL_SUN8I_H3) += pinctrl-sun8i-h3.o obj-$(CONFIG_PINCTRL_SUN9I_A80) += pinctrl-sun9i-a80.o diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-h3.c b/drivers/pinctrl/sunxi/pinctrl-sun8i-h3.c new file mode 100644 index 0000000..77d4cf0 --- /dev/null +++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-h3.c @@ -0,0 +1,515 @@ +/* + * Allwinner H3 SoCs pinctrl driver. + * + * Copyright (C) 2015 Jens Kuske + * + * Based on pinctrl-sun8i-a23.c, which is: + * Copyright (C) 2014 Chen-Yu Tsai + * Copyright (C) 2014 Maxime Ripard + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include +#include +#include +#include +#include + +#include "pinctrl-sunxi.h" + +static const struct sunxi_desc_pin sun8i_h3_pins[] = { + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart2"), /* TX */ + SUNXI_FUNCTION(0x3, "jtag"), /* MS */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)), /* PA_EINT0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart2"), /* RX */ + SUNXI_FUNCTION(0x3, "jtag"), /* CK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)), /* PA_EINT1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart2"), /* RTS */ + SUNXI_FUNCTION(0x3, "jtag"), /* DO */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)), /* PA_EINT2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart2"), /* CTS */ + SUNXI_FUNCTION(0x3, "jtag"), /* DI */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)), /* PA_EINT3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart0"), /* TX */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)), /* PA_EINT4 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart0"), /* RX */ + SUNXI_FUNCTION(0x3, "pwm0"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)), /* PA_EINT5 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "sim"), /* PWREN */ + SUNXI_FUNCTION(0x3, "pwm1"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)), /* PA_EINT6 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "sim"), /* CLK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)), /* PA_EINT7 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 8), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "sim"), /* DATA */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)), /* PA_EINT8 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 9), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "sim"), /* RST */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)), /* PA_EINT9 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 10), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "sim"), /* DET */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)), /* PA_EINT10 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 11), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c0"), /* SCK */ + SUNXI_FUNCTION(0x3, "di"), /* TX */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 11)), /* PA_EINT11 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 12), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c0"), /* SDA */ + SUNXI_FUNCTION(0x3, "di"), /* RX */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 12)), /* PA_EINT12 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 13), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi1"), /* CS */ + SUNXI_FUNCTION(0x3, "uart3"), /* TX */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 13)), /* PA_EINT13 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 14), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi1"), /* CLK */ + SUNXI_FUNCTION(0x3, "uart3"), /* RX */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 14)), /* PA_EINT14 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 15), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */ + SUNXI_FUNCTION(0x3, "uart3"), /* RTS */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 15)), /* PA_EINT15 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 16), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi1"), /* MISO */ + SUNXI_FUNCTION(0x3, "uart3"), /* CTS */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 16)), /* PA_EINT16 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 17), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spdif"), /* OUT */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 17)), /* PA_EINT17 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 18), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s0"), /* SYNC */ + SUNXI_FUNCTION(0x3, "i2c1"), /* SCK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 18)), /* PA_EINT18 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 19), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s0"), /* CLK */ + SUNXI_FUNCTION(0x3, "i2c1"), /* SDA */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 19)), /* PA_EINT19 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 20), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s0"), /* DOUT */ + SUNXI_FUNCTION(0x3, "sim"), /* VPPEN */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 20)), /* PA_EINT20 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 21), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s0"), /* DIN */ + SUNXI_FUNCTION(0x3, "sim"), /* VPPPP */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 21)), /* PA_EINT21 */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* WE */ + SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* ALE */ + SUNXI_FUNCTION(0x3, "spi0")), /* MISO */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* CLE */ + SUNXI_FUNCTION(0x3, "spi0")), /* CLK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* CE1 */ + SUNXI_FUNCTION(0x3, "spi0")), /* CS */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0")), /* CE0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* RE */ + SUNXI_FUNCTION(0x3, "mmc2")), /* CLK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* RB0 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* CMD */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0")), /* RB1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* DQ0 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* DQ1 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* DQ2 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* DQ3 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* DQ4 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D4 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* DQ5 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D5 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand"), /* DQ6 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D6 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand"), /* DQ7 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D7 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand"), /* DQS */ + SUNXI_FUNCTION(0x3, "mmc2")), /* RST */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac")), /* RXD3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac")), /* RXD2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac")), /* RXD1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac")), /* RXD0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac")), /* RXCK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac")), /* RXCTL/RXDV */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac")), /* RXERR */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac")), /* TXD3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 8), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac")), /* TXD2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 9), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac")), /* TXD1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac")), /* TXD0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac")), /* CRS */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac")), /* TXCK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac")), /* TXCTL/TXEN */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac")), /* TXERR */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac")), /* CLKIN/COL */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 16), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac")), /* MDC */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 17), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac")), /* MDIO */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* PCLK */ + SUNXI_FUNCTION(0x3, "ts")), /* CLK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* MCLK */ + SUNXI_FUNCTION(0x3, "ts")), /* ERR */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* HSYNC */ + SUNXI_FUNCTION(0x3, "ts")), /* SYNC */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* VSYNC */ + SUNXI_FUNCTION(0x3, "ts")), /* DVLD */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D0 */ + SUNXI_FUNCTION(0x3, "ts")), /* D0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D1 */ + SUNXI_FUNCTION(0x3, "ts")), /* D1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D2 */ + SUNXI_FUNCTION(0x3, "ts")), /* D2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D3 */ + SUNXI_FUNCTION(0x3, "ts")), /* D3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D4 */ + SUNXI_FUNCTION(0x3, "ts")), /* D4 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D5 */ + SUNXI_FUNCTION(0x3, "ts")), /* D5 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D6 */ + SUNXI_FUNCTION(0x3, "ts")), /* D6 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D7 */ + SUNXI_FUNCTION(0x3, "ts")), /* D7 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 12), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* SCK */ + SUNXI_FUNCTION(0x3, "i2c2")), /* SCK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 13), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* SDA */ + SUNXI_FUNCTION(0x3, "i2c2")), /* SDA */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 14), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 15), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out")), + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */ + SUNXI_FUNCTION(0x3, "jtag")), /* MS */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */ + SUNXI_FUNCTION(0x3, "jtag")), /* DI */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */ + SUNXI_FUNCTION(0x3, "uart0")), /* TX */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */ + SUNXI_FUNCTION(0x3, "jtag")), /* DO */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */ + SUNXI_FUNCTION(0x3, "uart0")), /* RX */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */ + SUNXI_FUNCTION(0x3, "jtag")), /* CK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out")), + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 0)), /* PG_EINT0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 1)), /* PG_EINT1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc1"), /* D0 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 2)), /* PG_EINT2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc1"), /* D1 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 3)), /* PG_EINT3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc1"), /* D2 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 4)), /* PG_EINT4 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc1"), /* D3 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 5)), /* PG_EINT5 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart1"), /* TX */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 6)), /* PG_EINT6 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart1"), /* RX */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 7)), /* PG_EINT7 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart1"), /* RTS */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 8)), /* PG_EINT8 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart1"), /* CTS */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 9)), /* PG_EINT9 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s1"), /* SYNC */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 10)), /* PG_EINT10 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s1"), /* CLK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 11)), /* PG_EINT11 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s1"), /* DOUT */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 12)), /* PG_EINT12 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 13), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s1"), /* DIN */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 13)), /* PG_EINT13 */ +}; + +static const struct sunxi_pinctrl_desc sun8i_h3_pinctrl_data = { + .pins = sun8i_h3_pins, + .npins = ARRAY_SIZE(sun8i_h3_pins), + .irq_banks = 2, +}; + +static int sun8i_h3_pinctrl_probe(struct platform_device *pdev) +{ + return sunxi_pinctrl_init(pdev, + &sun8i_h3_pinctrl_data); +} + +static const struct of_device_id sun8i_h3_pinctrl_match[] = { + { .compatible = "allwinner,sun8i-h3-pinctrl", }, + {} +}; + +static struct platform_driver sun8i_h3_pinctrl_driver = { + .probe = sun8i_h3_pinctrl_probe, + .driver = { + .name = "sun8i-h3-pinctrl", + .of_match_table = sun8i_h3_pinctrl_match, + }, +}; +builtin_platform_driver(sun8i_h3_pinctrl_driver); -- cgit v0.10.2 From fea0fe60527667282913cf9f2becb5f7c67d6185 Mon Sep 17 00:00:00 2001 From: Jeffy Chen Date: Wed, 9 Dec 2015 17:04:06 +0800 Subject: pinctrl: rockchip: add support for the rk3228 The pinctrl of rk3228 is much the same as rk3288's, but without pmu. Signed-off-by: Jeffy Chen Reviewed-by: Heiko Stuebner Acked-by: Rob Herring Signed-off-by: Linus Walleij diff --git a/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt index 391ef4b..0cd701b 100644 --- a/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt @@ -21,7 +21,8 @@ defined as gpio sub-nodes of the pinmux controller. Required properties for iomux controller: - compatible: one of "rockchip,rk2928-pinctrl", "rockchip,rk3066a-pinctrl" "rockchip,rk3066b-pinctrl", "rockchip,rk3188-pinctrl" - "rockchip,rk3288-pinctrl", "rockchip,rk3368-pinctrl" + "rockchip,rk3228-pinctrl", "rockchip,rk3288-pinctrl" + "rockchip,rk3368-pinctrl" - rockchip,grf: phandle referencing a syscon providing the "general register files" diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c index a065112..faab36e 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -614,6 +614,40 @@ static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, } } +#define RK3228_PULL_OFFSET 0x100 + +static void rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, + int pin_num, struct regmap **regmap, + int *reg, u8 *bit) +{ + struct rockchip_pinctrl *info = bank->drvdata; + + *regmap = info->regmap_base; + *reg = RK3228_PULL_OFFSET; + *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; + *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); + + *bit = (pin_num % RK3188_PULL_PINS_PER_REG); + *bit *= RK3188_PULL_BITS_PER_PIN; +} + +#define RK3228_DRV_GRF_OFFSET 0x200 + +static void rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, + int pin_num, struct regmap **regmap, + int *reg, u8 *bit) +{ + struct rockchip_pinctrl *info = bank->drvdata; + + *regmap = info->regmap_base; + *reg = RK3228_DRV_GRF_OFFSET; + *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; + *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); + + *bit = (pin_num % RK3288_DRV_PINS_PER_REG); + *bit *= RK3288_DRV_BITS_PER_PIN; +} + #define RK3368_PULL_GRF_OFFSET 0x100 #define RK3368_PULL_PMU_OFFSET 0x10 @@ -2143,6 +2177,23 @@ static struct rockchip_pin_ctrl rk3188_pin_ctrl = { .pull_calc_reg = rk3188_calc_pull_reg_and_bit, }; +static struct rockchip_pin_bank rk3228_pin_banks[] = { + PIN_BANK(0, 32, "gpio0"), + PIN_BANK(1, 32, "gpio1"), + PIN_BANK(2, 32, "gpio2"), + PIN_BANK(3, 32, "gpio3"), +}; + +static struct rockchip_pin_ctrl rk3228_pin_ctrl = { + .pin_banks = rk3228_pin_banks, + .nr_banks = ARRAY_SIZE(rk3228_pin_banks), + .label = "RK3228-GPIO", + .type = RK3288, + .grf_mux_offset = 0x0, + .pull_calc_reg = rk3228_calc_pull_reg_and_bit, + .drv_calc_reg = rk3228_calc_drv_reg_and_bit, +}; + static struct rockchip_pin_bank rk3288_pin_banks[] = { PIN_BANK_IOMUX_FLAGS(0, 24, "gpio0", IOMUX_SOURCE_PMU, IOMUX_SOURCE_PMU, @@ -2220,6 +2271,8 @@ static const struct of_device_id rockchip_pinctrl_dt_match[] = { .data = (void *)&rk3066b_pin_ctrl }, { .compatible = "rockchip,rk3188-pinctrl", .data = (void *)&rk3188_pin_ctrl }, + { .compatible = "rockchip,rk3228-pinctrl", + .data = (void *)&rk3228_pin_ctrl }, { .compatible = "rockchip,rk3288-pinctrl", .data = (void *)&rk3288_pin_ctrl }, { .compatible = "rockchip,rk3368-pinctrl", -- cgit v0.10.2 From e670b29815f301e47e81d42006c80be6b7aff01d Mon Sep 17 00:00:00 2001 From: Robert Jarzmik Date: Sat, 12 Dec 2015 22:43:05 +0100 Subject: pinctrl: pxa: pxa2xx: add pin control skeleton The wrong free functions were used to release temporary buffers. This didn't show up in the normal driver's life. Yet in suspend to RAM, the managed resource list is walked, and as memory was released, the list is corrupted and make the kernel Oops. Signed-off-by: Robert Jarzmik Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/pxa/pinctrl-pxa2xx.c b/drivers/pinctrl/pxa/pinctrl-pxa2xx.c index e019144..d90e205 100644 --- a/drivers/pinctrl/pxa/pinctrl-pxa2xx.c +++ b/drivers/pinctrl/pxa/pinctrl-pxa2xx.c @@ -292,7 +292,7 @@ static int pxa2xx_build_functions(struct pxa_pinctrl *pctl) if (!pctl->functions) return -ENOMEM; - kfree(functions); + devm_kfree(pctl->dev, functions); return 0; } @@ -328,7 +328,7 @@ static int pxa2xx_build_groups(struct pxa_pinctrl *pctl) memcpy(func->groups, gtmp, ngroups * sizeof(*gtmp)); } - kfree(gtmp); + devm_kfree(pctl->dev, gtmp); return 0; } -- cgit v0.10.2 From 57a9d1acd0695aa24782a3b10124cbe7e6f7faa3 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 26 Nov 2015 14:12:36 +0100 Subject: pinctrl: sh-pfc: r8a7779: Add SCIF_CLK support Add pins, groups, and a function for SCIF_CLK, which is the external clock source for the Baud Rate Generator for External Clock (BRG) on SCIF. Signed-off-by: Geert Uytterhoeven Acked-by: Laurent Pinchart Acked-by: Linus Walleij diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c index afc5d80..bd17ecc 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c @@ -2282,6 +2282,35 @@ static const unsigned int scif5_clk_d_pins[] = { static const unsigned int scif5_clk_d_mux[] = { SCK5_D_MARK, }; +/* - SCIF Clock ------------------------------------------------------------- */ +static const unsigned int scif_clk_pins[] = { + /* SCIF_CLK */ + RCAR_GP_PIN(4, 28), +}; +static const unsigned int scif_clk_mux[] = { + SCIF_CLK_MARK, +}; +static const unsigned int scif_clk_b_pins[] = { + /* SCIF_CLK */ + RCAR_GP_PIN(4, 5), +}; +static const unsigned int scif_clk_b_mux[] = { + SCIF_CLK_B_MARK, +}; +static const unsigned int scif_clk_c_pins[] = { + /* SCIF_CLK */ + RCAR_GP_PIN(4, 18), +}; +static const unsigned int scif_clk_c_mux[] = { + SCIF_CLK_C_MARK, +}; +static const unsigned int scif_clk_d_pins[] = { + /* SCIF_CLK */ + RCAR_GP_PIN(2, 29), +}; +static const unsigned int scif_clk_d_mux[] = { + SCIF_CLK_D_MARK, +}; /* - SDHI0 ------------------------------------------------------------------ */ static const unsigned int sdhi0_data1_pins[] = { /* D0 */ @@ -2693,6 +2722,10 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(scif5_clk_c), SH_PFC_PIN_GROUP(scif5_data_d), SH_PFC_PIN_GROUP(scif5_clk_d), + SH_PFC_PIN_GROUP(scif_clk), + SH_PFC_PIN_GROUP(scif_clk_b), + SH_PFC_PIN_GROUP(scif_clk_c), + SH_PFC_PIN_GROUP(scif_clk_d), SH_PFC_PIN_GROUP(sdhi0_data1), SH_PFC_PIN_GROUP(sdhi0_data4), SH_PFC_PIN_GROUP(sdhi0_ctrl), @@ -2902,6 +2935,13 @@ static const char * const scif5_groups[] = { "scif5_clk_d", }; +static const char * const scif_clk_groups[] = { + "scif_clk", + "scif_clk_b", + "scif_clk_c", + "scif_clk_d", +}; + static const char * const sdhi0_groups[] = { "sdhi0_data1", "sdhi0_data4", @@ -2997,6 +3037,7 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(scif3), SH_PFC_FUNCTION(scif4), SH_PFC_FUNCTION(scif5), + SH_PFC_FUNCTION(scif_clk), SH_PFC_FUNCTION(usb0), SH_PFC_FUNCTION(usb1), SH_PFC_FUNCTION(usb2), -- cgit v0.10.2 From 53ec9ccd1c62b644d81674e013b1800dd88ec92b Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 26 Nov 2015 14:13:45 +0100 Subject: pinctrl: sh-pfc: r8a7790: Add SCIF_CLK support Add pins, groups, and a function for SCIF_CLK, which is the external clock source for the Baud Rate Generator for External Clock (BRG) on (H)SCIF. Signed-off-by: Geert Uytterhoeven Acked-by: Laurent Pinchart Acked-by: Linus Walleij diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c index d99a5bc..a8b629b 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c @@ -3219,6 +3219,21 @@ static const unsigned int scifb2_data_c_pins[] = { static const unsigned int scifb2_data_c_mux[] = { SCIFB2_RXD_C_MARK, SCIFB2_TXD_C_MARK, }; +/* - SCIF Clock ------------------------------------------------------------- */ +static const unsigned int scif_clk_pins[] = { + /* SCIF_CLK */ + RCAR_GP_PIN(4, 26), +}; +static const unsigned int scif_clk_mux[] = { + SCIF_CLK_MARK, +}; +static const unsigned int scif_clk_b_pins[] = { + /* SCIF_CLK */ + RCAR_GP_PIN(5, 4), +}; +static const unsigned int scif_clk_b_mux[] = { + SCIF_CLK_B_MARK, +}; /* - SDHI0 ------------------------------------------------------------------ */ static const unsigned int sdhi0_data1_pins[] = { /* D0 */ @@ -4122,6 +4137,8 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(scifb2_clk_b), SH_PFC_PIN_GROUP(scifb2_ctrl_b), SH_PFC_PIN_GROUP(scifb2_data_c), + SH_PFC_PIN_GROUP(scif_clk), + SH_PFC_PIN_GROUP(scif_clk_b), SH_PFC_PIN_GROUP(sdhi0_data1), SH_PFC_PIN_GROUP(sdhi0_data4), SH_PFC_PIN_GROUP(sdhi0_ctrl), @@ -4538,6 +4555,11 @@ static const char * const scifb2_groups[] = { "scifb2_data_c", }; +static const char * const scif_clk_groups[] = { + "scif_clk", + "scif_clk_b", +}; + static const char * const sdhi0_groups[] = { "sdhi0_data1", "sdhi0_data4", @@ -4712,6 +4734,7 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(scifb0), SH_PFC_FUNCTION(scifb1), SH_PFC_FUNCTION(scifb2), + SH_PFC_FUNCTION(scif_clk), SH_PFC_FUNCTION(sdhi0), SH_PFC_FUNCTION(sdhi1), SH_PFC_FUNCTION(sdhi2), -- cgit v0.10.2 From ed66700c031917be7b5527a41ac572a1c714f0ed Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 26 Nov 2015 14:14:22 +0100 Subject: pinctrl: sh-pfc: r8a7794: Add SCIF_CLK support Add pins, groups, and a function for SCIF_CLK, which is the external clock source for the Baud Rate Generator for External Clock (BRG) on (H)SCIF. Signed-off-by: Geert Uytterhoeven Acked-by: Laurent Pinchart Acked-by: Linus Walleij diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7794.c b/drivers/pinctrl/sh-pfc/pfc-r8a7794.c index 10995fa..3718c78 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7794.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7794.c @@ -2625,6 +2625,21 @@ static const unsigned int scifb2_ctrl_pins[] = { static const unsigned int scifb2_ctrl_mux[] = { SCIFB2_RTS_N_MARK, SCIFB2_CTS_N_MARK, }; +/* - SCIF Clock ------------------------------------------------------------- */ +static const unsigned int scif_clk_pins[] = { + /* SCIF_CLK */ + RCAR_GP_PIN(1, 23), +}; +static const unsigned int scif_clk_mux[] = { + SCIF_CLK_MARK, +}; +static const unsigned int scif_clk_b_pins[] = { + /* SCIF_CLK */ + RCAR_GP_PIN(3, 29), +}; +static const unsigned int scif_clk_b_mux[] = { + SCIF_CLK_B_MARK, +}; /* - SDHI0 ------------------------------------------------------------------ */ static const unsigned int sdhi0_data1_pins[] = { /* D0 */ @@ -3052,6 +3067,8 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(scifb2_data), SH_PFC_PIN_GROUP(scifb2_clk), SH_PFC_PIN_GROUP(scifb2_ctrl), + SH_PFC_PIN_GROUP(scif_clk), + SH_PFC_PIN_GROUP(scif_clk_b), SH_PFC_PIN_GROUP(sdhi0_data1), SH_PFC_PIN_GROUP(sdhi0_data4), SH_PFC_PIN_GROUP(sdhi0_ctrl), @@ -3335,6 +3352,11 @@ static const char * const scifb2_groups[] = { "scifb2_ctrl", }; +static const char * const scif_clk_groups[] = { + "scif_clk", + "scif_clk_b", +}; + static const char * const sdhi0_groups[] = { "sdhi0_data1", "sdhi0_data4", @@ -3422,6 +3444,7 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(scifb0), SH_PFC_FUNCTION(scifb1), SH_PFC_FUNCTION(scifb2), + SH_PFC_FUNCTION(scif_clk), SH_PFC_FUNCTION(sdhi0), SH_PFC_FUNCTION(sdhi1), SH_PFC_FUNCTION(sdhi2), -- cgit v0.10.2 From 20cacae155f648bd68af15ca9e083e6f7e271124 Mon Sep 17 00:00:00 2001 From: Takeshi Kihara Date: Thu, 10 Dec 2015 18:07:12 +0100 Subject: pinctrl: sh-pfc: r8a7795: Add SDHI support Add SDHI[0-3] pinmux support to r8a7795 SoC. Signed-off-by: Takeshi Kihara Signed-off-by: Dirk Behme Reviewed-by: Geert Uytterhoeven Signed-off-by: Geert Uytterhoeven diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c index 35e0172..1e15d9b 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c @@ -2674,6 +2674,212 @@ static const unsigned int scif5_clk_pins[] = { static const unsigned int scif5_clk_mux[] = { SCK5_MARK, }; +/* - SDHI0 ------------------------------------------------------------------ */ +static const unsigned int sdhi0_data1_pins[] = { + /* D0 */ + RCAR_GP_PIN(3, 2), +}; +static const unsigned int sdhi0_data1_mux[] = { + SD0_DAT0_MARK, +}; +static const unsigned int sdhi0_data4_pins[] = { + /* D[0:3] */ + RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), + RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), +}; +static const unsigned int sdhi0_data4_mux[] = { + SD0_DAT0_MARK, SD0_DAT1_MARK, + SD0_DAT2_MARK, SD0_DAT3_MARK, +}; +static const unsigned int sdhi0_ctrl_pins[] = { + /* CLK, CMD */ + RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1), +}; +static const unsigned int sdhi0_ctrl_mux[] = { + SD0_CLK_MARK, SD0_CMD_MARK, +}; +static const unsigned int sdhi0_cd_pins[] = { + /* CD */ + RCAR_GP_PIN(3, 12), +}; +static const unsigned int sdhi0_cd_mux[] = { + SD0_CD_MARK, +}; +static const unsigned int sdhi0_wp_pins[] = { + /* WP */ + RCAR_GP_PIN(3, 13), +}; +static const unsigned int sdhi0_wp_mux[] = { + SD0_WP_MARK, +}; +/* - SDHI1 ------------------------------------------------------------------ */ +static const unsigned int sdhi1_data1_pins[] = { + /* D0 */ + RCAR_GP_PIN(3, 8), +}; +static const unsigned int sdhi1_data1_mux[] = { + SD1_DAT0_MARK, +}; +static const unsigned int sdhi1_data4_pins[] = { + /* D[0:3] */ + RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), + RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), +}; +static const unsigned int sdhi1_data4_mux[] = { + SD1_DAT0_MARK, SD1_DAT1_MARK, + SD1_DAT2_MARK, SD1_DAT3_MARK, +}; +static const unsigned int sdhi1_ctrl_pins[] = { + /* CLK, CMD */ + RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7), +}; +static const unsigned int sdhi1_ctrl_mux[] = { + SD1_CLK_MARK, SD1_CMD_MARK, +}; +static const unsigned int sdhi1_cd_pins[] = { + /* CD */ + RCAR_GP_PIN(3, 14), +}; +static const unsigned int sdhi1_cd_mux[] = { + SD1_CD_MARK, +}; +static const unsigned int sdhi1_wp_pins[] = { + /* WP */ + RCAR_GP_PIN(3, 15), +}; +static const unsigned int sdhi1_wp_mux[] = { + SD1_WP_MARK, +}; +/* - SDHI2 ------------------------------------------------------------------ */ +static const unsigned int sdhi2_data1_pins[] = { + /* D0 */ + RCAR_GP_PIN(4, 2), +}; +static const unsigned int sdhi2_data1_mux[] = { + SD2_DAT0_MARK, +}; +static const unsigned int sdhi2_data4_pins[] = { + /* D[0:3] */ + RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3), + RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5), +}; +static const unsigned int sdhi2_data4_mux[] = { + SD2_DAT0_MARK, SD2_DAT1_MARK, + SD2_DAT2_MARK, SD2_DAT3_MARK, +}; +static const unsigned int sdhi2_data8_pins[] = { + /* D[0:7] */ + RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3), + RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5), + RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), + RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), +}; +static const unsigned int sdhi2_data8_mux[] = { + SD2_DAT0_MARK, SD2_DAT1_MARK, + SD2_DAT2_MARK, SD2_DAT3_MARK, + SD2_DAT4_MARK, SD2_DAT5_MARK, + SD2_DAT6_MARK, SD2_DAT7_MARK, +}; +static const unsigned int sdhi2_ctrl_pins[] = { + /* CLK, CMD */ + RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1), +}; +static const unsigned int sdhi2_ctrl_mux[] = { + SD2_CLK_MARK, SD2_CMD_MARK, +}; +static const unsigned int sdhi2_cd_a_pins[] = { + /* CD */ + RCAR_GP_PIN(4, 13), +}; +static const unsigned int sdhi2_cd_a_mux[] = { + SD2_CD_A_MARK, +}; +static const unsigned int sdhi2_cd_b_pins[] = { + /* CD */ + RCAR_GP_PIN(5, 10), +}; +static const unsigned int sdhi2_cd_b_mux[] = { + SD2_CD_B_MARK, +}; +static const unsigned int sdhi2_wp_a_pins[] = { + /* WP */ + RCAR_GP_PIN(4, 14), +}; +static const unsigned int sdhi2_wp_a_mux[] = { + SD2_WP_A_MARK, +}; +static const unsigned int sdhi2_wp_b_pins[] = { + /* WP */ + RCAR_GP_PIN(5, 11), +}; +static const unsigned int sdhi2_wp_b_mux[] = { + SD2_WP_B_MARK, +}; +static const unsigned int sdhi2_ds_pins[] = { + /* DS */ + RCAR_GP_PIN(4, 6), +}; +static const unsigned int sdhi2_ds_mux[] = { + SD2_DS_MARK, +}; +/* - SDHI3 ------------------------------------------------------------------ */ +static const unsigned int sdhi3_data1_pins[] = { + /* D0 */ + RCAR_GP_PIN(4, 9), +}; +static const unsigned int sdhi3_data1_mux[] = { + SD3_DAT0_MARK, +}; +static const unsigned int sdhi3_data4_pins[] = { + /* D[0:3] */ + RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10), + RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12), +}; +static const unsigned int sdhi3_data4_mux[] = { + SD3_DAT0_MARK, SD3_DAT1_MARK, + SD3_DAT2_MARK, SD3_DAT3_MARK, +}; +static const unsigned int sdhi3_data8_pins[] = { + /* D[0:7] */ + RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10), + RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12), + RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14), + RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16), +}; +static const unsigned int sdhi3_data8_mux[] = { + SD3_DAT0_MARK, SD3_DAT1_MARK, + SD3_DAT2_MARK, SD3_DAT3_MARK, + SD3_DAT4_MARK, SD3_DAT5_MARK, + SD3_DAT6_MARK, SD3_DAT7_MARK, +}; +static const unsigned int sdhi3_ctrl_pins[] = { + /* CLK, CMD */ + RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8), +}; +static const unsigned int sdhi3_ctrl_mux[] = { + SD3_CLK_MARK, SD3_CMD_MARK, +}; +static const unsigned int sdhi3_cd_pins[] = { + /* CD */ + RCAR_GP_PIN(4, 15), +}; +static const unsigned int sdhi3_cd_mux[] = { + SD3_CD_MARK, +}; +static const unsigned int sdhi3_wp_pins[] = { + /* WP */ + RCAR_GP_PIN(4, 16), +}; +static const unsigned int sdhi3_wp_mux[] = { + SD3_WP_MARK, +}; +static const unsigned int sdhi3_ds_pins[] = { + /* DS */ + RCAR_GP_PIN(4, 17), +}; +static const unsigned int sdhi3_ds_mux[] = { + SD3_DS_MARK, +}; /* - SCIF Clock ------------------------------------------------------------- */ static const unsigned int scif_clk_a_pins[] = { @@ -3047,6 +3253,32 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(scif5_clk), SH_PFC_PIN_GROUP(scif_clk_a), SH_PFC_PIN_GROUP(scif_clk_b), + SH_PFC_PIN_GROUP(sdhi0_data1), + SH_PFC_PIN_GROUP(sdhi0_data4), + SH_PFC_PIN_GROUP(sdhi0_ctrl), + SH_PFC_PIN_GROUP(sdhi0_cd), + SH_PFC_PIN_GROUP(sdhi0_wp), + SH_PFC_PIN_GROUP(sdhi1_data1), + SH_PFC_PIN_GROUP(sdhi1_data4), + SH_PFC_PIN_GROUP(sdhi1_ctrl), + SH_PFC_PIN_GROUP(sdhi1_cd), + SH_PFC_PIN_GROUP(sdhi1_wp), + SH_PFC_PIN_GROUP(sdhi2_data1), + SH_PFC_PIN_GROUP(sdhi2_data4), + SH_PFC_PIN_GROUP(sdhi2_data8), + SH_PFC_PIN_GROUP(sdhi2_ctrl), + SH_PFC_PIN_GROUP(sdhi2_cd_a), + SH_PFC_PIN_GROUP(sdhi2_wp_a), + SH_PFC_PIN_GROUP(sdhi2_cd_b), + SH_PFC_PIN_GROUP(sdhi2_wp_b), + SH_PFC_PIN_GROUP(sdhi2_ds), + SH_PFC_PIN_GROUP(sdhi3_data1), + SH_PFC_PIN_GROUP(sdhi3_data4), + SH_PFC_PIN_GROUP(sdhi3_data8), + SH_PFC_PIN_GROUP(sdhi3_ctrl), + SH_PFC_PIN_GROUP(sdhi3_cd), + SH_PFC_PIN_GROUP(sdhi3_wp), + SH_PFC_PIN_GROUP(sdhi3_ds), SH_PFC_PIN_GROUP(ssi0_data), SH_PFC_PIN_GROUP(ssi01239_ctrl), SH_PFC_PIN_GROUP(ssi1_data_a), @@ -3315,6 +3547,44 @@ static const char * const scif_clk_groups[] = { "scif_clk_b", }; +static const char * const sdhi0_groups[] = { + "sdhi0_data1", + "sdhi0_data4", + "sdhi0_ctrl", + "sdhi0_cd", + "sdhi0_wp", +}; + +static const char * const sdhi1_groups[] = { + "sdhi1_data1", + "sdhi1_data4", + "sdhi1_ctrl", + "sdhi1_cd", + "sdhi1_wp", +}; + +static const char * const sdhi2_groups[] = { + "sdhi2_data1", + "sdhi2_data4", + "sdhi2_data8", + "sdhi2_ctrl", + "sdhi2_cd_a", + "sdhi2_wp_a", + "sdhi2_cd_b", + "sdhi2_wp_b", + "sdhi2_ds", +}; + +static const char * const sdhi3_groups[] = { + "sdhi3_data1", + "sdhi3_data4", + "sdhi3_data8", + "sdhi3_ctrl", + "sdhi3_cd", + "sdhi3_wp", + "sdhi3_ds", +}; + static const char * const ssi_groups[] = { "ssi0_data", "ssi01239_ctrl", @@ -3365,6 +3635,10 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(scif4), SH_PFC_FUNCTION(scif5), SH_PFC_FUNCTION(scif_clk), + SH_PFC_FUNCTION(sdhi0), + SH_PFC_FUNCTION(sdhi1), + SH_PFC_FUNCTION(sdhi2), + SH_PFC_FUNCTION(sdhi3), SH_PFC_FUNCTION(ssi), }; -- cgit v0.10.2 From 34dc4e16af01fd6e300b894d67d62d966526a99e Mon Sep 17 00:00:00 2001 From: Takeshi Kihara Date: Mon, 14 Dec 2015 16:42:36 +0100 Subject: pinctrl: sh-pfc: r8a7795: Add SATA support This patch adds SATA0 pinmux support to r8a7795 SoC. Signed-off-by: Takeshi Kihara [uli: adjusted for new PFC driver] Signed-off-by: Ulrich Hecht Signed-off-by: Geert Uytterhoeven diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c index 1e15d9b..ce4f5cd 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c @@ -2492,6 +2492,22 @@ static const unsigned int msiof3_rxd_d_mux[] = { MSIOF3_RXD_D_MARK, }; +/* - SATA --------------------------------------------------------------------*/ +static const unsigned int sata0_devslp_a_pins[] = { + /* DEVSLP */ + RCAR_GP_PIN(6, 16), +}; +static const unsigned int sata0_devslp_a_mux[] = { + SATA_DEVSLP_A_MARK, +}; +static const unsigned int sata0_devslp_b_pins[] = { + /* DEVSLP */ + RCAR_GP_PIN(4, 6), +}; +static const unsigned int sata0_devslp_b_mux[] = { + SATA_DEVSLP_B_MARK, +}; + /* - SCIF0 ------------------------------------------------------------------ */ static const unsigned int scif0_data_pins[] = { /* RX, TX */ @@ -3226,6 +3242,8 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(msiof3_ss1_d), SH_PFC_PIN_GROUP(msiof3_txd_d), SH_PFC_PIN_GROUP(msiof3_rxd_d), + SH_PFC_PIN_GROUP(sata0_devslp_a), + SH_PFC_PIN_GROUP(sata0_devslp_b), SH_PFC_PIN_GROUP(scif0_data), SH_PFC_PIN_GROUP(scif0_clk), SH_PFC_PIN_GROUP(scif0_ctrl), @@ -3499,6 +3517,11 @@ static const char * const msiof3_groups[] = { "msiof3_rxd_d", }; +static const char * const sata0_groups[] = { + "sata0_devslp_a", + "sata0_devslp_b", +}; + static const char * const scif0_groups[] = { "scif0_data", "scif0_clk", @@ -3628,6 +3651,7 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(msiof1), SH_PFC_FUNCTION(msiof2), SH_PFC_FUNCTION(msiof3), + SH_PFC_FUNCTION(sata0), SH_PFC_FUNCTION(scif0), SH_PFC_FUNCTION(scif1), SH_PFC_FUNCTION(scif2), -- cgit v0.10.2 From 59508084e10642e8533cfd82327486ed24c73af4 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Tue, 15 Dec 2015 01:06:55 +0300 Subject: pinctrl: sh-pfc: r8a7791: add EtherAVB pin groups Add the EtherAVB pin groups to the R8A7791 PFC driver. Also add the copyright for all the Cogent Embedded's past work on this file. Signed-off-by: Sergei Shtylyov Signed-off-by: Geert Uytterhoeven diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c index c508ae4..4cfbb94 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c @@ -2,6 +2,7 @@ * r8a7791 processor support - PFC hardware block. * * Copyright (C) 2013 Renesas Electronics Corporation + * Copyright (C) 2014-2015 Cogent Embedded, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 @@ -1725,6 +1726,82 @@ static const unsigned int audio_clkout_mux[] = { AUDIO_CLKOUT_MARK, }; +/* - AVB -------------------------------------------------------------------- */ +static const unsigned int avb_link_pins[] = { + RCAR_GP_PIN(5, 14), +}; +static const unsigned int avb_link_mux[] = { + AVB_LINK_MARK, +}; +static const unsigned int avb_magic_pins[] = { + RCAR_GP_PIN(5, 11), +}; +static const unsigned int avb_magic_mux[] = { + AVB_MAGIC_MARK, +}; +static const unsigned int avb_phy_int_pins[] = { + RCAR_GP_PIN(5, 16), +}; +static const unsigned int avb_phy_int_mux[] = { + AVB_PHY_INT_MARK, +}; +static const unsigned int avb_mdio_pins[] = { + RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 9), +}; +static const unsigned int avb_mdio_mux[] = { + AVB_MDC_MARK, AVB_MDIO_MARK, +}; +static const unsigned int avb_mii_pins[] = { + RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 20), + RCAR_GP_PIN(5, 21), + + RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2), + RCAR_GP_PIN(5, 3), + + RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 10), + RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 26), RCAR_GP_PIN(5, 27), + RCAR_GP_PIN(5, 28), RCAR_GP_PIN(5, 29), +}; +static const unsigned int avb_mii_mux[] = { + AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK, + AVB_TXD3_MARK, + + AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK, + AVB_RXD3_MARK, + + AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK, + AVB_CRS_MARK, AVB_TX_EN_MARK, AVB_TX_ER_MARK, + AVB_TX_CLK_MARK, AVB_COL_MARK, +}; +static const unsigned int avb_gmii_pins[] = { + RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 20), + RCAR_GP_PIN(5, 21), RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 23), + RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25), + + RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2), + RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 5), + RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 7), + + RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 10), + RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 30), RCAR_GP_PIN(5, 17), + RCAR_GP_PIN(5, 26), RCAR_GP_PIN(5, 27), RCAR_GP_PIN(5, 28), + RCAR_GP_PIN(5, 29), +}; +static const unsigned int avb_gmii_mux[] = { + AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK, + AVB_TXD3_MARK, AVB_TXD4_MARK, AVB_TXD5_MARK, + AVB_TXD6_MARK, AVB_TXD7_MARK, + + AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK, + AVB_RXD3_MARK, AVB_RXD4_MARK, AVB_RXD5_MARK, + AVB_RXD6_MARK, AVB_RXD7_MARK, + + AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK, + AVB_CRS_MARK, AVB_GTX_CLK_MARK, AVB_GTXREFCLK_MARK, + AVB_TX_EN_MARK, AVB_TX_ER_MARK, AVB_TX_CLK_MARK, + AVB_COL_MARK, +}; + /* - CAN -------------------------------------------------------------------- */ static const unsigned int can0_data_pins[] = { @@ -4260,6 +4337,12 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(audio_clk_b_b), SH_PFC_PIN_GROUP(audio_clk_c), SH_PFC_PIN_GROUP(audio_clkout), + SH_PFC_PIN_GROUP(avb_link), + SH_PFC_PIN_GROUP(avb_magic), + SH_PFC_PIN_GROUP(avb_phy_int), + SH_PFC_PIN_GROUP(avb_mdio), + SH_PFC_PIN_GROUP(avb_mii), + SH_PFC_PIN_GROUP(avb_gmii), SH_PFC_PIN_GROUP(can0_data), SH_PFC_PIN_GROUP(can0_data_b), SH_PFC_PIN_GROUP(can0_data_c), @@ -4601,6 +4684,15 @@ static const char * const audio_clk_groups[] = { "audio_clkout", }; +static const char * const avb_groups[] = { + "avb_link", + "avb_magic", + "avb_phy_int", + "avb_mdio", + "avb_mii", + "avb_gmii", +}; + static const char * const can0_groups[] = { "can0_data", "can0_data_b", @@ -5090,6 +5182,7 @@ static const char * const vin2_groups[] = { static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(audio_clk), + SH_PFC_FUNCTION(avb), SH_PFC_FUNCTION(can0), SH_PFC_FUNCTION(can1), SH_PFC_FUNCTION(du), -- cgit v0.10.2 From 1a4ca6dd3dc8551fc0288ec76d046700366d7683 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 16 Dec 2015 08:47:11 +0100 Subject: MAINTAINERS: Add co-maintainer for Renesas Pin Controllers Add myself as a co-maintainer for Renesas Pin Controllers. Signed-off-by: Geert Uytterhoeven Acked-by: Laurent Pinchart Acked-by: Simon Horman Acked-by: Linus Walleij diff --git a/MAINTAINERS b/MAINTAINERS index e9caa4b..f625860 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -8351,6 +8351,7 @@ F: drivers/pinctrl/intel/ PIN CONTROLLER - RENESAS M: Laurent Pinchart +M: Geert Uytterhoeven L: linux-sh@vger.kernel.org S: Maintained F: drivers/pinctrl/sh-pfc/ -- cgit v0.10.2 From d4eed63bb8a3749a6cf19bbc98c943fafb4a826d Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Thu, 17 Dec 2015 14:50:45 +0100 Subject: pinctrl: fixup problematic flag This removes the set_irq_flags() call that unfortunately slipped into the BCM NSP driver. Reported-by: Stephen Rothwell Cc: Yendapally Reddy Dhananjaya Reddy Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/bcm/pinctrl-nsp-gpio.c b/drivers/pinctrl/bcm/pinctrl-nsp-gpio.c index 06b7aaf..1f66761 100644 --- a/drivers/pinctrl/bcm/pinctrl-nsp-gpio.c +++ b/drivers/pinctrl/bcm/pinctrl-nsp-gpio.c @@ -696,7 +696,6 @@ static int nsp_gpio_probe(struct platform_device *pdev) irq_set_chip_and_handler(irq, &nsp_gpio_irq_chip, handle_simple_irq); - set_irq_flags(irq, IRQF_VALID); irq_set_chip_data(irq, chip); } -- cgit v0.10.2 From 0202a111f8cc7abf9b45e6f555a707fda1fab6ab Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Mon, 21 Dec 2015 09:40:39 +0100 Subject: pinctrl: bcm/cygnys/iproc: fixup rebase issue Somehow this variable name screwed up in some rebase, fixed it. Reported-by: Stephen Rothwell Reported-by: Pramod Kumar Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/bcm/pinctrl-iproc-gpio.c b/drivers/pinctrl/bcm/pinctrl-iproc-gpio.c index 525ea13..314591a 100644 --- a/drivers/pinctrl/bcm/pinctrl-iproc-gpio.c +++ b/drivers/pinctrl/bcm/pinctrl-iproc-gpio.c @@ -637,7 +637,7 @@ static int iproc_gpio_register_pinconf(struct iproc_gpio *chip) return 0; } -static void iproc_gpio_unregister_pinconf(struct cygnus_gpio *chip) +static void iproc_gpio_unregister_pinconf(struct iproc_gpio *chip) { pinctrl_unregister(chip->pctl); } -- cgit v0.10.2 From 0eccc9cb4c1443c2665466e35f6e138381b8afd9 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Thu, 17 Dec 2015 00:39:42 +0800 Subject: pinctrl: sunxi: Add A80 special pin controller Like the previous designs, the A80 has a special pin controller for the critical pins, like the PMIC bus. Add a driver for this controller. Signed-off-by: Maxime Ripard [wens: Add A80 compatible strings to bindings doc; fix pin function names based on v1.3 datasheet; constify of_device_id table] Signed-off-by: Chen-Yu Tsai Acked-by: Rob Herring Signed-off-by: Linus Walleij diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt index e6ba602..9213b27 100644 --- a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt @@ -17,6 +17,8 @@ Required properties: "allwinner,sun8i-a23-pinctrl" "allwinner,sun8i-a23-r-pinctrl" "allwinner,sun8i-a33-pinctrl" + "allwinner,sun9i-a80-pinctrl" + "allwinner,sun9i-a80-r-pinctrl" "allwinner,sun8i-a83t-pinctrl" "allwinner,sun8i-h3-pinctrl" diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig index 89ab7f5..f8dbc8b 100644 --- a/drivers/pinctrl/sunxi/Kconfig +++ b/drivers/pinctrl/sunxi/Kconfig @@ -59,4 +59,9 @@ config PINCTRL_SUN9I_A80 def_bool MACH_SUN9I select PINCTRL_SUNXI_COMMON +config PINCTRL_SUN9I_A80_R + def_bool MACH_SUN9I + depends on RESET_CONTROLLER + select PINCTRL_SUNXI_COMMON + endif diff --git a/drivers/pinctrl/sunxi/Makefile b/drivers/pinctrl/sunxi/Makefile index 6bd818e..ef82f22 100644 --- a/drivers/pinctrl/sunxi/Makefile +++ b/drivers/pinctrl/sunxi/Makefile @@ -15,3 +15,4 @@ obj-$(CONFIG_PINCTRL_SUN8I_A33) += pinctrl-sun8i-a33.o obj-$(CONFIG_PINCTRL_SUN8I_A83T) += pinctrl-sun8i-a83t.o obj-$(CONFIG_PINCTRL_SUN8I_H3) += pinctrl-sun8i-h3.o obj-$(CONFIG_PINCTRL_SUN9I_A80) += pinctrl-sun9i-a80.o +obj-$(CONFIG_PINCTRL_SUN9I_A80_R) += pinctrl-sun9i-a80-r.o diff --git a/drivers/pinctrl/sunxi/pinctrl-sun9i-a80-r.c b/drivers/pinctrl/sunxi/pinctrl-sun9i-a80-r.c new file mode 100644 index 0000000..42547ff --- /dev/null +++ b/drivers/pinctrl/sunxi/pinctrl-sun9i-a80-r.c @@ -0,0 +1,181 @@ +/* + * Allwinner A80 SoCs special pins pinctrl driver. + * + * Copyright (C) 2014 Maxime Ripard + * Maxime Ripard + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include +#include +#include +#include +#include +#include + +#include "pinctrl-sunxi.h" + +static const struct sunxi_desc_pin sun9i_a80_r_pins[] = { + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x3, "s_uart"), /* TX */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)), /* PL_EINT0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x3, "s_uart"), /* RX */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)), /* PL_EINT1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x3, "s_jtag"), /* TMS */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)), /* PL_EINT2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x3, "s_jtag"), /* TCK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)), /* PL_EINT3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x3, "s_jtag"), /* TDO */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)), /* PL_EINT4 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x3, "s_jtag"), /* TDI */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)), /* PL_EINT5 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x3, "s_cir_rx"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)), /* PL_EINT6 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x3, "1wire"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)), /* PL_EINT7 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 8), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "s_ps2"), /* SCK1 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)), /* PL_EINT8 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 9), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "s_ps2"), /* SDA1 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)), /* PL_EINT9 */ + + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 0)), /* PM_EINT0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 1)), /* PM_EINT1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 2)), /* PM_EINT2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 3)), /* PM_EINT3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x3, "s_i2s1"), /* LRCKR */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 4)), /* PM_EINT4 */ + + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 8), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x3, "s_i2c1"), /* SCK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 8)), /* PM_EINT8 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 9), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x3, "s_i2c1"), /* SDA */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 9)), /* PM_EINT9 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 10), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "s_i2s0"), /* MCLK */ + SUNXI_FUNCTION(0x3, "s_i2s1")), /* MCLK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 11), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "s_i2s0"), /* BCLK */ + SUNXI_FUNCTION(0x3, "s_i2s1")), /* BCLK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 12), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "s_i2s0"), /* LRCK */ + SUNXI_FUNCTION(0x3, "s_i2s1")), /* LRCK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 13), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "s_i2s0"), /* DIN */ + SUNXI_FUNCTION(0x3, "s_i2s1")), /* DIN */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 14), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "s_i2s0"), /* DOUT */ + SUNXI_FUNCTION(0x3, "s_i2s1")), /* DOUT */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 15), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 15)), /* PM_EINT15 */ + + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(N, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "s_i2c0"), /* SCK */ + SUNXI_FUNCTION(0x3, "s_rsb")), /* SCK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(N, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "s_i2c0"), /* SDA */ + SUNXI_FUNCTION(0x3, "s_rsb")), /* SDA */ +}; + +static const struct sunxi_pinctrl_desc sun9i_a80_r_pinctrl_data = { + .pins = sun9i_a80_r_pins, + .npins = ARRAY_SIZE(sun9i_a80_r_pins), + .pin_base = PL_BASE, + .irq_banks = 2, +}; + +static int sun9i_a80_r_pinctrl_probe(struct platform_device *pdev) +{ + return sunxi_pinctrl_init(pdev, + &sun9i_a80_r_pinctrl_data); +} + +static const struct of_device_id sun9i_a80_r_pinctrl_match[] = { + { .compatible = "allwinner,sun9i-a80-r-pinctrl", }, + {} +}; +MODULE_DEVICE_TABLE(of, sun9i_a80_r_pinctrl_match); + +static struct platform_driver sun9i_a80_r_pinctrl_driver = { + .probe = sun9i_a80_r_pinctrl_probe, + .driver = { + .name = "sun9i-a80-r-pinctrl", + .owner = THIS_MODULE, + .of_match_table = sun9i_a80_r_pinctrl_match, + }, +}; +module_platform_driver(sun9i_a80_r_pinctrl_driver); + +MODULE_AUTHOR("Maxime Ripard Date: Mon, 21 Dec 2015 17:39:44 +0100 Subject: pinctrl-tegra: add missing of_node_put for_each_child_of_node performs an of_node_get on each iteration, so a return from the loop requires an of_node_put. A simplified version of the semantic patch that fixes this problem is as follows (http://coccinelle.lip6.fr): // @@ local idexpression n; expression e,e1; @@ for_each_child_of_node(e1,n) { ... ( of_node_put(n); | e = n | return n; | + of_node_put(n); ? return ...; ) ... } // Signed-off-by: Julia Lawall Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/pinctrl-tegra-xusb.c b/drivers/pinctrl/pinctrl-tegra-xusb.c index 84a43e6..bd3aa5a 100644 --- a/drivers/pinctrl/pinctrl-tegra-xusb.c +++ b/drivers/pinctrl/pinctrl-tegra-xusb.c @@ -253,8 +253,10 @@ static int tegra_xusb_padctl_dt_node_to_map(struct pinctrl_dev *pinctrl, err = tegra_xusb_padctl_parse_subnode(padctl, np, maps, &reserved_maps, num_maps); - if (err < 0) + if (err < 0) { + of_node_put(np); return err; + } } return 0; diff --git a/drivers/pinctrl/pinctrl-tegra.c b/drivers/pinctrl/pinctrl-tegra.c index 0fd7fd2..9da4da2 100644 --- a/drivers/pinctrl/pinctrl-tegra.c +++ b/drivers/pinctrl/pinctrl-tegra.c @@ -217,6 +217,7 @@ static int tegra_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev, if (ret < 0) { pinctrl_utils_dt_free_map(pctldev, *map, *num_maps); + of_node_put(np); return ret; } } -- cgit v0.10.2 From 2d98023c16048dc59aa54514b4b52da61aa66b13 Mon Sep 17 00:00:00 2001 From: Julia Lawall Date: Mon, 21 Dec 2015 17:39:45 +0100 Subject: pinctrl: sirf: add missing of_node_put for_each_child_of_node performs an of_node_get on each iteration, so a return from the loop requires an of_node_put. A simplified version of the semantic patch that fixes this problem is as follows (http://coccinelle.lip6.fr): // @@ local idexpression n; expression e,e1; @@ for_each_child_of_node(e1,n) { ... ( of_node_put(n); | e = n | return n; | + of_node_put(n); ? return ...; ) ... } // Signed-off-by: Julia Lawall Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/sirf/pinctrl-sirf.c b/drivers/pinctrl/sirf/pinctrl-sirf.c index 2a8d697..edf40df 100644 --- a/drivers/pinctrl/sirf/pinctrl-sirf.c +++ b/drivers/pinctrl/sirf/pinctrl-sirf.c @@ -85,12 +85,16 @@ static int sirfsoc_dt_node_to_map(struct pinctrl_dev *pctldev, /* calculate number of maps required */ for_each_child_of_node(np_config, np) { ret = of_property_read_string(np, "sirf,function", &function); - if (ret < 0) + if (ret < 0) { + of_node_put(np); return ret; + } ret = of_property_count_strings(np, "sirf,pins"); - if (ret < 0) + if (ret < 0) { + of_node_put(np); return ret; + } count += ret; } -- cgit v0.10.2 From d0b3ed4160201930b505ed9dedc4f80780ad4ff1 Mon Sep 17 00:00:00 2001 From: Julia Lawall Date: Mon, 21 Dec 2015 17:39:46 +0100 Subject: pinctrl: sh-pfc: add missing of_node_put for_each_child_of_node performs an of_node_get on each iteration, so a goto out of the loop requires an of_node_put. A simplified version of the semantic patch that fixes this problem is as follows (http://coccinelle.lip6.fr): // @@ local idexpression n; expression e,e1; identifier l; @@ for_each_child_of_node(e1,n) { ... ( of_node_put(n); | e = n | return n; | + of_node_put(n); ? goto l; ) ... } l: ... when != n // Signed-off-by: Julia Lawall Reviewed-by: Laurent Pinchart Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/sh-pfc/pinctrl.c b/drivers/pinctrl/sh-pfc/pinctrl.c index 863c3e3..87b0a59 100644 --- a/drivers/pinctrl/sh-pfc/pinctrl.c +++ b/drivers/pinctrl/sh-pfc/pinctrl.c @@ -273,8 +273,10 @@ static int sh_pfc_dt_node_to_map(struct pinctrl_dev *pctldev, for_each_child_of_node(np, child) { ret = sh_pfc_dt_subnode_to_map(pctldev, child, map, num_maps, &index); - if (ret < 0) + if (ret < 0) { + of_node_put(child); goto done; + } } /* If no mapping has been found in child nodes try the config node. */ -- cgit v0.10.2 From f7a81b7f4e9830323a7bbee8c4c7ab4c7c7ff6f4 Mon Sep 17 00:00:00 2001 From: Julia Lawall Date: Mon, 21 Dec 2015 17:39:47 +0100 Subject: pinctrl: rockchip: add missing of_node_put for_each_child_of_node performs an of_node_get on each iteration, so a return from the loop requires an of_node_put. A simplified version of the semantic patch that fixes this problem is as follows (http://coccinelle.lip6.fr): // @@ local idexpression n; expression e,e1; @@ for_each_child_of_node(e1,n) { ... ( of_node_put(n); | e = n | return n; | + of_node_put(n); ? return ...; ) ... } // Signed-off-by: Julia Lawall Reviewed-by: Heiko Stuebner Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c index faab36e..9128826 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -1292,8 +1292,10 @@ static int rockchip_pinctrl_parse_functions(struct device_node *np, func->groups[i] = child->name; grp = &info->groups[grp_index++]; ret = rockchip_pinctrl_parse_groups(child, grp, info, i++); - if (ret) + if (ret) { + of_node_put(child); return ret; + } } return 0; @@ -1338,6 +1340,7 @@ static int rockchip_pinctrl_parse_dt(struct platform_device *pdev, ret = rockchip_pinctrl_parse_functions(child, info, i++); if (ret) { dev_err(&pdev->dev, "failed to parse function\n"); + of_node_put(child); return ret; } } -- cgit v0.10.2 From 4fc8a4b2a4dd7704d950a01b1afec5e86af60565 Mon Sep 17 00:00:00 2001 From: Julia Lawall Date: Mon, 21 Dec 2015 17:39:48 +0100 Subject: pinctrl: mediatek: add missing of_node_put for_each_child_of_node performs an of_node_get on each iteration, so a return from the loop requires an of_node_put. A simplified version of the semantic patch that fixes this problem is as follows (http://coccinelle.lip6.fr): // @@ local idexpression n; expression e,e1; @@ for_each_child_of_node(e1,n) { ... ( of_node_put(n); | e = n | return n; | + of_node_put(n); ? return ...; ) ... } // Signed-off-by: Julia Lawall Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c index 8db7cdf..e22cbaf 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c @@ -598,6 +598,7 @@ static int mtk_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev, &reserved_maps, num_maps); if (ret < 0) { pinctrl_utils_dt_free_map(pctldev, *map, *num_maps); + of_node_put(np); return ret; } } -- cgit v0.10.2 From 53653c6b91750debba6dc4503003c851257fd340 Mon Sep 17 00:00:00 2001 From: Stefan Wahren Date: Mon, 21 Dec 2015 00:44:04 +0000 Subject: pinctrl: bcm2835: Fix memory leak in error path In case of an invalid pin value bcm2835_pctl_dt_node_to_map() would leak the pull configs of already assigned pins. So avoid this by calling the free map function in error case. Signed-off-by: Stefan Wahren Fixes: e1b2dc70cd5b ("pinctrl: add bcm2835 driver") Reviewed-by: Eric Anholt Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/bcm/pinctrl-bcm2835.c b/drivers/pinctrl/bcm/pinctrl-bcm2835.c index a1ea565..f26d374 100644 --- a/drivers/pinctrl/bcm/pinctrl-bcm2835.c +++ b/drivers/pinctrl/bcm/pinctrl-bcm2835.c @@ -794,7 +794,7 @@ static int bcm2835_pctl_dt_node_to_map(struct pinctrl_dev *pctldev, return 0; out: - kfree(maps); + bcm2835_pctl_dt_free_map(pctldev, maps, num_pins * maps_per_pin); return err; } -- cgit v0.10.2 From 6c741c74092c61465af206672ba567940a23d709 Mon Sep 17 00:00:00 2001 From: Daniel Kurtz Date: Tue, 22 Dec 2015 21:46:37 +0800 Subject: pinctrl: mediatek: convert to arch_initcall Move pinctrl initialization earlier in boot so that real devices can find their pctldev without probe deferring. Note: We don't change mt6397 probe order in this patch, since MT6397 is mfd PMIC, which depends on pwrap on main AP to work. Since pmic-wrap itself is module_platform_driver, we keep it as module_init. A later patch will convert both pmic-wrap, and all functions of the MT6397 mfd to arch_initcall. Signed-off-by: Daniel Kurtz Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8127.c b/drivers/pinctrl/mediatek/pinctrl-mt8127.c index b317b0b..98e0beb 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8127.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8127.c @@ -351,7 +351,7 @@ static int __init mtk_pinctrl_init(void) return platform_driver_register(&mtk_pinctrl_driver); } -module_init(mtk_pinctrl_init); +arch_initcall(mtk_pinctrl_init); MODULE_LICENSE("GPL v2"); MODULE_DESCRIPTION("MediaTek MT8127 Pinctrl Driver"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8135.c b/drivers/pinctrl/mediatek/pinctrl-mt8135.c index 404f117..1c153b8 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8135.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8135.c @@ -366,7 +366,7 @@ static int __init mtk_pinctrl_init(void) return platform_driver_register(&mtk_pinctrl_driver); } -module_init(mtk_pinctrl_init); +arch_initcall(mtk_pinctrl_init); MODULE_LICENSE("GPL"); MODULE_DESCRIPTION("MediaTek Pinctrl Driver"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8173.c b/drivers/pinctrl/mediatek/pinctrl-mt8173.c index ad27184..a62514e 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8173.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8173.c @@ -394,7 +394,7 @@ static int __init mtk_pinctrl_init(void) return platform_driver_register(&mtk_pinctrl_driver); } -module_init(mtk_pinctrl_init); +arch_initcall(mtk_pinctrl_init); MODULE_LICENSE("GPL v2"); MODULE_DESCRIPTION("MediaTek Pinctrl Driver"); -- cgit v0.10.2 From ce6c1cd2c324c027de87d6c249298c9f93463ee8 Mon Sep 17 00:00:00 2001 From: Dan Carpenter Date: Thu, 24 Dec 2015 10:25:32 +0300 Subject: pinctrl: nsp-gpio: forever loop in nsp_gpio_get_strength() There is a signedness bug here so the loop will never exit. Fixes: 8bfcbbbcabe0 ('pinctrl: nsp: add gpio-a driver support for Broadcom NSP SoC') Signed-off-by: Dan Carpenter Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/bcm/pinctrl-nsp-gpio.c b/drivers/pinctrl/bcm/pinctrl-nsp-gpio.c index 1f66761..725c36f 100644 --- a/drivers/pinctrl/bcm/pinctrl-nsp-gpio.c +++ b/drivers/pinctrl/bcm/pinctrl-nsp-gpio.c @@ -439,9 +439,10 @@ static int nsp_gpio_set_strength(struct nsp_gpio *chip, unsigned gpio, static int nsp_gpio_get_strength(struct nsp_gpio *chip, unsigned gpio, u16 *strength) { - unsigned int i, offset, shift; + unsigned int offset, shift; u32 val; unsigned long flags; + int i; offset = NSP_GPIO_DRV_CTRL; shift = gpio; -- cgit v0.10.2 From bda7c4c2b9767ce2af4394754498662d62079af5 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Fri, 25 Dec 2015 13:27:04 +0100 Subject: pinctrl: qcom: make PMIC drivers bool commit ab4256cfeab91569e1d96e7f0014538fe0845259 "pinctrl: qcom: pmic-gpio/mpp: of_irq_count() == npins" made the Qualcomm PMIC pin control drivers make use of of_irq_count() which is not an exported function, making modular builds fail. Fix this by marking the drivers as compiled-in/bool. Cc: Stephen Boyd Cc: Andy Gross Cc: Mark Brown Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig index eeac8cb..c658d9b 100644 --- a/drivers/pinctrl/qcom/Kconfig +++ b/drivers/pinctrl/qcom/Kconfig @@ -80,7 +80,7 @@ config PINCTRL_QDF2XXX Qualcomm Technologies QDF2xxx SOCs. config PINCTRL_QCOM_SPMI_PMIC - tristate "Qualcomm SPMI PMIC pin controller driver" + bool "Qualcomm SPMI PMIC pin controller driver" depends on GPIOLIB && OF && SPMI select REGMAP_SPMI select PINMUX @@ -93,7 +93,7 @@ config PINCTRL_QCOM_SPMI_PMIC devices are pm8841, pm8941 and pma8084. config PINCTRL_QCOM_SSBI_PMIC - tristate "Qualcomm SSBI PMIC pin controller driver" + bool "Qualcomm SSBI PMIC pin controller driver" depends on GPIOLIB && OF select PINMUX select PINCONF -- cgit v0.10.2 From c9f294ff6584782d20b4a766901a9cff7398bb20 Mon Sep 17 00:00:00 2001 From: John Crispin Date: Mon, 4 Jan 2016 22:27:57 +0100 Subject: pinctrl: lantiq: 2 pins have the wrong mux list The latest vendor SDK contained this patch. Signed-off-by: John Crispin Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/pinctrl-xway.c b/drivers/pinctrl/pinctrl-xway.c index b78baaa..7db7469 100644 --- a/drivers/pinctrl/pinctrl-xway.c +++ b/drivers/pinctrl/pinctrl-xway.c @@ -160,10 +160,10 @@ static const struct ltq_mfp_pin xway_mfp[] = { MFP_XWAY(GPIO41, GPIO, NONE, NONE, NONE), MFP_XWAY(GPIO42, GPIO, MDIO, NONE, NONE), MFP_XWAY(GPIO43, GPIO, MDIO, NONE, NONE), - MFP_XWAY(GPIO44, GPIO, NONE, SIN, GPHY), + MFP_XWAY(GPIO44, GPIO, MII, SIN, GPHY), MFP_XWAY(GPIO45, GPIO, NONE, GPHY, SIN), MFP_XWAY(GPIO46, GPIO, NONE, NONE, EXIN), - MFP_XWAY(GPIO47, GPIO, NONE, GPHY, SIN), + MFP_XWAY(GPIO47, GPIO, MII, GPHY, SIN), MFP_XWAY(GPIO48, GPIO, EBU, NONE, NONE), MFP_XWAY(GPIO49, GPIO, EBU, NONE, NONE), MFP_XWAY(GPIO50, GPIO, NONE, NONE, NONE), -- cgit v0.10.2 From 4b83555d5098e73cf2c5ca7f86c17ca0ba3b968e Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Wed, 6 Jan 2016 17:12:47 -0800 Subject: driver-core: platform: Add platform_irq_count() A recent patch added calls to of_irq_count() in the qcom pinctrl drivers and that caused module build failures because of_irq_count() is not an exported symbol. We shouldn't export of_irq_count() to modules because it's an internal OF API that shouldn't be used by drivers. Platform drivers should use platform device APIs instead. Therefore, add a platform_irq_count() API that mirrors the of_irq_count() API so that platform drivers can stay DT agnostic. Cc: Andy Gross Acked-by: Rob Herring Acked-by: Greg Kroah-Hartman Signed-off-by: Linus Walleij diff --git a/drivers/base/platform.c b/drivers/base/platform.c index 1dd6d3b..73e3994 100644 --- a/drivers/base/platform.c +++ b/drivers/base/platform.c @@ -117,6 +117,26 @@ int platform_get_irq(struct platform_device *dev, unsigned int num) EXPORT_SYMBOL_GPL(platform_get_irq); /** + * platform_irq_count - Count the number of IRQs a platform device uses + * @dev: platform device + * + * Return: Number of IRQs a platform device uses or EPROBE_DEFER + */ +int platform_irq_count(struct platform_device *dev) +{ + int ret, nr = 0; + + while ((ret = platform_get_irq(dev, nr)) >= 0) + nr++; + + if (ret == -EPROBE_DEFER) + return ret; + + return nr; +} +EXPORT_SYMBOL_GPL(platform_irq_count); + +/** * platform_get_resource_byname - get a resource for a device by name * @dev: platform device * @type: resource type diff --git a/include/linux/platform_device.h b/include/linux/platform_device.h index dc777be..6abd019 100644 --- a/include/linux/platform_device.h +++ b/include/linux/platform_device.h @@ -51,6 +51,7 @@ extern void arch_setup_pdev_archdata(struct platform_device *); extern struct resource *platform_get_resource(struct platform_device *, unsigned int, unsigned int); extern int platform_get_irq(struct platform_device *, unsigned int); +extern int platform_irq_count(struct platform_device *); extern struct resource *platform_get_resource_byname(struct platform_device *, unsigned int, const char *); -- cgit v0.10.2 From a5ea13f025e7bf3bb280a22f5fe63b7159358932 Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Wed, 6 Jan 2016 17:37:41 -0800 Subject: pinctrl: qcom: Use platform_irq_count() instead of of_irq_count() of_irq_count() is not an exported symbol (and it shouldn't be used by platform drivers anyway) so use platform_irq_count() instead. This allows us to make the qcom pinctrl drivers modular again. Cc: Rob Herring Cc: Andy Gross Cc: Bjorn Andersson Signed-off-by: Stephen Boyd Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c b/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c index 4eea62a..77f6a5c 100644 --- a/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c +++ b/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c @@ -702,9 +702,11 @@ static int pmic_gpio_probe(struct platform_device *pdev) return ret; } - npins = of_irq_count(dev->of_node); + npins = platform_irq_count(pdev); if (!npins) return -EINVAL; + if (npins < 0) + return npins; BUG_ON(npins > ARRAY_SIZE(pmic_gpio_groups)); diff --git a/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c b/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c index 8841bb7..2df4f29 100644 --- a/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c +++ b/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c @@ -804,9 +804,11 @@ static int pmic_mpp_probe(struct platform_device *pdev) return ret; } - npins = of_irq_count(dev->of_node); + npins = platform_irq_count(pdev); if (!npins) return -EINVAL; + if (npins < 0) + return npins; BUG_ON(npins > ARRAY_SIZE(pmic_mpp_groups)); diff --git a/drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c b/drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c index 78fa228..e51176e 100644 --- a/drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c +++ b/drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c @@ -667,16 +667,19 @@ static int pm8xxx_gpio_probe(struct platform_device *pdev) struct pinctrl_pin_desc *pins; struct pm8xxx_gpio *pctrl; int ret; - int i; + int i, npins; pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); if (!pctrl) return -ENOMEM; pctrl->dev = &pdev->dev; - pctrl->npins = of_irq_count(pdev->dev.of_node); - if (!pctrl->npins) + npins = platform_irq_count(pdev); + if (!npins) return -EINVAL; + if (npins < 0) + return npins; + pctrl->npins = npins; pctrl->regmap = dev_get_regmap(pdev->dev.parent, NULL); if (!pctrl->regmap) { diff --git a/drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c b/drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c index 0831063..e9f01de 100644 --- a/drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c +++ b/drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c @@ -758,16 +758,19 @@ static int pm8xxx_mpp_probe(struct platform_device *pdev) struct pinctrl_pin_desc *pins; struct pm8xxx_mpp *pctrl; int ret; - int i; + int i, npins; pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); if (!pctrl) return -ENOMEM; pctrl->dev = &pdev->dev; - pctrl->npins = of_irq_count(pdev->dev.of_node); - if (!pctrl->npins) + npins = platform_irq_count(pdev); + if (!npins) return -EINVAL; + if (npins < 0) + return npins; + pctrl->npins = npins; pctrl->regmap = dev_get_regmap(pdev->dev.parent, NULL); if (!pctrl->regmap) { -- cgit v0.10.2 From 4afaee3c2b7fb49d3ec1bcd89c7b960b5ae646b3 Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Wed, 6 Jan 2016 17:12:49 -0800 Subject: Revert "pinctrl: qcom: make PMIC drivers bool" This reverts commit bda7c4c2b9767ce2af4394754498662d62079af5. These drivers build as modules now that we use platform_irq_count() instead of of_irq_count(). Cc: Rob Herring Cc: Andy Gross Signed-off-by: Stephen Boyd Signed-off-by: Linus Walleij diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig index c658d9b..eeac8cb 100644 --- a/drivers/pinctrl/qcom/Kconfig +++ b/drivers/pinctrl/qcom/Kconfig @@ -80,7 +80,7 @@ config PINCTRL_QDF2XXX Qualcomm Technologies QDF2xxx SOCs. config PINCTRL_QCOM_SPMI_PMIC - bool "Qualcomm SPMI PMIC pin controller driver" + tristate "Qualcomm SPMI PMIC pin controller driver" depends on GPIOLIB && OF && SPMI select REGMAP_SPMI select PINMUX @@ -93,7 +93,7 @@ config PINCTRL_QCOM_SPMI_PMIC devices are pm8841, pm8941 and pma8084. config PINCTRL_QCOM_SSBI_PMIC - bool "Qualcomm SSBI PMIC pin controller driver" + tristate "Qualcomm SSBI PMIC pin controller driver" depends on GPIOLIB && OF select PINMUX select PINCONF -- cgit v0.10.2 From 14da0a91bf4ac2a90d64446ddaa39a4869530f8c Mon Sep 17 00:00:00 2001 From: Biao Huang Date: Mon, 28 Dec 2015 15:09:03 +0800 Subject: pinctrl: mediatek: Modify pinctrl bindings for mt2701 Signed-off-by: Biao Huang Acked-by: Rob Herring Reviewed-by: Mathias Brugger Signed-off-by: Linus Walleij diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt index 0480bc3..9ffb0b2 100644 --- a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt @@ -4,10 +4,11 @@ The Mediatek's Pin controller is used to control SoC pins. Required properties: - compatible: value should be one of the following. - (a) "mediatek,mt8135-pinctrl", compatible with mt8135 pinctrl. - (b) "mediatek,mt8173-pinctrl", compatible with mt8173 pinctrl. - (c) "mediatek,mt6397-pinctrl", compatible with mt6397 pinctrl. - (d) "mediatek,mt8127-pinctrl", compatible with mt8127 pinctrl. + "mediatek,mt2701-pinctrl", compatible with mt2701 pinctrl. + "mediatek,mt6397-pinctrl", compatible with mt6397 pinctrl. + "mediatek,mt8127-pinctrl", compatible with mt8127 pinctrl. + "mediatek,mt8135-pinctrl", compatible with mt8135 pinctrl. + "mediatek,mt8173-pinctrl", compatible with mt8173 pinctrl. - pins-are-numbered: Specify the subnodes are using numbered pinmux to specify pins. - gpio-controller : Marks the device node as a gpio controller. -- cgit v0.10.2