From 063de897c411af65cb113cb5fb9a0022f913460e Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Tue, 8 Jul 2014 18:21:14 +0200 Subject: ARM: at91/dt: sama5d3: define mpddr clock and ramc clocks Define the available clock for mprddr and take both mpddr_clk and ddrck in the ram controller driver. Signed-off-by: Alexandre Belloni Signed-off-by: Maxime Ripard Acked-by: Nicolas Ferre diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi index e0b15a6..04c35ce 100644 --- a/arch/arm/boot/dts/sama5d3.dtsi +++ b/arch/arm/boot/dts/sama5d3.dtsi @@ -402,8 +402,10 @@ }; ramc0: ramc@ffffea00 { - compatible = "atmel,at91sam9g45-ddramc"; + compatible = "atmel,sama5d3-ddramc"; reg = <0xffffea00 0x200>; + clocks = <&ddrck>, <&mpddr_clk>; + clock-names = "ddrck", "mpddr"; }; dbgu: serial@ffffee00 { @@ -1170,6 +1172,11 @@ #clock-cells = <0>; reg = <48>; }; + + mpddr_clk: mpddr_clk { + #clock-cells = <0>; + reg = <49>; + }; }; }; -- cgit v0.10.2 From 7e948346000cfc300f39f1c14335b2ef364257ef Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Tue, 8 Jul 2014 18:21:15 +0200 Subject: ARM: at91/dt: at91sam9: use ddrck in ramc Make the ram controller driver take the ddrck clock for at91sam9n12 and at91sam9x5. Signed-off-by: Alexandre Belloni Signed-off-by: Maxime Ripard Acked-by: Nicolas Ferre diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi index d1b82e6..1534e49 100644 --- a/arch/arm/boot/dts/at91sam9n12.dtsi +++ b/arch/arm/boot/dts/at91sam9n12.dtsi @@ -85,6 +85,8 @@ ramc0: ramc@ffffe800 { compatible = "atmel,at91sam9g45-ddramc"; reg = <0xffffe800 0x200>; + clocks = <&ddrck>; + clock-names = "ddrck"; }; pmc: pmc@fffffc00 { diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi index 1a57298..72e1483 100644 --- a/arch/arm/boot/dts/at91sam9x5.dtsi +++ b/arch/arm/boot/dts/at91sam9x5.dtsi @@ -93,6 +93,8 @@ ramc0: ramc@ffffe800 { compatible = "atmel,at91sam9g45-ddramc"; reg = <0xffffe800 0x200>; + clocks = <&ddrck>; + clock-names = "ddrck"; }; pmc: pmc@fffffc00 { -- cgit v0.10.2 From 1e165a7dc2f07054736a6a16bdc2fa024f3aa2d4 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Thu, 3 Jul 2014 12:01:29 +0200 Subject: ARM: at91/dt: Declare a second ram controller when relevant The G45 and 9263 SoCs has two identical ram controller, that are defined as a single node, with two reg cells. The proper way to support such a case is to have two separate DT nodes. Signed-off-by: Maxime Ripard Acked-by: Nicolas Ferre Acked-by: Alexandre Belloni diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi index fece866..e8ecb03 100644 --- a/arch/arm/boot/dts/at91sam9263.dtsi +++ b/arch/arm/boot/dts/at91sam9263.dtsi @@ -71,10 +71,14 @@ reg = <0xfffffc00 0x100>; }; - ramc: ramc@ffffe200 { + ramc0: ramc@ffffe200 { compatible = "atmel,at91sam9260-sdramc"; - reg = <0xffffe200 0x200 - 0xffffe800 0x200>; + reg = <0xffffe200 0x200>; + }; + + ramc1: ramc@ffffe800 { + compatible = "atmel,at91sam9260-sdramc"; + reg = <0xffffe800 0x200>; }; pit: timer@fffffd30 { diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi index ace6bf1..6f648b8 100644 --- a/arch/arm/boot/dts/at91sam9g45.dtsi +++ b/arch/arm/boot/dts/at91sam9g45.dtsi @@ -75,8 +75,12 @@ ramc0: ramc@ffffe400 { compatible = "atmel,at91sam9g45-ddramc"; - reg = <0xffffe400 0x200 - 0xffffe600 0x200>; + reg = <0xffffe400 0x200>; + }; + + ramc1: ramc@ffffe600 { + compatible = "atmel,at91sam9g45-ddramc"; + reg = <0xffffe600 0x200>; }; pmc: pmc@fffffc00 { -- cgit v0.10.2 From 16aa7f1f173f3ca105296cf2709cb039c99ffe4a Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Thu, 3 Jul 2014 14:08:47 +0200 Subject: ARM: at91/dt: sama5d3: Add shutdown controller The SAMA5D3 has a shutdown controller identical to the sam9x5 SoC family. Declare it in the DT. Signed-off-by: Maxime Ripard Acked-by: Nicolas Ferre Acked-by: Alexandre Belloni diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi index 04c35ce..97952ef 100644 --- a/arch/arm/boot/dts/sama5d3.dtsi +++ b/arch/arm/boot/dts/sama5d3.dtsi @@ -1185,6 +1185,11 @@ reg = <0xfffffe00 0x10>; }; + shutdown-controller@fffffe10 { + compatible = "atmel,at91sam9x5-shdwc"; + reg = <0xfffffe10 0x10>; + }; + pit: timer@fffffe30 { compatible = "atmel,at91sam9260-pit"; reg = <0xfffffe30 0xf>; -- cgit v0.10.2 From 2618a18246a6164c212c47ee6b0031ad85909cc9 Mon Sep 17 00:00:00 2001 From: Marek Belisko Date: Tue, 22 Jul 2014 21:30:14 +0200 Subject: ARM: dts: omap3-gta04: Add nand support Add the needed sections to enable nand support on gta04 board. Add nand partitions information. Signed-off-by: Marek Belisko Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/omap3-gta04.dts b/arch/arm/boot/dts/omap3-gta04.dts index 021311f..7d7ddd7 100644 --- a/arch/arm/boot/dts/omap3-gta04.dts +++ b/arch/arm/boot/dts/omap3-gta04.dts @@ -309,3 +309,57 @@ }; }; }; + +&gpmc { + ranges = <0 0 0x30000000 0x04>; /* CS0: NAND */ + + nand@0,0 { + reg = <0 0 0>; /* CS0, offset 0 */ + nand-bus-width = <16>; + ti,nand-ecc-opt = "bch8"; + + gpmc,sync-clk-ps = <0>; + gpmc,cs-on-ns = <0>; + gpmc,cs-rd-off-ns = <44>; + gpmc,cs-wr-off-ns = <44>; + gpmc,adv-on-ns = <6>; + gpmc,adv-rd-off-ns = <34>; + gpmc,adv-wr-off-ns = <44>; + gpmc,we-off-ns = <40>; + gpmc,oe-off-ns = <54>; + gpmc,access-ns = <64>; + gpmc,rd-cycle-ns = <82>; + gpmc,wr-cycle-ns = <82>; + gpmc,wr-access-ns = <40>; + gpmc,wr-data-mux-bus-ns = <0>; + gpmc,device-width = <2>; + + #address-cells = <1>; + #size-cells = <1>; + + x-loader@0 { + label = "X-Loader"; + reg = <0 0x80000>; + }; + + bootloaders@80000 { + label = "U-Boot"; + reg = <0x80000 0x1e0000>; + }; + + bootloaders_env@260000 { + label = "U-Boot Env"; + reg = <0x260000 0x20000>; + }; + + kernel@280000 { + label = "Kernel"; + reg = <0x280000 0x400000>; + }; + + filesystem@680000 { + label = "File System"; + reg = <0x680000 0xf980000>; + }; + }; +}; -- cgit v0.10.2 From 9edc57af01a22f227c30ae1261cf232ab8673cbf Mon Sep 17 00:00:00 2001 From: Marek Belisko Date: Tue, 22 Jul 2014 21:59:08 +0200 Subject: ARM: dts: omap3-gta04: Fix magnetometer model gta04 is using hmc5883l not hmc5843 so fix wrong compatible entry. Signed-off-by: Marek Belisko Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/omap3-gta04.dts b/arch/arm/boot/dts/omap3-gta04.dts index 7d7ddd7..4067495 100644 --- a/arch/arm/boot/dts/omap3-gta04.dts +++ b/arch/arm/boot/dts/omap3-gta04.dts @@ -220,7 +220,7 @@ /* compass aka magnetometer */ hmc5843@1e { - compatible = "honeywell,hmc5843"; + compatible = "honeywell,hmc5883l"; reg = <0x1e>; }; -- cgit v0.10.2 From e51c6beaefe3e2fc7490064b7a4a5f70cd861cde Mon Sep 17 00:00:00 2001 From: Marek Belisko Date: Tue, 22 Jul 2014 21:30:16 +0200 Subject: ARM: dts: omap3-gta04: Add wifi reset node Define gpio node in tca6507 which will be used as wifi reset pin. Signed-off-by: Marek Belisko Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/omap3-gta04.dts b/arch/arm/boot/dts/omap3-gta04.dts index 4067495..0c44827 100644 --- a/arch/arm/boot/dts/omap3-gta04.dts +++ b/arch/arm/boot/dts/omap3-gta04.dts @@ -196,6 +196,9 @@ #size-cells = <0>; reg = <0x45>; + gpio-controller; + #gpio-cells = <2>; + gta04_led0: red_aux@0 { label = "gta04:red:aux"; reg = <0x0>; @@ -216,6 +219,11 @@ label = "gta04:green:power"; reg = <0x4>; }; + + wifi_reset: wifi_reset@6 { + reg = <0x6>; + compatible = "gpio"; + }; }; /* compass aka magnetometer */ -- cgit v0.10.2 From 6c402f8d678ebc438c66fea8507f8c820843c26d Mon Sep 17 00:00:00 2001 From: Marek Belisko Date: Tue, 22 Jul 2014 21:30:17 +0200 Subject: ARM: dts: omap3-gta04: Move spi gpio pins to pmx_core2 Because of commit: 3d495383648a7cda3ea51a1e2fa5d288581479aa spi_gpio_pins node isn't valid anymore. Move to pmx_core2 node. Signed-off-by: Marek Belisko Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/omap3-gta04.dts b/arch/arm/boot/dts/omap3-gta04.dts index 0c44827..31ddd39 100644 --- a/arch/arm/boot/dts/omap3-gta04.dts +++ b/arch/arm/boot/dts/omap3-gta04.dts @@ -141,12 +141,15 @@ 0x0da (PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */ >; }; +}; +&omap3_pmx_core2 { spi_gpio_pins: spi_gpio_pinmux { - pinctrl-single,pins = <0x5a8 (PIN_OUTPUT | MUX_MODE4) /* clk */ - 0x5b6 (PIN_OUTPUT | MUX_MODE4) /* cs */ - 0x5b8 (PIN_OUTPUT | MUX_MODE4) /* tx */ - 0x5b4 (PIN_INPUT | MUX_MODE4) /* rx */ + pinctrl-single,pins = < + OMAP3630_CORE2_IOPAD(0x25d8, PIN_OUTPUT | MUX_MODE4) /* clk */ + OMAP3630_CORE2_IOPAD(0x25e6, PIN_OUTPUT | MUX_MODE4) /* cs */ + OMAP3630_CORE2_IOPAD(0x25e8, PIN_OUTPUT | MUX_MODE4) /* tx */ + OMAP3630_CORE2_IOPAD(0x25e4, PIN_INPUT | MUX_MODE4) /* rx */ >; }; }; -- cgit v0.10.2 From 1520a13bf03b3be8a87df665db878d0600560108 Mon Sep 17 00:00:00 2001 From: Marek Belisko Date: Tue, 22 Jul 2014 21:30:18 +0200 Subject: ARM: dts: omap3-gta04: Add USB host support Define USB Host port mode and the PHY device. Also provide pin multiplexer information for USB host pins. Signed-off-by: Marek Belisko Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/omap3-gta04.dts b/arch/arm/boot/dts/omap3-gta04.dts index 31ddd39..83bb1e0 100644 --- a/arch/arm/boot/dts/omap3-gta04.dts +++ b/arch/arm/boot/dts/omap3-gta04.dts @@ -74,9 +74,30 @@ }; }; }; + + hsusb2_phy: hsusb2_phy { + compatible = "usb-nop-xceiv"; + reset-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>; + }; }; &omap3_pmx_core { + pinctrl-names = "default"; + pinctrl-0 = < + &hsusb2_pins + >; + + hsusb2_pins: pinmux_hsusb2_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi1_cs3.hsusb2_data2 */ + OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_clk.hsusb2_data7 */ + OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_simo.hsusb2_data4 */ + OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_somi.hsusb2_data5 */ + OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs0.hsusb2_data6 */ + OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs1.hsusb2_data3 */ + >; + }; + uart1_pins: pinmux_uart1_pins { pinctrl-single,pins = < 0x152 (PIN_INPUT | MUX_MODE0) /* uart1_rx.uart1_rx */ @@ -144,6 +165,22 @@ }; &omap3_pmx_core2 { + pinctrl-names = "default"; + pinctrl-0 = < + &hsusb2_2_pins + >; + + hsusb2_2_pins: pinmux_hsusb2_2_pins { + pinctrl-single,pins = < + OMAP3630_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */ + OMAP3630_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */ + OMAP3630_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */ + OMAP3630_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */ + OMAP3630_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */ + OMAP3630_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */ + >; + }; + spi_gpio_pins: spi_gpio_pinmux { pinctrl-single,pins = < OMAP3630_CORE2_IOPAD(0x25d8, PIN_OUTPUT | MUX_MODE4) /* clk */ @@ -259,6 +296,14 @@ power = <50>; }; +&usbhshost { + port2-mode = "ehci-phy"; +}; + +&usbhsehci { + phys = <0 &hsusb2_phy>; +}; + &mmc1 { pinctrl-names = "default"; pinctrl-0 = <&mmc1_pins>; -- cgit v0.10.2 From 91b8457e6853540966960a50573d0e0d20f355ea Mon Sep 17 00:00:00 2001 From: Marek Belisko Date: Tue, 22 Jul 2014 21:30:19 +0200 Subject: ARM: dts: omap3-gta04: Add display alias Define alias for lcd display present on gta04 board. Signed-off-by: Marek Belisko Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/omap3-gta04.dts b/arch/arm/boot/dts/omap3-gta04.dts index 83bb1e0..ab58607 100644 --- a/arch/arm/boot/dts/omap3-gta04.dts +++ b/arch/arm/boot/dts/omap3-gta04.dts @@ -26,6 +26,10 @@ reg = <0x80000000 0x20000000>; /* 512 MB */ }; + aliases { + display0 = &lcd; + }; + gpio-keys { compatible = "gpio-keys"; -- cgit v0.10.2 From 4318bad2a02dcc678afab376713b1132ca333951 Mon Sep 17 00:00:00 2001 From: Marek Belisko Date: Tue, 22 Jul 2014 21:30:20 +0200 Subject: ARM: dts: omap3-gta04: Add twl4030 regulators parameters Define voltages and properties for various twl4030 regulators used on gta04 board. Signed-off-by: Marek Belisko Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/omap3-gta04.dts b/arch/arm/boot/dts/omap3-gta04.dts index ab58607..fd34f91 100644 --- a/arch/arm/boot/dts/omap3-gta04.dts +++ b/arch/arm/boot/dts/omap3-gta04.dts @@ -346,11 +346,37 @@ bb_uamp = <150>; }; +/* spare */ +&vaux1 { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <3000000>; +}; + +/* sensors */ +&vaux2 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; +}; + +/* camera */ +&vaux3 { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; +}; + +/* WLAN/BT */ &vaux4 { regulator-min-microvolt = <2800000>; regulator-max-microvolt = <3150000>; }; +/* GPS LNA */ +&vsim { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3150000>; +}; + /* Needed to power the DPI pins */ &vpll2 { regulator-always-on; -- cgit v0.10.2 From d17eb9b2a97131c75c7ea83ba981ebbe26135207 Mon Sep 17 00:00:00 2001 From: Marek Belisko Date: Mon, 28 Jul 2014 21:53:31 +0200 Subject: ARM: dts: omap3-gta04: Rename gta04.dts to gta04.dtsi and add a4 model This patch is preparation of adding more boards which have common moved to omap3-gta04.dtsi. Other boards have only small additions to omap3-gta04a4. Signed-off-by: Marek Belisko Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index b19f0c8..b812b6c 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -262,7 +262,7 @@ dtb-$(CONFIG_ARCH_OMAP3) += am3517-craneboard.dtb \ omap3-devkit8000.dtb \ omap3-evm.dtb \ omap3-evm-37xx.dtb \ - omap3-gta04.dtb \ + omap3-gta04a4.dtb \ omap3-igep0020.dtb \ omap3-igep0030.dtb \ omap3-ldp.dtb \ diff --git a/arch/arm/boot/dts/omap3-gta04.dts b/arch/arm/boot/dts/omap3-gta04.dts deleted file mode 100644 index fd34f91..0000000 --- a/arch/arm/boot/dts/omap3-gta04.dts +++ /dev/null @@ -1,451 +0,0 @@ -/* - * Copyright (C) 2013 Marek Belisko - * - * Based on omap3-beagle-xm.dts - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -/dts-v1/; - -#include "omap36xx.dtsi" - -/ { - model = "OMAP3 GTA04"; - compatible = "ti,omap3-gta04", "ti,omap36xx", "ti,omap3"; - - cpus { - cpu@0 { - cpu0-supply = <&vcc>; - }; - }; - - memory { - device_type = "memory"; - reg = <0x80000000 0x20000000>; /* 512 MB */ - }; - - aliases { - display0 = &lcd; - }; - - gpio-keys { - compatible = "gpio-keys"; - - aux-button { - label = "aux"; - linux,code = <169>; - gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; - gpio-key,wakeup; - }; - }; - - sound { - compatible = "ti,omap-twl4030"; - ti,model = "gta04"; - - ti,mcbsp = <&mcbsp2>; - ti,codec = <&twl_audio>; - }; - - spi_lcd { - compatible = "spi-gpio"; - #address-cells = <0x1>; - #size-cells = <0x0>; - pinctrl-names = "default"; - pinctrl-0 = <&spi_gpio_pins>; - - gpio-sck = <&gpio1 12 0>; - gpio-miso = <&gpio1 18 0>; - gpio-mosi = <&gpio1 20 0>; - cs-gpios = <&gpio1 19 0>; - num-chipselects = <1>; - - /* lcd panel */ - lcd: td028ttec1@0 { - compatible = "toppoly,td028ttec1"; - reg = <0>; - spi-max-frequency = <100000>; - spi-cpol; - spi-cpha; - - label = "lcd"; - port { - lcd_in: endpoint { - remote-endpoint = <&dpi_out>; - }; - }; - }; - }; - - hsusb2_phy: hsusb2_phy { - compatible = "usb-nop-xceiv"; - reset-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>; - }; -}; - -&omap3_pmx_core { - pinctrl-names = "default"; - pinctrl-0 = < - &hsusb2_pins - >; - - hsusb2_pins: pinmux_hsusb2_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi1_cs3.hsusb2_data2 */ - OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_clk.hsusb2_data7 */ - OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_simo.hsusb2_data4 */ - OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_somi.hsusb2_data5 */ - OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs0.hsusb2_data6 */ - OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs1.hsusb2_data3 */ - >; - }; - - uart1_pins: pinmux_uart1_pins { - pinctrl-single,pins = < - 0x152 (PIN_INPUT | MUX_MODE0) /* uart1_rx.uart1_rx */ - 0x14c (PIN_OUTPUT |MUX_MODE0) /* uart1_tx.uart1_tx */ - >; - }; - - uart2_pins: pinmux_uart2_pins { - pinctrl-single,pins = < - 0x14a (PIN_INPUT | MUX_MODE0) /* uart2_rx.uart2_rx */ - 0x148 (PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */ - >; - }; - - uart3_pins: pinmux_uart3_pins { - pinctrl-single,pins = < - 0x16e (PIN_INPUT | MUX_MODE0) /* uart3_rx.uart3_rx */ - 0x170 (PIN_OUTPUT | MUX_MODE0) /* uart3_tx.uart3_tx */ - >; - }; - - mmc1_pins: pinmux_mmc1_pins { - pinctrl-single,pins = < - 0x114 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ - 0x116 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ - 0x118 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */ - 0x11a (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */ - 0x11c (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */ - 0x11e (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */ - >; - }; - - dss_dpi_pins: pinmux_dss_dpi_pins { - pinctrl-single,pins = < - 0x0a4 (PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ - 0x0a6 (PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ - 0x0a8 (PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ - 0x0aa (PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ - 0x0ac (PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */ - 0x0ae (PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */ - 0x0b0 (PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */ - 0x0b2 (PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */ - 0x0b4 (PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */ - 0x0b6 (PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */ - 0x0b8 (PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */ - 0x0ba (PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */ - 0x0bc (PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */ - 0x0be (PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */ - 0x0c0 (PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */ - 0x0c2 (PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */ - 0x0c4 (PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */ - 0x0c6 (PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */ - 0x0c8 (PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */ - 0x0ca (PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */ - 0x0cc (PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */ - 0x0ce (PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */ - 0x0d0 (PIN_OUTPUT | MUX_MODE0) /* dss_data18.dss_data18 */ - 0x0d2 (PIN_OUTPUT | MUX_MODE0) /* dss_data19.dss_data19 */ - 0x0d4 (PIN_OUTPUT | MUX_MODE0) /* dss_data20.dss_data20 */ - 0x0d6 (PIN_OUTPUT | MUX_MODE0) /* dss_data21.dss_data21 */ - 0x0d8 (PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */ - 0x0da (PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */ - >; - }; -}; - -&omap3_pmx_core2 { - pinctrl-names = "default"; - pinctrl-0 = < - &hsusb2_2_pins - >; - - hsusb2_2_pins: pinmux_hsusb2_2_pins { - pinctrl-single,pins = < - OMAP3630_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */ - OMAP3630_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */ - OMAP3630_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */ - OMAP3630_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */ - OMAP3630_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */ - OMAP3630_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */ - >; - }; - - spi_gpio_pins: spi_gpio_pinmux { - pinctrl-single,pins = < - OMAP3630_CORE2_IOPAD(0x25d8, PIN_OUTPUT | MUX_MODE4) /* clk */ - OMAP3630_CORE2_IOPAD(0x25e6, PIN_OUTPUT | MUX_MODE4) /* cs */ - OMAP3630_CORE2_IOPAD(0x25e8, PIN_OUTPUT | MUX_MODE4) /* tx */ - OMAP3630_CORE2_IOPAD(0x25e4, PIN_INPUT | MUX_MODE4) /* rx */ - >; - }; -}; - -&i2c1 { - clock-frequency = <2600000>; - - twl: twl@48 { - reg = <0x48>; - interrupts = <7>; /* SYS_NIRQ cascaded to intc */ - interrupt-parent = <&intc>; - }; - - twl_audio: audio { - compatible = "ti,twl4030-audio"; - codec { - }; - }; -}; - -#include "twl4030.dtsi" -#include "twl4030_omap3.dtsi" - -&i2c2 { - clock-frequency = <400000>; - - /* pressure sensor */ - bmp085@77 { - compatible = "bosch,bmp085"; - reg = <0x77>; - interrupt-parent = <&gpio4>; - interrupts = <17 IRQ_TYPE_EDGE_RISING>; - }; - - /* accelerometer */ - bma180@41 { - compatible = "bosch,bma180"; - reg = <0x41>; - interrupt-parent = <&gpio3>; - interrupts = <19 IRQ_TYPE_LEVEL_HIGH>; - }; - - /* leds */ - tca6507@45 { - compatible = "ti,tca6507"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x45>; - - gpio-controller; - #gpio-cells = <2>; - - gta04_led0: red_aux@0 { - label = "gta04:red:aux"; - reg = <0x0>; - }; - - gta04_led1: green_aux@1 { - label = "gta04:green:aux"; - reg = <0x1>; - }; - - gta04_led3: red_power@3 { - label = "gta04:red:power"; - reg = <0x3>; - linux,default-trigger = "default-on"; - }; - - gta04_led4: green_power@4 { - label = "gta04:green:power"; - reg = <0x4>; - }; - - wifi_reset: wifi_reset@6 { - reg = <0x6>; - compatible = "gpio"; - }; - }; - - /* compass aka magnetometer */ - hmc5843@1e { - compatible = "honeywell,hmc5883l"; - reg = <0x1e>; - }; - - /* touchscreen */ - tsc2007@48 { - compatible = "ti,tsc2007"; - reg = <0x48>; - interrupt-parent = <&gpio6>; - interrupts = <0 IRQ_TYPE_EDGE_FALLING>; - gpios = <&gpio6 0 GPIO_ACTIVE_LOW>; - ti,x-plate-ohms = <600>; - }; -}; - -&i2c3 { - clock-frequency = <100000>; -}; - -&usb_otg_hs { - interface-type = <0>; - usb-phy = <&usb2_phy>; - phys = <&usb2_phy>; - phy-names = "usb2-phy"; - mode = <3>; - power = <50>; -}; - -&usbhshost { - port2-mode = "ehci-phy"; -}; - -&usbhsehci { - phys = <0 &hsusb2_phy>; -}; - -&mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - vmmc-supply = <&vmmc1>; - bus-width = <4>; - ti,non-removable; -}; - -&mmc2 { - vmmc-supply = <&vaux4>; - bus-width = <4>; - ti,non-removable; -}; - -&mmc3 { - status = "disabled"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins>; -}; - -&charger { - bb_uvolt = <3200000>; - bb_uamp = <150>; -}; - -/* spare */ -&vaux1 { - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <3000000>; -}; - -/* sensors */ -&vaux2 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; -}; - -/* camera */ -&vaux3 { - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; -}; - -/* WLAN/BT */ -&vaux4 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <3150000>; -}; - -/* GPS LNA */ -&vsim { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <3150000>; -}; - -/* Needed to power the DPI pins */ -&vpll2 { - regulator-always-on; -}; - -&dss { - pinctrl-names = "default"; - pinctrl-0 = < &dss_dpi_pins >; - - status = "okay"; - - port { - dpi_out: endpoint { - remote-endpoint = <&lcd_in>; - data-lines = <24>; - }; - }; -}; - -&gpmc { - ranges = <0 0 0x30000000 0x04>; /* CS0: NAND */ - - nand@0,0 { - reg = <0 0 0>; /* CS0, offset 0 */ - nand-bus-width = <16>; - ti,nand-ecc-opt = "bch8"; - - gpmc,sync-clk-ps = <0>; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <44>; - gpmc,cs-wr-off-ns = <44>; - gpmc,adv-on-ns = <6>; - gpmc,adv-rd-off-ns = <34>; - gpmc,adv-wr-off-ns = <44>; - gpmc,we-off-ns = <40>; - gpmc,oe-off-ns = <54>; - gpmc,access-ns = <64>; - gpmc,rd-cycle-ns = <82>; - gpmc,wr-cycle-ns = <82>; - gpmc,wr-access-ns = <40>; - gpmc,wr-data-mux-bus-ns = <0>; - gpmc,device-width = <2>; - - #address-cells = <1>; - #size-cells = <1>; - - x-loader@0 { - label = "X-Loader"; - reg = <0 0x80000>; - }; - - bootloaders@80000 { - label = "U-Boot"; - reg = <0x80000 0x1e0000>; - }; - - bootloaders_env@260000 { - label = "U-Boot Env"; - reg = <0x260000 0x20000>; - }; - - kernel@280000 { - label = "Kernel"; - reg = <0x280000 0x400000>; - }; - - filesystem@680000 { - label = "File System"; - reg = <0x680000 0xf980000>; - }; - }; -}; diff --git a/arch/arm/boot/dts/omap3-gta04.dtsi b/arch/arm/boot/dts/omap3-gta04.dtsi new file mode 100644 index 0000000..fd34f91 --- /dev/null +++ b/arch/arm/boot/dts/omap3-gta04.dtsi @@ -0,0 +1,451 @@ +/* + * Copyright (C) 2013 Marek Belisko + * + * Based on omap3-beagle-xm.dts + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/dts-v1/; + +#include "omap36xx.dtsi" + +/ { + model = "OMAP3 GTA04"; + compatible = "ti,omap3-gta04", "ti,omap36xx", "ti,omap3"; + + cpus { + cpu@0 { + cpu0-supply = <&vcc>; + }; + }; + + memory { + device_type = "memory"; + reg = <0x80000000 0x20000000>; /* 512 MB */ + }; + + aliases { + display0 = &lcd; + }; + + gpio-keys { + compatible = "gpio-keys"; + + aux-button { + label = "aux"; + linux,code = <169>; + gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; + gpio-key,wakeup; + }; + }; + + sound { + compatible = "ti,omap-twl4030"; + ti,model = "gta04"; + + ti,mcbsp = <&mcbsp2>; + ti,codec = <&twl_audio>; + }; + + spi_lcd { + compatible = "spi-gpio"; + #address-cells = <0x1>; + #size-cells = <0x0>; + pinctrl-names = "default"; + pinctrl-0 = <&spi_gpio_pins>; + + gpio-sck = <&gpio1 12 0>; + gpio-miso = <&gpio1 18 0>; + gpio-mosi = <&gpio1 20 0>; + cs-gpios = <&gpio1 19 0>; + num-chipselects = <1>; + + /* lcd panel */ + lcd: td028ttec1@0 { + compatible = "toppoly,td028ttec1"; + reg = <0>; + spi-max-frequency = <100000>; + spi-cpol; + spi-cpha; + + label = "lcd"; + port { + lcd_in: endpoint { + remote-endpoint = <&dpi_out>; + }; + }; + }; + }; + + hsusb2_phy: hsusb2_phy { + compatible = "usb-nop-xceiv"; + reset-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>; + }; +}; + +&omap3_pmx_core { + pinctrl-names = "default"; + pinctrl-0 = < + &hsusb2_pins + >; + + hsusb2_pins: pinmux_hsusb2_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi1_cs3.hsusb2_data2 */ + OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_clk.hsusb2_data7 */ + OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_simo.hsusb2_data4 */ + OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_somi.hsusb2_data5 */ + OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs0.hsusb2_data6 */ + OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs1.hsusb2_data3 */ + >; + }; + + uart1_pins: pinmux_uart1_pins { + pinctrl-single,pins = < + 0x152 (PIN_INPUT | MUX_MODE0) /* uart1_rx.uart1_rx */ + 0x14c (PIN_OUTPUT |MUX_MODE0) /* uart1_tx.uart1_tx */ + >; + }; + + uart2_pins: pinmux_uart2_pins { + pinctrl-single,pins = < + 0x14a (PIN_INPUT | MUX_MODE0) /* uart2_rx.uart2_rx */ + 0x148 (PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */ + >; + }; + + uart3_pins: pinmux_uart3_pins { + pinctrl-single,pins = < + 0x16e (PIN_INPUT | MUX_MODE0) /* uart3_rx.uart3_rx */ + 0x170 (PIN_OUTPUT | MUX_MODE0) /* uart3_tx.uart3_tx */ + >; + }; + + mmc1_pins: pinmux_mmc1_pins { + pinctrl-single,pins = < + 0x114 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ + 0x116 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ + 0x118 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */ + 0x11a (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */ + 0x11c (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */ + 0x11e (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */ + >; + }; + + dss_dpi_pins: pinmux_dss_dpi_pins { + pinctrl-single,pins = < + 0x0a4 (PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ + 0x0a6 (PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ + 0x0a8 (PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ + 0x0aa (PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ + 0x0ac (PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */ + 0x0ae (PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */ + 0x0b0 (PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */ + 0x0b2 (PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */ + 0x0b4 (PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */ + 0x0b6 (PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */ + 0x0b8 (PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */ + 0x0ba (PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */ + 0x0bc (PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */ + 0x0be (PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */ + 0x0c0 (PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */ + 0x0c2 (PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */ + 0x0c4 (PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */ + 0x0c6 (PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */ + 0x0c8 (PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */ + 0x0ca (PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */ + 0x0cc (PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */ + 0x0ce (PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */ + 0x0d0 (PIN_OUTPUT | MUX_MODE0) /* dss_data18.dss_data18 */ + 0x0d2 (PIN_OUTPUT | MUX_MODE0) /* dss_data19.dss_data19 */ + 0x0d4 (PIN_OUTPUT | MUX_MODE0) /* dss_data20.dss_data20 */ + 0x0d6 (PIN_OUTPUT | MUX_MODE0) /* dss_data21.dss_data21 */ + 0x0d8 (PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */ + 0x0da (PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */ + >; + }; +}; + +&omap3_pmx_core2 { + pinctrl-names = "default"; + pinctrl-0 = < + &hsusb2_2_pins + >; + + hsusb2_2_pins: pinmux_hsusb2_2_pins { + pinctrl-single,pins = < + OMAP3630_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */ + OMAP3630_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */ + OMAP3630_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */ + OMAP3630_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */ + OMAP3630_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */ + OMAP3630_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */ + >; + }; + + spi_gpio_pins: spi_gpio_pinmux { + pinctrl-single,pins = < + OMAP3630_CORE2_IOPAD(0x25d8, PIN_OUTPUT | MUX_MODE4) /* clk */ + OMAP3630_CORE2_IOPAD(0x25e6, PIN_OUTPUT | MUX_MODE4) /* cs */ + OMAP3630_CORE2_IOPAD(0x25e8, PIN_OUTPUT | MUX_MODE4) /* tx */ + OMAP3630_CORE2_IOPAD(0x25e4, PIN_INPUT | MUX_MODE4) /* rx */ + >; + }; +}; + +&i2c1 { + clock-frequency = <2600000>; + + twl: twl@48 { + reg = <0x48>; + interrupts = <7>; /* SYS_NIRQ cascaded to intc */ + interrupt-parent = <&intc>; + }; + + twl_audio: audio { + compatible = "ti,twl4030-audio"; + codec { + }; + }; +}; + +#include "twl4030.dtsi" +#include "twl4030_omap3.dtsi" + +&i2c2 { + clock-frequency = <400000>; + + /* pressure sensor */ + bmp085@77 { + compatible = "bosch,bmp085"; + reg = <0x77>; + interrupt-parent = <&gpio4>; + interrupts = <17 IRQ_TYPE_EDGE_RISING>; + }; + + /* accelerometer */ + bma180@41 { + compatible = "bosch,bma180"; + reg = <0x41>; + interrupt-parent = <&gpio3>; + interrupts = <19 IRQ_TYPE_LEVEL_HIGH>; + }; + + /* leds */ + tca6507@45 { + compatible = "ti,tca6507"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x45>; + + gpio-controller; + #gpio-cells = <2>; + + gta04_led0: red_aux@0 { + label = "gta04:red:aux"; + reg = <0x0>; + }; + + gta04_led1: green_aux@1 { + label = "gta04:green:aux"; + reg = <0x1>; + }; + + gta04_led3: red_power@3 { + label = "gta04:red:power"; + reg = <0x3>; + linux,default-trigger = "default-on"; + }; + + gta04_led4: green_power@4 { + label = "gta04:green:power"; + reg = <0x4>; + }; + + wifi_reset: wifi_reset@6 { + reg = <0x6>; + compatible = "gpio"; + }; + }; + + /* compass aka magnetometer */ + hmc5843@1e { + compatible = "honeywell,hmc5883l"; + reg = <0x1e>; + }; + + /* touchscreen */ + tsc2007@48 { + compatible = "ti,tsc2007"; + reg = <0x48>; + interrupt-parent = <&gpio6>; + interrupts = <0 IRQ_TYPE_EDGE_FALLING>; + gpios = <&gpio6 0 GPIO_ACTIVE_LOW>; + ti,x-plate-ohms = <600>; + }; +}; + +&i2c3 { + clock-frequency = <100000>; +}; + +&usb_otg_hs { + interface-type = <0>; + usb-phy = <&usb2_phy>; + phys = <&usb2_phy>; + phy-names = "usb2-phy"; + mode = <3>; + power = <50>; +}; + +&usbhshost { + port2-mode = "ehci-phy"; +}; + +&usbhsehci { + phys = <0 &hsusb2_phy>; +}; + +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; + vmmc-supply = <&vmmc1>; + bus-width = <4>; + ti,non-removable; +}; + +&mmc2 { + vmmc-supply = <&vaux4>; + bus-width = <4>; + ti,non-removable; +}; + +&mmc3 { + status = "disabled"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins>; +}; + +&charger { + bb_uvolt = <3200000>; + bb_uamp = <150>; +}; + +/* spare */ +&vaux1 { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <3000000>; +}; + +/* sensors */ +&vaux2 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; +}; + +/* camera */ +&vaux3 { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; +}; + +/* WLAN/BT */ +&vaux4 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3150000>; +}; + +/* GPS LNA */ +&vsim { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3150000>; +}; + +/* Needed to power the DPI pins */ +&vpll2 { + regulator-always-on; +}; + +&dss { + pinctrl-names = "default"; + pinctrl-0 = < &dss_dpi_pins >; + + status = "okay"; + + port { + dpi_out: endpoint { + remote-endpoint = <&lcd_in>; + data-lines = <24>; + }; + }; +}; + +&gpmc { + ranges = <0 0 0x30000000 0x04>; /* CS0: NAND */ + + nand@0,0 { + reg = <0 0 0>; /* CS0, offset 0 */ + nand-bus-width = <16>; + ti,nand-ecc-opt = "bch8"; + + gpmc,sync-clk-ps = <0>; + gpmc,cs-on-ns = <0>; + gpmc,cs-rd-off-ns = <44>; + gpmc,cs-wr-off-ns = <44>; + gpmc,adv-on-ns = <6>; + gpmc,adv-rd-off-ns = <34>; + gpmc,adv-wr-off-ns = <44>; + gpmc,we-off-ns = <40>; + gpmc,oe-off-ns = <54>; + gpmc,access-ns = <64>; + gpmc,rd-cycle-ns = <82>; + gpmc,wr-cycle-ns = <82>; + gpmc,wr-access-ns = <40>; + gpmc,wr-data-mux-bus-ns = <0>; + gpmc,device-width = <2>; + + #address-cells = <1>; + #size-cells = <1>; + + x-loader@0 { + label = "X-Loader"; + reg = <0 0x80000>; + }; + + bootloaders@80000 { + label = "U-Boot"; + reg = <0x80000 0x1e0000>; + }; + + bootloaders_env@260000 { + label = "U-Boot Env"; + reg = <0x260000 0x20000>; + }; + + kernel@280000 { + label = "Kernel"; + reg = <0x280000 0x400000>; + }; + + filesystem@680000 { + label = "File System"; + reg = <0x680000 0xf980000>; + }; + }; +}; diff --git a/arch/arm/boot/dts/omap3-gta04a4.dts b/arch/arm/boot/dts/omap3-gta04a4.dts new file mode 100644 index 0000000..c918bb1 --- /dev/null +++ b/arch/arm/boot/dts/omap3-gta04a4.dts @@ -0,0 +1,13 @@ +/* + * Copyright (C) 2014 Marek Belisko + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "omap3-gta04.dtsi" + +/ { + model = "Goldelico GTA04A4"; +}; -- cgit v0.10.2 From 4cf64060a6ee4c2ab609fb915d924bdc98805875 Mon Sep 17 00:00:00 2001 From: Marek Belisko Date: Mon, 28 Jul 2014 21:53:32 +0200 Subject: ARM: dts: Add gta04a3 model Add gta04a3 model with additional acceleromer. Signed-off-by: Marek Belisko Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index b812b6c..455845e 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -262,6 +262,7 @@ dtb-$(CONFIG_ARCH_OMAP3) += am3517-craneboard.dtb \ omap3-devkit8000.dtb \ omap3-evm.dtb \ omap3-evm-37xx.dtb \ + omap3-gta04a3.dtb \ omap3-gta04a4.dtb \ omap3-igep0020.dtb \ omap3-igep0030.dtb \ diff --git a/arch/arm/boot/dts/omap3-gta04a3.dts b/arch/arm/boot/dts/omap3-gta04a3.dts new file mode 100644 index 0000000..3099a89 --- /dev/null +++ b/arch/arm/boot/dts/omap3-gta04a3.dts @@ -0,0 +1,48 @@ +/* + * Copyright (C) 2014 H. Nikolaus Schaller + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "omap3-gta04.dtsi" + +/ { + model = "Goldelico GTA04A3"; +}; + +&i2c2 { + + /* alternate accelerometer that might be installed on some GTA04A3 boards */ + lis302@1d { + compatible = "st,lis331dlh", "st,lis3lv02d"; + reg = <0x1d>; + interrupt-parent = <&gpio3>; + interrupts = <18 (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_EDGE_RISING)>; + Vdd-supply = <&vaux2>; + Vdd_IO-supply = <&vaux2>; + + st,click-single-x; + st,click-single-y; + st,click-single-z; + st,click-thresh-x = <8>; + st,click-thresh-y = <8>; + st,click-thresh-z = <10>; + st,click-click-time-limit = <9>; + st,click-latency = <50>; + st,irq1-click; + st,wakeup-x-lo; + st,wakeup-x-hi; + st,wakeup-y-lo; + st,wakeup-y-hi; + st,wakeup-z-lo; + st,wakeup-z-hi; + st,min-limit-x = <32>; + st,min-limit-y = <3>; + st,min-limit-z = <3>; + st,max-limit-x = <3>; + st,max-limit-y = <32>; + st,max-limit-z = <32>; + }; +}; -- cgit v0.10.2 From c9940680b599300c3fb46e799986b736d394432d Mon Sep 17 00:00:00 2001 From: Marek Belisko Date: Mon, 28 Jul 2014 21:53:33 +0200 Subject: ARM: dts: Add gta04a5 model Add model a5 which have additional jack detection. Signed-off-by: Marek Belisko [tony@atomide.com: fixed a typo for make dtbs to work] Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 455845e..3323028 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -264,6 +264,7 @@ dtb-$(CONFIG_ARCH_OMAP3) += am3517-craneboard.dtb \ omap3-evm-37xx.dtb \ omap3-gta04a3.dtb \ omap3-gta04a4.dtb \ + omap3-gta04a5.dtb \ omap3-igep0020.dtb \ omap3-igep0030.dtb \ omap3-ldp.dtb \ diff --git a/arch/arm/boot/dts/omap3-gta04a5.dts b/arch/arm/boot/dts/omap3-gta04a5.dts new file mode 100644 index 0000000..52b386f --- /dev/null +++ b/arch/arm/boot/dts/omap3-gta04a5.dts @@ -0,0 +1,17 @@ +/* + * Copyright (C) 2014 H. Nikolaus Schaller + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "omap3-gta04.dtsi" + +/ { + model = "Goldelico GTA04A5"; + + sound { + ti,jack-det-gpio = <&twl_gpio 2 0>; /* GTA04A5 only */ + }; +}; -- cgit v0.10.2 From 356649ab6d6412b256a2ff789e50ddbe5d78aaec Mon Sep 17 00:00:00 2001 From: Jaehoon Chung Date: Thu, 7 Aug 2014 16:38:02 +0900 Subject: ARM: dts: rockchip: unuse the slot-node and deprecate the supports-highspeed for dw-mmc dw-mmc controller can support multiple slots. But, there are no use-cases anywhere. So we don't need to support the slot-node for dw-mmc controller. And "supports-highspeed" property in dw-mmc is deprecated. "supports-highspeed" property can be replaced with "cap-sd/mmc-highspeed". Signed-off-by: Jaehoon Chung Reviewed-by: Tushar Behera Reviewed-by: Ulf Hansson Reviewed-by: Heiko Stuebner Acked-by: Seungwon Jeon Signed-off-by: Heiko Stuebner diff --git a/arch/arm/boot/dts/rk3066a-bqcurie2.dts b/arch/arm/boot/dts/rk3066a-bqcurie2.dts index 042f821d..665dd56 100644 --- a/arch/arm/boot/dts/rk3066a-bqcurie2.dts +++ b/arch/arm/boot/dts/rk3066a-bqcurie2.dts @@ -150,12 +150,8 @@ num-slots = <1>; status = "okay"; vmmc-supply = <&vcc_sd0>; - - slot@0 { - reg = <0>; - bus-width = <4>; - disable-wp; - }; + bus-width = <4>; + disable-wp; }; &mmc1 { /* wifi */ @@ -166,11 +162,8 @@ pinctrl-names = "default"; pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_bus4>; - slot@0 { - reg = <0>; - bus-width = <4>; - disable-wp; - }; + bus-width = <4>; + disable-wp; }; &uart0 { diff --git a/arch/arm/boot/dts/rk3188-radxarock.dts b/arch/arm/boot/dts/rk3188-radxarock.dts index 171b610..ef72faf 100644 --- a/arch/arm/boot/dts/rk3188-radxarock.dts +++ b/arch/arm/boot/dts/rk3188-radxarock.dts @@ -181,11 +181,8 @@ status = "okay"; vmmc-supply = <&vcc_sd0>; - slot@0 { - reg = <0>; - bus-width = <4>; - disable-wp; - }; + bus-width = <4>; + disable-wp; }; &pinctrl { -- cgit v0.10.2 From 85095bf30f028f6dcb7d8177ab9b00425c11ca58 Mon Sep 17 00:00:00 2001 From: Doug Anderson Date: Tue, 12 Aug 2014 16:21:13 -0700 Subject: ARM: dts: Add emmc and sdmmc to the rk3288 device tree This adds support for the sdmmc and emmc ports on the rk3288. Signed-off-by: Doug Anderson Acked-by: Arnd Bergmann Signed-off-by: Heiko Stuebner diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index 5950b0a..36be7bb 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -78,6 +78,26 @@ clock-frequency = <24000000>; }; + sdmmc: dwmmc@ff0c0000 { + compatible = "rockchip,rk3288-dw-mshc"; + clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>; + clock-names = "biu", "ciu"; + fifo-depth = <0x100>; + interrupts = ; + reg = <0xff0c0000 0x4000>; + status = "disabled"; + }; + + emmc: dwmmc@ff0f0000 { + compatible = "rockchip,rk3288-dw-mshc"; + clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>; + clock-names = "biu", "ciu"; + fifo-depth = <0x100>; + interrupts = ; + reg = <0xff0f0000 0x4000>; + status = "disabled"; + }; + i2c1: i2c@ff140000 { compatible = "rockchip,rk3288-i2c"; reg = <0xff140000 0x1000>; -- cgit v0.10.2 From 2c31d9498cb85dcf37806237870e8ccf4dbf84e0 Mon Sep 17 00:00:00 2001 From: Doug Anderson Date: Tue, 12 Aug 2014 16:21:14 -0700 Subject: ARM: dts: Enable emmc and sdmmc on the rk3288-evb boards This enables basic SD and eMMC support. Things are not yet running at the fastest speed and we don't have the regulators specified, but we can at least use the eMMC and SD cards now. A note: * Though MMC DDR50 mode is partially supported in the dw_mmc rk3288-specific code in Addy's patch, Addy's patch doesn't add tuning support. That means DDR50 mode is not reliable. From the 3288 TRM: "Tuning is required for other speed modes-such as DDR50-even though the output delay from the card is less than one cycle." Thus, we don't enable MMC DDR50 mode in this patch. Signed-off-by: Doug Anderson Acked-by: Arnd Bergmann Signed-off-by: Heiko Stuebner diff --git a/arch/arm/boot/dts/rk3288-evb.dtsi b/arch/arm/boot/dts/rk3288-evb.dtsi index 4f57209..ebce49a 100644 --- a/arch/arm/boot/dts/rk3288-evb.dtsi +++ b/arch/arm/boot/dts/rk3288-evb.dtsi @@ -49,6 +49,30 @@ }; }; +&emmc { + broken-cd; + bus-width = <8>; + cap-mmc-highspeed; + disable-wp; + non-removable; + num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_pwr &emmc_bus8>; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + card-detect-delay = <200>; + disable-wp; /* wp not hooked up */ + num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; + status = "okay"; +}; + &i2c0 { status = "okay"; }; -- cgit v0.10.2 From 91ff8cd8c3aae34a26b517506cc1ff809401a490 Mon Sep 17 00:00:00 2001 From: Doug Anderson Date: Mon, 11 Aug 2014 11:47:29 -0700 Subject: ARM: dts: Move the PMIC interrupt pinctrl line to rk3288-evb common The PMIC interrupt pinctrl line was added to the rk3288-evb-act8846, but it's the same line on both the ACT8846 version and the RK808 version. This makes a lot of sense since they share the same SoC daugherboard. Move the pinctrl definition to the common file so we can use it for the RK808 version. NOTE: The PMIC interrupt doesn't _actually_ go to the PMIC on the ACT8846 version of the board (it does on the RK808), but our convention is to label things as they're labelled on the schematics. In the very least you can argue that this is the interrupt from the PMIC daughtercard even if it doesn't actually go to the PMIC chip. Signed-off-by: Doug Anderson Signed-off-by: Heiko Stuebner diff --git a/arch/arm/boot/dts/rk3288-evb-act8846.dts b/arch/arm/boot/dts/rk3288-evb-act8846.dts index 7d59ff4..a76dd44 100644 --- a/arch/arm/boot/dts/rk3288-evb-act8846.dts +++ b/arch/arm/boot/dts/rk3288-evb-act8846.dts @@ -26,7 +26,7 @@ interrupts = <4 IRQ_TYPE_EDGE_FALLING>; pinctrl-names = "default"; - pinctrl-0 = <&hym8563_int>; + pinctrl-0 = <&pmic_int>; #clock-cells = <0>; clock-output-names = "xin32k"; @@ -124,11 +124,3 @@ }; }; }; - -&pinctrl { - hym8563 { - hym8563_int: hym8563-int { - rockchip,pins = ; - }; - }; -}; diff --git a/arch/arm/boot/dts/rk3288-evb.dtsi b/arch/arm/boot/dts/rk3288-evb.dtsi index ebce49a..2964370 100644 --- a/arch/arm/boot/dts/rk3288-evb.dtsi +++ b/arch/arm/boot/dts/rk3288-evb.dtsi @@ -108,6 +108,12 @@ }; }; + pmic { + pmic_int: pmic-int { + rockchip,pins = ; + }; + }; + usb { host_vbus_drv: host-vbus-drv { rockchip,pins = <0 14 RK_FUNC_GPIO &pcfg_pull_none>; -- cgit v0.10.2 From 0b8d1d579b4130f33a8776691453238839cb1973 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Sat, 2 Aug 2014 04:04:21 +0400 Subject: ARM: shmobile: r8a7791: add VIN DT support Define the generic R8A7791 parts of the VIN[0-2] device nodes. Add aliases for the VIN[0-2] device nodes. Signed-off-by: Sergei Shtylyov Signed-off-by: Simon Horman diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi index 0d82a4b..0f28921 100644 --- a/arch/arm/boot/dts/r8a7791.dtsi +++ b/arch/arm/boot/dts/r8a7791.dtsi @@ -34,6 +34,9 @@ spi1 = &msiof0; spi2 = &msiof1; spi3 = &msiof2; + vin0 = &vin0; + vin1 = &vin1; + vin2 = &vin2; }; cpus { @@ -518,6 +521,30 @@ status = "disabled"; }; + vin0: video@e6ef0000 { + compatible = "renesas,vin-r8a7791"; + clocks = <&mstp8_clks R8A7791_CLK_VIN0>; + reg = <0 0xe6ef0000 0 0x1000>; + interrupts = <0 188 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + vin1: video@e6ef1000 { + compatible = "renesas,vin-r8a7791"; + clocks = <&mstp8_clks R8A7791_CLK_VIN1>; + reg = <0 0xe6ef1000 0 0x1000>; + interrupts = <0 189 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + vin2: video@e6ef2000 { + compatible = "renesas,vin-r8a7791"; + clocks = <&mstp8_clks R8A7791_CLK_VIN2>; + reg = <0 0xe6ef2000 0 0x1000>; + interrupts = <0 190 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + clocks { #address-cells = <2>; #size-cells = <2>; -- cgit v0.10.2 From 8d62f4f75320db5e95d3610547a26e4487c30742 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Sat, 2 Aug 2014 04:05:54 +0400 Subject: ARM: shmobile: henninger: add VIN0/ADV7180 DT support Define the Henninger board dependent part of the VIN0 device node. Add the device node for Analog Devices ADV7180 video decoder to I2C2 bus. Add the necessary subnodes to interconnect VIN0 and ADV7180 devices. Signed-off-by: Sergei Shtylyov Signed-off-by: Simon Horman diff --git a/arch/arm/boot/dts/r8a7791-henninger.dts b/arch/arm/boot/dts/r8a7791-henninger.dts index 3a2ef0a..f1b56de 100644 --- a/arch/arm/boot/dts/r8a7791-henninger.dts +++ b/arch/arm/boot/dts/r8a7791-henninger.dts @@ -135,6 +135,11 @@ renesas,groups = "usb1"; renesas,function = "usb1"; }; + + vin0_pins: vin0 { + renesas,groups = "vin0_data8", "vin0_clk"; + renesas,function = "vin0"; + }; }; &scif0 { @@ -191,6 +196,19 @@ status = "okay"; clock-frequency = <400000>; + + composite-in@20 { + compatible = "adi,adv7180"; + reg = <0x20>; + remote = <&vin0>; + + port { + adv7180: endpoint { + bus-width = <8>; + remote-endpoint = <&vin0ep>; + }; + }; + }; }; &qspi { @@ -260,3 +278,20 @@ &pciec { status = "okay"; }; + +/* composite video input */ +&vin0 { + status = "ok"; + pinctrl-0 = <&vin0_pins>; + pinctrl-names = "default"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + vin0ep: endpoint { + remote-endpoint = <&adv7180>; + bus-width = <8>; + }; + }; +}; -- cgit v0.10.2 From 2cf088105db14c00ad69df09b9b4a37c2370ff44 Mon Sep 17 00:00:00 2001 From: "sergei.shtylyov@cogentembedded.com" Date: Wed, 6 Aug 2014 22:38:22 +0400 Subject: ARM: shmobile: koelsch: add VIN1/ADV7180 DT support Define the Koelsch board dependent part of the VIN1 device node. Add the device node for Analog Devices ADV7180 video decoder to I2C2 bus. Add the necessary subnodes to interconnect VIN1 and ADV7180 devices. Signed-off-by: Sergei Shtylyov Signed-off-by: Simon Horman diff --git a/arch/arm/boot/dts/r8a7791-koelsch.dts b/arch/arm/boot/dts/r8a7791-koelsch.dts index 23486c0..6be43da 100644 --- a/arch/arm/boot/dts/r8a7791-koelsch.dts +++ b/arch/arm/boot/dts/r8a7791-koelsch.dts @@ -289,6 +289,11 @@ renesas,groups = "usb1"; renesas,function = "usb1"; }; + + vin1_pins: vin1 { + renesas,groups = "vin1_data8", "vin1_clk"; + renesas,function = "vin1"; + }; }; ðer { @@ -412,6 +417,19 @@ status = "okay"; clock-frequency = <400000>; + composite-in@20 { + compatible = "adi,adv7180"; + reg = <0x20>; + remote = <&vin1>; + + port { + adv7180: endpoint { + bus-width = <8>; + remote-endpoint = <&vin1ep>; + }; + }; + }; + eeprom@50 { compatible = "renesas,24c02"; reg = <0x50>; @@ -459,3 +477,20 @@ &cpu0 { cpu0-supply = <&vdd_dvfs>; }; + +/* composite video input */ +&vin1 { + status = "ok"; + pinctrl-0 = <&vin1_pins>; + pinctrl-names = "default"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + vin1ep: endpoint { + remote-endpoint = <&adv7180>; + bus-width = <8>; + }; + }; +}; -- cgit v0.10.2 From c819acdab3bf02795db6d16a17426e21c99c3c28 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Sat, 19 Jul 2014 01:50:23 +0200 Subject: ARM: shmobile: r8a7790: Add DMAC clocks to DT Add the SYS-DMAC0 and SYS-DMAC1 clocks to the MSTP2 clock node. They will be used by the upcoming DMAC DT nodes. Signed-off-by: Laurent Pinchart Signed-off-by: Simon Horman diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index d9ddecb..220662f 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -758,16 +758,19 @@ compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>; clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, - <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>; + <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&zs_clk>, + <&zs_clk>; #clock-cells = <1>; renesas,clock-indices = < R8A7790_CLK_SCIFA2 R8A7790_CLK_SCIFA1 R8A7790_CLK_SCIFA0 R8A7790_CLK_MSIOF2 R8A7790_CLK_SCIFB0 R8A7790_CLK_SCIFB1 R8A7790_CLK_MSIOF1 R8A7790_CLK_MSIOF3 R8A7790_CLK_SCIFB2 + R8A7790_CLK_SYS_DMAC1 R8A7790_CLK_SYS_DMAC0 >; clock-output-names = "scifa2", "scifa1", "scifa0", "msiof2", "scifb0", - "scifb1", "msiof1", "msiof3", "scifb2"; + "scifb1", "msiof1", "msiof3", "scifb2", + "sys-dmac1", "sys-dmac0"; }; mstp3_clks: mstp3_clks@e615013c { compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; -- cgit v0.10.2 From b9fea49c79f23212ff21ef2f305ea4ae865db860 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Sat, 19 Jul 2014 01:50:24 +0200 Subject: ARM: shmobile: r8a7790: Add DMAC devices to DT Instantiate the two system DMA controllers in the r8a7790 device tree. Signed-off-by: Laurent Pinchart Signed-off-by: Simon Horman diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index 220662f..3707f0e 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -217,6 +217,65 @@ <0 3 IRQ_TYPE_LEVEL_HIGH>; }; + dmac0: dma-controller@e6700000 { + compatible = "renesas,rcar-dmac"; + reg = <0 0xe6700000 0 0x20000>; + interrupts = <0 197 IRQ_TYPE_LEVEL_HIGH + 0 200 IRQ_TYPE_LEVEL_HIGH + 0 201 IRQ_TYPE_LEVEL_HIGH + 0 202 IRQ_TYPE_LEVEL_HIGH + 0 203 IRQ_TYPE_LEVEL_HIGH + 0 204 IRQ_TYPE_LEVEL_HIGH + 0 205 IRQ_TYPE_LEVEL_HIGH + 0 206 IRQ_TYPE_LEVEL_HIGH + 0 207 IRQ_TYPE_LEVEL_HIGH + 0 208 IRQ_TYPE_LEVEL_HIGH + 0 209 IRQ_TYPE_LEVEL_HIGH + 0 210 IRQ_TYPE_LEVEL_HIGH + 0 211 IRQ_TYPE_LEVEL_HIGH + 0 212 IRQ_TYPE_LEVEL_HIGH + 0 213 IRQ_TYPE_LEVEL_HIGH + 0 214 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14"; + clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC0>; + clock-names = "fck"; + #dma-cells = <1>; + dma-channels = <15>; + }; + + dmac1: dma-controller@e6720000 { + compatible = "renesas,rcar-dmac"; + reg = <0 0xe6720000 0 0x20000>; + interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH + 0 216 IRQ_TYPE_LEVEL_HIGH + 0 217 IRQ_TYPE_LEVEL_HIGH + 0 218 IRQ_TYPE_LEVEL_HIGH + 0 219 IRQ_TYPE_LEVEL_HIGH + 0 308 IRQ_TYPE_LEVEL_HIGH + 0 309 IRQ_TYPE_LEVEL_HIGH + 0 310 IRQ_TYPE_LEVEL_HIGH + 0 311 IRQ_TYPE_LEVEL_HIGH + 0 312 IRQ_TYPE_LEVEL_HIGH + 0 313 IRQ_TYPE_LEVEL_HIGH + 0 314 IRQ_TYPE_LEVEL_HIGH + 0 315 IRQ_TYPE_LEVEL_HIGH + 0 316 IRQ_TYPE_LEVEL_HIGH + 0 317 IRQ_TYPE_LEVEL_HIGH + 0 318 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14"; + clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC1>; + clock-names = "fck"; + #dma-cells = <1>; + dma-channels = <15>; + }; i2c0: i2c@e6508000 { #address-cells = <1>; #size-cells = <0>; -- cgit v0.10.2 From fde8feefc489652749920f18123ad9e48b427c5e Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Sat, 19 Jul 2014 01:50:25 +0200 Subject: ARM: shmobile: r8a7791: Add DMAC devices to DT Instantiate the two system DMA controllers in the r8a7791 device tree. Signed-off-by: Laurent Pinchart Signed-off-by: Simon Horman diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi index 0f28921..146ed64 100644 --- a/arch/arm/boot/dts/r8a7791.dtsi +++ b/arch/arm/boot/dts/r8a7791.dtsi @@ -209,6 +209,66 @@ <0 17 IRQ_TYPE_LEVEL_HIGH>; }; + dmac0: dma-controller@e6700000 { + compatible = "renesas,rcar-dmac"; + reg = <0 0xe6700000 0 0x20000>; + interrupts = <0 197 IRQ_TYPE_LEVEL_HIGH + 0 200 IRQ_TYPE_LEVEL_HIGH + 0 201 IRQ_TYPE_LEVEL_HIGH + 0 202 IRQ_TYPE_LEVEL_HIGH + 0 203 IRQ_TYPE_LEVEL_HIGH + 0 204 IRQ_TYPE_LEVEL_HIGH + 0 205 IRQ_TYPE_LEVEL_HIGH + 0 206 IRQ_TYPE_LEVEL_HIGH + 0 207 IRQ_TYPE_LEVEL_HIGH + 0 208 IRQ_TYPE_LEVEL_HIGH + 0 209 IRQ_TYPE_LEVEL_HIGH + 0 210 IRQ_TYPE_LEVEL_HIGH + 0 211 IRQ_TYPE_LEVEL_HIGH + 0 212 IRQ_TYPE_LEVEL_HIGH + 0 213 IRQ_TYPE_LEVEL_HIGH + 0 214 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14"; + clocks = <&mstp2_clks R8A7791_CLK_SYS_DMAC0>; + clock-names = "fck"; + #dma-cells = <1>; + dma-channels = <15>; + }; + + dmac1: dma-controller@e6720000 { + compatible = "renesas,rcar-dmac"; + reg = <0 0xe6720000 0 0x20000>; + interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH + 0 216 IRQ_TYPE_LEVEL_HIGH + 0 217 IRQ_TYPE_LEVEL_HIGH + 0 218 IRQ_TYPE_LEVEL_HIGH + 0 219 IRQ_TYPE_LEVEL_HIGH + 0 308 IRQ_TYPE_LEVEL_HIGH + 0 309 IRQ_TYPE_LEVEL_HIGH + 0 310 IRQ_TYPE_LEVEL_HIGH + 0 311 IRQ_TYPE_LEVEL_HIGH + 0 312 IRQ_TYPE_LEVEL_HIGH + 0 313 IRQ_TYPE_LEVEL_HIGH + 0 314 IRQ_TYPE_LEVEL_HIGH + 0 315 IRQ_TYPE_LEVEL_HIGH + 0 316 IRQ_TYPE_LEVEL_HIGH + 0 317 IRQ_TYPE_LEVEL_HIGH + 0 318 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14"; + clocks = <&mstp2_clks R8A7791_CLK_SYS_DMAC1>; + clock-names = "fck"; + #dma-cells = <1>; + dma-channels = <15>; + }; + /* The memory map in the User's Manual maps the cores to bus numbers */ i2c0: i2c@e6508000 { #address-cells = <1>; -- cgit v0.10.2 From 591f2fa4eb0aae09cd76d276bb59e25824a7d408 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 6 Aug 2014 14:59:06 +0200 Subject: ARM: shmobile: r8a7791 dtsi: Enable DMA for QSPI Add a DMA property to the QSPI node Signed-off-by: Geert Uytterhoeven Acked-by: Laurent Pinchart Signed-off-by: Simon Horman diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi index 146ed64..ab55efd 100644 --- a/arch/arm/boot/dts/r8a7791.dtsi +++ b/arch/arm/boot/dts/r8a7791.dtsi @@ -1012,6 +1012,8 @@ reg = <0 0xe6b10000 0 0x2c>; interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp9_clks R8A7791_CLK_QSPI_MOD>; + dmas = <&dmac0 0x17>, <&dmac0 0x18>; + dma-names = "tx", "rx"; num-cs = <1>; #address-cells = <1>; #size-cells = <0>; -- cgit v0.10.2 From a5ce27f5f3285520496af0fe5282395ac07c4138 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 6 Aug 2014 14:59:07 +0200 Subject: ARM: shmobile: r8a7791 dtsi: Enable DMA for MSIOF Add register sets used for access by the DMA engine, and DMA properties to the MSIOF nodes. Signed-off-by: Geert Uytterhoeven Acked-by: Laurent Pinchart Signed-off-by: Simon Horman diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi index ab55efd..f26226e 100644 --- a/arch/arm/boot/dts/r8a7791.dtsi +++ b/arch/arm/boot/dts/r8a7791.dtsi @@ -1022,9 +1022,11 @@ msiof0: spi@e6e20000 { compatible = "renesas,msiof-r8a7791"; - reg = <0 0xe6e20000 0 0x0064>; + reg = <0 0xe6e20000 0 0x0064>, <0 0xe7e20000 0 0x0064>; interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp0_clks R8A7791_CLK_MSIOF0>; + dmas = <&dmac0 0x51>, <&dmac0 0x52>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1032,9 +1034,11 @@ msiof1: spi@e6e10000 { compatible = "renesas,msiof-r8a7791"; - reg = <0 0xe6e10000 0 0x0064>; + reg = <0 0xe6e10000 0 0x0064>, <0 0xe7e10000 0 0x0064>; interrupts = <0 157 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp2_clks R8A7791_CLK_MSIOF1>; + dmas = <&dmac0 0x55>, <&dmac0 0x56>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1042,9 +1046,11 @@ msiof2: spi@e6e00000 { compatible = "renesas,msiof-r8a7791"; - reg = <0 0xe6e00000 0 0x0064>; + reg = <0 0xe6e00000 0 0x0064>, <0 0xe7e00000 0 0x0064>; interrupts = <0 158 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp2_clks R8A7791_CLK_MSIOF2>; + dmas = <&dmac0 0x41>, <&dmac0 0x42>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; -- cgit v0.10.2 From 37cf3d61a94790c6f12c6e6e7a28640b8531a8af Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 6 Aug 2014 14:59:08 +0200 Subject: ARM: shmobile: r8a7790 dtsi: Enable DMA for QSPI Add a DMA property to the QSPI node Signed-off-by: Geert Uytterhoeven Acked-by: Laurent Pinchart Signed-off-by: Simon Horman diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index 3707f0e..6dc328d 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -946,6 +946,8 @@ reg = <0 0xe6b10000 0 0x2c>; interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp9_clks R8A7790_CLK_QSPI_MOD>; + dmas = <&dmac0 0x17>, <&dmac0 0x18>; + dma-names = "tx", "rx"; num-cs = <1>; #address-cells = <1>; #size-cells = <0>; -- cgit v0.10.2 From fbff66886b9c5f657b6649a264551ac572fae0b7 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 6 Aug 2014 14:59:09 +0200 Subject: ARM: shmobile: r8a7790 dtsi: Enable DMA for MSIOF Add register sets used for access by the DMA engine, and DMA properties to the MSIOF nodes. Signed-off-by: Geert Uytterhoeven Acked-by: Laurent Pinchart Signed-off-by: Simon Horman diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index 6dc328d..60f8551 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -956,9 +956,11 @@ msiof0: spi@e6e20000 { compatible = "renesas,msiof-r8a7790"; - reg = <0 0xe6e20000 0 0x0064>; + reg = <0 0xe6e20000 0 0x0064>, <0 0xe7e20000 0 0x0064>; interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp0_clks R8A7790_CLK_MSIOF0>; + dmas = <&dmac0 0x51>, <&dmac0 0x52>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -966,9 +968,11 @@ msiof1: spi@e6e10000 { compatible = "renesas,msiof-r8a7790"; - reg = <0 0xe6e10000 0 0x0064>; + reg = <0 0xe6e10000 0 0x0064>, <0 0xe7e10000 0 0x0064>; interrupts = <0 157 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp2_clks R8A7790_CLK_MSIOF1>; + dmas = <&dmac0 0x55>, <&dmac0 0x56>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -976,9 +980,11 @@ msiof2: spi@e6e00000 { compatible = "renesas,msiof-r8a7790"; - reg = <0 0xe6e00000 0 0x0064>; + reg = <0 0xe6e00000 0 0x0064>, <0 0xe7e00000 0 0x0064>; interrupts = <0 158 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp2_clks R8A7790_CLK_MSIOF2>; + dmas = <&dmac0 0x41>, <&dmac0 0x42>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -986,9 +992,11 @@ msiof3: spi@e6c90000 { compatible = "renesas,msiof-r8a7790"; - reg = <0 0xe6c90000 0 0x0064>; + reg = <0 0xe6c90000 0 0x0064>, <0 0xe7c90000 0 0x0064>; interrupts = <0 159 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp2_clks R8A7790_CLK_MSIOF3>; + dmas = <&dmac0 0x45>, <&dmac0 0x46>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; -- cgit v0.10.2 From 9f685bfc30edb4cba5d5ae142a9967cd0d74c40a Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Wed, 13 Aug 2014 00:16:18 +0400 Subject: ARM: shmobile: r8a7790: add VIN device nodes Add device nodes for the four video input controllers on the R8A7790. Signed-off-by: Ben Dooks [Sergei: renamed VIN device nodes, edited changelog] Signed-off-by: Sergei Shtylyov Signed-off-by: Simon Horman diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index 60f8551..2278bd0 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -33,6 +33,10 @@ spi2 = &msiof1; spi3 = &msiof2; spi4 = &msiof3; + vin0 = &vin0; + vin1 = &vin1; + vin2 = &vin2; + vin3 = &vin3; }; cpus { @@ -532,6 +536,38 @@ status = "disabled"; }; + vin0: video@e6ef0000 { + compatible = "renesas,vin-r8a7790"; + clocks = <&mstp8_clks R8A7790_CLK_VIN0>; + reg = <0 0xe6ef0000 0 0x1000>; + interrupts = <0 188 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + vin1: video@e6ef1000 { + compatible = "renesas,vin-r8a7790"; + clocks = <&mstp8_clks R8A7790_CLK_VIN1>; + reg = <0 0xe6ef1000 0 0x1000>; + interrupts = <0 189 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + vin2: video@e6ef2000 { + compatible = "renesas,vin-r8a7790"; + clocks = <&mstp8_clks R8A7790_CLK_VIN2>; + reg = <0 0xe6ef2000 0 0x1000>; + interrupts = <0 190 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + vin3: video@e6ef3000 { + compatible = "renesas,vin-r8a7790"; + clocks = <&mstp8_clks R8A7790_CLK_VIN3>; + reg = <0 0xe6ef3000 0 0x1000>; + interrupts = <0 191 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + clocks { #address-cells = <2>; #size-cells = <2>; -- cgit v0.10.2 From d594c9775409a4276133db5e34dbd791329c5eae Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Wed, 13 Aug 2014 00:18:26 +0400 Subject: ARM: shmobile: lager: add VIN1/ADV7180 device nodes Add the Lager board specific device node part for VIN1 (composite video in); add the device node for Analog Devices ADV7180 video decoder to IIC2 bus. Add the necessary subnodes to interconnect VIN1 and ADV7180 devices. Signed-off-by: Ben Dooks [Sergei: rebased, edited changelog and summary] Signed-off-by: Sergei Shtylyov Signed-off-by: Simon Horman diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts index 856b423..b5f56bc 100644 --- a/arch/arm/boot/dts/r8a7790-lager.dts +++ b/arch/arm/boot/dts/r8a7790-lager.dts @@ -234,6 +234,11 @@ renesas,groups = "usb2"; renesas,function = "usb2"; }; + + vin1_pins: vin { + renesas,groups = "vin1_data8", "vin1_clk"; + renesas,function = "vin1"; + }; }; ðer { @@ -366,6 +371,19 @@ status = "ok"; pinctrl-0 = <&iic2_pins>; pinctrl-names = "default"; + + composite-in@20 { + compatible = "adi,adv7180"; + reg = <0x20>; + remote = <&vin1>; + + port { + adv7180: endpoint { + bus-width = <8>; + remote-endpoint = <&vin1ep0>; + }; + }; + }; }; &iic3 { @@ -401,3 +419,21 @@ pinctrl-0 = <&usb2_pins>; pinctrl-names = "default"; }; + +/* composite video input */ +&vin1 { + pinctrl-0 = <&vin1_pins>; + pinctrl-names = "default"; + + status = "ok"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + vin1ep0: endpoint { + remote-endpoint = <&adv7180>; + bus-width = <8>; + }; + }; +}; -- cgit v0.10.2 From 3b1213f551145c124630fb592a8321724a40da32 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Wed, 30 Jul 2014 20:56:07 +0800 Subject: ARM: dts: sun8i: add rtc device node sun8i shares the same rtc hardware as sun6i. Now that we have a driver for it, add a device node to the DTSI for it so we can use it. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard diff --git a/arch/arm/boot/dts/sun8i-a23.dtsi b/arch/arm/boot/dts/sun8i-a23.dtsi index 54ac0787..62f002e 100644 --- a/arch/arm/boot/dts/sun8i-a23.dtsi +++ b/arch/arm/boot/dts/sun8i-a23.dtsi @@ -285,6 +285,12 @@ interrupts = <1 9 0xf04>; }; + rtc: rtc@01f00000 { + compatible = "allwinner,sun6i-a31-rtc"; + reg = <0x01f00000 0x54>; + interrupts = <0 40 4>, <0 41 4>; + }; + prcm@01f01400 { compatible = "allwinner,sun8i-a23-prcm"; reg = <0x01f01400 0x200>; -- cgit v0.10.2 From 5e7004351a8f144400873f0ad34690ec7cc97f01 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Wed, 30 Jul 2014 20:56:06 +0800 Subject: ARM: dts: sun6i: add rtc device node Now that we have a driver for sun6i's rtc hardware, add a device node for it so we can use it. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi index 44b07e5..8fdf90d 100644 --- a/arch/arm/boot/dts/sun6i-a31.dtsi +++ b/arch/arm/boot/dts/sun6i-a31.dtsi @@ -779,6 +779,12 @@ interrupts = <1 9 0xf04>; }; + rtc: rtc@01f00000 { + compatible = "allwinner,sun6i-a31-rtc"; + reg = <0x01f00000 0x54>; + interrupts = <0 40 4>, <0 41 4>; + }; + nmi_intc: interrupt-controller@01f00c0c { compatible = "allwinner,sun6i-a31-sc-nmi"; interrupt-controller; -- cgit v0.10.2 From 1324f53211398cd157edbedfe933fe21a9628b99 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Emilio=20L=C3=B3pez?= Date: Mon, 4 Aug 2014 17:09:57 -0300 Subject: ARM: sun4i: dt: Add node to represent the DMA controller MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Let's add a node to represent the A10 DMA controller on the device tree. Signed-off-by: Emilio López Reviewed-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi index 459cb63..ce2fbb3 100644 --- a/arch/arm/boot/dts/sun4i-a10.dtsi +++ b/arch/arm/boot/dts/sun4i-a10.dtsi @@ -339,6 +339,14 @@ #size-cells = <1>; ranges; + dma: dma-controller@01c02000 { + compatible = "allwinner,sun4i-a10-dma"; + reg = <0x01c02000 0x1000>; + interrupts = <27>; + clocks = <&ahb_gates 6>; + #dma-cells = <2>; + }; + spi0: spi@01c05000 { compatible = "allwinner,sun4i-a10-spi"; reg = <0x01c05000 0x1000>; -- cgit v0.10.2 From 6a5775e482c4e6639090dd1a2c349d325da8732b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Emilio=20L=C3=B3pez?= Date: Mon, 4 Aug 2014 17:09:58 -0300 Subject: ARM: sun5i: dt: Add nodes to represent the DMA controllers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The A10S and A13 SoCs have sun4i-compatible DMA controllers. Let's add the corresponding nodes to represent them on the device tree. Signed-off-by: Emilio López Reviewed-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi index 24b0ad3..aa6f126 100644 --- a/arch/arm/boot/dts/sun5i-a10s.dtsi +++ b/arch/arm/boot/dts/sun5i-a10s.dtsi @@ -300,6 +300,14 @@ #size-cells = <1>; ranges; + dma: dma-controller@01c02000 { + compatible = "allwinner,sun4i-a10-dma"; + reg = <0x01c02000 0x1000>; + interrupts = <27>; + clocks = <&ahb_gates 6>; + #dma-cells = <2>; + }; + spi0: spi@01c05000 { compatible = "allwinner,sun4i-a10-spi"; reg = <0x01c05000 0x1000>; diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi index bf86e65..cce04d1 100644 --- a/arch/arm/boot/dts/sun5i-a13.dtsi +++ b/arch/arm/boot/dts/sun5i-a13.dtsi @@ -298,6 +298,14 @@ #size-cells = <1>; ranges; + dma: dma-controller@01c02000 { + compatible = "allwinner,sun4i-a10-dma"; + reg = <0x01c02000 0x1000>; + interrupts = <27>; + clocks = <&ahb_gates 6>; + #dma-cells = <2>; + }; + spi0: spi@01c05000 { compatible = "allwinner,sun4i-a10-spi"; reg = <0x01c05000 0x1000>; -- cgit v0.10.2 From 316e0b0eebcfb030cdf265554fb34ef78380bf5f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Emilio=20L=C3=B3pez?= Date: Mon, 4 Aug 2014 17:09:59 -0300 Subject: ARM: sun7i: dt: Add node to represent the DMA controller MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The A20 SoC has a sun4i-compatible DMA controller. Let's add a node to represent it on the device tree. Signed-off-by: Emilio López Reviewed-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index 4011628..c13b832 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -423,6 +423,14 @@ interrupts = <0 0 4>; }; + dma: dma-controller@01c02000 { + compatible = "allwinner,sun4i-a10-dma"; + reg = <0x01c02000 0x1000>; + interrupts = <0 27 4>; + clocks = <&ahb_gates 6>; + #dma-cells = <2>; + }; + spi0: spi@01c05000 { compatible = "allwinner,sun4i-a10-spi"; reg = <0x01c05000 0x1000>; -- cgit v0.10.2 From 4192ff81174609e7d548e7a04d6fd940e860472e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Emilio=20L=C3=B3pez?= Date: Mon, 4 Aug 2014 17:10:00 -0300 Subject: ARM: sun4i: dt: enable DMA on SPI MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit All of our SPI controllers support DMA transfers, so let's add the properties here so they can be used when it's best to do so. Signed-off-by: Emilio López Reviewed-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi index ce2fbb3..14cf436 100644 --- a/arch/arm/boot/dts/sun4i-a10.dtsi +++ b/arch/arm/boot/dts/sun4i-a10.dtsi @@ -353,6 +353,8 @@ interrupts = <10>; clocks = <&ahb_gates 20>, <&spi0_clk>; clock-names = "ahb", "mod"; + dmas = <&dma 1 27>, <&dma 1 26>; + dma-names = "rx", "tx"; status = "disabled"; #address-cells = <1>; #size-cells = <0>; @@ -364,6 +366,8 @@ interrupts = <11>; clocks = <&ahb_gates 21>, <&spi1_clk>; clock-names = "ahb", "mod"; + dmas = <&dma 1 9>, <&dma 1 8>; + dma-names = "rx", "tx"; status = "disabled"; #address-cells = <1>; #size-cells = <0>; @@ -459,6 +463,8 @@ interrupts = <12>; clocks = <&ahb_gates 22>, <&spi2_clk>; clock-names = "ahb", "mod"; + dmas = <&dma 1 29>, <&dma 1 28>; + dma-names = "rx", "tx"; status = "disabled"; #address-cells = <1>; #size-cells = <0>; @@ -498,6 +504,8 @@ interrupts = <50>; clocks = <&ahb_gates 23>, <&spi3_clk>; clock-names = "ahb", "mod"; + dmas = <&dma 1 31>, <&dma 1 30>; + dma-names = "rx", "tx"; status = "disabled"; #address-cells = <1>; #size-cells = <0>; -- cgit v0.10.2 From fed4c5c676f41359c7dbee635bd98e25e54c40f4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Emilio=20L=C3=B3pez?= Date: Mon, 4 Aug 2014 17:10:01 -0300 Subject: ARM: sun5i: dt: enable DMA on SPI MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit All of our SPI controllers support DMA transfers, so let's add the properties here so they can be used when it's best to do so. Signed-off-by: Emilio López Reviewed-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi index aa6f126..02aa41f 100644 --- a/arch/arm/boot/dts/sun5i-a10s.dtsi +++ b/arch/arm/boot/dts/sun5i-a10s.dtsi @@ -314,6 +314,8 @@ interrupts = <10>; clocks = <&ahb_gates 20>, <&spi0_clk>; clock-names = "ahb", "mod"; + dmas = <&dma 1 27>, <&dma 1 26>; + dma-names = "rx", "tx"; status = "disabled"; #address-cells = <1>; #size-cells = <0>; @@ -325,6 +327,8 @@ interrupts = <11>; clocks = <&ahb_gates 21>, <&spi1_clk>; clock-names = "ahb", "mod"; + dmas = <&dma 1 9>, <&dma 1 8>; + dma-names = "rx", "tx"; status = "disabled"; #address-cells = <1>; #size-cells = <0>; @@ -411,6 +415,8 @@ interrupts = <12>; clocks = <&ahb_gates 22>, <&spi2_clk>; clock-names = "ahb", "mod"; + dmas = <&dma 1 29>, <&dma 1 28>; + dma-names = "rx", "tx"; status = "disabled"; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi index cce04d1..d8f02ee 100644 --- a/arch/arm/boot/dts/sun5i-a13.dtsi +++ b/arch/arm/boot/dts/sun5i-a13.dtsi @@ -312,6 +312,8 @@ interrupts = <10>; clocks = <&ahb_gates 20>, <&spi0_clk>; clock-names = "ahb", "mod"; + dmas = <&dma 1 27>, <&dma 1 26>; + dma-names = "rx", "tx"; status = "disabled"; #address-cells = <1>; #size-cells = <0>; @@ -323,6 +325,8 @@ interrupts = <11>; clocks = <&ahb_gates 21>, <&spi1_clk>; clock-names = "ahb", "mod"; + dmas = <&dma 1 9>, <&dma 1 8>; + dma-names = "rx", "tx"; status = "disabled"; #address-cells = <1>; #size-cells = <0>; @@ -384,6 +388,8 @@ interrupts = <12>; clocks = <&ahb_gates 22>, <&spi2_clk>; clock-names = "ahb", "mod"; + dmas = <&dma 1 29>, <&dma 1 28>; + dma-names = "rx", "tx"; status = "disabled"; #address-cells = <1>; #size-cells = <0>; -- cgit v0.10.2 From ffec7210e11bb06c970c83ea0c3f2d7a1142458f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Emilio=20L=C3=B3pez?= Date: Mon, 4 Aug 2014 17:10:02 -0300 Subject: ARM: sun7i: dt: enable DMA on SPI MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit All of our SPI controllers support DMA transfers, so let's add the properties here so they can be used when it's best to do so. Signed-off-by: Emilio López Reviewed-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index c13b832..db22ef9 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -437,6 +437,8 @@ interrupts = <0 10 4>; clocks = <&ahb_gates 20>, <&spi0_clk>; clock-names = "ahb", "mod"; + dmas = <&dma 1 27>, <&dma 1 26>; + dma-names = "rx", "tx"; status = "disabled"; #address-cells = <1>; #size-cells = <0>; @@ -448,6 +450,8 @@ interrupts = <0 11 4>; clocks = <&ahb_gates 21>, <&spi1_clk>; clock-names = "ahb", "mod"; + dmas = <&dma 1 9>, <&dma 1 8>; + dma-names = "rx", "tx"; status = "disabled"; #address-cells = <1>; #size-cells = <0>; @@ -543,6 +547,8 @@ interrupts = <0 12 4>; clocks = <&ahb_gates 22>, <&spi2_clk>; clock-names = "ahb", "mod"; + dmas = <&dma 1 29>, <&dma 1 28>; + dma-names = "rx", "tx"; status = "disabled"; #address-cells = <1>; #size-cells = <0>; @@ -582,6 +588,8 @@ interrupts = <0 50 4>; clocks = <&ahb_gates 23>, <&spi3_clk>; clock-names = "ahb", "mod"; + dmas = <&dma 1 31>, <&dma 1 30>; + dma-names = "rx", "tx"; status = "disabled"; #address-cells = <1>; #size-cells = <0>; -- cgit v0.10.2 From 6b2b16f5790e4187e1b38dfe495ae08eda235485 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Sun, 17 Aug 2014 11:52:07 +0800 Subject: ARM: dts: sun8i: Add PIO controller node to the sun8i dtsi Now that we have a driver for the sun8i PIO controller, add the corresponding device node to the dtsi. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard diff --git a/arch/arm/boot/dts/sun8i-a23.dtsi b/arch/arm/boot/dts/sun8i-a23.dtsi index 62f002e..08184f6 100644 --- a/arch/arm/boot/dts/sun8i-a23.dtsi +++ b/arch/arm/boot/dts/sun8i-a23.dtsi @@ -187,6 +187,20 @@ #size-cells = <1>; ranges; + pio: pinctrl@01c20800 { + compatible = "allwinner,sun8i-a23-pinctrl"; + reg = <0x01c20800 0x400>; + interrupts = <0 11 4>, + <0 15 4>, + <0 17 4>; + clocks = <&apb1_gates 5>; + gpio-controller; + interrupt-controller; + #address-cells = <1>; + #size-cells = <0>; + #gpio-cells = <3>; + }; + ahb1_rst: reset@01c202c0 { #reset-cells = <1>; compatible = "allwinner,sun6i-a31-clock-reset"; -- cgit v0.10.2 From b6a8711261b2979051832d1389d14c35dbf09dc6 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Sun, 17 Aug 2014 11:52:08 +0800 Subject: ARM: dts: sun8i: Add R_PIO controller node to the dtsi Now that we have a driver for the R_PIO controller, add the corresponding device node to the dtsi. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard diff --git a/arch/arm/boot/dts/sun8i-a23.dtsi b/arch/arm/boot/dts/sun8i-a23.dtsi index 08184f6..cb1fbfc 100644 --- a/arch/arm/boot/dts/sun8i-a23.dtsi +++ b/arch/arm/boot/dts/sun8i-a23.dtsi @@ -359,5 +359,18 @@ resets = <&apb0_rst 4>; status = "disabled"; }; + + r_pio: pinctrl@01f02c00 { + compatible = "allwinner,sun8i-a23-r-pinctrl"; + reg = <0x01f02c00 0x400>; + interrupts = <0 45 4>; + clocks = <&apb0_gates 0>; + resets = <&apb0_rst 0>; + gpio-controller; + interrupt-controller; + #address-cells = <1>; + #size-cells = <0>; + #gpio-cells = <3>; + }; }; }; -- cgit v0.10.2 From c4021571e35d10233d331773124568ef94cee66d Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Sun, 17 Aug 2014 11:52:09 +0800 Subject: ARM: dts: sun8i: Add pinmux set for uart0 uart0 on sun8i is only muxed with mmc0, which makes it a poor choice for the console. However, some tablets only have pads for uart0 available on the circuit board. Here we add the uart0 pinmux set for people who need it. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard diff --git a/arch/arm/boot/dts/sun8i-a23.dtsi b/arch/arm/boot/dts/sun8i-a23.dtsi index cb1fbfc..cbd481e 100644 --- a/arch/arm/boot/dts/sun8i-a23.dtsi +++ b/arch/arm/boot/dts/sun8i-a23.dtsi @@ -199,6 +199,13 @@ #address-cells = <1>; #size-cells = <0>; #gpio-cells = <3>; + + uart0_pins_a: uart0@0 { + allwinner,pins = "PF2", "PF4"; + allwinner,function = "uart0"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; }; ahb1_rst: reset@01c202c0 { -- cgit v0.10.2 From 813097915853100d6cb0655c75f64e67a1ef57a8 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Sun, 17 Aug 2014 11:52:10 +0800 Subject: ARM: dts: sun8i: Add pin muxing option for R_UART R_UART is available on extra pads on certain tablets, which makes it ideal for use as a console. Here we add the pins for it. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard diff --git a/arch/arm/boot/dts/sun8i-a23.dtsi b/arch/arm/boot/dts/sun8i-a23.dtsi index cbd481e..32c195c 100644 --- a/arch/arm/boot/dts/sun8i-a23.dtsi +++ b/arch/arm/boot/dts/sun8i-a23.dtsi @@ -378,6 +378,13 @@ #address-cells = <1>; #size-cells = <0>; #gpio-cells = <3>; + + r_uart_pins_a: r_uart@0 { + allwinner,pins = "PL2", "PL3"; + allwinner,function = "s_uart"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; }; }; }; -- cgit v0.10.2 From 1c602064e00a81b1600bed6b2fe17dffe80b01e0 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Sun, 17 Aug 2014 11:52:11 +0800 Subject: ARM: dts: sun8i: ippo-q8h: Add pinctrl properties for R_UART Now that we have R_PIO controller support and the pinmux for R_UART, add the correct pinctrl properties to the R_UART node. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard diff --git a/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts b/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts index 34002e3..224f53e 100644 --- a/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts +++ b/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts @@ -24,6 +24,8 @@ soc@01c00000 { r_uart: serial@01f02800 { + pinctrl-names = "default"; + pinctrl-0 = <&r_uart_pins_a>; status = "okay"; }; }; -- cgit v0.10.2 From 4b7ecb38d87045968f477a4a4e98b859cd66b9b4 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Sun, 17 Aug 2014 11:52:12 +0800 Subject: ARM: dts: sun8i: Add mmc clocks to the dtsi The MMC module clocks on sun8i are the same as those found on previous Allwinner SoCs, module 0 clocks. This patch adds the clocks nodes to the dtsi with existing drivers. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard diff --git a/arch/arm/boot/dts/sun8i-a23.dtsi b/arch/arm/boot/dts/sun8i-a23.dtsi index 32c195c..9bd5dcc 100644 --- a/arch/arm/boot/dts/sun8i-a23.dtsi +++ b/arch/arm/boot/dts/sun8i-a23.dtsi @@ -179,6 +179,30 @@ "apb2_uart1", "apb2_uart2", "apb2_uart3", "apb2_uart4"; }; + + mmc0_clk: clk@01c20088 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-mod0-clk"; + reg = <0x01c20088 0x4>; + clocks = <&osc24M>, <&pll6>; + clock-output-names = "mmc0"; + }; + + mmc1_clk: clk@01c2008c { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-mod0-clk"; + reg = <0x01c2008c 0x4>; + clocks = <&osc24M>, <&pll6>; + clock-output-names = "mmc1"; + }; + + mmc2_clk: clk@01c20090 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-mod0-clk"; + reg = <0x01c20090 0x4>; + clocks = <&osc24M>, <&pll6>; + clock-output-names = "mmc2"; + }; }; soc@01c00000 { -- cgit v0.10.2 From cdb6fd6798339efd6e1cb768d9d504929342b91b Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Sun, 17 Aug 2014 11:52:13 +0800 Subject: ARM: dts: sun8i: Add pin-muxing info for the mmc controllers This adds pin-muxing info for the mmc controller / port combinations which are known to be used on actual boards. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard diff --git a/arch/arm/boot/dts/sun8i-a23.dtsi b/arch/arm/boot/dts/sun8i-a23.dtsi index 9bd5dcc..342b52a 100644 --- a/arch/arm/boot/dts/sun8i-a23.dtsi +++ b/arch/arm/boot/dts/sun8i-a23.dtsi @@ -230,6 +230,20 @@ allwinner,drive = <0>; allwinner,pull = <0>; }; + + mmc0_pins_a: mmc0@0 { + allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5"; + allwinner,function = "mmc0"; + allwinner,drive = <2>; + allwinner,pull = <0>; + }; + + mmc1_pins_a: mmc1@0 { + allwinner,pins = "PG0","PG1","PG2","PG3","PG4","PG5"; + allwinner,function = "mmc1"; + allwinner,drive = <2>; + allwinner,pull = <0>; + }; }; ahb1_rst: reset@01c202c0 { -- cgit v0.10.2 From eacda1f11fcb8e38cdc9954c1f9cce295315bcab Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Sun, 17 Aug 2014 11:52:14 +0800 Subject: ARM: dts: sun8i: Add mmc controller nodes Add nodes for the 3 mmc controllers found on A23 SoCs to the sun8i DTSI. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard diff --git a/arch/arm/boot/dts/sun8i-a23.dtsi b/arch/arm/boot/dts/sun8i-a23.dtsi index 342b52a..284522e 100644 --- a/arch/arm/boot/dts/sun8i-a23.dtsi +++ b/arch/arm/boot/dts/sun8i-a23.dtsi @@ -211,6 +211,39 @@ #size-cells = <1>; ranges; + mmc0: mmc@01c0f000 { + compatible = "allwinner,sun5i-a13-mmc"; + reg = <0x01c0f000 0x1000>; + clocks = <&ahb1_gates 8>, <&mmc0_clk>; + clock-names = "ahb", "mmc"; + resets = <&ahb1_rst 8>; + reset-names = "ahb"; + interrupts = <0 60 4>; + status = "disabled"; + }; + + mmc1: mmc@01c10000 { + compatible = "allwinner,sun5i-a13-mmc"; + reg = <0x01c10000 0x1000>; + clocks = <&ahb1_gates 9>, <&mmc1_clk>; + clock-names = "ahb", "mmc"; + resets = <&ahb1_rst 9>; + reset-names = "ahb"; + interrupts = <0 61 4>; + status = "disabled"; + }; + + mmc2: mmc@01c11000 { + compatible = "allwinner,sun5i-a13-mmc"; + reg = <0x01c11000 0x1000>; + clocks = <&ahb1_gates 10>, <&mmc2_clk>; + clock-names = "ahb", "mmc"; + resets = <&ahb1_rst 10>; + reset-names = "ahb"; + interrupts = <0 62 4>; + status = "disabled"; + }; + pio: pinctrl@01c20800 { compatible = "allwinner,sun8i-a23-pinctrl"; reg = <0x01c20800 0x400>; -- cgit v0.10.2 From cd78d3f2d716c291481206d4f87f1eeb20278f24 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Sun, 17 Aug 2014 11:52:15 +0800 Subject: ARM: dts: sun8i: Enable mmc controller on ippo-q8h-v5 The card detect pin setting was taken from the original fex file, and is confirmed to work. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard diff --git a/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts b/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts index 224f53e..ef1e4f3 100644 --- a/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts +++ b/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts @@ -13,6 +13,7 @@ /dts-v1/; /include/ "sun8i-a23.dtsi" +/include/ "sunxi-common-regulators.dtsi" / { model = "Ippo Q8H Dual Core Tablet (v5)"; @@ -23,6 +24,25 @@ }; soc@01c00000 { + mmc0: mmc@01c0f000 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_q8h>; + vmmc-supply = <®_vcc3v0>; + bus-width = <4>; + cd-gpios = <&pio 1 4 0>; /* PB4 */ + cd-inverted; + status = "okay"; + }; + + pinctrl@01c20800 { + mmc0_cd_pin_q8h: mmc0_cd_pin@0 { + allwinner,pins = "PB4"; + allwinner,function = "gpio_in"; + allwinner,drive = <0>; + allwinner,pull = <1>; + }; + }; + r_uart: serial@01f02800 { pinctrl-names = "default"; pinctrl-0 = <&r_uart_pins_a>; -- cgit v0.10.2 From 1890f518d9dd62f02c23046890ce5c288906a045 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Sun, 17 Aug 2014 11:52:16 +0800 Subject: ARM: dts: sun8i: Add pin-muxing info for the i2c controllers This adds pin-muxing info for the i2c controller / port combinations which are known to be used on actual boards. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard diff --git a/arch/arm/boot/dts/sun8i-a23.dtsi b/arch/arm/boot/dts/sun8i-a23.dtsi index 284522e..9386d1f 100644 --- a/arch/arm/boot/dts/sun8i-a23.dtsi +++ b/arch/arm/boot/dts/sun8i-a23.dtsi @@ -277,6 +277,27 @@ allwinner,drive = <2>; allwinner,pull = <0>; }; + + i2c0_pins_a: i2c0@0 { + allwinner,pins = "PH2", "PH3"; + allwinner,function = "i2c0"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + + i2c1_pins_a: i2c1@0 { + allwinner,pins = "PH4", "PH5"; + allwinner,function = "i2c1"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + + i2c2_pins_a: i2c2@0 { + allwinner,pins = "PE12", "PE13"; + allwinner,function = "i2c2"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; }; ahb1_rst: reset@01c202c0 { -- cgit v0.10.2 From dd2d62dfede7aa2bd87b3fb07db0c7450ca7ea41 Mon Sep 17 00:00:00 2001 From: Gregory CLEMENT Date: Thu, 31 Jul 2014 16:32:02 +0200 Subject: ARM: mvebu: Add RTC support for Armada 375 The Armada 375 SoC has the same real time clock as the one used in other Marvell EBU platforms. This patch consequently updates the Device Tree of the Armada 375 SoC to describe the internal RTC. Signed-off-by: Gregory CLEMENT Link: https://lkml.kernel.org/r/1406817122-15675-1-git-send-email-gregory.clement@free-electrons.com Signed-off-by: Jason Cooper diff --git a/arch/arm/boot/dts/armada-375.dtsi b/arch/arm/boot/dts/armada-375.dtsi index c1e49e7..de65714 100644 --- a/arch/arm/boot/dts/armada-375.dtsi +++ b/arch/arm/boot/dts/armada-375.dtsi @@ -185,6 +185,12 @@ }; }; + rtc@10300 { + compatible = "marvell,orion-rtc"; + reg = <0x10300 0x20>; + interrupts = ; + }; + spi0: spi@10600 { compatible = "marvell,orion-spi"; reg = <0x10600 0x50>; -- cgit v0.10.2 From a43f99d260d30be8480f76b2c3eeb283a7115623 Mon Sep 17 00:00:00 2001 From: Ezequiel Garcia Date: Mon, 11 Aug 2014 09:14:36 -0300 Subject: ARM: mvebu: Add network pin mux configuration for the Armada 370 SoC This commit adds the pin mux configuration for the two network interfaces and the MDIO interface in the Armada 370 SoC .dtsi file. Only the configuration for RGMII is added for now. Acked-by: Sebastian Hesselbarth Signed-off-by: Ezequiel Garcia Acked-by: Andrew Lunn Link: https://lkml.kernel.org/r/1407759281-11513-2-git-send-email-ezequiel.garcia@free-electrons.com Signed-off-by: Jason Cooper diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi index 21b588b..f2c55f3 100644 --- a/arch/arm/boot/dts/armada-370.dtsi +++ b/arch/arm/boot/dts/armada-370.dtsi @@ -151,6 +151,25 @@ "mpp62", "mpp60", "mpp58"; marvell,function = "audio"; }; + + mdio_pins: mdio-pins { + marvell,pins = "mpp17", "mpp18"; + marvell,function = "ge"; + }; + + ge0_rgmii_pins: ge0-rgmii-pins { + marvell,pins = "mpp5", "mpp6", "mpp7", "mpp8", + "mpp9", "mpp10", "mpp11", "mpp12", + "mpp13", "mpp14", "mpp15", "mpp16"; + marvell,function = "ge0"; + }; + + ge1_rgmii_pins: ge1-rgmii-pins { + marvell,pins = "mpp19", "mpp20", "mpp21", "mpp22", + "mpp23", "mpp24", "mpp25", "mpp26", + "mpp27", "mpp28", "mpp29", "mpp30"; + marvell,function = "ge1"; + }; }; gpio0: gpio@18100 { -- cgit v0.10.2 From 7d9d5d28ddb5b93a5445b5460d5da52d5143837f Mon Sep 17 00:00:00 2001 From: Ezequiel Garcia Date: Mon, 11 Aug 2014 09:14:37 -0300 Subject: ARM: mvebu: Add proper pin muxing on Globalscale Mirabox board This commit adds the required pin muxing for the network interfaces and the MDIO interface to be properly initialized. For instance, this makes it possible for a bootloader to initialize and access the network interfaces. Signed-off-by: Ezequiel Garcia Acked-by: Andrew Lunn Link: https://lkml.kernel.org/r/1407759281-11513-3-git-send-email-ezequiel.garcia@free-electrons.com Signed-off-by: Jason Cooper diff --git a/arch/arm/boot/dts/armada-370-mirabox.dts b/arch/arm/boot/dts/armada-370-mirabox.dts index 097df7d8..2b6d24e 100644 --- a/arch/arm/boot/dts/armada-370-mirabox.dts +++ b/arch/arm/boot/dts/armada-370-mirabox.dts @@ -91,6 +91,8 @@ }; mdio { + pinctrl-0 = <&mdio_pins>; + pinctrl-names = "default"; phy0: ethernet-phy@0 { reg = <0>; }; @@ -100,11 +102,15 @@ }; }; ethernet@70000 { + pinctrl-0 = <&ge0_rgmii_pins>; + pinctrl-names = "default"; status = "okay"; phy = <&phy0>; phy-mode = "rgmii-id"; }; ethernet@74000 { + pinctrl-0 = <&ge1_rgmii_pins>; + pinctrl-names = "default"; status = "okay"; phy = <&phy1>; phy-mode = "rgmii-id"; -- cgit v0.10.2 From fea038ed55aec9a1dc59719e5e2728fe7e2148f8 Mon Sep 17 00:00:00 2001 From: Ezequiel Garcia Date: Mon, 11 Aug 2014 09:14:38 -0300 Subject: ARM: mvebu: Add proper pin muxing on the Armada 370 DB board This commit adds the required pin muxing for the network interfaces and the MDIO interface to be properly initialized. For instance, this makes it possible for a bootloader to initialize and access the network interfaces Signed-off-by: Ezequiel Garcia Acked-by: Andrew Lunn Link: https://lkml.kernel.org/r/1407759281-11513-4-git-send-email-ezequiel.garcia@free-electrons.com Signed-off-by: Jason Cooper diff --git a/arch/arm/boot/dts/armada-370-db.dts b/arch/arm/boot/dts/armada-370-db.dts index 416f4e5..a495e58 100644 --- a/arch/arm/boot/dts/armada-370-db.dts +++ b/arch/arm/boot/dts/armada-370-db.dts @@ -43,6 +43,8 @@ }; mdio { + pinctrl-0 = <&mdio_pins>; + pinctrl-names = "default"; phy0: ethernet-phy@0 { reg = <0>; }; @@ -53,11 +55,15 @@ }; ethernet@70000 { + pinctrl-0 = <&ge0_rgmii_pins>; + pinctrl-names = "default"; status = "okay"; phy = <&phy0>; phy-mode = "rgmii-id"; }; ethernet@74000 { + pinctrl-0 = <&ge1_rgmii_pins>; + pinctrl-names = "default"; status = "okay"; phy = <&phy1>; phy-mode = "rgmii-id"; -- cgit v0.10.2 From 8c640da6ac8b9a15429473114e0b8b248cf67080 Mon Sep 17 00:00:00 2001 From: Ezequiel Garcia Date: Mon, 11 Aug 2014 09:14:39 -0300 Subject: ARM: mvebu: Add proper pin muxing on Netgear ReadyNAS 102 This commit adds the required pin muxing for the network interfaces and the MDIO interface to be properly initialized. For instance, this makes it possible for a bootloader to initialize and access the network interfaces Signed-off-by: Ezequiel Garcia Acked-by: Andrew Lunn Link: https://lkml.kernel.org/r/1407759281-11513-5-git-send-email-ezequiel.garcia@free-electrons.com Signed-off-by: Jason Cooper diff --git a/arch/arm/boot/dts/armada-370-netgear-rn102.dts b/arch/arm/boot/dts/armada-370-netgear-rn102.dts index d6d572e..03f917e 100644 --- a/arch/arm/boot/dts/armada-370-netgear-rn102.dts +++ b/arch/arm/boot/dts/armada-370-netgear-rn102.dts @@ -101,12 +101,16 @@ }; mdio { + pinctrl-0 = <&mdio_pins>; + pinctrl-names = "default"; phy0: ethernet-phy@0 { /* Marvell 88E1318 */ reg = <0>; }; }; ethernet@74000 { + pinctrl-0 = <&ge1_rgmii_pins>; + pinctrl-names = "default"; status = "okay"; phy = <&phy0>; phy-mode = "rgmii-id"; -- cgit v0.10.2 From a1451ab2f024be656fc1b5e560e5854b9d7e70fe Mon Sep 17 00:00:00 2001 From: Ezequiel Garcia Date: Mon, 11 Aug 2014 09:14:40 -0300 Subject: ARM: mvebu: Add proper pin muxing on Netgear ReadyNAS 104 This commit adds the required pin muxing for the network interfaces and the MDIO interface to be properly initialized. For instance, this makes it possible for a bootloader to initialize and access the network interfaces Signed-off-by: Ezequiel Garcia Acked-by: Andrew Lunn Link: https://lkml.kernel.org/r/1407759281-11513-6-git-send-email-ezequiel.garcia@free-electrons.com Signed-off-by: Jason Cooper diff --git a/arch/arm/boot/dts/armada-370-netgear-rn104.dts b/arch/arm/boot/dts/armada-370-netgear-rn104.dts index c5fe8b5..f56bb1b 100644 --- a/arch/arm/boot/dts/armada-370-netgear-rn104.dts +++ b/arch/arm/boot/dts/armada-370-netgear-rn104.dts @@ -86,6 +86,8 @@ }; mdio { + pinctrl-0 = <&mdio_pins>; + pinctrl-names = "default"; phy0: ethernet-phy@0 { /* Marvell 88E1318 */ reg = <0>; }; @@ -96,12 +98,16 @@ }; ethernet@70000 { + pinctrl-0 = <&ge0_rgmii_pins>; + pinctrl-names = "default"; status = "okay"; phy = <&phy0>; phy-mode = "rgmii-id"; }; ethernet@74000 { + pinctrl-0 = <&ge1_rgmii_pins>; + pinctrl-names = "default"; status = "okay"; phy = <&phy1>; phy-mode = "rgmii-id"; -- cgit v0.10.2 From 9dfb5c417c3210fe84a74b4cd30549e06962bd06 Mon Sep 17 00:00:00 2001 From: Ezequiel Garcia Date: Mon, 11 Aug 2014 09:14:41 -0300 Subject: ARM: mvebu: Add proper pin muxing on Armada 370 RD board This commit adds the required pin muxing for the network interfaces and the MDIO interface to be properly initialized. For instance, this makes it possible for a bootloader to initialize and access the network interfaces Only the second network interface is pin muxed. The first network interface is connected to the PHY using SGMII, which uses a dedicated SerDes lane. Signed-off-by: Ezequiel Garcia Acked-by: Andrew Lunn Link: https://lkml.kernel.org/r/1407759281-11513-7-git-send-email-ezequiel.garcia@free-electrons.com Signed-off-by: Jason Cooper diff --git a/arch/arm/boot/dts/armada-370-rd.dts b/arch/arm/boot/dts/armada-370-rd.dts index 4169f40..ca13d9c 100644 --- a/arch/arm/boot/dts/armada-370-rd.dts +++ b/arch/arm/boot/dts/armada-370-rd.dts @@ -59,6 +59,8 @@ }; mdio { + pinctrl-0 = <&mdio_pins>; + pinctrl-names = "default"; phy0: ethernet-phy@0 { reg = <0>; }; @@ -74,6 +76,8 @@ phy-mode = "sgmii"; }; ethernet@74000 { + pinctrl-0 = <&ge1_rgmii_pins>; + pinctrl-names = "default"; status = "okay"; phy = <&phy1>; phy-mode = "rgmii-id"; -- cgit v0.10.2 From eea6653aae7bc85e38104f9c3a22471cba04da68 Mon Sep 17 00:00:00 2001 From: Daniel Drake Date: Mon, 18 Aug 2014 11:39:50 -0500 Subject: ARM: dts: Enable PMIC interrupts for exynos4412-odroid-common The ODROID kernel shows that the PMIC interrupt line is hooked up to pin GPX3-2. This is needed for the max77686-irq driver to create the PMIC IRQ domain, which is needed by max77686-rtc. Signed-off-by: Daniel Drake Reviewed-by: Tomasz Figa Tested-by: Tomeu Vizoso Signed-off-by: Kukjin Kim diff --git a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi index 6d6d23c..cb6f55f 100644 --- a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi +++ b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi @@ -148,6 +148,10 @@ max77686: pmic@09 { compatible = "maxim,max77686"; + interrupt-parent = <&gpx3>; + interrupts = <2 0>; + pinctrl-names = "default"; + pinctrl-0 = <&max77686_irq>; reg = <0x09>; #clock-cells = <1>; @@ -368,4 +372,11 @@ samsung,pins = "gpx1-3"; samsung,pin-pud = <0>; }; + + max77686_irq: max77686-irq { + samsung,pins = "gpx3-2"; + samsung,pin-function = <0>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; }; -- cgit v0.10.2 From cc3fe7abda0abb9936598a90feaa2e323d62200d Mon Sep 17 00:00:00 2001 From: Daniel Drake Date: Mon, 18 Aug 2014 11:39:53 -0500 Subject: ARM: dts: ODROID i2c improvements for exynos4412-odroid-common Increase max i2c bus frequency beyond the default for faster data transfers. According to the manual, these faster speeds are only available when the board is wired up the right way. In this case, the vendor kernel has run at this speed for a long time. sda-delay is needed for talking to RTC on PMIC, otherwise the i2c controller never sees an ACK. Strangely the other PMIC i2c slave (the main one) works fine even without this delay. I Chose value 100 to match the vendor kernel. Signed-off-by: Daniel Drake Reviewed-by: Tomasz Figa Tested-by: Tomeu Vizoso Signed-off-by: Kukjin Kim diff --git a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi index cb6f55f..adadaf9 100644 --- a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi +++ b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi @@ -134,6 +134,8 @@ i2c@13860000 { pinctrl-0 = <&i2c0_bus>; pinctrl-names = "default"; + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <400000>; status = "okay"; usb3503: usb3503@08 { -- cgit v0.10.2 From 0a97ea3b62fabc1c0eaca49bc584376b5cf0961b Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Tue, 19 Aug 2014 00:51:50 +0800 Subject: ARM: dts: sun8i: Add i2c controller nodes Add nodes for the 3 i2c controllers found on A23 SoCs to the sun8i DTSI. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard diff --git a/arch/arm/boot/dts/sun8i-a23.dtsi b/arch/arm/boot/dts/sun8i-a23.dtsi index 9386d1f..2ec86d36 100644 --- a/arch/arm/boot/dts/sun8i-a23.dtsi +++ b/arch/arm/boot/dts/sun8i-a23.dtsi @@ -387,6 +387,39 @@ status = "disabled"; }; + i2c0: i2c@01c2ac00 { + compatible = "allwinner,sun6i-a31-i2c"; + reg = <0x01c2ac00 0x400>; + interrupts = <0 6 4>; + clocks = <&apb2_gates 0>; + resets = <&apb2_rst 0>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c1: i2c@01c2b000 { + compatible = "allwinner,sun6i-a31-i2c"; + reg = <0x01c2b000 0x400>; + interrupts = <0 7 4>; + clocks = <&apb2_gates 1>; + resets = <&apb2_rst 1>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c2: i2c@01c2b400 { + compatible = "allwinner,sun6i-a31-i2c"; + reg = <0x01c2b400 0x400>; + interrupts = <0 8 4>; + clocks = <&apb2_gates 2>; + resets = <&apb2_rst 2>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + gic: interrupt-controller@01c81000 { compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; reg = <0x01c81000 0x1000>, -- cgit v0.10.2 From dc66085b7a03c1c73774254ff7ac59159810b628 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Tue, 19 Aug 2014 00:51:51 +0800 Subject: ARM: dts: sun8i: Enable i2c controllers on ippo-q8h-v5 i2c0 is connected to the gsl1680 capacitive touch panel controller. i2c1 is connected to an mma7660 3-axis accelerometer. i2c2 is connected to the front and back gc0309 camera sensors. The camera sensors require additional regulators be enabled before they are available. All these peripherals are not supported by the kernel yet. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard diff --git a/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts b/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts index ef1e4f3..e9b8cca 100644 --- a/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts +++ b/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts @@ -43,6 +43,25 @@ }; }; + i2c0: i2c@01c2ac00 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "okay"; + }; + + i2c1: i2c@01c2b000 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins_a>; + status = "okay"; + }; + + i2c2: i2c@01c2b400 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins_a>; + /* pull-ups and devices require PMIC regulator */ + status = "failed"; + }; + r_uart: serial@01f02800 { pinctrl-names = "default"; pinctrl-0 = <&r_uart_pins_a>; -- cgit v0.10.2 From 447a0470a7b9745fc91a75182f37f7710fa91290 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Tue, 19 Aug 2014 01:45:45 +0800 Subject: ARM: dt: sunxi: Remove i2c controller clock-frequency that matches default The clock-frequency values of the i2c controller nodes match the defaults of the driver. Remove the properties to use the defaults, and be consistent with sun8i. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi index 14cf436..380f914 100644 --- a/arch/arm/boot/dts/sun4i-a10.dtsi +++ b/arch/arm/boot/dts/sun4i-a10.dtsi @@ -765,7 +765,6 @@ reg = <0x01c2ac00 0x400>; interrupts = <7>; clocks = <&apb1_gates 0>; - clock-frequency = <100000>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; @@ -776,7 +775,6 @@ reg = <0x01c2b000 0x400>; interrupts = <8>; clocks = <&apb1_gates 1>; - clock-frequency = <100000>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; @@ -787,7 +785,6 @@ reg = <0x01c2b400 0x400>; interrupts = <9>; clocks = <&apb1_gates 2>; - clock-frequency = <100000>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi index 02aa41f..d73a228 100644 --- a/arch/arm/boot/dts/sun5i-a10s.dtsi +++ b/arch/arm/boot/dts/sun5i-a10s.dtsi @@ -578,7 +578,6 @@ reg = <0x01c2ac00 0x400>; interrupts = <7>; clocks = <&apb1_gates 0>; - clock-frequency = <100000>; status = "disabled"; }; @@ -589,7 +588,6 @@ reg = <0x01c2b000 0x400>; interrupts = <8>; clocks = <&apb1_gates 1>; - clock-frequency = <100000>; status = "disabled"; }; @@ -600,7 +598,6 @@ reg = <0x01c2b400 0x400>; interrupts = <9>; clocks = <&apb1_gates 2>; - clock-frequency = <100000>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi index d8f02ee..c4b5d78 100644 --- a/arch/arm/boot/dts/sun5i-a13.dtsi +++ b/arch/arm/boot/dts/sun5i-a13.dtsi @@ -504,7 +504,6 @@ reg = <0x01c2ac00 0x400>; interrupts = <7>; clocks = <&apb1_gates 0>; - clock-frequency = <100000>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; @@ -515,7 +514,6 @@ reg = <0x01c2b000 0x400>; interrupts = <8>; clocks = <&apb1_gates 1>; - clock-frequency = <100000>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; @@ -526,7 +524,6 @@ reg = <0x01c2b400 0x400>; interrupts = <9>; clocks = <&apb1_gates 2>; - clock-frequency = <100000>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi index 8fdf90d..1c2ec91 100644 --- a/arch/arm/boot/dts/sun6i-a31.dtsi +++ b/arch/arm/boot/dts/sun6i-a31.dtsi @@ -657,7 +657,6 @@ reg = <0x01c2ac00 0x400>; interrupts = <0 6 4>; clocks = <&apb2_gates 0>; - clock-frequency = <100000>; resets = <&apb2_rst 0>; status = "disabled"; }; @@ -667,7 +666,6 @@ reg = <0x01c2b000 0x400>; interrupts = <0 7 4>; clocks = <&apb2_gates 1>; - clock-frequency = <100000>; resets = <&apb2_rst 1>; status = "disabled"; }; @@ -677,7 +675,6 @@ reg = <0x01c2b400 0x400>; interrupts = <0 8 4>; clocks = <&apb2_gates 2>; - clock-frequency = <100000>; resets = <&apb2_rst 2>; status = "disabled"; }; @@ -687,7 +684,6 @@ reg = <0x01c2b800 0x400>; interrupts = <0 9 4>; clocks = <&apb2_gates 3>; - clock-frequency = <100000>; resets = <&apb2_rst 3>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index db22ef9..c658e34 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -915,7 +915,6 @@ reg = <0x01c2ac00 0x400>; interrupts = <0 7 4>; clocks = <&apb1_gates 0>; - clock-frequency = <100000>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; @@ -926,7 +925,6 @@ reg = <0x01c2b000 0x400>; interrupts = <0 8 4>; clocks = <&apb1_gates 1>; - clock-frequency = <100000>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; @@ -937,7 +935,6 @@ reg = <0x01c2b400 0x400>; interrupts = <0 9 4>; clocks = <&apb1_gates 2>; - clock-frequency = <100000>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; @@ -948,7 +945,6 @@ reg = <0x01c2b800 0x400>; interrupts = <0 88 4>; clocks = <&apb1_gates 3>; - clock-frequency = <100000>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; @@ -959,7 +955,6 @@ reg = <0x01c2c000 0x400>; interrupts = <0 89 4>; clocks = <&apb1_gates 15>; - clock-frequency = <100000>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; -- cgit v0.10.2 From df08d2eb66d9805118d9a94c1df0129b193c9a4f Mon Sep 17 00:00:00 2001 From: Andreas Faerber Date: Mon, 18 Aug 2014 13:33:30 -0500 Subject: ARM: dts: Fix MMC pinctrl for exynos5250-snow The pinctrl properties should be on the device directly and not on the slot sub-node. Reported-by: Doug Anderson Cc: Jaehoon Chung Reviewed-by: Tomasz Figa Signed-off-by: Andreas Faerber Reviewed-by: Doug Anderson Signed-off-by: Kukjin Kim diff --git a/arch/arm/boot/dts/exynos5250-snow.dts b/arch/arm/boot/dts/exynos5250-snow.dts index f2b8c41..eb437f6 100644 --- a/arch/arm/boot/dts/exynos5250-snow.dts +++ b/arch/arm/boot/dts/exynos5250-snow.dts @@ -240,10 +240,8 @@ */ mmc@12230000 { status = "okay"; - slot@0 { - pinctrl-names = "default"; - pinctrl-0 = <&sd3_clk &sd3_cmd &sd3_bus4>; - }; + pinctrl-names = "default"; + pinctrl-0 = <&sd3_clk &sd3_cmd &sd3_bus4>; }; i2c@12CD0000 { -- cgit v0.10.2 From 5fbc3f20d0bbf72423152f145e30a1d9e01ceadb Mon Sep 17 00:00:00 2001 From: Andreas Faerber Date: Mon, 18 Aug 2014 14:00:35 -0500 Subject: ARM: dts: Fold exynos5250-cros-common into exynos5250-snow exynos5250-cros-common.dtsi was meant for sharing common pieces across ChromeOS devices. This turned out premature, as several devices ended up in the common file that are not common after all. Since the remaining common ChromeOS pieces are fairly minor, exynos5250-cros-common.dtsi was requested to be merged into the Snow device tree, sharing only the keyboard controller for now. This may be re-evaluated as both mature. Suggested-by: Doug Anderson Reviewed-by: Tomasz Figa Signed-off-by: Andreas Faerber Reviewed-by: Doug Anderson Signed-off-by: Kukjin Kim diff --git a/arch/arm/boot/dts/exynos5250-cros-common.dtsi b/arch/arm/boot/dts/exynos5250-cros-common.dtsi deleted file mode 100644 index e603e9c..0000000 --- a/arch/arm/boot/dts/exynos5250-cros-common.dtsi +++ /dev/null @@ -1,164 +0,0 @@ -/* - * Common device tree include for all Exynos 5250 boards based off of Daisy. - * - * Copyright (c) 2012 Google, Inc - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -/ { - aliases { - }; - - memory { - reg = <0x40000000 0x80000000>; - }; - - chosen { - }; - - pinctrl@11400000 { - /* - * Disabled pullups since external part has its own pullups and - * double-pulling gets us out of spec in some cases. - */ - i2c2_bus: i2c2-bus { - samsung,pin-pud = <0>; - }; - }; - - i2c@12C60000 { - status = "okay"; - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <378000>; - }; - - i2c@12C70000 { - status = "okay"; - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <378000>; - }; - - i2c@12C80000 { - status = "okay"; - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <66000>; - - hdmiddc@50 { - compatible = "samsung,exynos4210-hdmiddc"; - reg = <0x50>; - }; - }; - - i2c@12C90000 { - status = "okay"; - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <66000>; - }; - - i2c@12CA0000 { - status = "okay"; - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <66000>; - }; - - i2c@12CB0000 { - status = "okay"; - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <66000>; - }; - - i2c@12CD0000 { - status = "okay"; - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <66000>; - }; - - i2c@12CE0000 { - status = "okay"; - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <378000>; - - hdmiphy: hdmiphy@38 { - compatible = "samsung,exynos4212-hdmiphy"; - reg = <0x38>; - }; - }; - - mmc@12200000 { - num-slots = <1>; - supports-highspeed; - broken-cd; - card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; - pinctrl-names = "default"; - pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4 &sd0_bus8>; - - slot@0 { - reg = <0>; - bus-width = <8>; - }; - }; - - mmc@12220000 { - num-slots = <1>; - supports-highspeed; - card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; - pinctrl-names = "default"; - pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; - - slot@0 { - reg = <0>; - bus-width = <4>; - wp-gpios = <&gpc2 1 0>; - }; - }; - - mmc@12230000 { - num-slots = <1>; - supports-highspeed; - broken-cd; - card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; - /* See board-specific dts files for pin setup */ - - slot@0 { - reg = <0>; - bus-width = <4>; - }; - }; - - spi_1: spi@12d30000 { - status = "okay"; - samsung,spi-src-clk = <0>; - num-cs = <1>; - }; - - hdmi { - hpd-gpio = <&gpx3 7 0>; - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_hpd_irq>; - phy = <&hdmiphy>; - ddc = <&i2c_2>; - }; - - gpio-keys { - compatible = "gpio-keys"; - - power { - label = "Power"; - gpios = <&gpx1 3 1>; - linux,code = <116>; /* KEY_POWER */ - gpio-key,wakeup; - }; - }; -}; diff --git a/arch/arm/boot/dts/exynos5250-snow.dts b/arch/arm/boot/dts/exynos5250-snow.dts index eb437f6..1c36cd7 100644 --- a/arch/arm/boot/dts/exynos5250-snow.dts +++ b/arch/arm/boot/dts/exynos5250-snow.dts @@ -10,7 +10,6 @@ /dts-v1/; #include "exynos5250.dtsi" -#include "exynos5250-cros-common.dtsi" / { model = "Google Snow"; @@ -20,6 +19,13 @@ i2c104 = &i2c_104; }; + memory { + reg = <0x40000000 0x80000000>; + }; + + chosen { + }; + rtc@101E0000 { status = "okay"; }; @@ -93,6 +99,13 @@ gpio-keys { compatible = "gpio-keys"; + power { + label = "Power"; + gpios = <&gpx1 3 1>; + linux,code = <116>; /* KEY_POWER */ + gpio-key,wakeup; + }; + lid-switch { label = "Lid"; gpios = <&gpx3 5 1>; @@ -226,24 +239,6 @@ }; }; - mmc@12200000 { - status = "okay"; - }; - - mmc@12220000 { - status = "okay"; - }; - - /* - * On Snow we've got SIP WiFi and so can keep drive strengths low to - * reduce EMI. - */ - mmc@12230000 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&sd3_clk &sd3_cmd &sd3_bus4>; - }; - i2c@12CD0000 { max98095: codec@11 { compatible = "maxim,max98095"; @@ -292,6 +287,11 @@ }; hdmi { + hpd-gpio = <&gpx3 7 0>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_hpd_irq>; + phy = <&hdmiphy>; + ddc = <&i2c_2>; hdmi-en-supply = <&tps65090_fet7>; vdd-supply = <&ldo8_reg>; vdd_osc-supply = <&ldo10_reg>; @@ -343,6 +343,10 @@ }; &i2c_0 { + status = "okay"; + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <378000>; + max77686@09 { compatible = "maxim,max77686"; interrupt-parent = <&gpx3>; @@ -489,6 +493,10 @@ }; &i2c_1 { + status = "okay"; + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <378000>; + trackpad { reg = <0x67>; compatible = "cypress,cyapa"; @@ -498,6 +506,118 @@ }; }; +/* + * Disabled pullups since external part has its own pullups and + * double-pulling gets us out of spec in some cases. + */ +&i2c2_bus { + samsung,pin-pud = <0>; +}; + +&i2c_2 { + status = "okay"; + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <66000>; + + hdmiddc@50 { + compatible = "samsung,exynos4210-hdmiddc"; + reg = <0x50>; + }; +}; + +&i2c_3 { + status = "okay"; + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <66000>; +}; + +&i2c_4 { + status = "okay"; + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <66000>; +}; + +&i2c_5 { + status = "okay"; + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <66000>; +}; + +&i2c_7 { + status = "okay"; + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <66000>; +}; + +&i2c_8 { + status = "okay"; + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <378000>; + + hdmiphy: hdmiphy@38 { + compatible = "samsung,exynos4212-hdmiphy"; + reg = <0x38>; + }; +}; + +&mmc_0 { + status = "okay"; + num-slots = <1>; + supports-highspeed; + broken-cd; + card-detect-delay = <200>; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <2 3>; + samsung,dw-mshc-ddr-timing = <1 2>; + pinctrl-names = "default"; + pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4 &sd0_bus8>; + + slot@0 { + reg = <0>; + bus-width = <8>; + }; +}; + +&mmc_2 { + status = "okay"; + num-slots = <1>; + supports-highspeed; + card-detect-delay = <200>; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <2 3>; + samsung,dw-mshc-ddr-timing = <1 2>; + pinctrl-names = "default"; + pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; + + slot@0 { + reg = <0>; + bus-width = <4>; + wp-gpios = <&gpc2 1 0>; + }; +}; + +/* + * On Snow we've got SIP WiFi and so can keep drive strengths low to + * reduce EMI. + */ +&mmc_3 { + status = "okay"; + num-slots = <1>; + supports-highspeed; + broken-cd; + card-detect-delay = <200>; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <2 3>; + samsung,dw-mshc-ddr-timing = <1 2>; + pinctrl-names = "default"; + pinctrl-0 = <&sd3_clk &sd3_cmd &sd3_bus4>; + + slot@0 { + reg = <0>; + bus-width = <4>; + }; +}; + &pinctrl_0 { max77686_irq: max77686-irq { samsung,pins = "gpx3-2"; @@ -507,4 +627,10 @@ }; }; +&spi_1 { + status = "okay"; + samsung,spi-src-clk = <0>; + num-cs = <1>; +}; + #include "cros-ec-keyboard.dtsi" -- cgit v0.10.2 From aaa25a5a33cb2f406e59ff06a86b7f91026c2fa2 Mon Sep 17 00:00:00 2001 From: Jaehoon Chung Date: Mon, 18 Aug 2014 11:55:32 -0500 Subject: ARM: dts: unuse the slot-node and deprecate the supports-highspeed for dw-mmc in exynos dw-mmc controller can support multiple slots. But, there are no use-cases anywhere. So we don't need to support the slot-node for dw-mmc controller. And "supports-highspeed" property in dw-mmc is deprecated. "supports-highspeed" property can be replaced with "cap-sd/mmc-highspeed". Signed-off-by: Jaehoon Chung Reviewed-by: Tushar Behera Reviewed-by: Ulf Hansson Tested-by: Sachin Kamat [kgene.kim@samsung.com: rebased exynos5250-snow changes] Signed-off-by: Kukjin Kim diff --git a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi index adadaf9..c697ff0 100644 --- a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi +++ b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi @@ -54,17 +54,13 @@ status = "okay"; num-slots = <1>; - supports-highspeed; broken-cd; card-detect-delay = <200>; samsung,dw-mshc-ciu-div = <3>; samsung,dw-mshc-sdr-timing = <2 3>; samsung,dw-mshc-ddr-timing = <1 2>; - - slot@0 { - reg = <0>; - bus-width = <8>; - }; + bus-width = <8>; + cap-mmc-highspeed; }; watchdog@10060000 { diff --git a/arch/arm/boot/dts/exynos4412-origen.dts b/arch/arm/boot/dts/exynos4412-origen.dts index e925c9f..de15114 100644 --- a/arch/arm/boot/dts/exynos4412-origen.dts +++ b/arch/arm/boot/dts/exynos4412-origen.dts @@ -137,17 +137,13 @@ status = "okay"; num-slots = <1>; - supports-highspeed; broken-cd; card-detect-delay = <200>; samsung,dw-mshc-ciu-div = <3>; samsung,dw-mshc-sdr-timing = <2 3>; samsung,dw-mshc-ddr-timing = <1 2>; - - slot@0 { - reg = <0>; - bus-width = <8>; - }; + bus-width = <8>; + cap-mmc-highspeed; }; codec@13400000 { diff --git a/arch/arm/boot/dts/exynos4412-trats2.dts b/arch/arm/boot/dts/exynos4412-trats2.dts index 11967f4..5e066cd 100644 --- a/arch/arm/boot/dts/exynos4412-trats2.dts +++ b/arch/arm/boot/dts/exynos4412-trats2.dts @@ -520,7 +520,6 @@ mmc@12550000 { num-slots = <1>; - supports-highspeed; broken-cd; non-removable; card-detect-delay = <200>; @@ -532,11 +531,8 @@ pinctrl-0 = <&sd4_clk &sd4_cmd &sd4_bus4 &sd4_bus8>; pinctrl-names = "default"; status = "okay"; - - slot@0 { - reg = <0>; - bus-width = <8>; - }; + bus-width = <8>; + cap-mmc-highspeed; }; serial@13800000 { diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts index d0de1f5..42a3590 100644 --- a/arch/arm/boot/dts/exynos5250-arndale.dts +++ b/arch/arm/boot/dts/exynos5250-arndale.dts @@ -401,7 +401,6 @@ mmc_0: mmc@12200000 { status = "okay"; num-slots = <1>; - supports-highspeed; broken-cd; card-detect-delay = <200>; samsung,dw-mshc-ciu-div = <3>; @@ -410,17 +409,13 @@ vmmc-supply = <&mmc_reg>; pinctrl-names = "default"; pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>; - - slot@0 { - reg = <0>; - bus-width = <8>; - }; + bus-width = <8>; + cap-mmc-highspeed; }; mmc_2: mmc@12220000 { status = "okay"; num-slots = <1>; - supports-highspeed; card-detect-delay = <200>; samsung,dw-mshc-ciu-div = <3>; samsung,dw-mshc-sdr-timing = <2 3>; @@ -428,12 +423,9 @@ vmmc-supply = <&mmc_reg>; pinctrl-names = "default"; pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; - - slot@0 { - reg = <0>; - bus-width = <4>; - disable-wp; - }; + bus-width = <4>; + disable-wp; + cap-sd-highspeed; }; i2s0: i2s@03830000 { diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts index b4b35ad..6a0f4c0 100644 --- a/arch/arm/boot/dts/exynos5250-smdk5250.dts +++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts @@ -284,7 +284,6 @@ mmc@12200000 { status = "okay"; num-slots = <1>; - supports-highspeed; broken-cd; card-detect-delay = <200>; samsung,dw-mshc-ciu-div = <3>; @@ -292,29 +291,22 @@ samsung,dw-mshc-ddr-timing = <1 2>; pinctrl-names = "default"; pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>; - - slot@0 { - reg = <0>; - bus-width = <8>; - }; + bus-width = <8>; + cap-mmc-highspeed; }; mmc@12220000 { status = "okay"; num-slots = <1>; - supports-highspeed; card-detect-delay = <200>; samsung,dw-mshc-ciu-div = <3>; samsung,dw-mshc-sdr-timing = <2 3>; samsung,dw-mshc-ddr-timing = <1 2>; pinctrl-names = "default"; pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; - - slot@0 { - reg = <0>; - bus-width = <4>; - disable-wp; - }; + bus-width = <4>; + disable-wp; + cap-sd-highspeed; }; spi_1: spi@12d30000 { diff --git a/arch/arm/boot/dts/exynos5250-snow.dts b/arch/arm/boot/dts/exynos5250-snow.dts index 1c36cd7..2a62459 100644 --- a/arch/arm/boot/dts/exynos5250-snow.dts +++ b/arch/arm/boot/dts/exynos5250-snow.dts @@ -563,7 +563,6 @@ &mmc_0 { status = "okay"; num-slots = <1>; - supports-highspeed; broken-cd; card-detect-delay = <200>; samsung,dw-mshc-ciu-div = <3>; @@ -571,29 +570,22 @@ samsung,dw-mshc-ddr-timing = <1 2>; pinctrl-names = "default"; pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4 &sd0_bus8>; - - slot@0 { - reg = <0>; - bus-width = <8>; - }; + bus-width = <8>; + cap-mmc-highspeed; }; &mmc_2 { status = "okay"; num-slots = <1>; - supports-highspeed; card-detect-delay = <200>; samsung,dw-mshc-ciu-div = <3>; samsung,dw-mshc-sdr-timing = <2 3>; samsung,dw-mshc-ddr-timing = <1 2>; pinctrl-names = "default"; pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; - - slot@0 { - reg = <0>; - bus-width = <4>; - wp-gpios = <&gpc2 1 0>; - }; + bus-width = <4>; + wp-gpios = <&gpc2 1 0>; + cap-sd-highspeed; }; /* @@ -603,7 +595,6 @@ &mmc_3 { status = "okay"; num-slots = <1>; - supports-highspeed; broken-cd; card-detect-delay = <200>; samsung,dw-mshc-ciu-div = <3>; @@ -611,11 +602,8 @@ samsung,dw-mshc-ddr-timing = <1 2>; pinctrl-names = "default"; pinctrl-0 = <&sd3_clk &sd3_cmd &sd3_bus4>; - - slot@0 { - reg = <0>; - bus-width = <4>; - }; + bus-width = <4>; + cap-sd-highspeed; }; &pinctrl_0 { diff --git a/arch/arm/boot/dts/exynos5260-xyref5260.dts b/arch/arm/boot/dts/exynos5260-xyref5260.dts index 8c84ab2..a803b60 100644 --- a/arch/arm/boot/dts/exynos5260-xyref5260.dts +++ b/arch/arm/boot/dts/exynos5260-xyref5260.dts @@ -69,7 +69,7 @@ num-slots = <1>; broken-cd; bypass-smu; - supports-highspeed; + cap-mmc-highspeed; supports-hs200-mode; /* 200 Mhz */ card-detect-delay = <200>; samsung,dw-mshc-ciu-div = <3>; @@ -77,27 +77,19 @@ samsung,dw-mshc-ddr-timing = <0 2>; pinctrl-names = "default"; pinctrl-0 = <&sd0_rdqs &sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8>; - - slot@0 { - reg = <0>; - bus-width = <8>; - }; + bus-width = <8>; }; &mmc_2 { status = "okay"; num-slots = <1>; - supports-highspeed; + cap-sd-highspeed; card-detect-delay = <200>; samsung,dw-mshc-ciu-div = <3>; samsung,dw-mshc-sdr-timing = <2 3>; samsung,dw-mshc-ddr-timing = <1 2>; pinctrl-names = "default"; pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>; - - slot@0 { - reg = <0>; - bus-width = <4>; - disable-wp; - }; + bus-width = <4>; + disable-wp; }; diff --git a/arch/arm/boot/dts/exynos5410-smdk5410.dts b/arch/arm/boot/dts/exynos5410-smdk5410.dts index 7275bbd..be3e025 100644 --- a/arch/arm/boot/dts/exynos5410-smdk5410.dts +++ b/arch/arm/boot/dts/exynos5410-smdk5410.dts @@ -40,33 +40,25 @@ &mmc_0 { status = "okay"; num-slots = <1>; - supports-highspeed; + cap-mmc-highspeed; broken-cd; card-detect-delay = <200>; samsung,dw-mshc-ciu-div = <3>; samsung,dw-mshc-sdr-timing = <2 3>; samsung,dw-mshc-ddr-timing = <1 2>; - - slot@0 { - reg = <0>; - bus-width = <8>; - }; + bus-width = <8>; }; &mmc_2 { status = "okay"; num-slots = <1>; - supports-highspeed; + cap-sd-highspeed; card-detect-delay = <200>; samsung,dw-mshc-ciu-div = <3>; samsung,dw-mshc-sdr-timing = <2 3>; samsung,dw-mshc-ddr-timing = <1 2>; - - slot@0 { - reg = <0>; - bus-width = <4>; - disable-wp; - }; + bus-width = <4>; + disable-wp; }; &uart0 { diff --git a/arch/arm/boot/dts/exynos5420-arndale-octa.dts b/arch/arm/boot/dts/exynos5420-arndale-octa.dts index 434fd9d..70a559c 100644 --- a/arch/arm/boot/dts/exynos5420-arndale-octa.dts +++ b/arch/arm/boot/dts/exynos5420-arndale-octa.dts @@ -50,7 +50,6 @@ mmc@12200000 { status = "okay"; broken-cd; - supports-highspeed; card-detect-delay = <200>; samsung,dw-mshc-ciu-div = <3>; samsung,dw-mshc-sdr-timing = <0 4>; @@ -58,16 +57,12 @@ pinctrl-names = "default"; pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>; vmmc-supply = <&ldo10_reg>; - - slot@0 { - reg = <0>; - bus-width = <8>; - }; + bus-width = <8>; + cap-mmc-highspeed; }; mmc@12220000 { status = "okay"; - supports-highspeed; card-detect-delay = <200>; samsung,dw-mshc-ciu-div = <3>; samsung,dw-mshc-sdr-timing = <2 3>; @@ -75,11 +70,8 @@ pinctrl-names = "default"; pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; vmmc-supply = <&ldo10_reg>; - - slot@0 { - reg = <0>; - bus-width = <4>; - }; + bus-width = <4>; + cap-sd-highspeed; }; hsi2c_4: i2c@12CA0000 { diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts b/arch/arm/boot/dts/exynos5420-peach-pit.dts index 228a6b1..7b1ed2c 100644 --- a/arch/arm/boot/dts/exynos5420-peach-pit.dts +++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts @@ -187,7 +187,7 @@ num-slots = <1>; broken-cd; caps2-mmc-hs200-1_8v; - supports-highspeed; + cap-mmc-highspeed; non-removable; card-detect-delay = <200>; clock-frequency = <400000000>; @@ -196,17 +196,13 @@ samsung,dw-mshc-ddr-timing = <0 2>; pinctrl-names = "default"; pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>; - - slot@0 { - reg = <0>; - bus-width = <8>; - }; + bus-width = <8>; }; &mmc_2 { status = "okay"; num-slots = <1>; - supports-highspeed; + cap-sd-highspeed; card-detect-delay = <200>; clock-frequency = <400000000>; samsung,dw-mshc-ciu-div = <3>; @@ -214,11 +210,7 @@ samsung,dw-mshc-ddr-timing = <1 2>; pinctrl-names = "default"; pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; - - slot@0 { - reg = <0>; - bus-width = <4>; - }; + bus-width = <4>; }; diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts b/arch/arm/boot/dts/exynos5420-smdk5420.dts index 6052aa9..8be3d7b 100644 --- a/arch/arm/boot/dts/exynos5420-smdk5420.dts +++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts @@ -76,34 +76,26 @@ mmc@12200000 { status = "okay"; broken-cd; - supports-highspeed; card-detect-delay = <200>; samsung,dw-mshc-ciu-div = <3>; samsung,dw-mshc-sdr-timing = <0 4>; samsung,dw-mshc-ddr-timing = <0 2>; pinctrl-names = "default"; pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>; - - slot@0 { - reg = <0>; - bus-width = <8>; - }; + bus-width = <8>; + cap-mmc-highspeed; }; mmc@12220000 { status = "okay"; - supports-highspeed; card-detect-delay = <200>; samsung,dw-mshc-ciu-div = <3>; samsung,dw-mshc-sdr-timing = <2 3>; samsung,dw-mshc-ddr-timing = <1 2>; pinctrl-names = "default"; pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; - - slot@0 { - reg = <0>; - bus-width = <4>; - }; + bus-width = <4>; + cap-sd-highspeed; }; dp-controller@145B0000 { diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts b/arch/arm/boot/dts/exynos5800-peach-pi.dts index f3ee48b..a587dd6 100644 --- a/arch/arm/boot/dts/exynos5800-peach-pi.dts +++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts @@ -185,7 +185,7 @@ num-slots = <1>; broken-cd; caps2-mmc-hs200-1_8v; - supports-highspeed; + cap-mmc-highspeed; non-removable; card-detect-delay = <200>; clock-frequency = <400000000>; @@ -194,17 +194,13 @@ samsung,dw-mshc-ddr-timing = <0 2>; pinctrl-names = "default"; pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>; - - slot@0 { - reg = <0>; - bus-width = <8>; - }; + bus-width = <8>; }; &mmc_2 { status = "okay"; num-slots = <1>; - supports-highspeed; + cap-sd-highspeed; card-detect-delay = <200>; clock-frequency = <400000000>; samsung,dw-mshc-ciu-div = <3>; @@ -212,11 +208,7 @@ samsung,dw-mshc-ddr-timing = <1 2>; pinctrl-names = "default"; pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; - - slot@0 { - reg = <0>; - bus-width = <4>; - }; + bus-width = <4>; }; -- cgit v0.10.2 From a130548d8c06d4fda098f25a6b3dec62beec27cc Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Mon, 18 Aug 2014 13:26:51 -0500 Subject: ARM: dts: Improve Peach Pit and Pi power scheme The DeviceTree files for the Peach Pit and Pi machines have a simplistic model of the connections between the different regulators since not all the tps65090 regulators get their input supply voltage from the VDC. DCDC1-3, LD0-1 and fet7 parent supply is indded VDC but the fet1-6 get their input supply from the DCDC1 and DCDC2 output voltage rails. Update the DeviceTree to better reflect the real connections between tps65090 regulators. Having this information in the DTS is useful since FETs are switches that don't provide an output voltage so the regulator core needs to fetch the FET parent output voltage if the child voltage is queried. Signed-off-by: Javier Martinez Canillas Acked-by: Mark Brown Acked-by: Doug Anderson Signed-off-by: Kukjin Kim diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts b/arch/arm/boot/dts/exynos5420-peach-pit.dts index 7b1ed2c..ab06148 100644 --- a/arch/arm/boot/dts/exynos5420-peach-pit.dts +++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts @@ -357,12 +357,12 @@ vsys2-supply = <&vbat>; vsys3-supply = <&vbat>; infet1-supply = <&vbat>; - infet2-supply = <&vbat>; - infet3-supply = <&vbat>; - infet4-supply = <&vbat>; - infet5-supply = <&vbat>; - infet6-supply = <&vbat>; - infet7-supply = <&vbat>; + infet2-supply = <&tps65090_dcdc1>; + infet3-supply = <&tps65090_dcdc2>; + infet4-supply = <&tps65090_dcdc2>; + infet5-supply = <&tps65090_dcdc2>; + infet6-supply = <&tps65090_dcdc2>; + infet7-supply = <&tps65090_dcdc1>; vsys-l1-supply = <&vbat>; vsys-l2-supply = <&vbat>; diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts b/arch/arm/boot/dts/exynos5800-peach-pi.dts index a587dd6..9ae98aa 100644 --- a/arch/arm/boot/dts/exynos5800-peach-pi.dts +++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts @@ -355,12 +355,12 @@ vsys2-supply = <&vbat>; vsys3-supply = <&vbat>; infet1-supply = <&vbat>; - infet2-supply = <&vbat>; - infet3-supply = <&vbat>; - infet4-supply = <&vbat>; - infet5-supply = <&vbat>; - infet6-supply = <&vbat>; - infet7-supply = <&vbat>; + infet2-supply = <&tps65090_dcdc1>; + infet3-supply = <&tps65090_dcdc2>; + infet4-supply = <&tps65090_dcdc2>; + infet5-supply = <&tps65090_dcdc2>; + infet6-supply = <&tps65090_dcdc2>; + infet7-supply = <&tps65090_dcdc1>; vsys-l1-supply = <&vbat>; vsys-l2-supply = <&vbat>; -- cgit v0.10.2 From 7b5bace34fe1ab412fb44ad1aaeaf9081b898d0a Mon Sep 17 00:00:00 2001 From: Wills Wang Date: Tue, 19 Aug 2014 15:33:00 +0800 Subject: ARM: dts: sun7i: Add uart3/4/5, i2c3 and spi2 pinmux This patch add generic dts node for uart3/4/5, i2c3 and spi2. Reviewed-by: Chen-Yu Tsai Signed-off-by: Wills Wang Signed-off-by: Maxime Ripard diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index c658e34..9f16074 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -634,6 +634,27 @@ allwinner,pull = <0>; }; + uart3_pins_a: uart3@0 { + allwinner,pins = "PG6", "PG7", "PG8", "PG9"; + allwinner,function = "uart3"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + + uart4_pins_a: uart4@0 { + allwinner,pins = "PG10", "PG11"; + allwinner,function = "uart4"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + + uart5_pins_a: uart5@0 { + allwinner,pins = "PI10", "PI11"; + allwinner,function = "uart5"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + uart6_pins_a: uart6@0 { allwinner,pins = "PI12", "PI13"; allwinner,function = "uart6"; @@ -669,6 +690,13 @@ allwinner,pull = <0>; }; + i2c3_pins_a: i2c3@0 { + allwinner,pins = "PI0", "PI1"; + allwinner,function = "i2c3"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + emac_pins_a: emac0@0 { allwinner,pins = "PA0", "PA1", "PA2", "PA3", "PA4", "PA5", "PA6", @@ -734,6 +762,13 @@ allwinner,pull = <0>; }; + spi2_pins_b: spi2@1 { + allwinner,pins = "PB14", "PB15", "PB16", "PB17"; + allwinner,function = "spi2"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + mmc0_pins_a: mmc0@0 { allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5"; allwinner,function = "mmc0"; -- cgit v0.10.2 From d95d6d47138ec1a3ab0a528470f98f8082f389d0 Mon Sep 17 00:00:00 2001 From: Wills Wang Date: Tue, 19 Aug 2014 15:33:01 +0800 Subject: ARM: dts: sun7i: Add Merrii A20 Hummingbird board This adds support for the A20 Hummingbird: http://www.merrii.com/en/pla_d.asp?id=171 This patch enable most on-board peripherals supported on current kernel, such as uart, i2c, spi, pwm, ohci/ehci, gmac and mmc. Reviewed-by: Chen-Yu Tsai Signed-off-by: Wills Wang Signed-off-by: Maxime Ripard diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index b8c5cd3..c72f653 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -416,6 +416,7 @@ dtb-$(CONFIG_MACH_SUN6I) += \ dtb-$(CONFIG_MACH_SUN7I) += \ sun7i-a20-cubieboard2.dtb \ sun7i-a20-cubietruck.dtb \ + sun7i-a20-hummingbird.dtb \ sun7i-a20-i12-tvbox.dtb \ sun7i-a20-olinuxino-micro.dtb \ sun7i-a20-pcduino3.dtb diff --git a/arch/arm/boot/dts/sun7i-a20-hummingbird.dts b/arch/arm/boot/dts/sun7i-a20-hummingbird.dts new file mode 100644 index 0000000..0e4bfa3 --- /dev/null +++ b/arch/arm/boot/dts/sun7i-a20-hummingbird.dts @@ -0,0 +1,236 @@ +/* + * Copyright 2013 Wills Wang + * + * Wills Wang + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +/include/ "sun7i-a20.dtsi" +/include/ "sunxi-common-regulators.dtsi" + +/ { + model = "Merrii A20 Hummingbird"; + compatible = "merrii,a20-hummingbird", "allwinner,sun7i-a20"; + + soc@01c00000 { + mmc0: mmc@01c0f000 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + vmmc-supply = <®_vcc3v0>; + bus-width = <4>; + cd-gpios = <&pio 7 1 0>; /* PH1 */ + cd-inverted; + status = "okay"; + }; + + mmc3: mmc@01c12000 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc3_pins_a>; + vmmc-supply = <®_mmc3_vdd>; + bus-width = <4>; + non-removable; + status = "okay"; + }; + + usbphy: phy@01c13400 { + usb1_vbus-supply = <®_usb1_vbus>; + usb2_vbus-supply = <®_usb2_vbus>; + status = "okay"; + }; + + ehci0: usb@01c14000 { + status = "okay"; + }; + + ohci0: usb@01c14400 { + status = "okay"; + }; + + ahci: sata@01c18000 { + target-supply = <®_ahci_5v>; + status = "okay"; + }; + + ehci1: usb@01c1c000 { + status = "okay"; + }; + + ohci1: usb@01c1c400 { + status = "okay"; + }; + + pio: pinctrl@01c20800 { + ahci_pwr_pin_a20_hummingbird: ahci_pwr_pin@0 { + allwinner,pins = "PH15"; + allwinner,function = "gpio_out"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + + usb1_vbus_pin_a20_hummingbird: usb1_vbus_pin@0 { + allwinner,pins = "PH2"; + allwinner,function = "gpio_out"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + + mmc3_vdd_pin_a20_hummingbird: mmc3_vdd_pin@0 { + allwinner,pins = "PH9"; + allwinner,function = "gpio_out"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + + gmac_vdd_pin_a20_hummingbird: gmac_vdd_pin@0 { + allwinner,pins = "PH16"; + allwinner,function = "gpio_out"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + }; + + pwm: pwm@01c20e00 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_pins_a>; + status = "okay"; + }; + + ir0: ir@01c21800 { + pinctrl-names = "default"; + pinctrl-0 = <&ir0_pins_a>; + status = "okay"; + }; + + uart0: serial@01c28000 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; + }; + + uart2: serial@01c28800 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins_a>; + status = "okay"; + }; + + uart3: serial@01c28c00 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins_a>; + status = "okay"; + }; + + uart4: serial@01c29000 { + pinctrl-names = "default"; + pinctrl-0 = <&uart4_pins_a>; + status = "okay"; + }; + + uart5: serial@01c29400 { + pinctrl-names = "default"; + pinctrl-0 = <&uart5_pins_a>; + status = "okay"; + }; + + i2c0: i2c@01c2ac00 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "okay"; + + axp209: pmic@34 { + compatible = "x-powers,axp209"; + reg = <0x34>; + interrupt-parent = <&nmi_intc>; + interrupts = <0 8>; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + i2c1: i2c@01c2b000 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins_a>; + status = "okay"; + }; + + i2c2: i2c@01c2b400 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins_a>; + status = "okay"; + }; + + i2c3: i2c@01c2b800 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_pins_a>; + status = "okay"; + }; + + spi2: spi@01c17000 { + pinctrl-names = "default"; + pinctrl-0 = <&spi2_pins_b>; + status = "okay"; + }; + + gmac: ethernet@01c50000 { + pinctrl-names = "default"; + pinctrl-0 = <&gmac_pins_rgmii_a>; + phy = <&phy1>; + phy-mode = "rgmii"; + phy-supply = <®_gmac_vdd>; + /* phy reset config */ + snps,reset-gpio = <&pio 0 17 0>; /* PA17 */ + snps,reset-active-low; + /* wait 1s after reset, otherwise fail to read phy id */ + snps,reset-delays-us = <0 10000 1000000>; + status = "okay"; + + phy1: ethernet-phy@1 { + reg = <1>; + }; + }; + }; + + reg_ahci_5v: ahci-5v { + pinctrl-0 = <&ahci_pwr_pin_a20_hummingbird>; + gpio = <&pio 7 15 0>; /* PH15 */ + status = "okay"; + }; + + reg_usb1_vbus: usb1-vbus { + pinctrl-0 = <&usb1_vbus_pin_a20_hummingbird>; + gpio = <&pio 7 2 0>; /* PH2 */ + status = "okay"; + }; + + reg_usb2_vbus: usb2-vbus { + status = "okay"; + }; + + reg_mmc3_vdd: mmc3_vdd { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc3_vdd_pin_a20_hummingbird>; + regulator-name = "mmc3_vdd"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + enable-active-high; + gpio = <&pio 7 9 0>; /* PH9 */ + }; + + reg_gmac_vdd: gmac_vdd { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&gmac_vdd_pin_a20_hummingbird>; + regulator-name = "gmac_vdd"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + enable-active-high; + gpio = <&pio 7 16 0>; /* PH16 */ + }; +}; -- cgit v0.10.2 From 98a295339e565457c732610585da965e4f4f6a26 Mon Sep 17 00:00:00 2001 From: Georgi Djakov Date: Tue, 3 Jun 2014 17:29:40 +0300 Subject: ARM: dts: qcom: Add APQ8084 Global Clock Controller DT node This patch adds the necessary node to probe the global clock controller on APQ8084 platforms. Signed-off-by: Georgi Djakov Reviewed-by: Stephen Boyd diff --git a/arch/arm/boot/dts/qcom-apq8084.dtsi b/arch/arm/boot/dts/qcom-apq8084.dtsi index e3e009a..1e785df 100644 --- a/arch/arm/boot/dts/qcom-apq8084.dtsi +++ b/arch/arm/boot/dts/qcom-apq8084.dtsi @@ -2,6 +2,8 @@ #include "skeleton.dtsi" +#include + / { model = "Qualcomm APQ 8084"; compatible = "qcom,apq8084"; @@ -175,5 +177,13 @@ compatible = "qcom,pshold"; reg = <0xfc4ab000 0x4>; }; + + gcc: clock-controller@fc400000 { + compatible = "qcom,gcc-apq8084"; + #clock-cells = <1>; + #reset-cells = <1>; + reg = <0xfc400000 0x4000>; + }; + }; }; -- cgit v0.10.2 From 14ff1c43881aa8f43d0ec0fa264dc9ed995f801b Mon Sep 17 00:00:00 2001 From: Georgi Djakov Date: Tue, 3 Jun 2014 17:29:41 +0300 Subject: ARM: dts: qcom: Add APQ8084 serial port DT node Add the necessary DT node to probe the serial driver on APQ8084 platforms. Signed-off-by: Georgi Djakov Reviewed-by: Stephen Boyd diff --git a/arch/arm/boot/dts/qcom-apq8084-mtp.dts b/arch/arm/boot/dts/qcom-apq8084-mtp.dts index 9dae387..8ecec58 100644 --- a/arch/arm/boot/dts/qcom-apq8084-mtp.dts +++ b/arch/arm/boot/dts/qcom-apq8084-mtp.dts @@ -3,4 +3,10 @@ / { model = "Qualcomm APQ 8084-MTP"; compatible = "qcom,apq8084-mtp", "qcom,apq8084"; + + soc { + serial@f995e000 { + status = "okay"; + }; + }; }; diff --git a/arch/arm/boot/dts/qcom-apq8084.dtsi b/arch/arm/boot/dts/qcom-apq8084.dtsi index 1e785df..b5b156e 100644 --- a/arch/arm/boot/dts/qcom-apq8084.dtsi +++ b/arch/arm/boot/dts/qcom-apq8084.dtsi @@ -185,5 +185,13 @@ reg = <0xfc400000 0x4000>; }; + serial@f995e000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0xf995e000 0x1000>; + interrupts = <0 114 0x0>; + clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; }; }; -- cgit v0.10.2 From 68de308b1c02f3b11705406b07e84790eb1a37e9 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Fri, 7 Mar 2014 10:56:59 -0600 Subject: ARM: qcom: Add initial IPQ8064 SoC and AP148 device trees Add basic IPQ8064 SoC include device tree and support for basic booting on the AP148 Reference board with support for UART, I2C, and SPI. Signed-off-by: Kumar Gala diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index b8c5cd3..a097a04 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -342,6 +342,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \ qcom-apq8064-ifc6410.dtb \ qcom-apq8074-dragonboard.dtb \ qcom-apq8084-mtp.dtb \ + qcom-ipq8064-ap148.dtb \ qcom-msm8660-surf.dtb \ qcom-msm8960-cdp.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += \ diff --git a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts new file mode 100644 index 0000000..95e6495 --- /dev/null +++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts @@ -0,0 +1,85 @@ +#include "qcom-ipq8064-v1.0.dtsi" + +/ { + model = "Qualcomm IPQ8064/AP148"; + compatible = "qcom,ipq8064-ap148", "qcom,ipq8064"; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + rsvd@41200000 { + reg = <0x41200000 0x300000>; + no-map; + }; + }; + + soc { + pinmux@800000 { + i2c4_pins: i2c4_pinmux { + pins = "gpio12", "gpio13"; + function = "gsbi4"; + bias-disable; + }; + + spi_pins: spi_pins { + mux { + pins = "gpio18", "gpio19", "gpio21"; + function = "gsbi5"; + drive-strength = <10>; + bias-none; + }; + }; + }; + + gsbi@16300000 { + qcom,mode = ; + status = "ok"; + serial@16340000 { + status = "ok"; + }; + + i2c4: i2c@16380000 { + status = "ok"; + + clock-frequency = <200000>; + + pinctrl-0 = <&i2c4_pins>; + pinctrl-names = "default"; + }; + }; + + gsbi5: gsbi@1a200000 { + qcom,mode = ; + status = "ok"; + + spi4: spi@1a280000 { + status = "ok"; + spi-max-frequency = <50000000>; + + pinctrl-0 = <&spi_pins>; + pinctrl-names = "default"; + + cs-gpios = <&qcom_pinmux 20 0>; + + flash: m25p80@0 { + compatible = "s25fl256s1"; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <50000000>; + reg = <0>; + + partition@0 { + label = "rootfs"; + reg = <0x0 0x1000000>; + }; + + partition@1 { + label = "scratch"; + reg = <0x1000000 0x1000000>; + }; + }; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi b/arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi new file mode 100644 index 0000000..7093b07 --- /dev/null +++ b/arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi @@ -0,0 +1 @@ +#include "qcom-ipq8064.dtsi" diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi new file mode 100644 index 0000000..244f857 --- /dev/null +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi @@ -0,0 +1,250 @@ +/dts-v1/; + +#include "skeleton.dtsi" +#include +#include + +/ { + model = "Qualcomm IPQ8064"; + compatible = "qcom,ipq8064"; + interrupt-parent = <&intc>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "qcom,krait"; + enable-method = "qcom,kpss-acc-v1"; + device_type = "cpu"; + reg = <0>; + next-level-cache = <&L2>; + qcom,acc = <&acc0>; + qcom,saw = <&saw0>; + }; + + cpu@1 { + compatible = "qcom,krait"; + enable-method = "qcom,kpss-acc-v1"; + device_type = "cpu"; + reg = <1>; + next-level-cache = <&L2>; + qcom,acc = <&acc1>; + qcom,saw = <&saw1>; + }; + + L2: l2-cache { + compatible = "cache"; + cache-level = <2>; + }; + }; + + cpu-pmu { + compatible = "qcom,krait-pmu"; + interrupts = <1 10 0x304>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + nss@40000000 { + reg = <0x40000000 0x1000000>; + no-map; + }; + + smem@41000000 { + reg = <0x41000000 0x200000>; + no-map; + }; + }; + + soc: soc { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "simple-bus"; + + qcom_pinmux: pinmux@800000 { + compatible = "qcom,ipq8064-pinctrl"; + reg = <0x800000 0x4000>; + + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <0 32 0x4>; + }; + + intc: interrupt-controller@2000000 { + compatible = "qcom,msm-qgic2"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0x02000000 0x1000>, + <0x02002000 0x1000>; + }; + + timer@200a000 { + compatible = "qcom,kpss-timer", "qcom,msm-timer"; + interrupts = <1 1 0x301>, + <1 2 0x301>, + <1 3 0x301>; + reg = <0x0200a000 0x100>; + clock-frequency = <25000000>, + <32768>; + cpu-offset = <0x80000>; + }; + + acc0: clock-controller@2088000 { + compatible = "qcom,kpss-acc-v1"; + reg = <0x02088000 0x1000>, <0x02008000 0x1000>; + }; + + acc1: clock-controller@2098000 { + compatible = "qcom,kpss-acc-v1"; + reg = <0x02098000 0x1000>, <0x02008000 0x1000>; + }; + + saw0: regulator@2089000 { + compatible = "qcom,saw2"; + reg = <0x02089000 0x1000>, <0x02009000 0x1000>; + regulator; + }; + + saw1: regulator@2099000 { + compatible = "qcom,saw2"; + reg = <0x02099000 0x1000>, <0x02009000 0x1000>; + regulator; + }; + + gsbi2: gsbi@12480000 { + compatible = "qcom,gsbi-v1.0.0"; + reg = <0x12480000 0x100>; + clocks = <&gcc GSBI2_H_CLK>; + clock-names = "iface"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + status = "disabled"; + + serial@12490000 { + compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; + reg = <0x12490000 0x1000>, + <0x12480000 0x1000>; + interrupts = <0 195 0x0>; + clocks = <&gcc GSBI2_UART_CLK>, <&gcc GSBI2_H_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + + i2c@124a0000 { + compatible = "qcom,i2c-qup-v1.1.1"; + reg = <0x124a0000 0x1000>; + interrupts = <0 196 0>; + + clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + }; + + }; + + gsbi4: gsbi@16300000 { + compatible = "qcom,gsbi-v1.0.0"; + reg = <0x16300000 0x100>; + clocks = <&gcc GSBI4_H_CLK>; + clock-names = "iface"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + status = "disabled"; + + serial@16340000 { + compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; + reg = <0x16340000 0x1000>, + <0x16300000 0x1000>; + interrupts = <0 152 0x0>; + clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + + i2c@16380000 { + compatible = "qcom,i2c-qup-v1.1.1"; + reg = <0x16380000 0x1000>; + interrupts = <0 153 0>; + + clocks = <&gcc GSBI4_QUP_CLK>, <&gcc GSBI4_H_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + gsbi5: gsbi@1a200000 { + compatible = "qcom,gsbi-v1.0.0"; + reg = <0x1a200000 0x100>; + clocks = <&gcc GSBI5_H_CLK>; + clock-names = "iface"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + status = "disabled"; + + serial@1a240000 { + compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; + reg = <0x1a240000 0x1000>, + <0x1a200000 0x1000>; + interrupts = <0 154 0x0>; + clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + + i2c@1a280000 { + compatible = "qcom,i2c-qup-v1.1.1"; + reg = <0x1a280000 0x1000>; + interrupts = <0 155 0>; + + clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + }; + + spi@1a280000 { + compatible = "qcom,spi-qup-v1.1.1"; + reg = <0x1a280000 0x1000>; + interrupts = <0 155 0>; + + clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + qcom,ssbi@500000 { + compatible = "qcom,ssbi"; + reg = <0x00500000 0x1000>; + qcom,controller-type = "pmic-arbiter"; + }; + + gcc: clock-controller@900000 { + compatible = "qcom,gcc-ipq8064"; + reg = <0x00900000 0x4000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + }; +}; diff --git a/arch/arm/mach-qcom/board.c b/arch/arm/mach-qcom/board.c index c437a99..6d8bbf7 100644 --- a/arch/arm/mach-qcom/board.c +++ b/arch/arm/mach-qcom/board.c @@ -18,6 +18,8 @@ static const char * const qcom_dt_match[] __initconst = { "qcom,apq8064", "qcom,apq8074-dragonboard", "qcom,apq8084", + "qcom,ipq8062", + "qcom,ipq8064", "qcom,msm8660-surf", "qcom,msm8960-cdp", NULL -- cgit v0.10.2 From da076a888ab19f13816372796ed231e7d6ff5fed Mon Sep 17 00:00:00 2001 From: Mikhail Ulyanov Date: Tue, 19 Aug 2014 16:50:49 +0400 Subject: ARM: shmobile: r8a7790: Add JPU clock dt and CPG define. Signed-off-by: Mikhail Ulyanov Acked-by: Laurent Pinchart Signed-off-by: Simon Horman diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index 2278bd0..c11541d 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -836,17 +836,17 @@ mstp1_clks: mstp1_clks@e6150134 { compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>; - clocks = <&p_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>, + clocks = <&m2_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>, <&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>; #clock-cells = <1>; renesas,clock-indices = < - R8A7790_CLK_TMU1 R8A7790_CLK_TMU3 R8A7790_CLK_TMU2 + R8A7790_CLK_JPU R8A7790_CLK_TMU1 R8A7790_CLK_TMU3 R8A7790_CLK_TMU2 R8A7790_CLK_CMT0 R8A7790_CLK_TMU0 R8A7790_CLK_VSP1_DU1 R8A7790_CLK_VSP1_DU0 R8A7790_CLK_VSP1_R R8A7790_CLK_VSP1_S >; clock-output-names = - "tmu1", "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1", + "jpu", "tmu1", "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1", "vsp1-du0", "vsp1-rt", "vsp1-sy"; }; mstp2_clks: mstp2_clks@e6150138 { diff --git a/include/dt-bindings/clock/r8a7790-clock.h b/include/dt-bindings/clock/r8a7790-clock.h index f929a79e..8ea7ab0 100644 --- a/include/dt-bindings/clock/r8a7790-clock.h +++ b/include/dt-bindings/clock/r8a7790-clock.h @@ -26,6 +26,7 @@ #define R8A7790_CLK_MSIOF0 0 /* MSTP1 */ +#define R8A7790_CLK_JPU 6 #define R8A7790_CLK_TMU1 11 #define R8A7790_CLK_TMU3 21 #define R8A7790_CLK_TMU2 22 -- cgit v0.10.2 From ed48b5d6fd339d145df5a6a1e48cf56ef265cf4f Mon Sep 17 00:00:00 2001 From: Mikhail Ulyanov Date: Tue, 19 Aug 2014 16:50:51 +0400 Subject: ARM: shmobile: r8a7791: Add JPU clock dt and CPG define. Signed-off-by: Mikhail Ulyanov Acked-by: Laurent Pinchart Signed-off-by: Simon Horman diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi index f26226e..d62c237 100644 --- a/arch/arm/boot/dts/r8a7791.dtsi +++ b/arch/arm/boot/dts/r8a7791.dtsi @@ -857,16 +857,16 @@ mstp1_clks: mstp1_clks@e6150134 { compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>; - clocks = <&p_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>, + clocks = <&m2_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>, <&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>; #clock-cells = <1>; renesas,clock-indices = < - R8A7791_CLK_TMU1 R8A7791_CLK_TMU3 R8A7791_CLK_TMU2 + R8A7791_CLK_JPU R8A7791_CLK_TMU1 R8A7791_CLK_TMU3 R8A7791_CLK_TMU2 R8A7791_CLK_CMT0 R8A7791_CLK_TMU0 R8A7791_CLK_VSP1_DU1 R8A7791_CLK_VSP1_DU0 R8A7791_CLK_VSP1_S >; clock-output-names = - "tmu1", "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1", + "jpu", "tmu1", "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1", "vsp1-du0", "vsp1-sy"; }; mstp2_clks: mstp2_clks@e6150138 { diff --git a/include/dt-bindings/clock/r8a7791-clock.h b/include/dt-bindings/clock/r8a7791-clock.h index f0d4d10..58c3f49 100644 --- a/include/dt-bindings/clock/r8a7791-clock.h +++ b/include/dt-bindings/clock/r8a7791-clock.h @@ -25,6 +25,7 @@ #define R8A7791_CLK_MSIOF0 0 /* MSTP1 */ +#define R8A7791_CLK_JPU 6 #define R8A7791_CLK_TMU1 11 #define R8A7791_CLK_TMU3 21 #define R8A7791_CLK_TMU2 22 -- cgit v0.10.2 From d6fb17ad7c9e0aa28ce0bc2e33790f9459677370 Mon Sep 17 00:00:00 2001 From: Ulrich Hecht Date: Fri, 8 Aug 2014 16:23:09 +0200 Subject: ARM: shmobile: r8a7740: clock register bits Contains the header file with the clock pulse generator and MSTP bits. Signed-off-by: Ulrich Hecht Signed-off-by: Simon Horman diff --git a/include/dt-bindings/clock/r8a7740-clock.h b/include/dt-bindings/clock/r8a7740-clock.h new file mode 100644 index 0000000..f6b4b0f --- /dev/null +++ b/include/dt-bindings/clock/r8a7740-clock.h @@ -0,0 +1,77 @@ +/* + * Copyright 2014 Ulrich Hecht + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef __DT_BINDINGS_CLOCK_R8A7740_H__ +#define __DT_BINDINGS_CLOCK_R8A7740_H__ + +/* CPG */ +#define R8A7740_CLK_SYSTEM 0 +#define R8A7740_CLK_PLLC0 1 +#define R8A7740_CLK_PLLC1 2 +#define R8A7740_CLK_PLLC2 3 +#define R8A7740_CLK_R 4 +#define R8A7740_CLK_USB24S 5 +#define R8A7740_CLK_I 6 +#define R8A7740_CLK_ZG 7 +#define R8A7740_CLK_B 8 +#define R8A7740_CLK_M1 9 +#define R8A7740_CLK_HP 10 +#define R8A7740_CLK_HPP 11 +#define R8A7740_CLK_USBP 12 +#define R8A7740_CLK_S 13 +#define R8A7740_CLK_ZB 14 +#define R8A7740_CLK_M3 15 +#define R8A7740_CLK_CP 16 + +/* MSTP1 */ +#define R8A7740_CLK_CEU21 28 +#define R8A7740_CLK_CEU20 27 +#define R8A7740_CLK_TMU0 25 +#define R8A7740_CLK_LCDC1 17 +#define R8A7740_CLK_IIC0 16 +#define R8A7740_CLK_TMU1 11 +#define R8A7740_CLK_LCDC0 0 + +/* MSTP2 */ +#define R8A7740_CLK_SCIFA6 30 +#define R8A7740_CLK_SCIFA7 22 +#define R8A7740_CLK_DMAC1 18 +#define R8A7740_CLK_DMAC2 17 +#define R8A7740_CLK_DMAC3 16 +#define R8A7740_CLK_USBDMAC 14 +#define R8A7740_CLK_SCIFA5 7 +#define R8A7740_CLK_SCIFB 6 +#define R8A7740_CLK_SCIFA0 4 +#define R8A7740_CLK_SCIFA1 3 +#define R8A7740_CLK_SCIFA2 2 +#define R8A7740_CLK_SCIFA3 1 +#define R8A7740_CLK_SCIFA4 0 + +/* MSTP3 */ +#define R8A7740_CLK_CMT1 29 +#define R8A7740_CLK_FSI 28 +#define R8A7740_CLK_IIC1 23 +#define R8A7740_CLK_USBF 20 +#define R8A7740_CLK_SDHI0 14 +#define R8A7740_CLK_SDHI1 13 +#define R8A7740_CLK_MMC 12 +#define R8A7740_CLK_GETHER 9 +#define R8A7740_CLK_TPU0 4 + +/* MSTP4 */ +#define R8A7740_CLK_USBH 16 +#define R8A7740_CLK_SDHI2 15 +#define R8A7740_CLK_USBFUNC 7 +#define R8A7740_CLK_USBPHY 6 + +/* SUBCK* */ +#define R8A7740_CLK_SUBCK 9 +#define R8A7740_CLK_SUBCK2 10 + +#endif /* __DT_BINDINGS_CLOCK_R8A7740_H__ */ -- cgit v0.10.2 From 6a7147f53f29887e627d84c0a562c8bb87691e9d Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 20 Aug 2014 16:28:31 +0200 Subject: ARM: shmobile: r8a7779 dtsi: Remove superfluous interrupt-parent There's already an "interrupt-parent = <&gic>;" at the top, which is inherited by all child nodes, so the "interrupt-parent" properties in the serial nodes can be removed. Signed-off-by: Geert Uytterhoeven Acked-by: Magnus Damm Signed-off-by: Simon Horman diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi index 58d0d95..0e64c76 100644 --- a/arch/arm/boot/dts/r8a7779.dtsi +++ b/arch/arm/boot/dts/r8a7779.dtsi @@ -199,7 +199,6 @@ scif0: serial@ffe40000 { compatible = "renesas,scif-r8a7779", "renesas,scif"; reg = <0xffe40000 0x100>; - interrupt-parent = <&gic>; interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg_clocks R8A7779_CLK_P>; clock-names = "sci_ick"; @@ -209,7 +208,6 @@ scif1: serial@ffe41000 { compatible = "renesas,scif-r8a7779", "renesas,scif"; reg = <0xffe41000 0x100>; - interrupt-parent = <&gic>; interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg_clocks R8A7779_CLK_P>; clock-names = "sci_ick"; @@ -219,7 +217,6 @@ scif2: serial@ffe42000 { compatible = "renesas,scif-r8a7779", "renesas,scif"; reg = <0xffe42000 0x100>; - interrupt-parent = <&gic>; interrupts = <0 90 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg_clocks R8A7779_CLK_P>; clock-names = "sci_ick"; @@ -229,7 +226,6 @@ scif3: serial@ffe43000 { compatible = "renesas,scif-r8a7779", "renesas,scif"; reg = <0xffe43000 0x100>; - interrupt-parent = <&gic>; interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg_clocks R8A7779_CLK_P>; clock-names = "sci_ick"; @@ -239,7 +235,6 @@ scif4: serial@ffe44000 { compatible = "renesas,scif-r8a7779", "renesas,scif"; reg = <0xffe44000 0x100>; - interrupt-parent = <&gic>; interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg_clocks R8A7779_CLK_P>; clock-names = "sci_ick"; @@ -249,7 +244,6 @@ scif5: serial@ffe45000 { compatible = "renesas,scif-r8a7779", "renesas,scif"; reg = <0xffe45000 0x100>; - interrupt-parent = <&gic>; interrupts = <0 93 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg_clocks R8A7779_CLK_P>; clock-names = "sci_ick"; -- cgit v0.10.2 From 980724eb5b56b43d0ff2c7a7f5cf6e5ba290d2e5 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 20 Aug 2014 16:28:32 +0200 Subject: ARM: shmobile: r8a7790 dtsi: Remove superfluous interrupt-parent There's already an "interrupt-parent = <&gic>;" at the top, which is inherited by all child nodes, so the "interrupt-parent" property in the sound node can be removed. Signed-off-by: Geert Uytterhoeven Acked-by: Magnus Damm Signed-off-by: Simon Horman diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index c11541d..4b6915a 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -1126,7 +1126,6 @@ rcar_sound: rcar_sound@0xec500000 { #sound-dai-cells = <1>; compatible = "renesas,rcar_sound-r8a7790", "renesas,rcar_sound-gen2", "renesas,rcar_sound"; - interrupt-parent = <&gic>; reg = <0 0xec500000 0 0x1000>, /* SCU */ <0 0xec5a0000 0 0x100>, /* ADG */ <0 0xec540000 0 0x1000>, /* SSIU */ -- cgit v0.10.2 From 5fb1453c2ff02ce5e5298351ff774e19f8d9dbb3 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 20 Aug 2014 16:31:02 +0200 Subject: ARM: shmobile: r8a7791 dtsi: Remove superfluous interrupt-parent There's already an "interrupt-parent = <&gic>;" at the top, which is inherited by all child nodes, so the "interrupt-parent" property in the sound node can be removed. Signed-off-by: Geert Uytterhoeven Acked-by: Magnus Damm Signed-off-by: Simon Horman diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi index d62c237..9ee1d41 100644 --- a/arch/arm/boot/dts/r8a7791.dtsi +++ b/arch/arm/boot/dts/r8a7791.dtsi @@ -1124,7 +1124,6 @@ rcar_sound: rcar_sound@0xec500000 { #sound-dai-cells = <1>; compatible = "renesas,rcar_sound-r8a7791", "renesas,rcar_sound-gen2", "renesas,rcar_sound"; - interrupt-parent = <&gic>; reg = <0 0xec500000 0 0x1000>, /* SCU */ <0 0xec5a0000 0 0x100>, /* ADG */ <0 0xec540000 0 0x1000>, /* SSIU */ -- cgit v0.10.2 From f170b97c9ad0b8ba3e99f02cbadc7676383fee09 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 20 Aug 2014 16:28:34 +0200 Subject: ARM: shmobile: sh73a0 dtsi: Move interrupt-parent to the top Add an "interrupt-parent = <&gic>;" at the top, which is inherited by all child nodes, so the "interrupt-parent" properties can be removed from the individual child nodes. Signed-off-by: Geert Uytterhoeven Acked-by: Magnus Damm Signed-off-by: Simon Horman diff --git a/arch/arm/boot/dts/sh73a0.dtsi b/arch/arm/boot/dts/sh73a0.dtsi index 910b790..c959355 100644 --- a/arch/arm/boot/dts/sh73a0.dtsi +++ b/arch/arm/boot/dts/sh73a0.dtsi @@ -14,6 +14,7 @@ / { compatible = "renesas,sh73a0"; + interrupt-parent = <&gic>; cpus { #address-cells = <1>; @@ -54,7 +55,6 @@ <0xe6900020 1>, <0xe6900040 1>, <0xe6900060 1>; - interrupt-parent = <&gic>; interrupts = <0 1 IRQ_TYPE_LEVEL_HIGH 0 2 IRQ_TYPE_LEVEL_HIGH 0 3 IRQ_TYPE_LEVEL_HIGH @@ -74,7 +74,6 @@ <0xe6900024 1>, <0xe6900044 1>, <0xe6900064 1>; - interrupt-parent = <&gic>; interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH 0 10 IRQ_TYPE_LEVEL_HIGH 0 11 IRQ_TYPE_LEVEL_HIGH @@ -95,7 +94,6 @@ <0xe6900028 1>, <0xe6900048 1>, <0xe6900068 1>; - interrupt-parent = <&gic>; interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH 0 18 IRQ_TYPE_LEVEL_HIGH 0 19 IRQ_TYPE_LEVEL_HIGH @@ -115,7 +113,6 @@ <0xe690002c 1>, <0xe690004c 1>, <0xe690006c 1>; - interrupt-parent = <&gic>; interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH 0 26 IRQ_TYPE_LEVEL_HIGH 0 27 IRQ_TYPE_LEVEL_HIGH @@ -131,7 +128,6 @@ #size-cells = <0>; compatible = "renesas,rmobile-iic"; reg = <0xe6820000 0x425>; - interrupt-parent = <&gic>; interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH 0 168 IRQ_TYPE_LEVEL_HIGH 0 169 IRQ_TYPE_LEVEL_HIGH @@ -144,7 +140,6 @@ #size-cells = <0>; compatible = "renesas,rmobile-iic"; reg = <0xe6822000 0x425>; - interrupt-parent = <&gic>; interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH 0 52 IRQ_TYPE_LEVEL_HIGH 0 53 IRQ_TYPE_LEVEL_HIGH @@ -157,7 +152,6 @@ #size-cells = <0>; compatible = "renesas,rmobile-iic"; reg = <0xe6824000 0x425>; - interrupt-parent = <&gic>; interrupts = <0 171 IRQ_TYPE_LEVEL_HIGH 0 172 IRQ_TYPE_LEVEL_HIGH 0 173 IRQ_TYPE_LEVEL_HIGH @@ -170,7 +164,6 @@ #size-cells = <0>; compatible = "renesas,rmobile-iic"; reg = <0xe6826000 0x425>; - interrupt-parent = <&gic>; interrupts = <0 183 IRQ_TYPE_LEVEL_HIGH 0 184 IRQ_TYPE_LEVEL_HIGH 0 185 IRQ_TYPE_LEVEL_HIGH @@ -183,7 +176,6 @@ #size-cells = <0>; compatible = "renesas,rmobile-iic"; reg = <0xe6828000 0x425>; - interrupt-parent = <&gic>; interrupts = <0 187 IRQ_TYPE_LEVEL_HIGH 0 188 IRQ_TYPE_LEVEL_HIGH 0 189 IRQ_TYPE_LEVEL_HIGH @@ -194,7 +186,6 @@ mmcif: mmc@e6bd0000 { compatible = "renesas,sh-mmcif"; reg = <0xe6bd0000 0x100>; - interrupt-parent = <&gic>; interrupts = <0 140 IRQ_TYPE_LEVEL_HIGH 0 141 IRQ_TYPE_LEVEL_HIGH>; reg-io-width = <4>; @@ -204,7 +195,6 @@ sdhi0: sd@ee100000 { compatible = "renesas,sdhi-sh73a0"; reg = <0xee100000 0x100>; - interrupt-parent = <&gic>; interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH 0 84 IRQ_TYPE_LEVEL_HIGH 0 85 IRQ_TYPE_LEVEL_HIGH>; @@ -216,7 +206,6 @@ sdhi1: sd@ee120000 { compatible = "renesas,sdhi-sh73a0"; reg = <0xee120000 0x100>; - interrupt-parent = <&gic>; interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH 0 89 IRQ_TYPE_LEVEL_HIGH>; toshiba,mmc-wrprotect-disable; @@ -227,7 +216,6 @@ sdhi2: sd@ee140000 { compatible = "renesas,sdhi-sh73a0"; reg = <0xee140000 0x100>; - interrupt-parent = <&gic>; interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH 0 105 IRQ_TYPE_LEVEL_HIGH>; toshiba,mmc-wrprotect-disable; @@ -238,7 +226,6 @@ scifa0: serial@e6c40000 { compatible = "renesas,scifa-sh73a0", "renesas,scifa"; reg = <0xe6c40000 0x100>; - interrupt-parent = <&gic>; interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; @@ -246,7 +233,6 @@ scifa1: serial@e6c50000 { compatible = "renesas,scifa-sh73a0", "renesas,scifa"; reg = <0xe6c50000 0x100>; - interrupt-parent = <&gic>; interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; @@ -254,7 +240,6 @@ scifa2: serial@e6c60000 { compatible = "renesas,scifa-sh73a0", "renesas,scifa"; reg = <0xe6c60000 0x100>; - interrupt-parent = <&gic>; interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; @@ -262,7 +247,6 @@ scifa3: serial@e6c70000 { compatible = "renesas,scifa-sh73a0", "renesas,scifa"; reg = <0xe6c70000 0x100>; - interrupt-parent = <&gic>; interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; @@ -270,7 +254,6 @@ scifa4: serial@e6c80000 { compatible = "renesas,scifa-sh73a0", "renesas,scifa"; reg = <0xe6c80000 0x100>; - interrupt-parent = <&gic>; interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; @@ -278,7 +261,6 @@ scifa5: serial@e6cb0000 { compatible = "renesas,scifa-sh73a0", "renesas,scifa"; reg = <0xe6cb0000 0x100>; - interrupt-parent = <&gic>; interrupts = <0 79 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; @@ -286,7 +268,6 @@ scifa6: serial@e6cc0000 { compatible = "renesas,scifa-sh73a0", "renesas,scifa"; reg = <0xe6cc0000 0x100>; - interrupt-parent = <&gic>; interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; @@ -294,7 +275,6 @@ scifa7: serial@e6cd0000 { compatible = "renesas,scifa-sh73a0", "renesas,scifa"; reg = <0xe6cd0000 0x100>; - interrupt-parent = <&gic>; interrupts = <0 143 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; @@ -302,7 +282,6 @@ scifb8: serial@e6c30000 { compatible = "renesas,scifb-sh73a0", "renesas,scifb"; reg = <0xe6c30000 0x100>; - interrupt-parent = <&gic>; interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; @@ -328,7 +307,6 @@ #sound-dai-cells = <1>; compatible = "renesas,sh_fsi2"; reg = <0xec230000 0x400>; - interrupt-parent = <&gic>; interrupts = <0 146 0x4>; status = "disabled"; }; -- cgit v0.10.2 From 06b57f1d9ea7b495af4b3e3b4372e5a4ebc1f7d9 Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Fri, 1 Aug 2014 09:13:25 +0300 Subject: ARM: davinci: da8xx-dt: add OF_DEV_AUXDATA entry for mcasp0 Add OF_DEV_AUXDATA for mcasp to be able to use clocks. Signed-off-by: Peter Ujfalusi Signed-off-by: Sekhar Nori diff --git a/arch/arm/mach-davinci/da8xx-dt.c b/arch/arm/mach-davinci/da8xx-dt.c index ed19287..f703d82 100644 --- a/arch/arm/mach-davinci/da8xx-dt.c +++ b/arch/arm/mach-davinci/da8xx-dt.c @@ -46,6 +46,7 @@ static struct of_dev_auxdata da850_auxdata_lookup[] __initdata = { OF_DEV_AUXDATA("ti,davinci_mdio", 0x01e24000, "davinci_mdio.0", NULL), OF_DEV_AUXDATA("ti,davinci-dm6467-emac", 0x01e20000, "davinci_emac.1", NULL), + OF_DEV_AUXDATA("ti,da830-mcasp-audio", 0x01d00000, "davinci-mcasp.0", NULL), {} }; -- cgit v0.10.2 From ee766e4d0712e510898e4413fd968f8cdb450bcf Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Fri, 1 Aug 2014 09:13:26 +0300 Subject: ARM: DTS: da850: Add node for edma0 Add DT node for edma0. Signed-off-by: Peter Ujfalusi Signed-off-by: Sekhar Nori diff --git a/arch/arm/boot/dts/da850.dtsi b/arch/arm/boot/dts/da850.dtsi index b695548..41ce4e8 100644 --- a/arch/arm/boot/dts/da850.dtsi +++ b/arch/arm/boot/dts/da850.dtsi @@ -150,6 +150,12 @@ }; }; + edma0: edma@01c00000 { + compatible = "ti,edma3"; + reg = <0x0 0x10000>; + interrupts = <11 13 12>; + #dma-cells = <1>; + }; serial0: serial@1c42000 { compatible = "ns16550a"; reg = <0x42000 0x100>; -- cgit v0.10.2 From db74904eb84c6ad3bde17ccd9d7ee1e2a7822ed9 Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Fri, 1 Aug 2014 09:13:27 +0300 Subject: ARM: DTS: da850: Add node for McASP Node for mcasp0 Signed-off-by: Peter Ujfalusi Signed-off-by: Sekhar Nori diff --git a/arch/arm/boot/dts/da850.dtsi b/arch/arm/boot/dts/da850.dtsi index 41ce4e8..0bd98cd 100644 --- a/arch/arm/boot/dts/da850.dtsi +++ b/arch/arm/boot/dts/da850.dtsi @@ -276,6 +276,19 @@ ti,davinci-gpio-unbanked = <0>; status = "disabled"; }; + + mcasp0: mcasp@01d00000 { + compatible = "ti,da830-mcasp-audio"; + reg = <0x100000 0x2000>, + <0x102000 0x400000>; + reg-names = "mpu", "dat"; + interrupts = <54>; + interrupt-names = "common"; + status = "disabled"; + dmas = <&edma0 1>, + <&edma0 0>; + dma-names = "tx", "rx"; + }; }; nand_cs3@62000000 { compatible = "ti,davinci-nand"; -- cgit v0.10.2 From 4ec582e924825e649ca4cdc1fb9eac0b97c75d60 Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Fri, 1 Aug 2014 09:13:28 +0300 Subject: ARM: DTS: da850-evm: Enable McASP via DT boot Add pinctrl nodes for the McASP0 pins and configure McASP to the desired mode for the board. Signed-off-by: Peter Ujfalusi Signed-off-by: Sekhar Nori diff --git a/arch/arm/boot/dts/da850-evm.dts b/arch/arm/boot/dts/da850-evm.dts index 1e11e5a..1422c31 100644 --- a/arch/arm/boot/dts/da850-evm.dts +++ b/arch/arm/boot/dts/da850-evm.dts @@ -17,6 +17,18 @@ soc { pmx_core: pinmux@1c14120 { status = "okay"; + + mcasp0_pins: pinmux_mcasp0_pins { + pinctrl-single,bits = < + /* + * AHCLKX, ACLKX, AFSX, AHCLKR, ACLKR, + * AFSR, AMUTE + */ + 0x00 0x11111111 0xffffffff + /* AXR11, AXR12 */ + 0x04 0x00011000 0x000ff000 + >; + }; }; serial0: serial@1c42000 { status = "okay"; @@ -170,3 +182,21 @@ }; }; }; + +&mcasp0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcasp0_pins>; + + op-mode = <0>; /* MCASP_IIS_MODE */ + tdm-slots = <2>; + /* 4 serializer */ + serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ + 0 0 0 0 + 0 0 0 0 + 0 0 0 1 + 2 0 0 0 + >; + tx-num-evt = <32>; + rx-num-evt = <32>; +}; -- cgit v0.10.2 From 204a87ed4bf80257ed89fd1647628d6b05545ad0 Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Fri, 1 Aug 2014 09:13:29 +0300 Subject: ARM: DTS: da850-evm: Add node for tlv320aic3106 codec The board uses aic3106 for audio. Signed-off-by: Peter Ujfalusi Signed-off-by: Sekhar Nori diff --git a/arch/arm/boot/dts/da850-evm.dts b/arch/arm/boot/dts/da850-evm.dts index 1422c31..41715b4 100644 --- a/arch/arm/boot/dts/da850-evm.dts +++ b/arch/arm/boot/dts/da850-evm.dts @@ -51,6 +51,19 @@ tps: tps@48 { reg = <0x48>; }; + tlv320aic3106: tlv320aic3106@18 { + compatible = "ti,tlv320aic3106"; + reg = <0x18>; + status = "okay"; + + /* Regulators */ + IOVDD-supply = <&vdcdc2_reg>; + /* Derived from VBAT: Baseboard 3.3V / 1.8V */ + AVDD-supply = <&vbat>; + DRVDD-supply = <&vbat>; + DVDD-supply = <&vbat>; + }; + }; wdt: wdt@1c21000 { status = "okay"; -- cgit v0.10.2 From 3f526696e7840239844fc7ff9b5cf014d7192c42 Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Fri, 1 Aug 2014 09:13:30 +0300 Subject: ARM: DTS: da850-evm: Enable audio via simple-card The audio on the board is using McASP <-> tlv320aic3106 codec and we have LineIn and LineOut jacks. Signed-off-by: Peter Ujfalusi Signed-off-by: Sekhar Nori diff --git a/arch/arm/boot/dts/da850-evm.dts b/arch/arm/boot/dts/da850-evm.dts index 41715b4..4f935ad 100644 --- a/arch/arm/boot/dts/da850-evm.dts +++ b/arch/arm/boot/dts/da850-evm.dts @@ -52,6 +52,7 @@ reg = <0x48>; }; tlv320aic3106: tlv320aic3106@18 { + #sound-dai-cells = <0>; compatible = "ti,tlv320aic3106"; reg = <0x18>; status = "okay"; @@ -142,6 +143,33 @@ regulator-max-microvolt = <5000000>; regulator-boot-on; }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "DA850/OMAP-L138 EVM"; + simple-audio-card,widgets = + "Line", "Line In", + "Line", "Line Out"; + simple-audio-card,routing = + "LINE1L", "Line In", + "LINE1R", "Line In", + "Line Out", "LLOUT", + "Line Out", "RLOUT"; + simple-audio-card,format = "dsp_b"; + simple-audio-card,bitclock-master = <&link0_codec>; + simple-audio-card,frame-master = <&link0_codec>; + simple-audio-card,bitclock-inversion; + + simple-audio-card,cpu { + sound-dai = <&mcasp0>; + system-clock-frequency = <24576000>; + }; + + link0_codec: simple-audio-card,codec { + sound-dai = <&tlv320aic3106>; + system-clock-frequency = <24576000>; + }; + }; }; /include/ "tps6507x.dtsi" @@ -197,6 +225,7 @@ }; &mcasp0 { + #sound-dai-cells = <0>; status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&mcasp0_pins>; -- cgit v0.10.2 From fdd690969b8b05b0636ac46a66a885c5b1ccd651 Mon Sep 17 00:00:00 2001 From: Mikko Perttunen Date: Wed, 16 Jul 2014 11:54:17 +0300 Subject: ARM: tegra: Add SATA controller to Tegra124 device tree This adds the integrated AHCI-compliant Serial ATA controller present in Tegra124 systems-on-chip to the Tegra124 device tree. Signed-off-by: Mikko Perttunen [swarren, fixed node sort order] Signed-off-by: Stephen Warren diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index 03916ef..727d395 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -480,6 +480,31 @@ reset-names = "fuse"; }; + sata@0,70020000 { + compatible = "nvidia,tegra124-ahci"; + + reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */ + <0x0 0x70020000 0x0 0x7000>; /* SATA */ + + interrupts = ; + + clocks = <&tegra_car TEGRA124_CLK_SATA>, + <&tegra_car TEGRA124_CLK_SATA_OOB>, + <&tegra_car TEGRA124_CLK_CML1>, + <&tegra_car TEGRA124_CLK_PLL_E>; + clock-names = "sata", "sata-oob", "cml1", "pll_e"; + + resets = <&tegra_car 124>, + <&tegra_car 123>, + <&tegra_car 129>; + reset-names = "sata", "sata-oob", "sata-cold"; + + phys = <&padctl TEGRA_XUSB_PADCTL_SATA>; + phy-names = "sata-phy"; + + status = "disabled"; + }; + hda@0,70030000 { compatible = "nvidia,tegra124-hda", "nvidia,tegra30-hda"; reg = <0x0 0x70030000 0x0 0x10000>; -- cgit v0.10.2 From 1b3ce99f930f991cb2e2b848f35321e23b6020a6 Mon Sep 17 00:00:00 2001 From: Mikko Perttunen Date: Wed, 16 Jul 2014 11:54:18 +0300 Subject: ARM: tegra: Add SATA and SATA power to Jetson TK1 device tree This enables the integrated SATA controller on the Tegra124 system-on-chip on the Jetson TK1 board and adds regulators for the onboard Molex connector commonly used to power SATA devices. The regulators are marked always-on since they can be used for other purposes than powering SATA devices. Signed-off-by: Mikko Perttunen [swarren, fixed node sort order] Signed-off-by: Stephen Warren diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1.dts b/arch/arm/boot/dts/tegra124-jetson-tk1.dts index 624b0fb..ef578a7 100644 --- a/arch/arm/boot/dts/tegra124-jetson-tk1.dts +++ b/arch/arm/boot/dts/tegra124-jetson-tk1.dts @@ -1619,6 +1619,18 @@ nvidia,sys-clock-req-active-high; }; + /* Serial ATA */ + sata@0,70020000 { + status = "okay"; + + hvdd-supply = <&vdd_3v3_lp0>; + vddio-supply = <&vdd_1v05_run>; + avdd-supply = <&vdd_1v05_run>; + + target-5v-supply = <&vdd_5v0_sata>; + target-12v-supply = <&vdd_12v0_sata>; + }; + padctl@0,7009f000 { pinctrl-0 = <&padctl_default>; pinctrl-names = "default"; @@ -1828,6 +1840,29 @@ enable-active-high; vin-supply = <&vdd_5v0_sys>; }; + + /* Molex power connector */ + vdd_5v0_sata: regulator@13 { + compatible = "regulator-fixed"; + reg = <13>; + regulator-name = "+5V_SATA"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA_GPIO(EE, 2) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_5v0_sys>; + }; + + vdd_12v0_sata: regulator@14 { + compatible = "regulator-fixed"; + reg = <14>; + regulator-name = "+12V_SATA"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + gpio = <&gpio TEGRA_GPIO(EE, 2) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_mux>; + }; }; sound { -- cgit v0.10.2 From b0da12d59d9432aed9f2ae04d6baa8a0e9bc384c Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Fri, 22 Aug 2014 15:07:13 -0600 Subject: ARM: tegra: add PCIe-related pins to the Jetson TK1 pinmux tables This pinmux tables currently omit any configuration for PCIe clk_req, wake, and rst pins, which in turn causes intermittent failures in U-Boot's PCIe support. Import an updated version of the pinmux tables which rectifies this. (While I'm still hoping to remove the pinmux tables from DTs for Tegra124+ devices, while they're still here, they may as well be complete and correct). Signed-off-by: Stephen Warren diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1.dts b/arch/arm/boot/dts/tegra124-jetson-tk1.dts index ef578a7..3ea4153 100644 --- a/arch/arm/boot/dts/tegra124-jetson-tk1.dts +++ b/arch/arm/boot/dts/tegra124-jetson-tk1.dts @@ -1231,6 +1231,41 @@ nvidia,tristate = ; nvidia,enable-input = ; }; + pex_l0_rst_n_pdd1 { + nvidia,pins = "pex_l0_rst_n_pdd1"; + nvidia,function = "pe0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pex_l0_clkreq_n_pdd2 { + nvidia,pins = "pex_l0_clkreq_n_pdd2"; + nvidia,function = "pe0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pex_wake_n_pdd3 { + nvidia,pins = "pex_wake_n_pdd3"; + nvidia,function = "pe"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pex_l1_rst_n_pdd5 { + nvidia,pins = "pex_l1_rst_n_pdd5"; + nvidia,function = "pe1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pex_l1_clkreq_n_pdd6 { + nvidia,pins = "pex_l1_clkreq_n_pdd6"; + nvidia,function = "pe1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; clk3_out_pee0 { nvidia,pins = "clk3_out_pee0"; nvidia,function = "extperiph3"; -- cgit v0.10.2 From b10231344f64352bcfc1112b4d33c53e0a63fbcc Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 26 Aug 2014 08:14:03 +0200 Subject: ARM: tegra: Add device tree nodes for flow controller These nodes are required so that the flow controller driver can obtain the I/O memory region from device tree rather than hard-coding it. Signed-off-by: Thierry Reding Signed-off-by: Stephen Warren diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi index 80b8edd..2ca9c18 100644 --- a/arch/arm/boot/dts/tegra114.dtsi +++ b/arch/arm/boot/dts/tegra114.dtsi @@ -157,6 +157,11 @@ #reset-cells = <1>; }; + flow-controller@60007000 { + compatible = "nvidia,tegra114-flowctrl"; + reg = <0x60007000 0x1000>; + }; + apbdma: dma@6000a000 { compatible = "nvidia,tegra114-apbdma"; reg = <0x6000a000 0x1400>; diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index 727d395..a6e4814 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -137,6 +137,11 @@ #reset-cells = <1>; }; + flow-controller@0,60007000 { + compatible = "nvidia,tegra124-flowctrl"; + reg = <0x0 0x60007000 0x0 0x1000>; + }; + gpio: gpio@0,6000d000 { compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio"; reg = <0x0 0x6000d000 0x0 0x1000>; diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index 1908f69..3b374c4 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -190,6 +190,11 @@ #reset-cells = <1>; }; + flow-controller@60007000 { + compatible = "nvidia,tegra20-flowctrl"; + reg = <0x60007000 0x1000>; + }; + apbdma: dma@6000a000 { compatible = "nvidia,tegra20-apbdma"; reg = <0x6000a000 0x1200>; diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index 6b35c29..aa6ccea 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi @@ -272,6 +272,11 @@ #reset-cells = <1>; }; + flow-controller@60007000 { + compatible = "nvidia,tegra30-flowctrl"; + reg = <0x60007000 0x1000>; + }; + apbdma: dma@6000a000 { compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma"; reg = <0x6000a000 0x1400>; -- cgit v0.10.2 From a71b4438af8242f383906071205db95a8b8e7b6d Mon Sep 17 00:00:00 2001 From: FUKAUMI Naoki Date: Wed, 20 Aug 2014 14:25:03 +0900 Subject: ARM: sun7i: Add support for Olimex A20-OLinuXino-LIME This patch adds support for Olimex A20-OLinuXino-LIME board. Signed-off-by: FUKAUMI Naoki Signed-off-by: Maxime Ripard diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index c72f653..ecb55a3 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -418,6 +418,7 @@ dtb-$(CONFIG_MACH_SUN7I) += \ sun7i-a20-cubietruck.dtb \ sun7i-a20-hummingbird.dtb \ sun7i-a20-i12-tvbox.dtb \ + sun7i-a20-olinuxino-lime.dtb \ sun7i-a20-olinuxino-micro.dtb \ sun7i-a20-pcduino3.dtb dtb-$(CONFIG_MACH_SUN8I) += \ diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts new file mode 100644 index 0000000..1eb8175 --- /dev/null +++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts @@ -0,0 +1,137 @@ +/* + * This is based on sun4i-a10-olinuxino-lime.dts + * + * Copyright 2014 - Hans de Goede + * Copyright (c) 2014 FUKAUMI Naoki + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +/include/ "sun7i-a20.dtsi" +/include/ "sunxi-common-regulators.dtsi" + +/ { + model = "Olimex A20-OLinuXino-LIME"; + compatible = "olimex,a20-olinuxino-lime", "allwinner,sun7i-a20"; + + soc@01c00000 { + mmc0: mmc@01c0f000 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 7 1 0>; /* PH1 */ + cd-inverted; + status = "okay"; + }; + + usbphy: phy@01c13400 { + usb1_vbus-supply = <®_usb1_vbus>; + usb2_vbus-supply = <®_usb2_vbus>; + status = "okay"; + }; + + ehci0: usb@01c14000 { + status = "okay"; + }; + + ohci0: usb@01c14400 { + status = "okay"; + }; + + ahci: sata@01c18000 { + target-supply = <®_ahci_5v>; + status = "okay"; + }; + + ehci1: usb@01c1c000 { + status = "okay"; + }; + + ohci1: usb@01c1c400 { + status = "okay"; + }; + + pinctrl@01c20800 { + ahci_pwr_pin_olinuxinolime: ahci_pwr_pin@1 { + allwinner,pins = "PC3"; + allwinner,function = "gpio_out"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + + led_pins_olinuxinolime: led_pins@0 { + allwinner,pins = "PH2"; + allwinner,function = "gpio_out"; + allwinner,drive = <1>; + allwinner,pull = <0>; + }; + }; + + uart0: serial@01c28000 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; + }; + + i2c0: i2c@01c2ac00 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "okay"; + + axp209: pmic@34 { + compatible = "x-powers,axp209"; + reg = <0x34>; + interrupt-parent = <&nmi_intc>; + interrupts = <0 8>; + + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + gmac: ethernet@01c50000 { + pinctrl-names = "default"; + pinctrl-0 = <&gmac_pins_mii_a>; + phy = <&phy1>; + phy-mode = "mii"; + status = "okay"; + + phy1: ethernet-phy@1 { + reg = <1>; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pins_olinuxinolime>; + + green { + label = "a20-olinuxino-lime:green:usr"; + gpios = <&pio 7 2 0>; + default-state = "on"; + }; + }; + + reg_ahci_5v: ahci-5v { + pinctrl-0 = <&ahci_pwr_pin_olinuxinolime>; + gpio = <&pio 2 3 0>; + status = "okay"; + }; + + reg_usb1_vbus: usb1-vbus { + status = "okay"; + }; + + reg_usb2_vbus: usb2-vbus { + status = "okay"; + }; +}; -- cgit v0.10.2 From df542df3f572af7e5f8279e78d86614483d9670d Mon Sep 17 00:00:00 2001 From: Doug Anderson Date: Mon, 25 Aug 2014 15:59:26 -0700 Subject: ARM: dts: Add main PWM info to rk3288 This adds the PWM info (other than the VOP PWM) to the main rk3288 dtsi file. Signed-off-by: Caesar Wang Signed-off-by: Doug Anderson Signed-off-by: Heiko Stuebner diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index 36be7bb..7342b24 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -261,6 +261,50 @@ status = "disabled"; }; + pwm0: pwm@ff680000 { + compatible = "rockchip,rk3288-pwm"; + reg = <0xff680000 0x10>; + #pwm-cells = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_pin>; + clocks = <&cru PCLK_PWM>; + clock-names = "pwm"; + status = "disabled"; + }; + + pwm1: pwm@ff680010 { + compatible = "rockchip,rk3288-pwm"; + reg = <0xff680010 0x10>; + #pwm-cells = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm1_pin>; + clocks = <&cru PCLK_PWM>; + clock-names = "pwm"; + status = "disabled"; + }; + + pwm2: pwm@ff680020 { + compatible = "rockchip,rk3288-pwm"; + reg = <0xff680020 0x10>; + #pwm-cells = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm2_pin>; + clocks = <&cru PCLK_PWM>; + clock-names = "pwm"; + status = "disabled"; + }; + + pwm3: pwm@ff680030 { + compatible = "rockchip,rk3288-pwm"; + reg = <0xff680030 0x10>; + #pwm-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm3_pin>; + clocks = <&cru PCLK_PWM>; + clock-names = "pwm"; + status = "disabled"; + }; + pmu: power-management@ff730000 { compatible = "rockchip,rk3288-pmu", "syscon"; reg = <0xff730000 0x100>; @@ -611,5 +655,29 @@ rockchip,pins = <5 15 3 &pcfg_pull_none>; }; }; + + pwm0 { + pwm0_pin: pwm0-pin { + rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + pwm1 { + pwm1_pin: pwm1-pin { + rockchip,pins = <7 1 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + pwm2 { + pwm2_pin: pwm2-pin { + rockchip,pins = <7 22 3 &pcfg_pull_none>; + }; + }; + + pwm3 { + pwm3_pin: pwm3-pin { + rockchip,pins = <7 23 3 &pcfg_pull_none>; + }; + }; }; }; -- cgit v0.10.2 From 0541f94fdff89fb7bc14bf5fe0da21d9d19a0c6d Mon Sep 17 00:00:00 2001 From: Doug Anderson Date: Mon, 25 Aug 2014 15:59:27 -0700 Subject: ARM: dts: Enable PWM backlight on rk3288-evb PWM0 is the PWM associated with the LCD backlight. Enable it. Signed-off-by: Doug Anderson Signed-off-by: Heiko Stuebner diff --git a/arch/arm/boot/dts/rk3288-evb.dtsi b/arch/arm/boot/dts/rk3288-evb.dtsi index 2964370..98b69d0 100644 --- a/arch/arm/boot/dts/rk3288-evb.dtsi +++ b/arch/arm/boot/dts/rk3288-evb.dtsi @@ -10,6 +10,7 @@ * GNU General Public License for more details. */ +#include #include "rk3288.dtsi" / { @@ -17,6 +18,48 @@ reg = <0x0 0x80000000>; }; + backlight { + compatible = "pwm-backlight"; + brightness-levels = < + 0 1 2 3 4 5 6 7 + 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 + 24 25 26 27 28 29 30 31 + 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255>; + default-brightness-level = <128>; + enable-gpios = <&gpio7 2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&bl_en>; + pwms = <&pwm0 0 1000000 PWM_POLARITY_INVERTED>; + }; + gpio-keys { compatible = "gpio-keys"; #address-cells = <1>; @@ -81,6 +124,10 @@ status = "okay"; }; +&pwm0 { + status = "okay"; +}; + &uart0 { status = "okay"; }; @@ -102,6 +149,12 @@ }; &pinctrl { + backlight { + bl_en: bl-en { + rockchip,pins = <7 2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + buttons { pwrbtn: pwrbtn { rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>; -- cgit v0.10.2 From 4721ab855d1a1d3e472ff38d1cae06e23e0520cf Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Heiko=20St=C3=BCbner?= Date: Wed, 20 Aug 2014 21:07:22 +0200 Subject: ARM: dts: rockchip: add hym8563 rtc to Radxa Rock board The Radxa Rock uses a hym8563 as rtc. Add the i2c device and necessary pinconfig for the interrupt pin - labeled rtc_int in the schematics. Signed-off-by: Heiko Stuebner diff --git a/arch/arm/boot/dts/rk3188-radxarock.dts b/arch/arm/boot/dts/rk3188-radxarock.dts index ef72faf..ff35acfa 100644 --- a/arch/arm/boot/dts/rk3188-radxarock.dts +++ b/arch/arm/boot/dts/rk3188-radxarock.dts @@ -80,6 +80,17 @@ status = "okay"; clock-frequency = <400000>; + rtc@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + interrupt-parent = <&gpio0>; + interrupts = <13 IRQ_TYPE_EDGE_FALLING>; + pinctrl-names = "default"; + pinctrl-0 = <&rtc_int>; + #clock-cells = <0>; + clock-output-names = "xin32k"; + }; + act8846: act8846@5a { compatible = "active-semi,act8846"; reg = <0x5a>; @@ -196,6 +207,12 @@ }; }; + hym8563 { + rtc_int: rtc-int { + rockchip,pins = ; + }; + }; + ir-receiver { ir_recv_pin: ir-recv-pin { rockchip,pins = ; -- cgit v0.10.2 From f23a6179d45e9d144bf2eb2bd82b2f1270f85fcf Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Heiko=20St=C3=BCbner?= Date: Wed, 20 Aug 2014 21:09:24 +0200 Subject: ARM: dts: rockchip: add saradc nodes Add the core device nodes for the SARADC found on both the Cortex-A9 series (rk3066 and rk3188) as well as the newer rk3288. Signed-off-by: Heiko Stuebner diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index 7342b24..9eda097 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -98,6 +98,16 @@ status = "disabled"; }; + saradc: saradc@ff100000 { + compatible = "rockchip,saradc"; + reg = <0xff100000 0x100>; + interrupts = ; + #io-channel-cells = <1>; + clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; + clock-names = "saradc", "apb_pclk"; + status = "disabled"; + }; + i2c1: i2c@ff140000 { compatible = "rockchip,rk3288-i2c"; reg = <0xff140000 0x1000>; diff --git a/arch/arm/boot/dts/rk3xxx.dtsi b/arch/arm/boot/dts/rk3xxx.dtsi index 8caf85d..cce4a07 100644 --- a/arch/arm/boot/dts/rk3xxx.dtsi +++ b/arch/arm/boot/dts/rk3xxx.dtsi @@ -264,4 +264,14 @@ clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; status = "disabled"; }; + + saradc: saradc@2006c000 { + compatible = "rockchip,saradc"; + reg = <0x2006c000 0x100>; + interrupts = ; + #io-channel-cells = <1>; + clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; + clock-names = "saradc", "apb_pclk"; + status = "disabled"; + }; }; -- cgit v0.10.2 From ba2b7d0ad59f4e3fb2619f840b8e89060ab5dc61 Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Wed, 6 Aug 2014 16:31:27 -0500 Subject: MAINTAINERS: update entries for ARM/SOCFPGA platform Update email address, add W and T entries. Signed-off-by: Dinh Nguyen diff --git a/MAINTAINERS b/MAINTAINERS index 1ff06de..dd19acd 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1367,12 +1367,15 @@ F: arch/arm/mach-shmobile/ F: drivers/sh/ ARM/SOCFPGA ARCHITECTURE -M: Dinh Nguyen +M: Dinh Nguyen S: Maintained F: arch/arm/mach-socfpga/ +W: http://www.rocketboards.org +T: git://git.rocketboards.org/linux-socfpga.git +T: git://git.rocketboards.org/linux-socfpga-next.git ARM/SOCFPGA CLOCK FRAMEWORK SUPPORT -M: Dinh Nguyen +M: Dinh Nguyen S: Maintained F: drivers/clk/socfpga/ -- cgit v0.10.2 From bd597f47ca4bf7a522a0298a95c7f9b2f0a75b9e Mon Sep 17 00:00:00 2001 From: Steve Twiss Date: Fri, 22 Aug 2014 15:26:55 +0100 Subject: devicetree: Dialog Semiconductor consolidate existing vendor prefixes to standardise on 'dlg' This patch series updates the device tree vendor prefix for Dialog Semiconductor. Various methods are currently used throughout the kernel: 'diasemi', 'dialog' and 'dlg'. Others have also been suggested. This patch set aims to consolidate the usage of the vendor prefix to use a common standard. The prefix 'dlg' is used. Signed-off-by: Steve Twiss Acked-by: Simon Horman Acked-by: Rob Herring Acked-by: Lee Jones Acked-by: Shawn Guo Signed-off-by: Lee Jones diff --git a/Documentation/devicetree/bindings/i2c/trivial-devices.txt b/Documentation/devicetree/bindings/i2c/trivial-devices.txt index 6af570e..5af3d9d 100644 --- a/Documentation/devicetree/bindings/i2c/trivial-devices.txt +++ b/Documentation/devicetree/bindings/i2c/trivial-devices.txt @@ -44,7 +44,7 @@ dallas,ds1775 Tiny Digital Thermometer and Thermostat dallas,ds3232 Extremely Accurate I²C RTC with Integrated Crystal and SRAM dallas,ds4510 CPU Supervisor with Nonvolatile Memory and Programmable I/O dallas,ds75 Digital Thermometer and Thermostat -dialog,da9053 DA9053: flexible system level PMIC with multicore support +dlg,da9053 DA9053: flexible system level PMIC with multicore support epson,rx8025 High-Stability. I2C-Bus INTERFACE REAL TIME CLOCK MODULE epson,rx8581 I2C-BUS INTERFACE REAL TIME CLOCK MODULE fsl,mag3110 MAG3110: Xtrinsic High Accuracy, 3D Magnetometer diff --git a/Documentation/devicetree/bindings/regulator/da9210.txt b/Documentation/devicetree/bindings/regulator/da9210.txt index f120f22..3297c53 100644 --- a/Documentation/devicetree/bindings/regulator/da9210.txt +++ b/Documentation/devicetree/bindings/regulator/da9210.txt @@ -2,7 +2,7 @@ Required properties: -- compatible: must be "diasemi,da9210" +- compatible: must be "dlg,da9210" - reg: the i2c slave address of the regulator. It should be 0x68. Any standard regulator properties can be used to configure the single da9210 @@ -11,7 +11,7 @@ DCDC. Example: da9210@68 { - compatible = "diasemi,da9210"; + compatible = "dlg,da9210"; reg = <0x68>; regulator-min-microvolt = <900000>; diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index ac7269f..f4318d7 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -38,6 +38,7 @@ dallas Maxim Integrated Products (formerly Dallas Semiconductor) davicom DAVICOM Semiconductor, Inc. denx Denx Software Engineering digi Digi International Inc. +dlg Dialog Semiconductor dlink D-Link Corporation dmo Data Modul AG ebv EBV Elektronik diff --git a/arch/arm/boot/dts/imx53-smd.dts b/arch/arm/boot/dts/imx53-smd.dts index 5ec1590..1d32557 100644 --- a/arch/arm/boot/dts/imx53-smd.dts +++ b/arch/arm/boot/dts/imx53-smd.dts @@ -265,7 +265,7 @@ }; pmic: dialog@48 { - compatible = "dialog,da9053", "dialog,da9052"; + compatible = "dlg,da9053", "dlg,da9052"; reg = <0x48>; }; }; diff --git a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi index 2694aa8..0e50bb0 100644 --- a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi +++ b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi @@ -83,7 +83,7 @@ }; pmic@58 { - compatible = "dialog,da9063"; + compatible = "dlg,da9063"; reg = <0x58>; interrupt-parent = <&gpio4>; interrupts = <17 0x8>; /* active-low GPIO4_17 */ diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts index 856b423..e3db105 100644 --- a/arch/arm/boot/dts/r8a7790-lager.dts +++ b/arch/arm/boot/dts/r8a7790-lager.dts @@ -374,7 +374,7 @@ status = "okay"; vdd_dvfs: regulator@68 { - compatible = "diasemi,da9210"; + compatible = "dlg,da9210"; reg = <0x68>; regulator-min-microvolt = <1000000>; diff --git a/arch/arm/boot/dts/r8a7791-koelsch.dts b/arch/arm/boot/dts/r8a7791-koelsch.dts index be59014..be29711 100644 --- a/arch/arm/boot/dts/r8a7791-koelsch.dts +++ b/arch/arm/boot/dts/r8a7791-koelsch.dts @@ -419,7 +419,7 @@ clock-frequency = <100000>; vdd_dvfs: regulator@68 { - compatible = "diasemi,da9210"; + compatible = "dlg,da9210"; reg = <0x68>; regulator-min-microvolt = <1000000>; diff --git a/drivers/mfd/da9055-core.c b/drivers/mfd/da9055-core.c index caf8dcf..b4d920c 100644 --- a/drivers/mfd/da9055-core.c +++ b/drivers/mfd/da9055-core.c @@ -296,73 +296,73 @@ static struct resource da9055_ld05_6_resource = { static const struct mfd_cell da9055_devs[] = { { - .of_compatible = "dialog,da9055-gpio", + .of_compatible = "dlg,da9055-gpio", .name = "da9055-gpio", }, { - .of_compatible = "dialog,da9055-regulator", + .of_compatible = "dlg,da9055-regulator", .name = "da9055-regulator", .id = 1, }, { - .of_compatible = "dialog,da9055-regulator", + .of_compatible = "dlg,da9055-regulator", .name = "da9055-regulator", .id = 2, }, { - .of_compatible = "dialog,da9055-regulator", + .of_compatible = "dlg,da9055-regulator", .name = "da9055-regulator", .id = 3, }, { - .of_compatible = "dialog,da9055-regulator", + .of_compatible = "dlg,da9055-regulator", .name = "da9055-regulator", .id = 4, }, { - .of_compatible = "dialog,da9055-regulator", + .of_compatible = "dlg,da9055-regulator", .name = "da9055-regulator", .id = 5, }, { - .of_compatible = "dialog,da9055-regulator", + .of_compatible = "dlg,da9055-regulator", .name = "da9055-regulator", .id = 6, }, { - .of_compatible = "dialog,da9055-regulator", + .of_compatible = "dlg,da9055-regulator", .name = "da9055-regulator", .id = 7, .resources = &da9055_ld05_6_resource, .num_resources = 1, }, { - .of_compatible = "dialog,da9055-regulator", + .of_compatible = "dlg,da9055-regulator", .name = "da9055-regulator", .resources = &da9055_ld05_6_resource, .num_resources = 1, .id = 8, }, { - .of_compatible = "dialog,da9055-onkey", + .of_compatible = "dlg,da9055-onkey", .name = "da9055-onkey", .resources = &da9055_onkey_resource, .num_resources = 1, }, { - .of_compatible = "dialog,da9055-rtc", + .of_compatible = "dlg,da9055-rtc", .name = "da9055-rtc", .resources = da9055_rtc_resource, .num_resources = ARRAY_SIZE(da9055_rtc_resource), }, { - .of_compatible = "dialog,da9055-hwmon", + .of_compatible = "dlg,da9055-hwmon", .name = "da9055-hwmon", .resources = &da9055_hwmon_resource, .num_resources = 1, }, { - .of_compatible = "dialog,da9055-watchdog", + .of_compatible = "dlg,da9055-watchdog", .name = "da9055-watchdog", }, }; -- cgit v0.10.2 From 4d50e6dd7a019993504a419d0057051788e477f1 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 28 Aug 2014 10:20:40 +0200 Subject: ARM: shmobile: r8a7779 dtsi: Add SoC-specific thermal compatible property The thermal node used the generic compatible property only. Add the SoC-specific one, to make it future proof. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi index 0e64c76..b749101 100644 --- a/arch/arm/boot/dts/r8a7779.dtsi +++ b/arch/arm/boot/dts/r8a7779.dtsi @@ -256,7 +256,7 @@ }; thermal@ffc48000 { - compatible = "renesas,rcar-thermal"; + compatible = "renesas,thermal-r8a7779", "renesas,rcar-thermal"; reg = <0xffc48000 0x38>; }; -- cgit v0.10.2 From a2cfaa7458e714aa00be98c630afaa1a4766e2ad Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 28 Aug 2014 10:20:39 +0200 Subject: ARM: shmobile: r8a73a4 dtsi: Add SoC-specific thermal compatible property The thermal node used the generic compatible property only. Add the SoC-specific one, to make it future proof. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman diff --git a/arch/arm/boot/dts/r8a73a4.dtsi b/arch/arm/boot/dts/r8a73a4.dtsi index d8ec505..fba39a2 100644 --- a/arch/arm/boot/dts/r8a73a4.dtsi +++ b/arch/arm/boot/dts/r8a73a4.dtsi @@ -165,7 +165,7 @@ }; thermal@e61f0000 { - compatible = "renesas,rcar-thermal"; + compatible = "renesas,thermal-r8a73a4", "renesas,rcar-thermal"; reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>, <0 0xe61f0200 0 0x38>, <0 0xe61f0300 0 0x38>; interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>; -- cgit v0.10.2 From d2c2a0776899ba2d9d560815d0bcab486b8e64ab Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 28 Aug 2014 10:05:20 +0200 Subject: ARM: shmobile: Add platform device tree bindings documentation Add Renesas SH-Mobile, R-Mobile, and R-Car Platform Device Tree Bindings Documentation, listing supported SoCs and boards. This allows to use checkpatch to validate DTSes referring to Renesas shmobile SoCs, and boards containing those SoCs. Signed-off-by: Geert Uytterhoeven [horms+renesas@verge.net.au: tweaked title] Signed-off-by: Simon Horman diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt b/Documentation/devicetree/bindings/arm/shmobile.txt new file mode 100644 index 0000000..5d1c5c0 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/shmobile.txt @@ -0,0 +1,71 @@ +Renesas SH-Mobile, R-Mobile, and R-Car Platform Device Tree Bindings +-------------------------------------------------------------------- + +SoCs: + + - Emma Mobile EV2 + compatible = "renesas,emev2" + - RZ/A1H (R7S72100) + compatible = "renesas,r7s72100" + - SH-Mobile AP4 (R8A73720/SH7372) + compatible = "renesas,sh7372" + - SH-Mobile AG5 (R8A73A00/SH73A0) + compatible = "renesas,sh73a0" + - R-Mobile APE6 (R8A73A40) + compatible = "renesas,r8a73a4" + - R-Mobile A1 (R8A77400) + compatible = "renesas,r8a7740" + - R-Car M1A (R8A77781) + compatible = "renesas,r8a7778" + - R-Car H1 (R8A77790) + compatible = "renesas,r8a7779" + - R-Car H2 (R8A77900) + compatible = "renesas,r8a7790" + - R-Car M2-W (R8A77910) + compatible = "renesas,r8a7791" + - R-Car V2H (R8A77920) + compatible = "renesas,r8a7792" + - R-Car M2-N (R8A77930) + compatible = "renesas,r8a7793" + - R-Car E2 (R8A77940) + compatible = "renesas,r8a7794" + + +Boards: + + - Alt + compatible = "renesas,alt", "renesas,r8a7794" + - APE6-EVM + compatible = "renesas,ape6evm", "renesas,r8a73a4" + - APE6-EVM - Reference Device Tree Implementation + compatible = "renesas,ape6evm-reference", "renesas,r8a73a4" + - Atmark Techno Armadillo-800 EVA + compatible = "renesas,armadillo800eva" + - BOCK-W + compatible = "renesas,bockw", "renesas,r8a7778" + - BOCK-W - Reference Device Tree Implementation + compatible = "renesas,bockw-reference", "renesas,r8a7778" + - Genmai (RTK772100BC00000BR) + compatible = "renesas,genmai", "renesas,r7s72100" + - Gose + compatible = "renesas,gose", "renesas,r8a7793" + - Henninger + compatible = "renesas,henninger", "renesas,r8a7791" + - Koelsch (RTP0RC7791SEB00010S) + compatible = "renesas,koelsch", "renesas,r8a7791" + - KZM9D + compatible = "renesas,kzm9d", "renesas,emev2" + - KZM-A9-GT + compatible = "renesas,kzm9g", "renesas,sh73a0" + - KZM-A9-GT - Reference Device Tree Implementation + compatible = "renesas,kzm9g-reference", "renesas,sh73a0" + - Lager (RTP0RC7790SEB00010S) + compatible = "renesas,lager", "renesas,r8a7790" + - Mackerel (R0P7372LC0016RL, AP4 EVM 2nd) + compatible = "renesas,mackerel" + - Marzen + compatible = "renesas,marzen", "renesas,r8a7779" + +Note: Reference Device Tree Implementations are temporary implementations + to ease the migration from platform devices to Device Tree, and are + intended to be removed in the future. -- cgit v0.10.2 From 74d90de2d0c20162d247cb2f9896e1aa7df98616 Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Tue, 22 Jul 2014 16:07:47 +0200 Subject: ARM: at91/dt: sam9x5: fix ADC compatible string Use the correct compatible string for the ADC of the at91sam9x5 family of SoCs. Signed-off-by: Alexandre Belloni Signed-off-by: Nicolas Ferre diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi index 765a1e3..726274f 100644 --- a/arch/arm/boot/dts/at91sam9x5.dtsi +++ b/arch/arm/boot/dts/at91sam9x5.dtsi @@ -968,7 +968,7 @@ adc0: adc@f804c000 { #address-cells = <1>; #size-cells = <0>; - compatible = "atmel,at91sam9260-adc"; + compatible = "atmel,at91sam9x5-adc"; reg = <0xf804c000 0x100>; interrupts = <19 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&adc_clk>, -- cgit v0.10.2 From 2fbda374a2add291bce8036c5084f955bbef7a94 Mon Sep 17 00:00:00 2001 From: Bo Shen Date: Wed, 27 Aug 2014 17:52:49 +0800 Subject: ARM: at91/dt: sam9n12ek: ohci: add port and vbus property Add the port number and vbus property for ohci port, or else if bootloader won't configure the vbus pin, the 5v supply is not power on, so can not work with usb devices. Signed-off-by: Bo Shen Signed-off-by: Nicolas Ferre diff --git a/arch/arm/boot/dts/at91sam9n12ek.dts b/arch/arm/boot/dts/at91sam9n12ek.dts index 83d7237..13bb24e 100644 --- a/arch/arm/boot/dts/at91sam9n12ek.dts +++ b/arch/arm/boot/dts/at91sam9n12ek.dts @@ -136,6 +136,8 @@ }; usb0: ohci@00500000 { + num-ports = <1>; + atmel,vbus-gpio = <&pioB 7 GPIO_ACTIVE_LOW>; status = "okay"; }; }; -- cgit v0.10.2 From f8aa6867a2365fa98de6932cce420d6106a5ddd1 Mon Sep 17 00:00:00 2001 From: Ezra Savard Date: Fri, 29 Aug 2014 07:38:37 -0700 Subject: ARM: zynq: DT: Add LEDs to zc702 DT Adds LEDs to the zc702 devicetree for use with the leds-gpio driver. Signed-off-by: Ezra Savard Reviewed-by: Soren Brinkmann Signed-off-by: Michal Simek diff --git a/arch/arm/boot/dts/zynq-zc702.dts b/arch/arm/boot/dts/zynq-zc702.dts index 835c308..b29e0f9 100644 --- a/arch/arm/boot/dts/zynq-zc702.dts +++ b/arch/arm/boot/dts/zynq-zc702.dts @@ -27,6 +27,15 @@ bootargs = "console=ttyPS0,115200 earlyprintk"; }; + leds { + compatible = "gpio-leds"; + + ds23 { + label = "ds23"; + gpios = <&gpio0 10 0>; + linux,default-trigger = "heartbeat"; + }; + }; }; &can0 { -- cgit v0.10.2 From da45581ea825d53a459a90deb48a50b99369502b Mon Sep 17 00:00:00 2001 From: Soren Brinkmann Date: Wed, 20 Aug 2014 08:56:57 -0700 Subject: ARM: zynq: DT: Fix Ethernet phy modes The used PHYs should be qualified as 'rgmii-id' instead of just 'rgmii'. For the Zed board this seems to make a difference between working and broken Ethernet. Signed-off-by: Soren Brinkmann Signed-off-by: Michal Simek diff --git a/arch/arm/boot/dts/zynq-zc702.dts b/arch/arm/boot/dts/zynq-zc702.dts index b29e0f9..1a50f9f 100644 --- a/arch/arm/boot/dts/zynq-zc702.dts +++ b/arch/arm/boot/dts/zynq-zc702.dts @@ -44,7 +44,7 @@ &gem0 { status = "okay"; - phy-mode = "rgmii"; + phy-mode = "rgmii-id"; }; &i2c0 { diff --git a/arch/arm/boot/dts/zynq-zc706.dts b/arch/arm/boot/dts/zynq-zc706.dts index 4cc9913..3d9cb02 100644 --- a/arch/arm/boot/dts/zynq-zc706.dts +++ b/arch/arm/boot/dts/zynq-zc706.dts @@ -32,7 +32,7 @@ &gem0 { status = "okay"; - phy-mode = "rgmii"; + phy-mode = "rgmii-id"; }; &i2c0 { diff --git a/arch/arm/boot/dts/zynq-zed.dts b/arch/arm/boot/dts/zynq-zed.dts index 82d7ef1..42deb1b 100644 --- a/arch/arm/boot/dts/zynq-zed.dts +++ b/arch/arm/boot/dts/zynq-zed.dts @@ -32,7 +32,7 @@ &gem0 { status = "okay"; - phy-mode = "rgmii"; + phy-mode = "rgmii-id"; }; &sdhci0 { -- cgit v0.10.2 From edbd35e70dd563f5e8062bed292a9900073fca48 Mon Sep 17 00:00:00 2001 From: Soren Brinkmann Date: Wed, 20 Aug 2014 08:56:58 -0700 Subject: ARM: zynq: DT: Move size/address properties to dtsi MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Move the GEM's size and address cells properties to the common dtsi file. Cc: Andreas Färber Signed-off-by: Soren Brinkmann Reviewed-by: Andreas Färber Signed-off-by: Michal Simek diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi index 6cc83d4..4e6e96e 100644 --- a/arch/arm/boot/dts/zynq-7000.dtsi +++ b/arch/arm/boot/dts/zynq-7000.dtsi @@ -195,6 +195,8 @@ interrupts = <0 22 4>; clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>; clock-names = "pclk", "hclk", "tx_clk"; + #address-cells = <1>; + #size-cells = <0>; }; gem1: ethernet@e000c000 { @@ -204,6 +206,8 @@ interrupts = <0 45 4>; clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>; clock-names = "pclk", "hclk", "tx_clk"; + #address-cells = <1>; + #size-cells = <0>; }; sdhci0: sdhci@e0100000 { diff --git a/arch/arm/boot/dts/zynq-parallella.dts b/arch/arm/boot/dts/zynq-parallella.dts index 41afd9d..690e620 100644 --- a/arch/arm/boot/dts/zynq-parallella.dts +++ b/arch/arm/boot/dts/zynq-parallella.dts @@ -38,8 +38,6 @@ status = "okay"; phy-mode = "rgmii-id"; phy-handle = <ðernet_phy>; - #address-cells = <1>; - #size-cells = <0>; ethernet_phy: ethernet-phy@0 { /* Marvell 88E1318 */ -- cgit v0.10.2 From aeb29453e38cc7a501c6dd98e160a7ddd781f12f Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 21 Aug 2014 11:19:46 +0200 Subject: ARM: zynq: DT: Update years in header Add this year to the header. Signed-off-by: Michal Simek diff --git a/arch/arm/boot/dts/zynq-zc702.dts b/arch/arm/boot/dts/zynq-zc702.dts index 1a50f9f..8eab484 100644 --- a/arch/arm/boot/dts/zynq-zc702.dts +++ b/arch/arm/boot/dts/zynq-zc702.dts @@ -1,5 +1,5 @@ /* - * Copyright (C) 2011 Xilinx + * Copyright (C) 2011 - 2014 Xilinx * Copyright (C) 2012 National Instruments Corp. * * This software is licensed under the terms of the GNU General Public diff --git a/arch/arm/boot/dts/zynq-zc706.dts b/arch/arm/boot/dts/zynq-zc706.dts index 3d9cb02..5efe200 100644 --- a/arch/arm/boot/dts/zynq-zc706.dts +++ b/arch/arm/boot/dts/zynq-zc706.dts @@ -1,7 +1,6 @@ /* - * Copyright (C) 2011 Xilinx + * Copyright (C) 2011 - 2014 Xilinx * Copyright (C) 2012 National Instruments Corp. - * Copyright (C) 2013 Xilinx * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and diff --git a/arch/arm/boot/dts/zynq-zed.dts b/arch/arm/boot/dts/zynq-zed.dts index 42deb1b..93d1ed1 100644 --- a/arch/arm/boot/dts/zynq-zed.dts +++ b/arch/arm/boot/dts/zynq-zed.dts @@ -1,7 +1,6 @@ /* - * Copyright (C) 2011 Xilinx + * Copyright (C) 2011 - 2014 Xilinx * Copyright (C) 2012 National Instruments Corp. - * Copyright (C) 2013 Xilinx * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and -- cgit v0.10.2 From b65186da8cb846b7bbea05304809638b1c8282fd Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 21 Aug 2014 11:21:09 +0200 Subject: ARM: zynq: DT: Use 0x prefix for memory nodes Be align with the rest of zynq DTS and have 0 written as 0x0. Signed-off-by: Michal Simek diff --git a/arch/arm/boot/dts/zynq-parallella.dts b/arch/arm/boot/dts/zynq-parallella.dts index 690e620..aadde02 100644 --- a/arch/arm/boot/dts/zynq-parallella.dts +++ b/arch/arm/boot/dts/zynq-parallella.dts @@ -25,7 +25,7 @@ memory { device_type = "memory"; - reg = <0 0x40000000>; + reg = <0x0 0x40000000>; }; chosen { diff --git a/arch/arm/boot/dts/zynq-zc706.dts b/arch/arm/boot/dts/zynq-zc706.dts index 5efe200..88f732f 100644 --- a/arch/arm/boot/dts/zynq-zc706.dts +++ b/arch/arm/boot/dts/zynq-zc706.dts @@ -20,7 +20,7 @@ memory { device_type = "memory"; - reg = <0 0x40000000>; + reg = <0x0 0x40000000>; }; chosen { diff --git a/arch/arm/boot/dts/zynq-zed.dts b/arch/arm/boot/dts/zynq-zed.dts index 93d1ed1..00eda36 100644 --- a/arch/arm/boot/dts/zynq-zed.dts +++ b/arch/arm/boot/dts/zynq-zed.dts @@ -20,7 +20,7 @@ memory { device_type = "memory"; - reg = <0 0x20000000>; + reg = <0x0 0x20000000>; }; chosen { -- cgit v0.10.2 From 357a454efde5686cb03fa25b8c5e9f8b60608e3b Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 21 Aug 2014 11:22:40 +0200 Subject: ARM: zynq: DT: Extend compatible string for zedboard Aling compatible property with others and have xlnx,zynq-zed in compatible list too. Signed-off-by: Michal Simek diff --git a/arch/arm/boot/dts/zynq-zed.dts b/arch/arm/boot/dts/zynq-zed.dts index 00eda36..2b2dc4d 100644 --- a/arch/arm/boot/dts/zynq-zed.dts +++ b/arch/arm/boot/dts/zynq-zed.dts @@ -16,7 +16,7 @@ / { model = "Zynq Zed Development Board"; - compatible = "xlnx,zynq-7000"; + compatible = "xlnx,zynq-zed", "xlnx,zynq-7000"; memory { device_type = "memory"; -- cgit v0.10.2 From 41683583126c7c5ca302b43e7b6295dc58dba779 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 21 Aug 2014 11:27:05 +0200 Subject: ARM: zynq: DT: Describe interrupt-names for pl330 Signed-off-by: Michal Simek diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi index 4e6e96e..5185a7c 100644 --- a/arch/arm/boot/dts/zynq-7000.dtsi +++ b/arch/arm/boot/dts/zynq-7000.dtsi @@ -260,6 +260,8 @@ compatible = "arm,pl330", "arm,primecell"; reg = <0xf8003000 0x1000>; interrupt-parent = <&intc>; + interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3", + "dma4", "dma5", "dma6", "dma7"; interrupts = <0 13 4>, <0 14 4>, <0 15 4>, <0 16 4>, <0 17 4>, -- cgit v0.10.2 From e65b15852a4ac11113d42e9f6e55af908a2b30ef Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 21 Aug 2014 12:45:05 +0200 Subject: ARM: zynq: DT: Fix coding style issues in dtsi Remove space before semicolon. sed -i 's/}\ ;/};/g' arch/arm/boot/dts/zynq-* Signed-off-by: Michal Simek diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi index 5185a7c..5e68c24 100644 --- a/arch/arm/boot/dts/zynq-7000.dtsi +++ b/arch/arm/boot/dts/zynq-7000.dtsi @@ -218,7 +218,7 @@ interrupt-parent = <&intc>; interrupts = <0 24 4>; reg = <0xe0100000 0x1000>; - } ; + }; sdhci1: sdhci@e0101000 { compatible = "arasan,sdhci-8.9a"; @@ -228,7 +228,7 @@ interrupt-parent = <&intc>; interrupts = <0 47 4>; reg = <0xe0101000 0x1000>; - } ; + }; slcr: slcr@f8000000 { #address-cells = <1>; @@ -277,7 +277,7 @@ devcfg: devcfg@f8007000 { compatible = "xlnx,zynq-devcfg-1.0"; reg = <0xf8007000 0x100>; - } ; + }; global_timer: timer@f8f00200 { compatible = "arm,cortex-a9-global-timer"; @@ -309,6 +309,6 @@ compatible = "arm,cortex-a9-twd-timer"; reg = <0xf8f00600 0x20>; clocks = <&clkc 4>; - } ; + }; }; }; -- cgit v0.10.2 From 71e8a328cb4893cdae88ab7653ede1b3d2605ad8 Mon Sep 17 00:00:00 2001 From: Boris BREZILLON Date: Thu, 10 Jul 2014 21:59:53 +0200 Subject: ARM: at91/dt: describe rgmii ethernet phy connected to sama5d3xek boards Add ethernet-phy nodes and specify phy interrupt (connected to pin PB25) and board specific timing configs. Atmel has two different HW designs for its CPU modules: the first one (produced by Embest) is connecting PHYAD[0-2] pins to pull up resistors and the other one (produced by Ronetix) is connecting PHYAD0 to a pull up resistor and PHYAD[1-2] to pull down resistors. As a result, Ronetix design will have its PHY available at address 0x1 and Embest design at 0x7. By defining both phys we're letting the phy core detect the one actually available on the MDIO bus. Signed-off-by: Boris BREZILLON Tested-by: Bo Shen Acked-by: Florian Fainelli Signed-off-by: Nicolas Ferre diff --git a/arch/arm/boot/dts/sama5d3xcm.dtsi b/arch/arm/boot/dts/sama5d3xcm.dtsi index f7d8583..962dc28 100644 --- a/arch/arm/boot/dts/sama5d3xcm.dtsi +++ b/arch/arm/boot/dts/sama5d3xcm.dtsi @@ -36,6 +36,36 @@ macb0: ethernet@f0028000 { phy-mode = "rgmii"; + #address-cells = <1>; + #size-cells = <0>; + + ethernet-phy@1 { + reg = <0x1>; + interrupt-parent = <&pioB>; + interrupts = <25 IRQ_TYPE_EDGE_FALLING>; + txen-skew-ps = <800>; + txc-skew-ps = <3000>; + rxdv-skew-ps = <400>; + rxc-skew-ps = <3000>; + rxd0-skew-ps = <400>; + rxd1-skew-ps = <400>; + rxd2-skew-ps = <400>; + rxd3-skew-ps = <400>; + }; + + ethernet-phy@7 { + reg = <0x7>; + interrupt-parent = <&pioB>; + interrupts = <25 IRQ_TYPE_EDGE_FALLING>; + txen-skew-ps = <800>; + txc-skew-ps = <3000>; + rxdv-skew-ps = <400>; + rxc-skew-ps = <3000>; + rxd0-skew-ps = <400>; + rxd1-skew-ps = <400>; + rxd2-skew-ps = <400>; + rxd3-skew-ps = <400>; + }; }; pmc: pmc@fffffc00 { -- cgit v0.10.2 From 5f8157309624929e05ece846d3ca8a3a64988378 Mon Sep 17 00:00:00 2001 From: Boris BREZILLON Date: Thu, 10 Jul 2014 21:59:54 +0200 Subject: ARM: at91: remove phy fixup for sama5d3xek boards These board specific delays are now configured through micrel's specific DT bindings (see Documentation/devicetree/bindings/net/micrel-ksz9021.txt). Remove this phy fixup registration from sama5 DT machine file to keep it as generic as possible. Signed-off-by: Boris BREZILLON Tested-by: Bo Shen Signed-off-by: Nicolas Ferre diff --git a/arch/arm/mach-at91/board-dt-sama5.c b/arch/arm/mach-at91/board-dt-sama5.c index 075ec05..70b2504 100644 --- a/arch/arm/mach-at91/board-dt-sama5.c +++ b/arch/arm/mach-at91/board-dt-sama5.c @@ -46,30 +46,8 @@ static void __init at91_dt_init_irq(void) of_irq_init(irq_of_match); } -static int ksz9021rn_phy_fixup(struct phy_device *phy) -{ - int value; - - /* Set delay values */ - value = MICREL_KSZ9021_RGMII_CLK_CTRL_PAD_SCEW | 0x8000; - phy_write(phy, MICREL_KSZ9021_EXTREG_CTRL, value); - value = 0xF2F4; - phy_write(phy, MICREL_KSZ9021_EXTREG_DATA_WRITE, value); - value = MICREL_KSZ9021_RGMII_RX_DATA_PAD_SCEW | 0x8000; - phy_write(phy, MICREL_KSZ9021_EXTREG_CTRL, value); - value = 0x2222; - phy_write(phy, MICREL_KSZ9021_EXTREG_DATA_WRITE, value); - - return 0; -} - static void __init sama5_dt_device_init(void) { - if (of_machine_is_compatible("atmel,sama5d3xcm") && - IS_ENABLED(CONFIG_PHYLIB)) - phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK, - ksz9021rn_phy_fixup); - of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); } -- cgit v0.10.2 From 99e544c782ba03855b9b6762b73915565065dbf8 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 28 Aug 2014 10:21:55 +0200 Subject: ARM: shmobile: r8a7779 dtsi: Use tabs for indentation Checkpatch says: ERROR: code indent should use tabs where possible Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi index b749101..05b68f4 100644 --- a/arch/arm/boot/dts/r8a7779.dtsi +++ b/arch/arm/boot/dts/r8a7779.dtsi @@ -398,10 +398,10 @@ /* Gate clocks */ mstp0_clks: clocks@ffc80030 { compatible = "renesas,r8a7779-mstp-clocks", - "renesas,cpg-mstp-clocks"; + "renesas,cpg-mstp-clocks"; reg = <0xffc80030 4>; clocks = <&cpg_clocks R8A7779_CLK_S>, - <&cpg_clocks R8A7779_CLK_P>, + <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_S>, @@ -435,7 +435,7 @@ }; mstp1_clks: clocks@ffc80034 { compatible = "renesas,r8a7779-mstp-clocks", - "renesas,cpg-mstp-clocks"; + "renesas,cpg-mstp-clocks"; reg = <0xffc80034 4>, <0xffc80044 4>; clocks = <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>, @@ -464,7 +464,7 @@ }; mstp3_clks: clocks@ffc8003c { compatible = "renesas,r8a7779-mstp-clocks", - "renesas,cpg-mstp-clocks"; + "renesas,cpg-mstp-clocks"; reg = <0xffc8003c 4>; clocks = <&s4_clk>, <&s4_clk>, <&s4_clk>, <&s4_clk>, <&s4_clk>, <&s4_clk>; -- cgit v0.10.2 From 40c488df84f9fbf4b84b4baed6e2cec4a2d946ed Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 28 Aug 2014 10:21:56 +0200 Subject: ARM: shmobile: kzm9g-reference dts: Use tabs for indentation Checkpatch says: ERROR: code indent should use tabs where possible Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman diff --git a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts index 18662ae..477f815 100644 --- a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts +++ b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts @@ -66,7 +66,7 @@ }; vmmc_sdhi0: regulator@2 { - compatible = "regulator-fixed"; + compatible = "regulator-fixed"; regulator-name = "SDHI0 Vcc"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; @@ -75,7 +75,7 @@ }; vmmc_sdhi2: regulator@3 { - compatible = "regulator-fixed"; + compatible = "regulator-fixed"; regulator-name = "SDHI2 Vcc"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; -- cgit v0.10.2 From d24cd78399a3625a69887c8124638260c1c37a2b Mon Sep 17 00:00:00 2001 From: Ludovic Desroches Date: Tue, 12 Aug 2014 16:37:57 +0200 Subject: ARM: at91: sama5d3: add usart dma configurations Add the DMA configuration for USARTs mainly because it is not obvious to add the FIFO flag which is needed for rx. Signed-off-by: Ludovic Desroches Signed-off-by: Nicolas Ferre diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi index 7702a0d..70a941f 100644 --- a/arch/arm/boot/dts/sama5d3.dtsi +++ b/arch/arm/boot/dts/sama5d3.dtsi @@ -177,6 +177,9 @@ compatible = "atmel,at91sam9260-usart"; reg = <0xf001c000 0x100>; interrupts = <12 IRQ_TYPE_LEVEL_HIGH 5>; + dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(3)>, + <&dma0 2 (AT91_DMA_CFG_PER_ID(4) | AT91_DMA_CFG_FIFOCFG_ASAP)>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart0>; clocks = <&usart0_clk>; @@ -188,6 +191,9 @@ compatible = "atmel,at91sam9260-usart"; reg = <0xf0020000 0x100>; interrupts = <13 IRQ_TYPE_LEVEL_HIGH 5>; + dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(5)>, + <&dma0 2 (AT91_DMA_CFG_PER_ID(6) | AT91_DMA_CFG_FIFOCFG_ASAP)>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart1>; clocks = <&usart1_clk>; @@ -333,6 +339,9 @@ compatible = "atmel,at91sam9260-usart"; reg = <0xf8020000 0x100>; interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>; + dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(7)>, + <&dma1 2 (AT91_DMA_CFG_PER_ID(8) | AT91_DMA_CFG_FIFOCFG_ASAP)>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart2>; clocks = <&usart2_clk>; @@ -344,6 +353,9 @@ compatible = "atmel,at91sam9260-usart"; reg = <0xf8024000 0x100>; interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>; + dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(9)>, + <&dma1 2 (AT91_DMA_CFG_PER_ID(10) | AT91_DMA_CFG_FIFOCFG_ASAP)>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart3>; clocks = <&usart3_clk>; @@ -412,6 +424,9 @@ compatible = "atmel,at91sam9260-usart"; reg = <0xffffee00 0x200>; interrupts = <2 IRQ_TYPE_LEVEL_HIGH 7>; + dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(13)>, + <&dma1 2 (AT91_DMA_CFG_PER_ID(14) | AT91_DMA_CFG_FIFOCFG_ASAP)>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_dbgu>; clocks = <&dbgu_clk>; -- cgit v0.10.2 From 34f137b1c2b864d495620e24dfc3ec75c9ca34df Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Heiko=20St=C3=BCbner?= Date: Thu, 14 Aug 2014 23:00:56 +0200 Subject: ARM: rockchip: enable the AMBA bus This is needed to access the pl330 dma controllers on Rockchip SoCs. Signed-off-by: Heiko Stuebner Reviewed-by: Doug Anderson Tested-by: Kever Yang diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index d168669..ac5803c 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -4,6 +4,7 @@ config ARCH_ROCKCHIP select PINCTRL_ROCKCHIP select ARCH_HAS_RESET_CONTROLLER select ARCH_REQUIRE_GPIOLIB + select ARM_AMBA select ARM_GIC select CACHE_L2X0 select HAVE_ARM_ARCH_TIMER -- cgit v0.10.2 From 982891c3859f310935226c58ad84f3fb88a79e54 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Heiko=20St=C3=BCbner?= Date: Thu, 14 Aug 2014 23:01:25 +0200 Subject: ARM: dts: rockchip: add rk3288 dma controllers Add both the bus and peripheral pl330 dma controllers present in rk3288 socs. The first dma controller can change between secure and non-secure mode. Both instances are added but the non-secure variant is left disabled by default, as on the majority of boards the bootloader leaves it in secure mode. Signed-off-by: Heiko Stuebner Tested-by: Kever Yang diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index 5950b0a..add0e11 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -62,6 +62,44 @@ }; }; + amba { + compatible = "arm,amba-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + dmac_peri: dma-controller@ff250000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0xff250000 0x4000>; + interrupts = , + ; + #dma-cells = <1>; + clocks = <&cru ACLK_DMAC2>; + clock-names = "apb_pclk"; + }; + + dmac_bus_ns: dma-controller@ff600000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0xff600000 0x4000>; + interrupts = , + ; + #dma-cells = <1>; + clocks = <&cru ACLK_DMAC1>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + dmac_bus_s: dma-controller@ffb20000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0xffb20000 0x4000>; + interrupts = , + ; + #dma-cells = <1>; + clocks = <&cru ACLK_DMAC1>; + clock-names = "apb_pclk"; + }; + }; + xin24m: oscillator { compatible = "fixed-clock"; clock-frequency = <24000000>; -- cgit v0.10.2 From ac42f481b75b98076b47fac60796657508f80abe Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Heiko=20St=C3=BCbner?= Date: Thu, 14 Aug 2014 23:01:50 +0200 Subject: ARM: dts: rockchip: add rk3066 and rk3188 dma controllers Add both the cpu and peripheral pl330 dma controllers present in rk3188 socs. The first dma controller can change between secure and non-secure mode. Both instances are added but the non-secure variant is left disabled by default, as on the majority of boards the bootloader leaves it in secure mode. Signed-off-by: Heiko Stuebner diff --git a/arch/arm/boot/dts/rk3xxx.dtsi b/arch/arm/boot/dts/rk3xxx.dtsi index 8caf85d..b5bd3a6 100644 --- a/arch/arm/boot/dts/rk3xxx.dtsi +++ b/arch/arm/boot/dts/rk3xxx.dtsi @@ -28,6 +28,44 @@ i2c4 = &i2c4; }; + amba { + compatible = "arm,amba-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + dmac1_s: dma-controller@20018000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x20018000 0x4000>; + interrupts = , + ; + #dma-cells = <1>; + clocks = <&cru ACLK_DMA1>; + clock-names = "apb_pclk"; + }; + + dmac1_ns: dma-controller@2001c000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x2001c000 0x4000>; + interrupts = , + ; + #dma-cells = <1>; + clocks = <&cru ACLK_DMA1>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + dmac2: dma-controller@20078000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x20078000 0x4000>; + interrupts = , + ; + #dma-cells = <1>; + clocks = <&cru ACLK_DMA2>; + clock-names = "apb_pclk"; + }; + }; + xin24m: oscillator { compatible = "fixed-clock"; clock-frequency = <24000000>; -- cgit v0.10.2 From bf8f0392306869412887bf4a681fea9cb8062fc5 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Tue, 2 Sep 2014 09:57:09 -0600 Subject: ARM: tegra: add touchpad to Venice2 DT Venice2 contains an Atmel MXT touchpad. Add an I2C node for it to DT. The Linux driver doesn't quite work on this platform yet, but adding the DT node causes no issues, and will allow the device to work once the driver is fixed. Signed-off-by: Stephen Warren diff --git a/arch/arm/boot/dts/tegra124-venice2.dts b/arch/arm/boot/dts/tegra124-venice2.dts index 70ad91d..dcbe585 100644 --- a/arch/arm/boot/dts/tegra124-venice2.dts +++ b/arch/arm/boot/dts/tegra124-venice2.dts @@ -606,6 +606,14 @@ i2c@0,7000c400 { status = "okay"; clock-frequency = <100000>; + + trackpad@4b { + compatible = "atmel,maxtouch"; + reg = <0x4b>; + interrupt-parent = <&gpio>; + interrupts = ; + linux,gpio-keymap = <0 0 0 BTN_LEFT>; + }; }; i2c@0,7000c500 { -- cgit v0.10.2 From f1a07231611c9c6f6a9a49c5a0f230b4f594d5b4 Mon Sep 17 00:00:00 2001 From: Addy Ke Date: Tue, 19 Aug 2014 18:21:08 +0800 Subject: ARM: dts: Add sdio0 and sdio1 to the rk3288 This patch requires that land in order to compile. Reviewed-by: Doug Anderson Signed-off-by: Addy Ke Signed-off-by: Heiko Stuebner diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index 9eda097..5f866e0 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -88,6 +88,26 @@ status = "disabled"; }; + sdio0: dwmmc@ff0d0000 { + compatible = "rockchip,rk3288-dw-mshc"; + clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>; + clock-names = "biu", "ciu"; + fifo-depth = <0x100>; + interrupts = ; + reg = <0xff0d0000 0x4000>; + status = "disabled"; + }; + + sdio1: dwmmc@ff0e0000 { + compatible = "rockchip,rk3288-dw-mshc"; + clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>; + clock-names = "biu", "ciu"; + fifo-depth = <0x100>; + interrupts = ; + reg = <0xff0e0000 0x4000>; + status = "disabled"; + }; + emmc: dwmmc@ff0f0000 { compatible = "rockchip,rk3288-dw-mshc"; clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>; @@ -562,6 +582,88 @@ }; }; + sdio0 { + sdio0_bus1: sdio0-bus1 { + rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>; + }; + + sdio0_bus4: sdio0-bus4 { + rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>, + <4 21 RK_FUNC_1 &pcfg_pull_up>, + <4 22 RK_FUNC_1 &pcfg_pull_up>, + <4 23 RK_FUNC_1 &pcfg_pull_up>; + }; + + sdio0_cmd: sdio0-cmd { + rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_up>; + }; + + sdio0_clk: sdio0-clk { + rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none>; + }; + + sdio0_cd: sdio0-cd { + rockchip,pins = <4 26 RK_FUNC_1 &pcfg_pull_up>; + }; + + sdio0_wp: sdio0-wp { + rockchip,pins = <4 27 RK_FUNC_1 &pcfg_pull_up>; + }; + + sdio0_pwr: sdio0-pwr { + rockchip,pins = <4 28 RK_FUNC_1 &pcfg_pull_up>; + }; + + sdio0_bkpwr: sdio0-bkpwr { + rockchip,pins = <4 29 RK_FUNC_1 &pcfg_pull_up>; + }; + + sdio0_int: sdio0-int { + rockchip,pins = <4 30 RK_FUNC_1 &pcfg_pull_up>; + }; + }; + + sdio1 { + sdio1_bus1: sdio1-bus1 { + rockchip,pins = <3 24 4 &pcfg_pull_up>; + }; + + sdio1_bus4: sdio1-bus4 { + rockchip,pins = <3 24 4 &pcfg_pull_up>, + <3 25 4 &pcfg_pull_up>, + <3 26 4 &pcfg_pull_up>, + <3 27 4 &pcfg_pull_up>; + }; + + sdio1_cd: sdio1-cd { + rockchip,pins = <3 28 4 &pcfg_pull_up>; + }; + + sdio1_wp: sdio1-wp { + rockchip,pins = <3 29 4 &pcfg_pull_up>; + }; + + sdio1_bkpwr: sdio1-bkpwr { + rockchip,pins = <3 30 4 &pcfg_pull_up>; + }; + + sdio1_int: sdio1-int { + rockchip,pins = <3 31 4 &pcfg_pull_up>; + }; + + sdio1_cmd: sdio1-cmd { + rockchip,pins = <4 6 4 &pcfg_pull_up>; + }; + + sdio1_clk: sdio1-clk { + rockchip,pins = <4 7 4 &pcfg_pull_none>; + }; + + sdio1_pwr: sdio1-pwr { + rockchip,pins = <4 9 4 &pcfg_pull_up>; + }; + }; + emmc { emmc_clk: emmc-clk { rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>; -- cgit v0.10.2 From 126f998e4ae8bc45cd72c7e62c53767c007fc319 Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Wed, 3 Sep 2014 09:49:01 +0900 Subject: ARM: shmobile: lager: correct memory map The base address of the second memory region on the lager board is 0x140000000. Update the tag used in the dts file accordingly. This is a documentation fix and should have no run-time affect. This problem was introduced when the second memory region was added to the lager dts file by 62bc32a2573c4219 ("ARM: shmobile: Include all 4 GiB of memory on Lager)" in v3.14. Reported-by: NAOYA SHIIBA Signed-off-by: Simon Horman diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts index b5f56bc..f467c6d 100644 --- a/arch/arm/boot/dts/r8a7790-lager.dts +++ b/arch/arm/boot/dts/r8a7790-lager.dts @@ -32,7 +32,7 @@ reg = <0 0x40000000 0 0x40000000>; }; - memory@180000000 { + memory@140000000 { device_type = "memory"; reg = <1 0x40000000 0 0xc0000000>; }; -- cgit v0.10.2 From f5bbe55a270fa153465df23c266f61973c4c7dc0 Mon Sep 17 00:00:00 2001 From: Jaehoon Chung Date: Mon, 11 Aug 2014 15:57:50 -0500 Subject: ARM: dts: socfpga: unuse the slot-node and deprecate the supports-highspeed for dw-mmc dw-mmc controller can support multiple slots. But, there are no use-cases anywhere. So we don't need to support the slot-node for dw-mmc controller. And "supports-highspeed" property in dw-mmc is deprecated. "supports-highspeed" property can be replaced with "cap-sd/mmc-highspeed". Signed-off-by: Jaehoon Chung Reviewed-by: Tushar Behera Reviewed-by: Ulf Hansson Acked-by: Seungwon Jeon Signed-off-by: Dinh Nguyen diff --git a/arch/arm/boot/dts/socfpga_arria5.dtsi b/arch/arm/boot/dts/socfpga_arria5.dtsi index 12d1c2c..468fc4c 100644 --- a/arch/arm/boot/dts/socfpga_arria5.dtsi +++ b/arch/arm/boot/dts/socfpga_arria5.dtsi @@ -29,13 +29,10 @@ dwmmc0@ff704000 { num-slots = <1>; - supports-highspeed; broken-cd; - - slot@0 { - reg = <0>; - bus-width = <4>; - }; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; }; sysmgr@ffd08000 { diff --git a/arch/arm/boot/dts/socfpga_cyclone5.dtsi b/arch/arm/boot/dts/socfpga_cyclone5.dtsi index bf51182..1ee03c4 100644 --- a/arch/arm/boot/dts/socfpga_cyclone5.dtsi +++ b/arch/arm/boot/dts/socfpga_cyclone5.dtsi @@ -30,13 +30,10 @@ dwmmc0@ff704000 { num-slots = <1>; - supports-highspeed; broken-cd; - - slot@0 { - reg = <0>; - bus-width = <4>; - }; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; }; ethernet@ff702000 { diff --git a/arch/arm/boot/dts/socfpga_vt.dts b/arch/arm/boot/dts/socfpga_vt.dts index 09792b4..f9345e0 100644 --- a/arch/arm/boot/dts/socfpga_vt.dts +++ b/arch/arm/boot/dts/socfpga_vt.dts @@ -43,13 +43,10 @@ dwmmc0@ff704000 { num-slots = <1>; - supports-highspeed; broken-cd; - - slot@0 { - reg = <0>; - bus-width = <4>; - }; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; }; ethernet@ff700000 { -- cgit v0.10.2 From 6314b318735a7b02271255ea4dae91ed95f528a1 Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Wed, 13 Aug 2014 16:29:28 -0500 Subject: ARM: dts: socfpga: remove extra alias in the ArriaV devkit commit [2755e187 dts: socfpga: Add DTS entry for adding the stmmac glue layer for stmmac.] added an extra ethernet alias in the ArriaV devkit board file. This patch removes it. Signed-off-by: Dinh Nguyen diff --git a/arch/arm/boot/dts/socfpga_arria5_socdk.dts b/arch/arm/boot/dts/socfpga_arria5_socdk.dts index d532d17..27d551c 100644 --- a/arch/arm/boot/dts/socfpga_arria5_socdk.dts +++ b/arch/arm/boot/dts/socfpga_arria5_socdk.dts @@ -37,13 +37,6 @@ */ ethernet0 = &gmac1; }; - - aliases { - /* this allow the ethaddr uboot environmnet variable contents - * to be added to the gmac1 device tree blob. - */ - ethernet0 = &gmac1; - }; }; &gmac1 { -- cgit v0.10.2 From 8126def857fdc5aba60a72a3a883f5eccf7c91d7 Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Thu, 14 Aug 2014 10:21:48 -0500 Subject: ARM: dts: socfpga: Add SD card detect Revision D of the SOCFGPA devkit has a GPIO line used for SD/MMC card detect. Signed-off-by: Dinh Nguyen Acked-by: Pavel Machek diff --git a/arch/arm/boot/dts/socfpga_cyclone5.dtsi b/arch/arm/boot/dts/socfpga_cyclone5.dtsi index 1ee03c4..33cad8b 100644 --- a/arch/arm/boot/dts/socfpga_cyclone5.dtsi +++ b/arch/arm/boot/dts/socfpga_cyclone5.dtsi @@ -28,7 +28,7 @@ }; }; - dwmmc0@ff704000 { + mmc0: dwmmc0@ff704000 { num-slots = <1>; broken-cd; bus-width = <4>; diff --git a/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts b/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts index 45de151..d7296a5 100644 --- a/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts +++ b/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts @@ -68,6 +68,10 @@ }; }; +&mmc0 { + cd-gpios = <&gpio1 18 0>; +}; + &usb1 { status = "okay"; }; -- cgit v0.10.2 From c6dcb1010239e484a461178d3318b35ef44dbcf0 Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Thu, 14 Aug 2014 10:37:22 -0500 Subject: ARM: dts: socfpga: memreserve first 4KB for future system use This patch adds a /memreserve/ section to reserve the first 4K for future use by the system. One possible use-case is trampoline code used to bring secondary cores online. Signed-off-by: Dinh Nguyen Acked-by: Pavel Machek --- v3: Update commit message based on Mark Rutland's comment v2: Add a comment in the dts files diff --git a/arch/arm/boot/dts/socfpga_arria5.dtsi b/arch/arm/boot/dts/socfpga_arria5.dtsi index 468fc4c..03e8268 100644 --- a/arch/arm/boot/dts/socfpga_arria5.dtsi +++ b/arch/arm/boot/dts/socfpga_arria5.dtsi @@ -15,6 +15,8 @@ */ /dts-v1/; +/* First 4KB has trampoline code for secondary cores. */ +/memreserve/ 0x00000000 0x0001000; #include "socfpga.dtsi" / { diff --git a/arch/arm/boot/dts/socfpga_cyclone5.dtsi b/arch/arm/boot/dts/socfpga_cyclone5.dtsi index 33cad8b..28c05e7 100644 --- a/arch/arm/boot/dts/socfpga_cyclone5.dtsi +++ b/arch/arm/boot/dts/socfpga_cyclone5.dtsi @@ -16,6 +16,8 @@ */ /dts-v1/; +/* First 4KB has trampoline code for secondary cores. */ +/memreserve/ 0x00000000 0x0001000; #include "socfpga.dtsi" / { -- cgit v0.10.2 From 75a41826e2c5dc1dc0fd5195fc29b031c97337af Mon Sep 17 00:00:00 2001 From: Thor Thayer Date: Tue, 26 Aug 2014 16:09:32 -0500 Subject: arm: dts: Add Altera SDRAM EDAC bindings & devicetree entries. Add the Altera SDRAM EDAC bindings and device tree changes to the Altera SoC project. There was a discussion thread on whether this driver should be an mfd driver or just make use of syscon, which is already a mfd. Ultimately, the decision to use a simple syscon interface was reached.[1] [1] https://lkml.org/lkml/2014/7/30/514 Signed-off-by: Thor Thayer Acked-by: Pavel Machek [dinguyen] cleaned-up commit header and remove version history. Signed-off-by: Dinh Nguyen diff --git a/Documentation/devicetree/bindings/arm/altera/socfpga-sdram-edac.txt b/Documentation/devicetree/bindings/arm/altera/socfpga-sdram-edac.txt new file mode 100644 index 0000000..d0ce01d --- /dev/null +++ b/Documentation/devicetree/bindings/arm/altera/socfpga-sdram-edac.txt @@ -0,0 +1,15 @@ +Altera SOCFPGA SDRAM Error Detection & Correction [EDAC] +The EDAC accesses a range of registers in the SDRAM controller. + +Required properties: +- compatible : should contain "altr,sdram-edac"; +- altr,sdr-syscon : phandle of the sdr module +- interrupts : Should contain the SDRAM ECC IRQ in the + appropriate format for the IRQ controller. + +Example: + sdramedac { + compatible = "altr,sdram-edac"; + altr,sdr-syscon = <&sdr>; + interrupts = <0 39 4>; + }; diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi index 4d77ad6..45fce2c 100644 --- a/arch/arm/boot/dts/socfpga.dtsi +++ b/arch/arm/boot/dts/socfpga.dtsi @@ -607,6 +607,17 @@ }; }; + sdr: sdr@ffc25000 { + compatible = "syscon"; + reg = <0xffc25000 0x1000>; + }; + + sdramedac { + compatible = "altr,sdram-edac"; + altr,sdr-syscon = <&sdr>; + interrupts = <0 39 4>; + }; + L2: l2-cache@fffef000 { compatible = "arm,pl310-cache"; reg = <0xfffef000 0x1000>; -- cgit v0.10.2 From edfbad068bde82ef228c551569ae4eabeacaf9a6 Mon Sep 17 00:00:00 2001 From: Dylan Reid Date: Thu, 4 Sep 2014 15:20:34 -0700 Subject: ARM: tegra: Move pwm and dpaux labels to tegra124.dtsi These labels will be used by other boards in addition to Venice2, move them to tegra124.dtsi so they are defined in a common place. Signed-off-by: Dylan Reid Signed-off-by: Stephen Warren diff --git a/arch/arm/boot/dts/tegra124-venice2.dts b/arch/arm/boot/dts/tegra124-venice2.dts index dcbe585..a076a2c 100644 --- a/arch/arm/boot/dts/tegra124-venice2.dts +++ b/arch/arm/boot/dts/tegra124-venice2.dts @@ -36,7 +36,7 @@ nvidia,panel = <&panel>; }; - dpaux: dpaux@0,545c0000 { + dpaux@0,545c0000 { vdd-supply = <&vdd_3v3_panel>; status = "okay"; }; @@ -587,7 +587,7 @@ status = "okay"; }; - pwm: pwm@0,7000a000 { + pwm@0,7000a000 { status = "okay"; }; diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index a6e4814..0ba3a0b 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -78,7 +78,7 @@ status = "disabled"; }; - dpaux@0,545c0000 { + dpaux: dpaux@0,545c0000 { compatible = "nvidia,tegra124-dpaux"; reg = <0x0 0x545c0000 0x0 0x00040000>; interrupts = ; @@ -272,7 +272,7 @@ status = "disabled"; }; - pwm@0,7000a000 { + pwm: pwm@0,7000a000 { compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm"; reg = <0x0 0x7000a000 0x0 0x100>; #pwm-cells = <2>; -- cgit v0.10.2 From eb481f9ac95cc9350436311036e3a513e1993430 Mon Sep 17 00:00:00 2001 From: Dylan Reid Date: Thu, 4 Sep 2014 15:20:35 -0700 Subject: ARM: tegra: add Acer Chromebook 13 device tree The Acer Chromebook 13, codenamed Big, contains an NVIDIA tegra124 processor and is similar to the Venice2 reference platform. The keyboard, USB 2, audio, sdcard and emmc have been tested and work on the 1366x768 models. The Full HD models haven't been tested yet. WiFi does not yet work, it needs at least some PMIC changes to enable the 32k clock. The elan trackpad is not yet functional but hopefully will be soon as there are patches under review. There is also an issue on reboot because the TPM isn't reset. It will cause the stock firmware to enter recovery mode. This can be worked around by an EC-reset, press the refresh and power keys at the same time. Signed-off-by: Dylan Reid Signed-off-by: Stephen Warren diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index b8c5cd3..25d0b9f 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -440,6 +440,7 @@ dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \ tegra114-roth.dtb \ tegra114-tn7.dtb \ tegra124-jetson-tk1.dtb \ + tegra124-nyan-big.dtb \ tegra124-venice2.dtb dtb-$(CONFIG_ARCH_U300) += ste-u300.dtb dtb-$(CONFIG_ARCH_U8500) += ste-snowball.dtb \ diff --git a/arch/arm/boot/dts/tegra124-nyan-big.dts b/arch/arm/boot/dts/tegra124-nyan-big.dts new file mode 100644 index 0000000..7d0784c --- /dev/null +++ b/arch/arm/boot/dts/tegra124-nyan-big.dts @@ -0,0 +1,1136 @@ +/dts-v1/; + +#include +#include "tegra124.dtsi" + +/ { + model = "Acer Chromebook 13 CB5-311"; + compatible = "google,nyan-big", "nvidia,tegra124"; + + aliases { + rtc0 = "/i2c@0,7000d000/pmic@40"; + rtc1 = "/rtc@0,7000e000"; + }; + + memory { + reg = <0x0 0x80000000 0x0 0x80000000>; + }; + + host1x@0,50000000 { + hdmi@0,54280000 { + status = "okay"; + + vdd-supply = <&vdd_3v3_hdmi>; + pll-supply = <&vdd_hdmi_pll>; + hdmi-supply = <&vdd_5v0_hdmi>; + + nvidia,ddc-i2c-bus = <&hdmi_ddc>; + nvidia,hpd-gpio = + <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; + }; + + sor@0,54540000 { + status = "okay"; + + nvidia,dpaux = <&dpaux>; + nvidia,panel = <&panel>; + }; + + dpaux@0,545c0000 { + vdd-supply = <&vdd_3v3_panel>; + status = "okay"; + }; + }; + + pinmux@0,70000868 { + pinctrl-names = "default"; + pinctrl-0 = <&pinmux_default>; + + pinmux_default: common { + dap_mclk1_pw4 { + nvidia,pins = "dap_mclk1_pw4"; + nvidia,function = "extperiph1"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + }; + dap2_din_pa4 { + nvidia,pins = "dap2_din_pa4"; + nvidia,function = "i2s1"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + }; + dap2_dout_pa5 { + nvidia,pins = "dap2_dout_pa5", + "dap2_fs_pa2", + "dap2_sclk_pa3"; + nvidia,function = "i2s1"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + }; + dvfs_pwm_px0 { + nvidia,pins = "dvfs_pwm_px0", + "dvfs_clk_px2"; + nvidia,function = "cldvfs"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + }; + ulpi_clk_py0 { + nvidia,pins = "ulpi_clk_py0", + "ulpi_nxt_py2", + "ulpi_stp_py3"; + nvidia,function = "spi1"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + }; + ulpi_dir_py1 { + nvidia,pins = "ulpi_dir_py1"; + nvidia,function = "spi1"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + }; + cam_i2c_scl_pbb1 { + nvidia,pins = "cam_i2c_scl_pbb1", + "cam_i2c_sda_pbb2"; + nvidia,function = "i2c3"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,lock = ; + nvidia,open-drain = ; + }; + gen2_i2c_scl_pt5 { + nvidia,pins = "gen2_i2c_scl_pt5", + "gen2_i2c_sda_pt6"; + nvidia,function = "i2c2"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,lock = ; + nvidia,open-drain = ; + }; + pg4 { + nvidia,pins = "pg4", + "pg5", + "pg6", + "pi3"; + nvidia,function = "spi4"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + }; + pg7 { + nvidia,pins = "pg7"; + nvidia,function = "spi4"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + }; + ph1 { + nvidia,pins = "ph1"; + nvidia,function = "pwm1"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + }; + pk0 { + nvidia,pins = "pk0", + "kb_row15_ps7", + "clk_32k_out_pa0"; + nvidia,function = "soc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc1_clk_pz0 { + nvidia,pins = "sdmmc1_clk_pz0"; + nvidia,function = "sdmmc1"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + }; + sdmmc1_cmd_pz1 { + nvidia,pins = "sdmmc1_cmd_pz1", + "sdmmc1_dat0_py7", + "sdmmc1_dat1_py6", + "sdmmc1_dat2_py5", + "sdmmc1_dat3_py4"; + nvidia,function = "sdmmc1"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + }; + sdmmc3_clk_pa6 { + nvidia,pins = "sdmmc3_clk_pa6"; + nvidia,function = "sdmmc3"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + }; + sdmmc3_cmd_pa7 { + nvidia,pins = "sdmmc3_cmd_pa7", + "sdmmc3_dat0_pb7", + "sdmmc3_dat1_pb6", + "sdmmc3_dat2_pb5", + "sdmmc3_dat3_pb4", + "kb_col4_pq4", + "sdmmc3_clk_lb_out_pee4", + "sdmmc3_clk_lb_in_pee5", + "sdmmc3_cd_n_pv2"; + nvidia,function = "sdmmc3"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + }; + sdmmc4_clk_pcc4 { + nvidia,pins = "sdmmc4_clk_pcc4"; + nvidia,function = "sdmmc4"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + }; + sdmmc4_cmd_pt7 { + nvidia,pins = "sdmmc4_cmd_pt7", + "sdmmc4_dat0_paa0", + "sdmmc4_dat1_paa1", + "sdmmc4_dat2_paa2", + "sdmmc4_dat3_paa3", + "sdmmc4_dat4_paa4", + "sdmmc4_dat5_paa5", + "sdmmc4_dat6_paa6", + "sdmmc4_dat7_paa7"; + nvidia,function = "sdmmc4"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + }; + pwr_i2c_scl_pz6 { + nvidia,pins = "pwr_i2c_scl_pz6", + "pwr_i2c_sda_pz7"; + nvidia,function = "i2cpwr"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,lock = ; + nvidia,open-drain = ; + }; + jtag_rtck { + nvidia,pins = "jtag_rtck"; + nvidia,function = "rtck"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + }; + clk_32k_in { + nvidia,pins = "clk_32k_in"; + nvidia,function = "clk"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + }; + core_pwr_req { + nvidia,pins = "core_pwr_req"; + nvidia,function = "pwron"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + }; + cpu_pwr_req { + nvidia,pins = "cpu_pwr_req"; + nvidia,function = "cpu"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + }; + pwr_int_n { + nvidia,pins = "pwr_int_n"; + nvidia,function = "pmi"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + }; + reset_out_n { + nvidia,pins = "reset_out_n"; + nvidia,function = "reset_out_n"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + }; + clk3_out_pee0 { + nvidia,pins = "clk3_out_pee0"; + nvidia,function = "extperiph3"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + }; + gen1_i2c_sda_pc5 { + nvidia,pins = "gen1_i2c_sda_pc5", + "gen1_i2c_scl_pc4"; + nvidia,function = "i2c1"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,lock = ; + nvidia,open-drain = ; + }; + hdmi_cec_pee3 { + nvidia,pins = "hdmi_cec_pee3"; + nvidia,function = "cec"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,lock = ; + nvidia,open-drain = ; + }; + hdmi_int_pn7 { + nvidia,pins = "hdmi_int_pn7"; + nvidia,function = "rsvd1"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + }; + ddc_scl_pv4 { + nvidia,pins = "ddc_scl_pv4", + "ddc_sda_pv5"; + nvidia,function = "i2c4"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,lock = ; + nvidia,rcv-sel = ; + }; + kb_row10_ps2 { + nvidia,pins = "kb_row10_ps2"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row9_ps1 { + nvidia,pins = "kb_row9_ps1"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + usb_vbus_en0_pn4 { + nvidia,pins = "usb_vbus_en0_pn4", + "usb_vbus_en1_pn5"; + nvidia,function = "usb"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,lock = ; + nvidia,open-drain = ; + }; + drive_sdio1 { + nvidia,pins = "drive_sdio1"; + nvidia,high-speed-mode = ; + nvidia,schmitt = ; + nvidia,pull-down-strength = <36>; + nvidia,pull-up-strength = <20>; + nvidia,slew-rate-rising = ; + nvidia,slew-rate-falling = ; + }; + drive_sdio3 { + nvidia,pins = "drive_sdio3"; + nvidia,high-speed-mode = ; + nvidia,schmitt = ; + nvidia,pull-down-strength = <22>; + nvidia,pull-up-strength = <36>; + nvidia,slew-rate-rising = ; + nvidia,slew-rate-falling = ; + }; + drive_gma { + nvidia,pins = "drive_gma"; + nvidia,high-speed-mode = ; + nvidia,schmitt = ; + nvidia,pull-down-strength = <2>; + nvidia,pull-up-strength = <1>; + nvidia,slew-rate-rising = ; + nvidia,slew-rate-falling = ; + nvidia,drive-type = <1>; + }; + codec_irq_l { + nvidia,pins = "ph4"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_bl_en { + nvidia,pins = "ph2"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + touch_irq_l { + nvidia,pins = "gpio_w3_aud_pw3"; + nvidia,function = "spi6"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + tpm_davint_l { + nvidia,pins = "ph6"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ts_irq_l { + nvidia,pins = "pk2"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ts_reset_l { + nvidia,pins = "pk4"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ts_shdn_l { + nvidia,pins = "pk1"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ph7 { + nvidia,pins = "ph7"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_col0_ap { + nvidia,pins = "kb_col0_pq0"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lid_open { + nvidia,pins = "kb_row4_pr4"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + en_vdd_sd { + nvidia,pins = "kb_row0_pr0"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ac_ok { + nvidia,pins = "pj0"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sensor_irq_l { + nvidia,pins = "pi6"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + wifi_en { + nvidia,pins = "gpio_x7_aud_px7"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + en_vdd_bl { + nvidia,pins = "dap3_dout_pp2"; + nvidia,function = "i2s2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + en_vdd_hdmi { + nvidia,pins = "spdif_in_pk6"; + nvidia,function = "spdif"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + soc_warm_reset_l { + nvidia,pins = "pi5"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + hp_det_l { + nvidia,pins = "pi7"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + mic_det_l { + nvidia,pins = "kb_row7_pr7"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + }; + }; + + serial@0,70006000 { + /* Debug connector on the bottom of the board near SD card. */ + status = "okay"; + }; + + pwm@0,7000a000 { + status = "okay"; + }; + + i2c@0,7000c000 { + status = "okay"; + clock-frequency = <100000>; + + acodec: audio-codec@10 { + compatible = "maxim,max98090"; + reg = <0x10>; + interrupt-parent = <&gpio>; + interrupts = ; + }; + + temperature-sensor@4c { + compatible = "ti,tmp451"; + reg = <0x4c>; + interrupt-parent = <&gpio>; + interrupts = ; + + #thermal-sensor-cells = <1>; + }; + }; + + i2c@0,7000c400 { + status = "okay"; + clock-frequency = <100000>; + }; + + i2c@0,7000c500 { + status = "okay"; + clock-frequency = <400000>; + + tpm@20 { + compatible = "infineon,slb9645tt"; + reg = <0x20>; + }; + }; + + hdmi_ddc: i2c@0,7000c700 { + status = "okay"; + clock-frequency = <100000>; + }; + + i2c@0,7000d000 { + status = "okay"; + clock-frequency = <400000>; + + pmic: pmic@40 { + compatible = "ams,as3722"; + reg = <0x40>; + interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; + + ams,system-power-controller; + + #interrupt-cells = <2>; + interrupt-controller; + + gpio-controller; + #gpio-cells = <2>; + + pinctrl-names = "default"; + pinctrl-0 = <&as3722_default>; + + as3722_default: pinmux { + gpio0 { + pins = "gpio0"; + function = "gpio"; + bias-pull-down; + }; + + gpio1 { + pins = "gpio1"; + function = "gpio"; + bias-pull-up; + }; + + gpio2_4_7 { + pins = "gpio2", "gpio4", "gpio7"; + function = "gpio"; + bias-pull-up; + }; + + gpio3_6 { + pins = "gpio3", "gpio6"; + bias-high-impedance; + }; + + gpio5 { + pins = "gpio5"; + function = "clk32k-out"; + bias-pull-down; + }; + }; + + regulators { + vsup-sd2-supply = <&vdd_5v0_sys>; + vsup-sd3-supply = <&vdd_5v0_sys>; + vsup-sd4-supply = <&vdd_5v0_sys>; + vsup-sd5-supply = <&vdd_5v0_sys>; + vin-ldo0-supply = <&vdd_1v35_lp0>; + vin-ldo1-6-supply = <&vdd_3v3_run>; + vin-ldo2-5-7-supply = <&vddio_1v8>; + vin-ldo3-4-supply = <&vdd_3v3_sys>; + vin-ldo9-10-supply = <&vdd_5v0_sys>; + vin-ldo11-supply = <&vdd_3v3_run>; + + sd0 { + regulator-name = "+VDD_CPU_AP"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1350000>; + regulator-min-microamp = <3500000>; + regulator-max-microamp = <3500000>; + regulator-always-on; + regulator-boot-on; + ams,ext-control = <2>; + }; + + sd1 { + regulator-name = "+VDD_CORE"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1350000>; + regulator-min-microamp = <2500000>; + regulator-max-microamp = <4000000>; + regulator-always-on; + regulator-boot-on; + ams,ext-control = <1>; + }; + + vdd_1v35_lp0: sd2 { + regulator-name = "+1.35V_LP0(sd2)"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + }; + + sd3 { + regulator-name = "+1.35V_LP0(sd3)"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_1v05_run: sd4 { + regulator-name = "+1.05V_RUN"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + }; + + vddio_1v8: sd5 { + regulator-name = "+1.8V_VDDIO"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + sd6 { + regulator-name = "+VDD_GPU_AP"; + regulator-min-microvolt = <650000>; + regulator-max-microvolt = <1200000>; + regulator-min-microamp = <3500000>; + regulator-max-microamp = <3500000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo0 { + regulator-name = "+1.05V_RUN_AVDD"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + regulator-boot-on; + regulator-always-on; + ams,ext-control = <1>; + }; + + ldo1 { + regulator-name = "+1.8V_RUN_CAM"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo2 { + regulator-name = "+1.2V_GEN_AVDD"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3 { + regulator-name = "+1.00V_LP0_VDD_RTC"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-boot-on; + regulator-always-on; + ams,enable-tracking; + }; + + vdd_run_cam: ldo4 { + regulator-name = "+3.3V_RUN_CAM"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + ldo5 { + regulator-name = "+1.2V_RUN_CAM_FRONT"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + vddio_sdmmc3: ldo6 { + regulator-name = "+VDDIO_SDMMC3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + ldo7 { + regulator-name = "+1.05V_RUN_CAM_REAR"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + }; + + ldo9 { + regulator-name = "+2.8V_RUN_TOUCH"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + ldo10 { + regulator-name = "+2.8V_RUN_CAM_AF"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + ldo11 { + regulator-name = "+1.8V_RUN_VPP_FUSE"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + }; + }; + }; + + spi@0,7000d400 { + status = "okay"; + + cros_ec: cros-ec@0 { + compatible = "google,cros-ec-spi"; + spi-max-frequency = <3000000>; + interrupt-parent = <&gpio>; + interrupts = ; + reg = <0>; + + google,cros-ec-spi-msg-delay = <2000>; + + i2c-tunnel { + compatible = "google,cros-ec-i2c-tunnel"; + #address-cells = <1>; + #size-cells = <0>; + + google,remote-bus = <0>; + + charger: bq24735@9 { + compatible = "ti,bq24735"; + reg = <0x9>; + interrupt-parent = <&gpio>; + interrupts = ; + ti,ac-detect-gpios = <&gpio + TEGRA_GPIO(J, 0) + GPIO_ACTIVE_HIGH>; + }; + + battery: sbs-battery@b { + compatible = "sbs,sbs-battery"; + reg = <0xb>; + sbs,i2c-retry-count = <2>; + sbs,poll-retry-count = <10>; + power-supplies = <&charger>; + }; + }; + }; + }; + + spi@0,7000da00 { + status = "okay"; + spi-max-frequency = <25000000>; + + flash@0 { + compatible = "winbond,w25q32dw"; + reg = <0>; + }; + }; + + pmc@0,7000e400 { + nvidia,invert-interrupt; + nvidia,suspend-mode = <0>; + nvidia,cpu-pwr-good-time = <500>; + nvidia,cpu-pwr-off-time = <300>; + nvidia,core-pwr-good-time = <641 3845>; + nvidia,core-pwr-off-time = <61036>; + nvidia,core-power-req-active-high; + nvidia,sys-clock-req-active-high; + }; + + hda@0,70030000 { + status = "okay"; + }; + + sdhci@0,700b0000 { /* WiFi/BT on this bus */ + status = "okay"; + power-gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_HIGH>; + bus-width = <4>; + no-1-8-v; + non-removable; + }; + + sdhci@0,700b0400 { /* SD Card on this bus */ + status = "okay"; + cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; + power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>; + wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>; + bus-width = <4>; + no-1-8-v; + vqmmc-supply = <&vddio_sdmmc3>; + }; + + sdhci@0,700b0600 { /* eMMC on this bus */ + status = "okay"; + bus-width = <8>; + no-1-8-v; + non-removable; + }; + + ahub@0,70300000 { + i2s@0,70301100 { + status = "okay"; + }; + }; + + usb@0,7d000000 { /* Rear external USB port. */ + status = "okay"; + }; + + usb-phy@0,7d000000 { + status = "okay"; + vbus-supply = <&vdd_usb1_vbus>; + }; + + usb@0,7d004000 { /* Internal webcam. */ + status = "okay"; + }; + + usb-phy@0,7d004000 { + status = "okay"; + vbus-supply = <&vdd_run_cam>; + }; + + usb@0,7d008000 { /* Left external USB port. */ + status = "okay"; + }; + + usb-phy@0,7d008000 { + status = "okay"; + vbus-supply = <&vdd_usb3_vbus>; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + + enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; + power-supply = <&vdd_led>; + pwms = <&pwm 1 1000000>; + + default-brightness-level = <224>; + brightness-levels = + < 0 1 2 3 4 5 6 7 + 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 + 24 25 26 27 28 29 30 31 + 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + 256>; + }; + + clocks { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + clk32k_in: clock@0 { + compatible = "fixed-clock"; + reg = <0>; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + lid { + label = "Lid"; + gpios = <&gpio TEGRA_GPIO(R, 4) GPIO_ACTIVE_LOW>; + linux,input-type = <5>; + linux,code = ; + debounce-interval = <1>; + gpio-key,wakeup; + }; + + power { + label = "Power"; + gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <30>; + gpio-key,wakeup; + }; + }; + + panel: panel { + compatible = "auo,b133xtn01"; + + backlight = <&backlight>; + ddc-i2c-bus = <&dpaux>; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + vdd_mux: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "+VDD_MUX"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_5v0_sys: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "+5V_SYS"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vdd_mux>; + }; + + vdd_3v3_sys: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "+3.3V_SYS"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vdd_mux>; + }; + + vdd_3v3_run: regulator@3 { + compatible = "regulator-fixed"; + reg = <3>; + regulator-name = "+3.3V_RUN"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + gpio = <&pmic 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_3v3_sys>; + }; + + vdd_3v3_hdmi: regulator@4 { + compatible = "regulator-fixed"; + reg = <4>; + regulator-name = "+3.3V_AVDD_HDMI_AP_GATED"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vdd_3v3_run>; + }; + + vdd_led: regulator@5 { + compatible = "regulator-fixed"; + reg = <5>; + regulator-name = "+VDD_LED"; + gpio = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_mux>; + }; + + vdd_5v0_ts: regulator@6 { + compatible = "regulator-fixed"; + reg = <6>; + regulator-name = "+5V_VDD_TS_SW"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_5v0_sys>; + }; + + vdd_usb1_vbus: regulator@7 { + compatible = "regulator-fixed"; + reg = <7>; + regulator-name = "+5V_USB_HS"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>; + enable-active-high; + gpio-open-drain; + vin-supply = <&vdd_5v0_sys>; + }; + + vdd_usb3_vbus: regulator@8 { + compatible = "regulator-fixed"; + reg = <8>; + regulator-name = "+5V_USB_SS"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>; + enable-active-high; + gpio-open-drain; + vin-supply = <&vdd_5v0_sys>; + }; + + vdd_3v3_panel: regulator@9 { + compatible = "regulator-fixed"; + reg = <9>; + regulator-name = "+3.3V_PANEL"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pmic 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_3v3_run>; + }; + + vdd_3v3_lp0: regulator@10 { + compatible = "regulator-fixed"; + reg = <10>; + regulator-name = "+3.3V_LP0"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + /* + * TODO: find a way to wire this up with the USB EHCI + * controllers so that it can be enabled on demand. + */ + regulator-always-on; + gpio = <&pmic 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_3v3_sys>; + }; + + vdd_hdmi_pll: regulator@11 { + compatible = "regulator-fixed"; + reg = <11>; + regulator-name = "+1.05V_RUN_AVDD_HDMI_PLL"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>; + vin-supply = <&vdd_1v05_run>; + }; + + vdd_5v0_hdmi: regulator@12 { + compatible = "regulator-fixed"; + reg = <12>; + regulator-name = "+5V_HDMI_CON"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_5v0_sys>; + }; + }; + + sound { + compatible = "nvidia,tegra-audio-max98090-nyan-big", + "nvidia,tegra-audio-max98090"; + nvidia,model = "Acer Chromebook 13"; + + nvidia,audio-routing = + "Headphones", "HPR", + "Headphones", "HPL", + "Speakers", "SPKR", + "Speakers", "SPKL", + "Mic Jack", "MICBIAS", + "DMICL", "Int Mic", + "DMICR", "Int Mic", + "IN34", "Mic Jack"; + + nvidia,i2s-controller = <&tegra_i2s1>; + nvidia,audio-codec = <&acodec>; + + clocks = <&tegra_car TEGRA124_CLK_PLL_A>, + <&tegra_car TEGRA124_CLK_PLL_A_OUT0>, + <&tegra_car TEGRA124_CLK_EXTERN1>; + clock-names = "pll_a", "pll_a_out0", "mclk"; + + nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(I, 7) GPIO_ACTIVE_HIGH>; + }; +}; + +#include "cros-ec-keyboard.dtsi" -- cgit v0.10.2 From 6dbaff2bfb2ab0cf5590b193ca6ba52b8990a919 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Wed, 3 Sep 2014 09:42:06 -0600 Subject: ARM: tegra: rely on bootloader pinmux programming on Tegra124 The defined mechanism for programming the Tegra pinmux is to perform all of the following at once in order, before using any I/O controller that is affected by the pinmux: - Set the CLAMP_INPUTS_WHEN_TRISTATED PMC register bit. - Set up any GPIO pins to their "initial" state. - Program all pinmux settings in one go. Other methods such as: - Not setting CLAMP_INPUTS_WHEN_TRISTATED. - Not setting GPIOs to their "initial" state before programming the pinmux settings of the related pin, in particular the mux function. - Not programming the entire pinmux at once, in order to avoid possible conflicting settings. ... are not qualified or supported by NVIDIA ASIC/syseng. They could cause glitches or undesired output levels on some pins, or controller malfunction. While we've been getting away with doing something different on many Tegra boards without issue, I believe we've just been getting lucky. I'd like to switch all Tegra124 systems to the correct scheme now so they provide the right example to follow, and require that any new boards we support upstream work in the same fashion. While it would be nice to update boards containing older SoCs for consistency, I don't anticipate doing so. It's too much churn to change at this time. At least with all Tegra124 boards converted, the most recent boards provide the correct example. Since the bootloader needs to reprogram the pinmux to access certain peripherals, it must program the entire pinmux due to the supported rules above. As such, there is no need to program any part of the pinmux from the kernel, unless dynamic pinmuxing is used. Given this, we couuld simply remove the pinmux "default" state from the DT entirely. However, some bootloaders parse the DT to perform their initial pinmux setup, so it's useful to keep the pinmux data in DT. To allow this while avoiding redundant work in the kernel, rename the "default" state to "boot". The kernel won't apply this, but bootloaders can still look for this state name and apply it. Note however that the DT provides zero information about the required initial GPIO setup, so bootloaders using this approach are not likely to operate correctly without an additional GPIO initialization table somewhere. Previous discussions on the DT mailing list have rejected adding such a table to DT... The following U-Boot commits fully initialize the pinmux: Jetson TK1: 4ff213b8e478 ARM: tegra: clamp inputs on Jetson TK1 Venice2: 3365479ce78a ARM: tegra: Venice2 pinmux spreadsheet updates Both are part of U-Boot v2014.07 and later. Without those commits, the only fallout I see from this change is that HDMI on Venice2 no longer works. Given the very small user-base of this platform, I feel that requiring a bootloader update is reasonable. Signed-off-by: Stephen Warren diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1.dts b/arch/arm/boot/dts/tegra124-jetson-tk1.dts index 3ea4153..64828c2 100644 --- a/arch/arm/boot/dts/tegra124-jetson-tk1.dts +++ b/arch/arm/boot/dts/tegra124-jetson-tk1.dts @@ -31,10 +31,10 @@ }; pinmux: pinmux@0,70000868 { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; + pinctrl-names = "boot"; + pinctrl-0 = <&state_boot>; - state_default: pinmux { + state_boot: pinmux { clk_32k_out_pa0 { nvidia,pins = "clk_32k_out_pa0"; nvidia,function = "soc"; diff --git a/arch/arm/boot/dts/tegra124-venice2.dts b/arch/arm/boot/dts/tegra124-venice2.dts index a076a2c..1300885 100644 --- a/arch/arm/boot/dts/tegra124-venice2.dts +++ b/arch/arm/boot/dts/tegra124-venice2.dts @@ -43,10 +43,10 @@ }; pinmux: pinmux@0,70000868 { - pinctrl-names = "default"; - pinctrl-0 = <&pinmux_default>; + pinctrl-names = "boot"; + pinctrl-0 = <&pinmux_boot>; - pinmux_default: common { + pinmux_boot: common { dap_mclk1_pw4 { nvidia,pins = "dap_mclk1_pw4"; nvidia,function = "extperiph1"; -- cgit v0.10.2 From 6c3ba72415b15440ffc8085e502fbeca01dc2035 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Tue, 2 Sep 2014 19:25:26 +0200 Subject: ARM: sun6i: Relicense the A31 DTSI under GPLv2/X11 The current GPL only licensing on the DTSI makes it very impractical for other software components licensed under another license. In order to make it easier for them to reuse our device trees, relicense our DTSI first under a GPL/X11 dual-license. Hopefully, the DTS will follow soon. Signed-off-by: Maxime Ripard Acked-by: Boris BREZILLON Acked-by: Carlo Caione Acked-by: Chen-Yu Tsai Acked-by: Hans de Goede Acked-by: Arnd Bergmann diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi index 1c2ec91..eb686e7 100644 --- a/arch/arm/boot/dts/sun6i-a31.dtsi +++ b/arch/arm/boot/dts/sun6i-a31.dtsi @@ -3,12 +3,48 @@ * * Maxime Ripard * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this library; if not, write to the Free + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. */ /include/ "skeleton.dtsi" -- cgit v0.10.2 From 394c56ce557b8ea7e74c7b2684a21f0dd434aae1 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Tue, 2 Sep 2014 19:25:26 +0200 Subject: ARM: sun7i: Relicense the A20 DTSI under GPLv2/X11 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The current GPL only licensing on the DTSI makes it very impractical for other software components licensed under another license. In order to make it easier for them to reuse our device trees, relicense our DTSI first under a GPL/X11 dual-license. Hopefully, the DTS will follow soon. Signed-off-by: Maxime Ripard Acked-by: Alexander Bersenev Acked-by: Alexandre Belloni Acked-by: Carlo Caione Acked-by: Chen-Yu Tsai Acked-by: Emilio López Acked-by: Hans de Goede Acked-by: Marc Zyngier Acked-by: Oliver Schinagl Acked-by: Roman Byshko Acked-by: Arnd Bergmann diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index 9f16074..a96b994 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -3,12 +3,48 @@ * * Maxime Ripard * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this library; if not, write to the Free + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. */ /include/ "skeleton.dtsi" -- cgit v0.10.2 From d02fc738a9a9e6cddeed0bf00771286e22d52dee Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Tue, 2 Sep 2014 19:25:26 +0200 Subject: ARM: sun8i: Relicense the A23 DTSI under GPLv2/X11 The current GPL only licensing on the DTSI makes it very impractical for other software components licensed under another license. In order to make it easier for them to reuse our device trees, relicense our DTSI first under a GPL/X11 dual-license. Hopefully, the DTS will follow soon. Signed-off-by: Maxime Ripard Acked-by: Chen-Yu Tsai Acked-by: Arnd Bergmann diff --git a/arch/arm/boot/dts/sun8i-a23.dtsi b/arch/arm/boot/dts/sun8i-a23.dtsi index 2ec86d36..a350392 100644 --- a/arch/arm/boot/dts/sun8i-a23.dtsi +++ b/arch/arm/boot/dts/sun8i-a23.dtsi @@ -3,12 +3,48 @@ * * Chen-Yu Tsai * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this library; if not, write to the Free + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. */ /include/ "skeleton.dtsi" -- cgit v0.10.2 From 7e9711aacc25fa6728c0625e4cfe7a141201b676 Mon Sep 17 00:00:00 2001 From: Keerthy J Date: Mon, 28 Jul 2014 11:48:53 +0530 Subject: ARM: dts: dra72-evm: Enable I2C1 node I2C1 bus is used for the following peripherals P8 connector (MLB) TLV320AIC3106 Audio codec J15 LCD header 24WC256 eeprom TMP102AIDRLT temperature sensor PCF8575 GPIO expander PCA9306 i2c voltage translator -> Goes to P9 for comm interface P2 expansion connector TPS65917 PMIC The slowest speed of all the peripherals seems to be 400KHz. Tested-by: Lokesh Vutla Signed-off-by: Nishanth Menon Signed-off-by: Keerthy Tested-by: Nishanth Menon Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/dra72-evm.dts b/arch/arm/boot/dts/dra72-evm.dts index 5147023..1e12862 100644 --- a/arch/arm/boot/dts/dra72-evm.dts +++ b/arch/arm/boot/dts/dra72-evm.dts @@ -19,6 +19,22 @@ }; }; +&dra7_pmx_core { + i2c1_pins: pinmux_i2c1_pins { + pinctrl-single,pins = < + 0x400 (PIN_INPUT | MUX_MODE0) /* i2c1_sda.i2c1_sda */ + 0x404 (PIN_INPUT | MUX_MODE0) /* i2c1_scl.i2c1_scl */ + >; + }; +}; + +&i2c1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + clock-frequency = <400000>; +}; + &uart1 { status = "okay"; }; -- cgit v0.10.2 From b359c4264c64909867c2005bc71cbc7431d2d464 Mon Sep 17 00:00:00 2001 From: Keerthy J Date: Mon, 28 Jul 2014 11:48:54 +0530 Subject: ARM: dts: dra72-evm: Add tps65917 PMIC node DRA72x-evm uses TPS65917 PMIC. Add the node. NOTE: LDO2 is actually unused, but the usage if any is expected to be between 1.8 to 3.3v IO voltage. So define the node. NOTE: Interrupt used is crossbar number based. Tested-by: Lokesh Vutla Signed-off-by: Nishanth Menon Signed-off-by: Keerthy Tested-by: Nishanth Menon Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/dra72-evm.dts b/arch/arm/boot/dts/dra72-evm.dts index 1e12862..4107428 100644 --- a/arch/arm/boot/dts/dra72-evm.dts +++ b/arch/arm/boot/dts/dra72-evm.dts @@ -33,6 +33,110 @@ pinctrl-names = "default"; pinctrl-0 = <&i2c1_pins>; clock-frequency = <400000>; + + tps65917: tps65917@58 { + compatible = "ti,tps65917"; + reg = <0x58>; + + interrupts = ; /* IRQ_SYS_1N */ + interrupt-parent = <&gic>; + interrupt-controller; + #interrupt-cells = <2>; + + ti,system-power-controller; + + tps65917_pmic { + compatible = "ti,tps65917-pmic"; + + regulators { + smps1_reg: smps1 { + /* VDD_MPU */ + regulator-name = "smps1"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1250000>; + regulator-always-on; + regulator-boot-on; + }; + + smps2_reg: smps2 { + /* VDD_CORE */ + regulator-name = "smps2"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1030000>; + regulator-boot-on; + regulator-always-on; + }; + + smps3_reg: smps3 { + /* VDD_GPU IVA DSPEVE */ + regulator-name = "smps3"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1250000>; + regulator-boot-on; + regulator-always-on; + }; + + smps4_reg: smps4 { + /* VDDS1V8 */ + regulator-name = "smps4"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + smps5_reg: smps5 { + /* VDD_DDR */ + regulator-name = "smps5"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1_reg: ldo1 { + /* LDO1_OUT --> SDIO */ + regulator-name = "ldo1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + }; + + ldo2_reg: ldo2 { + /* LDO2_OUT --> TP1017 (UNUSED) */ + regulator-name = "ldo2"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + ldo3_reg: ldo3 { + /* VDDA_1V8_PHY */ + regulator-name = "ldo3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo5_reg: ldo5 { + /* VDDA_1V8_PLL */ + regulator-name = "ldo5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo4_reg: ldo4 { + /* VDDA_3V_USB: VDDA_USBHS33 */ + regulator-name = "ldo4"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + }; + }; + }; + }; }; &uart1 { -- cgit v0.10.2 From 0e0cb99d17614711834aa8b4c6b397bf8b8596a5 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Mon, 18 Aug 2014 14:07:55 -0500 Subject: ARM: OMAP2+: board-generic: add support for AM57xx family AM57xx processor family are variants of DRA7 family of processors and targetted at industrial and non-automotive applications. Signed-off-by: Nishanth Menon Signed-off-by: Tony Lindgren diff --git a/Documentation/devicetree/bindings/arm/omap/omap.txt b/Documentation/devicetree/bindings/arm/omap/omap.txt index 0edc903..ddd9bcd 100644 --- a/Documentation/devicetree/bindings/arm/omap/omap.txt +++ b/Documentation/devicetree/bindings/arm/omap/omap.txt @@ -85,6 +85,18 @@ SoCs: - DRA722 compatible = "ti,dra722", "ti,dra72", "ti,dra7" +- AM5728 + compatible = "ti,am5728", "ti,dra742", "ti,dra74", "ti,dra7" + +- AM5726 + compatible = "ti,am5726", "ti,dra742", "ti,dra74", "ti,dra7" + +- AM5718 + compatible = "ti,am5718", "ti,dra722", "ti,dra72", "ti,dra7" + +- AM5716 + compatible = "ti,am5716", "ti,dra722", "ti,dra72", "ti,dra7" + - AM4372 compatible = "ti,am4372", "ti,am43" diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c index 9480997..bdb5194 100644 --- a/arch/arm/mach-omap2/board-generic.c +++ b/arch/arm/mach-omap2/board-generic.c @@ -241,6 +241,8 @@ MACHINE_END #ifdef CONFIG_SOC_DRA7XX static const char *dra74x_boards_compat[] __initconst = { + "ti,am5728", + "ti,am5726", "ti,dra742", "ti,dra7", NULL, @@ -260,6 +262,8 @@ DT_MACHINE_START(DRA74X_DT, "Generic DRA74X (Flattened Device Tree)") MACHINE_END static const char *dra72x_boards_compat[] __initconst = { + "ti,am5718", + "ti,am5716", "ti,dra722", NULL, }; -- cgit v0.10.2 From 63dd5bc03a1ac9dd90807f6f3fc2475c0d4f046a Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Fri, 29 Aug 2014 12:40:03 +0200 Subject: ARM: OMAP2+: tao3530: Add pdata-quirk for the mmc2 internal clock Set internal clock source for MMC2 on tao3530. Signed-off-by: Stefan Roese Cc: Thorsten Eisbein Cc: Tapani Utriainen Cc: Tony Lindgren Signed-off-by: Tony Lindgren diff --git a/arch/arm/mach-omap2/pdata-quirks.c b/arch/arm/mach-omap2/pdata-quirks.c index 90c88d4..b9d091b 100644 --- a/arch/arm/mach-omap2/pdata-quirks.c +++ b/arch/arm/mach-omap2/pdata-quirks.c @@ -253,6 +253,11 @@ static void __init nokia_n900_legacy_init(void) } } + +static void __init omap3_tao3530_legacy_init(void) +{ + hsmmc2_internal_input_clk(); +} #endif /* CONFIG_ARCH_OMAP3 */ #ifdef CONFIG_ARCH_OMAP4 @@ -377,6 +382,7 @@ static struct pdata_init pdata_quirks[] __initdata = { { "ti,omap3-evm-37xx", omap3_evm_legacy_init, }, { "ti,omap3-zoom3", omap3_zoom_legacy_init, }, { "ti,am3517-evm", am3517_evm_legacy_init, }, + { "technexion,omap3-tao3530", omap3_tao3530_legacy_init, }, #endif #ifdef CONFIG_ARCH_OMAP4 { "ti,omap4-sdp", omap4_sdp_legacy_init, }, -- cgit v0.10.2 From 30d95c6d70920348c58649c35a8d41915cd7db9c Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Fri, 29 Aug 2014 12:40:04 +0200 Subject: ARM: dts: omap3: Add Technexion TAO3530 SOM omap3-tao3530.dtsi The Technexion TAO3530 is a OMAP3530 based SOM. This patch adds the basic support for it as an dtsi file which can be included by baseboard equipped with this SOM. E.g. the Technexion Thunder baseboard. Signed-off-by: Stefan Roese Cc: Thorsten Eisbein Cc: Tapani Utriainen Cc: Tony Lindgren Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/omap3-tao3530.dtsi b/arch/arm/boot/dts/omap3-tao3530.dtsi new file mode 100644 index 0000000..b30f387 --- /dev/null +++ b/arch/arm/boot/dts/omap3-tao3530.dtsi @@ -0,0 +1,337 @@ +/* + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2014 Stefan Roese + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/dts-v1/; + +#include "omap34xx-hs.dtsi" + +/ { + cpus { + cpu@0 { + cpu0-supply = <&vcc>; + }; + }; + + memory { + device_type = "memory"; + reg = <0x80000000 0x10000000>; /* 256 MB */ + }; + + /* HS USB Port 2 Power */ + hsusb2_power: hsusb2_power_reg { + compatible = "regulator-fixed"; + regulator-name = "hsusb2_vbus"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&twl_gpio 18 0>; /* GPIO LEDA */ + startup-delay-us = <70000>; + }; + + /* HS USB Host PHY on PORT 2 */ + hsusb2_phy: hsusb2_phy { + compatible = "usb-nop-xceiv"; + reset-gpios = <&gpio6 2 GPIO_ACTIVE_LOW>; /* gpio_162 */ + vcc-supply = <&hsusb2_power>; + }; + + sound { + compatible = "ti,omap-twl4030"; + ti,model = "omap3beagle"; + + /* McBSP2 is used for onboard sound, same as on beagle */ + ti,mcbsp = <&mcbsp2>; + ti,codec = <&twl_audio>; + }; + + /* Regulator to enable/switch the vcc of the Wifi module */ + mmc2_sdio_poweron: regulator-mmc2-sdio-poweron { + compatible = "regulator-fixed"; + regulator-name = "regulator-mmc2-sdio-poweron"; + regulator-min-microvolt = <3150000>; + regulator-max-microvolt = <3150000>; + gpio = <&gpio5 29 GPIO_ACTIVE_LOW>; /* gpio_157 */ + enable-active-low; + startup-delay-us = <10000>; + }; +}; + +&omap3_pmx_core { + hsusbb2_pins: pinmux_hsusbb2_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */ + OMAP3_CORE1_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */ + OMAP3_CORE1_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */ + OMAP3_CORE1_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */ + OMAP3_CORE1_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */ + OMAP3_CORE1_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */ + OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi1_cs3.hsusb2_data2 */ + OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_clk.hsusb2_data7 */ + OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_simo.hsusb2_data4 */ + OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_somi.hsusb2_data5 */ + OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs0.hsusb2_data6 */ + OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs1.hsusb2_data3 */ + >; + }; + + mmc1_pins: pinmux_mmc1_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ + OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ + OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */ + OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */ + OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */ + OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */ + OMAP3_CORE1_IOPAD(0x2150, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat4.sdmmc1_dat4 */ + OMAP3_CORE1_IOPAD(0x2152, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat5.sdmmc1_dat5 */ + OMAP3_CORE1_IOPAD(0x2154, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat6.sdmmc1_dat6 */ + OMAP3_CORE1_IOPAD(0x2156, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat7.sdmmc1_dat7 */ + >; + }; + + mmc2_pins: pinmux_mmc2_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */ + OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */ + OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */ + OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */ + OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */ + OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */ + >; + }; + + /* wlan GPIO output for WLAN_EN */ + wlan_gpio: pinmux_wlan_gpio { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x218e, PIN_OUTPUT | MUX_MODE4) /* mcbsp1_fsr gpio_157 */ + >; + }; + + uart3_pins: pinmux_uart3_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ + OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */ + >; + }; + + i2c3_pins: pinmux_i2c3_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_scl.i2c3_scl */ + OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_sda.i2c3_sda */ + >; + }; + + mcspi1_pins: pinmux_mcspi1_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x21c8, PIN_INPUT | MUX_MODE0) /* mcspi1_clk.mcspi1_clk */ + OMAP3_CORE1_IOPAD(0x21ca, PIN_OUTPUT | MUX_MODE0) /* mcspi1_simo.mcspi1_simo */ + OMAP3_CORE1_IOPAD(0x21cc, PIN_INPUT_PULLUP | MUX_MODE0) /* mcspi1_somi.mcspi1_somi */ + OMAP3_CORE1_IOPAD(0x21ce, PIN_OUTPUT | MUX_MODE0) /* mcspi1_cs0.mcspi1_cs0 */ + >; + }; + + mcspi3_pins: pinmux_mcspi3_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x25dc, PIN_OUTPUT | MUX_MODE1) /* etk_d0.mcspi3_simo gpio14 INPUT | MODE1 */ + OMAP3_CORE1_IOPAD(0x25de, PIN_INPUT_PULLUP | MUX_MODE1) /* etk_d1.mcspi3_somi gpio15 INPUT | MODE1 */ + OMAP3_CORE1_IOPAD(0x25e0, PIN_OUTPUT | MUX_MODE1) /* etk_d2.mcspi3_cs0 gpio16 INPUT | MODE1 */ + OMAP3_CORE1_IOPAD(0x25e2, PIN_INPUT | MUX_MODE1) /* etk_d3.mcspi3_clk gpio17 INPUT | MODE1 */ + >; + }; + + mcbsp3_pins: pinmux_mcbsp3_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x216c, PIN_OUTPUT | MUX_MODE0) /* mcbsp3_dx.uart2_cts */ + OMAP3_CORE1_IOPAD(0x216e, PIN_INPUT | MUX_MODE0) /* mcbsp3_dr.uart2_rts */ + OMAP3_CORE1_IOPAD(0x2170, PIN_INPUT | MUX_MODE0) /* mcbsp3_clk.uart2_tx */ + OMAP3_CORE1_IOPAD(0x2172, PIN_INPUT | MUX_MODE0) /* mcbsp3_fsx.uart2_rx */ + >; + }; +}; + +/* McBSP1: mux'ed with GPIO158 as clock for HA-DSP */ +&mcbsp1 { + status = "disabled"; +}; + +&mcbsp2 { + status = "okay"; +}; + +&i2c1 { + clock-frequency = <2600000>; + + twl: twl@48 { + reg = <0x48>; + interrupts = <7>; /* SYS_NIRQ cascaded to intc */ + interrupt-parent = <&intc>; + + twl_audio: audio { + compatible = "ti,twl4030-audio"; + codec { + }; + }; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_pins>; +}; + +&mcspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&mcspi1_pins>; + + spidev@0 { + compatible = "spidev"; + spi-max-frequency = <48000000>; + reg = <0>; + spi-cpha; + }; +}; + +&mcspi3 { + pinctrl-names = "default"; + pinctrl-0 = <&mcspi3_pins>; + + spidev@0 { + compatible = "spidev"; + spi-max-frequency = <48000000>; + reg = <0>; + spi-cpha; + }; +}; + +#include "twl4030.dtsi" +#include "twl4030_omap3.dtsi" + +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; + vmmc-supply = <&vmmc1>; + vmmc_aux-supply = <&vsim>; + cd-gpios = <&twl_gpio 0 0>; + bus-width = <8>; +}; + +// WiFi (Marvell 88W8686) on MMC2/SDIO +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_pins>; + vmmc-supply = <&mmc2_sdio_poweron>; + non-removable; + bus-width = <4>; + cap-power-off-card; +}; + +&mmc3 { + status = "disabled"; +}; + +&usbhshost { + port2-mode = "ehci-phy"; +}; + +&usbhsehci { + phys = <0 &hsusb2_phy>; +}; + +&twl_gpio { + ti,use-leds; + /* pullups: BIT(1) */ + ti,pullups = <0x000002>; + /* + * pulldowns: + * BIT(2), BIT(6), BIT(7), BIT(8), BIT(13) + * BIT(15), BIT(16), BIT(17) + */ + ti,pulldowns = <0x03a1c4>; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins>; +}; + +&mcbsp3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcbsp3_pins>; +}; + +&gpmc { + ranges = <0 0 0x00000000 0x01000000>; + + nand@0,0 { + reg = <0 0 0>; /* CS0, offset 0 */ + nand-bus-width = <16>; + gpmc,device-width = <2>; /* GPMC_DEVWIDTH_16BIT */ + ti,nand-ecc-opt = "sw"; + + gpmc,cs-on-ns = <0>; + gpmc,cs-rd-off-ns = <36>; + gpmc,cs-wr-off-ns = <36>; + gpmc,adv-on-ns = <6>; + gpmc,adv-rd-off-ns = <24>; + gpmc,adv-wr-off-ns = <36>; + gpmc,oe-on-ns = <6>; + gpmc,oe-off-ns = <48>; + gpmc,we-on-ns = <6>; + gpmc,we-off-ns = <30>; + gpmc,rd-cycle-ns = <72>; + gpmc,wr-cycle-ns = <72>; + gpmc,access-ns = <54>; + gpmc,wr-access-ns = <30>; + + #address-cells = <1>; + #size-cells = <1>; + + x-loader@0 { + label = "X-Loader"; + reg = <0 0x80000>; + }; + + bootloaders@80000 { + label = "U-Boot"; + reg = <0x80000 0x1e0000>; + }; + + bootloaders_env@260000 { + label = "U-Boot Env"; + reg = <0x260000 0x20000>; + }; + + kernel@280000 { + label = "Kernel"; + reg = <0x280000 0x400000>; + }; + + filesystem@680000 { + label = "File System"; + reg = <0x680000 0xf980000>; + }; + }; +}; + +&usb_otg_hs { + interface-type = <0>; + usb-phy = <&usb2_phy>; + phys = <&usb2_phy>; + phy-names = "usb2-phy"; + mode = <3>; + power = <50>; +}; + +&vaux2 { + regulator-name = "vdd_ehci"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; +}; -- cgit v0.10.2 From d3a7a7479f149492b151516d62fff42328446e04 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Fri, 29 Aug 2014 12:40:05 +0200 Subject: ARM: dts: omap3: Add Technexion Thunder support (TAO3530 SOM based) This baseboard is equipped with the Technexion TAO35030 SOM. So includes this dtsi. Some Thunder specific features are: - LCD panel Signed-off-by: Stefan Roese Cc: Thorsten Eisbein Cc: Tapani Utriainen Cc: Tony Lindgren Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index ca10479..2026f307 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -311,6 +311,7 @@ dtb-$(CONFIG_ARCH_OMAP3) += am3517-craneboard.dtb \ omap3-sbc-t3517.dtb \ omap3-sbc-t3530.dtb \ omap3-sbc-t3730.dtb \ + omap3-thunder.dtb \ omap3-zoom3.dtb dtb-$(CONFIG_SOC_AM33XX) += am335x-base0033.dtb \ am335x-bone.dtb \ diff --git a/arch/arm/boot/dts/omap3-thunder.dts b/arch/arm/boot/dts/omap3-thunder.dts new file mode 100644 index 0000000..d659515 --- /dev/null +++ b/arch/arm/boot/dts/omap3-thunder.dts @@ -0,0 +1,129 @@ +/* + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2014 Stefan Roese + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "omap3-tao3530.dtsi" + +/ { + model = "TI OMAP3 Thunder baseboard with TAO3530 SOM"; + compatible = "technexion,omap3-thunder", "technexion,omap3-tao3530", "ti,omap34xx", "ti,omap3"; +}; + +&omap3_pmx_core { + dss_dpi_pins: pinmux_dss_dpi_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ + OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ + OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ + OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ + OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */ + OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */ + OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */ + OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */ + OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */ + OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */ + OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */ + OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */ + OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */ + OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */ + OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */ + OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */ + OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */ + OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */ + OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */ + OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */ + OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */ + OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */ + OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE0) /* dss_data18.dss_data18 */ + OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE0) /* dss_data19.dss_data19 */ + OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE0) /* dss_data20.dss_data20 */ + OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE0) /* dss_data21.dss_data21 */ + OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */ + OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */ + >; + }; + + lte430_pins: pinmux_lte430_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2168, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat6.gpio_138 */ + >; + }; + + backlight_pins: pinmux_backlight_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x216a, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat7.gpio_139 */ + >; + }; +}; + +/* Needed to power the DPI pins */ +&vpll2 { + regulator-always-on; +}; + +&dss { + status = "ok"; + + pinctrl-names = "default"; + pinctrl-0 = <&dss_dpi_pins>; + + port { + dpi_out: endpoint { + remote-endpoint = <&lcd_in>; + data-lines = <24>; + }; + }; +}; + +/ { + aliases { + display0 = &lcd0; + }; + + lcd0: display@0 { + compatible = "samsung,lte430wq-f0c", "panel-dpi"; + label = "lcd"; + + pinctrl-names = "default"; + pinctrl-0 = <<e430_pins>; + enable-gpios = <&gpio5 10 GPIO_ACTIVE_LOW>; /* gpio_138 */ + + port { + lcd_in: endpoint { + remote-endpoint = <&dpi_out>; + }; + }; + + panel-timing { + clock-frequency = <9000000>; + hactive = <480>; + vactive = <272>; + hfront-porch = <3>; + hback-porch = <2>; + hsync-len = <42>; + vback-porch = <2>; + vfront-porch = <3>; + vsync-len = <11>; + + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <1>; + }; + }; + + backlight { + compatible = "gpio-backlight"; + + pinctrl-names = "default"; + pinctrl-0 = <&backlight_pins>; + gpios = <&gpio5 11 GPIO_ACTIVE_HIGH>; /* gpio_139 */ + + default-on; + }; +}; -- cgit v0.10.2 From e2459357f613f681a516e7c67ef8336bc475a482 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Fri, 29 Aug 2014 12:40:06 +0200 Subject: ARM: dts: omap3: Add HEAD acoustics omap3-ha.dts and omap3-ha-lcd.dts (TAO3530 based) These baseboards are equipped with the Technexion TAO35030 SOM. So they include this dtsi. The common parts are extracted into an "common" dtsi file. The main difference between both boards is, that the *lcd has DSS support enabled for the LCD. Some HEAD acoustics specific features are: - LED handling - Special FPGA/DSP audio driver (not included in this series) - powerdown GPIO Signed-off-by: Stefan Roese Cc: Thorsten Eisbein Cc: Tapani Utriainen Cc: Tony Lindgren Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 2026f307..ee399dc 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -289,6 +289,8 @@ dtb-$(CONFIG_ARCH_OMAP3) += am3517-craneboard.dtb \ omap3-gta04a3.dtb \ omap3-gta04a4.dtb \ omap3-gta04a5.dtb \ + omap3-ha.dtb \ + omap3-ha-lcd.dtb \ omap3-igep0020.dtb \ omap3-igep0030.dtb \ omap3-ldp.dtb \ diff --git a/arch/arm/boot/dts/omap3-ha-common.dtsi b/arch/arm/boot/dts/omap3-ha-common.dtsi new file mode 100644 index 0000000..bd66545 --- /dev/null +++ b/arch/arm/boot/dts/omap3-ha-common.dtsi @@ -0,0 +1,88 @@ +/* + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2014 Stefan Roese + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "omap3-tao3530.dtsi" + +/ { + gpio_poweroff { + pinctrl-names = "default"; + pinctrl-0 = <&poweroff_pins>; + + compatible = "gpio-poweroff"; + gpios = <&gpio6 8 GPIO_ACTIVE_LOW>; /* GPIO 168 */ + }; +}; + +&omap3_pmx_core { + sound2_pins: pinmux_sound2_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x209e, PIN_OUTPUT | MUX_MODE4) /* gpmc_d8 gpio_44 */ + >; + }; + + led_blue_pins: pinmux_led_blue_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2110, PIN_OUTPUT | MUX_MODE4) /* cam_xclka gpio_96, LED blue */ + >; + }; + + led_green_pins: pinmux_led_green_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2126, PIN_OUTPUT | MUX_MODE4) /* cam_d8 gpio_107, LED green */ + >; + }; + + led_red_pins: pinmux_led_red_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x212e, PIN_OUTPUT_PULLUP | MUX_MODE4) /* cam_xclkb gpio_111, LED red */ + >; + }; + + poweroff_pins: pinmux_poweroff_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x21be, PIN_OUTPUT_PULLUP | MUX_MODE4) /* i2c2_scl gpio_168 */ + >; + }; + + powerdown_input_pins: pinmux_powerdown_input_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x21c0, PIN_INPUT_PULLUP | MUX_MODE4) /* i2c2_sda gpio_183 */ + >; + }; + + fpga_boot0_pins: fpga_boot0_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x211a, PIN_INPUT | MUX_MODE4) /* cam_d2 gpio_101 */ + OMAP3_CORE1_IOPAD(0x211c, PIN_OUTPUT | MUX_MODE4) /* cam_d3 gpio_102 */ + OMAP3_CORE1_IOPAD(0x211e, PIN_OUTPUT | MUX_MODE4) /* cam_d4 gpio_103 */ + OMAP3_CORE1_IOPAD(0x2120, PIN_INPUT_PULLUP | MUX_MODE4) /* cam_d5 gpio_104 */ + >; + }; + + fpga_boot1_pins: fpga_boot1_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x20a2, PIN_INPUT | MUX_MODE4) /* gpmc_d10 gpio_46 */ + OMAP3_CORE1_IOPAD(0x20a4, PIN_OUTPUT | MUX_MODE4) /* gpmc_d11 gpio_47 */ + OMAP3_CORE1_IOPAD(0x20a6, PIN_OUTPUT | MUX_MODE4) /* gpmc_d12 gpio_48 */ + OMAP3_CORE1_IOPAD(0x20a8, PIN_INPUT_PULLUP | MUX_MODE4) /* gpmc_d13 gpio_49 */ + >; + }; +}; + +/* I2C2: mux'ed with GPIO168 which is connected to nKILL_POWER */ +&i2c2 { + status = "disabled"; +}; + +&i2c3 { + clock-frequency = <100000>; + + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_pins>; +}; diff --git a/arch/arm/boot/dts/omap3-ha-lcd.dts b/arch/arm/boot/dts/omap3-ha-lcd.dts new file mode 100644 index 0000000..11aa28d --- /dev/null +++ b/arch/arm/boot/dts/omap3-ha-lcd.dts @@ -0,0 +1,165 @@ +/* + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2014 Stefan Roese + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "omap3-ha-common.dtsi" + +/ { + model = "TI OMAP3 HEAD acoustics LCD-baseboard with TAO3530 SOM"; + compatible = "headacoustics,omap3-ha-lcd", "technexion,omap3-tao3530", "ti,omap34xx", "ti,omap3"; +}; + +&omap3_pmx_core { + pinctrl-names = "default"; + pinctrl-0 = < + &hsusbb2_pins + &powerdown_input_pins + &fpga_boot0_pins + &fpga_boot1_pins + &led_blue_pins + &led_green_pins + &led_red_pins + &touchscreen_wake_pins + >; + + touchscreen_irq_pins: pinmux_touchscreen_irq_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2164, PIN_INPUT_PULLUP | MUX_MODE4) /* gpio_136, Touchscreen IRQ */ + >; + }; + + touchscreen_wake_pins: pinmux_touchscreen_wake_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x212c, PIN_OUTPUT_PULLUP | MUX_MODE4) /* gpio_110, Touchscreen Wake */ + >; + }; + + dss_dpi_pins: pinmux_dss_dpi_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ + OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ + OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ + OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ + OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */ + OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */ + OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */ + OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */ + OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */ + OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */ + OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */ + OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */ + OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */ + OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */ + OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */ + OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */ + OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */ + OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */ + OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */ + OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */ + OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */ + OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */ + OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE0) /* dss_data18.dss_data18 */ + OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE0) /* dss_data19.dss_data19 */ + OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE0) /* dss_data20.dss_data20 */ + OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE0) /* dss_data21.dss_data21 */ + OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */ + OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */ + >; + }; + + lte430_pins: pinmux_lte430_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2168, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat6.gpio_138 */ + >; + }; + + backlight_pins: pinmux_backlight_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x216a, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat7.gpio_139 */ + >; + }; +}; + +/* I2C2: mux'ed with GPIO168 which is connected to nKILL_POWER */ +&i2c2 { + status = "disabled"; +}; + +&i2c3 { + clock-frequency = <100000>; + + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_pins>; +}; + +/* Needed to power the DPI pins */ +&vpll2 { + regulator-always-on; +}; + +&dss { + status = "ok"; + + pinctrl-names = "default"; + pinctrl-0 = <&dss_dpi_pins>; + + port { + dpi_out: endpoint { + remote-endpoint = <&lcd_in>; + data-lines = <24>; + }; + }; +}; + +/ { + aliases { + display0 = &lcd0; + }; + + lcd0: display@0 { + compatible = "panel-dpi"; + label = "lcd"; + + pinctrl-names = "default"; + pinctrl-0 = <<e430_pins>; + enable-gpios = <&gpio5 10 GPIO_ACTIVE_LOW>; /* gpio_138 */ + + port { + lcd_in: endpoint { + remote-endpoint = <&dpi_out>; + }; + }; + + panel-timing { + clock-frequency = <31250000>; + hactive = <800>; + vactive = <480>; + hfront-porch = <40>; + hback-porch = <86>; + hsync-len = <1>; + vback-porch = <30>; + vfront-porch = <13>; + vsync-len = <3>; + + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <1>; + }; + }; + + backlight { + compatible = "gpio-backlight"; + + pinctrl-names = "default"; + pinctrl-0 = <&backlight_pins>; + gpios = <&gpio5 11 GPIO_ACTIVE_HIGH>; /* gpio_139 */ + + default-on; + }; +}; diff --git a/arch/arm/boot/dts/omap3-ha.dts b/arch/arm/boot/dts/omap3-ha.dts new file mode 100644 index 0000000..fde3256 --- /dev/null +++ b/arch/arm/boot/dts/omap3-ha.dts @@ -0,0 +1,28 @@ +/* + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2014 Stefan Roese + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "omap3-ha-common.dtsi" + +/ { + model = "TI OMAP3 HEAD acoustics baseboard with TAO3530 SOM"; + compatible = "headacoustics,omap3-ha", "technexion,omap3-tao3530", "ti,omap34xx", "ti,omap3"; +}; + +&omap3_pmx_core { + pinctrl-names = "default"; + pinctrl-0 = < + &hsusbb2_pins + &powerdown_input_pins + &fpga_boot0_pins + &fpga_boot1_pins + &led_blue_pins + &led_green_pins + &led_red_pins + >; +}; -- cgit v0.10.2 From 84ace6741bd9b957d3b6dc39fe63fee0f1bd5039 Mon Sep 17 00:00:00 2001 From: Tomi Valkeinen Date: Thu, 4 Sep 2014 09:28:32 +0300 Subject: ARM: dts: omap5.dtsi: add DSS RFBI node The RFBI node for OMAP DSS was left out when adding the rest of the DSS nodes, because it was not clear how to set up the clocks for the RFBI. However, it seems that if there is a HWMOD for a device, we also need a DT node for it. Otherwise, at boot, we get: WARNING: CPU: 0 PID: 1 at arch/arm/mach-omap2/omap_hwmod.c:2542 _init+0x464/0x4e0() omap_hwmod: dss_rfbi: doesn't have mpu register target base Now that v3.17-rc3 contains a fix 8fd46439e1f5 ("ARM: dts: omap54xx-clocks: Fix the l3 and l4 clock rates") for the L3 ICLK required by the RFBI, let's add the RFBI node to get rid of the warning. Signed-off-by: Tomi Valkeinen [tony@atomide.com: updated description per comments from Nishant] Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi index fc8df17..1e6ff61 100644 --- a/arch/arm/boot/dts/omap5.dtsi +++ b/arch/arm/boot/dts/omap5.dtsi @@ -945,6 +945,15 @@ clock-names = "fck"; }; + rfbi: encoder@58002000 { + compatible = "ti,omap5-rfbi"; + reg = <0x58002000 0x100>; + status = "disabled"; + ti,hwmods = "dss_rfbi"; + clocks = <&dss_dss_clk>, <&l3_iclk_div>; + clock-names = "fck", "ick"; + }; + dsi1: encoder@58004000 { compatible = "ti,omap5-dsi"; reg = <0x58004000 0x200>, -- cgit v0.10.2 From 91890c0e89bed0d24e4fe50b97dd8fc9c9f81283 Mon Sep 17 00:00:00 2001 From: Dmitry Lifshitz Date: Thu, 4 Sep 2014 16:02:53 +0300 Subject: ARM: dts: sbc-t54: fix model property CM-T54 CoM can be used with various custom baseboards, other than SB-T54 (supplied with SBC-T54 single board computer). Update model property of SBC-T54 DT to clarify this. Signed-off-by: Dmitry Lifshitz Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/omap5-sbc-t54.dts b/arch/arm/boot/dts/omap5-sbc-t54.dts index aa98fea..8e89793 100644 --- a/arch/arm/boot/dts/omap5-sbc-t54.dts +++ b/arch/arm/boot/dts/omap5-sbc-t54.dts @@ -1,11 +1,11 @@ /* - * Suppport for CompuLab SBC-T54 with CM-T54 + * Suppport for CompuLab CM-T54 on SB-T54 baseboard */ #include "omap5-cm-t54.dts" / { - model = "CompuLab SBC-T54 with CM-T54"; + model = "CompuLab CM-T54 on SB-T54"; compatible = "compulab,omap5-sbc-t54", "compulab,omap5-cm-t54", "ti,omap5"; }; -- cgit v0.10.2 From 83c9b2afe66abf5dc6dab68da738557001fb5660 Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Fri, 5 Sep 2014 22:12:05 +0100 Subject: ARM: dts: am335x-boneblack: Add names for remaining regulators Add regulator-name properties for the regulators that don't have them, allowing the kernel to display the name from the schematic rather than the name of the regulator on the PMIC in order to improve diagnostics. Signed-off-by: Mark Brown Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/am335x-bone-common.dtsi b/arch/arm/boot/dts/am335x-bone-common.dtsi index bde1777..fe983d2 100644 --- a/arch/arm/boot/dts/am335x-bone-common.dtsi +++ b/arch/arm/boot/dts/am335x-bone-common.dtsi @@ -227,6 +227,7 @@ &tps { regulators { dcdc1_reg: regulator@0 { + regulator-name = "vdds_dpr"; regulator-always-on; }; @@ -249,18 +250,22 @@ }; ldo1_reg: regulator@3 { + regulator-name = "vio,vrtc,vdds"; regulator-always-on; }; ldo2_reg: regulator@4 { + regulator-name = "vdd_3v3aux"; regulator-always-on; }; ldo3_reg: regulator@5 { + regulator-name = "vdd_1v8"; regulator-always-on; }; ldo4_reg: regulator@6 { + regulator-name = "vdd_3v3a"; regulator-always-on; }; }; -- cgit v0.10.2 From 0dce5454d5c258582a7da5590332d9e085886bf7 Mon Sep 17 00:00:00 2001 From: Ulrich Hecht Date: Fri, 5 Sep 2014 12:23:48 +0200 Subject: ARM: shmobile: Initial r8a7794 SoC device tree Signed-off-by: Hisashi Nakamura [uli: reduced to minimum, added cmt, enabled scif2, split off board part] Signed-off-by: Ulrich Hecht Acked-by: Magnus Damm Signed-off-by: Simon Horman diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi new file mode 100644 index 0000000..d4e8bce --- /dev/null +++ b/arch/arm/boot/dts/r8a7794.dtsi @@ -0,0 +1,531 @@ +/* + * Device Tree Source for the r8a7794 SoC + * + * Copyright (C) 2014 Renesas Electronics Corporation + * Copyright (C) 2014 Ulrich Hecht + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +#include +#include +#include + +/ { + compatible = "renesas,r8a7794"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0>; + clock-frequency = <1000000000>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <1>; + clock-frequency = <1000000000>; + }; + }; + + gic: interrupt-controller@f1001000 { + compatible = "arm,cortex-a7-gic"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0 0xf1001000 0 0x1000>, + <0 0xf1002000 0 0x1000>, + <0 0xf1004000 0 0x2000>, + <0 0xf1006000 0 0x2000>; + interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; + }; + + cmt0: timer@ffca0000 { + compatible = "renesas,cmt-48-gen2"; + reg = <0 0xffca0000 0 0x1004>; + interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>, + <0 143 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp1_clks R8A7794_CLK_CMT0>; + clock-names = "fck"; + + renesas,channels-mask = <0x60>; + + status = "disabled"; + }; + + cmt1: timer@e6130000 { + compatible = "renesas,cmt-48-gen2"; + reg = <0 0xe6130000 0 0x1004>; + interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>, + <0 121 IRQ_TYPE_LEVEL_HIGH>, + <0 122 IRQ_TYPE_LEVEL_HIGH>, + <0 123 IRQ_TYPE_LEVEL_HIGH>, + <0 124 IRQ_TYPE_LEVEL_HIGH>, + <0 125 IRQ_TYPE_LEVEL_HIGH>, + <0 126 IRQ_TYPE_LEVEL_HIGH>, + <0 127 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A7794_CLK_CMT1>; + clock-names = "fck"; + + renesas,channels-mask = <0xff>; + + status = "disabled"; + }; + + irqc0: interrupt-controller@e61c0000 { + compatible = "renesas,irqc-r8a7794", "renesas,irqc"; + #interrupt-cells = <2>; + interrupt-controller; + reg = <0 0xe61c0000 0 0x200>; + interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>, + <0 1 IRQ_TYPE_LEVEL_HIGH>, + <0 2 IRQ_TYPE_LEVEL_HIGH>, + <0 3 IRQ_TYPE_LEVEL_HIGH>, + <0 12 IRQ_TYPE_LEVEL_HIGH>, + <0 13 IRQ_TYPE_LEVEL_HIGH>, + <0 14 IRQ_TYPE_LEVEL_HIGH>, + <0 15 IRQ_TYPE_LEVEL_HIGH>, + <0 16 IRQ_TYPE_LEVEL_HIGH>, + <0 17 IRQ_TYPE_LEVEL_HIGH>; + }; + + scifa0: serial@e6c40000 { + compatible = "renesas,scifa-r8a7794", "renesas,scifa"; + reg = <0 0xe6c40000 0 64>; + interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp2_clks R8A7794_CLK_SCIFA0>; + clock-names = "sci_ick"; + status = "disabled"; + }; + + scifa1: serial@e6c50000 { + compatible = "renesas,scifa-r8a7794", "renesas,scifa"; + reg = <0 0xe6c50000 0 64>; + interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp2_clks R8A7794_CLK_SCIFA1>; + clock-names = "sci_ick"; + status = "disabled"; + }; + + scifa2: serial@e6c60000 { + compatible = "renesas,scifa-r8a7794", "renesas,scifa"; + reg = <0 0xe6c60000 0 64>; + interrupts = <0 151 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp2_clks R8A7794_CLK_SCIFA2>; + clock-names = "sci_ick"; + status = "disabled"; + }; + + scifa3: serial@e6c70000 { + compatible = "renesas,scifa-r8a7794", "renesas,scifa"; + reg = <0 0xe6c70000 0 64>; + interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp11_clks R8A7794_CLK_SCIFA3>; + clock-names = "sci_ick"; + status = "disabled"; + }; + + scifa4: serial@e6c78000 { + compatible = "renesas,scifa-r8a7794", "renesas,scifa"; + reg = <0 0xe6c78000 0 64>; + interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp11_clks R8A7794_CLK_SCIFA4>; + clock-names = "sci_ick"; + status = "disabled"; + }; + + scifa5: serial@e6c80000 { + compatible = "renesas,scifa-r8a7794", "renesas,scifa"; + reg = <0 0xe6c80000 0 64>; + interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp11_clks R8A7794_CLK_SCIFA5>; + clock-names = "sci_ick"; + status = "disabled"; + }; + + scifb0: serial@e6c20000 { + compatible = "renesas,scifb-r8a7794", "renesas,scifb"; + reg = <0 0xe6c20000 0 64>; + interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp2_clks R8A7794_CLK_SCIFB0>; + clock-names = "sci_ick"; + status = "disabled"; + }; + + scifb1: serial@e6c30000 { + compatible = "renesas,scifb-r8a7794", "renesas,scifb"; + reg = <0 0xe6c30000 0 64>; + interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp2_clks R8A7794_CLK_SCIFB1>; + clock-names = "sci_ick"; + status = "disabled"; + }; + + scifb2: serial@e6ce0000 { + compatible = "renesas,scifb-r8a7794", "renesas,scifb"; + reg = <0 0xe6ce0000 0 64>; + interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp2_clks R8A7794_CLK_SCIFB2>; + clock-names = "sci_ick"; + status = "disabled"; + }; + + scif0: serial@e6e60000 { + compatible = "renesas,scif-r8a7794", "renesas,scif"; + reg = <0 0xe6e60000 0 64>; + interrupts = <0 152 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp7_clks R8A7794_CLK_SCIF0>; + clock-names = "sci_ick"; + status = "disabled"; + }; + + scif1: serial@e6e68000 { + compatible = "renesas,scif-r8a7794", "renesas,scif"; + reg = <0 0xe6e68000 0 64>; + interrupts = <0 153 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp7_clks R8A7794_CLK_SCIF1>; + clock-names = "sci_ick"; + status = "disabled"; + }; + + scif2: serial@e6e58000 { + compatible = "renesas,scif-r8a7794", "renesas,scif"; + reg = <0 0xe6e58000 0 64>; + interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp7_clks R8A7794_CLK_SCIF2>; + clock-names = "sci_ick"; + status = "disabled"; + }; + + scif3: serial@e6ea8000 { + compatible = "renesas,scif-r8a7794", "renesas,scif"; + reg = <0 0xe6ea8000 0 64>; + interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp7_clks R8A7794_CLK_SCIF3>; + clock-names = "sci_ick"; + status = "disabled"; + }; + + scif4: serial@e6ee0000 { + compatible = "renesas,scif-r8a7794", "renesas,scif"; + reg = <0 0xe6ee0000 0 64>; + interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp7_clks R8A7794_CLK_SCIF4>; + clock-names = "sci_ick"; + status = "disabled"; + }; + + scif5: serial@e6ee8000 { + compatible = "renesas,scif-r8a7794", "renesas,scif"; + reg = <0 0xe6ee8000 0 64>; + interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp7_clks R8A7794_CLK_SCIF5>; + clock-names = "sci_ick"; + status = "disabled"; + }; + + hscif0: serial@e62c0000 { + compatible = "renesas,hscif-r8a7794", "renesas,hscif"; + reg = <0 0xe62c0000 0 96>; + interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp7_clks R8A7794_CLK_HSCIF0>; + clock-names = "sci_ick"; + status = "disabled"; + }; + + hscif1: serial@e62c8000 { + compatible = "renesas,hscif-r8a7794", "renesas,hscif"; + reg = <0 0xe62c8000 0 96>; + interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp7_clks R8A7794_CLK_HSCIF1>; + clock-names = "sci_ick"; + status = "disabled"; + }; + + hscif2: serial@e62d0000 { + compatible = "renesas,hscif-r8a7794", "renesas,hscif"; + reg = <0 0xe62d0000 0 96>; + interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp7_clks R8A7794_CLK_HSCIF2>; + clock-names = "sci_ick"; + status = "disabled"; + }; + + clocks { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* External root clock */ + extal_clk: extal_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overriden by the board. */ + clock-frequency = <0>; + clock-output-names = "extal"; + }; + + /* Special CPG clocks */ + cpg_clocks: cpg_clocks@e6150000 { + compatible = "renesas,r8a7794-cpg-clocks", + "renesas,rcar-gen2-cpg-clocks"; + reg = <0 0xe6150000 0 0x1000>; + clocks = <&extal_clk>; + #clock-cells = <1>; + clock-output-names = "main", "pll0", "pll1", "pll3", + "lb", "qspi", "sdh", "sd0", "z"; + }; + + /* Fixed factor clocks */ + pll1_div2_clk: pll1_div2_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7794_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <2>; + clock-mult = <1>; + clock-output-names = "pll1_div2"; + }; + zg_clk: zg_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7794_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <6>; + clock-mult = <1>; + clock-output-names = "zg"; + }; + zx_clk: zx_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7794_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <3>; + clock-mult = <1>; + clock-output-names = "zx"; + }; + zs_clk: zs_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7794_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <6>; + clock-mult = <1>; + clock-output-names = "zs"; + }; + hp_clk: hp_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7794_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <12>; + clock-mult = <1>; + clock-output-names = "hp"; + }; + i_clk: i_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7794_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <2>; + clock-mult = <1>; + clock-output-names = "i"; + }; + b_clk: b_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7794_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <12>; + clock-mult = <1>; + clock-output-names = "b"; + }; + p_clk: p_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7794_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <24>; + clock-mult = <1>; + clock-output-names = "p"; + }; + cl_clk: cl_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7794_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <48>; + clock-mult = <1>; + clock-output-names = "cl"; + }; + m2_clk: m2_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7794_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <8>; + clock-mult = <1>; + clock-output-names = "m2"; + }; + imp_clk: imp_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7794_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <4>; + clock-mult = <1>; + clock-output-names = "imp"; + }; + rclk_clk: rclk_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7794_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <(48 * 1024)>; + clock-mult = <1>; + clock-output-names = "rclk"; + }; + oscclk_clk: oscclk_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7794_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <(12 * 1024)>; + clock-mult = <1>; + clock-output-names = "oscclk"; + }; + zb3_clk: zb3_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7794_CLK_PLL3>; + #clock-cells = <0>; + clock-div = <4>; + clock-mult = <1>; + clock-output-names = "zb3"; + }; + zb3d2_clk: zb3d2_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7794_CLK_PLL3>; + #clock-cells = <0>; + clock-div = <8>; + clock-mult = <1>; + clock-output-names = "zb3d2"; + }; + ddr_clk: ddr_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7794_CLK_PLL3>; + #clock-cells = <0>; + clock-div = <8>; + clock-mult = <1>; + clock-output-names = "ddr"; + }; + mp_clk: mp_clk { + compatible = "fixed-factor-clock"; + clocks = <&pll1_div2_clk>; + #clock-cells = <0>; + clock-div = <15>; + clock-mult = <1>; + clock-output-names = "mp"; + }; + cp_clk: cp_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7794_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <48>; + clock-mult = <1>; + clock-output-names = "cp"; + }; + + acp_clk: acp_clk { + compatible = "fixed-factor-clock"; + clocks = <&extal_clk>; + #clock-cells = <0>; + clock-div = <2>; + clock-mult = <1>; + clock-output-names = "acp"; + }; + + /* Gate clocks */ + mstp0_clks: mstp0_clks@e6150130 { + compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>; + clocks = <&mp_clk>; + #clock-cells = <1>; + renesas,clock-indices = ; + clock-output-names = "msiof0"; + }; + mstp1_clks: mstp1_clks@e6150134 { + compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>; + clocks = <&p_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>, + <&cp_clk>, + <&zs_clk>, <&zs_clk>, <&zs_clk>; + #clock-cells = <1>; + renesas,clock-indices = < + R8A7794_CLK_TMU1 R8A7794_CLK_TMU3 R8A7794_CLK_TMU2 + R8A7794_CLK_CMT0 R8A7794_CLK_TMU0 + >; + clock-output-names = + "tmu1", "tmu3", "tmu2", "cmt0", "tmu0"; + }; + mstp2_clks: mstp2_clks@e6150138 { + compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>; + clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, + <&mp_clk>, <&mp_clk>, <&mp_clk>; + #clock-cells = <1>; + renesas,clock-indices = < + R8A7794_CLK_SCIFA2 R8A7794_CLK_SCIFA1 R8A7794_CLK_SCIFA0 + R8A7794_CLK_MSIOF2 R8A7794_CLK_SCIFB0 R8A7794_CLK_SCIFB1 + R8A7794_CLK_MSIOF1 R8A7794_CLK_SCIFB2 + >; + clock-output-names = + "scifa2", "scifa1", "scifa0", "msiof2", "scifb0", + "scifb1", "msiof1", "scifb2"; + }; + mstp3_clks: mstp3_clks@e615013c { + compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; + clocks = <&rclk_clk>; + #clock-cells = <1>; + renesas,clock-indices = < + R8A7794_CLK_CMT1 + >; + clock-output-names = + "cmt1"; + }; + mstp7_clks: mstp7_clks@e615014c { + compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>; + clocks = <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>, + <&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>; + #clock-cells = <1>; + renesas,clock-indices = < + R8A7794_CLK_HSCIF2 R8A7794_CLK_SCIF5 + R8A7794_CLK_SCIF4 R8A7794_CLK_HSCIF1 R8A7794_CLK_HSCIF0 + R8A7794_CLK_SCIF3 R8A7794_CLK_SCIF2 R8A7794_CLK_SCIF1 + R8A7794_CLK_SCIF0 + >; + clock-output-names = + "hscif2", "scif5", "scif4", "hscif1", "hscif0", + "scif3", "scif2", "scif1", "scif0"; + }; + mstp8_clks: mstp8_clks@e6150990 { + compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>; + clocks = <&p_clk>; + #clock-cells = <1>; + renesas,clock-indices = < + R8A7794_CLK_ETHER + >; + clock-output-names = + "ether"; + }; + mstp11_clks: mstp11_clks@e615099c { + compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>; + clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>; + #clock-cells = <1>; + renesas,clock-indices = < + R8A7794_CLK_SCIFA3 R8A7794_CLK_SCIFA4 R8A7794_CLK_SCIFA5 + >; + clock-output-names = "scifa3", "scifa4", "scifa5"; + }; + }; +}; diff --git a/include/dt-bindings/clock/r8a7794-clock.h b/include/dt-bindings/clock/r8a7794-clock.h new file mode 100644 index 0000000..9ac1043 --- /dev/null +++ b/include/dt-bindings/clock/r8a7794-clock.h @@ -0,0 +1,80 @@ +/* + * Copyright (C) 2014 Renesas Electronics Corporation + * Copyright 2013 Ideas On Board SPRL + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef __DT_BINDINGS_CLOCK_R8A7794_H__ +#define __DT_BINDINGS_CLOCK_R8A7794_H__ + +/* CPG */ +#define R8A7794_CLK_MAIN 0 +#define R8A7794_CLK_PLL0 1 +#define R8A7794_CLK_PLL1 2 +#define R8A7794_CLK_PLL3 3 +#define R8A7794_CLK_LB 4 +#define R8A7794_CLK_QSPI 5 +#define R8A7794_CLK_SDH 6 +#define R8A7794_CLK_SD0 7 +#define R8A7794_CLK_Z 8 + +/* MSTP0 */ +#define R8A7794_CLK_MSIOF0 0 + +/* MSTP1 */ +#define R8A7794_CLK_TMU1 11 +#define R8A7794_CLK_TMU3 21 +#define R8A7794_CLK_TMU2 22 +#define R8A7794_CLK_CMT0 24 +#define R8A7794_CLK_TMU0 25 + +/* MSTP2 */ +#define R8A7794_CLK_SCIFA2 2 +#define R8A7794_CLK_SCIFA1 3 +#define R8A7794_CLK_SCIFA0 4 +#define R8A7794_CLK_MSIOF2 5 +#define R8A7794_CLK_SCIFB0 6 +#define R8A7794_CLK_SCIFB1 7 +#define R8A7794_CLK_MSIOF1 8 +#define R8A7794_CLK_SCIFB2 16 + +/* MSTP3 */ +#define R8A7794_CLK_CMT1 29 + +/* MSTP5 */ +#define R8A7794_CLK_THERMAL 22 +#define R8A7794_CLK_PWM 23 + +/* MSTP7 */ +#define R8A7794_CLK_HSCIF2 13 +#define R8A7794_CLK_SCIF5 14 +#define R8A7794_CLK_SCIF4 15 +#define R8A7794_CLK_HSCIF1 16 +#define R8A7794_CLK_HSCIF0 17 +#define R8A7794_CLK_SCIF3 18 +#define R8A7794_CLK_SCIF2 19 +#define R8A7794_CLK_SCIF1 20 +#define R8A7794_CLK_SCIF0 21 + +/* MSTP8 */ +#define R8A7794_CLK_ETHER 13 + +/* MSTP9 */ +#define R8A7794_CLK_GPIO6 5 +#define R8A7794_CLK_GPIO5 7 +#define R8A7794_CLK_GPIO4 8 +#define R8A7794_CLK_GPIO3 9 +#define R8A7794_CLK_GPIO2 10 +#define R8A7794_CLK_GPIO1 11 +#define R8A7794_CLK_GPIO0 12 + +/* MSTP11 */ +#define R8A7794_CLK_SCIFA3 6 +#define R8A7794_CLK_SCIFA4 7 +#define R8A7794_CLK_SCIFA5 8 + +#endif /* __DT_BINDINGS_CLOCK_R8A7794_H__ */ -- cgit v0.10.2 From a742795be9ceae2853ca71f216193f29da151da8 Mon Sep 17 00:00:00 2001 From: Ulrich Hecht Date: Fri, 5 Sep 2014 12:23:49 +0200 Subject: ARM: shmobile: Initial Alt board device tree Signed-off-by: Hisashi Nakamura [uli: reduced to minimum, added cmt, enabled scif2, split off from SoC] Signed-off-by: Ulrich Hecht Acked-by: Magnus Damm Signed-off-by: Simon Horman diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index b8c5cd3..81c1df9 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -375,7 +375,8 @@ dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += emev2-kzm9d.dtb \ r8a7791-henninger.dtb \ r8a7791-koelsch.dtb \ r8a7790-lager.dtb \ - r8a7779-marzen.dtb + r8a7779-marzen.dtb \ + r8a7794-alt.dtb dtb-$(CONFIG_ARCH_SOCFPGA) += socfpga_arria5_socdk.dtb \ socfpga_cyclone5_socdk.dtb \ socfpga_cyclone5_sockit.dtb \ diff --git a/arch/arm/boot/dts/r8a7794-alt.dts b/arch/arm/boot/dts/r8a7794-alt.dts new file mode 100644 index 0000000..79d06ef --- /dev/null +++ b/arch/arm/boot/dts/r8a7794-alt.dts @@ -0,0 +1,47 @@ +/* + * Device Tree Source for the Alt board + * + * Copyright (C) 2014 Renesas Electronics Corporation + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +/dts-v1/; +#include "r8a7794.dtsi" + +/ { + model = "Alt"; + compatible = "renesas,alt", "renesas,r8a7794"; + + aliases { + serial0 = &scif2; + }; + + chosen { + bootargs = "console=ttySC0,38400 ignore_loglevel rw root=/dev/nfs ip=dhcp"; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0 0x40000000 0 0x40000000>; + }; + + lbsc { + #address-cells = <1>; + #size-cells = <1>; + }; +}; + +&extal_clk { + clock-frequency = <20000000>; +}; + +&cmt0 { + status = "ok"; +}; + +&scif2 { + status = "ok"; +}; -- cgit v0.10.2 From 12dd3653aebe81ea205e226079afb4f119954ec0 Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Fri, 8 Aug 2014 11:55:58 +0800 Subject: ARM: dts: add rk3288 dwc2 controller support rk3288 has two kind of usb controller, this add the dwc2 controller for otg and host1. Controller can works with usb PHY default setting and Vbus on. Signed-off-by: Kever Yang Reviewed-by: Doug Anderson Tested-by: Doug Anderson Signed-off-by: Heiko Stuebner diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index 5f866e0..2ac3488 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -256,6 +256,26 @@ /* NOTE: ohci@ff520000 doesn't actually work on hardware */ + usb_host1: usb@ff540000 { + compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb", + "snps,dwc2"; + reg = <0xff540000 0x40000>; + interrupts = ; + clocks = <&cru HCLK_USBHOST1>; + clock-names = "otg"; + status = "disabled"; + }; + + usb_otg: usb@ff580000 { + compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb", + "snps,dwc2"; + reg = <0xff580000 0x40000>; + interrupts = ; + clocks = <&cru HCLK_OTG0>; + clock-names = "otg"; + status = "disabled"; + }; + usb_hsic: usb@ff5c0000 { compatible = "generic-ehci"; reg = <0xff5c0000 0x100>; -- cgit v0.10.2 From ddf8303f8d818cc002f523c7130aff2c0b1f9a2e Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Fri, 8 Aug 2014 11:55:59 +0800 Subject: ARM: dts: Enable USB host1(dwc) on rk3288-evb USB host1 port is the host A port nearby the otg port. Signed-off-by: Kever Yang Signed-off-by: Heiko Stuebner diff --git a/arch/arm/boot/dts/rk3288-evb.dtsi b/arch/arm/boot/dts/rk3288-evb.dtsi index 98b69d0..cb83cea 100644 --- a/arch/arm/boot/dts/rk3288-evb.dtsi +++ b/arch/arm/boot/dts/rk3288-evb.dtsi @@ -177,3 +177,7 @@ &usb_host0_ehci { status = "okay"; }; + +&usb_host1 { + status = "okay"; +}; -- cgit v0.10.2 From 1f53170b80aeb3991b4a250a581422abf93bddb2 Mon Sep 17 00:00:00 2001 From: huang lin Date: Fri, 5 Sep 2014 09:53:11 -0700 Subject: ARM: dts: Add SPI nodes to rk3288 This adds basic SPI nodes to the base rk3288 device tree file. A few notes: * It's assumed that most users of the SPI ports are using chip select 0. Thus the default pinctrl for the ports enables chip select 0 (but not chip select 1 on ports that have it). If a board wants to use chip select 1 or wants a GPIO chip select the board should override the pinctrl (just like boards can override UART pinctrl if they have hardware flow control). * Since SPI DMA support appears broken and the SPI works fine without DMA we don't include the DMA references. That can come in a later change. Signed-off-by: huang lin Signed-off-by: Doug Anderson Signed-off-by: Heiko Stuebner diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index 2ac3488..82fc2fa 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -34,6 +34,9 @@ serial2 = &uart2; serial3 = &uart3; serial4 = &uart4; + spi0 = &spi0; + spi1 = &spi1; + spi2 = &spi2; }; cpus { @@ -128,6 +131,45 @@ status = "disabled"; }; + spi0: spi@ff110000 { + compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi"; + clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; + clock-names = "spiclk", "apb_pclk"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; + reg = <0xff110000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi1: spi@ff120000 { + compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi"; + clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; + clock-names = "spiclk", "apb_pclk"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; + reg = <0xff120000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi2: spi@ff130000 { + compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi"; + clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>; + clock-names = "spiclk", "apb_pclk"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>; + reg = <0xff130000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + i2c1: i2c@ff140000 { compatible = "rockchip,rk3288-i2c"; reg = <0xff140000 0x1000>; @@ -720,6 +762,56 @@ }; }; + spi0 { + spi0_clk: spi0-clk { + rockchip,pins = <5 12 RK_FUNC_1 &pcfg_pull_up>; + }; + spi0_cs0: spi0-cs0 { + rockchip,pins = <5 13 RK_FUNC_1 &pcfg_pull_up>; + }; + spi0_tx: spi0-tx { + rockchip,pins = <5 14 RK_FUNC_1 &pcfg_pull_up>; + }; + spi0_rx: spi0-rx { + rockchip,pins = <5 15 RK_FUNC_1 &pcfg_pull_up>; + }; + spi0_cs1: spi0-cs1 { + rockchip,pins = <5 16 RK_FUNC_1 &pcfg_pull_up>; + }; + }; + spi1 { + spi1_clk: spi1-clk { + rockchip,pins = <7 12 RK_FUNC_2 &pcfg_pull_up>; + }; + spi1_cs0: spi1-cs0 { + rockchip,pins = <7 13 RK_FUNC_2 &pcfg_pull_up>; + }; + spi1_rx: spi1-rx { + rockchip,pins = <7 14 RK_FUNC_2 &pcfg_pull_up>; + }; + spi1_tx: spi1-tx { + rockchip,pins = <7 15 RK_FUNC_2 &pcfg_pull_up>; + }; + }; + + spi2 { + spi2_cs1: spi2-cs1 { + rockchip,pins = <8 3 RK_FUNC_1 &pcfg_pull_up>; + }; + spi2_clk: spi2-clk { + rockchip,pins = <8 6 RK_FUNC_1 &pcfg_pull_up>; + }; + spi2_cs0: spi2-cs0 { + rockchip,pins = <8 7 RK_FUNC_1 &pcfg_pull_up>; + }; + spi2_rx: spi2-rx { + rockchip,pins = <8 8 RK_FUNC_1 &pcfg_pull_up>; + }; + spi2_tx: spi2-tx { + rockchip,pins = <8 9 RK_FUNC_1 &pcfg_pull_up>; + }; + }; + uart0 { uart0_xfer: uart0-xfer { rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>, -- cgit v0.10.2 From d7f9a3887b91df6404bb4aae101efecc4a4909f7 Mon Sep 17 00:00:00 2001 From: Doug Anderson Date: Wed, 3 Sep 2014 16:05:23 -0700 Subject: ARM: dts: Add mshc aliases for rk3288 It's convenient (and less confusing to people reading logs) if the eMMC port on rk3288 is consistenly marked with mmc0 and the sdmmc port on rk3288 is consistently marked with mmc1. Add the appropriate aliases. Signed-off-by: Doug Anderson Reviewed-by: Sonny Rao Signed-off-by: Heiko Stuebner diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index 82fc2fa..37a8ac8 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -29,6 +29,10 @@ i2c3 = &i2c3; i2c4 = &i2c4; i2c5 = &i2c5; + mshc0 = &emmc; + mshc1 = &sdmmc; + mshc2 = &sdio0; + mshc3 = &sdio1; serial0 = &uart0; serial1 = &uart1; serial2 = &uart2; -- cgit v0.10.2 From 60c20784f243199599a425f73b8060da3a0f5ead Mon Sep 17 00:00:00 2001 From: Doug Anderson Date: Tue, 26 Aug 2014 10:28:43 -0700 Subject: ARM: dts: Add rk808 PMIC to rk3288-evb-rk808 This adds initial support. For now, regulators are always on and we don't specify the input supply for all of the regulators. Signed-off-by: huang lin Signed-off-by: Doug Anderson Signed-off-by: Heiko Stuebner diff --git a/arch/arm/boot/dts/rk3288-evb-rk808.dts b/arch/arm/boot/dts/rk3288-evb-rk808.dts index 9a88b6c..36db177 100644 --- a/arch/arm/boot/dts/rk3288-evb-rk808.dts +++ b/arch/arm/boot/dts/rk3288-evb-rk808.dts @@ -16,3 +16,134 @@ / { compatible = "rockchip,rk3288-evb-rk808", "rockchip,rk3288"; }; + +&i2c0 { + status = "okay"; + + rk808: pmic@1b { + compatible = "rockchip,rk808"; + reg = <0x1b>; + interrupt-parent = <&gpio0>; + interrupts = <4 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int>; + rockchip,system-power-controller; + wakeup-source; + #clock-cells = <1>; + clock-output-names = "xin32k", "rk808-clkout2"; + + vcc8-supply = <&vcc_18>; + vcc9-supply = <&vcc_io>; + vcc10-supply = <&vcc_io>; + vcc12-supply = <&vcc_io>; + vddio-supply = <&vccio_pmu>; + + regulators { + vdd_cpu: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1300000>; + regulator-name = "vdd_arm"; + }; + + vdd_gpu: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1250000>; + regulator-name = "vdd_gpu"; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_ddr"; + }; + + vcc_io: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_io"; + }; + + vccio_pmu: LDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_pmu"; + }; + + vcc_tp: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_tp"; + }; + + vdd_10: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-name = "vdd_10"; + }; + + vcc18_lcd: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc18_lcd"; + }; + + vccio_sd: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_sd"; + }; + + vdd10_lcd: LDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-name = "vdd10_lcd"; + }; + + vcc_18: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_18"; + }; + + vcca_codec: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcca_codec"; + }; + + vcc_wl: SWITCH_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_wl"; + }; + + vcc_lcd: SWITCH_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_lcd"; + }; + }; + }; +}; -- cgit v0.10.2 From 924c31cc688231292119aa1bdbf7ce349c42ca49 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Fri, 23 May 2014 00:58:08 -0500 Subject: ARM: dts: OMAP5: switch to compatible pinctrl Now that ti,omap5-padconf is available, switch over to that compatible property. Retain pinctrl-single for legacy support. While at it, mark pinctrl as interrupt controller so that it can be used with interrupts-extended property for wakeup events. Signed-off-by: Nishanth Menon diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi index fc8df17..ea08ad8 100644 --- a/arch/arm/boot/dts/omap5.dtsi +++ b/arch/arm/boot/dts/omap5.dtsi @@ -187,18 +187,22 @@ }; omap5_pmx_core: pinmux@4a002840 { - compatible = "ti,omap4-padconf", "pinctrl-single"; + compatible = "ti,omap5-padconf", "pinctrl-single"; reg = <0x4a002840 0x01b6>; #address-cells = <1>; #size-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; pinctrl-single,register-width = <16>; pinctrl-single,function-mask = <0x7fff>; }; omap5_pmx_wkup: pinmux@4ae0c840 { - compatible = "ti,omap4-padconf", "pinctrl-single"; + compatible = "ti,omap5-padconf", "pinctrl-single"; reg = <0x4ae0c840 0x0038>; #address-cells = <1>; #size-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; pinctrl-single,register-width = <16>; pinctrl-single,function-mask = <0x7fff>; }; -- cgit v0.10.2 From 817c0378c50c2aab2b026caab7486df6895ed8a2 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Thu, 22 May 2014 23:47:46 -0500 Subject: ARM: dts: DRA7: switch to compatible pinctrl Now that ti,dra7-padconf is available, switch over to that compatible property. Retain pinctrl-single for legacy support. While at it, mark pinctrl as interrupt controller so that it can be used with interrupts-extended property for wakeup events. Signed-off-by: Nishanth Menon diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index 97f603c..f8654a8 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -217,10 +217,12 @@ }; dra7_pmx_core: pinmux@4a003400 { - compatible = "pinctrl-single"; + compatible = "ti,dra7-padconf", "pinctrl-single"; reg = <0x4a003400 0x0464>; #address-cells = <1>; #size-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; pinctrl-single,register-width = <32>; pinctrl-single,function-mask = <0x3fffffff>; }; -- cgit v0.10.2 From d8c5bab676774b9c260c7990b84a06a09310fbec Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Thu, 22 May 2014 23:47:46 -0500 Subject: ARM: dts: AM437x: switch to compatible pinctrl Now that ti,am437-padconf is available, switch over to that compatible property. Retain pinctrl-single for legacy support. While at it, mark the pinctrl as interrupt controller so that it can be used with interrupts-extended property for wakeup events. Signed-off-by: Nishanth Menon diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi index 9b3d2ba..b384830 100644 --- a/arch/arm/boot/dts/am4372.dtsi +++ b/arch/arm/boot/dts/am4372.dtsi @@ -58,10 +58,12 @@ }; am43xx_pinmux: pinmux@44e10800 { - compatible = "pinctrl-single"; + compatible = "ti,am437-padconf", "pinctrl-single"; reg = <0x44e10800 0x31c>; #address-cells = <1>; #size-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; pinctrl-single,register-width = <32>; pinctrl-single,function-mask = <0xffffffff>; }; -- cgit v0.10.2 From e2265abe7a18e5e6880d0cd35e2db08bcd237366 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Fri, 23 May 2014 00:04:02 -0500 Subject: ARM: dts: OMAP5 / DRA7: switch over to interrupts-extended property for UART We've had deeper idle states working on omaps for few years now, but only in the legacy mode. When booted with device tree, the wake-up events did not have a chance to work until commit 3e6cee1786a1 ("pinctrl: single: Add support for wake-up interrupts") that recently got merged. In addition to that we also needed commit 79d9701559a9 ("of/irq: create interrupts-extended property") that's now also merged. Note that there's no longer need to specify the wake-up bit in the pinctrl settings, the request_irq on the wake-up pin takes care of that. Signed-off-by: Nishanth Menon diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index f8654a8..4e50dea 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -330,7 +330,7 @@ uart1: serial@4806a000 { compatible = "ti,omap4-uart"; reg = <0x4806a000 0x100>; - interrupts = ; + interrupts-extended = <&gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "uart1"; clock-frequency = <48000000>; status = "disabled"; @@ -339,7 +339,7 @@ uart2: serial@4806c000 { compatible = "ti,omap4-uart"; reg = <0x4806c000 0x100>; - interrupts = ; + interrupts-extended = <&gic GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "uart2"; clock-frequency = <48000000>; status = "disabled"; @@ -348,7 +348,7 @@ uart3: serial@48020000 { compatible = "ti,omap4-uart"; reg = <0x48020000 0x100>; - interrupts = ; + interrupts-extended = <&gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "uart3"; clock-frequency = <48000000>; status = "disabled"; @@ -357,7 +357,7 @@ uart4: serial@4806e000 { compatible = "ti,omap4-uart"; reg = <0x4806e000 0x100>; - interrupts = ; + interrupts-extended = <&gic GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "uart4"; clock-frequency = <48000000>; status = "disabled"; @@ -366,7 +366,7 @@ uart5: serial@48066000 { compatible = "ti,omap4-uart"; reg = <0x48066000 0x100>; - interrupts = ; + interrupts-extended = <&gic GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "uart5"; clock-frequency = <48000000>; status = "disabled"; @@ -375,7 +375,7 @@ uart6: serial@48068000 { compatible = "ti,omap4-uart"; reg = <0x48068000 0x100>; - interrupts = ; + interrupts-extended = <&gic GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "uart6"; clock-frequency = <48000000>; status = "disabled"; @@ -384,7 +384,7 @@ uart7: serial@48420000 { compatible = "ti,omap4-uart"; reg = <0x48420000 0x100>; - interrupts = ; + interrupts-extended = <&gic GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "uart7"; clock-frequency = <48000000>; status = "disabled"; @@ -393,7 +393,7 @@ uart8: serial@48422000 { compatible = "ti,omap4-uart"; reg = <0x48422000 0x100>; - interrupts = ; + interrupts-extended = <&gic GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "uart8"; clock-frequency = <48000000>; status = "disabled"; @@ -402,7 +402,7 @@ uart9: serial@48424000 { compatible = "ti,omap4-uart"; reg = <0x48424000 0x100>; - interrupts = ; + interrupts-extended = <&gic GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "uart9"; clock-frequency = <48000000>; status = "disabled"; @@ -411,7 +411,7 @@ uart10: serial@4ae2b000 { compatible = "ti,omap4-uart"; reg = <0x4ae2b000 0x100>; - interrupts = ; + interrupts-extended = <&gic GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "uart10"; clock-frequency = <48000000>; status = "disabled"; diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi index ea08ad8..b840db0 100644 --- a/arch/arm/boot/dts/omap5.dtsi +++ b/arch/arm/boot/dts/omap5.dtsi @@ -451,7 +451,7 @@ uart1: serial@4806a000 { compatible = "ti,omap4-uart"; reg = <0x4806a000 0x100>; - interrupts = ; + interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "uart1"; clock-frequency = <48000000>; }; @@ -459,7 +459,7 @@ uart2: serial@4806c000 { compatible = "ti,omap4-uart"; reg = <0x4806c000 0x100>; - interrupts = ; + interrupts-extended = <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "uart2"; clock-frequency = <48000000>; }; @@ -467,7 +467,7 @@ uart3: serial@48020000 { compatible = "ti,omap4-uart"; reg = <0x48020000 0x100>; - interrupts = ; + interrupts-extended = <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "uart3"; clock-frequency = <48000000>; }; @@ -475,7 +475,7 @@ uart4: serial@4806e000 { compatible = "ti,omap4-uart"; reg = <0x4806e000 0x100>; - interrupts = ; + interrupts-extended = <&gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "uart4"; clock-frequency = <48000000>; }; @@ -483,7 +483,7 @@ uart5: serial@48066000 { compatible = "ti,omap4-uart"; reg = <0x48066000 0x100>; - interrupts = ; + interrupts-extended = <&gic GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "uart5"; clock-frequency = <48000000>; }; @@ -491,7 +491,7 @@ uart6: serial@48068000 { compatible = "ti,omap4-uart"; reg = <0x48068000 0x100>; - interrupts = ; + interrupts-extended = <&gic GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "uart6"; clock-frequency = <48000000>; }; -- cgit v0.10.2 From 66b0436977e2c62388d48836ff784f1fedb49c4f Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Fri, 6 Jun 2014 20:53:22 -0500 Subject: ARM: dts: dra7-evm: Mark uart1 rxd as wakeup capable Mark rxd as wakeupcapable for 115200n8 no hardware-flow control configuration. If h/w flow control is being used, then rts/cts appropriately should be used. Signed-off-by: Nishanth Menon diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts index 50f8022..08434c7 100644 --- a/arch/arm/boot/dts/dra7-evm.dts +++ b/arch/arm/boot/dts/dra7-evm.dts @@ -303,6 +303,8 @@ status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&uart1_pins>; + interrupts-extended = <&gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, + <&dra7_pmx_core 0x3e0>; }; &uart2 { -- cgit v0.10.2 From e86ed56adb571cddd47ba3a008e2353b057ba70b Mon Sep 17 00:00:00 2001 From: Gregory CLEMENT Date: Tue, 2 Sep 2014 10:15:18 +0200 Subject: ARM: mvebu: add SSCG to Armada 370 Device Tree The Armada 370 SoC has a Spread Spectrum Clock Generator. This commit adds the description of this generator to the Device Tree describing this SoC. Signed-off-by: Gregory CLEMENT Tested-by: Leigh Brown Link: https://lkml.kernel.org/r/1409645719-20003-4-git-send-email-gregory.clement@free-electrons.com Signed-off-by: Jason Cooper diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi index f2c55f3..6b3c23b 100644 --- a/arch/arm/boot/dts/armada-370.dtsi +++ b/arch/arm/boot/dts/armada-370.dtsi @@ -225,6 +225,10 @@ status = "okay"; }; + sscg@18330 { + reg = <0x18330 0x4>; + }; + interrupt-controller@20000 { reg = <0x20a00 0x1d0>, <0x21870 0x58>; }; -- cgit v0.10.2 From ccf8ca4bfb7247f0f209c41d9d9c84736b14651d Mon Sep 17 00:00:00 2001 From: Greg Ungerer Date: Mon, 8 Sep 2014 13:30:29 +1000 Subject: ARM: mvebu: use improved armada spi device tree compatible name Switch the Armada SoC SPI port device tree binding to use the new improved armada-370-spi compatible name. This allows for a wider range of baud rates to be used. Signed-off-by: Greg Ungerer Tested-by: Ezequiel Garcia Reviewed-by: Ezequiel Garcia Link: https://lkml.kernel.org/r/1410147029-30067-1-git-send-email-gerg@uclinux.org Signed-off-by: Jason Cooper diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi index 23227e0..83286ec 100644 --- a/arch/arm/boot/dts/armada-370-xp.dtsi +++ b/arch/arm/boot/dts/armada-370-xp.dtsi @@ -110,7 +110,7 @@ }; spi0: spi@10600 { - compatible = "marvell,orion-spi"; + compatible = "marvell,armada-370-spi", "marvell,orion-spi"; reg = <0x10600 0x28>; #address-cells = <1>; #size-cells = <0>; @@ -121,7 +121,7 @@ }; spi1: spi@10680 { - compatible = "marvell,orion-spi"; + compatible = "marvell,armada-370-spi", "marvell,orion-spi"; reg = <0x10680 0x28>; #address-cells = <1>; #size-cells = <0>; -- cgit v0.10.2 From 7a6540ca856aeb5adbdee80836af7c2326e55d3b Mon Sep 17 00:00:00 2001 From: Philipp Zabel Date: Mon, 8 Sep 2014 11:19:18 +0200 Subject: ARM: mvebu: Change vendor prefix for Intersil Corporation to isil Currently there is a wild mixture of isl, isil, and intersil compatibles in the kernel. At this point, changing the vendor symbol to the most often used variant, which is equal to the NASDAQ symbol, isil, should not hurt. Signed-off-by: Philipp Zabel Link: https://lkml.kernel.org/r/1410167960-554-4-git-send-email-p.zabel@pengutronix.de Signed-off-by: Jason Cooper diff --git a/arch/arm/boot/dts/armada-370-netgear-rn102.dts b/arch/arm/boot/dts/armada-370-netgear-rn102.dts index 03f917e..29a7c4e 100644 --- a/arch/arm/boot/dts/armada-370-netgear-rn102.dts +++ b/arch/arm/boot/dts/armada-370-netgear-rn102.dts @@ -126,7 +126,7 @@ status = "okay"; isl12057: isl12057@68 { - compatible = "isl,isl12057"; + compatible = "isil,isl12057"; reg = <0x68>; }; diff --git a/arch/arm/boot/dts/armada-370-netgear-rn104.dts b/arch/arm/boot/dts/armada-370-netgear-rn104.dts index f56bb1b..c8b23c0 100644 --- a/arch/arm/boot/dts/armada-370-netgear-rn104.dts +++ b/arch/arm/boot/dts/armada-370-netgear-rn104.dts @@ -123,7 +123,7 @@ status = "okay"; isl12057: isl12057@68 { - compatible = "isl,isl12057"; + compatible = "isil,isl12057"; reg = <0x68>; }; diff --git a/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts b/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts index 0cf999a..252def8 100644 --- a/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts +++ b/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts @@ -174,7 +174,7 @@ status = "okay"; isl12057: isl12057@68 { - compatible = "isl,isl12057"; + compatible = "isil,isl12057"; reg = <0x68>; }; -- cgit v0.10.2 From 0f4fc382428f71453d195925a3c63efc48452417 Mon Sep 17 00:00:00 2001 From: Doug Anderson Date: Wed, 10 Sep 2014 21:30:15 -0700 Subject: ARM: dts: Switch i2c0 to 400kHz on rk3288-evb-rk808 We should be able to talk to the PMIC at 400kHz. No need to talk at the slow 100kHz. As measured by ftrace (with a bunch of extra patches, since cpufreq for rk808 hasn't landed yet): before this change: cpu0_set_target() => ~500us after this change: cpu0_set_target() => ~300us Signed-off-by: Doug Anderson Reviewed-by Addy Ke Tested-by Addy Ke Signed-off-by: Heiko Stuebner diff --git a/arch/arm/boot/dts/rk3288-evb-rk808.dts b/arch/arm/boot/dts/rk3288-evb-rk808.dts index 36db177..ff522f8 100644 --- a/arch/arm/boot/dts/rk3288-evb-rk808.dts +++ b/arch/arm/boot/dts/rk3288-evb-rk808.dts @@ -18,6 +18,7 @@ }; &i2c0 { + clock-frequency = <400000>; status = "okay"; rk808: pmic@1b { -- cgit v0.10.2 From fa410c099d9688ca06a9e46df8b2edf183487935 Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Tue, 24 Jun 2014 14:03:53 -0700 Subject: ARM: dts: msm: Add 8921 PMIC to ssbi bus Add the PMIC and the sub-devices that are currently supported in the kernel to the DT. Signed-off-by: Stephen Boyd Signed-off-by: Kumar Gala diff --git a/arch/arm/boot/dts/qcom-msm8960-cdp.dts b/arch/arm/boot/dts/qcom-msm8960-cdp.dts index 8f75cc4..8b10812 100644 --- a/arch/arm/boot/dts/qcom-msm8960-cdp.dts +++ b/arch/arm/boot/dts/qcom-msm8960-cdp.dts @@ -1,3 +1,5 @@ +#include + #include "qcom-msm8960.dtsi" / { @@ -14,3 +16,16 @@ }; }; }; + +&pmicintc { + keypad@148 { + linux,keymap = < + MATRIX_KEY(0, 0, KEY_VOLUMEUP) + MATRIX_KEY(0, 1, KEY_VOLUMEDOWN) + MATRIX_KEY(0, 2, KEY_CAMERA_FOCUS) + MATRIX_KEY(0, 3, KEY_CAMERA) + >; + keypad,num-rows = <1>; + keypad,num-columns = <5>; + }; +}; diff --git a/arch/arm/boot/dts/qcom-msm8960.dtsi b/arch/arm/boot/dts/qcom-msm8960.dtsi index 5303e53..2f67724 100644 --- a/arch/arm/boot/dts/qcom-msm8960.dtsi +++ b/arch/arm/boot/dts/qcom-msm8960.dtsi @@ -143,6 +143,43 @@ compatible = "qcom,ssbi"; reg = <0x500000 0x1000>; qcom,controller-type = "pmic-arbiter"; + + pmicintc: pmic@0 { + compatible = "qcom,pm8921"; + interrupt-parent = <&msmgpio>; + interrupts = <104 8>; + #interrupt-cells = <2>; + interrupt-controller; + #address-cells = <1>; + #size-cells = <0>; + + pwrkey@1c { + compatible = "qcom,pm8921-pwrkey"; + reg = <0x1c>; + interrupt-parent = <&pmicintc>; + interrupts = <50 1>, <51 1>; + debounce = <15625>; + pull-up; + }; + + keypad@148 { + compatible = "qcom,pm8921-keypad"; + reg = <0x148>; + interrupt-parent = <&pmicintc>; + interrupts = <74 1>, <75 1>; + debounce = <15>; + scan-delay = <32>; + row-hold = <91500>; + }; + + rtc@11d { + compatible = "qcom,pm8921-rtc"; + interrupt-parent = <&pmicintc>; + interrupts = <39 1>; + reg = <0x11d>; + allow-set-time; + }; + }; }; rng@1a500000 { -- cgit v0.10.2 From 94ae991d63805b39baffacee0e8f25ddce0e83bc Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Tue, 24 Jun 2014 14:03:54 -0700 Subject: ARM: dts: msm: Add 8058 PMIC to ssbi bus Add the PMIC and the sub-devices that are currently supported in the kernel to the DT. Signed-off-by: Stephen Boyd Signed-off-by: Kumar Gala diff --git a/arch/arm/boot/dts/qcom-msm8660-surf.dts b/arch/arm/boot/dts/qcom-msm8660-surf.dts index 45180ad..ff7c53f 100644 --- a/arch/arm/boot/dts/qcom-msm8660-surf.dts +++ b/arch/arm/boot/dts/qcom-msm8660-surf.dts @@ -1,3 +1,5 @@ +#include + #include "qcom-msm8660.dtsi" / { @@ -14,3 +16,31 @@ }; }; }; + +&pmicintc { + keypad@148 { + linux,keymap = < + MATRIX_KEY(0, 0, KEY_FN_F1) + MATRIX_KEY(0, 1, KEY_UP) + MATRIX_KEY(0, 2, KEY_LEFT) + MATRIX_KEY(0, 3, KEY_VOLUMEUP) + MATRIX_KEY(1, 0, KEY_FN_F2) + MATRIX_KEY(1, 1, KEY_RIGHT) + MATRIX_KEY(1, 2, KEY_DOWN) + MATRIX_KEY(1, 3, KEY_VOLUMEDOWN) + MATRIX_KEY(2, 3, KEY_ENTER) + MATRIX_KEY(4, 0, KEY_CAMERA_FOCUS) + MATRIX_KEY(4, 1, KEY_UP) + MATRIX_KEY(4, 2, KEY_LEFT) + MATRIX_KEY(4, 3, KEY_HOME) + MATRIX_KEY(4, 4, KEY_FN_F3) + MATRIX_KEY(5, 0, KEY_CAMERA) + MATRIX_KEY(5, 1, KEY_RIGHT) + MATRIX_KEY(5, 2, KEY_DOWN) + MATRIX_KEY(5, 3, KEY_BACK) + MATRIX_KEY(5, 4, KEY_MENU) + >; + keypad,num-rows = <6>; + keypad,num-columns = <5>; + }; +}; diff --git a/arch/arm/boot/dts/qcom-msm8660.dtsi b/arch/arm/boot/dts/qcom-msm8660.dtsi index 53837aaa2f..a3fd26b 100644 --- a/arch/arm/boot/dts/qcom-msm8660.dtsi +++ b/arch/arm/boot/dts/qcom-msm8660.dtsi @@ -103,6 +103,48 @@ compatible = "qcom,ssbi"; reg = <0x500000 0x1000>; qcom,controller-type = "pmic-arbiter"; + + pmicintc: pmic@0 { + compatible = "qcom,pm8058"; + interrupt-parent = <&msmgpio>; + interrupts = <88 8>; + #interrupt-cells = <2>; + interrupt-controller; + #address-cells = <1>; + #size-cells = <0>; + + pwrkey@1c { + compatible = "qcom,pm8058-pwrkey"; + reg = <0x1c>; + interrupt-parent = <&pmicintc>; + interrupts = <50 1>, <51 1>; + debounce = <15625>; + pull-up; + }; + + keypad@148 { + compatible = "qcom,pm8058-keypad"; + reg = <0x148>; + interrupt-parent = <&pmicintc>; + interrupts = <74 1>, <75 1>; + debounce = <15>; + scan-delay = <32>; + row-hold = <91500>; + }; + + rtc@11d { + compatible = "qcom,pm8058-rtc"; + interrupt-parent = <&pmicintc>; + interrupts = <39 1>; + reg = <0x11d>; + allow-set-time; + }; + + vibrator@4a { + compatible = "qcom,pm8058-vib"; + reg = <0x4a>; + }; + }; }; }; }; -- cgit v0.10.2 From 66c04e30f4a6e6ed998a6c154a6c45b3cd5b3fde Mon Sep 17 00:00:00 2001 From: Georgi Djakov Date: Wed, 3 Sep 2014 19:50:31 +0300 Subject: ARM: dts: qcom: Add initial IFC6540 board device tree Add basic support for the IFC6540 single-board computer boards, that are based on the APQ8084 SoC. This patch adds the initial device tree and the neccessary nodes required for enabling the serial port and eMMC. Signed-off-by: Georgi Djakov Signed-off-by: Kumar Gala diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index a097a04..aaa1a68 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -341,6 +341,7 @@ dtb-$(CONFIG_ARCH_PRIMA2) += prima2-evb.dtb dtb-$(CONFIG_ARCH_QCOM) += \ qcom-apq8064-ifc6410.dtb \ qcom-apq8074-dragonboard.dtb \ + qcom-apq8084-ifc6540.dtb \ qcom-apq8084-mtp.dtb \ qcom-ipq8064-ap148.dtb \ qcom-msm8660-surf.dtb \ diff --git a/arch/arm/boot/dts/qcom-apq8084-ifc6540.dts b/arch/arm/boot/dts/qcom-apq8084-ifc6540.dts new file mode 100644 index 0000000..c9ff108 --- /dev/null +++ b/arch/arm/boot/dts/qcom-apq8084-ifc6540.dts @@ -0,0 +1,23 @@ +#include "qcom-apq8084.dtsi" + +/ { + model = "Qualcomm APQ8084/IFC6540"; + compatible = "qcom,apq8084-ifc6540", "qcom,apq8084"; + + soc { + serial@f995e000 { + status = "okay"; + }; + + sdhci@f9824900 { + bus-width = <8>; + non-removable; + status = "okay"; + }; + + sdhci@f98a4900 { + cd-gpios = <&tlmm 122 GPIO_ACTIVE_LOW>; + bus-width = <4>; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom-apq8084.dtsi b/arch/arm/boot/dts/qcom-apq8084.dtsi index b5b156e..b9ac63c 100644 --- a/arch/arm/boot/dts/qcom-apq8084.dtsi +++ b/arch/arm/boot/dts/qcom-apq8084.dtsi @@ -3,6 +3,7 @@ #include "skeleton.dtsi" #include +#include / { model = "Qualcomm APQ 8084"; @@ -193,5 +194,27 @@ clock-names = "core", "iface"; status = "disabled"; }; + + sdhci@f9824900 { + compatible = "qcom,sdhci-msm-v4"; + reg = <0xf9824900 0x11c>, <0xf9824000 0x800>; + reg-names = "hc_mem", "core_mem"; + interrupts = <0 123 0>, <0 138 0>; + interrupt-names = "hc_irq", "pwr_irq"; + clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + + sdhci@f98a4900 { + compatible = "qcom,sdhci-msm-v4"; + reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>; + reg-names = "hc_mem", "core_mem"; + interrupts = <0 125 0>, <0 221 0>; + interrupt-names = "hc_irq", "pwr_irq"; + clocks = <&gcc GCC_SDCC2_APPS_CLK>, <&gcc GCC_SDCC2_AHB_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; }; }; -- cgit v0.10.2 From 44980b284d389121161a4d8cad5b08d4c0b78abd Mon Sep 17 00:00:00 2001 From: Georgi Djakov Date: Wed, 3 Sep 2014 19:28:15 +0300 Subject: ARM: dts: qcom: Add TLMM DT node for APQ8084 This patch adds the TLMM node for the APQ8084 platform. Reviewed-by: Bjorn Andersson Signed-off-by: Georgi Djakov Acked-by: Linus Walleij Signed-off-by: Kumar Gala diff --git a/arch/arm/boot/dts/qcom-apq8084.dtsi b/arch/arm/boot/dts/qcom-apq8084.dtsi index b9ac63c..1f130bc 100644 --- a/arch/arm/boot/dts/qcom-apq8084.dtsi +++ b/arch/arm/boot/dts/qcom-apq8084.dtsi @@ -186,6 +186,16 @@ reg = <0xfc400000 0x4000>; }; + tlmm: pinctrl@fd510000 { + compatible = "qcom,apq8084-pinctrl"; + reg = <0xfd510000 0x4000>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <0 208 0>; + }; + serial@f995e000 { compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; reg = <0xf995e000 0x1000>; -- cgit v0.10.2 From 8b8936fc358f830e514bafdebe109e06a4a7aabd Mon Sep 17 00:00:00 2001 From: Pramod Gurav Date: Fri, 29 Aug 2014 20:00:56 +0530 Subject: ARM: DT: APQ8064: Add pinctrl support This patch adds device tree nodes to support pinctrl for apq8064 SOC CC: Rob Herring CC: Pawel Moll CC: Mark Rutland CC: Ian Campbell CC: Kumar Gala CC: devicetree@vger.kernel.org CC: linux-arm-kernel@lists.infradead.org Signed-off-by: Pramod Gurav Signed-off-by: Kumar Gala diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index 92bf793..23745f2 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -3,6 +3,7 @@ #include "skeleton.dtsi" #include #include +#include / { model = "Qualcomm APQ8064"; @@ -70,6 +71,17 @@ ranges; compatible = "simple-bus"; + tlmm_pinmux: pinctrl@800000 { + compatible = "qcom,apq8064-pinctrl"; + reg = <0x800000 0x4000>; + + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>; + }; + intc: interrupt-controller@2000000 { compatible = "qcom,msm-qgic2"; interrupt-controller; -- cgit v0.10.2 From cd6dd11a23e1b4d630c6fe517b74a44ed7c54ab9 Mon Sep 17 00:00:00 2001 From: Pramod Gurav Date: Fri, 29 Aug 2014 20:00:57 +0530 Subject: ARM: DT: APQ8064: Add node for ps_hold function in pinctrl This patch adds DT support to configure GPIO_78 as function ps_hold on apq8064. CC: Rob Herring CC: Pawel Moll CC: Mark Rutland CC: Ian Campbell CC: Kumar Gala CC: devicetree@vger.kernel.org CC: linux-arm-kernel@lists.infradead.org Signed-off-by: Pramod Gurav Signed-off-by: Kumar Gala diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index 23745f2..2a897b0 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -80,6 +80,16 @@ interrupt-controller; #interrupt-cells = <2>; interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>; + + pinctrl-names = "default"; + pinctrl-0 = <&ps_hold>; + + ps_hold: ps_hold { + mux { + pins = "gpio78"; + function = "ps_hold"; + }; + }; }; intc: interrupt-controller@2000000 { -- cgit v0.10.2 From 3fe5e3cee0662a6114d19b4d7e05c7463c85e212 Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Wed, 16 Jul 2014 13:49:43 -0700 Subject: ARM: dts: qcom: Add 8064 multimedia clock controller node Add the mmcc node so that we can probe and use the multimedia clocks on apq8064. Signed-off-by: Stephen Boyd Signed-off-by: Kumar Gala diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index 2a897b0..c8098bc 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -2,6 +2,7 @@ #include "skeleton.dtsi" #include +#include #include #include @@ -188,5 +189,12 @@ #clock-cells = <1>; #reset-cells = <1>; }; + + mmcc: clock-controller@4000000 { + compatible = "qcom,mmcc-apq8064"; + reg = <0x4000000 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; }; }; -- cgit v0.10.2 From 045644ffe618f140791643aa8b78ad2587e8de0f Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Tue, 29 Apr 2014 08:33:52 +0100 Subject: ARM: DT: apq8064: Add sdcc support via mcci driver. This patch adds support to SD card controller using generic pl180 mmci driver. This patch also adds temporary fixed regulator to get it going till the actual regulator is mainlined. Signed-off-by: Srinivas Kandagatla Signed-off-by: Kumar Gala diff --git a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts index 7c2441d..90db8af 100644 --- a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts +++ b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts @@ -12,5 +12,17 @@ status = "ok"; }; }; + + amba { + /* eMMC */ + sdcc1: sdcc@12400000 { + status = "okay"; + }; + + /* External micro SD card */ + sdcc3: sdcc@12180000 { + status = "okay"; + }; + }; }; }; diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index c8098bc..32075e8 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -196,5 +196,54 @@ #clock-cells = <1>; #reset-cells = <1>; }; + + /* Temporary fixed regulator */ + vsdcc_fixed: vsdcc-regulator { + compatible = "regulator-fixed"; + regulator-name = "SDCC Power"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + regulator-always-on; + }; + + amba { + compatible = "arm,amba-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + sdcc1: sdcc@12400000 { + status = "disabled"; + compatible = "arm,pl18x", "arm,primecell"; + arm,primecell-periphid = <0x00051180>; + reg = <0x12400000 0x2000>; + interrupts = ; + interrupt-names = "cmd_irq"; + clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; + clock-names = "mclk", "apb_pclk"; + bus-width = <8>; + max-frequency = <96000000>; + non-removable; + cap-sd-highspeed; + cap-mmc-highspeed; + vmmc-supply = <&vsdcc_fixed>; + }; + + sdcc3: sdcc@12180000 { + compatible = "arm,pl18x", "arm,primecell"; + arm,primecell-periphid = <0x00051180>; + status = "disabled"; + reg = <0x12180000 0x2000>; + interrupts = ; + interrupt-names = "cmd_irq"; + clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>; + clock-names = "mclk", "apb_pclk"; + bus-width = <4>; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency = <192000000>; + no-1-8-v; + vmmc-supply = <&vsdcc_fixed>; + }; + }; }; }; -- cgit v0.10.2 From edb81ca3bf586ad526ee67b245cb87f7c7142a87 Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Fri, 16 May 2014 20:18:53 +0100 Subject: ARM: DT: QCOM: apq8064: Add dma support for sdcc node This patch adds dma support in both sdcc1 and sdcc3 device node. Signed-off-by: Srinivas Kandagatla Signed-off-by: Kumar Gala diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index 32075e8..b1e476a 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -206,6 +206,26 @@ regulator-always-on; }; + sdcc1bam:dma@12402000{ + compatible = "qcom,bam-v1.3.0"; + reg = <0x12402000 0x8000>; + interrupts = <0 98 0>; + clocks = <&gcc SDC1_H_CLK>; + clock-names = "bam_clk"; + #dma-cells = <1>; + qcom,ee = <0>; + }; + + sdcc3bam:dma@12182000{ + compatible = "qcom,bam-v1.3.0"; + reg = <0x12182000 0x8000>; + interrupts = <0 96 0>; + clocks = <&gcc SDC3_H_CLK>; + clock-names = "bam_clk"; + #dma-cells = <1>; + qcom,ee = <0>; + }; + amba { compatible = "arm,amba-bus"; #address-cells = <1>; @@ -226,6 +246,8 @@ cap-sd-highspeed; cap-mmc-highspeed; vmmc-supply = <&vsdcc_fixed>; + dmas = <&sdcc1bam 2>, <&sdcc1bam 1>; + dma-names = "tx", "rx"; }; sdcc3: sdcc@12180000 { @@ -243,6 +265,8 @@ max-frequency = <192000000>; no-1-8-v; vmmc-supply = <&vsdcc_fixed>; + dmas = <&sdcc3bam 2>, <&sdcc3bam 1>; + dma-names = "tx", "rx"; }; }; }; -- cgit v0.10.2 From d27704d1ec2f9ba06247b402c58a6f2febecef78 Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Wed, 10 Sep 2014 14:27:23 -0500 Subject: ARM: dts: OMAP2+: Add sub mailboxes device node information MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The sub-mailbox devices are added to the Mailbox DT nodes on OMAP2420, OMAP2430, OMAP3, AM33xx, AM43xx, OMAP4 and OMAP5 family of SoCs. This data represents the same mailboxes that used to be represented in hwmod attribute data previously. The node name is chosen based on the .name field of omap_mbox_dev_info structure used in the hwmod data. Cc: "Benoît Cousson" Cc: Rob Herring Cc: Pawel Moll Cc: Mark Rutland Cc: Ian Campbell Cc: Kumar Gala Signed-off-by: Suman Anna Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi index 3a0a161..e4f165a 100644 --- a/arch/arm/boot/dts/am33xx.dtsi +++ b/arch/arm/boot/dts/am33xx.dtsi @@ -354,6 +354,10 @@ ti,hwmods = "mailbox"; ti,mbox-num-users = <4>; ti,mbox-num-fifos = <8>; + mbox_wkupm3: wkup_m3 { + ti,mbox-tx = <0 0 0>; + ti,mbox-rx = <0 0 3>; + }; }; timer1: timer@44e31000 { diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi index b384830..2f7570e 100644 --- a/arch/arm/boot/dts/am4372.dtsi +++ b/arch/arm/boot/dts/am4372.dtsi @@ -170,6 +170,10 @@ ti,hwmods = "mailbox"; ti,mbox-num-users = <4>; ti,mbox-num-fifos = <8>; + mbox_wkupm3: wkup_m3 { + ti,mbox-tx = <0 0 0>; + ti,mbox-rx = <0 0 3>; + }; }; timer1: timer@44e31000 { diff --git a/arch/arm/boot/dts/omap2420.dtsi b/arch/arm/boot/dts/omap2420.dtsi index 9be3c12..ae89aad 100644 --- a/arch/arm/boot/dts/omap2420.dtsi +++ b/arch/arm/boot/dts/omap2420.dtsi @@ -159,6 +159,14 @@ ti,hwmods = "mailbox"; ti,mbox-num-users = <4>; ti,mbox-num-fifos = <6>; + mbox_dsp: dsp { + ti,mbox-tx = <0 0 0>; + ti,mbox-rx = <1 0 0>; + }; + mbox_iva: iva { + ti,mbox-tx = <2 1 3>; + ti,mbox-rx = <3 1 3>; + }; }; timer1: timer@48028000 { diff --git a/arch/arm/boot/dts/omap2430.dtsi b/arch/arm/boot/dts/omap2430.dtsi index 1a00f15..b56d7161 100644 --- a/arch/arm/boot/dts/omap2430.dtsi +++ b/arch/arm/boot/dts/omap2430.dtsi @@ -249,6 +249,10 @@ ti,hwmods = "mailbox"; ti,mbox-num-users = <4>; ti,mbox-num-fifos = <6>; + mbox_dsp: dsp { + ti,mbox-tx = <0 0 0>; + ti,mbox-rx = <1 0 0>; + }; }; timer1: timer@49018000 { diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi index 575a49b..b2ae8b8 100644 --- a/arch/arm/boot/dts/omap3.dtsi +++ b/arch/arm/boot/dts/omap3.dtsi @@ -334,6 +334,10 @@ interrupts = <26>; ti,mbox-num-users = <2>; ti,mbox-num-fifos = <2>; + mbox_dsp: dsp { + ti,mbox-tx = <0 0 0>; + ti,mbox-rx = <1 0 0>; + }; }; mcspi1: spi@48098000 { diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi index 69408b5..bc54d66 100644 --- a/arch/arm/boot/dts/omap4.dtsi +++ b/arch/arm/boot/dts/omap4.dtsi @@ -656,6 +656,14 @@ ti,hwmods = "mailbox"; ti,mbox-num-users = <3>; ti,mbox-num-fifos = <8>; + mbox_ipu: mbox_ipu { + ti,mbox-tx = <0 0 0>; + ti,mbox-rx = <1 0 0>; + }; + mbox_dsp: mbox_dsp { + ti,mbox-tx = <3 0 0>; + ti,mbox-rx = <2 0 0>; + }; }; timer1: timer@4a318000 { diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi index 4bf3930..30ce71a 100644 --- a/arch/arm/boot/dts/omap5.dtsi +++ b/arch/arm/boot/dts/omap5.dtsi @@ -646,6 +646,14 @@ ti,hwmods = "mailbox"; ti,mbox-num-users = <3>; ti,mbox-num-fifos = <8>; + mbox_ipu: mbox_ipu { + ti,mbox-tx = <0 0 0>; + ti,mbox-rx = <1 0 0>; + }; + mbox_dsp: mbox_dsp { + ti,mbox-tx = <3 0 0>; + ti,mbox-rx = <2 0 0>; + }; }; timer1: timer@4ae18000 { -- cgit v0.10.2 From 064ac05080062ffa41fd4699583933d58a4a32d4 Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Sun, 14 Sep 2014 00:45:15 +0900 Subject: ARM: dts: Add support max77802 PMIC for exynos based Peach boards Exynos5420 based Peach Pit and Exynos5800 based Peach Pi boards uses a Maxim 77802 power management IC to drive regulators and its Real Time Clock. This patch adds support for this chip. These are the device nodes and pinctrl configuration that are present on the Peach pit DeviceTree source file in the the Chrome OS kernel 3.8 tree. Signed-off-by: Javier Martinez Canillas Tested-by: Naveen Krishna Chatradhi Reviewed-by: Doug Anderson Signed-off-by: Kukjin Kim diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts b/arch/arm/boot/dts/exynos5420-peach-pit.dts index ab06148..304e3bd 100644 --- a/arch/arm/boot/dts/exynos5420-peach-pit.dts +++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts @@ -11,6 +11,7 @@ /dts-v1/; #include #include +#include #include "exynos5420.dtsi" / { @@ -144,6 +145,338 @@ ddc = <&i2c_2>; }; +&hsi2c_4 { + status = "okay"; + clock-frequency = <400000>; + + max77802-pmic@9 { + compatible = "maxim,max77802"; + interrupt-parent = <&gpx3>; + interrupts = <1 IRQ_TYPE_NONE>; + pinctrl-names = "default"; + pinctrl-0 = <&max77802_irq>, <&pmic_selb>, + <&pmic_dvs_1>, <&pmic_dvs_2>, <&pmic_dvs_3>; + wakeup-source; + reg = <0x9>; + #clock-cells = <1>; + + inb1-supply = <&tps65090_dcdc2>; + inb2-supply = <&tps65090_dcdc1>; + inb3-supply = <&tps65090_dcdc2>; + inb4-supply = <&tps65090_dcdc2>; + inb5-supply = <&tps65090_dcdc1>; + inb6-supply = <&tps65090_dcdc2>; + inb7-supply = <&tps65090_dcdc1>; + inb8-supply = <&tps65090_dcdc1>; + inb9-supply = <&tps65090_dcdc1>; + inb10-supply = <&tps65090_dcdc1>; + + inl1-supply = <&buck5_reg>; + inl2-supply = <&buck7_reg>; + inl3-supply = <&buck9_reg>; + inl4-supply = <&buck9_reg>; + inl5-supply = <&buck9_reg>; + inl6-supply = <&tps65090_dcdc2>; + inl7-supply = <&buck9_reg>; + inl9-supply = <&tps65090_dcdc2>; + inl10-supply = <&buck7_reg>; + + regulators { + buck1_reg: BUCK1 { + regulator-name = "vdd_mif"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + regulator-boot-on; + regulator-ramp-delay = <12500>; + }; + + buck2_reg: BUCK2 { + regulator-name = "vdd_arm"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + regulator-ramp-delay = <12500>; + }; + + buck3_reg: BUCK3 { + regulator-name = "vdd_int"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + regulator-always-on; + regulator-boot-on; + regulator-ramp-delay = <12500>; + }; + + buck4_reg: BUCK4 { + regulator-name = "vdd_g3d"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1400000>; + regulator-always-on; + regulator-boot-on; + regulator-ramp-delay = <12500>; + }; + + buck5_reg: BUCK5 { + regulator-name = "vdd_1v2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + }; + + buck6_reg: BUCK6 { + regulator-name = "vdd_kfc"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + regulator-ramp-delay = <12500>; + }; + + buck7_reg: BUCK7 { + regulator-name = "vdd_1v35"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + }; + + buck8_reg: BUCK8 { + regulator-name = "vdd_emmc"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + regulator-always-on; + regulator-boot-on; + }; + + buck9_reg: BUCK9 { + regulator-name = "vdd_2v"; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + regulator-always-on; + regulator-boot-on; + }; + + buck10_reg: BUCK10 { + regulator-name = "vdd_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo1_reg: LDO1 { + regulator-name = "vdd_1v0"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + ldo2_reg: LDO2 { + regulator-name = "vdd_1v2_2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + ldo3_reg: LDO3 { + regulator-name = "vdd_1v8_3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vqmmc_sdcard: ldo4_reg: LDO4 { + regulator-name = "vdd_sd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + }; + + ldo5_reg: LDO5 { + regulator-name = "vdd_1v8_5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo6_reg: LDO6 { + regulator-name = "vdd_1v8_6"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo7_reg: LDO7 { + regulator-name = "vdd_1v8_7"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo8_reg: LDO8 { + regulator-name = "vdd_ldo8"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + ldo9_reg: LDO9 { + regulator-name = "vdd_ldo9"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo10_reg: LDO10 { + regulator-name = "vdd_ldo10"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo11_reg: LDO11 { + regulator-name = "vdd_ldo11"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo12_reg: LDO12 { + regulator-name = "vdd_ldo12"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + }; + + ldo13_reg: LDO13 { + regulator-name = "vdd_ldo13"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo14_reg: LDO14 { + regulator-name = "vdd_ldo14"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo15_reg: LDO15 { + regulator-name = "vdd_ldo15"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + ldo17_reg: LDO17 { + regulator-name = "vdd_g3ds"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1400000>; + regulator-always-on; + }; + + ldo18_reg: LDO18 { + regulator-name = "ldo_18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo19_reg: LDO19 { + regulator-name = "ldo_19"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo20_reg: LDO20 { + regulator-name = "ldo_20"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo21_reg: LDO21 { + regulator-name = "ldo_21"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + ldo23_reg: LDO23 { + regulator-name = "ldo_23"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + ldo24_reg: LDO24 { + regulator-name = "ldo_24"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + ldo25_reg: LDO25 { + regulator-name = "ldo_25"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + ldo26_reg: LDO26 { + regulator-name = "ldo_26"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + ldo27_reg: LDO27 { + regulator-name = "ldo_27"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + ldo28_reg: LDO28 { + regulator-name = "ldo_28"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo29_reg: LDO29 { + regulator-name = "ldo_29"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo30_reg: LDO30 { + regulator-name = "vdd_mifs"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + ldo32_reg: LDO32 { + regulator-name = "ldo_32"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; + + ldo33_reg: LDO33 { + regulator-name = "ldo_33"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + ldo34_reg: LDO34 { + regulator-name = "ldo_34"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; + + ldo35_reg: LDO35 { + regulator-name = "ldo_35"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + }; + }; +}; + &hsi2c_7 { status = "okay"; @@ -269,12 +602,42 @@ samsung,pin-drv = <0>; }; + max77802_irq: max77802-irq { + samsung,pins = "gpx3-1"; + samsung,pin-function = <0>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + hdmi_hpd_irq: hdmi-hpd-irq { samsung,pins = "gpx3-7"; samsung,pin-function = <0>; samsung,pin-pud = <1>; samsung,pin-drv = <0>; }; + + pmic_dvs_1: pmic-dvs-1 { + samsung,pins = "gpy7-6"; + samsung,pin-function = <1>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; +}; + +&pinctrl_2 { + pmic_dvs_2: pmic-dvs-2 { + samsung,pins = "gpj4-2"; + samsung,pin-function = <1>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + pmic_dvs_3: pmic-dvs-3 { + samsung,pins = "gpj4-3"; + samsung,pin-function = <1>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; }; &pinctrl_3 { @@ -304,6 +667,14 @@ samsung,pin-pud = <0>; samsung,pin-drv = <0>; }; + + pmic_selb: pmic-selb { + samsung,pins = "gph0-2", "gph0-3", "gph0-4", "gph0-5", + "gph0-6"; + samsung,pin-function = <1>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; }; &rtc { diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts b/arch/arm/boot/dts/exynos5800-peach-pi.dts index 9ae98aa..315a8cb 100644 --- a/arch/arm/boot/dts/exynos5800-peach-pi.dts +++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts @@ -11,6 +11,7 @@ /dts-v1/; #include #include +#include #include "exynos5800.dtsi" / { @@ -142,6 +143,338 @@ ddc = <&i2c_2>; }; +&hsi2c_4 { + status = "okay"; + clock-frequency = <400000>; + + max77802-pmic@9 { + compatible = "maxim,max77802"; + interrupt-parent = <&gpx3>; + interrupts = <1 IRQ_TYPE_NONE>; + pinctrl-names = "default"; + pinctrl-0 = <&max77802_irq>, <&pmic_selb>, + <&pmic_dvs_1>, <&pmic_dvs_2>, <&pmic_dvs_3>; + wakeup-source; + reg = <0x9>; + #clock-cells = <1>; + + inb1-supply = <&tps65090_dcdc2>; + inb2-supply = <&tps65090_dcdc1>; + inb3-supply = <&tps65090_dcdc2>; + inb4-supply = <&tps65090_dcdc2>; + inb5-supply = <&tps65090_dcdc1>; + inb6-supply = <&tps65090_dcdc2>; + inb7-supply = <&tps65090_dcdc1>; + inb8-supply = <&tps65090_dcdc1>; + inb9-supply = <&tps65090_dcdc1>; + inb10-supply = <&tps65090_dcdc1>; + + inl1-supply = <&buck5_reg>; + inl2-supply = <&buck7_reg>; + inl3-supply = <&buck9_reg>; + inl4-supply = <&buck9_reg>; + inl5-supply = <&buck9_reg>; + inl6-supply = <&tps65090_dcdc2>; + inl7-supply = <&buck9_reg>; + inl9-supply = <&tps65090_dcdc2>; + inl10-supply = <&buck7_reg>; + + regulators { + buck1_reg: BUCK1 { + regulator-name = "vdd_mif"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + regulator-boot-on; + regulator-ramp-delay = <12500>; + }; + + buck2_reg: BUCK2 { + regulator-name = "vdd_arm"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + regulator-ramp-delay = <12500>; + }; + + buck3_reg: BUCK3 { + regulator-name = "vdd_int"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + regulator-always-on; + regulator-boot-on; + regulator-ramp-delay = <12500>; + }; + + buck4_reg: BUCK4 { + regulator-name = "vdd_g3d"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1400000>; + regulator-always-on; + regulator-boot-on; + regulator-ramp-delay = <12500>; + }; + + buck5_reg: BUCK5 { + regulator-name = "vdd_1v2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + }; + + buck6_reg: BUCK6 { + regulator-name = "vdd_kfc"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + regulator-ramp-delay = <12500>; + }; + + buck7_reg: BUCK7 { + regulator-name = "vdd_1v35"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + }; + + buck8_reg: BUCK8 { + regulator-name = "vdd_emmc"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + regulator-always-on; + regulator-boot-on; + }; + + buck9_reg: BUCK9 { + regulator-name = "vdd_2v"; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + regulator-always-on; + regulator-boot-on; + }; + + buck10_reg: BUCK10 { + regulator-name = "vdd_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo1_reg: LDO1 { + regulator-name = "vdd_1v0"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + ldo2_reg: LDO2 { + regulator-name = "vdd_1v2_2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + ldo3_reg: LDO3 { + regulator-name = "vdd_1v8_3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vqmmc_sdcard: ldo4_reg: LDO4 { + regulator-name = "vdd_sd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + }; + + ldo5_reg: LDO5 { + regulator-name = "vdd_1v8_5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo6_reg: LDO6 { + regulator-name = "vdd_1v8_6"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo7_reg: LDO7 { + regulator-name = "vdd_1v8_7"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo8_reg: LDO8 { + regulator-name = "vdd_ldo8"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + ldo9_reg: LDO9 { + regulator-name = "vdd_ldo9"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo10_reg: LDO10 { + regulator-name = "vdd_ldo10"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo11_reg: LDO11 { + regulator-name = "vdd_ldo11"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo12_reg: LDO12 { + regulator-name = "vdd_ldo12"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + }; + + ldo13_reg: LDO13 { + regulator-name = "vdd_ldo13"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo14_reg: LDO14 { + regulator-name = "vdd_ldo14"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo15_reg: LDO15 { + regulator-name = "vdd_ldo15"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + ldo17_reg: LDO17 { + regulator-name = "vdd_g3ds"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1400000>; + regulator-always-on; + }; + + ldo18_reg: LDO18 { + regulator-name = "ldo_18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo19_reg: LDO19 { + regulator-name = "ldo_19"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo20_reg: LDO20 { + regulator-name = "ldo_20"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo21_reg: LDO21 { + regulator-name = "ldo_21"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + ldo23_reg: LDO23 { + regulator-name = "ldo_23"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + ldo24_reg: LDO24 { + regulator-name = "ldo_24"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + ldo25_reg: LDO25 { + regulator-name = "ldo_25"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + ldo26_reg: LDO26 { + regulator-name = "ldo_26"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + ldo27_reg: LDO27 { + regulator-name = "ldo_27"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + ldo28_reg: LDO28 { + regulator-name = "ldo_28"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo29_reg: LDO29 { + regulator-name = "ldo_29"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo30_reg: LDO30 { + regulator-name = "vdd_mifs"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + ldo32_reg: LDO32 { + regulator-name = "ldo_32"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; + + ldo33_reg: LDO33 { + regulator-name = "ldo_33"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + ldo34_reg: LDO34 { + regulator-name = "ldo_34"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; + + ldo35_reg: LDO35 { + regulator-name = "ldo_35"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + }; + }; +}; + &hsi2c_7 { status = "okay"; @@ -267,12 +600,42 @@ samsung,pin-drv = <0>; }; + max77802_irq: max77802-irq { + samsung,pins = "gpx3-1"; + samsung,pin-function = <0>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + hdmi_hpd_irq: hdmi-hpd-irq { samsung,pins = "gpx3-7"; samsung,pin-function = <0>; samsung,pin-pud = <1>; samsung,pin-drv = <0>; }; + + pmic_dvs_1: pmic-dvs-1 { + samsung,pins = "gpy7-6"; + samsung,pin-function = <1>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; +}; + +&pinctrl_2 { + pmic_dvs_2: pmic-dvs-2 { + samsung,pins = "gpj4-2"; + samsung,pin-function = <1>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + pmic_dvs_3: pmic-dvs-3 { + samsung,pins = "gpj4-3"; + samsung,pin-function = <1>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; }; &pinctrl_3 { @@ -302,6 +665,14 @@ samsung,pin-pud = <0>; samsung,pin-drv = <0>; }; + + pmic_selb: pmic-selb { + samsung,pins = "gph0-2", "gph0-3", "gph0-4", "gph0-5", + "gph0-6"; + samsung,pin-function = <1>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; }; &rtc { -- cgit v0.10.2 From 1dcd48c80063652966bbf5d588d50f9781e813e1 Mon Sep 17 00:00:00 2001 From: Rahul Sharma Date: Sun, 14 Sep 2014 00:45:19 +0900 Subject: ARM: dts: add hdmi regulators for exynos5800-peach-pi Adding regulators for HDMI for Peach-pi board. Signed-off-by: Rahul Sharma Reviewed-by: Javier Martinez Canillas Signed-off-by: Javier Martinez Canillas Reviewed-by: Doug Anderson Signed-off-by: Kukjin Kim diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts b/arch/arm/boot/dts/exynos5800-peach-pi.dts index 315a8cb..7c2095b 100644 --- a/arch/arm/boot/dts/exynos5800-peach-pi.dts +++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts @@ -141,6 +141,11 @@ pinctrl-names = "default"; pinctrl-0 = <&hdmi_hpd_irq>; ddc = <&i2c_2>; + + hdmi-en-supply = <&tps65090_fet7>; + vdd-supply = <&ldo8_reg>; + vdd_osc-supply = <&ldo10_reg>; + vdd_pll-supply = <&ldo8_reg>; }; &hsi2c_4 { -- cgit v0.10.2 From e634a15242b99217189d43624b57de3fe73d47a5 Mon Sep 17 00:00:00 2001 From: Rahul Sharma Date: Sun, 14 Sep 2014 00:45:23 +0900 Subject: ARM: dts: add hdmi regulators for exynos5420-peach-pit Adding regulators for hdmi for peach-pit board. Signed-off-by: Rahul Sharma Reviewed-by: Javier Martinez Canillas Signed-off-by: Javier Martinez Canillas Reviewed-by: Doug Anderson Signed-off-by: Kukjin Kim diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts b/arch/arm/boot/dts/exynos5420-peach-pit.dts index 304e3bd..88f1620 100644 --- a/arch/arm/boot/dts/exynos5420-peach-pit.dts +++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts @@ -143,6 +143,11 @@ pinctrl-names = "default"; pinctrl-0 = <&hdmi_hpd_irq>; ddc = <&i2c_2>; + + hdmi-en-supply = <&tps65090_fet7>; + vdd-supply = <&ldo8_reg>; + vdd_osc-supply = <&ldo10_reg>; + vdd_pll-supply = <&ldo8_reg>; }; &hsi2c_4 { -- cgit v0.10.2 From 7b4880389053266c12e00e4a8fd5916c86161960 Mon Sep 17 00:00:00 2001 From: Naveen Krishna Chatradhi Date: Sun, 14 Sep 2014 00:46:56 +0900 Subject: ARM: dts: Add thermistor dts fragment used by exynos based Peach boards This patch creates a thermistor fragment carrying the NTC Thermistor nodes as children of the IIO based ADC. This fragment is included in exynos5420-peach-pit.dts and exynos5800-peach-pi.dts. Signed-off-by: Naveen Krishna Chatradhi Signed-off-by: Javier Martinez Canillas Reviewed-by: Doug Anderson Signed-off-by: Kukjin Kim diff --git a/arch/arm/boot/dts/cros-adc-thermistors.dtsi b/arch/arm/boot/dts/cros-adc-thermistors.dtsi new file mode 100644 index 0000000..acd4fe1 --- /dev/null +++ b/arch/arm/boot/dts/cros-adc-thermistors.dtsi @@ -0,0 +1,44 @@ +/* + * Thermistor dts fragment for devices that use Thermistors as + * children of the IIO based ADC. + * + * Currently, used by Exynos5420 based Peach PIT and + * Exynos5800 based Peach PI. + * + * Copyright (c) 2014 Samsung Electronics Co., Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +&adc { + ncp15wb473@3 { + compatible = "murata,ncp15wb473"; + pullup-uv = <1800000>; + pullup-ohm = <47000>; + pulldown-ohm = <0>; + io-channels = <&adc 3>; + }; + ncp15wb473@4 { + compatible = "murata,ncp15wb473"; + pullup-uv = <1800000>; + pullup-ohm = <47000>; + pulldown-ohm = <0>; + io-channels = <&adc 4>; + }; + ncp15wb473@5 { + compatible = "murata,ncp15wb473"; + pullup-uv = <1800000>; + pullup-ohm = <47000>; + pulldown-ohm = <0>; + io-channels = <&adc 5>; + }; + ncp15wb473@6 { + compatible = "murata,ncp15wb473"; + pullup-uv = <1800000>; + pullup-ohm = <47000>; + pulldown-ohm = <0>; + io-channels = <&adc 6>; + }; +}; diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts b/arch/arm/boot/dts/exynos5420-peach-pit.dts index 88f1620..07115b7 100644 --- a/arch/arm/boot/dts/exynos5420-peach-pit.dts +++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts @@ -103,6 +103,11 @@ }; }; +&adc { + status = "okay"; + vdd-supply = <&ldo9_reg>; +}; + &dp { status = "okay"; pinctrl-names = "default"; @@ -813,3 +818,4 @@ }; #include "cros-ec-keyboard.dtsi" +#include "cros-adc-thermistors.dtsi" diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts b/arch/arm/boot/dts/exynos5800-peach-pi.dts index 7c2095b..1c128e1 100644 --- a/arch/arm/boot/dts/exynos5800-peach-pi.dts +++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts @@ -101,6 +101,11 @@ }; }; +&adc { + status = "okay"; + vdd-supply = <&ldo9_reg>; +}; + &dp { status = "okay"; pinctrl-names = "default"; @@ -811,3 +816,4 @@ }; #include "cros-ec-keyboard.dtsi" +#include "cros-adc-thermistors.dtsi" -- cgit v0.10.2 From dc0cf1a3ecd53c55aecd7182bce15843ca29c895 Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Sun, 14 Sep 2014 00:47:17 +0900 Subject: ARM: dts: Add ISL29018 sensor for exynos based Peach boards The Exynos5420 based Peach Pit and the Exynos5800 based Peach Pi machines have an i2c ISL29018 light sensor. This patch adds the device nodes needed to support this device. These DTS snippets were taken from the downstream Chrome OS 3.8 kernel Device Tree for Peach Pit and Pi boards. Signed-off-by: Javier Martinez Canillas Reviewed-by: Doug Anderson Signed-off-by: Kukjin Kim diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts b/arch/arm/boot/dts/exynos5420-peach-pit.dts index 07115b7..b8fea56 100644 --- a/arch/arm/boot/dts/exynos5420-peach-pit.dts +++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts @@ -498,6 +498,12 @@ pinctrl-names = "default"; pinctrl-0 = <&max98090_irq>; }; + + light-sensor@44 { + compatible = "isil,isl29018"; + reg = <0x44>; + vcc-supply = <&tps65090_fet5>; + }; }; &hsi2c_9 { diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts b/arch/arm/boot/dts/exynos5800-peach-pi.dts index 1c128e1..17537f0 100644 --- a/arch/arm/boot/dts/exynos5800-peach-pi.dts +++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts @@ -496,6 +496,12 @@ pinctrl-names = "default"; pinctrl-0 = <&max98091_irq>; }; + + light-sensor@44 { + compatible = "isil,isl29018"; + reg = <0x44>; + vcc-supply = <&tps65090_fet5>; + }; }; &hsi2c_9 { -- cgit v0.10.2 From 8be6a6d04ceae15de160ca4cbc0915baaee801e4 Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Sun, 14 Sep 2014 00:47:22 +0900 Subject: ARM: dts: Set i2c7 clock at 400kHz for exynos based Peach boards The downstream ChromeOS 3.8 kernel sets the clock frequency for the I2C bus 7 at 400kHz. Do the same change in mainline. Suggested-by: Doug Anderson Signed-off-by: Javier Martinez Canillas Reviewed-by: Doug Anderson Signed-off-by: Kukjin Kim diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts b/arch/arm/boot/dts/exynos5420-peach-pit.dts index b8fea56..f247709 100644 --- a/arch/arm/boot/dts/exynos5420-peach-pit.dts +++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts @@ -489,6 +489,7 @@ &hsi2c_7 { status = "okay"; + clock-frequency = <400000>; max98090: codec@10 { compatible = "maxim,max98090"; diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts b/arch/arm/boot/dts/exynos5800-peach-pi.dts index 17537f0..88b3544 100644 --- a/arch/arm/boot/dts/exynos5800-peach-pi.dts +++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts @@ -487,6 +487,7 @@ &hsi2c_7 { status = "okay"; + clock-frequency = <400000>; max98091: codec@10 { compatible = "maxim,max98091"; -- cgit v0.10.2 From 6a9e7318f288d7f01b0d178d41566406c0843d38 Mon Sep 17 00:00:00 2001 From: Sjoerd Simons Date: Sun, 14 Sep 2014 01:33:15 +0900 Subject: ARM: dts: Add support Atmel touchpad for exynos5420-peach-pit The Peach Pit board has an Atmel maXTouch trackpad device. Add the needed Device Tree nodes to support it. This Device Tree change is based on the Chrome OS 3.8 tree but adapted to use the mainline Atmel maXTouch DT binding. Signed-off-by: Sjoerd Simons Signed-off-by: Javier Martinez Canillas Reviewed-by: Dmitry Torokhov Signed-off-by: Kukjin Kim diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts b/arch/arm/boot/dts/exynos5420-peach-pit.dts index f247709..22c8224 100644 --- a/arch/arm/boot/dts/exynos5420-peach-pit.dts +++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts @@ -507,6 +507,28 @@ }; }; +&hsi2c_8 { + status = "okay"; + clock-frequency = <333000>; + + /* Atmel mXT336S */ + trackpad@4b { + compatible = "atmel,maxtouch"; + reg = <0x4b>; + interrupt-parent = <&gpx1>; + interrupts = <1 IRQ_TYPE_EDGE_FALLING>; + wakeup-source; + pinctrl-names = "default"; + pinctrl-0 = <&trackpad_irq>; + linux,gpio-keymap = ; /* GPIO3 */ + }; +}; + &hsi2c_9 { status = "okay"; clock-frequency = <400000>; @@ -591,6 +613,13 @@ samsung,pin-drv = <0>; }; + trackpad_irq: trackpad-irq { + samsung,pins = "gpx1-1"; + samsung,pin-function = <0xf>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + power_key_irq: power-key-irq { samsung,pins = "gpx1-2"; samsung,pin-function = <0>; -- cgit v0.10.2 From 132fd5be706f3d91a3589f493e1ec3ec85adba6c Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Sun, 14 Sep 2014 01:33:20 +0900 Subject: ARM: dts: Add support Atmel touchpad for exynos5800-peach-pi The Peach Pi board has an Atmel maXTouch trackpad device. Add the needed Device Tree nodes to support it. This Device Tree change is based on the Chrome OS 3.8 tree but adapted to use the mainline Atmel maXTouch DT binding. Signed-off-by: Javier Martinez Canillas Reviewed-by: Dmitry Torokhov Signed-off-by: Kukjin Kim diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts b/arch/arm/boot/dts/exynos5800-peach-pi.dts index 88b3544..025a095 100644 --- a/arch/arm/boot/dts/exynos5800-peach-pi.dts +++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts @@ -505,6 +505,27 @@ }; }; +&hsi2c_8 { + status = "okay"; + clock-frequency = <333000>; + /* Atmel mXT540S */ + trackpad@4b { + compatible = "atmel,maxtouch"; + reg = <0x4b>; + interrupt-parent = <&gpx1>; + interrupts = <1 IRQ_TYPE_EDGE_FALLING>; + wakeup-source; + pinctrl-names = "default"; + pinctrl-0 = <&trackpad_irq>; + linux,gpio-keymap = ; /* GPIO 3 */ + }; +}; + &hsi2c_9 { status = "okay"; clock-frequency = <400000>; @@ -589,6 +610,13 @@ samsung,pin-drv = <0>; }; + trackpad_irq: trackpad-irq { + samsung,pins = "gpx1-1"; + samsung,pin-function = <0xf>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + power_key_irq: power-key-irq { samsung,pins = "gpx1-2"; samsung,pin-function = <0>; -- cgit v0.10.2 From a98c3c23868fbb5eda3fd321cab89c6e34cc5b47 Mon Sep 17 00:00:00 2001 From: Ajay Kumar Date: Sun, 14 Sep 2014 02:16:35 +0900 Subject: ARM: dts: update display related nodes for exynos5250-snow Add DT nodes for ptn3460 bridge chip and panel. Add backlight enable pin and backlight power supply for pwm-backlight. Also add bridge phandle needed by dp to enable display on snow. Signed-off-by: Ajay Kumar Signed-off-by: Kukjin Kim diff --git a/arch/arm/boot/dts/exynos5250-snow.dts b/arch/arm/boot/dts/exynos5250-snow.dts index 2a62459..e51fcef 100644 --- a/arch/arm/boot/dts/exynos5250-snow.dts +++ b/arch/arm/boot/dts/exynos5250-snow.dts @@ -9,6 +9,7 @@ */ /dts-v1/; +#include #include "exynos5250.dtsi" / { @@ -194,7 +195,7 @@ dcdc3 { ti,enable-ext-control; }; - fet1 { + fet1: fet1 { regulator-name = "vcd_led"; ti,overcurrent-wait = <3>; }; @@ -217,7 +218,7 @@ regulator-always-on; ti,overcurrent-wait = <3>; }; - fet6 { + fet6: fet6 { regulator-name = "lcd_vdd"; ti,overcurrent-wait = <3>; }; @@ -246,6 +247,15 @@ pinctrl-0 = <&max98095_en>; pinctrl-names = "default"; }; + + ptn3460: lvds-bridge@20 { + compatible = "nxp,ptn3460"; + reg = <0x20>; + powerdown-gpios = <&gpy2 5 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpx1 5 GPIO_ACTIVE_HIGH>; + edid-emulation = <5>; + panel = <&panel>; + }; }; i2s0: i2s@03830000 { @@ -298,11 +308,13 @@ vdd_pll-supply = <&ldo8_reg>; }; - backlight { + backlight: backlight { compatible = "pwm-backlight"; pwms = <&pwm 0 1000000 0>; brightness-levels = <0 100 500 1000 1500 2000 2500 2800>; default-brightness-level = <7>; + enable-gpios = <&gpx3 0 GPIO_ACTIVE_HIGH>; + power-supply = <&fet1>; pinctrl-0 = <&pwm0_out>; pinctrl-names = "default"; }; @@ -312,6 +324,12 @@ samsung,invert-vclk; }; + panel: panel { + compatible = "auo,b116xw03"; + power-supply = <&fet6>; + backlight = <&backlight>; + }; + dp-controller@145B0000 { status = "okay"; pinctrl-names = "default"; @@ -323,22 +341,7 @@ samsung,link-rate = <0x0a>; samsung,lane-count = <2>; samsung,hpd-gpio = <&gpx0 7 0>; - - display-timings { - native-mode = <&timing1>; - - timing1: timing@1 { - clock-frequency = <70589280>; - hactive = <1366>; - vactive = <768>; - hfront-porch = <40>; - hback-porch = <40>; - hsync-len = <32>; - vback-porch = <10>; - vfront-porch = <12>; - vsync-len = <6>; - }; - }; + bridge = <&ptn3460>; }; }; -- cgit v0.10.2 From 3b8fe9859112dd46c5aff521ec51e9e301278873 Mon Sep 17 00:00:00 2001 From: Ajay Kumar Date: Sun, 14 Sep 2014 02:20:18 +0900 Subject: ARM: dts: update display related nodes for exynos5420-peach-pit Add DT nodes for ps8622 bridge chip and panel. Add backlight power supply for pwm-backlight. Also add bridge phandle needed by dp to enable display on peach_pit. Signed-off-by: Ajay Kumar Signed-off-by: Kukjin Kim diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts b/arch/arm/boot/dts/exynos5420-peach-pit.dts index 22c8224..9a23382 100644 --- a/arch/arm/boot/dts/exynos5420-peach-pit.dts +++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts @@ -31,11 +31,12 @@ i2c20 = "/spi@12d40000/cros-ec@0/i2c-tunnel"; }; - backlight { + backlight: backlight { compatible = "pwm-backlight"; pwms = <&pwm 0 1000000 0>; brightness-levels = <0 100 500 1000 1500 2000 2500 2800>; default-brightness-level = <7>; + power-supply = <&tps65090_fet1>; pinctrl-0 = <&pwm0_out>; pinctrl-names = "default"; }; @@ -101,6 +102,12 @@ regulator-boot-on; regulator-always-on; }; + + panel: panel { + compatible = "auo,b116xw03"; + power-supply = <&tps65090_fet6>; + backlight = <&backlight>; + }; }; &adc { @@ -119,22 +126,7 @@ samsung,link-rate = <0x06>; samsung,lane-count = <2>; samsung,hpd-gpio = <&gpx2 6 0>; - - display-timings { - native-mode = <&timing1>; - - timing1: timing@1 { - clock-frequency = <70589280>; - hactive = <1366>; - vactive = <768>; - hfront-porch = <40>; - hback-porch = <40>; - hsync-len = <32>; - vback-porch = <10>; - vfront-porch = <12>; - vsync-len = <6>; - }; - }; + bridge = <&ps8625>; }; &fimd { @@ -505,6 +497,16 @@ reg = <0x44>; vcc-supply = <&tps65090_fet5>; }; + + ps8625: lvds-bridge@48 { + compatible = "parade,ps8625"; + reg = <0x48>; + sleep-gpios = <&gpx3 5 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpy7 7 GPIO_ACTIVE_HIGH>; + lane-count = <2>; + panel = <&panel>; + use-external-pwm; + }; }; &hsi2c_8 { -- cgit v0.10.2 From ce6965ebcc0a5fa4bcaeba14956ae57c4e7f339c Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Tue, 9 Sep 2014 15:27:27 +0200 Subject: ARM: dts: rockchip: remove rockchip,bus-index from rk3xxx i2c0 This is a remnant from the first i2c driver iteration that seems to have been forgotten and thus made its way into the dtsi. Remove it. Signed-off-by: Heiko Stuebner diff --git a/arch/arm/boot/dts/rk3xxx.dtsi b/arch/arm/boot/dts/rk3xxx.dtsi index cce4a07..c021df3 100644 --- a/arch/arm/boot/dts/rk3xxx.dtsi +++ b/arch/arm/boot/dts/rk3xxx.dtsi @@ -135,7 +135,6 @@ #size-cells = <0>; rockchip,grf = <&grf>; - rockchip,bus-index = <0>; clock-names = "i2c"; clocks = <&cru PCLK_I2C0>; -- cgit v0.10.2 From fd14e6f9b461c73c8706a2c7d3fb12fe07e59942 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Tue, 9 Sep 2014 15:37:27 +0200 Subject: ARM: dts: rockchip: add dwc2 controllers for rk3066 and rk3188 Add the two dwc2 controllers providing an otg and a designated host port. Signed-off-by: Heiko Stuebner diff --git a/arch/arm/boot/dts/rk3xxx.dtsi b/arch/arm/boot/dts/rk3xxx.dtsi index c021df3..c873624 100644 --- a/arch/arm/boot/dts/rk3xxx.dtsi +++ b/arch/arm/boot/dts/rk3xxx.dtsi @@ -91,6 +91,24 @@ status = "disabled"; }; + usb_otg: usb@10180000 { + compatible = "rockchip,rk3066-usb", "snps,dwc2"; + reg = <0x10180000 0x40000>; + interrupts = ; + clocks = <&cru HCLK_OTG0>; + clock-names = "otg"; + status = "disabled"; + }; + + usb_host: usb@101c0000 { + compatible = "snps,dwc2"; + reg = <0x101c0000 0x40000>; + interrupts = ; + clocks = <&cru HCLK_OTG1>; + clock-names = "otg"; + status = "disabled"; + }; + mmc0: dwmmc@10214000 { compatible = "rockchip,rk2928-dw-mshc"; reg = <0x10214000 0x1000>; -- cgit v0.10.2 From f1c8547f56f1da9db51fe3281479c823e949a9fd Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Tue, 9 Sep 2014 15:40:52 +0200 Subject: ARM: dts: rockchip: enable usb ports on Radxa Rock This enables both the otg and host port and adds the vbus regulators on the Radxa Rock board. As we don't have phy support yet, the vbus regulators are added in always-on mode. Signed-off-by: Heiko Stuebner diff --git a/arch/arm/boot/dts/rk3188-radxarock.dts b/arch/arm/boot/dts/rk3188-radxarock.dts index ff35acfa..1be0c34 100644 --- a/arch/arm/boot/dts/rk3188-radxarock.dts +++ b/arch/arm/boot/dts/rk3188-radxarock.dts @@ -65,6 +65,19 @@ pinctrl-0 = <&ir_recv_pin>; }; + vcc_otg: usb-otg-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio2 31 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&host_vbus_drv>; + regulator-name = "otg-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + vcc_sd0: sdmmc-regulator { compatible = "regulator-fixed"; regulator-name = "sdmmc-supply"; @@ -74,6 +87,19 @@ startup-delay-us = <100000>; vin-supply = <&vcc_io>; }; + + vcc_host: usb-host-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&otg_vbus_drv>; + regulator-name = "host-pwr"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; }; &i2c1 { @@ -218,6 +244,15 @@ rockchip,pins = ; }; }; + + usb { + host_vbus_drv: host-vbus-drv { + rockchip,pins = <0 3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + otg_vbus_drv: otg-vbus-drv { + rockchip,pins = <2 31 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; }; &uart0 { @@ -236,6 +271,14 @@ status = "okay"; }; +&usb_host { + status = "okay"; +}; + +&usb_otg { + status = "okay"; +}; + &wdt { status = "okay"; }; -- cgit v0.10.2 From 39c2bd782a2c50c51bced96ad3f2c97d4997d949 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Wed, 10 Sep 2014 16:28:02 +0200 Subject: ARM: dts: rockchip: add Cortex-A9 SPI controller nodes This adds basic spi nodes and pinctrl settings to the rk3066 and rk3188 devicetree files. Signed-off-by: Heiko Stuebner diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi index 879a818..8021eed 100644 --- a/arch/arm/boot/dts/rk3066a.dtsi +++ b/arch/arm/boot/dts/rk3066a.dtsi @@ -238,6 +238,42 @@ }; }; + spi0 { + spi0_clk: spi0-clk { + rockchip,pins = ; + }; + spi0_cs0: spi0-cs0 { + rockchip,pins = ; + }; + spi0_tx: spi0-tx { + rockchip,pins = ; + }; + spi0_rx: spi0-rx { + rockchip,pins = ; + }; + spi0_cs1: spi0-cs1 { + rockchip,pins = ; + }; + }; + + spi1 { + spi1_clk: spi1-clk { + rockchip,pins = ; + }; + spi1_cs0: spi1-cs0 { + rockchip,pins = ; + }; + spi1_rx: spi1-rx { + rockchip,pins = ; + }; + spi1_tx: spi1-tx { + rockchip,pins = ; + }; + spi1_cs1: spi1-cs1 { + rockchip,pins = ; + }; + }; + uart0 { uart0_xfer: uart0-xfer { rockchip,pins = , @@ -406,6 +442,16 @@ pinctrl-0 = <&pwm3_out>; }; +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; +}; + +&spi1 { + pinctrl-names = "default"; + pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_xfer>; diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi index ee801a9..573ef61 100644 --- a/arch/arm/boot/dts/rk3188.dtsi +++ b/arch/arm/boot/dts/rk3188.dtsi @@ -206,6 +206,42 @@ }; }; + spi0 { + spi0_clk: spi0-clk { + rockchip,pins = ; + }; + spi0_cs0: spi0-cs0 { + rockchip,pins = ; + }; + spi0_tx: spi0-tx { + rockchip,pins = ; + }; + spi0_rx: spi0-rx { + rockchip,pins = ; + }; + spi0_cs1: spi0-cs1 { + rockchip,pins = ; + }; + }; + + spi1 { + spi1_clk: spi1-clk { + rockchip,pins = ; + }; + spi1_cs0: spi1-cs0 { + rockchip,pins = ; + }; + spi1_rx: spi1-rx { + rockchip,pins = ; + }; + spi1_tx: spi1-tx { + rockchip,pins = ; + }; + spi1_cs1: spi1-cs1 { + rockchip,pins = ; + }; + }; + uart0 { uart0_xfer: uart0-xfer { rockchip,pins = , @@ -381,6 +417,18 @@ pinctrl-0 = <&pwm3_out>; }; +&spi0 { + compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi"; + pinctrl-names = "default"; + pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; +}; + +&spi1 { + compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi"; + pinctrl-names = "default"; + pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_xfer>; diff --git a/arch/arm/boot/dts/rk3xxx.dtsi b/arch/arm/boot/dts/rk3xxx.dtsi index c873624..7bcd698 100644 --- a/arch/arm/boot/dts/rk3xxx.dtsi +++ b/arch/arm/boot/dts/rk3xxx.dtsi @@ -26,6 +26,8 @@ i2c2 = &i2c2; i2c3 = &i2c3; i2c4 = &i2c4; + spi0 = &spi0; + spi1 = &spi1; }; xin24m: oscillator { @@ -291,4 +293,26 @@ clock-names = "saradc", "apb_pclk"; status = "disabled"; }; + + spi0: spi@20070000 { + compatible = "rockchip,rk3066-spi"; + clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; + clock-names = "spiclk", "apb_pclk"; + interrupts = ; + reg = <0x20070000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi1: spi@20074000 { + compatible = "rockchip,rk3066-spi"; + clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; + clock-names = "spiclk", "apb_pclk"; + interrupts = ; + reg = <0x20074000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; }; -- cgit v0.10.2 From 4ff4ae1258a9d091e3ab4e467ca101cd6f0ccdd0 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Wed, 10 Sep 2014 17:04:36 +0200 Subject: ARM: dts: rockchip: add emmc nodes for rk3066 and rk3188 Add the controller node, pinctrl settings for the customizable pins and sort the controllers like on rk3288 as emmc, sdmmc, sdio for handling convenience. Signed-off-by: Heiko Stuebner diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi index 8021eed..ad9c2db 100644 --- a/arch/arm/boot/dts/rk3066a.dtsi +++ b/arch/arm/boot/dts/rk3066a.dtsi @@ -179,6 +179,27 @@ bias-disable; }; + emmc { + emmc_clk: emmc-clk { + rockchip,pins = ; + }; + + emmc_cmd: emmc-cmd { + rockchip,pins = ; + }; + + emmc_rst: emmc-rst { + rockchip,pins = ; + }; + + /* + * The data pins are shared between nandc and emmc and + * not accessible through pinctrl. Also they should've + * been already set correctly by firmware, as + * flash/emmc is the boot-device. + */ + }; + i2c0 { i2c0_xfer: i2c0-xfer { rockchip,pins = , diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi index 573ef61..9a1ff0b 100644 --- a/arch/arm/boot/dts/rk3188.dtsi +++ b/arch/arm/boot/dts/rk3188.dtsi @@ -147,6 +147,27 @@ bias-disable; }; + emmc { + emmc_clk: emmc-clk { + rockchip,pins = ; + }; + + emmc_cmd: emmc-cmd { + rockchip,pins = ; + }; + + emmc_rst: emmc-rst { + rockchip,pins = ; + }; + + /* + * The data pins are shared between nandc and emmc and + * not accessible through pinctrl. Also they should've + * been already set correctly by firmware, as + * flash/emmc is the boot-device. + */ + }; + i2c0 { i2c0_xfer: i2c0-xfer { rockchip,pins = , diff --git a/arch/arm/boot/dts/rk3xxx.dtsi b/arch/arm/boot/dts/rk3xxx.dtsi index 7bcd698..c383f5c 100644 --- a/arch/arm/boot/dts/rk3xxx.dtsi +++ b/arch/arm/boot/dts/rk3xxx.dtsi @@ -26,6 +26,9 @@ i2c2 = &i2c2; i2c3 = &i2c3; i2c4 = &i2c4; + mshc0 = &emmc; + mshc1 = &mmc0; + mshc2 = &mmc1; spi0 = &spi0; spi1 = &spi1; }; @@ -137,6 +140,17 @@ status = "disabled"; }; + emmc: dwmmc@1021c000 { + compatible = "rockchip,rk2928-dw-mshc"; + reg = <0x1021c000 0x1000>; + interrupts = ; + + clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>; + clock-names = "biu", "ciu"; + + status = "disabled"; + }; + pmu: pmu@20004000 { compatible = "rockchip,rk3066-pmu", "syscon"; reg = <0x20004000 0x100>; -- cgit v0.10.2 From 71557d70b3c1c391ade6622a1369a3f2b695a1d8 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Wed, 10 Sep 2014 17:10:35 +0200 Subject: ARM: dts: rockchip: clean up rk3xxx mmc nodes Commit 356649ab6d64 ("ARM: dts: rockchip: unuse the slot-node and deprecate the supports-highspeed for dw-mmc") removed the slots but not the #xx-cells properties describing the subnodes. Do this now. Signed-off-by: Heiko Stuebner diff --git a/arch/arm/boot/dts/rk3xxx.dtsi b/arch/arm/boot/dts/rk3xxx.dtsi index c383f5c..9945bb9 100644 --- a/arch/arm/boot/dts/rk3xxx.dtsi +++ b/arch/arm/boot/dts/rk3xxx.dtsi @@ -118,8 +118,6 @@ compatible = "rockchip,rk2928-dw-mshc"; reg = <0x10214000 0x1000>; interrupts = ; - #address-cells = <1>; - #size-cells = <0>; clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>; clock-names = "biu", "ciu"; @@ -131,8 +129,6 @@ compatible = "rockchip,rk2928-dw-mshc"; reg = <0x10218000 0x1000>; interrupts = ; - #address-cells = <1>; - #size-cells = <0>; clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>; clock-names = "biu", "ciu"; -- cgit v0.10.2 From e8db78dd6af727fdbeefa1fc624bc5d7c572d841 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Thu, 11 Sep 2014 11:56:56 +0200 Subject: ARM: mvebu: add gpio fan support to Armada 370 RD The Armada 370 RD platform has a GPIO-controlled fan on MPP8, so this commit adds the relevant hardware description to Armada 370 RD Device Tree. Signed-off-by: Thomas Petazzoni Acked-by: Andrew Lunn Link: https://lkml.kernel.org/r/1410429419-29820-2-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper diff --git a/arch/arm/boot/dts/armada-370-rd.dts b/arch/arm/boot/dts/armada-370-rd.dts index ca13d9c..ea61d8c 100644 --- a/arch/arm/boot/dts/armada-370-rd.dts +++ b/arch/arm/boot/dts/armada-370-rd.dts @@ -50,6 +50,13 @@ }; internal-regs { + pinctrl { + fan_pins: fan-pins { + marvell,pins = "mpp8"; + marvell,function = "gpio"; + }; + }; + serial@12000 { status = "okay"; }; @@ -110,6 +117,14 @@ }; }; + gpio-fan { + compatible = "gpio-fan"; + gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>; + gpio-fan,speed-map = <0 0 3000 1>; + pinctrl-0 = <&fan_pins>; + pinctrl-names = "default"; + }; + nand@d0000 { status = "okay"; num-cs = <1>; -- cgit v0.10.2 From 5b1e9e80c044442cc80eb6bb03b11165515eedb8 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Thu, 11 Sep 2014 11:56:57 +0200 Subject: ARM: mvebu: add user LED support of Armada 370 RD The Armada 370 RD has a GPIO controlled LED connected on MPP32, so this commit adds the relevant hardware description to Armada 370 RD Device Tree. Signed-off-by: Thomas Petazzoni Acked-by: Andrew Lunn Link: https://lkml.kernel.org/r/1410429419-29820-3-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper diff --git a/arch/arm/boot/dts/armada-370-rd.dts b/arch/arm/boot/dts/armada-370-rd.dts index ea61d8c..14c66e4 100644 --- a/arch/arm/boot/dts/armada-370-rd.dts +++ b/arch/arm/boot/dts/armada-370-rd.dts @@ -55,6 +55,11 @@ marvell,pins = "mpp8"; marvell,function = "gpio"; }; + + led_pins: led-pins { + marvell,pins = "mpp32"; + marvell,function = "gpio"; + }; }; serial@12000 { @@ -125,6 +130,18 @@ pinctrl-names = "default"; }; + gpio_leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pins>; + + sw_led { + label = "370rd:green:sw"; + gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; + default-state = "keep"; + }; + }; + nand@d0000 { status = "okay"; num-cs = <1>; -- cgit v0.10.2 From 0a0752c6ee58f28a29e78f1a8c38f2f1b11cba9f Mon Sep 17 00:00:00 2001 From: Ajay Kumar Date: Sun, 14 Sep 2014 09:22:45 +0900 Subject: ARM: dts: update display related nodes for exynos5800-peach-pi Add DT nodes for panel-simple "auo,b133htn01" panel. Add backlight enable pin and backlight power supply for pwm-backlight. Also, add panel phandle needed by dp to enable display on peach_pi. Signed-off-by: Ajay Kumar Signed-off-by: Kukjin Kim diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts b/arch/arm/boot/dts/exynos5800-peach-pi.dts index 025a095..1d31c81 100644 --- a/arch/arm/boot/dts/exynos5800-peach-pi.dts +++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts @@ -29,11 +29,13 @@ i2c20 = "/spi@12d40000/cros-ec@0/i2c-tunnel"; }; - backlight { + backlight: backlight { compatible = "pwm-backlight"; pwms = <&pwm 0 1000000 0>; brightness-levels = <0 100 500 1000 1500 2000 2500 2800>; default-brightness-level = <7>; + enable-gpios = <&gpx2 2 GPIO_ACTIVE_HIGH>; + power-supply = <&tps65090_fet1>; pinctrl-0 = <&pwm0_out>; pinctrl-names = "default"; }; @@ -99,6 +101,12 @@ regulator-boot-on; regulator-always-on; }; + + panel: panel { + compatible = "auo,b133htn01"; + power-supply = <&tps65090_fet6>; + backlight = <&backlight>; + }; }; &adc { @@ -117,22 +125,7 @@ samsung,link-rate = <0x0a>; samsung,lane-count = <2>; samsung,hpd-gpio = <&gpx2 6 0>; - - display-timings { - native-mode = <&timing1>; - - timing1: timing@1 { - clock-frequency = <150660000>; - hactive = <1920>; - vactive = <1080>; - hfront-porch = <60>; - hback-porch = <172>; - hsync-len = <80>; - vback-porch = <25>; - vfront-porch = <10>; - vsync-len = <10>; - }; - }; + panel = <&panel>; }; &fimd { -- cgit v0.10.2 From 72a810810ff9e7a80f71f09f431c1b52156cbdda Mon Sep 17 00:00:00 2001 From: Bartlomiej Zolnierkiewicz Date: Sun, 14 Sep 2014 10:08:33 +0900 Subject: ARM: dts: remove old USB2 PHY node hook for exynos5250-arndale drivers/usb/phy/phy-samsung-usb2 driver got replaced by drivers/phy/phy-samsung-usb2 one. Remove the leftover hook from Arndale dts file. Cc: Mark Brown Cc: Kamil Debski Cc: Vivek Gautam Signed-off-by: Bartlomiej Zolnierkiewicz Acked-by: Kyungmin Park Acked-by: Kishon Vijay Abraham I Reviewed-by: Vivek Gautam Reviewed-by: Jingoo Han Signed-off-by: Kukjin Kim diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts index 42a3590..3acd97e 100644 --- a/arch/arm/boot/dts/exynos5250-arndale.dts +++ b/arch/arm/boot/dts/exynos5250-arndale.dts @@ -562,8 +562,4 @@ connect-gpios = <&gpd1 7 1>; }; }; - - usb@12110000 { - usb-phy = <&usb2_phy>; - }; }; -- cgit v0.10.2 From 9b02732643d9f4b92b14f5ec041c166bd36033fc Mon Sep 17 00:00:00 2001 From: Bartlomiej Zolnierkiewicz Date: Sun, 14 Sep 2014 10:08:37 +0900 Subject: ARM: dts: remove old USB2 PHY node for exynos5250 drivers/usb/phy/phy-samsung-usb2 driver got replaced by drivers/phy/phy-samsung-usb2 one. Remove the leftover USB2 PHY node (EHCI/OHCI USB nodes are using the new one already) from Exynos5250 dtsi file. Cc: Mark Brown Cc: Kamil Debski Cc: Vivek Gautam Signed-off-by: Bartlomiej Zolnierkiewicz Acked-by: Kyungmin Park Acked-by: Kishon Vijay Abraham I Reviewed-by: Vivek Gautam Reviewed-by: Jingoo Han Signed-off-by: Kukjin Kim diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi index 492e1ef..f21b9aa 100644 --- a/arch/arm/boot/dts/exynos5250.dtsi +++ b/arch/arm/boot/dts/exynos5250.dtsi @@ -603,21 +603,6 @@ }; }; - usb2_phy: usbphy@12130000 { - compatible = "samsung,exynos5250-usb2phy"; - reg = <0x12130000 0x100>; - clocks = <&clock CLK_FIN_PLL>, <&clock CLK_USB2>; - clock-names = "ext_xtal", "usbhost"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - usbphy-sys { - reg = <0x10040704 0x8>, - <0x10050230 0x4>; - }; - }; - usb2_phy_gen: phy@12130000 { compatible = "samsung,exynos5250-usb2-phy"; reg = <0x12130000 0x100>; -- cgit v0.10.2 From 34abee398119acaed0b1fb4318eca5b364cf74e2 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 15 Sep 2014 12:21:17 +0200 Subject: ARM: shmobile: r8a73a4 dtsi: Add SoC-specific irqc compatible property The interrupt controller used the generic compatible property only. Add the SoC-specific one, to make it future proof. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman diff --git a/arch/arm/boot/dts/r8a73a4.dtsi b/arch/arm/boot/dts/r8a73a4.dtsi index fba39a2..ef152e3 100644 --- a/arch/arm/boot/dts/r8a73a4.dtsi +++ b/arch/arm/boot/dts/r8a73a4.dtsi @@ -51,7 +51,7 @@ }; irqc0: interrupt-controller@e61c0000 { - compatible = "renesas,irqc"; + compatible = "renesas,irqc-r8a73a4", "renesas,irqc"; #interrupt-cells = <2>; interrupt-controller; reg = <0 0xe61c0000 0 0x200>; @@ -90,7 +90,7 @@ }; irqc1: interrupt-controller@e61c0200 { - compatible = "renesas,irqc"; + compatible = "renesas,irqc-r8a73a4", "renesas,irqc"; #interrupt-cells = <2>; interrupt-controller; reg = <0 0xe61c0200 0 0x200>; -- cgit v0.10.2 From 10f34a1341e374f372e3ff82f674e2475b262f9b Mon Sep 17 00:00:00 2001 From: Stefan Agner Date: Fri, 18 Jul 2014 16:25:18 +0200 Subject: ARM: dts: vf610-colibri: split device tree for carrier boards The Colibri VF61 is a module which needs a carrier board to actually run. Different carrier board have different hardware support, hence we should reflect this in the device tree files. This patch adds the Colibri Evaluation Board, which supports almost all peripherals defined in the Colibri standard. Also align the compatible naming, file splitting and file naming with the scheme which was choosen for the Tegra based modules. Signed-off-by: Stefan Agner Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index b8c5cd3..acb6b42 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -240,7 +240,7 @@ dtb-$(CONFIG_ARCH_MXC) += \ imx6q-tx6q-1110.dtb \ imx6sl-evk.dtb \ imx6sx-sdb.dtb \ - vf610-colibri.dtb \ + vf610-colibri-eval-v3.dtb \ vf610-cosmic.dtb \ vf610-twr.dtb dtb-$(CONFIG_ARCH_MXS) += imx23-evk.dtb \ diff --git a/arch/arm/boot/dts/vf610-colibri-eval-v3.dts b/arch/arm/boot/dts/vf610-colibri-eval-v3.dts new file mode 100644 index 0000000..7fb3066 --- /dev/null +++ b/arch/arm/boot/dts/vf610-colibri-eval-v3.dts @@ -0,0 +1,46 @@ +/* + * Copyright 2014 Toradex AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +/dts-v1/; +#include "vf610-colibri.dtsi" + +/ { + model = "Toradex Colibri VF61 on Colibri Evaluation Board"; + compatible = "toradex,vf610-colibri_vf61-on-eval", "toradex,vf610-colibri_vf61", "fsl,vf610"; + + chosen { + bootargs = "console=ttyLP0,115200"; + }; +}; + +&esdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc1>; + bus-width = <4>; + status = "okay"; +}; + +&fec1 { + phy-mode = "rmii"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/vf610-colibri.dts b/arch/arm/boot/dts/vf610-colibri.dts deleted file mode 100644 index aecc7db..0000000 --- a/arch/arm/boot/dts/vf610-colibri.dts +++ /dev/null @@ -1,123 +0,0 @@ -/* - * Copyright 2014 Toradex AG - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -/dts-v1/; -#include "vf610.dtsi" - -/ { - model = "Toradex Colibri VF61 COM"; - compatible = "toradex,vf610-colibri", "fsl,vf610"; - - chosen { - bootargs = "console=ttyLP0,115200"; - }; - - memory { - reg = <0x80000000 0x10000000>; - }; - - clocks { - enet_ext { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <50000000>; - }; - }; - -}; - -&esdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc1>; - bus-width = <4>; - status = "okay"; -}; - -&fec1 { - phy-mode = "rmii"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec1>; - status = "okay"; -}; - -&L2 { - arm,data-latency = <2 1 2>; - arm,tag-latency = <3 2 3>; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart0>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&iomuxc { - vf610-colibri { - pinctrl_esdhc1: esdhc1grp { - fsl,fsl,pins = < - VF610_PAD_PTA24__ESDHC1_CLK 0x31ef - VF610_PAD_PTA25__ESDHC1_CMD 0x31ef - VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef - VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef - VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef - VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef - VF610_PAD_PTB20__GPIO_42 0x219d - >; - }; - - pinctrl_fec1: fec1grp { - fsl,pins = < - VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2 - VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3 - VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1 - VF610_PAD_PTC12__ENET_RMII_RXD1 0x30d1 - VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1 - VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1 - VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2 - VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2 - VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2 - >; - }; - - pinctrl_uart0: uart0grp { - fsl,pins = < - VF610_PAD_PTB10__UART0_TX 0x21a2 - VF610_PAD_PTB11__UART0_RX 0x21a1 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - VF610_PAD_PTB4__UART1_TX 0x21a2 - VF610_PAD_PTB5__UART1_RX 0x21a1 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - VF610_PAD_PTD0__UART2_TX 0x21a2 - VF610_PAD_PTD1__UART2_RX 0x21a1 - VF610_PAD_PTD2__UART2_RTS 0x21a2 - VF610_PAD_PTD3__UART2_CTS 0x21a1 - >; - }; - }; -}; diff --git a/arch/arm/boot/dts/vf610-colibri.dtsi b/arch/arm/boot/dts/vf610-colibri.dtsi new file mode 100644 index 0000000..e595c29 --- /dev/null +++ b/arch/arm/boot/dts/vf610-colibri.dtsi @@ -0,0 +1,113 @@ +/* + * Copyright 2014 Toradex AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include "vf610.dtsi" + +/ { + model = "Toradex Colibri VF61 COM"; + compatible = "toradex,vf610-colibri_vf61", "fsl,vf610"; + + memory { + reg = <0x80000000 0x10000000>; + }; + + clocks { + enet_ext { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + }; + }; + +}; + +&esdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc1>; + bus-width = <4>; +}; + +&fec1 { + phy-mode = "rmii"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; +}; + +&L2 { + arm,data-latency = <2 1 2>; + arm,tag-latency = <3 2 3>; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart0>; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; +}; + +&iomuxc { + vf610-colibri { + pinctrl_esdhc1: esdhc1grp { + fsl,pins = < + VF610_PAD_PTA24__ESDHC1_CLK 0x31ef + VF610_PAD_PTA25__ESDHC1_CMD 0x31ef + VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef + VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef + VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef + VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef + VF610_PAD_PTB20__GPIO_42 0x219d + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2 + VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3 + VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1 + VF610_PAD_PTC12__ENET_RMII_RXD1 0x30d1 + VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1 + VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1 + VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2 + VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2 + VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2 + >; + }; + + pinctrl_uart0: uart0grp { + fsl,pins = < + VF610_PAD_PTB10__UART0_TX 0x21a2 + VF610_PAD_PTB11__UART0_RX 0x21a1 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + VF610_PAD_PTB4__UART1_TX 0x21a2 + VF610_PAD_PTB5__UART1_RX 0x21a1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + VF610_PAD_PTD0__UART2_TX 0x21a2 + VF610_PAD_PTD1__UART2_RX 0x21a1 + VF610_PAD_PTD2__UART2_RTS 0x21a2 + VF610_PAD_PTD3__UART2_CTS 0x21a1 + >; + }; + }; +}; -- cgit v0.10.2 From 78827ec071ef4971a89e1da6349f2b73539639c3 Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Wed, 23 Jul 2014 19:29:11 +0200 Subject: ARM: dts: imx6qdl-sabresd: add always on pcie regulator Everything in the PCI specification assumes devices to be enumerable on startup. This is only possible if they have power available. A future improvement may allow this regulator to be switched off for D3hot and D3cold power states, but there is a lot of work to do the pcie host controller side for this to work. To keep things simple always enable the regulator for now. Signed-off-by: Lucas Stach Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi index ec43dde..07fb302 100644 --- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi @@ -54,6 +54,19 @@ gpio = <&gpio4 10 0>; enable-active-high; }; + + reg_pcie: regulator@3 { + compatible = "regulator-fixed"; + reg = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie_reg>; + regulator-name = "MPCIE_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio3 19 0>; + regulator-always-on; + enable-active-high; + }; }; gpio-keys { @@ -400,6 +413,12 @@ >; }; + pinctrl_pcie_reg: pciereggrp { + fsl,pins = < + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x1b0b0 + >; + }; + pinctrl_pwm1: pwm1grp { fsl,pins = < MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1 -- cgit v0.10.2 From 43c3c0069493849892ac34ccfc328e5043ac9e6b Mon Sep 17 00:00:00 2001 From: Michael Olbrich Date: Fri, 25 Jul 2014 12:49:51 +0200 Subject: ARM: dts: nitrogen6x: add i2c2 Signed-off-by: Michael Olbrich Signed-off-by: Lucas Stach Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi b/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi index 42ff525..f402eb9 100644 --- a/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi +++ b/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi @@ -189,6 +189,13 @@ }; }; +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + &iomuxc { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_hog>; @@ -266,6 +273,13 @@ >; }; + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + pinctrl_pwm1: pwm1grp { fsl,pins = < MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1 -- cgit v0.10.2 From d653620e8fba04b1677bc3104dcbdc413673f0c7 Mon Sep 17 00:00:00 2001 From: Michael Olbrich Date: Fri, 25 Jul 2014 12:49:52 +0200 Subject: ARM: dts: nitrogen6x: add hdmi Signed-off-by: Michael Olbrich Signed-off-by: Lucas Stach Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi b/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi index f402eb9..f07d947 100644 --- a/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi +++ b/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi @@ -174,6 +174,11 @@ status = "okay"; }; +&hdmi { + ddc-i2c-bus = <&i2c2>; + status = "okay"; +}; + &i2c1 { clock-frequency = <100000>; pinctrl-names = "default"; -- cgit v0.10.2 From 1dffdd6816faa0cb3936a3a354223a95d646de22 Mon Sep 17 00:00:00 2001 From: Philipp Zabel Date: Fri, 25 Jul 2014 12:49:53 +0200 Subject: ARM: dts: nitrogen6x: add i2c3 Signed-off-by: Philipp Zabel Signed-off-by: Lucas Stach Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi b/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi index f07d947..2c67048 100644 --- a/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi +++ b/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi @@ -201,6 +201,13 @@ status = "okay"; }; +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; +}; + &iomuxc { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_hog>; @@ -285,6 +292,13 @@ >; }; + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1 + >; + }; + pinctrl_pwm1: pwm1grp { fsl,pins = < MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1 -- cgit v0.10.2 From d0eb8fc5a59200a51b47f91b14242751b3225dda Mon Sep 17 00:00:00 2001 From: Alexander Shiyan Date: Sat, 26 Jul 2014 13:45:29 +0400 Subject: ARM: dts: i.MX1: Add i.MX1 template This patch adds basic devicetree template for i.MX1 based SoCs. Signed-off-by: Alexander Shiyan Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/imx1-pinfunc.h b/arch/arm/boot/dts/imx1-pinfunc.h new file mode 100644 index 0000000..22bec8b --- /dev/null +++ b/arch/arm/boot/dts/imx1-pinfunc.h @@ -0,0 +1,302 @@ +/* + * Copyright (C) 2014 Alexander Shiyan + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#ifndef __DTS_IMX1_PINFUNC_H +#define __DTS_IMX1_PINFUNC_H + +/* + * The pin function ID is a tuple of + * + * mux_id consists of + * function + (direction << 2) + (gpio_oconf << 4) + (gpio_iconfa << 8) + (gpio_iconfb << 10) + * + * function: 0 - Primary function + * 1 - Alternate function + * 2 - GPIO + * direction: 0 - Input + * 1 - Output + * gpio_oconf: 0 - A_IN + * 1 - B_IN + * 2 - A_OUT + * 3 - Data Register + * gpio_iconfa/b: 0 - GPIO_IN + * 1 - Interrupt Status Register + * 2 - 0 + * 3 - 1 + * + * 'pin' is an integer between 0 and 0xbf. i.MX1 has 4 ports with 32 configurable + * configurable pins each. 'pin' is PORT * 32 + PORT_PIN, PORT_PIN is the pin + * number on the specific port (between 0 and 31). + */ + +#define MX1_PAD_A24__A24 0x00 0x004 +#define MX1_PAD_A24__GPIO1_0 0x00 0x032 +#define MX1_PAD_A24__SPI2_CLK 0x00 0x006 +#define MX1_PAD_TIN__TIN 0x01 0x000 +#define MX1_PAD_TIN__GPIO1_1 0x01 0x032 +#define MX1_PAD_TIN__SPI2_RXD 0x01 0x022 +#define MX1_PAD_PWMO__PWMO 0x02 0x004 +#define MX1_PAD_PWMO__GPIO1_2 0x02 0x032 +#define MX1_PAD_CSI_MCLK__CSI_MCLK 0x03 0x004 +#define MX1_PAD_CSI_MCLK__GPIO1_3 0x03 0x032 +#define MX1_PAD_CSI_D0__CSI_D0 0x04 0x000 +#define MX1_PAD_CSI_D0__GPIO1_4 0x04 0x032 +#define MX1_PAD_CSI_D1__CSI_D1 0x05 0x000 +#define MX1_PAD_CSI_D1__GPIO1_5 0x05 0x032 +#define MX1_PAD_CSI_D2__CSI_D2 0x06 0x000 +#define MX1_PAD_CSI_D2__GPIO1_6 0x06 0x032 +#define MX1_PAD_CSI_D3__CSI_D3 0x07 0x000 +#define MX1_PAD_CSI_D3__GPIO1_7 0x07 0x032 +#define MX1_PAD_CSI_D4__CSI_D4 0x08 0x000 +#define MX1_PAD_CSI_D4__GPIO1_8 0x08 0x032 +#define MX1_PAD_CSI_D5__CSI_D5 0x09 0x000 +#define MX1_PAD_CSI_D5__GPIO1_9 0x09 0x032 +#define MX1_PAD_CSI_D6__CSI_D6 0x0a 0x000 +#define MX1_PAD_CSI_D6__GPIO1_10 0x0a 0x032 +#define MX1_PAD_CSI_D7__CSI_D7 0x0b 0x000 +#define MX1_PAD_CSI_D7__GPIO1_11 0x0b 0x032 +#define MX1_PAD_CSI_VSYNC__CSI_VSYNC 0x0c 0x000 +#define MX1_PAD_CSI_VSYNC__GPIO1_12 0x0c 0x032 +#define MX1_PAD_CSI_HSYNC__CSI_HSYNC 0x0d 0x000 +#define MX1_PAD_CSI_HSYNC__GPIO1_13 0x0d 0x032 +#define MX1_PAD_CSI_PIXCLK__CSI_PIXCLK 0x0e 0x000 +#define MX1_PAD_CSI_PIXCLK__GPIO1_14 0x0e 0x032 +#define MX1_PAD_I2C_SDA__I2C_SDA 0x0f 0x000 +#define MX1_PAD_I2C_SDA__GPIO1_15 0x0f 0x032 +#define MX1_PAD_I2C_SCL__I2C_SCL 0x10 0x004 +#define MX1_PAD_I2C_SCL__GPIO1_16 0x10 0x032 +#define MX1_PAD_DTACK__DTACK 0x11 0x000 +#define MX1_PAD_DTACK__GPIO1_17 0x11 0x032 +#define MX1_PAD_DTACK__SPI2_SS 0x11 0x002 +#define MX1_PAD_DTACK__A25 0x11 0x016 +#define MX1_PAD_BCLK__BCLK 0x12 0x004 +#define MX1_PAD_BCLK__GPIO1_18 0x12 0x032 +#define MX1_PAD_LBA__LBA 0x13 0x004 +#define MX1_PAD_LBA__GPIO1_19 0x13 0x032 +#define MX1_PAD_ECB__ECB 0x14 0x000 +#define MX1_PAD_ECB__GPIO1_20 0x14 0x032 +#define MX1_PAD_A0__A0 0x15 0x004 +#define MX1_PAD_A0__GPIO1_21 0x15 0x032 +#define MX1_PAD_CS4__CS4 0x16 0x004 +#define MX1_PAD_CS4__GPIO1_22 0x16 0x032 +#define MX1_PAD_CS5__CS5 0x17 0x004 +#define MX1_PAD_CS5__GPIO1_23 0x17 0x032 +#define MX1_PAD_A16__A16 0x18 0x004 +#define MX1_PAD_A16__GPIO1_24 0x18 0x032 +#define MX1_PAD_A17__A17 0x19 0x004 +#define MX1_PAD_A17__GPIO1_25 0x19 0x032 +#define MX1_PAD_A18__A18 0x1a 0x004 +#define MX1_PAD_A18__GPIO1_26 0x1a 0x032 +#define MX1_PAD_A19__A19 0x1b 0x004 +#define MX1_PAD_A19__GPIO1_27 0x1b 0x032 +#define MX1_PAD_A20__A20 0x1c 0x004 +#define MX1_PAD_A20__GPIO1_28 0x1c 0x032 +#define MX1_PAD_A21__A21 0x1d 0x004 +#define MX1_PAD_A21__GPIO1_29 0x1d 0x032 +#define MX1_PAD_A22__A22 0x1e 0x004 +#define MX1_PAD_A22__GPIO1_30 0x1e 0x032 +#define MX1_PAD_A23__A23 0x1f 0x004 +#define MX1_PAD_A23__GPIO1_31 0x1f 0x032 +#define MX1_PAD_SD_DAT0__SD_DAT0 0x28 0x000 +#define MX1_PAD_SD_DAT0__MS_PI0 0x28 0x001 +#define MX1_PAD_SD_DAT0__GPIO2_8 0x28 0x032 +#define MX1_PAD_SD_DAT1__SD_DAT1 0x29 0x000 +#define MX1_PAD_SD_DAT1__MS_PI1 0x29 0x001 +#define MX1_PAD_SD_DAT1__GPIO2_9 0x29 0x032 +#define MX1_PAD_SD_DAT2__SD_DAT2 0x2a 0x000 +#define MX1_PAD_SD_DAT2__MS_SCLKI 0x2a 0x001 +#define MX1_PAD_SD_DAT2__GPIO2_10 0x2a 0x032 +#define MX1_PAD_SD_DAT3__SD_DAT3 0x2b 0x000 +#define MX1_PAD_SD_DAT3__MS_SDIO 0x2b 0x001 +#define MX1_PAD_SD_DAT3__GPIO2_11 0x2b 0x032 +#define MX1_PAD_SD_SCLK__SD_SCLK 0x2c 0x004 +#define MX1_PAD_SD_SCLK__MS_SCLKO 0x2c 0x005 +#define MX1_PAD_SD_SCLK__GPIO2_12 0x2c 0x032 +#define MX1_PAD_SD_CMD__SD_CMD 0x2d 0x000 +#define MX1_PAD_SD_CMD__MS_BS 0x2d 0x005 +#define MX1_PAD_SD_CMD__GPIO2_13 0x2d 0x032 +#define MX1_PAD_SIM_SVEN__SIM_SVEN 0x2e 0x004 +#define MX1_PAD_SIM_SVEN__SSI_RXFS 0x2e 0x001 +#define MX1_PAD_SIM_SVEN__GPIO2_14 0x2e 0x032 +#define MX1_PAD_SIM_PD__SIM_PD 0x2f 0x000 +#define MX1_PAD_SIM_PD__SSI_RXCLK 0x2f 0x001 +#define MX1_PAD_SIM_PD__GPIO2_15 0x2f 0x032 +#define MX1_PAD_SIM_TX__SIM_TX 0x30 0x000 +#define MX1_PAD_SIM_TX__SSI_RXDAT 0x30 0x001 +#define MX1_PAD_SIM_TX__GPIO2_16 0x30 0x032 +#define MX1_PAD_SIM_RX__SIM_RX 0x31 0x000 +#define MX1_PAD_SIM_RX__SSI_TXDAT 0x31 0x005 +#define MX1_PAD_SIM_RX__GPIO2_17 0x31 0x032 +#define MX1_PAD_SIM_RST__SIM_RST 0x32 0x004 +#define MX1_PAD_SIM_RST__SSI_TXFS 0x32 0x001 +#define MX1_PAD_SIM_RST__GPIO2_18 0x32 0x032 +#define MX1_PAD_SIM_CLK__SIM_CLK 0x33 0x004 +#define MX1_PAD_SIM_CLK__SSI_TXCLK 0x33 0x001 +#define MX1_PAD_SIM_CLK__GPIO2_19 0x33 0x032 +#define MX1_PAD_USBD_AFE__USBD_AFE 0x34 0x004 +#define MX1_PAD_USBD_AFE__GPIO2_20 0x34 0x032 +#define MX1_PAD_USBD_OE__USBD_OE 0x35 0x004 +#define MX1_PAD_USBD_OE__GPIO2_21 0x35 0x032 +#define MX1_PAD_USBD_RCV__USBD_RCV 0x36 0x000 +#define MX1_PAD_USBD_RCV__GPIO2_22 0x36 0x032 +#define MX1_PAD_USBD_SUSPND__USBD_SUSPND 0x37 0x004 +#define MX1_PAD_USBD_SUSPND__GPIO2_23 0x37 0x032 +#define MX1_PAD_USBD_VP__USBD_VP 0x38 0x000 +#define MX1_PAD_USBD_VP__GPIO2_24 0x38 0x032 +#define MX1_PAD_USBD_VM__USBD_VM 0x39 0x000 +#define MX1_PAD_USBD_VM__GPIO2_25 0x39 0x032 +#define MX1_PAD_USBD_VPO__USBD_VPO 0x3a 0x004 +#define MX1_PAD_USBD_VPO__GPIO2_26 0x3a 0x032 +#define MX1_PAD_USBD_VMO__USBD_VMO 0x3b 0x004 +#define MX1_PAD_USBD_VMO__GPIO2_27 0x3b 0x032 +#define MX1_PAD_UART2_CTS__UART2_CTS 0x3c 0x004 +#define MX1_PAD_UART2_CTS__GPIO2_28 0x3c 0x032 +#define MX1_PAD_UART2_RTS__UART2_RTS 0x3d 0x000 +#define MX1_PAD_UART2_RTS__GPIO2_29 0x3d 0x032 +#define MX1_PAD_UART2_TXD__UART2_TXD 0x3e 0x004 +#define MX1_PAD_UART2_TXD__GPIO2_30 0x3e 0x032 +#define MX1_PAD_UART2_RXD__UART2_RXD 0x3f 0x000 +#define MX1_PAD_UART2_RXD__GPIO2_31 0x3f 0x032 +#define MX1_PAD_SSI_RXFS__SSI_RXFS 0x43 0x000 +#define MX1_PAD_SSI_RXFS__GPIO3_3 0x43 0x032 +#define MX1_PAD_SSI_RXCLK__SSI_RXCLK 0x44 0x000 +#define MX1_PAD_SSI_RXCLK__GPIO3_4 0x44 0x032 +#define MX1_PAD_SSI_RXDAT__SSI_RXDAT 0x45 0x000 +#define MX1_PAD_SSI_RXDAT__GPIO3_5 0x45 0x032 +#define MX1_PAD_SSI_TXDAT__SSI_TXDAT 0x46 0x004 +#define MX1_PAD_SSI_TXDAT__GPIO3_6 0x46 0x032 +#define MX1_PAD_SSI_TXFS__SSI_TXFS 0x47 0x000 +#define MX1_PAD_SSI_TXFS__GPIO3_7 0x47 0x032 +#define MX1_PAD_SSI_TXCLK__SSI_TXCLK 0x48 0x000 +#define MX1_PAD_SSI_TXCLK__GPIO3_8 0x48 0x032 +#define MX1_PAD_UART1_CTS__UART1_CTS 0x49 0x004 +#define MX1_PAD_UART1_CTS__GPIO3_9 0x49 0x032 +#define MX1_PAD_UART1_RTS__UART1_RTS 0x4a 0x000 +#define MX1_PAD_UART1_RTS__GPIO3_10 0x4a 0x032 +#define MX1_PAD_UART1_TXD__UART1_TXD 0x4b 0x004 +#define MX1_PAD_UART1_TXD__GPIO3_11 0x4b 0x032 +#define MX1_PAD_UART1_RXD__UART1_RXD 0x4c 0x000 +#define MX1_PAD_UART1_RXD__GPIO3_12 0x4c 0x032 +#define MX1_PAD_SPI1_RDY__SPI1_RDY 0x4d 0x000 +#define MX1_PAD_SPI1_RDY__GPIO3_13 0x4d 0x032 +#define MX1_PAD_SPI1_SCLK__SPI1_SCLK 0x4e 0x004 +#define MX1_PAD_SPI1_SCLK__GPIO3_14 0x4e 0x032 +#define MX1_PAD_SPI1_SS__SPI1_SS 0x4f 0x000 +#define MX1_PAD_SPI1_SS__GPIO3_15 0x4f 0x032 +#define MX1_PAD_SPI1_MISO__SPI1_MISO 0x50 0x000 +#define MX1_PAD_SPI1_MISO__GPIO3_16 0x50 0x032 +#define MX1_PAD_SPI1_MOSI__SPI1_MOSI 0x51 0x004 +#define MX1_PAD_SPI1_MOSI__GPIO3_17 0x51 0x032 +#define MX1_PAD_BT13__BT13 0x53 0x004 +#define MX1_PAD_BT13__SSI2_RXCLK 0x53 0x001 +#define MX1_PAD_BT13__GPIO3_19 0x53 0x032 +#define MX1_PAD_BT12__BT12 0x54 0x004 +#define MX1_PAD_BT12__SSI2_TXFS 0x54 0x001 +#define MX1_PAD_BT12__GPIO3_20 0x54 0x032 +#define MX1_PAD_BT11__BT11 0x55 0x004 +#define MX1_PAD_BT11__SSI2_TXCLK 0x55 0x001 +#define MX1_PAD_BT11__GPIO3_21 0x55 0x032 +#define MX1_PAD_BT10__BT10 0x56 0x004 +#define MX1_PAD_BT10__SSI2_TX 0x56 0x001 +#define MX1_PAD_BT10__GPIO3_22 0x56 0x032 +#define MX1_PAD_BT9__BT9 0x57 0x004 +#define MX1_PAD_BT9__SSI2_RX 0x57 0x001 +#define MX1_PAD_BT9__GPIO3_23 0x57 0x032 +#define MX1_PAD_BT8__BT8 0x58 0x004 +#define MX1_PAD_BT8__SSI2_RXFS 0x58 0x001 +#define MX1_PAD_BT8__GPIO3_24 0x58 0x032 +#define MX1_PAD_BT8__UART3_RI 0x58 0x016 +#define MX1_PAD_BT7__BT7 0x59 0x004 +#define MX1_PAD_BT7__GPIO3_25 0x59 0x032 +#define MX1_PAD_BT7__UART3_DSR 0x59 0x016 +#define MX1_PAD_BT6__BT6 0x5a 0x004 +#define MX1_PAD_BT6__GPIO3_26 0x5a 0x032 +#define MX1_PAD_BT6__SPI2_SS3 0x5a 0x016 +#define MX1_PAD_BT6__UART3_DTR 0x5a 0x022 +#define MX1_PAD_BT5__BT5 0x5b 0x000 +#define MX1_PAD_BT5__GPIO3_27 0x5b 0x032 +#define MX1_PAD_BT5__UART3_DCD 0x5b 0x016 +#define MX1_PAD_BT4__BT4 0x5c 0x000 +#define MX1_PAD_BT4__GPIO3_28 0x5c 0x032 +#define MX1_PAD_BT4__UART3_CTS 0x5c 0x016 +#define MX1_PAD_BT3__BT3 0x5d 0x000 +#define MX1_PAD_BT3__GPIO3_29 0x5d 0x032 +#define MX1_PAD_BT3__UART3_RTS 0x5d 0x022 +#define MX1_PAD_BT2__BT2 0x5e 0x004 +#define MX1_PAD_BT2__GPIO3_30 0x5e 0x032 +#define MX1_PAD_BT2__UART3_TX 0x5e 0x016 +#define MX1_PAD_BT1__BT1 0x5f 0x000 +#define MX1_PAD_BT1__GPIO3_31 0x5f 0x032 +#define MX1_PAD_BT1__UART3_RX 0x5f 0x022 +#define MX1_PAD_LSCLK__LSCLK 0x66 0x004 +#define MX1_PAD_LSCLK__GPIO4_6 0x66 0x032 +#define MX1_PAD_REV__REV 0x67 0x004 +#define MX1_PAD_REV__UART2_DTR 0x67 0x001 +#define MX1_PAD_REV__GPIO4_7 0x67 0x032 +#define MX1_PAD_REV__SPI2_CLK 0x67 0x006 +#define MX1_PAD_CLS__CLS 0x68 0x004 +#define MX1_PAD_CLS__UART2_DCD 0x68 0x005 +#define MX1_PAD_CLS__GPIO4_8 0x68 0x032 +#define MX1_PAD_CLS__SPI2_SS 0x68 0x002 +#define MX1_PAD_PS__PS 0x69 0x004 +#define MX1_PAD_PS__UART2_RI 0x69 0x005 +#define MX1_PAD_PS__GPIO4_9 0x69 0x032 +#define MX1_PAD_PS__SPI2_RXD 0x69 0x022 +#define MX1_PAD_SPL_SPR__SPL_SPR 0x6a 0x004 +#define MX1_PAD_SPL_SPR__UART2_DSR 0x6a 0x005 +#define MX1_PAD_SPL_SPR__GPIO4_10 0x6a 0x032 +#define MX1_PAD_SPL_SPR__SPI2_TXD 0x6a 0x006 +#define MX1_PAD_CONTRAST__CONTRAST 0x6b 0x004 +#define MX1_PAD_CONTRAST__GPIO4_11 0x6b 0x032 +#define MX1_PAD_CONTRAST__SPI2_SS2 0x6b 0x012 +#define MX1_PAD_ACD_OE__ACD_OE 0x6c 0x004 +#define MX1_PAD_ACD_OE__GPIO4_12 0x6c 0x032 +#define MX1_PAD_LP_HSYNC__LP_HSYNC 0x6d 0x004 +#define MX1_PAD_LP_HSYNC__GPIO4_13 0x6d 0x032 +#define MX1_PAD_FLM_VSYNC__FLM_VSYNC 0x6e 0x004 +#define MX1_PAD_FLM_VSYNC__GPIO4_14 0x6e 0x032 +#define MX1_PAD_LD0__LD0 0x6f 0x004 +#define MX1_PAD_LD0__GPIO4_15 0x6f 0x032 +#define MX1_PAD_LD1__LD1 0x70 0x004 +#define MX1_PAD_LD1__GPIO4_16 0x70 0x032 +#define MX1_PAD_LD2__LD2 0x71 0x004 +#define MX1_PAD_LD2__GPIO4_17 0x71 0x032 +#define MX1_PAD_LD3__LD3 0x72 0x004 +#define MX1_PAD_LD3__GPIO4_18 0x72 0x032 +#define MX1_PAD_LD4__LD4 0x73 0x004 +#define MX1_PAD_LD4__GPIO4_19 0x73 0x032 +#define MX1_PAD_LD5__LD5 0x74 0x004 +#define MX1_PAD_LD5__GPIO4_20 0x74 0x032 +#define MX1_PAD_LD6__LD6 0x75 0x004 +#define MX1_PAD_LD6__GPIO4_21 0x75 0x032 +#define MX1_PAD_LD7__LD7 0x76 0x004 +#define MX1_PAD_LD7__GPIO4_22 0x76 0x032 +#define MX1_PAD_LD8__LD8 0x77 0x004 +#define MX1_PAD_LD8__GPIO4_23 0x77 0x032 +#define MX1_PAD_LD9__LD9 0x78 0x004 +#define MX1_PAD_LD9__GPIO4_24 0x78 0x032 +#define MX1_PAD_LD10__LD10 0x79 0x004 +#define MX1_PAD_LD10__GPIO4_25 0x79 0x032 +#define MX1_PAD_LD11__LD11 0x7a 0x004 +#define MX1_PAD_LD11__GPIO4_26 0x7a 0x032 +#define MX1_PAD_LD12__LD12 0x7b 0x004 +#define MX1_PAD_LD12__GPIO4_27 0x7b 0x032 +#define MX1_PAD_LD13__LD13 0x7c 0x004 +#define MX1_PAD_LD13__GPIO4_28 0x7c 0x032 +#define MX1_PAD_LD14__LD14 0x7d 0x004 +#define MX1_PAD_LD14__GPIO4_29 0x7d 0x032 +#define MX1_PAD_LD15__LD15 0x7e 0x004 +#define MX1_PAD_LD15__GPIO4_30 0x7e 0x032 +#define MX1_PAD_TMR2OUT__TMR2OUT 0x7f 0x000 +#define MX1_PAD_TMR2OUT__GPIO4_31 0x7f 0x032 +#define MX1_PAD_TMR2OUT__SPI2_TXD 0x7f 0x006 + +#endif diff --git a/arch/arm/boot/dts/imx1.dtsi b/arch/arm/boot/dts/imx1.dtsi new file mode 100644 index 0000000..22f5d1d --- /dev/null +++ b/arch/arm/boot/dts/imx1.dtsi @@ -0,0 +1,266 @@ +/* + * Copyright (C) 2014 Alexander Shiyan + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include "skeleton.dtsi" +#include "imx1-pinfunc.h" + +#include +#include +#include + +/ { + aliases { + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + gpio3 = &gpio4; + i2c0 = &i2c; + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + spi0 = &cspi1; + spi1 = &cspi2; + }; + + aitc: aitc-interrupt-controller@00223000 { + compatible = "fsl,imx1-aitc", "fsl,avic"; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0x00223000 0x1000>; + }; + + cpus { + #size-cells = <0>; + #address-cells = <1>; + + cpu: cpu@0 { + device_type = "cpu"; + compatible = "arm,arm920t"; + operating-points = <200000 1900000>; + clock-latency = <62500>; + clocks = <&clks IMX1_CLK_MCU>; + voltage-tolerance = <5>; + }; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + interrupt-parent = <&aitc>; + ranges; + + aipi@00200000 { + compatible = "fsl,aipi-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x00200000 0x10000>; + ranges; + + gpt1: timer@00202000 { + compatible = "fsl,imx1-gpt"; + reg = <0x00202000 0x1000>; + interrupts = <59>; + clocks = <&clks IMX1_CLK_HCLK>, + <&clks IMX1_CLK_PER1>; + clock-names = "ipg", "per"; + }; + + gpt2: timer@00203000 { + compatible = "fsl,imx1-gpt"; + reg = <0x00203000 0x1000>; + interrupts = <58>; + clocks = <&clks IMX1_CLK_HCLK>, + <&clks IMX1_CLK_PER1>; + clock-names = "ipg", "per"; + }; + + fb: fb@00205000 { + compatible = "fsl,imx1-fb"; + reg = <0x00205000 0x1000>; + interrupts = <14>; + clocks = <&clks IMX1_CLK_DUMMY>, + <&clks IMX1_CLK_DUMMY>, + <&clks IMX1_CLK_PER2>; + clock-names = "ipg", "ahb", "per"; + status = "disabled"; + }; + + uart1: serial@00206000 { + compatible = "fsl,imx1-uart"; + reg = <0x00206000 0x1000>; + interrupts = <30 29 26>; + clocks = <&clks IMX1_CLK_HCLK>, + <&clks IMX1_CLK_PER1>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + uart2: serial@00207000 { + compatible = "fsl,imx1-uart"; + reg = <0x00207000 0x1000>; + interrupts = <24 23 20>; + clocks = <&clks IMX1_CLK_HCLK>, + <&clks IMX1_CLK_PER1>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + pwm: pwm@00208000 { + #pwm-cells = <2>; + compatible = "fsl,imx1-pwm"; + reg = <0x00208000 0x1000>; + interrupts = <34>; + clocks = <&clks IMX1_CLK_DUMMY>, + <&clks IMX1_CLK_PER1>; + clock-names = "ipg", "per"; + }; + + dma: dma@00209000 { + compatible = "fsl,imx1-dma"; + reg = <0x00209000 0x1000>; + interrupts = <61 60>; + clocks = <&clks IMX1_CLK_HCLK>, + <&clks IMX1_CLK_DMA_GATE>; + clock-names = "ipg", "ahb"; + #dma-cells = <1>; + }; + + uart3: serial@0020a000 { + compatible = "fsl,imx1-uart"; + reg = <0x0020a000 0x1000>; + interrupts = <54 4 1>; + clocks = <&clks IMX1_CLK_UART3_GATE>, + <&clks IMX1_CLK_PER1>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + }; + + aipi@00210000 { + compatible = "fsl,aipi-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x00210000 0x10000>; + ranges; + + cspi1: cspi@00213000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx1-cspi"; + reg = <0x00213000 0x1000>; + interrupts = <41>; + clocks = <&clks IMX1_CLK_DUMMY>, + <&clks IMX1_CLK_PER1>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + i2c: i2c@00217000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx1-i2c"; + reg = <0x00217000 0x1000>; + interrupts = <39>; + clocks = <&clks IMX1_CLK_HCLK>; + status = "disabled"; + }; + + cspi2: cspi@00219000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx1-cspi"; + reg = <0x00219000 0x1000>; + interrupts = <40>; + clocks = <&clks IMX1_CLK_DUMMY>, + <&clks IMX1_CLK_PER1>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + clks: ccm@0021b000 { + compatible = "fsl,imx1-ccm"; + reg = <0x0021b000 0x1000>; + #clock-cells = <1>; + }; + + iomuxc: iomuxc@0021c000 { + compatible = "fsl,imx1-iomuxc"; + reg = <0x0021c000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + gpio1: gpio@0021c000 { + compatible = "fsl,imx1-gpio"; + reg = <0x0021c000 0x100>; + interrupts = <11>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio@0021c100 { + compatible = "fsl,imx1-gpio"; + reg = <0x0021c100 0x100>; + interrupts = <12>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio@0021c200 { + compatible = "fsl,imx1-gpio"; + reg = <0x0021c200 0x100>; + interrupts = <13>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio4: gpio@0021c300 { + compatible = "fsl,imx1-gpio"; + reg = <0x0021c300 0x100>; + interrupts = <62>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + }; + + weim: weim@00220000 { + #address-cells = <2>; + #size-cells = <1>; + compatible = "fsl,imx1-weim"; + reg = <0x00220000 0x1000>; + clocks = <&clks IMX1_CLK_DUMMY>; + ranges = < + 0 0 0x10000000 0x02000000 + 1 0 0x12000000 0x01000000 + 2 0 0x13000000 0x01000000 + 3 0 0x14000000 0x01000000 + 4 0 0x15000000 0x01000000 + 5 0 0x16000000 0x01000000 + >; + status = "disabled"; + }; + + esram: esram@00300000 { + compatible = "mmio-sram"; + reg = <0x00300000 0x20000>; + }; + }; +}; -- cgit v0.10.2 From 2998b332b8a8e727637f3a5811ed46a31124380c Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Tue, 5 Aug 2014 17:34:52 +0800 Subject: ARM: dts: add thermal sensor support for i.mx6sl Add thermal sensor support for i.MX6SL. Signed-off-by: Anson Huang Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi index c75800c..505da9e 100644 --- a/arch/arm/boot/dts/imx6sl.dtsi +++ b/arch/arm/boot/dts/imx6sl.dtsi @@ -529,6 +529,14 @@ }; }; + tempmon: tempmon { + compatible = "fsl,imx6q-tempmon"; + interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>; + fsl,tempmon = <&anatop>; + fsl,tempmon-data = <&ocotp>; + clocks = <&clks IMX6SL_CLK_PLL3_USB_OTG>; + }; + usbphy1: usbphy@020c9000 { compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy"; reg = <0x020c9000 0x1000>; @@ -784,7 +792,7 @@ }; ocotp: ocotp@021bc000 { - compatible = "fsl,imx6sl-ocotp"; + compatible = "fsl,imx6sl-ocotp", "syscon"; reg = <0x021bc000 0x4000>; }; -- cgit v0.10.2 From d8c99930f1402931809f6da2dfd42d56c620e0d7 Mon Sep 17 00:00:00 2001 From: Bill Pringlemeir Date: Tue, 5 Aug 2014 13:34:01 -0400 Subject: ARM: dts: vf610-twr: Add ttyLP2 device. The ttyLP1 is already the default console/serial port. The tower board will route ttyLP2 to the same connectors depending on the JP23/24 settings. See: http://lists.infradead.org/pipermail/linux-arm-kernel/2014-July/276457.html http://lists.infradead.org/pipermail/linux-arm-kernel/2014-July/275576.html Signed-off-by: Bill Pringlemeir Acked-by: Stefan Agner Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/vf610-twr.dts b/arch/arm/boot/dts/vf610-twr.dts index e4bffba..82d16ac 100644 --- a/arch/arm/boot/dts/vf610-twr.dts +++ b/arch/arm/boot/dts/vf610-twr.dts @@ -220,8 +220,6 @@ VF610_PAD_PTB1__FTM0_CH1 0x1582 VF610_PAD_PTB2__FTM0_CH2 0x1582 VF610_PAD_PTB3__FTM0_CH3 0x1582 - VF610_PAD_PTB6__FTM0_CH6 0x1582 - VF610_PAD_PTB7__FTM0_CH7 0x1582 >; }; @@ -243,6 +241,13 @@ VF610_PAD_PTB5__UART1_RX 0x21a1 >; }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + VF610_PAD_PTB6__UART2_TX 0x21a2 + VF610_PAD_PTB7__UART2_RX 0x21a1 + >; + }; }; }; @@ -264,3 +269,9 @@ pinctrl-0 = <&pinctrl_uart1>; status = "okay"; }; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; -- cgit v0.10.2 From 0f4290579fe55fd471fb6aa39fd37a44538f7a97 Mon Sep 17 00:00:00 2001 From: Markus Pargmann Date: Thu, 7 Aug 2014 21:52:38 +0200 Subject: ARM: dts: imx25: remove imx35-sdma compatible The preloaded script addresses on imx25 and imx35 are different, so imx25 is not compatible with imx35-sdma unless a custom firmware is loaded. Signed-off-by: Markus Pargmann Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/imx25.dtsi b/arch/arm/boot/dts/imx25.dtsi index c174039..4d40e55 100644 --- a/arch/arm/boot/dts/imx25.dtsi +++ b/arch/arm/boot/dts/imx25.dtsi @@ -453,7 +453,7 @@ }; sdma: sdma@53fd4000 { - compatible = "fsl,imx25-sdma", "fsl,imx35-sdma"; + compatible = "fsl,imx25-sdma"; reg = <0x53fd4000 0x4000>; clocks = <&clks 112>, <&clks 68>; clock-names = "ipg", "ahb"; -- cgit v0.10.2 From 1a3c460cb9e6f9ff41a7116a485d18120311776f Mon Sep 17 00:00:00 2001 From: Michael Grzeschik Date: Thu, 7 Aug 2014 21:52:40 +0200 Subject: ARM: dts: imx25-pinfunc: Add several pin configurations This patch adds pin configurations for: - csi aud6 - cspi1 uart3 - csi uart5 - cc - csi sdhc2 - csi cspi3 - sd1 cspi2 - cspi1 pwm Signed-off-by: Michael Grzeschik Signed-off-by: Markus Pargmann Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/imx25-pinfunc.h b/arch/arm/boot/dts/imx25-pinfunc.h index 9238a95..88eebb1 100644 --- a/arch/arm/boot/dts/imx25-pinfunc.h +++ b/arch/arm/boot/dts/imx25-pinfunc.h @@ -247,6 +247,7 @@ #define MX25_PAD_OE_ACD__GPIO_1_25 0x114 0x30c 0x000 0x15 0x000 #define MX25_PAD_CONTRAST__CONTRAST 0x118 0x310 0x000 0x10 0x000 +#define MX25_PAD_CONTRAST__CC4 0x118 0x310 0x000 0x11 0x000 #define MX25_PAD_CONTRAST__PWM4_PWMO 0x118 0x310 0x000 0x14 0x000 #define MX25_PAD_CONTRAST__FEC_CRS 0x118 0x310 0x508 0x15 0x001 @@ -260,6 +261,7 @@ #define MX25_PAD_CSI_D2__CSPI3_MOSI 0x120 0x318 0x000 0x17 0x000 #define MX25_PAD_CSI_D3__CSI_D3 0x124 0x31c 0x000 0x10 0x000 +#define MX25_PAD_CSI_D3__UART5_TXD_MUX 0x124 0x31c 0x000 0x11 0x000 #define MX25_PAD_CSI_D3__GPIO_1_28 0x124 0x31c 0x000 0x15 0x000 #define MX25_PAD_CSI_D3__CSPI3_MISO 0x124 0x31c 0x4b4 0x17 0x001 @@ -269,31 +271,46 @@ #define MX25_PAD_CSI_D4__CSPI3_SCLK 0x128 0x320 0x000 0x17 0x000 #define MX25_PAD_CSI_D5__CSI_D5 0x12c 0x324 0x000 0x10 0x000 +#define MX25_PAD_CSI_D5__UART5_CTS 0x12c 0x324 0x000 0x11 0x001 #define MX25_PAD_CSI_D5__GPIO_1_30 0x12c 0x324 0x000 0x15 0x000 #define MX25_PAD_CSI_D5__CSPI3_RDY 0x12c 0x324 0x000 0x17 0x000 #define MX25_PAD_CSI_D6__CSI_D6 0x130 0x328 0x000 0x10 0x000 +#define MX25_PAD_CSI_D6__SDHC2_CMD 0x130 0x328 0x4e0 0x12 0x001 #define MX25_PAD_CSI_D6__GPIO_1_31 0x130 0x328 0x000 0x15 0x000 #define MX25_PAD_CSI_D7__CSI_D7 0x134 0x32c 0x000 0x10 0x000 +#define MX25_PAD_CSI_D7__SDHC2_DAT_CLK 0x134 0x32C 0x4dc 0x12 0x001 #define MX25_PAD_CSI_D7__GPIO_1_6 0x134 0x32c 0x000 0x15 0x000 #define MX25_PAD_CSI_D8__CSI_D8 0x138 0x330 0x000 0x10 0x000 +#define MX25_PAD_CSI_D8__AUD6_RXC 0x138 0x330 0x000 0x12 0x001 #define MX25_PAD_CSI_D8__GPIO_1_7 0x138 0x330 0x000 0x15 0x000 +#define MX25_PAD_CSI_D8__CSPI3_SS2 0x138 0x330 0x4c4 0x17 0x000 #define MX25_PAD_CSI_D9__CSI_D9 0x13c 0x334 0x000 0x10 0x000 +#define MX25_PAD_CSI_D9__AUD6_RXFS 0x13c 0x334 0x000 0x12 0x001 #define MX25_PAD_CSI_D9__GPIO_4_21 0x13c 0x334 0x000 0x15 0x000 +#define MX25_PAD_CSI_D9__CSPI3_SS3 0x13c 0x334 0x4c8 0x17 0x000 #define MX25_PAD_CSI_MCLK__CSI_MCLK 0x140 0x338 0x000 0x10 0x000 +#define MX25_PAD_CSI_MCLK__AUD6_TXD 0x140 0x338 0x000 0x11 0x001 +#define MX25_PAD_CSI_MCLK__SDHC2_DAT0 0x140 0x338 0x4e4 0x12 0x001 #define MX25_PAD_CSI_MCLK__GPIO_1_8 0x140 0x338 0x000 0x15 0x000 #define MX25_PAD_CSI_VSYNC__CSI_VSYNC 0x144 0x33c 0x000 0x10 0x000 +#define MX25_PAD_CSI_VSYNC__AUD6_RXD 0x144 0x33c 0x000 0x11 0x001 +#define MX25_PAD_CSI_VSYNC__SDHC2_DAT1 0x144 0x33c 0x4e8 0x12 0x001 #define MX25_PAD_CSI_VSYNC__GPIO_1_9 0x144 0x33c 0x000 0x15 0x000 #define MX25_PAD_CSI_HSYNC__CSI_HSYNC 0x148 0x340 0x000 0x10 0x000 +#define MX25_PAD_CSI_HSYNC__AUD6_TXC 0x148 0x340 0x000 0x11 0x001 +#define MX25_PAD_CSI_HSYNC__SDHC2_DAT2 0x148 0x340 0x4ec 0x12 0x001 #define MX25_PAD_CSI_HSYNC__GPIO_1_10 0x148 0x340 0x000 0x15 0x000 #define MX25_PAD_CSI_PIXCLK__CSI_PIXCLK 0x14c 0x344 0x000 0x10 0x000 +#define MX25_PAD_CSI_PIXCLK__AUD6_TXFS 0x14c 0x344 0x000 0x11 0x001 +#define MX25_PAD_CSI_PIXCLK__SDHC2_DAT3 0x14c 0x344 0x4f0 0x12 0x001 #define MX25_PAD_CSI_PIXCLK__GPIO_1_11 0x14c 0x344 0x000 0x15 0x000 #define MX25_PAD_I2C1_CLK__I2C1_CLK 0x150 0x348 0x000 0x10 0x000 @@ -303,18 +320,24 @@ #define MX25_PAD_I2C1_DAT__GPIO_1_13 0x154 0x34c 0x000 0x15 0x000 #define MX25_PAD_CSPI1_MOSI__CSPI1_MOSI 0x158 0x350 0x000 0x10 0x000 +#define MX25_PAD_CSPI1_MOSI__UART3_RXD 0x158 0x350 0x000 0x12 0x000 #define MX25_PAD_CSPI1_MOSI__GPIO_1_14 0x158 0x350 0x000 0x15 0x000 #define MX25_PAD_CSPI1_MISO__CSPI1_MISO 0x15c 0x354 0x000 0x10 0x000 +#define MX25_PAD_CSPI1_MISO__UART3_TXD 0x15c 0x354 0x000 0x12 0x000 #define MX25_PAD_CSPI1_MISO__GPIO_1_15 0x15c 0x354 0x000 0x15 0x000 #define MX25_PAD_CSPI1_SS0__CSPI1_SS0 0x160 0x358 0x000 0x10 0x000 +#define MX25_PAD_CSPI1_SS0__PWM2_PWMO 0x160 0x358 0x000 0x12 0x000 #define MX25_PAD_CSPI1_SS0__GPIO_1_16 0x160 0x358 0x000 0x15 0x000 #define MX25_PAD_CSPI1_SS1__CSPI1_SS1 0x164 0x35c 0x000 0x10 0x000 +#define MX25_PAD_CSPI1_SS1__I2C3_DAT 0x164 0x35C 0x528 0x11 0x001 +#define MX25_PAD_CSPI1_SS1__UART3_RTS 0x164 0x35c 0x000 0x12 0x000 #define MX25_PAD_CSPI1_SS1__GPIO_1_17 0x164 0x35c 0x000 0x15 0x000 #define MX25_PAD_CSPI1_SCLK__CSPI1_SCLK 0x168 0x360 0x000 0x10 0x000 +#define MX25_PAD_CSPI1_SCLK__UART3_CTS 0x168 0x360 0x000 0x12 0x000 #define MX25_PAD_CSPI1_SCLK__GPIO_1_18 0x168 0x360 0x000 0x15 0x000 #define MX25_PAD_CSPI1_RDY__CSPI1_RDY 0x16c 0x364 0x000 0x10 0x000 @@ -328,6 +351,7 @@ #define MX25_PAD_UART1_RTS__UART1_RTS 0x178 0x370 0x000 0x10 0x000 #define MX25_PAD_UART1_RTS__CSI_D0 0x178 0x370 0x488 0x11 0x001 +#define MX25_PAD_UART1_RTS__CC3 0x178 0x370 0x000 0x12 0x000 #define MX25_PAD_UART1_RTS__GPIO_4_24 0x178 0x370 0x000 0x15 0x000 #define MX25_PAD_UART1_CTS__UART1_CTS 0x17c 0x374 0x000 0x10 0x000 @@ -342,6 +366,7 @@ #define MX25_PAD_UART2_RTS__UART2_RTS 0x188 0x380 0x000 0x10 0x000 #define MX25_PAD_UART2_RTS__FEC_COL 0x188 0x380 0x504 0x12 0x002 +#define MX25_PAD_UART2_RTS__CC1 0x188 0x380 0x000 0x13 0x000 #define MX25_PAD_UART2_RTS__GPIO_4_28 0x188 0x380 0x000 0x15 0x000 #define MX25_PAD_UART2_CTS__FEC_RX_ER 0x18c 0x384 0x518 0x12 0x002 @@ -349,14 +374,17 @@ #define MX25_PAD_UART2_CTS__GPIO_4_29 0x18c 0x384 0x000 0x15 0x000 #define MX25_PAD_SD1_CMD__SD1_CMD 0x190 0x388 0x000 0x10 0x000 +#define MX25_PAD_SD1_CMD__CSPI2_MOSI 0x190 0x388 0x4a0 0x11 0x001 #define MX25_PAD_SD1_CMD__FEC_RDATA2 0x190 0x388 0x50c 0x12 0x002 #define MX25_PAD_SD1_CMD__GPIO_2_23 0x190 0x388 0x000 0x15 0x000 #define MX25_PAD_SD1_CLK__SD1_CLK 0x194 0x38c 0x000 0x10 0x000 +#define MX25_PAD_SD1_CLK__CSPI2_MISO 0x194 0x38c 0x49c 0x11 0x001 #define MX25_PAD_SD1_CLK__FEC_RDATA3 0x194 0x38c 0x510 0x12 0x002 #define MX25_PAD_SD1_CLK__GPIO_2_24 0x194 0x38c 0x000 0x15 0x000 #define MX25_PAD_SD1_DATA0__SD1_DATA0 0x198 0x390 0x000 0x10 0x000 +#define MX25_PAD_SD1_DATA0__CSPI2_SCLK 0x198 0x390 0x494 0x11 0x001 #define MX25_PAD_SD1_DATA0__GPIO_2_25 0x198 0x390 0x000 0x15 0x000 #define MX25_PAD_SD1_DATA1__SD1_DATA1 0x19c 0x394 0x000 0x10 0x000 @@ -457,14 +485,15 @@ #define MX25_PAD_GPIO_C__CAN2_TX 0x1fc 0x3f8 0x000 0x16 0x000 #define MX25_PAD_GPIO_D__GPIO_D 0x200 0x3fc 0x000 0x10 0x000 -#define MX25_PAD_GPIO_E__LD16 0x204 0x400 0x000 0x02 0x000 #define MX25_PAD_GPIO_D__CAN2_RX 0x200 0x3fc 0x484 0x16 0x001 #define MX25_PAD_GPIO_E__GPIO_E 0x204 0x400 0x000 0x10 0x000 -#define MX25_PAD_GPIO_F__LD17 0x208 0x404 0x000 0x02 0x000 +#define MX25_PAD_GPIO_E__I2C3_CLK 0x204 0x400 0x524 0x11 0x002 +#define MX25_PAD_GPIO_E__LD16 0x204 0x400 0x000 0x12 0x000 #define MX25_PAD_GPIO_E__AUD7_TXD 0x204 0x400 0x000 0x14 0x000 #define MX25_PAD_GPIO_F__GPIO_F 0x208 0x404 0x000 0x10 0x000 +#define MX25_PAD_GPIO_F__LD17 0x208 0x404 0x000 0x12 0x000 #define MX25_PAD_GPIO_F__AUD7_TXC 0x208 0x404 0x000 0x14 0x000 #define MX25_PAD_EXT_ARMCLK__EXT_ARMCLK 0x20c 0x000 0x000 0x10 0x000 -- cgit v0.10.2 From 77d6386b3b2848b06a60a549a765651d0690d193 Mon Sep 17 00:00:00 2001 From: Marc Kleine-Budde Date: Fri, 8 Aug 2014 11:24:21 +0200 Subject: ARM: dts: imx28: add pinmuxing for mmc1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Marc Kleine-Budde [ukl: rebase from ancient kernel version] Signed-off-by: Uwe Kleine-König Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi index a95cc53..defb98a 100644 --- a/arch/arm/boot/dts/imx28.dtsi +++ b/arch/arm/boot/dts/imx28.dtsi @@ -489,6 +489,38 @@ fsl,pull-up = ; }; + mmc1_4bit_pins_a: mmc1-4bit@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_GPMI_D00__SSP1_D0 + MX28_PAD_GPMI_D01__SSP1_D1 + MX28_PAD_GPMI_D02__SSP1_D2 + MX28_PAD_GPMI_D03__SSP1_D3 + MX28_PAD_GPMI_RDY1__SSP1_CMD + MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT + MX28_PAD_GPMI_WRN__SSP1_SCK + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + mmc1_cd_cfg: mmc1-cd-cfg { + fsl,pinmux-ids = < + MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT + >; + fsl,pull-up = ; + }; + + mmc1_sck_cfg: mmc1-sck-cfg { + fsl,pinmux-ids = < + MX28_PAD_GPMI_WRN__SSP1_SCK + >; + fsl,drive-strength = ; + fsl,pull-up = ; + }; + + mmc2_4bit_pins_a: mmc2-4bit@0 { reg = <0>; fsl,pinmux-ids = < -- cgit v0.10.2 From 17c63dd0c3f285a78d9becd36bd5db4d7d7e8e7b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Fri, 8 Aug 2014 11:24:22 +0200 Subject: ARM: dts: imx28: add alternative pinmuxing for i2c1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Uwe Kleine-König Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi index defb98a..47f68ac 100644 --- a/arch/arm/boot/dts/imx28.dtsi +++ b/arch/arm/boot/dts/imx28.dtsi @@ -585,6 +585,17 @@ fsl,pull-up = ; }; + i2c1_pins_b: i2c1@1 { + reg = <1>; + fsl,pinmux-ids = < + MX28_PAD_AUART2_CTS__I2C1_SCL + MX28_PAD_AUART2_RTS__I2C1_SDA + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + saif0_pins_a: saif0@0 { reg = <0>; fsl,pinmux-ids = < -- cgit v0.10.2 From e34a68a316e71290d1d46a24ec6d80420c785759 Mon Sep 17 00:00:00 2001 From: Stefan Agner Date: Mon, 18 Aug 2014 22:07:11 +0200 Subject: ARM: dts: vf610: Add USB PHY and controller This adds USB PHY and USB controller nodes. Vybrid SoCs have two independent USB cores which each supports DR (dual role). However, real OTG is not supported since the OTG ID pin is not available. The PHYs are located within the anadig register range, hence we need to change the length of the anadig registers. Signed-off-by: Stefan Agner Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/vf610.dtsi b/arch/arm/boot/dts/vf610.dtsi index 583dd36..dc5cd11 100644 --- a/arch/arm/boot/dts/vf610.dtsi +++ b/arch/arm/boot/dts/vf610.dtsi @@ -27,6 +27,8 @@ gpio2 = &gpio3; gpio3 = &gpio4; gpio4 = &gpio5; + usbphy0 = &usbphy0; + usbphy1 = &usbphy1; }; cpus { @@ -297,9 +299,25 @@ gpio-ranges = <&iomuxc 0 128 7>; }; - anatop@40050000 { - compatible = "fsl,vf610-anatop"; - reg = <0x40050000 0x1000>; + anatop: anatop@40050000 { + compatible = "fsl,vf610-anatop", "syscon"; + reg = <0x40050000 0x400>; + }; + + usbphy0: usbphy@40050800 { + compatible = "fsl,vf610-usbphy"; + reg = <0x40050800 0x400>; + interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks VF610_CLK_USBPHY0>; + fsl,anatop = <&anatop>; + }; + + usbphy1: usbphy@40050c00 { + compatible = "fsl,vf610-usbphy"; + reg = <0x40050c00 0x400>; + interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks VF610_CLK_USBPHY1>; + fsl,anatop = <&anatop>; }; i2c0: i2c@40066000 { @@ -321,6 +339,18 @@ reg = <0x4006b000 0x1000>; #clock-cells = <1>; }; + + usbdev0: usb@40034000 { + compatible = "fsl,vf610-usb", "fsl,imx27-usb"; + reg = <0x40034000 0x800>; + interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks VF610_CLK_USBC0>; + fsl,usbphy = <&usbphy0>; + dr_mode = "peripheral"; + status = "disabled"; + }; + + }; aips1: aips-bus@40080000 { @@ -383,6 +413,16 @@ status = "disabled"; }; + usbh1: usb@400b4000 { + compatible = "fsl,vf610-usb", "fsl,imx27-usb"; + reg = <0x400b4000 0x800>; + interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks VF610_CLK_USBC1>; + fsl,usbphy = <&usbphy1>; + dr_mode = "host"; + status = "disabled"; + }; + ftm: ftm@400b8000 { compatible = "fsl,ftm-timer"; reg = <0x400b8000 0x1000 0x400b9000 0x1000>; -- cgit v0.10.2 From 763dab227874c0550bdc0aed5b1e4ac04ea3971a Mon Sep 17 00:00:00 2001 From: Stefan Agner Date: Mon, 18 Aug 2014 22:07:14 +0200 Subject: ARM: dts: vf610: Add usbmisc for non-core registers Add device tree node for usbmisc which controls the non-core USB registers. This is required to use the property to disable the over- current detection. Signed-off-by: Stefan Agner Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/vf610.dtsi b/arch/arm/boot/dts/vf610.dtsi index dc5cd11..4d2ec32 100644 --- a/arch/arm/boot/dts/vf610.dtsi +++ b/arch/arm/boot/dts/vf610.dtsi @@ -346,11 +346,17 @@ interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks VF610_CLK_USBC0>; fsl,usbphy = <&usbphy0>; + fsl,usbmisc = <&usbmisc0 0>; dr_mode = "peripheral"; status = "disabled"; }; - + usbmisc0: usb@40034800 { + #index-cells = <1>; + compatible = "fsl,vf610-usbmisc"; + reg = <0x40034800 0x200>; + clocks = <&clks VF610_CLK_USBC0>; + }; }; aips1: aips-bus@40080000 { @@ -419,10 +425,18 @@ interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks VF610_CLK_USBC1>; fsl,usbphy = <&usbphy1>; + fsl,usbmisc = <&usbmisc1 0>; dr_mode = "host"; status = "disabled"; }; + usbmisc1: usb@400b4800 { + #index-cells = <1>; + compatible = "fsl,vf610-usbmisc"; + reg = <0x400b4800 0x200>; + clocks = <&clks VF610_CLK_USBC1>; + }; + ftm: ftm@400b8000 { compatible = "fsl,ftm-timer"; reg = <0x400b8000 0x1000 0x400b9000 0x1000>; -- cgit v0.10.2 From 0500953b4970ac1c56a26492024e74480982c088 Mon Sep 17 00:00:00 2001 From: Stefan Agner Date: Mon, 18 Aug 2014 22:07:16 +0200 Subject: ARM: dts: vf610-colibri: Add USB support Add USB support for Colibri VF61 modules. The Colibri standard pinout defines a pin for USB over-current. However, due to lack of pinmux options, the USB hosts over-current protection signal of the Colibri standard could not be connected to the PHY's over-current protection. Hence we need to disable the over-current functionality of the USB controller. Signed-off-by: Stefan Agner Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/vf610-colibri.dtsi b/arch/arm/boot/dts/vf610-colibri.dtsi index e595c29..0cd8343 100644 --- a/arch/arm/boot/dts/vf610-colibri.dtsi +++ b/arch/arm/boot/dts/vf610-colibri.dtsi @@ -59,6 +59,16 @@ pinctrl-0 = <&pinctrl_uart2>; }; +&usbdev0 { + disable-over-current; + status = "okay"; +}; + +&usbh1 { + disable-over-current; + status = "okay"; +}; + &iomuxc { vf610-colibri { pinctrl_esdhc1: esdhc1grp { -- cgit v0.10.2 From 49b2ae0ca02cbc972255ade1c96a6a1c347cbd8c Mon Sep 17 00:00:00 2001 From: Stefan Agner Date: Mon, 18 Aug 2014 22:07:17 +0200 Subject: ARM: dts: vf610-twr: Add USB support Add USB support for Freescale Vybrid tower. The USB hosts over-current protection signal is not connected to the PHY's over- current protection, hence we need to disable it. Signed-off-by: Stefan Agner Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/vf610-twr.dts b/arch/arm/boot/dts/vf610-twr.dts index 82d16ac..189b697 100644 --- a/arch/arm/boot/dts/vf610-twr.dts +++ b/arch/arm/boot/dts/vf610-twr.dts @@ -275,3 +275,13 @@ pinctrl-0 = <&pinctrl_uart2>; status = "okay"; }; + +&usbdev0 { + disable-over-current; + status = "okay"; +}; + +&usbh1 { + disable-over-current; + status = "okay"; +}; -- cgit v0.10.2 From ce253b5622c1e8da28d0be938747692414355681 Mon Sep 17 00:00:00 2001 From: Alexander Shiyan Date: Tue, 19 Aug 2014 10:33:47 +0400 Subject: ARM: i.MX: dts: Add support for the Freescale i.MX1 ADS board This patch adds support for the Freescale (Motorola) i.MX1 ADS board. This change is intended to further remove non-DT support for this board. Signed-off-by: Alexander Shiyan Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index acb6b42..5a70f83 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -161,6 +161,7 @@ dtb-$(CONFIG_ARCH_LPC32XX) += ea3250.dtb phy3250.dtb dtb-$(CONFIG_ARCH_MARCO) += marco-evb.dtb dtb-$(CONFIG_ARCH_MOXART) += moxart-uc7112lx.dtb dtb-$(CONFIG_ARCH_MXC) += \ + imx1-ads.dtb \ imx25-eukrea-mbimxsd25-baseboard.dtb \ imx25-eukrea-mbimxsd25-baseboard-cmo-qvga.dtb \ imx25-eukrea-mbimxsd25-baseboard-dvi-svga.dtb \ diff --git a/arch/arm/boot/dts/imx1-ads.dts b/arch/arm/boot/dts/imx1-ads.dts new file mode 100644 index 0000000..af4eee5 --- /dev/null +++ b/arch/arm/boot/dts/imx1-ads.dts @@ -0,0 +1,152 @@ +/* + * Copyright (C) 2014 Alexander Shiyan + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +#include "imx1.dtsi" + +/ { + model = "Freescale MX1 ADS"; + compatible = "fsl,imx1ads", "fsl,imx1"; + + chosen { + stdout-path = &uart1; + }; + + memory { + reg = <0x08000000 0x04000000>; + }; + + clocks { + #address-cells = <1>; + #size-cells = <0>; + + clk32 { + compatible = "fsl,imx-clk32", "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32000>; + }; + }; +}; + +&cspi1 { + pinctrl-0 = <&pinctrl_cspi1>; + fsl,spi-num-chipselects = <1>; + cs-gpios = <&gpio3 15 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&i2c { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c>; + status = "okay"; + + extgpio0: pcf8575@22 { + compatible = "nxp,pcf8575"; + reg = <0x22>; + gpio-controller; + #gpio-cells = <2>; + }; + + extgpio1: pcf8575@24 { + compatible = "nxp,pcf8575"; + reg = <0x24>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + fsl,uart-has-rtscts; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + fsl,uart-has-rtscts; + status = "okay"; +}; + +&weim { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_weim>; + status = "okay"; + + nor: nor@0,0 { + compatible = "cfi-flash"; + reg = <0 0x00000000 0x02000000>; + bank-width = <4>; + fsl,weim-cs-timing = <0x00003e00 0x00000801>; + #address-cells = <1>; + #size-cells = <1>; + }; +}; + +&iomuxc { + imx1-ads { + pinctrl_cspi1: cspi1grp { + fsl,pins = < + MX1_PAD_SPI1_MISO__SPI1_MISO 0x0 + MX1_PAD_SPI1_MOSI__SPI1_MOSI 0x0 + MX1_PAD_SPI1_RDY__SPI1_RDY 0x0 + MX1_PAD_SPI1_SCLK__SPI1_SCLK 0x0 + MX1_PAD_SPI1_SS__GPIO3_15 0x0 + >; + }; + + pinctrl_i2c: i2cgrp { + fsl,pins = < + MX1_PAD_I2C_SCL__I2C_SCL 0x0 + MX1_PAD_I2C_SDA__I2C_SDA 0x0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX1_PAD_UART1_TXD__UART1_TXD 0x0 + MX1_PAD_UART1_RXD__UART1_RXD 0x0 + MX1_PAD_UART1_CTS__UART1_CTS 0x0 + MX1_PAD_UART1_RTS__UART1_RTS 0x0 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX1_PAD_UART2_TXD__UART2_TXD 0x0 + MX1_PAD_UART2_RXD__UART2_RXD 0x0 + MX1_PAD_UART2_CTS__UART2_CTS 0x0 + MX1_PAD_UART2_RTS__UART2_RTS 0x0 + >; + }; + + pinctrl_weim: weimgrp { + fsl,pins = < + MX1_PAD_A0__A0 0x0 + MX1_PAD_A16__A16 0x0 + MX1_PAD_A17__A17 0x0 + MX1_PAD_A18__A18 0x0 + MX1_PAD_A19__A19 0x0 + MX1_PAD_A20__A20 0x0 + MX1_PAD_A21__A21 0x0 + MX1_PAD_A22__A22 0x0 + MX1_PAD_A23__A23 0x0 + MX1_PAD_A24__A24 0x0 + MX1_PAD_BCLK__BCLK 0x0 + MX1_PAD_CS4__CS4 0x0 + MX1_PAD_DTACK__DTACK 0x0 + MX1_PAD_ECB__ECB 0x0 + MX1_PAD_LBA__LBA 0x0 + >; + }; + }; +}; -- cgit v0.10.2 From 6ff7f51ef9d34a7be945468de8383f29e151ce11 Mon Sep 17 00:00:00 2001 From: Alexander Shiyan Date: Tue, 19 Aug 2014 20:00:09 +0400 Subject: ARM: i.MX: dts: Add simple-card support This patch adds simple-card support to the i.MX SoCs. Signed-off-by: Alexander Shiyan Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/imx25.dtsi b/arch/arm/boot/dts/imx25.dtsi index 4d40e55..58d3c3c 100644 --- a/arch/arm/boot/dts/imx25.dtsi +++ b/arch/arm/boot/dts/imx25.dtsi @@ -239,6 +239,7 @@ }; ssi2: ssi@50014000 { + #sound-dai-cells = <0>; compatible = "fsl,imx25-ssi", "fsl,imx21-ssi"; reg = <0x50014000 0x4000>; interrupts = <11>; @@ -274,6 +275,7 @@ }; ssi1: ssi@50034000 { + #sound-dai-cells = <0>; compatible = "fsl,imx25-ssi", "fsl,imx21-ssi"; reg = <0x50034000 0x4000>; interrupts = <12>; diff --git a/arch/arm/boot/dts/imx35.dtsi b/arch/arm/boot/dts/imx35.dtsi index 442e216..6932928 100644 --- a/arch/arm/boot/dts/imx35.dtsi +++ b/arch/arm/boot/dts/imx35.dtsi @@ -114,6 +114,7 @@ }; ssi1: ssi@43fa0000 { + #sound-dai-cells = <0>; compatible = "fsl,imx35-ssi", "fsl,imx21-ssi"; reg = <0x43fa0000 0x4000>; interrupts = <11>; diff --git a/arch/arm/boot/dts/imx50.dtsi b/arch/arm/boot/dts/imx50.dtsi index c0e0f60..620b0f0 100644 --- a/arch/arm/boot/dts/imx50.dtsi +++ b/arch/arm/boot/dts/imx50.dtsi @@ -145,6 +145,7 @@ }; ssi2: ssi@50014000 { + #sound-dai-cells = <0>; compatible = "fsl,imx50-ssi", "fsl,imx51-ssi", "fsl,imx21-ssi"; @@ -454,6 +455,7 @@ }; ssi1: ssi@63fcc000 { + #sound-dai-cells = <0>; compatible = "fsl,imx50-ssi", "fsl,imx51-ssi", "fsl,imx21-ssi"; reg = <0x63fcc000 0x4000>; diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi index 17c05a6..92660e1 100644 --- a/arch/arm/boot/dts/imx51.dtsi +++ b/arch/arm/boot/dts/imx51.dtsi @@ -210,6 +210,7 @@ }; ssi2: ssi@70014000 { + #sound-dai-cells = <0>; compatible = "fsl,imx51-ssi", "fsl,imx21-ssi"; reg = <0x70014000 0x4000>; interrupts = <30>; @@ -499,6 +500,7 @@ }; ssi1: ssi@83fcc000 { + #sound-dai-cells = <0>; compatible = "fsl,imx51-ssi", "fsl,imx21-ssi"; reg = <0x83fcc000 0x4000>; interrupts = <29>; @@ -554,6 +556,7 @@ }; ssi3: ssi@83fe8000 { + #sound-dai-cells = <0>; compatible = "fsl,imx51-ssi", "fsl,imx21-ssi"; reg = <0x83fe8000 0x4000>; interrupts = <96>; diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi index c6c58c1..c670d5f 100644 --- a/arch/arm/boot/dts/imx53.dtsi +++ b/arch/arm/boot/dts/imx53.dtsi @@ -221,6 +221,7 @@ }; ssi2: ssi@50014000 { + #sound-dai-cells = <0>; compatible = "fsl,imx53-ssi", "fsl,imx51-ssi", "fsl,imx21-ssi"; @@ -661,6 +662,7 @@ }; ssi1: ssi@63fcc000 { + #sound-dai-cells = <0>; compatible = "fsl,imx53-ssi", "fsl,imx51-ssi", "fsl,imx21-ssi"; reg = <0x63fcc000 0x4000>; @@ -688,6 +690,7 @@ }; ssi3: ssi@63fe8000 { + #sound-dai-cells = <0>; compatible = "fsl,imx53-ssi", "fsl,imx51-ssi", "fsl,imx21-ssi"; reg = <0x63fe8000 0x4000>; diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi index c701af9..6692115 100644 --- a/arch/arm/boot/dts/imx6qdl.dtsi +++ b/arch/arm/boot/dts/imx6qdl.dtsi @@ -273,6 +273,7 @@ }; ssi1: ssi@02028000 { + #sound-dai-cells = <0>; compatible = "fsl,imx6q-ssi", "fsl,imx51-ssi"; reg = <0x02028000 0x4000>; @@ -286,6 +287,7 @@ }; ssi2: ssi@0202c000 { + #sound-dai-cells = <0>; compatible = "fsl,imx6q-ssi", "fsl,imx51-ssi"; reg = <0x0202c000 0x4000>; @@ -299,6 +301,7 @@ }; ssi3: ssi@02030000 { + #sound-dai-cells = <0>; compatible = "fsl,imx6q-ssi", "fsl,imx51-ssi"; reg = <0x02030000 0x4000>; diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi index 505da9e..4c400fc 100644 --- a/arch/arm/boot/dts/imx6sl.dtsi +++ b/arch/arm/boot/dts/imx6sl.dtsi @@ -226,6 +226,7 @@ }; ssi1: ssi@02028000 { + #sound-dai-cells = <0>; compatible = "fsl,imx6sl-ssi", "fsl,imx51-ssi"; reg = <0x02028000 0x4000>; @@ -239,6 +240,7 @@ }; ssi2: ssi@0202c000 { + #sound-dai-cells = <0>; compatible = "fsl,imx6sl-ssi", "fsl,imx51-ssi"; reg = <0x0202c000 0x4000>; @@ -252,6 +254,7 @@ }; ssi3: ssi@02030000 { + #sound-dai-cells = <0>; compatible = "fsl,imx6sl-ssi", "fsl,imx51-ssi"; reg = <0x02030000 0x4000>; diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi index f4b9da6..63d9d82 100644 --- a/arch/arm/boot/dts/imx6sx.dtsi +++ b/arch/arm/boot/dts/imx6sx.dtsi @@ -298,6 +298,7 @@ }; ssi1: ssi@02028000 { + #sound-dai-cells = <0>; compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi"; reg = <0x02028000 0x4000>; interrupts = ; @@ -311,6 +312,7 @@ }; ssi2: ssi@0202c000 { + #sound-dai-cells = <0>; compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi"; reg = <0x0202c000 0x4000>; interrupts = ; @@ -324,6 +326,7 @@ }; ssi3: ssi@02030000 { + #sound-dai-cells = <0>; compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi"; reg = <0x02030000 0x4000>; interrupts = ; -- cgit v0.10.2 From 4e394cd999fe99cbebd0c8ca753d000d6db66f59 Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Fri, 22 Aug 2014 14:52:54 -0700 Subject: ARM: dts: Gateworks GW5520 support (i.MX6) Add support for the Gateworks GW5520 board. Signed-off-by: Tim Harvey Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 5a70f83..60a6214 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -200,6 +200,7 @@ dtb-$(CONFIG_ARCH_MXC) += \ imx6dl-gw52xx.dtb \ imx6dl-gw53xx.dtb \ imx6dl-gw54xx.dtb \ + imx6dl-gw552x.dtb \ imx6dl-hummingboard.dtb \ imx6dl-nitrogen6x.dtb \ imx6dl-phytec-pbab01.dtb \ @@ -224,6 +225,7 @@ dtb-$(CONFIG_ARCH_MXC) += \ imx6q-gw53xx.dtb \ imx6q-gw5400-a.dtb \ imx6q-gw54xx.dtb \ + imx6q-gw552x.dtb \ imx6q-nitrogen6x.dtb \ imx6q-phytec-pbab01.dtb \ imx6q-rex-pro.dtb \ diff --git a/arch/arm/boot/dts/imx6dl-gw552x.dts b/arch/arm/boot/dts/imx6dl-gw552x.dts new file mode 100644 index 0000000..a4b700c --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-gw552x.dts @@ -0,0 +1,20 @@ +/* + * Copyright 2014 Gateworks Corporation + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; + +#include "imx6dl.dtsi" +#include "imx6qdl-gw552x.dtsi" + +/ { + model = "Gateworks Ventana i.MX6 DualLite/Solo GW552X"; + compatible = "gw,imx6dl-gw552x", "gw,ventana", "fsl,imx6dl"; +}; diff --git a/arch/arm/boot/dts/imx6q-gw552x.dts b/arch/arm/boot/dts/imx6q-gw552x.dts new file mode 100644 index 0000000..f87a8fa --- /dev/null +++ b/arch/arm/boot/dts/imx6q-gw552x.dts @@ -0,0 +1,24 @@ +/* + * Copyright 2014 Gateworks Corporation + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; + +#include "imx6q.dtsi" +#include "imx6qdl-gw552x.dtsi" + +/ { + model = "Gateworks Ventana i.MX6 Dual/Quad GW552X"; + compatible = "gw,imx6q-gw552x", "gw,ventana", "fsl,imx6q"; +}; + +&sata { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6qdl-gw552x.dtsi b/arch/arm/boot/dts/imx6qdl-gw552x.dtsi new file mode 100644 index 0000000..5c6587f --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-gw552x.dtsi @@ -0,0 +1,267 @@ +/* + * Copyright 2014 Gateworks Corporation + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include + +/ { + /* these are used by bootloader for disabling nodes */ + aliases { + led0 = &led0; + led1 = &led1; + led2 = &led2; + nand = &gpmi; + usb0 = &usbh1; + usb1 = &usbotg; + }; + + chosen { + bootargs = "console=ttymxc1,115200"; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + led0: user1 { + label = "user1"; + gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */ + default-state = "on"; + linux,default-trigger = "heartbeat"; + }; + + led1: user2 { + label = "user2"; + gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */ + default-state = "off"; + }; + + led2: user3 { + label = "user3"; + gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */ + default-state = "off"; + }; + }; + + memory { + reg = <0x10000000 0x20000000>; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_1p0v: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "1P0V"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + reg_3p3v: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_5p0v: regulator@3 { + compatible = "regulator-fixed"; + reg = <3>; + regulator-name = "5P0V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + }; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand>; + status = "okay"; +}; + +&hdmi { + ddc-i2c-bus = <&i2c3>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + eeprom1: eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + pagesize = <16>; + }; + + eeprom2: eeprom@51 { + compatible = "atmel,24c02"; + reg = <0x51>; + pagesize = <16>; + }; + + eeprom3: eeprom@52 { + compatible = "atmel,24c02"; + reg = <0x52>; + pagesize = <16>; + }; + + eeprom4: eeprom@53 { + compatible = "atmel,24c02"; + reg = <0x53>; + pagesize = <16>; + }; + + gpio: pca9555@23 { + compatible = "nxp,pca9555"; + reg = <0x23>; + gpio-controller; + #gpio-cells = <2>; + }; + + rtc: ds1672@68 { + compatible = "dallas,ds1672"; + reg = <0x68>; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + status = "okay"; }; + +&usbh1 { + status = "okay"; +}; + +&iomuxc { + imx6qdl-gw552x { + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 + MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 + >; + }; + + pinctrl_gpmi_nand: gpminandgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 + MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 + MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 + MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 + MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 + MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 + MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 + MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 + MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 + MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 + MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 + MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 + MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 + MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 + MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 + MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_pcie: pciegrp { + fsl,pins = < + MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 + >; + }; + }; +}; -- cgit v0.10.2 From 1bb9dae59f673fa0adcc4cd1c9e5e822e1382bc2 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 19 Aug 2014 15:21:13 -0300 Subject: ARM: dts: imx6sl-evk.dts: Keep pinctrl nodes sorted Let's keep pinctrl nodes sorted. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/imx6sl-evk.dts b/arch/arm/boot/dts/imx6sl-evk.dts index 3f9e041..366eb02 100644 --- a/arch/arm/boot/dts/imx6sl-evk.dts +++ b/arch/arm/boot/dts/imx6sl-evk.dts @@ -329,12 +329,6 @@ >; }; - pinctrl_led: ledgrp { - fsl,pins = < - MX6SL_PAD_HSIC_STROBE__GPIO3_IO20 0x17059 - >; - }; - pinctrl_kpp: kppgrp { fsl,pins = < MX6SL_PAD_KEY_ROW0__KEY_ROW0 0x1b010 @@ -346,6 +340,12 @@ >; }; + pinctrl_led: ledgrp { + fsl,pins = < + MX6SL_PAD_HSIC_STROBE__GPIO3_IO20 0x17059 + >; + }; + pinctrl_uart1: uart1grp { fsl,pins = < MX6SL_PAD_UART1_RXD__UART1_RX_DATA 0x1b0b1 -- cgit v0.10.2 From e99b077bb340e37642b3eefda0de224ce1c8ee28 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 19 Aug 2014 15:21:14 -0300 Subject: ARM: dts: imx6sl-evk: Add LCD support Add support for the "MX28LCD Seiko 4.3' WVGA" panel. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/imx6sl-evk.dts b/arch/arm/boot/dts/imx6sl-evk.dts index 366eb02..9925c4a 100644 --- a/arch/arm/boot/dts/imx6sl-evk.dts +++ b/arch/arm/boot/dts/imx6sl-evk.dts @@ -20,6 +20,13 @@ reg = <0x80000000 0x40000000>; }; + backlight { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + }; + leds { compatible = "gpio-leds"; pinctrl-names = "default"; @@ -74,6 +81,14 @@ regulator-max-microvolt = <4325000>; regulator-boot-on; }; + + reg_lcd_3v3: regulator@4 { + compatible = "regulator-fixed"; + reg = <4>; + regulator-name = "lcd-3v3"; + gpio = <&gpio4 3 0>; + enable-active-high; + }; }; sound { @@ -340,12 +355,51 @@ >; }; + pinctrl_lcd: lcdgrp { + fsl,pins = < + MX6SL_PAD_LCD_DAT0__LCD_DATA00 0x1b0b0 + MX6SL_PAD_LCD_DAT1__LCD_DATA01 0x1b0b0 + MX6SL_PAD_LCD_DAT2__LCD_DATA02 0x1b0b0 + MX6SL_PAD_LCD_DAT3__LCD_DATA03 0x1b0b0 + MX6SL_PAD_LCD_DAT4__LCD_DATA04 0x1b0b0 + MX6SL_PAD_LCD_DAT5__LCD_DATA05 0x1b0b0 + MX6SL_PAD_LCD_DAT6__LCD_DATA06 0x1b0b0 + MX6SL_PAD_LCD_DAT7__LCD_DATA07 0x1b0b0 + MX6SL_PAD_LCD_DAT8__LCD_DATA08 0x1b0b0 + MX6SL_PAD_LCD_DAT9__LCD_DATA09 0x1b0b0 + MX6SL_PAD_LCD_DAT10__LCD_DATA10 0x1b0b0 + MX6SL_PAD_LCD_DAT11__LCD_DATA11 0x1b0b0 + MX6SL_PAD_LCD_DAT12__LCD_DATA12 0x1b0b0 + MX6SL_PAD_LCD_DAT13__LCD_DATA13 0x1b0b0 + MX6SL_PAD_LCD_DAT14__LCD_DATA14 0x1b0b0 + MX6SL_PAD_LCD_DAT15__LCD_DATA15 0x1b0b0 + MX6SL_PAD_LCD_DAT16__LCD_DATA16 0x1b0b0 + MX6SL_PAD_LCD_DAT17__LCD_DATA17 0x1b0b0 + MX6SL_PAD_LCD_DAT18__LCD_DATA18 0x1b0b0 + MX6SL_PAD_LCD_DAT19__LCD_DATA19 0x1b0b0 + MX6SL_PAD_LCD_DAT20__LCD_DATA20 0x1b0b0 + MX6SL_PAD_LCD_DAT21__LCD_DATA21 0x1b0b0 + MX6SL_PAD_LCD_DAT22__LCD_DATA22 0x1b0b0 + MX6SL_PAD_LCD_DAT23__LCD_DATA23 0x1b0b0 + MX6SL_PAD_LCD_CLK__LCD_CLK 0x1b0b0 + MX6SL_PAD_LCD_ENABLE__LCD_ENABLE 0x1b0b0 + MX6SL_PAD_LCD_HSYNC__LCD_HSYNC 0x1b0b0 + MX6SL_PAD_LCD_VSYNC__LCD_VSYNC 0x1b0b0 + >; + }; + pinctrl_led: ledgrp { fsl,pins = < MX6SL_PAD_HSIC_STROBE__GPIO3_IO20 0x17059 >; }; + pinctrl_pwm1: pwmgrp { + fsl,pins = < + MX6SL_PAD_PWM1__PWM1_OUT 0x110b0 + >; + }; + pinctrl_uart1: uart1grp { fsl,pins = < MX6SL_PAD_UART1_RXD__UART1_RX_DATA 0x1b0b1 @@ -488,6 +542,44 @@ status = "okay"; }; +&lcdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd>; + lcd-supply = <®_lcd_3v3>; + display = <&display>; + status = "okay"; + + display: display { + bits-per-pixel = <32>; + bus-width = <24>; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <33500000>; + hactive = <800>; + vactive = <480>; + hback-porch = <89>; + hfront-porch = <164>; + vback-porch = <23>; + vfront-porch = <10>; + hsync-len = <10>; + vsync-len = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + }; + }; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + &ssi2 { status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi index 4c400fc..ba67714 100644 --- a/arch/arm/boot/dts/imx6sl.dtsi +++ b/arch/arm/boot/dts/imx6sl.dtsi @@ -638,8 +638,14 @@ }; lcdif: lcdif@020f8000 { + compatible = "fsl,imx6sl-lcdif", "fsl,imx28-lcdif"; reg = <0x020f8000 0x4000>; interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6SL_CLK_LCDIF_PIX>, + <&clks IMX6SL_CLK_LCDIF_AXI>, + <&clks IMX6SL_CLK_DUMMY>; + clock-names = "pix", "axi", "disp_axi"; + status = "disabled"; }; dcp: dcp@020fc000 { -- cgit v0.10.2 From 7881fb3f2272eb6f24270e1e228362242696d013 Mon Sep 17 00:00:00 2001 From: Philipp Zabel Date: Fri, 22 Aug 2014 11:13:02 +0200 Subject: ARM: dts: nitrogen6x: Add Intersil ISL1208 RTC This patch adds the battery backed real time clock connected to I2C1 to the device tree. Signed-off-by: Philipp Zabel Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi b/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi index 2c67048..0821812 100644 --- a/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi +++ b/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi @@ -192,6 +192,11 @@ VDDA-supply = <®_2p5v>; VDDIO-supply = <®_3p3v>; }; + + rtc: rtc@6f { + compatible = "isil,isl1208"; + reg = <0x6f>; + }; }; &i2c2 { -- cgit v0.10.2 From 49bdf58e9b0479f854232407b1e298efe2b27e5c Mon Sep 17 00:00:00 2001 From: Steffen Trumtrar Date: Fri, 22 Aug 2014 14:02:27 +0200 Subject: ARM: dts: i.MX53: add pmu node The i.MX53 has a Cortex-A8 Performance Monitor Unit. Add it to the dtsi. Signed-off-by: Steffen Trumtrar Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi index c670d5f..6b198c6d 100644 --- a/arch/arm/boot/dts/imx53.dtsi +++ b/arch/arm/boot/dts/imx53.dtsi @@ -747,5 +747,10 @@ reg = <0xf8000000 0x20000>; clocks = <&clks IMX5_CLK_OCRAM>; }; + + pmu { + compatible = "arm,cortex-a8-pmu"; + interrupts = <77>; + }; }; }; -- cgit v0.10.2 From 4cd4f509c5dc3f935911c49f9813e2fc29063a6b Mon Sep 17 00:00:00 2001 From: Rabeeh Khoury Date: Sat, 23 Aug 2014 10:11:36 +0100 Subject: ARM: dts: hummingboard: Split HummingBoard DT to support s/dl and d/q Signed-off-by: Rabeeh Khoury Signed-off-by: Russell King Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 60a6214..b022972 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -226,6 +226,7 @@ dtb-$(CONFIG_ARCH_MXC) += \ imx6q-gw5400-a.dtb \ imx6q-gw54xx.dtb \ imx6q-gw552x.dtb \ + imx6q-hummingboard.dtb \ imx6q-nitrogen6x.dtb \ imx6q-phytec-pbab01.dtb \ imx6q-rex-pro.dtb \ diff --git a/arch/arm/boot/dts/imx6dl-hummingboard.dts b/arch/arm/boot/dts/imx6dl-hummingboard.dts index 7159854..44a0e67 100644 --- a/arch/arm/boot/dts/imx6dl-hummingboard.dts +++ b/arch/arm/boot/dts/imx6dl-hummingboard.dts @@ -1,206 +1,13 @@ /* - * Copyright (C) 2013,2014 Russell King + * Copyright (C) 2014 Rabeeh Khoury (rabeeh@solid-run.com) + * Based on dt work by Russell King */ /dts-v1/; #include "imx6dl.dtsi" -#include "imx6qdl-microsom.dtsi" -#include "imx6qdl-microsom-ar8035.dtsi" +#include "imx6qdl-hummingboard.dtsi" / { - model = "SolidRun HummingBoard DL/Solo"; - compatible = "solidrun,hummingboard", "fsl,imx6dl"; - - chosen { - stdout-path = &uart1; - }; - - ir_recv: ir-receiver { - compatible = "gpio-ir-receiver"; - gpios = <&gpio1 2 1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hummingboard_gpio1_2>; - }; - - regulators { - compatible = "simple-bus"; - - reg_3p3v: 3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_usbh1_vbus: usb-h1-vbus { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio1 0 0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hummingboard_usbh1_vbus>; - regulator-name = "usb_h1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - reg_usbotg_vbus: usb-otg-vbus { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio3 22 0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hummingboard_usbotg_vbus>; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - }; - - sound-spdif { - compatible = "fsl,imx-audio-spdif"; - model = "On-board SPDIF"; - /* IMX6 doesn't implement this yet */ - spdif-controller = <&spdif>; - spdif-out; - }; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hummingboard_flexcan1>; - status = "okay"; -}; - -&hdmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hummingboard_hdmi>; - ddc-i2c-bus = <&i2c2>; - status = "okay"; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hummingboard_i2c1>; - - /* - * Not fitted on Carrier-1 board... yet - status = "okay"; - - rtc: pcf8523@68 { - compatible = "nxp,pcf8523"; - reg = <0x68>; - }; - */ -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hummingboard_i2c2>; - status = "okay"; -}; - -&iomuxc { - hummingboard { - pinctrl_hummingboard_flexcan1: hummingboard-flexcan1 { - fsl,pins = < - MX6QDL_PAD_SD3_CLK__FLEXCAN1_RX 0x80000000 - MX6QDL_PAD_SD3_CMD__FLEXCAN1_TX 0x80000000 - >; - }; - - pinctrl_hummingboard_gpio1_2: hummingboard-gpio1_2 { - fsl,pins = < - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 - >; - }; - - pinctrl_hummingboard_hdmi: hummingboard-hdmi { - fsl,pins = < - MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0 - >; - }; - - pinctrl_hummingboard_i2c1: hummingboard-i2c1 { - fsl,pins = < - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 - >; - }; - - pinctrl_hummingboard_i2c2: hummingboard-i2c2 { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_hummingboard_spdif: hummingboard-spdif { - fsl,pins = ; - }; - - pinctrl_hummingboard_usbh1_vbus: hummingboard-usbh1-vbus { - fsl,pins = ; - }; - - pinctrl_hummingboard_usbotg_id: hummingboard-usbotg-id { - /* - * Similar to pinctrl_usbotg_2, but we want it - * pulled down for a fixed host connection. - */ - fsl,pins = ; - }; - - pinctrl_hummingboard_usbotg_vbus: hummingboard-usbotg-vbus { - fsl,pins = ; - }; - - pinctrl_hummingboard_usdhc2_aux: hummingboard-usdhc2-aux { - fsl,pins = < - MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1f071 - >; - }; - - pinctrl_hummingboard_usdhc2: hummingboard-usdhc2 { - fsl,pins = < - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x13059 - >; - }; - }; -}; - -&spdif { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hummingboard_spdif>; - status = "okay"; -}; - -&usbh1 { - disable-over-current; - vbus-supply = <®_usbh1_vbus>; - status = "okay"; -}; - -&usbotg { - disable-over-current; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hummingboard_usbotg_id>; - vbus-supply = <®_usbotg_vbus>; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = < - &pinctrl_hummingboard_usdhc2_aux - &pinctrl_hummingboard_usdhc2 - >; - vmmc-supply = <®_3p3v>; - cd-gpios = <&gpio1 4 0>; - status = "okay"; + model = "SolidRun HummingBoard Solo/DualLite"; + compatible = "solidrun,hummingboard/dl", "fsl,imx6dl"; }; diff --git a/arch/arm/boot/dts/imx6q-hummingboard.dts b/arch/arm/boot/dts/imx6q-hummingboard.dts new file mode 100644 index 0000000..0a35741 --- /dev/null +++ b/arch/arm/boot/dts/imx6q-hummingboard.dts @@ -0,0 +1,13 @@ +/* + * Copyright (C) 2014 Rabeeh Khoury (rabeeh@solid-run.com) + * Based on dt work by Russell King + */ +/dts-v1/; + +#include "imx6q.dtsi" +#include "imx6qdl-hummingboard.dtsi" + +/ { + model = "SolidRun HummingBoard Dual/Quad"; + compatible = "solidrun,hummingboard/q", "fsl,imx6q"; +}; diff --git a/arch/arm/boot/dts/imx6qdl-hummingboard.dtsi b/arch/arm/boot/dts/imx6qdl-hummingboard.dtsi new file mode 100644 index 0000000..bf38072 --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-hummingboard.dtsi @@ -0,0 +1,200 @@ +/* + * Copyright (C) 2013,2014 Russell King + */ +#include "imx6qdl-microsom.dtsi" +#include "imx6qdl-microsom-ar8035.dtsi" + +/ { + chosen { + stdout-path = &uart1; + }; + + ir_recv: ir-receiver { + compatible = "gpio-ir-receiver"; + gpios = <&gpio1 2 1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hummingboard_gpio1_2>; + }; + + regulators { + compatible = "simple-bus"; + + reg_3p3v: 3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_usbh1_vbus: usb-h1-vbus { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio1 0 0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hummingboard_usbh1_vbus>; + regulator-name = "usb_h1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_usbotg_vbus: usb-otg-vbus { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio3 22 0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hummingboard_usbotg_vbus>; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + }; + + sound-spdif { + compatible = "fsl,imx-audio-spdif"; + model = "On-board SPDIF"; + /* IMX6 doesn't implement this yet */ + spdif-controller = <&spdif>; + spdif-out; + }; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hummingboard_flexcan1>; + status = "okay"; +}; + +&hdmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hummingboard_hdmi>; + ddc-i2c-bus = <&i2c2>; + status = "okay"; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hummingboard_i2c1>; + + /* + * Not fitted on Carrier-1 board... yet + status = "okay"; + + rtc: pcf8523@68 { + compatible = "nxp,pcf8523"; + reg = <0x68>; + }; + */ +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hummingboard_i2c2>; + status = "okay"; +}; + +&iomuxc { + hummingboard { + pinctrl_hummingboard_flexcan1: hummingboard-flexcan1 { + fsl,pins = < + MX6QDL_PAD_SD3_CLK__FLEXCAN1_RX 0x80000000 + MX6QDL_PAD_SD3_CMD__FLEXCAN1_TX 0x80000000 + >; + }; + + pinctrl_hummingboard_gpio1_2: hummingboard-gpio1_2 { + fsl,pins = < + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 + >; + }; + + pinctrl_hummingboard_hdmi: hummingboard-hdmi { + fsl,pins = < + MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0 + >; + }; + + pinctrl_hummingboard_i2c1: hummingboard-i2c1 { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + >; + }; + + pinctrl_hummingboard_i2c2: hummingboard-i2c2 { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_hummingboard_spdif: hummingboard-spdif { + fsl,pins = ; + }; + + pinctrl_hummingboard_usbh1_vbus: hummingboard-usbh1-vbus { + fsl,pins = ; + }; + + pinctrl_hummingboard_usbotg_id: hummingboard-usbotg-id { + /* + * Similar to pinctrl_usbotg_2, but we want it + * pulled down for a fixed host connection. + */ + fsl,pins = ; + }; + + pinctrl_hummingboard_usbotg_vbus: hummingboard-usbotg-vbus { + fsl,pins = ; + }; + + pinctrl_hummingboard_usdhc2_aux: hummingboard-usdhc2-aux { + fsl,pins = < + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1f071 + >; + }; + + pinctrl_hummingboard_usdhc2: hummingboard-usdhc2 { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x13059 + >; + }; + }; +}; + +&spdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hummingboard_spdif>; + status = "okay"; +}; + +&usbh1 { + disable-over-current; + vbus-supply = <®_usbh1_vbus>; + status = "okay"; +}; + +&usbotg { + disable-over-current; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hummingboard_usbotg_id>; + vbus-supply = <®_usbotg_vbus>; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = < + &pinctrl_hummingboard_usdhc2_aux + &pinctrl_hummingboard_usdhc2 + >; + vmmc-supply = <®_3p3v>; + cd-gpios = <&gpio1 4 0>; + status = "okay"; +}; -- cgit v0.10.2 From 4011009d2300f23e60a780ac3fb3609aafd30874 Mon Sep 17 00:00:00 2001 From: Rabeeh Khoury Date: Sat, 23 Aug 2014 10:11:42 +0100 Subject: ARM: dts: hummingboard: add mSATA support for iMX6 quad/dual HummingBoard Initial patch from Rabeeh, but with the electrical properties added. Signed-off-by: Rabeeh Khoury Signed-off-by: Russell King Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/imx6q-hummingboard.dts b/arch/arm/boot/dts/imx6q-hummingboard.dts index 0a35741..c2bf847 100644 --- a/arch/arm/boot/dts/imx6q-hummingboard.dts +++ b/arch/arm/boot/dts/imx6q-hummingboard.dts @@ -11,3 +11,11 @@ model = "SolidRun HummingBoard Dual/Quad"; compatible = "solidrun,hummingboard/q", "fsl,imx6q"; }; + +&sata { + status = "okay"; + fsl,transmit-level-mV = <1025>; + fsl,transmit-boost-mdB = <3330>; + fsl,transmit-atten-16ths = <9>; + fsl,receive-eq-mdB = <3000>; +}; -- cgit v0.10.2 From af3f973b8706b9754eab4f3eccfd332a570046f9 Mon Sep 17 00:00:00 2001 From: Rabeeh Khoury Date: Sat, 23 Aug 2014 10:11:47 +0100 Subject: ARM: dts: hummingboard: gpio-ir on gpio 3,5 HummingBoard after rev 2.0 and the production one starting rev 3.0 uses gpio 3,5 (EIM_DA5 pad) as the gpio infra red receiver input. Since the original Carrier1 board is obsolete and we are retiring it, update the DT file for this. This will mean IR reception will not work on Carrier1 with this DT file. Signed-off-by: Rabeeh Khoury Signed-off-by: Russell King Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/imx6qdl-hummingboard.dtsi b/arch/arm/boot/dts/imx6qdl-hummingboard.dtsi index bf38072..1f35580 100644 --- a/arch/arm/boot/dts/imx6qdl-hummingboard.dtsi +++ b/arch/arm/boot/dts/imx6qdl-hummingboard.dtsi @@ -11,9 +11,9 @@ ir_recv: ir-receiver { compatible = "gpio-ir-receiver"; - gpios = <&gpio1 2 1>; + gpios = <&gpio3 5 1>; pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hummingboard_gpio1_2>; + pinctrl-0 = <&pinctrl_hummingboard_gpio3_5>; }; regulators { @@ -103,9 +103,9 @@ >; }; - pinctrl_hummingboard_gpio1_2: hummingboard-gpio1_2 { + pinctrl_hummingboard_gpio3_5: hummingboard-gpio3_5 { fsl,pins = < - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 + MX6QDL_PAD_EIM_DA5__GPIO3_IO05 0x80000000 >; }; -- cgit v0.10.2 From d56ac1929cfe00e2071524a6fcbb340f7faef66e Mon Sep 17 00:00:00 2001 From: Russell King Date: Sat, 23 Aug 2014 15:34:07 +0100 Subject: ARM: dts: hummingboard: fix configuration of IR input Add the IOMUX setting for the IR input, rather than relying on the boot loader. Signed-off-by: Russell King Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/imx6qdl-hummingboard.dtsi b/arch/arm/boot/dts/imx6qdl-hummingboard.dtsi index 1f35580..62841e8 100644 --- a/arch/arm/boot/dts/imx6qdl-hummingboard.dtsi +++ b/arch/arm/boot/dts/imx6qdl-hummingboard.dtsi @@ -105,7 +105,7 @@ pinctrl_hummingboard_gpio3_5: hummingboard-gpio3_5 { fsl,pins = < - MX6QDL_PAD_EIM_DA5__GPIO3_IO05 0x80000000 + MX6QDL_PAD_EIM_DA5__GPIO3_IO05 0x1b0b1 >; }; -- cgit v0.10.2 From acc3329e04029f41f69d07a22d5c450094230213 Mon Sep 17 00:00:00 2001 From: Alexander Shiyan Date: Sun, 31 Aug 2014 15:54:15 +0400 Subject: ARM: dts: Add support for the i.MX1 Armadeus APF9328 board This patch adds support for the i.MX1 APF9328 from Armadeus. This change is intended to further remove non-DT support for this board. Signed-off-by: Alexander Shiyan Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index b022972..b51d485 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -162,6 +162,7 @@ dtb-$(CONFIG_ARCH_MARCO) += marco-evb.dtb dtb-$(CONFIG_ARCH_MOXART) += moxart-uc7112lx.dtb dtb-$(CONFIG_ARCH_MXC) += \ imx1-ads.dtb \ + imx1-apf9328.dtb \ imx25-eukrea-mbimxsd25-baseboard.dtb \ imx25-eukrea-mbimxsd25-baseboard-cmo-qvga.dtb \ imx25-eukrea-mbimxsd25-baseboard-dvi-svga.dtb \ diff --git a/arch/arm/boot/dts/imx1-apf9328.dts b/arch/arm/boot/dts/imx1-apf9328.dts new file mode 100644 index 0000000..07d92fb --- /dev/null +++ b/arch/arm/boot/dts/imx1-apf9328.dts @@ -0,0 +1,129 @@ +/* + * Copyright (C) 2014 Alexander Shiyan + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +#include "imx1.dtsi" + +/ { + model = "Armadeus APF9328"; + compatible = "armadeus,imx1-apf9328", "fsl,imx1"; + + chosen { + stdout-path = &uart1; + }; + + memory { + reg = <0x08000000 0x00800000>; + }; +}; + +&i2c { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + fsl,uart-has-rtscts; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + fsl,uart-has-rtscts; + status = "okay"; +}; + +&weim { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_weim>; + status = "okay"; + + nor: nor@0,0 { + compatible = "cfi-flash"; + reg = <0 0x00000000 0x02000000>; + bank-width = <2>; + fsl,weim-cs-timing = <0x00330e04 0x00000d01>; + #address-cells = <1>; + #size-cells = <1>; + }; + + eth: eth@4,c00000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eth>; + compatible = "davicom,dm9000"; + reg = < + 4 0x00c00000 0x2 + 4 0x00c00002 0x2 + >; + interrupt-parent = <&gpio2>; + interrupts = <14 IRQ_TYPE_LEVEL_LOW>; + fsl,weim-cs-timing = <0x0000c700 0x19190d01>; + }; +}; + +&iomuxc { + imx1-apf9328 { + pinctrl_eth: ethgrp { + fsl,pins = < + MX1_PAD_SIM_SVEN__GPIO2_14 0x0 + >; + }; + + pinctrl_i2c: i2cgrp { + fsl,pins = < + MX1_PAD_I2C_SCL__I2C_SCL 0x0 + MX1_PAD_I2C_SDA__I2C_SDA 0x0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX1_PAD_UART1_TXD__UART1_TXD 0x0 + MX1_PAD_UART1_RXD__UART1_RXD 0x0 + MX1_PAD_UART1_CTS__UART1_CTS 0x0 + MX1_PAD_UART1_RTS__UART1_RTS 0x0 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX1_PAD_UART2_TXD__UART2_TXD 0x0 + MX1_PAD_UART2_RXD__UART2_RXD 0x0 + MX1_PAD_UART2_CTS__UART2_CTS 0x0 + MX1_PAD_UART2_RTS__UART2_RTS 0x0 + >; + }; + + pinctrl_weim: weimgrp { + fsl,pins = < + MX1_PAD_A0__A0 0x0 + MX1_PAD_A16__A16 0x0 + MX1_PAD_A17__A17 0x0 + MX1_PAD_A18__A18 0x0 + MX1_PAD_A19__A19 0x0 + MX1_PAD_A20__A20 0x0 + MX1_PAD_A21__A21 0x0 + MX1_PAD_A22__A22 0x0 + MX1_PAD_A23__A23 0x0 + MX1_PAD_A24__A24 0x0 + MX1_PAD_BCLK__BCLK 0x0 + MX1_PAD_CS4__CS4 0x0 + MX1_PAD_DTACK__DTACK 0x0 + MX1_PAD_ECB__ECB 0x0 + MX1_PAD_LBA__LBA 0x0 + >; + }; + }; +}; -- cgit v0.10.2 From fcd1730394330bdccac762190f8ec50d06c24daf Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Thu, 7 Aug 2014 19:39:41 +0200 Subject: ARM: imx6: add pci config space as platform resource Fixes "imx6q-pcie 1ffc000.pcie: missing *config* reg space" error exposed by new versions of the designware pcie driver. Signed-off-by: Lucas Stach Signed-off-by: Shawn Guo diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt index 9455fd0..6fbba53 100644 --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt @@ -17,7 +17,9 @@ Example: pcie@0x01000000 { compatible = "fsl,imx6q-pcie", "snps,dw-pcie"; - reg = <0x01ffc000 0x4000>; + reg = <0x01ffc000 0x04000>, + <0x01f00000 0x80000>; + reg-names = "dbi", "config"; #address-cells = <3>; #size-cells = <2>; device_type = "pci"; diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi index 6692115..70d7207 100644 --- a/arch/arm/boot/dts/imx6qdl.dtsi +++ b/arch/arm/boot/dts/imx6qdl.dtsi @@ -137,7 +137,9 @@ pcie: pcie@0x01000000 { compatible = "fsl,imx6q-pcie", "snps,dw-pcie"; - reg = <0x01ffc000 0x4000>; /* DBI */ + reg = <0x01ffc000 0x04000>, + <0x01f00000 0x80000>; + reg-names = "dbi", "config"; #address-cells = <3>; #size-cells = <2>; device_type = "pci"; -- cgit v0.10.2 From 7591e5cd1c10e5764aaf7ce50c7c6c50b7f6aa36 Mon Sep 17 00:00:00 2001 From: Philippe Reynes Date: Mon, 1 Sep 2014 20:44:32 +0200 Subject: ARM: dts: apf27dev: add max1027 in the dts Signed-off-by: Philippe Reynes Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/imx27-apf27dev.dts b/arch/arm/boot/dts/imx27-apf27dev.dts index 2b6d489..da306c5 100644 --- a/arch/arm/boot/dts/imx27-apf27dev.dts +++ b/arch/arm/boot/dts/imx27-apf27dev.dts @@ -67,6 +67,16 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_cspi1 &pinctrl_cspi1_cs>; status = "okay"; + + adc@0 { + compatible = "maxim,max1027"; + reg = <0>; + interrupt-parent = <&gpio5>; + interrupts = <15 IRQ_TYPE_EDGE_FALLING>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_max1027>; + spi-max-frequency = <10000000>; + }; }; &cspi2 { @@ -189,6 +199,13 @@ >; }; + pinctrl_max1027: max1027 { + fsl,pins = < + MX27_PAD_UART1_CTS__GPIO5_14 0x0 /* CNVST */ + MX27_PAD_UART1_RTS__GPIO5_15 0x0 /* EOC */ + >; + }; + pinctrl_pwm: pwmgrp { fsl,pins = < MX27_PAD_PWMO__PWMO 0x0 -- cgit v0.10.2 From 8c78c407bc1b0312e02a3ba9685495c6a2fa7f17 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 2 Sep 2014 15:00:43 -0300 Subject: ARM: dts: imx6sx: Add LCDIF compatible strings imx6sx has the same LCDIF controller IP as in mx28, so add the proper compatible strings. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi index 63d9d82..d137caca 100644 --- a/arch/arm/boot/dts/imx6sx.dtsi +++ b/arch/arm/boot/dts/imx6sx.dtsi @@ -1065,6 +1065,7 @@ }; lcdif1: lcdif@02220000 { + compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif"; reg = <0x02220000 0x4000>; interrupts = ; clocks = <&clks IMX6SX_CLK_LCDIF1_PIX>, @@ -1075,6 +1076,7 @@ }; lcdif2: lcdif@02224000 { + compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif"; reg = <0x02224000 0x4000>; interrupts = ; clocks = <&clks IMX6SX_CLK_LCDIF2_PIX>, -- cgit v0.10.2 From 31ffdbc80c8f139b0fe7f117d04bca0165e7e35e Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 2 Sep 2014 15:00:44 -0300 Subject: ARM: dts: imx6x-sdb: Add LCD support Add support for the "MX28LCD Seiko 4.3' WVGA" panel. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/imx6sx-sdb.dts b/arch/arm/boot/dts/imx6sx-sdb.dts index a3980d9..82d6b34 100644 --- a/arch/arm/boot/dts/imx6sx-sdb.dts +++ b/arch/arm/boot/dts/imx6sx-sdb.dts @@ -24,6 +24,13 @@ reg = <0x80000000 0x40000000>; }; + backlight { + compatible = "pwm-backlight"; + pwms = <&pwm3 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + }; + gpio-keys { compatible = "gpio-keys"; pinctrl-names = "default"; @@ -90,6 +97,14 @@ regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; }; + + reg_lcd_3v3: regulator@4 { + compatible = "regulator-fixed"; + reg = <4>; + regulator-name = "lcd-3v3"; + gpio = <&gpio3 27 0>; + enable-active-high; + }; }; sound { @@ -251,6 +266,44 @@ }; }; +&lcdif1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd>; + lcd-supply = <®_lcd_3v3>; + display = <&display0>; + status = "okay"; + + display0: display0 { + bits-per-pixel = <16>; + bus-width = <24>; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <33500000>; + hactive = <800>; + vactive = <480>; + hback-porch = <89>; + hfront-porch = <164>; + vback-porch = <23>; + vfront-porch = <10>; + hsync-len = <10>; + vsync-len = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + }; + }; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; + status = "okay"; +}; + &ssi2 { status = "okay"; }; @@ -365,6 +418,46 @@ >; }; + pinctrl_lcd: lcdgrp { + fsl,pins = < + MX6SX_PAD_LCD1_DATA00__LCDIF1_DATA_0 0x4001b0b0 + MX6SX_PAD_LCD1_DATA01__LCDIF1_DATA_1 0x4001b0b0 + MX6SX_PAD_LCD1_DATA02__LCDIF1_DATA_2 0x4001b0b0 + MX6SX_PAD_LCD1_DATA03__LCDIF1_DATA_3 0x4001b0b0 + MX6SX_PAD_LCD1_DATA04__LCDIF1_DATA_4 0x4001b0b0 + MX6SX_PAD_LCD1_DATA05__LCDIF1_DATA_5 0x4001b0b0 + MX6SX_PAD_LCD1_DATA06__LCDIF1_DATA_6 0x4001b0b0 + MX6SX_PAD_LCD1_DATA07__LCDIF1_DATA_7 0x4001b0b0 + MX6SX_PAD_LCD1_DATA08__LCDIF1_DATA_8 0x4001b0b0 + MX6SX_PAD_LCD1_DATA09__LCDIF1_DATA_9 0x4001b0b0 + MX6SX_PAD_LCD1_DATA10__LCDIF1_DATA_10 0x4001b0b0 + MX6SX_PAD_LCD1_DATA11__LCDIF1_DATA_11 0x4001b0b0 + MX6SX_PAD_LCD1_DATA12__LCDIF1_DATA_12 0x4001b0b0 + MX6SX_PAD_LCD1_DATA13__LCDIF1_DATA_13 0x4001b0b0 + MX6SX_PAD_LCD1_DATA14__LCDIF1_DATA_14 0x4001b0b0 + MX6SX_PAD_LCD1_DATA15__LCDIF1_DATA_15 0x4001b0b0 + MX6SX_PAD_LCD1_DATA16__LCDIF1_DATA_16 0x4001b0b0 + MX6SX_PAD_LCD1_DATA17__LCDIF1_DATA_17 0x4001b0b0 + MX6SX_PAD_LCD1_DATA18__LCDIF1_DATA_18 0x4001b0b0 + MX6SX_PAD_LCD1_DATA19__LCDIF1_DATA_19 0x4001b0b0 + MX6SX_PAD_LCD1_DATA20__LCDIF1_DATA_20 0x4001b0b0 + MX6SX_PAD_LCD1_DATA21__LCDIF1_DATA_21 0x4001b0b0 + MX6SX_PAD_LCD1_DATA22__LCDIF1_DATA_22 0x4001b0b0 + MX6SX_PAD_LCD1_DATA23__LCDIF1_DATA_23 0x4001b0b0 + MX6SX_PAD_LCD1_CLK__LCDIF1_CLK 0x4001b0b0 + MX6SX_PAD_LCD1_ENABLE__LCDIF1_ENABLE 0x4001b0b0 + MX6SX_PAD_LCD1_VSYNC__LCDIF1_VSYNC 0x4001b0b0 + MX6SX_PAD_LCD1_HSYNC__LCDIF1_HSYNC 0x4001b0b0 + MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 0x4001b0b0 + >; + }; + + pinctrl_pwm3: pwm3grp-1 { + fsl,pins = < + MX6SX_PAD_SD1_DATA2__PWM3_OUT 0x110b0 + >; + }; + pinctrl_vcc_sd3: vccsd3grp { fsl,pins = < MX6SX_PAD_KEY_COL1__GPIO2_IO_11 0x17059 -- cgit v0.10.2 From 20d412b2d805d650d1b820d41a80e023d6a98461 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 2 Sep 2014 22:45:12 -0300 Subject: ARM: dts: imx28-evk: Fix display duplicate name warning The lcdif node has a property named "display" and also a child node called "display", which causes the following warning: device-tree: Duplicate name in lcdif@80030000, renamed to "display#1" Rename the child node name in order to avoid the warning. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/imx28-evk.dts b/arch/arm/boot/dts/imx28-evk.dts index e4cc44c..09664fc 100644 --- a/arch/arm/boot/dts/imx28-evk.dts +++ b/arch/arm/boot/dts/imx28-evk.dts @@ -124,10 +124,10 @@ pinctrl-0 = <&lcdif_24bit_pins_a &lcdif_pins_evk>; lcd-supply = <®_lcd_3v3>; - display = <&display>; + display = <&display0>; status = "okay"; - display: display { + display0: display0 { bits-per-pixel = <32>; bus-width = <24>; -- cgit v0.10.2 From 3148092df08f741d677c8eadce5a409555eda32c Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 2 Sep 2014 22:45:13 -0300 Subject: ARM: dts: imx23-evk: Fix display duplicate name warning The lcdif node has a property named "display" and also a child node called "display", which causes the following warning: device-tree: Duplicate name in lcdif@80030000, renamed to "display#1" Rename the child node name in order to avoid the warning. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/imx23-evk.dts b/arch/arm/boot/dts/imx23-evk.dts index a33f66c..57e2997 100644 --- a/arch/arm/boot/dts/imx23-evk.dts +++ b/arch/arm/boot/dts/imx23-evk.dts @@ -60,10 +60,10 @@ pinctrl-names = "default"; pinctrl-0 = <&lcdif_24bit_pins_a>; lcd-supply = <®_lcd_3v3>; - display = <&display>; + display = <&display0>; status = "okay"; - display: display { + display0: display0 { bits-per-pixel = <32>; bus-width = <24>; -- cgit v0.10.2 From 3f50a61937b3fabe0c46123cef48e2569042ca07 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 2 Sep 2014 22:45:14 -0300 Subject: ARM: dts: imx6sl-evk: Fix display duplicate name warning The lcdif node has a property named "display" and also a child node called "display", which causes the following warning: device-tree: Duplicate name in lcdif@02220000, renamed to "display#1" Rename the child node name in order to avoid the warning. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/imx6sl-evk.dts b/arch/arm/boot/dts/imx6sl-evk.dts index 9925c4a..898d14f 100644 --- a/arch/arm/boot/dts/imx6sl-evk.dts +++ b/arch/arm/boot/dts/imx6sl-evk.dts @@ -546,10 +546,10 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_lcd>; lcd-supply = <®_lcd_3v3>; - display = <&display>; + display = <&display0>; status = "okay"; - display: display { + display0: display0 { bits-per-pixel = <32>; bus-width = <24>; -- cgit v0.10.2 From d46c2dc14e92a7d7153f24b1e03321fc694ae906 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Thu, 4 Sep 2014 22:31:18 -0300 Subject: ARM: dts: imx28-apx4devkit: Fix display duplicate name warning The lcdif node has a property named "display" and also a child node called "display", which causes the following warning: device-tree: Duplicate name in lcdif@80030000, renamed to "display#1" Rename the child node name in order to avoid the warning. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/imx28-apx4devkit.dts b/arch/arm/boot/dts/imx28-apx4devkit.dts index e1ce917..1092b76 100644 --- a/arch/arm/boot/dts/imx28-apx4devkit.dts +++ b/arch/arm/boot/dts/imx28-apx4devkit.dts @@ -94,10 +94,10 @@ pinctrl-names = "default"; pinctrl-0 = <&lcdif_24bit_pins_a &lcdif_pins_apx4>; - display = <&display>; + display = <&display0>; status = "okay"; - display: display { + display0: display0 { bits-per-pixel = <32>; bus-width = <24>; -- cgit v0.10.2 From ee99b4636b3108a3a6d92f1189b797006e4416e9 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Thu, 4 Sep 2014 22:31:19 -0300 Subject: ARM: dts: imx28-apf28dev: Fix display duplicate name warning The lcdif node has a property named "display" and also a child node called "display", which causes the following warning: device-tree: Duplicate name in lcdif@80030000, renamed to "display#1" Rename the child node name in order to avoid the wa Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/imx28-apf28dev.dts b/arch/arm/boot/dts/imx28-apf28dev.dts index 221cac4..1f38a05 100644 --- a/arch/arm/boot/dts/imx28-apf28dev.dts +++ b/arch/arm/boot/dts/imx28-apf28dev.dts @@ -83,10 +83,10 @@ pinctrl-names = "default"; pinctrl-0 = <&lcdif_16bit_pins_a &lcdif_pins_apf28dev>; - display = <&display>; + display = <&display0>; status = "okay"; - display: display { + display0: display0 { bits-per-pixel = <16>; bus-width = <16>; -- cgit v0.10.2 From 7029b396b08aeb15d8cb23c4bff3e10c1f518238 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Thu, 4 Sep 2014 22:31:20 -0300 Subject: ARM: dts: imx28-cfa100: Fix display duplicate name warning The lcdif node has a property named "display" and also a child node called "display", which causes the following warning: device-tree: Duplicate name in lcdif@80030000, renamed to "display#1" Rename the child node name in order to avoid the warning. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/imx28-cfa10049.dts b/arch/arm/boot/dts/imx28-cfa10049.dts index 7d51459..ef944b6 100644 --- a/arch/arm/boot/dts/imx28-cfa10049.dts +++ b/arch/arm/boot/dts/imx28-cfa10049.dts @@ -177,10 +177,10 @@ pinctrl-0 = <&lcdif_18bit_pins_cfa10049 &lcdif_pins_cfa10049 &lcdif_pins_cfa10049_pullup>; - display = <&display>; + display = <&display0>; status = "okay"; - display: display { + display0: display0 { bits-per-pixel = <32>; bus-width = <18>; diff --git a/arch/arm/boot/dts/imx28-cfa10055.dts b/arch/arm/boot/dts/imx28-cfa10055.dts index c3900e7..6a34114 100644 --- a/arch/arm/boot/dts/imx28-cfa10055.dts +++ b/arch/arm/boot/dts/imx28-cfa10055.dts @@ -92,10 +92,10 @@ pinctrl-0 = <&lcdif_18bit_pins_cfa10055 &lcdif_pins_cfa10055 &lcdif_pins_cfa10055_pullup>; - display = <&display>; + display = <&display0>; status = "okay"; - display: display { + display0: display0 { bits-per-pixel = <32>; bus-width = <18>; diff --git a/arch/arm/boot/dts/imx28-cfa10056.dts b/arch/arm/boot/dts/imx28-cfa10056.dts index cef959a..ba6495c 100644 --- a/arch/arm/boot/dts/imx28-cfa10056.dts +++ b/arch/arm/boot/dts/imx28-cfa10056.dts @@ -64,10 +64,10 @@ pinctrl-0 = <&lcdif_24bit_pins_a &lcdif_pins_cfa10056 &lcdif_pins_cfa10056_pullup >; - display = <&display>; + display = <&display0>; status = "okay"; - display: display { + display0: display0 { bits-per-pixel = <32>; bus-width = <24>; diff --git a/arch/arm/boot/dts/imx28-cfa10057.dts b/arch/arm/boot/dts/imx28-cfa10057.dts index c4e00ce..5df0b24 100644 --- a/arch/arm/boot/dts/imx28-cfa10057.dts +++ b/arch/arm/boot/dts/imx28-cfa10057.dts @@ -78,10 +78,10 @@ pinctrl-names = "default"; pinctrl-0 = <&lcdif_18bit_pins_cfa10057 &lcdif_pins_cfa10057>; - display = <&display>; + display = <&display0>; status = "okay"; - display: display { + display0: display0 { bits-per-pixel = <32>; bus-width = <18>; diff --git a/arch/arm/boot/dts/imx28-cfa10058.dts b/arch/arm/boot/dts/imx28-cfa10058.dts index 7c9cc78..f5c6dce 100644 --- a/arch/arm/boot/dts/imx28-cfa10058.dts +++ b/arch/arm/boot/dts/imx28-cfa10058.dts @@ -51,10 +51,10 @@ pinctrl-names = "default"; pinctrl-0 = <&lcdif_24bit_pins_a &lcdif_pins_cfa10058>; - display = <&display>; + display = <&display0>; status = "okay"; - display: display { + display0: display0 { bits-per-pixel = <32>; bus-width = <24>; -- cgit v0.10.2 From 7f0d61d6365c01b5941e2c166684392ccf9c340c Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Thu, 4 Sep 2014 22:31:21 -0300 Subject: ARM: dts: imx28-m28cu: Fix display duplicate name warning The lcdif node has a property named "display" and also a child node called "display", which causes the following warning: device-tree: Duplicate name in lcdif@80030000, renamed to "display#1" Rename the child node name in order to avoid the warning. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/imx28-m28cu3.dts b/arch/arm/boot/dts/imx28-m28cu3.dts index 9348ce5..2df63be 100644 --- a/arch/arm/boot/dts/imx28-m28cu3.dts +++ b/arch/arm/boot/dts/imx28-m28cu3.dts @@ -115,10 +115,10 @@ pinctrl-names = "default"; pinctrl-0 = <&lcdif_24bit_pins_a &lcdif_pins_m28>; - display = <&display>; + display = <&display0>; status = "okay"; - display: display0 { + display0: display0 { bits-per-pixel = <32>; bus-width = <24>; -- cgit v0.10.2 From 58a32d91306787d6733767321a14c39afc136d93 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Thu, 4 Sep 2014 22:31:22 -0300 Subject: ARM: dts: imx28-tx28: Fix display duplicate name warning MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The lcdif node has a property named "display" and also a child node called "display", which causes the following warning: device-tree: Duplicate name in lcdif@80030000, renamed to "display#1" Rename the child node name in order to avoid the warning. Signed-off-by: Fabio Estevam Acked-by: Lothar Waßmann Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/imx28-tx28.dts b/arch/arm/boot/dts/imx28-tx28.dts index e14bd86..f947fbb 100644 --- a/arch/arm/boot/dts/imx28-tx28.dts +++ b/arch/arm/boot/dts/imx28-tx28.dts @@ -21,7 +21,7 @@ aliases { can0 = &can0; can1 = &can1; - display = &display; + display = &display0; ds1339 = &ds1339; gpio5 = &gpio5; lcdif = &lcdif; @@ -309,10 +309,10 @@ pinctrl-names = "default"; pinctrl-0 = <&lcdif_24bit_pins_a &lcdif_sync_pins_a &tx28_lcdif_ctrl_pins>; lcd-supply = <®_lcd>; - display = <&display>; + display = <&display0>; status = "okay"; - display: display@0 { + display0: display0 { bits-per-pixel = <32>; bus-width = <24>; display-timings { -- cgit v0.10.2 From 433fb101132047383b550c58585b5a38797c90d1 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Thu, 4 Sep 2014 22:31:23 -0300 Subject: ARM: dts: imx28-m28evk: Fix display duplicate name warning The lcdif node has a property named "display" and also a child node called "display", which causes the following warning: device-tree: Duplicate name in lcdif@80030000, renamed to "display#1" Rename the child node name in order to avoid the warning. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/imx28-m28evk.dts b/arch/arm/boot/dts/imx28-m28evk.dts index b3c09ae..e35cc6b 100644 --- a/arch/arm/boot/dts/imx28-m28evk.dts +++ b/arch/arm/boot/dts/imx28-m28evk.dts @@ -81,10 +81,10 @@ pinctrl-names = "default"; pinctrl-0 = <&lcdif_24bit_pins_a &lcdif_pins_m28>; - display = <&display>; + display = <&display0>; status = "okay"; - display: display { + display0: display0 { bits-per-pixel = <16>; bus-width = <18>; -- cgit v0.10.2 From 9a060c1a3bb8f5f3940ddb82cb7aa76a843b96cc Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Fri, 5 Sep 2014 09:46:10 -0300 Subject: ARM: dts: imx6qdl-sabresd: Configure the pins locally Passing '0x80000000' to the pin configuration means that kernel will skip the IOMUXC_SW_PAD_CTL configuration and will use whathever values come from the bootloader. Instead of relying on the bootloader setup, let's configure it in the kernel to have predictable settings. '0x1b0b0' is the default POR value for all these pins and has also been verified that the pins are using this value by manually inspecting the IOMUXC_SW_PAD_CTL registers, so no functional change has been made. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi index 07fb302..baf2f00 100644 --- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi @@ -327,15 +327,15 @@ imx6qdl-sabresd { pinctrl_hog: hoggrp { fsl,pins = < - MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x80000000 - MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x80000000 - MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x80000000 - MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x80000000 + MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0 + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 + MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0 + MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 - MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x80000000 - MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000 - MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x80000000 + MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x1b0b0 + MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 + MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0 >; }; @@ -380,9 +380,9 @@ pinctrl_gpio_keys: gpio_keysgrp { fsl,pins = < - MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x80000000 - MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x80000000 - MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x80000000 + MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1b0b0 + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 + MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b0 >; }; @@ -409,7 +409,7 @@ pinctrl_pcie: pciegrp { fsl,pins = < - MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x80000000 + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 >; }; @@ -487,7 +487,7 @@ gpio_leds { pinctrl_gpio_leds: gpioledsgrp { fsl,pins = < - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 >; }; }; -- cgit v0.10.2 From 935632e9938e3e286b9c62a7e54d35c428533cc9 Mon Sep 17 00:00:00 2001 From: Shengjiu Wang Date: Tue, 9 Sep 2014 17:13:26 +0800 Subject: ARM: dts: imx6qdl: add baud clock and clock-names for ssi Baud clock is used for bit clock generation in master mode. Ipg clock is peripheral clock and peripheral access clock. Signed-off-by: Shengjiu Wang Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi index 70d7207..0de8806 100644 --- a/arch/arm/boot/dts/imx6qdl.dtsi +++ b/arch/arm/boot/dts/imx6qdl.dtsi @@ -280,7 +280,9 @@ "fsl,imx51-ssi"; reg = <0x02028000 0x4000>; interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_SSI1_IPG>; + clocks = <&clks IMX6QDL_CLK_SSI1_IPG>, + <&clks IMX6QDL_CLK_SSI1>; + clock-names = "ipg", "baud"; dmas = <&sdma 37 1 0>, <&sdma 38 1 0>; dma-names = "rx", "tx"; @@ -294,7 +296,9 @@ "fsl,imx51-ssi"; reg = <0x0202c000 0x4000>; interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_SSI2_IPG>; + clocks = <&clks IMX6QDL_CLK_SSI2_IPG>, + <&clks IMX6QDL_CLK_SSI2>; + clock-names = "ipg", "baud"; dmas = <&sdma 41 1 0>, <&sdma 42 1 0>; dma-names = "rx", "tx"; @@ -308,7 +312,9 @@ "fsl,imx51-ssi"; reg = <0x02030000 0x4000>; interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_SSI3_IPG>; + clocks = <&clks IMX6QDL_CLK_SSI3_IPG>, + <&clks IMX6QDL_CLK_SSI3>; + clock-names = "ipg", "baud"; dmas = <&sdma 45 1 0>, <&sdma 46 1 0>; dma-names = "rx", "tx"; -- cgit v0.10.2 From 50a8835b9caf40c08b1c7ad440946dd2b6c3eb6a Mon Sep 17 00:00:00 2001 From: Shengjiu Wang Date: Tue, 9 Sep 2014 17:13:27 +0800 Subject: ARM: dts: imx6sl: add baud clock and clock-names for ssi Baud clock is used for bit clock generation in master mode. Ipg clock is peripheral clock and peripheral access clock. Signed-off-by: Shengjiu Wang Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi index ba67714..dfd83e6 100644 --- a/arch/arm/boot/dts/imx6sl.dtsi +++ b/arch/arm/boot/dts/imx6sl.dtsi @@ -231,7 +231,9 @@ "fsl,imx51-ssi"; reg = <0x02028000 0x4000>; interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_SSI1>; + clocks = <&clks IMX6SL_CLK_SSI1_IPG>, + <&clks IMX6SL_CLK_SSI1>; + clock-names = "ipg", "baud"; dmas = <&sdma 37 1 0>, <&sdma 38 1 0>; dma-names = "rx", "tx"; @@ -245,7 +247,9 @@ "fsl,imx51-ssi"; reg = <0x0202c000 0x4000>; interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_SSI2>; + clocks = <&clks IMX6SL_CLK_SSI2_IPG>, + <&clks IMX6SL_CLK_SSI2>; + clock-names = "ipg", "baud"; dmas = <&sdma 41 1 0>, <&sdma 42 1 0>; dma-names = "rx", "tx"; @@ -259,7 +263,9 @@ "fsl,imx51-ssi"; reg = <0x02030000 0x4000>; interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_SSI3>; + clocks = <&clks IMX6SL_CLK_SSI3_IPG>, + <&clks IMX6SL_CLK_SSI3>; + clock-names = "ipg", "baud"; dmas = <&sdma 45 1 0>, <&sdma 46 1 0>; dma-names = "rx", "tx"; -- cgit v0.10.2 From e905e7f8d2ed6c59d4b1f2a4cad53b6c2d7eb785 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Lothar=20Wa=C3=9Fmann?= Date: Tue, 9 Sep 2014 13:26:00 +0200 Subject: ARM: dts: imx28-tx28: remove spidev labels and add third instance of spidev MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The labels on the spidev nodes are not used and not required, so remove them. The TX28 supports 3 chipselects on the SPI interface. Make all those chipselects available to the user. Signed-off-by: Lothar Waßmann Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/imx28-tx28.dts b/arch/arm/boot/dts/imx28-tx28.dts index f947fbb..4e790c2 100644 --- a/arch/arm/boot/dts/imx28-tx28.dts +++ b/arch/arm/boot/dts/imx28-tx28.dts @@ -619,17 +619,23 @@ clock-frequency = <57600000>; status = "okay"; - spidev0: spi@0 { + spi@0 { compatible = "spidev"; reg = <0>; spi-max-frequency = <57600000>; }; - spidev1: spi@1 { + spi@1 { compatible = "spidev"; reg = <1>; spi-max-frequency = <57600000>; }; + + spi@2 { + compatible = "spidev"; + reg = <2>; + spi-max-frequency = <57600000>; + }; }; &usb0 { -- cgit v0.10.2 From 4d6480ac8c063e270e5edb63b8cf721a6e01f1e6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Lothar=20Wa=C3=9Fmann?= Date: Tue, 9 Sep 2014 13:26:01 +0200 Subject: ARM: dts: imx28-tx28: use GPIO flags MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Lothar Waßmann Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/imx28-tx28.dts b/arch/arm/boot/dts/imx28-tx28.dts index 4e790c2..cfe6b31 100644 --- a/arch/arm/boot/dts/imx28-tx28.dts +++ b/arch/arm/boot/dts/imx28-tx28.dts @@ -37,7 +37,7 @@ onewire { compatible = "w1-gpio"; - gpios = <&gpio2 7 0>; + gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>; status = "disabled"; }; @@ -52,7 +52,7 @@ regulator-name = "usb0_vbus"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; - gpio = <&gpio0 18 0>; + gpio = <&gpio0 18 GPIO_ACTIVE_HIGH>; enable-active-high; }; @@ -62,7 +62,7 @@ regulator-name = "usb1_vbus"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; - gpio = <&gpio3 27 0>; + gpio = <&gpio3 27 GPIO_ACTIVE_HIGH>; enable-active-high; }; @@ -90,7 +90,7 @@ regulator-name = "CAN XCVR"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - gpio = <&gpio1 0 0>; + gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&tx28_flexcan_xcvr_pins>; }; @@ -101,7 +101,7 @@ regulator-name = "LCD POWER"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - gpio = <&gpio1 31 0>; + gpio = <&gpio1 31 GPIO_ACTIVE_HIGH>; enable-active-high; }; @@ -111,7 +111,7 @@ regulator-name = "LCD RESET"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - gpio = <&gpio3 30 0>; + gpio = <&gpio3 30 GPIO_ACTIVE_HIGH>; startup-delay-us = <300000>; enable-active-high; regulator-always-on; @@ -143,7 +143,7 @@ user_led: user { label = "Heartbeat"; - gpios = <&gpio4 10 0>; + gpios = <&gpio4 10 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; }; @@ -172,16 +172,16 @@ matrix_keypad: matrix-keypad@0 { compatible = "gpio-matrix-keypad"; col-gpios = < - &gpio5 0 0 - &gpio5 1 0 - &gpio5 2 0 - &gpio5 3 0 + &gpio5 0 GPIO_ACTIVE_HIGH + &gpio5 1 GPIO_ACTIVE_HIGH + &gpio5 2 GPIO_ACTIVE_HIGH + &gpio5 3 GPIO_ACTIVE_HIGH >; row-gpios = < - &gpio5 4 0 - &gpio5 5 0 - &gpio5 6 0 - &gpio5 7 0 + &gpio5 4 GPIO_ACTIVE_HIGH + &gpio5 5 GPIO_ACTIVE_HIGH + &gpio5 6 GPIO_ACTIVE_HIGH + &gpio5 7 GPIO_ACTIVE_HIGH >; /* sample keymap */ linux,keymap = < @@ -284,8 +284,8 @@ pinctrl-0 = <&tx28_edt_ft5x06_pins>; interrupt-parent = <&gpio2>; interrupts = <5 0>; - reset-gpios = <&gpio2 6 1>; - wake-gpios = <&gpio4 9 0>; + reset-gpios = <&gpio2 6 GPIO_ACTIVE_LOW>; + wake-gpios = <&gpio4 9 GPIO_ACTIVE_HIGH>; }; touchscreen: tsc2007@48 { @@ -295,7 +295,7 @@ pinctrl-0 = <&tx28_tsc2007_pins>; interrupt-parent = <&gpio3>; interrupts = <20 0>; - pendown-gpio = <&gpio3 20 1>; + pendown-gpio = <&gpio3 20 GPIO_ACTIVE_LOW>; ti,x-plate-ohms = /bits/ 16 <660>; }; -- cgit v0.10.2 From d7dbe2c78f74f1d6514b2ea4fc3f4740f01f70c5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Lothar=20Wa=C3=9Fmann?= Date: Tue, 9 Sep 2014 13:26:02 +0200 Subject: ARM: dts: imx28-tx28: add spi-gpio as alternative for spi-mxs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The spi-mxs driver does not allow full duplex SPI transfers. The spi-gpio driver may be used as an alternative if this is required. Make the choice between those drivers easier for the end user by providing settings for both drivers. Signed-off-by: Lothar Waßmann Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/imx28-tx28.dts b/arch/arm/boot/dts/imx28-tx28.dts index cfe6b31..81d4eb4 100644 --- a/arch/arm/boot/dts/imx28-tx28.dts +++ b/arch/arm/boot/dts/imx28-tx28.dts @@ -27,6 +27,8 @@ lcdif = &lcdif; lcdif_23bit_pins = &tx28_lcdif_23bit_pins; lcdif_24bit_pins = &lcdif_24bit_pins_a; + spi_gpio = &spi_gpio; + spi_mxs = &ssp3; stk5led = &user_led; usbotg = &usb0; }; @@ -203,6 +205,44 @@ col-scan-delay-us = <5000>; linux,no-autorepeat; }; + + spi_gpio: spi-gpio { + compatible = "spi-gpio"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&tx28_spi_gpio_pins>; + + gpio-sck = <&gpio2 24 GPIO_ACTIVE_HIGH>; + gpio-mosi = <&gpio2 25 GPIO_ACTIVE_HIGH>; + gpio-miso = <&gpio2 26 GPIO_ACTIVE_HIGH>; + num-chipselects = <3>; + cs-gpios = < + &gpio2 27 GPIO_ACTIVE_LOW + &gpio3 8 GPIO_ACTIVE_LOW + &gpio3 9 GPIO_ACTIVE_LOW + >; + /* enable this and disable ssp3 below, if you need full duplex SPI transfer */ + status = "disabled"; + + spi@0 { + compatible = "spidev"; + reg = <0>; + spi-max-frequency = <57600000>; + }; + + spi@1 { + compatible = "spidev"; + reg = <1>; + spi-max-frequency = <57600000>; + }; + + spi@2 { + compatible = "spidev"; + reg = <2>; + spi-max-frequency = <57600000>; + }; + }; }; /* 2nd TX-Std UART - (A)UART1 */ @@ -558,6 +598,20 @@ fsl,pull-up = ; }; + tx28_spi_gpio_pins: spi-gpiogrp { + fsl,pinmux-ids = < + MX28_PAD_AUART2_RX__GPIO_3_8 + MX28_PAD_AUART2_TX__GPIO_3_9 + MX28_PAD_SSP3_SCK__GPIO_2_24 + MX28_PAD_SSP3_MOSI__GPIO_2_25 + MX28_PAD_SSP3_MISO__GPIO_2_26 + MX28_PAD_SSP3_SS0__GPIO_2_27 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + tx28_tsc2007_pins: tx28-tsc2007-pins { fsl,pinmux-ids = < MX28_PAD_SAIF0_MCLK__GPIO_3_20 /* TSC2007 IRQ */ -- cgit v0.10.2 From 0361598baddc926d146b7f49e01c2231e19edaef Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Lothar=20Wa=C3=9Fmann?= Date: Tue, 9 Sep 2014 13:26:03 +0200 Subject: ARM: dts: imx28-tx28: add alias for CAN XCVR regulator MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This alias is used by U-Boot to enable/disable the regulator depending on baseboard type. Signed-off-by: Lothar Waßmann Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/imx28-tx28.dts b/arch/arm/boot/dts/imx28-tx28.dts index 81d4eb4..a5b27c8 100644 --- a/arch/arm/boot/dts/imx28-tx28.dts +++ b/arch/arm/boot/dts/imx28-tx28.dts @@ -27,6 +27,7 @@ lcdif = &lcdif; lcdif_23bit_pins = &tx28_lcdif_23bit_pins; lcdif_24bit_pins = &lcdif_24bit_pins_a; + reg_can_xcvr = ®_can_xcvr; spi_gpio = &spi_gpio; spi_mxs = &ssp3; stk5led = &user_led; -- cgit v0.10.2 From ea3b555e44a62a31fc90e1e034a8c797b92db28e Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Mon, 8 Sep 2014 23:07:26 -0700 Subject: ARM: dts: imx: ventana: remove unsupported dt nodes The general device-tree rule is to not include nodes that do not have a driver or bindings in a dts/dtsi. Remove the place-holder nodes from the Gateworks Ventana boards until a time that a driver with proper bindings exists. Signed-off-by: Tim Harvey Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/imx6q-gw5400-a.dts b/arch/arm/boot/dts/imx6q-gw5400-a.dts index 22e6f8e..d1ab780 100644 --- a/arch/arm/boot/dts/imx6q-gw5400-a.dts +++ b/arch/arm/boot/dts/imx6q-gw5400-a.dts @@ -199,11 +199,6 @@ #gpio-cells = <2>; }; - hwmon: gsc@29 { - compatible = "gw,gsp"; - reg = <0x29>; - }; - rtc: ds1672@68 { compatible = "dallas,ds1672"; reg = <0x68>; @@ -314,16 +309,6 @@ }; }; }; - - pciswitch: pex8609@3f { - compatible = "plx,pex8609"; - reg = <0x3f>; - }; - - pciclkgen: si52147@6b { - compatible = "sil,si52147"; - reg = <0x6b>; - }; }; &i2c3 { @@ -345,11 +330,6 @@ VDDIO-supply = <®_3p3v>; }; - hdmiin: adv7611@4c { - compatible = "adi,adv7611"; - reg = <0x4c>; - }; - touchscreen: egalax_ts@04 { compatible = "eeti,egalax_ts"; reg = <0x04>; @@ -357,16 +337,6 @@ interrupts = <12 2>; /* gpio7_12 active low */ wakeup-gpios = <&gpio7 12 0>; }; - - videoout: adv7393@2a { - compatible = "adi,adv7393"; - reg = <0x2a>; - }; - - videoin: adv7180@20 { - compatible = "adi,adv7180"; - reg = <0x20>; - }; }; &iomuxc { diff --git a/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi index 0db15af..f36492c 100644 --- a/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi @@ -143,11 +143,6 @@ #gpio-cells = <2>; }; - hwmon: gsc@29 { - compatible = "gw,gsp"; - reg = <0x29>; - }; - rtc: ds1672@68 { compatible = "dallas,ds1672"; reg = <0x68>; @@ -159,53 +154,6 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c2>; status = "okay"; - - pmic: ltc3676@3c { - compatible = "lltc,ltc3676"; - reg = <0x3c>; - - regulators { - sw1_reg: ltc3676__sw1 { - regulator-min-microvolt = <1175000>; - regulator-max-microvolt = <1175000>; - regulator-boot-on; - regulator-always-on; - }; - - sw2_reg: ltc3676__sw2 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3_reg: ltc3676__sw3 { - regulator-min-microvolt = <1175000>; - regulator-max-microvolt = <1175000>; - regulator-boot-on; - regulator-always-on; - }; - - sw4_reg: ltc3676__sw4 { - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo2_reg: ltc3676__ldo2 { - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo4_reg: ltc3676__ldo4 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - }; - }; }; &i2c3 { @@ -213,11 +161,6 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c3>; status = "okay"; - - videoin: adv7180@20 { - compatible = "adi,adv7180"; - reg = <0x20>; - }; }; &iomuxc { diff --git a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi index 234e7b7..0b65c7d 100644 --- a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi @@ -197,11 +197,6 @@ #gpio-cells = <2>; }; - hwmon: gsc@29 { - compatible = "gw,gsp"; - reg = <0x29>; - }; - rtc: ds1672@68 { compatible = "dallas,ds1672"; reg = <0x68>; @@ -213,65 +208,6 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c2>; status = "okay"; - - pciswitch: pex8609@3f { - compatible = "plx,pex8609"; - reg = <0x3f>; - }; - - pmic: ltc3676@3c { - compatible = "lltc,ltc3676"; - reg = <0x3c>; - - regulators { - sw1_reg: ltc3676__sw1 { - regulator-min-microvolt = <1175000>; - regulator-max-microvolt = <1175000>; - regulator-boot-on; - regulator-always-on; - }; - - sw2_reg: ltc3676__sw2 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3_reg: ltc3676__sw3 { - regulator-min-microvolt = <1175000>; - regulator-max-microvolt = <1175000>; - regulator-boot-on; - regulator-always-on; - }; - - sw4_reg: ltc3676__sw4 { - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo2_reg: ltc3676__ldo2 { - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo3_reg: ltc3676__ldo3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo4_reg: ltc3676__ldo4 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - }; - }; }; &i2c3 { @@ -280,11 +216,6 @@ pinctrl-0 = <&pinctrl_i2c3>; status = "okay"; - accelerometer: fxos8700@1e { - compatible = "fsl,fxos8700"; - reg = <0x13>; - }; - codec: sgtl5000@0a { compatible = "fsl,sgtl5000"; reg = <0x0a>; @@ -300,11 +231,6 @@ interrupts = <12 2>; /* gpio7_12 active low */ wakeup-gpios = <&gpio7 12 0>; }; - - videoin: adv7180@20 { - compatible = "adi,adv7180"; - reg = <0x20>; - }; }; &iomuxc { diff --git a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi index 143f84f..0488cd1 100644 --- a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi @@ -206,11 +206,6 @@ #gpio-cells = <2>; }; - hwmon: gsc@29 { - compatible = "gw,gsp"; - reg = <0x29>; - }; - rtc: ds1672@68 { compatible = "dallas,ds1672"; reg = <0x68>; @@ -222,77 +217,6 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c2>; status = "okay"; - - pciclkgen: si53156@6b { - compatible = "sil,si53156"; - reg = <0x6b>; - }; - - pciswitch: pex8606@3f { - compatible = "plx,pex8606"; - reg = <0x3f>; - }; - - pmic: ltc3676@3c { - compatible = "lltc,ltc3676"; - reg = <0x3c>; - - regulators { - /* VDD_SOC */ - sw1_reg: ltc3676__sw1 { - regulator-min-microvolt = <1175000>; - regulator-max-microvolt = <1175000>; - regulator-boot-on; - regulator-always-on; - }; - - /* VDD_1P8 */ - sw2_reg: ltc3676__sw2 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - /* VDD_ARM */ - sw3_reg: ltc3676__sw3 { - regulator-min-microvolt = <1175000>; - regulator-max-microvolt = <1175000>; - regulator-boot-on; - regulator-always-on; - }; - - /* VDD_DDR */ - sw4_reg: ltc3676__sw4 { - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-boot-on; - regulator-always-on; - }; - - /* VDD_2P5 */ - ldo2_reg: ltc3676__ldo2 { - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-boot-on; - regulator-always-on; - }; - - /* VDD_1P8 */ - ldo3_reg: ltc3676__ldo3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - /* VDD_HIGH */ - ldo4_reg: ltc3676__ldo4 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - }; - }; }; &i2c3 { @@ -301,11 +225,6 @@ pinctrl-0 = <&pinctrl_i2c3>; status = "okay"; - accelerometer: fxos8700@1e { - compatible = "fsl,fxos8700"; - reg = <0x1e>; - }; - codec: sgtl5000@0a { compatible = "fsl,sgtl5000"; reg = <0x0a>; @@ -314,11 +233,6 @@ VDDIO-supply = <®_3p3v>; }; - hdmiin: adv7611@4c { - compatible = "adi,adv7611"; - reg = <0x4c>; - }; - touchscreen: egalax_ts@04 { compatible = "eeti,egalax_ts"; reg = <0x04>; @@ -326,16 +240,6 @@ interrupts = <11 2>; /* gpio1_11 active low */ wakeup-gpios = <&gpio1 11 0>; }; - - videoout: adv7393@2a { - compatible = "adi,adv7393"; - reg = <0x2a>; - }; - - videoin: adv7180@20 { - compatible = "adi,adv7180"; - reg = <0x20>; - }; }; &iomuxc { diff --git a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi index 16e7ad3..620e4cf 100644 --- a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi @@ -196,11 +196,6 @@ #gpio-cells = <2>; }; - hwmon: gsc@29 { - compatible = "gw,gsp"; - reg = <0x29>; - }; - rtc: ds1672@68 { compatible = "dallas,ds1672"; reg = <0x68>; @@ -311,16 +306,6 @@ }; }; }; - - pciswitch: pex8609@3f { - compatible = "plx,pex8609"; - reg = <0x3f>; - }; - - pciclkgen: si52147@6b { - compatible = "sil,si52147"; - reg = <0x6b>; - }; }; &i2c3 { @@ -329,11 +314,6 @@ pinctrl-0 = <&pinctrl_i2c3>; status = "okay"; - accelerometer: fxos8700@1e { - compatible = "fsl,fxos8700"; - reg = <0x1e>; - }; - codec: sgtl5000@0a { compatible = "fsl,sgtl5000"; reg = <0x0a>; @@ -342,11 +322,6 @@ VDDIO-supply = <®_3p3v>; }; - hdmiin: adv7611@4c { - compatible = "adi,adv7611"; - reg = <0x4c>; - }; - touchscreen: egalax_ts@04 { compatible = "eeti,egalax_ts"; reg = <0x04>; @@ -354,16 +329,6 @@ interrupts = <12 2>; /* gpio7_12 active low */ wakeup-gpios = <&gpio7 12 0>; }; - - videoout: adv7393@2a { - compatible = "adi,adv7393"; - reg = <0x2a>; - }; - - videoin: adv7180@20 { - compatible = "adi,adv7180"; - reg = <0x20>; - }; }; &iomuxc { -- cgit v0.10.2 From e32ba7a7dad114d87c4d7411d07af7a26e4119ce Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Mon, 8 Sep 2014 23:07:27 -0700 Subject: ARM: dts: imx: ventana: remove unused aliases Remove aliases that are either not used by bootloader or are provided via included dtsi files. Signed-off-by: Tim Harvey Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/imx6q-gw5400-a.dts b/arch/arm/boot/dts/imx6q-gw5400-a.dts index d1ab780..035f2b1 100644 --- a/arch/arm/boot/dts/imx6q-gw5400-a.dts +++ b/arch/arm/boot/dts/imx6q-gw5400-a.dts @@ -18,7 +18,6 @@ /* these are used by bootloader for disabling nodes */ aliases { - ethernet0 = &fec; ethernet1 = ð1; i2c0 = &i2c1; i2c1 = &i2c2; @@ -26,12 +25,10 @@ led0 = &led0; led1 = &led1; led2 = &led2; - sky2 = ð1; ssi0 = &ssi1; spi0 = &ecspi1; usb0 = &usbh1; usb1 = &usbotg; - usdhc2 = &usdhc3; }; chosen { diff --git a/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi index f36492c..482ef28 100644 --- a/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi @@ -12,8 +12,6 @@ / { /* these are used by bootloader for disabling nodes */ aliases { - can0 = &can1; - ethernet0 = &fec; led0 = &led0; led1 = &led1; nand = &gpmi; diff --git a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi index 0b65c7d..f8c4ab4 100644 --- a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi @@ -12,7 +12,6 @@ / { /* these are used by bootloader for disabling nodes */ aliases { - ethernet0 = &fec; led0 = &led0; led1 = &led1; led2 = &led2; @@ -20,7 +19,6 @@ ssi0 = &ssi1; usb0 = &usbh1; usb1 = &usbotg; - usdhc2 = &usdhc3; }; chosen { diff --git a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi index 0488cd1..01edfd99 100644 --- a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi @@ -12,18 +12,14 @@ / { /* these are used by bootloader for disabling nodes */ aliases { - can0 = &can1; - ethernet0 = &fec; ethernet1 = ð1; led0 = &led0; led1 = &led1; led2 = &led2; nand = &gpmi; - sky2 = ð1; ssi0 = &ssi1; usb0 = &usbh1; usb1 = &usbotg; - usdhc2 = &usdhc3; }; chosen { diff --git a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi index 620e4cf..fab9c7a 100644 --- a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi @@ -12,18 +12,14 @@ / { /* these are used by bootloader for disabling nodes */ aliases { - can0 = &can1; - ethernet0 = &fec; ethernet1 = ð1; led0 = &led0; led1 = &led1; led2 = &led2; nand = &gpmi; - sky2 = ð1; ssi0 = &ssi1; usb0 = &usbh1; usb1 = &usbotg; - usdhc2 = &usdhc3; }; chosen { -- cgit v0.10.2 From 326cdb16552c3670fefd583d94fe797e776130b6 Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Mon, 8 Sep 2014 23:07:28 -0700 Subject: ARM: dts: imx: ventana: use gpio constants Use the gpio contants defined in bindings for active high/low Signed-off-by: Tim Harvey Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/imx6q-gw5400-a.dts b/arch/arm/boot/dts/imx6q-gw5400-a.dts index 035f2b1..9687cd8 100644 --- a/arch/arm/boot/dts/imx6q-gw5400-a.dts +++ b/arch/arm/boot/dts/imx6q-gw5400-a.dts @@ -10,6 +10,7 @@ */ /dts-v1/; +#include #include "imx6q.dtsi" / { @@ -40,20 +41,20 @@ led0: user1 { label = "user1"; - gpios = <&gpio4 6 0>; /* 102 -> MX6_PANLEDG */ + gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* 102 -> MX6_PANLEDG */ default-state = "on"; linux,default-trigger = "heartbeat"; }; led1: user2 { label = "user2"; - gpios = <&gpio4 10 0>; /* 106 -> MX6_PANLEDR */ + gpios = <&gpio4 10 GPIO_ACTIVE_HIGH>; /* 106 -> MX6_PANLEDR */ default-state = "off"; }; led2: user3 { label = "user3"; - gpios = <&gpio4 15 1>; /* 111 -> MX6_LOCLED# */ + gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* 111 -> MX6_LOCLED# */ default-state = "off"; }; }; @@ -64,7 +65,7 @@ pps { compatible = "pps-gpio"; - gpios = <&gpio1 5 0>; + gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; status = "okay"; }; @@ -106,7 +107,7 @@ regulator-name = "usb_otg_vbus"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; - gpio = <&gpio3 22 0>; + gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; enable-active-high; }; }; @@ -134,7 +135,7 @@ &ecspi1 { fsl,spi-num-chipselects = <1>; - cs-gpios = <&gpio3 19 0>; + cs-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi1>; status = "okay"; @@ -150,7 +151,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet>; phy-mode = "rgmii"; - phy-reset-gpios = <&gpio1 30 0>; + phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>; status = "okay"; }; @@ -331,8 +332,8 @@ compatible = "eeti,egalax_ts"; reg = <0x04>; interrupt-parent = <&gpio7>; - interrupts = <12 2>; /* gpio7_12 active low */ - wakeup-gpios = <&gpio7 12 0>; + interrupts = <12 2>; + wakeup-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>; }; }; @@ -462,7 +463,7 @@ }; &pcie { - reset-gpio = <&gpio1 29 0>; + reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>; status = "okay"; eth1: sky2@8 { /* MAC/PHY on bus 8 */ @@ -508,7 +509,7 @@ &usdhc3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc3>; - cd-gpios = <&gpio7 0 0>; + cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; vmmc-supply = <®_3p3v>; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi index 482ef28..fa2cae4 100644 --- a/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi @@ -9,6 +9,8 @@ * http://www.gnu.org/copyleft/gpl.html */ +#include + / { /* these are used by bootloader for disabling nodes */ aliases { @@ -28,14 +30,14 @@ led0: user1 { label = "user1"; - gpios = <&gpio4 6 0>; /* 102 -> MX6_PANLEDG */ + gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */ default-state = "on"; linux,default-trigger = "heartbeat"; }; led1: user2 { label = "user2"; - gpios = <&gpio4 7 0>; /* 103 -> MX6_PANLEDR */ + gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */ default-state = "off"; }; }; @@ -46,7 +48,7 @@ pps { compatible = "pps-gpio"; - gpios = <&gpio1 26 0>; + gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; status = "okay"; }; @@ -79,7 +81,7 @@ regulator-name = "usb_otg_vbus"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; - gpio = <&gpio3 22 0>; + gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; enable-active-high; }; }; @@ -89,7 +91,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet>; phy-mode = "rgmii"; - phy-reset-gpios = <&gpio1 30 0>; + phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; status = "okay"; }; @@ -279,7 +281,7 @@ }; &pcie { - reset-gpio = <&gpio1 0 0>; + reset-gpio = <&gpio1 0 GPIO_ACTIVE_LOW>; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi index f8c4ab4..53f4a0b 100644 --- a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi @@ -9,6 +9,8 @@ * http://www.gnu.org/copyleft/gpl.html */ +#include + / { /* these are used by bootloader for disabling nodes */ aliases { @@ -37,20 +39,20 @@ led0: user1 { label = "user1"; - gpios = <&gpio4 6 0>; /* 102 -> MX6_PANLEDG */ + gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */ default-state = "on"; linux,default-trigger = "heartbeat"; }; led1: user2 { label = "user2"; - gpios = <&gpio4 7 0>; /* 103 -> MX6_PANLEDR */ + gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */ default-state = "off"; }; led2: user3 { label = "user3"; - gpios = <&gpio4 15 1>; /* 111 - MX6_LOCLED# */ + gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */ default-state = "off"; }; }; @@ -61,7 +63,7 @@ pps { compatible = "pps-gpio"; - gpios = <&gpio1 26 0>; + gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; status = "okay"; }; @@ -113,7 +115,7 @@ regulator-name = "usb_otg_vbus"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; - gpio = <&gpio3 22 0>; + gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; enable-active-high; }; }; @@ -143,7 +145,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet>; phy-mode = "rgmii"; - phy-reset-gpios = <&gpio1 30 0>; + phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; status = "okay"; }; @@ -226,8 +228,8 @@ compatible = "eeti,egalax_ts"; reg = <0x04>; interrupt-parent = <&gpio7>; - interrupts = <12 2>; /* gpio7_12 active low */ - wakeup-gpios = <&gpio7 12 0>; + interrupts = <12 2>; + wakeup-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>; }; }; @@ -402,7 +404,7 @@ }; &pcie { - reset-gpio = <&gpio1 29 0>; + reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>; status = "okay"; }; @@ -449,7 +451,7 @@ &usdhc3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc3>; - cd-gpios = <&gpio7 0 0>; + cd-gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>; vmmc-supply = <®_3p3v>; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi index 01edfd99..2074df6 100644 --- a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi @@ -9,6 +9,8 @@ * http://www.gnu.org/copyleft/gpl.html */ +#include + / { /* these are used by bootloader for disabling nodes */ aliases { @@ -38,20 +40,20 @@ led0: user1 { label = "user1"; - gpios = <&gpio4 6 0>; /* 102 -> MX6_PANLEDG */ + gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */ default-state = "on"; linux,default-trigger = "heartbeat"; }; led1: user2 { label = "user2"; - gpios = <&gpio4 7 0>; /* 103 -> MX6_PANLEDR */ + gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */ default-state = "off"; }; led2: user3 { label = "user3"; - gpios = <&gpio4 15 1>; /* 111 -> MX6_LOCLED# */ + gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */ default-state = "off"; }; }; @@ -62,7 +64,7 @@ pps { compatible = "pps-gpio"; - gpios = <&gpio1 26 0>; + gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; status = "okay"; }; @@ -114,7 +116,7 @@ regulator-name = "usb_otg_vbus"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; - gpio = <&gpio3 22 0>; + gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; enable-active-high; }; }; @@ -150,7 +152,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet>; phy-mode = "rgmii"; - phy-reset-gpios = <&gpio1 30 0>; + phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; status = "okay"; }; @@ -233,8 +235,8 @@ compatible = "eeti,egalax_ts"; reg = <0x04>; interrupt-parent = <&gpio1>; - interrupts = <11 2>; /* gpio1_11 active low */ - wakeup-gpios = <&gpio1 11 0>; + interrupts = <11 2>; + wakeup-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; }; }; @@ -418,7 +420,7 @@ }; &pcie { - reset-gpio = <&gpio1 29 0>; + reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>; status = "okay"; eth1: sky2@8 { /* MAC/PHY on bus 8 */ @@ -470,7 +472,7 @@ &usdhc3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc3>; - cd-gpios = <&gpio7 0 0>; + cd-gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>; vmmc-supply = <®_3p3v>; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi index fab9c7a..ab7827a 100644 --- a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi @@ -9,6 +9,8 @@ * http://www.gnu.org/copyleft/gpl.html */ +#include + / { /* these are used by bootloader for disabling nodes */ aliases { @@ -38,20 +40,20 @@ led0: user1 { label = "user1"; - gpios = <&gpio4 6 0>; /* 102 -> MX6_PANLEDG */ + gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */ default-state = "on"; linux,default-trigger = "heartbeat"; }; led1: user2 { label = "user2"; - gpios = <&gpio4 7 0>; /* 103 -> MX6_PANLEDR */ + gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */ default-state = "off"; }; led2: user3 { label = "user3"; - gpios = <&gpio4 15 1>; /* 111 -> MX6_LOCLED# */ + gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */ default-state = "off"; }; }; @@ -62,7 +64,7 @@ pps { compatible = "pps-gpio"; - gpios = <&gpio1 26 0>; + gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; status = "okay"; }; @@ -104,7 +106,7 @@ regulator-name = "usb_otg_vbus"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; - gpio = <&gpio3 22 0>; + gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; enable-active-high; }; }; @@ -140,7 +142,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet>; phy-mode = "rgmii"; - phy-reset-gpios = <&gpio1 30 0>; + phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; status = "okay"; }; @@ -322,8 +324,8 @@ compatible = "eeti,egalax_ts"; reg = <0x04>; interrupt-parent = <&gpio7>; - interrupts = <12 2>; /* gpio7_12 active low */ - wakeup-gpios = <&gpio7 12 0>; + interrupts = <12 2>; + wakeup-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>; }; }; @@ -501,7 +503,7 @@ }; &pcie { - reset-gpio = <&gpio1 29 0>; + reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>; status = "okay"; eth1: sky2@8 { /* MAC/PHY on bus 8 */ @@ -557,7 +559,7 @@ &usdhc3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc3>; - cd-gpios = <&gpio7 0 0>; + cd-gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>; vmmc-supply = <®_3p3v>; status = "okay"; }; -- cgit v0.10.2 From 73e005c111bc3f77ca3793d465539a11e7604c71 Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Mon, 8 Sep 2014 23:07:29 -0700 Subject: ARM: dts: imx: ventana: configure padconf for all pins Follow the convention of configuring padconf for all pins and not leaving any 0x80000000 to leave them un-configured. Signed-off-by: Tim Harvey Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/imx6q-gw5400-a.dts b/arch/arm/boot/dts/imx6q-gw5400-a.dts index 9687cd8..eb28f63 100644 --- a/arch/arm/boot/dts/imx6q-gw5400-a.dts +++ b/arch/arm/boot/dts/imx6q-gw5400-a.dts @@ -344,18 +344,18 @@ imx6q-gw5400-a { pinctrl_hog: hoggrp { fsl,pins = < - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000 /* OTG_PWR_EN */ - MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x80000000 /* SPINOR_CS0# */ - MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x80000000 /* PCIE IRQ */ - MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 /* PCIE RST */ + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x0001b0b0 /* OTG_PWR_EN */ + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x0001b0b0 /* SPINOR_CS0# */ + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x0001b0b0 /* PCIE IRQ */ + MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x0001b0b0 /* PCIE RST */ MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000130b0 /* AUD4_MCK */ - MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x80000000 /* GPS_PPS */ - MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x80000000 /* TOUCH_IRQ# */ - MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x80000000 /* user1 led */ - MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x80000000 /* user2 led */ - MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x80000000 /* user3 led */ - MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x80000000 /* USBHUB_RST# */ - MX6QDL_PAD_SD1_DAT3__GPIO1_IO21 0x80000000 /* MIPI_DIO */ + MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x0001b0b0 /* GPS_PPS */ + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x0001b0b0 /* TOUCH_IRQ# */ + MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x0001b0b0 /* user1 led */ + MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x0001b0b0 /* user2 led */ + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x0001b0b0 /* user3 led */ + MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x4001b0b0 /* USBHUB_RST# */ + MX6QDL_PAD_SD1_DAT3__GPIO1_IO21 0x4001b0b0 /* MIPI_DIO */ >; }; diff --git a/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi index fa2cae4..2853a10 100644 --- a/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi @@ -170,14 +170,14 @@ imx6qdl-gw51xx { pinctrl_hog: hoggrp { fsl,pins = < - MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x80000000 /* MEZZ_DIO0 */ - MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x80000000 /* MEZZ_DIO1 */ - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000 /* OTG_PWR_EN */ - MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x80000000 /* GPS_PPS */ - MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x80000000 /* PHY Reset */ - MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x80000000 /* PCIE_RST# */ - MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x80000000 /* user1 led */ - MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x80000000 /* user2 led */ + MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x4001b0b0 /* MEZZ_DIO0 */ + MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x4001b0b0 /* MEZZ_DIO1 */ + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x0001b0b0 /* OTG_PWR_EN */ + MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x0001b0b0 /* GPS_PPS */ + MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x0001b0b0 /* PHY Reset */ + MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x0001b0b0 /* PCIE_RST# */ + MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x0001b0b0 /* user1 led */ + MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x0001b0b0 /* user2 led */ >; }; diff --git a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi index 53f4a0b..26b1395 100644 --- a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi @@ -240,23 +240,23 @@ imx6qdl-gw52xx { pinctrl_hog: hoggrp { fsl,pins = < - MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x80000000 /* MEZZ_DIO0 */ - MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x80000000 /* MEZZ_DIO1 */ - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000 /* OTG_PWR_EN */ - MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x80000000 /* VIDDEC_PDN# */ - MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x80000000 /* PHY Reset */ - MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 /* PCIE_RST# */ - MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x80000000 /* GPS_PWDN */ - MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x80000000 /* GPS_PPS */ + MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x4001b0b0 /* MEZZ_DIO0 */ + MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x4001b0b0 /* MEZZ_DIO1 */ + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x0001b0b0 /* OTG_PWR_EN */ + MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x0001b0b0 /* VIDDEC_PDN# */ + MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x0001b0b0 /* PHY Reset */ + MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x0001b0b0 /* PCIE_RST# */ + MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x4001b0b0 /* GPS_PWDN */ + MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x0001b0b0 /* GPS_PPS */ MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000130b0 /* AUD4_MCK */ - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 /* USB_SEL_PCI */ - MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x80000000 /* TOUCH_IRQ# */ - MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x80000000 /* user1 led */ - MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x80000000 /* user2 led */ - MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x80000000 /* user3 led */ - MX6QDL_PAD_SD2_CMD__GPIO1_IO11 0x80000000 /* LVDS_TCH# */ - MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x80000000 /* SD3_CD# */ - MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x80000000 /* UART2_EN# */ + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x4001b0b0 /* USB_SEL_PCI */ + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x0001b0b0 /* TOUCH_IRQ# */ + MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x0001b0b0 /* user1 led */ + MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x0001b0b0 /* user2 led */ + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x0001b0b0 /* user3 led */ + MX6QDL_PAD_SD2_CMD__GPIO1_IO11 0x0001b0b0 /* LVDS_TCH# */ + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x0001b0b0 /* SD3_CD# */ + MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x4001b0b0 /* UART2_EN# */ >; }; diff --git a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi index 2074df6..e6e298b 100644 --- a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi @@ -247,25 +247,25 @@ imx6qdl-gw53xx { pinctrl_hog: hoggrp { fsl,pins = < - MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x80000000 /* PCIE6EXP_DIO0 */ - MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x80000000 /* PCIE6EXP_DIO1 */ - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000 /* OTG_PWR_EN */ - MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x80000000 /* GPS_SHDN */ - MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x80000000 /* GPS_PPS */ - MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x80000000 /* PCIE IRQ */ - MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 /* PCIE RST */ + MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x4001b0b0 /* PCIE6EXP_DIO0 */ + MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x4001b0b0 /* PCIE6EXP_DIO1 */ + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x0001b0b0 /* OTG_PWR_EN */ + MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x4001b0b0 /* GPS_SHDN */ + MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x0001b0b0 /* GPS_PPS */ + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x0001b0b0 /* PCIE IRQ */ + MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x0001b0b0 /* PCIE RST */ MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000130b0 /* AUD4_MCK */ - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 /* CAN_STBY */ - MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x80000000 /* PMIC_IRQ# */ - MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x80000000 /* HUB_RST# */ - MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x80000000 /* PCIE_WDIS# */ - MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x80000000 /* ACCEL_IRQ# */ - MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x80000000 /* user1 led */ - MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x80000000 /* USBOTG_OC# */ - MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x80000000 /* user2 led */ - MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x80000000 /* user3 led */ - MX6QDL_PAD_SD2_CMD__GPIO1_IO11 0x80000000 /* TOUCH_IRQ# */ - MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x80000000 /* SD3_DET# */ + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x4001b0b0 /* CAN_STBY */ + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */ + MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x4001b0b0 /* HUB_RST# */ + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x4001b0b0 /* PCIE_WDIS# */ + MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x0001b0b0 /* ACCEL_IRQ# */ + MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x0001b0b0 /* user1 led */ + MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x0001b0b0 /* USBOTG_OC# */ + MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x0001b0b0 /* user2 led */ + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x0001b0b0 /* user3 led */ + MX6QDL_PAD_SD2_CMD__GPIO1_IO11 0x0001b0b0 /* TOUCH_IRQ# */ + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x0001b0b0 /* SD3_DET# */ >; }; @@ -301,8 +301,8 @@ pinctrl_flexcan1: flexcan1grp { fsl,pins = < - MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000 - MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x80000000 + MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1 + MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1 >; }; diff --git a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi index ab7827a..a366a93 100644 --- a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi @@ -336,19 +336,19 @@ imx6qdl-gw54xx { pinctrl_hog: hoggrp { fsl,pins = < - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000 /* OTG_PWR_EN */ - MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x80000000 /* SPINOR_CS0# */ - MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x80000000 /* GPS_PPS */ - MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x80000000 /* PCIE IRQ */ - MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 /* PCIE RST */ + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x0001b0b0 /* OTG_PWR_EN */ + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x0001b0b0 /* SPINOR_CS0# */ + MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x0001b0b0 /* GPS_PPS */ + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x0001b0b0 /* PCIE IRQ */ + MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x0001b0b0 /* PCIE RST */ MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000130b0 /* AUD4_MCK */ - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 /* CAN_STBY */ - MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x80000000 /* TOUCH_IRQ# */ - MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x80000000 /* user1 led */ - MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x80000000 /* user2 led */ - MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x80000000 /* user3 led */ - MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x80000000 /* USBHUB_RST# */ - MX6QDL_PAD_SD1_DAT3__GPIO1_IO21 0x80000000 /* MIPI_DIO */ + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x4001b0b0 /* CAN_STBY */ + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x0001b0b0 /* TOUCH_IRQ# */ + MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x0001b0b0 /* user1 led */ + MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x0001b0b0 /* user2 led */ + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x0001b0b0 /* user3 led */ + MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x4001b0b0 /* USBHUB_RST# */ + MX6QDL_PAD_SD1_DAT3__GPIO1_IO21 0x4001b0b0 /* MIPI_DIO */ >; }; @@ -384,8 +384,8 @@ pinctrl_flexcan1: flexcan1grp { fsl,pins = < - MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000 - MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x80000000 + MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1 + MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1 >; }; -- cgit v0.10.2 From b5f37b76053afe8863ce9a753903932eb542eca9 Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Mon, 8 Sep 2014 23:07:30 -0700 Subject: ARM: dts: imx: ventana: cleanup pinctrl groups Follow the conventions for pinctrl: - grouping pinctrl in logical alphabatized groups - remove any pinctrl not being used by a driver or needed by user - move iomuxc to bottom of file for readability Signed-off-by: Tim Harvey Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/imx6q-gw5400-a.dts b/arch/arm/boot/dts/imx6q-gw5400-a.dts index eb28f63..822ffb2 100644 --- a/arch/arm/boot/dts/imx6q-gw5400-a.dts +++ b/arch/arm/boot/dts/imx6q-gw5400-a.dts @@ -38,6 +38,8 @@ leds { compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; led0: user1 { label = "user1"; @@ -65,6 +67,8 @@ pps { compatible = "pps-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; status = "okay"; }; @@ -337,27 +341,64 @@ }; }; -&iomuxc { +&ldb { + status = "okay"; +}; + +&pcie { + reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>; + status = "okay"; + + eth1: sky2@8 { /* MAC/PHY on bus 8 */ + compatible = "marvell,sky2"; + }; +}; + +&ssi1 { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + status = "okay"; +}; + +&usbh1 { + vbus-supply = <®_usb_h1_vbus>; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_3p3v>; + status = "okay"; +}; + +&iomuxc { imx6q-gw5400-a { - pinctrl_hog: hoggrp { - fsl,pins = < - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x0001b0b0 /* OTG_PWR_EN */ - MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x0001b0b0 /* SPINOR_CS0# */ - MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x0001b0b0 /* PCIE IRQ */ - MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x0001b0b0 /* PCIE RST */ - MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000130b0 /* AUD4_MCK */ - MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x0001b0b0 /* GPS_PPS */ - MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x0001b0b0 /* TOUCH_IRQ# */ - MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x0001b0b0 /* user1 led */ - MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x0001b0b0 /* user2 led */ - MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x0001b0b0 /* user3 led */ - MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x4001b0b0 /* USBHUB_RST# */ - MX6QDL_PAD_SD1_DAT3__GPIO1_IO21 0x4001b0b0 /* MIPI_DIO */ - >; - }; pinctrl_audmux: audmuxgrp { fsl,pins = < @@ -365,6 +406,7 @@ MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0 MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0 MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0 + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */ >; }; @@ -373,6 +415,7 @@ MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x1b0b0 /* SPINOR_CS0# */ >; }; @@ -397,6 +440,14 @@ >; }; + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 /* user1 led */ + MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 /* user2 led */ + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 /* user3 led */ + >; + }; + pinctrl_i2c1: i2c1grp { fsl,pins = < MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 @@ -418,6 +469,19 @@ >; }; + pinctrl_pcie: pciegrp { + fsl,pins = < + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 /* PCIE IRQ */ + MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* PCIE RST */ + >; + }; + + pinctrl_pps: ppsgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b0 /* GPS_PPS */ + >; + }; + pinctrl_uart1: uart1grp { fsl,pins = < MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 @@ -442,6 +506,7 @@ pinctrl_usbotg: usbotggrp { fsl,pins = < MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* OTG_PWR_EN */ >; }; @@ -457,59 +522,3 @@ }; }; }; - -&ldb { - status = "okay"; -}; - -&pcie { - reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>; - status = "okay"; - - eth1: sky2@8 { /* MAC/PHY on bus 8 */ - compatible = "marvell,sky2"; - }; -}; - -&ssi1 { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&uart5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart5>; - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_usb_otg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - disable-over-current; - status = "okay"; -}; - -&usbh1 { - vbus-supply = <®_usb_h1_vbus>; - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; - cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; - vmmc-supply = <®_3p3v>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi index 2853a10..f2867c4 100644 --- a/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi @@ -27,6 +27,8 @@ leds { compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; led0: user1 { label = "user1"; @@ -48,6 +50,8 @@ pps { compatible = "pps-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pps>; gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; status = "okay"; }; @@ -163,24 +167,51 @@ status = "okay"; }; -&iomuxc { +&pcie { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; + pinctrl-0 = <&pinctrl_pcie>; + reset-gpio = <&gpio1 0 GPIO_ACTIVE_LOW>; + status = "okay"; +}; - imx6qdl-gw51xx { - pinctrl_hog: hoggrp { - fsl,pins = < - MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x4001b0b0 /* MEZZ_DIO0 */ - MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x4001b0b0 /* MEZZ_DIO1 */ - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x0001b0b0 /* OTG_PWR_EN */ - MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x0001b0b0 /* GPS_PPS */ - MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x0001b0b0 /* PHY Reset */ - MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x0001b0b0 /* PCIE_RST# */ - MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x0001b0b0 /* user1 led */ - MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x0001b0b0 /* user2 led */ - >; - }; +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + status = "okay"; +}; + +&usbh1 { + status = "okay"; +}; + +&iomuxc { + imx6qdl-gw51xx { pinctrl_enet: enetgrp { fsl,pins = < MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 @@ -199,6 +230,14 @@ MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 + MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 /* PHY Reset */ + >; + }; + + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 + MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 >; }; @@ -244,6 +283,18 @@ >; }; + pinctrl_pcie: pciegrp { + fsl,pins = < + MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 + >; + }; + + pinctrl_pps: ppsgrp { + fsl,pins = < + MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1 + >; + }; + pinctrl_uart1: uart1grp { fsl,pins = < MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 @@ -275,48 +326,8 @@ pinctrl_usbotg: usbotggrp { fsl,pins = < MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* OTG_PWR_EN */ >; }; }; }; - -&pcie { - reset-gpio = <&gpio1 0 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - status = "okay"; -}; - -&uart5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart5>; - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_usb_otg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - disable-over-current; - status = "okay"; -}; - -&usbh1 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi index 26b1395..6d137b4 100644 --- a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi @@ -36,6 +36,8 @@ leds { compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; led0: user1 { label = "user1"; @@ -63,6 +65,8 @@ pps { compatible = "pps-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pps>; gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; status = "okay"; }; @@ -233,39 +237,96 @@ }; }; -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; +&ldb { + status = "okay"; - imx6qdl-gw52xx { - pinctrl_hog: hoggrp { - fsl,pins = < - MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x4001b0b0 /* MEZZ_DIO0 */ - MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x4001b0b0 /* MEZZ_DIO1 */ - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x0001b0b0 /* OTG_PWR_EN */ - MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x0001b0b0 /* VIDDEC_PDN# */ - MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x0001b0b0 /* PHY Reset */ - MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x0001b0b0 /* PCIE_RST# */ - MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x4001b0b0 /* GPS_PWDN */ - MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x0001b0b0 /* GPS_PPS */ - MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000130b0 /* AUD4_MCK */ - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x4001b0b0 /* USB_SEL_PCI */ - MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x0001b0b0 /* TOUCH_IRQ# */ - MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x0001b0b0 /* user1 led */ - MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x0001b0b0 /* user2 led */ - MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x0001b0b0 /* user3 led */ - MX6QDL_PAD_SD2_CMD__GPIO1_IO11 0x0001b0b0 /* LVDS_TCH# */ - MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x0001b0b0 /* SD3_CD# */ - MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x4001b0b0 /* UART2_EN# */ - >; + lvds-channel@0 { + fsl,data-mapping = "spwg"; + fsl,data-width = <18>; + status = "okay"; + + display-timings { + native-mode = <&timing0>; + timing0: hsd100pxn1 { + clock-frequency = <65000000>; + hactive = <1024>; + vactive = <768>; + hback-porch = <220>; + hfront-porch = <40>; + vback-porch = <21>; + vfront-porch = <7>; + hsync-len = <60>; + vsync-len = <10>; + }; }; + }; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; + status = "okay"; +}; + +&ssi1 { + fsl,mode = "i2s-slave"; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + status = "okay"; +}; + +&usbh1 { + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + cd-gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>; + vmmc-supply = <®_3p3v>; + status = "okay"; +}; + +&iomuxc { + imx6qdl-gw52xx { pinctrl_audmux: audmuxgrp { fsl,pins = < MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0 MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0 MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0 MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0 + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */ >; }; @@ -287,6 +348,15 @@ MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 + MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 /* PHY Reset */ + >; + }; + + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 + MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 >; }; @@ -332,6 +402,18 @@ >; }; + pinctrl_pcie: pciegrp { + fsl,pins = < + MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* PCIE_RST# */ + >; + }; + + pinctrl_pps: ppsgrp { + fsl,pins = < + MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1 + >; + }; + pinctrl_pwm4: pwm4grp { fsl,pins = < MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 @@ -362,6 +444,7 @@ pinctrl_usbotg: usbotggrp { fsl,pins = < MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* OTG_PWR_EN */ >; }; @@ -373,85 +456,8 @@ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 /* CD */ >; }; }; }; - -&ldb { - status = "okay"; - - lvds-channel@0 { - fsl,data-mapping = "spwg"; - fsl,data-width = <18>; - status = "okay"; - - display-timings { - native-mode = <&timing0>; - timing0: hsd100pxn1 { - clock-frequency = <65000000>; - hactive = <1024>; - vactive = <768>; - hback-porch = <220>; - hfront-porch = <40>; - vback-porch = <21>; - vfront-porch = <7>; - hsync-len = <60>; - vsync-len = <10>; - }; - }; - }; -}; - -&pcie { - reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&pwm4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm4>; - status = "okay"; -}; - -&ssi1 { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&uart5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart5>; - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_usb_otg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - disable-over-current; - status = "okay"; -}; - -&usbh1 { - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; - cd-gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>; - vmmc-supply = <®_3p3v>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi index e6e298b..cade1bd 100644 --- a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi @@ -37,6 +37,8 @@ leds { compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; led0: user1 { label = "user1"; @@ -64,6 +66,8 @@ pps { compatible = "pps-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pps>; gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; status = "okay"; }; @@ -240,41 +244,101 @@ }; }; -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; +&ldb { + status = "okay"; - imx6qdl-gw53xx { - pinctrl_hog: hoggrp { - fsl,pins = < - MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x4001b0b0 /* PCIE6EXP_DIO0 */ - MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x4001b0b0 /* PCIE6EXP_DIO1 */ - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x0001b0b0 /* OTG_PWR_EN */ - MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x4001b0b0 /* GPS_SHDN */ - MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x0001b0b0 /* GPS_PPS */ - MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x0001b0b0 /* PCIE IRQ */ - MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x0001b0b0 /* PCIE RST */ - MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000130b0 /* AUD4_MCK */ - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x4001b0b0 /* CAN_STBY */ - MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */ - MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x4001b0b0 /* HUB_RST# */ - MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x4001b0b0 /* PCIE_WDIS# */ - MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x0001b0b0 /* ACCEL_IRQ# */ - MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x0001b0b0 /* user1 led */ - MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x0001b0b0 /* USBOTG_OC# */ - MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x0001b0b0 /* user2 led */ - MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x0001b0b0 /* user3 led */ - MX6QDL_PAD_SD2_CMD__GPIO1_IO11 0x0001b0b0 /* TOUCH_IRQ# */ - MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x0001b0b0 /* SD3_DET# */ - >; + lvds-channel@1 { + fsl,data-mapping = "spwg"; + fsl,data-width = <18>; + status = "okay"; + + display-timings { + native-mode = <&timing0>; + timing0: hsd100pxn1 { + clock-frequency = <65000000>; + hactive = <1024>; + vactive = <768>; + hback-porch = <220>; + hfront-porch = <40>; + vback-porch = <21>; + vfront-porch = <7>; + hsync-len = <60>; + vsync-len = <10>; + }; }; + }; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>; + status = "okay"; + + eth1: sky2@8 { /* MAC/PHY on bus 8 */ + compatible = "marvell,sky2"; + }; +}; + +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; + status = "okay"; +}; + +&ssi1 { + fsl,mode = "i2s-slave"; + status = "okay"; +}; +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + status = "okay"; +}; + +&usbh1 { + vbus-supply = <®_usb_h1_vbus>; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + cd-gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>; + vmmc-supply = <®_3p3v>; + status = "okay"; +}; + +&iomuxc { + imx6qdl-gw53xx { pinctrl_audmux: audmuxgrp { fsl,pins = < MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0 MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0 MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0 MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0 + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */ >; }; @@ -303,6 +367,15 @@ fsl,pins = < MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1 + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x4001b0b0 /* CAN_STBY */ + >; + }; + + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 + MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 >; }; @@ -348,6 +421,19 @@ >; }; + pinctrl_pcie: pciegrp { + fsl,pins = < + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 /* PCIE IRQ */ + MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* PCIE RST */ + >; + }; + + pinctrl_pps: ppsgrp { + fsl,pins = < + MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1 + >; + }; + pinctrl_pwm4: pwm4grp { fsl,pins = < MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 @@ -378,6 +464,8 @@ pinctrl_usbotg: usbotggrp { fsl,pins = < MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* PWR_EN */ + MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0 /* OC */ >; }; @@ -389,90 +477,8 @@ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 /* CD */ >; }; }; }; - -&ldb { - status = "okay"; - - lvds-channel@1 { - fsl,data-mapping = "spwg"; - fsl,data-width = <18>; - status = "okay"; - - display-timings { - native-mode = <&timing0>; - timing0: hsd100pxn1 { - clock-frequency = <65000000>; - hactive = <1024>; - vactive = <768>; - hback-porch = <220>; - hfront-porch = <40>; - vback-porch = <21>; - vfront-porch = <7>; - hsync-len = <60>; - vsync-len = <10>; - }; - }; - }; -}; - -&pcie { - reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>; - status = "okay"; - - eth1: sky2@8 { /* MAC/PHY on bus 8 */ - compatible = "marvell,sky2"; - }; -}; - -&pwm4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm4>; - status = "okay"; -}; - -&ssi1 { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&uart5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart5>; - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_usb_otg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - disable-over-current; - status = "okay"; -}; - -&usbh1 { - vbus-supply = <®_usb_h1_vbus>; - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; - cd-gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>; - vmmc-supply = <®_3p3v>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi index a366a93..cf13239 100644 --- a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi @@ -37,6 +37,8 @@ leds { compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; led0: user1 { label = "user1"; @@ -64,6 +66,8 @@ pps { compatible = "pps-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pps>; gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; status = "okay"; }; @@ -329,35 +333,106 @@ }; }; -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; +&ldb { + status = "okay"; - imx6qdl-gw54xx { - pinctrl_hog: hoggrp { - fsl,pins = < - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x0001b0b0 /* OTG_PWR_EN */ - MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x0001b0b0 /* SPINOR_CS0# */ - MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x0001b0b0 /* GPS_PPS */ - MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x0001b0b0 /* PCIE IRQ */ - MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x0001b0b0 /* PCIE RST */ - MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000130b0 /* AUD4_MCK */ - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x4001b0b0 /* CAN_STBY */ - MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x0001b0b0 /* TOUCH_IRQ# */ - MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x0001b0b0 /* user1 led */ - MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x0001b0b0 /* user2 led */ - MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x0001b0b0 /* user3 led */ - MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x4001b0b0 /* USBHUB_RST# */ - MX6QDL_PAD_SD1_DAT3__GPIO1_IO21 0x4001b0b0 /* MIPI_DIO */ - >; + lvds-channel@1 { + fsl,data-mapping = "spwg"; + fsl,data-width = <18>; + status = "okay"; + + display-timings { + native-mode = <&timing0>; + timing0: hsd100pxn1 { + clock-frequency = <65000000>; + hactive = <1024>; + vactive = <768>; + hback-porch = <220>; + hfront-porch = <40>; + vback-porch = <21>; + vfront-porch = <7>; + hsync-len = <60>; + vsync-len = <10>; + }; }; + }; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>; + status = "okay"; + + eth1: sky2@8 { /* MAC/PHY on bus 8 */ + compatible = "marvell,sky2"; + }; +}; +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; + status = "okay"; +}; + +&ssi1 { + fsl,mode = "i2s-slave"; + status = "okay"; +}; + +&ssi2 { + fsl,mode = "i2s-slave"; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + status = "okay"; +}; + +&usbh1 { + vbus-supply = <®_usb_h1_vbus>; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + cd-gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>; + vmmc-supply = <®_3p3v>; + status = "okay"; +}; + +&iomuxc { + imx6qdl-gw54xx { pinctrl_audmux: audmuxgrp { fsl,pins = < MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0 MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0 MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0 MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0 + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */ >; }; @@ -386,6 +461,15 @@ fsl,pins = < MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1 + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x4001b0b0 /* CAN_STBY */ + >; + }; + + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 + MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 >; }; @@ -431,6 +515,19 @@ >; }; + pinctrl_pcie: pciegrp { + fsl,pins = < + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 /* PCIE IRQ */ + MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* PCIE RST */ + >; + }; + + pinctrl_pps: ppsgrp { + fsl,pins = < + MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1 + >; + }; + pinctrl_pwm4: pwm4grp { fsl,pins = < MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 @@ -461,6 +558,7 @@ pinctrl_usbotg: usbotggrp { fsl,pins = < MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* PWR_EN */ >; }; @@ -476,90 +574,3 @@ }; }; }; - -&ldb { - status = "okay"; - - lvds-channel@1 { - fsl,data-mapping = "spwg"; - fsl,data-width = <18>; - status = "okay"; - - display-timings { - native-mode = <&timing0>; - timing0: hsd100pxn1 { - clock-frequency = <65000000>; - hactive = <1024>; - vactive = <768>; - hback-porch = <220>; - hfront-porch = <40>; - vback-porch = <21>; - vfront-porch = <7>; - hsync-len = <60>; - vsync-len = <10>; - }; - }; - }; -}; - -&pcie { - reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>; - status = "okay"; - - eth1: sky2@8 { /* MAC/PHY on bus 8 */ - compatible = "marvell,sky2"; - }; -}; - -&pwm4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm4>; - status = "okay"; -}; - -&ssi1 { - status = "okay"; -}; - -&ssi2 { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&uart5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart5>; - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_usb_otg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - disable-over-current; - status = "okay"; -}; - -&usbh1 { - vbus-supply = <®_usb_h1_vbus>; - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; - cd-gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>; - vmmc-supply = <®_3p3v>; - status = "okay"; -}; -- cgit v0.10.2 From 7cab35c3643d9ad3b34eaf8501ab5292b6d41fcf Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Mon, 8 Sep 2014 23:07:31 -0700 Subject: ARM: dts: imx: ventana: add canbus support for GW52xx The GW52xx baseboard supports CANbus so we enable it, configure its pinmux and CAN_STBY gpio. Signed-off-by: Tim Harvey Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi index 6d137b4..d3c0bf5 100644 --- a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi @@ -145,6 +145,12 @@ status = "okay"; }; +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + status = "okay"; +}; + &fec { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet>; @@ -352,6 +358,14 @@ >; }; + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1 + MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1 + MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x4001b0b0 /* CAN_STBY */ + >; + }; + pinctrl_gpio_leds: gpioledsgrp { fsl,pins = < MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 -- cgit v0.10.2 From 2b2244a3e7c3d537f436a3580999b3032628d17d Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Thu, 11 Sep 2014 11:29:41 +0800 Subject: ARM: dts: imx6: make gpt per clock can be from OSC Original gpt per clk parent is from ipg_per clk which may be scaled when system enter low bus mode, as ipg clk will be lower in low bus mode, to keep system clk NOT drift, select gpt per clk parent from OSC which is at fixed freq always. On i.mx6qdl, add a osc_per clk source for i.mx6q TO > 1.0 and all i.MX6dl SoC. On i.mx6sx, just make gpt per clk from OSC. Signed-off-by: Anson Huang Signed-off-by: Shawn Guo diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi index 0de8806..9596ed5 100644 --- a/arch/arm/boot/dts/imx6qdl.dtsi +++ b/arch/arm/boot/dts/imx6qdl.dtsi @@ -407,8 +407,9 @@ reg = <0x02098000 0x4000>; interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6QDL_CLK_GPT_IPG>, - <&clks IMX6QDL_CLK_GPT_IPG_PER>; - clock-names = "ipg", "per"; + <&clks IMX6QDL_CLK_GPT_IPG_PER>, + <&clks IMX6QDL_CLK_GPT_3M>; + clock-names = "ipg", "per", "osc_per"; }; gpio1: gpio@0209c000 { diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi index d137caca..888dd76 100644 --- a/arch/arm/boot/dts/imx6sx.dtsi +++ b/arch/arm/boot/dts/imx6sx.dtsi @@ -421,7 +421,7 @@ reg = <0x02098000 0x4000>; interrupts = ; clocks = <&clks IMX6SX_CLK_GPT_BUS>, - <&clks IMX6SX_CLK_GPT_SERIAL>; + <&clks IMX6SX_CLK_GPT_3M>; clock-names = "ipg", "per"; }; -- cgit v0.10.2 From de8b6054780e464038676baf399c816e239dd9b3 Mon Sep 17 00:00:00 2001 From: Zhangfei Gao Date: Tue, 19 Aug 2014 11:00:33 +0800 Subject: ARM: dts: hix5hd2: add gmac node Signed-off-by: Zhangfei Gao Signed-off-by: Wei Xu diff --git a/arch/arm/boot/dts/hisi-x5hd2-dkb.dts b/arch/arm/boot/dts/hisi-x5hd2-dkb.dts index 05b44c2..0da3f3b 100644 --- a/arch/arm/boot/dts/hisi-x5hd2-dkb.dts +++ b/arch/arm/boot/dts/hisi-x5hd2-dkb.dts @@ -51,3 +51,31 @@ &uart0 { status = "okay"; }; + +&gmac0 { + #address-cells = <1>; + #size-cells = <0>; + phy-handle = <&phy2>; + phy-mode = "mii"; + /* Placeholder, overwritten by bootloader */ + mac-address = [00 00 00 00 00 00]; + status = "okay"; + + phy2: ethernet-phy@2 { + reg = <2>; + }; +}; + +&gmac1 { + #address-cells = <1>; + #size-cells = <0>; + phy-handle = <&phy1>; + phy-mode = "rgmii"; + /* Placeholder, overwritten by bootloader */ + mac-address = [00 00 00 00 00 00]; + status = "okay"; + + phy1: ethernet-phy@1 { + reg = <1>; + }; +}; diff --git a/arch/arm/boot/dts/hisi-x5hd2.dtsi b/arch/arm/boot/dts/hisi-x5hd2.dtsi index f85ba29..012525c 100644 --- a/arch/arm/boot/dts/hisi-x5hd2.dtsi +++ b/arch/arm/boot/dts/hisi-x5hd2.dtsi @@ -166,5 +166,21 @@ #clock-cells = <1>; }; }; + + gmac0: ethernet@1840000 { + compatible = "hisilicon,hix5hd2-gmac"; + reg = <0x1840000 0x1000>,<0x184300c 0x4>; + interrupts = <0 71 4>; + clocks = <&clock HIX5HD2_MAC0_CLK>; + status = "disabled"; + }; + + gmac1: ethernet@1841000 { + compatible = "hisilicon,hix5hd2-gmac"; + reg = <0x1841000 0x1000>,<0x1843010 0x4>; + interrupts = <0 72 4>; + clocks = <&clock HIX5HD2_MAC1_CLK>; + status = "disabled"; + }; }; }; -- cgit v0.10.2 From b196e1ca400dca770ac22d158741cf646207a6e2 Mon Sep 17 00:00:00 2001 From: Zhangfei Gao Date: Wed, 20 Aug 2014 14:37:48 +0800 Subject: ARM: dts: hix5hd2: add mmc node Signed-off-by: Zhangfei Gao Signed-off-by: Wei Xu diff --git a/arch/arm/boot/dts/hisi-x5hd2.dtsi b/arch/arm/boot/dts/hisi-x5hd2.dtsi index 012525c..802331b 100644 --- a/arch/arm/boot/dts/hisi-x5hd2.dtsi +++ b/arch/arm/boot/dts/hisi-x5hd2.dtsi @@ -167,6 +167,23 @@ }; }; + /* unremovable emmc as mmcblk0 */ + mmc: mmc@1830000 { + compatible = "snps,dw-mshc"; + reg = <0x1830000 0x1000>; + interrupts = <0 35 4>; + clocks = <&clock HIX5HD2_MMC_CIU_RST>, <&clock HIX5HD2_MMC_BIU_CLK>; + clock-names = "ciu", "biu"; + }; + + sd: mmc@1820000 { + compatible = "snps,dw-mshc"; + reg = <0x1820000 0x1000>; + interrupts = <0 34 4>; + clocks = <&clock HIX5HD2_SD_CIU_RST>, <&clock HIX5HD2_SD_BIU_CLK>; + clock-names = "ciu","biu"; + }; + gmac0: ethernet@1840000 { compatible = "hisilicon,hix5hd2-gmac"; reg = <0x1840000 0x1000>,<0x184300c 0x4>; -- cgit v0.10.2 From f16c7fb2f3ff258322850ac6f558d3b61ceb5a2b Mon Sep 17 00:00:00 2001 From: Zhangfei Gao Date: Wed, 20 Aug 2014 14:57:44 +0800 Subject: ARM: dts: hix5hd2: add usb node Signed-off-by: Zhangfei Gao Signed-off-by: Jiancheng Xue Signed-off-by: Wei Xu diff --git a/arch/arm/boot/dts/hisi-x5hd2.dtsi b/arch/arm/boot/dts/hisi-x5hd2.dtsi index 802331b..9252264 100644 --- a/arch/arm/boot/dts/hisi-x5hd2.dtsi +++ b/arch/arm/boot/dts/hisi-x5hd2.dtsi @@ -199,5 +199,19 @@ clocks = <&clock HIX5HD2_MAC1_CLK>; status = "disabled"; }; + + usb0: ehci@1890000 { + compatible = "generic-ehci"; + reg = <0x1890000 0x1000>; + interrupts = <0 66 4>; + clocks = <&clock HIX5HD2_USB_CLK>; + }; + + usb1: ohci@1880000 { + compatible = "generic-ohci"; + reg = <0x1880000 0x1000>; + interrupts = <0 67 4>; + clocks = <&clock HIX5HD2_USB_CLK>; + }; }; }; -- cgit v0.10.2 From 420a2d55f0464a4b4762411ca7047979d9ad17eb Mon Sep 17 00:00:00 2001 From: Zhangfei Gao Date: Wed, 20 Aug 2014 15:14:39 +0800 Subject: ARM: dts: hix5hd2: add sata node Signed-off-by: Jiancheng Xue Signed-off-by: Zhangfei Gao Signed-off-by: Wei Xu diff --git a/arch/arm/boot/dts/hisi-x5hd2-dkb.dts b/arch/arm/boot/dts/hisi-x5hd2-dkb.dts index 0da3f3b..375a10c 100644 --- a/arch/arm/boot/dts/hisi-x5hd2-dkb.dts +++ b/arch/arm/boot/dts/hisi-x5hd2-dkb.dts @@ -79,3 +79,8 @@ reg = <1>; }; }; + +&ahci { + phys = <&sata_phy>; + phy-names = "sata-phy"; +}; diff --git a/arch/arm/boot/dts/hisi-x5hd2.dtsi b/arch/arm/boot/dts/hisi-x5hd2.dtsi index 9252264..18f52f0 100644 --- a/arch/arm/boot/dts/hisi-x5hd2.dtsi +++ b/arch/arm/boot/dts/hisi-x5hd2.dtsi @@ -213,5 +213,25 @@ interrupts = <0 67 4>; clocks = <&clock HIX5HD2_USB_CLK>; }; + + peripheral_ctrl: syscon@a20000 { + compatible = "syscon"; + reg = <0xa20000 0x1000>; + }; + + sata_phy: phy@1900000 { + compatible = "hisilicon,hix5hd2-sata-phy"; + reg = <0x1900000 0x10000>; + #phy-cells = <0>; + hisilicon,peripheral-syscon = <&peripheral_ctrl>; + hisilicon,power-reg = <0x8 10>; + }; + + ahci: sata@1900000 { + compatible = "hisilicon,hisi-ahci"; + reg = <0x1900000 0x10000>; + interrupts = <0 70 4>; + clocks = <&clock HIX5HD2_SATA_CLK>; + }; }; }; -- cgit v0.10.2 From 6868feb6dd97ec1b273cca95e8dec9471f1d9f23 Mon Sep 17 00:00:00 2001 From: Zhangfei Gao Date: Wed, 20 Aug 2014 15:36:37 +0800 Subject: ARM: dts: hix5hd2: add gpio node Signed-off-by: Jiancheng Xue Signed-off-by: Zhangfei Gao Signed-off-by: Wei Xu diff --git a/arch/arm/boot/dts/hisi-x5hd2.dtsi b/arch/arm/boot/dts/hisi-x5hd2.dtsi index 18f52f0..152f3ad 100644 --- a/arch/arm/boot/dts/hisi-x5hd2.dtsi +++ b/arch/arm/boot/dts/hisi-x5hd2.dtsi @@ -131,6 +131,240 @@ clock-names = "apb_pclk"; status = "disabled"; }; + + gpio0: gpio@b20000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0xb20000 0x1000>; + interrupts = <0 108 0x4>; + gpio-controller; + #gpio-cells = <2>; + clocks = <&clock HIX5HD2_FIXED_100M>; + clock-names = "apb_pclk"; + interrupt-controller; + #interrupt-cells = <2>; + status = "disabled"; + }; + + gpio1: gpio@b21000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0xb21000 0x1000>; + interrupts = <0 109 0x4>; + gpio-controller; + #gpio-cells = <2>; + clocks = <&clock HIX5HD2_FIXED_100M>; + clock-names = "apb_pclk"; + interrupt-controller; + #interrupt-cells = <2>; + status = "disabled"; + }; + + gpio2: gpio@b22000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0xb22000 0x1000>; + interrupts = <0 110 0x4>; + gpio-controller; + #gpio-cells = <2>; + clocks = <&clock HIX5HD2_FIXED_100M>; + clock-names = "apb_pclk"; + interrupt-controller; + #interrupt-cells = <2>; + status = "disabled"; + }; + + gpio3: gpio@b23000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0xb23000 0x1000>; + interrupts = <0 111 0x4>; + gpio-controller; + #gpio-cells = <2>; + clocks = <&clock HIX5HD2_FIXED_100M>; + clock-names = "apb_pclk"; + interrupt-controller; + #interrupt-cells = <2>; + status = "disabled"; + }; + + gpio4: gpio@b24000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0xb24000 0x1000>; + interrupts = <0 112 0x4>; + gpio-controller; + #gpio-cells = <2>; + clocks = <&clock HIX5HD2_FIXED_100M>; + clock-names = "apb_pclk"; + interrupt-controller; + #interrupt-cells = <2>; + status = "disabled"; + }; + + gpio5: gpio@004000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x004000 0x1000>; + interrupts = <0 113 0x4>; + gpio-controller; + #gpio-cells = <2>; + clocks = <&clock HIX5HD2_FIXED_100M>; + clock-names = "apb_pclk"; + interrupt-controller; + #interrupt-cells = <2>; + status = "disabled"; + }; + + gpio6: gpio@b26000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0xb26000 0x1000>; + interrupts = <0 114 0x4>; + gpio-controller; + #gpio-cells = <2>; + clocks = <&clock HIX5HD2_FIXED_100M>; + clock-names = "apb_pclk"; + interrupt-controller; + #interrupt-cells = <2>; + status = "disabled"; + }; + + gpio7: gpio@b27000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0xb27000 0x1000>; + interrupts = <0 115 0x4>; + gpio-controller; + #gpio-cells = <2>; + clocks = <&clock HIX5HD2_FIXED_100M>; + clock-names = "apb_pclk"; + interrupt-controller; + #interrupt-cells = <2>; + status = "disabled"; + }; + + gpio8: gpio@b28000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0xb28000 0x1000>; + interrupts = <0 116 0x4>; + gpio-controller; + #gpio-cells = <2>; + clocks = <&clock HIX5HD2_FIXED_100M>; + clock-names = "apb_pclk"; + interrupt-controller; + #interrupt-cells = <2>; + status = "disabled"; + }; + + gpio9: gpio@b29000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0xb29000 0x1000>; + interrupts = <0 117 0x4>; + gpio-controller; + #gpio-cells = <2>; + clocks = <&clock HIX5HD2_FIXED_100M>; + clock-names = "apb_pclk"; + interrupt-controller; + #interrupt-cells = <2>; + status = "disabled"; + }; + + gpio10: gpio@b2a000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0xb2a000 0x1000>; + interrupts = <0 118 0x4>; + gpio-controller; + #gpio-cells = <2>; + clocks = <&clock HIX5HD2_FIXED_100M>; + clock-names = "apb_pclk"; + interrupt-controller; + #interrupt-cells = <2>; + status = "disabled"; + }; + + gpio11: gpio@b2b000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0xb2b000 0x1000>; + interrupts = <0 119 0x4>; + gpio-controller; + #gpio-cells = <2>; + clocks = <&clock HIX5HD2_FIXED_100M>; + clock-names = "apb_pclk"; + interrupt-controller; + #interrupt-cells = <2>; + status = "disabled"; + }; + + gpio12: gpio@b2c000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0xb2c000 0x1000>; + interrupts = <0 120 0x4>; + gpio-controller; + #gpio-cells = <2>; + clocks = <&clock HIX5HD2_FIXED_100M>; + clock-names = "apb_pclk"; + interrupt-controller; + #interrupt-cells = <2>; + status = "disabled"; + }; + + gpio13: gpio@b2d000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0xb2d000 0x1000>; + interrupts = <0 121 0x4>; + gpio-controller; + #gpio-cells = <2>; + clocks = <&clock HIX5HD2_FIXED_100M>; + clock-names = "apb_pclk"; + interrupt-controller; + #interrupt-cells = <2>; + status = "disabled"; + }; + + gpio14: gpio@b2e000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0xb2e000 0x1000>; + interrupts = <0 122 0x4>; + gpio-controller; + #gpio-cells = <2>; + clocks = <&clock HIX5HD2_FIXED_100M>; + clock-names = "apb_pclk"; + interrupt-controller; + #interrupt-cells = <2>; + status = "disabled"; + }; + + gpio15: gpio@b2f000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0xb2f000 0x1000>; + interrupts = <0 123 0x4>; + gpio-controller; + #gpio-cells = <2>; + clocks = <&clock HIX5HD2_FIXED_100M>; + clock-names = "apb_pclk"; + interrupt-controller; + #interrupt-cells = <2>; + status = "disabled"; + }; + + gpio16: gpio@b30000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0xb30000 0x1000>; + interrupts = <0 124 0x4>; + gpio-controller; + #gpio-cells = <2>; + clocks = <&clock HIX5HD2_FIXED_100M>; + clock-names = "apb_pclk"; + interrupt-controller; + #interrupt-cells = <2>; + status = "disabled"; + }; + + gpio17: gpio@b31000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0xb31000 0x1000>; + interrupts = <0 125 0x4>; + gpio-controller; + #gpio-cells = <2>; + clocks = <&clock HIX5HD2_FIXED_100M>; + clock-names = "apb_pclk"; + interrupt-controller; + #interrupt-cells = <2>; + status = "disabled"; + }; }; local_timer@00a00600 { -- cgit v0.10.2 From 610bd8722ef40b649b51f01045c5d1903f41b583 Mon Sep 17 00:00:00 2001 From: Zhangfei Gao Date: Wed, 20 Aug 2014 15:38:26 +0800 Subject: ARM: dts: hix5hd2: add wdg node Signed-off-by: Jiancheng Xue Signed-off-by: Zhangfei Gao Signed-off-by: Wei Xu diff --git a/arch/arm/boot/dts/hisi-x5hd2.dtsi b/arch/arm/boot/dts/hisi-x5hd2.dtsi index 152f3ad..b3a87d7 100644 --- a/arch/arm/boot/dts/hisi-x5hd2.dtsi +++ b/arch/arm/boot/dts/hisi-x5hd2.dtsi @@ -365,6 +365,15 @@ #interrupt-cells = <2>; status = "disabled"; }; + + wdt0: watchdog@a2c000 { + compatible = "arm,sp805", "arm,primecell"; + arm,primecell-periphid = <0x00141805>; + reg = <0xa2c000 0x1000>; + interrupts = <0 29 4>; + clocks = <&clock HIX5HD2_WDG0_RST>; + clock-names = "apb_pclk"; + }; }; local_timer@00a00600 { -- cgit v0.10.2 From f62f40475137c905d8e4bcbe9870b4d7e4fed91f Mon Sep 17 00:00:00 2001 From: Soren Brinkmann Date: Wed, 20 Aug 2014 08:56:59 -0700 Subject: ARM: zynq: DT: Add Ethernet phys Add missing Ethernet phys to Zynq DTs. Signed-off-by: Soren Brinkmann Signed-off-by: Michal Simek diff --git a/arch/arm/boot/dts/zynq-zc702.dts b/arch/arm/boot/dts/zynq-zc702.dts index 8eab484..94e2cda 100644 --- a/arch/arm/boot/dts/zynq-zc702.dts +++ b/arch/arm/boot/dts/zynq-zc702.dts @@ -45,6 +45,11 @@ &gem0 { status = "okay"; phy-mode = "rgmii-id"; + phy-handle = <ðernet_phy>; + + ethernet_phy: ethernet-phy@7 { + reg = <7>; + }; }; &i2c0 { diff --git a/arch/arm/boot/dts/zynq-zc706.dts b/arch/arm/boot/dts/zynq-zc706.dts index 88f732f..a8bbdfb 100644 --- a/arch/arm/boot/dts/zynq-zc706.dts +++ b/arch/arm/boot/dts/zynq-zc706.dts @@ -32,6 +32,11 @@ &gem0 { status = "okay"; phy-mode = "rgmii-id"; + phy-handle = <ðernet_phy>; + + ethernet_phy: ethernet-phy@7 { + reg = <7>; + }; }; &i2c0 { diff --git a/arch/arm/boot/dts/zynq-zed.dts b/arch/arm/boot/dts/zynq-zed.dts index 2b2dc4d..697779a 100644 --- a/arch/arm/boot/dts/zynq-zed.dts +++ b/arch/arm/boot/dts/zynq-zed.dts @@ -32,6 +32,11 @@ &gem0 { status = "okay"; phy-mode = "rgmii-id"; + phy-handle = <ðernet_phy>; + + ethernet_phy: ethernet-phy@0 { + reg = <0>; + }; }; &sdhci0 { -- cgit v0.10.2 From 6f752f70a3a344af53d0e8100c2f7c15074b0651 Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Sat, 6 Sep 2014 12:40:16 +0100 Subject: ARM: zynq: Add ISL9305 regulator on Parallella board There is an ISL9305 regulator on the Parallella board, add it to the DT along with descriptions of all the supplies. Signed-off-by: Mark Brown Signed-off-by: Michal Simek diff --git a/arch/arm/boot/dts/zynq-parallella.dts b/arch/arm/boot/dts/zynq-parallella.dts index aadde02..e1f51ca 100644 --- a/arch/arm/boot/dts/zynq-parallella.dts +++ b/arch/arm/boot/dts/zynq-parallella.dts @@ -51,6 +51,29 @@ &i2c0 { status = "okay"; + + isl9305: isl9305@68 { + compatible = "isl,isl9305"; + reg = <0x68>; + + regulators { + dcd1 { + regulator-name = "VDD_DSP"; + regulator-always-on; + }; + dcd2 { + regulator-name = "1P35V"; + regulator-always-on; + }; + ldo1 { + regulator-name = "VDD_ADJ"; + }; + ldo2 { + regulator-name = "VDD_GPIO"; + regulator-always-on; + }; + }; + }; }; &sdhci1 { -- cgit v0.10.2 From 66fa6cf29fc67ecbc42efd632c2310688530e441 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Tue, 16 Sep 2014 18:53:10 +0200 Subject: ARM: dts: rockchip: fix swapped Radxa Rock pinctrl references The host and otg regulator pinctrl settings got swapped, making the host reference the otg pinctrl and the other way round. The actual pins are correct (gpio0-3 for host and gpio2-31 for otg). Reported-by: Naoki FUKAUMI Signed-off-by: Heiko Stuebner diff --git a/arch/arm/boot/dts/rk3188-radxarock.dts b/arch/arm/boot/dts/rk3188-radxarock.dts index 1be0c34..c08744d 100644 --- a/arch/arm/boot/dts/rk3188-radxarock.dts +++ b/arch/arm/boot/dts/rk3188-radxarock.dts @@ -70,7 +70,7 @@ enable-active-high; gpio = <&gpio2 31 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; - pinctrl-0 = <&host_vbus_drv>; + pinctrl-0 = <&otg_vbus_drv>; regulator-name = "otg-vbus"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; @@ -93,7 +93,7 @@ enable-active-high; gpio = <&gpio0 3 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; - pinctrl-0 = <&otg_vbus_drv>; + pinctrl-0 = <&host_vbus_drv>; regulator-name = "host-pwr"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; -- cgit v0.10.2 From bee1cef6011c308352c4d428922449953ffb257b Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Tue, 16 Sep 2014 18:59:36 +0200 Subject: ARM: dts: rockchip: fix rk3188 emmc pull references Fix a copy'n'paste error making the rk3188 emmc pinctrl nodes reference the pcfg_pull_default setting that is not available on rk3188. Reported-by: Naoki FUKAUMI Signed-off-by: Heiko Stuebner diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi index 9a1ff0b..82732f5 100644 --- a/arch/arm/boot/dts/rk3188.dtsi +++ b/arch/arm/boot/dts/rk3188.dtsi @@ -149,15 +149,15 @@ emmc { emmc_clk: emmc-clk { - rockchip,pins = ; + rockchip,pins = ; }; emmc_cmd: emmc-cmd { - rockchip,pins = ; + rockchip,pins = ; }; emmc_rst: emmc-rst { - rockchip,pins = ; + rockchip,pins = ; }; /* -- cgit v0.10.2 From 08adafd4a1f8c9b6e2c49d955a0e45743c9ffd9a Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 16 Sep 2014 21:57:16 +0200 Subject: ARM: shmobile: Add manufacturer for KZM boards KZM-A9-Dual and KZM-A9-GT are manufactured by Kyoto Microcomputer Co. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt b/Documentation/devicetree/bindings/arm/shmobile.txt index 5d1c5c0..51147cb 100644 --- a/Documentation/devicetree/bindings/arm/shmobile.txt +++ b/Documentation/devicetree/bindings/arm/shmobile.txt @@ -53,11 +53,11 @@ Boards: compatible = "renesas,henninger", "renesas,r8a7791" - Koelsch (RTP0RC7791SEB00010S) compatible = "renesas,koelsch", "renesas,r8a7791" - - KZM9D + - Kyoto Microcomputer Co. KZM-A9-Dual compatible = "renesas,kzm9d", "renesas,emev2" - - KZM-A9-GT + - Kyoto Microcomputer Co. KZM-A9-GT compatible = "renesas,kzm9g", "renesas,sh73a0" - - KZM-A9-GT - Reference Device Tree Implementation + - Kyoto Microcomputer Co. KZM-A9-GT - Reference Device Tree Implementation compatible = "renesas,kzm9g-reference", "renesas,sh73a0" - Lager (RTP0RC7790SEB00010S) compatible = "renesas,lager", "renesas,r8a7790" -- cgit v0.10.2 From feb60beacd036400a9e1afe762892c08b4811ded Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 16 Sep 2014 21:37:57 +0200 Subject: Documentation: arm: add hardware datasheet reference for Marvell Armada XP Some time ago, the "Function Specifications" for the Marvell Armada XP processor has been released. However, the "Hardware Specifications" were not released at the same time. They have now been released publicly, so this commit updates the Marvell documentation file with the references to this new documentation. Three documents are available, one for each of the three variants of Armada XP: 78230, 78260 and 78460. Signed-off-by: Thomas Petazzoni Link: https://lkml.kernel.org/r/1410896277-32476-1-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper diff --git a/Documentation/arm/Marvell/README b/Documentation/arm/Marvell/README index 4dc66c1..1745379 100644 --- a/Documentation/arm/Marvell/README +++ b/Documentation/arm/Marvell/README @@ -103,6 +103,10 @@ EBU Armada family NOTE: not to be confused with the non-SMP 78xx0 SoCs Product Brief: http://www.marvell.com/embedded-processors/armada-xp/assets/Marvell-ArmadaXP-SoC-product%20brief.pdf Functional Spec: http://www.marvell.com/embedded-processors/armada-xp/assets/ARMADA-XP-Functional-SpecDatasheet.pdf + Hardware Specs: + http://www.marvell.com/embedded-processors/armada-xp/assets/HW_MV78230_OS.PDF + http://www.marvell.com/embedded-processors/armada-xp/assets/HW_MV78260_OS.PDF + http://www.marvell.com/embedded-processors/armada-xp/assets/HW_MV78460_OS.PDF Core: Sheeva ARMv7 compatible -- cgit v0.10.2 From 32c741d07f7fdb1974eb07420fc143d479bfe19f Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Wed, 17 Sep 2014 15:45:39 +0200 Subject: ARM: mvebu: switch the Armada 370 RD board to internal registers at 0xf1000000 Recent bootloader versions from Marvell that have DT support and various other new features remap the internal registers at 0xf1000000. We have already done this change for most of the development boards from Marvell, and this commit does this change for the Marvell Armada 370 RD board. Signed-off-by: Thomas Petazzoni Link: https://lkml.kernel.org/r/1410961539-10388-1-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper diff --git a/arch/arm/boot/dts/armada-370-rd.dts b/arch/arm/boot/dts/armada-370-rd.dts index 14c66e4..f57a8f84 100644 --- a/arch/arm/boot/dts/armada-370-rd.dts +++ b/arch/arm/boot/dts/armada-370-rd.dts @@ -9,6 +9,15 @@ * This file is licensed under the terms of the GNU General Public * License version 2. This program is licensed "as is" without any * warranty of any kind, whether express or implied. + * + * Note: this Device Tree assumes that the bootloader has remapped the + * internal registers to 0xf1000000 (instead of the default + * 0xd0000000). The 0xf1000000 is the default used by the recent, + * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier + * boards were delivered with an older version of the bootloader that + * left internal registers mapped at 0xd0000000. If you are in this + * situation, you should either update your bootloader (preferred + * solution) or the below Device Tree should be adjusted. */ /dts-v1/; @@ -30,7 +39,7 @@ }; soc { - ranges = ; pcie-controller { -- cgit v0.10.2 From a5a68f7509b86bf08a18ed6e4af9226ca5be1634 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Wed, 17 Sep 2014 00:04:45 +0800 Subject: ARM: dts: sunxi: Add fixed 5V regulator Most if not all boards we've seen have a fixed 5V regulator, which is the main power supply and/or fixed output of the PMIC. Add this one to the common regulators DTSI. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard diff --git a/arch/arm/boot/dts/sunxi-common-regulators.dtsi b/arch/arm/boot/dts/sunxi-common-regulators.dtsi index 3d021ef..c9c5b10 100644 --- a/arch/arm/boot/dts/sunxi-common-regulators.dtsi +++ b/arch/arm/boot/dts/sunxi-common-regulators.dtsi @@ -86,4 +86,11 @@ regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; + + reg_vcc5v0: vcc5v0 { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; }; -- cgit v0.10.2 From 6717f3d1286c5bb9b73a7a97f1e71333b72d82f9 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Wed, 17 Sep 2014 00:04:46 +0800 Subject: ARM: dts: sun5i: Add DT for HSG H702 tablet board This is a Q8 format 7 inch tablet with an Allwinner A13 SoC. It has 512MB DRAM, 4GB NAND flash, an accelerometer, camera, RTL8188-based WiFi, and micro SD slot for external storage. It is likely made by a subsidiary of Hanns.G (Hannstar). Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index ecb55a3..2f42b18 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -406,6 +406,7 @@ dtb-$(CONFIG_MACH_SUN4I) += \ dtb-$(CONFIG_MACH_SUN5I) += \ sun5i-a10s-olinuxino-micro.dtb \ sun5i-a10s-r7-tv-dongle.dtb \ + sun5i-a13-hsg-h702.dtb \ sun5i-a13-olinuxino.dtb \ sun5i-a13-olinuxino-micro.dtb dtb-$(CONFIG_MACH_SUN6I) += \ diff --git a/arch/arm/boot/dts/sun5i-a13-hsg-h702.dts b/arch/arm/boot/dts/sun5i-a13-hsg-h702.dts new file mode 100644 index 0000000..8b3cd090 --- /dev/null +++ b/arch/arm/boot/dts/sun5i-a13-hsg-h702.dts @@ -0,0 +1,130 @@ +/* + * Copyright 2014 Chen-Yu Tsai + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this library; if not, write to the Free + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +/include/ "sun5i-a13.dtsi" +/include/ "sunxi-common-regulators.dtsi" + +/ { + model = "HSG H702"; + compatible = "hsg,h702", "allwinner,sun5i-a13"; + + soc@01c00000 { + mmc0: mmc@01c0f000 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_h702>; + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 6 0 0>; /* PG0 */ + cd-inverted; + status = "okay"; + }; + + usbphy: phy@01c13400 { + /* + * There doesn't seem to be a GPIO for controlling + * usb1 vbus, despite the fex file saying otherwise. + */ + usb1_vbus-supply = <®_vcc5v0>; + status = "okay"; + }; + + ehci0: usb@01c14000 { + status = "okay"; + }; + + ohci0: usb@01c14400 { + status = "okay"; + }; + + pinctrl@01c20800 { + mmc0_cd_pin_h702: mmc0_cd_pin@0 { + allwinner,pins = "PG0"; + allwinner,function = "gpio_in"; + allwinner,drive = <0>; + allwinner,pull = <1>; + }; + }; + + uart1: serial@01c28400 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins_b>; + status = "okay"; + }; + + i2c0: i2c@01c2ac00 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "okay"; + + axp209: pmic@34 { + compatible = "x-powers,axp209"; + reg = <0x34>; + interrupts = <0>; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + i2c1: i2c@01c2b000 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins_a>; + status = "okay"; + + pcf8563: rtc@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; + }; + + i2c2: i2c@01c2b400 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins_a>; + status = "okay"; + }; + }; +}; -- cgit v0.10.2 From ee588e2a30269d0572fc9ebdd7527f9711d6366d Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Wed, 17 Sep 2014 10:02:44 -0600 Subject: ARM: tegra: add PCIe to Tegra124 DT Add the PCIe controller device tree node and hook up the PCIe PHY from the XUSB pad controller. Signed-off-by: Thierry Reding Signed-off-by: Stephen Warren diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index 0ba3a0b..478c555 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -12,6 +12,72 @@ #address-cells = <2>; #size-cells = <2>; + pcie-controller@0,01003000 { + compatible = "nvidia,tegra124-pcie"; + device_type = "pci"; + reg = <0x0 0x01003000 0x0 0x00000800 /* PADS registers */ + 0x0 0x01003800 0x0 0x00000800 /* AFI registers */ + 0x0 0x02000000 0x0 0x10000000>; /* configuration space */ + reg-names = "pads", "afi", "cs"; + interrupts = , /* controller interrupt */ + ; /* MSI interrupt */ + interrupt-names = "intr", "msi"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; + + bus-range = <0x00 0xff>; + #address-cells = <3>; + #size-cells = <2>; + + ranges = <0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000 /* port 0 configuration space */ + 0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000 /* port 1 configuration space */ + 0x81000000 0 0x0 0x0 0x12000000 0 0x00010000 /* downstream I/O (64 KiB) */ + 0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000 /* non-prefetchable memory (208 MiB) */ + 0xc2000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */ + + clocks = <&tegra_car TEGRA124_CLK_PCIE>, + <&tegra_car TEGRA124_CLK_AFI>, + <&tegra_car TEGRA124_CLK_PLL_E>, + <&tegra_car TEGRA124_CLK_CML0>; + clock-names = "pex", "afi", "pll_e", "cml"; + resets = <&tegra_car 70>, + <&tegra_car 72>, + <&tegra_car 74>; + reset-names = "pex", "afi", "pcie_x"; + status = "disabled"; + + phys = <&padctl TEGRA_XUSB_PADCTL_PCIE>; + phy-names = "pcie"; + + pci@1,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>; + reg = <0x000800 0 0 0 0>; + status = "disabled"; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + + nvidia,num-lanes = <2>; + }; + + pci@2,0 { + device_type = "pci"; + assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>; + reg = <0x001000 0 0 0 0>; + status = "disabled"; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + + nvidia,num-lanes = <1>; + }; + }; + host1x@0,50000000 { compatible = "nvidia,tegra124-host1x", "simple-bus"; reg = <0x0 0x50000000 0x0 0x00034000>; -- cgit v0.10.2 From 8e2b9e4df655f3708fb8b712f0e66e6ea700995e Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Wed, 17 Sep 2014 10:02:45 -0600 Subject: ARM: tegra: enable PCIe in Jetson TK1 DT Enable both PCIe ports, one of which is connected to an onboard ethernet chip, whereas the other goes to a miniPCIe slot. Signed-off-by: Thierry Reding [swarren, fixed PCIe supply property names in DT] Signed-off-by: Stephen Warren diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1.dts b/arch/arm/boot/dts/tegra124-jetson-tk1.dts index 64828c2..029c9a02 100644 --- a/arch/arm/boot/dts/tegra124-jetson-tk1.dts +++ b/arch/arm/boot/dts/tegra124-jetson-tk1.dts @@ -16,6 +16,26 @@ reg = <0x0 0x80000000 0x0 0x80000000>; }; + pcie-controller@0,01003000 { + status = "okay"; + + avddio-pex-supply = <&vdd_1v05_run>; + dvddio-pex-supply = <&vdd_1v05_run>; + avdd-pex-pll-supply = <&vdd_1v05_run>; + hvdd-pex-supply = <&vdd_3v3_lp0>; + hvdd-pex-pll-e-supply = <&vdd_3v3_lp0>; + vddio-pex-ctl-supply = <&vdd_3v3_lp0>; + avdd-pll-erefe-supply = <&avdd_1v05_run>; + + pci@1,0 { + status = "okay"; + }; + + pci@2,0 { + status = "okay"; + }; + }; + host1x@0,50000000 { hdmi@0,54280000 { status = "okay"; @@ -1550,7 +1570,7 @@ regulator-always-on; }; - ldo0 { + avdd_1v05_run: ldo0 { regulator-name = "+1.05V_RUN_AVDD"; regulator-min-microvolt = <1050000>; regulator-max-microvolt = <1050000>; -- cgit v0.10.2 From bf7f6b0432871cb68f3e3f4961a33cc6be05bc75 Mon Sep 17 00:00:00 2001 From: "kiran.padwal@smartplayin.com" Date: Tue, 16 Sep 2014 17:15:38 +0530 Subject: ARM: dts: qcom: Add I2C dt node for MSM8974 and DB8074 board Add support for i2c controller on the DB8074 board. It also adds necessary DT support for i2c eeprom which is present on DB8074 board. Signed-off-by: Kiran Padwal Signed-off-by: Kumar Gala diff --git a/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts b/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts index b4dfb01..4737049 100644 --- a/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts +++ b/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts @@ -22,6 +22,13 @@ pinctrl@fd510000 { + i2c11_pins: i2c11 { + mux { + pins = "gpio83", "gpio84"; + function = "blsp_i2c11"; + }; + }; + spi8_default: spi8_default { mosi { pins = "gpio45"; @@ -41,5 +48,19 @@ }; }; }; + + i2c@f9967000 { + status = "okay"; + clock-frequency = <200000>; + pinctrl-0 = <&i2c11_pins>; + pinctrl-names = "default"; + + eeprom: eeprom@52 { + compatible = "atmel,24c128"; + reg = <0x52>; + pagesize = <32>; + read-only; + }; + }; }; }; diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index 69dca2a..e265ec1 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -1,8 +1,8 @@ /dts-v1/; -#include "skeleton.dtsi" - +#include #include +#include "skeleton.dtsi" / { model = "Qualcomm MSM8974"; @@ -236,5 +236,16 @@ #interrupt-cells = <2>; interrupts = <0 208 0>; }; + + blsp_i2c11: i2c@f9967000 { + status = "disable"; + compatible = "qcom,i2c-qup-v2.1.1"; + reg = <0xf9967000 0x1000>; + interrupts = <0 105 IRQ_TYPE_NONE>; + clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; + clock-names = "core", "iface"; + #address-cells = <1>; + #size-cells = <0>; + }; }; }; -- cgit v0.10.2 From 0be5fef161151b8841d3e3d33d815695384a9451 Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Wed, 17 Sep 2014 06:39:35 +0100 Subject: ARM: DT: apq8064: add support to sdcc4 for wlan. This patch adds sdcc4 node to enable wlan support on IFC6410 Signed-off-by: Srinivas Kandagatla Signed-off-by: Kumar Gala diff --git a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts index 90db8af..27c7dfe 100644 --- a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts +++ b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts @@ -23,6 +23,10 @@ sdcc3: sdcc@12180000 { status = "okay"; }; + /* WLAN */ + sdcc4: sdcc@121c0000 { + status = "okay"; + }; }; }; }; diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index b1e476a..f31d20b 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -85,6 +85,13 @@ pinctrl-names = "default"; pinctrl-0 = <&ps_hold>; + sdc4_gpios: sdc4-gpios { + pios { + pins = "gpio63", "gpio64", "gpio65", "gpio66", "gpio67", "gpio68"; + function = "sdc4"; + }; + }; + ps_hold: ps_hold { mux { pins = "gpio78"; @@ -226,6 +233,16 @@ qcom,ee = <0>; }; + sdcc4bam:dma@121c2000{ + compatible = "qcom,bam-v1.3.0"; + reg = <0x121c2000 0x8000>; + interrupts = <0 95 0>; + clocks = <&gcc SDC4_H_CLK>; + clock-names = "bam_clk"; + #dma-cells = <1>; + qcom,ee = <0>; + }; + amba { compatible = "arm,amba-bus"; #address-cells = <1>; @@ -268,6 +285,27 @@ dmas = <&sdcc3bam 2>, <&sdcc3bam 1>; dma-names = "tx", "rx"; }; + + sdcc4: sdcc@121c0000 { + compatible = "arm,pl18x", "arm,primecell"; + arm,primecell-periphid = <0x00051180>; + status = "disabled"; + reg = <0x121c0000 0x2000>; + interrupts = ; + interrupt-names = "cmd_irq"; + clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>; + clock-names = "mclk", "apb_pclk"; + bus-width = <4>; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency = <48000000>; + vmmc-supply = <&vsdcc_fixed>; + vqmmc-supply = <&vsdcc_fixed>; + dmas = <&sdcc4bam 2>, <&sdcc4bam 1>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&sdc4_gpios>; + }; }; }; }; -- cgit v0.10.2 From 8c3166f5d74b7936d29dc44f778e759c1b9fb43a Mon Sep 17 00:00:00 2001 From: "kiran.padwal@smartplayin.com" Date: Wed, 17 Sep 2014 16:00:25 +0530 Subject: ARM: DT: apq8064: Add i2c device nodes This patch adds i2c pinctrl DT node for IFC6410 board. It also adds necessary DT support for i2c eeprom which is present on IFC6410. Signed-off-by: Kiran Padwal Signed-off-by: Kumar Gala diff --git a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts index 27c7dfe..b396c83 100644 --- a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts +++ b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts @@ -5,6 +5,33 @@ compatible = "qcom,apq8064-ifc6410", "qcom,apq8064"; soc { + pinctrl@800000 { + i2c1_pins: i2c1 { + mux { + pins = "gpio20", "gpio21"; + function = "gsbi1"; + }; + }; + }; + + gsbi@12440000 { + status = "okay"; + qcom,mode = ; + + i2c@12460000 { + status = "okay"; + clock-frequency = <200000>; + pinctrl-0 = <&i2c1_pins>; + pinctrl-names = "default"; + + eeprom: eeprom@52 { + compatible = "atmel,24c128"; + reg = <0x52>; + pagesize = <32>; + }; + }; + }; + gsbi@16600000 { status = "ok"; qcom,mode = ; diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index f31d20b..b3154c0 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -163,6 +163,48 @@ regulator; }; + gsbi1: gsbi@12440000 { + status = "disabled"; + compatible = "qcom,gsbi-v1.0.0"; + reg = <0x12440000 0x100>; + clocks = <&gcc GSBI1_H_CLK>; + clock-names = "iface"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + i2c1: i2c@12460000 { + compatible = "qcom,i2c-qup-v1.1.1"; + reg = <0x12460000 0x1000>; + interrupts = <0 194 IRQ_TYPE_NONE>; + clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>; + clock-names = "core", "iface"; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + gsbi2: gsbi@12480000 { + status = "disabled"; + compatible = "qcom,gsbi-v1.0.0"; + reg = <0x12480000 0x100>; + clocks = <&gcc GSBI2_H_CLK>; + clock-names = "iface"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + i2c2: i2c@124a0000 { + compatible = "qcom,i2c-qup-v1.1.1"; + reg = <0x124a0000 0x1000>; + interrupts = <0 196 IRQ_TYPE_NONE>; + clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>; + clock-names = "core", "iface"; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + gsbi7: gsbi@16600000 { status = "disabled"; compatible = "qcom,gsbi-v1.0.0"; -- cgit v0.10.2 From fe855dbfd3fde8fd3093e51992904e3c875a4a02 Mon Sep 17 00:00:00 2001 From: Bo Shen Date: Thu, 18 Sep 2014 14:56:43 +0200 Subject: ARM: at91: sama5d3xek: reserve dma channel for audio We set the DMA configuration on USARTs in the SoC DT in (ARM: at91: sama5d3: add usart dma configurations). As the audio must work with DMA channels, we reserve some dma channels for audio, or else audio won't work. Signed-off-by: Bo Shen [nicolas.ferre@atmel.com: move to the sama5d3xmb.dtsi to cover all board variants] Signed-off-by: Nicolas Ferre diff --git a/arch/arm/boot/dts/sama5d3xmb.dtsi b/arch/arm/boot/dts/sama5d3xmb.dtsi index b8c6f20..49c10d3 100644 --- a/arch/arm/boot/dts/sama5d3xmb.dtsi +++ b/arch/arm/boot/dts/sama5d3xmb.dtsi @@ -25,6 +25,8 @@ }; spi0: spi@f0004000 { + dmas = <0>, <0>; /* Do not use DMA for spi0 */ + m25p80@0 { compatible = "atmel,at25df321a"; spi-max-frequency = <50000000>; @@ -51,6 +53,7 @@ }; usart1: serial@f0020000 { + dmas = <0>, <0>; /* Do not use DMA for usart1 */ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart1 &pinctrl_usart1_rts_cts>; status = "okay"; @@ -132,6 +135,7 @@ }; dbgu: serial@ffffee00 { + dmas = <0>, <0>; /* Do not use DMA for dbgu */ status = "okay"; }; -- cgit v0.10.2 From 496d3c2898cedf66530e057e68b54ffe5055154c Mon Sep 17 00:00:00 2001 From: Bo Shen Date: Wed, 11 Jun 2014 18:14:41 +0800 Subject: ARM: at91/dt: at91sam9rl: switch ssc compatible string As the SSC integrate in at91sam9rl support frame sync length extension, so switch compatible string to support this feature. Signed-off-by: Bo Shen Signed-off-by: Nicolas Ferre diff --git a/arch/arm/boot/dts/at91sam9rl.dtsi b/arch/arm/boot/dts/at91sam9rl.dtsi index ab56c8b..f0b4352 100644 --- a/arch/arm/boot/dts/at91sam9rl.dtsi +++ b/arch/arm/boot/dts/at91sam9rl.dtsi @@ -204,7 +204,7 @@ }; ssc0: ssc@fffc0000 { - compatible = "atmel,at91rm9200-ssc"; + compatible = "atmel,at91sam9rl-ssc"; reg = <0xfffc0000 0x4000>; interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; @@ -213,7 +213,7 @@ }; ssc1: ssc@fffc4000 { - compatible = "atmel,at91rm9200-ssc"; + compatible = "atmel,at91sam9rl-ssc"; reg = <0xfffc4000 0x4000>; interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; -- cgit v0.10.2 From 9bd277300fd81d69c335fc6a48d1b802dac4c7c3 Mon Sep 17 00:00:00 2001 From: Bo Shen Date: Wed, 11 Jun 2014 18:14:42 +0800 Subject: ARM: at91/dt: at91sam9g20: switch ssc compatible string As the SSC integrate in at91sam9g20 support frame sync length extension, so switch compatible string to support this feature. Signed-off-by: Bo Shen Signed-off-by: Nicolas Ferre diff --git a/arch/arm/boot/dts/at91sam9g20.dtsi b/arch/arm/boot/dts/at91sam9g20.dtsi index 31f7652..5734dc1 100644 --- a/arch/arm/boot/dts/at91sam9g20.dtsi +++ b/arch/arm/boot/dts/at91sam9g20.dtsi @@ -22,6 +22,10 @@ compatible = "atmel,at91sam9g20-i2c"; }; + ssc0: ssc@fffbc000 { + compatible = "atmel,at91sam9rl-ssc"; + }; + adc0: adc@fffe0000 { atmel,adc-startup-time = <40>; }; -- cgit v0.10.2 From 0a51d644c20f5c88fd3a659119d1903f74927082 Mon Sep 17 00:00:00 2001 From: David Dueck Date: Wed, 17 Sep 2014 10:33:32 +0200 Subject: ARM: at91/dt: Fix typo regarding can0_clk Otherwise the clock for can0 will never get enabled. Signed-off-by: David Dueck Signed-off-by: Anthony Harivel Acked-by: Boris Brezillon Cc: stable@vger.kernel.org # v3.14 Signed-off-by: Nicolas Ferre diff --git a/arch/arm/boot/dts/sama5d3_can.dtsi b/arch/arm/boot/dts/sama5d3_can.dtsi index a077585..eaf4145 100644 --- a/arch/arm/boot/dts/sama5d3_can.dtsi +++ b/arch/arm/boot/dts/sama5d3_can.dtsi @@ -40,7 +40,7 @@ atmel,clk-output-range = <0 66000000>; }; - can1_clk: can0_clk { + can1_clk: can1_clk { #clock-cells = <0>; reg = <41>; atmel,clk-output-range = <0 66000000>; -- cgit v0.10.2 From 97735da4e3fc2cad464994f615b0d2211f132497 Mon Sep 17 00:00:00 2001 From: Boris BREZILLON Date: Tue, 9 Sep 2014 12:14:20 +0200 Subject: ARM: at91/dt: declare sckc node on at91sam9g45 Declare the SCKC (Slow Clock Configuration) block and its clks. Make use of the clk32k clk instead of slow_osc where appropriate. Signed-off-by: Boris BREZILLON Acked-by: Alexandre Belloni Signed-off-by: Nicolas Ferre diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi index 857fd3e..6d3d68e 100644 --- a/arch/arm/boot/dts/at91sam9g45.dtsi +++ b/arch/arm/boot/dts/at91sam9g45.dtsi @@ -165,7 +165,7 @@ compatible = "atmel,at91rm9200-clk-master"; #clock-cells = <0>; interrupts-extended = <&pmc AT91_PMC_MCKRDY>; - clocks = <&slow_xtal>, <&main>, <&plladiv>, <&utmi>; + clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>; atmel,clk-output-range = <0 133333333>; atmel,clk-divisors = <1 2 4 3>; }; @@ -181,7 +181,7 @@ #address-cells = <1>; #size-cells = <0>; interrupt-parent = <&pmc>; - clocks = <&slow_xtal>, <&main>, <&plladiv>, <&utmi>, <&mck>; + clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>; prog0: prog0 { #clock-cells = <0>; @@ -1165,6 +1165,32 @@ atmel,can-isoc; }; }; + + sckc@fffffd50 { + compatible = "atmel,at91sam9x5-sckc"; + reg = <0xfffffd50 0x4>; + + slow_osc: slow_osc { + compatible = "atmel,at91sam9x5-clk-slow-osc"; + #clock-cells = <0>; + atmel,startup-time-usec = <1200000>; + clocks = <&slow_xtal>; + }; + + slow_rc_osc: slow_rc_osc { + compatible = "atmel,at91sam9x5-clk-slow-rc-osc"; + #clock-cells = <0>; + atmel,startup-time-usec = <75>; + clock-frequency = <32768>; + clock-accuracy = <50000000>; + }; + + clk32k: slck { + compatible = "atmel,at91sam9x5-clk-slow"; + #clock-cells = <0>; + clocks = <&slow_rc_osc &slow_osc>; + }; + }; }; fb0: fb@0x00500000 { -- cgit v0.10.2 From 8a85ba2075a5fde3bc4c69c3f972f5144522453c Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Tue, 16 Sep 2014 10:43:57 +0200 Subject: ARM: at91/dt: sama5d3: add the nfc clock The atmel_nand driver is now able to handle the nfc clock, add it to sama5d3. Signed-off-by: Alexandre Belloni Signed-off-by: Nicolas Ferre diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi index 70a941f..277541b 100644 --- a/arch/arm/boot/dts/sama5d3.dtsi +++ b/arch/arm/boot/dts/sama5d3.dtsi @@ -1020,6 +1020,11 @@ reg = <2>; }; + hsmc_clk: hsmc_clk { + #clock-cells = <0>; + reg = <5>; + }; + pioA_clk: pioA_clk { #clock-cells = <0>; reg = <6>; @@ -1420,6 +1425,7 @@ 0xffffc000 0x00000070 /* NFC HSMC regs */ 0x00200000 0x00100000 /* NFC SRAM banks */ >; + clocks = <&hsmc_clk>; }; }; }; -- cgit v0.10.2 From e0065cf719a9d84a05c9722d149c9ce8f0508a36 Mon Sep 17 00:00:00 2001 From: Marek Roszko Date: Sat, 23 Aug 2014 23:12:05 -0400 Subject: ARM: at91/dt: sama5d3: use new pinctrl compatible string This switches the SAMA5D3 to use the new atmel,sama5d3-pinctrl id that was added with the drive strength options patch. Signed-off-by: Marek Roszko Acked-by: Linus Walleij [nicolas.ferre@atmel.com: second compatible string kept as at91sam9x5] Signed-off-by: Nicolas Ferre diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi index 277541b..5f4144d 100644 --- a/arch/arm/boot/dts/sama5d3.dtsi +++ b/arch/arm/boot/dts/sama5d3.dtsi @@ -445,7 +445,7 @@ pinctrl@fffff200 { #address-cells = <1>; #size-cells = <1>; - compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus"; + compatible = "atmel,sama5d3-pinctrl", "atmel,at91sam9x5-pinctrl", "simple-bus"; ranges = <0xfffff200 0xfffff200 0xa00>; atmel,mux-mask = < /* A B C */ -- cgit v0.10.2 From 28ce556b2eb5a38aecd8292ef7e1da4599766bd6 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Thu, 18 Sep 2014 09:03:36 -0700 Subject: ARM: dts: omap3-overo: Fix UART wake-up events Compared to legacy booting, we don't have wake-up events enabled for device tree based booting. This means that if deeper idle states are enabled, the device won't wake up to UART events and seems like it has hung. Let's fix that by adding the wake-up interrupt. Note that we don't need to set the PIN_OFF_WAKEUPENABLE any longer, that's handled by the wake-up interrupt when the serial driver does request_irq on it. Tested with the following on omap3-overo-summit that has the ES2.1 omap: #!/bin/bash uarts=$(find /sys/class/tty/ttyO*/device/power/ -type d) for uart in $uarts; do echo 3000 > $uart/autosuspend_delay_ms done uarts=$(find /sys/class/tty/ttyO*/power/ -type d) for uart in $uarts; do echo enabled > $uart/wakeup echo auto > $uart/control done echo 1 > /sys/kernel/debug/pm_debug/enable_off_mode # grep -i uart /proc/interrupts 90: 1085 INTC 74 OMAP UART2 338: 5 pinctrl 366 OMAP UART2 # grep ^core_pwrdm /sys/kernel/debug/pm_debug/count core_pwrdm (ON),OFF:1654,RET:131,INA:39,ON:1825... Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/omap3-overo-common-peripherals.dtsi b/arch/arm/boot/dts/omap3-overo-common-peripherals.dtsi index 5831bcc..520453d 100644 --- a/arch/arm/boot/dts/omap3-overo-common-peripherals.dtsi +++ b/arch/arm/boot/dts/omap3-overo-common-peripherals.dtsi @@ -36,8 +36,8 @@ uart3_pins: pinmux_uart3_pins { pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ - OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */ + OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ + OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */ >; }; }; @@ -88,6 +88,7 @@ }; &uart3 { + interrupts-extended = <&intc 74 &omap3_pmx_core OMAP3_UART3_RX>; pinctrl-names = "default"; pinctrl-0 = <&uart3_pins>; }; -- cgit v0.10.2 From 7c1babdcee6a99fcc61a9403b4c24baa6ef7cf1f Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Thu, 18 Sep 2014 09:03:36 -0700 Subject: ARM: dts: omap: Remove WAKEUPENABLE mux options for UARTs This is no longer needed as the device specific wake-up event can now be specified with interrupts-extended property where the second interrupt is the pinctrl-single register, such as the UART3 RX pin. Note that twl4030_omap3.dtsi needs to set WAKEUPENABLE for off-idle to properly trigger the PMIC scripts. And GPIO pins still need to set WAKEUPENABLE for wake-up events. Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/omap3-beagle-xm.dts b/arch/arm/boot/dts/omap3-beagle-xm.dts index 1becefc..06a8aec 100644 --- a/arch/arm/boot/dts/omap3-beagle-xm.dts +++ b/arch/arm/boot/dts/omap3-beagle-xm.dts @@ -174,8 +174,8 @@ uart3_pins: pinmux_uart3_pins { pinctrl-single,pins = < - 0x16e (PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ - 0x170 (PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx OUTPUT | MODE0 */ + 0x16e (PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ + 0x170 (PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx OUTPUT | MODE0 */ >; }; -- cgit v0.10.2 From a4ff93c185787412936bc8414f14f50bdd56e546 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Thu, 18 Sep 2014 09:03:36 -0700 Subject: ARM: dts: Do not set pulls for I2C lines There are external pulls on these lines and enabling the internal pulls can cause issue. This is because the internal pulls are parallel with the external pulls. So let's clear the internal I2C pulls. Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/omap3-n900.dts b/arch/arm/boot/dts/omap3-n900.dts index 1fe45d1..f0d8236 100644 --- a/arch/arm/boot/dts/omap3-n900.dts +++ b/arch/arm/boot/dts/omap3-n900.dts @@ -136,22 +136,22 @@ i2c1_pins: pinmux_i2c1_pins { pinctrl-single,pins = < - 0x18a (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl */ - 0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda */ + 0x18a (PIN_INPUT | MUX_MODE0) /* i2c1_scl */ + 0x18c (PIN_INPUT | MUX_MODE0) /* i2c1_sda */ >; }; i2c2_pins: pinmux_i2c2_pins { pinctrl-single,pins = < - 0x18e (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_scl */ - 0x190 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_sda */ + 0x18e (PIN_INPUT | MUX_MODE0) /* i2c2_scl */ + 0x190 (PIN_INPUT | MUX_MODE0) /* i2c2_sda */ >; }; i2c3_pins: pinmux_i2c3_pins { pinctrl-single,pins = < - 0x192 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_scl */ - 0x194 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_sda */ + 0x192 (PIN_INPUT | MUX_MODE0) /* i2c3_scl */ + 0x194 (PIN_INPUT | MUX_MODE0) /* i2c3_sda */ >; }; -- cgit v0.10.2 From 271d4c6bc709d922e5f8913bcb64d6c53a752e31 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Thu, 18 Sep 2014 09:03:36 -0700 Subject: ARM: dts: Add support for Ethernet on some N900 macro boards As we have support for this in board-rx51-peripherals.c, let's add it to the .dts files too. Note that the reset GPIO will eventually go to the driver. For now let's just pull it down and skip any further reset in case the bootloader has configured the MAC address so NFSroot works. Also note that after 3430-sdp are using proper GPMC timings we can remove the tests for smsc,lan91c94 in gpmc.c. Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/omap3-n900.dts b/arch/arm/boot/dts/omap3-n900.dts index f0d8236..19a5857 100644 --- a/arch/arm/boot/dts/omap3-n900.dts +++ b/arch/arm/boot/dts/omap3-n900.dts @@ -134,6 +134,14 @@ >; }; + ethernet_pins: pinmux_ethernet_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x20b4, PIN_INPUT_PULLDOWN | MUX_MODE4) /* gpmc_ncs3.gpio_54 */ + OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE4) /* dss_data16.gpio_86 */ + OMAP3_CORE1_IOPAD(0x219c, PIN_OUTPUT | MUX_MODE4) /* uart3_rts_sd.gpio_164 */ + >; + }; + i2c1_pins: pinmux_i2c1_pins { pinctrl-single,pins = < 0x18a (PIN_INPUT | MUX_MODE0) /* i2c1_scl */ @@ -578,6 +586,8 @@ &gpmc { ranges = <0 0 0x04000000 0x10000000>; /* 256MB */ + ranges = <0 0 0x01000000 0x01000000>, /* 16 MB for OneNAND */ + <1 0 0x02000000 0x01000000>; /* 16 MB for smc91c96 */ /* gpio-irq for dma: 65 */ @@ -646,6 +656,38 @@ reg = <0x004c0000 0x0fb40000>; }; }; + + ethernet@gpmc { + compatible = "smsc,lan91c94"; + interrupt-parent = <&gpio2>; + interrupts = <22 IRQ_TYPE_LEVEL_HIGH>; /* gpio54 */ + reg = <1 0x300 0xf>; /* 16 byte IO range at offset 0x300 */ + bank-width = <2>; + pinctrl-names = "default"; + pinctrl-0 = <ðernet_pins>; + gpmc,device-width = <2>; + gpmc,sync-clk-ps = <0>; + gpmc,cs-on-ns = <0>; + gpmc,cs-rd-off-ns = <48>; + gpmc,cs-wr-off-ns = <24>; + gpmc,adv-on-ns = <0>; + gpmc,adv-rd-off-ns = <0>; + gpmc,adv-wr-off-ns = <0>; + gpmc,we-on-ns = <12>; + gpmc,we-off-ns = <18>; + gpmc,oe-on-ns = <12>; + gpmc,oe-off-ns = <48>; + gpmc,page-burst-access-ns = <0>; + gpmc,access-ns = <42>; + gpmc,rd-cycle-ns = <180>; + gpmc,wr-cycle-ns = <180>; + gpmc,bus-turnaround-ns = <0>; + gpmc,cycle2cycle-delay-ns = <0>; + gpmc,wait-monitoring-ns = <0>; + gpmc,clk-activation-ns = <0>; + gpmc,wr-access-ns = <0>; + gpmc,wr-data-mux-bus-ns = <12>; + }; }; &mcspi1 { diff --git a/arch/arm/mach-omap2/pdata-quirks.c b/arch/arm/mach-omap2/pdata-quirks.c index b9d091b..61e8394 100644 --- a/arch/arm/mach-omap2/pdata-quirks.c +++ b/arch/arm/mach-omap2/pdata-quirks.c @@ -252,6 +252,9 @@ static void __init nokia_n900_legacy_init(void) platform_device_register(&omap3_rom_rng_device); } + + /* Only on some development boards */ + gpio_request_one(164, GPIOF_OUT_INIT_LOW, "smc91x reset"); } static void __init omap3_tao3530_legacy_init(void) -- cgit v0.10.2 From 7f5736c31bc9ec539fcb404292ee7e494922c07c Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Thu, 18 Sep 2014 09:03:36 -0700 Subject: ARM: dts: Enable PMIC idle configuration for LDP With the IO chain reconfigure fixed, we can now enable the PMIC scripts for LDP. Note that at least on my es3.0 based LDP, the UART seems to be flakey after wake-up events from off-idle and hangs but eventually continues. Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/omap3-ldp.dts b/arch/arm/boot/dts/omap3-ldp.dts index af272c1..72dca0b 100644 --- a/arch/arm/boot/dts/omap3-ldp.dts +++ b/arch/arm/boot/dts/omap3-ldp.dts @@ -159,6 +159,11 @@ reg = <0x48>; interrupts = <7>; /* SYS_NIRQ cascaded to intc */ interrupt-parent = <&intc>; + + twl_power: power { + compatible = "ti,twl4030-power-idle"; + ti,use_poweroff; + }; }; }; -- cgit v0.10.2 From 68dac838d3c3ae8e31bdd9ff512e2a4a111287d0 Mon Sep 17 00:00:00 2001 From: Dmitry Lifshitz Date: Wed, 17 Sep 2014 15:10:03 +0300 Subject: ARM: dts: sbc-t54: fix mux mode comment style Follow the comment style of mode0_name.modeX_name for pins which mux mode differs from MUX_MODE0. Signed-off-by: Dmitry Lifshitz Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/omap5-sbc-t54.dts b/arch/arm/boot/dts/omap5-sbc-t54.dts index 8e89793..337bbbc 100644 --- a/arch/arm/boot/dts/omap5-sbc-t54.dts +++ b/arch/arm/boot/dts/omap5-sbc-t54.dts @@ -19,8 +19,8 @@ mmc1_aux_pins: pinmux_mmc1_aux_pins { pinctrl-single,pins = < - OMAP5_IOPAD(0x0174, PIN_INPUT_PULLUP | MUX_MODE6) /* gpio8_228 */ - OMAP5_IOPAD(0x0176, PIN_INPUT_PULLUP | MUX_MODE6) /* gpio8_229 */ + OMAP5_IOPAD(0x0174, PIN_INPUT_PULLUP | MUX_MODE6) /* timer5_pwm_evt.gpio8_228 */ + OMAP5_IOPAD(0x0176, PIN_INPUT_PULLUP | MUX_MODE6) /* timer6_pwm_evt.gpio8_229 */ >; }; }; -- cgit v0.10.2 From db5790f89f82759ba51a2c65969cb45befa61a00 Mon Sep 17 00:00:00 2001 From: Dmitry Lifshitz Date: Wed, 17 Sep 2014 15:10:04 +0300 Subject: ARM: dts: cm-t54: fix mux mode comment style Follow the comment style of mode0_name.modeX_name for pins which mux mode differs from MUX_MODE0. Signed-off-by: Dmitry Lifshitz Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/omap5-cm-t54.dts b/arch/arm/boot/dts/omap5-cm-t54.dts index b8698ca..29007d1 100644 --- a/arch/arm/boot/dts/omap5-cm-t54.dts +++ b/arch/arm/boot/dts/omap5-cm-t54.dts @@ -127,8 +127,8 @@ wlan_gpios_pins: pinmux_wlan_gpios_pins { pinctrl-single,pins = < - OMAP5_IOPAD(0x019c, PIN_OUTPUT_PULLDOWN | MUX_MODE6) /* gpio4_109 */ - OMAP5_IOPAD(0x019e, PIN_OUTPUT_PULLDOWN | MUX_MODE6) /* gpio4_110 */ + OMAP5_IOPAD(0x019c, PIN_OUTPUT_PULLDOWN | MUX_MODE6) /* abemcpdm_ul_data.gpio4_109 */ + OMAP5_IOPAD(0x019e, PIN_OUTPUT_PULLDOWN | MUX_MODE6) /* abemcpdm_dl_data.gpio4_110 */ >; }; -- cgit v0.10.2 From 6097b5a5341614e36153d90189ac3ad75f19ce09 Mon Sep 17 00:00:00 2001 From: Dmitry Lifshitz Date: Wed, 17 Sep 2014 15:10:05 +0300 Subject: ARM: dts: cm-t54: add HDMI/DVI display data Add DSS related pinmux and display data nodes required to support HDMI and DVI video out on CM-T54. Signed-off-by: Dmitry Lifshitz Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/omap5-cm-t54.dts b/arch/arm/boot/dts/omap5-cm-t54.dts index 29007d1..a3faca9 100644 --- a/arch/arm/boot/dts/omap5-cm-t54.dts +++ b/arch/arm/boot/dts/omap5-cm-t54.dts @@ -16,6 +16,11 @@ reg = <0x80000000 0x7F000000>; /* 2048 MB */ }; + aliases { + display0 = &hdmi0; + display1 = &dvi0; + }; + vmmcsd_fixed: fixed-regulator-mmcsd { compatible = "regulator-fixed"; regulator-name = "vmmcsd_fixed"; @@ -66,6 +71,64 @@ default-state = "off"; }; }; + + hdmi0: connector@0 { + compatible = "hdmi-connector"; + label = "hdmi"; + + type = "a"; + + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_conn_pins>; + + hpd-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>; /* GPIO 193, HPD */ + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&hdmi_out>; + }; + }; + }; + + tfp410: encoder@0 { + compatible = "ti,tfp410"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + tfp410_in: endpoint@0 { + remote-endpoint = <&dpi_dvi_out>; + }; + }; + + port@1 { + reg = <1>; + + tfp410_out: endpoint@0 { + remote-endpoint = <&dvi_connector_in>; + }; + }; + }; + }; + + dvi0: connector@1 { + compatible = "dvi-connector"; + label = "dvi"; + + digital; + + ddc-i2c-bus = <&i2c2>; + + port { + dvi_connector_in: endpoint { + remote-endpoint = <&tfp410_out>; + }; + }; + }; }; &omap5_pmx_core { @@ -88,6 +151,13 @@ >; }; + i2c2_pins: pinmux_i2c2_pins { + pinctrl-single,pins = < + OMAP5_IOPAD(0x01b8, PIN_INPUT | MUX_MODE0) /* i2c2_scl */ + OMAP5_IOPAD(0x01ba, PIN_INPUT | MUX_MODE0) /* i2c2_sda */ + >; + }; + mmc1_pins: pinmux_mmc1_pins { pinctrl-single,pins = < OMAP5_IOPAD(0x01e2, PIN_INPUT_PULLUP | MUX_MODE0) /* sdcard_clk */ @@ -144,6 +214,53 @@ OMAP5_IOPAD(0x00b6, PIN_OUTPUT | MUX_MODE6) /* hsi2_acdata.gpio3_83 */ >; }; + + dss_hdmi_pins: pinmux_dss_hdmi_pins { + pinctrl-single,pins = < + OMAP5_IOPAD(0x013c, PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_cec */ + OMAP5_IOPAD(0x0140, PIN_INPUT | MUX_MODE0) /* hdmi_ddc_scl */ + OMAP5_IOPAD(0x0142, PIN_INPUT | MUX_MODE0) /* hdmi_ddc_sda */ + >; + }; + + hdmi_conn_pins: pinmux_hdmi_conn_pins { + pinctrl-single,pins = < + OMAP5_IOPAD(0x013e, PIN_INPUT | MUX_MODE6) /* hdmi_hpd.gpio7_193 */ + >; + }; + + dss_dpi_pins: pinmux_dss_dpi_pins { + pinctrl-single,pins = < + OMAP5_IOPAD(0x0104, PIN_OUTPUT | MUX_MODE3) /* rfbi_data15.dispc_data15 */ + OMAP5_IOPAD(0x0106, PIN_OUTPUT | MUX_MODE3) /* rfbi_data14.dispc_data14 */ + OMAP5_IOPAD(0x0108, PIN_OUTPUT | MUX_MODE3) /* rfbi_data13.dispc_data13 */ + OMAP5_IOPAD(0x010a, PIN_OUTPUT | MUX_MODE3) /* rfbi_data12.dispc_data12 */ + OMAP5_IOPAD(0x010c, PIN_OUTPUT | MUX_MODE3) /* rfbi_data11.dispc_data11 */ + OMAP5_IOPAD(0x010e, PIN_OUTPUT | MUX_MODE3) /* rfbi_data10.dispc_data10 */ + OMAP5_IOPAD(0x0110, PIN_OUTPUT | MUX_MODE3) /* rfbi_data9.dispc_data9 */ + OMAP5_IOPAD(0x0112, PIN_OUTPUT | MUX_MODE3) /* rfbi_data8.dispc_data8 */ + OMAP5_IOPAD(0x0114, PIN_OUTPUT | MUX_MODE3) /* rfbi_data7.dispc_data7 */ + OMAP5_IOPAD(0x0116, PIN_OUTPUT | MUX_MODE3) /* rfbi_data6.dispc_data6 */ + OMAP5_IOPAD(0x0118, PIN_OUTPUT | MUX_MODE3) /* rfbi_data5.dispc_data5 */ + OMAP5_IOPAD(0x011a, PIN_OUTPUT | MUX_MODE3) /* rfbi_data4.dispc_data4 */ + OMAP5_IOPAD(0x011c, PIN_OUTPUT | MUX_MODE3) /* rfbi_data3.dispc_data3 */ + OMAP5_IOPAD(0x011e, PIN_OUTPUT | MUX_MODE3) /* rfbi_data2.dispc_data2 */ + OMAP5_IOPAD(0x0120, PIN_OUTPUT | MUX_MODE3) /* rfbi_data1.dispc_data1 */ + OMAP5_IOPAD(0x0122, PIN_OUTPUT | MUX_MODE3) /* rfbi_data0.dispc_data0 */ + OMAP5_IOPAD(0x0124, PIN_OUTPUT | MUX_MODE3) /* rfbi_we.dispc_vsync */ + OMAP5_IOPAD(0x0126, PIN_OUTPUT | MUX_MODE3) /* rfbi_cs0.dispc_hsync */ + OMAP5_IOPAD(0x0128, PIN_OUTPUT | MUX_MODE3) /* rfbi_a0.dispc_de */ + OMAP5_IOPAD(0x012a, PIN_OUTPUT | MUX_MODE3) /* rfbi_re.dispc_pclk */ + OMAP5_IOPAD(0x012c, PIN_OUTPUT | MUX_MODE3) /* rfbi_hsync0.dispc_data17 */ + OMAP5_IOPAD(0x012e, PIN_OUTPUT | MUX_MODE3) /* rfbi_te_vsync0.dispc_data16 */ + OMAP5_IOPAD(0x0130, PIN_OUTPUT | MUX_MODE3) /* gpio6_182.dispc_data18 */ + OMAP5_IOPAD(0x0132, PIN_OUTPUT | MUX_MODE3) /* gpio6_183.dispc_data19 */ + OMAP5_IOPAD(0x0134, PIN_OUTPUT | MUX_MODE3) /* gpio6_184.dispc_data20 */ + OMAP5_IOPAD(0x0136, PIN_OUTPUT | MUX_MODE3) /* gpio6_185.dispc_data21 */ + OMAP5_IOPAD(0x0138, PIN_OUTPUT | MUX_MODE3) /* gpio6_186.dispc_data22 */ + OMAP5_IOPAD(0x013a, PIN_OUTPUT | MUX_MODE3) /* gpio6_187.dispc_data23 */ + >; + }; }; &mmc1 { @@ -399,6 +516,13 @@ }; }; +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins>; + + clock-frequency = <100000>; +}; + &usbhshost { port2-mode = "ehci-hsic"; port3-mode = "ehci-hsic"; @@ -411,3 +535,37 @@ &cpu0 { cpu0-supply = <&smps123_reg>; }; + +&dss { + status = "ok"; + + pinctrl-names = "default"; + pinctrl-0 = <&dss_dpi_pins>; + + port { + dpi_dvi_out: endpoint@0 { + remote-endpoint = <&tfp410_in>; + data-lines = <24>; + }; + }; +}; + +&dsi2 { + status = "ok"; + vdd-supply = <&ldo4_reg>; +}; + +&hdmi { + status = "ok"; + vdda-supply = <&ldo4_reg>; + + pinctrl-names = "default"; + pinctrl-0 = <&dss_hdmi_pins>; + + port { + hdmi_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + lanes = <1 0 3 2 5 4 7 6>; + }; + }; +}; -- cgit v0.10.2 From ac84d6cc182971079df846c7814fbc5fd7b7e0f8 Mon Sep 17 00:00:00 2001 From: Dmitry Lifshitz Date: Wed, 17 Sep 2014 15:10:06 +0300 Subject: ARM: dts: cm-t54: add Startek LCD support Add DT support for Startek KD050C LCD 800x480 panel. Signed-off-by: Dmitry Lifshitz Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/omap5-cm-t54.dts b/arch/arm/boot/dts/omap5-cm-t54.dts index a3faca9..7323b70 100644 --- a/arch/arm/boot/dts/omap5-cm-t54.dts +++ b/arch/arm/boot/dts/omap5-cm-t54.dts @@ -19,6 +19,7 @@ aliases { display0 = &hdmi0; display1 = &dvi0; + display2 = &lcd0; }; vmmcsd_fixed: fixed-regulator-mmcsd { @@ -72,6 +73,38 @@ }; }; + lcd0: display { + compatible = "startek,startek-kd050c", "panel-dpi"; + label = "lcd"; + + pinctrl-names = "default"; + pinctrl-0 = <&lcd_pins>; + + enable-gpios = <&gpio8 3 GPIO_ACTIVE_HIGH>; + + panel-timing { + clock-frequency = <33000000>; + hactive = <800>; + vactive = <480>; + hfront-porch = <40>; + hback-porch = <40>; + hsync-len = <43>; + vback-porch = <29>; + vfront-porch = <13>; + vsync-len = <3>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <1>; + }; + + port { + lcd_in: endpoint { + remote-endpoint = <&dpi_lcd_out>; + }; + }; + }; + hdmi0: connector@0 { compatible = "hdmi-connector"; label = "hdmi"; @@ -223,6 +256,12 @@ >; }; + lcd_pins: pinmux_lcd_pins { + pinctrl-single,pins = < + OMAP5_IOPAD(0x0172, PIN_OUTPUT_PULLDOWN | MUX_MODE6) /* timer11_pwm_evt.gpio8_227 */ + >; + }; + hdmi_conn_pins: pinmux_hdmi_conn_pins { pinctrl-single,pins = < OMAP5_IOPAD(0x013e, PIN_INPUT | MUX_MODE6) /* hdmi_hpd.gpio7_193 */ @@ -547,6 +586,11 @@ remote-endpoint = <&tfp410_in>; data-lines = <24>; }; + + dpi_lcd_out: endpoint@1 { + remote-endpoint = <&lcd_in>; + data-lines = <24>; + }; }; }; -- cgit v0.10.2 From 1a3290b813ee71843480ece01493e23a2f4a807a Mon Sep 17 00:00:00 2001 From: Dmitry Lifshitz Date: Wed, 17 Sep 2014 15:10:07 +0300 Subject: ARM: dts: cm-t54: add ADS7846 touchscreen support Add ADS7846 touchscreen support. Signed-off-by: Dmitry Lifshitz Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/omap5-cm-t54.dts b/arch/arm/boot/dts/omap5-cm-t54.dts index 7323b70..88f3dc6 100644 --- a/arch/arm/boot/dts/omap5-cm-t54.dts +++ b/arch/arm/boot/dts/omap5-cm-t54.dts @@ -51,6 +51,13 @@ enable-active-high; }; + ads7846reg: ads7846-reg { + compatible = "regulator-fixed"; + regulator-name = "ads7846-reg"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + /* HS USB Host PHY on PORT 2 */ hsusb2_phy: hsusb2_phy { compatible = "usb-nop-xceiv"; @@ -164,6 +171,15 @@ }; }; +&omap5_pmx_wkup { + + ads7846_pins: pinmux_ads7846_pins { + pinctrl-single,pins = < + 0x02 (PIN_INPUT_PULLDOWN | MUX_MODE6) /* llib_wakereqin.gpio1_wk15 */ + >; + }; +}; + &omap5_pmx_core { pinctrl-names = "default"; pinctrl-0 = < @@ -300,6 +316,51 @@ OMAP5_IOPAD(0x013a, PIN_OUTPUT | MUX_MODE3) /* gpio6_187.dispc_data23 */ >; }; + + mcspi2_pins: pinmux_mcspi1_pins { + pinctrl-single,pins = < + OMAP5_IOPAD(0x00fc, PIN_INPUT | MUX_MODE0) /* mcspi2_clk */ + OMAP5_IOPAD(0x00fe, PIN_INPUT | MUX_MODE0) /* mcspi2_simo */ + OMAP5_IOPAD(0x0100, PIN_INPUT | MUX_MODE0) /* mcspi2_somi */ + OMAP5_IOPAD(0x0102, PIN_INPUT | MUX_MODE0) /* mcspi2_cs0 */ + >; + }; +}; + +&mcspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&mcspi2_pins>; + + /* touch controller */ + ads7846@0 { + pinctrl-names = "default"; + pinctrl-0 = <&ads7846_pins>; + + compatible = "ti,ads7846"; + vcc-supply = <&ads7846reg>; + + reg = <0>; /* CS0 */ + spi-max-frequency = <1500000>; + + interrupt-parent = <&gpio1>; + interrupts = <15 0>; /* gpio1_wk15 */ + pendown-gpio = <&gpio1 15 0>; + + + ti,x-min = /bits/ 16 <0x0>; + ti,x-max = /bits/ 16 <0x0fff>; + ti,y-min = /bits/ 16 <0x0>; + ti,y-max = /bits/ 16 <0x0fff>; + + ti,x-plate-ohms = /bits/ 16 <180>; + ti,pressure-max = /bits/ 16 <255>; + + ti,debounce-max = /bits/ 16 <30>; + ti,debounce-tol = /bits/ 16 <10>; + ti,debounce-rep = /bits/ 16 <1>; + + linux,wakeup; + }; }; &mmc1 { -- cgit v0.10.2 From be9d32e8ab4c1668abce1dae8ce4db9e9f3e874a Mon Sep 17 00:00:00 2001 From: Dmitry Lifshitz Date: Wed, 17 Sep 2014 15:10:08 +0300 Subject: ARM: dts: cm-t54: setup omap_dwc3 Add "extcon" and "vbus-supply" properties of DWC3 node. Signed-off-by: Dmitry Lifshitz Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/omap5-cm-t54.dts b/arch/arm/boot/dts/omap5-cm-t54.dts index 88f3dc6..880333a 100644 --- a/arch/arm/boot/dts/omap5-cm-t54.dts +++ b/arch/arm/boot/dts/omap5-cm-t54.dts @@ -632,6 +632,11 @@ phys = <0 &hsusb2_phy &hsusb3_phy>; }; +&usb3 { + extcon = <&extcon_usb3>; + vbus-supply = <&smps10_out1_reg>; +}; + &cpu0 { cpu0-supply = <&smps123_reg>; }; -- cgit v0.10.2 From 4dd7933ad606af457bc85b1afdaaac68aa993abf Mon Sep 17 00:00:00 2001 From: Erik van Luijk Date: Tue, 2 Sep 2014 12:52:12 +0200 Subject: ARM: at91/dt: at91sam9m10g45ek add rtc node Add rtc node to both the at91sam9g45 SoC family and the at91sam9m10g45ek board. Signed-off-by: Erik van Luijk Acked-by: Boris Brezillon Signed-off-by: Nicolas Ferre diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi index 6d3d68e..d3f6513 100644 --- a/arch/arm/boot/dts/at91sam9g45.dtsi +++ b/arch/arm/boot/dts/at91sam9g45.dtsi @@ -1191,6 +1191,13 @@ clocks = <&slow_rc_osc &slow_osc>; }; }; + + rtc@fffffdb0 { + compatible = "atmel,at91rm9200-rtc"; + reg = <0xfffffdb0 0x30>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + status = "disabled"; + }; }; fb0: fb@0x00500000 { diff --git a/arch/arm/boot/dts/at91sam9m10g45ek.dts b/arch/arm/boot/dts/at91sam9m10g45ek.dts index 96ccc7d..d8dd226 100644 --- a/arch/arm/boot/dts/at91sam9m10g45ek.dts +++ b/arch/arm/boot/dts/at91sam9m10g45ek.dts @@ -160,6 +160,10 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm_leds>; }; + + rtc@fffffdb0 { + status = "okay"; + }; }; fb0: fb@0x00500000 { -- cgit v0.10.2 From f53e3c538da314913e5d3d82c9610f8da42bd894 Mon Sep 17 00:00:00 2001 From: Lucas Weaver Date: Tue, 19 Aug 2014 08:54:00 -0500 Subject: ARM: dts: DRA7: Add PMU nodes DRA74x and DRA72x family of processors vary slightly in the number of CPUs. So, add different instances of PMU for each of these processor groups. Further, since the interrupts bypass crossbar and are directly connected to GIC, mark the dts nodes with relevant information. Tested with perf utility. Reviewed-by: Felipe Balbi Signed-off-by: Lucas Weaver Signed-off-by: Nishanth Menon Signed-off-by: Tony Lindgren diff --git a/arch/arm/boot/dts/dra72x.dtsi b/arch/arm/boot/dts/dra72x.dtsi index f1ec22f..e5a3d23 100644 --- a/arch/arm/boot/dts/dra72x.dtsi +++ b/arch/arm/boot/dts/dra72x.dtsi @@ -22,4 +22,9 @@ reg = <0>; }; }; + + pmu { + compatible = "arm,cortex-a15-pmu"; + interrupts = ; + }; }; diff --git a/arch/arm/boot/dts/dra74x.dtsi b/arch/arm/boot/dts/dra74x.dtsi index a4e8bb9..3be544c 100644 --- a/arch/arm/boot/dts/dra74x.dtsi +++ b/arch/arm/boot/dts/dra74x.dtsi @@ -38,4 +38,10 @@ reg = <1>; }; }; + + pmu { + compatible = "arm,cortex-a15-pmu"; + interrupts = , + ; + }; }; -- cgit v0.10.2 From 2bf172cfddee1fc7012980edc97f62526f65281a Mon Sep 17 00:00:00 2001 From: Daniel Mack Date: Thu, 14 Aug 2014 11:46:12 +0200 Subject: ARM: pxa: dts: fix mmc controller compatible string The vendor prefix was renamed from "mrvl" to "marvell". Follow this change in the dts file. Signed-off-by: Daniel Mack Signed-off-by: Haojian Zhuang diff --git a/arch/arm/boot/dts/pxa2xx.dtsi b/arch/arm/boot/dts/pxa2xx.dtsi index a5e90f0..0e8dbff 100644 --- a/arch/arm/boot/dts/pxa2xx.dtsi +++ b/arch/arm/boot/dts/pxa2xx.dtsi @@ -120,7 +120,7 @@ }; mmc0: mmc@41100000 { - compatible = "mrvl,pxa-mmc"; + compatible = "marvell,pxa-mmc"; reg = <0x41100000 0x1000>; interrupts = <23>; status = "disabled"; -- cgit v0.10.2 From 7a08cf77dbb976cec39c300201cebfee94552f54 Mon Sep 17 00:00:00 2001 From: Daniel Mack Date: Thu, 14 Aug 2014 11:46:13 +0200 Subject: ARM: pxa: dts: fix ohci controller compatible string The vendor prefix was renamed from "mrvl" to "marvell". Follow this change in the dts file. Signed-off-by: Daniel Mack Signed-off-by: Haojian Zhuang diff --git a/arch/arm/boot/dts/pxa2xx.dtsi b/arch/arm/boot/dts/pxa2xx.dtsi index 0e8dbff..c08f8462 100644 --- a/arch/arm/boot/dts/pxa2xx.dtsi +++ b/arch/arm/boot/dts/pxa2xx.dtsi @@ -113,7 +113,7 @@ }; usb0: ohci@4c000000 { - compatible = "mrvl,pxa-ohci"; + compatible = "marvell,pxa-ohci"; reg = <0x4c000000 0x10000>; interrupts = <3>; status = "disabled"; -- cgit v0.10.2 From d07fe967189ff7c32f5a78b4f28c2ccbab850091 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Thu, 18 Sep 2014 11:24:40 +0800 Subject: ARM: dts: sun8i: Add DMA controller node Add the DMA controller node and DMA bindings to the supported devices. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard diff --git a/arch/arm/boot/dts/sun8i-a23.dtsi b/arch/arm/boot/dts/sun8i-a23.dtsi index a350392..6146ef1 100644 --- a/arch/arm/boot/dts/sun8i-a23.dtsi +++ b/arch/arm/boot/dts/sun8i-a23.dtsi @@ -247,6 +247,15 @@ #size-cells = <1>; ranges; + dma: dma-controller@01c02000 { + compatible = "allwinner,sun8i-a23-dma"; + reg = <0x01c02000 0x1000>; + interrupts = <0 50 4>; + clocks = <&ahb1_gates 6>; + resets = <&ahb1_rst 6>; + #dma-cells = <1>; + }; + mmc0: mmc@01c0f000 { compatible = "allwinner,sun5i-a13-mmc"; reg = <0x01c0f000 0x1000>; @@ -376,6 +385,8 @@ reg-io-width = <4>; clocks = <&apb2_gates 16>; resets = <&apb2_rst 16>; + dmas = <&dma 6>, <&dma 6>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -387,6 +398,8 @@ reg-io-width = <4>; clocks = <&apb2_gates 17>; resets = <&apb2_rst 17>; + dmas = <&dma 7>, <&dma 7>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -398,6 +411,8 @@ reg-io-width = <4>; clocks = <&apb2_gates 18>; resets = <&apb2_rst 18>; + dmas = <&dma 8>, <&dma 8>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -409,6 +424,8 @@ reg-io-width = <4>; clocks = <&apb2_gates 19>; resets = <&apb2_rst 19>; + dmas = <&dma 9>, <&dma 9>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -420,6 +437,8 @@ reg-io-width = <4>; clocks = <&apb2_gates 20>; resets = <&apb2_rst 20>; + dmas = <&dma 10>, <&dma 10>; + dma-names = "rx", "tx"; status = "disabled"; }; -- cgit v0.10.2 From 6051ddd4f94894cce8fde3aa29f90ae6c567fc46 Mon Sep 17 00:00:00 2001 From: Romain Perier Date: Fri, 19 Sep 2014 12:36:27 +0000 Subject: ARM: dts: rockchip: Remove "regulator-always-on" in vcc_rmii for Radxa Rock On Rockchip RK3188 SoCs the platform driver emac_rockchip is used. This variant driver enables this regulator when the device driver is loaded. The phy no longer needs to be always on. Signed-off-by: Romain Perier Signed-off-by: Heiko Stuebner diff --git a/arch/arm/boot/dts/rk3188-radxarock.dts b/arch/arm/boot/dts/rk3188-radxarock.dts index c08744d..61d364e 100644 --- a/arch/arm/boot/dts/rk3188-radxarock.dts +++ b/arch/arm/boot/dts/rk3188-radxarock.dts @@ -186,7 +186,6 @@ regulator-name = "VCC_RMII"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - regulator-always-on; }; vccio_wl: REG10 { -- cgit v0.10.2 From 55602a09dd7e0cad5f85b0945bfcbac2898540a0 Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Fri, 19 Sep 2014 16:50:50 -0700 Subject: ARM: DT: msm8660: Add sdcc nodes Add the sdcc nodes to support the SD card controller using pl180 mmci driver. We also add a temporary fixed regulator until the regulator driver is mainlined. Cc: Srinivas Kandagatla Signed-off-by: Stephen Boyd Signed-off-by: Kumar Gala diff --git a/arch/arm/boot/dts/qcom-msm8660-surf.dts b/arch/arm/boot/dts/qcom-msm8660-surf.dts index ff7c53f..e0883c3 100644 --- a/arch/arm/boot/dts/qcom-msm8660-surf.dts +++ b/arch/arm/boot/dts/qcom-msm8660-surf.dts @@ -14,6 +14,18 @@ status = "ok"; }; }; + + amba { + /* eMMC */ + sdcc1: sdcc@12400000 { + status = "okay"; + }; + + /* External micro SD card */ + sdcc3: sdcc@12180000 { + status = "okay"; + }; + }; }; }; diff --git a/arch/arm/boot/dts/qcom-msm8660.dtsi b/arch/arm/boot/dts/qcom-msm8660.dtsi index a3fd26b..0affd61 100644 --- a/arch/arm/boot/dts/qcom-msm8660.dtsi +++ b/arch/arm/boot/dts/qcom-msm8660.dtsi @@ -2,6 +2,7 @@ /include/ "skeleton.dtsi" +#include #include #include @@ -146,5 +147,55 @@ }; }; }; + + /* Temporary fixed regulator */ + vsdcc_fixed: vsdcc-regulator { + compatible = "regulator-fixed"; + regulator-name = "SDCC Power"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + regulator-always-on; + }; + + amba { + compatible = "arm,amba-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + sdcc1: sdcc@12400000 { + status = "disabled"; + compatible = "arm,pl18x", "arm,primecell"; + arm,primecell-periphid = <0x00051180>; + reg = <0x12400000 0x8000>; + interrupts = ; + interrupt-names = "cmd_irq"; + clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; + clock-names = "mclk", "apb_pclk"; + bus-width = <8>; + max-frequency = <48000000>; + non-removable; + cap-sd-highspeed; + cap-mmc-highspeed; + vmmc-supply = <&vsdcc_fixed>; + }; + + sdcc3: sdcc@12180000 { + compatible = "arm,pl18x", "arm,primecell"; + arm,primecell-periphid = <0x00051180>; + status = "disabled"; + reg = <0x12180000 0x8000>; + interrupts = ; + interrupt-names = "cmd_irq"; + clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>; + clock-names = "mclk", "apb_pclk"; + bus-width = <4>; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency = <48000000>; + no-1-8-v; + vmmc-supply = <&vsdcc_fixed>; + }; + }; }; + }; -- cgit v0.10.2 From aabff7bfe55afd01d71a5f11d4a84bd873c20f5e Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Fri, 19 Sep 2014 16:50:51 -0700 Subject: ARM: DT: msm8960: Add sdcc nodes Add the sdcc nodes to support the SD card controller using pl180 mmci driver. We also add a temporary fixed regulator until the regulator driver is mainlined. Cc: Srinivas Kandagatla Signed-off-by: Stephen Boyd Signed-off-by: Kumar Gala diff --git a/arch/arm/boot/dts/qcom-msm8960-cdp.dts b/arch/arm/boot/dts/qcom-msm8960-cdp.dts index 8b10812..7f70fae 100644 --- a/arch/arm/boot/dts/qcom-msm8960-cdp.dts +++ b/arch/arm/boot/dts/qcom-msm8960-cdp.dts @@ -14,6 +14,18 @@ status = "ok"; }; }; + + amba { + /* eMMC */ + sdcc1: sdcc@12400000 { + status = "okay"; + }; + + /* External micro SD card */ + sdcc3: sdcc@12180000 { + status = "okay"; + }; + }; }; }; diff --git a/arch/arm/boot/dts/qcom-msm8960.dtsi b/arch/arm/boot/dts/qcom-msm8960.dtsi index 2f67724..e1b0d5c 100644 --- a/arch/arm/boot/dts/qcom-msm8960.dtsi +++ b/arch/arm/boot/dts/qcom-msm8960.dtsi @@ -2,6 +2,7 @@ /include/ "skeleton.dtsi" +#include #include #include @@ -188,5 +189,54 @@ clocks = <&gcc PRNG_CLK>; clock-names = "core"; }; + + /* Temporary fixed regulator */ + vsdcc_fixed: vsdcc-regulator { + compatible = "regulator-fixed"; + regulator-name = "SDCC Power"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + regulator-always-on; + }; + + amba { + compatible = "arm,amba-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + sdcc1: sdcc@12400000 { + status = "disabled"; + compatible = "arm,pl18x", "arm,primecell"; + arm,primecell-periphid = <0x00051180>; + reg = <0x12400000 0x8000>; + interrupts = ; + interrupt-names = "cmd_irq"; + clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; + clock-names = "mclk", "apb_pclk"; + bus-width = <8>; + max-frequency = <96000000>; + non-removable; + cap-sd-highspeed; + cap-mmc-highspeed; + vmmc-supply = <&vsdcc_fixed>; + }; + + sdcc3: sdcc@12180000 { + compatible = "arm,pl18x", "arm,primecell"; + arm,primecell-periphid = <0x00051180>; + status = "disabled"; + reg = <0x12180000 0x8000>; + interrupts = ; + interrupt-names = "cmd_irq"; + clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>; + clock-names = "mclk", "apb_pclk"; + bus-width = <4>; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency = <192000000>; + no-1-8-v; + vmmc-supply = <&vsdcc_fixed>; + }; + }; }; }; -- cgit v0.10.2 From a392d42de7e9372b1049be1dee1aeefa51e14345 Mon Sep 17 00:00:00 2001 From: Grygorii Strashko Date: Mon, 22 Sep 2014 15:19:27 -0400 Subject: ARM: dts: keystone: add keystone irq controller node Add Keystone IRQ controller IP node which allows ARM CorePac core to receive signals from DSP cores. Signed-off-by: Grygorii Strashko Signed-off-by: Santosh Shilimkar diff --git a/arch/arm/boot/dts/keystone.dtsi b/arch/arm/boot/dts/keystone.dtsi index 9e31fe7..1820d9e 100644 --- a/arch/arm/boot/dts/keystone.dtsi +++ b/arch/arm/boot/dts/keystone.dtsi @@ -277,5 +277,13 @@ clock-names = "fck"; bus_freq = <2500000>; }; + + kirq0: keystone_irq@26202a0 { + compatible = "ti,keystone-irq"; + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + ti,syscon-dev = <&devctrl 0x2a0>; + }; }; }; -- cgit v0.10.2 From a3d3ee3f7d0b754dc06de68248d752231dddc9a5 Mon Sep 17 00:00:00 2001 From: Grygorii Strashko Date: Mon, 22 Sep 2014 15:19:27 -0400 Subject: ARM: dts: keystone: add dsp gpio controllers nodes Add Keystone 2 DSP GPIO nodes for SoCs: k2hk: DSP GPIO banks 0-7 correspond to DSP0-DSP7 k2l: DSP GPIO banks 0-3 correspond to DSP0-DSP3 k2e: DSP GPIO bank 0 corresponds to DSP0 Signed-off-by: Grygorii Strashko Signed-off-by: Santosh Shilimkar diff --git a/arch/arm/boot/dts/k2e.dtsi b/arch/arm/boot/dts/k2e.dtsi index 03d0190..13cf35a 100644 --- a/arch/arm/boot/dts/k2e.dtsi +++ b/arch/arm/boot/dts/k2e.dtsi @@ -76,5 +76,12 @@ usb-phy = <&usb1_phy>, <&usb1_phy>; }; }; + + dspgpio0: keystone_dsp_gpio@02620240 { + compatible = "ti,keystone-dsp-gpio"; + gpio-controller; + #gpio-cells = <2>; + gpio,syscon-dev = <&devctrl 0x240>; + }; }; }; diff --git a/arch/arm/boot/dts/k2hk.dtsi b/arch/arm/boot/dts/k2hk.dtsi index c73899c..d721f4b 100644 --- a/arch/arm/boot/dts/k2hk.dtsi +++ b/arch/arm/boot/dts/k2hk.dtsi @@ -42,5 +42,61 @@ soc { /include/ "k2hk-clocks.dtsi" + + dspgpio0: keystone_dsp_gpio@02620240 { + compatible = "ti,keystone-dsp-gpio"; + gpio-controller; + #gpio-cells = <2>; + gpio,syscon-dev = <&devctrl 0x240>; + }; + + dspgpio1: keystone_dsp_gpio@2620244 { + compatible = "ti,keystone-dsp-gpio"; + gpio-controller; + #gpio-cells = <2>; + gpio,syscon-dev = <&devctrl 0x244>; + }; + + dspgpio2: keystone_dsp_gpio@2620248 { + compatible = "ti,keystone-dsp-gpio"; + gpio-controller; + #gpio-cells = <2>; + gpio,syscon-dev = <&devctrl 0x248>; + }; + + dspgpio3: keystone_dsp_gpio@262024c { + compatible = "ti,keystone-dsp-gpio"; + gpio-controller; + #gpio-cells = <2>; + gpio,syscon-dev = <&devctrl 0x24c>; + }; + + dspgpio4: keystone_dsp_gpio@2620250 { + compatible = "ti,keystone-dsp-gpio"; + gpio-controller; + #gpio-cells = <2>; + gpio,syscon-dev = <&devctrl 0x250>; + }; + + dspgpio5: keystone_dsp_gpio@2620254 { + compatible = "ti,keystone-dsp-gpio"; + gpio-controller; + #gpio-cells = <2>; + gpio,syscon-dev = <&devctrl 0x254>; + }; + + dspgpio6: keystone_dsp_gpio@2620258 { + compatible = "ti,keystone-dsp-gpio"; + gpio-controller; + #gpio-cells = <2>; + gpio,syscon-dev = <&devctrl 0x258>; + }; + + dspgpio7: keystone_dsp_gpio@262025c { + compatible = "ti,keystone-dsp-gpio"; + gpio-controller; + #gpio-cells = <2>; + gpio,syscon-dev = <&devctrl 0x25c>; + }; }; }; diff --git a/arch/arm/boot/dts/k2l.dtsi b/arch/arm/boot/dts/k2l.dtsi index 1f7f479..e3bb142 100644 --- a/arch/arm/boot/dts/k2l.dtsi +++ b/arch/arm/boot/dts/k2l.dtsi @@ -51,5 +51,33 @@ clocks = <&clkuart3>; interrupts = ; }; + + dspgpio0: keystone_dsp_gpio@02620240 { + compatible = "ti,keystone-dsp-gpio"; + gpio-controller; + #gpio-cells = <2>; + gpio,syscon-dev = <&devctrl 0x240>; + }; + + dspgpio1: keystone_dsp_gpio@2620244 { + compatible = "ti,keystone-dsp-gpio"; + gpio-controller; + #gpio-cells = <2>; + gpio,syscon-dev = <&devctrl 0x244>; + }; + + dspgpio2: keystone_dsp_gpio@2620248 { + compatible = "ti,keystone-dsp-gpio"; + gpio-controller; + #gpio-cells = <2>; + gpio,syscon-dev = <&devctrl 0x248>; + }; + + dspgpio3: keystone_dsp_gpio@262024c { + compatible = "ti,keystone-dsp-gpio"; + gpio-controller; + #gpio-cells = <2>; + gpio,syscon-dev = <&devctrl 0x24c>; + }; }; }; -- cgit v0.10.2 From 48443f07bd077f127d9157f22d8b5eefe28537a1 Mon Sep 17 00:00:00 2001 From: Karicheri Muralidharan Date: Mon, 22 Sep 2014 15:19:27 -0400 Subject: ARM: dts: keystone: k2l: Fix chip selects for SPI devices There are 5 chip selects per SPI0 and SPI2 and 3 per SPI1. SPI2 needs to be pinned out to use and by default they are disabled. So keep the state disabled to reflect default. Signed-off-by: Murali Karicheri Signed-off-by: Grygorii Strashko Signed-off-by: Santosh Shilimkar diff --git a/arch/arm/boot/dts/k2l.dtsi b/arch/arm/boot/dts/k2l.dtsi index e3bb142..291db43 100644 --- a/arch/arm/boot/dts/k2l.dtsi +++ b/arch/arm/boot/dts/k2l.dtsi @@ -81,3 +81,17 @@ }; }; }; + +&spi0 { + ti,davinci-spi-num-cs = <5>; +}; + +&spi1 { + ti,davinci-spi-num-cs = <3>; +}; + +&spi2 { + ti,davinci-spi-num-cs = <5>; + /* Pin muxed. Enabled and configured by Bootloader */ + status = "disabled"; +}; -- cgit v0.10.2 From b2ed7d98e1c7098f452cf95ab69211a2f8e02ac8 Mon Sep 17 00:00:00 2001 From: "Karicheri, Muralidharan" Date: Mon, 22 Sep 2014 15:19:28 -0400 Subject: ARM: dts: keystone: fix bindings for pcie and usb clock nodes Fix incorrect clock names for usb1, pcie1 and domain register offset for pcie1 clock nodes on K2E EVM Signed-off-by: Murali Karicheri Signed-off-by: Santosh Shilimkar diff --git a/arch/arm/boot/dts/k2e-clocks.dtsi b/arch/arm/boot/dts/k2e-clocks.dtsi index 598afe9..4773d6a 100644 --- a/arch/arm/boot/dts/k2e-clocks.dtsi +++ b/arch/arm/boot/dts/k2e-clocks.dtsi @@ -40,7 +40,7 @@ clocks { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&chipclk16>; - clock-output-names = "usb"; + clock-output-names = "usb1"; reg = <0x02350004 0xb00>, <0x02350000 0x400>; reg-names = "control", "domain"; domain-id = <0>; @@ -60,8 +60,8 @@ clocks { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&chipclk12>; - clock-output-names = "pcie"; - reg = <0x0235006c 0xb00>, <0x02350000 0x400>; + clock-output-names = "pcie1"; + reg = <0x0235006c 0xb00>, <0x02350048 0x400>; reg-names = "control", "domain"; domain-id = <18>; }; -- cgit v0.10.2 From 995425883e4087a4bfd61d12e442089d1201fc5c Mon Sep 17 00:00:00 2001 From: Matthias Brugger Date: Mon, 18 Aug 2014 16:58:00 +0200 Subject: ARM: dts: Build dtb for Mediatek board This allows the "make dtbs" to build the aquaris5 dtb for the Mediatek SoC. Signed-off-by: Matthias Brugger Signed-off-by: Olof Johansson diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index dd0ebd2..7ad40de 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -499,6 +499,7 @@ dtb-$(CONFIG_MACH_DOVE) += dove-cm-a510.dtb \ dove-d2plug.dtb \ dove-d3plug.dtb \ dove-dove-db.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt6589-aquaris5.dtb targets += dtbs dtbs_install targets += $(dtb-y) -- cgit v0.10.2 From 510f1d72e526e776243397142cbcd459dd2a2efa Mon Sep 17 00:00:00 2001 From: Matthias Brugger Date: Mon, 18 Aug 2014 16:58:00 +0200 Subject: ARM: dts: mt6589: Fix typo in GIC unit address This changes the unit address of the gic node to it's first register area. Signed-off-by: Matthias Brugger Signed-off-by: Olof Johansson diff --git a/arch/arm/boot/dts/mt6589.dtsi b/arch/arm/boot/dts/mt6589.dtsi index d0297a0..742c9bd 100644 --- a/arch/arm/boot/dts/mt6589.dtsi +++ b/arch/arm/boot/dts/mt6589.dtsi @@ -81,7 +81,7 @@ clock-names = "system-clk", "rtc-clk"; }; - gic: interrupt-controller@10212000 { + gic: interrupt-controller@10211000 { compatible = "arm,cortex-a15-gic"; interrupt-controller; #interrupt-cells = <3>; -- cgit v0.10.2 From d82df11466df3e0934c7e7aa2f5e08c284e1fd9d Mon Sep 17 00:00:00 2001 From: Matthias Brugger Date: Mon, 18 Aug 2014 16:58:00 +0200 Subject: ARM: dts: mt6589-aquaris5: Add boot argument earlyprintk Add boot argument for earlyprintk to the aquaris5 device tree file. Signed-off-by: Matthias Brugger Signed-off-by: Olof Johansson diff --git a/arch/arm/boot/dts/mt6589-aquaris5.dts b/arch/arm/boot/dts/mt6589-aquaris5.dts index 443b446..74cb1ba 100644 --- a/arch/arm/boot/dts/mt6589-aquaris5.dts +++ b/arch/arm/boot/dts/mt6589-aquaris5.dts @@ -19,6 +19,10 @@ / { model = "bq Aquaris5"; + chosen { + bootargs = "earlyprintk"; + }; + memory { reg = <0x80000000 0x40000000>; }; -- cgit v0.10.2 From 6e9cb2633698ddadd2493b3793dbc9723f570538 Mon Sep 17 00:00:00 2001 From: Matthias Brugger Date: Mon, 18 Aug 2014 16:58:00 +0200 Subject: ARM: dts: mediatek: Add compatible property for aquaris5 Add the missing 'compatible' property to device tree root node of - mt6589-aquaris5.dts and document the new values. Signed-off-by: Matthias Brugger Signed-off-by: Olof Johansson diff --git a/Documentation/devicetree/bindings/arm/mediatek.txt b/Documentation/devicetree/bindings/arm/mediatek.txt index d6ac71f..fa25226 100644 --- a/Documentation/devicetree/bindings/arm/mediatek.txt +++ b/Documentation/devicetree/bindings/arm/mediatek.txt @@ -6,3 +6,9 @@ Required root node property: compatible: must contain "mediatek,mt6589" + +Supported boards: + +- bq Aquaris5 smart phone: + Required root node properties: + - compatible = "mundoreader,bq-aquaris5", "mediatek,mt6589"; diff --git a/arch/arm/boot/dts/mt6589-aquaris5.dts b/arch/arm/boot/dts/mt6589-aquaris5.dts index 74cb1ba..0da0470 100644 --- a/arch/arm/boot/dts/mt6589-aquaris5.dts +++ b/arch/arm/boot/dts/mt6589-aquaris5.dts @@ -18,6 +18,7 @@ / { model = "bq Aquaris5"; + compatible = "mundoreader,bq-aquaris5", "mediatek,mt6589"; chosen { bootargs = "earlyprintk"; -- cgit v0.10.2 From 7e9b2828f25ec156623da0c2156604066de5514d Mon Sep 17 00:00:00 2001 From: Matthias Brugger Date: Mon, 18 Aug 2014 16:58:00 +0200 Subject: ARM: dts: mt6589: Change compatible string for GIC This patch changes the compatible string of the GIC to the new "arm,cortex-a7-gic" which does reflect the actual hardware. Signed-off-by: Matthias Brugger Signed-off-by: Olof Johansson diff --git a/arch/arm/boot/dts/mt6589.dtsi b/arch/arm/boot/dts/mt6589.dtsi index 742c9bd..e3c7600 100644 --- a/arch/arm/boot/dts/mt6589.dtsi +++ b/arch/arm/boot/dts/mt6589.dtsi @@ -82,7 +82,7 @@ }; gic: interrupt-controller@10211000 { - compatible = "arm,cortex-a15-gic"; + compatible = "arm,cortex-a7-gic"; interrupt-controller; #interrupt-cells = <3>; reg = <0x10211000 0x1000>, -- cgit v0.10.2 From 6b112e24142176382f2c627e6e9c4b958601c120 Mon Sep 17 00:00:00 2001 From: Carlo Caione Date: Tue, 9 Sep 2014 22:12:56 +0200 Subject: ARM: meson: dts: add basic Meson/Meson6/Meson6-atv1200 DTSI/DTS The Meson6 SoC is produced by Amlogic inc. and it is based on 2 Cortex A9 and an ARM Mali-400 GPU. This patch adds two basic DTSI for the preliminary support of Meson and Meson6 SoCs. Another DTS is also added for supporting the atv1200 board, produced by Geniatech inc. Signed-off-by: Carlo Caione Signed-off-by: Arnd Bergmann diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index fb1fee9..efd0899 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -159,6 +159,7 @@ dtb-$(CONFIG_MACH_KIRKWOOD) += kirkwood-b3.dtb \ kirkwood-ts419-6282.dtb dtb-$(CONFIG_ARCH_LPC32XX) += ea3250.dtb phy3250.dtb dtb-$(CONFIG_ARCH_MARCO) += marco-evb.dtb +dtb-$(CONFIG_MACH_MESON6) += meson6-atv1200.dtb dtb-$(CONFIG_ARCH_MOXART) += moxart-uc7112lx.dtb dtb-$(CONFIG_ARCH_MXC) += \ imx1-ads.dtb \ diff --git a/arch/arm/boot/dts/meson.dtsi b/arch/arm/boot/dts/meson.dtsi new file mode 100644 index 0000000..55feb14 --- /dev/null +++ b/arch/arm/boot/dts/meson.dtsi @@ -0,0 +1,105 @@ +/* + * Copyright 2014 Carlo Caione + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this library; if not, write to the Free + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/include/ "skeleton.dtsi" + +/ { + interrupt-parent = <&gic>; + + gic: interrupt-controller@c4301000 { + compatible = "arm,cortex-a9-gic"; + reg = <0xc4301000 0x1000>, + <0xc4300100 0x0100>; + interrupt-controller; + #interrupt-cells = <3>; + }; + + timer@c1109940 { + compatible = "amlogic,meson6-timer"; + reg = <0xc1109940 0x14>; + interrupts = <0 10 1>; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + uart_AO: serial@c81004c0 { + compatible = "amlogic,meson-uart"; + reg = <0xc81004c0 0x14>; + interrupts = <0 90 1>; + clocks = <&clk81>; + status = "disabled"; + }; + + uart_A: serial@c81084c0 { + compatible = "amlogic,meson-uart"; + reg = <0xc81084c0 0x14>; + interrupts = <0 90 1>; + clocks = <&clk81>; + status = "disabled"; + }; + + uart_B: serial@c81084dc { + compatible = "amlogic,meson-uart"; + reg = <0xc81084dc 0x14>; + interrupts = <0 90 1>; + clocks = <&clk81>; + status = "disabled"; + }; + + uart_C: serial@c8108700 { + compatible = "amlogic,meson-uart"; + reg = <0xc8108700 0x14>; + interrupts = <0 90 1>; + clocks = <&clk81>; + status = "disabled"; + }; + }; +}; /* end of / */ diff --git a/arch/arm/boot/dts/meson6-atv1200.dts b/arch/arm/boot/dts/meson6-atv1200.dts new file mode 100644 index 0000000..dc2541f --- /dev/null +++ b/arch/arm/boot/dts/meson6-atv1200.dts @@ -0,0 +1,66 @@ +/* + * Copyright 2014 Carlo Caione + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this library; if not, write to the Free + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +/include/ "meson6.dtsi" + +/ { + model = "Geniatech ATV1200"; + compatible = "geniatech,atv1200"; + + aliases { + serial0 = &uart_AO; + }; + + memory { + reg = <0x40000000 0x80000000>; + }; +}; + +&uart_AO { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/meson6.dtsi b/arch/arm/boot/dts/meson6.dtsi new file mode 100644 index 0000000..4ba4912 --- /dev/null +++ b/arch/arm/boot/dts/meson6.dtsi @@ -0,0 +1,78 @@ +/* + * Copyright 2014 Carlo Caione + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this library; if not, write to the Free + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/include/ "meson.dtsi" + +/ { + model = "Amlogic Meson6 SoC"; + compatible = "amlogic,meson6"; + + interrupt-parent = <&gic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@200 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0x200>; + }; + + cpu@201 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0x201>; + }; + }; + + clk81: clk@0 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <200000000>; + }; +}; /* end of / */ -- cgit v0.10.2 From 2d3a2cdbbd1d1abed2ef6f5804036331a666ca07 Mon Sep 17 00:00:00 2001 From: Carlo Caione Date: Wed, 10 Sep 2014 22:17:19 +0200 Subject: ARM: meson: documentation: add bindings documentation Add vendor prefixes and basic documentation for MesonX SoCs bindings Signed-off-by: Carlo Caione Signed-off-by: Arnd Bergmann diff --git a/Documentation/devicetree/bindings/arm/amlogic.txt b/Documentation/devicetree/bindings/arm/amlogic.txt new file mode 100644 index 0000000..7eece72 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/amlogic.txt @@ -0,0 +1,8 @@ +Amlogic MesonX device tree bindings +------------------------------------------- + +Boards with the Amlogic Meson6 SoC shall have the following properties: + +Required root node property: + +compatible = "amlogic,meson6"; diff --git a/Documentation/devicetree/bindings/arm/geniatech.txt b/Documentation/devicetree/bindings/arm/geniatech.txt new file mode 100644 index 0000000..74ccba4 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/geniatech.txt @@ -0,0 +1,5 @@ +Geniatech platforms device tree bindings +------------------------------------------- + +Geniatech ATV1200 + - compatible = "geniatech,atv1200" diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index f4318d7..c681434 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -14,6 +14,7 @@ allwinner Allwinner Technology Co., Ltd. altr Altera Corp. amcc Applied Micro Circuits Corporation (APM, formally AMCC) amd Advanced Micro Devices (AMD), Inc. +amlogic Amlogic, Inc. ams AMS AG amstaos AMS-Taos Inc. apm Applied Micro Circuits Corporation (APM) @@ -53,6 +54,7 @@ excito Excito fsl Freescale Semiconductor GEFanuc GE Fanuc Intelligent Platforms Embedded Systems, Inc. gef GE Fanuc Intelligent Platforms Embedded Systems, Inc. +geniatech Geniatech, Inc. globalscale Globalscale Technologies, Inc. gmt Global Mixed-mode Technology, Inc. google Google, Inc. -- cgit v0.10.2 From 667bbd533772e2539cf7d7fed7cd7d284a624e37 Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Tue, 16 Sep 2014 19:51:36 -0600 Subject: ARM: bcm2835: add I2S pinctrl to device tree Signed-off-by: Florian Meier [Tweaked slightly to disable by default -- broonie] Signed-off-by: Mark Brown [swarren, removed duplicate i2s node] Signed-off-by: Stephen Warren Signed-off-by: Arnd Bergmann diff --git a/arch/arm/boot/dts/bcm2835-rpi-b.dts b/arch/arm/boot/dts/bcm2835-rpi-b.dts index 2a3b1c1..58a0d60 100644 --- a/arch/arm/boot/dts/bcm2835-rpi-b.dts +++ b/arch/arm/boot/dts/bcm2835-rpi-b.dts @@ -23,7 +23,7 @@ &gpio { pinctrl-names = "default"; - pinctrl-0 = <&gpioout &alt0 &alt3>; + pinctrl-0 = <&gpioout &alt0 &alt2 &alt3>; gpioout: gpioout { brcm,pins = <6>; @@ -39,6 +39,12 @@ brcm,pins = <48 49 50 51 52 53>; brcm,function = <7>; /* alt3 */ }; + + /* I2S interface */ + alt2: alt2 { + brcm,pins = <28 29 30 31>; + brcm,function = <6>; /* alt2 */ + }; }; &i2c0 { diff --git a/arch/arm/boot/dts/bcm2835.dtsi b/arch/arm/boot/dts/bcm2835.dtsi index b8473c4..3342cb1 100644 --- a/arch/arm/boot/dts/bcm2835.dtsi +++ b/arch/arm/boot/dts/bcm2835.dtsi @@ -99,6 +99,7 @@ dmas = <&dma 2>, <&dma 3>; dma-names = "tx", "rx"; + status = "disabled"; }; spi: spi@7e204000 { -- cgit v0.10.2 From 478a4f81af4936c683a03488e15b087e28cb4f0d Mon Sep 17 00:00:00 2001 From: Pawel Moll Date: Thu, 18 Sep 2014 10:23:06 +0100 Subject: ARM: vexpress: Add CLCD Device Tree properties ... for V2M-P1 motherboard CLCD (limited to 640x480 16bpp and using dedicated video RAM bank) and for V2P-CA9 (up to 1024x768 16bpp). Signed-off-by: Pawel Moll Signed-off-by: Arnd Bergmann diff --git a/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi b/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi index 756c986..2efb205 100644 --- a/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi +++ b/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi @@ -41,7 +41,7 @@ bank-width = <4>; }; - vram@2,00000000 { + v2m_video_ram: vram@2,00000000 { compatible = "arm,vexpress-vram"; reg = <2 0x00000000 0x00800000>; }; @@ -246,9 +246,41 @@ clcd@1f0000 { compatible = "arm,pl111", "arm,primecell"; reg = <0x1f0000 0x1000>; + interrupt-names = "combined"; interrupts = <14>; clocks = <&v2m_oscclk1>, <&smbclk>; clock-names = "clcdclk", "apb_pclk"; + memory-region = <&v2m_video_ram>; + max-memory-bandwidth = <50350000>; /* 16bpp @ 25.175MHz */ + + port { + v2m_clcd_pads: endpoint { + remote-endpoint = <&v2m_clcd_panel>; + arm,pl11x,tft-r0g0b0-pads = <0 8 16>; + }; + }; + + panel { + compatible = "panel-dpi"; + + port { + v2m_clcd_panel: endpoint { + remote-endpoint = <&v2m_clcd_pads>; + }; + }; + + panel-timing { + clock-frequency = <25175000>; + hactive = <640>; + hback-porch = <40>; + hfront-porch = <24>; + hsync-len = <96>; + vactive = <480>; + vback-porch = <32>; + vfront-porch = <11>; + vsync-len = <2>; + }; + }; }; }; @@ -350,7 +382,7 @@ /* CLCD clock */ compatible = "arm,vexpress-osc"; arm,vexpress-sysreg,func = <1 1>; - freq-range = <23750000 63500000>; + freq-range = <23750000 65000000>; #clock-cells = <0>; clock-output-names = "v2m:oscclk1"; }; diff --git a/arch/arm/boot/dts/vexpress-v2m.dtsi b/arch/arm/boot/dts/vexpress-v2m.dtsi index ba856d6..cb3090f 100644 --- a/arch/arm/boot/dts/vexpress-v2m.dtsi +++ b/arch/arm/boot/dts/vexpress-v2m.dtsi @@ -40,7 +40,7 @@ bank-width = <4>; }; - vram@3,00000000 { + v2m_video_ram: vram@3,00000000 { compatible = "arm,vexpress-vram"; reg = <3 0x00000000 0x00800000>; }; @@ -245,9 +245,41 @@ clcd@1f000 { compatible = "arm,pl111", "arm,primecell"; reg = <0x1f000 0x1000>; + interrupt-names = "combined"; interrupts = <14>; clocks = <&v2m_oscclk1>, <&smbclk>; clock-names = "clcdclk", "apb_pclk"; + memory-region = <&v2m_video_ram>; + max-memory-bandwidth = <50350000>; /* 16bpp @ 25.175MHz */ + + port { + v2m_clcd_pads: endpoint { + remote-endpoint = <&v2m_clcd_panel>; + arm,pl11x,tft-r0g0b0-pads = <0 8 16>; + }; + }; + + panel { + compatible = "panel-dpi"; + + port { + v2m_clcd_panel: endpoint { + remote-endpoint = <&v2m_clcd_pads>; + }; + }; + + panel-timing { + clock-frequency = <25175000>; + hactive = <640>; + hback-porch = <40>; + hfront-porch = <24>; + hsync-len = <96>; + vactive = <480>; + vback-porch = <32>; + vfront-porch = <11>; + vsync-len = <2>; + }; + }; }; }; @@ -349,7 +381,7 @@ /* CLCD clock */ compatible = "arm,vexpress-osc"; arm,vexpress-sysreg,func = <1 1>; - freq-range = <23750000 63500000>; + freq-range = <23750000 65000000>; #clock-cells = <0>; clock-output-names = "v2m:oscclk1"; }; diff --git a/arch/arm/boot/dts/vexpress-v2p-ca9.dts b/arch/arm/boot/dts/vexpress-v2p-ca9.dts index 62d9b22..23662b5 100644 --- a/arch/arm/boot/dts/vexpress-v2p-ca9.dts +++ b/arch/arm/boot/dts/vexpress-v2p-ca9.dts @@ -70,9 +70,40 @@ clcd@10020000 { compatible = "arm,pl111", "arm,primecell"; reg = <0x10020000 0x1000>; + interrupt-names = "combined"; interrupts = <0 44 4>; clocks = <&oscclk1>, <&oscclk2>; clock-names = "clcdclk", "apb_pclk"; + max-memory-bandwidth = <130000000>; /* 16bpp @ 63.5MHz */ + + port { + clcd_pads: endpoint { + remote-endpoint = <&clcd_panel>; + arm,pl11x,tft-r0g0b0-pads = <0 8 16>; + }; + }; + + panel { + compatible = "panel-dpi"; + + port { + clcd_panel: endpoint { + remote-endpoint = <&clcd_pads>; + }; + }; + + panel-timing { + clock-frequency = <63500127>; + hactive = <1024>; + hback-porch = <152>; + hfront-porch = <48>; + hsync-len = <104>; + vactive = <768>; + vback-porch = <23>; + vfront-porch = <3>; + vsync-len = <4>; + }; + }; }; memory-controller@100e0000 { -- cgit v0.10.2 From a0f95e35c7a518ea4c63762511733156023eed77 Mon Sep 17 00:00:00 2001 From: Jianqun Date: Fri, 12 Sep 2014 18:54:55 +0800 Subject: ARM: dts: add rk3288 i2s controller Add dt for rk3288 i2s controller, since i2s clock pins and data pins default to be GPIO, this patch also add pinctrl to mux them. Tested on RK3288 board. Signed-off-by: Jianqun Xu Signed-off-by: Heiko Stuebner Signed-off-by: Arnd Bergmann diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index be276bd..874e66d 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -469,6 +469,21 @@ status = "disabled"; }; + i2s: i2s@ff890000 { + compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s"; + reg = <0xff890000 0x10000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>; + dma-names = "tx", "rx"; + clock-names = "i2s_hclk", "i2s_clk"; + clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_bus>; + status = "disabled"; + }; + gic: interrupt-controller@ffc01000 { compatible = "arm,gic-400"; interrupt-controller; @@ -661,6 +676,17 @@ }; }; + i2s0 { + i2s0_bus: i2s0-bus { + rockchip,pins = <6 0 RK_FUNC_1 &pcfg_pull_none>, + <6 1 RK_FUNC_1 &pcfg_pull_none>, + <6 2 RK_FUNC_1 &pcfg_pull_none>, + <6 3 RK_FUNC_1 &pcfg_pull_none>, + <6 4 RK_FUNC_1 &pcfg_pull_none>, + <6 8 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + sdmmc { sdmmc_clk: sdmmc-clk { rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>; -- cgit v0.10.2 From 32bb231845325ca4d19bba414f8883f3e0d6436f Mon Sep 17 00:00:00 2001 From: Olof Johansson Date: Thu, 25 Sep 2014 17:41:19 -0700 Subject: Revert "ARM: dts: hix5hd2: add wdg node" This reverts commit 610bd8722ef40b649b51f01045c5d1903f41b583. "ARM: dts: hix5hd2: add wdg node" causes a build breakage due to an undefined constatns: Error: arch/arm/boot/dts/hisi-x5hd2.dtsi:374.22-23 syntax error (Don't you just looove the dtc error messages? They are so informative!) Signed-off-by: Olof Johansson diff --git a/arch/arm/boot/dts/hisi-x5hd2.dtsi b/arch/arm/boot/dts/hisi-x5hd2.dtsi index b3a87d7..152f3ad 100644 --- a/arch/arm/boot/dts/hisi-x5hd2.dtsi +++ b/arch/arm/boot/dts/hisi-x5hd2.dtsi @@ -365,15 +365,6 @@ #interrupt-cells = <2>; status = "disabled"; }; - - wdt0: watchdog@a2c000 { - compatible = "arm,sp805", "arm,primecell"; - arm,primecell-periphid = <0x00141805>; - reg = <0xa2c000 0x1000>; - interrupts = <0 29 4>; - clocks = <&clock HIX5HD2_WDG0_RST>; - clock-names = "apb_pclk"; - }; }; local_timer@00a00600 { -- cgit v0.10.2 From 3a75d1ad9a14dfbc8ea02824457729b79444e74f Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Fri, 26 Sep 2014 14:15:54 +0200 Subject: Revert "Merge tag 'hix5hd2-dt-for-3.18' of git://github.com/hisilicon/linux-hisi into next/dt" Apparently most of the newly added nodes had the same problem, so instead of reverting the individual patches, this undoes the effect of the merge and backs out all of them at once. Signed-off-by: Arnd Bergmann diff --git a/arch/arm/boot/dts/hisi-x5hd2-dkb.dts b/arch/arm/boot/dts/hisi-x5hd2-dkb.dts index 375a10c..05b44c2 100644 --- a/arch/arm/boot/dts/hisi-x5hd2-dkb.dts +++ b/arch/arm/boot/dts/hisi-x5hd2-dkb.dts @@ -51,36 +51,3 @@ &uart0 { status = "okay"; }; - -&gmac0 { - #address-cells = <1>; - #size-cells = <0>; - phy-handle = <&phy2>; - phy-mode = "mii"; - /* Placeholder, overwritten by bootloader */ - mac-address = [00 00 00 00 00 00]; - status = "okay"; - - phy2: ethernet-phy@2 { - reg = <2>; - }; -}; - -&gmac1 { - #address-cells = <1>; - #size-cells = <0>; - phy-handle = <&phy1>; - phy-mode = "rgmii"; - /* Placeholder, overwritten by bootloader */ - mac-address = [00 00 00 00 00 00]; - status = "okay"; - - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&ahci { - phys = <&sata_phy>; - phy-names = "sata-phy"; -}; diff --git a/arch/arm/boot/dts/hisi-x5hd2.dtsi b/arch/arm/boot/dts/hisi-x5hd2.dtsi index 152f3ad..f85ba29 100644 --- a/arch/arm/boot/dts/hisi-x5hd2.dtsi +++ b/arch/arm/boot/dts/hisi-x5hd2.dtsi @@ -131,240 +131,6 @@ clock-names = "apb_pclk"; status = "disabled"; }; - - gpio0: gpio@b20000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0xb20000 0x1000>; - interrupts = <0 108 0x4>; - gpio-controller; - #gpio-cells = <2>; - clocks = <&clock HIX5HD2_FIXED_100M>; - clock-names = "apb_pclk"; - interrupt-controller; - #interrupt-cells = <2>; - status = "disabled"; - }; - - gpio1: gpio@b21000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0xb21000 0x1000>; - interrupts = <0 109 0x4>; - gpio-controller; - #gpio-cells = <2>; - clocks = <&clock HIX5HD2_FIXED_100M>; - clock-names = "apb_pclk"; - interrupt-controller; - #interrupt-cells = <2>; - status = "disabled"; - }; - - gpio2: gpio@b22000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0xb22000 0x1000>; - interrupts = <0 110 0x4>; - gpio-controller; - #gpio-cells = <2>; - clocks = <&clock HIX5HD2_FIXED_100M>; - clock-names = "apb_pclk"; - interrupt-controller; - #interrupt-cells = <2>; - status = "disabled"; - }; - - gpio3: gpio@b23000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0xb23000 0x1000>; - interrupts = <0 111 0x4>; - gpio-controller; - #gpio-cells = <2>; - clocks = <&clock HIX5HD2_FIXED_100M>; - clock-names = "apb_pclk"; - interrupt-controller; - #interrupt-cells = <2>; - status = "disabled"; - }; - - gpio4: gpio@b24000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0xb24000 0x1000>; - interrupts = <0 112 0x4>; - gpio-controller; - #gpio-cells = <2>; - clocks = <&clock HIX5HD2_FIXED_100M>; - clock-names = "apb_pclk"; - interrupt-controller; - #interrupt-cells = <2>; - status = "disabled"; - }; - - gpio5: gpio@004000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x004000 0x1000>; - interrupts = <0 113 0x4>; - gpio-controller; - #gpio-cells = <2>; - clocks = <&clock HIX5HD2_FIXED_100M>; - clock-names = "apb_pclk"; - interrupt-controller; - #interrupt-cells = <2>; - status = "disabled"; - }; - - gpio6: gpio@b26000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0xb26000 0x1000>; - interrupts = <0 114 0x4>; - gpio-controller; - #gpio-cells = <2>; - clocks = <&clock HIX5HD2_FIXED_100M>; - clock-names = "apb_pclk"; - interrupt-controller; - #interrupt-cells = <2>; - status = "disabled"; - }; - - gpio7: gpio@b27000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0xb27000 0x1000>; - interrupts = <0 115 0x4>; - gpio-controller; - #gpio-cells = <2>; - clocks = <&clock HIX5HD2_FIXED_100M>; - clock-names = "apb_pclk"; - interrupt-controller; - #interrupt-cells = <2>; - status = "disabled"; - }; - - gpio8: gpio@b28000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0xb28000 0x1000>; - interrupts = <0 116 0x4>; - gpio-controller; - #gpio-cells = <2>; - clocks = <&clock HIX5HD2_FIXED_100M>; - clock-names = "apb_pclk"; - interrupt-controller; - #interrupt-cells = <2>; - status = "disabled"; - }; - - gpio9: gpio@b29000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0xb29000 0x1000>; - interrupts = <0 117 0x4>; - gpio-controller; - #gpio-cells = <2>; - clocks = <&clock HIX5HD2_FIXED_100M>; - clock-names = "apb_pclk"; - interrupt-controller; - #interrupt-cells = <2>; - status = "disabled"; - }; - - gpio10: gpio@b2a000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0xb2a000 0x1000>; - interrupts = <0 118 0x4>; - gpio-controller; - #gpio-cells = <2>; - clocks = <&clock HIX5HD2_FIXED_100M>; - clock-names = "apb_pclk"; - interrupt-controller; - #interrupt-cells = <2>; - status = "disabled"; - }; - - gpio11: gpio@b2b000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0xb2b000 0x1000>; - interrupts = <0 119 0x4>; - gpio-controller; - #gpio-cells = <2>; - clocks = <&clock HIX5HD2_FIXED_100M>; - clock-names = "apb_pclk"; - interrupt-controller; - #interrupt-cells = <2>; - status = "disabled"; - }; - - gpio12: gpio@b2c000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0xb2c000 0x1000>; - interrupts = <0 120 0x4>; - gpio-controller; - #gpio-cells = <2>; - clocks = <&clock HIX5HD2_FIXED_100M>; - clock-names = "apb_pclk"; - interrupt-controller; - #interrupt-cells = <2>; - status = "disabled"; - }; - - gpio13: gpio@b2d000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0xb2d000 0x1000>; - interrupts = <0 121 0x4>; - gpio-controller; - #gpio-cells = <2>; - clocks = <&clock HIX5HD2_FIXED_100M>; - clock-names = "apb_pclk"; - interrupt-controller; - #interrupt-cells = <2>; - status = "disabled"; - }; - - gpio14: gpio@b2e000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0xb2e000 0x1000>; - interrupts = <0 122 0x4>; - gpio-controller; - #gpio-cells = <2>; - clocks = <&clock HIX5HD2_FIXED_100M>; - clock-names = "apb_pclk"; - interrupt-controller; - #interrupt-cells = <2>; - status = "disabled"; - }; - - gpio15: gpio@b2f000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0xb2f000 0x1000>; - interrupts = <0 123 0x4>; - gpio-controller; - #gpio-cells = <2>; - clocks = <&clock HIX5HD2_FIXED_100M>; - clock-names = "apb_pclk"; - interrupt-controller; - #interrupt-cells = <2>; - status = "disabled"; - }; - - gpio16: gpio@b30000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0xb30000 0x1000>; - interrupts = <0 124 0x4>; - gpio-controller; - #gpio-cells = <2>; - clocks = <&clock HIX5HD2_FIXED_100M>; - clock-names = "apb_pclk"; - interrupt-controller; - #interrupt-cells = <2>; - status = "disabled"; - }; - - gpio17: gpio@b31000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0xb31000 0x1000>; - interrupts = <0 125 0x4>; - gpio-controller; - #gpio-cells = <2>; - clocks = <&clock HIX5HD2_FIXED_100M>; - clock-names = "apb_pclk"; - interrupt-controller; - #interrupt-cells = <2>; - status = "disabled"; - }; }; local_timer@00a00600 { @@ -400,72 +166,5 @@ #clock-cells = <1>; }; }; - - /* unremovable emmc as mmcblk0 */ - mmc: mmc@1830000 { - compatible = "snps,dw-mshc"; - reg = <0x1830000 0x1000>; - interrupts = <0 35 4>; - clocks = <&clock HIX5HD2_MMC_CIU_RST>, <&clock HIX5HD2_MMC_BIU_CLK>; - clock-names = "ciu", "biu"; - }; - - sd: mmc@1820000 { - compatible = "snps,dw-mshc"; - reg = <0x1820000 0x1000>; - interrupts = <0 34 4>; - clocks = <&clock HIX5HD2_SD_CIU_RST>, <&clock HIX5HD2_SD_BIU_CLK>; - clock-names = "ciu","biu"; - }; - - gmac0: ethernet@1840000 { - compatible = "hisilicon,hix5hd2-gmac"; - reg = <0x1840000 0x1000>,<0x184300c 0x4>; - interrupts = <0 71 4>; - clocks = <&clock HIX5HD2_MAC0_CLK>; - status = "disabled"; - }; - - gmac1: ethernet@1841000 { - compatible = "hisilicon,hix5hd2-gmac"; - reg = <0x1841000 0x1000>,<0x1843010 0x4>; - interrupts = <0 72 4>; - clocks = <&clock HIX5HD2_MAC1_CLK>; - status = "disabled"; - }; - - usb0: ehci@1890000 { - compatible = "generic-ehci"; - reg = <0x1890000 0x1000>; - interrupts = <0 66 4>; - clocks = <&clock HIX5HD2_USB_CLK>; - }; - - usb1: ohci@1880000 { - compatible = "generic-ohci"; - reg = <0x1880000 0x1000>; - interrupts = <0 67 4>; - clocks = <&clock HIX5HD2_USB_CLK>; - }; - - peripheral_ctrl: syscon@a20000 { - compatible = "syscon"; - reg = <0xa20000 0x1000>; - }; - - sata_phy: phy@1900000 { - compatible = "hisilicon,hix5hd2-sata-phy"; - reg = <0x1900000 0x10000>; - #phy-cells = <0>; - hisilicon,peripheral-syscon = <&peripheral_ctrl>; - hisilicon,power-reg = <0x8 10>; - }; - - ahci: sata@1900000 { - compatible = "hisilicon,hisi-ahci"; - reg = <0x1900000 0x10000>; - interrupts = <0 70 4>; - clocks = <&clock HIX5HD2_SATA_CLK>; - }; }; }; -- cgit v0.10.2 From cfb198ceed66cc7b7014f1185ff5d5e625805b7a Mon Sep 17 00:00:00 2001 From: Grygorii Strashko Date: Wed, 1 Oct 2014 09:58:25 -0400 Subject: ARM: dts: keystone: fix io range for usb_phy0 The IO range size is set incorrectly for USB PHY0 deivice it should be 24 instead of 32. Otherwise, It causes USB PHY1 probing failure. Signed-off-by: Grygorii Strashko Signed-off-by: Santosh Shilimkar diff --git a/arch/arm/boot/dts/keystone.dtsi b/arch/arm/boot/dts/keystone.dtsi index 1820d9e..5d3e83f 100644 --- a/arch/arm/boot/dts/keystone.dtsi +++ b/arch/arm/boot/dts/keystone.dtsi @@ -172,7 +172,7 @@ compatible = "ti,keystone-usbphy"; #address-cells = <1>; #size-cells = <1>; - reg = <0x2620738 32>; + reg = <0x2620738 24>; status = "disabled"; }; -- cgit v0.10.2 From b741bb2878a981db14bef1662d958aae43d168ff Mon Sep 17 00:00:00 2001 From: Grygorii Strashko Date: Wed, 1 Oct 2014 09:58:25 -0400 Subject: ARM: dts: keystone-k2e: update usb1 node for dma properties Keystone supports dma-coherent on USB master and also needs dma-ranges to specify the hardware alias memory range in which DMA can be operational. Such configuration applied for USB0 devices, but It's missed for USB1 device which is present only in K2E SoC - hence apply it. Signed-off-by: Grygorii Strashko Signed-off-by: Santosh Shilimkar diff --git a/arch/arm/boot/dts/k2e.dtsi b/arch/arm/boot/dts/k2e.dtsi index 13cf35a..7e63997 100644 --- a/arch/arm/boot/dts/k2e.dtsi +++ b/arch/arm/boot/dts/k2e.dtsi @@ -67,6 +67,8 @@ clock-names = "usb"; interrupts = ; ranges; + dma-coherent; + dma-ranges; status = "disabled"; dwc3@25010000 { -- cgit v0.10.2 From 9a84c8928dde3e032ec482a3f59f5f7e8929cca5 Mon Sep 17 00:00:00 2001 From: Grygorii Strashko Date: Wed, 1 Oct 2014 09:58:25 -0400 Subject: ARM: dts: keystone-k2e: fix mdio io start address The K2E MDIO io space has different start address. Hence, fix it to be 0x24200f00 according to TRM. Signed-off-by: Grygorii Strashko Signed-off-by: Santosh Shilimkar diff --git a/arch/arm/boot/dts/k2e.dtsi b/arch/arm/boot/dts/k2e.dtsi index 7e63997..c358b4b 100644 --- a/arch/arm/boot/dts/k2e.dtsi +++ b/arch/arm/boot/dts/k2e.dtsi @@ -87,3 +87,7 @@ }; }; }; + +&mdio { + reg = <0x24200f00 0x100>; +}; -- cgit v0.10.2 From 45aa70d1f77e3b88f776a34cf2b38858d922ca9b Mon Sep 17 00:00:00 2001 From: Grygorii Strashko Date: Wed, 1 Oct 2014 09:59:33 -0400 Subject: ARM: dts: keystone-k2l: fix mdio io start address The K2L MDIO io space has different start address. Hence, fix it to be 0x26200f00 according to TRM. Signed-off-by: Grygorii Strashko Signed-off-by: Santosh Shilimkar diff --git a/arch/arm/boot/dts/k2l.dtsi b/arch/arm/boot/dts/k2l.dtsi index 291db43..e32c3ba 100644 --- a/arch/arm/boot/dts/k2l.dtsi +++ b/arch/arm/boot/dts/k2l.dtsi @@ -95,3 +95,7 @@ /* Pin muxed. Enabled and configured by Bootloader */ status = "disabled"; }; + +&mdio { + reg = <0x26200f00 0x100>; +}; -- cgit v0.10.2 From d4ac2cfea724d3874ce3f1f624bcd40e78b1a9d4 Mon Sep 17 00:00:00 2001 From: Carlo Caione Date: Mon, 15 Sep 2014 20:51:58 +0200 Subject: ARM: DTS: meson: update DTSI to add watchdog node Reviewed-by: Guenter Roeck Signed-off-by: Carlo Caione diff --git a/arch/arm/boot/dts/meson.dtsi b/arch/arm/boot/dts/meson.dtsi index 55feb14..e6539ea 100644 --- a/arch/arm/boot/dts/meson.dtsi +++ b/arch/arm/boot/dts/meson.dtsi @@ -70,6 +70,11 @@ #size-cells = <1>; ranges; + wdt: watchdog@c1109900 { + compatible = "amlogic,meson6-wdt"; + reg = <0xc1109900 0x8>; + }; + uart_AO: serial@c81004c0 { compatible = "amlogic,meson-uart"; reg = <0xc81004c0 0x14>; -- cgit v0.10.2