From 69f3dc379bef56f9fe3b815cd41a7ae34e2c9047 Mon Sep 17 00:00:00 2001 From: Chun-Hao Lin Date: Tue, 29 Dec 2015 22:13:37 +0800 Subject: r8169:Fix typo in setting RTL8168EP and RTL8168H D3cold PFM mode The register for setting D3code PFM mode is MISC_1, not DLLPR. Signed-off-by: Chunhao Lin Reviewed-by: Francois Romieu Signed-off-by: David S. Miller diff --git a/drivers/net/ethernet/realtek/r8169.c b/drivers/net/ethernet/realtek/r8169.c index 58365bc..0decc1b 100644 --- a/drivers/net/ethernet/realtek/r8169.c +++ b/drivers/net/ethernet/realtek/r8169.c @@ -6127,7 +6127,7 @@ static void rtl_hw_start_8168h_1(struct rtl8169_private *tp) RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07); RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN); - RTL_W8(DLLPR, RTL_R8(MISC_1) & ~PFM_D3COLD_EN); + RTL_W8(MISC_1, RTL_R8(MISC_1) & ~PFM_D3COLD_EN); RTL_W8(DLLPR, RTL_R8(DLLPR) & ~TX_10M_PS_EN); @@ -6252,7 +6252,7 @@ static void rtl_hw_start_8168ep_2(struct rtl8169_private *tp) rtl_hw_start_8168ep(tp); RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN); - RTL_W8(DLLPR, RTL_R8(MISC_1) & ~PFM_D3COLD_EN); + RTL_W8(MISC_1, RTL_R8(MISC_1) & ~PFM_D3COLD_EN); } static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp) @@ -6274,7 +6274,7 @@ static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp) rtl_hw_start_8168ep(tp); RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN); - RTL_W8(DLLPR, RTL_R8(MISC_1) & ~PFM_D3COLD_EN); + RTL_W8(MISC_1, RTL_R8(MISC_1) & ~PFM_D3COLD_EN); data = r8168_mac_ocp_read(tp, 0xd3e2); data &= 0xf000; -- cgit v0.10.2 From c832c35f5f27f38b65d7d4d55906a3365ba6f33a Mon Sep 17 00:00:00 2001 From: Chun-Hao Lin Date: Tue, 29 Dec 2015 22:13:38 +0800 Subject: r8169:Fix typo in setting RTL8168H PHY PFM mode. The PHY PFM register is in PHY page 0x0a44 register 0x11, not 0x14. Signed-off-by: Chunhao Lin Signed-off-by: David S. Miller diff --git a/drivers/net/ethernet/realtek/r8169.c b/drivers/net/ethernet/realtek/r8169.c index 0decc1b..629f5e5 100644 --- a/drivers/net/ethernet/realtek/r8169.c +++ b/drivers/net/ethernet/realtek/r8169.c @@ -3894,7 +3894,7 @@ static void rtl8168h_1_hw_phy_config(struct rtl8169_private *tp) /* disable phy pfm mode */ rtl_writephy(tp, 0x1f, 0x0a44); - rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0080); + rtl_w0w1_phy(tp, 0x11, 0x0000, 0x0080); rtl_writephy(tp, 0x1f, 0x0000); /* Check ALDPS bit, disable it if enabled */ @@ -3967,7 +3967,7 @@ static void rtl8168h_2_hw_phy_config(struct rtl8169_private *tp) /* disable phy pfm mode */ rtl_writephy(tp, 0x1f, 0x0a44); - rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0080); + rtl_w0w1_phy(tp, 0x11, 0x0000, 0x0080); rtl_writephy(tp, 0x1f, 0x0000); /* Check ALDPS bit, disable it if enabled */ -- cgit v0.10.2 From 1016a4a1f4018c9a1db411b38f46bd00b96f4e83 Mon Sep 17 00:00:00 2001 From: Chun-Hao Lin Date: Tue, 29 Dec 2015 22:13:39 +0800 Subject: r8169:Correct the way of setting RTL8168DP ephy The original way is wrong, it always writes ephy reg 0x03. Signed-off-by: Chunhao Lin Signed-off-by: David S. Miller diff --git a/drivers/net/ethernet/realtek/r8169.c b/drivers/net/ethernet/realtek/r8169.c index 629f5e5..17d5571 100644 --- a/drivers/net/ethernet/realtek/r8169.c +++ b/drivers/net/ethernet/realtek/r8169.c @@ -5818,11 +5818,10 @@ static void rtl_hw_start_8168d_4(struct rtl8169_private *tp) void __iomem *ioaddr = tp->mmio_addr; struct pci_dev *pdev = tp->pci_dev; static const struct ephy_info e_info_8168d_4[] = { - { 0x0b, ~0, 0x48 }, - { 0x19, 0x20, 0x50 }, - { 0x0c, ~0, 0x20 } + { 0x0b, 0x0000, 0x0048 }, + { 0x19, 0x0020, 0x0050 }, + { 0x0c, 0x0100, 0x0020 } }; - int i; rtl_csi_access_enable_1(tp); @@ -5830,13 +5829,7 @@ static void rtl_hw_start_8168d_4(struct rtl8169_private *tp) RTL_W8(MaxTxPacketSize, TxPacketMax); - for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) { - const struct ephy_info *e = e_info_8168d_4 + i; - u16 w; - - w = rtl_ephy_read(tp, e->offset); - rtl_ephy_write(tp, 0x03, (w & e->mask) | e->bits); - } + rtl_ephy_init(tp, e_info_8168d_4, ARRAY_SIZE(e_info_8168d_4)); rtl_enable_clock_request(pdev); } -- cgit v0.10.2