From e999dc50404d401150a5429b6459473a691fd1a0 Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Mon, 13 Jun 2011 12:14:07 +0100 Subject: ASoC: Fix Blackfin I2S _pointer() implementation return in bounds values The Blackfin DMA controller can report one frame beyond the end of the buffer in the wraparound case but ALSA requires that the pointer always be in the buffer. Do the wraparound to handle this. A similar bug is likely to apply to the other Blackfin PCM drivers but the code is less obvious to inspection and I don't have a user to test. Reported-by: Kieran O'Leary Acked-by: Liam Girdwood Signed-off-by: Mark Brown Cc: stable@kernel.org diff --git a/sound/soc/blackfin/bf5xx-i2s-pcm.c b/sound/soc/blackfin/bf5xx-i2s-pcm.c index b5101ef..f1fd95b 100644 --- a/sound/soc/blackfin/bf5xx-i2s-pcm.c +++ b/sound/soc/blackfin/bf5xx-i2s-pcm.c @@ -138,11 +138,20 @@ static snd_pcm_uframes_t bf5xx_pcm_pointer(struct snd_pcm_substream *substream) pr_debug("%s enter\n", __func__); if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { diff = sport_curr_offset_tx(sport); - frames = bytes_to_frames(substream->runtime, diff); } else { diff = sport_curr_offset_rx(sport); - frames = bytes_to_frames(substream->runtime, diff); } + + /* + * TX at least can report one frame beyond the end of the + * buffer if we hit the wraparound case - clamp to within the + * buffer as the ALSA APIs require. + */ + if (diff == snd_pcm_lib_buffer_bytes(substream)) + diff = 0; + + frames = bytes_to_frames(substream->runtime, diff); + return frames; } -- cgit v0.10.2 From 713d1369789f2a2336c3431b15276c968862bdb7 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Fri, 1 Jul 2011 13:56:13 -0600 Subject: ASoC: Tegra: I2S: Ensure clock is enabled when writing regs The I2S controller needs a clock to respond to register writes. Without this, register writes will at worst hang the CPU. In practice, I've only observed writes being dropped. Luckily, the dropped register writes historically had no effect: TEGRA_I2S_TIMING: The value we wrote was the reset default. TEGRA_I2S_FIFO_SCR: The default was for the FIFOs to request more data when one slot was empty. The requested value was for the FIFOs to request when four slots were empty. The DMA controller in the mainline kernel is configured to burst a single entry at a time into the FIFO, hence there was no issue. The only negative effect was on bus efficiency losses due to an increased number of arbitration attempts. However, in various non-upstream changes, the DMA controller now bursts four entries at a time into the FIFO. If there is only space for one entry, the data is simply dropped. In practice, this resulted in 3/4 of samples being dropped, and playback at 4x the expected rate and pitch. By fixing the clocking issue, this is solved. Signed-off-by: Stephen Warren Acked-by: Liam Girdwood Signed-off-by: Mark Brown diff --git a/sound/soc/tegra/tegra_i2s.c b/sound/soc/tegra/tegra_i2s.c index 6b817e2..95f03c1 100644 --- a/sound/soc/tegra/tegra_i2s.c +++ b/sound/soc/tegra/tegra_i2s.c @@ -222,12 +222,18 @@ static int tegra_i2s_hw_params(struct snd_pcm_substream *substream, if (i2sclock % (2 * srate)) reg |= TEGRA_I2S_TIMING_NON_SYM_ENABLE; + if (!i2s->clk_refs) + clk_enable(i2s->clk_i2s); + tegra_i2s_write(i2s, TEGRA_I2S_TIMING, reg); tegra_i2s_write(i2s, TEGRA_I2S_FIFO_SCR, TEGRA_I2S_FIFO_SCR_FIFO2_ATN_LVL_FOUR_SLOTS | TEGRA_I2S_FIFO_SCR_FIFO1_ATN_LVL_FOUR_SLOTS); + if (!i2s->clk_refs) + clk_disable(i2s->clk_i2s); + return 0; } -- cgit v0.10.2 From 8e9ddf811ba021506d2316fcfe619faa0ab3f567 Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Fri, 1 Jul 2011 17:24:46 -0700 Subject: ASoC: Ensure we delay long enough for WM8994 FLL to lock when starting This delay is very conservative. Signed-off-by: Mark Brown Acked-by: Liam Girdwood Cc: stable@kernel.org diff --git a/sound/soc/codecs/wm8994.c b/sound/soc/codecs/wm8994.c index 970a95c..c2fc035 100644 --- a/sound/soc/codecs/wm8994.c +++ b/sound/soc/codecs/wm8994.c @@ -1713,6 +1713,8 @@ static int _wm8994_set_fll(struct snd_soc_codec *codec, int id, int src, snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset, WM8994_FLL1_ENA | WM8994_FLL1_FRAC, reg); + + msleep(5); } wm8994->fll[id].in = freq_in; -- cgit v0.10.2